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[bsp/wch]ch32v307 PCLK1(APB1)分频注释纠错

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会飞的猪 2023-04-09 15:27:51 +08:00 committed by GitHub
parent 85294a8e86
commit 422a9ec167
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 6 additions and 6 deletions
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12
bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/system_ch32v30x.c
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@ -369,7 +369,7 @@ static void SetSysClockTo48(void)
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */ /* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */ /* PCLK1 = HCLK/2 */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
@ -441,7 +441,7 @@ static void SetSysClockTo56(void)
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */ /* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */ /* PCLK1 = HCLK/2 */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
@ -514,7 +514,7 @@ static void SetSysClockTo72(void)
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */ /* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */ /* PCLK1 = HCLK/2 */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
@ -588,7 +588,7 @@ static void SetSysClockTo96(void)
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */ /* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */ /* PCLK1 = HCLK/2 */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */ /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
@ -662,7 +662,7 @@ static void SetSysClockTo120(void)
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */ /* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */ /* PCLK1 = HCLK/2 */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */ /* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
@ -736,7 +736,7 @@ static void SetSysClockTo144(void)
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */ /* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */ /* PCLK1 = HCLK/2 */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */