Merge pull request #4108 from 0xcccccccccccc/rtt-ls2k

[bsp][loongson] 更新龙芯2K1000平台上的SPI驱动和UART驱动

bsp/ls2kdev/.config

@@ -52,6 +52,7 @@ CONFIG_RT_USING_MEMPOOL=y
 # CONFIG_RT_USING_NOHEAP is not set
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
 # CONFIG_RT_USING_MEMTRACE is not set
 CONFIG_RT_USING_HEAP=y
 
@@ -150,6 +151,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
@@ -159,7 +161,12 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
-# CONFIG_RT_USING_SPI is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
@@ -183,6 +190,7 @@ CONFIG_RT_USING_LIBC=y
 CONFIG_RT_USING_POSIX=y
 # CONFIG_RT_USING_POSIX_MMAP is not set
 # CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_GETLINE is not set
 # CONFIG_RT_USING_POSIX_AIO is not set
 # CONFIG_RT_USING_MODULE is not set
 
@@ -375,6 +383,8 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_AGILE_TELNET is not set
 # CONFIG_PKG_USING_NMEALIB is not set
 # CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
 
 #
 # security packages
@@ -453,6 +463,7 @@ CONFIG_PKG_LWEXT4_VER="latest"
 # CONFIG_PKG_USING_MININI is not set
 # CONFIG_PKG_USING_QBOOT is not set
 # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_PPOOL is not set
 
 #
 # peripheral libraries and drivers
@@ -505,6 +516,7 @@ CONFIG_PKG_LWEXT4_VER="latest"
 # CONFIG_PKG_USING_AGILE_CONSOLE is not set
 # CONFIG_PKG_USING_LD3320 is not set
 # CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
 
 #
 # miscellaneous packages
@@ -542,4 +554,8 @@ CONFIG_PKG_LWEXT4_VER="latest"
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
 CONFIG_SOC_LS2K1000=y

bsp/ls2kdev/README.md

@@ -97,7 +97,7 @@ msh >
 
 ```
 title   TFTPBOOT
- kernel tftfp://10.1.1.118/rtthread.elf
+ kernel tftp://10.1.1.118/rtthread.elf
  args console=tty root=/dev/sda2
  initrd (wd0,0)/initrd.img
 ```
@@ -114,11 +114,12 @@ title   TFTPBOOT
 
 | 驱动 | 支持情况  |  备注  |
 | ------ | ----  | :------:  |
-| UART | 支持 | UART0|
+| UART | 支持 | UART0\UART4,波特率可调 |
 | GPIO | 支持 | - |
 | PWM | 支持 | - |
 | GMAC | 支持 | 网卡驱动 |
 | RTC  | 支持 | - |
+| SPI | 支持 | - |
 
 ## 6. 联系人信息
 

bsp/ls2kdev/drivers/board.c

@@ -90,7 +90,7 @@ void rt_hw_board_init(void)
     /* init hardware UART device */
     rt_hw_uart_init();
     /* set console device */
-    rt_console_set_device("uart");
+    rt_console_set_device("uart0");
 #endif
 
 #ifdef RT_USING_HEAP

bsp/ls2kdev/drivers/clk.c

@@ -14,7 +14,8 @@
 #include <rtthread.h>
 #include "ls2k1000.h"
 
-struct loongson_pll {
+struct loongson_pll
+{
     rt_uint64_t PLL_SYS_0;
     rt_uint64_t PLL_SYS_1;
     rt_uint64_t PLL_DDR_0;

bsp/ls2kdev/drivers/drv_gpio.c

@@ -25,7 +25,8 @@ static void loongson_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t
     gpio = (void *)device->user_data;
     m = (rt_uint64_t)1 << pin;
 
-    switch (mode) {
+    switch (mode)
+    {
     case PIN_MODE_OUTPUT:
         gpio->GPIO0_OEN &= ~m;
         break;
@@ -52,7 +53,8 @@ static void loongson_pin_write(struct rt_device *device, rt_base_t pin, rt_base_
     struct loongson_gpio *gpio;
     rt_uint64_t m;
 
-    if (pin < 0 || pin >= 60) {
+    if (pin < 0 || pin >= 60)
+    {
         rt_kprintf("error\n");
         return;
     }
@@ -212,7 +214,8 @@ static void gpio_irq_handler(int irq, void *param)
     }
 }
 
-static struct rt_pin_ops loongson_pin_ops = {
+static struct rt_pin_ops loongson_pin_ops =
+{
     .pin_mode  = loongson_pin_mode,
     .pin_write = loongson_pin_write,
     .pin_read  = loongson_pin_read,

bsp/ls2kdev/drivers/drv_pwm.c

@@ -28,7 +28,8 @@
 #define CTRL_INVERT (1UL<<9)
 #define CTRL_DZONE  (1UL<<10)
 
-struct loongson_pwm {
+struct loongson_pwm
+{
     rt_uint32_t __PAD0;
     rt_uint32_t low_buffer;
     rt_uint32_t full_buffer;
@@ -91,7 +92,8 @@ static rt_err_t loongson_pwm_ioctl(struct rt_device_pwm *device, int cmd, void *
 
     cfg = (void *)arg;
 
-    switch (cmd) {
+    switch (cmd)
+    {
     case PWM_CMD_ENABLE:
         rc = loongson_pwm_enable(device, cfg->channel);
         break;
@@ -111,18 +113,21 @@ static rt_err_t loongson_pwm_ioctl(struct rt_device_pwm *device, int cmd, void *
     return rc;
 }
 
-struct rt_pwm_ops loongson_pwm_ops = {
+struct rt_pwm_ops loongson_pwm_ops =
+{
     .control = loongson_pwm_ioctl,
 };
 
-struct rt_device_pwm loongson_pwm = {
+struct rt_device_pwm loongson_pwm =
+{
     .ops = &loongson_pwm_ops,
 };
 
 int loongson_pwm_init(void)
 {
     int rc = RT_EOK;
-    static rt_uint32_t *priv[] = {
+    static rt_uint32_t *priv[] =
+    {
         (void *)PWM0_BASE,
         (void *)PWM1_BASE,
         (void *)PWM2_BASE,

bsp/ls2kdev/drivers/drv_rtc.c

@@ -19,7 +19,8 @@
 
 #ifdef RT_USING_RTC
 
-struct loongson_rtc {
+struct loongson_rtc
+{
     rt_uint32_t sys_toytrim;
     rt_uint32_t sys_toywrite0;
     rt_uint32_t sys_toywrite1;
@@ -45,7 +46,8 @@ struct loongson_rtc {
 #define __BF(number, n, m)   __RBF((number>>m), (n-m+1))
 #define BF(number, n, m)     (m<n ? __BF(number, n, m) : __BF(number, m, n))
 
-struct rtctime {
+struct rtctime
+{
     rt_uint32_t sys_toyread0;
     rt_uint32_t sys_toyread1;
     rt_uint32_t sys_rtcread0;
@@ -133,7 +135,8 @@ static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args)
     rtctm.sys_rtcread0 = hw_rtc->sys_rtcread0;
     tmptime = *localrtctime(&rtctm);
 
-    switch (cmd) {
+    switch (cmd)
+    {
     case RT_DEVICE_CTRL_RTC_GET_TIME:
         *t = mktime(&tmptime);
         break;
@@ -164,7 +167,8 @@ static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args)
 
 int rt_hw_rtc_init(void)
 {
-    static struct rt_device rtc = {
+    static struct rt_device rtc =
+    {
         .type      = RT_Device_Class_RTC,
         .init      = RT_NULL,
         .open      = rt_rtc_open,

bsp/ls2kdev/drivers/drv_spi.c

@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author                   Notes
+ * 2020-10-28     0xcccccccccccc           Initial Version
+ */
+/**
+ * @addtogroup ls2k
+ */
+/*@{*/
+#include <stdio.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include <rtthread.h>
+#include <drivers/spi.h>
+#include "drv_spi.h"
+
+#ifdef RT_USING_SPI
+static void spi_init(uint8_t spre_spr, uint8_t copl, uint8_t cpha)
+{
+    SET_SPI(SPSR, 0xc0 | (spre_spr & 0b00000011));
+    SET_SPI(PARAM, 0x40);
+    SET_SPI(PARAM2, 0x01);
+    SET_SPI(SPER, (spre_spr & 0b00001100) >> 2);
+    SET_SPI(SPCR, 0x50 | copl << 3 | cpha << 2);
+    SET_SPI(SOFTCS, 0xff);
+}
+
+static void spi_set_csn(uint8_t val) 
+{
+    SET_SPI(SOFTCS, val);
+}
+
+#ifdef RT_USING_SPI_GPIOCS
+    #include <drivers/pin.h>
+#endif
+static void spi_set_cs(unsigned char cs, int new_status) 
+{
+    if (cs < 4)
+    {
+        unsigned char val = 0;
+        val = GET_SPI(SOFTCS);
+        val |= 0x01 << cs ; // csen=1
+        if (new_status)         // cs = 1
+        {
+            val |= (0x10 << cs);            // csn=1
+        }
+        else                    // cs = 0
+        {
+            val &= ~(0x10 << cs);           // csn=0
+        }
+        SET_SPI(SOFTCS, val);
+        return ;
+    }
+#ifdef RT_USING_SPI_GPIOCS
+    else
+    {
+        rt_pin_mode(cs, PIN_MODE_OUTPUT); // with RT_USING_SPI_GPIOCS feature enabled, gpio will be used as csn pin.
+        rt_pin_write(cs, new_status);
+    }
+#endif
+}
+static uint8_t spi_write_for_response(uint8_t data)
+{
+    uint8_t val;
+    SET_SPI(TXFIFO, data);
+    while ((GET_SPI(SPSR))&RFEMPTY); //wait for echo
+    val = GET_SPI(RXFIFO);
+    return val;
+}
+
+static int cmd_spi_init(int argc, char *argv[])
+{
+    uint8_t spre_spr, cpol, cpha;
+    switch (argc)
+    {
+    case 2:
+        spre_spr = strtoul(argv[1], NULL, 0);
+        spi_init(spre_spr, 0, 0);
+        break;
+    case 4:
+        spre_spr = strtoul(argv[1], NULL, 0);
+        cpol = strtoul(argv[2], NULL, 0);
+        cpha = strtoul(argv[3], NULL, 0);
+        spi_init(spre_spr, 0, 0);
+        break;
+    default:
+        printf("\nusage : cmd_spi_init spre_spr <cpol> <cpha>\n(cmd_spi_init 0x4 0x0 0x0)\n0x4:div8 0xb:div4096\n");
+        break;
+    }
+}
+MSH_CMD_EXPORT(cmd_spi_init, cmd_spi_init);
+static int cmd_spi_set_csn(int argc, char *argv[])
+{
+    uint8_t val, csn;
+    switch (argc)
+    {
+    case 3:
+        csn = strtoul(argv[1], NULL, 0);
+        val = strtoul(argv[2], NULL, 0);
+        spi_set_cs(csn, val);
+        break;
+    default:
+        printf("usage:cmd_spi_set_csn csn val\n(0xbf for csn1 enable,0xff for csn1 disable)\n");
+        break;
+    }
+}
+MSH_CMD_EXPORT(cmd_spi_set_csn, cmd_spi_set_csn);
+static int cmd_spi_write(int argc, char *argv[])
+{
+    uint8_t data, resp;
+    switch (argc)
+    {
+    case 2:
+        data = strtoul(argv[1], NULL, 0);
+        resp = spi_write_for_response(data);
+        printf("resp:%2X\n", resp);
+        break;
+    default:
+        printf("usage:cmd_spi_write data\n");
+        break;
+    }
+}
+MSH_CMD_EXPORT(cmd_spi_write, cmd_spi_write);
+
+static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
+static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message);
+const static unsigned char SPI_DIV_TABLE[] = {0b0000, 0b0001, 0b0100, 0b0010, 0b0011, 0b0101, 0b0110, 0b0111, 0b1000, 0b1001, 0b1010, 0b1011};
+// 2      4      8      16     32     64      128   256    512    1024   2048   4096
+static rt_err_t configure(struct rt_spi_device *device,
+                          struct rt_spi_configuration *configuration)
+{
+
+    unsigned char cpol = 0;
+    unsigned char cpha = 0;
+
+    RT_ASSERT(NULL != device);
+    RT_ASSERT(NULL != configuration);
+
+    // baudrate
+    if (configuration->mode & RT_SPI_CPOL)      // cpol
+    {
+        cpol = 1;
+    }
+    else
+    {
+        cpol = 0;
+    }
+    if (configuration->mode & RT_SPI_CPHA)      // cpha
+    {
+        cpha = 1;
+    }
+    else
+    {
+        cpha = 0;
+    }
+
+    float spi_max_speed = ((float)APB_MAX_SPEED) / (8.0 / (float)APB_FREQSCALE);
+    uint64_t div = (uint64_t)(spi_max_speed / (float)configuration->max_hz);
+    int ctr = 0;
+    while (div != 1 && ctr < 12)
+    {
+        ctr++;
+        div = div >> 1;
+    }
+    spi_init(SPI_DIV_TABLE[ctr], cpol, cpha);
+
+    return RT_EOK;
+}
+static rt_uint32_t xfer(struct rt_spi_device *device,
+                        struct rt_spi_message *message)
+{
+
+    unsigned char cs = 0;
+    rt_uint32_t size = 0;
+    const rt_uint8_t *send_ptr = NULL;
+    rt_uint8_t *recv_ptr = NULL;
+    rt_uint8_t data = 0;
+    RT_ASSERT(NULL != device);
+    RT_ASSERT(NULL != message);
+    cs = (unsigned char)(device->parent.user_data);
+    size = message->length;
+    if (message->cs_take)
+    {
+        spi_set_cs(cs, 0);
+    }
+    // send data
+    send_ptr = message->send_buf;
+    recv_ptr = message->recv_buf;
+    while (size--)
+    {
+        data = 0xFF;
+        if (NULL != send_ptr)
+        {
+            data = *send_ptr++;
+        }
+        if (NULL != recv_ptr)
+        {
+            *recv_ptr++ = spi_write_for_response(data);
+        }
+        else
+        {
+            spi_write_for_response(data);
+        }
+    }
+    // release cs
+    if (message->cs_release)
+    {
+        spi_set_cs(cs, 1);
+    }
+    return message->length;
+}
+static struct rt_spi_ops loongson_spi_ops =
+{
+    .configure  = configure,
+    .xfer       = xfer
+};
+static struct rt_spi_bus loongson_spi;
+static int loongson_spi_init()
+{
+    //rt_kprintf("spi_init\n");
+    return rt_spi_bus_register(&loongson_spi, "spi", &loongson_spi_ops);
+}
+INIT_BOARD_EXPORT(loongson_spi_init);
+
+#endif
+/*@}*/

bsp/ls2kdev/drivers/drv_spi.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author                   Notes
+ * 2020-10-28     0xcccccccccccc           Initial Version
+ */
+/**
+ * @addtogroup ls2k
+ */
+/*@{*/
+#ifndef LS2K_DRV_SPI_H
+#define LS2K_DRV_SPI_H
+
+#include <rtthread.h>
+#include <rthw.h>
+
+// kseg1 byte operation
+#define KSEG1_STORE8(addr,val)	 *(volatile char *)(0xffffffffa0000000 | addr) = val
+#define KSEG1_LOAD8(addr)	 *(volatile char *)(0xffffffffa0000000 | addr) 
+// clock configurations
+#define APB_MAX_SPEED 125000000U
+#define APB_FREQSCALE (((KSEG1_LOAD8(0xffffffffbfe104d2)>>4)&0x7)+1)
+// base addrs
+#define SPI_BASE  0x1fff0220
+#define PMON_ADDR 0xa1000000
+#define FLASH_ADDR 0x000000
+// bit bias
+#define SPCR      0x0
+#define SPSR      0x1
+#define FIFO	  0x2
+#define TXFIFO    0x2
+#define RXFIFO    0x2
+#define SPER      0x3
+#define PARAM     0x4
+#define SOFTCS    0x5
+#define PARAM2    0x6
+#define RFEMPTY 1
+// SPI controller operaion macros
+#define SET_SPI(addr,val)        KSEG1_STORE8(SPI_BASE+addr,val)
+#define GET_SPI(addr)            KSEG1_LOAD8(SPI_BASE+addr)
+
+#endif
+/*@}*/

bsp/ls2kdev/drivers/drv_uart.c

@@ -6,37 +6,57 @@
  * Change Logs:
  * Date           Author       Notes
  * 2020-04-05     bigmagic     Initial version
+ * 2020-10-28     ma           Buadrate & Multi-Port support
  */
-
 /**
  * @addtogroup ls2k
  */
-
 /*@{*/
-
 #include <rtthread.h>
 #include <rtdevice.h>
 #include <rthw.h>
 #include "drv_uart.h"
-
 #define TRUE 1
 #define FALSE 0
-
+const struct serial_configure config_uart0 = {                                          
+    BAUD_RATE_115200, /* 921600 bits/s */  
+    DATA_BITS_8,      /* 8 databits */     
+    STOP_BITS_1,      /* 1 stopbit */      
+    PARITY_NONE,      /* No parity  */     
+    BIT_ORDER_LSB,    /* LSB first sent */ 
+    NRZ_NORMAL,       /* Normal mode */    
+    RT_SERIAL_RB_BUFSZ, /* Buffer size */  
+    0                                      
+};
 struct rt_uart_ls2k
 {
     void *base;
     rt_uint32_t IRQ;
 };
-
+static rt_err_t ls2k_uart_set_buad(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct rt_uart_ls2k *uart_dev = RT_NULL;
+    rt_err_t ret = RT_EOK;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+    uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
+    uint64_t brtc = (125000000U) / (16 * (cfg->baud_rate));
+    UART_LCR(uart_dev->base) = 0x80; // Activate buadcfg
+    UART_LSB(uart_dev->base) = brtc & 0xff;
+    UART_MSB(uart_dev->base) = brtc >> 8;
+    if (((((short)UART_MSB(uart_dev->base)) << 8) | UART_LSB(uart_dev->base)) != brtc) ret = RT_ERROR;
+    UART_LCR(uart_dev->base) = CFCR_8BITS; // Back to normal
+    UART_MCR(uart_dev->base) = MCR_IENABLE/* | MCR_DTR | MCR_RTS*/;
+    UART_IER(uart_dev->base) = 0;
+}
 static rt_err_t ls2k_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
     struct rt_uart_ls2k *uart_dev = RT_NULL;
-
     RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
-
+    ls2k_uart_set_buad(serial, cfg);
     uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
-
+    HWREG8(0xffffffffbfe10428) = 0x1f; // Enable Multi-Port Support, by default it's 0x11 ,which means UART0 & UART4 Controller is in single port mode.
     UART_IER(uart_dev->base) = 0; /* clear interrupt */
     UART_FCR(uart_dev->base) = 0xc1; /* reset UART Rx/Tx */
     /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
@@ -44,40 +64,30 @@ static rt_err_t ls2k_uart_configure(struct rt_serial_device *serial, struct seri
     UART_MCR(uart_dev->base) = 0x3;
     UART_LSR(uart_dev->base) = 0x60;
     UART_MSR(uart_dev->base) = 0xb0;
-
     return RT_EOK;
 }
-
 static rt_err_t ls2k_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
     struct rt_uart_ls2k *uart_dev = RT_NULL;
-
     RT_ASSERT(serial != RT_NULL);
     uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
-
     switch (cmd)
     {
     case RT_DEVICE_CTRL_CLR_INT: /* Disable RX IRQ */
         rt_hw_interrupt_mask(uart_dev->IRQ);
         break;
-
     case RT_DEVICE_CTRL_SET_INT: /* Enable RX IRQ */
         rt_hw_interrupt_umask(uart_dev->IRQ);
         UART_IER(uart_dev->base) |= (IER_IRxE | IER_ILE);
         break;
-
     default:
         break;
     }
-
     return RT_EOK;
-
 }
-
 static rt_bool_t uart_is_transmit_empty(struct rt_uart_ls2k *uart_dev)
 {
     unsigned char status = UART_LSR(uart_dev->base);
-
     if (status & (UARTLSR_TE | UARTLSR_TFE))
     {
         return TRUE;
@@ -87,50 +97,35 @@ static rt_bool_t uart_is_transmit_empty(struct rt_uart_ls2k *uart_dev)
         return FALSE;
     }
 }
-
 static int ls2k_uart_putc(struct rt_serial_device *serial, char c)
 {
     struct rt_uart_ls2k *uart_dev = RT_NULL;
-
     RT_ASSERT(serial != RT_NULL);
-
     uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
-
     while (FALSE == uart_is_transmit_empty(uart_dev))
         ;
-
     UART_DAT(uart_dev->base) = c;
-
     return 1;
 }
-
 static int ls2k_uart_getc(struct rt_serial_device *serial)
 {
     struct rt_uart_ls2k *uart_dev = RT_NULL;
-
     RT_ASSERT(serial != RT_NULL);
-
     uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
-
     if (LSR_RXRDY & UART_LSR(uart_dev->base))
     {
         return UART_DAT(uart_dev->base);
     }
-
     return -1;
 }
-
 /* UART interrupt handler */
 static void uart_irq_handler(int vector, void *param)
 {
     struct rt_serial_device *serial = (struct rt_serial_device *)param;
     struct rt_uart_ls2k *uart_dev = RT_NULL;
-
     RT_ASSERT(serial != RT_NULL);
-
     uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
     unsigned char iir = UART_IIR(uart_dev->base);
-
     /* Find out interrupt reason */
     if ((IIR_RXTOUT & iir) || (IIR_RXRDY & iir))
     {
@@ -138,9 +133,7 @@ static void uart_irq_handler(int vector, void *param)
         rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
         rt_interrupt_leave();
     }
-
 }
-
 static const struct rt_uart_ops ls2k_uart_ops =
 {
     ls2k_uart_configure,
@@ -148,31 +141,41 @@ static const struct rt_uart_ops ls2k_uart_ops =
     ls2k_uart_putc,
     ls2k_uart_getc,
 };
-
 struct rt_uart_ls2k uart_dev0 =
 {
     (void *)UARTx_BASE(0),
     LS2K_UART_0_1_2_3_IRQ,
 };
-struct rt_serial_device serial;
+struct rt_uart_ls2k uart_dev4 =
+{
+    (void *)UARTx_BASE(4),
+    LS2K_UART_4_5_6_7_IRQ,
+};
 
+struct rt_serial_device serial, serial4;
 
 void rt_hw_uart_init(void)
 {
-    struct rt_uart_ls2k *uart;
+    struct rt_uart_ls2k *uart, *uart4;
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
 
     uart = &uart_dev0;
-
+    uart4 = &uart_dev4;
     serial.ops    = &ls2k_uart_ops;
-    serial.config = config;
+    serial.config = config_uart0;
-
+    serial4.ops = &ls2k_uart_ops;
-    rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART");
+    serial4.config = config;
 
+    rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART0");
+    rt_hw_interrupt_install(uart4->IRQ, uart_irq_handler, &serial4, "UART4");
     /* register UART device */
     rt_hw_serial_register(&serial,
-                          "uart",
+                          "uart0",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
+    rt_hw_serial_register(&serial4,
+                          "uart4",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          &uart_dev4);
 }
 /*@}*/

bsp/ls2kdev/drivers/net/mii.c

@@ -32,7 +32,8 @@ static int mii_check_gmii_support(struct mii_if_info *mii)
     int reg;
 
     reg = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
-    if (reg & BMSR_ESTATEN) {
+    if (reg & BMSR_ESTATEN)
+    {
         reg = mii->mdio_read(mii->dev, mii->phy_id, MII_ESTATUS);
         if (reg & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF))
             return 1;
@@ -84,11 +85,13 @@ static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
 
     bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
     lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA);
-    if (mii->supports_gmii) {
+    if (mii->supports_gmii)
+    {
         bmcr2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
         lpa2 = mii->mdio_read(dev, mii->phy_id, MII_STAT1000);
     }
-    if (bmcr & BMCR_ANENABLE) {
+    if (bmcr & BMCR_ANENABLE)
+    {
         ecmd->advertising |= ADVERTISED_Autoneg;
         ecmd->autoneg = AUTONEG_ENABLE;
 
@@ -101,14 +104,19 @@ static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
         else
             ecmd->speed = SPEED_10;
         if ((lpa2 & LPA_1000FULL) || nego == LPA_100FULL ||
-            nego == LPA_10FULL) {
+                nego == LPA_10FULL)
+        {
             ecmd->duplex = DUPLEX_FULL;
             mii->full_duplex = 1;
-        } else {
+        }
+        else
+        {
             ecmd->duplex = DUPLEX_HALF;
             mii->full_duplex = 0;
         }
-    } else {
+    }
+    else
+    {
         ecmd->autoneg = AUTONEG_DISABLE;
 
         ecmd->speed = ((bmcr & BMCR_SPEED1000 &&

bsp/ls2kdev/drivers/net/synopGMAC_Dev.c

@@ -1136,7 +1136,8 @@ s32 synopGMAC_mac_init(synopGMACdevice *gmacdev)
 
         if (gmacdev -> Speed == SPEED1000)
             synopGMAC_select_gmii(gmacdev);
-        else{
+        else
+        {
             synopGMAC_select_mii(gmacdev);
 
             if (gmacdev -> Speed == SPEED100)
@@ -1870,11 +1871,13 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1
 
     gmacdev->TxBusy     = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? 0 : txover + 1;
 
-    if(synopGMAC_is_tx_desc_chained(txdesc)){
+    if (synopGMAC_is_tx_desc_chained(txdesc))
+    {
         gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2;
         synopGMAC_tx_desc_init_chain(txdesc);
     }
-    else{
+    else
+    {
         gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? gmacdev->TxDesc : (txdesc + 1);
         synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev, txdesc));
     }
@@ -2105,7 +2108,8 @@ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
     if (!synopGMAC_is_desc_empty(rxdesc))
         return -1;
 
-    if(synopGMAC_is_rx_desc_chained(rxdesc)){
+    if (synopGMAC_is_rx_desc_chained(rxdesc))
+    {
         rxdesc->length |= ((Length1 << DescSize1Shift) & DescSize1Mask);
 
         rxdesc->buffer1 = Buffer1;
@@ -2124,7 +2128,8 @@ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
         gmacdev->RxNext     = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1;
         gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2;
     }
-    else{
+    else
+    {
         rxdesc->length |= (((Length1 << DescSize1Shift) & DescSize1Mask) | ((Length2 << DescSize2Shift) & DescSize2Mask));
 
         rxdesc->buffer1 = Buffer1;
@@ -2177,7 +2182,8 @@ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
     if (!synopGMAC_is_desc_empty(rxdesc))
         return -1;
 
-    if(synopGMAC_is_rx_desc_chained(rxdesc)){
+    if (synopGMAC_is_rx_desc_chained(rxdesc))
+    {
         rxdesc->length |= ((Length1 << DescSize1Shift) & DescSize1Mask);
 
         rxdesc->buffer1 = Buffer1;
@@ -2191,7 +2197,8 @@ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
         gmacdev->RxNext     = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1;
         gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2;
     }
-    else{
+    else
+    {
         rxdesc->length |= (((Length1 << DescSize1Shift) & DescSize1Mask) | ((Length2 << DescSize2Shift) & DescSize2Mask));
 
         rxdesc->buffer1 = Buffer1;
@@ -2229,7 +2236,8 @@ s32 synopGMAC_set_rx_qptr_init(synopGMACdevice * gmacdev, u32 Buffer1, u32 Lengt
     if (!synopGMAC_is_desc_empty(rxdesc))
         return -1;
 
-    if(synopGMAC_is_rx_desc_chained(rxdesc)){
+    if (synopGMAC_is_rx_desc_chained(rxdesc))
+    {
         rxdesc->length |= ((Length1 << DescSize1Shift) & DescSize1Mask);
 
         rxdesc->buffer1 = Buffer1;
@@ -2244,7 +2252,8 @@ s32 synopGMAC_set_rx_qptr_init(synopGMACdevice * gmacdev, u32 Buffer1, u32 Lengt
         gmacdev->RxNext     = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1;
         gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2;
     }
-    else{
+    else
+    {
         rxdesc->length |= (((Length1 << DescSize1Shift) & DescSize1Mask) | ((Length2 << DescSize2Shift) & DescSize2Mask));
 
         rxdesc->buffer1 = Buffer1;
@@ -2323,12 +2332,14 @@ s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1
 
     gmacdev->RxBusy     = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1;
 
-    if(synopGMAC_is_rx_desc_chained(rxdesc)){
+    if (synopGMAC_is_rx_desc_chained(rxdesc))
+    {
         gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2;
         synopGMAC_rx_desc_init_chain(rxdesc);
         //synopGMAC_desc_init_chain(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc),0,0);
     }
-    else{
+    else
+    {
         gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? gmacdev->RxDesc : (rxdesc + 1);
         synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev, rxdesc));
     }
@@ -2392,11 +2403,13 @@ s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1
     len =  synopGMAC_get_rx_desc_frame_length(*Status);
     DEBUG_MES("Cache sync for data buffer in rx dma desc: length = 0x%x\n", len);
     gmacdev->RxBusy     = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1;
-    if(synopGMAC_is_rx_desc_chained(rxdesc)){
+    if (synopGMAC_is_rx_desc_chained(rxdesc))
+    {
         gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2;
         synopGMAC_rx_desc_init_chain(rxdesc);
     }
-    else{
+    else
+    {
         gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? gmacdev->RxDesc : (rxdesc + 1);
 //sw: raw data
 #if SYNOP_RX_DEBUG
@@ -2578,7 +2591,8 @@ void synopGMAC_resume_dma_rx(synopGMACdevice * gmacdev)
   */
 void synopGMAC_take_desc_ownership(DmaDesc *desc)
 {
-    if(desc){
+    if (desc)
+    {
         desc->status &= ~DescOwnByDma;  //Clear the DMA own bit
 //        desc->status |= DescError;    // Set the error to indicate this descriptor is bad
     }
@@ -2598,13 +2612,16 @@ void synopGMAC_take_desc_ownership_rx(synopGMACdevice * gmacdev)
     s32 i;
     DmaDesc *desc;
     desc = gmacdev->RxDesc;
-    for(i = 0; i < gmacdev->RxDescCount; i++){
+    for (i = 0; i < gmacdev->RxDescCount; i++)
-        if(synopGMAC_is_rx_desc_chained(desc)){    //This descriptor is in chain mode
+    {
+        if (synopGMAC_is_rx_desc_chained(desc))    //This descriptor is in chain mode
+        {
 
             synopGMAC_take_desc_ownership(desc);
             desc = (DmaDesc *)desc->data2;
         }
-        else{
+        else
+        {
             synopGMAC_take_desc_ownership(desc + i);
         }
     }
@@ -2624,12 +2641,15 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev)
     s32 i;
     DmaDesc *desc;
     desc = gmacdev->TxDesc;
-    for(i = 0; i < gmacdev->TxDescCount; i++){
+    for (i = 0; i < gmacdev->TxDescCount; i++)
-        if(synopGMAC_is_tx_desc_chained(desc)){    //This descriptor is in chain mode
+    {
+        if (synopGMAC_is_tx_desc_chained(desc))    //This descriptor is in chain mode
+        {
             synopGMAC_take_desc_ownership(desc);
             desc = (DmaDesc *)desc->data2;
         }
-        else{
+        else
+        {
             synopGMAC_take_desc_ownership(desc + i);
         }
     }
@@ -3544,15 +3564,18 @@ s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value)
 {
     u32 loop_variable;
     synopGMACWriteReg(gmacdev->MacBase, GmacTSAddend, addend_value); // Load the addend_value in to Addend register
-        for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
+    for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) //Wait till the busy bit gets cleared with in a certain amount of time
-        if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSADDREG)){ // if it is cleared then break
+    {
+        if (!((synopGMACReadReg(gmacdev->MacBase, GmacTSControl)) & GmacTSADDREG)) // if it is cleared then break
+        {
             break;
         }
         plat_delay(DEFAULT_DELAY_VARIABLE);
     }
     if (loop_variable < DEFAULT_LOOP_VARIABLE)
         synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSADDREG);
-        else{
+    else
+    {
         TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
         return -ESYNOPGMACPHYERR;
     }
@@ -3572,15 +3595,18 @@ s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32
     u32 loop_variable;
     synopGMACWriteReg(gmacdev->MacBase, GmacTSHighUpdate, high_value); // Load the high value to Timestamp High register
     synopGMACWriteReg(gmacdev->MacBase, GmacTSLowUpdate, low_value); // Load the high value to Timestamp High register
-    for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
+    for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) //Wait till the busy bit gets cleared with in a certain amount of time
-        if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSUPDT)){ // if it is cleared then break
+    {
+        if (!((synopGMACReadReg(gmacdev->MacBase, GmacTSControl)) & GmacTSUPDT)) // if it is cleared then break
+        {
             break;
         }
         plat_delay(DEFAULT_DELAY_VARIABLE);
     }
     if (loop_variable < DEFAULT_LOOP_VARIABLE)
         synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSUPDT);
-    else{
+    else
+    {
         TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
         return -ESYNOPGMACPHYERR;
     }
@@ -3601,15 +3627,18 @@ s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 lo
     u32 loop_variable;
     synopGMACWriteReg(gmacdev->MacBase, GmacTSHighUpdate, high_value); // Load the high value to Timestamp High register
     synopGMACWriteReg(gmacdev->MacBase, GmacTSLowUpdate, low_value); // Load the high value to Timestamp High register
-    for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
+    for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) //Wait till the busy bit gets cleared with in a certain amount of time
-        if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSINT)){ // if it is cleared then break
+    {
+        if (!((synopGMACReadReg(gmacdev->MacBase, GmacTSControl)) & GmacTSINT)) // if it is cleared then break
+        {
             break;
         }
         plat_delay(DEFAULT_DELAY_VARIABLE);
     }
     if (loop_variable < DEFAULT_LOOP_VARIABLE)
         synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSINT);
-    else{
+    else
+    {
         TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
         return -ESYNOPGMACPHYERR;
     }

bsp/ls2kdev/drivers/net/synopGMAC_plat.c

@@ -69,13 +69,16 @@ void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u3
 //    rt_kprintf("size = %d\n", size);
 //    rt_kprintf("bufaddr = %p\n", buf);
 //    rt_kprintf("i%%16 == %d\n", i%16);
-    if(i % 16 == 8){
+    if (i % 16 == 8)
+    {
         i += 8;
     }
-    else if(i % 16 == 4){
+    else if (i % 16 == 4)
+    {
         i += 12;
     }
-    else if(i % 16 == 12){
+    else if (i % 16 == 12)
+    {
         i += 4;
     }
 

bsp/ls2kdev/rtconfig.h

@@ -99,6 +99,7 @@
 #define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
+#define RT_USING_SPI
 
 /* Using USB */