From 11132bcb64a366e792764ffdd1361c1993aec02a Mon Sep 17 00:00:00 2001 From: 0xcccccccccccc <0xcccc@bupt.edu.cn> Date: Mon, 30 Nov 2020 14:46:52 +0800 Subject: [PATCH 1/6] - SPI support for ls2k1000 is now avaliable --- bsp/ls2kdev/.config | 18 +++++++++++++++++- bsp/ls2kdev/README.md | 8 +++++--- bsp/ls2kdev/rtconfig.h | 1 + bsp/ls2kdev/rtconfig.py | 2 +- 4 files changed, 24 insertions(+), 5 deletions(-) diff --git a/bsp/ls2kdev/.config b/bsp/ls2kdev/.config index 1189e52a5c..aec7c7c2b2 100644 --- a/bsp/ls2kdev/.config +++ b/bsp/ls2kdev/.config @@ -52,6 +52,7 @@ CONFIG_RT_USING_MEMPOOL=y # CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -150,6 +151,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set @@ -159,7 +161,12 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -183,6 +190,7 @@ CONFIG_RT_USING_LIBC=y CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_MMAP is not set # CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set @@ -375,6 +383,8 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -453,6 +463,7 @@ CONFIG_PKG_LWEXT4_VER="latest" # CONFIG_PKG_USING_MININI is not set # CONFIG_PKG_USING_QBOOT is not set # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -505,6 +516,7 @@ CONFIG_PKG_LWEXT4_VER="latest" # CONFIG_PKG_USING_AGILE_CONSOLE is not set # CONFIG_PKG_USING_LD3320 is not set # CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set # # miscellaneous packages @@ -542,4 +554,8 @@ CONFIG_PKG_LWEXT4_VER="latest" # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set CONFIG_SOC_LS2K1000=y diff --git a/bsp/ls2kdev/README.md b/bsp/ls2kdev/README.md index ff5ea50afb..302fd5f643 100644 --- a/bsp/ls2kdev/README.md +++ b/bsp/ls2kdev/README.md @@ -97,7 +97,7 @@ msh > ``` title TFTPBOOT - kernel tftfp://10.1.1.118/rtthread.elf + kernel tftp://10.1.1.118/rtthread.elf args console=tty root=/dev/sda2 initrd (wd0,0)/initrd.img ``` @@ -114,17 +114,19 @@ title TFTPBOOT | 驱动 | 支持情况 | 备注 | | ------ | ---- | :------: | -| UART | 支持 | UART0| +| UART | 支持 | UART0\UART4,波特率可调 | | GPIO | 支持 | - | | PWM | 支持 | - | | GMAC | 支持 | 网卡驱动 | | RTC | 支持 | - | +| SPI | 支持 | - | ## 6. 联系人信息 -维护人：[bernard][4] +维护人：[bernard][4],[0xcccccccccccc][5] [1]: http://ftp.loongnix.org/loongsonpi/pi_2/doc [2]: https://pan.baidu.com/s/17dbdOE4NAJ-qEW7drVRq2w [3]: http://ftp.loongnix.org/embedd/ls2k/ [4]: https://github.com/BernardXiong +[5]: https://github.com/0xcccccccccccc diff --git a/bsp/ls2kdev/rtconfig.h b/bsp/ls2kdev/rtconfig.h index 7399ca0336..b13f860ffd 100644 --- a/bsp/ls2kdev/rtconfig.h +++ b/bsp/ls2kdev/rtconfig.h @@ -99,6 +99,7 @@ #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN +#define RT_USING_SPI /* Using USB */ diff --git a/bsp/ls2kdev/rtconfig.py b/bsp/ls2kdev/rtconfig.py index 0988198426..e391bd87f0 100644 --- a/bsp/ls2kdev/rtconfig.py +++ b/bsp/ls2kdev/rtconfig.py @@ -16,7 +16,7 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = "/opt/mips-2015.05-19-mips-sde-elf-i686-pc-linux-gnu/mips-2015.05/bin/" + EXEC_PATH = "/home/ma/mips-2015.05/bin/" # EXEC_PATH = r'D:\mgc\embedded\codebench\bin' else: print('================ERROR===========================') From 0fc2b13b4544ee085d718af60b76495d282cffe2 Mon Sep 17 00:00:00 2001 From: 0xcccccccccccc <0xcccc@bupt.edu.cn> Date: Mon, 30 Nov 2020 14:57:21 +0800 Subject: [PATCH 2/6] - SPI is now supported on ls2k1000 platform. - Multi-Port & Adjustable Buadrate of UART controller feature added. --- bsp/ls2kdev/drivers/board.c | 2 +- bsp/ls2kdev/drivers/drv_spi.c | 269 +++++++++++++++++++++++++++++++++ bsp/ls2kdev/drivers/drv_spi.h | 43 ++++++ bsp/ls2kdev/drivers/drv_uart.c | 68 ++++++++- 4 files changed, 373 insertions(+), 9 deletions(-) create mode 100644 bsp/ls2kdev/drivers/drv_spi.c create mode 100644 bsp/ls2kdev/drivers/drv_spi.h diff --git a/bsp/ls2kdev/drivers/board.c b/bsp/ls2kdev/drivers/board.c index 30fb59091a..174c7ca8dc 100644 --- a/bsp/ls2kdev/drivers/board.c +++ b/bsp/ls2kdev/drivers/board.c @@ -90,7 +90,7 @@ void rt_hw_board_init(void) /* init hardware UART device */ rt_hw_uart_init(); /* set console device */ - rt_console_set_device("uart"); + rt_console_set_device("uart0"); #endif #ifdef RT_USING_HEAP diff --git a/bsp/ls2kdev/drivers/drv_spi.c b/bsp/ls2kdev/drivers/drv_spi.c new file mode 100644 index 0000000000..83ee66b7a9 --- /dev/null +++ b/bsp/ls2kdev/drivers/drv_spi.c @@ -0,0 +1,269 @@ +#include +#include +#include + +#include +#include + +#include "drv_spi.h" + +#ifdef RT_USING_SPI + + + +static void spi_init(uint8_t spre_spr,uint8_t copl,uint8_t cpha) +{ + //rt_kprintf("SPI initiating with spre_spr:%2X ,copl:%2X ,cpha:%2X\n",spre_spr,copl,cpha); + int d; + SET_SPI(SPSR, 0xc0|(spre_spr&0b00000011)); + SET_SPI(PARAM, 0x40); + SET_SPI(PARAM2,0x01); + SET_SPI(SPER, (spre_spr&0b00001100)>>2); + SET_SPI(SPCR, 0x50|copl<<3|cpha<<2); + SET_SPI(SOFTCS,0xff); +} + + +static void spi_set_csn(uint8_t val) //old method +{ + SET_SPI(SOFTCS,val); +} +// #define RT_USING_SPI_GPIOCS + +#ifdef RT_USING_SPI_GPIOCS +#include +#endif +static void spi_set_cs(unsigned char cs, int new_status) +{ + + if(cs<4){ + unsigned char val = 0; + + val = GET_SPI(SOFTCS); + val |= 0x01 << cs ; // csen=1 + if (new_status) // cs = 1 + { + val |= (0x10 << cs); // csn=1 + } + else // cs = 0 + { + val &= ~(0x10 << cs); // csn=0 + } + SET_SPI(SOFTCS,val); + + return ; + } + #ifdef RT_USING_SPI_GPIOCS + else{ + //rt_kprintf("[Warnning] GPIOCS is an experimental feature: \n "); + //rt_kprintf("[Warnning] GPIO%d will be set to OUTPUT with value %d \n ",cs,new_status); + rt_pin_mode(cs,PIN_MODE_OUTPUT); + rt_pin_write(cs,new_status); + } + #endif +} + +static uint8_t spi_write_for_response(uint8_t data) +{ + uint8_t val; + SET_SPI(TXFIFO,data); + while((GET_SPI(SPSR))&RFEMPTY);//wait for echo + val = GET_SPI(RXFIFO); + return val; +} + + + +static int cmd_spi_init(int argc,char* argv[]) +{ + uint8_t spre_spr,cpol,cpha; + switch (argc) + { + case 2: + + spre_spr=strtoul(argv[1], NULL, 0); + spi_init(spre_spr,0,0); + break; + case 4: + + spre_spr=strtoul(argv[1], NULL, 0); + cpol=strtoul(argv[2], NULL, 0); + cpha=strtoul(argv[3], NULL, 0); + spi_init(spre_spr,0,0); + break; + + default: + printf("\nusage : cmd_spi_init spre_spr \n(cmd_spi_init 0x4 0x0 0x0)\n0x4:div8 0xb:div4096\n"); + break; + } +} +MSH_CMD_EXPORT(cmd_spi_init,cmd_spi_init); + +static int cmd_spi_set_csn(int argc,char* argv[]) +{ + uint8_t val,csn; + switch (argc) + { + case 3: + csn=strtoul(argv[1], NULL, 0); + val=strtoul(argv[2], NULL, 0); + spi_set_cs(csn,val); + break; + + default: + printf("usage:cmd_spi_set_csn csn val\n(0xbf for csn1 enable,0xff for csn1 disable)\n"); + break; + } +} +MSH_CMD_EXPORT(cmd_spi_set_csn,cmd_spi_set_csn); + +static int cmd_spi_write(int argc,char* argv[]) +{ + uint8_t data,resp; + switch (argc) + { + case 2: + + data=strtoul(argv[1], NULL, 0); + resp=spi_write_for_response(data); + printf("resp:%2X\n",resp); + break; + + default: + printf("usage:cmd_spi_write data\n"); + break; + } +} +MSH_CMD_EXPORT(cmd_spi_write,cmd_spi_write); + + +static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); +static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message); + +const static unsigned char SPI_DIV_TABLE[]={0b0000,0b0001,0b0100,0b0010,0b0011,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011}; + // 2 4 8 16 32 64 128 256 512 1024 2048 4096 +static rt_err_t configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + + + unsigned char cpol = 0; + unsigned char cpha = 0; + + + RT_ASSERT(NULL != device); + RT_ASSERT(NULL != configuration); + + + // baudrate + if (configuration->mode & RT_SPI_CPOL) // cpol + { + cpol = 1; + } + else + { + cpol = 0; + } + if (configuration->mode & RT_SPI_CPHA) // cpha + { + cpha = 1; + } + else + { + cpha = 0; + } + //rt_kprintf("configure: cpol:%d cpha:%d\n",cpol,cpha); + + + float spi_max_speed=((float)APB_MAX_SPEED)/(8.0/(float)APB_FREQSCALE); + //rt_kprintf("spi max speed: %ld\n",(unsigned long)spi_max_speed); + + + uint64_t div=(uint64_t)(spi_max_speed/(float)configuration->max_hz); + //rt_kprintf("require speed: %ld\n",configuration->max_hz); + int ctr=0; + while(div!=1 && ctr<12){ + ctr++; + div=div>>1; + } + //rt_kprintf("spi speed set to: %ld\n",(unsigned long)((spi_max_speed)/(float)(1<parent.user_data); + size = message->length; + + //rt_kprintf("[%s] cs=%d\n", __FUNCTION__, cs); + + // take cs + if (message->cs_take) + { + spi_set_cs(cs, 0); + } + + // send data + send_ptr = message->send_buf; + recv_ptr = message->recv_buf; + while (size--) + { + data = 0xFF; + if (NULL != send_ptr) + { + data = *send_ptr++; + } + + if (NULL != recv_ptr) + { + *recv_ptr++ = spi_write_for_response(data); + } + else + { + spi_write_for_response(data); + } + } + + // release cs + if (message->cs_release) + { + spi_set_cs(cs, 1); + } + + return message->length; +} + +static struct rt_spi_ops loongson_spi_ops = +{ + .configure = configure, + .xfer = xfer +}; + +static struct rt_spi_bus loongson_spi; + +static int loongson_spi_init() +{ + //rt_kprintf("spi_init\n"); + return rt_spi_bus_register(&loongson_spi,"spi",&loongson_spi_ops); +} + +INIT_BOARD_EXPORT(loongson_spi_init); + + +#endif diff --git a/bsp/ls2kdev/drivers/drv_spi.h b/bsp/ls2kdev/drivers/drv_spi.h new file mode 100644 index 0000000000..08914e979b --- /dev/null +++ b/bsp/ls2kdev/drivers/drv_spi.h @@ -0,0 +1,43 @@ +#ifndef DRV_SPI_H +#define DRV_SPI_H + +#include +#include + + + +#define RFEMPTY 1 +#define KSEG1_STORE8(addr,val) *(volatile char *)(0xffffffffa0000000 | addr) = val +#define KSEG1_LOAD8(addr) *(volatile char *)(0xffffffffa0000000 | addr) + +#define APB_MAX_SPEED 125000000U +#define APB_FREQSCALE (((KSEG1_LOAD8(0xffffffffbfe104d2)>>4)&0x7)+1) + +#define SPI_BASE 0x1fff0220 +#define PMON_ADDR 0xa1000000 +#define FLASH_ADDR 0x000000 + +#define SPCR 0x0 +#define SPSR 0x1 +#define FIFO 0x2 +#define TXFIFO 0x2 +#define RXFIFO 0x2 +#define SPER 0x3 +#define PARAM 0x4 +#define SOFTCS 0x5 +#define PARAM2 0x6 + + + + +#define SET_SPI(addr,val) KSEG1_STORE8(SPI_BASE+addr,val) +#define GET_SPI(addr) KSEG1_LOAD8(SPI_BASE+addr) + + + +//void spi_init(uint8_t ,uint8_t,uint8_t); +//void spi_set_csn(uint8_t); +//uint8_t spi_write_for_response(uint8_t); + + +#endif diff --git a/bsp/ls2kdev/drivers/drv_uart.c b/bsp/ls2kdev/drivers/drv_uart.c index baed70b61f..7a59d12d32 100644 --- a/bsp/ls2kdev/drivers/drv_uart.c +++ b/bsp/ls2kdev/drivers/drv_uart.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2020-04-05 bigmagic Initial version + * 2020-10-28 ma Buadrate & Multi-Port support */ /** @@ -21,22 +22,51 @@ #define TRUE 1 #define FALSE 0 - +const struct serial_configure config_uart0 = { + BAUD_RATE_115200, /* 921600 bits/s */ + DATA_BITS_8, /* 8 databits */ + STOP_BITS_1, /* 1 stopbit */ + PARITY_NONE, /* No parity */ + BIT_ORDER_LSB, /* LSB first sent */ + NRZ_NORMAL, /* Normal mode */ + RT_SERIAL_RB_BUFSZ, /* Buffer size */ + 0 +}; struct rt_uart_ls2k { void *base; rt_uint32_t IRQ; }; +static rt_err_t ls2k_uart_set_buad(struct rt_serial_device *serial,struct serial_configure *cfg) +{ + struct rt_uart_ls2k *uart_dev = RT_NULL; + rt_err_t ret=RT_EOK; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data; + uint64_t brtc = (125000000U) / (16*(cfg->baud_rate)); + UART_LCR(uart_dev->base)=0x80; // Activate buadcfg + UART_LSB(uart_dev->base)= brtc & 0xff; + UART_MSB(uart_dev->base)= brtc >> 8; + + if(((((short)UART_MSB(uart_dev->base))<<8) | UART_LSB(uart_dev->base)) != brtc) ret=RT_ERROR; + + UART_LCR(uart_dev->base)= CFCR_8BITS;// Back to normal + UART_MCR(uart_dev->base)= MCR_IENABLE/* | MCR_DTR | MCR_RTS*/; + UART_IER(uart_dev->base) = 0; +} static rt_err_t ls2k_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { struct rt_uart_ls2k *uart_dev = RT_NULL; RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - + ls2k_uart_set_buad(serial,cfg); uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data; - + HWREG8(0xffffffffbfe10428)=0x1f;// Enable Multi-Port Support, by default it's 0x11 ,which means UART0 & UART4 Controller is in single port mode. UART_IER(uart_dev->base) = 0; /* clear interrupt */ UART_FCR(uart_dev->base) = 0xc1; /* reset UART Rx/Tx */ /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */ @@ -154,25 +184,47 @@ struct rt_uart_ls2k uart_dev0 = (void *)UARTx_BASE(0), LS2K_UART_0_1_2_3_IRQ, }; -struct rt_serial_device serial; +struct rt_uart_ls2k uart_dev4 = +{ + (void *)UARTx_BASE(4), + LS2K_UART_4_5_6_7_IRQ , +}; + + +struct rt_serial_device serial,serial4; void rt_hw_uart_init(void) { - struct rt_uart_ls2k *uart; + //UART0_1_ENABLE=0xff; + struct rt_uart_ls2k *uart,*uart4; struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + uart = &uart_dev0; + uart4=&uart_dev4; serial.ops = &ls2k_uart_ops; - serial.config = config; + serial.config = config_uart0; - rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART"); + serial4.ops= &ls2k_uart_ops; + serial4.config=config; + + + rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART0"); + rt_hw_interrupt_install(uart4->IRQ, uart_irq_handler, &serial4, "UART4"); /* register UART device */ rt_hw_serial_register(&serial, - "uart", + "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); + + rt_hw_serial_register(&serial4, + "uart4", + RT_DEVICE_FLAG_RDWR| RT_DEVICE_FLAG_INT_RX, + &uart_dev4); + } /*@}*/ From 0fc2211c77a90b9782d32edac6f55d4f7f3e1eab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E9=A9=AC=E6=B5=A9=E7=84=B6?= <43113435+0xcccccccccccc@users.noreply.github.com> Date: Tue, 1 Dec 2020 16:52:31 +0800 Subject: [PATCH 3/6] Update drv_uart.c fix indentataions --- bsp/ls2kdev/drivers/drv_uart.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/bsp/ls2kdev/drivers/drv_uart.c b/bsp/ls2kdev/drivers/drv_uart.c index 7a59d12d32..cee40ff036 100644 --- a/bsp/ls2kdev/drivers/drv_uart.c +++ b/bsp/ls2kdev/drivers/drv_uart.c @@ -47,16 +47,17 @@ static rt_err_t ls2k_uart_set_buad(struct rt_serial_device *serial,struct serial RT_ASSERT(cfg != RT_NULL); uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data; - uint64_t brtc = (125000000U) / (16*(cfg->baud_rate)); + uint64_t brtc = (125000000U) / (16*(cfg->baud_rate)); UART_LCR(uart_dev->base)=0x80; // Activate buadcfg UART_LSB(uart_dev->base)= brtc & 0xff; UART_MSB(uart_dev->base)= brtc >> 8; - if(((((short)UART_MSB(uart_dev->base))<<8) | UART_LSB(uart_dev->base)) != brtc) ret=RT_ERROR; + if(((((short)UART_MSB(uart_dev->base))<<8) | UART_LSB(uart_dev->base)) != brtc) + ret=RT_ERROR; UART_LCR(uart_dev->base)= CFCR_8BITS;// Back to normal - UART_MCR(uart_dev->base)= MCR_IENABLE/* | MCR_DTR | MCR_RTS*/; - UART_IER(uart_dev->base) = 0; + UART_MCR(uart_dev->base)= MCR_IENABLE/* | MCR_DTR | MCR_RTS*/; + UART_IER(uart_dev->base) = 0; } static rt_err_t ls2k_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { From 5d32b5d2d279c8e3886958b9427d6443e0688348 Mon Sep 17 00:00:00 2001 From: 0xcccccccccccc <0xcccc@bupt.edu.cn> Date: Mon, 7 Dec 2020 20:40:43 +0800 Subject: [PATCH 4/6] - fix indentations. --- bsp/ls2kdev/applications/main.c | 4 +- bsp/ls2kdev/drivers/board.c | 6 +- bsp/ls2kdev/drivers/clk.c | 3 +- bsp/ls2kdev/drivers/drv_gpio.c | 37 +- bsp/ls2kdev/drivers/drv_pwm.c | 15 +- bsp/ls2kdev/drivers/drv_rtc.c | 14 +- bsp/ls2kdev/drivers/drv_spi.c | 217 +-- bsp/ls2kdev/drivers/drv_uart.c | 71 +- bsp/ls2kdev/drivers/interrupt.c | 32 +- bsp/ls2kdev/drivers/net/mii.c | 40 +- bsp/ls2kdev/drivers/net/synopGMAC.c | 86 +- bsp/ls2kdev/drivers/net/synopGMAC_Dev.c | 1591 +++++++++++----------- bsp/ls2kdev/drivers/net/synopGMAC_plat.c | 41 +- 13 files changed, 1107 insertions(+), 1050 deletions(-) diff --git a/bsp/ls2kdev/applications/main.c b/bsp/ls2kdev/applications/main.c index bd975f4825..053e741bfa 100644 --- a/bsp/ls2kdev/applications/main.c +++ b/bsp/ls2kdev/applications/main.c @@ -10,8 +10,8 @@ #include -int main(int argc, char** argv) -{ +int main(int argc, char **argv) +{ rt_kprintf("Hi, this is RT-Thread!!\n"); return 0; } diff --git a/bsp/ls2kdev/drivers/board.c b/bsp/ls2kdev/drivers/board.c index 174c7ca8dc..1d165cf5ef 100644 --- a/bsp/ls2kdev/drivers/board.c +++ b/bsp/ls2kdev/drivers/board.c @@ -67,7 +67,7 @@ void rt_hw_timer_handler(void) */ void rt_hw_timer_init(void) { - write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND); + write_c0_compare(CPU_HZ / 2 / RT_TICK_PER_SECOND); write_c0_count(0); mips_unmask_cpu_irq(7); } @@ -94,12 +94,12 @@ void rt_hw_board_init(void) #endif #ifdef RT_USING_HEAP - rt_system_heap_init((void*)RT_HW_HEAP_BEGIN, (void*)RT_HW_HEAP_END); + rt_system_heap_init((void *)RT_HW_HEAP_BEGIN, (void *)RT_HW_HEAP_END); #endif /* init operating system timer */ rt_hw_timer_init(); - + #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif diff --git a/bsp/ls2kdev/drivers/clk.c b/bsp/ls2kdev/drivers/clk.c index 7a043e9ff4..b919713490 100644 --- a/bsp/ls2kdev/drivers/clk.c +++ b/bsp/ls2kdev/drivers/clk.c @@ -14,7 +14,8 @@ #include #include "ls2k1000.h" -struct loongson_pll { +struct loongson_pll +{ rt_uint64_t PLL_SYS_0; rt_uint64_t PLL_SYS_1; rt_uint64_t PLL_DDR_0; diff --git a/bsp/ls2kdev/drivers/drv_gpio.c b/bsp/ls2kdev/drivers/drv_gpio.c index 40a859082a..73a806afb2 100644 --- a/bsp/ls2kdev/drivers/drv_gpio.c +++ b/bsp/ls2kdev/drivers/drv_gpio.c @@ -25,7 +25,8 @@ static void loongson_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t gpio = (void *)device->user_data; m = (rt_uint64_t)1 << pin; - switch (mode) { + switch (mode) + { case PIN_MODE_OUTPUT: gpio->GPIO0_OEN &= ~m; break; @@ -52,7 +53,8 @@ static void loongson_pin_write(struct rt_device *device, rt_base_t pin, rt_base_ struct loongson_gpio *gpio; rt_uint64_t m; - if (pin < 0 || pin >= 60) { + if (pin < 0 || pin >= 60) + { rt_kprintf("error\n"); return; } @@ -90,11 +92,11 @@ static rt_err_t loongson_pin_attach_irq(struct rt_device *device, rt_int32_t pin gpio = (void *)device->user_data; - if(pin < 4) + if (pin < 4) { index = pin; } - else if(pin < 32) + else if (pin < 32) { index = 5; } @@ -102,7 +104,7 @@ static rt_err_t loongson_pin_attach_irq(struct rt_device *device, rt_int32_t pin { index = 6; } - + _g_gpio_irq_tbl[index].irq_cb[pin] = hdr; _g_gpio_irq_tbl[index].irq_arg[pin] = args; _g_gpio_irq_tbl[index].irq_type[pin] = mode; @@ -120,11 +122,11 @@ static rt_err_t loongson_pin_detach_irq(struct rt_device *device, rt_int32_t pin gpio = (void *)device->user_data; rt_uint8_t index; - if(pin < 4) + if (pin < 4) { index = pin; } - else if(pin < 32) + else if (pin < 32) { index = 5; } @@ -146,11 +148,11 @@ static rt_err_t loongson_pin_irq_enable(struct rt_device *device, rt_base_t pin, gpio = (void *)device->user_data; rt_uint8_t index; - if(pin < 4) + if (pin < 4) { index = pin; } - else if(pin < 32) + else if (pin < 32) { index = 5; } @@ -173,23 +175,23 @@ static void gpio_irq_handler(int irq, void *param) rt_uint32_t value; rt_uint32_t tmpvalue; - if(irq == LS2K_GPIO0_INT_IRQ) + if (irq == LS2K_GPIO0_INT_IRQ) { pin = 0; } - else if(irq == LS2K_GPIO1_INT_IRQ) + else if (irq == LS2K_GPIO1_INT_IRQ) { pin = 1; } - else if(irq == LS2K_GPIO2_INT_IRQ) + else if (irq == LS2K_GPIO2_INT_IRQ) { pin = 2; } - else if(irq == LS2K_GPIO3_INT_IRQ) + else if (irq == LS2K_GPIO3_INT_IRQ) { pin = 3; } - else if(irq == LS2K_GPIO_INTLO_IRQ) + else if (irq == LS2K_GPIO_INTLO_IRQ) { pin = 4; } @@ -197,12 +199,12 @@ static void gpio_irq_handler(int irq, void *param) { pin = 32; } - + while (value) { if ((value & 0x1) && (irq_def->irq_cb[pin] != RT_NULL)) { - if(irq_def->state[pin]) + if (irq_def->state[pin]) { irq_def->irq_cb[pin](irq_def->irq_arg[pin]); } @@ -212,7 +214,8 @@ static void gpio_irq_handler(int irq, void *param) } } -static struct rt_pin_ops loongson_pin_ops = { +static struct rt_pin_ops loongson_pin_ops = +{ .pin_mode = loongson_pin_mode, .pin_write = loongson_pin_write, .pin_read = loongson_pin_read, diff --git a/bsp/ls2kdev/drivers/drv_pwm.c b/bsp/ls2kdev/drivers/drv_pwm.c index f703d7834a..1b5c98755d 100644 --- a/bsp/ls2kdev/drivers/drv_pwm.c +++ b/bsp/ls2kdev/drivers/drv_pwm.c @@ -28,7 +28,8 @@ #define CTRL_INVERT (1UL<<9) #define CTRL_DZONE (1UL<<10) -struct loongson_pwm { +struct loongson_pwm +{ rt_uint32_t __PAD0; rt_uint32_t low_buffer; rt_uint32_t full_buffer; @@ -91,7 +92,8 @@ static rt_err_t loongson_pwm_ioctl(struct rt_device_pwm *device, int cmd, void * cfg = (void *)arg; - switch (cmd) { + switch (cmd) + { case PWM_CMD_ENABLE: rc = loongson_pwm_enable(device, cfg->channel); break; @@ -111,18 +113,21 @@ static rt_err_t loongson_pwm_ioctl(struct rt_device_pwm *device, int cmd, void * return rc; } -struct rt_pwm_ops loongson_pwm_ops = { +struct rt_pwm_ops loongson_pwm_ops = +{ .control = loongson_pwm_ioctl, }; -struct rt_device_pwm loongson_pwm = { +struct rt_device_pwm loongson_pwm = +{ .ops = &loongson_pwm_ops, }; int loongson_pwm_init(void) { int rc = RT_EOK; - static rt_uint32_t *priv[] = { + static rt_uint32_t *priv[] = + { (void *)PWM0_BASE, (void *)PWM1_BASE, (void *)PWM2_BASE, diff --git a/bsp/ls2kdev/drivers/drv_rtc.c b/bsp/ls2kdev/drivers/drv_rtc.c index ee125122e3..ef8dfcda82 100644 --- a/bsp/ls2kdev/drivers/drv_rtc.c +++ b/bsp/ls2kdev/drivers/drv_rtc.c @@ -19,7 +19,8 @@ #ifdef RT_USING_RTC -struct loongson_rtc { +struct loongson_rtc +{ rt_uint32_t sys_toytrim; rt_uint32_t sys_toywrite0; rt_uint32_t sys_toywrite1; @@ -45,7 +46,8 @@ struct loongson_rtc { #define __BF(number, n, m) __RBF((number>>m), (n-m+1)) #define BF(number, n, m) (msys_rtcread0; tmptime = *localrtctime(&rtctm); - switch (cmd) { + switch (cmd) + { case RT_DEVICE_CTRL_RTC_GET_TIME: *t = mktime(&tmptime); break; @@ -164,7 +167,8 @@ static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args) int rt_hw_rtc_init(void) { - static struct rt_device rtc = { + static struct rt_device rtc = + { .type = RT_Device_Class_RTC, .init = RT_NULL, .open = rt_rtc_open, diff --git a/bsp/ls2kdev/drivers/drv_spi.c b/bsp/ls2kdev/drivers/drv_spi.c index 83ee66b7a9..5249cc7c51 100644 --- a/bsp/ls2kdev/drivers/drv_spi.c +++ b/bsp/ls2kdev/drivers/drv_spi.c @@ -11,142 +11,144 @@ -static void spi_init(uint8_t spre_spr,uint8_t copl,uint8_t cpha) -{ - //rt_kprintf("SPI initiating with spre_spr:%2X ,copl:%2X ,cpha:%2X\n",spre_spr,copl,cpha); - int d; - SET_SPI(SPSR, 0xc0|(spre_spr&0b00000011)); - SET_SPI(PARAM, 0x40); - SET_SPI(PARAM2,0x01); - SET_SPI(SPER, (spre_spr&0b00001100)>>2); - SET_SPI(SPCR, 0x50|copl<<3|cpha<<2); - SET_SPI(SOFTCS,0xff); +static void spi_init(uint8_t spre_spr, uint8_t copl, uint8_t cpha) +{ + //rt_kprintf("SPI initiating with spre_spr:%2X ,copl:%2X ,cpha:%2X\n",spre_spr,copl,cpha); + int d; + SET_SPI(SPSR, 0xc0 | (spre_spr & 0b00000011)); + SET_SPI(PARAM, 0x40); + SET_SPI(PARAM2, 0x01); + SET_SPI(SPER, (spre_spr & 0b00001100) >> 2); + SET_SPI(SPCR, 0x50 | copl << 3 | cpha << 2); + SET_SPI(SOFTCS, 0xff); } static void spi_set_csn(uint8_t val) //old method { - SET_SPI(SOFTCS,val); + SET_SPI(SOFTCS, val); } // #define RT_USING_SPI_GPIOCS #ifdef RT_USING_SPI_GPIOCS -#include + #include #endif static void spi_set_cs(unsigned char cs, int new_status) { - if(cs<4){ + if (cs < 4) + { unsigned char val = 0; - val = GET_SPI(SOFTCS); - val |= 0x01 << cs ; // csen=1 - if (new_status) // cs = 1 - { - val |= (0x10 << cs); // csn=1 - } - else // cs = 0 - { - val &= ~(0x10 << cs); // csn=0 - } - SET_SPI(SOFTCS,val); + val = GET_SPI(SOFTCS); + val |= 0x01 << cs ; // csen=1 + if (new_status) // cs = 1 + { + val |= (0x10 << cs); // csn=1 + } + else // cs = 0 + { + val &= ~(0x10 << cs); // csn=0 + } + SET_SPI(SOFTCS, val); - return ; + return ; } - #ifdef RT_USING_SPI_GPIOCS - else{ +#ifdef RT_USING_SPI_GPIOCS + else + { //rt_kprintf("[Warnning] GPIOCS is an experimental feature: \n "); //rt_kprintf("[Warnning] GPIO%d will be set to OUTPUT with value %d \n ",cs,new_status); - rt_pin_mode(cs,PIN_MODE_OUTPUT); - rt_pin_write(cs,new_status); + rt_pin_mode(cs, PIN_MODE_OUTPUT); + rt_pin_write(cs, new_status); } - #endif +#endif } static uint8_t spi_write_for_response(uint8_t data) { - uint8_t val; - SET_SPI(TXFIFO,data); - while((GET_SPI(SPSR))&RFEMPTY);//wait for echo - val = GET_SPI(RXFIFO); - return val; + uint8_t val; + SET_SPI(TXFIFO, data); + while ((GET_SPI(SPSR))&RFEMPTY); //wait for echo + val = GET_SPI(RXFIFO); + return val; } -static int cmd_spi_init(int argc,char* argv[]) +static int cmd_spi_init(int argc, char *argv[]) { - uint8_t spre_spr,cpol,cpha; - switch (argc) - { - case 2: - - spre_spr=strtoul(argv[1], NULL, 0); - spi_init(spre_spr,0,0); - break; - case 4: - - spre_spr=strtoul(argv[1], NULL, 0); - cpol=strtoul(argv[2], NULL, 0); - cpha=strtoul(argv[3], NULL, 0); - spi_init(spre_spr,0,0); - break; - - default: - printf("\nusage : cmd_spi_init spre_spr \n(cmd_spi_init 0x4 0x0 0x0)\n0x4:div8 0xb:div4096\n"); - break; - } -} -MSH_CMD_EXPORT(cmd_spi_init,cmd_spi_init); + uint8_t spre_spr, cpol, cpha; + switch (argc) + { + case 2: -static int cmd_spi_set_csn(int argc,char* argv[]) -{ - uint8_t val,csn; - switch (argc) - { - case 3: - csn=strtoul(argv[1], NULL, 0); - val=strtoul(argv[2], NULL, 0); - spi_set_cs(csn,val); - break; - - default: - printf("usage:cmd_spi_set_csn csn val\n(0xbf for csn1 enable,0xff for csn1 disable)\n"); - break; - } -} -MSH_CMD_EXPORT(cmd_spi_set_csn,cmd_spi_set_csn); + spre_spr = strtoul(argv[1], NULL, 0); + spi_init(spre_spr, 0, 0); + break; + case 4: -static int cmd_spi_write(int argc,char* argv[]) -{ - uint8_t data,resp; - switch (argc) - { - case 2: - - data=strtoul(argv[1], NULL, 0); - resp=spi_write_for_response(data); - printf("resp:%2X\n",resp); - break; - - default: - printf("usage:cmd_spi_write data\n"); - break; - } + spre_spr = strtoul(argv[1], NULL, 0); + cpol = strtoul(argv[2], NULL, 0); + cpha = strtoul(argv[3], NULL, 0); + spi_init(spre_spr, 0, 0); + break; + + default: + printf("\nusage : cmd_spi_init spre_spr \n(cmd_spi_init 0x4 0x0 0x0)\n0x4:div8 0xb:div4096\n"); + break; + } } -MSH_CMD_EXPORT(cmd_spi_write,cmd_spi_write); +MSH_CMD_EXPORT(cmd_spi_init, cmd_spi_init); + +static int cmd_spi_set_csn(int argc, char *argv[]) +{ + uint8_t val, csn; + switch (argc) + { + case 3: + csn = strtoul(argv[1], NULL, 0); + val = strtoul(argv[2], NULL, 0); + spi_set_cs(csn, val); + break; + + default: + printf("usage:cmd_spi_set_csn csn val\n(0xbf for csn1 enable,0xff for csn1 disable)\n"); + break; + } +} +MSH_CMD_EXPORT(cmd_spi_set_csn, cmd_spi_set_csn); + +static int cmd_spi_write(int argc, char *argv[]) +{ + uint8_t data, resp; + switch (argc) + { + case 2: + + data = strtoul(argv[1], NULL, 0); + resp = spi_write_for_response(data); + printf("resp:%2X\n", resp); + break; + + default: + printf("usage:cmd_spi_write data\n"); + break; + } +} +MSH_CMD_EXPORT(cmd_spi_write, cmd_spi_write); static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message); -const static unsigned char SPI_DIV_TABLE[]={0b0000,0b0001,0b0100,0b0010,0b0011,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011}; - // 2 4 8 16 32 64 128 256 512 1024 2048 4096 +const static unsigned char SPI_DIV_TABLE[] = {0b0000, 0b0001, 0b0100, 0b0010, 0b0011, 0b0101, 0b0110, 0b0111, 0b1000, 0b1001, 0b1010, 0b1011}; +// 2 4 8 16 32 64 128 256 512 1024 2048 4096 static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) { - + unsigned char cpol = 0; unsigned char cpha = 0; @@ -173,21 +175,22 @@ static rt_err_t configure(struct rt_spi_device *device, cpha = 0; } //rt_kprintf("configure: cpol:%d cpha:%d\n",cpol,cpha); - - - float spi_max_speed=((float)APB_MAX_SPEED)/(8.0/(float)APB_FREQSCALE); + + + float spi_max_speed = ((float)APB_MAX_SPEED) / (8.0 / (float)APB_FREQSCALE); //rt_kprintf("spi max speed: %ld\n",(unsigned long)spi_max_speed); - - uint64_t div=(uint64_t)(spi_max_speed/(float)configuration->max_hz); + + uint64_t div = (uint64_t)(spi_max_speed / (float)configuration->max_hz); //rt_kprintf("require speed: %ld\n",configuration->max_hz); - int ctr=0; - while(div!=1 && ctr<12){ + int ctr = 0; + while (div != 1 && ctr < 12) + { ctr++; - div=div>>1; + div = div >> 1; } //rt_kprintf("spi speed set to: %ld\n",(unsigned long)((spi_max_speed)/(float)(1<parent.user_data); + cs = (unsigned char)(device->parent.user_data); size = message->length; //rt_kprintf("[%s] cs=%d\n", __FUNCTION__, cs); @@ -258,9 +261,9 @@ static struct rt_spi_ops loongson_spi_ops = static struct rt_spi_bus loongson_spi; static int loongson_spi_init() -{ +{ //rt_kprintf("spi_init\n"); - return rt_spi_bus_register(&loongson_spi,"spi",&loongson_spi_ops); + return rt_spi_bus_register(&loongson_spi, "spi", &loongson_spi_ops); } INIT_BOARD_EXPORT(loongson_spi_init); diff --git a/bsp/ls2kdev/drivers/drv_uart.c b/bsp/ls2kdev/drivers/drv_uart.c index 7a59d12d32..29c58728ef 100644 --- a/bsp/ls2kdev/drivers/drv_uart.c +++ b/bsp/ls2kdev/drivers/drv_uart.c @@ -22,41 +22,42 @@ #define TRUE 1 #define FALSE 0 -const struct serial_configure config_uart0 = { - BAUD_RATE_115200, /* 921600 bits/s */ - DATA_BITS_8, /* 8 databits */ - STOP_BITS_1, /* 1 stopbit */ - PARITY_NONE, /* No parity */ - BIT_ORDER_LSB, /* LSB first sent */ - NRZ_NORMAL, /* Normal mode */ - RT_SERIAL_RB_BUFSZ, /* Buffer size */ - 0 +const struct serial_configure config_uart0 = +{ + BAUD_RATE_115200, /* 921600 bits/s */ + DATA_BITS_8, /* 8 databits */ + STOP_BITS_1, /* 1 stopbit */ + PARITY_NONE, /* No parity */ + BIT_ORDER_LSB, /* LSB first sent */ + NRZ_NORMAL, /* Normal mode */ + RT_SERIAL_RB_BUFSZ, /* Buffer size */ + 0 }; struct rt_uart_ls2k { void *base; rt_uint32_t IRQ; }; -static rt_err_t ls2k_uart_set_buad(struct rt_serial_device *serial,struct serial_configure *cfg) +static rt_err_t ls2k_uart_set_buad(struct rt_serial_device *serial, struct serial_configure *cfg) { struct rt_uart_ls2k *uart_dev = RT_NULL; - rt_err_t ret=RT_EOK; + rt_err_t ret = RT_EOK; RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - - uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data; - uint64_t brtc = (125000000U) / (16*(cfg->baud_rate)); - UART_LCR(uart_dev->base)=0x80; // Activate buadcfg - UART_LSB(uart_dev->base)= brtc & 0xff; - UART_MSB(uart_dev->base)= brtc >> 8; - if(((((short)UART_MSB(uart_dev->base))<<8) | UART_LSB(uart_dev->base)) != brtc) ret=RT_ERROR; - - UART_LCR(uart_dev->base)= CFCR_8BITS;// Back to normal - UART_MCR(uart_dev->base)= MCR_IENABLE/* | MCR_DTR | MCR_RTS*/; - UART_IER(uart_dev->base) = 0; + uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data; + uint64_t brtc = (125000000U) / (16 * (cfg->baud_rate)); + UART_LCR(uart_dev->base) = 0x80; // Activate buadcfg + UART_LSB(uart_dev->base) = brtc & 0xff; + UART_MSB(uart_dev->base) = brtc >> 8; + + if (((((short)UART_MSB(uart_dev->base)) << 8) | UART_LSB(uart_dev->base)) != brtc) ret = RT_ERROR; + + UART_LCR(uart_dev->base) = CFCR_8BITS; // Back to normal + UART_MCR(uart_dev->base) = MCR_IENABLE/* | MCR_DTR | MCR_RTS*/; + UART_IER(uart_dev->base) = 0; } static rt_err_t ls2k_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { @@ -64,9 +65,9 @@ static rt_err_t ls2k_uart_configure(struct rt_serial_device *serial, struct seri RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - ls2k_uart_set_buad(serial,cfg); + ls2k_uart_set_buad(serial, cfg); uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data; - HWREG8(0xffffffffbfe10428)=0x1f;// Enable Multi-Port Support, by default it's 0x11 ,which means UART0 & UART4 Controller is in single port mode. + HWREG8(0xffffffffbfe10428) = 0x1f; // Enable Multi-Port Support, by default it's 0x11 ,which means UART0 & UART4 Controller is in single port mode. UART_IER(uart_dev->base) = 0; /* clear interrupt */ UART_FCR(uart_dev->base) = 0xc1; /* reset UART Rx/Tx */ /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */ @@ -93,7 +94,7 @@ static rt_err_t ls2k_uart_control(struct rt_serial_device *serial, int cmd, void case RT_DEVICE_CTRL_SET_INT: /* Enable RX IRQ */ rt_hw_interrupt_umask(uart_dev->IRQ); - UART_IER(uart_dev->base) |= (IER_IRxE|IER_ILE); + UART_IER(uart_dev->base) |= (IER_IRxE | IER_ILE); break; default: @@ -187,29 +188,29 @@ struct rt_uart_ls2k uart_dev0 = struct rt_uart_ls2k uart_dev4 = { (void *)UARTx_BASE(4), - LS2K_UART_4_5_6_7_IRQ , + LS2K_UART_4_5_6_7_IRQ, }; -struct rt_serial_device serial,serial4; +struct rt_serial_device serial, serial4; void rt_hw_uart_init(void) { //UART0_1_ENABLE=0xff; - struct rt_uart_ls2k *uart,*uart4; + struct rt_uart_ls2k *uart, *uart4; struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - - + + uart = &uart_dev0; - uart4=&uart_dev4; + uart4 = &uart_dev4; serial.ops = &ls2k_uart_ops; serial.config = config_uart0; - serial4.ops= &ls2k_uart_ops; - serial4.config=config; + serial4.ops = &ls2k_uart_ops; + serial4.config = config; rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART0"); @@ -223,8 +224,8 @@ void rt_hw_uart_init(void) rt_hw_serial_register(&serial4, "uart4", - RT_DEVICE_FLAG_RDWR| RT_DEVICE_FLAG_INT_RX, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart_dev4); - + } /*@}*/ diff --git a/bsp/ls2kdev/drivers/interrupt.c b/bsp/ls2kdev/drivers/interrupt.c index 97f5994ec7..9e9c210aa0 100644 --- a/bsp/ls2kdev/drivers/interrupt.c +++ b/bsp/ls2kdev/drivers/interrupt.c @@ -58,24 +58,24 @@ static void liointc_init(void) //set irq mode void liointc_set_irq_mode(int irq, int mode) { - if(irq < 32) + if (irq < 32) { - if(mode == PIN_IRQ_MODE_RISING) + if (mode == PIN_IRQ_MODE_RISING) { HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) |= (0x0 << (irq)); HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq)); } - else if(mode == PIN_IRQ_MODE_FALLING) + else if (mode == PIN_IRQ_MODE_FALLING) { HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq)); HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq)); } - else if(mode == PIN_IRQ_MODE_HIGH_LEVEL) + else if (mode == PIN_IRQ_MODE_HIGH_LEVEL) { HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq)); HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq)); } - else if(mode == PIN_IRQ_MODE_LOW_LEVEL) + else if (mode == PIN_IRQ_MODE_LOW_LEVEL) { HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_POL) |= (0x0 << (irq)); HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq)); @@ -88,22 +88,22 @@ void liointc_set_irq_mode(int irq, int mode) } else { - if(mode == PIN_IRQ_MODE_RISING) + if (mode == PIN_IRQ_MODE_RISING) { HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) |= (0x0 << (irq - 32)); HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq - 32)); } - else if(mode == PIN_IRQ_MODE_FALLING) + else if (mode == PIN_IRQ_MODE_FALLING) { HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq - 32)); HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x1 << (irq - 32)); } - else if(mode == PIN_IRQ_MODE_HIGH_LEVEL) + else if (mode == PIN_IRQ_MODE_HIGH_LEVEL) { HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) |= (0x1 << (irq - 32)); HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq - 32)); } - else if(mode == PIN_IRQ_MODE_LOW_LEVEL) + else if (mode == PIN_IRQ_MODE_LOW_LEVEL) { HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_POL) |= (0x0 << (irq - 32)); HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_EDGE) |= (0x0 << (irq - 32)); @@ -166,7 +166,7 @@ void rt_hw_interrupt_init(void) } rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) + void *param, const char *name) { rt_isr_handler_t old_handler = RT_NULL; @@ -181,7 +181,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, irq_handle_table[vector].param = param; } - if(vector <= 32) + if (vector <= 32) { mips_unmask_cpu_irq(2); } @@ -189,7 +189,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, { mips_unmask_cpu_irq(3); } - + return old_handler; } @@ -213,11 +213,11 @@ void rt_do_mips_cpu_irq(rt_uint32_t ip) void rt_hw_interrupt_umask(int irq) { - if(irq < LIOINTC0_IRQBASE + 32) + if (irq < LIOINTC0_IRQBASE + 32) { HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_ENABLE) = (1 << irq); } - else if(irq < LIOINTC1_IRQBASE + 32) + else if (irq < LIOINTC1_IRQBASE + 32) { HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_ENABLE) = (1 << (irq - 32)); } @@ -225,11 +225,11 @@ void rt_hw_interrupt_umask(int irq) void rt_hw_interrupt_mask(int irq) { - if(irq < LIOINTC0_IRQBASE + 32) + if (irq < LIOINTC0_IRQBASE + 32) { HWREG32(LIOINTC0_BASE + LIOINTC_REG_INTC_DISABLE) = (1 << irq); } - else if(irq < LIOINTC1_IRQBASE + 32) + else if (irq < LIOINTC1_IRQBASE + 32) { HWREG32(LIOINTC1_BASE + LIOINTC_REG_INTC_DISABLE) = (1 << (irq - 32)); } diff --git a/bsp/ls2kdev/drivers/net/mii.c b/bsp/ls2kdev/drivers/net/mii.c index a0b3a7adce..d83caef6de 100644 --- a/bsp/ls2kdev/drivers/net/mii.c +++ b/bsp/ls2kdev/drivers/net/mii.c @@ -9,7 +9,7 @@ */ #include "mii.h" -static inline unsigned int mii_nway_result (unsigned int negotiated) +static inline unsigned int mii_nway_result(unsigned int negotiated) { unsigned int ret; @@ -32,7 +32,8 @@ static int mii_check_gmii_support(struct mii_if_info *mii) int reg; reg = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); - if (reg & BMSR_ESTATEN) { + if (reg & BMSR_ESTATEN) + { reg = mii->mdio_read(mii->dev, mii->phy_id, MII_ESTATUS); if (reg & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) return 1; @@ -43,7 +44,7 @@ static int mii_check_gmii_support(struct mii_if_info *mii) static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) { - struct synopGMACNetworkAdapter * dev = mii->dev; + struct synopGMACNetworkAdapter *dev = mii->dev; u32 advert, bmcr, lpa, nego; u32 advert2 = 0, bmcr2 = 0, lpa2 = 0; @@ -53,7 +54,7 @@ static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII); if (mii->supports_gmii) ecmd->supported |= SUPPORTED_1000baseT_Half | - SUPPORTED_1000baseT_Full; + SUPPORTED_1000baseT_Full; /* only supports twisted-pair */ ecmd->port = PORT_MII; @@ -84,36 +85,43 @@ static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA); - if (mii->supports_gmii) { + if (mii->supports_gmii) + { bmcr2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000); lpa2 = mii->mdio_read(dev, mii->phy_id, MII_STAT1000); } - if (bmcr & BMCR_ANENABLE) { + if (bmcr & BMCR_ANENABLE) + { ecmd->advertising |= ADVERTISED_Autoneg; ecmd->autoneg = AUTONEG_ENABLE; - + nego = mii_nway_result(advert & lpa); - if ((bmcr2 & (ADVERTISE_1000HALF | ADVERTISE_1000FULL)) & - (lpa2 >> 2)) + if ((bmcr2 & (ADVERTISE_1000HALF | ADVERTISE_1000FULL)) & + (lpa2 >> 2)) ecmd->speed = SPEED_1000; else if (nego == LPA_100FULL || nego == LPA_100HALF) ecmd->speed = SPEED_100; else ecmd->speed = SPEED_10; if ((lpa2 & LPA_1000FULL) || nego == LPA_100FULL || - nego == LPA_10FULL) { + nego == LPA_10FULL) + { ecmd->duplex = DUPLEX_FULL; mii->full_duplex = 1; - } else { + } + else + { ecmd->duplex = DUPLEX_HALF; mii->full_duplex = 0; } - } else { + } + else + { ecmd->autoneg = AUTONEG_DISABLE; - ecmd->speed = ((bmcr & BMCR_SPEED1000 && - (bmcr & BMCR_SPEED100) == 0) ? SPEED_1000 : - (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10); + ecmd->speed = ((bmcr & BMCR_SPEED1000 && + (bmcr & BMCR_SPEED100) == 0) ? SPEED_1000 : + (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10); ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; } @@ -122,7 +130,7 @@ static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) return 0; } -static int mii_link_ok (struct mii_if_info *mii) +static int mii_link_ok(struct mii_if_info *mii) { /* first, a dummy read, needed to latch some MII phys */ mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); diff --git a/bsp/ls2kdev/drivers/net/synopGMAC.c b/bsp/ls2kdev/drivers/net/synopGMAC.c index f3ffec6892..22e51de712 100644 --- a/bsp/ls2kdev/drivers/net/synopGMAC.c +++ b/bsp/ls2kdev/drivers/net/synopGMAC.c @@ -119,7 +119,7 @@ s32 synopGMAC_setup_tx_desc_queue(synopGMACdevice *gmacdev, u32 no_of_desc, u32 gmacdev->TxDescCount = 0; first_desc = (DmaDesc *)plat_alloc_consistent_dmaable_memory(gmacdev, sizeof(DmaDesc) * (no_of_desc), &dma_addr); - + if (first_desc == NULL) { rt_kprintf("Error in Tx Descriptors memory allocation\n"); @@ -300,7 +300,7 @@ static rt_err_t eth_init(rt_device_t device) { struct eth_device *eth_device = (struct eth_device *)device; RT_ASSERT(eth_device != RT_NULL); - + s32 ijk; s32 status = 0; u64 dma_addr; @@ -490,7 +490,7 @@ rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p) dma_addr = plat_dma_map_single(gmacdev, (void *)pbuf, p->tot_len); status = synopGMAC_set_tx_qptr(gmacdev, dma_addr, p->tot_len, pbuf, 0, 0, 0, offload_needed, &index, dpr); - + if (status < 0) { rt_kprintf("%s No More Free Tx Descriptors\n", __FUNCTION__); @@ -501,7 +501,7 @@ rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p) } synopGMAC_resume_dma_tx(gmacdev); - + s32 desc_index; u64 data1, data2; @@ -598,48 +598,48 @@ struct pbuf *rt_eth_rx(rt_device_t device) } /*Handle the Receive Descriptors*/ - desc_index = synopGMAC_get_rx_qptr(gmacdev, &status, &dma_addr1, NULL, &data1, &dma_addr2, NULL, &data2); + desc_index = synopGMAC_get_rx_qptr(gmacdev, &status, &dma_addr1, NULL, &data1, &dma_addr2, NULL, &data2); - if(((u32)desc_index >= RECEIVE_DESC_SIZE) && (desc_index != -1)) + if (((u32)desc_index >= RECEIVE_DESC_SIZE) && (desc_index != -1)) + { + rt_kprintf("host receive descriptor address pointer = 0x%08x\n", synopGMACReadReg(gmacdev->DmaBase, DmaRxCurrDesc)); + rt_kprintf("host receive buffer = 0x%08x\n", synopGMACReadReg(gmacdev->DmaBase, DmaRxCurrAddr)); + rt_kprintf("desc_index error!!!!,tick = %d\n", rt_tick_get()); + while (1); + } + + if (desc_index >= 0 && data1 != 0) + { + DEBUG_MES("Received Data at Rx Descriptor %d for skb 0x%08x whose status is %08x\n", desc_index, dma_addr1, status); + + if (synopGMAC_is_rx_desc_valid(status) || SYNOP_PHY_LOOPBACK) { - rt_kprintf("host receive descriptor address pointer = 0x%08x\n",synopGMACReadReg(gmacdev->DmaBase,DmaRxCurrDesc)); - rt_kprintf("host receive buffer = 0x%08x\n",synopGMACReadReg(gmacdev->DmaBase,DmaRxCurrAddr)); - rt_kprintf("desc_index error!!!!,tick = %d\n",rt_tick_get()); - while(1); + dma_addr1 = plat_dma_map_single(gmacdev, (void *)data1, RX_BUF_SIZE); + len = synopGMAC_get_rx_desc_frame_length(status) - 4; //Not interested in Ethernet CRC bytes + pbuf = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); + if (pbuf == 0) rt_kprintf("===error in pbuf_alloc\n"); + rt_memcpy(pbuf->payload, (char *)data1, len); + DEBUG_MES("==get pkg len: %d\n", len); } - - if (desc_index >= 0 && data1 != 0) + else + { + rt_kprintf("s: %08x\n", status); + adapter->synopGMACNetStats.rx_errors++; + adapter->synopGMACNetStats.collisions += synopGMAC_is_rx_frame_collision(status); + adapter->synopGMACNetStats.rx_crc_errors += synopGMAC_is_rx_crc(status); + adapter->synopGMACNetStats.rx_frame_errors += synopGMAC_is_frame_dribbling_errors(status); + adapter->synopGMACNetStats.rx_length_errors += synopGMAC_is_rx_frame_length_errors(status); + } + desc_index = synopGMAC_set_rx_qptr(gmacdev, dma_addr1, RX_BUF_SIZE, (u64)data1, 0, 0, 0); + if (desc_index < 0) { - DEBUG_MES("Received Data at Rx Descriptor %d for skb 0x%08x whose status is %08x\n", desc_index, dma_addr1, status); - - if (synopGMAC_is_rx_desc_valid(status) || SYNOP_PHY_LOOPBACK) - { - dma_addr1 = plat_dma_map_single(gmacdev, (void *)data1, RX_BUF_SIZE); - len = synopGMAC_get_rx_desc_frame_length(status)-4; //Not interested in Ethernet CRC bytes - pbuf = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); - if (pbuf == 0) rt_kprintf("===error in pbuf_alloc\n"); - rt_memcpy(pbuf->payload, (char *)data1, len); - DEBUG_MES("==get pkg len: %d\n", len); - } - else - { - rt_kprintf("s: %08x\n", status); - adapter->synopGMACNetStats.rx_errors++; - adapter->synopGMACNetStats.collisions += synopGMAC_is_rx_frame_collision(status); - adapter->synopGMACNetStats.rx_crc_errors += synopGMAC_is_rx_crc(status); - adapter->synopGMACNetStats.rx_frame_errors += synopGMAC_is_frame_dribbling_errors(status); - adapter->synopGMACNetStats.rx_length_errors += synopGMAC_is_rx_frame_length_errors(status); - } - desc_index = synopGMAC_set_rx_qptr(gmacdev, dma_addr1, RX_BUF_SIZE, (u64)data1, 0, 0, 0); - if (desc_index < 0) - { #if SYNOP_RX_DEBUG - rt_kprintf("Cannot set Rx Descriptor for data1 %08x\n", (u32)data1); + rt_kprintf("Cannot set Rx Descriptor for data1 %08x\n", (u32)data1); #endif - - plat_free_memory((void *)data1); - } + + plat_free_memory((void *)data1); } + } rt_sem_release(&sem_lock); DEBUG_MES("%s : before return \n", __FUNCTION__); return pbuf; @@ -930,7 +930,7 @@ int rt_hw_eth_init(void) rt_kprintf("Error in Memory Allocataion, Founction : %s \n", __FUNCTION__); } memset((char *)synopGMACadapter, 0, sizeof(struct synopGMACNetworkAdapter)); - + synopGMACadapter->synopGMACdev = NULL; synopGMACadapter->synopGMACdev = (synopGMACdevice *) plat_alloc_memory(sizeof(synopGMACdevice)); @@ -940,13 +940,13 @@ int rt_hw_eth_init(void) } memset((char *)synopGMACadapter->synopGMACdev, 0, sizeof(synopGMACdevice)); - + /* * Attach the device to MAC struct This will configure all the required base addresses * such as Mac base, configuration base, phy base address(out of 32 possible phys) * */ synopGMAC_attach(synopGMACadapter->synopGMACdev, (gmac_base + MACBASE), gmac_base + DMABASE, DEFAULT_PHY_BASE, mac_addr0); - + init_phy(synopGMACadapter->synopGMACdev); synopGMAC_reset(synopGMACadapter->synopGMACdev); @@ -980,7 +980,7 @@ int rt_hw_eth_init(void) eth_dev.parent.eth_tx = rt_eth_tx; eth_dev.parent.eth_rx = rt_eth_rx; - + eth_device_init(&(eth_dev.parent), "e0"); eth_device_linkchange(ð_dev.parent, RT_TRUE); //linkup the e0 for lwip to check return 0; diff --git a/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c b/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c index cdd4585670..e6fea9f2ec 100644 --- a/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c +++ b/bsp/ls2kdev/drivers/net/synopGMAC_Dev.c @@ -22,13 +22,13 @@ * @param[in] clk divider value. * \return Reuturns 0 on success else return the error value. */ -s32 synopGMAC_set_mdc_clk_div(synopGMACdevice *gmacdev,u32 clk_div_val) +s32 synopGMAC_set_mdc_clk_div(synopGMACdevice *gmacdev, u32 clk_div_val) { u32 orig_data; - orig_data = synopGMACReadReg(gmacdev -> MacBase,GmacGmiiAddr);//set the mdc clock to the user defined value - orig_data &= (~GmiiCsrClkMask); + orig_data = synopGMACReadReg(gmacdev -> MacBase, GmacGmiiAddr); //set the mdc clock to the user defined value + orig_data &= (~GmiiCsrClkMask); orig_data |= clk_div_val; - synopGMACWriteReg(gmacdev -> MacBase,GmacGmiiAddr,orig_data); + synopGMACWriteReg(gmacdev -> MacBase, GmacGmiiAddr, orig_data); return 0; } @@ -42,7 +42,7 @@ s32 synopGMAC_set_mdc_clk_div(synopGMACdevice *gmacdev,u32 clk_div_val) u32 synopGMAC_get_mdc_clk_div(synopGMACdevice *gmacdev) { u32 data; - data = synopGMACReadReg(gmacdev->MacBase,GmacGmiiAddr); + data = synopGMACReadReg(gmacdev->MacBase, GmacGmiiAddr); data &= GmiiCsrClkMask; return data; } @@ -57,21 +57,21 @@ u32 synopGMAC_get_mdc_clk_div(synopGMACdevice *gmacdev) * @param[out] u16 data read from the respective phy register (only valid iff return value is 0). * \return Returns 0 on success else return the error status. */ -s32 synopGMAC_read_phy_reg(u64 RegBase,u32 PhyBase, u32 RegOffset, u16 * data ) +s32 synopGMAC_read_phy_reg(u64 RegBase, u32 PhyBase, u32 RegOffset, u16 *data) { u64 addr; u32 loop_variable; - addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) - | GmiiCsrClk3; //sw: add GmiiCsrClk + addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) + | GmiiCsrClk3; //sw: add GmiiCsrClk addr = addr | GmiiBusy ; //Gmii busy bit - synopGMACWriteReg(RegBase,GmacGmiiAddr,addr); + synopGMACWriteReg(RegBase, GmacGmiiAddr, addr); //write the address from where the data to be read in GmiiGmiiAddr register of synopGMAC ip - for(loop_variable = 0;loop_variable < DEFAULT_LOOP_VARIABLE;loop_variable++) - { + for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) + { //Wait till the busy bit gets cleared within a certain amount of time - if (!(synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy)) + if (!(synopGMACReadReg(RegBase, GmacGmiiAddr) & GmiiBusy)) { break; } @@ -79,18 +79,18 @@ s32 synopGMAC_read_phy_reg(u64 RegBase,u32 PhyBase, u32 RegOffset, u16 * data ) plat_delay(DEFAULT_DELAY_VARIABLE); } - if(loop_variable < DEFAULT_LOOP_VARIABLE) + if (loop_variable < DEFAULT_LOOP_VARIABLE) { - *data = (u16)(synopGMACReadReg(RegBase,GmacGmiiData) & 0xFFFF); + *data = (u16)(synopGMACReadReg(RegBase, GmacGmiiData) & 0xFFFF); } else { TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); return -ESYNOPGMACPHYERR; } - //sw + //sw #if SYNOP_REG_DEBUG - printf("read phy reg: offset = 0x%x\tdata = 0x%x\n",RegOffset,*data); + printf("read phy reg: offset = 0x%x\tdata = 0x%x\n", RegOffset, *data); #endif return -ESYNOPGMACNOERR; @@ -110,16 +110,16 @@ s32 synopGMAC_write_phy_reg(u64 RegBase, u32 PhyBase, u32 RegOffset, u16 data) u32 addr; u32 loop_variable; - synopGMACWriteReg(RegBase,GmacGmiiData,data); // write the data in to GmacGmiiData register of synopGMAC ip + synopGMACWriteReg(RegBase, GmacGmiiData, data); // write the data in to GmacGmiiData register of synopGMAC ip addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) | GmiiWrite | GmiiCsrClk3; //sw: add GmiiCsrclk addr = addr | GmiiBusy ; //set Gmii clk to 20-35 Mhz and Gmii busy bit - synopGMACWriteReg(RegBase,GmacGmiiAddr,addr); - for(loop_variable = 0;loop_variable < DEFAULT_LOOP_VARIABLE;loop_variable++) + synopGMACWriteReg(RegBase, GmacGmiiAddr, addr); + for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) { - if (!(synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy)) + if (!(synopGMACReadReg(RegBase, GmacGmiiAddr) & GmiiBusy)) { break; } @@ -127,7 +127,7 @@ s32 synopGMAC_write_phy_reg(u64 RegBase, u32 PhyBase, u32 RegOffset, u16 data) plat_delay(DEFAULT_DELAY_VARIABLE); } - if(loop_variable < DEFAULT_LOOP_VARIABLE) + if (loop_variable < DEFAULT_LOOP_VARIABLE) { return -ESYNOPGMACNOERR; } @@ -137,28 +137,28 @@ s32 synopGMAC_write_phy_reg(u64 RegBase, u32 PhyBase, u32 RegOffset, u16 data) return -ESYNOPGMACPHYERR; } #if SYNOP_REG_DEBUG - printf("write phy reg: offset = 0x%x\tdata = 0x%x",RegOffset,data); + printf("write phy reg: offset = 0x%x\tdata = 0x%x", RegOffset, data); #endif } /** - * Function to configure the phy in loopback mode. + * Function to configure the phy in loopback mode. * * @param[in] pointer to synopGMACdevice. * @param[in] enable or disable the loopback. * \return 0 on success else return the error status. - * \note Don't get confused with mac loop-back synopGMAC_loopback_on(synopGMACdevice *) + * \note Don't get confused with mac loop-back synopGMAC_loopback_on(synopGMACdevice *) * and synopGMAC_loopback_off(synopGMACdevice *) functions. */ #if UNUSED -s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev,bool loopback) +s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback) { s32 status = -ESYNOPGMACNOERR; u16 temp; - status = synopGMAC_read_phy_reg(gmacdev -> MacBase, gmacdev -> PhyBase,PHY_CONTROL_REG,&temp); + status = synopGMAC_read_phy_reg(gmacdev -> MacBase, gmacdev -> PhyBase, PHY_CONTROL_REG, &temp); - if(loopback) + if (loopback) { temp |= 0x4000; } @@ -167,7 +167,7 @@ s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev,bool loopback) temp = temp; } - status = synopGMAC_write_phy_reg(gmacdev -> MacBase,gmacdev -> PhyBase,PHY_CONTROL_REG,temp); + status = synopGMAC_write_phy_reg(gmacdev -> MacBase, gmacdev -> PhyBase, PHY_CONTROL_REG, temp); return status; } @@ -179,60 +179,60 @@ s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev,bool loopback) * \return Always return 0. */ -s32 synopGMAC_read_version(synopGMACdevice *gmacdev) -{ +s32 synopGMAC_read_version(synopGMACdevice *gmacdev) +{ u32 data = 0; - data = synopGMACReadReg(gmacdev -> MacBase,GmacVersion); + data = synopGMACReadReg(gmacdev -> MacBase, GmacVersion); gmacdev -> Version = data; return 0; } /** - * Function to reset the GMAC core. + * Function to reset the GMAC core. * This reests the DMA and GMAC core. After reset all the registers holds their respective reset value * @param[in] pointer to synopGMACdevice. * \return 0 on success else return the error status. */ -s32 synopGMAC_reset(synopGMACdevice *gmacdev) -{ +s32 synopGMAC_reset(synopGMACdevice *gmacdev) +{ u32 data = 0; - synopGMACWriteReg(gmacdev -> DmaBase,DmaBusMode,DmaResetOn); + synopGMACWriteReg(gmacdev -> DmaBase, DmaBusMode, DmaResetOn); plat_delay(DEFAULT_LOOP_VARIABLE); - data = synopGMACReadReg(gmacdev -> DmaBase,DmaBusMode); - TR("DATA after Reset = %08x\n",data); - - return 0; + data = synopGMACReadReg(gmacdev -> DmaBase, DmaBusMode); + TR("DATA after Reset = %08x\n", data); + + return 0; } /** - * Function to program DMA bus mode register. - * + * Function to program DMA bus mode register. + * * The Bus Mode register is programmed with the value given. The bits to be set are * bit wise or'ed and sent as the second argument to this function. * @param[in] pointer to synopGMACdevice. * @param[in] the data to be programmed. * \return 0 on success else return the error status. */ -s32 synopGMAC_dma_bus_mode_init(synopGMACdevice *gmacdev,u32 init_value) +s32 synopGMAC_dma_bus_mode_init(synopGMACdevice *gmacdev, u32 init_value) { - synopGMACWriteReg(gmacdev -> DmaBase,DmaBusMode,init_value); + synopGMACWriteReg(gmacdev -> DmaBase, DmaBusMode, init_value); return 0; } /** - * Function to program DMA Control register(Operation Mode Register 0x18). - * + * Function to program DMA Control register(Operation Mode Register 0x18). + * * The Dma Control register is programmed with the value given. The bits to be set are * bit wise or'ed and sent as the second argument to this function. * @param[in] pointer to synopGMACdevice. * @param[in] the data to be programmed. * \return 0 on success else return the error status. */ -s32 synopGMAC_dma_control_init(synopGMACdevice *gmacdev,u32 init_value) +s32 synopGMAC_dma_control_init(synopGMACdevice *gmacdev, u32 init_value) { - synopGMACWriteReg(gmacdev -> DmaBase,DmaControl,init_value); + synopGMACWriteReg(gmacdev -> DmaBase, DmaControl, init_value); return 0; } @@ -240,7 +240,7 @@ s32 synopGMAC_dma_control_init(synopGMACdevice *gmacdev,u32 init_value) /*Gmac configuration functions*/ /** - * Enable the watchdog timer on the receiver. + * Enable the watchdog timer on the receiver. * When enabled, Gmac enables Watchdog timer, and GMAC allows no more than * 2048 bytes of data (10,240 if Jumbo frame enabled). * @param[in] pointer to synopGMACdevice. @@ -248,11 +248,11 @@ s32 synopGMAC_dma_control_init(synopGMACdevice *gmacdev,u32 init_value) */ void synopGMAC_wd_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacConfig,GmacWatchdog); + synopGMACClearBits(gmacdev -> MacBase, GmacConfig, GmacWatchdog); return; } /** - * Disable the watchdog timer on the receiver. + * Disable the watchdog timer on the receiver. * When disabled, Gmac disabled watchdog timer, and can receive frames up to * 16,384 bytes. * @param[in] pointer to synopGMACdevice. @@ -261,24 +261,24 @@ void synopGMAC_wd_enable(synopGMACdevice *gmacdev) void synopGMAC_wd_disable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacWatchdog); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacWatchdog); return; } /** - * Enables the Jabber frame support. + * Enables the Jabber frame support. * When enabled, GMAC disabled the jabber timer, and can transfer 16,384 byte frames. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_jab_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacConfig,GmacJabber); + synopGMACClearBits(gmacdev -> MacBase, GmacConfig, GmacJabber); return; } /** - * Disables the Jabber frame support. - * When disabled, GMAC enables jabber timer. It cuts of transmitter if application + * Disables the Jabber frame support. + * When disabled, GMAC enables jabber timer. It cuts of transmitter if application * sends more than 2048 bytes of data (10240 if Jumbo frame enabled). * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -286,13 +286,13 @@ void synopGMAC_jab_enable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_jab_disable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacJabber); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacJabber); return; } #endif /** - * Enables Frame bursting (Only in Half Duplex Mode). + * Enables Frame bursting (Only in Half Duplex Mode). * When enabled, GMAC allows frame bursting in GMII Half Duplex mode. * Reserved in 10/100 and Full-Duplex configurations. * @param[in] pointer to synopGMACdevice. @@ -300,11 +300,11 @@ void synopGMAC_jab_disable(synopGMACdevice *gmacdev) */ void synopGMAC_frame_burst_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacFrameBurst); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacFrameBurst); return; } /** - * Disables Frame bursting. + * Disables Frame bursting. * When Disabled, frame bursting is not supported. * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -312,13 +312,13 @@ void synopGMAC_frame_burst_enable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_frame_burst_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacConfig,GmacFrameBurst); + synopGMACClearBits(gmacdev -> MacBase, GmacConfig, GmacFrameBurst); return; } #endif /** - * Enable Jumbo frame support. + * Enable Jumbo frame support. * When Enabled GMAC supports jumbo frames of 9018/9022(VLAN tagged). * Giant frame error is not reported in receive frame status. * @param[in] pointer to synopGMACdevice. @@ -327,12 +327,12 @@ void synopGMAC_frame_burst_disable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_jumbo_frame_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacJumboFrame); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacJumboFrame); return; } #endif /** - * Disable Jumbo frame support. + * Disable Jumbo frame support. * When Disabled GMAC does not supports jumbo frames. * Giant frame error is reported in receive frame status. * @param[in] pointer to synopGMACdevice. @@ -340,12 +340,12 @@ void synopGMAC_jumbo_frame_enable(synopGMACdevice *gmacdev) */ void synopGMAC_jumbo_frame_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacConfig,GmacJumboFrame); + synopGMACClearBits(gmacdev -> MacBase, GmacConfig, GmacJumboFrame); return; } /** - * Disable Carrier sense. + * Disable Carrier sense. * When Disabled GMAC ignores CRS signal during frame transmission * in half duplex mode. * @param[in] pointer to synopGMACdevice. @@ -355,7 +355,7 @@ void synopGMAC_jumbo_frame_disable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_disable_crs(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacDisableCrs); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacDisableCrs); return; } #endif @@ -363,41 +363,41 @@ void synopGMAC_disable_crs(synopGMACdevice *gmacdev) /** - * Selects the GMII port. + * Selects the GMII port. * When called GMII (1000Mbps) port is selected (programmable only in 10/100/1000 Mbps configuration). * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_select_gmii(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacConfig,GmacMiiGmii); + synopGMACClearBits(gmacdev -> MacBase, GmacConfig, GmacMiiGmii); return; } /** - * Selects the MII port. + * Selects the MII port. * When called MII (10/100Mbps) port is selected (programmable only in 10/100/1000 Mbps configuration). * @param[in] pointer to synopGMACdevice. * \return returns void. */ -void synopGMAC_select_mii(synopGMACdevice * gmacdev) +void synopGMAC_select_mii(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacMiiGmii); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacMiiGmii); return; } /** - * Enables Receive Own bit (Only in Half Duplex Mode). + * Enables Receive Own bit (Only in Half Duplex Mode). * When enaled GMAC receives all the packets given by phy while transmitting. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_rx_own_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacConfig,GmacRxOwn); + synopGMACClearBits(gmacdev -> MacBase, GmacConfig, GmacRxOwn); return; } /** - * Disables Receive Own bit (Only in Half Duplex Mode). + * Disables Receive Own bit (Only in Half Duplex Mode). * When enaled GMAC disables the reception of frames when gmii_txen_o is asserted. * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -405,13 +405,13 @@ void synopGMAC_rx_own_enable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_rx_own_disable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacRxOwn); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacRxOwn); return; } #endif /** - * Sets the GMAC in loopback mode. + * Sets the GMAC in loopback mode. * When on GMAC operates in loop-back mode at GMII/MII. * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -420,65 +420,65 @@ void synopGMAC_rx_own_disable(synopGMACdevice *gmacdev) */ void synopGMAC_loopback_on(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacLoopback); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacLoopback); return; } /** - * Sets the GMAC in Normal mode. + * Sets the GMAC in Normal mode. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_loopback_off(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacConfig,GmacLoopback); + synopGMACClearBits(gmacdev -> MacBase, GmacConfig, GmacLoopback); return; } /** - * Sets the GMAC core in Full-Duplex mode. + * Sets the GMAC core in Full-Duplex mode. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_set_full_duplex(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacDuplex); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacDuplex); return; } /** - * Sets the GMAC core in Half-Duplex mode. + * Sets the GMAC core in Half-Duplex mode. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_set_half_duplex(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacConfig,GmacDuplex); + synopGMACClearBits(gmacdev -> MacBase, GmacConfig, GmacDuplex); return; } /** * GMAC tries retransmission (Only in Half Duplex mode). - * If collision occurs on the GMII/MII, GMAC attempt retries based on the - * back off limit configured. + * If collision occurs on the GMII/MII, GMAC attempt retries based on the + * back off limit configured. * @param[in] pointer to synopGMACdevice. * \return returns void. * \note This function is tightly coupled with synopGMAC_back_off_limit(synopGMACdev *, u32). */ void synopGMAC_retry_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacConfig,GmacRetry); + synopGMACClearBits(gmacdev -> MacBase, GmacConfig, GmacRetry); return; } /** * GMAC tries only one transmission (Only in Half Duplex mode). * If collision occurs on the GMII/MII, GMAC will ignore the current frami - * transmission and report a frame abort with excessive collision in tranmit frame status. + * transmission and report a frame abort with excessive collision in tranmit frame status. * @param[in] pointer to synopGMACdevice. * \return returns void. */ #if UNUSED void synopGMAC_retry_disable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacRetry); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacRetry); return; } #endif @@ -487,27 +487,27 @@ void synopGMAC_retry_disable(synopGMACdevice *gmacdev) * GMAC strips the Pad/FCS field of incoming frames. * This is true only if the length field value is less than or equal to * 1500 bytes. All received frames with length field greater than or equal to - * 1501 bytes are passed to the application without stripping the Pad/FCS field. + * 1501 bytes are passed to the application without stripping the Pad/FCS field. * @param[in] pointer to synopGMACdevice. * \return returns void. */ #if UNUSED void synopGMAC_pad_crc_strip_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacPadCrcStrip); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacPadCrcStrip); return; } #endif /** * GMAC doesnot strips the Pad/FCS field of incoming frames. - * GMAC will pass all the incoming frames to Host unmodified. + * GMAC will pass all the incoming frames to Host unmodified. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_pad_crc_strip_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacConfig,GmacPadCrcStrip); - u32 status = synopGMACReadReg(gmacdev -> MacBase,GmacConfig); + synopGMACClearBits(gmacdev -> MacBase, GmacConfig, GmacPadCrcStrip); + u32 status = synopGMACReadReg(gmacdev -> MacBase, GmacConfig); DEBUG_MES("strips status : %u\n", status & GmacPadCrcStrip); return; } @@ -517,31 +517,31 @@ void synopGMAC_pad_crc_strip_disable(synopGMACdevice *gmacdev) * \return returns void. * \note This function is tightly coupled with synopGMAC_retry_enable(synopGMACdevice * gmacdev) */ -void synopGMAC_back_off_limit(synopGMACdevice *gmacdev,u32 value) +void synopGMAC_back_off_limit(synopGMACdevice *gmacdev, u32 value) { u32 data; - data = synopGMACReadReg(gmacdev -> MacBase,GmacConfig); + data = synopGMACReadReg(gmacdev -> MacBase, GmacConfig); data &= (~GmacBackoffLimit); data |= value; - synopGMACWriteReg(gmacdev -> MacBase,GmacConfig,data); + synopGMACWriteReg(gmacdev -> MacBase, GmacConfig, data); return; } /** * Enables the Deferral check in GMAC (Only in Half Duplex mode) - * GMAC issues a Frame Abort Status, along with the excessive deferral error bit set in the + * GMAC issues a Frame Abort Status, along with the excessive deferral error bit set in the * transmit frame status when transmit state machine is deferred for more than * - 24,288 bit times in 10/100Mbps mode - * - 155,680 bit times in 1000Mbps mode or Jumbo frame mode in 10/100Mbps operation. + * - 155,680 bit times in 1000Mbps mode or Jumbo frame mode in 10/100Mbps operation. * @param[in] pointer to synopGMACdevice. * \return returns void. * \note Deferral begins when transmitter is ready to transmit, but is prevented because of - * an active CRS (carrier sense) + * an active CRS (carrier sense) */ #if UNUSED void synopGMAC_deferral_check_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacDeferralCheck); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacDeferralCheck); return; } #endif @@ -553,7 +553,7 @@ void synopGMAC_deferral_check_enable(synopGMACdevice *gmacdev) */ void synopGMAC_deferral_check_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacConfig,GmacDeferralCheck); + synopGMACClearBits(gmacdev -> MacBase, GmacConfig, GmacDeferralCheck); return; } /** @@ -563,7 +563,7 @@ void synopGMAC_deferral_check_disable(synopGMACdevice *gmacdev) */ void synopGMAC_rx_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacRx); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacRx); return; } /** @@ -575,7 +575,7 @@ void synopGMAC_rx_enable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_rx_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacConfig,GmacRx); + synopGMACClearBits(gmacdev -> MacBase, GmacConfig, GmacRx); return; } #endif @@ -586,7 +586,7 @@ void synopGMAC_rx_disable(synopGMACdevice *gmacdev) */ void synopGMAC_tx_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacTx); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacTx); return; } /** @@ -598,7 +598,7 @@ void synopGMAC_tx_enable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_tx_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacConfig,GmacTx); + synopGMACClearBits(gmacdev -> MacBase, GmacConfig, GmacTx); return; } #endif @@ -608,27 +608,27 @@ void synopGMAC_tx_disable(synopGMACdevice *gmacdev) /** * Disables reception of all the frames to application. - * GMAC passes only those received frames to application which + * GMAC passes only those received frames to application which * pass SA/DA address filtering. * @param[in] pointer to synopGMACdevice. - * \return void. + * \return void. */ void synopGMAC_frame_filter_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacFrameFilter,GmacFilter); + synopGMACClearBits(gmacdev -> MacBase, GmacFrameFilter, GmacFilter); return; } - /** - * Enables reception of all the frames to application. - * GMAC passes all the frames received to application irrespective of whether they - * pass SA/DA address filtering or not. - * @param[in] pointer to synopGMACdevice. - * \return returns void. - */ +/** + * Enables reception of all the frames to application. + * GMAC passes all the frames received to application irrespective of whether they + * pass SA/DA address filtering or not. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ void synopGMAC_frame_filter_disable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacFrameFilter,GmacFilter); + synopGMACSetBits(gmacdev -> MacBase, GmacFrameFilter, GmacFilter); return; } @@ -637,12 +637,12 @@ void synopGMAC_frame_filter_disable(synopGMACdevice *gmacdev) * This function is called when the Hash filtering is to be enabled. * @param[in] pointer to synopGMACdevice. * @param[in] data to be written to hash table high register. - * \return void. + * \return void. */ #if UNUSED -void synopGMAC_write_hash_table_high(synopGMACdevice *gmacdev,u32 data) +void synopGMAC_write_hash_table_high(synopGMACdevice *gmacdev, u32 data) { - synopGMACWriteReg(gmacdev -> MacBase,GmacHashHigh,data); + synopGMACWriteReg(gmacdev -> MacBase, GmacHashHigh, data); return; } #endif @@ -652,70 +652,70 @@ void synopGMAC_write_hash_table_high(synopGMACdevice *gmacdev,u32 data) * This function is called when the Hash filtering is to be enabled. * @param[in] pointer to synopGMACdevice. * @param[in] data to be written to hash table low register. - * \return void. + * \return void. */ #if UNUSED -void synopGMAC_write_hash_table_low(synopGMACdevice *gmacdev,u32 data) +void synopGMAC_write_hash_table_low(synopGMACdevice *gmacdev, u32 data) { - synopGMACWriteReg(gmacdev -> MacBase,GmacHashLow,data); + synopGMACWriteReg(gmacdev -> MacBase, GmacHashLow, data); return; } #endif /** * Enables Hash or Perfect filter (only if Hash filter is enabled in H/W). - * Only frames matching either perfect filtering or Hash Filtering as per HMC and HUC + * Only frames matching either perfect filtering or Hash Filtering as per HMC and HUC * configuration are sent to application. * @param[in] pointer to synopGMACdevice. - * \return void. + * \return void. */ #if UNUSED void synopGMAC_hash_perfect_filter_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacFrameFilter,GmacHashPerfectFilter); + synopGMACSetBits(gmacdev -> MacBase, GmacFrameFilter, GmacHashPerfectFilter); return; } #endif /** * Enables only Hash(only if Hash filter is enabled in H/W). - * Only frames matching Hash Filtering as per HMC and HUC + * Only frames matching Hash Filtering as per HMC and HUC * configuration are sent to application. * @param[in] pointer to synopGMACdevice. - * \return void. + * \return void. */ #if UNUSED void synopGMAC_Hash_filter_only_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacFrameFilter,GmacHashPerfectFilter); + synopGMACClearBits(gmacdev -> MacBase, GmacFrameFilter, GmacHashPerfectFilter); return; } #endif /** * Enables Source address filtering. - * When enabled source address filtering is performed. Only frames matching SA filtering are passed to application with - * SAMatch bit of RxStatus is set. GMAC drops failed frames. + * When enabled source address filtering is performed. Only frames matching SA filtering are passed to application with + * SAMatch bit of RxStatus is set. GMAC drops failed frames. * @param[in] pointer to synopGMACdevice. * \return void. - * \note This function is overriden by synopGMAC_frame_filter_disable(synopGMACdevice *) + * \note This function is overriden by synopGMAC_frame_filter_disable(synopGMACdevice *) */ #if UNUSED void synopGMAC_src_addr_filter_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacFrameFilter,GmacSrcAddrFilter); + synopGMACSetBits(gmacdev -> MacBase, GmacFrameFilter, GmacSrcAddrFilter); return; } #endif /** * Disables Source address filtering. - * When disabled GMAC forwards the received frames with updated SAMatch bit in RxStatus. + * When disabled GMAC forwards the received frames with updated SAMatch bit in RxStatus. * @param[in] pointer to synopGMACdevice. * \return void. */ void synopGMAC_src_addr_filter_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacFrameFilter,GmacSrcAddrFilter); + synopGMACClearBits(gmacdev -> MacBase, GmacFrameFilter, GmacSrcAddrFilter); return; } /** @@ -726,7 +726,7 @@ void synopGMAC_src_addr_filter_disable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_dst_addr_filter_inverse(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacFrameFilter,GmacDestAddrFilterInv); + synopGMACSetBits(gmacdev -> MacBase, GmacFrameFilter, GmacDestAddrFilterInv); return; } #endif @@ -737,7 +737,7 @@ void synopGMAC_dst_addr_filter_inverse(synopGMACdevice *gmacdev) */ void synopGMAC_dst_addr_filter_normal(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacFrameFilter,GmacDestAddrFilterInv); + synopGMACClearBits(gmacdev -> MacBase, GmacFrameFilter, GmacDestAddrFilterInv); return; } @@ -748,13 +748,13 @@ void synopGMAC_dst_addr_filter_normal(synopGMACdevice *gmacdev) * \return void. * \note Depends on RFE of FlowControlRegister[2] */ -void synopGMAC_set_pass_control(synopGMACdevice *gmacdev,u32 passcontrol) -{ +void synopGMAC_set_pass_control(synopGMACdevice *gmacdev, u32 passcontrol) +{ u32 data; - data = synopGMACReadReg(gmacdev -> MacBase,GmacFrameFilter); + data = synopGMACReadReg(gmacdev -> MacBase, GmacFrameFilter); data &= (~GmacPassControl); data |= passcontrol; - synopGMACWriteReg(gmacdev -> MacBase,GmacFrameFilter,data); + synopGMACWriteReg(gmacdev -> MacBase, GmacFrameFilter, data); return; } @@ -766,7 +766,7 @@ void synopGMAC_set_pass_control(synopGMACdevice *gmacdev,u32 passcontrol) */ void synopGMAC_broadcast_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacFrameFilter,GmacBroadcast); + synopGMACClearBits(gmacdev -> MacBase, GmacFrameFilter, GmacBroadcast); return; } /** @@ -776,7 +776,7 @@ void synopGMAC_broadcast_enable(synopGMACdevice *gmacdev) * \return void. */ #if UNUSED -void synopGMAC_broadcast_disable(synopGMACdevice * gmacdev) +void synopGMAC_broadcast_disable(synopGMACdevice *gmacdev) { synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacBroadcast); return; @@ -792,7 +792,7 @@ void synopGMAC_broadcast_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_multicast_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacFrameFilter,GmacMulticastFilter); + synopGMACSetBits(gmacdev -> MacBase, GmacFrameFilter, GmacMulticastFilter); return; } #endif @@ -804,7 +804,7 @@ void synopGMAC_multicast_enable(synopGMACdevice *gmacdev) */ void synopGMAC_multicast_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacFrameFilter,GmacMulticastFilter); + synopGMACClearBits(gmacdev -> MacBase, GmacFrameFilter, GmacMulticastFilter); return; } @@ -817,20 +817,20 @@ void synopGMAC_multicast_disable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_multicast_hash_filter_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacFrameFilter,GmacMcastHashFilter); + synopGMACSetBits(gmacdev -> MacBase, GmacFrameFilter, GmacMcastHashFilter); return; } #endif /** * Disables multicast hash filtering. - * When disabled GMAC performs perfect destination address filtering for multicast frames, it compares + * When disabled GMAC performs perfect destination address filtering for multicast frames, it compares * DA field with the value programmed in DA register. * @param[in] pointer to synopGMACdevice. * \return void. */ void synopGMAC_multicast_hash_filter_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacFrameFilter,GmacMcastHashFilter); + synopGMACClearBits(gmacdev -> MacBase, GmacFrameFilter, GmacMcastHashFilter); return; } @@ -844,7 +844,7 @@ void synopGMAC_multicast_hash_filter_disable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_promisc_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacFrameFilter,GmacPromiscuousMode); + synopGMACSetBits(gmacdev -> MacBase, GmacFrameFilter, GmacPromiscuousMode); return; } #endif @@ -856,7 +856,7 @@ void synopGMAC_promisc_enable(synopGMACdevice *gmacdev) */ void synopGMAC_promisc_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacFrameFilter,GmacPromiscuousMode); + synopGMACClearBits(gmacdev -> MacBase, GmacFrameFilter, GmacPromiscuousMode); return; } @@ -869,23 +869,23 @@ void synopGMAC_promisc_disable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_unicast_hash_filter_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacFrameFilter,GmacUcastHashFilter); + synopGMACSetBits(gmacdev -> MacBase, GmacFrameFilter, GmacUcastHashFilter); return; } #endif /** * Disables multicast hash filtering. - * When disabled GMAC performs perfect destination address filtering for unicast frames, it compares + * When disabled GMAC performs perfect destination address filtering for unicast frames, it compares * DA field with the value programmed in DA register. * @param[in] pointer to synopGMACdevice. * \return void. */ void synopGMAC_unicast_hash_filter_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacFrameFilter,GmacUcastHashFilter); + synopGMACClearBits(gmacdev -> MacBase, GmacFrameFilter, GmacUcastHashFilter); return; } - + /*Flow control configuration functions*/ /** @@ -898,7 +898,7 @@ void synopGMAC_unicast_hash_filter_disable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_unicast_pause_frame_detect_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacFlowControl,GmacUnicastPauseFrame); + synopGMACSetBits(gmacdev -> MacBase, GmacFlowControl, GmacUnicastPauseFrame); return; } #endif @@ -910,7 +910,7 @@ void synopGMAC_unicast_pause_frame_detect_enable(synopGMACdevice *gmacdev) */ void synopGMAC_unicast_pause_frame_detect_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacFlowControl,GmacUnicastPauseFrame); + synopGMACClearBits(gmacdev -> MacBase, GmacFlowControl, GmacUnicastPauseFrame); return; } /** @@ -921,7 +921,7 @@ void synopGMAC_unicast_pause_frame_detect_disable(synopGMACdevice *gmacdev) */ void synopGMAC_rx_flow_control_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacFlowControl,GmacRxFlowControl); + synopGMACSetBits(gmacdev -> MacBase, GmacFlowControl, GmacRxFlowControl); return; } /** @@ -932,12 +932,12 @@ void synopGMAC_rx_flow_control_enable(synopGMACdevice *gmacdev) */ void synopGMAC_rx_flow_control_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacFlowControl,GmacRxFlowControl); + synopGMACClearBits(gmacdev -> MacBase, GmacFlowControl, GmacRxFlowControl); return; } /** * Tx flow control enable. - * When Enabled + * When Enabled * - In full duplex GMAC enables flow control operation to transmit pause frames. * - In Half duplex GMAC enables the back pressure operation * @param[in] pointer to synopGMACdevice. @@ -945,13 +945,13 @@ void synopGMAC_rx_flow_control_disable(synopGMACdevice *gmacdev) */ void synopGMAC_tx_flow_control_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev -> MacBase,GmacFlowControl,GmacTxFlowControl); + synopGMACSetBits(gmacdev -> MacBase, GmacFlowControl, GmacTxFlowControl); return; } /** * Tx flow control disable. - * When Disabled + * When Disabled * - In full duplex GMAC will not transmit any pause frames. * - In Half duplex GMAC disables the back pressure feature. * @param[in] pointer to synopGMACdevice. @@ -959,7 +959,7 @@ void synopGMAC_tx_flow_control_enable(synopGMACdevice *gmacdev) */ void synopGMAC_tx_flow_control_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev -> MacBase,GmacFlowControl,GmacTxFlowControl); + synopGMACClearBits(gmacdev -> MacBase, GmacFlowControl, GmacTxFlowControl); return; } @@ -975,18 +975,18 @@ void synopGMAC_tx_flow_control_disable(synopGMACdevice *gmacdev) void synopGMAC_tx_activate_flow_control(synopGMACdevice *gmacdev) { //In case of full duplex check for this bit to b'0. if it is read as b'1 indicates that - //control frame transmission is in progress. - if(gmacdev -> Speed == FULLDUPLEX) + //control frame transmission is in progress. + if (gmacdev -> Speed == FULLDUPLEX) { - if(!synopGMACCheckBits(gmacdev -> MacBase,GmacFlowControl,GmacFlowControlBackPressure)) + if (!synopGMACCheckBits(gmacdev -> MacBase, GmacFlowControl, GmacFlowControlBackPressure)) { - synopGMACSetBits(gmacdev -> MacBase,GmacFlowControl,GmacFlowControlBackPressure); + synopGMACSetBits(gmacdev -> MacBase, GmacFlowControl, GmacFlowControlBackPressure); } } else//if half duplex mode - { - - synopGMACSetBits(gmacdev -> MacBase,GmacFlowControl,GmacFlowControlBackPressure); + { + + synopGMACSetBits(gmacdev -> MacBase, GmacFlowControl, GmacFlowControlBackPressure); } return; @@ -1002,9 +1002,9 @@ void synopGMAC_tx_activate_flow_control(synopGMACdevice *gmacdev) void synopGMAC_tx_deactivate_flow_control(synopGMACdevice *gmacdev) { //In full duplex this bit is automatically cleared after transmitting a pause control frame. - if(gmacdev->Speed == HALFDUPLEX) + if (gmacdev->Speed == HALFDUPLEX) { - synopGMACSetBits(gmacdev -> MacBase,GmacFlowControl,GmacFlowControlBackPressure); + synopGMACSetBits(gmacdev -> MacBase, GmacFlowControl, GmacFlowControlBackPressure); } return; @@ -1022,13 +1022,13 @@ void synopGMAC_pause_control(synopGMACdevice *gmacdev) { u32 omr_reg; u32 mac_flow_control_reg; - omr_reg = synopGMACReadReg(gmacdev -> DmaBase,DmaControl); + omr_reg = synopGMACReadReg(gmacdev -> DmaBase, DmaControl); omr_reg |= DmaRxFlowCtrlAct4K | DmaRxFlowCtrlDeact5K | DmaEnHwFlowCtrl; - synopGMACWriteReg(gmacdev -> DmaBase,DmaControl,omr_reg); + synopGMACWriteReg(gmacdev -> DmaBase, DmaControl, omr_reg); - mac_flow_control_reg = synopGMACReadReg(gmacdev -> MacBase,GmacFlowControl); + mac_flow_control_reg = synopGMACReadReg(gmacdev -> MacBase, GmacFlowControl); mac_flow_control_reg |= GmacRxFlowControl | GmacTxFlowControl | 0xFFFF0000; - synopGMACWriteReg(gmacdev -> MacBase,GmacFlowControl,mac_flow_control_reg); + synopGMACWriteReg(gmacdev -> MacBase, GmacFlowControl, mac_flow_control_reg); return; } @@ -1043,8 +1043,8 @@ void synopGMAC_pause_control(synopGMACdevice *gmacdev) s32 synopGMAC_mac_init(synopGMACdevice *gmacdev) { u32 PHYreg; - - if(gmacdev->DuplexMode == FULLDUPLEX) + + if (gmacdev->DuplexMode == FULLDUPLEX) { TR("\n===phy FULLDUPLEX MODE\n"); //sw: debug synopGMAC_wd_enable(gmacdev); @@ -1060,16 +1060,16 @@ s32 synopGMAC_mac_init(synopGMACdevice *gmacdev) synopGMAC_set_full_duplex(gmacdev); //1 synopGMAC_retry_enable(gmacdev); synopGMAC_pad_crc_strip_disable(gmacdev); - synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0); + synopGMAC_back_off_limit(gmacdev, GmacBackoffLimit0); synopGMAC_deferral_check_disable(gmacdev); - + synopGMAC_tx_enable(gmacdev); //according to Tang Dan's commitment synopGMAC_rx_enable(gmacdev); - synopGMACSetBits(gmacdev -> DmaBase,DmaControl,DmaStoreAndForward);//3 - synopGMACSetBits(gmacdev -> DmaBase,DmaControl,DmaFwdErrorFrames); + synopGMACSetBits(gmacdev -> DmaBase, DmaControl, DmaStoreAndForward); //3 + synopGMACSetBits(gmacdev -> DmaBase, DmaControl, DmaFwdErrorFrames); - if(gmacdev -> Speed == SPEED1000) + if (gmacdev -> Speed == SPEED1000) { synopGMAC_select_gmii(gmacdev); } @@ -1077,21 +1077,21 @@ s32 synopGMAC_mac_init(synopGMACdevice *gmacdev) { synopGMAC_select_mii(gmacdev); - if(gmacdev -> Speed == SPEED100) + if (gmacdev -> Speed == SPEED100) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacFESpeed100); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacFESpeed100); } else { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacFESpeed10); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacFESpeed10); } } - + /*Frame Filter Configuration*/ - //synopGMAC_frame_filter_enable(gmacdev); //2 - synopGMAC_frame_filter_disable(gmacdev); //2 - synopGMAC_set_pass_control(gmacdev,GmacPassControl0); + //synopGMAC_frame_filter_enable(gmacdev); //2 + synopGMAC_frame_filter_disable(gmacdev); //2 + synopGMAC_set_pass_control(gmacdev, GmacPassControl0); synopGMAC_broadcast_enable(gmacdev); synopGMAC_src_addr_filter_disable(gmacdev); synopGMAC_multicast_disable(gmacdev); @@ -1100,7 +1100,7 @@ s32 synopGMAC_mac_init(synopGMACdevice *gmacdev) synopGMAC_multicast_hash_filter_disable(gmacdev); synopGMAC_promisc_disable(gmacdev); synopGMAC_unicast_hash_filter_disable(gmacdev); - + /*Flow Control Configuration*/ synopGMAC_unicast_pause_frame_detect_disable(gmacdev); synopGMAC_rx_flow_control_enable(gmacdev); @@ -1108,9 +1108,9 @@ s32 synopGMAC_mac_init(synopGMACdevice *gmacdev) } else//for Half Duplex configuration { - + TR("\n===phy HALFDUPLEX MODE\n"); //sw: debug - synopGMAC_wd_enable(gmacdev ); + synopGMAC_wd_enable(gmacdev); synopGMAC_jab_enable(gmacdev); synopGMAC_frame_burst_enable(gmacdev); synopGMAC_jumbo_frame_disable(gmacdev); @@ -1123,40 +1123,41 @@ s32 synopGMAC_mac_init(synopGMACdevice *gmacdev) synopGMAC_set_half_duplex(gmacdev); synopGMAC_retry_enable(gmacdev); synopGMAC_pad_crc_strip_disable(gmacdev); - synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0); + synopGMAC_back_off_limit(gmacdev, GmacBackoffLimit0); synopGMAC_deferral_check_disable(gmacdev); //sw: set efe & tsf - synopGMACSetBits(gmacdev -> DmaBase,DmaControl,DmaStoreAndForward); - synopGMACSetBits(gmacdev -> DmaBase,DmaControl,DmaFwdErrorFrames); + synopGMACSetBits(gmacdev -> DmaBase, DmaControl, DmaStoreAndForward); + synopGMACSetBits(gmacdev -> DmaBase, DmaControl, DmaFwdErrorFrames); //sw: put it in the end - synopGMAC_tx_enable(gmacdev); + synopGMAC_tx_enable(gmacdev); synopGMAC_rx_enable(gmacdev); - if(gmacdev -> Speed == SPEED1000) + if (gmacdev -> Speed == SPEED1000) synopGMAC_select_gmii(gmacdev); - else{ + else + { synopGMAC_select_mii(gmacdev); - if(gmacdev -> Speed == SPEED100) + if (gmacdev -> Speed == SPEED100) { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacFESpeed100); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacFESpeed100); } else { - synopGMACSetBits(gmacdev -> MacBase,GmacConfig,GmacFESpeed10); + synopGMACSetBits(gmacdev -> MacBase, GmacConfig, GmacFESpeed10); } } - + // synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDisableCrs); // synopGMAC_select_gmii(gmacdev); /*Frame Filter Configuration*/ - synopGMAC_frame_filter_enable(gmacdev); + synopGMAC_frame_filter_enable(gmacdev); // synopGMAC_frame_filter_disable(gmacdev); - synopGMAC_set_pass_control(gmacdev,GmacPassControl0); + synopGMAC_set_pass_control(gmacdev, GmacPassControl0); synopGMAC_broadcast_enable(gmacdev); synopGMAC_src_addr_filter_disable(gmacdev); synopGMAC_multicast_disable(gmacdev); @@ -1166,11 +1167,11 @@ s32 synopGMAC_mac_init(synopGMACdevice *gmacdev) synopGMAC_promisc_disable(gmacdev); // synopGMAC_promisc_enable(gmacdev); synopGMAC_unicast_hash_filter_disable(gmacdev); - + //sw: loopback mode // synopGMAC_loopback_on(gmacdev); - - /*Flow Control Configuration*/ + + /*Flow Control Configuration*/ synopGMAC_unicast_pause_frame_detect_disable(gmacdev); synopGMAC_rx_flow_control_disable(gmacdev); synopGMAC_tx_flow_control_disable(gmacdev); @@ -1190,14 +1191,14 @@ s32 synopGMAC_mac_init(synopGMACdevice *gmacdev) * @param[in] buffer containing mac address to be programmed. * \return 0 upon success. Error code upon failure. */ -s32 synopGMAC_set_mac_addr(synopGMACdevice *gmacdev,u32 MacHigh,u32 MacLow,u8 *MacAddr) +s32 synopGMAC_set_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr) { u32 data; data = (MacAddr[5] << 8) | MacAddr[4]; - synopGMACWriteReg(gmacdev -> MacBase,MacHigh,data); + synopGMACWriteReg(gmacdev -> MacBase, MacHigh, data); data = (MacAddr[3] << 24) | (MacAddr[2] << 16) | (MacAddr[1] << 8) | MacAddr[0]; - synopGMACWriteReg(gmacdev -> MacBase,MacLow,data); + synopGMACWriteReg(gmacdev -> MacBase, MacLow, data); return 0; } @@ -1212,19 +1213,19 @@ s32 synopGMAC_set_mac_addr(synopGMACdevice *gmacdev,u32 MacHigh,u32 MacLow,u8 *M * @param[out] buffer containing the device mac address. * \return 0 upon success. Error code upon failure. */ -s32 synopGMAC_get_mac_addr(synopGMACdevice *gmacdev,u32 MacHigh,u32 MacLow,u8 *MacAddr) +s32 synopGMAC_get_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr) { u32 data; - - data = synopGMACReadReg(gmacdev -> MacBase,MacHigh); + + data = synopGMACReadReg(gmacdev -> MacBase, MacHigh); MacAddr[5] = (data >> 8) & 0xff; MacAddr[4] = (data) & 0xff; - data = synopGMACReadReg(gmacdev -> MacBase,MacLow); + data = synopGMACReadReg(gmacdev -> MacBase, MacLow); MacAddr[3] = (data >> 24) & 0xff; MacAddr[2] = (data >> 16) & 0xff; - MacAddr[1] = (data >> 8 ) & 0xff; - MacAddr[0] = (data ) & 0xff; + MacAddr[1] = (data >> 8) & 0xff; + MacAddr[0] = (data) & 0xff; // rt_kprintf("MacAddr = 0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\n",MacAddr[0],MacAddr[1],MacAddr[2],MacAddr[3],MacAddr[4],MacAddr[5]); @@ -1240,13 +1241,13 @@ s32 synopGMAC_get_mac_addr(synopGMACdevice *gmacdev,u32 MacHigh,u32 MacLow,u8 *M * @param[in] GMAC IP dma base address. * @param[in] GMAC IP phy base address. * \return 0 upon success. Error code upon failure. - * \note This is important function. No kernel api provided by Synopsys + * \note This is important function. No kernel api provided by Synopsys */ -s32 synopGMAC_attach(synopGMACdevice *gmacdev,u64 macBase,u64 dmaBase,u64 phyBase,u8 *mac_addr) +s32 synopGMAC_attach(synopGMACdevice *gmacdev, u64 macBase, u64 dmaBase, u64 phyBase, u8 *mac_addr) { /*Make sure the Device data strucure is cleared before we proceed further*/ - rt_memset((void *)gmacdev,0,sizeof(synopGMACdevice)); + rt_memset((void *)gmacdev, 0, sizeof(synopGMACdevice)); /*Populate the mac and dma base addresses*/ gmacdev -> MacBase = macBase; gmacdev -> DmaBase = dmaBase; @@ -1254,28 +1255,28 @@ s32 synopGMAC_attach(synopGMACdevice *gmacdev,u64 macBase,u64 dmaBase,u64 phyBas // rt_kprintf("gmacdev->DmaBase = 0x%x\n", gmacdev->DmaBase); // rt_kprintf("dmaBase = 0x%x\n", dmaBase); { - int i,j; + int i, j; u16 data; - for (i = phyBase,j = 0;j < 32;i = (i + 1) & 0x1f,j++) + for (i = phyBase, j = 0; j < 32; i = (i + 1) & 0x1f, j++) { - synopGMAC_read_phy_reg(gmacdev -> MacBase,i,2,&data); + synopGMAC_read_phy_reg(gmacdev -> MacBase, i, 2, &data); - if(data != 0 && data != 0xffff) + if (data != 0 && data != 0xffff) { break; } - synopGMAC_read_phy_reg(gmacdev -> MacBase,i,3,&data); + synopGMAC_read_phy_reg(gmacdev -> MacBase, i, 3, &data); - if(data != 0 && data != 0xffff) + if (data != 0 && data != 0xffff) { break; } } - if(j == 32) - { + if (j == 32) + { rt_kprintf("phy_detect: can't find PHY!\n"); } @@ -1285,9 +1286,9 @@ s32 synopGMAC_attach(synopGMACdevice *gmacdev,u64 macBase,u64 dmaBase,u64 phyBas // synopGMAC_get_mac_addr(gmacdev, GmacAddr0High, GmacAddr0Low, mac_addr); /* Program/flash in the station/IP's Mac address */ - synopGMAC_set_mac_addr(gmacdev,GmacAddr0High,GmacAddr0Low,mac_addr); + synopGMAC_set_mac_addr(gmacdev, GmacAddr0High, GmacAddr0Low, mac_addr); - return 0; + return 0; } @@ -1305,10 +1306,10 @@ s32 synopGMAC_attach(synopGMACdevice *gmacdev,u64 macBase,u64 dmaBase,u64 phyBas * \note Initialization of the buffer1, buffer2, data1,data2 and status are not done here. This only initializes whether one wants to use this descriptor * in chain mode or ring mode. For chain mode of operation the buffer2 and data2 are programmed before calling this function. */ -void synopGMAC_rx_desc_init_ring(DmaDesc *desc,bool last_ring_desc) +void synopGMAC_rx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) { desc -> length = last_ring_desc ? RxDescEndOfRing : 0; - desc -> status = 0; + desc -> status = 0; desc -> buffer1 = 0; desc -> buffer2 = 0; desc -> data1 = 0; @@ -1318,7 +1319,7 @@ void synopGMAC_rx_desc_init_ring(DmaDesc *desc,bool last_ring_desc) return; } -void synopGMAC_rx_desc_recycle(DmaDesc *desc,bool last_ring_desc) +void synopGMAC_rx_desc_recycle(DmaDesc *desc, bool last_ring_desc) { desc -> status = DescOwnByDma; desc -> length = last_ring_desc ? RxDescEndOfRing : 0; @@ -1345,14 +1346,14 @@ void synopGMAC_rx_desc_recycle(DmaDesc *desc,bool last_ring_desc) */ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) { - #ifdef ENH_DESC +#ifdef ENH_DESC desc -> status = last_ring_desc ? TxDescEndOfRing : 0; - desc -> length = 0; - #else + desc -> length = 0; +#else desc -> length = last_ring_desc ? TxDescEndOfRing : 0; desc -> status = 0; - #endif -//sw +#endif +//sw desc -> buffer1 = 0; desc -> buffer2 = 0; desc -> data1 = 0; @@ -1373,7 +1374,7 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) * \return void. */ -void synopGMAC_rx_desc_init_chain(DmaDesc * desc) +void synopGMAC_rx_desc_init_chain(DmaDesc *desc) { desc -> status = 0; desc -> length = RxDescChain; @@ -1391,14 +1392,14 @@ void synopGMAC_rx_desc_init_chain(DmaDesc * desc) * @param[in] whether end of ring * \return void. */ -void synopGMAC_tx_desc_init_chain(DmaDesc * desc) +void synopGMAC_tx_desc_init_chain(DmaDesc *desc) { - #ifdef ENH_DESC +#ifdef ENH_DESC desc -> status = TxDescChain; desc -> length = 0; - #else +#else desc -> length = TxDescChain; - #endif +#endif desc -> buffer1 = 0; desc -> data1 = 0; return; @@ -1408,57 +1409,57 @@ s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev) { s32 i; - for(i = 0;i < gmacdev -> TxDescCount;i++) + for (i = 0; i < gmacdev -> TxDescCount; i++) { synopGMAC_tx_desc_init_ring(gmacdev -> TxDesc + i, i == gmacdev -> TxDescCount - 1); } - TR("At line %d\n",__LINE__); + TR("At line %d\n", __LINE__); - for(i = 0; i < gmacdev -> RxDescCount; i++) + for (i = 0; i < gmacdev -> RxDescCount; i++) { synopGMAC_rx_desc_init_ring(gmacdev -> RxDesc + i, i == gmacdev -> RxDescCount - 1); } - + gmacdev -> TxNext = 0; gmacdev -> TxBusy = 0; gmacdev -> RxNext = 0; gmacdev -> RxBusy = 0; - + return -ESYNOPGMACNOERR; } /** * Programs the DmaRxBaseAddress with the Rx descriptor base address. - * Rx Descriptor's base address is available in the gmacdev structure. This function progrms the + * Rx Descriptor's base address is available in the gmacdev structure. This function progrms the * Dma Rx Base address with the starting address of the descriptor ring or chain. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_init_rx_desc_base(synopGMACdevice *gmacdev) { - DEBUG_MES("gmacdev->RxDescDma = %08x\n",gmacdev -> RxDescDma); - synopGMACWriteReg(gmacdev -> DmaBase,DmaRxBaseAddr,(u32)gmacdev -> RxDescDma); + DEBUG_MES("gmacdev->RxDescDma = %08x\n", gmacdev -> RxDescDma); + synopGMACWriteReg(gmacdev -> DmaBase, DmaRxBaseAddr, (u32)gmacdev -> RxDescDma); return; } /** * Programs the DmaTxBaseAddress with the Tx descriptor base address. - * Tx Descriptor's base address is available in the gmacdev structure. This function progrms the + * Tx Descriptor's base address is available in the gmacdev structure. This function progrms the * Dma Tx Base address with the starting address of the descriptor ring or chain. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_init_tx_desc_base(synopGMACdevice *gmacdev) { - synopGMACWriteReg(gmacdev -> DmaBase,DmaTxBaseAddr,(u32)gmacdev -> TxDescDma); + synopGMACWriteReg(gmacdev -> DmaBase, DmaTxBaseAddr, (u32)gmacdev -> TxDescDma); return; } -/** +/** * Makes the Dma as owner for this descriptor. * This function sets the own bit of status field of the DMA descriptor, - * indicating the DMA is the owner for this descriptor. + * indicating the DMA is the owner for this descriptor. * @param[in] pointer to DmaDesc structure. * \return returns void. */ @@ -1467,7 +1468,7 @@ void synopGMAC_set_owner_dma(DmaDesc *desc) desc -> status |= DescOwnByDma; } -/** +/** * set tx descriptor to indicate SOF. * This Descriptor contains the start of ethernet frame. * @param[in] pointer to DmaDesc structure. @@ -1475,14 +1476,14 @@ void synopGMAC_set_owner_dma(DmaDesc *desc) */ void synopGMAC_set_desc_sof(DmaDesc *desc) { - #ifdef ENH_DESC +#ifdef ENH_DESC desc -> status |= DescTxFirst;//ENH_DESC - #else +#else desc -> length |= DescTxFirst; - #endif +#endif } -/** +/** * set tx descriptor to indicate EOF. * This descriptor contains the End of ethernet frame. * @param[in] pointer to DmaDesc structure. @@ -1490,59 +1491,59 @@ void synopGMAC_set_desc_sof(DmaDesc *desc) */ void synopGMAC_set_desc_eof(DmaDesc *desc) { - #ifdef ENH_DESC +#ifdef ENH_DESC desc -> status |= DescTxLast;//ENH_DESC - #else +#else desc -> length |= DescTxLast; - #endif +#endif } -/** +/** * checks whether this descriptor contains start of frame. - * This function is to check whether the descriptor's data buffer + * This function is to check whether the descriptor's data buffer * contains a fresh ethernet frame? * @param[in] pointer to DmaDesc structure. * \return returns true if SOF in current descriptor, else returns fail. */ bool synopGMAC_is_sof_in_rx_desc(DmaDesc *desc) { - return ((desc -> status & DescRxFirst) == DescRxFirst); + return ((desc -> status & DescRxFirst) == DescRxFirst); } -/** +/** * checks whether this descriptor contains end of frame. - * This function is to check whether the descriptor's data buffer + * This function is to check whether the descriptor's data buffer * contains end of ethernet frame? * @param[in] pointer to DmaDesc structure. * \return returns true if SOF in current descriptor, else returns fail. */ bool synopGMAC_is_eof_in_rx_desc(DmaDesc *desc) { - return ((desc -> status & DescRxLast) == DescRxLast); + return ((desc -> status & DescRxLast) == DescRxLast); } -/** +/** * checks whether destination address filter failed in the rx frame. * @param[in] pointer to DmaDesc structure. * \return returns true if Failed, false if not. */ bool synopGMAC_is_da_filter_failed(DmaDesc *desc) { - return ((desc -> status & DescDAFilterFail) == DescDAFilterFail); + return ((desc -> status & DescDAFilterFail) == DescDAFilterFail); } -/** +/** * checks whether source address filter failed in the rx frame. * @param[in] pointer to DmaDesc structure. * \return returns true if Failed, false if not. */ bool synopGMAC_is_sa_filter_failed(DmaDesc *desc) { - return ((desc -> status & DescSAFilterFail) == DescSAFilterFail); + return ((desc -> status & DescSAFilterFail) == DescSAFilterFail); } -/** +/** * Checks whether the descriptor is owned by DMA. * If descriptor is owned by DMA then the OWN bit is set to 1. This API is same for both ring and chain mode. * @param[in] pointer to DmaDesc structure. @@ -1586,7 +1587,7 @@ bool synopGMAC_is_desc_valid(u32 status) bool synopGMAC_is_desc_empty(DmaDesc *desc) { //if both the buffer1 length and buffer2 length are zero desc is empty - return(((desc -> length & DescSize1Mask) == 0) && ((desc -> length & DescSize2Mask) == 0)); + return (((desc -> length & DescSize1Mask) == 0) && ((desc -> length & DescSize2Mask) == 0)); } @@ -1697,7 +1698,7 @@ bool synopGMAC_is_frame_dribbling_errors(u32 status) bool synopGMAC_is_rx_frame_length_errors(u32 status) { //u32 synopGMAC_dma_rx_length_errors(u32 status) - return((status & DescRxLengthError) == DescRxLengthError); + return ((status & DescRxLengthError) == DescRxLengthError); } /** @@ -1708,7 +1709,7 @@ bool synopGMAC_is_rx_frame_length_errors(u32 status) * \return returns true if it is last descriptor, false if not. * \note This function should not be called before initializing the descriptor using synopGMAC_desc_init(). */ -bool synopGMAC_is_last_rx_desc(synopGMACdevice *gmacdev,DmaDesc *desc) +bool synopGMAC_is_last_rx_desc(synopGMACdevice *gmacdev, DmaDesc *desc) { //bool synopGMAC_is_last_desc(DmaDesc *desc) return (((desc -> length & RxDescEndOfRing) == RxDescEndOfRing) || ((u64)gmacdev -> RxDesc == desc -> data2)); @@ -1722,7 +1723,7 @@ bool synopGMAC_is_last_rx_desc(synopGMACdevice *gmacdev,DmaDesc *desc) * \return returns true if it is last descriptor, false if not. * \note This function should not be called before initializing the descriptor using synopGMAC_desc_init(). */ -bool synopGMAC_is_last_tx_desc(synopGMACdevice *gmacdev,DmaDesc *desc) +bool synopGMAC_is_last_tx_desc(synopGMACdevice *gmacdev, DmaDesc *desc) { //bool synopGMAC_is_last_desc(DmaDesc *desc) #ifdef ENH_DESC @@ -1740,7 +1741,7 @@ bool synopGMAC_is_last_tx_desc(synopGMACdevice *gmacdev,DmaDesc *desc) */ bool synopGMAC_is_rx_desc_chained(DmaDesc *desc) { - return((desc -> length & RxDescChain) == RxDescChain); + return ((desc -> length & RxDescChain) == RxDescChain); } /** @@ -1752,9 +1753,9 @@ bool synopGMAC_is_rx_desc_chained(DmaDesc *desc) bool synopGMAC_is_tx_desc_chained(DmaDesc *desc) { #ifdef ENH_DESC - return((desc -> status & TxDescChain) == TxDescChain); + return ((desc -> status & TxDescChain) == TxDescChain); #else - return((desc -> length & TxDescChain) == TxDescChain); + return ((desc -> length & TxDescChain) == TxDescChain); #endif } @@ -1772,44 +1773,44 @@ bool synopGMAC_is_tx_desc_chained(DmaDesc *desc) * @param[out] virtual address of buffer2. * \return returns void. */ -void synopGMAC_get_desc_data(DmaDesc *desc,u32 *Status,u32 *Buffer1,u32 *Length1,u64 *Data1,u32 *Buffer2,u32 *Length2,u64 *Data2) +void synopGMAC_get_desc_data(DmaDesc *desc, u32 *Status, u32 *Buffer1, u32 *Length1, u64 *Data1, u32 *Buffer2, u32 *Length2, u64 *Data2) { - if(Status != 0) + if (Status != 0) { *Status = desc -> status; } - if(Buffer1 != 0) + if (Buffer1 != 0) { *Buffer1 = desc -> buffer1; } - if(Length1 != 0) + if (Length1 != 0) { *Length1 = (desc -> length & DescSize1Mask) >> DescSize1Shift; } - if(Data1 != 0) + if (Data1 != 0) { *Data1 = desc -> data1; } - if(Buffer2 != 0) + if (Buffer2 != 0) { *Buffer2 = desc -> buffer2; } - if(Length2 != 0) + if (Length2 != 0) { *Length2 = (desc -> length & DescSize2Mask) >> DescSize2Shift; } - if(Data2 != 0) + if (Data2 != 0) { *Data2 = desc -> data2; } - + return; } @@ -1818,7 +1819,7 @@ void synopGMAC_get_desc_data(DmaDesc *desc,u32 *Status,u32 *Buffer1,u32 *Length1 * This function is defined two times. Once when the code is compiled for ENHANCED DESCRIPTOR SUPPORT and Once for Normal descriptor * Get the index and address of Tx desc. * This api is same for both ring mode and chain mode. - * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is + * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is * over. This returns the descriptor fields to the caller. * @param[in] pointer to synopGMACdevice. * @param[out] status field of the descriptor. @@ -1831,127 +1832,129 @@ void synopGMAC_get_desc_data(DmaDesc *desc,u32 *Status,u32 *Buffer1,u32 *Length1 * @param[out] u32 data indicating whether the descriptor is in ring mode or chain mode. * \return returns present tx descriptor index on success. Negative value if error. */ -s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2, - u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_Low) +s32 synopGMAC_get_tx_qptr(synopGMACdevice *gmacdev, u32 *Status, u32 *Buffer1, u32 *Length1, u64 *Data1, u32 *Buffer2, u32 *Length2, u64 *Data2, + u32 *Ext_Status, u32 *Time_Stamp_High, u32 *Time_Stamp_Low) { u32 txover = gmacdev->TxBusy; - DmaDesc * txdesc = gmacdev->TxBusyDesc; - - if(synopGMAC_is_desc_owned_by_dma(txdesc)) + DmaDesc *txdesc = gmacdev->TxBusyDesc; + + if (synopGMAC_is_desc_owned_by_dma(txdesc)) return -1; - if(synopGMAC_is_desc_empty(txdesc)) + if (synopGMAC_is_desc_empty(txdesc)) return -1; (gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now - if(Status != 0) + if (Status != 0) *Status = txdesc->status; - if(Ext_Status != 0) + if (Ext_Status != 0) *Ext_Status = txdesc->extstatus; - if(Time_Stamp_High != 0) - *Time_Stamp_High = txdesc->timestamphigh; - if(Time_Stamp_Low != 0) - *Time_Stamp_High = txdesc->timestamplow; + if (Time_Stamp_High != 0) + *Time_Stamp_High = txdesc->timestamphigh; + if (Time_Stamp_Low != 0) + *Time_Stamp_High = txdesc->timestamplow; - if(Buffer1 != 0) + if (Buffer1 != 0) *Buffer1 = txdesc->buffer1; - if(Length1 != 0) + if (Length1 != 0) *Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift; - if(Data1 != 0) + if (Data1 != 0) *Data1 = txdesc->data1; - if(Buffer2 != 0) + if (Buffer2 != 0) *Buffer2 = txdesc->buffer2; - if(Length2 != 0) + if (Length2 != 0) *Length2 = (txdesc->length & DescSize2Mask) >> DescSize2Shift; - if(Data1 != 0) + if (Data1 != 0) *Data2 = txdesc->data2; - gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; + gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? 0 : txover + 1; - if(synopGMAC_is_tx_desc_chained(txdesc)){ - gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; - synopGMAC_tx_desc_init_chain(txdesc); - } - else{ - gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); - synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc)); - } - TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); - - return txover; -} -#else - -/** - * Get the index and address of Tx desc. - * This api is same for both ring mode and chain mode. - * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is - * over. This returns the descriptor fields to the caller. - * @param[in] pointer to synopGMACdevice. - * @param[out] status field of the descriptor. - * @param[out] Dma-able buffer1 pointer. - * @param[out] length of buffer1 (Max is 2048). - * @param[out] virtual pointer for buffer1. - * @param[out] Dma-able buffer2 pointer. - * @param[out] length of buffer2 (Max is 2048). - * @param[out] virtual pointer for buffer2. - * @param[out] u32 data indicating whether the descriptor is in ring mode or chain mode. - * \return returns present tx descriptor index on success. Negative value if error. - */ -s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2 ) -{ - u32 txover = gmacdev->TxBusy; - DmaDesc * txdesc = gmacdev->TxBusyDesc; - int i; -//sw: dbg - //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_R); - //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); -#if SYNOP_TX_DEBUG - printf("Cache sync before get a used tx dma desc!\n"); - printf("\n==%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); -#endif - if(synopGMAC_is_desc_owned_by_dma(txdesc)) - { - return -1; - } -// gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; -// gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); - if(synopGMAC_is_desc_empty(txdesc)) - { - return -1; - } - (gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now - - if(Status != 0) - *Status = txdesc->status; - - if(Buffer1 != 0) - *Buffer1 = txdesc->buffer1; - if(Length1 != 0) - *Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift; - if(Data1 != 0) - *Data1 = txdesc->data1; - - if(Buffer2 != 0) - *Buffer2 = txdesc->buffer2; - if(Length2 != 0) - *Length2 = (txdesc->length & DescSize2Mask) >> DescSize2Shift; - if(Data1 != 0) - *Data2 = txdesc->data2; - - gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; - - if(synopGMAC_is_tx_desc_chained(txdesc)) + if (synopGMAC_is_tx_desc_chained(txdesc)) { gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; synopGMAC_tx_desc_init_chain(txdesc); } else { - gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); - synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc)); + gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? gmacdev->TxDesc : (txdesc + 1); + synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev, txdesc)); + } + TR("%02d %08x %08x %08x %08x %08x %08x %08x\n", txover, (u32)txdesc, txdesc->status, txdesc->length, txdesc->buffer1, txdesc->buffer2, txdesc->data1, txdesc->data2); + + return txover; +} +#else + +/** + * Get the index and address of Tx desc. + * This api is same for both ring mode and chain mode. + * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is + * over. This returns the descriptor fields to the caller. + * @param[in] pointer to synopGMACdevice. + * @param[out] status field of the descriptor. + * @param[out] Dma-able buffer1 pointer. + * @param[out] length of buffer1 (Max is 2048). + * @param[out] virtual pointer for buffer1. + * @param[out] Dma-able buffer2 pointer. + * @param[out] length of buffer2 (Max is 2048). + * @param[out] virtual pointer for buffer2. + * @param[out] u32 data indicating whether the descriptor is in ring mode or chain mode. + * \return returns present tx descriptor index on success. Negative value if error. + */ +s32 synopGMAC_get_tx_qptr(synopGMACdevice *gmacdev, u32 *Status, u32 *Buffer1, u32 *Length1, u64 *Data1, u32 *Buffer2, u32 *Length2, u64 *Data2) +{ + u32 txover = gmacdev->TxBusy; + DmaDesc *txdesc = gmacdev->TxBusyDesc; + int i; +//sw: dbg + //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_R); + //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); +#if SYNOP_TX_DEBUG + printf("Cache sync before get a used tx dma desc!\n"); + printf("\n==%02d %08x %08x %08x %08x %08x %08x %08x\n", txover, (u32)txdesc, txdesc->status, txdesc->length, txdesc->buffer1, txdesc->buffer2, txdesc->data1, txdesc->data2); +#endif + if (synopGMAC_is_desc_owned_by_dma(txdesc)) + { + return -1; + } +// gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; +// gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); + if (synopGMAC_is_desc_empty(txdesc)) + { + return -1; + } + (gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now + + if (Status != 0) + *Status = txdesc->status; + + if (Buffer1 != 0) + *Buffer1 = txdesc->buffer1; + if (Length1 != 0) + *Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift; + if (Data1 != 0) + *Data1 = txdesc->data1; + + if (Buffer2 != 0) + *Buffer2 = txdesc->buffer2; + if (Length2 != 0) + *Length2 = (txdesc->length & DescSize2Mask) >> DescSize2Shift; + if (Data1 != 0) + *Data2 = txdesc->data2; + + gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? 0 : txover + 1; + + if (synopGMAC_is_tx_desc_chained(txdesc)) + { + gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; + synopGMAC_tx_desc_init_chain(txdesc); + } + else + { + gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? gmacdev->TxDesc : (txdesc + 1); + synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev, txdesc)); } //printf("%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); @@ -1959,16 +1962,16 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 printf("Cache sync after re-init a tx dma desc!\n"); #endif - return txover; + return txover; } #endif /** * Populate the tx desc structure with the buffer address. - * Once the driver has a packet ready to be transmitted, this function is called with the + * Once the driver has a packet ready to be transmitted, this function is called with the * valid dma-able buffer addresses and their lengths. This function populates the descriptor * and make the DMA the owner for the descriptor. This function also controls whether Checksum - * offloading to be done in hardware or not. + * offloading to be done in hardware or not. * This api is same for both ring mode and chain mode. * @param[in] pointer to synopGMACdevice. * @param[in] Dma-able buffer1 pointer. @@ -1982,62 +1985,62 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 * \return returns present tx descriptor index on success. Negative value if error. */ u32 len; -s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u64 Data1, u32 Buffer2, u32 Length2, u64 Data2,u32 offload_needed,u32 * index, DmaDesc * Dpr) +s32 synopGMAC_set_tx_qptr(synopGMACdevice *gmacdev, u32 Buffer1, u32 Length1, u64 Data1, u32 Buffer2, u32 Length2, u64 Data2, u32 offload_needed, u32 *index, DmaDesc *Dpr) { u32 txnext = gmacdev->TxNext; - DmaDesc * txdesc = gmacdev->TxNextDesc; + DmaDesc *txdesc = gmacdev->TxNextDesc; *index = txnext; Dpr = txdesc; - if(!synopGMAC_is_desc_empty(txdesc)) + if (!synopGMAC_is_desc_empty(txdesc)) { TR("set tx qptr: desc empty!\n"); return -1; } (gmacdev->BusyTxDesc)++; //busy tx descriptor is reduced by one as it will be handed over to Processor now - - if(synopGMAC_is_tx_desc_chained(txdesc)) + + if (synopGMAC_is_tx_desc_chained(txdesc)) { - txdesc->length |= ((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC - #else - txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor - #endif + txdesc->length |= ((Length1 << DescSize1Shift) & DescSize1Mask); +#ifdef ENH_DESC + txdesc->status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC +#else + txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor +#endif - txdesc->buffer1 = Buffer1; - txdesc->data1 = Data1; + txdesc->buffer1 = Buffer1; + txdesc->data1 = Data1; - if(offload_needed) - { - /* - Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, - before calling any of the functions given below. - */ - synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); - synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); + if (offload_needed) + { + /* + Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, + before calling any of the functions given below. + */ + synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); + synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); // synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); - } - #ifdef ENH_DESC - txdesc->status |= DescOwnByDma;//ENH_DESC - #else - txdesc->status = DescOwnByDma; - #endif + } +#ifdef ENH_DESC + txdesc->status |= DescOwnByDma;//ENH_DESC +#else + txdesc->status = DescOwnByDma; +#endif - gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; - gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2; + gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? 0 : txnext + 1; + gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2; } else { // printf("synopGMAC_set_tx_qptr:in ring mode\n"); - txdesc->length |= (((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC - #else - txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor - #endif + txdesc->length |= (((Length1 << DescSize1Shift) & DescSize1Mask) | ((Length2 << DescSize2Shift) & DescSize2Mask)); +#ifdef ENH_DESC + txdesc->status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC +#else + txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor +#endif txdesc->buffer1 = Buffer1; txdesc->data1 = Data1; @@ -2045,31 +2048,31 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u txdesc->buffer2 = Buffer2; txdesc->data2 = Data2; - if(offload_needed) + if (offload_needed) { - /* - Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, - before calling any of the functions given below. - */ + /* + Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, + before calling any of the functions given below. + */ //sw: i am not sure about the checksum.so i omit it in the outside - synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); - synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); + synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); + synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); // synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); } - #ifdef ENH_DESC +#ifdef ENH_DESC txdesc->status |= DescOwnByDma;//ENH_DESC - #else +#else // printf("synopGMAC_set_tx_qptr:give the tx descroptor to dma\n"); txdesc->status = DescOwnByDma; - #endif +#endif - gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; - gmacdev->TxNextDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); + gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? 0 : txnext + 1; + gmacdev->TxNextDesc = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? gmacdev->TxDesc : (txdesc + 1); } #if SYNOP_TX_DEBUG - printf("%02d %08x %08x %08x %08x %08x %08x %08x\n",txnext,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); + printf("%02d %08x %08x %08x %08x %08x %08x %08x\n", txnext, (u32)txdesc, txdesc->status, txdesc->length, txdesc->buffer1, txdesc->buffer2, txdesc->data1, txdesc->data2); #endif //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); #if SYNOP_TX_DEBUG @@ -2079,7 +2082,7 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u #if SYNOP_TX_DEBUG //printf("Cache sync for data in the buf of the tx desc!\n"); #endif - return txnext; + return txnext; } #ifdef ENH_DESC_8W /** @@ -2097,16 +2100,17 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u * \return returns present rx descriptor index on success. Negative value if error. */ // dma_addr RX_BUF_SIZE skb -s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u64 Data1, u32 Buffer2, u32 Length2, u64 Data2) +s32 synopGMAC_set_rx_qptr(synopGMACdevice *gmacdev, u32 Buffer1, u32 Length1, u64 Data1, u32 Buffer2, u32 Length2, u64 Data2) { u32 rxnext = gmacdev->RxNext; - DmaDesc * rxdesc = gmacdev->RxNextDesc; + DmaDesc *rxdesc = gmacdev->RxNextDesc; - if(!synopGMAC_is_desc_empty(rxdesc)) + if (!synopGMAC_is_desc_empty(rxdesc)) return -1; - if(synopGMAC_is_rx_desc_chained(rxdesc)){ - rxdesc->length |= ((Length1 <length |= ((Length1 << DescSize1Shift) & DescSize1Mask); rxdesc->buffer1 = Buffer1; rxdesc->data1 = Data1; @@ -2116,16 +2120,17 @@ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u rxdesc->timestamplow = 0; rxdesc->timestamphigh = 0; - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; - + if ((rxnext % MODULO_INTERRUPT) != 0) + rxdesc->length |= RxDisIntCompl; + rxdesc->status = DescOwnByDma; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; } - else{ - rxdesc->length |= (((Length1 <length |= (((Length1 << DescSize1Shift) & DescSize1Mask) | ((Length2 << DescSize2Shift) & DescSize2Mask)); rxdesc->buffer1 = Buffer1; rxdesc->data1 = Data1; @@ -2137,16 +2142,16 @@ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u rxdesc->buffer2 = Buffer2; rxdesc->data2 = Data2; - - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + + if ((rxnext % MODULO_INTERRUPT) != 0) + rxdesc->length |= RxDisIntCompl; rxdesc->status = DescOwnByDma; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); } #if SYNOP_RX_DEBUG - TR("%02d %08x %08x %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2,rxdesc->dummy1,rxdesc->dummy2); + TR("%02d %08x %08x %08x %08x %08x %08x %08x %08x %08x\n", rxnext, (u32)rxdesc, rxdesc->status, rxdesc->length, rxdesc->buffer1, rxdesc->buffer2, rxdesc->data1, rxdesc->data2, rxdesc->dummy1, rxdesc->dummy2); #endif (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one @@ -2169,100 +2174,104 @@ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u * @param[in] u32 data indicating whether the descriptor is in ring mode or chain mode. * \return returns present rx descriptor index on success. Negative value if error. */ -s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u64 Data1, u32 Buffer2, u32 Length2, u64 Data2) +s32 synopGMAC_set_rx_qptr(synopGMACdevice *gmacdev, u32 Buffer1, u32 Length1, u64 Data1, u32 Buffer2, u32 Length2, u64 Data2) { u32 rxnext = gmacdev->RxNext; - DmaDesc * rxdesc = gmacdev->RxNextDesc; + DmaDesc *rxdesc = gmacdev->RxNextDesc; - if(!synopGMAC_is_desc_empty(rxdesc)) + if (!synopGMAC_is_desc_empty(rxdesc)) return -1; - if(synopGMAC_is_rx_desc_chained(rxdesc)){ - rxdesc->length |= ((Length1 <length |= ((Length1 << DescSize1Shift) & DescSize1Mask); rxdesc->buffer1 = Buffer1; rxdesc->data1 = Data1; - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + if ((rxnext % MODULO_INTERRUPT) != 0) + rxdesc->length |= RxDisIntCompl; rxdesc->status = DescOwnByDma; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; } - else{ - rxdesc->length |= (((Length1 <length |= (((Length1 << DescSize1Shift) & DescSize1Mask) | ((Length2 << DescSize2Shift) & DescSize2Mask)); rxdesc->buffer1 = Buffer1; rxdesc->data1 = Data1; rxdesc->buffer2 = Buffer2; rxdesc->data2 = Data2; - - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + + if ((rxnext % MODULO_INTERRUPT) != 0) + rxdesc->length |= RxDisIntCompl; rxdesc->status = DescOwnByDma; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); } #if SYNOP_RX_DEBUG - TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + TR("%02d %08x %08x %08x %08x %08x %08x %08x\n", rxnext, (u32)rxdesc, rxdesc->status, rxdesc->length, rxdesc->buffer1, rxdesc->buffer2, rxdesc->data1, rxdesc->data2); #endif (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one return rxnext; } -s32 synopGMAC_set_rx_qptr_init(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u64 Data1, u32 Buffer2, u32 Length2, u64 Data2) +s32 synopGMAC_set_rx_qptr_init(synopGMACdevice *gmacdev, u32 Buffer1, u32 Length1, u64 Data1, u32 Buffer2, u32 Length2, u64 Data2) { u32 rxnext = gmacdev->RxNext; - DmaDesc * rxdesc = gmacdev->RxNextDesc; + DmaDesc *rxdesc = gmacdev->RxNextDesc; -/* sw - if(synopGMAC_is_desc_owned_by_dma(rxdesc)) - return -1; -*/ + /* sw + if(synopGMAC_is_desc_owned_by_dma(rxdesc)) + return -1; + */ - if(!synopGMAC_is_desc_empty(rxdesc)) + if (!synopGMAC_is_desc_empty(rxdesc)) return -1; - if(synopGMAC_is_rx_desc_chained(rxdesc)){ - rxdesc->length |= ((Length1 <length |= ((Length1 << DescSize1Shift) & DescSize1Mask); rxdesc->buffer1 = Buffer1; rxdesc->data1 = Data1; - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + if ((rxnext % MODULO_INTERRUPT) != 0) + rxdesc->length |= RxDisIntCompl; rxdesc->status = DescOwnByDma; rxdesc->status = 0; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; } - else{ - rxdesc->length |= (((Length1 <length |= (((Length1 << DescSize1Shift) & DescSize1Mask) | ((Length2 << DescSize2Shift) & DescSize2Mask)); rxdesc->buffer1 = Buffer1; rxdesc->data1 = Data1; rxdesc->buffer2 = Buffer2; rxdesc->data2 = Data2; - - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + + if ((rxnext % MODULO_INTERRUPT) != 0) + rxdesc->length |= RxDisIntCompl; rxdesc->status = DescOwnByDma; rxdesc->status = 0; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); } - TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + TR("%02d %08x %08x %08x %08x %08x %08x %08x\n", rxnext, (u32)rxdesc, rxdesc->status, rxdesc->length, rxdesc->buffer1, rxdesc->buffer2, rxdesc->data1, rxdesc->data2); (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one return rxnext; } @@ -2273,7 +2282,7 @@ s32 synopGMAC_set_rx_qptr_init(synopGMACdevice * gmacdev, u32 Buffer1, u32 Lengt * Get back the descriptor from DMA after data has been received. * When the DMA indicates that the data is received (interrupt is generated), this function should be * called to get the descriptor and hence the data buffers received. With successful return from this - * function caller gets the descriptor fields for processing. check the parameters to understand the + * function caller gets the descriptor fields for processing. check the parameters to understand the * fields returned.` * @param[in] pointer to synopGMACdevice. * @param[out] pointer to hold the status of DMA. @@ -2285,56 +2294,58 @@ s32 synopGMAC_set_rx_qptr_init(synopGMACdevice * gmacdev, u32 Buffer1, u32 Lengt * @param[out] virtual pointer for buffer2. * \return returns present rx descriptor index on success. Negative value if error. */ -s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2, - u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_Low) +s32 synopGMAC_get_rx_qptr(synopGMACdevice *gmacdev, u32 *Status, u32 *Buffer1, u32 *Length1, u64 *Data1, u32 *Buffer2, u32 *Length2, u64 *Data2, + u32 *Ext_Status, u32 *Time_Stamp_High, u32 *Time_Stamp_Low) { - u32 rxnext = gmacdev->RxBusy; // index of descriptor the DMA just completed. May be useful when data - //is spread over multiple buffers/descriptors - DmaDesc * rxdesc = gmacdev->RxBusyDesc; - if(synopGMAC_is_desc_owned_by_dma(rxdesc)) + u32 rxnext = gmacdev->RxBusy; // index of descriptor the DMA just completed. May be useful when data + //is spread over multiple buffers/descriptors + DmaDesc *rxdesc = gmacdev->RxBusyDesc; + if (synopGMAC_is_desc_owned_by_dma(rxdesc)) return -1; - if(synopGMAC_is_desc_empty(rxdesc)) + if (synopGMAC_is_desc_empty(rxdesc)) return -1; - - if(Status != 0) + + if (Status != 0) *Status = rxdesc->status;// send the status of this descriptor - if(Ext_Status != 0) + if (Ext_Status != 0) *Ext_Status = rxdesc->extstatus; - if(Time_Stamp_High != 0) - *Time_Stamp_High = rxdesc->timestamphigh; - if(Time_Stamp_Low != 0) - *Time_Stamp_Low = rxdesc->timestamplow; + if (Time_Stamp_High != 0) + *Time_Stamp_High = rxdesc->timestamphigh; + if (Time_Stamp_Low != 0) + *Time_Stamp_Low = rxdesc->timestamplow; - if(Length1 != 0) + if (Length1 != 0) *Length1 = (rxdesc->length & DescSize1Mask) >> DescSize1Shift; - if(Buffer1 != 0) + if (Buffer1 != 0) *Buffer1 = rxdesc->buffer1; - if(Data1 != 0) + if (Data1 != 0) *Data1 = rxdesc->data1; - if(Length2 != 0) + if (Length2 != 0) *Length2 = (rxdesc->length & DescSize2Mask) >> DescSize2Shift; - if(Buffer2 != 0) + if (Buffer2 != 0) *Buffer2 = rxdesc->buffer2; - if(Data1 != 0) + if (Data1 != 0) *Data2 = rxdesc->data2; - gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1; - if(synopGMAC_is_rx_desc_chained(rxdesc)){ - gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2; + if (synopGMAC_is_rx_desc_chained(rxdesc)) + { + gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2; synopGMAC_rx_desc_init_chain(rxdesc); //synopGMAC_desc_init_chain(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc),0,0); } - else{ - gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); - synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc)); + else + { + gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev, rxdesc)); } - TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + TR("%02d %08x %08x %08x %08x %08x %08x %08x\n", rxnext, (u32)rxdesc, rxdesc->status, rxdesc->length, rxdesc->buffer1, rxdesc->buffer2, rxdesc->data1, rxdesc->data2); (gmacdev->BusyRxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now - return(rxnext); + return (rxnext); } #else @@ -2343,7 +2354,7 @@ s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 * Get back the descriptor from DMA after data has been received. * When the DMA indicates that the data is received (interrupt is generated), this function should be * called to get the descriptor and hence the data buffers received. With successful return from this - * function caller gets the descriptor fields for processing. check the parameters to understand the + * function caller gets the descriptor fields for processing. check the parameters to understand the * fields returned.` * @param[in] pointer to synopGMACdevice. * @param[out] pointer to hold the status of DMA. @@ -2355,61 +2366,63 @@ s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 * @param[out] virtual pointer for buffer2. * \return returns present rx descriptor index on success. Negative value if error. */ -s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2) +s32 synopGMAC_get_rx_qptr(synopGMACdevice *gmacdev, u32 *Status, u32 *Buffer1, u32 *Length1, u64 *Data1, u32 *Buffer2, u32 *Length2, u64 *Data2) { - u32 rxnext = gmacdev->RxBusy; // index of descriptor the DMA just completed. May be useful when data - //is spread over multiple buffers/descriptors - DmaDesc * rxdesc = gmacdev->RxBusyDesc; + u32 rxnext = gmacdev->RxBusy; // index of descriptor the DMA just completed. May be useful when data + //is spread over multiple buffers/descriptors + DmaDesc *rxdesc = gmacdev->RxBusyDesc; u32 len; - if(synopGMAC_is_desc_owned_by_dma(rxdesc)) + if (synopGMAC_is_desc_owned_by_dma(rxdesc)) { DEBUG_MES("synopGMAC_get_rx_qptr:DMA descriptor is owned by GMAC!\n"); return -1; } - - if(synopGMAC_is_desc_empty(rxdesc)) + + if (synopGMAC_is_desc_empty(rxdesc)) { DEBUG_MES("synopGMAC_get_rx_qptr:rx desc is empty!\n"); return -1; } - if(Status != 0) + if (Status != 0) *Status = rxdesc->status;// send the status of this descriptor - if(Length1 != 0) + if (Length1 != 0) *Length1 = (rxdesc->length & DescSize1Mask) >> DescSize1Shift; - if(Buffer1 != 0) + if (Buffer1 != 0) *Buffer1 = rxdesc->buffer1; - if(Data1 != 0) + if (Data1 != 0) *Data1 = rxdesc->data1; - if(Length2 != 0) + if (Length2 != 0) *Length2 = (rxdesc->length & DescSize2Mask) >> DescSize2Shift; - if(Buffer2 != 0) + if (Buffer2 != 0) *Buffer2 = rxdesc->buffer2; - if(Data1 != 0) + if (Data1 != 0) *Data2 = rxdesc->data2; len = synopGMAC_get_rx_desc_frame_length(*Status); - DEBUG_MES("Cache sync for data buffer in rx dma desc: length = 0x%x\n",len); - gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - if(synopGMAC_is_rx_desc_chained(rxdesc)){ - gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2; + DEBUG_MES("Cache sync for data buffer in rx dma desc: length = 0x%x\n", len); + gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1; + if (synopGMAC_is_rx_desc_chained(rxdesc)) + { + gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2; synopGMAC_rx_desc_init_chain(rxdesc); } - else{ - gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); -//sw: raw data + else + { + gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); +//sw: raw data #if SYNOP_RX_DEBUG - DEBUG_MES("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + DEBUG_MES("%02d %08x %08x %08x %08x %08x %08x %08x\n", rxnext, (u32)rxdesc, rxdesc->status, rxdesc->length, rxdesc->buffer1, rxdesc->buffer2, rxdesc->data1, rxdesc->data2); #endif - synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc)); + synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev, rxdesc)); } #if SYNOP_RX_DEBUG - DEBUG_MES("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + DEBUG_MES("%02d %08x %08x %08x %08x %08x %08x %08x\n", rxnext, (u32)rxdesc, rxdesc->status, rxdesc->length, rxdesc->buffer1, rxdesc->buffer2, rxdesc->data1, rxdesc->data2); #endif (gmacdev->BusyRxDesc)--; //This returns one descriptor to processor. So busy count will be decremented by one - return(rxnext); + return (rxnext); } @@ -2425,11 +2438,11 @@ void synopGMAC_clear_interrupt(synopGMACdevice *gmacdev) { u32 data; data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); - TR("DMA status reg = 0x%x before cleared!\n",data); - synopGMACWriteReg(gmacdev->DmaBase, DmaStatus ,data); - // plat_delay(DEFAULT_LOOP_VARIABLE); + TR("DMA status reg = 0x%x before cleared!\n", data); + synopGMACWriteReg(gmacdev->DmaBase, DmaStatus, data); + // plat_delay(DEFAULT_LOOP_VARIABLE); // data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); - TR("DMA status reg = 0x%x after cleared!\n",data); + TR("DMA status reg = 0x%x after cleared!\n", data); } /** @@ -2442,17 +2455,17 @@ u32 synopGMAC_get_interrupt_type(synopGMACdevice *gmacdev) u32 data; u32 interrupts = 0; data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); - + //data = data & ~0x84; //sw: some bits shoud not be cleaned - synopGMACWriteReg(gmacdev->DmaBase, DmaStatus ,data); //manju: I think this is the appropriate location to clear the interrupts - plat_delay(DEFAULT_LOOP_VARIABLE); - if(data & DmaIntErrorMask) interrupts |= synopGMACDmaError; - if(data & DmaIntRxNormMask) interrupts |= synopGMACDmaRxNormal; - if(data & DmaIntRxAbnMask) interrupts |= synopGMACDmaRxAbnormal; - if(data & DmaIntRxStoppedMask) interrupts |= synopGMACDmaRxStopped; - if(data & DmaIntTxNormMask) interrupts |= synopGMACDmaTxNormal; - if(data & DmaIntTxAbnMask) interrupts |= synopGMACDmaTxAbnormal; - if(data & DmaIntTxStoppedMask) interrupts |= synopGMACDmaTxStopped; + synopGMACWriteReg(gmacdev->DmaBase, DmaStatus, data); //manju: I think this is the appropriate location to clear the interrupts + plat_delay(DEFAULT_LOOP_VARIABLE); + if (data & DmaIntErrorMask) interrupts |= synopGMACDmaError; + if (data & DmaIntRxNormMask) interrupts |= synopGMACDmaRxNormal; + if (data & DmaIntRxAbnMask) interrupts |= synopGMACDmaRxAbnormal; + if (data & DmaIntRxStoppedMask) interrupts |= synopGMACDmaRxStopped; + if (data & DmaIntTxNormMask) interrupts |= synopGMACDmaTxNormal; + if (data & DmaIntTxAbnMask) interrupts |= synopGMACDmaTxAbnormal; + if (data & DmaIntTxStoppedMask) interrupts |= synopGMACDmaTxStopped; return interrupts; } @@ -2465,7 +2478,7 @@ u32 synopGMAC_get_interrupt_type(synopGMACdevice *gmacdev) #if UNUSED u32 synopGMAC_get_interrupt_mask(synopGMACdevice *gmacdev) { - return(synopGMACReadReg(gmacdev->DmaBase, DmaInterrupt)); + return (synopGMACReadReg(gmacdev->DmaBase, DmaInterrupt)); } #endif @@ -2520,14 +2533,14 @@ void synopGMAC_disable_interrupt(synopGMACdevice *gmacdev, u32 interrupts) * @param[in] pointer to synopGMACdevice. * \return returns void. */ -void synopGMAC_enable_dma_rx(synopGMACdevice * gmacdev) +void synopGMAC_enable_dma_rx(synopGMACdevice *gmacdev) { // synopGMACSetBits(gmacdev->DmaBase, DmaControl, DmaRxStart); u32 data; data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); - data |= DmaRxStart; + data |= DmaRxStart; TR0(" ===33334\n"); - synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, data); TR0(" ===33344\n"); } @@ -2536,13 +2549,13 @@ void synopGMAC_enable_dma_rx(synopGMACdevice * gmacdev) * @param[in] pointer to synopGMACdevice. * \return returns void. */ -void synopGMAC_enable_dma_tx(synopGMACdevice * gmacdev) +void synopGMAC_enable_dma_tx(synopGMACdevice *gmacdev) { // synopGMACSetBits(gmacdev->DmaBase, DmaControl, DmaTxStart); u32 data; data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); - data |= DmaTxStart; - synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); + data |= DmaTxStart; + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, data); } @@ -2553,7 +2566,7 @@ void synopGMAC_enable_dma_tx(synopGMACdevice * gmacdev) * @param[in] pointer to synopGMACdevice. * \return returns void. */ -void synopGMAC_resume_dma_tx(synopGMACdevice * gmacdev) +void synopGMAC_resume_dma_tx(synopGMACdevice *gmacdev) { synopGMACWriteReg(gmacdev->DmaBase, DmaTxPollDemand, 1); @@ -2565,7 +2578,7 @@ void synopGMAC_resume_dma_tx(synopGMACdevice * gmacdev) * @param[in] pointer to synopGMACdevice. * \return returns void. */ -void synopGMAC_resume_dma_rx(synopGMACdevice * gmacdev) +void synopGMAC_resume_dma_rx(synopGMACdevice *gmacdev) { synopGMACWriteReg(gmacdev->DmaBase, DmaRxPollDemand, 0); @@ -2576,9 +2589,10 @@ void synopGMAC_resume_dma_rx(synopGMACdevice * gmacdev) * @param[in] pointer to synopGMACdevice. * \return returns void. */ -void synopGMAC_take_desc_ownership(DmaDesc * desc) +void synopGMAC_take_desc_ownership(DmaDesc *desc) { - if(desc){ + if (desc) + { desc->status &= ~DescOwnByDma; //Clear the DMA own bit // desc->status |= DescError; // Set the error to indicate this descriptor is bad } @@ -2593,18 +2607,21 @@ void synopGMAC_take_desc_ownership(DmaDesc * desc) * \return returns void. * \note Make sure to disable the transmission before calling this function, otherwise may result in racing situation. */ -void synopGMAC_take_desc_ownership_rx(synopGMACdevice * gmacdev) +void synopGMAC_take_desc_ownership_rx(synopGMACdevice *gmacdev) { s32 i; DmaDesc *desc; desc = gmacdev->RxDesc; - for(i = 0; i < gmacdev->RxDescCount; i++){ - if(synopGMAC_is_rx_desc_chained(desc)){ //This descriptor is in chain mode - + for (i = 0; i < gmacdev->RxDescCount; i++) + { + if (synopGMAC_is_rx_desc_chained(desc)) //This descriptor is in chain mode + { + synopGMAC_take_desc_ownership(desc); desc = (DmaDesc *)desc->data2; } - else{ + else + { synopGMAC_take_desc_ownership(desc + i); } } @@ -2619,20 +2636,23 @@ void synopGMAC_take_desc_ownership_rx(synopGMACdevice * gmacdev) * \return returns void. * \note Make sure to disable the transmission before calling this function, otherwise may result in racing situation. */ -void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev) +void synopGMAC_take_desc_ownership_tx(synopGMACdevice *gmacdev) { s32 i; DmaDesc *desc; desc = gmacdev->TxDesc; - for(i = 0; i < gmacdev->TxDescCount; i++){ - if(synopGMAC_is_tx_desc_chained(desc)){ //This descriptor is in chain mode + for (i = 0; i < gmacdev->TxDescCount; i++) + { + if (synopGMAC_is_tx_desc_chained(desc)) //This descriptor is in chain mode + { synopGMAC_take_desc_ownership(desc); desc = (DmaDesc *)desc->data2; } - else{ + else + { synopGMAC_take_desc_ownership(desc + i); } - } + } } /** @@ -2641,27 +2661,27 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev) * \return returns void. */ -void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev) -{ +void synopGMAC_disable_dma_tx(synopGMACdevice *gmacdev) +{ // synopGMACClearBits(gmacdev->DmaBase, DmaControl, DmaTxStart); u32 data; data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); - data &= (~DmaTxStart); - synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); + data &= (~DmaTxStart); + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, data); } /** * Disable the DMA for Reception. * @param[in] pointer to synopGMACdevice. * \return returns void. */ -void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev) -{ +void synopGMAC_disable_dma_rx(synopGMACdevice *gmacdev) +{ // synopGMACClearBits(gmacdev->DmaBase, DmaControl, DmaRxStart); u32 data; data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); - data &= (~DmaRxStart); - synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); -} + data &= (~DmaRxStart); + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, data); +} /*******************PMT APIs***************************************/ /** * Enables the assertion of PMT interrupt. @@ -2673,8 +2693,8 @@ void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_pmt_int_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); - return; + synopGMACClearBits(gmacdev->MacBase, GmacInterruptMask, GmacPmtIntMask); + return; } #endif /** @@ -2686,8 +2706,8 @@ void synopGMAC_pmt_int_enable(synopGMACdevice *gmacdev) */ void synopGMAC_pmt_int_disable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); - return; + synopGMACSetBits(gmacdev->MacBase, GmacInterruptMask, GmacPmtIntMask); + return; } /** * Enables the power down mode of GMAC. @@ -2698,7 +2718,7 @@ void synopGMAC_pmt_int_disable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_power_down_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtPowerDown); + synopGMACSetBits(gmacdev->MacBase, GmacPmtCtrlStatus, GmacPmtPowerDown); return; } #endif @@ -2712,7 +2732,7 @@ void synopGMAC_power_down_enable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_power_down_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtPowerDown); + synopGMACClearBits(gmacdev->MacBase, GmacPmtCtrlStatus, GmacPmtPowerDown); return; } #endif @@ -2724,7 +2744,7 @@ void synopGMAC_power_down_disable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_enable_pmt_interrupt(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + synopGMACClearBits(gmacdev->MacBase, GmacInterruptMask, GmacPmtIntMask); } #endif /** @@ -2735,7 +2755,7 @@ void synopGMAC_enable_pmt_interrupt(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_disable_pmt_interrupt(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + synopGMACSetBits(gmacdev->MacBase, GmacInterruptMask, GmacPmtIntMask); } #endif /** @@ -2746,13 +2766,13 @@ void synopGMAC_disable_pmt_interrupt(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_magic_packet_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtMagicPktEnable); + synopGMACSetBits(gmacdev->MacBase, GmacPmtCtrlStatus, GmacPmtMagicPktEnable); return; } #endif /** - * Enables GMAC to look for wake up frame. + * Enables GMAC to look for wake up frame. * Wake up frame is defined by the user. * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -2760,7 +2780,7 @@ void synopGMAC_magic_packet_enable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_wakeup_frame_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtWakeupFrameEnable); + synopGMACSetBits(gmacdev->MacBase, GmacPmtCtrlStatus, GmacPmtWakeupFrameEnable); return; } #endif @@ -2773,7 +2793,7 @@ void synopGMAC_wakeup_frame_enable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_pmt_unicast_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtGlobalUnicast); + synopGMACSetBits(gmacdev->MacBase, GmacPmtCtrlStatus, GmacPmtGlobalUnicast); return; } #endif @@ -2785,8 +2805,8 @@ void synopGMAC_pmt_unicast_enable(synopGMACdevice *gmacdev) bool synopGMAC_is_magic_packet_received(synopGMACdevice *gmacdev) { u32 data; - data = synopGMACReadReg(gmacdev->MacBase,GmacPmtCtrlStatus); - return((data & GmacPmtMagicPktReceived) == GmacPmtMagicPktReceived); + data = synopGMACReadReg(gmacdev->MacBase, GmacPmtCtrlStatus); + return ((data & GmacPmtMagicPktReceived) == GmacPmtMagicPktReceived); } /** * Checks whether the packet received is a wakeup frame?. @@ -2796,8 +2816,8 @@ bool synopGMAC_is_magic_packet_received(synopGMACdevice *gmacdev) bool synopGMAC_is_wakeup_frame_received(synopGMACdevice *gmacdev) { u32 data; - data = synopGMACReadReg(gmacdev->MacBase,GmacPmtCtrlStatus); - return((data & GmacPmtWakeupFrameReceived) == GmacPmtWakeupFrameReceived); + data = synopGMACReadReg(gmacdev->MacBase, GmacPmtCtrlStatus); + return ((data & GmacPmtWakeupFrameReceived) == GmacPmtWakeupFrameReceived); } /** @@ -2810,12 +2830,12 @@ bool synopGMAC_is_wakeup_frame_received(synopGMACdevice *gmacdev) * \return returns void. */ #if UNUSED -void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filter_contents) +void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 *filter_contents) { s32 i; - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtFrmFilterPtrReset); - plat_delay(10); - for(i =0; iMacBase, GmacPmtCtrlStatus, GmacPmtFrmFilterPtrReset); + plat_delay(10); + for (i = 0; i < WAKEUP_REG_LENGTH; i++) synopGMACWriteReg(gmacdev->MacBase, GmacWakeupAddr, *(filter_contents + i)); return; @@ -2834,7 +2854,7 @@ void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filte #if UNUSED void synopGMAC_mmc_counters_stop(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterFreeze); + synopGMACSetBits(gmacdev->MacBase, GmacMmcCntrl, GmacMmcCounterFreeze); return; } #endif @@ -2846,7 +2866,7 @@ void synopGMAC_mmc_counters_stop(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_mmc_counters_resume(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterFreeze); + synopGMACClearBits(gmacdev->MacBase, GmacMmcCntrl, GmacMmcCounterFreeze); return; } #endif @@ -2859,7 +2879,7 @@ void synopGMAC_mmc_counters_resume(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_mmc_counters_set_selfclear(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterResetOnRead); + synopGMACSetBits(gmacdev->MacBase, GmacMmcCntrl, GmacMmcCounterResetOnRead); return; } #endif @@ -2872,7 +2892,7 @@ void synopGMAC_mmc_counters_set_selfclear(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_mmc_counters_reset_selfclear(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterResetOnRead); + synopGMACClearBits(gmacdev->MacBase, GmacMmcCntrl, GmacMmcCounterResetOnRead); return; } #endif @@ -2885,7 +2905,7 @@ void synopGMAC_mmc_counters_reset_selfclear(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_mmc_counters_disable_rollover(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterStopRollover); + synopGMACSetBits(gmacdev->MacBase, GmacMmcCntrl, GmacMmcCounterStopRollover); return; } /** @@ -2896,7 +2916,7 @@ void synopGMAC_mmc_counters_disable_rollover(synopGMACdevice *gmacdev) */ void synopGMAC_mmc_counters_enable_rollover(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterStopRollover); + synopGMACClearBits(gmacdev->MacBase, GmacMmcCntrl, GmacMmcCounterStopRollover); return; } @@ -2908,7 +2928,7 @@ void synopGMAC_mmc_counters_enable_rollover(synopGMACdevice *gmacdev) */ u32 synopGMAC_read_mmc_counter(synopGMACdevice *gmacdev, u32 counter) { - return( synopGMACReadReg(gmacdev->MacBase,counter)); + return (synopGMACReadReg(gmacdev->MacBase, counter)); } #endif /** @@ -2918,7 +2938,7 @@ u32 synopGMAC_read_mmc_counter(synopGMACdevice *gmacdev, u32 counter) */ u32 synopGMAC_read_mmc_rx_int_status(synopGMACdevice *gmacdev) { - return( synopGMACReadReg(gmacdev->MacBase,GmacMmcIntrRx)); + return (synopGMACReadReg(gmacdev->MacBase, GmacMmcIntrRx)); } /** * Read the MMC Tx interrupt status. @@ -2927,7 +2947,7 @@ u32 synopGMAC_read_mmc_rx_int_status(synopGMACdevice *gmacdev) */ u32 synopGMAC_read_mmc_tx_int_status(synopGMACdevice *gmacdev) { - return( synopGMACReadReg(gmacdev->MacBase,GmacMmcIntrTx)); + return (synopGMACReadReg(gmacdev->MacBase, GmacMmcIntrTx)); } /** * Disable the MMC Tx interrupt. @@ -2938,7 +2958,7 @@ u32 synopGMAC_read_mmc_tx_int_status(synopGMACdevice *gmacdev) */ void synopGMAC_disable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcIntrMaskTx,mask); + synopGMACSetBits(gmacdev->MacBase, GmacMmcIntrMaskTx, mask); return; } /** @@ -2951,7 +2971,7 @@ void synopGMAC_disable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask) #if UNUSED void synopGMAC_enable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcIntrMaskTx,mask); + synopGMACClearBits(gmacdev->MacBase, GmacMmcIntrMaskTx, mask); } #endif /** @@ -2963,7 +2983,7 @@ void synopGMAC_enable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask) */ void synopGMAC_disable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcIntrMaskRx,mask); + synopGMACSetBits(gmacdev->MacBase, GmacMmcIntrMaskRx, mask); return; } /** @@ -2976,7 +2996,7 @@ void synopGMAC_disable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) #if UNUSED void synopGMAC_enable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcIntrMaskRx,mask); + synopGMACClearBits(gmacdev->MacBase, GmacMmcIntrMaskRx, mask); return; } #endif @@ -2989,7 +3009,7 @@ void synopGMAC_enable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) */ void synopGMAC_disable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcRxIpcIntrMask,mask); + synopGMACSetBits(gmacdev->MacBase, GmacMmcRxIpcIntrMask, mask); return; } /** @@ -3002,7 +3022,7 @@ void synopGMAC_disable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) #if UNUSED void synopGMAC_enable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcRxIpcIntrMask,mask); + synopGMACClearBits(gmacdev->MacBase, GmacMmcRxIpcIntrMask, mask); return; } #endif @@ -3020,7 +3040,7 @@ void synopGMAC_enable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) #if UNUSED void synopGMAC_enable_rx_chksum_offload(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacConfig,GmacRxIpcOffload); + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRxIpcOffload); return; } /** @@ -3031,18 +3051,18 @@ void synopGMAC_enable_rx_chksum_offload(synopGMACdevice *gmacdev) */ void synopGMAC_disable_rx_Ipchecksum_offload(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacConfig,GmacRxIpcOffload); + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRxIpcOffload); } /** * Instruct the DMA to drop the packets fails tcp ip checksum. - * This is to instruct the receive DMA engine to drop the recevied packet if they + * This is to instruct the receive DMA engine to drop the recevied packet if they * fails the tcp/ip checksum in hardware. Valid only when full checksum offloading is enabled(type-2). * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_rx_tcpip_chksum_drop_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->DmaBase,DmaControl,DmaDisableDropTcpCs); + synopGMACClearBits(gmacdev->DmaBase, DmaControl, DmaDisableDropTcpCs); return; } /** @@ -3054,12 +3074,12 @@ void synopGMAC_rx_tcpip_chksum_drop_enable(synopGMACdevice *gmacdev) */ void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->DmaBase,DmaControl,DmaDisableDropTcpCs); + synopGMACSetBits(gmacdev->DmaBase, DmaControl, DmaDisableDropTcpCs); return; } #endif -/** +/** * When the Enhanced Descriptor is enabled then the bit 0 of RDES0 indicates whether the * Extended Status is available (RDES4). Time Stamp feature and the Checksum Offload Engine2 * makes use of this extended status to provide the status of the received packet. @@ -3075,9 +3095,9 @@ void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev) * @param[in] u32 status field of the corresponding descriptor. * \return returns TRUE or FALSE. */ -bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status) // extended status present indicates that the RDES4 need to be probed +bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev, u32 status) // extended status present indicates that the RDES4 need to be probed { - return((status & DescRxEXTsts ) != 0 ); // if extstatus set then it returns 1 + return ((status & DescRxEXTsts) != 0); // if extstatus set then it returns 1 } /** * This function returns true if the IP header checksum bit is set in the extended status. @@ -3087,9 +3107,9 @@ bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status) * @param[in] u32 status field of the corresponding descriptor. * \return returns TRUE or FALSE. */ -bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status) // IP header (IPV4) checksum error +bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev, u32 ext_status) // IP header (IPV4) checksum error { - return((ext_status & DescRxIpHeaderError) != 0 ); // if IPV4 header error return 1 + return ((ext_status & DescRxIpHeaderError) != 0); // if IPV4 header error return 1 } /** * This function returns true if the Checksum is bypassed in the hardware. @@ -3099,9 +3119,9 @@ bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status) * @param[in] u32 status field of the corresponding descriptor. * \return returns TRUE or FALSE. */ -bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_status) // Hardware engine bypassed the checksum computation/checking +bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev, u32 ext_status) // Hardware engine bypassed the checksum computation/checking { - return((ext_status & DescRxChkSumBypass ) != 0 ); // if checksum offloading bypassed return 1 + return ((ext_status & DescRxChkSumBypass) != 0); // if checksum offloading bypassed return 1 } /** * This function returns true if payload checksum error is set in the extended status. @@ -3111,9 +3131,9 @@ bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_statu * @param[in] u32 status field of the corresponding descriptor. * \return returns TRUE or FALSE. */ -bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status) // IP payload checksum is in error (UDP/TCP/ICMP checksum error) +bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev, u32 ext_status) // IP payload checksum is in error (UDP/TCP/ICMP checksum error) { - return((ext_status & DescRxIpPayloadError) != 0 ); // if IP payload error return 1 + return ((ext_status & DescRxIpPayloadError) != 0); // if IP payload error return 1 } #endif @@ -3125,22 +3145,22 @@ bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status) */ u32 synopGMAC_is_rx_checksum_error(synopGMACdevice *gmacdev, u32 status) { - if (((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) - return RxLenLT600; - else if(((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) - return RxIpHdrPayLoadChkBypass; - else if(((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) - return RxChkBypass; - else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) - return RxNoChkError; - else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) - return RxPayLoadChkError; - else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) == 0)) - return RxIpHdrChkError; - else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) - return RxIpHdrPayLoadChkError; + if (((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) + return RxLenLT600; + else if (((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) + return RxIpHdrPayLoadChkBypass; + else if (((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) + return RxChkBypass; + else if (((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) + return RxNoChkError; + else if (((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) + return RxPayLoadChkError; + else if (((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) == 0)) + return RxIpHdrChkError; + else if (((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) + return RxIpHdrPayLoadChkError; else - return RxIpHdrPayLoadRes; + return RxIpHdrPayLoadRes; } /** * Checks if any Ipv4 header checksum error in the frame just transmitted. @@ -3152,7 +3172,7 @@ u32 synopGMAC_is_rx_checksum_error(synopGMACdevice *gmacdev, u32 status) */ bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 status) { - return((status & DescTxIpv4ChkError) == DescTxIpv4ChkError); + return ((status & DescTxIpv4ChkError) == DescTxIpv4ChkError); } /** @@ -3165,7 +3185,7 @@ bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 sta */ bool synopGMAC_is_tx_payload_checksum_error(synopGMACdevice *gmacdev, u32 status) { - return((status & DescTxPayChkError) == DescTxPayChkError); + return ((status & DescTxPayChkError) == DescTxPayChkError); } /** * The check summ offload engine is bypassed in the tx path. @@ -3176,11 +3196,11 @@ bool synopGMAC_is_tx_payload_checksum_error(synopGMACdevice *gmacdev, u32 status */ void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *desc) { - #ifdef ENH_DESC +#ifdef ENH_DESC desc->status = (desc->length & (~DescTxCisMask));//ENH_DESC - #else +#else desc->length = (desc->length & (~DescTxCisMask)); - #endif +#endif } /** * The check summ offload engine is enabled to do only IPV4 header checksum. @@ -3191,11 +3211,11 @@ void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *des */ void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *desc) { - #ifdef ENH_DESC +#ifdef ENH_DESC desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisIpv4HdrCs);//ENH_DESC - #else +#else desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisIpv4HdrCs); - #endif +#endif } /** @@ -3208,11 +3228,11 @@ void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *de */ void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *desc) { - #ifdef ENH_DESC +#ifdef ENH_DESC desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisTcpOnlyCs);//ENH_DESC - #else +#else desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpOnlyCs); - #endif +#endif } /** * The check summ offload engine is enabled to do complete checksum computation. @@ -3225,11 +3245,11 @@ void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *de */ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc *desc) { - #ifdef ENH_DESC +#ifdef ENH_DESC desc->status = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpPseudoCs); - #else +#else desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpPseudoCs); - #endif +#endif } /*******************Ip checksum offloading APIs***************************************/ @@ -3238,7 +3258,7 @@ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc * At this time the driver supports the IEEE time stamping feature when the Enhanced Descriptors are enabled. * For normal descriptor and the IEEE time stamp (version 1), driver support is not proviced * Please make sure you have enabled the Advanced timestamp feature in the hardware and the driver should - * be compiled with the ADV_TME_STAMP feature. + * be compiled with the ADV_TME_STAMP feature. * Some of the APIs provided here may not be valid for all configurations. Please make sure you call the * API with due care. */ @@ -3252,47 +3272,47 @@ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc #if UNUSED void synopGMAC_TS_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENA); + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSENA); return; } /** - * This function disables the timestamping. + * This function disables the timestamping. * When disabled timestamp is not added to tx and receive frames and timestamp generator is suspended. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask, GmacTSIntMask); + synopGMACClearBits(gmacdev->MacBase, GmacInterruptMask, GmacTSIntMask); return; } /** - * Enable the interrupt to get timestamping interrupt. - * This enables the host to get the interrupt when (1) system time is greater or equal to the + * Enable the interrupt to get timestamping interrupt. + * This enables the host to get the interrupt when (1) system time is greater or equal to the * target time high and low register or (2) there is a overflow in th esecond register. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_int_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); - return; + synopGMACClearBits(gmacdev->MacBase, GmacInterruptMask, GmacPmtIntMask); + return; } /** - * Disable the interrupt to get timestamping interrupt. + * Disable the interrupt to get timestamping interrupt. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); - return; + synopGMACSetBits(gmacdev->MacBase, GmacInterruptMask, GmacPmtIntMask); + return; } /** - * Enable MAC address for PTP frame filtering. + * Enable MAC address for PTP frame filtering. * When enabled, uses MAC address (apart from MAC address 0) to filter the PTP frames when * PTP is sent directly over Ethernet. * @param[in] pointer to synopGMACdevice @@ -3300,23 +3320,23 @@ void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_mac_addr_filt_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENMACADDR); + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSENMACADDR); return; } /** - * Disables MAC address for PTP frame filtering. + * Disables MAC address for PTP frame filtering. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSENMACADDR); + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSENMACADDR); return; } /** - * Selet the type of clock mode for PTP. + * Selet the type of clock mode for PTP. * Please note to use one of the follwoing as the clk_type argument. * GmacTSOrdClk = 0x00000000, 00=> Ordinary clock * GmacTSBouClk = 0x00010000, 01=> Boundary clock @@ -3329,16 +3349,16 @@ void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev) void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type) { u32 clkval; - clkval = synopGMACReadReg(gmacdev->MacBase,GmacTSControl); //set the mdc clock to the user defined value - clkval = clkval | clk_type; - synopGMACWriteReg(gmacdev->MacBase,GmacTSControl,clkval); + clkval = synopGMACReadReg(gmacdev->MacBase, GmacTSControl); //set the mdc clock to the user defined value + clkval = clkval | clk_type; + synopGMACWriteReg(gmacdev->MacBase, GmacTSControl, clkval); return; } /** - * Enable Snapshot for messages relevant to Master. - * When enabled, snapshot is taken for messages relevant to master mode only, else snapshot is taken for messages relevant - * to slave node. + * Enable Snapshot for messages relevant to Master. + * When enabled, snapshot is taken for messages relevant to master mode only, else snapshot is taken for messages relevant + * to slave node. * Valid only for Ordinary clock and Boundary clock * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3346,13 +3366,13 @@ void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type) */ void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSMSTRENA); + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSMSTRENA); return; } /** - * Disable Snapshot for messages relevant to Master. - * When disabled, snapshot is taken for messages relevant - * to slave node. + * Disable Snapshot for messages relevant to Master. + * When disabled, snapshot is taken for messages relevant + * to slave node. * Valid only for Ordinary clock and Boundary clock * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3360,11 +3380,11 @@ void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSMSTRENA); + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSMSTRENA); return; } /** - * Enable Snapshot for Event messages. + * Enable Snapshot for Event messages. * When enabled, snapshot is taken for event messages only (SYNC, Delay_Req, Pdelay_Req or Pdelay_Resp) * When disabled, snapshot is taken for all messages except Announce, Management and Signaling. * Reserved when "Advanced Time Stamp" is not selected @@ -3373,11 +3393,11 @@ void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSEVNTENA); + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSEVNTENA); return; } /** - * Disable Snapshot for Event messages. + * Disable Snapshot for Event messages. * When disabled, snapshot is taken for all messages except Announce, Management and Signaling. * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3385,12 +3405,12 @@ void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSEVNTENA); + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSEVNTENA); return; } /** - * Enable time stamp snapshot for IPV4 frames. + * Enable time stamp snapshot for IPV4 frames. * When enabled, time stamp snapshot is taken for IPV4 frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3398,11 +3418,11 @@ void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV4ENA); + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSIPV4ENA); return; } /** - * Disable time stamp snapshot for IPV4 frames. + * Disable time stamp snapshot for IPV4 frames. * When disabled, time stamp snapshot is not taken for IPV4 frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3410,11 +3430,11 @@ void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV4ENA); + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSIPV4ENA); return; } // Only for "Advanced Time Stamp" /** - * Enable time stamp snapshot for IPV6 frames. + * Enable time stamp snapshot for IPV6 frames. * When enabled, time stamp snapshot is taken for IPV6 frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3422,11 +3442,11 @@ void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_IPV6_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV6ENA); + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSIPV6ENA); return; } /** - * Disable time stamp snapshot for IPV6 frames. + * Disable time stamp snapshot for IPV6 frames. * When disabled, time stamp snapshot is not taken for IPV6 frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3434,12 +3454,12 @@ void synopGMAC_TS_IPV6_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_IPV6_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV6ENA); + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSIPV6ENA); return; } /** - * Enable time stamp snapshot for PTP over Ethernet frames. + * Enable time stamp snapshot for PTP over Ethernet frames. * When enabled, time stamp snapshot is taken for PTP over Ethernet frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3447,11 +3467,11 @@ void synopGMAC_TS_IPV6_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_ptp_over_ethernet_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPENA); + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSIPENA); return; } /** - * Disable time stamp snapshot for PTP over Ethernet frames. + * Disable time stamp snapshot for PTP over Ethernet frames. * When disabled, time stamp snapshot is not taken for PTP over Ethernet frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3459,57 +3479,57 @@ void synopGMAC_TS_ptp_over_ethernet_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPENA); + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSIPENA); return; } /** - * Snoop PTP packet for version 2 format + * Snoop PTP packet for version 2 format * When set the PTP packets are snooped using the version 2 format. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSVER2ENA); + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSVER2ENA); return; } /** - * Snoop PTP packet for version 2 format + * Snoop PTP packet for version 2 format * When set the PTP packets are snooped using the version 2 format. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSVER2ENA); + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSVER2ENA); return; } /** - * Timestamp digital rollover + * Timestamp digital rollover * When set the timestamp low register rolls over after 0x3B9A_C9FF value. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSCTRLSSR); + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSCTRLSSR); return; -} +} /** - * Timestamp binary rollover + * Timestamp binary rollover * When set the timestamp low register rolls over after 0x7FFF_FFFF value. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSCTRLSSR); + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSCTRLSSR); return; } /** - * Enable Time Stamp for All frames + * Enable Time Stamp for All frames * When set the timestamp snap shot is enabled for all frames received by the core. * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3517,11 +3537,11 @@ void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENALL); + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSENALL); return; } /** - * Disable Time Stamp for All frames + * Disable Time Stamp for All frames * When reset the timestamp snap shot is not enabled for all frames received by the core. * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3529,11 +3549,11 @@ void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSENALL); + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSENALL); return; } /** - * Addend Register Update + * Addend Register Update * This function loads the contents of Time stamp addend register with the supplied 32 value. * This is reserved function when only coarse correction option is selected * @param[in] pointer to synopGMACdevice @@ -3543,23 +3563,26 @@ void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev) s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value) { u32 loop_variable; - synopGMACWriteReg(gmacdev->MacBase,GmacTSAddend,addend_value);// Load the addend_value in to Addend register - for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time - if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSADDREG)){ // if it is cleared then break - break; - } + synopGMACWriteReg(gmacdev->MacBase, GmacTSAddend, addend_value); // Load the addend_value in to Addend register + for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) //Wait till the busy bit gets cleared with in a certain amount of time + { + if (!((synopGMACReadReg(gmacdev->MacBase, GmacTSControl)) & GmacTSADDREG)) // if it is cleared then break + { + break; + } plat_delay(DEFAULT_DELAY_VARIABLE); - } - if(loop_variable < DEFAULT_LOOP_VARIABLE) - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSADDREG); - else{ - TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; - } + } + if (loop_variable < DEFAULT_LOOP_VARIABLE) + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSADDREG); + else + { + TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; + } return -ESYNOPGMACNOERR; } /** - * time stamp Update + * time stamp Update * This function updates (adds/subtracts) with the value specified in the Timestamp High Update and * Timestamp Low Update register. * @param[in] pointer to synopGMACdevice @@ -3570,17 +3593,20 @@ s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value) s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value) { u32 loop_variable; - synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register - synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register - for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time - if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSUPDT)){ // if it is cleared then break + synopGMACWriteReg(gmacdev->MacBase, GmacTSHighUpdate, high_value); // Load the high value to Timestamp High register + synopGMACWriteReg(gmacdev->MacBase, GmacTSLowUpdate, low_value); // Load the high value to Timestamp High register + for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) //Wait till the busy bit gets cleared with in a certain amount of time + { + if (!((synopGMACReadReg(gmacdev->MacBase, GmacTSControl)) & GmacTSUPDT)) // if it is cleared then break + { break; - } + } plat_delay(DEFAULT_DELAY_VARIABLE); } - if(loop_variable < DEFAULT_LOOP_VARIABLE) - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSUPDT); - else{ + if (loop_variable < DEFAULT_LOOP_VARIABLE) + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSUPDT); + else + { TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); return -ESYNOPGMACPHYERR; } @@ -3588,7 +3614,7 @@ s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 } /** - * time stamp Initialize + * time stamp Initialize * This function Loads/Initializes h the value specified in the Timestamp High Update and * Timestamp Low Update register. * @param[in] pointer to synopGMACdevice @@ -3599,17 +3625,20 @@ s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value) { u32 loop_variable; - synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register - synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register - for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time - if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSINT)){ // if it is cleared then break + synopGMACWriteReg(gmacdev->MacBase, GmacTSHighUpdate, high_value); // Load the high value to Timestamp High register + synopGMACWriteReg(gmacdev->MacBase, GmacTSLowUpdate, low_value); // Load the high value to Timestamp High register + for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) //Wait till the busy bit gets cleared with in a certain amount of time + { + if (!((synopGMACReadReg(gmacdev->MacBase, GmacTSControl)) & GmacTSINT)) // if it is cleared then break + { break; - } + } plat_delay(DEFAULT_DELAY_VARIABLE); } - if(loop_variable < DEFAULT_LOOP_VARIABLE) - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSINT); - else{ + if (loop_variable < DEFAULT_LOOP_VARIABLE) + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSINT); + else + { TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); return -ESYNOPGMACPHYERR; } @@ -3617,40 +3646,40 @@ s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 lo } /** - * Time Stamp Update Coarse + * Time Stamp Update Coarse * When reset the timestamp update is done using coarse method. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSCFUPDT); + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSCFUPDT); return; } /** - * Time Stamp Update Fine + * Time Stamp Update Fine * When reset the timestamp update is done using Fine method. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSCFUPDT); + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSCFUPDT); return; } /** - * Load the Sub Second Increment value in to Sub Second increment register + * Load the Sub Second Increment value in to Sub Second increment register * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_value) { - synopGMACWriteReg(gmacdev->MacBase,GmacTSSubSecIncr,(sub_sec_inc_value & GmacSSINCMsk)); + synopGMACWriteReg(gmacdev->MacBase, GmacTSSubSecIncr, (sub_sec_inc_value & GmacSSINCMsk)); return; } /** - * Reads the time stamp contents in to the respective pointers + * Reads the time stamp contents in to the respective pointers * These registers are readonly. * This function returns the 48 bit time stamp assuming Version 2 timestamp with higher word is selected. * @param[in] pointer to synopGMACdevice @@ -3658,40 +3687,40 @@ void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_value * @param[in] pointer to hold 32 bit second register contents * @param[in] pointer to hold 32 bit subnanosecond register contents * \return returns void - * \note Please note that since the atomic access to the timestamp registers is not possible, - * the contents read may be different from the actual time stamp. + * \note Please note that since the atomic access to the timestamp registers is not possible, + * the contents read may be different from the actual time stamp. */ -void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, u32 * sec_val, u32 * sub_sec_val) +void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 *higher_sec_val, u32 *sec_val, u32 *sub_sec_val) { - * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask); - * sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSHigh); - * sub_sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSLow); + * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase, GmacTSHighWord) & GmacTSHighWordMask); + * sec_val = synopGMACReadReg(gmacdev->MacBase, GmacTSHigh); + * sub_sec_val = synopGMACReadReg(gmacdev->MacBase, GmacTSLow); return; } /** - * Loads the time stamp higher sec value from the value supplied + * Loads the time stamp higher sec value from the value supplied * @param[in] pointer to synopGMACdevice * @param[in] 16 higher bit second register contents passed as 32 bit value * \return returns void */ void synopGMAC_TS_load_timestamp_higher_val(synopGMACdevice *gmacdev, u32 higher_sec_val) { - synopGMACWriteReg(gmacdev->MacBase,GmacTSHighWord, (higher_sec_val & GmacTSHighWordMask)); + synopGMACWriteReg(gmacdev->MacBase, GmacTSHighWord, (higher_sec_val & GmacTSHighWordMask)); return; } /** - * Reads the time stamp higher sec value to respective pointers + * Reads the time stamp higher sec value to respective pointers * @param[in] pointer to synopGMACdevice * @param[in] pointer to hold 16 higher bit second register contents * \return returns void */ -void synopGMAC_TS_read_timestamp_higher_val(synopGMACdevice *gmacdev, u16 * higher_sec_val) +void synopGMAC_TS_read_timestamp_higher_val(synopGMACdevice *gmacdev, u16 *higher_sec_val) { - * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask); + * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase, GmacTSHighWord) & GmacTSHighWordMask); return; } /** - * Load the Target time stamp registers + * Load the Target time stamp registers * This function Loads the target time stamp registers with the values proviced * @param[in] pointer to synopGMACdevice * @param[in] target Timestamp High value @@ -3700,22 +3729,22 @@ void synopGMAC_TS_read_timestamp_higher_val(synopGMACdevice *gmacdev, u16 * high */ void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val) { - synopGMACWriteReg(gmacdev->MacBase,GmacTSTargetTimeHigh,sec_val); - synopGMACWriteReg(gmacdev->MacBase,GmacTSTargetTimeLow,sub_sec_val); + synopGMACWriteReg(gmacdev->MacBase, GmacTSTargetTimeHigh, sec_val); + synopGMACWriteReg(gmacdev->MacBase, GmacTSTargetTimeLow, sub_sec_val); return; } /** - * Reads the Target time stamp registers + * Reads the Target time stamp registers * This function Loads the target time stamp registers with the values proviced * @param[in] pointer to synopGMACdevice * @param[in] pointer to hold target Timestamp High value * @param[in] pointer to hold target Timestamp Low value * \return returns 0 for Success or else Failure */ -void synopGMAC_TS_read_target_timestamp(synopGMACdevice *gmacdev, u32 * sec_val, u32 * sub_sec_val) +void synopGMAC_TS_read_target_timestamp(synopGMACdevice *gmacdev, u32 *sec_val, u32 *sub_sec_val) { - * sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSTargetTimeHigh); - * sub_sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSTargetTimeLow); + * sec_val = synopGMACReadReg(gmacdev->MacBase, GmacTSTargetTimeHigh); + * sub_sec_val = synopGMACReadReg(gmacdev->MacBase, GmacTSTargetTimeLow); return; } #endif diff --git a/bsp/ls2kdev/drivers/net/synopGMAC_plat.c b/bsp/ls2kdev/drivers/net/synopGMAC_plat.c index 64ccb91e60..0c938e9949 100644 --- a/bsp/ls2kdev/drivers/net/synopGMAC_plat.c +++ b/bsp/ls2kdev/drivers/net/synopGMAC_plat.c @@ -33,49 +33,52 @@ void flush_cache(unsigned long start_addr, unsigned long size) } //convert virtual address to physical address -dma_addr_t __attribute__((weak)) gmac_dmamap(unsigned long va,u32 size) +dma_addr_t __attribute__((weak)) gmac_dmamap(unsigned long va, u32 size) { - return VA_TO_PA (va); + return VA_TO_PA(va); //return UNCACHED_TO_PHYS(va); } /** - * This is a wrapper function for Memory allocation routine. In linux Kernel + * This is a wrapper function for Memory allocation routine. In linux Kernel * it it kmalloc function * @param[in] bytes in bytes to allocate */ -void *plat_alloc_memory(u32 bytes) +void *plat_alloc_memory(u32 bytes) { //return (void*)malloc((size_t)bytes, M_DEVBUF, M_DONTWAIT); - void *buf = (void*)rt_malloc((u32)bytes); + void *buf = (void *)rt_malloc((u32)bytes); flush_cache((unsigned long)buf, bytes); return buf; } /** - * This is a wrapper function for consistent dma-able Memory allocation routine. + * This is a wrapper function for consistent dma-able Memory allocation routine. * In linux Kernel, it depends on pci dev structure * @param[in] bytes in bytes to allocate */ //allocate a space aligned to 16-byte boundary without cache -void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u32 *addr) +void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u32 *addr) { void *buf; - buf = (void*)rt_malloc((u32)(size + 16)); + buf = (void *)rt_malloc((u32)(size + 16)); //CPU_IOFlushDCache( buf,size, SYNC_W); unsigned long i = (unsigned long)buf; // rt_kprintf("size = %d\n", size); // rt_kprintf("bufaddr = %p\n", buf); // rt_kprintf("i%%16 == %d\n", i%16); - if(i % 16 == 8){ + if (i % 16 == 8) + { i += 8; } - else if(i % 16 == 4){ + else if (i % 16 == 4) + { i += 12; } - else if(i % 16 == 12){ + else if (i % 16 == 12) + { i += 4; } @@ -91,26 +94,26 @@ void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u3 * In linux Kernel, it depends on pci dev structure * @param[in] bytes in bytes to allocate */ -//void plat_free_consistent_dmaable_memory(void * addr) -void plat_free_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, void * addr,u64 dma_addr) +//void plat_free_consistent_dmaable_memory(void * addr) +void plat_free_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, void *addr, u64 dma_addr) { - rt_free((void*)PHYS_TO_CACHED(UNCACHED_TO_PHYS(addr))); + rt_free((void *)PHYS_TO_CACHED(UNCACHED_TO_PHYS(addr))); return; } /** - * This is a wrapper function for Memory free routine. In linux Kernel + * This is a wrapper function for Memory free routine. In linux Kernel * it it kfree function * @param[in] buffer pointer to be freed */ -void plat_free_memory(void *buffer) +void plat_free_memory(void *buffer) { rt_free(buffer); return ; } //convert virtual address to physical address and flush cache -dma_addr_t plat_dma_map_single(void *hwdev,void *ptr,u32 size) +dma_addr_t plat_dma_map_single(void *hwdev, void *ptr, u32 size) { unsigned long addr = (unsigned long) ptr; //CPU_IOFlushDCache(addr,size, direction); @@ -119,8 +122,8 @@ dma_addr_t plat_dma_map_single(void *hwdev,void *ptr,u32 size) } /** - * This is a wrapper function for platform dependent delay - * Take care while passing the argument to this function + * This is a wrapper function for platform dependent delay + * Take care while passing the argument to this function * @param[in] buffer pointer to be freed */ void plat_delay(u32 delay) From edc4028944c66e6106c40a759b3f49432fe82e6c Mon Sep 17 00:00:00 2001 From: 0xcccccccccccc <0xcccc@bupt.edu.cn> Date: Tue, 8 Dec 2020 10:13:52 +0800 Subject: [PATCH 5/6] - Remove duplicated line feeds and unnecessary annotations. - Maintainers information is now corrected. - Withdraw the modification on EXEC_PATH of the gcc toolchain. --- bsp/ls2kdev/README.md | 5 ++- bsp/ls2kdev/drivers/drv_spi.c | 62 ++-------------------------------- bsp/ls2kdev/drivers/drv_spi.h | 27 +++++---------- bsp/ls2kdev/drivers/drv_uart.c | 49 --------------------------- bsp/ls2kdev/rtconfig.py | 2 +- 5 files changed, 14 insertions(+), 131 deletions(-) diff --git a/bsp/ls2kdev/README.md b/bsp/ls2kdev/README.md index 302fd5f643..89e041ad71 100644 --- a/bsp/ls2kdev/README.md +++ b/bsp/ls2kdev/README.md @@ -123,10 +123,9 @@ title TFTPBOOT ## 6. 联系人信息 -维护人：[bernard][4],[0xcccccccccccc][5] +维护人：[bernard][4] [1]: http://ftp.loongnix.org/loongsonpi/pi_2/doc [2]: https://pan.baidu.com/s/17dbdOE4NAJ-qEW7drVRq2w [3]: http://ftp.loongnix.org/embedd/ls2k/ -[4]: https://github.com/BernardXiong -[5]: https://github.com/0xcccccccccccc +[4]: https://github.com/BernardXiong \ No newline at end of file diff --git a/bsp/ls2kdev/drivers/drv_spi.c b/bsp/ls2kdev/drivers/drv_spi.c index 5249cc7c51..2fa90ef121 100644 --- a/bsp/ls2kdev/drivers/drv_spi.c +++ b/bsp/ls2kdev/drivers/drv_spi.c @@ -1,20 +1,13 @@ #include #include #include - #include #include - #include "drv_spi.h" #ifdef RT_USING_SPI - - - static void spi_init(uint8_t spre_spr, uint8_t copl, uint8_t cpha) { - //rt_kprintf("SPI initiating with spre_spr:%2X ,copl:%2X ,cpha:%2X\n",spre_spr,copl,cpha); - int d; SET_SPI(SPSR, 0xc0 | (spre_spr & 0b00000011)); SET_SPI(PARAM, 0x40); SET_SPI(PARAM2, 0x01); @@ -23,23 +16,19 @@ static void spi_init(uint8_t spre_spr, uint8_t copl, uint8_t cpha) SET_SPI(SOFTCS, 0xff); } - -static void spi_set_csn(uint8_t val) //old method +static void spi_set_csn(uint8_t val) { SET_SPI(SOFTCS, val); } -// #define RT_USING_SPI_GPIOCS #ifdef RT_USING_SPI_GPIOCS #include #endif -static void spi_set_cs(unsigned char cs, int new_status) +static void spi_set_cs(unsigned char cs, int new_status) { - if (cs < 4) { unsigned char val = 0; - val = GET_SPI(SOFTCS); val |= 0x01 << cs ; // csen=1 if (new_status) // cs = 1 @@ -51,20 +40,16 @@ static void spi_set_cs(unsigned char cs, int new_status) val &= ~(0x10 << cs); // csn=0 } SET_SPI(SOFTCS, val); - return ; } #ifdef RT_USING_SPI_GPIOCS else { - //rt_kprintf("[Warnning] GPIOCS is an experimental feature: \n "); - //rt_kprintf("[Warnning] GPIO%d will be set to OUTPUT with value %d \n ",cs,new_status); - rt_pin_mode(cs, PIN_MODE_OUTPUT); + rt_pin_mode(cs, PIN_MODE_OUTPUT); // with RT_USING_SPI_GPIOCS feature enabled, gpio will be used as csn pin. rt_pin_write(cs, new_status); } #endif } - static uint8_t spi_write_for_response(uint8_t data) { uint8_t val; @@ -74,33 +59,27 @@ static uint8_t spi_write_for_response(uint8_t data) return val; } - - static int cmd_spi_init(int argc, char *argv[]) { uint8_t spre_spr, cpol, cpha; switch (argc) { case 2: - spre_spr = strtoul(argv[1], NULL, 0); spi_init(spre_spr, 0, 0); break; case 4: - spre_spr = strtoul(argv[1], NULL, 0); cpol = strtoul(argv[2], NULL, 0); cpha = strtoul(argv[3], NULL, 0); spi_init(spre_spr, 0, 0); break; - default: printf("\nusage : cmd_spi_init spre_spr \n(cmd_spi_init 0x4 0x0 0x0)\n0x4:div8 0xb:div4096\n"); break; } } MSH_CMD_EXPORT(cmd_spi_init, cmd_spi_init); - static int cmd_spi_set_csn(int argc, char *argv[]) { uint8_t val, csn; @@ -111,26 +90,22 @@ static int cmd_spi_set_csn(int argc, char *argv[]) val = strtoul(argv[2], NULL, 0); spi_set_cs(csn, val); break; - default: printf("usage:cmd_spi_set_csn csn val\n(0xbf for csn1 enable,0xff for csn1 disable)\n"); break; } } MSH_CMD_EXPORT(cmd_spi_set_csn, cmd_spi_set_csn); - static int cmd_spi_write(int argc, char *argv[]) { uint8_t data, resp; switch (argc) { case 2: - data = strtoul(argv[1], NULL, 0); resp = spi_write_for_response(data); printf("resp:%2X\n", resp); break; - default: printf("usage:cmd_spi_write data\n"); break; @@ -138,25 +113,20 @@ static int cmd_spi_write(int argc, char *argv[]) } MSH_CMD_EXPORT(cmd_spi_write, cmd_spi_write); - static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message); - const static unsigned char SPI_DIV_TABLE[] = {0b0000, 0b0001, 0b0100, 0b0010, 0b0011, 0b0101, 0b0110, 0b0111, 0b1000, 0b1001, 0b1010, 0b1011}; // 2 4 8 16 32 64 128 256 512 1024 2048 4096 static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) { - unsigned char cpol = 0; unsigned char cpha = 0; - RT_ASSERT(NULL != device); RT_ASSERT(NULL != configuration); - // baudrate if (configuration->mode & RT_SPI_CPOL) // cpol { @@ -174,54 +144,36 @@ static rt_err_t configure(struct rt_spi_device *device, { cpha = 0; } - //rt_kprintf("configure: cpol:%d cpha:%d\n",cpol,cpha); - float spi_max_speed = ((float)APB_MAX_SPEED) / (8.0 / (float)APB_FREQSCALE); - //rt_kprintf("spi max speed: %ld\n",(unsigned long)spi_max_speed); - - uint64_t div = (uint64_t)(spi_max_speed / (float)configuration->max_hz); - //rt_kprintf("require speed: %ld\n",configuration->max_hz); int ctr = 0; while (div != 1 && ctr < 12) { ctr++; div = div >> 1; } - //rt_kprintf("spi speed set to: %ld\n",(unsigned long)((spi_max_speed)/(float)(1<parent.user_data); size = message->length; - - //rt_kprintf("[%s] cs=%d\n", __FUNCTION__, cs); - - // take cs if (message->cs_take) { spi_set_cs(cs, 0); } - // send data send_ptr = message->send_buf; recv_ptr = message->recv_buf; @@ -232,7 +184,6 @@ static rt_uint32_t xfer(struct rt_spi_device *device, { data = *send_ptr++; } - if (NULL != recv_ptr) { *recv_ptr++ = spi_write_for_response(data); @@ -242,31 +193,24 @@ static rt_uint32_t xfer(struct rt_spi_device *device, spi_write_for_response(data); } } - // release cs if (message->cs_release) { spi_set_cs(cs, 1); } - return message->length; } - static struct rt_spi_ops loongson_spi_ops = { .configure = configure, .xfer = xfer }; - static struct rt_spi_bus loongson_spi; - static int loongson_spi_init() { //rt_kprintf("spi_init\n"); return rt_spi_bus_register(&loongson_spi, "spi", &loongson_spi_ops); } - INIT_BOARD_EXPORT(loongson_spi_init); - #endif diff --git a/bsp/ls2kdev/drivers/drv_spi.h b/bsp/ls2kdev/drivers/drv_spi.h index 08914e979b..cbc3bee924 100644 --- a/bsp/ls2kdev/drivers/drv_spi.h +++ b/bsp/ls2kdev/drivers/drv_spi.h @@ -1,22 +1,20 @@ -#ifndef DRV_SPI_H -#define DRV_SPI_H +#ifndef LS2K_DRV_SPI_H +#define LS2K_DRV_SPI_H #include #include - - -#define RFEMPTY 1 +// kseg1 byte operation #define KSEG1_STORE8(addr,val) *(volatile char *)(0xffffffffa0000000 | addr) = val #define KSEG1_LOAD8(addr) *(volatile char *)(0xffffffffa0000000 | addr) - +// clock configurations #define APB_MAX_SPEED 125000000U #define APB_FREQSCALE (((KSEG1_LOAD8(0xffffffffbfe104d2)>>4)&0x7)+1) - +// base addrs #define SPI_BASE 0x1fff0220 #define PMON_ADDR 0xa1000000 #define FLASH_ADDR 0x000000 - +// bit bias #define SPCR 0x0 #define SPSR 0x1 #define FIFO 0x2 @@ -26,18 +24,9 @@ #define PARAM 0x4 #define SOFTCS 0x5 #define PARAM2 0x6 - - - - +#define RFEMPTY 1 +// SPI controller operaion macros #define SET_SPI(addr,val) KSEG1_STORE8(SPI_BASE+addr,val) #define GET_SPI(addr) KSEG1_LOAD8(SPI_BASE+addr) - - -//void spi_init(uint8_t ,uint8_t,uint8_t); -//void spi_set_csn(uint8_t); -//uint8_t spi_write_for_response(uint8_t); - - #endif diff --git a/bsp/ls2kdev/drivers/drv_uart.c b/bsp/ls2kdev/drivers/drv_uart.c index 2a98dc3933..9421078769 100644 --- a/bsp/ls2kdev/drivers/drv_uart.c +++ b/bsp/ls2kdev/drivers/drv_uart.c @@ -8,18 +8,14 @@ * 2020-04-05 bigmagic Initial version * 2020-10-28 ma Buadrate & Multi-Port support */ - /** * @addtogroup ls2k */ - /*@{*/ - #include #include #include #include "drv_uart.h" - #define TRUE 1 #define FALSE 0 const struct serial_configure config_uart0 = { @@ -39,21 +35,16 @@ struct rt_uart_ls2k }; static rt_err_t ls2k_uart_set_buad(struct rt_serial_device *serial, struct serial_configure *cfg) { - struct rt_uart_ls2k *uart_dev = RT_NULL; rt_err_t ret = RT_EOK; - RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data; uint64_t brtc = (125000000U) / (16 * (cfg->baud_rate)); UART_LCR(uart_dev->base) = 0x80; // Activate buadcfg UART_LSB(uart_dev->base) = brtc & 0xff; UART_MSB(uart_dev->base) = brtc >> 8; - if (((((short)UART_MSB(uart_dev->base)) << 8) | UART_LSB(uart_dev->base)) != brtc) ret = RT_ERROR; - UART_LCR(uart_dev->base) = CFCR_8BITS; // Back to normal UART_MCR(uart_dev->base) = MCR_IENABLE/* | MCR_DTR | MCR_RTS*/; UART_IER(uart_dev->base) = 0; @@ -61,7 +52,6 @@ static rt_err_t ls2k_uart_set_buad(struct rt_serial_device *serial, struct seria static rt_err_t ls2k_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { struct rt_uart_ls2k *uart_dev = RT_NULL; - RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); ls2k_uart_set_buad(serial, cfg); @@ -74,40 +64,30 @@ static rt_err_t ls2k_uart_configure(struct rt_serial_device *serial, struct seri UART_MCR(uart_dev->base) = 0x3; UART_LSR(uart_dev->base) = 0x60; UART_MSR(uart_dev->base) = 0xb0; - return RT_EOK; } - static rt_err_t ls2k_uart_control(struct rt_serial_device *serial, int cmd, void *arg) { struct rt_uart_ls2k *uart_dev = RT_NULL; - RT_ASSERT(serial != RT_NULL); uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data; - switch (cmd) { case RT_DEVICE_CTRL_CLR_INT: /* Disable RX IRQ */ rt_hw_interrupt_mask(uart_dev->IRQ); break; - case RT_DEVICE_CTRL_SET_INT: /* Enable RX IRQ */ rt_hw_interrupt_umask(uart_dev->IRQ); UART_IER(uart_dev->base) |= (IER_IRxE | IER_ILE); break; - default: break; } - return RT_EOK; - } - static rt_bool_t uart_is_transmit_empty(struct rt_uart_ls2k *uart_dev) { unsigned char status = UART_LSR(uart_dev->base); - if (status & (UARTLSR_TE | UARTLSR_TFE)) { return TRUE; @@ -117,50 +97,35 @@ static rt_bool_t uart_is_transmit_empty(struct rt_uart_ls2k *uart_dev) return FALSE; } } - static int ls2k_uart_putc(struct rt_serial_device *serial, char c) { struct rt_uart_ls2k *uart_dev = RT_NULL; - RT_ASSERT(serial != RT_NULL); - uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data; - while (FALSE == uart_is_transmit_empty(uart_dev)) ; - UART_DAT(uart_dev->base) = c; - return 1; } - static int ls2k_uart_getc(struct rt_serial_device *serial) { struct rt_uart_ls2k *uart_dev = RT_NULL; - RT_ASSERT(serial != RT_NULL); - uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data; - if (LSR_RXRDY & UART_LSR(uart_dev->base)) { return UART_DAT(uart_dev->base); } - return -1; } - /* UART interrupt handler */ static void uart_irq_handler(int vector, void *param) { struct rt_serial_device *serial = (struct rt_serial_device *)param; struct rt_uart_ls2k *uart_dev = RT_NULL; - RT_ASSERT(serial != RT_NULL); - uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data; unsigned char iir = UART_IIR(uart_dev->base); - /* Find out interrupt reason */ if ((IIR_RXTOUT & iir) || (IIR_RXRDY & iir)) { @@ -168,9 +133,7 @@ static void uart_irq_handler(int vector, void *param) rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); rt_interrupt_leave(); } - } - static const struct rt_uart_ops ls2k_uart_ops = { ls2k_uart_configure, @@ -178,7 +141,6 @@ static const struct rt_uart_ops ls2k_uart_ops = ls2k_uart_putc, ls2k_uart_getc, }; - struct rt_uart_ls2k uart_dev0 = { (void *)UARTx_BASE(0), @@ -190,41 +152,30 @@ struct rt_uart_ls2k uart_dev4 = LS2K_UART_4_5_6_7_IRQ, }; - struct rt_serial_device serial, serial4; - void rt_hw_uart_init(void) { - //UART0_1_ENABLE=0xff; struct rt_uart_ls2k *uart, *uart4; struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - - uart = &uart_dev0; uart4 = &uart_dev4; - serial.ops = &ls2k_uart_ops; serial.config = config_uart0; - serial4.ops = &ls2k_uart_ops; serial4.config = config; - rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART0"); rt_hw_interrupt_install(uart4->IRQ, uart_irq_handler, &serial4, "UART4"); - /* register UART device */ rt_hw_serial_register(&serial, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); - rt_hw_serial_register(&serial4, "uart4", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart_dev4); - } /*@}*/ diff --git a/bsp/ls2kdev/rtconfig.py b/bsp/ls2kdev/rtconfig.py index e391bd87f0..0988198426 100644 --- a/bsp/ls2kdev/rtconfig.py +++ b/bsp/ls2kdev/rtconfig.py @@ -16,7 +16,7 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = "/home/ma/mips-2015.05/bin/" + EXEC_PATH = "/opt/mips-2015.05-19-mips-sde-elf-i686-pc-linux-gnu/mips-2015.05/bin/" # EXEC_PATH = r'D:\mgc\embedded\codebench\bin' else: print('================ERROR===========================') From 90560e87c584f5a6a16a42aa6205ecfefb4e935f Mon Sep 17 00:00:00 2001 From: 0xcccccccccccc <0xcccc@bupt.edu.cn> Date: Fri, 11 Dec 2020 00:45:58 +0800 Subject: [PATCH 6/6] - Copyright information added. --- bsp/ls2kdev/drivers/drv_spi.c | 14 ++++++++++++++ bsp/ls2kdev/drivers/drv_spi.h | 14 ++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/bsp/ls2kdev/drivers/drv_spi.c b/bsp/ls2kdev/drivers/drv_spi.c index 2fa90ef121..3f3ad90802 100644 --- a/bsp/ls2kdev/drivers/drv_spi.c +++ b/bsp/ls2kdev/drivers/drv_spi.c @@ -1,3 +1,16 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-28 0xcccccccccccc Initial Version + */ +/** + * @addtogroup ls2k + */ +/*@{*/ #include #include #include @@ -214,3 +227,4 @@ static int loongson_spi_init() INIT_BOARD_EXPORT(loongson_spi_init); #endif +/*@}*/ diff --git a/bsp/ls2kdev/drivers/drv_spi.h b/bsp/ls2kdev/drivers/drv_spi.h index cbc3bee924..0b254d4fc2 100644 --- a/bsp/ls2kdev/drivers/drv_spi.h +++ b/bsp/ls2kdev/drivers/drv_spi.h @@ -1,3 +1,16 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-28 0xcccccccccccc Initial Version + */ +/** + * @addtogroup ls2k + */ +/*@{*/ #ifndef LS2K_DRV_SPI_H #define LS2K_DRV_SPI_H @@ -30,3 +43,4 @@ #define GET_SPI(addr) KSEG1_LOAD8(SPI_BASE+addr) #endif +/*@}*/