libs/rt-thread
libs
/
rt-thread
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

修改格式

This commit is contained in:
Huang bo 2021-12-15 11:10:13 +08:00
parent b8db37f53f
commit 3e32b36c2b
3 changed files with 49 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

68
bsp/ti-tms320c6678/common/common.c
View File

@ -10,9 +10,9 @@
#include "common.h"
CSL_BootcfgRegs * gpBootCfgRegs = (CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS;
CSL_CgemRegs * gpCGEM_regs = (CSL_CgemRegs *)CSL_CGEM0_5_REG_BASE_ADDRESS_REGS;
CSL_TmrPlusRegs * gpTimerRegs[9] = {
CSL_BootcfgRegs * gp_bootcfg_regs = (CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS;
CSL_CgemRegs * gp_cgem_regs = (CSL_CgemRegs *)CSL_CGEM0_5_REG_BASE_ADDRESS_REGS;
CSL_TmrPlusRegs * gp_timer_regs[9] = {
(CSL_TmrPlusRegs *)CSL_TIMER_0_REGS,
(CSL_TmrPlusRegs *)CSL_TIMER_1_REGS,
(CSL_TmrPlusRegs *)CSL_TIMER_2_REGS,
@ -29,22 +29,22 @@ void cpu_interrupt_init(void)
//clear interrupt and excpetion events
ICR = IFR;
ECR = EFR;
IER= 3; //disable all interrupts
IER = 3; //disable all interrupts
/* disable event combine */
gpCGEM_regs->EVTMASK[0] = 0xffffffff;
gpCGEM_regs->EVTMASK[1] = 0xffffffff;
gpCGEM_regs->EVTMASK[2] = 0xffffffff;
gpCGEM_regs->EVTMASK[3] = 0xffffffff;
gp_cgem_regs->EVTMASK[0] = 0xffffffff;
gp_cgem_regs->EVTMASK[1] = 0xffffffff;
gp_cgem_regs->EVTMASK[2] = 0xffffffff;
gp_cgem_regs->EVTMASK[3] = 0xffffffff;
/*Clear all CPU events*/
gpCGEM_regs->EVTCLR[0]= 0xFFFFFFFF;
gpCGEM_regs->EVTCLR[1]= 0xFFFFFFFF;
gpCGEM_regs->EVTCLR[2]= 0xFFFFFFFF;
gpCGEM_regs->EVTCLR[3]= 0xFFFFFFFF;
gp_cgem_regs->EVTCLR[0] = 0xFFFFFFFF;
gp_cgem_regs->EVTCLR[1] = 0xFFFFFFFF;
gp_cgem_regs->EVTCLR[2] = 0xFFFFFFFF;
gp_cgem_regs->EVTCLR[3] = 0xFFFFFFFF;
/*Interrupt Service Table Pointer to begining of LL2 memory*/
ISTP= 0x800000;
ISTP = 0x800000;
}
void keystone_cpu_init(void)
@ -56,10 +56,10 @@ void keystone_cpu_init(void)
/*===============================Timer=================================*/
void reset_timer(int timer_num)
{
if(gpTimerRegs[timer_num]->TGCR)
if(gp_timer_regs[timer_num]->TGCR)
{
gpTimerRegs[timer_num]->TGCR = 0;
gpTimerRegs[timer_num]->TCR= 0;
gp_timer_regs[timer_num]->TGCR = 0;
gp_timer_regs[timer_num]->TCR= 0;
}
}
@ -67,8 +67,8 @@ void timer64_init(Timer64_Config * tmrCfg)
{
reset_timer(tmrCfg->timer_num);
gpTimerRegs[tmrCfg->timer_num]->CNTLO = 0;
gpTimerRegs[tmrCfg->timer_num]->CNTHI = 0;
gp_timer_regs[tmrCfg->timer_num]->CNTLO = 0;
gp_timer_regs[tmrCfg->timer_num]->CNTHI = 0;
/*please note, in clock mode, two timer periods generate a clock,
one timer period output high voltage level, the other timer period
@ -80,17 +80,17 @@ void timer64_init(Timer64_Config * tmrCfg)
}
/*the value written into period register is the expected value minus one*/
gpTimerRegs[tmrCfg->timer_num]->PRDLO = _loll(tmrCfg->period-1);
gpTimerRegs[tmrCfg->timer_num]->PRDHI = _hill(tmrCfg->period-1);
gp_timer_regs[tmrCfg->timer_num]->PRDLO = _loll(tmrCfg->period-1);
gp_timer_regs[tmrCfg->timer_num]->PRDHI = _hill(tmrCfg->period-1);
if(tmrCfg->reload_period>1)
{
gpTimerRegs[tmrCfg->timer_num]->RELLO = _loll(tmrCfg->reload_period-1);
gpTimerRegs[tmrCfg->timer_num]->RELHI = _hill(tmrCfg->reload_period-1);
gp_timer_regs[tmrCfg->timer_num]->RELLO = _loll(tmrCfg->reload_period-1);
gp_timer_regs[tmrCfg->timer_num]->RELHI = _hill(tmrCfg->reload_period-1);
}
if(TIMER_WATCH_DOG == tmrCfg->timerMode)
{
gpTimerRegs[tmrCfg->timer_num]->TGCR =
gp_timer_regs[tmrCfg->timer_num]->TGCR =
/*Select watch-dog mode*/
(CSL_TMR_TIMMODE_WDT << CSL_TMR_TGCR_TIMMODE_SHIFT)
/*Remove the timer from reset*/
@ -99,18 +99,18 @@ void timer64_init(Timer64_Config * tmrCfg)
}
else if(TIMER_PERIODIC_WAVE == tmrCfg->timerMode)
{
gpTimerRegs[tmrCfg->timer_num]->TGCR = TMR_TGCR_PLUSEN_MASK
gp_timer_regs[tmrCfg->timer_num]->TGCR = TMR_TGCR_PLUSEN_MASK
/*for plus featuers, dual 32-bit unchained timer mode should be used*/
| (CSL_TMR_TIMMODE_DUAL_UNCHAINED << CSL_TMR_TGCR_TIMMODE_SHIFT)
/*Remove the timer from reset*/
| (CSL_TMR_TGCR_TIMLORS_MASK);
//in plus mode, interrupt/event must be enabled manually
gpTimerRegs[tmrCfg->timer_num]->INTCTL_STAT= TMR_INTCTLSTAT_EN_ALL_CLR_ALL;
gp_timer_regs[tmrCfg->timer_num]->INTCTL_STAT= TMR_INTCTLSTAT_EN_ALL_CLR_ALL;
}
else
{
gpTimerRegs[tmrCfg->timer_num]->TGCR =
gp_timer_regs[tmrCfg->timer_num]->TGCR =
/*Select 64-bit general timer mode*/
(CSL_TMR_TIMMODE_GPT << CSL_TMR_TGCR_TIMMODE_SHIFT)
/*Remove the timer from reset*/
@ -119,16 +119,16 @@ void timer64_init(Timer64_Config * tmrCfg)
}
/*make timer stop with emulation*/
gpTimerRegs[tmrCfg->timer_num]->EMUMGT_CLKSPD = (gpTimerRegs[tmrCfg->timer_num]->EMUMGT_CLKSPD&
gp_timer_regs[tmrCfg->timer_num]->EMUMGT_CLKSPD = (gp_timer_regs[tmrCfg->timer_num]->EMUMGT_CLKSPD&
~(CSL_TMR_EMUMGT_CLKSPD_FREE_MASK|CSL_TMR_EMUMGT_CLKSPD_SOFT_MASK));
if(TIMER_WATCH_DOG == tmrCfg->timerMode)
{
/*enable watchdog timer*/
gpTimerRegs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
gp_timer_regs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
| (CSL_TMR_WDTCR_WDKEY_CMD1 << CSL_TMR_WDTCR_WDKEY_SHIFT);
gpTimerRegs[tmrCfg->timer_num]->TCR=
gp_timer_regs[tmrCfg->timer_num]->TCR =
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
/*The timer is enabled continuously*/
@ -141,12 +141,12 @@ void timer64_init(Timer64_Config * tmrCfg)
| (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
/*active watchdog timer*/
gpTimerRegs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
gp_timer_regs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
| (CSL_TMR_WDTCR_WDKEY_CMD2 << CSL_TMR_WDTCR_WDKEY_SHIFT);
}
else if(TIMER_ONE_SHOT_PULSE == tmrCfg->timerMode)
{
gpTimerRegs[tmrCfg->timer_num]->TCR =
gp_timer_regs[tmrCfg->timer_num]->TCR =
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
/*The timer is enabled one-shot*/
@ -160,7 +160,7 @@ void timer64_init(Timer64_Config * tmrCfg)
}
else if(TIMER_PERIODIC_CLOCK == tmrCfg->timerMode)
{
gpTimerRegs[tmrCfg->timer_num]->TCR =
gp_timer_regs[tmrCfg->timer_num]->TCR =
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
/*The timer is enabled continuously*/
@ -174,7 +174,7 @@ void timer64_init(Timer64_Config * tmrCfg)
}
else if(TIMER_PERIODIC_WAVE == tmrCfg->timerMode)
{
gpTimerRegs[tmrCfg->timer_num]->TCR =
gp_timer_regs[tmrCfg->timer_num]->TCR =
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
/*The timer is enabled continuously with period reload*/
@ -188,7 +188,7 @@ void timer64_init(Timer64_Config * tmrCfg)
}
else /*TIMER_PERIODIC_PULSE*/
{
gpTimerRegs[tmrCfg->timer_num]->TCR =
gp_timer_regs[tmrCfg->timer_num]->TCR =
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
/*The timer is enabled continuously*/

24
bsp/ti-tms320c6678/common/common.h
View File

@ -21,8 +21,8 @@
/* DSP core clock speed in Hz */
#define DSP_CORE_SPEED_HZ 1000000000
extern CSL_CgemRegs * gpCGEM_regs;
extern CSL_BootcfgRegs * gpBootCfgRegs;
extern CSL_CgemRegs * gp_cgem_regs;
extern CSL_BootcfgRegs * gp_bootcfg_regs;
/*----------------------Timer plus registers definition----------------*/
typedef struct {
@ -69,16 +69,16 @@ typedef struct {
#define CSL_TMR_ENAMODE_CONT_RELOAD 3
extern CSL_TmrPlusRegs * gpTimer0Regs;
extern CSL_TmrPlusRegs * gpTimer1Regs;
extern CSL_TmrPlusRegs * gpTimer2Regs;
extern CSL_TmrPlusRegs * gpTimer3Regs;
extern CSL_TmrPlusRegs * gpTimer4Regs;
extern CSL_TmrPlusRegs * gpTimer5Regs;
extern CSL_TmrPlusRegs * gpTimer6Regs;
extern CSL_TmrPlusRegs * gpTimer7Regs;
extern CSL_TmrPlusRegs * gpTimer8Regs;
extern CSL_TmrPlusRegs * gpTimerRegs[];
extern CSL_TmrPlusRegs * gp_timer0_regs;
extern CSL_TmrPlusRegs * gp_timer1_regs;
extern CSL_TmrPlusRegs * gp_timer2_regs;
extern CSL_TmrPlusRegs * gp_timer3_regs;
extern CSL_TmrPlusRegs * gp_timer4_regs;
extern CSL_TmrPlusRegs * gp_timer5_regs;
extern CSL_TmrPlusRegs * gp_timer6_regs;
extern CSL_TmrPlusRegs * gp_timer7_regs;
extern CSL_TmrPlusRegs * gp_timer8_regs;
extern CSL_TmrPlusRegs * gp_timer_regs[];
typedef enum
{

6
bsp/ti-tms320c6678/driver/drv_timer.c
View File

@ -36,7 +36,7 @@ void rt_hw_systick_isr(void)
void rt_hw_system_timer_init(void)
{
// initial system timer interrupt, map local timer interrupt to INT14
gpCGEM_regs->INTMUX3 = (CSL_GEM_TINTLN << CSL_CGEM_INTMUX3_INTSEL14_SHIFT);
gp_cgem_regs->INTMUX3 = (CSL_GEM_TINTLN << CSL_CGEM_INTMUX3_INTSEL14_SHIFT);
// enable CPU INT14
rt_hw_interrupt_umask(1 << 14);
@ -45,7 +45,7 @@ void rt_hw_system_timer_init(void)
/**
* The function initial system timer.
* Use local timer (==DNUM of a core) to generate a clock on TIMO0,interrupts are generated as well
* Use local timer (== DNUM of a core) to generate a clock on TIMO0,interrupts are generated as well
*
*/
void rt_hw_system_timer_start(void)
@ -53,7 +53,7 @@ void rt_hw_system_timer_start(void)
Timer64_Config tmrCfg;
// select output on TIMO0 from local timer.
gpBootCfgRegs->TOUTSEL = (DNUM*2) << CSL_BOOTCFG_TOUTSEL_TOUTSEL0_SHIFT;
gp_bootcfg_regs->TOUTSEL = (DNUM*2) << CSL_BOOTCFG_TOUTSEL_TOUTSEL0_SHIFT;
// configure the timer to generate clocks and interrupts
tmrCfg.timer_num = DNUM;