1. [bsp] tm4c129x update TivaWare to 2.1.4.178

bsp/tm4c129x/applications/board.h

@@ -35,14 +35,14 @@ extern uint32_t SysClock;
 // </RDTConfigurator>
 
 #ifdef __CC_ARM
-extern int Image$$RW_IRAM1$$ZI$$Limit;
+extern int Image$$RW_IRAM$$ZI$$Limit;
-#define HEAP_BEGIN  ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#define HEAP_BEGIN  ((void *)&Image$$RW_IRAM$$ZI$$Limit)
 #elif __ICCARM__
 #pragma section="HEAP"
 #define HEAP_BEGIN  (__segment_end("HEAP"))
 #else
-extern int __bss_end;
+extern int _ebss;
-#define HEAP_BEGIN  ((void *)&__bss_end)
+#define HEAP_BEGIN  ((void *)&_ebss)
 #endif
 #define HEAP_END    (0x20000000 + 256*1024)
 

bsp/tm4c129x/libraries/driverlib/adc.c

@@ -2,7 +2,7 @@
 //
 // adc.c - Driver for the ADC.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -78,7 +78,7 @@
 // sequencers.
 //
 //*****************************************************************************
-static uint8_t g_pui8OversampleFactor[3];
+static uint8_t g_pui8OversampleFactor[2][3];
 
 //*****************************************************************************
 //
@@ -107,7 +107,7 @@ _ADCIntNumberGet(uint32_t ui32Base, uint32_t ui32SequenceNum)
     {
         ui8Int = ((ui32Base == ADC0_BASE) ?
                   (INT_ADC0SS0_TM4C123 + ui32SequenceNum) :
-                  (INT_ADC0SS0_TM4C123 + ui32SequenceNum));
+                  (INT_ADC1SS0_TM4C123 + ui32SequenceNum));
     }
     else if(CLASS_IS_TM4C129)
     {
@@ -502,6 +502,8 @@ void
 ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
                      uint32_t ui32Trigger, uint32_t ui32Priority)
 {
+    uint32_t ui32Gen;
+
     //
     // Check the arugments.
     //
@@ -545,11 +547,18 @@ ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
     //
     // Set the source PWM module for this sequence's PWM triggers.
     //
-    ui32SequenceNum *= 2;
+    ui32Gen = ui32Trigger & 0x0f;
-    HWREG(ui32Base + ADC_O_TSSEL) = ((HWREG(ui32Base + ADC_O_TSSEL) &
+    if(ui32Gen >= ADC_TRIGGER_PWM0 && ui32Gen <= ADC_TRIGGER_PWM3)
-                                      ~(0x30 << ui32SequenceNum)) |
+    {
-                                     ((ui32Trigger & 0x30) <<
+        //
-                                      ui32SequenceNum));
+        // Set the shift for the module and generator
+        //
+        ui32Gen = (ui32Gen - ADC_TRIGGER_PWM0) * 8;
+        
+        HWREG(ui32Base + ADC_O_TSSEL) = ((HWREG(ui32Base + ADC_O_TSSEL) &
+                                         ~(0x30 << ui32Gen)) |
+                                         ((ui32Trigger & 0x30) << ui32Gen));
+    }
 }
 
 //*****************************************************************************
@@ -924,6 +933,7 @@ ADCSoftwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
                                uint32_t ui32Factor)
 {
     uint32_t ui32Value;
+    uint32_t ui32ADCInst;
 
     //
     // Check the arguments.
@@ -941,10 +951,22 @@ ADCSoftwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
     {
     }
 
+    //
+    // Evaluate the ADC Instance.
+    //
+    if(ui32Base == ADC0_BASE)
+    {
+        ui32ADCInst = 0;
+    }
+    else
+    {
+        ui32ADCInst = 1;
+    }
+
     //
     // Save the shift factor.
     //
-    g_pui8OversampleFactor[ui32SequenceNum] = ui32Value;
+    g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum] = ui32Value;
 }
 
 //*****************************************************************************
@@ -968,14 +990,30 @@ void
 ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
                                    uint32_t ui32Step, uint32_t ui32Config)
 {
+    uint32_t ui32ADCInst;
+
+    //
+    // Evaluate the ADC Instance.
+    //
+    if(ui32Base == ADC0_BASE)
+    {
+        ui32ADCInst = 0;
+    }
+    else
+    {
+        ui32ADCInst = 1;
+    }
+
     //
     // Check the arguments.
     //
     ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
     ASSERT(ui32SequenceNum < 3);
     ASSERT(((ui32SequenceNum == 0) &&
-            (ui32Step < (8 >> g_pui8OversampleFactor[ui32SequenceNum]))) ||
+            (ui32Step < 
-           (ui32Step < (4 >> g_pui8OversampleFactor[ui32SequenceNum])));
+            (8 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))) ||
+           (ui32Step < 
+           (4 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum])));
 
     //
     // Get the offset of the sequence to be configured.
@@ -985,13 +1023,14 @@ ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
     //
     // Compute the shift for the bits that control this step.
     //
-    ui32Step *= 4 << g_pui8OversampleFactor[ui32SequenceNum];
+    ui32Step *= 4 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum];
 
     //
     // Loop through the hardware steps that make up this step of the software
     // oversampled sequence.
     //
-    for(ui32SequenceNum = 1 << g_pui8OversampleFactor[ui32SequenceNum];
+    for(ui32SequenceNum = 
+        (1 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]);
         ui32SequenceNum; ui32SequenceNum--)
     {
         //
@@ -1054,6 +1093,20 @@ ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum,
                              uint32_t *pui32Buffer, uint32_t ui32Count)
 {
     uint32_t ui32Idx, ui32Accum;
+    uint32_t ui32ADCInst;
+
+    //
+    // Evaluate the ADC Instance.
+    //
+    if(ui32Base == ADC0_BASE)
+    {
+        ui32ADCInst = 0;
+    }
+    else
+    {
+        ui32ADCInst = 1;
+    }
+
 
     //
     // Check the arguments.
@@ -1061,8 +1114,10 @@ ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum,
     ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
     ASSERT(ui32SequenceNum < 3);
     ASSERT(((ui32SequenceNum == 0) &&
-            (ui32Count < (8 >> g_pui8OversampleFactor[ui32SequenceNum]))) ||
+            (ui32Count < 
-           (ui32Count < (4 >> g_pui8OversampleFactor[ui32SequenceNum])));
+            (8 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))) ||
+            (ui32Count < 
+            (4 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum])));
 
     //
     // Get the offset of the sequence to be read.
@@ -1078,8 +1133,8 @@ ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum,
         // Compute the sum of the samples.
         //
         ui32Accum = 0;
-        for(ui32Idx = 1 << g_pui8OversampleFactor[ui32SequenceNum]; ui32Idx;
+        for(ui32Idx = 1 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum];
-            ui32Idx--)
+            ui32Idx; ui32Idx--)
         {
             //
             // Read the FIFO and add it to the accumulator.
@@ -1090,7 +1145,8 @@ ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum,
         //
         // Write the averaged sample to the output buffer.
         //
-        *pui32Buffer++ = ui32Accum >> g_pui8OversampleFactor[ui32SequenceNum];
+        *pui32Buffer++ = 
+            ui32Accum >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum];
     }
 }
 
@@ -1605,7 +1661,12 @@ ADCIntStatusEx(uint32_t ui32Base, bool bMasked)
 void
 ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
 {
-    HWREG(ui32Base + ADC_O_ISC) |= ui32IntFlags;
+    //
+    // Note: The interrupt bits are "W1C" so we DO NOT use a logical OR
+    // here to clear the requested bits. Doing so would clear all outstanding
+    // interrupts rather than just those which the caller has specified.
+    //
+    HWREG(ui32Base + ADC_O_ISC) = ui32IntFlags;
 }
 
 //*****************************************************************************
@@ -1616,12 +1677,10 @@ ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
 //! \param ui32Ref is the reference to use.
 //!
 //! The ADC reference is set as specified by \e ui32Ref.  It must be one of
-//! \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V for internal or
+//! \b ADC_REF_INT, or \b ADC_REF_EXT_3V for internal or external reference
-//! external reference.  If \b ADC_REF_INT is chosen, then an internal 3V
+//! If \b ADC_REF_INT is chosen, then an internal 3V reference is used and 
-//! reference is used and no external reference is needed.  If
+//! no external reference is needed.  If \b ADC_REF_EXT_3V is chosen, then
-//! \b ADC_REF_EXT_3V is chosen, then a 3V reference must be supplied to the
+//! a 3V reference must be supplied to the AVREF pin.
-//! AVREF pin.  If \b ADC_REF_EXT_1V is chosen, then a 1V external reference
-//! must be supplied to the AVREF pin.
 //!
 //! \note The ADC reference can only be selected on parts that have an external
 //! reference.  Consult the data sheet for your part to determine if there is
@@ -1637,8 +1696,7 @@ ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref)
     // Check the arguments.
     //
     ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
-    ASSERT((ui32Ref == ADC_REF_INT) || (ui32Ref == ADC_REF_EXT_3V) ||
+    ASSERT((ui32Ref == ADC_REF_INT) || (ui32Ref == ADC_REF_EXT_3V));
-           (ui32Ref == ADC_REF_EXT_1V));
 
     //
     // Set the reference.
@@ -1654,7 +1712,7 @@ ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref)
 //! \param ui32Base is the base address of the ADC module.
 //!
 //! Returns the value of the ADC reference setting.  The returned value is one
-//! of \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V.
+//! of \b ADC_REF_INT, or \b ADC_REF_EXT_3V.
 //!
 //! \note The value returned by this function is only meaningful if used on a
 //! part that is capable of using an external reference.  Consult the data
@@ -1919,18 +1977,14 @@ ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config,
     //
     // Check the argument.
     //
-    ASSERT(ui32Base == ADC0_BASE);
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
+    ASSERT((ui32ClockDiv - 1) <= (ADC_CC_CLKDIV_M >> ADC_CC_CLKDIV_S));
 
     //
     // A rate must be supplied.
     //
     ASSERT((ui32Config & ADC_CLOCK_RATE_FULL) != 0);
 
-    //
-    // Clock must be valid divider.
-    //
-    ASSERT(((ui32ClockDiv - 1) & ~ADC_CC_CLKDIV_M) == 0);
-
     //
     // Write the sample conversion rate.
     //
@@ -1982,7 +2036,7 @@ ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv)
     //
     // Check the argument.
     //
-    ASSERT(ui32Base == ADC0_BASE);
+    ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE));
 
     //
     // Read the current configuration.
@@ -2006,7 +2060,7 @@ ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv)
     //
     // Add in the sample interval to the configuration.
     //
-    ui32Config = (HWREG(ui32Base + ADC_O_PC) & ADC_PC_SR_M) << 4;
+    ui32Config |= (HWREG(ui32Base + ADC_O_PC) & ADC_PC_SR_M) << 4;
 
     return(ui32Config);
 }

bsp/tm4c129x/libraries/driverlib/adc.h

@@ -2,7 +2,7 @@
 //
 // adc.h - ADC headers for using the ADC driver functions.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -206,7 +206,6 @@ extern "C"
 //*****************************************************************************
 #define ADC_REF_INT             0x00000000  // Internal reference
 #define ADC_REF_EXT_3V          0x00000001  // External 3V reference
-#define ADC_REF_EXT_1V          0x00000003  // External 1V reference
 
 //*****************************************************************************
 //

bsp/tm4c129x/libraries/driverlib/aes.c

@@ -2,7 +2,7 @@
 //
 // aes.c - Driver for the AES module.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/aes.h

@@ -2,7 +2,7 @@
 //
 // aes.h - Defines and Macros for the AES module.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/can.c

@@ -2,7 +2,7 @@
 //
 // can.c - Driver for the CAN module.
 //
-// Copyright (c) 2006-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2006-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/can.h

@@ -2,7 +2,7 @@
 //
 // can.h - Defines and Macros for the CAN controller.
 //
-// Copyright (c) 2006-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2006-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/comp.c

@@ -2,7 +2,7 @@
 //
 // comp.c - Driver for the analog comparator.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/comp.h

@@ -2,7 +2,7 @@
 //
 // comp.h - Prototypes for the analog comparator driver.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/cpu.c

@@ -3,7 +3,7 @@
 // cpu.c - Instruction wrappers for special CPU instructions needed by the
 //         drivers.
 //
-// Copyright (c) 2006-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2006-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -34,7 +34,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/cpu.h

@@ -2,7 +2,7 @@
 //
 // cpu.h - Prototypes for the CPU instruction wrapper functions.
 //
-// Copyright (c) 2006-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2006-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/crc.c

@@ -2,7 +2,7 @@
 //
 // crc.c - Driver for the CRC module.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/crc.h

@@ -2,7 +2,7 @@
 //
 // crc.h - Defines and Macros for CRC module.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -65,7 +65,7 @@ extern "C"
 #define CRC_CFG_RESINV          0x00000200  // Result Inverse Enable
 #define CRC_CFG_OBR             0x00000100  // Output Reverse Enable
 #define CRC_CFG_IBR             0x00000080  // Bit reverse enable
-#define CRC_CFG_ENDIAN_SBHW     0x00000000  // Swap byte in half-word
+#define CRC_CFG_ENDIAN_SBHW     0x00000020  // Swap byte in half-word
 #define CRC_CFG_ENDIAN_SHW      0x00000010  // Swap half-word
 #define CRC_CFG_TYPE_P8005      0x00000000  // Polynomial 0x8005
 #define CRC_CFG_TYPE_P1021      0x00000001  // Polynomial 0x1021

bsp/tm4c129x/libraries/driverlib/debug.h

@@ -2,7 +2,7 @@
 //
 // debug.h - Macros for assisting debug of the driver library.
 //
-// Copyright (c) 2006-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2006-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/des.c

@@ -2,7 +2,7 @@
 //
 // des.c - Driver for the DES data transformation.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/des.h

@@ -2,7 +2,7 @@
 //
 // des.h - Defines and Macros for the DES module.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/eeprom.c

@@ -2,7 +2,7 @@
 //
 // eeprom.c - Driver for programming the on-chip EEPROM.
 //
-// Copyright (c) 2010-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2010-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/eeprom.h

@@ -2,7 +2,7 @@
 //
 // eeprom.h - Prototypes for the EEPROM driver.
 //
-// Copyright (c) 2010-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2010-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/emac.c

@@ -3,7 +3,7 @@
 // emac.c - Driver for the Integrated Ethernet Controller on Snowflake-class
 //          Tiva devices.
 //
-// Copyright (c) 2013-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2013-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -34,7 +34,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -161,7 +161,8 @@
 // masked (or enabled) via the DMAIM register.
 //
 //*****************************************************************************
-#define EMAC_NON_MASKED_INTS    (EMAC_DMARIS_TT |                             \
+#define EMAC_NON_MASKED_INTS    (EMAC_DMARIS_LPI |                            \
+                                 EMAC_DMARIS_TT |                             \
                                  EMAC_DMARIS_PMT |                            \
                                  EMAC_DMARIS_MMC)
 
@@ -207,6 +208,14 @@ g_pi16MIIClockDiv[] =
 #define NUM_CLOCK_DIVISORS      (sizeof(g_pi16MIIClockDiv) /                  \
                                  sizeof(g_pi16MIIClockDiv[0]))
 
+//*****************************************************************************
+//
+// The define for accessing PHY registers in the MMD address space.
+//
+//*****************************************************************************
+#define DEV_ADDR(x) ((x & 0xF000) >> 12)
+#define REG_ADDR(x) ((x & 0x0FFF))
+
 //*****************************************************************************
 //
 //! Initializes the Ethernet MAC and sets bus-related DMA parameters.
@@ -2917,7 +2926,6 @@ EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr)
     //
     HWREG(ui32Base + EMAC_O_MIIADDR) =
         ((HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_CR_M) |
-					EMAC_MIIADDR_CR_100_150 |
          (ui8RegAddr << EMAC_MIIADDR_MII_S) |
          (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIB);
 
@@ -4682,6 +4690,291 @@ EMACPowerManagementStatusGet(uint32_t ui32Base)
             EMAC_PMTCTLSTAT_PWRDWN));
 }
 
+//*****************************************************************************
+//
+//! Enables the wake-on-LAN feature of the MAC controller.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function is used to enable the wake-on-LAN feature of the MAC
+//! controller. It is done by first checking if the transmit path is idle and
+//! disabling the trasnmitter and the transmit DMA controller. Then it checks
+//! if any data from the network is being actively received and if not then it
+//! disables the receive DMA controller.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACWoLEnter(uint32_t ui32Base)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Check if the Transmit interrupt bit is clear.
+    //
+    while(HWREG(ui32Base + EMAC_O_DMARIS) == EMAC_DMARIS_TI)
+    {
+    }
+
+    //
+    // Disable transmission in the MAC configuration register.
+    //
+    HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_TE;
+
+    //
+    // Disable the MAC transmit path in the opmode register.
+    //
+    HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_ST;
+
+    //
+    // Check if the Receive FIFO is empty.
+    //
+    while((HWREG(ui32Base + EMAC_O_STATUS) & EMAC_STATUS_RX_FIFO_LEVEL_MASK) ==
+          EMAC_STATUS_RX_FIFO_EMPTY)
+    {
+    }
+
+    //
+    // Disable the MAC receive path.
+    //
+    HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_SR;
+}
+
+//*****************************************************************************
+//
+//! Configures the LPI timers and control register.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param bLPIConfig is state of LPI trasnmit automate bit.
+//! \param ui16LPILSTimer is the value of LS timer in milli-seconds.
+//! \param ui16LPITWTimer is the value of TW timer in micro-seconds.
+//!
+//! This function is used to configure the LPI timer and control registers when
+//! the link is established as EEE mode or when the link is lost. When the link
+//! is established as EEE, then \e ui16LPILSTimer is programmed as the link
+//! status timer value and \e ui16LPITWTimer is programmed as the transmit wait 
+//! timer value. The parameter \e bLPIConfig is used to decide if the transmit
+//! path must be automated or should be under user control.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACLPIConfig(uint32_t ui32Base, bool bLPIConfig, uint16_t ui16LPILSTimer,
+              uint16_t ui16LPITWTimer)
+{
+    uint32_t ui32TimerValue;
+
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+    
+    ui32TimerValue = ((ui16LPILSTimer << EMAC_LPITIMERCTL_LST_S) &
+                       EMAC_LPITIMERCTL_LST_M);
+    ui32TimerValue |= ui16LPITWTimer & EMAC_LPITIMERCTL_TWT_M;
+
+    //
+    // Update the LPI Timer.
+    //
+    HWREG(ui32Base + EMAC_O_LPITIMERCTL) = ui32TimerValue;
+
+    //
+    // Configure the LPI Control registers.
+    //
+    if(bLPIConfig)
+    {
+        HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_LPITXA;
+    }
+    else
+    {
+        HWREG(ui32Base + EMAC_O_LPICTLSTAT) = 0x0;
+    }
+}
+
+//*****************************************************************************
+//
+//! Enables the transmit path for LPI mode entry.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function is used to enable the transmit path in LPI mode when there
+//! is no more data to be transmitted by the MAC controller.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACLPIEnter(uint32_t ui32Base)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_LPIEN;
+}
+
+//*****************************************************************************
+//
+//! Returns the status of the LPI link.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function may be used to read the status of the transmit and receive
+//! path when the link is configured in LPI mode.
+//!
+//! \return Returns the lower 16 bits of the LPI Control and Status register.
+//
+//*****************************************************************************
+uint16_t
+EMACLPIStatus(uint32_t ui32Base)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Configure the LPI Control registers.
+    //
+    return(HWREG(ui32Base + EMAC_O_LPICTLSTAT) & 0xFFFF);
+}
+
+//*****************************************************************************
+//
+//! Sets the link status of the external PHY.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function is used to set the link status of the external PHY when the
+//! link is established in EEE mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACLPILinkSet(uint32_t ui32Base)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Configure the LPI Control registers.
+    //
+    HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_PLS;
+}
+
+//*****************************************************************************
+//
+//! Clears the link status of the external PHY.
+//!
+//! \param ui32Base is the base address of the controller.
+//!
+//! This function is used to clear the link status of the external PHY when the
+//! link is lost due to a disconnect or EEE mode link is not established.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACLPILinkClear(uint32_t ui32Base)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui32Base == EMAC0_BASE);
+
+    //
+    // Configure the LPI Control registers.
+    //
+    HWREG(ui32Base + EMAC_O_LPICTLSTAT) &= ~(EMAC_LPICTLSTAT_PLS);
+}
+
+//*****************************************************************************
+//
+//! Writes a value to an extended PHY register in MMD address space.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui8PhyAddr is the physical address of the PHY to access.
+//! \param ui16RegAddr is the address of the PHY extended register to be
+//! accessed.
+//! \param ui16Value is the value to write to the register.
+//!
+//! When uhen connected to an external PHY supporting extended registers in MMD
+//! address space, this function allows a value to be written to the MMD
+//! register specified by \e ui16RegAddr.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EMACPHYMMDWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr,
+                uint16_t ui16Data)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui8PhyAddr < 32);
+
+    //
+    // Set the address of the register we're about to write.
+    //
+    EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, DEV_ADDR(ui16RegAddr));
+    EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_ADDAR,  REG_ADDR(ui16RegAddr));
+
+    //
+    // Write the extended register value.
+    //
+    EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, 
+                 (0x4000 | DEV_ADDR(ui16RegAddr)));
+    EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, ui16Data);
+}
+
+//*****************************************************************************
+//
+//! Reads from an extended PHY register in MMD address space.
+//!
+//! \param ui32Base is the base address of the controller.
+//! \param ui8PhyAddr is the physical address of the PHY to access.
+//! \param ui16RegAddr is the address of the PHY extended register to be
+//! accessed.
+//!
+//! When connected to an external PHY supporting extended registers, this
+//! this function returns the contents of the MMD register specified by
+//! \e ui16RegAddr.
+//!
+//! \return Returns the 16-bit value read from the PHY.
+//
+//*****************************************************************************
+uint16_t
+EMACPHYMMDRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr)
+{
+    //
+    // Parameter sanity check.
+    //
+    ASSERT(ui8PhyAddr < 32);
+
+    //
+    // Set the address of the register we're about to read.
+    //
+    EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, DEV_ADDR(ui16RegAddr));
+    EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_ADDAR,  REG_ADDR(ui16RegAddr));
+
+    //
+    // Read the extended register value.
+    //
+    EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, 
+                 (0x4000 | DEV_ADDR(ui16RegAddr)));
+    return(EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_ADDAR));
+}
+
 //*****************************************************************************
 //
 // Close the Doxygen group.

bsp/tm4c129x/libraries/driverlib/emac.h

@@ -3,7 +3,7 @@
 // emac.h - Defines and Macros for the Ethernet module on Snowflake-class
 //          devices.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -34,7 +34,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -708,6 +708,12 @@ struct tEMACDMADescriptor
 #define EMAC_INT_NORMAL_INT               0x00010000
 #define EMAC_INT_ABNORMAL_INT             0x00008000
 
+//
+// This interrupt source is readable using EMACIntStatus but must
+// be cleared by calling the EMACEEEStatus().
+//
+#define EMAC_INT_LPI                      0x40000000
+
 //
 // This interrupt source is readable using EMACIntStatus but must
 // be cleared by calling the EMACTimestampIntStatus().
@@ -1012,7 +1018,17 @@ extern void EMACPowerManagementControlSet(uint32_t ui32Base,
                                           uint32_t ui32Flags);
 extern uint32_t EMACPowerManagementControlGet(uint32_t ui32Base);
 extern uint32_t EMACPowerManagementStatusGet(uint32_t ui32Base);
-
+extern void EMACWoLEnter(uint32_t ui32Base);
+extern void EMACLPIConfig(uint32_t ui32Base, bool bLPIConfig,
+                          uint16_t ui16LPILSTimer, uint16_t ui16LPITWTimer);
+extern void EMACLPIEnter(uint32_t ui32Base);
+extern uint16_t EMACLPIStatus(uint32_t ui32Base);
+extern void EMACLPILinkSet(uint32_t ui32Base);
+extern void EMACLPILinkClear(uint32_t ui32Base);
+extern void EMACPHYMMDWrite(uint32_t ui32Base, uint8_t ui8PhyAddr,
+                            uint16_t ui16RegAddr, uint16_t ui16Data);
+extern uint16_t EMACPHYMMDRead(uint32_t ui32Base, uint8_t ui8PhyAddr,
+                               uint16_t ui16RegAddr);
 //*****************************************************************************
 //
 // Mark the end of the C bindings section for C++ compilers.

bsp/tm4c129x/libraries/driverlib/epi.c

@@ -2,7 +2,7 @@
 //
 // epi.c - Driver for the EPI module.
 //
-// Copyright (c) 2008-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2008-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/epi.h

@@ -2,7 +2,7 @@
 //
 // epi.h - Prototypes and macros for the EPI module.
 //
-// Copyright (c) 2008-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2008-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/flash.c

@@ -2,7 +2,7 @@
 //
 // flash.c - Driver for programming the on-chip flash.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -581,7 +581,81 @@ FlashUserSet(uint32_t ui32User0, uint32_t ui32User1)
 
 //*****************************************************************************
 //
-//! Saves the user registers.
+//! Gets all the user registers.
+//!
+//! \param pui32User0 is a pointer to the location to store USER Register 0.
+//! \param pui32User1 is a pointer to the location to store USER Register 1.
+//! \param pui32User2 is a pointer to the location to store USER Register 2.
+//! \param pui32User3 is a pointer to the location to store USER Register 3.
+//!
+//! This function reads the contents of user registers 0, 1, 2 and 3, and
+//! stores them in the specified locations.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+int32_t
+FlashAllUserRegisterGet(uint32_t *pui32User0, uint32_t *pui32User1,
+                        uint32_t *pui32User2, uint32_t *pui32User3)
+{
+    //
+    // Verify that the pointers are valid.
+    //
+    ASSERT(pui32User0 != 0);
+    ASSERT(pui32User1 != 0);
+    ASSERT(pui32User2 != 0);
+    ASSERT(pui32User3 != 0);
+
+    //
+    // Get and store the current value of the user registers.
+    //
+    *pui32User0 = HWREG(FLASH_USERREG0);
+    *pui32User1 = HWREG(FLASH_USERREG1);
+    *pui32User2 = HWREG(FLASH_USERREG2);
+    *pui32User3 = HWREG(FLASH_USERREG3);
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Sets the user registers 0 to 3
+//!
+//! \param ui32User0 is the value to store in USER Register 0.
+//! \param ui32User1 is the value to store in USER Register 1.
+//! \param ui32User2 is the value to store in USER Register 2.
+//! \param ui32User3 is the value to store in USER Register 3.
+//!
+//! This function sets the contents of the user registers 0, 1, 2 and 3 to
+//! the specified values.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+int32_t
+FlashAllUserRegisterSet(uint32_t ui32User0, uint32_t ui32User1,
+                        uint32_t ui32User2, uint32_t ui32User3)
+{
+    //
+    // Save the new values into the user registers.
+    //
+    HWREG(FLASH_USERREG0) = ui32User0;
+    HWREG(FLASH_USERREG1) = ui32User1;
+    HWREG(FLASH_USERREG2) = ui32User2;
+    HWREG(FLASH_USERREG3) = ui32User3;
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
+//*****************************************************************************
+//
+//! Saves the user registers 0 and 1.
 //!
 //! This function makes the currently programmed user register 0 and 1 settings
 //! permanent.  This operation is non-reversible; a chip reset or power cycle
@@ -628,6 +702,58 @@ FlashUserSave(void)
     return(0);
 }
 
+//*****************************************************************************
+//
+//! Saves the user registers.
+//!
+//! This function makes the currently programmed user register 0, 1, 2 and 3
+//! settings permanent.  This operation is non-reversible; a chip reset or
+//! power cycle does not change the flash protection.
+//!
+//! This function does not return until the protection has been saved.
+//!
+//! \note To ensure data integrity of the user registers, the commits should
+//! not be interrupted with a power loss.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+int32_t
+FlashAllUserRegisterSave(void)
+{
+    uint32_t ui32Index;
+
+    //
+    // Setting the MSB of FMA will trigger a permanent save of a USER Register.
+    // The 2 least signigicant bits, specify the exact User Register to save.
+    // The value of the least significant bits for
+    // USER Register 0 is 00,
+    // USER Register 1 is 01,
+    // USER Register 2 is 10 and
+    // USER Register 3 is 11.
+    //
+    for(ui32Index = 0; ui32Index < 4; ui32Index++)
+    {
+        //
+        // Tell the flash controller to commit a USER Register.
+        //
+        HWREG(FLASH_FMA) = (0x80000000 + ui32Index);
+        HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
+
+        //
+        // Wait until the write has completed.
+        //
+        while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
+        {
+        }
+    }
+
+    //
+    // Success.
+    //
+    return(0);
+}
+
 //*****************************************************************************
 //
 //! Registers an interrupt handler for the flash interrupt.

bsp/tm4c129x/libraries/driverlib/flash.h

@@ -2,7 +2,7 @@
 //
 // flash.h - Prototypes for the flash driver.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -93,7 +93,16 @@ extern int32_t FlashProtectSet(uint32_t ui32Address,
 extern int32_t FlashProtectSave(void);
 extern int32_t FlashUserGet(uint32_t *pui32User0, uint32_t *pui32User1);
 extern int32_t FlashUserSet(uint32_t ui32User0, uint32_t ui32User1);
+extern int32_t FlashAllUserRegisterGet(uint32_t *pui32User0,
+                                       uint32_t *pui32User1,
+                                       uint32_t *pui32User2,
+                                       uint32_t *pui32User3);
+extern int32_t FlashAllUserRegisterSet(uint32_t ui32User0,
+                                       uint32_t ui32User1,
+                                       uint32_t ui32User2,
+                                       uint32_t ui32User3);
 extern int32_t FlashUserSave(void);
+extern int32_t FlashAllUserRegisterSave(void);
 extern void FlashIntRegister(void (*pfnHandler)(void));
 extern void FlashIntUnregister(void);
 extern void FlashIntEnable(uint32_t ui32IntFlags);

bsp/tm4c129x/libraries/driverlib/fpu.c

@@ -3,7 +3,7 @@
 // fpu.c - Routines for manipulating the floating-point unit in the Cortex-M
 //         processor.
 //
-// Copyright (c) 2011-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2011-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -34,7 +34,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/fpu.h

@@ -2,7 +2,7 @@
 //
 // fpu.h - Prototypes for the floatint point manipulation routines.
 //
-// Copyright (c) 2011-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2011-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/gpio.c

@@ -2,7 +2,7 @@
 //
 // gpio.c - API for GPIO ports
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -116,6 +116,9 @@ static const uint32_t g_ppui32GPIOIntMapSnowflake[][2] =
     { GPIO_PORTN_BASE, INT_GPION_TM4C129 },
     { GPIO_PORTP_BASE, INT_GPIOP0_TM4C129 },
     { GPIO_PORTQ_BASE, INT_GPIOQ0_TM4C129 },
+    { GPIO_PORTR_BASE, INT_GPIOR_TM4C129 },
+    { GPIO_PORTS_BASE, INT_GPIOS_TM4C129 },
+    { GPIO_PORTT_BASE, INT_GPIOT_TM4C129 },
 };
 static const uint_fast32_t g_ui32GPIOIntMapSnowflakeRows =
     (sizeof(g_ppui32GPIOIntMapSnowflake) /
@@ -406,11 +409,14 @@ GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins,
     // Check the arguments.
     //
     ASSERT(_GPIOBaseValid(ui32Port));
-    ASSERT((ui32IntType == GPIO_FALLING_EDGE) ||
+    ASSERT(((ui32IntType & 0xF) == GPIO_FALLING_EDGE) ||
-           (ui32IntType == GPIO_RISING_EDGE) ||
+           ((ui32IntType & 0xF) == GPIO_RISING_EDGE) ||
-           (ui32IntType == GPIO_BOTH_EDGES) ||
+           ((ui32IntType & 0xF) == GPIO_BOTH_EDGES) ||
-           (ui32IntType == GPIO_LOW_LEVEL) ||
+           ((ui32IntType & 0xF) == GPIO_LOW_LEVEL) ||
-           (ui32IntType == GPIO_HIGH_LEVEL));
+           ((ui32IntType & 0xF) == GPIO_HIGH_LEVEL));
+    ASSERT(((ui32IntType & 0x000F0000) == 0) ||
+           (((ui32IntType & 0x000F0000) == GPIO_DISCRETE_INT) &&
+            ((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE))));
 
     //
     // Set the pin interrupt type.
@@ -981,6 +987,99 @@ GPIOIntUnregister(uint32_t ui32Port)
     IntUnregister(ui32Int);
 }
 
+//*****************************************************************************
+//
+//! Registers an interrupt handler for an individual pin of a GPIO port.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui32Pin is the pin whose interrupt is to be registered.
+//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling
+//! function.
+//!
+//! This function ensures that the interrupt handler specified by
+//! \e pfnIntHandler is called when an interrupt is detected from the selected
+//! pin of a GPIO port.  This function also enables the corresponding GPIO pin
+//! interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntRegisterPin(uint32_t ui32Port, uint32_t ui32Pin,
+                   void (*pfnIntHandler)(void))
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE));
+    ASSERT((ui32Pin > 0) && (ui32Pin < 8));
+    ASSERT(pfnIntHandler != 0);
+
+    //
+    // Get the interrupt number associated with the specified GPIO.
+    //
+    ui32Int = _GPIOIntNumberGet(ui32Port);
+
+    //
+    // Register the interrupt handler.
+    //
+    IntRegister((ui32Int + ui32Pin), pfnIntHandler);
+
+    //
+    // Enable the GPIO pin interrupt.
+    //
+    IntEnable(ui32Int + ui32Pin);
+}
+
+//*****************************************************************************
+//
+//! Removes an interrupt handler for an individual pin of a GPIO port.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui32Pin is the pin whose interrupt is to be unregistered.
+//!
+//! This function unregisters the interrupt handler for the specified pin of a
+//! GPIO port.  This function also disables the corresponding GPIO pin
+//! interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntUnregisterPin(uint32_t ui32Port, uint32_t ui32Pin)
+{
+    uint32_t ui32Int;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE));
+    ASSERT((ui32Pin > 0) && (ui32Pin < 8));
+
+    //
+    // Get the interrupt number associated with the specified GPIO.
+    //
+    ui32Int = _GPIOIntNumberGet(ui32Port);
+
+    //
+    // Disable the GPIO pin interrupt.
+    //
+    IntDisable(ui32Int + ui32Pin);
+
+    //
+    // UnRegister the interrupt handler.
+    //
+    IntUnregister(ui32Int + ui32Pin);
+}
+
 //*****************************************************************************
 //
 //! Reads the values present of the specified pin(s).
@@ -1199,6 +1298,78 @@ GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins)
                      GPIO_PIN_TYPE_ANALOG);
 }
 
+//*****************************************************************************
+//
+//! Configures pin(s) for use as an analog comparator output.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The analog comparator output pins must be properly configured for the analog
+//! comparator to function correctly.  This function provides the proper
+//! configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be inputs.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as an clock to be output from the device.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The system control output pin must be properly configured for the DIVSCLK to
+//! function correctly. This function provides the proper configuration for
+//! those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be inputs.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
 //*****************************************************************************
 //
 //! Configures pin(s) for use by the external peripheral interface.
@@ -1487,6 +1658,42 @@ GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins)
     GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_OUT);
 }
 
+//*****************************************************************************
+//
+//! Configures pin(s) for use as an Hibernate RTC Clock.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The hibernate output pin must be properly configured for the RTCCLK to
+//! function correctly. This function provides the proper configuration for the
+//! RTC Clock to be output from the device.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be inputs.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
 //*****************************************************************************
 //
 //! Configures pin for use as SDA by the I2C peripheral.
@@ -1640,24 +1847,24 @@ GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins)
 
 //*****************************************************************************
 //
-//! Configures pin(s) for use by the LPC module.
+//! Configures pin(s) for use by the 1-Wire module.
 //!
 //! \param ui32Port is the base address of the GPIO port.
 //! \param ui8Pins is the bit-packed representation of the pin(s).
 //!
-//! The LPC pins must be properly configured for the LPC module to function
+//! The 1-Wire pin must be properly configured for the 1-Wire peripheral to
-//! correctly.  This function provides a typical configuration for those
+//! function correctly.  This function provides a typical configuration for
-//! pin(s); other configurations may work as well depending upon the board
+//! those pin(s); other configurations may work as well depending upon the
-//! setup (for example, using the on-chip pull-ups).
+//! board setup (for example, using the on-chip pull-ups).
 //!
 //! The pin(s) are specified using a bit-packed byte, where each bit that is
 //! set identifies the pin to be accessed, and where bit 0 of the byte
 //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
 //!
-//! \note This function cannot be used to turn any pin into an LPC pin; it only
+//! \note This function cannot be used to turn any pin into a 1-Wire pin; it
-//! configures an LPC pin for proper operation.  Note that a GPIOPinConfigure()
+//! only configures a 1-Wire pin for proper operation.  Note that a
-//! function call is also required to properly configure a pin for the LPC
+//! GPIOPinConfigure() function call is also required to properly configure a
-//! function.
+//! pin for the 1-Wire function.
 //!
 //! \note A subset of GPIO pins on Tiva devices, notably those used by the
 //! JTAG/SWD interface and any pin capable of acting as an NMI input, are
@@ -1671,7 +1878,7 @@ GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins)
 //
 //*****************************************************************************
 void
-GPIOPinTypeLPC(uint32_t ui32Port, uint8_t ui8Pins)
+GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins)
 {
     //
     // Check the arguments.
@@ -1686,107 +1893,6 @@ GPIOPinTypeLPC(uint32_t ui32Port, uint8_t ui8Pins)
     //
     // Set the pad(s) for standard push-pull operation.
     //
-    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
-}
-
-//*****************************************************************************
-//
-//! Configures a pin for receive use by the PECI module.
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! The PECI receive pin must be properly configured for the PECI module to
-//! function correctly.  This function provides a typical configuration for
-//! that pin.
-//!
-//! The pin is specified using a bit-packed byte, where each bit that is set
-//! identifies the pin to be accessed, and where bit 0 of the byte represents
-//! GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This function cannot be used to turn any pin into a PECI receive pin;
-//! it only configures a PECI receive pin for proper operation.  Note that a
-//! GPIOPinConfigure() function call is also required to properly configure a
-//! pin for the PECI receive function.
-//!
-//! \note A subset of GPIO pins on Tiva devices, notably those used by the
-//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
-//! locked against inadvertent reconfiguration.  These pins must be unlocked
-//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
-//! registers before this function can be called.  Please see the ``gpio_jtag''
-//! example application for the mechanism required and consult your part
-//! datasheet for information on affected pins.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypePECIRx(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_GPIOBaseValid(ui32Port));
-
-    //
-    // Make the pin(s) be inputs.
-    //
-    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN);
-
-    //
-    // Set the pad(s) for analog operation.
-    //
-    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA,
-                     GPIO_PIN_TYPE_ANALOG);
-}
-
-//*****************************************************************************
-//
-//! Configures a pin for transmit use by the PECI module.
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! The PECI transmit pin must be properly configured for the PECI module to
-//! function correctly.  This function provides a typical configuration for
-//! that pin.
-//!
-//! The pin is specified using a bit-packed byte, where each bit that is set
-//! identifies the pin to be accessed, and where bit 0 of the byte represents
-//! GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This function cannot be used to turn any pin into a PECI transmit
-//! pin; it only configures a PECI transmit pin for proper operation.  Note
-//! that a GPIOPinConfigure() function call is also required to properly
-//! configure the pin for the PECI transmit function.
-//!
-//! \note A subset of GPIO pins on Tiva devices, notably those used by the
-//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
-//! locked against inadvertent reconfiguration.  These pins must be unlocked
-//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
-//! registers before this function can be called.  Please see the ``gpio_jtag''
-//! example application for the mechanism required and consult your part
-//! datasheet for information on affected pins.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypePECITx(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_GPIOBaseValid(ui32Port));
-
-    //
-    // Make the pin(s) be inputs.
-    //
-    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
-
-    //
-    // Set the pad(s) for analog operation.
-    //
     GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
 }
 
@@ -1995,6 +2101,56 @@ GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins)
     GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
 }
 
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the Trace peripheral.
+//!
+//! \param ui32Port is the base address of the GPIO port.
+//! \param ui8Pins is the bit-packed representation of the pin(s).
+//!
+//! The Trace pins must be properly configured for the Trace peripheral to
+//! function correctly.  This function provides a typical configuration for
+//! those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This function cannot be used to turn any pin into a trace pin; it
+//! only configures a trace pin for proper operation.  Note that a
+//! GPIOPinConfigure() function call is also required to properly configure a
+//! pin for the Trace function.
+//!
+//! \note A subset of GPIO pins on Tiva devices, notably those used by the
+//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
+//! locked against inadvertent reconfiguration.  These pins must be unlocked
+//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
+//! registers before this function can be called.  Please see the ``gpio_jtag''
+//! example application for the mechanism required and consult your part
+//! datasheet for information on affected pins.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_GPIOBaseValid(ui32Port));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
 //*****************************************************************************
 //
 //! Configures pin(s) for use by the UART peripheral.
@@ -2244,211 +2400,6 @@ GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins)
                      GPIO_PIN_TYPE_WAKE_LOW);
 }
 
-//*****************************************************************************
-//
-//! Configures pin(s) for use as scan matrix keyboard rows (outputs).
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! The GPIO pins must be properly configured in order to function correctly as
-//! scan matrix keyboard outputs.  This function provides the proper
-//! configuration for those pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This function cannot be used to turn any pin into a scan matrix
-//! keyboard row pin; it only configures a scan matrix keyboard row pin for
-//! proper operation.  Note that a GPIOPinConfigure() function call is also
-//! required to properly configure a pin for the scan matrix keyboard
-//! function.
-//!
-//! \note A subset of GPIO pins on Tiva devices, notably those used by the
-//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
-//! locked against inadvertent reconfiguration.  These pins must be unlocked
-//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
-//! registers before this function can be called.  Please see the ``gpio_jtag''
-//! example application for the mechanism required and consult your part
-//! datasheet for information on affected pins.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeKBRow(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_GPIOBaseValid(ui32Port));
-
-    //
-    // Make the pin(s) be peripheral controlled.
-    //
-    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
-
-    //
-    // Set the pad(s) for push/pull operation.
-    //
-    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use as scan matrix keyboard columns (inputs).
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! The GPIO pins must be properly configured in order to function correctly as
-//! scan matrix keyboard inputs.  This function provides the proper
-//! configuration for those pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This function cannot be used to turn any pin into a scan matrix
-//! keyboard column pin; it only configures a scan matrix keyboard column pin
-//! for proper operation.  Note that a GPIOPinConfigure() function call is also
-//! required to properly configure a pin for the scan matrix keyboard
-//! function.
-//!
-//! \note A subset of GPIO pins on Tiva devices, notably those used by the
-//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
-//! locked against inadvertent reconfiguration.  These pins must be unlocked
-//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
-//! registers before this function can be called.  Please see the ``gpio_jtag''
-//! example application for the mechanism required and consult your part
-//! datasheet for information on affected pins.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeKBColumn(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_GPIOBaseValid(ui32Port));
-
-    //
-    // Make the pin(s) be peripheral controlled.
-    //
-    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
-
-    //
-    // Set the pad(s) for standard push-pull operation.
-    //
-    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA,
-                     GPIO_PIN_TYPE_STD_WPU);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use as an LED sequencer output.
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! The GPIO pins must be properly configured in order to function correctly as
-//! LED sequencers.  This function provides the proper configuration for those
-//! pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This function cannot be used to turn any pin into an LED sequencer
-//! output pin; it only configures an LED sequencer output pin for proper
-//! operation.  Note that a GPIOPinConfigure() function call is also
-//! required to properly configure a pin for the LED sequencer function.
-//!
-//! \note A subset of GPIO pins on Tiva devices, notably those used by the
-//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
-//! locked against inadvertent reconfiguration.  These pins must be unlocked
-//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
-//! registers before this function can be called.  Please see the ``gpio_jtag''
-//! example application for the mechanism required and consult your part
-//! datasheet for information on affected pins.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeLEDSeq(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_GPIOBaseValid(ui32Port));
-
-    //
-    // Make the pin(s) be peripheral controlled.
-    //
-    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
-
-    //
-    // Set the pad(s) for push/pull operation and 8mA strength.  The external
-    // hardware should be set up such that we sink current when the LED is
-    // turned on, hence the 8mA configuration choice.
-    //
-    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use as Consumer Infrared inputs or outputs.
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! The GPIO pins must be properly configured in order to function correctly as
-//! Consumer Infrared pins.  This function provides the proper configuration
-//! for those pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This function cannot be used to turn any pin into a CIR pin; it only
-//! configures a CIR pin for proper operation.  Note that a GPIOPinConfigure()
-//! function call is also required to properly configure a pin for the
-//! Consumer Infrared function.
-//!
-//! \note A subset of GPIO pins on Tiva devices, notably those used by the
-//! JTAG/SWD interface and any pin capable of acting as an NMI input, are
-//! locked against inadvertent reconfiguration.  These pins must be unlocked
-//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR
-//! registers before this function can be called.  Please see the ``gpio_jtag''
-//! example application for the mechanism required and consult your part
-//! datasheet for information on affected pins.
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-GPIOPinTypeCIR(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(_GPIOBaseValid(ui32Port));
-
-    //
-    // Make the pin(s) be peripheral controlled.
-    //
-    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
-
-    //
-    // Set the pad(s) for standard push-pull operation.
-    //
-    GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
-}
-
 //*****************************************************************************
 //
 //! Retrieves the wake pins status.
@@ -2475,7 +2426,7 @@ GPIOPinTypeCIR(uint32_t ui32Port, uint8_t ui8Pins)
 uint32_t
 GPIOPinWakeStatus(uint32_t ui32Port)
 {
-    return(ui32Port + GPIO_O_WAKESTAT);
+    return(HWREG(ui32Port + GPIO_O_WAKESTAT));
 }
 
 //*****************************************************************************
@@ -2513,7 +2464,7 @@ GPIOPinConfigure(uint32_t ui32PinConfig)
     //
     // Check the argument.
     //
-    ASSERT(((ui32PinConfig >> 16) & 0xff) < 15);
+    ASSERT(((ui32PinConfig >> 16) & 0xff) < 18);
     ASSERT(((ui32PinConfig >> 8) & 0xe3) == 0);
 
     //

bsp/tm4c129x/libraries/driverlib/gpio.h

@@ -2,7 +2,7 @@
 //
 // gpio.h - Defines and Macros for GPIO API.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -154,25 +154,33 @@ extern uint32_t GPIOIntStatus(uint32_t ui32Port, bool bMasked);
 extern void GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags);
 extern void GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void));
 extern void GPIOIntUnregister(uint32_t ui32Port);
+extern void GPIOIntRegisterPin(uint32_t ui32Port, uint32_t ui32Pin,
+                               void (*pfnIntHandler)(void));
+extern void GPIOIntUnregisterPin(uint32_t ui32Port, uint32_t ui32Pin);
 extern int32_t GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val);
 extern void GPIOPinConfigure(uint32_t ui32PinConfig);
 extern void GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins);
+extern void GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins);
 extern void GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins);

bsp/tm4c129x/libraries/driverlib/hibernate.c

@@ -2,7 +2,7 @@
 //
 // hibernate.c - Driver for the Hibernation module
 //
-// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2007-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -124,10 +124,12 @@ _HibernateWriteComplete(void)
 //! This function enables the Hibernation module for operation.  This function
 //! should be called before any of the Hibernation module features are used.
 //!
-//! The peripheral clock is the same as the processor clock.  This value is
+//! The peripheral clock is the same as the processor clock.  The frequency of
-//! returned by SysCtlClockGet(), or it can be explicitly hard-coded if it is
+//! the system clock is the value returned by SysCtlClockGet() for TM4C123x
-//! constant and known (to save the code/execution overhead of a call to
+//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices,
-//! SysCtlClockGet()).
+//! or it can be explicitly hard coded if it is constant and known (to save the
+//! code/execution overhead of a call to SysCtlClockGet() or fetch of the 
+//! variable call holding the return value of SysCtlClockFreqSet()).
 //!
 //! \return None.
 //
@@ -2067,7 +2069,7 @@ HibernateTamperIOEnable(uint32_t ui32Input, uint32_t ui32Config)
     //
     // Set tamper I/O configuration for the requested input.
     //
-    ui32Temp |= (ui32Mask | ((ui32Config | HIB_TPIO_EN0) << (ui32Input << 3)));
+    ui32Temp = (ui32Mask | ((ui32Config | HIB_TPIO_EN0) << (ui32Input << 3)));
 
     //
     // Unlock the tamper registers.

bsp/tm4c129x/libraries/driverlib/hibernate.h

@@ -2,7 +2,7 @@
 //
 // hibernate.h - API definition for the Hibernation module.
 //
-// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2007-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/i2c.c

@@ -2,7 +2,7 @@
 //
 // i2c.c - Driver for Inter-IC (I2C) bus block.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -190,10 +190,12 @@ _I2CIntNumberGet(uint32_t ui32Base)
 //! initial communication with the slave is done at either 100 Kbps or
 //! 400 Kbps.
 //!
-//! The peripheral clock is the same as the processor clock.  This value is
+//! The peripheral clock is the same as the processor clock.  The frequency of
-//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
+//! the system clock is the value returned by SysCtlClockGet() for TM4C123x
-//! constant and known (to save the code/execution overhead of a call to
+//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices,
-//! SysCtlClockGet()).
+//! or it can be explicitly hard coded if it is constant and known (to save the
+//! code/execution overhead of a call to SysCtlClockGet() or fetch of the 
+//! variable call holding the return value of SysCtlClockFreqSet()).
 //!
 //! \return None.
 //
@@ -1983,7 +1985,7 @@ I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length)
     //
     // Check the arguments.
     //
-    ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 255));
+    ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 256));
 
     //
     // Set the burst length.
@@ -2061,9 +2063,28 @@ I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config)
     ASSERT(_I2CBaseValid(ui32Base));
 
     //
-    // Configure the glitch filter field of MTPR.
+    // Configure the glitch filter field of MTPR if it is TM4C129
     //
-    HWREG(ui32Base + I2C_O_MTPR) |= ui32Config;
+    if(CLASS_IS_TM4C129)
+    {
+        HWREG(ui32Base + I2C_O_MTPR) |= ui32Config;
+    }
+
+    //
+    // Configure the glitch filter if it is TM4C123
+    //
+    if(CLASS_IS_TM4C123)
+    {
+        //
+        // Configure the glitch filter pulse width
+        //
+        HWREG(ui32Base + I2C_O_MCR2) |= (ui32Config >> 12);
+
+        //
+        // Enable the glitch filter by setting the GFE bit
+        //
+        HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_GFE;
+    }
 }
 
 //*****************************************************************************
@@ -2135,6 +2156,35 @@ I2CSlaveFIFODisable(uint32_t ui32Base)
     HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA;
 }
 
+//*****************************************************************************
+//
+//! Enables internal loopback mode for an I2C port.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function configures an I2C port in internal loopback mode to help with
+//! diagnostics and debug.  In this mode, the SDA and SCL signals from master
+//! and slave modules are internally connected.  This allows data to be
+//! transferred between the master and slave modules of the same I2C port,
+//! without having to go through I/O's.  I2CMasterDataPut(), I2CSlaveDataPut(),
+//! I2CMasterDataGet(),I2CSlaveDataGet() can be used along with this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2CLoopbackEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_I2CBaseValid(ui32Base));
+
+    //
+    // Write the loopback enable bit to the register.
+    //
+    HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_LPBK;
+}
+
 //*****************************************************************************
 //
 // Close the Doxygen group.

bsp/tm4c129x/libraries/driverlib/i2c.h

@@ -2,7 +2,7 @@
 //
 // i2c.h - Prototypes for the I2C Driver.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -281,7 +281,7 @@ extern "C"
 // Prototypes for the APIs.
 //
 //*****************************************************************************
-extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void));
+extern void I2CIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
 extern void I2CIntUnregister(uint32_t ui32Base);
 extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
 extern void I2CTxFIFOFlush(uint32_t ui32Base);
@@ -348,6 +348,7 @@ extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked);
 extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base,
                                       bool bMasked);
 extern uint32_t I2CSlaveStatus(uint32_t ui32Base);
+extern void I2CLoopbackEnable(uint32_t ui32Base);
 
 //*****************************************************************************
 //

bsp/tm4c129x/libraries/driverlib/interrupt.c

@@ -2,7 +2,7 @@
 //
 // interrupt.c - Driver for the NVIC Interrupt Controller.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/interrupt.h

@@ -2,7 +2,7 @@
 //
 // interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/lcd.c

@@ -2,7 +2,7 @@
 //
 // lcd.c - Defines and Macros for the LCD Controller module.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/lcd.h

@@ -2,7 +2,7 @@
 //
 // lcd.h - Defines and Macros for the LCD Controller module.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/mpu.c

@@ -2,7 +2,7 @@
 //
 // mpu.c - Driver for the Cortex-M3 memory protection unit (MPU).
 //
-// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2007-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/mpu.h

@@ -2,7 +2,7 @@
 //
 // mpu.h - Defines and Macros for the memory protection unit.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/onewire.c

@@ -2,7 +2,7 @@
 //
 // onewire.c - Driver for OneWire master module.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -454,10 +454,6 @@ _OneWireIntNumberGet(uint32_t ui32Base)
     //
     // Find the valid interrupt number for the 1-Wire module.
     //
-    if(CLASS_IS_TM4E111)
-    {
-        ui32Int = INT_ONEWIRE0_TM4E111;
-    }
     if(CLASS_IS_TM4C129)
     {
         ui32Int = INT_ONEWIRE0_TM4C129;

bsp/tm4c129x/libraries/driverlib/onewire.h

@@ -2,7 +2,7 @@
 //
 // onewire.h - Prototypes for the OneWire Driver.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/pin_map.h

@@ -2,7 +2,7 @@
 //
 // pin_map.h - Mapping of peripherals to pins for all parts.
 //
-// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2007-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -11207,6 +11207,466 @@
 
 #endif // PART_TM4C123GH6ZRB
 
+//*****************************************************************************
+//
+// TM4C123GH6ZXR Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_TM4C123GH6ZXR
+
+#define GPIO_PA0_U0RX           0x00000001
+#define GPIO_PA0_CAN1RX         0x00000008
+
+#define GPIO_PA1_U0TX           0x00000401
+#define GPIO_PA1_CAN1TX         0x00000408
+
+#define GPIO_PA2_SSI0CLK        0x00000802
+
+#define GPIO_PA3_SSI0FSS        0x00000C02
+
+#define GPIO_PA4_SSI0RX         0x00001002
+
+#define GPIO_PA5_SSI0TX         0x00001402
+
+#define GPIO_PA6_I2C1SCL        0x00001803
+#define GPIO_PA6_M1PWM2         0x00001805
+
+#define GPIO_PA7_I2C1SDA        0x00001C03
+#define GPIO_PA7_M1PWM3         0x00001C05
+
+#define GPIO_PB0_U1RX           0x00010001
+#define GPIO_PB0_T2CCP0         0x00010007
+
+#define GPIO_PB1_U1TX           0x00010401
+#define GPIO_PB1_T2CCP1         0x00010407
+
+#define GPIO_PB2_I2C0SCL        0x00010803
+#define GPIO_PB2_T3CCP0         0x00010807
+
+#define GPIO_PB3_I2C0SDA        0x00010C03
+#define GPIO_PB3_T3CCP1         0x00010C07
+
+#define GPIO_PB4_SSI2CLK        0x00011002
+#define GPIO_PB4_M0PWM2         0x00011004
+#define GPIO_PB4_T1CCP0         0x00011007
+#define GPIO_PB4_CAN0RX         0x00011008
+
+#define GPIO_PB5_SSI2FSS        0x00011402
+#define GPIO_PB5_M0PWM3         0x00011404
+#define GPIO_PB5_T1CCP1         0x00011407
+#define GPIO_PB5_CAN0TX         0x00011408
+
+#define GPIO_PB6_SSI2RX         0x00011802
+#define GPIO_PB6_I2C5SCL        0x00011803
+#define GPIO_PB6_M0PWM0         0x00011804
+#define GPIO_PB6_T0CCP0         0x00011807
+
+#define GPIO_PB7_SSI2TX         0x00011C02
+#define GPIO_PB7_I2C5SDA        0x00011C03
+#define GPIO_PB7_M0PWM1         0x00011C04
+#define GPIO_PB7_T0CCP1         0x00011C07
+
+#define GPIO_PC0_TCK            0x00020001
+#define GPIO_PC0_SWCLK          0x00020001
+#define GPIO_PC0_T4CCP0         0x00020007
+
+#define GPIO_PC1_TMS            0x00020401
+#define GPIO_PC1_SWDIO          0x00020401
+#define GPIO_PC1_T4CCP1         0x00020407
+
+#define GPIO_PC2_TDI            0x00020801
+#define GPIO_PC2_T5CCP0         0x00020807
+
+#define GPIO_PC3_SWO            0x00020C01
+#define GPIO_PC3_TDO            0x00020C01
+#define GPIO_PC3_T5CCP1         0x00020C07
+
+#define GPIO_PC4_U4RX           0x00021001
+#define GPIO_PC4_U1RX           0x00021002
+#define GPIO_PC4_M0PWM6         0x00021004
+#define GPIO_PC4_IDX1           0x00021006
+#define GPIO_PC4_WT0CCP0        0x00021007
+#define GPIO_PC4_U1RTS          0x00021008
+
+#define GPIO_PC5_U4TX           0x00021401
+#define GPIO_PC5_U1TX           0x00021402
+#define GPIO_PC5_M0PWM7         0x00021404
+#define GPIO_PC5_PHA1           0x00021406
+#define GPIO_PC5_WT0CCP1        0x00021407
+#define GPIO_PC5_U1CTS          0x00021408
+
+#define GPIO_PC6_U3RX           0x00021801
+#define GPIO_PC6_PHB1           0x00021806
+#define GPIO_PC6_WT1CCP0        0x00021807
+#define GPIO_PC6_USB0EPEN       0x00021808
+
+#define GPIO_PC7_U3TX           0x00021C01
+#define GPIO_PC7_WT1CCP1        0x00021C07
+#define GPIO_PC7_USB0PFLT       0x00021C08
+
+#define GPIO_PD0_SSI3CLK        0x00030001
+#define GPIO_PD0_SSI1CLK        0x00030002
+#define GPIO_PD0_I2C3SCL        0x00030003
+#define GPIO_PD0_M0PWM6         0x00030004
+#define GPIO_PD0_M1PWM0         0x00030005
+#define GPIO_PD0_WT2CCP0        0x00030007
+
+#define GPIO_PD1_SSI3FSS        0x00030401
+#define GPIO_PD1_SSI1FSS        0x00030402
+#define GPIO_PD1_I2C3SDA        0x00030403
+#define GPIO_PD1_M0PWM7         0x00030404
+#define GPIO_PD1_M1PWM1         0x00030405
+#define GPIO_PD1_WT2CCP1        0x00030407
+
+#define GPIO_PD2_SSI3RX         0x00030801
+#define GPIO_PD2_SSI1RX         0x00030802
+#define GPIO_PD2_M0FAULT0       0x00030804
+#define GPIO_PD2_WT3CCP0        0x00030807
+#define GPIO_PD2_USB0EPEN       0x00030808
+
+#define GPIO_PD3_SSI3TX         0x00030C01
+#define GPIO_PD3_SSI1TX         0x00030C02
+#define GPIO_PD3_IDX0           0x00030C06
+#define GPIO_PD3_WT3CCP1        0x00030C07
+#define GPIO_PD3_USB0PFLT       0x00030C08
+
+#define GPIO_PD4_U6RX           0x00031001
+#define GPIO_PD4_WT4CCP0        0x00031007
+
+#define GPIO_PD5_U6TX           0x00031401
+#define GPIO_PD5_WT4CCP1        0x00031407
+
+#define GPIO_PD6_U2RX           0x00031801
+#define GPIO_PD6_M0FAULT0       0x00031804
+#define GPIO_PD6_PHA0           0x00031806
+#define GPIO_PD6_WT5CCP0        0x00031807
+
+#define GPIO_PD7_U2TX           0x00031C01
+#define GPIO_PD7_M0FAULT1       0x00031C04
+#define GPIO_PD7_PHB0           0x00031C06
+#define GPIO_PD7_WT5CCP1        0x00031C07
+#define GPIO_PD7_NMI            0x00031C08
+
+#define GPIO_PE0_U7RX           0x00040001
+
+#define GPIO_PE1_U7TX           0x00040401
+
+#define GPIO_PE4_U5RX           0x00041001
+#define GPIO_PE4_I2C2SCL        0x00041003
+#define GPIO_PE4_M0PWM4         0x00041004
+#define GPIO_PE4_M1PWM2         0x00041005
+#define GPIO_PE4_CAN0RX         0x00041008
+
+#define GPIO_PE5_U5TX           0x00041401
+#define GPIO_PE5_I2C2SDA        0x00041403
+#define GPIO_PE5_M0PWM5         0x00041404
+#define GPIO_PE5_M1PWM3         0x00041405
+#define GPIO_PE5_CAN0TX         0x00041408
+
+#define GPIO_PE6_CAN1RX         0x00041808
+
+#define GPIO_PE7_U1RI           0x00041C01
+#define GPIO_PE7_CAN1TX         0x00041C08
+
+#define GPIO_PF0_U1RTS          0x00050001
+#define GPIO_PF0_SSI1RX         0x00050002
+#define GPIO_PF0_CAN0RX         0x00050003
+#define GPIO_PF0_M1PWM4         0x00050005
+#define GPIO_PF0_PHA0           0x00050006
+#define GPIO_PF0_T0CCP0         0x00050007
+#define GPIO_PF0_NMI            0x00050008
+#define GPIO_PF0_C0O            0x00050009
+#define GPIO_PF0_TRD2           0x0005000E
+
+#define GPIO_PF1_U1CTS          0x00050401
+#define GPIO_PF1_SSI1TX         0x00050402
+#define GPIO_PF1_M1PWM5         0x00050405
+#define GPIO_PF1_PHB0           0x00050406
+#define GPIO_PF1_T0CCP1         0x00050407
+#define GPIO_PF1_C1O            0x00050409
+#define GPIO_PF1_TRD1           0x0005040E
+
+#define GPIO_PF2_U1DCD          0x00050801
+#define GPIO_PF2_SSI1CLK        0x00050802
+#define GPIO_PF2_M0FAULT0       0x00050804
+#define GPIO_PF2_M1PWM6         0x00050805
+#define GPIO_PF2_T1CCP0         0x00050807
+#define GPIO_PF2_C2O            0x00050809
+#define GPIO_PF2_TRD0           0x0005080E
+
+#define GPIO_PF3_U1DSR          0x00050C01
+#define GPIO_PF3_SSI1FSS        0x00050C02
+#define GPIO_PF3_CAN0TX         0x00050C03
+#define GPIO_PF3_M0FAULT1       0x00050C04
+#define GPIO_PF3_M1PWM7         0x00050C05
+#define GPIO_PF3_T1CCP1         0x00050C07
+#define GPIO_PF3_TRCLK          0x00050C0E
+
+#define GPIO_PF4_U1DTR          0x00051001
+#define GPIO_PF4_M0FAULT2       0x00051004
+#define GPIO_PF4_M1FAULT0       0x00051005
+#define GPIO_PF4_IDX0           0x00051006
+#define GPIO_PF4_T2CCP0         0x00051007
+#define GPIO_PF4_USB0EPEN       0x00051008
+#define GPIO_PF4_TRD3           0x0005100E
+
+#define GPIO_PF5_M0FAULT3       0x00051404
+#define GPIO_PF5_T2CCP1         0x00051407
+#define GPIO_PF5_USB0PFLT       0x00051408
+
+#define GPIO_PF6_I2C2SCL        0x00051803
+#define GPIO_PF6_T3CCP0         0x00051807
+
+#define GPIO_PF7_I2C2SDA        0x00051C03
+#define GPIO_PF7_M1FAULT0       0x00051C05
+#define GPIO_PF7_T3CCP1         0x00051C07
+
+#define GPIO_PG0_I2C3SCL        0x00060003
+#define GPIO_PG0_M1FAULT1       0x00060005
+#define GPIO_PG0_PHA1           0x00060006
+#define GPIO_PG0_T4CCP0         0x00060007
+
+#define GPIO_PG1_I2C3SDA        0x00060403
+#define GPIO_PG1_M1FAULT2       0x00060405
+#define GPIO_PG1_PHB1           0x00060406
+#define GPIO_PG1_T4CCP1         0x00060407
+
+#define GPIO_PG2_I2C4SCL        0x00060803
+#define GPIO_PG2_M0FAULT1       0x00060804
+#define GPIO_PG2_M1PWM0         0x00060805
+#define GPIO_PG2_T5CCP0         0x00060807
+
+#define GPIO_PG3_I2C4SDA        0x00060C03
+#define GPIO_PG3_M0FAULT2       0x00060C04
+#define GPIO_PG3_M1PWM1         0x00060C05
+#define GPIO_PG3_PHA1           0x00060C06
+#define GPIO_PG3_T5CCP1         0x00060C07
+
+#define GPIO_PG4_U2RX           0x00061001
+#define GPIO_PG4_I2C1SCL        0x00061003
+#define GPIO_PG4_M0PWM4         0x00061004
+#define GPIO_PG4_M1PWM2         0x00061005
+#define GPIO_PG4_PHB1           0x00061006
+#define GPIO_PG4_WT0CCP0        0x00061007
+#define GPIO_PG4_USB0EPEN       0x00061008
+
+#define GPIO_PG5_U2TX           0x00061401
+#define GPIO_PG5_I2C1SDA        0x00061403
+#define GPIO_PG5_M0PWM5         0x00061404
+#define GPIO_PG5_M1PWM3         0x00061405
+#define GPIO_PG5_IDX1           0x00061406
+#define GPIO_PG5_WT0CCP1        0x00061407
+#define GPIO_PG5_USB0PFLT       0x00061408
+
+#define GPIO_PG6_I2C5SCL        0x00061803
+#define GPIO_PG6_M0PWM6         0x00061804
+#define GPIO_PG6_WT1CCP0        0x00061807
+
+#define GPIO_PG7_I2C5SDA        0x00061C03
+#define GPIO_PG7_M0PWM7         0x00061C04
+#define GPIO_PG7_IDX1           0x00061C05
+#define GPIO_PG7_WT1CCP1        0x00061C07
+
+#define GPIO_PH0_SSI3CLK        0x00070002
+#define GPIO_PH0_M0PWM0         0x00070004
+#define GPIO_PH0_M0FAULT0       0x00070006
+#define GPIO_PH0_WT2CCP0        0x00070007
+
+#define GPIO_PH1_SSI3FSS        0x00070402
+#define GPIO_PH1_M0PWM1         0x00070404
+#define GPIO_PH1_IDX0           0x00070405
+#define GPIO_PH1_M0FAULT1       0x00070406
+#define GPIO_PH1_WT2CCP1        0x00070407
+
+#define GPIO_PH2_SSI3RX         0x00070802
+#define GPIO_PH2_M0PWM2         0x00070804
+#define GPIO_PH2_M0FAULT2       0x00070806
+#define GPIO_PH2_WT5CCP0        0x00070807
+
+#define GPIO_PH3_SSI3TX         0x00070C02
+#define GPIO_PH3_M0PWM3         0x00070C04
+#define GPIO_PH3_M0FAULT3       0x00070C06
+#define GPIO_PH3_WT5CCP1        0x00070C07
+
+#define GPIO_PH4_SSI2CLK        0x00071002
+#define GPIO_PH4_M0PWM4         0x00071004
+#define GPIO_PH4_PHA0           0x00071005
+#define GPIO_PH4_WT3CCP0        0x00071007
+
+#define GPIO_PH5_SSI2FSS        0x00071402
+#define GPIO_PH5_M0PWM5         0x00071404
+#define GPIO_PH5_PHB0           0x00071405
+#define GPIO_PH5_WT3CCP1        0x00071407
+
+#define GPIO_PH6_SSI2RX         0x00071802
+#define GPIO_PH6_M0PWM6         0x00071804
+#define GPIO_PH6_WT4CCP0        0x00071807
+
+#define GPIO_PH7_SSI2TX         0x00071C02
+#define GPIO_PH7_M0PWM7         0x00071C04
+#define GPIO_PH7_WT4CCP1        0x00071C07
+
+#define GPIO_PJ0_U4RX           0x00080001
+#define GPIO_PJ0_T1CCP0         0x00080007
+
+#define GPIO_PJ1_U4TX           0x00080401
+#define GPIO_PJ1_T1CCP1         0x00080407
+
+#define GPIO_PJ2_U5RX           0x00080801
+#define GPIO_PJ2_IDX0           0x00080805
+#define GPIO_PJ2_T2CCP0         0x00080807
+
+#define GPIO_PJ3_U5TX           0x00080C01
+#define GPIO_PJ3_T2CCP1         0x00080C07
+
+#define GPIO_PJ4_U6RX           0x00081001
+#define GPIO_PJ4_T3CCP0         0x00081007
+
+#define GPIO_PJ5_U6TX           0x00081401
+#define GPIO_PJ5_T3CCP1         0x00081407
+
+#define GPIO_PK0_SSI3CLK        0x00090002
+#define GPIO_PK0_M1FAULT0       0x00090006
+
+#define GPIO_PK1_SSI3FSS        0x00090402
+#define GPIO_PK1_M1FAULT1       0x00090406
+
+#define GPIO_PK2_SSI3RX         0x00090802
+#define GPIO_PK2_M1FAULT2       0x00090806
+
+#define GPIO_PK3_SSI3TX         0x00090C02
+#define GPIO_PK3_M1FAULT3       0x00090C06
+
+#define GPIO_PK4_U7RX           0x00091001
+#define GPIO_PK4_M0FAULT0       0x00091006
+#define GPIO_PK4_RTCCLK         0x00091007
+#define GPIO_PK4_C0O            0x00091008
+
+#define GPIO_PK5_U7TX           0x00091401
+#define GPIO_PK5_M0FAULT1       0x00091406
+#define GPIO_PK5_C1O            0x00091408
+
+#define GPIO_PK6_M0FAULT2       0x00091806
+#define GPIO_PK6_WT1CCP0        0x00091807
+#define GPIO_PK6_C2O            0x00091808
+
+#define GPIO_PK7_M0FAULT3       0x00091C06
+#define GPIO_PK7_WT1CCP1        0x00091C07
+
+#define GPIO_PL0_T0CCP0         0x000A0007
+#define GPIO_PL0_WT0CCP0        0x000A0008
+
+#define GPIO_PL1_T0CCP1         0x000A0407
+#define GPIO_PL1_WT0CCP1        0x000A0408
+
+#define GPIO_PL2_T1CCP0         0x000A0807
+#define GPIO_PL2_WT1CCP0        0x000A0808
+
+#define GPIO_PL3_T1CCP1         0x000A0C07
+#define GPIO_PL3_WT1CCP1        0x000A0C08
+
+#define GPIO_PL4_T2CCP0         0x000A1007
+#define GPIO_PL4_WT2CCP0        0x000A1008
+
+#define GPIO_PL5_T2CCP1         0x000A1407
+#define GPIO_PL5_WT2CCP1        0x000A1408
+
+#define GPIO_PL6_T3CCP0         0x000A1807
+#define GPIO_PL6_WT3CCP0        0x000A1808
+
+#define GPIO_PL7_T3CCP1         0x000A1C07
+#define GPIO_PL7_WT3CCP1        0x000A1C08
+
+#define GPIO_PM0_T4CCP0         0x000B0007
+#define GPIO_PM0_WT4CCP0        0x000B0008
+
+#define GPIO_PM1_T4CCP1         0x000B0407
+#define GPIO_PM1_WT4CCP1        0x000B0408
+
+#define GPIO_PM2_T5CCP0         0x000B0807
+#define GPIO_PM2_WT5CCP0        0x000B0808
+
+#define GPIO_PM3_T5CCP1         0x000B0C07
+#define GPIO_PM3_WT5CCP1        0x000B0C08
+
+#define GPIO_PM6_M0PWM4         0x000B1802
+#define GPIO_PM6_WT0CCP0        0x000B1807
+
+#define GPIO_PM7_M0PWM5         0x000B1C02
+#define GPIO_PM7_WT0CCP1        0x000B1C07
+
+#define GPIO_PN0_CAN0RX         0x000C0001
+
+#define GPIO_PN1_CAN0TX         0x000C0401
+
+#define GPIO_PN2_M0PWM6         0x000C0802
+#define GPIO_PN2_WT2CCP0        0x000C0807
+
+#define GPIO_PN3_M0PWM7         0x000C0C02
+#define GPIO_PN3_WT2CCP1        0x000C0C07
+
+#define GPIO_PN4_M1PWM4         0x000C1002
+#define GPIO_PN4_WT3CCP0        0x000C1007
+
+#define GPIO_PN5_M1PWM5         0x000C1402
+#define GPIO_PN5_WT3CCP1        0x000C1407
+
+#define GPIO_PN6_M1PWM6         0x000C1802
+#define GPIO_PN6_WT4CCP0        0x000C1807
+
+#define GPIO_PN7_M1PWM7         0x000C1C02
+#define GPIO_PN7_WT4CCP1        0x000C1C07
+
+#define GPIO_PP0_M0PWM0         0x000D0001
+#define GPIO_PP0_T4CCP0         0x000D0007
+
+#define GPIO_PP1_M0PWM1         0x000D0401
+#define GPIO_PP1_T4CCP1         0x000D0407
+
+#define GPIO_PP2_M0PWM2         0x000D0801
+#define GPIO_PP2_T5CCP0         0x000D0807
+
+#define GPIO_PP3_M0PWM3         0x000D0C01
+#define GPIO_PP3_T5CCP1         0x000D0C07
+
+#define GPIO_PP4_M0PWM4         0x000D1001
+#define GPIO_PP4_WT0CCP0        0x000D1007
+
+#define GPIO_PP5_M0PWM5         0x000D1401
+#define GPIO_PP5_WT0CCP1        0x000D1407
+
+#define GPIO_PP6_M0PWM6         0x000D1801
+#define GPIO_PP6_WT1CCP0        0x000D1807
+
+#define GPIO_PP7_M0PWM7         0x000D1C01
+#define GPIO_PP7_WT1CCP1        0x000D1C07
+
+#define GPIO_PQ0_M1PWM0         0x000E0001
+#define GPIO_PQ0_WT2CCP0        0x000E0007
+
+#define GPIO_PQ1_M1PWM1         0x000E0401
+#define GPIO_PQ1_WT2CCP1        0x000E0407
+
+#define GPIO_PQ2_M1PWM2         0x000E0801
+#define GPIO_PQ2_WT3CCP0        0x000E0807
+
+#define GPIO_PQ3_M1PWM3         0x000E0C01
+#define GPIO_PQ3_WT3CCP1        0x000E0C07
+
+#define GPIO_PQ4_M1PWM4         0x000E1001
+#define GPIO_PQ4_WT4CCP0        0x000E1007
+
+#define GPIO_PQ5_M1PWM5         0x000E1401
+#define GPIO_PQ5_WT4CCP1        0x000E1407
+
+#define GPIO_PQ6_M1PWM6         0x000E1801
+#define GPIO_PQ6_WT5CCP0        0x000E1807
+
+#define GPIO_PQ7_M1PWM7         0x000E1C01
+#define GPIO_PQ7_WT5CCP1        0x000E1C07
+
+#endif // PART_TM4C123GH6ZXR
+
 //*****************************************************************************
 //
 // TM4C1290NCPDT Port/Pin Mapping Definitions

bsp/tm4c129x/libraries/driverlib/pwm.c

@@ -2,7 +2,7 @@
 //
 // pwm.c - API for the PWM modules
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/pwm.h

@@ -2,7 +2,7 @@
 //
 // pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/qei.c

@@ -2,7 +2,7 @@
 //
 // qei.c - Driver for the Quadrature Encoder with Index.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -274,6 +274,96 @@ QEIErrorGet(uint32_t ui32Base)
     return((HWREG(ui32Base + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false);
 }
 
+//*****************************************************************************
+//
+//! Enables the input filter.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//!
+//! This function enables operation of the input filter in the quadrature
+//! encoder module.  The module must be configured before input filter is
+//! enabled.
+//!
+//! \sa QEIFilterConfigure() and QEIEnable()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIFilterEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Enable the input filter.
+    //
+    HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_FILTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the input filter.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//!
+//! This function disables operation of the input filter in the quadrature
+//! encoder module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIFilterDisable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+
+    //
+    // Disable the input filter.
+    //
+    HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_FILTEN);
+}
+
+//*****************************************************************************
+//
+//! Configures the input filter.
+//!
+//! \param ui32Base is the base address of the quadrature encoder module.
+//! \param ui32FiltCnt specifies the filter count applied to the input quadrature
+//! signal before it is counted; can be one of \b QEI_FILTCNT_2,
+//! \b QEI_FILTCNT_3, \b QEI_FILTCNT_4, \b QEI_FILTCNT_5, \b QEI_FILTCNT_6,
+//! \b QEI_FILTCNT_7, \b QEI_FILTCNT_8, \b QEI_FILTCNT_9, \b QEI_FILTCNT_10,
+//! \b QEI_FILTCNT_11, \b QEI_FILTCNT_12, \b QEI_FILTCNT_13, \b QEI_FILTCNT_14,
+//! \b QEI_FILTCNT_15, \b QEI_FILTCNT_16 or \b QEI_FILTCNT_17
+//!
+//! This function configures the operation of the input filter prescale count.
+//! as specified by \e ui32FiltCnt before the input signals are sent to the
+//! quadrature encoder module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIFilterConfigure(uint32_t ui32Base, uint32_t ui32FiltCnt)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE));
+    ASSERT(!(ui32FiltCnt & ~(QEI_CTL_FILTCNT_M)));
+
+    //
+    // Set the input filter prescale count.
+    //
+    HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) &
+                                    ~(QEI_CTL_FILTCNT_M)) | ui32FiltCnt);
+}
+
 //*****************************************************************************
 //
 //! Enables the velocity capture.

bsp/tm4c129x/libraries/driverlib/qei.h

@@ -2,7 +2,7 @@
 //
 // qei.h - Prototypes for the Quadrature Encoder Driver.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -65,6 +65,29 @@ extern "C"
 #define QEI_CONFIG_NO_SWAP      0x00000000  // Do not swap ChA and ChB
 #define QEI_CONFIG_SWAP         0x00000002  // Swap ChA and ChB
 
+//*****************************************************************************
+//
+// Values that can be passed to QEIFilterConfigure as the ui32PreDiv
+// parameter.
+//
+//*****************************************************************************
+#define QEI_FILTCNT_2           0x00000000  // Filter Count of 2 System Clocks
+#define QEI_FILTCNT_3           0x00010000  // Filter Count of 3 System Clocks
+#define QEI_FILTCNT_4           0x00020000  // Filter Count of 4 System Clocks
+#define QEI_FILTCNT_5           0x00030000  // Filter Count of 5 System Clocks
+#define QEI_FILTCNT_6           0x00040000  // Filter Count of 6 System Clocks
+#define QEI_FILTCNT_7           0x00050000  // Filter Count of 7 System Clocks
+#define QEI_FILTCNT_8           0x00060000  // Filter Count of 8 System Clocks
+#define QEI_FILTCNT_9           0x00070000  // Filter Count of 9 System Clocks
+#define QEI_FILTCNT_10          0x00080000  // Filter Count of 10 System Clocks
+#define QEI_FILTCNT_11          0x00090000  // Filter Count of 11 System Clocks
+#define QEI_FILTCNT_12          0x000A0000  // Filter Count of 12 System Clocks
+#define QEI_FILTCNT_13          0x000B0000  // Filter Count of 13 System Clocks
+#define QEI_FILTCNT_14          0x000C0000  // Filter Count of 14 System Clocks
+#define QEI_FILTCNT_15          0x000D0000  // Filter Count of 15 System Clocks
+#define QEI_FILTCNT_16          0x000E0000  // Filter Count of 16 System Clocks
+#define QEI_FILTCNT_17          0x000F0000  // Filter Count of 17 System Clocks
+
 //*****************************************************************************
 //
 // Values that can be passed to QEIVelocityConfigure as the ui32PreDiv
@@ -104,6 +127,9 @@ extern uint32_t QEIPositionGet(uint32_t ui32Base);
 extern void QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position);
 extern int32_t QEIDirectionGet(uint32_t ui32Base);
 extern bool QEIErrorGet(uint32_t ui32Base);
+extern void QEIFilterEnable(uint32_t ui32Base);
+extern void QEIFilterDisable(uint32_t ui32Base);
+extern void QEIFilterConfigure(uint32_t ui32Base, uint32_t ui32FiltCnt);
 extern void QEIVelocityEnable(uint32_t ui32Base);
 extern void QEIVelocityDisable(uint32_t ui32Base);
 extern void QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv,

bsp/tm4c129x/libraries/driverlib/readme.txt

@@ -2,7 +2,7 @@ This project will build the TivaWare Peripheral Driver Library.
 
 -------------------------------------------------------------------------------
 
-Copyright (c) 2006-2014 Texas Instruments Incorporated.  All rights reserved.
+Copyright (c) 2006-2017 Texas Instruments Incorporated.  All rights reserved.
 Software License Agreement
 
   Redistribution and use in source and binary forms, with or without
@@ -33,4 +33,4 @@ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.

bsp/tm4c129x/libraries/driverlib/rom_map.h

@@ -3,7 +3,7 @@
 // rom_map.h - Macros to facilitate calling functions in the ROM when they are
 //             available and in flash otherwise.
 //
-// Copyright (c) 2008-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2008-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -34,7 +34,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -5854,13 +5854,6 @@
 #define MAP_USBEndpointDataAvail                                              \
         USBEndpointDataAvail
 #endif
-#ifdef ROM_USBOTGHostRequest
-#define MAP_USBOTGHostRequest                                                 \
-        ROM_USBOTGHostRequest
-#else
-#define MAP_USBOTGHostRequest                                                 \
-        USBOTGHostRequest
-#endif
 #ifdef ROM_USBModeGet
 #define MAP_USBModeGet                                                        \
         ROM_USBModeGet

bsp/tm4c129x/libraries/driverlib/rtos_bindings.h

@@ -3,7 +3,7 @@
 // rtos_bindings.h - Macros intended to aid porting of TivaWare modules
 //                   for use with an RTOS.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -34,7 +34,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/shamd5.c

@@ -2,7 +2,7 @@
 //
 // shamd5.c - Driver for the SHA/MD5 module.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/shamd5.h

@@ -2,7 +2,7 @@
 //
 // shamd5.h - Defines and Macros for the SHA/MD5.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/ssi.c

@@ -2,7 +2,7 @@
 //
 // ssi.c - Driver for Synchronous Serial Interface.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -209,10 +209,12 @@ _SSIIntNumberGet(uint32_t ui32Base)
 //! The \e ui32DataWidth parameter defines the width of the data transfers and
 //! can be a value between 4 and 16, inclusive.
 //!
-//! The peripheral clock is the same as the processor clock.  This value is
+//! The peripheral clock is the same as the processor clock.  The frequency of
-//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
+//! the system clock is the value returned by SysCtlClockGet() for TM4C123x
-//! constant and known (to save the code/execution overhead of a call to
+//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices,
-//! SysCtlClockGet()).
+//! or it can be explicitly hard coded if it is constant and known (to save the
+//! code/execution overhead of a call to SysCtlClockGet() or fetch of the 
+//! variable call holding the return value of SysCtlClockFreqSet()).
 //!
 //! \return None.
 //
@@ -239,8 +241,7 @@ SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
            (ui32Protocol == SSI_FRF_TI) ||
            (ui32Protocol == SSI_FRF_NMW));
     ASSERT((ui32Mode == SSI_MODE_MASTER) ||
-           (ui32Mode == SSI_MODE_SLAVE) ||
+           (ui32Mode == SSI_MODE_SLAVE));
-           (ui32Mode == SSI_MODE_SLAVE_OD));
     ASSERT(((ui32Mode == SSI_MODE_MASTER) &&
             (ui32BitRate <= (ui32SSIClk / 2))) ||
            ((ui32Mode != SSI_MODE_MASTER) &&
@@ -251,8 +252,7 @@ SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
     //
     // Set the mode.
     //
-    ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;
+    ui32RegVal = (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
-    ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
     HWREG(ui32Base + SSI_O_CR1) = ui32RegVal;
 
     //

bsp/tm4c129x/libraries/driverlib/ssi.h

@@ -2,7 +2,7 @@
 //
 // ssi.h - Prototypes for the Synchronous Serial Interface Driver.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/sw_crc.c

@@ -2,7 +2,7 @@
 //
 // sw_crc.c - Software CRC functions.
 //
-// Copyright (c) 2010-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2010-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/sw_crc.h

@@ -2,7 +2,7 @@
 //
 // sw_crc.h - Prototypes for the software CRC functions.
 //
-// Copyright (c) 2010-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2010-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/sysctl.c

@@ -2,7 +2,7 @@
 //
 // sysctl.c - Driver for the system controller.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -128,59 +128,61 @@ static const uint32_t g_pui32Xtals[] =
         ((uint32_t)mi | (uint32_t)(mf << SYSCTL_PLLFREQ0_MFRAC_S))
 #define PLL_N_TO_REG(n)                                                       \
         ((uint32_t)(n - 1) << SYSCTL_PLLFREQ1_N_S)
+#define PLL_Q_TO_REG(q)                                                       \
+        ((uint32_t)(q - 1) << SYSCTL_PLLFREQ1_Q_S)
 
 //*****************************************************************************
 //
 // Look up of the values that go into the PLLFREQ0 and PLLFREQ1 registers.
 //
 //*****************************************************************************
-static const uint32_t g_pppui32XTALtoVCO[MAX_VCO_ENTRIES][MAX_XTAL_ENTRIES][2] =
+static const uint32_t g_pppui32XTALtoVCO[MAX_VCO_ENTRIES][MAX_XTAL_ENTRIES][3] =
 {
     {
         //
         // VCO 320 MHz
         //
-        { PLL_M_TO_REG(64, 0),   PLL_N_TO_REG(1) },     // 5 MHz
+        { PLL_M_TO_REG(64, 0),   PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 5 MHz
-        { PLL_M_TO_REG(62, 512), PLL_N_TO_REG(1) },     // 5.12 MHz
+        { PLL_M_TO_REG(62, 512), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 5.12 MHz
-        { PLL_M_TO_REG(160, 0),  PLL_N_TO_REG(3) },     // 6 MHz
+        { PLL_M_TO_REG(160, 0),  PLL_N_TO_REG(3), PLL_Q_TO_REG(2) },     // 6 MHz
-        { PLL_M_TO_REG(52, 85),  PLL_N_TO_REG(1) },     // 6.144 MHz
+        { PLL_M_TO_REG(52, 85),  PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 6.144 MHz
-        { PLL_M_TO_REG(43, 412), PLL_N_TO_REG(1) },     // 7.3728 MHz
+        { PLL_M_TO_REG(43, 412), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 7.3728 MHz
-        { PLL_M_TO_REG(40, 0),   PLL_N_TO_REG(1) },     // 8 MHz
+        { PLL_M_TO_REG(40, 0),   PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 8 MHz
-        { PLL_M_TO_REG(39, 64),  PLL_N_TO_REG(1) },     // 8.192 MHz
+        { PLL_M_TO_REG(39, 64),  PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 8.192 MHz
-        { PLL_M_TO_REG(32, 0),   PLL_N_TO_REG(1) },     // 10 MHz
+        { PLL_M_TO_REG(32, 0),   PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 10 MHz
-        { PLL_M_TO_REG(80, 0),   PLL_N_TO_REG(3) },     // 12 MHz
+        { PLL_M_TO_REG(80, 0),   PLL_N_TO_REG(3), PLL_Q_TO_REG(2) },     // 12 MHz
-        { PLL_M_TO_REG(26, 43),  PLL_N_TO_REG(1) },     // 12.288 MHz
+        { PLL_M_TO_REG(26, 43),  PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 12.288 MHz
-        { PLL_M_TO_REG(23, 613), PLL_N_TO_REG(1) },     // 13.56 MHz
+        { PLL_M_TO_REG(23, 613), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 13.56 MHz
-        { PLL_M_TO_REG(22, 358), PLL_N_TO_REG(1) },     // 14.318180 MHz
+        { PLL_M_TO_REG(22, 358), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 14.318180 MHz
-        { PLL_M_TO_REG(20, 0),   PLL_N_TO_REG(1) },     // 16 MHz
+        { PLL_M_TO_REG(20, 0),   PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 16 MHz
-        { PLL_M_TO_REG(19, 544), PLL_N_TO_REG(1) },     // 16.384 MHz
+        { PLL_M_TO_REG(19, 544), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 16.384 MHz
-        { PLL_M_TO_REG(160, 0),  PLL_N_TO_REG(9) },     // 18 MHz
+        { PLL_M_TO_REG(160, 0),  PLL_N_TO_REG(9), PLL_Q_TO_REG(2) },     // 18 MHz
-        { PLL_M_TO_REG(16, 0),   PLL_N_TO_REG(1) },     // 20 MHz
+        { PLL_M_TO_REG(16, 0),   PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 20 MHz
-        { PLL_M_TO_REG(40, 0),   PLL_N_TO_REG(3) },     // 24 MHz
+        { PLL_M_TO_REG(40, 0),   PLL_N_TO_REG(3), PLL_Q_TO_REG(2) },     // 24 MHz
-        { PLL_M_TO_REG(64, 0),   PLL_N_TO_REG(5) },     // 25 MHz
+        { PLL_M_TO_REG(64, 0),   PLL_N_TO_REG(5), PLL_Q_TO_REG(2) },     // 25 MHz
     },
     {
         //
         // VCO 480 MHz
         //
-        { PLL_M_TO_REG(96, 0),   PLL_N_TO_REG(1) },     // 5 MHz
+        { PLL_M_TO_REG(96, 0),   PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 5 MHz
-        { PLL_M_TO_REG(93, 768), PLL_N_TO_REG(1) },     // 5.12 MHz
+        { PLL_M_TO_REG(93, 768), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 5.12 MHz
-        { PLL_M_TO_REG(80, 0),   PLL_N_TO_REG(1) },     // 6 MHz
+        { PLL_M_TO_REG(80, 0),   PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 6 MHz
-        { PLL_M_TO_REG(78, 128), PLL_N_TO_REG(1) },     // 6.144 MHz
+        { PLL_M_TO_REG(78, 128), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 6.144 MHz
-        { PLL_M_TO_REG(65, 107), PLL_N_TO_REG(1) },     // 7.3728 MHz
+        { PLL_M_TO_REG(65, 107), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 7.3728 MHz
-        { PLL_M_TO_REG(60, 0),   PLL_N_TO_REG(1) },     // 8 MHz
+        { PLL_M_TO_REG(60, 0),   PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 8 MHz
-        { PLL_M_TO_REG(58, 608), PLL_N_TO_REG(1) },     // 8.192 MHz
+        { PLL_M_TO_REG(58, 608), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 8.192 MHz
-        { PLL_M_TO_REG(48, 0),   PLL_N_TO_REG(1) },     // 10 MHz
+        { PLL_M_TO_REG(48, 0),   PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 10 MHz
-        { PLL_M_TO_REG(40, 0),   PLL_N_TO_REG(1) },     // 12 MHz
+        { PLL_M_TO_REG(40, 0),   PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 12 MHz
-        { PLL_M_TO_REG(39, 64),  PLL_N_TO_REG(1) },     // 12.288 MHz
+        { PLL_M_TO_REG(39, 64),  PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 12.288 MHz
-        { PLL_M_TO_REG(35, 408), PLL_N_TO_REG(1) },     // 13.56 MHz
+        { PLL_M_TO_REG(35, 408), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 13.56 MHz
-        { PLL_M_TO_REG(33, 536), PLL_N_TO_REG(1) },     // 14.318180 MHz
+        { PLL_M_TO_REG(33, 536), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 14.318180 MHz
-        { PLL_M_TO_REG(30, 0),   PLL_N_TO_REG(1) },     // 16 MHz
+        { PLL_M_TO_REG(30, 0),   PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 16 MHz
-        { PLL_M_TO_REG(29, 304), PLL_N_TO_REG(1) },     // 16.384 MHz
+        { PLL_M_TO_REG(29, 304), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 16.384 MHz
-        { PLL_M_TO_REG(80, 0),   PLL_N_TO_REG(3) },     // 18 MHz
+        { PLL_M_TO_REG(80, 0),   PLL_N_TO_REG(3), PLL_Q_TO_REG(2) },     // 18 MHz
-        { PLL_M_TO_REG(24, 0),   PLL_N_TO_REG(1) },     // 20 MHz
+        { PLL_M_TO_REG(24, 0),   PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 20 MHz
-        { PLL_M_TO_REG(20, 0),   PLL_N_TO_REG(1) },     // 24 MHz
+        { PLL_M_TO_REG(20, 0),   PLL_N_TO_REG(1), PLL_Q_TO_REG(2) },     // 24 MHz
-        { PLL_M_TO_REG(96, 0),   PLL_N_TO_REG(5) },     // 25 MHz
+        { PLL_M_TO_REG(96, 0),   PLL_N_TO_REG(5), PLL_Q_TO_REG(2) },     // 25 MHz
     },
 };
 
@@ -202,7 +204,7 @@ g_sXTALtoMEMTIM[] =
                  (0 << SYSCTL_MEMTIM0_EWS_S) |
                  SYSCTL_MEMTIM0_MB1) },
     { 40000000, (SYSCTL_MEMTIM0_FBCHT_1_5 | (1 << SYSCTL_MEMTIM0_FWS_S) |
-                 SYSCTL_MEMTIM0_FBCHT_1_5 | (1 << SYSCTL_MEMTIM0_EWS_S) |
+                 SYSCTL_MEMTIM0_EBCHT_1_5 | (1 << SYSCTL_MEMTIM0_EWS_S) |
                  SYSCTL_MEMTIM0_MB1) },
     { 60000000, (SYSCTL_MEMTIM0_FBCHT_2 | (2 << SYSCTL_MEMTIM0_FWS_S) |
                  SYSCTL_MEMTIM0_EBCHT_2 | (2 << SYSCTL_MEMTIM0_EWS_S) |
@@ -329,8 +331,8 @@ _SysCtlFrequencyGet(uint32_t ui32Xtal)
 //*****************************************************************************
 static const uint32_t g_pui32VCOFrequencies[MAX_VCO_ENTRIES] =
 {
-    320000000,                              // VCO 320
+    160000000,                              // VCO 320
-    480000000,                              // VCO 480
+    240000000,                              // VCO 480
 };
 
 //*****************************************************************************
@@ -418,6 +420,8 @@ _SysCtlPeripheralValid(uint32_t ui32Peripheral)
            (ui32Peripheral == SYSCTL_PERIPH_TIMER3) ||
            (ui32Peripheral == SYSCTL_PERIPH_TIMER4) ||
            (ui32Peripheral == SYSCTL_PERIPH_TIMER5) ||
+           (ui32Peripheral == SYSCTL_PERIPH_TIMER6) ||
+           (ui32Peripheral == SYSCTL_PERIPH_TIMER7) ||
            (ui32Peripheral == SYSCTL_PERIPH_UART0) ||
            (ui32Peripheral == SYSCTL_PERIPH_UART1) ||
            (ui32Peripheral == SYSCTL_PERIPH_UART2) ||
@@ -2076,6 +2080,13 @@ SysCtlResetBehaviorGet(void)
 //! function returns the current system frequency which may not match the
 //! requested frequency.
 //!
+//! If the application is using an external crystal then the frequency is
+//! set by using one of the following values:
+//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_6MHZ, \b SYSCTL_XTAL_8MHZ,
+//! \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, \b SYSCTL_XTAL_16MHZ,
+//! \b SYSCTL_XTAL_18MHZ, \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or
+//! \b SYSCTL_XTAL_25MHz.
+//!
 //! The oscillator source is chosen with one of the following values:
 //!
 //! - \b SYSCTL_OSC_MAIN to use an external crystal or oscillator.
@@ -2116,8 +2127,8 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock)
 {
     int32_t i32Timeout, i32VCOIdx, i32XtalIdx;
     uint32_t ui32MOSCCTL;
+    uint32_t ui32Delay;
     uint32_t ui32SysDiv, ui32Osc, ui32OscSelect, ui32RSClkConfig;
-    bool bNewPLL;
 
     //
     // TM4C123 devices should not use this function.
@@ -2205,6 +2216,32 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock)
         }
 
         HWREG(SYSCTL_MOSCCTL) = ui32MOSCCTL;
+        
+        //
+        // Timeout using the legacy delay value.
+        //
+        ui32Delay = 524288;
+
+        while((HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS) == 0)
+        {
+            ui32Delay--;
+
+            if(ui32Delay == 0)
+            {
+                break;
+            }
+        }
+
+        //
+        // If the main oscillator failed to start up then do not switch to
+        // it and return.
+        //
+        if(ui32Delay == 0)
+        {
+            return(0);
+        }
+
+        
     }
     else
     {
@@ -2270,44 +2307,6 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock)
         //
         i32XtalIdx -= SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ);
 
-        //
-        // If there were no changes to the PLL do not force the PLL to lock by
-        // writing the PLL settings.
-        //
-        if((HWREG(SYSCTL_PLLFREQ1) !=
-            g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][1]) ||
-           (HWREG(SYSCTL_PLLFREQ0) !=
-            (g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][0] |
-             SYSCTL_PLLFREQ0_PLLPWR)))
-        {
-            bNewPLL = true;
-        }
-        else
-        {
-            bNewPLL = false;
-        }
-
-        //
-        // If there are new PLL settings write them.
-        //
-        if(bNewPLL)
-        {
-            //
-            // Set the oscillator source.
-            //
-            HWREG(SYSCTL_RSCLKCFG) |= ui32OscSelect;
-
-            //
-            // Set the M, N and Q values provided from the table and preserve
-            // the power state of the main PLL.
-            //
-            HWREG(SYSCTL_PLLFREQ1) =
-                g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][1];
-            HWREG(SYSCTL_PLLFREQ0) =
-                (g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][0] |
-                 (HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR));
-        }
-
         //
         // Calculate the System divider such that we get a frequency that is
         // the closest to the requested frequency without going over.
@@ -2316,9 +2315,25 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock)
                      ui32SysClock;
 
         //
-        // Calculate the actual system clock.
+        // Set the oscillator source.
         //
-        ui32SysClock = _SysCtlFrequencyGet(ui32Osc) / ui32SysDiv;
+        HWREG(SYSCTL_RSCLKCFG) |= ui32OscSelect;
+
+        //
+        // Set the M, N and Q values provided from the table and preserve
+        // the power state of the main PLL.
+        //
+        HWREG(SYSCTL_PLLFREQ1) =
+            g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][1];
+        HWREG(SYSCTL_PLLFREQ1) |= PLL_Q_TO_REG(ui32SysDiv);
+        HWREG(SYSCTL_PLLFREQ0) =
+            (g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][0] |
+             (HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR));
+
+        //
+        // Calculate the actual system clock as PSYSDIV is always div-by 2.
+        //
+        ui32SysClock = _SysCtlFrequencyGet(ui32Osc) / 2;
 
         //
         // Set the Flash and EEPROM timing values.
@@ -2330,13 +2345,10 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock)
         //
         if(HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR)
         {
-            if(bNewPLL == true)
+            //
-            {
+            // Trigger the PLL to lock to the new frequency.
-                //
+            //
-                // Trigger the PLL to lock to the new frequency.
+            HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_NEWFREQ;
-                //
-                HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_NEWFREQ;
-            }
         }
         else
         {
@@ -2363,9 +2375,8 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock)
         if(i32Timeout)
         {
             ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG);
-            ui32RSClkConfig |= ((ui32SysDiv - 1) <<
+            ui32RSClkConfig |= (1 << SYSCTL_RSCLKCFG_PSYSDIV_S) |
-                                SYSCTL_RSCLKCFG_PSYSDIV_S) | ui32OscSelect |
+                                ui32OscSelect | SYSCTL_RSCLKCFG_USEPLL;
-                               SYSCTL_RSCLKCFG_USEPLL;
             ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU;
 
             //
@@ -2462,6 +2473,11 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock)
         HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig;
     }
 
+    //
+    // Finally change the OSCSRC back to PIOSC
+    //
+    HWREG(SYSCTL_RSCLKCFG) &= ~(SYSCTL_RSCLKCFG_OSCSRC_M);
+
     return(ui32SysClock);
 }
 
@@ -2865,11 +2881,6 @@ SysCtlClockGet(void)
                 ui32Max = 80000000;
                 break;
             }
-            case SYSCTL_DC1_MINSYSDIV_66:
-            {
-                ui32Max = 66666666;
-                break;
-            }
             case SYSCTL_DC1_MINSYSDIV_50:
             {
                 ui32Max = 50000000;
@@ -3507,6 +3518,93 @@ SysCtlVoltageEventClear(uint32_t ui32Status)
     HWREG(SYSCTL_PWRTC) |= ui32Status;
 }
 
+//*****************************************************************************
+//
+//! Gets the effective VCO frequency.
+//!
+//! \param ui32Crystal holds the crystal value used for the PLL.
+//! \param pui32VCOFrequency is a pointer to the storage location which holds 
+//! value of the VCO computed.
+//!
+//! This function calculates the VCO of the PLL before the system divider is
+//! applied
+//!
+//! \return \b true if the PLL is configured correctly and a VCO is valid or
+//! \b false if the device is not TM4C129x or the PLL is not used
+//
+//*****************************************************************************
+bool
+SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency)
+{
+    int32_t i32XtalIdx;
+    uint32_t ui32RSClkConfig, ui32PLLFreq0, ui32PLLFreq1, ui32Osc;
+    uint32_t ui32MInt, ui32MFrac, ui32NDiv, ui32QDiv, ui32TempVCO;
+
+    //
+    // Check if TM4C123 device is being used. should not use this function.
+    //
+    if(CLASS_IS_TM4C123)
+    {
+        //
+        // Return error if TM4C123.
+        //
+        *pui32VCOFrequency = 0;
+        return(false);
+    }
+
+    //
+    // Read the RSCLKCFG register to determine if PLL is being used.
+    //
+    ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG);
+
+    //
+    // Check if PLL is used.
+    //
+    if((ui32RSClkConfig & SYSCTL_RSCLKCFG_USEPLL) != SYSCTL_RSCLKCFG_USEPLL)
+    {
+        //
+        // Return error if PLL is not used.
+        //
+        *pui32VCOFrequency = 0;
+        return(false);  
+    }
+    
+    //
+    // Get the index of the crystal from the ui32Config parameter.
+    //
+    i32XtalIdx = SysCtlXtalCfgToIndex(ui32Crystal);
+
+    //
+    // Get the value of the crystal frequency based on the index
+    //
+    ui32Osc = g_pui32Xtals[i32XtalIdx];
+
+    //
+    // Read the PLLFREQ0 and PLLFREQ1 registers to get information on the
+    // MINT, MFRAC, N and Q values of the PLL
+    //
+    ui32PLLFreq0 = HWREG(SYSCTL_PLLFREQ0);
+    ui32PLLFreq1 = HWREG(SYSCTL_PLLFREQ1);
+
+    ui32MInt = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MINT_M) >> 
+               SYSCTL_PLLFREQ0_MINT_S;
+    ui32MFrac = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MFRAC_M) >> 
+                SYSCTL_PLLFREQ0_MFRAC_S;
+    ui32NDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_N_M) >> 
+               SYSCTL_PLLFREQ1_N_S;
+    ui32QDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_Q_M) >> 
+               SYSCTL_PLLFREQ1_Q_S;
+
+    //
+    // Calculate the VCO at the output of the PLL
+    //
+    ui32TempVCO = (ui32Osc * ui32MInt) + ((ui32Osc * ui32MFrac) / 1024);
+    ui32TempVCO /= ((ui32NDiv + 1) * (ui32QDiv + 1));
+    
+    *pui32VCOFrequency = ui32TempVCO;
+    return(true);
+}
+
 //*****************************************************************************
 //
 //! Returns the current NMI status.

bsp/tm4c129x/libraries/driverlib/sysctl.h

@@ -2,7 +2,7 @@
 //
 // sysctl.h - Prototypes for the system control driver.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -642,6 +642,7 @@ extern void SysCtlNMIClear(uint32_t ui32Status);
 extern void SysCtlVoltageEventConfig(uint32_t ui32Config);
 extern uint32_t SysCtlVoltageEventStatus(void);
 extern void SysCtlVoltageEventClear(uint32_t ui32Status);
+extern bool SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency);
 
 //*****************************************************************************
 //

bsp/tm4c129x/libraries/driverlib/sysexc.c

@@ -2,7 +2,7 @@
 //
 // sysexc.c - Routines for the System Exception Module.
 //
-// Copyright (c) 2011-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2011-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/sysexc.h

@@ -2,7 +2,7 @@
 //
 // sysexc.h - Prototypes for the System Exception Module routines.
 //
-// Copyright (c) 2011-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2011-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/systick.c

@@ -2,7 +2,7 @@
 //
 // systick.c - Driver for the SysTick timer in NVIC.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/systick.h

@@ -2,7 +2,7 @@
 //
 // systick.h - Prototypes for the SysTick driver.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/tiva_timer.c

@@ -2,7 +2,7 @@
 //
 // timer.c - Driver for the timer module.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -121,6 +121,7 @@ _TimerBaseValid(uint32_t ui32Base)
     return((ui32Base == TIMER0_BASE) || (ui32Base == TIMER1_BASE) ||
            (ui32Base == TIMER2_BASE) || (ui32Base == TIMER3_BASE) ||
            (ui32Base == TIMER4_BASE) || (ui32Base == TIMER5_BASE) ||
+           (ui32Base == TIMER6_BASE) || (ui32Base == TIMER7_BASE) ||
            (ui32Base == WTIMER0_BASE) || (ui32Base == WTIMER1_BASE) ||
            (ui32Base == WTIMER2_BASE) || (ui32Base == WTIMER3_BASE) ||
            (ui32Base == WTIMER4_BASE) || (ui32Base == WTIMER5_BASE));
@@ -362,7 +363,9 @@ TimerConfigure(uint32_t ui32Base, uint32_t ui32Config)
              ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
              ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) ||
              ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
+             ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT_UP) ||
              ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
+             ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME_UP) ||
              ((ui32Config & 0x000000ff) == TIMER_CFG_A_PWM)) &&
             (((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
              ((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) ||

bsp/tm4c129x/libraries/driverlib/tiva_timer.h

@@ -2,7 +2,7 @@
 //
 // timer.h - Prototypes for the timer module
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,12 +33,12 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
-#ifndef __DRIVERLIB_TIVA_TIMER_H__
+#ifndef __DRIVERLIB_TIMER_H__
-#define __DRIVERLIB_TIVA_TIMER_H__
+#define __DRIVERLIB_TIMER_H__
 
 //*****************************************************************************
 //

bsp/tm4c129x/libraries/driverlib/uart.c

@@ -2,7 +2,7 @@
 //
 // uart.c - Driver for the UART.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -352,9 +352,14 @@ UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel,
 //! zero, respectively).
 //!
 //! The peripheral clock is the same as the processor clock.  The frequency of
-//! the system clock is the value returned by SysCtlClockGet(), or it can be
+//! the system clock is the value returned by SysCtlClockGet() for TM4C123x
-//! explicitly hard coded if it is constant and known (to save the
+//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices,
-//! code/execution overhead of a call to SysCtlClockGet()).
+//! or it can be explicitly hard coded if it is constant and known (to save the
+//! code/execution overhead of a call to SysCtlClockGet() or fetch of the 
+//! variable call holding the return value of SysCtlClockFreqSet()).
+//!
+//! The function disables the UART by calling UARTDisable() before changing the
+//! the parameters and enables the UART by calling UARTEnable().
 //!
 //! For Tiva parts that have the ability to specify the UART baud clock
 //! source (via UARTClockSourceSet()), the peripheral clock can be changed to
@@ -451,9 +456,11 @@ UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
 //! UARTConfigSetExpClk().
 //!
 //! The peripheral clock is the same as the processor clock.  The frequency of
-//! the system clock is the value returned by SysCtlClockGet(), or it can be
+//! the system clock is the value returned by SysCtlClockGet() for TM4C123x
-//! explicitly hard coded if it is constant and known (to save the
+//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices,
-//! code/execution overhead of a call to SysCtlClockGet()).
+//! or it can be explicitly hard coded if it is constant and known (to save the
+//! code/execution overhead of a call to SysCtlClockGet() or fetch of the 
+//! variable call holding the return value of SysCtlClockFreqSet()).
 //!
 //! For Tiva parts that have the ability to specify the UART baud clock
 //! source (via UARTClockSourceSet()), the peripheral clock can be changed to
@@ -1950,6 +1957,35 @@ UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr)
     HWREG(ui32Base + UART_O_LCRH) = ui32LCRH;
 }
 
+//*****************************************************************************
+//
+//! Enables internal loopback mode for a UART port
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function configures a UART port in internal loopback mode to help with
+//! diagnostics and debug.  In this mode, the transmit and receive terminals of
+//! the same UART port are internally connected.  Hence, the data transmitted
+//! on the UnTx output is received on the UxRx input, without having to go
+//! through I/O's.  UARTCharPut(), UARTCharGet() functions can be used along 
+//! with this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void UARTLoopbackEnable(uint32_t ui32Base)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(_UARTBaseValid(ui32Base));
+
+    //
+    // Write the Loopback Enable bit to register.
+    //
+    HWREG(ui32Base + UART_O_CTL) |= UART_CTL_LBE;
+}
+
 //*****************************************************************************
 //
 // Close the Doxygen group.

bsp/tm4c129x/libraries/driverlib/uart.h

@@ -2,7 +2,7 @@
 //
 // uart.h - Defines and Macros for the UART.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -242,6 +242,7 @@ extern void UART9BitDisable(uint32_t ui32Base);
 extern void UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr,
                             uint8_t ui8Mask);
 extern void UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr);
+extern void UARTLoopbackEnable(uint32_t ui32Base);
 
 //*****************************************************************************
 //

bsp/tm4c129x/libraries/driverlib/udma.c

@@ -2,7 +2,7 @@
 //
 // udma.c - Driver for the micro-DMA controller.
 //
-// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2007-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -1072,9 +1072,9 @@ uDMAChannelModeGet(uint32_t ui32ChannelStructIndex)
 //! controller generates an interrupt.  The \e ui32IntChannel parameter should
 //! be one of the following:
 //!
-//! - \b UDMA_INT_SW to register an interrupt handler to process interrupts
+//! - \b INT_UDMA to register an interrupt handler to process interrupts
 //!   from the uDMA software channel (UDMA_CHANNEL_SW)
-//! - \b UDMA_INT_ERR to register an interrupt handler to process uDMA error
+//! - \b INT_UDMAERR to register an interrupt handler to process uDMA error
 //!   interrupts
 //!
 //! \sa IntRegister() for important information about registering interrupt
@@ -1095,8 +1095,6 @@ uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void))
     // Check the arguments.
     //
     ASSERT(pfnHandler);
-    ASSERT((ui32IntChannel == UDMA_INT_SW) ||
-           (ui32IntChannel == UDMA_INT_ERR));
 
     //
     // Register the interrupt handler.
@@ -1117,7 +1115,7 @@ uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void))
 //!
 //! This function disables and unregisters the handler to be called for the
 //! specified uDMA interrupt.  The \e ui32IntChannel parameter should be one of
-//! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function
+//! \b INT_UDMA or \b INT_UDMAERR as documented for the function
 //! uDMAIntRegister().
 //!
 //! \sa IntRegister() for important information about registering interrupt
@@ -1230,7 +1228,7 @@ uDMAChannelAssign(uint32_t ui32Mapping)
     //
     // Check the parameters
     //
-    ASSERT((ui32Mapping & 0xffffff00) < 0x00050000);
+    ASSERT((ui32Mapping & 0xffffff00) < 0x00090000);
 
     //
     // Extract the channel number and map encoding value from the parameter.

bsp/tm4c129x/libraries/driverlib/udma.h

@@ -2,7 +2,7 @@
 //
 // udma.h - Prototypes and macros for the uDMA controller.
 //
-// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2007-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -290,15 +290,6 @@ tDMAControlTable;
 #define UDMA_PRI_SELECT         0x00000000
 #define UDMA_ALT_SELECT         0x00000020
 
-//*****************************************************************************
-//
-// uDMA interrupt sources, to be passed to uDMAIntRegister() and
-// uDMAIntUnregister().
-//
-//*****************************************************************************
-#define UDMA_INT_SW             62
-#define UDMA_INT_ERR            63
-
 //*****************************************************************************
 //
 // Channel numbers to be passed to API functions that require a channel number

bsp/tm4c129x/libraries/driverlib/usb.c

@@ -2,7 +2,7 @@
 //
 // usb.c - Driver for the USB Interface.
 //
-// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2007-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -152,6 +152,7 @@ _USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint,
 // \param ui32Base specifies the USB module base address.
 // \param ui32Endpoint is the endpoint index to target for this write.
 // \param ui32IndexedReg is the indexed register to write to.
+// \param ui32Size is a value of 1 or 2 indicating the byte size of the read.
 //
 // This function is used internally to access the indexed registers for each
 // endpoint.  The only registers that are indexed are the FIFO configuration
@@ -165,7 +166,7 @@ _USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint,
               uint32_t ui32IndexedReg, uint32_t ui32Size)
 {
     uint8_t ui8Index;
-    uint8_t ui8Value;
+    uint32_t ui32Value;
 
     //
     // Check the arguments.
@@ -193,14 +194,14 @@ _USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint,
         //
         // Get the value.
         //
-        ui8Value = HWREGB(ui32Base + ui32IndexedReg);
+        ui32Value = HWREGB(ui32Base + ui32IndexedReg);
     }
     else
     {
         //
         // Get the value.
         //
-        ui8Value = HWREGH(ui32Base + ui32IndexedReg);
+        ui32Value = HWREGH(ui32Base + ui32IndexedReg);
     }
 
     //
@@ -211,7 +212,7 @@ _USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint,
     //
     // Return the register's value.
     //
-    return(ui8Value);
+    return(ui32Value);
 }
 
 //*****************************************************************************

bsp/tm4c129x/libraries/driverlib/usb.h

@@ -2,7 +2,7 @@
 //
 // usb.h - Prototypes for the USB Interface Driver.
 //
-// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2007-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/watchdog.c

@@ -2,7 +2,7 @@
 //
 // watchdog.c - Driver for the Watchdog Timer Module.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/driverlib/watchdog.h

@@ -2,7 +2,7 @@
 //
 // watchdog.h - Prototypes for the Watchdog Timer API
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
+// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/asmdefs.h

@@ -2,7 +2,7 @@
 //
 // asmdefs.h - Macros to allow assembly code be portable among toolchains.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_adc.h

@@ -2,7 +2,7 @@
 //
 // hw_adc.h - Macros used when accessing the ADC hardware.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -412,7 +412,6 @@
 // The following are defines for the bit fields in the ADC_O_CTL register.
 //
 //*****************************************************************************
-#define ADC_CTL_DITHER          0x00000040  // Dither Mode Enable
 #define ADC_CTL_VREF_M          0x00000003  // Voltage Reference Select
 #define ADC_CTL_VREF_INTERNAL   0x00000000  // VDDA and GNDA are the voltage
                                             // references

bsp/tm4c129x/libraries/inc/hw_aes.h

@@ -2,7 +2,7 @@
 //
 // hw_aes.h - Macros used when accessing the AES hardware.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_can.h

@@ -2,7 +2,7 @@
 //
 // hw_can.h - Defines and macros used when accessing the CAN controllers.
 //
-// Copyright (c) 2006-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2006-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_ccm.h

@@ -2,7 +2,7 @@
 //
 // hw_ccm.h - Macros used when accessing the CCM hardware.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_comp.h

@@ -2,7 +2,7 @@
 //
 // hw_comp.h - Macros used when accessing the comparator hardware.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_des.h

@@ -2,7 +2,7 @@
 //
 // hw_des.h - Macros used when accessing the DES hardware.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_eeprom.h

@@ -2,7 +2,7 @@
 //
 // hw_eeprom.h - Macros used when accessing the EEPROM controller.
 //
-// Copyright (c) 2011-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2011-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_emac.h

@@ -2,7 +2,7 @@
 //
 // hw_emac.h - Macros used when accessing the EMAC hardware.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -58,6 +58,10 @@
                                             // Frame Filter
 #define EMAC_O_PMTCTLSTAT       0x0000002C  // Ethernet MAC PMT Control and
                                             // Status Register
+#define EMAC_O_LPICTLSTAT       0x00000030  // Ethernet MAC Low Power Idle
+                                            // Control and Status Register
+#define EMAC_O_LPITIMERCTL      0x00000034  // Ethernet MAC Low Power Idle
+                                            // Timer Control Register
 #define EMAC_O_RIS              0x00000038  // Ethernet MAC Raw Interrupt
                                             // Status
 #define EMAC_O_IM               0x0000003C  // Ethernet MAC Interrupt Mask
@@ -295,19 +299,6 @@
 //*****************************************************************************
 #define EMAC_FLOWCTL_PT_M       0xFFFF0000  // Pause Time
 #define EMAC_FLOWCTL_DZQP       0x00000080  // Disable Zero-Quanta Pause
-#define EMAC_FLOWCTL_PLT_M      0x00000030  // Pause Low Threshold
-#define EMAC_FLOWCTL_PLT_4      0x00000000  // The threshold is Pause time
-                                            // minus 4 slot times (PT - 4 slot
-                                            // times)
-#define EMAC_FLOWCTL_PLT_28     0x00000010  // The threshold is Pause time
-                                            // minus 28 slot times (PT - 28
-                                            // slot times)
-#define EMAC_FLOWCTL_PLT_144    0x00000020  // The threshold is Pause time
-                                            // minus 144 slot times (PT - 144
-                                            // slot times)
-#define EMAC_FLOWCTL_PLT_156    0x00000030  // The threshold is Pause time
-                                            // minus 256 slot times (PT - 256
-                                            // slot times)
 #define EMAC_FLOWCTL_UP         0x00000008  // Unicast Pause Frame Detect
 #define EMAC_FLOWCTL_RFE        0x00000004  // Receive Flow Control Enable
 #define EMAC_FLOWCTL_TFE        0x00000002  // Transmit Flow Control Enable
@@ -418,11 +409,40 @@
 #define EMAC_PMTCTLSTAT_RWKPTR_S                                              \
                                 24
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_LPICTLSTAT
+// register.
+//
+//*****************************************************************************
+#define EMAC_LPICTLSTAT_LPITXA  0x00080000  // LPI TX Automate
+#define EMAC_LPICTLSTAT_PLSEN   0x00040000  // PHY Link Status Enable
+#define EMAC_LPICTLSTAT_PLS     0x00020000  // PHY Link Status
+#define EMAC_LPICTLSTAT_LPIEN   0x00010000  // LPI Enable
+#define EMAC_LPICTLSTAT_RLPIST  0x00000200  // Receive LPI State
+#define EMAC_LPICTLSTAT_TLPIST  0x00000100  // Transmit LPI State
+#define EMAC_LPICTLSTAT_RLPIEX  0x00000008  // Receive LPI Exit
+#define EMAC_LPICTLSTAT_RLPIEN  0x00000004  // Receive LPI Entry
+#define EMAC_LPICTLSTAT_TLPIEX  0x00000002  // Transmit LPI Exit
+#define EMAC_LPICTLSTAT_TLPIEN  0x00000001  // Transmit LPI Entry
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_LPITIMERCTL
+// register.
+//
+//*****************************************************************************
+#define EMAC_LPITIMERCTL_LST_M  0x03FF0000  // Low Power Idle LS Timer
+#define EMAC_LPITIMERCTL_LST_S  16
+#define EMAC_LPITIMERCTL_TWT_M  0x0000FFFF  // Low Power Idle TW Timer
+#define EMAC_LPITIMERCTL_TWT_S  0
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EMAC_O_RIS register.
 //
 //*****************************************************************************
+#define EMAC_RIS_LPI            0x00000400  // LPI Interrupt Status
 #define EMAC_RIS_TS             0x00000200  // Timestamp Interrupt Status
 #define EMAC_RIS_MMCTX          0x00000040  // MMC Transmit Interrupt Status
 #define EMAC_RIS_MMCRX          0x00000020  // MMC Receive Interrupt Status
@@ -434,6 +454,7 @@
 // The following are defines for the bit fields in the EMAC_O_IM register.
 //
 //*****************************************************************************
+#define EMAC_IM_LPI             0x00000400  // LPI Interrupt Mask
 #define EMAC_IM_TSI             0x00000200  // Timestamp Interrupt Mask
 #define EMAC_IM_PMT             0x00000008  // PMT Interrupt Mask
 
@@ -875,77 +896,6 @@
 #define EMAC_PPSCTRL_PPSCTRL_M  0x0000000F  // EN0PPS Output Frequency Control
                                             // (PPSCTRL) or Command Control
                                             // (PPSCMD)
-#define EMAC_PPSCTRL_PPSCTRL_1HZ                                              \
-                                0x00000000  // When the PPSEN0 bit = 0x0, the
-                                            // EN0PPS signal is 1 pulse of the
-                                            // PTP reference clock.(of width
-                                            // clk_ptp_i) every second
-#define EMAC_PPSCTRL_PPSCTRL_2HZ                                              \
-                                0x00000001  // When the PPSEN0 bit = 0x0, the
-                                            // binary rollover is 2 Hz, and the
-                                            // digital rollover is 1 Hz
-#define EMAC_PPSCTRL_PPSCTRL_4HZ                                              \
-                                0x00000002  // When the PPSEN0 bit = 0x0, the
-                                            // binary rollover is 4 Hz, and the
-                                            // digital rollover is 2 Hz
-#define EMAC_PPSCTRL_PPSCTRL_8HZ                                              \
-                                0x00000003  // When thePPSEN0 bit = 0x0, the
-                                            // binary rollover is 8 Hz, and the
-                                            // digital rollover is 4 Hz,
-#define EMAC_PPSCTRL_PPSCTRL_16HZ                                             \
-                                0x00000004  // When thePPSEN0 bit = 0x0, the
-                                            // binary rollover is 16 Hz, and
-                                            // the digital rollover is 8 Hz
-#define EMAC_PPSCTRL_PPSCTRL_32HZ                                             \
-                                0x00000005  // When thePPSEN0 bit = 0x0, the
-                                            // binary rollover is 32 Hz, and
-                                            // the digital rollover is 16 Hz
-#define EMAC_PPSCTRL_PPSCTRL_64HZ                                             \
-                                0x00000006  // When thePPSEN0 bit = 0x0, the
-                                            // binary rollover is 64 Hz, and
-                                            // the digital rollover is 32 Hz
-#define EMAC_PPSCTRL_PPSCTRL_128HZ                                            \
-                                0x00000007  // When thePPSEN0 bit = 0x0, the
-                                            // binary rollover is 128 Hz, and
-                                            // the digital rollover is 64 Hz
-#define EMAC_PPSCTRL_PPSCTRL_256HZ                                            \
-                                0x00000008  // When thePPSEN0 bit = 0x0, the
-                                            // binary rollover is 256 Hz, and
-                                            // the digital rollover is 128 Hz
-#define EMAC_PPSCTRL_PPSCTRL_512HZ                                            \
-                                0x00000009  // When thePPSEN0 bit = 0x0, the
-                                            // binary rollover is 512 Hz, and
-                                            // the digital rollover is 256 Hz
-#define EMAC_PPSCTRL_PPSCTRL_1024HZ                                           \
-                                0x0000000A  // When the PPSEN0 bit = 0x0, the
-                                            // binary rollover is 1.024 kHz,
-                                            // and the digital rollover is 512
-                                            // Hz
-#define EMAC_PPSCTRL_PPSCTRL_2048HZ                                           \
-                                0x0000000B  // When thePPSEN0 bit = 0x0, the
-                                            // binary rollover is 2.048 kHz,
-                                            // and the digital rollover is
-                                            // 1.024 kHz
-#define EMAC_PPSCTRL_PPSCTRL_4096HZ                                           \
-                                0x0000000C  // When thePPSEN0 bit = 0x0, the
-                                            // binary rollover is 4.096 kHz,
-                                            // and the digital rollover is
-                                            // 2.048 kHz
-#define EMAC_PPSCTRL_PPSCTRL_8192HZ                                           \
-                                0x0000000D  // When thePPSEN0 bit = 0x0, the
-                                            // binary rollover is 8.192 kHz,
-                                            // and the digital rollover is
-                                            // 4.096 kHz
-#define EMAC_PPSCTRL_PPSCTRL_16384HZ                                          \
-                                0x0000000E  // When thePPSEN0 bit = 0x0, the
-                                            // binary rollover is 16.384 kHz,
-                                            // and the digital rollover is
-                                            // 8.092 kHz
-#define EMAC_PPSCTRL_PPSCTRL_32768HZ                                          \
-                                0x0000000F  // When thePPSEN0 bit = 0x0, the
-                                            // binary rollover is 32.768 KHz,
-                                            // and the digital rollover is
-                                            // 16.384 KHz
 
 //*****************************************************************************
 //
@@ -1039,6 +989,7 @@
 // The following are defines for the bit fields in the EMAC_O_DMARIS register.
 //
 //*****************************************************************************
+#define EMAC_DMARIS_LPI         0x40000000  // LPI Trigger Interrupt Status
 #define EMAC_DMARIS_TT          0x20000000  // Timestamp Trigger Interrupt
                                             // Status
 #define EMAC_DMARIS_PMT         0x10000000  // MAC PMT Interrupt Status
@@ -1832,6 +1783,84 @@
 //*****************************************************************************
 #ifndef DEPRECATED
 
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// EMAC_O_PPSCTRL register.
+//
+//*****************************************************************************
+#define EMAC_PPSCTRL_PPSCTRL_1HZ                                              \
+                                0x00000000  // When the PPSEN0 bit = 0x0, the
+                                            // EN0PPS signal is 1 pulse of the
+                                            // PTP reference clock.(of width
+                                            // clk_ptp_i) every second
+#define EMAC_PPSCTRL_PPSCTRL_2HZ                                              \
+                                0x00000001  // When the PPSEN0 bit = 0x0, the
+                                            // binary rollover is 2 Hz, and the
+                                            // digital rollover is 1 Hz
+#define EMAC_PPSCTRL_PPSCTRL_4HZ                                              \
+                                0x00000002  // When the PPSEN0 bit = 0x0, the
+                                            // binary rollover is 4 Hz, and the
+                                            // digital rollover is 2 Hz
+#define EMAC_PPSCTRL_PPSCTRL_8HZ                                              \
+                                0x00000003  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 8 Hz, and the
+                                            // digital rollover is 4 Hz,
+#define EMAC_PPSCTRL_PPSCTRL_16HZ                                             \
+                                0x00000004  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 16 Hz, and
+                                            // the digital rollover is 8 Hz
+#define EMAC_PPSCTRL_PPSCTRL_32HZ                                             \
+                                0x00000005  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 32 Hz, and
+                                            // the digital rollover is 16 Hz
+#define EMAC_PPSCTRL_PPSCTRL_64HZ                                             \
+                                0x00000006  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 64 Hz, and
+                                            // the digital rollover is 32 Hz
+#define EMAC_PPSCTRL_PPSCTRL_128HZ                                            \
+                                0x00000007  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 128 Hz, and
+                                            // the digital rollover is 64 Hz
+#define EMAC_PPSCTRL_PPSCTRL_256HZ                                            \
+                                0x00000008  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 256 Hz, and
+                                            // the digital rollover is 128 Hz
+#define EMAC_PPSCTRL_PPSCTRL_512HZ                                            \
+                                0x00000009  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 512 Hz, and
+                                            // the digital rollover is 256 Hz
+#define EMAC_PPSCTRL_PPSCTRL_1024HZ                                           \
+                                0x0000000A  // When the PPSEN0 bit = 0x0, the
+                                            // binary rollover is 1.024 kHz,
+                                            // and the digital rollover is 512
+                                            // Hz
+#define EMAC_PPSCTRL_PPSCTRL_2048HZ                                           \
+                                0x0000000B  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 2.048 kHz,
+                                            // and the digital rollover is
+                                            // 1.024 kHz
+#define EMAC_PPSCTRL_PPSCTRL_4096HZ                                           \
+                                0x0000000C  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 4.096 kHz,
+                                            // and the digital rollover is
+                                            // 2.048 kHz
+#define EMAC_PPSCTRL_PPSCTRL_8192HZ                                           \
+                                0x0000000D  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 8.192 kHz,
+                                            // and the digital rollover is
+                                            // 4.096 kHz
+#define EMAC_PPSCTRL_PPSCTRL_16384HZ                                          \
+                                0x0000000E  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 16.384 kHz,
+                                            // and the digital rollover is
+                                            // 8.092 kHz
+#define EMAC_PPSCTRL_PPSCTRL_32768HZ                                          \
+                                0x0000000F  // When thePPSEN0 bit = 0x0, the
+                                            // binary rollover is 32.768 KHz,
+                                            // and the digital rollover is
+                                            // 16.384 KHz
+
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the EMAC_O_CC

bsp/tm4c129x/libraries/inc/hw_epi.h

@@ -2,7 +2,7 @@
 //
 // hw_epi.h - Macros for use in accessing the EPI registers.
 //
-// Copyright (c) 2008-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2008-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_fan.h

@@ -2,7 +2,7 @@
 //
 // hw_fan.h - Macros used when accessing the fan control hardware.
 //
-// Copyright (c) 2010-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2010-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_flash.h

@@ -2,7 +2,7 @@
 //
 // hw_flash.h - Macros used when accessing the flash controller.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_gpio.h

@@ -2,7 +2,7 @@
 //
 // hw_gpio.h - Defines and Macros for GPIO hardware.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_hibernate.h

@@ -2,7 +2,7 @@
 //
 // hw_hibernate.h - Defines and Macros for the Hibernation module.
 //
-// Copyright (c) 2007-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2007-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_i2c.h

@@ -2,7 +2,7 @@
 //
 // hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_ints.h

@@ -3,7 +3,7 @@
 // hw_ints.h - Macros that define the interrupt assignment on Tiva C Series
 // MCUs.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -34,7 +34,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -313,7 +313,7 @@
     defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \
     defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \
     defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \
-    defined(PART_TM4C123GH6ZRB)
+    defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH6ZXR)
 #define INT_RESOLVE(intname, class) intname##TM4C123
 
 //*****************************************************************************

bsp/tm4c129x/libraries/inc/hw_lcd.h

@@ -2,7 +2,7 @@
 //
 // hw_lcd.h - Defines and macros used when accessing the LCD controller.
 //
-// Copyright (c) 2011-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2011-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_memmap.h

@@ -2,7 +2,7 @@
 //
 // hw_memmap.h - Macros defining the memory map of the device.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_nvic.h

@@ -2,7 +2,7 @@
 //
 // hw_nvic.h - Macros used when accessing the NVIC hardware.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_onewire.h

@@ -0,0 +1,223 @@
+//*****************************************************************************
+//
+// hw_onewire.h - Macros used when accessing the One wire hardware.
+//
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_ONEWIRE_H__
+#define __HW_ONEWIRE_H__
+
+//*****************************************************************************
+//
+// The following are defines for the One wire register offsets.
+//
+//*****************************************************************************
+#define ONEWIRE_O_CS            0x00000000  // 1-Wire Control and Status
+#define ONEWIRE_O_TIM           0x00000004  // 1-Wire Timing Override
+#define ONEWIRE_O_DATW          0x00000008  // 1-Wire Data Write
+#define ONEWIRE_O_DATR          0x0000000C  // 1-Wire Data Read
+#define ONEWIRE_O_IM            0x00000100  // 1-Wire Interrupt Mask
+#define ONEWIRE_O_RIS           0x00000104  // 1-Wire Raw Interrupt Status
+#define ONEWIRE_O_MIS           0x00000108  // 1-Wire Masked Interrupt Status
+#define ONEWIRE_O_ICR           0x0000010C  // 1-Wire Interrupt Clear
+#define ONEWIRE_O_DMA           0x00000120  // 1-Wire uDMA Control
+#define ONEWIRE_O_PP            0x00000FC0  // 1-Wire Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_CS register.
+//
+//*****************************************************************************
+#define ONEWIRE_CS_USEALT       0x80000000  // Two Wire Enable
+#define ONEWIRE_CS_ALTP         0x40000000  // Alternate Polarity Enable
+#define ONEWIRE_CS_BSIZE_M      0x00070000  // Last Byte Size
+#define ONEWIRE_CS_BSIZE_8      0x00000000  // 8 bits (1 byte)
+#define ONEWIRE_CS_BSIZE_1      0x00010000  // 1 bit
+#define ONEWIRE_CS_BSIZE_2      0x00020000  // 2 bits
+#define ONEWIRE_CS_BSIZE_3      0x00030000  // 3 bits
+#define ONEWIRE_CS_BSIZE_4      0x00040000  // 4 bits
+#define ONEWIRE_CS_BSIZE_5      0x00050000  // 5 bits
+#define ONEWIRE_CS_BSIZE_6      0x00060000  // 6 bits
+#define ONEWIRE_CS_BSIZE_7      0x00070000  // 7 bits
+#define ONEWIRE_CS_STUCK        0x00000400  // STUCK Status
+#define ONEWIRE_CS_NOATR        0x00000200  // Answer-to-Reset Status
+#define ONEWIRE_CS_BUSY         0x00000100  // Busy Status
+#define ONEWIRE_CS_SKATR        0x00000080  // Skip Answer-to-Reset Enable
+#define ONEWIRE_CS_LSAM         0x00000040  // Late Sample Enable
+#define ONEWIRE_CS_ODRV         0x00000020  // Overdrive Enable
+#define ONEWIRE_CS_SZ_M         0x00000018  // Data Operation Size
+#define ONEWIRE_CS_OP_M         0x00000006  // Operation Request
+#define ONEWIRE_CS_OP_NONE      0x00000000  // No operation
+#define ONEWIRE_CS_OP_RD        0x00000002  // Read
+#define ONEWIRE_CS_OP_WR        0x00000004  // Write
+#define ONEWIRE_CS_OP_WRRD      0x00000006  // Write/Read
+#define ONEWIRE_CS_RST          0x00000001  // Reset Request
+#define ONEWIRE_CS_SZ_S         3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_TIM register.
+//
+//*****************************************************************************
+#define ONEWIRE_TIM_W1TIM_M     0xF0000000  // Value '1' Timing
+#define ONEWIRE_TIM_W0TIM_M     0x0F800000  // Value '0' Timing
+#define ONEWIRE_TIM_W0REST_M    0x00780000  // Rest Time
+#define ONEWIRE_TIM_W1SAM_M     0x00078000  // Sample Time
+#define ONEWIRE_TIM_ATRSAM_M    0x00007800  // Answer-to-Reset Sample
+#define ONEWIRE_TIM_ATRTIM_M    0x000007C0  // Answer-to-Reset/Rest Period
+#define ONEWIRE_TIM_RSTTIM_M    0x0000003F  // Reset Low Time
+#define ONEWIRE_TIM_W1TIM_S     28
+#define ONEWIRE_TIM_W0TIM_S     23
+#define ONEWIRE_TIM_W0REST_S    19
+#define ONEWIRE_TIM_W1SAM_S     15
+#define ONEWIRE_TIM_ATRSAM_S    11
+#define ONEWIRE_TIM_ATRTIM_S    6
+#define ONEWIRE_TIM_RSTTIM_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_DATW register.
+//
+//*****************************************************************************
+#define ONEWIRE_DATW_B3_M       0xFF000000  // Upper Data Byte
+#define ONEWIRE_DATW_B2_M       0x00FF0000  // Upper Middle Data Byte
+#define ONEWIRE_DATW_B1_M       0x0000FF00  // Lower Middle Data Byte
+#define ONEWIRE_DATW_B0_M       0x000000FF  // Lowest Data Byte
+#define ONEWIRE_DATW_B3_S       24
+#define ONEWIRE_DATW_B2_S       16
+#define ONEWIRE_DATW_B1_S       8
+#define ONEWIRE_DATW_B0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_DATR register.
+//
+//*****************************************************************************
+#define ONEWIRE_DATR_B3_M       0xFF000000  // Upper Data Byte
+#define ONEWIRE_DATR_B2_M       0x00FF0000  // Upper Middle Data Byte
+#define ONEWIRE_DATR_B1_M       0x0000FF00  // Lower Middle Data Byte
+#define ONEWIRE_DATR_B0_M       0x000000FF  // Lowest Data Byte
+#define ONEWIRE_DATR_B3_S       24
+#define ONEWIRE_DATR_B2_S       16
+#define ONEWIRE_DATR_B1_S       8
+#define ONEWIRE_DATR_B0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_IM register.
+//
+//*****************************************************************************
+#define ONEWIRE_IM_DMA          0x00000010  // DMA Done Interrupt Mask
+#define ONEWIRE_IM_STUCK        0x00000008  // Stuck Status Interrupt Mask
+#define ONEWIRE_IM_NOATR        0x00000004  // No Answer-to-Reset Interrupt
+                                            // Mask
+#define ONEWIRE_IM_OPC          0x00000002  // Operation Complete Interrupt
+                                            // Mask
+#define ONEWIRE_IM_RST          0x00000001  // Reset Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_RIS register.
+//
+//*****************************************************************************
+#define ONEWIRE_RIS_DMA         0x00000010  // DMA Done Raw Interrupt Status
+#define ONEWIRE_RIS_STUCK       0x00000008  // Stuck Status Raw Interrupt
+                                            // Status
+#define ONEWIRE_RIS_NOATR       0x00000004  // No Answer-to-Reset Raw Interrupt
+                                            // Status
+#define ONEWIRE_RIS_OPC         0x00000002  // Operation Complete Raw Interrupt
+                                            // Status
+#define ONEWIRE_RIS_RST         0x00000001  // Reset Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_MIS register.
+//
+//*****************************************************************************
+#define ONEWIRE_MIS_DMA         0x00000010  // DMA Done Masked Interrupt Status
+#define ONEWIRE_MIS_STUCK       0x00000008  // Stuck Status Masked Interrupt
+                                            // Status
+#define ONEWIRE_MIS_NOATR       0x00000004  // No Answer-to-Reset Masked
+                                            // Interrupt Status
+#define ONEWIRE_MIS_OPC         0x00000002  // Operation Complete Masked
+                                            // Interrupt Status
+#define ONEWIRE_MIS_RST         0x00000001  // Reset Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_ICR register.
+//
+//*****************************************************************************
+#define ONEWIRE_ICR_DMA         0x00000010  // DMA Done Interrupt Clear
+#define ONEWIRE_ICR_STUCK       0x00000008  // Stuck Status Interrupt Clear
+#define ONEWIRE_ICR_NOATR       0x00000004  // No Answer-to-Reset Interrupt
+                                            // Clear
+#define ONEWIRE_ICR_OPC         0x00000002  // Operation Complete Interrupt
+                                            // Clear
+#define ONEWIRE_ICR_RST         0x00000001  // Reset Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_DMA register.
+//
+//*****************************************************************************
+#define ONEWIRE_DMA_SG          0x00000008  // Scatter-Gather Enable
+#define ONEWIRE_DMA_DMAOP_M     0x00000006  // uDMA Operation
+#define ONEWIRE_DMA_DMAOP_DIS   0x00000000  // uDMA disabled
+#define ONEWIRE_DMA_DMAOP_RDSNG 0x00000002  // uDMA single read: 1-Wire
+                                            // requests uDMA to read
+                                            // ONEWIREDATR register after each
+                                            // read transaction
+#define ONEWIRE_DMA_DMAOP_WRMUL 0x00000004  // uDMA multiple write: 1-Wire
+                                            // requests uDMA to load whenever
+                                            // the ONEWIREDATW register is
+                                            // empty
+#define ONEWIRE_DMA_DMAOP_RDMUL 0x00000006  // uDMA multiple read: An initial
+                                            // read occurs and subsequent reads
+                                            // start after uDMA has read the
+                                            // ONEWIREDATR register
+#define ONEWIRE_DMA_RST         0x00000001  // uDMA Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_PP register.
+//
+//*****************************************************************************
+#define ONEWIRE_PP_DMAP         0x00000010  // uDMA Present
+#define ONEWIRE_PP_CNT_M        0x00000003  // 1-Wire Bus Count
+#define ONEWIRE_PP_CNT_S        0
+
+#endif // __HW_ONEWIRE_H__

bsp/tm4c129x/libraries/inc/hw_pwm.h

@@ -2,7 +2,7 @@
 //
 // hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_qei.h

@@ -2,7 +2,7 @@
 //
 // hw_qei.h - Macros used when accessing the QEI hardware.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_shamd5.h

@@ -2,7 +2,7 @@
 //
 // hw_shamd5.h - Macros used when accessing the SHA/MD5 hardware.
 //
-// Copyright (c) 2012-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2012-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_ssi.h

@@ -2,7 +2,7 @@
 //
 // hw_ssi.h - Macros used when accessing the SSI hardware.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -102,7 +102,6 @@
 #define SSI_CR1_MODE_ADVANCED   0x000000C0  // Advanced SSI Mode with 8-bit
                                             // packet size
 #define SSI_CR1_EOT             0x00000010  // End of Transmission
-#define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable
 #define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
 #define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
                                             // Enable

bsp/tm4c129x/libraries/inc/hw_sysctl.h

@@ -2,7 +2,7 @@
 //
 // hw_sysctl.h - Macros used when accessing the system control hardware.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -425,6 +425,10 @@
 #define SYSCTL_PRLCD            0x400FEA90  // LCD Controller Peripheral Ready
 #define SYSCTL_PROWIRE          0x400FEA98  // 1-Wire Peripheral Ready
 #define SYSCTL_PREMAC           0x400FEA9C  // Ethernet MAC Peripheral Ready
+#define SYSCTL_UNIQUEID0        0x400FEF20  // Unique ID 0
+#define SYSCTL_UNIQUEID1        0x400FEF24  // Unique ID 1
+#define SYSCTL_UNIQUEID2        0x400FEF28  // Unique ID 2
+#define SYSCTL_UNIQUEID3        0x400FEF2C  // Unique ID 3
 #define SYSCTL_CCMCGREQ         0x44030204  // Cryptographic Modules Clock
                                             // Gating Request
 
@@ -666,10 +670,8 @@
 #define SYSCTL_DC1_ADC1         0x00020000  // ADC Module 1 Present
 #define SYSCTL_DC1_ADC0         0x00010000  // ADC Module 0 Present
 #define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider
-#define SYSCTL_DC1_MINSYSDIV_80 0x00001000  // Specifies an 80-MHz CPU clock
+#define SYSCTL_DC1_MINSYSDIV_80 0x00002000  // Specifies an 80-MHz CPU clock
                                             // with a PLL divider of 2.5
-#define SYSCTL_DC1_MINSYSDIV_66 0x00002000  // Specifies a 66-MHz CPU clock
-                                            // with a PLL divider of 3
 #define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz CPU clock
                                             // with a PLL divider of 4
 #define SYSCTL_DC1_MINSYSDIV_40 0x00004000  // Specifies a 40-MHz CPU clock
@@ -1040,7 +1042,6 @@
 //*****************************************************************************
 #define SYSCTL_RESC_MOSCFAIL    0x00010000  // MOSC Failure Reset
 #define SYSCTL_RESC_HSSR        0x00001000  // HSSR Reset
-#define SYSCTL_RESC_HIB         0x00000040  // HIB Reset
 #define SYSCTL_RESC_WDT1        0x00000020  // Watchdog Timer 1 Reset
 #define SYSCTL_RESC_SW          0x00000010  // Software Reset
 #define SYSCTL_RESC_WDT0        0x00000008  // Watchdog Timer 0 Reset
@@ -3660,6 +3661,42 @@
 #define SYSCTL_PREMAC_R0        0x00000001  // Ethernet MAC Module 0 Peripheral
                                             // Ready
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_UNIQUEID0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_UNIQUEID0_ID_M   0xFFFFFFFF  // Unique ID
+#define SYSCTL_UNIQUEID0_ID_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_UNIQUEID1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_UNIQUEID1_ID_M   0xFFFFFFFF  // Unique ID
+#define SYSCTL_UNIQUEID1_ID_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_UNIQUEID2
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_UNIQUEID2_ID_M   0xFFFFFFFF  // Unique ID
+#define SYSCTL_UNIQUEID2_ID_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_UNIQUEID3
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_UNIQUEID3_ID_M   0xFFFFFFFF  // Unique ID
+#define SYSCTL_UNIQUEID3_ID_S   0
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SYSCTL_CCMCGREQ
@@ -3690,6 +3727,14 @@
                                 0x000A0000  // Tiva(TM) C Series TM4C129-class
                                             // microcontrollers
 
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RESC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_HIB         0x00000040  // HIB Reset
+
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the SYSCTL_PWRTC

bsp/tm4c129x/libraries/inc/hw_sysexc.h

@@ -2,7 +2,7 @@
 //
 // hw_sysexc.h - Macros used when accessing the system exception module.
 //
-// Copyright (c) 2011-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2011-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_timer.h

@@ -2,7 +2,7 @@
 //
 // hw_timer.h - Defines and macros used when accessing the timer.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_types.h

@@ -2,7 +2,7 @@
 //
 // hw_types.h - Common types and macros.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/tm4c129x/libraries/inc/hw_uart.h

@@ -2,7 +2,7 @@
 //
 // hw_uart.h - Macros and defines used when accessing the UART hardware.
 //
-// Copyright (c) 2005-2014 Texas Instruments Incorporated.  All rights reserved.
+// Copyright (c) 2005-2017 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
 //   Redistribution and use in source and binary forms, with or without
@@ -33,7 +33,7 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // 
-// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
 //
 //*****************************************************************************