update at91sam9260 project directory structure.

bsp/at91sam9260/SConscript

@@ -1,24 +1,14 @@
-import rtconfig
+# for module compiling
+import os
 Import('RTT_ROOT')
-from building import *
 
-src_bsp = ['application.c', 'startup.c', 'board.c']
-src_drv = ['usart.c']
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
 
-if GetDepend('RT_USING_LED'):
-	src_drv += ['led.c']
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
 
-if GetDepend('RT_USING_SDIO'):
-	src_drv += ['at91_mci.c']
-
-if GetDepend('RT_USING_LWIP'):
-	src_drv += ['macb.c']
-
-if GetDepend('RT_USING_I2C') and GetDepend('RT_USING_I2C_BITOPS'):
-	src_drv += ['at91_i2c_gpio.c']
-
-src	= File(src_bsp + src_drv)
-CPPPATH = [RTT_ROOT + '/bsp/at91sam9260']
-group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
+Return('objs')

bsp/at91sam9260/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/at91sam9260/drivers/SConscript

@@ -0,0 +1,31 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'drivers')
+
+# add the general drvers.
+src = Split("""
+board.c
+usart.c
+""")
+
+# add Ethernet drvers.
+if GetDepend('RT_USING_LED'):
+	src += ['led.c']
+
+if GetDepend('RT_USING_SDIO'):
+	src += ['at91_mci.c']
+
+if GetDepend('RT_USING_LWIP'):
+	src += ['macb.c']
+
+if GetDepend('RT_USING_I2C') and GetDepend('RT_USING_I2C_BITOPS'):
+	src += ['at91_i2c_gpio.c']
+
+    
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/at91sam9260/drivers/board.c

@@ -16,6 +16,7 @@
 #include <rthw.h>
 
 #include "board.h"
+#include <mmu.h>
 
 /**
  * @addtogroup at91sam9260
@@ -24,13 +25,21 @@
 
 
 extern void rt_hw_clock_init(void);
-extern void rt_hw_mmu_init(void);
 
 extern void rt_hw_get_clock(void);
 extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
 extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
 extern void rt_dbgu_isr(void);
 
+static struct mem_desc at91_mem_desc[] = {
+	{ 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB },     /* None cached for 4G memory */
+	{ 0x20000000, 0x24000000-1, 0x20000000, RW_CB },     /* 64M cached SDRAM memory */
+	{ 0x00000000, 0x100000, 0x20000000, RW_CB },         /* isr vector table */
+	{ 0x90000000, 0x90400000 - 1, 0x00200000, RW_NCNB }, /* 4K SRAM0 + 4k SRAM1 */
+	{ 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB }   /* 64M none-cached SDRAM memory */
+};
+
+
 #define PIT_CPIV(x)	((x) & AT91_PIT_CPIV)
 #define PIT_PICNT(x)	(((x) & AT91_PIT_PICNT) >> 20)
 
@@ -132,7 +141,7 @@ void rt_hw_board_init()
 	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 
 	/* initialize mmu */
-	rt_hw_mmu_init();
+	rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
 
 	/* initialize timer0 */
 	rt_hw_timer_init();

bsp/at91sam9260/platform/SConscript

@@ -0,0 +1,26 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd  = GetCurrentDir()
+CPPPATH = [cwd]
+
+# The set of source files associated with this SConscript file.
+if rtconfig.PLATFORM == 'armcc':
+	src = Glob('*.c') + Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+	src = Glob('*.c') + Glob('*_gcc.S') + Glob('*_init.S')
+
+if rtconfig.PLATFORM == 'iar':
+	src = Glob('*.c') + Glob('*_iar.S')
+
+if rtconfig.PLATFORM == 'cl':
+	src = Glob('*.c')
+
+if rtconfig.PLATFORM == 'mingw':
+	src = Glob('*.c')
+
+group = DefineGroup('platform', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/at91sam9260/platform/reset.c

@@ -0,0 +1,34 @@
+/*
+ * File      : reset.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-01-13     weety      modified from mini2440
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "at91sam926x.h"
+
+/**
+ * @addtogroup AT91SAM926X
+ */
+/*@{*/
+
+void machine_reset(void)
+{
+	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
+}
+
+void machine_shutdown(void)
+{
+	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
+/*@}*/

bsp/at91sam9260/platform/trap.c

@@ -156,7 +156,6 @@ void rt_hw_trap_irq()
 		at91_sys_write(AT91_AIC_EOICR, 0);
 		return;
 	}
-	//at91_sys_write(AT91_AIC_EOICR, 0x55555555);
 	
 	/* get interrupt service routine */
 	isr_func = irq_desc[irq].handler;

bsp/at91sam9260/rtconfig.py

@@ -2,7 +2,7 @@ import os
 
 # toolchains options
 ARCH     = 'arm'
-CPU      = 'at91sam926x'
+CPU      = 'arm926'
 TextBase = '0x20000000'
 
 CROSS_TOOL 	= 'gcc'

libcpu/arm/arm926/cpuport.c

@@ -14,16 +14,13 @@
 
 #include <rthw.h>
 #include <rtthread.h>
-#include "at91sam926x.h"
-
-/**
- * @addtogroup AT91SAM926X
- */
-/*@{*/
 
 #define ICACHE_MASK	(rt_uint32_t)(1 << 12)
 #define DCACHE_MASK	(rt_uint32_t)(1 << 2)
 
+extern void machine_reset(void);
+extern void machine_shutdown(void);
+
 #ifdef __GNUC__
 rt_inline rt_uint32_t cp15_rd(void)
 {
@@ -148,16 +145,6 @@ rt_base_t rt_hw_cpu_dcache_status()
 	return (cp15_rd() & DCACHE_MASK);
 }
 
-static void at91sam9260_reset(void)
-{
-	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
-}
-
-static void at91sam9260_poweroff(void)
-{
-	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
-
 /**
  * reset cpu by dog's time-out
  *
@@ -166,7 +153,7 @@ void rt_hw_cpu_reset()
 {
 	
 	rt_kprintf("Restarting system...\n");
-	at91sam9260_reset();
+	machine_reset();
 
 	while(1);	/* loop forever and wait for reset to happen */
 
@@ -183,7 +170,7 @@ void rt_hw_cpu_shutdown()
 	rt_kprintf("shutdown...\n");
 
 	level = rt_hw_interrupt_disable();
-	at91sam9260_poweroff();
+	machine_shutdown();
 	while (level)
 	{
 		RT_ASSERT(0);

libcpu/arm/arm926/mmu.c

@@ -11,31 +11,7 @@
  * Date           Author       Notes
  */
 
-#include <rtthread.h>
-
-#define CACHE_LINE_SIZE	32
-
-#define DESC_SEC		(0x2|(1<<4))
-#define CB				(3<<2)  //cache_on, write_back
-#define CNB				(2<<2)  //cache_on, write_through
-#define NCB				(1<<2)  //cache_off,WR_BUF on
-#define NCNB			(0<<2)  //cache_off,WR_BUF off
-#define AP_RW			(3<<10) //supervisor=RW, user=RW
-#define AP_RO			(2<<10) //supervisor=RW, user=RO
-
-#define DOMAIN_FAULT	(0x0)
-#define DOMAIN_CHK		(0x1)
-#define DOMAIN_NOTCHK	(0x3)
-#define DOMAIN0			(0x0<<5)
-#define DOMAIN1			(0x1<<5)
-
-#define DOMAIN0_ATTR	(DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR	(DOMAIN_FAULT<<2)
-
-#define RW_CB		(AP_RW|DOMAIN0|CB|DESC_SEC)		/* Read/Write, cache, write back */
-#define RW_CNB		(AP_RW|DOMAIN0|CNB|DESC_SEC)	/* Read/Write, cache, write through */
-#define RW_NCNB		(AP_RW|DOMAIN0|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
-#define RW_FAULT	(AP_RW|DOMAIN1|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
+#include "mmu.h"
 
 #ifdef __CC_ARM
 void mmu_setttbase(rt_uint32_t i)
@@ -459,7 +435,7 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrS
     }
 }
 
-void rt_hw_mmu_init(void)
+void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size)
 {
 	/* disable I/D cache */
 	mmu_disable_dcache();
@@ -468,11 +444,12 @@ void rt_hw_mmu_init(void)
 	mmu_invalidate_tlb();
 
 	/* set page table */
-	mmu_setmtt(0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB); /* None cached for 4G memory */
-  	mmu_setmtt(0x20000000, 0x24000000-1, 0x20000000, RW_CB); /* 64M cached SDRAM memory */
-	mmu_setmtt(0x00000000, 0x100000, 0x20000000, RW_CB); /* isr vector table */
-	mmu_setmtt(0x90000000, 0x90400000 - 1, 0x00200000, RW_NCNB); /* 4K SRAM0 + 4k SRAM1 */
-	mmu_setmtt(0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB); /* 64M none-cached SDRAM memory */
+	for (; size > 0; size--)
+	{
+		mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, 
+			mdesc->paddr_start, mdesc->attr);
+		mdesc++;
+	}
 
 	/* set MMU table address */
 	mmu_setttbase((rt_uint32_t)_page_table);

libcpu/arm/arm926/mmu.h

@@ -0,0 +1,53 @@
+/*
+ * File      : mmu.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#ifndef __MMU_H__
+#define __MMU_H__
+
+#include <rtthread.h>
+
+#define CACHE_LINE_SIZE	32
+
+#define DESC_SEC		(0x2|(1<<4))
+#define CB				(3<<2)  //cache_on, write_back
+#define CNB				(2<<2)  //cache_on, write_through
+#define NCB				(1<<2)  //cache_off,WR_BUF on
+#define NCNB			(0<<2)  //cache_off,WR_BUF off
+#define AP_RW			(3<<10) //supervisor=RW, user=RW
+#define AP_RO			(2<<10) //supervisor=RW, user=RO
+
+#define DOMAIN_FAULT	(0x0)
+#define DOMAIN_CHK		(0x1)
+#define DOMAIN_NOTCHK	(0x3)
+#define DOMAIN0			(0x0<<5)
+#define DOMAIN1			(0x1<<5)
+
+#define DOMAIN0_ATTR	(DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR	(DOMAIN_FAULT<<2)
+
+#define RW_CB		(AP_RW|DOMAIN0|CB|DESC_SEC)		/* Read/Write, cache, write back */
+#define RW_CNB		(AP_RW|DOMAIN0|CNB|DESC_SEC)	/* Read/Write, cache, write through */
+#define RW_NCNB		(AP_RW|DOMAIN0|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
+#define RW_FAULT	(AP_RW|DOMAIN1|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
+
+struct mem_desc {
+	rt_uint32_t vaddr_start;
+	rt_uint32_t vaddr_end;
+	rt_uint32_t paddr_start;
+	rt_uint32_t attr;
+};
+
+void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
+
+#endif
+