Fixed sample rate not set correctly under slave I2S mode.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@530 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong
parent
acd0943ff8
commit
3a72099612
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@ -97,49 +97,49 @@ static void GPIO_Configuration(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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/* Disable the JTAG interface and enable the SWJ interface */
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GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
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/* Disable the JTAG interface and enable the SWJ interface */
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GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
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/* PC5 CODEC CS */
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GPIO_InitStructure.GPIO_Pin = CODEC_CSB_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_Init(CODEC_CSB_PORT, &GPIO_InitStructure);
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/* PC5 CODEC CS */
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GPIO_InitStructure.GPIO_Pin = CODEC_CSB_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_Init(CODEC_CSB_PORT, &GPIO_InitStructure);
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// WS
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GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
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// WS
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GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
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#if CODEC_MASTER_MODE
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
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#else
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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#endif
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GPIO_Init(CODEC_I2S_WS_PORT, &GPIO_InitStructure);
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GPIO_Init(CODEC_I2S_WS_PORT, &GPIO_InitStructure);
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// CK
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GPIO_InitStructure.GPIO_Pin = CODEC_I2S_CK_PIN;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
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// CK
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GPIO_InitStructure.GPIO_Pin = CODEC_I2S_CK_PIN;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
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#if CODEC_MASTER_MODE
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
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#else
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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#endif
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GPIO_Init(CODEC_I2S_CK_PORT, &GPIO_InitStructure);
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GPIO_Init(CODEC_I2S_CK_PORT, &GPIO_InitStructure);
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// SD
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GPIO_InitStructure.GPIO_Pin = CODEC_I2S_SD_PIN;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_Init(CODEC_I2S_SD_PORT, &GPIO_InitStructure);
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// SD
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GPIO_InitStructure.GPIO_Pin = CODEC_I2S_SD_PIN;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_Init(CODEC_I2S_SD_PORT, &GPIO_InitStructure);
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#ifdef CODEC_USE_MCO
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/* MCO configure */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA,&GPIO_InitStructure);
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/* MCO configure */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA,&GPIO_InitStructure);
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RCC_MCOConfig(RCC_MCO_HSE);
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RCC_MCOConfig(RCC_MCO_HSE);
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#endif
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}
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@ -147,132 +147,132 @@ static void DMA_Configuration(rt_uint32_t addr, rt_size_t size)
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{
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DMA_InitTypeDef DMA_InitStructure;
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/* DMA Channel configuration ----------------------------------------------*/
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DMA_Cmd(CODEC_I2S_DMA, DISABLE);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&(CODEC_I2S_PORT->DR));
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DMA_InitStructure.DMA_MemoryBaseAddr = (u32) addr;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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DMA_InitStructure.DMA_BufferSize = size;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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DMA_Init(CODEC_I2S_DMA, &DMA_InitStructure);
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/* DMA Channel configuration ----------------------------------------------*/
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DMA_Cmd(CODEC_I2S_DMA, DISABLE);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&(CODEC_I2S_PORT->DR));
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DMA_InitStructure.DMA_MemoryBaseAddr = (u32) addr;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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DMA_InitStructure.DMA_BufferSize = size;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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DMA_Init(CODEC_I2S_DMA, &DMA_InitStructure);
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/* Enable SPI DMA Tx request */
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SPI_I2S_DMACmd(CODEC_I2S_PORT, SPI_I2S_DMAReq_Tx, ENABLE);
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/* Enable SPI DMA Tx request */
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SPI_I2S_DMACmd(CODEC_I2S_PORT, SPI_I2S_DMAReq_Tx, ENABLE);
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DMA_ITConfig(CODEC_I2S_DMA, DMA_IT_TC, ENABLE);
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DMA_Cmd(CODEC_I2S_DMA, ENABLE);
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DMA_ITConfig(CODEC_I2S_DMA, DMA_IT_TC, ENABLE);
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DMA_Cmd(CODEC_I2S_DMA, ENABLE);
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}
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static void I2S_Configuration(uint32_t I2S_AudioFreq)
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{
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I2S_InitTypeDef I2S_InitStructure;
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I2S_InitTypeDef I2S_InitStructure;
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/* I2S peripheral configuration */
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I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
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I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
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I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
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I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq;
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I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
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/* I2S peripheral configuration */
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I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
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I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
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I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
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I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq;
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I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
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/* I2S2 configuration */
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/* I2S2 configuration */
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#if CODEC_MASTER_MODE
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I2S_InitStructure.I2S_Mode = I2S_Mode_SlaveTx;
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I2S_InitStructure.I2S_Mode = I2S_Mode_SlaveTx;
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#else
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I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
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I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
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#endif
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I2S_Init(CODEC_I2S_PORT, &I2S_InitStructure);
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I2S_Init(CODEC_I2S_PORT, &I2S_InitStructure);
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}
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uint8_t SPI_WriteByte(unsigned char data)
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{
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//Wait until the transmit buffer is empty
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while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
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// Send the byte
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SPI_I2S_SendData(SPI1, data);
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//Wait until the transmit buffer is empty
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while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
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// Send the byte
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SPI_I2S_SendData(SPI1, data);
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//Wait until a data is received
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while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
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// Get the received data
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data = SPI_I2S_ReceiveData(SPI1);
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//Wait until a data is received
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while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
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// Get the received data
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data = SPI_I2S_ReceiveData(SPI1);
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// Return the shifted data
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return data;
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// Return the shifted data
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return data;
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}
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static void codec_send(rt_uint16_t s_data)
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{
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codec_reset_csb();
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SPI_WriteByte((s_data >> 8) & 0xFF);
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SPI_WriteByte(s_data & 0xFF);
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codec_set_csb();
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codec_reset_csb();
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SPI_WriteByte((s_data >> 8) & 0xFF);
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SPI_WriteByte(s_data & 0xFF);
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codec_set_csb();
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}
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static rt_err_t codec_init(rt_device_t dev)
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{
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codec_send(REG_SOFTWARE_RESET);
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codec_send(REG_SOFTWARE_RESET);
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// 1.5x boost power up sequence.
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// Mute all outputs.
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codec_send(REG_LOUT1_VOL | LOUT1MUTE);
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codec_send(REG_ROUT1_VOL | ROUT1MUTE);
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codec_send(REG_LOUT2_VOL | LOUT2MUTE);
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codec_send(REG_ROUT2_VOL | ROUT2MUTE);
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// Enable unused output chosen from L/ROUT2, OUT3 or OUT4.
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codec_send(REG_POWER_MANAGEMENT3 | OUT4EN);
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// Set BUFDCOPEN=1 and BUFIOEN=1 in register R1
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN);
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// Set SPKBOOST=1 in register R49.
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codec_send(REG_OUTPUT | SPKBOOST);
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// Set VMIDSEL[1:0] to required value in register R1.
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K);
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// Set L/RMIXEN=1 and DACENL/R=1 in register R3.
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codec_send(REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR);
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// Set BIASEN=1 in register R1.
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K | BIASEN);
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// Set L/ROUT2EN=1 in register R3.
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codec_send(REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR | LOUT2EN | ROUT2EN);
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// Enable other mixers as required.
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// Enable other outputs as required.
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codec_send(REG_POWER_MANAGEMENT2 | LOUT1EN | ROUT1EN | BOOSTENL | BOOSTENR | INPPGAENL | INPPGAENR);
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// 1.5x boost power up sequence.
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// Mute all outputs.
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codec_send(REG_LOUT1_VOL | LOUT1MUTE);
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codec_send(REG_ROUT1_VOL | ROUT1MUTE);
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codec_send(REG_LOUT2_VOL | LOUT2MUTE);
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codec_send(REG_ROUT2_VOL | ROUT2MUTE);
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// Enable unused output chosen from L/ROUT2, OUT3 or OUT4.
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codec_send(REG_POWER_MANAGEMENT3 | OUT4EN);
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// Set BUFDCOPEN=1 and BUFIOEN=1 in register R1
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN);
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// Set SPKBOOST=1 in register R49.
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codec_send(REG_OUTPUT | SPKBOOST);
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// Set VMIDSEL[1:0] to required value in register R1.
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K);
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// Set L/RMIXEN=1 and DACENL/R=1 in register R3.
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codec_send(REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR);
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// Set BIASEN=1 in register R1.
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K | BIASEN);
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// Set L/ROUT2EN=1 in register R3.
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codec_send(REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR | LOUT2EN | ROUT2EN);
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// Enable other mixers as required.
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// Enable other outputs as required.
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codec_send(REG_POWER_MANAGEMENT2 | LOUT1EN | ROUT1EN | BOOSTENL | BOOSTENR | INPPGAENL | INPPGAENR);
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// Digital inferface setup.
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codec_send(REG_AUDIO_INTERFACE | BCP_NORMAL | LRP_NORMAL | WL_16BITS | FMT_I2S);
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// Digital inferface setup.
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codec_send(REG_AUDIO_INTERFACE | BCP_NORMAL | LRP_NORMAL | WL_16BITS | FMT_I2S);
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// PLL setup.
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// fs = 44.1KHz * 256fs = 11.2896MHz
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// F_PLL = 11.2896MHz * 4 * 2 = 90.3168MHz
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// R = 90.3168MHz / 12.288MHz = 7.35
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// PLL_N = 7
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// PLL_K = 0x59999A (0x5A5A5A for STM32's 44.117KHz fs generated from 72MHz clock)
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codec_send(REG_PLL_N | 7);
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// PLL setup.
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// fs = 44.1KHz * 256fs = 11.2896MHz
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// F_PLL = 11.2896MHz * 4 * 2 = 90.3168MHz
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// R = 90.3168MHz / 12.288MHz = 7.35
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// PLL_N = 7
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// PLL_K = 0x59999A (0x5A5A5A for STM32's 44.117KHz fs generated from 72MHz clock)
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codec_send(REG_PLL_N | 7);
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#if CODEC_MASTER_MODE
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codec_send(REG_PLL_K1 | 0x16);
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codec_send(REG_PLL_K2 | 0xCC);
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codec_send(REG_PLL_K3 | 0x19A);
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codec_send(REG_PLL_K1 | 0x16);
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codec_send(REG_PLL_K2 | 0xCC);
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codec_send(REG_PLL_K3 | 0x19A);
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#else
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codec_send(REG_PLL_K1 | 0x16);
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codec_send(REG_PLL_K2 | 0x12D);
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codec_send(REG_PLL_K3 | 0x5A);
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codec_send(REG_PLL_K1 | 0x16);
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codec_send(REG_PLL_K2 | 0x12D);
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codec_send(REG_PLL_K3 | 0x5A);
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#endif
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K | BIASEN | PLLEN);
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codec_send(r06);
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K | BIASEN | PLLEN);
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codec_send(r06);
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// Enable DAC 128x oversampling.
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codec_send(REG_DAC | DACOSR128);
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// Enable DAC 128x oversampling.
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codec_send(REG_DAC | DACOSR128);
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// Set LOUT2/ROUT2 in BTL operation.
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codec_send(REG_BEEP | INVROUT2);
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// Set LOUT2/ROUT2 in BTL operation.
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codec_send(REG_BEEP | INVROUT2);
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// Set output volume.
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vol(25);
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// Set output volume.
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vol(25);
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return RT_EOK;
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return RT_EOK;
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}
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// Exported functions
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@ -280,136 +280,136 @@ static rt_err_t codec_init(rt_device_t dev)
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void vol(uint16_t v)
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{
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v = (v & VOL_MASK) << VOL_POS;
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codec_send(REG_LOUT1_VOL | v);
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codec_send(REG_ROUT1_VOL | HPVU | v);
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codec_send(REG_LOUT2_VOL | v);
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codec_send(REG_ROUT2_VOL | SPKVU | v);
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v = (v & VOL_MASK) << VOL_POS;
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codec_send(REG_LOUT1_VOL | v);
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codec_send(REG_ROUT1_VOL | HPVU | v);
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codec_send(REG_LOUT2_VOL | v);
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codec_send(REG_ROUT2_VOL | SPKVU | v);
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}
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void eq(codec_eq_args_t args)
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{
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switch (args->channel)
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{
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case 1:
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codec_send(REG_EQ1 | ((args->frequency & EQC_MASK) << EQC_POS) | ((args->gain & EQG_MASK) << EQG_POS) | (args->mode_bandwidth ? EQ3DMODE_DAC : EQ3DMODE_ADC));
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break;
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switch (args->channel)
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{
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case 1:
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codec_send(REG_EQ1 | ((args->frequency & EQC_MASK) << EQC_POS) | ((args->gain & EQG_MASK) << EQG_POS) | (args->mode_bandwidth ? EQ3DMODE_DAC : EQ3DMODE_ADC));
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break;
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case 2:
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codec_send(REG_EQ2 | ((args->frequency & EQC_MASK) << EQC_POS) | ((args->gain & EQG_MASK) << EQG_POS) | (args->mode_bandwidth ? EQ2BW_WIDE : EQ2BW_NARROW));
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break;
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case 2:
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codec_send(REG_EQ2 | ((args->frequency & EQC_MASK) << EQC_POS) | ((args->gain & EQG_MASK) << EQG_POS) | (args->mode_bandwidth ? EQ2BW_WIDE : EQ2BW_NARROW));
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break;
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case 3:
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codec_send(REG_EQ3 | ((args->frequency & EQC_MASK) << EQC_POS) | ((args->gain & EQG_MASK) << EQG_POS) | (args->mode_bandwidth ? EQ3BW_WIDE : EQ3BW_NARROW));
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break;
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case 3:
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codec_send(REG_EQ3 | ((args->frequency & EQC_MASK) << EQC_POS) | ((args->gain & EQG_MASK) << EQG_POS) | (args->mode_bandwidth ? EQ3BW_WIDE : EQ3BW_NARROW));
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break;
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case 4:
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codec_send(REG_EQ4 | ((args->frequency & EQC_MASK) << EQC_POS) | ((args->gain & EQG_MASK) << EQG_POS) | (args->mode_bandwidth ? EQ4BW_WIDE : EQ4BW_NARROW));
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break;
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case 4:
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codec_send(REG_EQ4 | ((args->frequency & EQC_MASK) << EQC_POS) | ((args->gain & EQG_MASK) << EQG_POS) | (args->mode_bandwidth ? EQ4BW_WIDE : EQ4BW_NARROW));
|
||||
break;
|
||||
|
||||
case 5:
|
||||
codec_send(REG_EQ5 | ((args->frequency & EQC_MASK) << EQC_POS) | ((args->gain & EQG_MASK) << EQG_POS));
|
||||
break;
|
||||
}
|
||||
case 5:
|
||||
codec_send(REG_EQ5 | ((args->frequency & EQC_MASK) << EQC_POS) | ((args->gain & EQG_MASK) << EQG_POS));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// TODO eq1() ~ eq5() are just for testing. To be removed.
|
||||
void eq1(uint8_t freq, uint8_t gain, uint8_t mode)
|
||||
{
|
||||
codec_send(REG_EQ1 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS) | (mode ? EQ3DMODE_DAC : EQ3DMODE_ADC));
|
||||
codec_send(REG_EQ1 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS) | (mode ? EQ3DMODE_DAC : EQ3DMODE_ADC));
|
||||
}
|
||||
|
||||
void eq2(uint8_t freq, uint8_t gain, uint8_t bw)
|
||||
{
|
||||
codec_send(REG_EQ2 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS) | (bw ? EQ2BW_WIDE : EQ2BW_NARROW));
|
||||
codec_send(REG_EQ2 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS) | (bw ? EQ2BW_WIDE : EQ2BW_NARROW));
|
||||
}
|
||||
|
||||
void eq3(uint8_t freq, uint8_t gain, uint8_t bw)
|
||||
{
|
||||
codec_send(REG_EQ3 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS) | (bw ? EQ3BW_WIDE : EQ3BW_NARROW));
|
||||
codec_send(REG_EQ3 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS) | (bw ? EQ3BW_WIDE : EQ3BW_NARROW));
|
||||
}
|
||||
|
||||
void eq4(uint8_t freq, uint8_t gain, uint8_t bw)
|
||||
{
|
||||
codec_send(REG_EQ4 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS) | (bw ? EQ4BW_WIDE : EQ4BW_NARROW));
|
||||
codec_send(REG_EQ4 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS) | (bw ? EQ4BW_WIDE : EQ4BW_NARROW));
|
||||
}
|
||||
|
||||
void eq5(uint8_t freq, uint8_t gain)
|
||||
{
|
||||
codec_send(REG_EQ2 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS));
|
||||
codec_send(REG_EQ2 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS));
|
||||
}
|
||||
|
||||
void eq3d(uint8_t depth)
|
||||
{
|
||||
codec_send(REG_3D | ((depth & DEPTH3D_MASK) << DEPTH3D_POS));
|
||||
codec_send(REG_3D | ((depth & DEPTH3D_MASK) << DEPTH3D_POS));
|
||||
}
|
||||
|
||||
rt_err_t sample_rate(int sr)
|
||||
{
|
||||
uint16_t r07 = REG_ADDITIONAL;
|
||||
uint16_t r07 = REG_ADDITIONAL;
|
||||
|
||||
switch (sr)
|
||||
{
|
||||
case 8000:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV6 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_8KHZ;
|
||||
break;
|
||||
switch (sr)
|
||||
{
|
||||
case 8000:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV6 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_8KHZ;
|
||||
break;
|
||||
|
||||
case 11025:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV8 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_12KHZ;
|
||||
break;
|
||||
case 11025:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV8 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_12KHZ;
|
||||
break;
|
||||
|
||||
#if CODEC_MASTER_MODE
|
||||
case 12000:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV4 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_12KHZ;
|
||||
break;
|
||||
case 12000:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV4 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_12KHZ;
|
||||
break;
|
||||
#endif
|
||||
|
||||
case 16000:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV3 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_16KHZ;
|
||||
break;
|
||||
case 16000:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV3 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_16KHZ;
|
||||
break;
|
||||
|
||||
case 22050:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV4 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_24KHZ;
|
||||
break;
|
||||
case 22050:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV4 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_24KHZ;
|
||||
break;
|
||||
|
||||
#if CODEC_MASTER_MODE
|
||||
case 24000:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV2 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_24KHZ;
|
||||
break;
|
||||
case 24000:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV2 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_24KHZ;
|
||||
break;
|
||||
#endif
|
||||
|
||||
case 32000:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1_5 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_32KHZ;
|
||||
break;
|
||||
case 32000:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1_5 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_32KHZ;
|
||||
break;
|
||||
|
||||
case 44100:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV2 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_48KHZ;
|
||||
break;
|
||||
case 44100:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV2 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_48KHZ;
|
||||
break;
|
||||
|
||||
case 48000:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_48KHZ;
|
||||
break;
|
||||
case 48000:
|
||||
r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1 | BCLK_DIV8 | (r06 & MS);
|
||||
r07 |= SR_48KHZ;
|
||||
break;
|
||||
|
||||
default:
|
||||
return RT_ERROR;
|
||||
}
|
||||
codec_send(r06);
|
||||
codec_send(r07);
|
||||
default:
|
||||
return RT_ERROR;
|
||||
}
|
||||
codec_send(r06);
|
||||
codec_send(r07);
|
||||
|
||||
#if !CODEC_MASTER_MODE
|
||||
I2S_Configuration((uint32_t) sr);
|
||||
I2S_Configuration((uint32_t) sr);
|
||||
#endif
|
||||
|
||||
return RT_EOK;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
FINSH_FUNCTION_EXPORT(vol, Set volume);
|
||||
|
|
@ -424,217 +424,219 @@ FINSH_FUNCTION_EXPORT(sample_rate, Set sample rate);
|
|||
static rt_err_t codec_open(rt_device_t dev, rt_uint16_t oflag)
|
||||
{
|
||||
#if !CODEC_MASTER_MODE
|
||||
/* enable I2S */
|
||||
I2S_Cmd(CODEC_I2S_PORT, ENABLE);
|
||||
/* enable I2S */
|
||||
I2S_Cmd(CODEC_I2S_PORT, ENABLE);
|
||||
#endif
|
||||
|
||||
return RT_EOK;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t codec_close(rt_device_t dev)
|
||||
{
|
||||
#if CODEC_MASTER_MODE
|
||||
if (r06 & MS)
|
||||
{
|
||||
CODEC_I2S_DMA->CCR &= ~DMA_CCR1_EN;
|
||||
while ((CODEC_I2S_PORT->SR & SPI_I2S_FLAG_TXE) == 0);
|
||||
while ((CODEC_I2S_PORT->SR & SPI_I2S_FLAG_BSY) != 0);
|
||||
CODEC_I2S_PORT->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
|
||||
if (r06 & MS)
|
||||
{
|
||||
CODEC_I2S_DMA->CCR &= ~DMA_CCR1_EN;
|
||||
while ((CODEC_I2S_PORT->SR & SPI_I2S_FLAG_TXE) == 0);
|
||||
while ((CODEC_I2S_PORT->SR & SPI_I2S_FLAG_BSY) != 0);
|
||||
CODEC_I2S_PORT->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
|
||||
|
||||
r06 &= ~MS;
|
||||
codec_send(r06);
|
||||
r06 &= ~MS;
|
||||
codec_send(r06);
|
||||
|
||||
/* remove all data node */
|
||||
if (codec.parent.tx_complete != RT_NULL)
|
||||
{
|
||||
rt_base_t level = rt_hw_interrupt_disable();
|
||||
/* remove all data node */
|
||||
if (codec.parent.tx_complete != RT_NULL)
|
||||
{
|
||||
rt_base_t level = rt_hw_interrupt_disable();
|
||||
|
||||
do
|
||||
{
|
||||
codec.parent.tx_complete(&codec.parent, codec.data_list[codec.read_index].data_ptr);
|
||||
codec.read_index++;
|
||||
if (codec.read_index >= DATA_NODE_MAX)
|
||||
{
|
||||
codec.read_index = 0;
|
||||
}
|
||||
}
|
||||
while (codec.read_index != codec.put_index);
|
||||
do
|
||||
{
|
||||
codec.parent.tx_complete(&codec.parent, codec.data_list[codec.read_index].data_ptr);
|
||||
codec.read_index++;
|
||||
if (codec.read_index >= DATA_NODE_MAX)
|
||||
{
|
||||
codec.read_index = 0;
|
||||
}
|
||||
}
|
||||
while (codec.read_index != codec.put_index);
|
||||
|
||||
rt_hw_interrupt_enable(level);
|
||||
}
|
||||
}
|
||||
rt_hw_interrupt_enable(level);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return RT_EOK;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t codec_control(rt_device_t dev, rt_uint8_t cmd, void *args)
|
||||
{
|
||||
switch (cmd)
|
||||
{
|
||||
case CODEC_CMD_RESET:
|
||||
codec_init(dev);
|
||||
break;
|
||||
switch (cmd)
|
||||
{
|
||||
case CODEC_CMD_RESET:
|
||||
codec_init(dev);
|
||||
break;
|
||||
|
||||
case CODEC_CMD_VOLUME:
|
||||
vol(*((uint16_t*) args));
|
||||
break;
|
||||
case CODEC_CMD_VOLUME:
|
||||
vol(*((uint16_t*) args));
|
||||
break;
|
||||
|
||||
case CODEC_CMD_SAMPLERATE:
|
||||
sample_rate(*((int*) args));
|
||||
break;
|
||||
case CODEC_CMD_SAMPLERATE:
|
||||
dev->close(dev);
|
||||
sample_rate(*((int*) args));
|
||||
dev->open(dev,0);
|
||||
break;
|
||||
|
||||
case CODEC_CMD_EQ:
|
||||
eq((codec_eq_args_t) args);
|
||||
break;
|
||||
case CODEC_CMD_EQ:
|
||||
eq((codec_eq_args_t) args);
|
||||
break;
|
||||
|
||||
case CODEC_CMD_3D:
|
||||
eq3d(*((uint8_t*) args));
|
||||
break;
|
||||
case CODEC_CMD_3D:
|
||||
eq3d(*((uint8_t*) args));
|
||||
break;
|
||||
|
||||
default:
|
||||
return RT_ERROR;
|
||||
}
|
||||
return RT_EOK;
|
||||
default:
|
||||
return RT_ERROR;
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t codec_write(rt_device_t dev, rt_off_t pos,
|
||||
const void* buffer, rt_size_t size)
|
||||
const void* buffer, rt_size_t size)
|
||||
{
|
||||
struct codec_device* device;
|
||||
struct codec_data_node* node;
|
||||
rt_uint32_t level;
|
||||
rt_uint16_t next_index;
|
||||
struct codec_device* device;
|
||||
struct codec_data_node* node;
|
||||
rt_uint32_t level;
|
||||
rt_uint16_t next_index;
|
||||
|
||||
device = (struct codec_device*) dev;
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
device = (struct codec_device*) dev;
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
|
||||
next_index = device->put_index + 1;
|
||||
if (next_index >= DATA_NODE_MAX)
|
||||
next_index = 0;
|
||||
next_index = device->put_index + 1;
|
||||
if (next_index >= DATA_NODE_MAX)
|
||||
next_index = 0;
|
||||
|
||||
/* check data_list full */
|
||||
if (next_index == device->read_index)
|
||||
{
|
||||
rt_set_errno(-RT_EFULL);
|
||||
return 0;
|
||||
}
|
||||
/* check data_list full */
|
||||
if (next_index == device->read_index)
|
||||
{
|
||||
rt_set_errno(-RT_EFULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
node = &device->data_list[device->put_index];
|
||||
device->put_index = next_index;
|
||||
level = rt_hw_interrupt_disable();
|
||||
node = &device->data_list[device->put_index];
|
||||
device->put_index = next_index;
|
||||
|
||||
/* set node attribute */
|
||||
node->data_ptr = (rt_uint16_t*) buffer;
|
||||
node->data_size = size >> 1; /* size is byte unit, convert to half word unit */
|
||||
/* set node attribute */
|
||||
node->data_ptr = (rt_uint16_t*) buffer;
|
||||
node->data_size = size >> 1; /* size is byte unit, convert to half word unit */
|
||||
|
||||
next_index = device->read_index + 1;
|
||||
if (next_index >= DATA_NODE_MAX)
|
||||
next_index = 0;
|
||||
next_index = device->read_index + 1;
|
||||
if (next_index >= DATA_NODE_MAX)
|
||||
next_index = 0;
|
||||
|
||||
/* check data list whether is empty */
|
||||
if (next_index == device->put_index)
|
||||
{
|
||||
DMA_Configuration((rt_uint32_t) node->data_ptr, node->data_size);
|
||||
/* check data list whether is empty */
|
||||
if (next_index == device->put_index)
|
||||
{
|
||||
DMA_Configuration((rt_uint32_t) node->data_ptr, node->data_size);
|
||||
|
||||
#if CODEC_MASTER_MODE
|
||||
if ((r06 & MS) == 0)
|
||||
{
|
||||
CODEC_I2S_PORT->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
||||
r06 |= MS;
|
||||
codec_send(r06);
|
||||
}
|
||||
if ((r06 & MS) == 0)
|
||||
{
|
||||
CODEC_I2S_PORT->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
||||
r06 |= MS;
|
||||
codec_send(r06);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
rt_hw_interrupt_enable(level);
|
||||
}
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
return size;
|
||||
return size;
|
||||
}
|
||||
|
||||
rt_err_t codec_hw_init(void)
|
||||
{
|
||||
rt_device_t dev;
|
||||
rt_device_t dev;
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(CODEC_I2S_RCC_APB1, ENABLE);
|
||||
RCC_AHBPeriphClockCmd(CODEC_I2S_RCC_AHB, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE);
|
||||
RCC_APB1PeriphClockCmd(CODEC_I2S_RCC_APB1, ENABLE);
|
||||
RCC_AHBPeriphClockCmd(CODEC_I2S_RCC_AHB, ENABLE);
|
||||
|
||||
NVIC_Configuration();
|
||||
GPIO_Configuration();
|
||||
I2S_Configuration(I2S_AudioFreq_44k);
|
||||
NVIC_Configuration();
|
||||
GPIO_Configuration();
|
||||
I2S_Configuration(I2S_AudioFreq_44k);
|
||||
|
||||
dev = (rt_device_t) &codec;
|
||||
dev->type = RT_Device_Class_Sound;
|
||||
dev->rx_indicate = RT_NULL;
|
||||
dev->tx_complete = RT_NULL;
|
||||
dev->init = codec_init;
|
||||
dev->open = codec_open;
|
||||
dev->close = codec_close;
|
||||
dev->read = RT_NULL;
|
||||
dev->write = codec_write;
|
||||
dev->control = codec_control;
|
||||
dev->private = RT_NULL;
|
||||
dev = (rt_device_t) &codec;
|
||||
dev->type = RT_Device_Class_Sound;
|
||||
dev->rx_indicate = RT_NULL;
|
||||
dev->tx_complete = RT_NULL;
|
||||
dev->init = codec_init;
|
||||
dev->open = codec_open;
|
||||
dev->close = codec_close;
|
||||
dev->read = RT_NULL;
|
||||
dev->write = codec_write;
|
||||
dev->control = codec_control;
|
||||
dev->private = RT_NULL;
|
||||
|
||||
/* set read_index and put index to 0 */
|
||||
codec.read_index = 0;
|
||||
codec.put_index = 0;
|
||||
/* set read_index and put index to 0 */
|
||||
codec.read_index = 0;
|
||||
codec.put_index = 0;
|
||||
|
||||
/* unselect */
|
||||
codec_set_csb();
|
||||
/* unselect */
|
||||
codec_set_csb();
|
||||
|
||||
/* register the device */
|
||||
return rt_device_register(&codec.parent, "snd", RT_DEVICE_FLAG_WRONLY | RT_DEVICE_FLAG_DMA_TX);
|
||||
/* register the device */
|
||||
return rt_device_register(&codec.parent, "snd", RT_DEVICE_FLAG_WRONLY | RT_DEVICE_FLAG_DMA_TX);
|
||||
}
|
||||
|
||||
void codec_dma_isr(void)
|
||||
{
|
||||
/* switch to next buffer */
|
||||
rt_uint16_t next_index;
|
||||
void* data_ptr;
|
||||
/* switch to next buffer */
|
||||
rt_uint16_t next_index;
|
||||
void* data_ptr;
|
||||
|
||||
next_index = codec.read_index + 1;
|
||||
if (next_index >= DATA_NODE_MAX)
|
||||
next_index = 0;
|
||||
next_index = codec.read_index + 1;
|
||||
if (next_index >= DATA_NODE_MAX)
|
||||
next_index = 0;
|
||||
|
||||
/* save current data pointer */
|
||||
data_ptr = codec.data_list[codec.read_index].data_ptr;
|
||||
/* save current data pointer */
|
||||
data_ptr = codec.data_list[codec.read_index].data_ptr;
|
||||
|
||||
codec.read_index = next_index;
|
||||
if (next_index != codec.put_index)
|
||||
{
|
||||
/* enable next dma request */
|
||||
DMA_Configuration((rt_uint32_t) codec.data_list[codec.read_index].data_ptr, codec.data_list[codec.read_index].data_size);
|
||||
codec.read_index = next_index;
|
||||
if (next_index != codec.put_index)
|
||||
{
|
||||
/* enable next dma request */
|
||||
DMA_Configuration((rt_uint32_t) codec.data_list[codec.read_index].data_ptr, codec.data_list[codec.read_index].data_size);
|
||||
|
||||
#if CODEC_MASTER_MODE
|
||||
if ((r06 & MS) == 0)
|
||||
{
|
||||
CODEC_I2S_PORT->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
||||
r06 |= MS;
|
||||
codec_send(r06);
|
||||
}
|
||||
if ((r06 & MS) == 0)
|
||||
{
|
||||
CODEC_I2S_PORT->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
||||
r06 |= MS;
|
||||
codec_send(r06);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
else
|
||||
{
|
||||
#if CODEC_MASTER_MODE
|
||||
if (r06 & MS)
|
||||
{
|
||||
CODEC_I2S_DMA->CCR &= ~DMA_CCR1_EN;
|
||||
while ((CODEC_I2S_PORT->SR & SPI_I2S_FLAG_TXE) == 0);
|
||||
while ((CODEC_I2S_PORT->SR & SPI_I2S_FLAG_BSY) != 0);
|
||||
CODEC_I2S_PORT->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
|
||||
if (r06 & MS)
|
||||
{
|
||||
CODEC_I2S_DMA->CCR &= ~DMA_CCR1_EN;
|
||||
while ((CODEC_I2S_PORT->SR & SPI_I2S_FLAG_TXE) == 0);
|
||||
while ((CODEC_I2S_PORT->SR & SPI_I2S_FLAG_BSY) != 0);
|
||||
CODEC_I2S_PORT->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
|
||||
|
||||
r06 &= ~MS;
|
||||
codec_send(r06);
|
||||
}
|
||||
r06 &= ~MS;
|
||||
codec_send(r06);
|
||||
}
|
||||
#endif
|
||||
|
||||
rt_kprintf("*\n");
|
||||
}
|
||||
rt_kprintf("*\n");
|
||||
}
|
||||
|
||||
/* notify transmitted complete. */
|
||||
if (codec.parent.tx_complete != RT_NULL)
|
||||
{
|
||||
codec.parent.tx_complete(&codec.parent, data_ptr);
|
||||
}
|
||||
/* notify transmitted complete. */
|
||||
if (codec.parent.tx_complete != RT_NULL)
|
||||
{
|
||||
codec.parent.tx_complete(&codec.parent, data_ptr);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue