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update stm32 porting. 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1506 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong@gmail.com 2011-06-15 00:30:35 +00:00
parent 782e8f01dc
commit 39d549ed72
13 changed files with 351 additions and 960 deletions
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158
libcpu/arm/stm32/context_gcc.S
View File

@ -23,10 +23,10 @@
.thumb .thumb
.text .text
.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ .equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */
.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ .equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */
.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
/* /*
* rt_base_t rt_hw_interrupt_disable(); * rt_base_t rt_hw_interrupt_disable();
@ -34,9 +34,9 @@
.global rt_hw_interrupt_disable .global rt_hw_interrupt_disable
.type rt_hw_interrupt_disable, %function .type rt_hw_interrupt_disable, %function
rt_hw_interrupt_disable: rt_hw_interrupt_disable:
MRS r0, PRIMASK MRS r0, PRIMASK
CPSID I CPSID I
BX LR BX LR
/* /*
* void rt_hw_interrupt_enable(rt_base_t level); * void rt_hw_interrupt_enable(rt_base_t level);
@ -44,8 +44,8 @@ rt_hw_interrupt_disable:
.global rt_hw_interrupt_enable .global rt_hw_interrupt_enable
.type rt_hw_interrupt_enable, %function .type rt_hw_interrupt_enable, %function
rt_hw_interrupt_enable: rt_hw_interrupt_enable:
MSR PRIMASK, r0 MSR PRIMASK, r0
BX LR BX LR
/* /*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
@ -59,25 +59,25 @@ rt_hw_interrupt_enable:
rt_hw_context_switch_interrupt: rt_hw_context_switch_interrupt:
rt_hw_context_switch: rt_hw_context_switch:
/* set rt_thread_switch_interrput_flag to 1 */ /* set rt_thread_switch_interrput_flag to 1 */
LDR r2, =rt_thread_switch_interrput_flag LDR r2, =rt_thread_switch_interrput_flag
LDR r3, [r2] LDR r3, [r2]
CMP r3, #1 CMP r3, #1
BEQ _reswitch BEQ _reswitch
MOV r3, #1 MOV r3, #1
STR r3, [r2] STR r3, [r2]
LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
STR r0, [r2] STR r0, [r2]
_reswitch: _reswitch:
LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
STR r1, [r2] STR r1, [r2]
LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
LDR r1, =NVIC_PENDSVSET LDR r1, =NVIC_PENDSVSET
STR r1, [r0] STR r1, [r0]
BX LR BX LR
/* r0 --> swith from thread stack /* r0 --> swith from thread stack
* r1 --> swith to thread stack * r1 --> swith to thread stack
@ -86,42 +86,42 @@ _reswitch:
.global rt_hw_pend_sv .global rt_hw_pend_sv
.type rt_hw_pend_sv, %function .type rt_hw_pend_sv, %function
rt_hw_pend_sv: rt_hw_pend_sv:
/* disable interrupt to protect context switch */ /* disable interrupt to protect context switch */
MRS r2, PRIMASK MRS r2, PRIMASK
CPSID I CPSID I
/* get rt_thread_switch_interrupt_flag */ /* get rt_thread_switch_interrupt_flag */
LDR r0, =rt_thread_switch_interrput_flag LDR r0, =rt_thread_switch_interrput_flag
LDR r1, [r0] LDR r1, [r0]
CBZ r1, pendsv_exit /* pendsv already handled */ CBZ r1, pendsv_exit /* pendsv already handled */
/* clear rt_thread_switch_interrput_flag to 0 */ /* clear rt_thread_switch_interrput_flag to 0 */
MOV r1, #0x00 MOV r1, #0x00
STR r1, [r0] STR r1, [r0]
LDR r0, =rt_interrupt_from_thread LDR r0, =rt_interrupt_from_thread
LDR r1, [r0] LDR r1, [r0]
CBZ r1, swtich_to_thread /* skip register save at the first time */ CBZ r1, swtich_to_thread /* skip register save at the first time */
MRS r1, psp /* get from thread stack pointer */ MRS r1, psp /* get from thread stack pointer */
STMFD r1!, {r4 - r11} /* push r4 - r11 register */ STMFD r1!, {r4 - r11} /* push r4 - r11 register */
LDR r0, [r0] LDR r0, [r0]
STR r1, [r0] /* update from thread stack pointer */ STR r1, [r0] /* update from thread stack pointer */
swtich_to_thread: swtich_to_thread:
LDR r1, =rt_interrupt_to_thread LDR r1, =rt_interrupt_to_thread
LDR r1, [r1] LDR r1, [r1]
LDR r1, [r1] /* load thread stack pointer */ LDR r1, [r1] /* load thread stack pointer */
LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */ LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */
MSR psp, r1 /* update stack pointer */ MSR psp, r1 /* update stack pointer */
pendsv_exit: pendsv_exit:
/* restore interrupt */ /* restore interrupt */
MSR PRIMASK, r2 MSR PRIMASK, r2
ORR lr, lr, #0x04 ORR lr, lr, #0x04
BX lr BX lr
/* /*
* void rt_hw_context_switch_to(rt_uint32 to); * void rt_hw_context_switch_to(rt_uint32 to);
@ -130,37 +130,49 @@ pendsv_exit:
.global rt_hw_context_switch_to .global rt_hw_context_switch_to
.type rt_hw_context_switch_to, %function .type rt_hw_context_switch_to, %function
rt_hw_context_switch_to: rt_hw_context_switch_to:
LDR r1, =rt_interrupt_to_thread LDR r1, =rt_interrupt_to_thread
STR r0, [r1] STR r0, [r1]
/* set from thread to 0 */ /* set from thread to 0 */
LDR r1, =rt_interrupt_from_thread LDR r1, =rt_interrupt_from_thread
MOV r0, #0x0 MOV r0, #0x0
STR r0, [r1] STR r0, [r1]
/* set interrupt flag to 1 */ /* set interrupt flag to 1 */
LDR r1, =rt_thread_switch_interrput_flag LDR r1, =rt_thread_switch_interrput_flag
MOV r0, #1 MOV r0, #1
STR r0, [r1] STR r0, [r1]
/* set the PendSV exception priority */ /* set the PendSV exception priority */
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] /* read */ LDR.W r2, [r0,#0x00] /* read */
ORR r1,r1,r2 /* modify */ ORR r1,r1,r2 /* modify */
STR r1, [r0] /* write-back */ STR r1, [r0] /* write-back */
LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
LDR r1, =NVIC_PENDSVSET LDR r1, =NVIC_PENDSVSET
STR r1, [r0] STR r1, [r0]
CPSIE I /* enable interrupts at processor level */ CPSIE I /* enable interrupts at processor level */
/* never reach here! */ /* never reach here! */
/* compatible with old version */ /* compatible with old version */
.global rt_hw_interrupt_thread_switch .global rt_hw_interrupt_thread_switch
.type rt_hw_interrupt_thread_switch, %function .type rt_hw_interrupt_thread_switch, %function
rt_hw_interrupt_thread_switch: rt_hw_interrupt_thread_switch:
BX lr BX lr
NOP NOP
.global rt_hw_hard_fault
.type rt_hw_hard_fault, %function
rt_hw_hard_fault:
/* get current context */
MRS r0, psp /* get fault thread stack pointer */
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {lr}
ORR lr, lr, #0x04
BX lr

147
libcpu/arm/stm32/context_iar.S
View File

@ -28,26 +28,26 @@ NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV excep
REQUIRE8 REQUIRE8
PRESERVE8 PRESERVE8
IMPORT rt_thread_switch_interrput_flag IMPORT rt_thread_switch_interrput_flag
IMPORT rt_interrupt_from_thread IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread IMPORT rt_interrupt_to_thread
;/* ;/*
; * rt_base_t rt_hw_interrupt_disable(); ; * rt_base_t rt_hw_interrupt_disable();
; */ ; */
EXPORT rt_hw_interrupt_disable EXPORT rt_hw_interrupt_disable
rt_hw_interrupt_disable: rt_hw_interrupt_disable:
MRS r0, PRIMASK MRS r0, PRIMASK
CPSID I CPSID I
BX LR BX LR
;/* ;/*
; * void rt_hw_interrupt_enable(rt_base_t level); ; * void rt_hw_interrupt_enable(rt_base_t level);
; */ ; */
EXPORT rt_hw_interrupt_enable EXPORT rt_hw_interrupt_enable
rt_hw_interrupt_enable: rt_hw_interrupt_enable:
MSR PRIMASK, r0 MSR PRIMASK, r0
BX LR BX LR
;/* ;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
@ -55,92 +55,92 @@ rt_hw_interrupt_enable:
; * r1 --> to ; * r1 --> to
; */ ; */
EXPORT rt_hw_context_switch_interrupt EXPORT rt_hw_context_switch_interrupt
EXPORT rt_hw_context_switch EXPORT rt_hw_context_switch
rt_hw_context_switch_interrupt: rt_hw_context_switch_interrupt:
rt_hw_context_switch: rt_hw_context_switch:
; set rt_thread_switch_interrput_flag to 1 ; set rt_thread_switch_interrput_flag to 1
LDR r2, =rt_thread_switch_interrput_flag LDR r2, =rt_thread_switch_interrput_flag
LDR r3, [r2] LDR r3, [r2]
CMP r3, #1 CMP r3, #1
BEQ _reswitch BEQ _reswitch
MOV r3, #1 MOV r3, #1
STR r3, [r2] STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2] STR r0, [r2]
_reswitch _reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2] STR r1, [r2]
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET LDR r1, =NVIC_PENDSVSET
STR r1, [r0] STR r1, [r0]
BX LR BX LR
; r0 --> swith from thread stack ; r0 --> swith from thread stack
; r1 --> swith to thread stack ; r1 --> swith to thread stack
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
EXPORT rt_hw_pend_sv EXPORT rt_hw_pend_sv
rt_hw_pend_sv: rt_hw_pend_sv:
; disable interrupt to protect context switch ; disable interrupt to protect context switch
MRS r2, PRIMASK MRS r2, PRIMASK
CPSID I CPSID I
; get rt_thread_switch_interrupt_flag ; get rt_thread_switch_interrupt_flag
LDR r0, =rt_thread_switch_interrput_flag LDR r0, =rt_thread_switch_interrput_flag
LDR r1, [r0] LDR r1, [r0]
CBZ r1, pendsv_exit ; pendsv already handled CBZ r1, pendsv_exit ; pendsv already handled
; clear rt_thread_switch_interrput_flag to 0 ; clear rt_thread_switch_interrput_flag to 0
MOV r1, #0x00 MOV r1, #0x00
STR r1, [r0] STR r1, [r0]
LDR r0, =rt_interrupt_from_thread LDR r0, =rt_interrupt_from_thread
LDR r1, [r0] LDR r1, [r0]
CBZ r1, swtich_to_thread ; skip register save at the first time CBZ r1, swtich_to_thread ; skip register save at the first time
MRS r1, psp ; get from thread stack pointer MRS r1, psp ; get from thread stack pointer
STMFD r1!, {r4 - r11} ; push r4 - r11 register STMFD r1!, {r4 - r11} ; push r4 - r11 register
LDR r0, [r0] LDR r0, [r0]
STR r1, [r0] ; update from thread stack pointer STR r1, [r0] ; update from thread stack pointer
swtich_to_thread swtich_to_thread
LDR r1, =rt_interrupt_to_thread LDR r1, =rt_interrupt_to_thread
LDR r1, [r1] LDR r1, [r1]
LDR r1, [r1] ; load thread stack pointer LDR r1, [r1] ; load thread stack pointer
LDMFD r1!, {r4 - r11} ; pop r4 - r11 register LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
MSR psp, r1 ; update stack pointer MSR psp, r1 ; update stack pointer
pendsv_exit pendsv_exit
; restore interrupt ; restore interrupt
MSR PRIMASK, r2 MSR PRIMASK, r2
ORR lr, lr, #0x04 ORR lr, lr, #0x04
BX lr BX lr
;/* ;/*
; * void rt_hw_context_switch_to(rt_uint32 to); ; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to ; * r0 --> to
; */ ; */
EXPORT rt_hw_context_switch_to EXPORT rt_hw_context_switch_to
rt_hw_context_switch_to: rt_hw_context_switch_to:
LDR r1, =rt_interrupt_to_thread LDR r1, =rt_interrupt_to_thread
STR r0, [r1] STR r0, [r1]
; set from thread to 0 ; set from thread to 0
LDR r1, =rt_interrupt_from_thread LDR r1, =rt_interrupt_from_thread
MOV r0, #0x0 MOV r0, #0x0
STR r0, [r1] STR r0, [r1]
; set interrupt flag to 1 ; set interrupt flag to 1
LDR r1, =rt_thread_switch_interrput_flag LDR r1, =rt_thread_switch_interrput_flag
MOV r0, #1 MOV r0, #1
STR r0, [r1] STR r0, [r1]
; set the PendSV exception priority ; set the PendSV exception priority
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read LDR.W r2, [r0,#0x00] ; read
@ -153,11 +153,24 @@ rt_hw_context_switch_to:
CPSIE I ; enable interrupts at processor level CPSIE I ; enable interrupts at processor level
; never reach here! ; never reach here!
; compatible with old version ; compatible with old version
EXPORT rt_hw_interrupt_thread_switch EXPORT rt_hw_interrupt_thread_switch
rt_hw_interrupt_thread_switch: rt_hw_interrupt_thread_switch:
BX lr BX lr
IMPORT rt_hw_hard_fault_exception
EXPORT rt_hw_hard_fault
rt_hw_hard_fault:
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {lr}
ORR lr, lr, #0x04
BX lr
END END

182
libcpu/arm/stm32/context_rvds.S
View File

@ -22,33 +22,33 @@ NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
AREA |.text|, CODE, READONLY, ALIGN=2 AREA |.text|, CODE, READONLY, ALIGN=2
THUMB THUMB
REQUIRE8 REQUIRE8
PRESERVE8 PRESERVE8
IMPORT rt_thread_switch_interrput_flag IMPORT rt_thread_switch_interrput_flag
IMPORT rt_interrupt_from_thread IMPORT rt_interrupt_from_thread
IMPORT rt_interrupt_to_thread IMPORT rt_interrupt_to_thread
;/* ;/*
; * rt_base_t rt_hw_interrupt_disable(); ; * rt_base_t rt_hw_interrupt_disable();
; */ ; */
rt_hw_interrupt_disable PROC rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable EXPORT rt_hw_interrupt_disable
MRS r0, PRIMASK MRS r0, PRIMASK
CPSID I CPSID I
BX LR BX LR
ENDP ENDP
;/* ;/*
; * void rt_hw_interrupt_enable(rt_base_t level); ; * void rt_hw_interrupt_enable(rt_base_t level);
; */ ; */
rt_hw_interrupt_enable PROC rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable EXPORT rt_hw_interrupt_enable
MSR PRIMASK, r0 MSR PRIMASK, r0
BX LR BX LR
ENDP ENDP
;/* ;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
@ -56,74 +56,74 @@ rt_hw_interrupt_enable PROC
; * r1 --> to ; * r1 --> to
; */ ; */
rt_hw_context_switch_interrupt rt_hw_context_switch_interrupt
EXPORT rt_hw_context_switch_interrupt EXPORT rt_hw_context_switch_interrupt
rt_hw_context_switch PROC rt_hw_context_switch PROC
EXPORT rt_hw_context_switch EXPORT rt_hw_context_switch
; set rt_thread_switch_interrput_flag to 1 ; set rt_thread_switch_interrput_flag to 1
LDR r2, =rt_thread_switch_interrput_flag LDR r2, =rt_thread_switch_interrput_flag
LDR r3, [r2] LDR r3, [r2]
CMP r3, #1 CMP r3, #1
BEQ _reswitch BEQ _reswitch
MOV r3, #1 MOV r3, #1
STR r3, [r2] STR r3, [r2]
LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
STR r0, [r2] STR r0, [r2]
_reswitch _reswitch
LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
STR r1, [r2] STR r1, [r2]
LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
LDR r1, =NVIC_PENDSVSET LDR r1, =NVIC_PENDSVSET
STR r1, [r0] STR r1, [r0]
BX LR BX LR
ENDP ENDP
; r0 --> swith from thread stack ; r0 --> swith from thread stack
; r1 --> swith to thread stack ; r1 --> swith to thread stack
; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
rt_hw_pend_sv PROC rt_hw_pend_sv PROC
EXPORT rt_hw_pend_sv EXPORT rt_hw_pend_sv
; disable interrupt to protect context switch ; disable interrupt to protect context switch
MRS r2, PRIMASK MRS r2, PRIMASK
CPSID I CPSID I
; get rt_thread_switch_interrupt_flag ; get rt_thread_switch_interrupt_flag
LDR r0, =rt_thread_switch_interrput_flag LDR r0, =rt_thread_switch_interrput_flag
LDR r1, [r0] LDR r1, [r0]
CBZ r1, pendsv_exit ; pendsv already handled CBZ r1, pendsv_exit ; pendsv already handled
; clear rt_thread_switch_interrput_flag to 0 ; clear rt_thread_switch_interrput_flag to 0
MOV r1, #0x00 MOV r1, #0x00
STR r1, [r0] STR r1, [r0]
LDR r0, =rt_interrupt_from_thread LDR r0, =rt_interrupt_from_thread
LDR r1, [r0] LDR r1, [r0]
CBZ r1, swtich_to_thread ; skip register save at the first time CBZ r1, swtich_to_thread ; skip register save at the first time
MRS r1, psp ; get from thread stack pointer MRS r1, psp ; get from thread stack pointer
STMFD r1!, {r4 - r11} ; push r4 - r11 register STMFD r1!, {r4 - r11} ; push r4 - r11 register
LDR r0, [r0] LDR r0, [r0]
STR r1, [r0] ; update from thread stack pointer STR r1, [r0] ; update from thread stack pointer
swtich_to_thread swtich_to_thread
LDR r1, =rt_interrupt_to_thread LDR r1, =rt_interrupt_to_thread
LDR r1, [r1] LDR r1, [r1]
LDR r1, [r1] ; load thread stack pointer LDR r1, [r1] ; load thread stack pointer
LDMFD r1!, {r4 - r11} ; pop r4 - r11 register LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
MSR psp, r1 ; update stack pointer MSR psp, r1 ; update stack pointer
pendsv_exit pendsv_exit
; restore interrupt ; restore interrupt
MSR PRIMASK, r2 MSR PRIMASK, r2
ORR lr, lr, #0x04 ORR lr, lr, #0x04
BX lr BX lr
ENDP ENDP
;/* ;/*
; * void rt_hw_context_switch_to(rt_uint32 to); ; * void rt_hw_context_switch_to(rt_uint32 to);
@ -131,44 +131,58 @@ pendsv_exit
; * this fucntion is used to perform the first thread switch ; * this fucntion is used to perform the first thread switch
; */ ; */
rt_hw_context_switch_to PROC rt_hw_context_switch_to PROC
EXPORT rt_hw_context_switch_to EXPORT rt_hw_context_switch_to
; set to thread ; set to thread
LDR r1, =rt_interrupt_to_thread LDR r1, =rt_interrupt_to_thread
STR r0, [r1] STR r0, [r1]
; set from thread to 0 ; set from thread to 0
LDR r1, =rt_interrupt_from_thread LDR r1, =rt_interrupt_from_thread
MOV r0, #0x0 MOV r0, #0x0
STR r0, [r1] STR r0, [r1]
; set interrupt flag to 1 ; set interrupt flag to 1
LDR r1, =rt_thread_switch_interrput_flag LDR r1, =rt_thread_switch_interrput_flag
MOV r0, #1 MOV r0, #1
STR r0, [r1] STR r0, [r1]
; set the PendSV exception priority ; set the PendSV exception priority
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read LDR.W r2, [r0,#0x00] ; read
ORR r1,r1,r2 ; modify ORR r1,r1,r2 ; modify
STR r1, [r0] ; write-back STR r1, [r0] ; write-back
; trigger the PendSV exception (causes context switch) ; trigger the PendSV exception (causes context switch)
LDR r0, =NVIC_INT_CTRL LDR r0, =NVIC_INT_CTRL
LDR r1, =NVIC_PENDSVSET LDR r1, =NVIC_PENDSVSET
STR r1, [r0] STR r1, [r0]
; enable interrupts at processor level ; enable interrupts at processor level
CPSIE I CPSIE I
; never reach here! ; never reach here!
ENDP ENDP
; compatible with old version ; compatible with old version
rt_hw_interrupt_thread_switch PROC rt_hw_interrupt_thread_switch PROC
EXPORT rt_hw_interrupt_thread_switch EXPORT rt_hw_interrupt_thread_switch
BX lr BX lr
NOP NOP
ENDP ENDP
END IMPORT rt_hw_hard_fault_exception
EXPORT rt_hw_hard_fault
rt_hw_hard_fault PROC
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {lr}
ORR lr, lr, #0x04
BX lr
ENDP
END

42
libcpu/arm/stm32/cpu.c
View File

@ -1,42 +0,0 @@
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first version
*/
#include <rtthread.h>
/**
* @addtogroup S3C2410
*/
/*@{*/
/**
* reset cpu by dog's time-out
*
*/
void rt_hw_cpu_reset()
{
/*NOTREACHED*/
}
/**
* shutdown CPU
*
*/
void rt_hw_cpu_shutdown()
{
rt_kprintf("shutdown...\n");
RT_ASSERT(0);
}
/*@}*/

87
libcpu/arm/stm32/cpuport.c Normal file
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@ -0,0 +1,87 @@
/*
* File : cpuport.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-08-23 Bernard the first version
* 2011-06-03 Bernard merge all of C source code into cpuport.c
*/
#include <rtthread.h>
/* exception and interrupt handler table */
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrput_flag;
struct stack_contex
{
rt_uint32_t r0;
rt_uint32_t r1;
rt_uint32_t r2;
rt_uint32_t r3;
rt_uint32_t r12;
rt_uint32_t lr;
rt_uint32_t pc;
rt_uint32_t psr;
};
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
rt_uint8_t *stack_addr, void *texit)
{
unsigned long *stk;
stk = (unsigned long *)stack_addr;
*(stk) = 0x01000000L; /* PSR */
*(--stk) = (unsigned long)tentry; /* entry point, pc */
*(--stk) = (unsigned long)texit; /* lr */
*(--stk) = 0; /* r12 */
*(--stk) = 0; /* r3 */
*(--stk) = 0; /* r2 */
*(--stk) = 0; /* r1 */
*(--stk) = (unsigned long)parameter; /* r0 : argument */
*(--stk) = 0; /* r11 */
*(--stk) = 0; /* r10 */
*(--stk) = 0; /* r9 */
*(--stk) = 0; /* r8 */
*(--stk) = 0; /* r7 */
*(--stk) = 0; /* r6 */
*(--stk) = 0; /* r5 */
*(--stk) = 0; /* r4 */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
extern void rt_hw_interrupt_thread_switch(void);
extern void list_thread(void);
extern rt_thread_t rt_current_thread;
void rt_hw_hard_fault_exception(struct stack_contex* contex)
{
rt_kprintf("psr: 0x%08x\n", contex->psr);
rt_kprintf(" pc: 0x%08x\n", contex->pc);
rt_kprintf(" lr: 0x%08x\n", contex->lr);
rt_kprintf("r12: 0x%08x\n", contex->r12);
rt_kprintf("r03: 0x%08x\n", contex->r3);
rt_kprintf("r02: 0x%08x\n", contex->r2);
rt_kprintf("r01: 0x%08x\n", contex->r1);
rt_kprintf("r00: 0x%08x\n", contex->r0);
rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
#ifdef RT_USING_FINSH
list_thread();
#endif
while (1);
}
void rt_hw_cpu_shutdown()
{
rt_kprintf("shutdown...\n");
RT_ASSERT(0);
}

47
libcpu/arm/stm32/fault.c
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@ -1,47 +0,0 @@
/*
* File : fault.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first version
*/
#include <rtthread.h>
struct stack_contex
{
rt_uint32_t r0;
rt_uint32_t r1;
rt_uint32_t r2;
rt_uint32_t r3;
rt_uint32_t r12;
rt_uint32_t lr;
rt_uint32_t pc;
rt_uint32_t psr;
};
extern void rt_hw_interrupt_thread_switch(void);
extern void list_thread(void);
extern rt_thread_t rt_current_thread;
void rt_hw_hard_fault_exception(struct stack_contex* contex)
{
rt_kprintf("psr: 0x%08x\n", contex->psr);
rt_kprintf(" pc: 0x%08x\n", contex->pc);
rt_kprintf(" lr: 0x%08x\n", contex->lr);
rt_kprintf("r12: 0x%08x\n", contex->r12);
rt_kprintf("r03: 0x%08x\n", contex->r3);
rt_kprintf("r02: 0x%08x\n", contex->r2);
rt_kprintf("r01: 0x%08x\n", contex->r1);
rt_kprintf("r00: 0x%08x\n", contex->r0);
rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
#ifdef RT_USING_FINSH
list_thread();
#endif
while (1);
}

31
libcpu/arm/stm32/fault_gcc.S
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@ -1,31 +0,0 @@
/*
* File : fault_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-10-11 Bernard first version
*/
.cpu cortex-m3
.fpu softvfp
.syntax unified
.thumb
.text
.global rt_hw_hard_fault
.type rt_hw_hard_fault, %function
rt_hw_hard_fault:
/* get current context */
MRS r0, psp /* get fault thread stack pointer */
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {lr}
ORR lr, lr, #0x04
BX lr

34
libcpu/arm/stm32/fault_iar.S
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@ -1,34 +0,0 @@
;/*
; * File : fault_iar.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-17 Bernard first version
; */
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
IMPORT rt_hw_hard_fault_exception
EXPORT rt_hw_hard_fault
rt_hw_hard_fault:
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {lr}
ORR lr, lr, #0x04
BX lr
END

35
libcpu/arm/stm32/fault_rvds.S
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@ -1,35 +0,0 @@
;/*
; * File : fault_rvds.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2006, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-17 Bernard first version
; */
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
IMPORT rt_hw_hard_fault_exception
rt_hw_hard_fault PROC
EXPORT rt_hw_hard_fault
; get current context
MRS r0, psp ; get fault thread stack pointer
PUSH {lr}
BL rt_hw_hard_fault_exception
POP {lr}
ORR lr, lr, #0x04
BX lr
ENDP
END

418
libcpu/arm/stm32/serial.c
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@ -1,418 +0,0 @@
/*
* File : serial.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-02-05 Bernard first version
* 2009-10-25 Bernard fix rt_serial_read bug when there is no data
* in the buffer.
* 2010-03-29 Bernard cleanup code.
*/
#include "serial.h"
#include <stm32f10x_dma.h>
#include <stm32f10x_usart.h>
static void rt_serial_enable_dma(DMA_Channel_TypeDef* dma_channel,
rt_uint32_t address, rt_uint32_t size);
/**
* @addtogroup STM32
*/
/*@{*/
/* RT-Thread Device Interface */
static rt_err_t rt_serial_init (rt_device_t dev)
{
struct stm32_serial_device* uart = (struct stm32_serial_device*) dev->user_data;
if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
{
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
rt_memset(uart->int_rx->rx_buffer, 0,
sizeof(uart->int_rx->rx_buffer));
uart->int_rx->read_index = 0;
uart->int_rx->save_index = 0;
}
if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
{
RT_ASSERT(uart->dma_tx->dma_channel != RT_NULL);
uart->dma_tx->list_head = uart->dma_tx->list_tail = RT_NULL;
/* init data node memory pool */
rt_mp_init(&(uart->dma_tx->data_node_mp), "dn",
uart->dma_tx->data_node_mem_pool,
sizeof(uart->dma_tx->data_node_mem_pool),
sizeof(struct stm32_serial_data_node));
}
/* Enable USART */
USART_Cmd(uart->uart_device, ENABLE);
dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
}
return RT_EOK;
}
static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
}
static rt_err_t rt_serial_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_uint8_t* ptr;
rt_err_t err_code;
struct stm32_serial_device* uart;
ptr = buffer;
err_code = RT_EOK;
uart = (struct stm32_serial_device*)dev->user_data;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* interrupt mode Rx */
while (size)
{
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (uart->int_rx->read_index != uart->int_rx->save_index)
{
/* read a character */
*ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
size--;
/* move to next position */
uart->int_rx->read_index ++;
if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
uart->int_rx->read_index = 0;
}
else
{
/* set error code */
err_code = -RT_EEMPTY;
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
}
else
{
/* polling mode */
while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
{
while (uart->uart_device->SR & USART_FLAG_RXNE)
{
*ptr = uart->uart_device->DR & 0xff;
ptr ++;
}
}
}
/* set error code */
rt_set_errno(err_code);
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
static void rt_serial_enable_dma(DMA_Channel_TypeDef* dma_channel,
rt_uint32_t address, rt_uint32_t size)
{
RT_ASSERT(dma_channel != RT_NULL);
/* disable DMA */
DMA_Cmd(dma_channel, DISABLE);
/* set buffer address */
dma_channel->CMAR = address;
/* set size */
dma_channel->CNDTR = size;
/* enable DMA */
DMA_Cmd(dma_channel, ENABLE);
}
static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_uint8_t* ptr;
rt_err_t err_code;
struct stm32_serial_device* uart;
err_code = RT_EOK;
ptr = (rt_uint8_t*)buffer;
uart = (struct stm32_serial_device*)dev->user_data;
if (dev->flag & RT_DEVICE_FLAG_INT_TX)
{
/* interrupt mode Tx, does not support */
RT_ASSERT(0);
}
else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
{
/* DMA mode Tx */
/* allocate a data node */
struct stm32_serial_data_node* data_node = (struct stm32_serial_data_node*)
rt_mp_alloc (&(uart->dma_tx->data_node_mp), RT_WAITING_FOREVER);
if (data_node == RT_NULL)
{
/* set error code */
err_code = -RT_ENOMEM;
}
else
{
rt_uint32_t level;
/* fill data node */
data_node->data_ptr = ptr;
data_node->data_size = size;
/* insert to data link */
data_node->next = RT_NULL;
/* disable interrupt */
level = rt_hw_interrupt_disable();
data_node->prev = uart->dma_tx->list_tail;
if (uart->dma_tx->list_tail != RT_NULL)
uart->dma_tx->list_tail->next = data_node;
uart->dma_tx->list_tail = data_node;
if (uart->dma_tx->list_head == RT_NULL)
{
/* start DMA to transmit data */
uart->dma_tx->list_head = data_node;
/* Enable DMA Channel */
rt_serial_enable_dma(uart->dma_tx->dma_channel,
(rt_uint32_t)uart->dma_tx->list_head->data_ptr,
uart->dma_tx->list_head->data_size);
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
}
else
{
/* polling mode */
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
while (!(uart->uart_device->SR & USART_FLAG_TXE));
uart->uart_device->DR = '\r';
}
while (!(uart->uart_device->SR & USART_FLAG_TXE));
uart->uart_device->DR = (*ptr & 0x1FF);
++ptr; --size;
}
}
else
{
/* write data directly */
while (size)
{
while (!(uart->uart_device->SR & USART_FLAG_TXE));
uart->uart_device->DR = (*ptr & 0x1FF);
++ptr; --size;
}
}
}
/* set error code */
rt_set_errno(err_code);
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
{
struct stm32_serial_device* uart;
RT_ASSERT(dev != RT_NULL);
uart = (struct stm32_serial_device*)dev->user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_SUSPEND:
/* suspend device */
dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
USART_Cmd(uart->uart_device, DISABLE);
break;
case RT_DEVICE_CTRL_RESUME:
/* resume device */
dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
USART_Cmd(uart->uart_device, ENABLE);
break;
}
return RT_EOK;
}
/*
* serial register for STM32
* support STM32F103VB and STM32F103ZE
*/
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial)
{
RT_ASSERT(device != RT_NULL);
if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
(flag & RT_DEVICE_FLAG_INT_TX))
{
RT_ASSERT(0);
}
device->type = RT_Device_Class_Char;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = rt_serial_init;
device->open = rt_serial_open;
device->close = rt_serial_close;
device->read = rt_serial_read;
device->write = rt_serial_write;
device->control = rt_serial_control;
device->user_data = serial;
/* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
}
/* ISR for serial interrupt */
void rt_hw_serial_isr(rt_device_t device)
{
struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
{
/* interrupt mode receive */
RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
/* save on rx buffer */
while (uart->uart_device->SR & USART_FLAG_RXNE)
{
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
/* save character */
uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->DR & 0xff;
uart->int_rx->save_index ++;
if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
uart->int_rx->save_index = 0;
/* if the next position is read index, discard this 'read char' */
if (uart->int_rx->save_index == uart->int_rx->read_index)
{
uart->int_rx->read_index ++;
if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
uart->int_rx->read_index = 0;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
/* clear interrupt */
USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
/* invoke callback */
if (device->rx_indicate != RT_NULL)
{
rt_size_t rx_length;
/* get rx length */
rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
uart->int_rx->save_index - uart->int_rx->read_index;
device->rx_indicate(device, rx_length);
}
}
if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
{
/* clear interrupt */
USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
}
}
/*
* ISR for DMA mode Tx
*/
void rt_hw_serial_dma_tx_isr(rt_device_t device)
{
rt_uint32_t level;
struct stm32_serial_data_node* data_node;
struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
/* DMA mode receive */
RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_TX);
/* get the first data node */
data_node = uart->dma_tx->list_head;
RT_ASSERT(data_node != RT_NULL);
/* invoke call to notify tx complete */
if (device->tx_complete != RT_NULL)
device->tx_complete(device, data_node->data_ptr);
/* disable interrupt */
level = rt_hw_interrupt_disable();
/* remove list head */
uart->dma_tx->list_head = data_node->next;
if (uart->dma_tx->list_head == RT_NULL) /* data link empty */
uart->dma_tx->list_tail = RT_NULL;
/* enable interrupt */
rt_hw_interrupt_enable(level);
/* release data node memory */
rt_mp_free(data_node);
if (uart->dma_tx->list_head != RT_NULL)
{
/* transmit next data node */
rt_serial_enable_dma(uart->dma_tx->dma_channel,
(rt_uint32_t)uart->dma_tx->list_head->data_ptr,
uart->dma_tx->list_head->data_size);
}
else
{
/* no data to be transmitted, disable DMA */
DMA_Cmd(uart->dma_tx->dma_channel, DISABLE);
}
}
/*@}*/

70
libcpu/arm/stm32/serial.h
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@ -1,70 +0,0 @@
/*
* File : serial.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first version
* 2010-03-29 Bernard remove interrupt tx and DMA rx mode.
*/
#ifndef __RT_HW_SERIAL_H__
#define __RT_HW_SERIAL_H__
#include <rthw.h>
#include <rtthread.h>
/* STM32F10x library definitions */
#include <stm32f10x.h>
#define UART_RX_BUFFER_SIZE 64
#define UART_TX_DMA_NODE_SIZE 4
/* data node for Tx Mode */
struct stm32_serial_data_node
{
rt_uint8_t *data_ptr;
rt_size_t data_size;
struct stm32_serial_data_node *next, *prev;
};
struct stm32_serial_dma_tx
{
/* DMA Channel */
DMA_Channel_TypeDef* dma_channel;
/* data list head and tail */
struct stm32_serial_data_node *list_head, *list_tail;
/* data node memory pool */
struct rt_mempool data_node_mp;
rt_uint8_t data_node_mem_pool[UART_TX_DMA_NODE_SIZE *
(sizeof(struct stm32_serial_data_node) + sizeof(void*))];
};
struct stm32_serial_int_rx
{
rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
rt_uint32_t read_index, save_index;
};
struct stm32_serial_device
{
USART_TypeDef* uart_device;
/* rx structure */
struct stm32_serial_int_rx* int_rx;
/* tx structure */
struct stm32_serial_dma_tx* dma_tx;
};
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial);
void rt_hw_serial_isr(rt_device_t device);
void rt_hw_serial_dma_tx_isr(rt_device_t device);
#endif

59
libcpu/arm/stm32/stack.c
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@ -1,59 +0,0 @@
/*
* File : stack.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-08-23 Bernard the first version
*/
#include <rtthread.h>
/**
* @addtogroup STM32
*/
/*@{*/
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
rt_uint8_t *stack_addr, void *texit)
{
unsigned long *stk;
stk = (unsigned long *)stack_addr;
*(stk) = 0x01000000L; /* PSR */
*(--stk) = (unsigned long)tentry; /* entry point, pc */
*(--stk) = (unsigned long)texit; /* lr */
*(--stk) = 0; /* r12 */
*(--stk) = 0; /* r3 */
*(--stk) = 0; /* r2 */
*(--stk) = 0; /* r1 */
*(--stk) = (unsigned long)parameter; /* r0 : argument */
*(--stk) = 0; /* r11 */
*(--stk) = 0; /* r10 */
*(--stk) = 0; /* r9 */
*(--stk) = 0; /* r8 */
*(--stk) = 0; /* r7 */
*(--stk) = 0; /* r6 */
*(--stk) = 0; /* r5 */
*(--stk) = 0; /* r4 */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/

1
libcpu/arm/stm32/start_rvds.S
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@ -138,6 +138,7 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD CAN2_RX1_IRQHandler ; CAN2 RX1 DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS DCD OTG_FS_IRQHandler ; USB OTG FS
; for STM32F2xx
__Vectors_End __Vectors_End