Merge pull request #462 from ArdaFu/master
[bsp][sam9260] Add GDB start scripts.
This commit is contained in:
Bernard Xiong
commit
37b3c8781a
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#------------------------------------------------
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# SDRAM initialization script for the AT91SAM9260
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#------------------------------------------------
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#----------------------------------------------------------------------------
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# _InitRSTC()
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# Function description
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# Initializes the RSTC (Reset controller).
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# This makes sense since the default is to not allow user resets, which makes it impossible to
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# apply a second RESET via J-Link
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#----------------------------------------------------------------------------
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define _InitRSTC
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# Allow user reset
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set *0xFFFFFD08=0xA5000001
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end
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#----------------------------------------------------------------------------
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# _MapRAMAt0()
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# Function description: Maps RAM at 0.
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#----------------------------------------------------------------------------
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define _MapRAMAt0
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echo "---------- SRAM remapped to 0 --------" \n
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# Test and set Remap
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set $__mac_i = *0xFFFFEF00
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if ( (($__mac_i & 0x01) == 0) || (($__mac_i & 0x02) == 0))
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#toggle remap bits
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set *0xFFFFEF00 = 0x03
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else
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echo "---------- The Remap is done ---------" \n
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end
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end
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#----------------------------------------------------------------------------
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#
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# _PllSetting()
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# Function description
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# Initializes the PMC.
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# 1. Enable the Main Oscillator
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# 2. Configure PLL
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# 3. Switch Master
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#----------------------------------------------------------------------------
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define __PllSetting
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if ((*(0xFFFFFC30)&0x3) != 0 )
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# Disable all PMC interrupt ( $$ JPP)
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# AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) #(PMC) Interrupt Disable Register
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# pPmc->PMC_IDR = 0xFFFFFFFF;
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set *0xFFFFFC64 = 0xFFFFFFFF
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# AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) #(PMC) Peripheral Clock Disable Register
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set *0xFFFFFC14 = 0xFFFFFFFF
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# Disable all clock only Processor clock is enabled.
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set *0xFFFFFC04 = 0xFFFFFFFE
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# AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) # (PMC) Master Clock Register
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set *0xFFFFFC30 = 0x00000001
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while ((*0xFFFFFC68 & 0x8) == 0)
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end
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# write reset value to PLLA and PLLB
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# AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) # (PMC) PLL A Register
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set *0xFFFFFC28 = 0x00003F00
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# AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) # (PMC) PLL B Register
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set *0xFFFFFC2C 0x00003F00
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while ((*0xFFFFFC68 & 0x2) == 0)
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end
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while ((*0xFFFFFC68 & 0x4) == 0)
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end
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echo "---------- PLL Enable ---------------" \n
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else
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echo "---------- Core in SLOW CLOCK mode ---" \n
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end
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end
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#----------------------------------------------------------------------------
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#
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# __PllSetting100MHz()
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# Function description
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# Set core at 200 MHz and MCK at 100 MHz
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#----------------------------------------------------------------------------
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define __PllSetting100MHz
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echo "---------- PLL Set at 100 MHz --------" \n
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#* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
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set *0xFFFFFC20=0x00004001
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while ((*0xFFFFFC68 & 0x1) == 0)
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end
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# AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) # (PMC) Master Clock Register
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set *0xFFFFFC30=0x00000001
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while ((*0xFFFFFC68 & 0x8) == 0)
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end
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#* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) |
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# (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
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set *0xFFFFFC28=0x2060BF09
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while ((*0xFFFFFC68 & 0x2) == 0)
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end
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# Configure PLLB
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set *0xFFFFFC2C=0x207C3F0C
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while ((*0xFFFFFC68 & 0x4) == 0)
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end
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#* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
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set *0xFFFFFC30=0x00000102
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while ((*0xFFFFFC68 & 0x8) == 0)
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end
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end
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#----------------------------------------------------------------------------
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# __initSDRAM()
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# Function description
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# Set SDRAM for works at 100 MHz
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#----------------------------------------------------------------------------
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define __initSDRAM
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# Configure EBI Chip select
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# pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC;
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# AT91C_CCFG_EBICSA ((AT91_REG *) 0xFFFFEF1C) # (CCFG) EBI Chip Select Assignement Register
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set *0xFFFFEF1C=0x0001003A
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# Configure PIOs
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# AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, AT91C_PC16_D16 to AT91C_PC16_D31
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# pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) # (PIOC) Select A Register
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# pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) # (PIOC) Select B Register
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# pPio->PIO_PDR = (periphAEnable | periphBEnable # Set in Periph mode
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set *0xFFFFF870=0xFFFF0000
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set *0xFFFFF874=0x00000000
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set *0xFFFFF804=0xFFFF0000
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# psdrc->SDRAMC_CR = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 |
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# AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 |
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# AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ;
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set *0xFFFFEA08=0x85227259
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set $i = 0
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while $i != 100
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set $i += 1
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end
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# psdrc->SDRAMC_MR = 0x00000002; # Set PRCHG AL
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set *0xFFFFEA00=0x00000002
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# *AT91C_SDRAM = 0x00000000; # Perform PRCHG
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set *0x20000000=0x00000000
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set $i = 0
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while $i != 100
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set $i += 1
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end
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# psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; # Set 1st CBR
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set *0xFFFFEA00=0x00000004
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# *(AT91C_SDRAM+4) = 0x00000001; # Perform CBR
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set *0x20000010=0x00000001
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# psdrc->SDRAMC_MR = 0x00000004; # Set 2 CBR
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set *0xFFFFEA00=0x00000004
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# *(AT91C_SDRAM+8) = 0x00000002; # Perform CBR
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set *0x20000020=0x00000002
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# psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; # Set 3 CBR
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set *0xFFFFEA00=0x00000004
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# *(AT91C_SDRAM+0xc) = 0x00000003; # Perform CBR
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set *0x20000030=0x00000003
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# psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; # Set 4 CBR
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set *0xFFFFEA00=0x00000004
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# *(AT91C_SDRAM+0x10) = 0x00000004; # Perform CBR
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set *0x20000040=0x00000004
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# psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; # Set 5 CBR
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set *0xFFFFEA00=0x00000004
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# *(AT91C_SDRAM+0x14) = 0x00000005; # Perform CBR
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set *0x20000050=0x00000005
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# psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; # Set 6 CBR
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set *0xFFFFEA00=0x00000004
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# *(AT91C_SDRAM+0x18) = 0x00000006; # Perform CBR
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set *0x20000060=0x00000006
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# psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; # Set 7 CBR
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set *0xFFFFEA00=0x00000004
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# *(AT91C_SDRAM+0x1c) = 0x00000007; # Perform CBR
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set *0x20000070=0x00000007
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# psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; # Set 8 CBR
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set *0xFFFFEA00=0x00000004
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# *(AT91C_SDRAM+0x20) = 0x00000008; # Perform CBR
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set *0x20000080=0x00000008
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# psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD; # Set LMR operation
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set *0xFFFFEA00=0x00000003
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# *(AT91C_SDRAM+0x24) = 0xcafedede; # Perform LMR burst=1, lat=2
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set *0x20000090=0xCAFEDEDE
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# psdrc->SDRAMC_TR = (AT91C_MASTER_CLOCK * 7)/1000000; # Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
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set *0xFFFFEA04=0x000002B9
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#* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; # Set Normal mode
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set *0xFFFFEA00=0x00000000
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#* *AT91C_SDRAM = 0x00000000; # Perform Normal mode
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set *0x20000000=0x00000000
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echo "---------- SDRAM Done at 100 MHz -----" \n
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end
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# Step1: Connect to the J-Link gdb server
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define reset
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#target remote localhost:2331
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monitor reset
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# Step2: Reset peripheral (RSTC_CR)
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#Init PLL
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__PllSetting
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__PllSetting100MHz
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__initSDRAM
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#* Set the RAM memory at 0x0020 0000 & 0x0000 0000
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_MapRAMAt0
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_InitRSTC
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# Step3: Load file(eg. getting-started project)
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load
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mon reg pc=0x20000000
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#info reg
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end
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