Bernard Xiong
GitHub
commit
33f7124b36
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@ -17,7 +17,7 @@
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Windows环境下推荐使用[env工具][1]进行编译。
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首先下载Linux上的gcc工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
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首先下载windows上的aarch64的gcc交叉编译工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
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将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。
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@ -0,0 +1,455 @@
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#
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# Automatically generated file; DO NOT EDIT.
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# RT-Thread Project Configuration
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#
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#
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# RT-Thread Kernel
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#
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CONFIG_RT_NAME_MAX=8
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# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
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# CONFIG_RT_USING_SMP is not set
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CONFIG_RT_ALIGN_SIZE=4
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# CONFIG_RT_THREAD_PRIORITY_8 is not set
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CONFIG_RT_THREAD_PRIORITY_32=y
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# CONFIG_RT_THREAD_PRIORITY_256 is not set
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CONFIG_RT_THREAD_PRIORITY_MAX=32
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CONFIG_RT_TICK_PER_SECOND=100
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CONFIG_RT_USING_OVERFLOW_CHECK=y
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CONFIG_RT_USING_HOOK=y
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CONFIG_RT_USING_IDLE_HOOK=y
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CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
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CONFIG_IDLE_THREAD_STACK_SIZE=2048
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CONFIG_RT_USING_TIMER_SOFT=y
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CONFIG_RT_TIMER_THREAD_PRIO=4
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CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
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CONFIG_RT_DEBUG=y
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# CONFIG_RT_DEBUG_COLOR is not set
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# CONFIG_RT_DEBUG_INIT_CONFIG is not set
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# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
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# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
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||||
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
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||||
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
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||||
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
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# CONFIG_RT_DEBUG_MEM_CONFIG is not set
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# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
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# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
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# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
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#
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# Inter-Thread communication
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#
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CONFIG_RT_USING_SEMAPHORE=y
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CONFIG_RT_USING_MUTEX=y
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CONFIG_RT_USING_EVENT=y
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CONFIG_RT_USING_MAILBOX=y
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CONFIG_RT_USING_MESSAGEQUEUE=y
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# CONFIG_RT_USING_SIGNALS is not set
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#
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# Memory Management
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#
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CONFIG_RT_USING_MEMPOOL=y
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# CONFIG_RT_USING_MEMHEAP is not set
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# CONFIG_RT_USING_NOHEAP is not set
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CONFIG_RT_USING_SMALL_MEM=y
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# CONFIG_RT_USING_SLAB is not set
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# CONFIG_RT_USING_MEMTRACE is not set
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CONFIG_RT_USING_HEAP=y
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#
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# Kernel Device Object
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#
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CONFIG_RT_USING_DEVICE=y
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# CONFIG_RT_USING_DEVICE_OPS is not set
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# CONFIG_RT_USING_INTERRUPT_INFO is not set
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CONFIG_RT_USING_CONSOLE=y
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CONFIG_RT_CONSOLEBUF_SIZE=128
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
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CONFIG_RT_VER_NUM=0x40003
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CONFIG_ARCH_CPU_64BIT=y
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# CONFIG_RT_USING_CPU_FFS is not set
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# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
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#
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# RT-Thread Components
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#
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CONFIG_RT_USING_COMPONENTS_INIT=y
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CONFIG_RT_USING_USER_MAIN=y
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CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
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CONFIG_RT_MAIN_THREAD_PRIORITY=10
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#
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# C++ features
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#
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# CONFIG_RT_USING_CPLUSPLUS is not set
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#
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# Command shell
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#
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CONFIG_RT_USING_FINSH=y
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CONFIG_FINSH_THREAD_NAME="tshell"
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CONFIG_FINSH_USING_HISTORY=y
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CONFIG_FINSH_HISTORY_LINES=5
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CONFIG_FINSH_USING_SYMTAB=y
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CONFIG_FINSH_USING_DESCRIPTION=y
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# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
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CONFIG_FINSH_THREAD_PRIORITY=20
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CONFIG_FINSH_THREAD_STACK_SIZE=4096
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CONFIG_FINSH_CMD_SIZE=80
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# CONFIG_FINSH_USING_AUTH is not set
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CONFIG_FINSH_USING_MSH=y
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CONFIG_FINSH_USING_MSH_DEFAULT=y
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# CONFIG_FINSH_USING_MSH_ONLY is not set
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CONFIG_FINSH_ARG_MAX=10
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#
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# Device virtual file system
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#
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CONFIG_RT_USING_DFS=y
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CONFIG_DFS_USING_WORKDIR=y
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CONFIG_DFS_FILESYSTEMS_MAX=2
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CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
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CONFIG_DFS_FD_MAX=16
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# CONFIG_RT_USING_DFS_MNTTABLE is not set
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# CONFIG_RT_USING_DFS_ELMFAT is not set
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CONFIG_RT_USING_DFS_DEVFS=y
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# CONFIG_RT_USING_DFS_ROMFS is not set
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# CONFIG_RT_USING_DFS_RAMFS is not set
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# CONFIG_RT_USING_DFS_UFFS is not set
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# CONFIG_RT_USING_DFS_JFFS2 is not set
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#
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# Device Drivers
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#
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CONFIG_RT_USING_DEVICE_IPC=y
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CONFIG_RT_PIPE_BUFSZ=512
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# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
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CONFIG_RT_USING_SERIAL=y
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CONFIG_RT_SERIAL_USING_DMA=y
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CONFIG_RT_SERIAL_RB_BUFSZ=64
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# CONFIG_RT_USING_CAN is not set
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# CONFIG_RT_USING_HWTIMER is not set
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# CONFIG_RT_USING_CPUTIME is not set
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# CONFIG_RT_USING_I2C is not set
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CONFIG_RT_USING_PIN=y
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# CONFIG_RT_USING_ADC is not set
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# CONFIG_RT_USING_PWM is not set
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# CONFIG_RT_USING_MTD_NOR is not set
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# CONFIG_RT_USING_MTD_NAND is not set
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# CONFIG_RT_USING_PM is not set
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# CONFIG_RT_USING_RTC is not set
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# CONFIG_RT_USING_SDIO is not set
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# CONFIG_RT_USING_SPI is not set
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# CONFIG_RT_USING_WDT is not set
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# CONFIG_RT_USING_AUDIO is not set
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# CONFIG_RT_USING_SENSOR is not set
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# CONFIG_RT_USING_TOUCH is not set
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||||
# CONFIG_RT_USING_HWCRYPTO is not set
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||||
# CONFIG_RT_USING_PULSE_ENCODER is not set
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||||
# CONFIG_RT_USING_INPUT_CAPTURE is not set
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# CONFIG_RT_USING_WIFI is not set
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#
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||||
# Using USB
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#
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# CONFIG_RT_USING_USB_HOST is not set
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# CONFIG_RT_USING_USB_DEVICE is not set
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||||
#
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||||
# POSIX layer and C standard library
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#
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CONFIG_RT_USING_LIBC=y
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# CONFIG_RT_USING_PTHREADS is not set
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CONFIG_RT_USING_POSIX=y
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||||
# CONFIG_RT_USING_POSIX_MMAP is not set
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# CONFIG_RT_USING_POSIX_TERMIOS is not set
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# CONFIG_RT_USING_POSIX_AIO is not set
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# CONFIG_RT_USING_MODULE is not set
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#
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# Network
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#
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#
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# Socket abstraction layer
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#
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# CONFIG_RT_USING_SAL is not set
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#
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# Network interface device
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#
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# CONFIG_RT_USING_NETDEV is not set
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#
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# light weight TCP/IP stack
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#
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# CONFIG_RT_USING_LWIP is not set
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#
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# AT commands
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#
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# CONFIG_RT_USING_AT is not set
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#
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# VBUS(Virtual Software BUS)
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#
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# CONFIG_RT_USING_VBUS is not set
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#
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# Utilities
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#
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# CONFIG_RT_USING_RYM is not set
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# CONFIG_RT_USING_ULOG is not set
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# CONFIG_RT_USING_UTEST is not set
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#
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||||
# RT-Thread online packages
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||||
#
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#
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# IoT - internet of things
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#
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# CONFIG_PKG_USING_PAHOMQTT is not set
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# CONFIG_PKG_USING_WEBCLIENT is not set
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# CONFIG_PKG_USING_WEBNET is not set
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# CONFIG_PKG_USING_MONGOOSE is not set
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# CONFIG_PKG_USING_MYMQTT is not set
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||||
# CONFIG_PKG_USING_WEBTERMINAL is not set
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||||
# CONFIG_PKG_USING_CJSON is not set
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||||
# CONFIG_PKG_USING_JSMN is not set
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||||
# CONFIG_PKG_USING_LIBMODBUS is not set
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||||
# CONFIG_PKG_USING_FREEMODBUS is not set
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||||
# CONFIG_PKG_USING_LJSON is not set
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# CONFIG_PKG_USING_EZXML is not set
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# CONFIG_PKG_USING_NANOPB is not set
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||||
#
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||||
# Wi-Fi
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||||
#
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||||
#
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||||
# Marvell WiFi
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||||
#
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||||
# CONFIG_PKG_USING_WLANMARVELL is not set
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||||
#
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||||
# Wiced WiFi
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||||
#
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||||
# CONFIG_PKG_USING_WLAN_WICED is not set
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||||
# CONFIG_PKG_USING_RW007 is not set
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||||
# CONFIG_PKG_USING_COAP is not set
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||||
# CONFIG_PKG_USING_NOPOLL is not set
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||||
# CONFIG_PKG_USING_NETUTILS is not set
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||||
# CONFIG_PKG_USING_PPP_DEVICE is not set
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||||
# CONFIG_PKG_USING_AT_DEVICE is not set
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||||
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
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||||
# CONFIG_PKG_USING_WIZNET is not set
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||||
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||||
#
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||||
# IoT Cloud
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||||
#
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||||
# CONFIG_PKG_USING_ONENET is not set
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||||
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
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||||
# CONFIG_PKG_USING_ALI_IOTKIT is not set
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||||
# CONFIG_PKG_USING_AZURE is not set
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||||
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
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||||
# CONFIG_PKG_USING_JIOT-C-SDK is not set
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||||
# CONFIG_PKG_USING_NIMBLE is not set
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||||
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
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||||
# CONFIG_PKG_USING_IPMSG is not set
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||||
# CONFIG_PKG_USING_LSSDP is not set
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||||
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
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||||
# CONFIG_PKG_USING_LIBRWS is not set
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||||
# CONFIG_PKG_USING_TCPSERVER is not set
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||||
# CONFIG_PKG_USING_PROTOBUF_C is not set
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||||
# CONFIG_PKG_USING_ONNX_PARSER is not set
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||||
# CONFIG_PKG_USING_ONNX_BACKEND is not set
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||||
# CONFIG_PKG_USING_DLT645 is not set
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||||
# CONFIG_PKG_USING_QXWZ is not set
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||||
# CONFIG_PKG_USING_SMTP_CLIENT is not set
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||||
# CONFIG_PKG_USING_ABUP_FOTA is not set
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||||
#
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||||
# security packages
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||||
#
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||||
# CONFIG_PKG_USING_MBEDTLS is not set
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||||
# CONFIG_PKG_USING_libsodium is not set
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||||
# CONFIG_PKG_USING_TINYCRYPT is not set
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#
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||||
# language packages
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||||
#
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||||
# CONFIG_PKG_USING_LUA is not set
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# CONFIG_PKG_USING_JERRYSCRIPT is not set
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||||
# CONFIG_PKG_USING_MICROPYTHON is not set
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||||
#
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||||
# multimedia packages
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||||
#
|
||||
# CONFIG_PKG_USING_OPENMV is not set
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||||
# CONFIG_PKG_USING_MUPDF is not set
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||||
# CONFIG_PKG_USING_STEMWIN is not set
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||||
# CONFIG_PKG_USING_WAVPLAYER is not set
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||||
# CONFIG_PKG_USING_TJPGD is not set
|
||||
|
||||
#
|
||||
# tools packages
|
||||
#
|
||||
# CONFIG_PKG_USING_CMBACKTRACE is not set
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||||
# CONFIG_PKG_USING_EASYFLASH is not set
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||||
# CONFIG_PKG_USING_EASYLOGGER is not set
|
||||
# CONFIG_PKG_USING_SYSTEMVIEW is not set
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||||
# CONFIG_PKG_USING_RDB is not set
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||||
# CONFIG_PKG_USING_QRCODE is not set
|
||||
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
|
||||
# CONFIG_PKG_USING_ADBD is not set
|
||||
# CONFIG_PKG_USING_COREMARK is not set
|
||||
# CONFIG_PKG_USING_DHRYSTONE is not set
|
||||
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
|
||||
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
|
||||
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
|
||||
# CONFIG_PKG_USING_BS8116A is not set
|
||||
|
||||
#
|
||||
# system packages
|
||||
#
|
||||
# CONFIG_PKG_USING_GUIENGINE is not set
|
||||
# CONFIG_PKG_USING_CAIRO is not set
|
||||
# CONFIG_PKG_USING_PIXMAN is not set
|
||||
# CONFIG_PKG_USING_LWEXT4 is not set
|
||||
# CONFIG_PKG_USING_PARTITION is not set
|
||||
# CONFIG_PKG_USING_FAL is not set
|
||||
# CONFIG_PKG_USING_SQLITE is not set
|
||||
# CONFIG_PKG_USING_RTI is not set
|
||||
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
|
||||
# CONFIG_PKG_USING_CMSIS is not set
|
||||
# CONFIG_PKG_USING_DFS_YAFFS is not set
|
||||
# CONFIG_PKG_USING_LITTLEFS is not set
|
||||
# CONFIG_PKG_USING_THREAD_POOL is not set
|
||||
# CONFIG_PKG_USING_ROBOTS is not set
|
||||
# CONFIG_PKG_USING_EV is not set
|
||||
|
||||
#
|
||||
# peripheral libraries and drivers
|
||||
#
|
||||
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
|
||||
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
|
||||
# CONFIG_PKG_USING_SHT2X is not set
|
||||
# CONFIG_PKG_USING_SHT3X is not set
|
||||
# CONFIG_PKG_USING_STM32_SDIO is not set
|
||||
# CONFIG_PKG_USING_ICM20608 is not set
|
||||
# CONFIG_PKG_USING_U8G2 is not set
|
||||
# CONFIG_PKG_USING_BUTTON is not set
|
||||
# CONFIG_PKG_USING_PCF8574 is not set
|
||||
# CONFIG_PKG_USING_SX12XX is not set
|
||||
# CONFIG_PKG_USING_SIGNAL_LED is not set
|
||||
# CONFIG_PKG_USING_LEDBLINK is not set
|
||||
# CONFIG_PKG_USING_WM_LIBRARIES is not set
|
||||
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
|
||||
# CONFIG_PKG_USING_INFRARED is not set
|
||||
# CONFIG_PKG_USING_ROSSERIAL is not set
|
||||
# CONFIG_PKG_USING_AGILE_BUTTON is not set
|
||||
# CONFIG_PKG_USING_AGILE_LED is not set
|
||||
# CONFIG_PKG_USING_AT24CXX is not set
|
||||
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
|
||||
# CONFIG_PKG_USING_AD7746 is not set
|
||||
# CONFIG_PKG_USING_PCA9685 is not set
|
||||
# CONFIG_PKG_USING_I2C_TOOLS is not set
|
||||
# CONFIG_PKG_USING_NRF24L01 is not set
|
||||
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
|
||||
# CONFIG_PKG_USING_MAX17048 is not set
|
||||
# CONFIG_PKG_USING_RPLIDAR is not set
|
||||
# CONFIG_PKG_USING_AS608 is not set
|
||||
|
||||
#
|
||||
# miscellaneous packages
|
||||
#
|
||||
# CONFIG_PKG_USING_LIBCSV is not set
|
||||
# CONFIG_PKG_USING_OPTPARSE is not set
|
||||
# CONFIG_PKG_USING_FASTLZ is not set
|
||||
# CONFIG_PKG_USING_MINILZO is not set
|
||||
# CONFIG_PKG_USING_QUICKLZ is not set
|
||||
# CONFIG_PKG_USING_MULTIBUTTON is not set
|
||||
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
|
||||
# CONFIG_PKG_USING_CANFESTIVAL is not set
|
||||
# CONFIG_PKG_USING_ZLIB is not set
|
||||
# CONFIG_PKG_USING_DSTR is not set
|
||||
# CONFIG_PKG_USING_TINYFRAME is not set
|
||||
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
|
||||
# CONFIG_PKG_USING_DIGITALCTRL is not set
|
||||
# CONFIG_PKG_USING_UPACKER is not set
|
||||
# CONFIG_PKG_USING_UPARAM is not set
|
||||
|
||||
#
|
||||
# samples: kernel and components samples
|
||||
#
|
||||
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
|
||||
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
|
||||
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
|
||||
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
|
||||
# CONFIG_PKG_USING_HELLO is not set
|
||||
# CONFIG_PKG_USING_VI is not set
|
||||
# CONFIG_PKG_USING_NNOM is not set
|
||||
# CONFIG_PKG_USING_LIBANN is not set
|
||||
# CONFIG_PKG_USING_ELAPACK is not set
|
||||
# CONFIG_PKG_USING_ARMv7M_DWT is not set
|
||||
# CONFIG_PKG_USING_VT100 is not set
|
||||
# CONFIG_PKG_USING_ULAPACK is not set
|
||||
# CONFIG_PKG_USING_UKAL is not set
|
||||
|
||||
#
|
||||
# Privated Packages of RealThread
|
||||
#
|
||||
# CONFIG_PKG_USING_CODEC is not set
|
||||
# CONFIG_PKG_USING_PLAYER is not set
|
||||
# CONFIG_PKG_USING_MPLAYER is not set
|
||||
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
|
||||
# CONFIG_PKG_USING_JS_PERSIMMON is not set
|
||||
# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
|
||||
|
||||
#
|
||||
# Network Utilities
|
||||
#
|
||||
# CONFIG_PKG_USING_WICED is not set
|
||||
# CONFIG_PKG_USING_CLOUDSDK is not set
|
||||
# CONFIG_PKG_USING_POWER_MANAGER is not set
|
||||
# CONFIG_PKG_USING_RT_OTA is not set
|
||||
# CONFIG_PKG_USING_RDBD_SRC is not set
|
||||
# CONFIG_PKG_USING_RTINSIGHT is not set
|
||||
# CONFIG_PKG_USING_SMARTCONFIG is not set
|
||||
# CONFIG_PKG_USING_RTX is not set
|
||||
# CONFIG_RT_USING_TESTCASE is not set
|
||||
# CONFIG_PKG_USING_NGHTTP2 is not set
|
||||
# CONFIG_PKG_USING_AVS is not set
|
||||
# CONFIG_PKG_USING_JOYLINK is not set
|
||||
# CONFIG_PKG_USING_STS is not set
|
||||
# CONFIG_PKG_USING_DLMS is not set
|
||||
# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
|
||||
# CONFIG_PKG_USING_ZBAR is not set
|
||||
CONFIG_BCM2711_SOC=y
|
||||
# CONFIG_BSP_SUPPORT_FPU is not set
|
||||
|
||||
#
|
||||
# Hardware Drivers Config
|
||||
#
|
||||
|
||||
#
|
||||
# BCM Peripheral Drivers
|
||||
#
|
||||
CONFIG_BSP_USING_UART=y
|
||||
CONFIG_RT_USING_UART0=y
|
||||
CONFIG_BSP_USING_GIC=y
|
||||
CONFIG_BSP_USING_GIC400=y
|
||||
# CONFIG_BSP_USING_GIC500 is not set
|
||||
CONFIG_BSP_USING_PIN=y
|
||||
CONFIG_BSP_USING_CORETIMER=y
|
||||
# CONFIG_BSP_USING_SYSTIMER is not set
|
||||
# CONFIG_BSP_USING_WDT is not set
|
||||
# CONFIG_BSP_USING_RTC is not set
|
||||
# CONFIG_BSP_USING_SDIO is not set
|
||||
|
||||
#
|
||||
# Board Peripheral Drivers
|
||||
#
|
||||
# CONFIG_BSP_USING_HDMI is not set
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
mainmenu "RT-Thread Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../../.."
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
option env="PKGS_ROOT"
|
||||
default "packages"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
|
||||
config BCM2711_SOC
|
||||
bool
|
||||
select ARCH_ARM_CORTEX_A72
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
select ARCH_CPU_64BIT
|
||||
default y
|
||||
|
||||
source "driver/Kconfig"
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
# Raspberry PI 4板级支持包说明
|
||||
|
||||
## 1. 简介
|
||||
|
||||
树莓派4B的核心处理器为博通BCM2711（四核1.5GHz，Cortex A72架构，树莓派3是四核A53）。LPDDR4内存，由5V/3A USB-C供电或GPIO 5V。
|
||||
|
||||
外设支持上，引入了双频Wi-Fi，蓝牙5.0，千兆网卡，MIPI CSI相机接口，两个USB口，40个扩展帧。
|
||||
|
||||
这份RT-Thread BSP是针对 Raspberry Pi 4的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
|
||||
|
||||
|
||||
## 2. 编译说明
|
||||
|
||||
Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。
|
||||
|
||||
将工具链解压到指定目录,并修改当前bsp下的`EXEC_PATH`为自定义gcc目录。
|
||||
|
||||
```
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'
|
||||
```
|
||||
|
||||
直接进入`bsp\raspberry-pi\raspi4`，输入scons编译即可。
|
||||
|
||||
|
||||
## 3. 执行
|
||||
|
||||
### 3.1 下载**Raspberry Pi Imager**，生成可以运行的raspbian SD卡
|
||||
|
||||
首先下载镜像
|
||||
|
||||
* [Raspberry Pi Imager for Ubuntu](https://downloads.raspberrypi.org/imager/imager_amd64.deb)
|
||||
* [Raspberry Pi Imager for Windows](https://downloads.raspberrypi.org/imager/imager.exe)
|
||||
* [Raspberry Pi Imager for macOS](https://downloads.raspberrypi.org/imager/imager.dmg)
|
||||
|
||||
### 3.2 准备好串口线
|
||||
|
||||
目前版本是使用raspi4的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示：
|
||||
|
||||
|
||||
|
||||
串口参数： 115200 8N1 ，硬件和软件流控为关。
|
||||
|
||||
### 3.3 程序下载
|
||||
|
||||
当编译生成了rtthread.bin文件后，我们可以将该文件放到sd卡上，并修改sd卡中的`config.txt`文件如下：
|
||||
|
||||
```
|
||||
enable_uart=1
|
||||
arm_64bit=1
|
||||
kernel=rtthread.bin
|
||||
```
|
||||
|
||||
按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息：
|
||||
|
||||
```text
|
||||
heap: 0x000c9350 - 0x040c9350
|
||||
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 4.0.3 build Apr 16 2020
|
||||
2006 - 2020 Copyright by rt-thread team
|
||||
Hi, this is RT-Thread!!
|
||||
msh />
|
||||
```
|
||||
|
||||
## 4. 支持情况
|
||||
|
||||
| 驱动 | 支持情况 | 备注 |
|
||||
| ------ | ---- | :------: |
|
||||
| UART | 支持 | UART0|
|
||||
|
||||
## 5. 联系人信息
|
||||
|
||||
维护人：[bernard][5]
|
||||
|
||||
[1]: https://www.rt-thread.org/page/download.html
|
||||
[2]: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads
|
||||
[3]: https://downloads.raspberrypi.org/raspbian_lite_latest
|
||||
[4]: https://etcher.io
|
||||
[5]: https://github.com/BernardXiong
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# for module compiling
|
||||
import os
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
from rtconfig import RTT_ROOT
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
from building import *
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
env['ASCOM'] = env['ASPPCOM']
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp')
|
||||
CPPPATH = [cwd, str(Dir('#'))]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-04-16 bigmagic first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
int main(int argc, char** argv)
|
||||
{
|
||||
rt_kprintf("Hi, this is RT-Thread!!\n");
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
|
||||
config BSP_SUPPORT_FPU
|
||||
bool "Using Float"
|
||||
default n
|
||||
|
||||
menu "Hardware Drivers Config"
|
||||
menu "BCM Peripheral Drivers"
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Using UART"
|
||||
select RT_USING_SERIAL
|
||||
default y
|
||||
|
||||
if BSP_USING_UART
|
||||
config RT_USING_UART0
|
||||
bool "Enabel UART 0"
|
||||
default y
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_GIC
|
||||
bool "Enable GIC"
|
||||
select RT_USING_GIC
|
||||
default y
|
||||
if BSP_USING_GIC
|
||||
config BSP_USING_GIC400
|
||||
bool "Enable GIC400"
|
||||
default y
|
||||
config BSP_USING_GIC500
|
||||
bool "Enable GIC500"
|
||||
default n
|
||||
endif
|
||||
|
||||
config BSP_USING_PIN
|
||||
bool "Using PIN"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
|
||||
config BSP_USING_CORETIMER
|
||||
bool "Using core timer"
|
||||
select RT_USING_CORETIMER
|
||||
default y
|
||||
|
||||
menuconfig BSP_USING_SYSTIMER
|
||||
bool "Enable SYSTIMER"
|
||||
select BSP_USING_SYSTIMER
|
||||
default n
|
||||
|
||||
if BSP_USING_SYSTIMER
|
||||
config RT_USING_SYSTIMER1
|
||||
bool "Enable sys timer1"
|
||||
default n
|
||||
config RT_USING_SYSTIMER3
|
||||
bool "Enable sys timer3"
|
||||
default n
|
||||
endif
|
||||
|
||||
config BSP_USING_WDT
|
||||
bool "Enable WDT"
|
||||
select RT_USING_WDT
|
||||
default n
|
||||
|
||||
menuconfig BSP_USING_RTC
|
||||
bool "Enable RTC"
|
||||
select RT_USING_RTC
|
||||
default n
|
||||
|
||||
if BSP_USING_RTC
|
||||
config BSP_USING_ALARM
|
||||
bool "Enable Alarm"
|
||||
select RT_USING_ALARM
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SDIO
|
||||
bool "Enable SDIO"
|
||||
select RT_USING_SDIO
|
||||
default n
|
||||
|
||||
if BSP_USING_SDIO
|
||||
config BSP_USING_SDIO0
|
||||
bool "Enable SDIO0"
|
||||
select RT_USING_SDIO
|
||||
default n
|
||||
endif
|
||||
endmenu
|
||||
|
||||
menu "Board Peripheral Drivers"
|
||||
menuconfig BSP_USING_HDMI
|
||||
bool "Enable HDMI"
|
||||
default n
|
||||
|
||||
if BSP_USING_HDMI
|
||||
config BSP_USING_HDMI_DISPLAY
|
||||
bool "HDMI DISPLAY"
|
||||
default n
|
||||
endif
|
||||
endmenu
|
||||
endmenu
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp')
|
||||
CPPPATH = [cwd, str(Dir('#'))]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-04-16 bigmagic first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "drv_uart.h"
|
||||
|
||||
#include "cp15.h"
|
||||
#include "mmu.h"
|
||||
|
||||
static rt_uint64_t timerStep;
|
||||
// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
|
||||
#define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040)
|
||||
#define TIMER_IRQ 30
|
||||
#define NON_SECURE_TIMER_IRQ (1 << 1)
|
||||
|
||||
int rt_hw_get_gtimer_frq(void);
|
||||
void rt_hw_set_gtimer_val(rt_uint64_t value);
|
||||
int rt_hw_get_gtimer_val(void);
|
||||
int rt_hw_get_cntpct_val(void);
|
||||
void rt_hw_gtimer_enable(void);
|
||||
|
||||
void core0_timer_enable_interrupt_controller()
|
||||
{
|
||||
CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ;
|
||||
}
|
||||
|
||||
void rt_hw_timer_isr(int vector, void *parameter)
|
||||
{
|
||||
rt_hw_set_gtimer_val(timerStep);
|
||||
rt_tick_increase();
|
||||
}
|
||||
|
||||
void rt_hw_timer_init(void)
|
||||
{
|
||||
rt_hw_interrupt_install(TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
|
||||
rt_hw_interrupt_umask(TIMER_IRQ);
|
||||
__ISB();
|
||||
timerStep = rt_hw_get_gtimer_frq();
|
||||
__DSB();
|
||||
timerStep /= RT_TICK_PER_SECOND;
|
||||
|
||||
rt_hw_gtimer_enable();
|
||||
rt_hw_set_gtimer_val(timerStep);
|
||||
core0_timer_enable_interrupt_controller();
|
||||
}
|
||||
|
||||
void idle_wfi(void)
|
||||
{
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the Hardware related stuffs. Called from rtthread_startup()
|
||||
* after interrupt disabled.
|
||||
*/
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
mmu_init();
|
||||
armv8_map(0, 0, 0x6400000, MEM_ATTR_MEMORY);
|
||||
armv8_map(0xFE200000, 0xFE200000, 0x200000, MEM_ATTR_IO);//uart gpio
|
||||
armv8_map(0xFF800000, 0xFF800000, 0x200000, MEM_ATTR_IO);//gic timer
|
||||
mmu_enable();
|
||||
|
||||
/* initialize hardware interrupt */
|
||||
rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
|
||||
rt_hw_vector_init(); // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
|
||||
|
||||
/* initialize uart */
|
||||
rt_hw_uart_init(); // driver/drv_uart.c
|
||||
#ifdef RT_USING_CONSOLE
|
||||
/* set console device */
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif /* RT_USING_CONSOLE */
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
/* initialize memory system */
|
||||
rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
|
||||
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
|
||||
#endif
|
||||
/* initialize timer for os tick */
|
||||
rt_hw_timer_init();
|
||||
rt_thread_idle_sethook(idle_wfi);
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-04-16 bigmagic first version
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H__
|
||||
#define BOARD_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern unsigned char __bss_start;
|
||||
extern unsigned char __bss_end;
|
||||
|
||||
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
|
||||
#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-04-16 bigmagic first version
|
||||
*/
|
||||
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#ifdef BSP_USING_PIN
|
||||
|
||||
static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
|
||||
{
|
||||
uint32_t fselnum = pin / 10;
|
||||
uint32_t fselrest = pin % 10;
|
||||
|
||||
uint32_t gpfsel = 0;
|
||||
gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3)));
|
||||
gpfsel |= (uint32_t)(mode << (fselrest * 3));
|
||||
|
||||
switch (fselnum)
|
||||
{
|
||||
case 0:
|
||||
GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel;
|
||||
break;
|
||||
case 1:
|
||||
GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
|
||||
break;
|
||||
case 2:
|
||||
GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel;
|
||||
break;
|
||||
case 3:
|
||||
GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel;
|
||||
break;
|
||||
case 4:
|
||||
GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel;
|
||||
break;
|
||||
case 5:
|
||||
GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
|
||||
{
|
||||
uint32_t num = pin / 32;
|
||||
|
||||
if(num == 0)
|
||||
{
|
||||
if(value == 0)
|
||||
{
|
||||
GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32);
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if(value == 0)
|
||||
{
|
||||
GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32);
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static const struct rt_pin_ops ops =
|
||||
{
|
||||
raspi_pin_mode,
|
||||
raspi_pin_write,
|
||||
raspi_pin_read,
|
||||
raspi_pin_attach_irq,
|
||||
raspi_pin_detach_irq,
|
||||
raspi_pin_irq_enable,
|
||||
};
|
||||
#endif
|
||||
|
||||
int rt_hw_gpio_init(void)
|
||||
{
|
||||
#ifdef BSP_USING_PIN
|
||||
rt_device_pin_register("gpio", &ops, RT_NULL);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(rt_hw_gpio_init);
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-04-16 bigmagic first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_GPIO_H__
|
||||
#define __DRV_GPIO_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "interrupt.h"
|
||||
|
||||
#define GPIO_BASE (0xFE000000 + 0x00200000)
|
||||
|
||||
#define GPIO_REG_GPFSEL0(BASE) HWREG32(BASE + 0x00)
|
||||
#define GPIO_REG_GPFSEL1(BASE) HWREG32(BASE + 0x04)
|
||||
#define GPIO_REG_GPFSEL2(BASE) HWREG32(BASE + 0x08)
|
||||
#define GPIO_REG_GPFSEL3(BASE) HWREG32(BASE + 0x0C)
|
||||
#define GPIO_REG_GPFSEL4(BASE) HWREG32(BASE + 0x10)
|
||||
#define GPIO_REG_GPFSEL5(BASE) HWREG32(BASE + 0x14)
|
||||
#define GPIO_REG_REV0(BASE) HWREG32(BASE + 0x18)
|
||||
#define GPIO_REG_GPSET0(BASE) HWREG32(BASE + 0x1C)
|
||||
#define GPIO_REG_GPSET1(BASE) HWREG32(BASE + 0x20)
|
||||
#define GPIO_REG_REV1(BASE) HWREG32(BASE + 0x24)
|
||||
#define GPIO_REG_GPCLR0(BASE) HWREG32(BASE + 0x28)
|
||||
#define GPIO_REG_GPCLR1(BASE) HWREG32(BASE + 0x2C)
|
||||
#define GPIO_REG_REV2(BASE) HWREG32(BASE + 0x30)
|
||||
#define GPIO_REG_GPLEV0(BASE) HWREG32(BASE + 0x34)
|
||||
#define GPIO_REG_GPLEV1(BASE) HWREG32(BASE + 0x38)
|
||||
#define GPIO_REG_REV3(BASE) HWREG32(BASE + 0x3C)
|
||||
#define GPIO_REG_GPEDS0(BASE) HWREG32(BASE + 0x40)
|
||||
#define GPIO_REG_GPEDS1(BASE) HWREG32(BASE + 0x44)
|
||||
#define GPIO_REG_REV4(BASE) HWREG32(BASE + 0x48)
|
||||
#define GPIO_REG_GPREN0(BASE) HWREG32(BASE + 0x4C)
|
||||
#define GPIO_REG_GPREN1(BASE) HWREG32(BASE + 0x50)
|
||||
#define GPIO_REG_REV5(BASE) HWREG32(BASE + 0x54)
|
||||
#define GPIO_REG_GPFEN0(BASE) HWREG32(BASE + 0x58)
|
||||
#define GPIO_REG_GPFEN1(BASE) HWREG32(BASE + 0x5C)
|
||||
#define GPIO_REG_REV6(BASE) HWREG32(BASE + 0x60)
|
||||
#define GPIO_REG_GPHEN0(BASE) HWREG32(BASE + 0x64)
|
||||
#define GPIO_REG_GPHEN1(BASE) HWREG32(BASE + 0x68)
|
||||
#define GPIO_REG_REV7(BASE) HWREG32(BASE + 0x6C)
|
||||
#define GPIO_REG_GPLEN0(BASE) HWREG32(BASE + 0x70)
|
||||
#define GPIO_REG_GPLEN1(BASE) HWREG32(BASE + 0x74)
|
||||
#define GPIO_REG_REV8(BASE) HWREG32(BASE + 0x78)
|
||||
#define GPIO_REG_GPAREN0(BASE) HWREG32(BASE + 0x7C)
|
||||
#define GPIO_REG_GPAREN1(BASE) HWREG32(BASE + 0x80)
|
||||
#define GPIO_REG_REV11(BASE) HWREG32(BASE + 0x84)
|
||||
#define GPIO_REG_GPAFEN0(BASE) HWREG32(BASE + 0x88)
|
||||
#define GPIO_REG_GPAFEN1(BASE) HWREG32(BASE + 0x8C)
|
||||
#define GPIO_REG_REV10(BASE) HWREG32(BASE + 0x90)
|
||||
#define GPIO_REG_GPPUD(BASE) HWREG32(BASE + 0x94)
|
||||
#define GPIO_REG_GPPUDCLK0(BASE) HWREG32(BASE + 0x98)
|
||||
#define GPIO_REG_GPPUDCLK1(BASE) HWREG32(BASE + 0x9C)
|
||||
#define GPIO_REG_REV9(BASE) HWREG32(BASE + 0xA0)
|
||||
#define GPIO_REG_TEST(BASE) HWREG32(BASE + 0xA4)
|
||||
|
||||
typedef enum {
|
||||
INPUT = 0b000,
|
||||
OUTPUT = 0b001,
|
||||
ALT0 = 0b100,
|
||||
ALT1 = 0b101,
|
||||
ALT2 = 0b110,
|
||||
ALT3 = 0b111,
|
||||
ALT4 = 0b011,
|
||||
ALT5 = 0b010
|
||||
} GPIO_FUNC;
|
||||
|
||||
|
||||
int rt_hw_gpio_init(void);
|
||||
|
||||
#endif /* __DRV_GPIO_H__ */
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-04-16 bigmagic first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "drv_uart.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#define UART0_BASE (0xFE000000 + 0x00201000)
|
||||
#define PL011_BASE UART0_BASE
|
||||
#define IRQ_PL011 (121 + 32)
|
||||
|
||||
#define UART_REFERENCE_CLOCK 48000000
|
||||
|
||||
struct hw_uart_device
|
||||
{
|
||||
rt_ubase_t hw_base;
|
||||
rt_uint32_t irqno;
|
||||
};
|
||||
|
||||
static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
struct hw_uart_device *uart;
|
||||
uint32_t bauddiv = (UART_REFERENCE_CLOCK / cfg->baud_rate)* 1000 / 16;
|
||||
uint32_t ibrd = bauddiv / 1000;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct hw_uart_device *)serial->parent.user_data;
|
||||
if(uart->hw_base == PL011_BASE)
|
||||
{
|
||||
uint32_t gpfsel = 0;
|
||||
|
||||
gpfsel &= ~((uint32_t)(0x07 << (4 * 3)));
|
||||
gpfsel |= (uint32_t)(ALT0 << (4 * 3));
|
||||
GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
|
||||
|
||||
gpfsel &= ~((uint32_t)(0x07 << (5 * 3)));
|
||||
gpfsel |= (uint32_t)(ALT0 << (5 * 3));
|
||||
GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
|
||||
|
||||
PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/
|
||||
PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/
|
||||
PL011_REG_IBRD(uart->hw_base) = ibrd;
|
||||
PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000);
|
||||
PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/
|
||||
PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct hw_uart_device *uart;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct hw_uart_device *)serial->parent.user_data;
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
/* disable rx irq */
|
||||
PL011_REG_IMSC(uart->hw_base) &= ~((uint32_t)PL011_IMSC_RXIM);
|
||||
rt_hw_interrupt_mask(uart->irqno);
|
||||
break;
|
||||
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
/* enable rx irq */
|
||||
PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM;
|
||||
rt_hw_interrupt_umask(uart->irqno);
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static int uart_putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
struct hw_uart_device *uart;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct hw_uart_device *)serial->parent.user_data;
|
||||
|
||||
while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF));
|
||||
PL011_REG_DR(uart->hw_base) = (uint8_t)c;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int uart_getc(struct rt_serial_device *serial)
|
||||
{
|
||||
int ch = -1;
|
||||
struct hw_uart_device *uart;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct hw_uart_device *)serial->parent.user_data;
|
||||
|
||||
if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0)
|
||||
{
|
||||
ch = PL011_REG_DR(uart->hw_base) & 0xff;
|
||||
}
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static const struct rt_uart_ops _uart_ops =
|
||||
{
|
||||
uart_configure,
|
||||
uart_control,
|
||||
uart_putc,
|
||||
uart_getc,
|
||||
};
|
||||
|
||||
static void rt_hw_uart_isr(int irqno, void *param)
|
||||
{
|
||||
struct rt_serial_device *serial = (struct rt_serial_device*)param;
|
||||
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
|
||||
PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE;
|
||||
}
|
||||
|
||||
|
||||
/* UART device driver structure */
|
||||
static struct hw_uart_device _uart0_device =
|
||||
{
|
||||
PL011_BASE,
|
||||
IRQ_PL011,
|
||||
};
|
||||
|
||||
static struct rt_serial_device _serial0;
|
||||
|
||||
int rt_hw_uart_init(void)
|
||||
{
|
||||
struct hw_uart_device *uart;
|
||||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||
|
||||
uart = &_uart0_device;
|
||||
|
||||
_serial0.ops = &_uart_ops;
|
||||
_serial0.config = config;
|
||||
|
||||
/* register UART1 device */
|
||||
rt_hw_serial_register(&_serial0, "uart",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
|
||||
uart);
|
||||
rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-04-16 bigmagic first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_UART_H__
|
||||
#define DRV_UART_H__
|
||||
|
||||
// register's bit
|
||||
#define PL011_FR_RI (1 << 8)
|
||||
#define PL011_FR_TXFE (1 << 7)
|
||||
#define PL011_FR_RXFF (1 << 6)
|
||||
#define PL011_FR_TXFF (1 << 5)
|
||||
#define PL011_FR_RXFE (1 << 4)
|
||||
#define PL011_FR_BUSY (1 << 3)
|
||||
#define PL011_FR_DCD (1 << 2)
|
||||
#define PL011_FR_DSR (1 << 1)
|
||||
#define PL011_FR_CTS (1 << 0)
|
||||
|
||||
#define PL011_LCRH_SPS (1 << 7)
|
||||
#define PL011_LCRH_WLEN_8 (3 << 5)
|
||||
#define PL011_LCRH_WLEN_7 (2 << 5)
|
||||
#define PL011_LCRH_WLEN_6 (1 << 5)
|
||||
#define PL011_LCRH_WLEN_5 (0 << 5)
|
||||
#define PL011_LCRH_FEN (1 << 4)
|
||||
#define PL011_LCRH_STP2 (1 << 3)
|
||||
#define PL011_LCRH_EPS (1 << 2)
|
||||
#define PL011_LCRH_PEN (1 << 1)
|
||||
#define PL011_LCRH_BRK (1 << 0)
|
||||
|
||||
#define PL011_CR_CTSEN (1 << 15)
|
||||
#define PL011_CR_RTSEN (1 << 14)
|
||||
#define PL011_CR_RTS (1 << 11)
|
||||
#define PL011_CR_DTR (1 << 10)
|
||||
#define PL011_CR_RXE (1 << 9)
|
||||
#define PL011_CR_TXE (1 << 8)
|
||||
#define PL011_CR_LBE (1 << 7)
|
||||
#define PL011_CR_SIRLP (1 << 2)
|
||||
#define PL011_CR_SIREN (1 << 1)
|
||||
#define PL011_CR_UARTEN (1 << 0)
|
||||
|
||||
#define PL011_IMSC_TXIM (1 << 5)
|
||||
#define PL011_IMSC_RXIM (1 << 4)
|
||||
|
||||
#define PL011_INTERRUPT_OVERRUN_ERROR (1 << 10)
|
||||
#define PL011_INTERRUPT_BREAK_ERROR (1 << 9)
|
||||
#define PL011_INTERRUPT_PARITY_ERROR (1 << 8)
|
||||
#define PL011_INTERRUPT_FRAMING_ERROR (1 << 7)
|
||||
#define PL011_INTERRUPT_RECEIVE_TIMEOUT (1 << 6)
|
||||
#define PL011_INTERRUPT_TRANSMIT (1 << 5)
|
||||
#define PL011_INTERRUPT_RECEIVE (1 << 4)
|
||||
#define PL011_INTERRUPT_nUARTCTS (1 << 1)
|
||||
|
||||
#define PL011_REG_DR(BASE) HWREG32(BASE + 0x00)
|
||||
#define PL011_REG_RSRECR(BASE) HWREG32(BASE + 0x04)
|
||||
#define PL011_REG_RESERVED0(BASE) HWREG32(BASE + 0x08)
|
||||
#define PL011_REG_FR(BASE) HWREG32(BASE + 0x18)
|
||||
#define PL011_REG_RESERVED1(BASE) HWREG32(BASE + 0x1C)
|
||||
#define PL011_REG_ILPR(BASE) HWREG32(BASE + 0x20)
|
||||
#define PL011_REG_IBRD(BASE) HWREG32(BASE + 0x24)
|
||||
#define PL011_REG_FBRD(BASE) HWREG32(BASE + 0x28)
|
||||
#define PL011_REG_LCRH(BASE) HWREG32(BASE + 0x2C)
|
||||
#define PL011_REG_CR(BASE) HWREG32(BASE + 0x30)
|
||||
#define PL011_REG_IFLS(BASE) HWREG32(BASE + 0x34)
|
||||
#define PL011_REG_IMSC(BASE) HWREG32(BASE + 0x38)
|
||||
#define PL011_REG_RIS(BASE) HWREG32(BASE + 0x3C)
|
||||
#define PL011_REG_MIS(BASE) HWREG32(BASE + 0x40)
|
||||
#define PL011_REG_ICR(BASE) HWREG32(BASE + 0x44)
|
||||
#define PL011_REG_DMACR(BASE) HWREG32(BASE + 0x48)
|
||||
#define PL011_REG_RESERVED2(BASE) HWREG32(BASE + 0x4C)
|
||||
#define PL011_REG_ITCR(BASE) HWREG32(BASE + 0x80)
|
||||
#define PL011_REG_ITIP(BASE) HWREG32(BASE + 0x84)
|
||||
#define PL011_REG_ITOP(BASE) HWREG32(BASE + 0x88)
|
||||
#define PL011_REG_TDR(BASE) HWREG32(BASE + 0x8C)
|
||||
|
||||
int rt_hw_uart_init(void);
|
||||
|
||||
#endif /* DRV_UART_H__ */
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#ifndef __RASPI4_H__
|
||||
#define __RASPI4_H__
|
||||
|
||||
#define ARM_GIC_NR_IRQS 512
|
||||
#define INTC_BASE 0xff800000
|
||||
#define GIC_V2_DISTRIBUTOR_BASE (INTC_BASE + 0x00041000)
|
||||
#define GIC_V2_CPU_INTERFACE_BASE (INTC_BASE + 0x00042000)
|
||||
#define GIC_V2_HYPERVISOR_BASE (INTC_BASE + 0x00044000)
|
||||
#define GIC_V2_VIRTUAL_CPU_BASE (INTC_BASE + 0x00046000)
|
||||
|
||||
#define GIC_PL400_DISTRIBUTOR_PPTR GIC_V2_DISTRIBUTOR_BASE
|
||||
#define GIC_PL400_CONTROLLER_PPTR GIC_V2_CPU_INTERFACE_BASE
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,153 @@
|
|||
/*
|
||||
* File : link.lds
|
||||
* COPYRIGHT (C) 2017, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* 2017-5-30 bernard first version
|
||||
*/
|
||||
|
||||
/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x80000;
|
||||
. = ALIGN(4096);
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.text.entrypoint)) /* The entry point */
|
||||
*(.vectors)
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
*(COMMON)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(16);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(16);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(16);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(16);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(16);
|
||||
|
||||
. = ALIGN(16);
|
||||
_etext = .;
|
||||
}
|
||||
|
||||
.eh_frame_hdr :
|
||||
{
|
||||
*(.eh_frame_hdr)
|
||||
*(.eh_frame_entry)
|
||||
}
|
||||
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
|
||||
|
||||
. = ALIGN(16);
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
|
||||
*(.data1)
|
||||
*(.data1.*)
|
||||
|
||||
. = ALIGN(16);
|
||||
_gp = ABSOLUTE(.); /* Base of small data */
|
||||
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
}
|
||||
|
||||
. = ALIGN(16);
|
||||
.ctors :
|
||||
{
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
KEEP(*(SORT(.ctors.*)))
|
||||
KEEP(*(.ctors))
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
}
|
||||
|
||||
.dtors :
|
||||
{
|
||||
PROVIDE(__dtors_start__ = .);
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*(.dtors))
|
||||
PROVIDE(__dtors_end__ = .);
|
||||
}
|
||||
|
||||
. = ALIGN(16);
|
||||
.bss :
|
||||
{
|
||||
PROVIDE(__bss_start = .);
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.dynbss)
|
||||
|
||||
PROVIDE(__bss_end = .);
|
||||
}
|
||||
_end = .;
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
|
||||
__bss_size = (__bss_end - __bss_start)>>3;
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Project Configuration */
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_ALIGN_SIZE 4
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 100
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 2048
|
||||
#define RT_USING_TIMER_SOFT
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 2048
|
||||
#define RT_DEBUG
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Kernel Device Object */
|
||||
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart"
|
||||
#define RT_VER_NUM 0x40003
|
||||
#define ARCH_CPU_64BIT
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
|
||||
/* C++ features */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_USING_MSH_DEFAULT
|
||||
#define FINSH_ARG_MAX 10
|
||||
|
||||
/* Device virtual file system */
|
||||
|
||||
#define RT_USING_DFS
|
||||
#define DFS_USING_WORKDIR
|
||||
#define DFS_FILESYSTEMS_MAX 2
|
||||
#define DFS_FILESYSTEM_TYPES_MAX 2
|
||||
#define DFS_FD_MAX 16
|
||||
#define RT_USING_DFS_DEVFS
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_PIPE_BUFSZ 512
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_PIN
|
||||
|
||||
/* Using USB */
|
||||
|
||||
|
||||
/* POSIX layer and C standard library */
|
||||
|
||||
#define RT_USING_LIBC
|
||||
#define RT_USING_POSIX
|
||||
|
||||
/* Network */
|
||||
|
||||
/* Socket abstraction layer */
|
||||
|
||||
|
||||
/* Network interface device */
|
||||
|
||||
|
||||
/* light weight TCP/IP stack */
|
||||
|
||||
|
||||
/* AT commands */
|
||||
|
||||
|
||||
/* VBUS(Virtual Software BUS) */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
|
||||
/* security packages */
|
||||
|
||||
|
||||
/* language packages */
|
||||
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
|
||||
/* tools packages */
|
||||
|
||||
|
||||
/* system packages */
|
||||
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
|
||||
/* Privated Packages of RealThread */
|
||||
|
||||
|
||||
/* Network Utilities */
|
||||
|
||||
#define BCM2711_SOC
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
/* BCM Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_UART
|
||||
#define RT_USING_UART0
|
||||
#define BSP_USING_GIC
|
||||
#define BSP_USING_GIC400
|
||||
#define BSP_USING_PIN
|
||||
#define BSP_USING_CORETIMER
|
||||
|
||||
/* Board Peripheral Drivers */
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH ='aarch64'
|
||||
CPU ='cortex-a72'
|
||||
CROSS_TOOL ='gcc'
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = r'../../..'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
# PREFIX = 'arm-none-eabi-'
|
||||
PREFIX = 'aarch64-elf-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -march=armv8-a -mtune=cortex-a72'
|
||||
CFLAGS = DEVICE + ' -Wall'
|
||||
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
|
||||
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
|
@ -9,6 +9,9 @@ cwd = GetCurrentDir()
|
|||
group = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
# add common code files
|
||||
group = group + SConscript(os.path.join('common', 'SConscript'))
|
||||
|
||||
# cpu porting code files
|
||||
if rtconfig.CPU != 'common':
|
||||
group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
|
||||
|
|
|
|||
|
|
@ -0,0 +1,24 @@
|
|||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
Import('rtconfig')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
# build for sub-directory
|
||||
list = os.listdir(cwd)
|
||||
objs = []
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
group = group + objs
|
||||
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
CPPPATH = [cwd]
|
||||
|
||||
gic400_group = Split('''
|
||||
gic_pl400.c
|
||||
''')
|
||||
|
||||
gic500_group = Split('''
|
||||
gic_pl500.c
|
||||
''')
|
||||
|
||||
src = ()
|
||||
if GetDepend('BSP_USING_GIC400'):
|
||||
src = gic400_group
|
||||
if GetDepend('BSP_USING_GIC500'):
|
||||
src = gic500_group
|
||||
|
||||
group = DefineGroup('gic', src, depend = ['BSP_USING_GIC'], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,262 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-20 Bernard first version
|
||||
* 2014-04-03 Grissiom many enhancements
|
||||
* 2018-11-22 Jesven add rt_hw_ipi_send()
|
||||
* add rt_hw_ipi_handler_install()
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "gic_pl400.h"
|
||||
#include "cp15.h"
|
||||
#include "iomap.h"
|
||||
|
||||
#define ARM_GIC_MAX_NR 1
|
||||
struct arm_gic
|
||||
{
|
||||
rt_uint32_t offset; /* the first interrupt index in the vector table */
|
||||
|
||||
rt_uint32_t dist_hw_base; /* the base address of the gic distributor */
|
||||
rt_uint32_t cpu_hw_base; /* the base addrees of the gic cpu interface */
|
||||
};
|
||||
|
||||
/* 'ARM_GIC_MAX_NR' is the number of cores */
|
||||
static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
|
||||
|
||||
static unsigned int _gic_max_irq;
|
||||
|
||||
int arm_gic_get_active_irq(rt_uint32_t index)
|
||||
{
|
||||
int irq;
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
|
||||
irq += _gic_table[index].offset;
|
||||
return irq;
|
||||
}
|
||||
|
||||
void arm_gic_ack(rt_uint32_t index, int irq)
|
||||
{
|
||||
rt_uint32_t mask = 1 << (irq % 32);
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0);
|
||||
|
||||
GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
|
||||
GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
|
||||
GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
|
||||
}
|
||||
|
||||
void arm_gic_mask(rt_uint32_t index, int irq)
|
||||
{
|
||||
rt_uint32_t mask = 1 << (irq % 32);
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0);
|
||||
|
||||
GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
|
||||
}
|
||||
|
||||
void arm_gic_clear_pending(rt_uint32_t index, int irq)
|
||||
{
|
||||
rt_uint32_t mask = 1 << (irq % 32);
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0);
|
||||
|
||||
GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
|
||||
}
|
||||
|
||||
void arm_gic_clear_active(rt_uint32_t index, int irq)
|
||||
{
|
||||
rt_uint32_t mask = 1 << (irq % 32);
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0);
|
||||
|
||||
GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
|
||||
}
|
||||
|
||||
/* Set up the cpu mask for the specific interrupt */
|
||||
void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
|
||||
{
|
||||
rt_uint32_t old_tgt;
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0);
|
||||
|
||||
old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
|
||||
|
||||
old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
|
||||
old_tgt |= cpumask << ((irq % 4)*8);
|
||||
|
||||
GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
|
||||
}
|
||||
|
||||
void arm_gic_umask(rt_uint32_t index, int irq)
|
||||
{
|
||||
rt_uint32_t mask = 1 << (irq % 32);
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
irq = irq - _gic_table[index].offset;
|
||||
RT_ASSERT(irq >= 0);
|
||||
|
||||
GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
|
||||
}
|
||||
|
||||
void arm_gic_dump_type(rt_uint32_t index)
|
||||
{
|
||||
unsigned int gic_type;
|
||||
|
||||
gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
|
||||
rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
|
||||
(GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
|
||||
_gic_table[index].dist_hw_base,
|
||||
_gic_max_irq,
|
||||
gic_type & (1 << 10) ? "has" : "no",
|
||||
gic_type);
|
||||
}
|
||||
|
||||
void arm_gic_dump(rt_uint32_t index)
|
||||
{
|
||||
unsigned int i, k;
|
||||
|
||||
k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
|
||||
rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
|
||||
rt_kprintf("--- hw mask ---\n");
|
||||
for (i = 0; i < _gic_max_irq / 32; i++)
|
||||
{
|
||||
rt_kprintf("0x%08x, ",
|
||||
GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
|
||||
i * 32));
|
||||
}
|
||||
rt_kprintf("\n--- hw pending ---\n");
|
||||
for (i = 0; i < _gic_max_irq / 32; i++)
|
||||
{
|
||||
rt_kprintf("0x%08x, ",
|
||||
GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
|
||||
i * 32));
|
||||
}
|
||||
rt_kprintf("\n--- hw active ---\n");
|
||||
for (i = 0; i < _gic_max_irq / 32; i++)
|
||||
{
|
||||
rt_kprintf("0x%08x, ",
|
||||
GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
|
||||
i * 32));
|
||||
}
|
||||
rt_kprintf("\n");
|
||||
}
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status);
|
||||
#endif
|
||||
|
||||
int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
|
||||
{
|
||||
unsigned int gic_type, i;
|
||||
rt_uint32_t cpumask = 1 << 0;
|
||||
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
_gic_table[index].dist_hw_base = dist_base;
|
||||
_gic_table[index].offset = irq_start;
|
||||
|
||||
/* Find out how many interrupts are supported. */
|
||||
gic_type = GIC_DIST_TYPE(dist_base);
|
||||
_gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
|
||||
|
||||
/*
|
||||
* The GIC only supports up to 1020 interrupt sources.
|
||||
* Limit this to either the architected maximum, or the
|
||||
* platform maximum.
|
||||
*/
|
||||
if (_gic_max_irq > 1020)
|
||||
_gic_max_irq = 1020;
|
||||
if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */
|
||||
_gic_max_irq = ARM_GIC_NR_IRQS;
|
||||
|
||||
cpumask |= cpumask << 8;
|
||||
cpumask |= cpumask << 16;
|
||||
cpumask |= cpumask << 24;
|
||||
|
||||
GIC_DIST_CTRL(dist_base) = 0x0;
|
||||
|
||||
/* Set all global interrupts to be level triggered, active low. */
|
||||
for (i = 32; i < _gic_max_irq; i += 16)
|
||||
GIC_DIST_CONFIG(dist_base, i) = 0x0;
|
||||
|
||||
/* Set all global interrupts to this CPU only. */
|
||||
for (i = 32; i < _gic_max_irq; i += 4)
|
||||
GIC_DIST_TARGET(dist_base, i) = cpumask;
|
||||
|
||||
/* Set priority on all interrupts. */
|
||||
for (i = 0; i < _gic_max_irq; i += 4)
|
||||
GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
|
||||
|
||||
/* Disable all interrupts. */
|
||||
for (i = 0; i < _gic_max_irq; i += 32)
|
||||
GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
|
||||
|
||||
#if 0
|
||||
/* All interrupts defaults to IGROUP1(IRQ). */
|
||||
for (i = 0; i < _gic_max_irq; i += 32)
|
||||
GIC_DIST_IGROUP(dist_base, i) = 0xffffffff;
|
||||
#endif
|
||||
for (i = 0; i < _gic_max_irq; i += 32)
|
||||
GIC_DIST_IGROUP(dist_base, i) = 0;
|
||||
|
||||
/* Enable group0 and group1 interrupt forwarding. */
|
||||
GIC_DIST_CTRL(dist_base) = 0x01;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
|
||||
{
|
||||
RT_ASSERT(index < ARM_GIC_MAX_NR);
|
||||
|
||||
_gic_table[index].cpu_hw_base = cpu_base;
|
||||
|
||||
GIC_CPU_PRIMASK(cpu_base) = 0xf0;
|
||||
GIC_CPU_BINPOINT(cpu_base) = 0x7;
|
||||
/* Enable CPU interrupt */
|
||||
GIC_CPU_CTRL(cpu_base) = 0x01;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void arm_gic_set_group(rt_uint32_t index, int vector, int group)
|
||||
{
|
||||
/* As for GICv2, there are only group0 and group1. */
|
||||
RT_ASSERT(group <= 1);
|
||||
RT_ASSERT(vector < _gic_max_irq);
|
||||
|
||||
if (group == 0)
|
||||
{
|
||||
GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
|
||||
vector) &= ~(1 << (vector % 32));
|
||||
}
|
||||
else if (group == 1)
|
||||
{
|
||||
GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
|
||||
vector) |= (1 << (vector % 32));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-20 Bernard first version
|
||||
*/
|
||||
|
||||
#ifndef __GIC_PL400_H__
|
||||
#define __GIC_PL400_H__
|
||||
|
||||
#include <rthw.h>
|
||||
#include <board.h>
|
||||
|
||||
#define __REG32(x) (*((volatile unsigned int*)((rt_uint64_t)x)))
|
||||
|
||||
#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00)
|
||||
#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04)
|
||||
#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08)
|
||||
#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c)
|
||||
#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10)
|
||||
#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14)
|
||||
#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18)
|
||||
|
||||
#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000)
|
||||
#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004)
|
||||
#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4)
|
||||
#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4)
|
||||
#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4)
|
||||
#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4)
|
||||
#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4)
|
||||
#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4)
|
||||
#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4)
|
||||
#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4)
|
||||
#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4)
|
||||
#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
|
||||
#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00)
|
||||
#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4)
|
||||
#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8)
|
||||
|
||||
int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
|
||||
int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
|
||||
|
||||
void arm_gic_mask(rt_uint32_t index, int irq);
|
||||
void arm_gic_umask(rt_uint32_t index, int irq);
|
||||
void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
|
||||
void arm_gic_set_group(rt_uint32_t index, int vector, int group);
|
||||
|
||||
int arm_gic_get_active_irq(rt_uint32_t index);
|
||||
void arm_gic_ack(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_clear_active(rt_uint32_t index, int irq);
|
||||
void arm_gic_clear_pending(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_dump_type(rt_uint32_t index);
|
||||
void arm_gic_dump(rt_uint32_t index);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -1,16 +1,13 @@
|
|||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
Import('rtconfig')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp')
|
||||
asm_src = Split('''
|
||||
context_gcc.S
|
||||
vector_gcc.S
|
||||
entry_point.S
|
||||
cpu_gcc.S
|
||||
cache.S
|
||||
''')
|
||||
src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('cpu', src + asm_src, depend = [''], CPPPATH = CPPPATH)
|
||||
group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* Date Author Notes
|
||||
* 2020-04-16 bigmagic first version
|
||||
*/
|
||||
|
||||
#ifndef __INTERRUPT_H__
|
||||
|
|
@ -19,8 +19,6 @@
|
|||
#define INT_IRQ 0x00
|
||||
#define INT_FIQ 0x01
|
||||
|
||||
//void rt_hw_vector_init(void);
|
||||
|
||||
void rt_hw_interrupt_init(void);
|
||||
void rt_hw_interrupt_mask(int vector);
|
||||
void rt_hw_interrupt_umask(int vector);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,13 @@
|
|||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
Import('rtconfig')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,111 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Date Author Notes
|
||||
* 2020-01-15 bigmagic the first version
|
||||
*/
|
||||
|
||||
.section ".text.entrypoint"
|
||||
|
||||
.set EL1_stack, __el1_stack
|
||||
|
||||
.global _start
|
||||
|
||||
// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware
|
||||
// loads 'kernel8.img' file in.
|
||||
_start:
|
||||
// read cpu id, stop slave cores
|
||||
mrs x1, mpidr_el1 // MPIDR_EL1: Multi-Processor Affinity Register
|
||||
and x1, x1, #3
|
||||
cbz x1, .L__cpu_0 // .L prefix is the local label in ELF
|
||||
|
||||
// cpu id > 0, stop
|
||||
// cpu id == 0 will also goto here after returned from entry() if possible
|
||||
.L__current_cpu_idle:
|
||||
wfe
|
||||
b .L__current_cpu_idle
|
||||
|
||||
.L__cpu_0: // cpu id == 0
|
||||
|
||||
// set stack before our code
|
||||
|
||||
/* Define stack pointer for current exception level */
|
||||
// ldr x2, =EL1_stack
|
||||
// mov sp, x2
|
||||
|
||||
ldr x1, =_start
|
||||
|
||||
// set up EL1
|
||||
mrs x0, CurrentEL // CurrentEL Register. bit 2, 3. Others reserved
|
||||
and x0, x0, #12 // clear reserved bits
|
||||
|
||||
// running at EL3?
|
||||
cmp x0, #12 // 1100b. So, EL3
|
||||
bne .L__not_in_el3 // 11? !EL3 -> 5:
|
||||
|
||||
// should never be executed, just for completeness. (EL3)
|
||||
mov x2, #0x5b1
|
||||
msr scr_el3, x2 // SCR_ELn Secure Configuration Register
|
||||
mov x2, #0x3c9
|
||||
msr spsr_el3, x2 // SPSR_ELn. Saved Program Status Register. 1111001001
|
||||
adr x2, .L__not_in_el3
|
||||
msr elr_el3, x2
|
||||
eret // Exception Return: from EL3, continue from .L__not_in_el3
|
||||
|
||||
// running at EL2 or EL1
|
||||
.L__not_in_el3:
|
||||
cmp x0, #4 // 0x04 0100 EL1
|
||||
beq .L__in_el1 // EL1 -> 5:
|
||||
|
||||
// in EL2
|
||||
msr sp_el1, x1 // Set sp of EL1 to _start
|
||||
|
||||
// enable CNTP for EL1
|
||||
mrs x0, cnthctl_el2 // Counter-timer Hypervisor Control register
|
||||
orr x0, x0, #3
|
||||
msr cnthctl_el2, x0
|
||||
msr cntvoff_el2, xzr
|
||||
|
||||
// enable AArch64 in EL1
|
||||
mov x0, #(1 << 31) // AArch64
|
||||
orr x0, x0, #(1 << 1) // SWIO hardwired on Pi3
|
||||
msr hcr_el2, x0
|
||||
mrs x0, hcr_el2
|
||||
|
||||
// change execution level to EL1
|
||||
mov x2, #0x3c4
|
||||
msr spsr_el2, x2 // 1111000100
|
||||
adr x2, .L__in_el1
|
||||
msr elr_el2, x2
|
||||
eret // exception return. from EL2. continue from .L__in_el1
|
||||
|
||||
.L__in_el1:
|
||||
mov sp, x1 // in EL1. Set sp to _start
|
||||
|
||||
// Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction
|
||||
mov x1, #0x00300000 // Don't trap any SIMD/FP instructions in both EL0 and EL1
|
||||
msr cpacr_el1, x1
|
||||
|
||||
mrs x1, sctlr_el1
|
||||
orr x1, x1, #(1 << 12)
|
||||
bic x1, x1, #(3 << 3)
|
||||
bic x1, x1, #(1 << 1)
|
||||
msr sctlr_el1, x1
|
||||
|
||||
// clear bss
|
||||
ldr x1, =__bss_start
|
||||
ldr w2, =__bss_size
|
||||
|
||||
.L__clean_bss_loop:
|
||||
cbz w2, .L__jump_to_entry
|
||||
str xzr, [x1], #8
|
||||
sub w2, w2, #1
|
||||
cbnz w2, .L__clean_bss_loop
|
||||
|
||||
// jump to C code, should not return
|
||||
.L__jump_to_entry:
|
||||
bl entry
|
||||
// for failsafe, halt this core too
|
||||
b .L__current_cpu_idle
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-04-16 bigmagic first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <gic_pl400.h>
|
||||
#include <board.h>
|
||||
#include <armv8.h>
|
||||
#include "iomap.h"
|
||||
|
||||
#define MAX_HANDLERS 256
|
||||
#define GIC_ACK_INTID_MASK 0x000003ff
|
||||
|
||||
#ifdef RT_USING_SMP
|
||||
#define rt_interrupt_nest rt_cpu_self()->irq_nest
|
||||
#else
|
||||
extern volatile rt_uint8_t rt_interrupt_nest;
|
||||
#endif
|
||||
|
||||
extern int system_vectors;
|
||||
|
||||
/* exception and interrupt handler table */
|
||||
struct rt_irq_desc isr_table[MAX_HANDLERS];
|
||||
|
||||
rt_ubase_t rt_interrupt_from_thread;
|
||||
rt_ubase_t rt_interrupt_to_thread;
|
||||
rt_ubase_t rt_thread_switch_interrupt_flag;
|
||||
|
||||
void rt_hw_vector_init(void)
|
||||
{
|
||||
rt_hw_set_current_vbar((rt_ubase_t)&system_vectors); // cpu_gcc.S
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initialize hardware interrupt
|
||||
*/
|
||||
void rt_hw_interrupt_init(void)
|
||||
{
|
||||
|
||||
rt_uint32_t gic_cpu_base = 0;
|
||||
rt_uint32_t gic_dist_base = 0;
|
||||
|
||||
/* initialize ARM GIC */
|
||||
gic_dist_base = GIC_PL400_DISTRIBUTOR_PPTR;
|
||||
gic_cpu_base = GIC_PL400_CONTROLLER_PPTR;
|
||||
arm_gic_dist_init(0, gic_dist_base, 0);
|
||||
arm_gic_cpu_init(0, gic_cpu_base);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will install a interrupt service routine to a interrupt.
|
||||
* @param vector the interrupt number
|
||||
* @param new_handler the interrupt service routine to be installed
|
||||
* @param old_handler the old interrupt service routine
|
||||
*/
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name)
|
||||
{
|
||||
rt_isr_handler_t old_handler = RT_NULL;
|
||||
|
||||
if (vector < MAX_HANDLERS)
|
||||
{
|
||||
old_handler = isr_table[vector].handler;
|
||||
|
||||
if (handler != RT_NULL)
|
||||
{
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
|
||||
#endif /* RT_USING_INTERRUPT_INFO */
|
||||
isr_table[vector].handler = handler;
|
||||
isr_table[vector].param = param;
|
||||
}
|
||||
}
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_mask(int vector)
|
||||
{
|
||||
arm_gic_mask(0, vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will un-mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_umask(int vector)
|
||||
{
|
||||
arm_gic_umask(0, vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function returns the active interrupt number.
|
||||
* @param none
|
||||
*/
|
||||
int rt_hw_interrupt_get_irq(void)
|
||||
{
|
||||
return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function acknowledges the interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_ack(int vector)
|
||||
{
|
||||
arm_gic_ack(0, vector);
|
||||
}
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-04-16 bigmagic first version
|
||||
*/
|
||||
|
||||
#ifndef __INTERRUPT_H__
|
||||
#define __INTERRUPT_H__
|
||||
|
||||
#include <rthw.h>
|
||||
#include <board.h>
|
||||
|
||||
#define INT_IRQ 0x00
|
||||
#define INT_FIQ 0x01
|
||||
|
||||
void rt_hw_interrupt_init(void);
|
||||
void rt_hw_interrupt_mask(int vector);
|
||||
void rt_hw_interrupt_umask(int vector);
|
||||
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-09-23 Bernard the first version
|
||||
* 2011-10-05 Bernard add thumb mode
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
#include <armv8.h>
|
||||
|
||||
#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0)
|
||||
#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0)
|
||||
#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0)
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||
rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
rt_ubase_t *stk;
|
||||
rt_ubase_t current_el;
|
||||
|
||||
stk = (rt_ubase_t*)stack_addr;
|
||||
|
||||
*(--stk) = ( rt_ubase_t ) 11; /* X1 */
|
||||
*(--stk) = ( rt_ubase_t ) parameter; /* X0 */
|
||||
*(--stk) = ( rt_ubase_t ) 33; /* X3 */
|
||||
*(--stk) = ( rt_ubase_t ) 22; /* X2 */
|
||||
*(--stk) = ( rt_ubase_t ) 55; /* X5 */
|
||||
*(--stk) = ( rt_ubase_t ) 44; /* X4 */
|
||||
*(--stk) = ( rt_ubase_t ) 77; /* X7 */
|
||||
*(--stk) = ( rt_ubase_t ) 66; /* X6 */
|
||||
*(--stk) = ( rt_ubase_t ) 99; /* X9 */
|
||||
*(--stk) = ( rt_ubase_t ) 88; /* X8 */
|
||||
*(--stk) = ( rt_ubase_t ) 11; /* X11 */
|
||||
*(--stk) = ( rt_ubase_t ) 10; /* X10 */
|
||||
*(--stk) = ( rt_ubase_t ) 13; /* X13 */
|
||||
*(--stk) = ( rt_ubase_t ) 12; /* X12 */
|
||||
*(--stk) = ( rt_ubase_t ) 15; /* X15 */
|
||||
*(--stk) = ( rt_ubase_t ) 14; /* X14 */
|
||||
*(--stk) = ( rt_ubase_t ) 17; /* X17 */
|
||||
*(--stk) = ( rt_ubase_t ) 16; /* X16 */
|
||||
*(--stk) = ( rt_ubase_t ) 19; /* X19 */
|
||||
*(--stk) = ( rt_ubase_t ) 18; /* X18 */
|
||||
*(--stk) = ( rt_ubase_t ) 21; /* X21 */
|
||||
*(--stk) = ( rt_ubase_t ) 20; /* X20 */
|
||||
*(--stk) = ( rt_ubase_t ) 23; /* X23 */
|
||||
*(--stk) = ( rt_ubase_t ) 22; /* X22 */
|
||||
*(--stk) = ( rt_ubase_t ) 25; /* X25 */
|
||||
*(--stk) = ( rt_ubase_t ) 24; /* X24 */
|
||||
*(--stk) = ( rt_ubase_t ) 27; /* X27 */
|
||||
*(--stk) = ( rt_ubase_t ) 26; /* X26 */
|
||||
*(--stk) = ( rt_ubase_t ) 29; /* X29 */
|
||||
*(--stk) = ( rt_ubase_t ) 28; /* X28 */
|
||||
*(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */
|
||||
*(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */
|
||||
|
||||
current_el = rt_hw_get_current_el();
|
||||
|
||||
if(current_el == 3)
|
||||
{
|
||||
*(--stk) = INITIAL_SPSR_EL3;
|
||||
}
|
||||
else if(current_el == 2)
|
||||
{
|
||||
*(--stk) = INITIAL_SPSR_EL2;
|
||||
}
|
||||
else
|
||||
{
|
||||
*(--stk) = INITIAL_SPSR_EL1;
|
||||
}
|
||||
|
||||
*(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */
|
||||
|
||||
/* return task's current stack address */
|
||||
return (rt_uint8_t *)stk;
|
||||
}
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Date Author Notes
|
||||
* 2018-10-06 ZhaoXiaowei the first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
|
||||
#include "interrupt.h"
|
||||
#include "armv8.h"
|
||||
|
||||
extern struct rt_thread *rt_current_thread;
|
||||
#ifdef RT_USING_FINSH
|
||||
extern long list_thread(void);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* this function will show registers of CPU
|
||||
*
|
||||
* @param regs the registers point
|
||||
*/
|
||||
void rt_hw_show_register(struct rt_hw_exp_stack *regs)
|
||||
{
|
||||
rt_kprintf("Execption:\n");
|
||||
rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
|
||||
rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
|
||||
rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
|
||||
rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
|
||||
rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
|
||||
rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
|
||||
rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
|
||||
rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
|
||||
rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
|
||||
rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
|
||||
}
|
||||
|
||||
/**
|
||||
* When comes across an instruction which it cannot handle,
|
||||
* it takes the undefined instruction trap.
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
|
||||
{
|
||||
rt_kprintf("error exception:\n");
|
||||
rt_hw_show_register(regs);
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
#define GIC_ACK_INTID_MASK 0x000003ff
|
||||
|
||||
int rt_hw_interrupt_get_irq(void);
|
||||
void rt_hw_interrupt_ack(int fiq_irq);
|
||||
|
||||
void rt_hw_trap_irq(void)
|
||||
{
|
||||
void *param;
|
||||
int ir;
|
||||
rt_isr_handler_t isr_func;
|
||||
extern struct rt_irq_desc isr_table[];
|
||||
|
||||
ir = rt_hw_interrupt_get_irq();
|
||||
if (ir == 1023)
|
||||
{
|
||||
/* Spurious interrupt */
|
||||
return;
|
||||
}
|
||||
|
||||
/* get interrupt service routine */
|
||||
isr_func = isr_table[ir].handler;
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
isr_table[ir].counter++;
|
||||
#endif
|
||||
if (isr_func)
|
||||
{
|
||||
/* Interrupt for myself. */
|
||||
param = isr_table[ir].param;
|
||||
/* turn to interrupt service routine */
|
||||
isr_func(ir, param);
|
||||
}
|
||||
|
||||
/* end of interrupt */
|
||||
rt_hw_interrupt_ack(ir);
|
||||
|
||||
}
|
||||
|
||||
void rt_hw_trap_fiq(void)
|
||||
{
|
||||
}
|
||||
Loading…
Reference in New Issue