[bsp]support cvitek sdhci drvier (#8849)

support cvitek sdhci drvier

bsp/cvitek/README.md

@@ -60,6 +60,10 @@ $ scons
 | i2c  | 支持 |  |
 | adc | 支持 |  |
 | spi | 支持 | 默认CS引脚，每个数据之间CS会拉高，请根据时序选择GPIO作为CS。若读取数据，tx需持续dummy数据。|
+| pwm | 支持 |  |
+| timer | 支持 |  |
+| wdt | 支持 |  |
+| sdio | 支持 |  |
 
 ## 支持开发板
 - milk-v duo: [https://milkv.io/duo](https://milkv.io/duo)

bsp/cvitek/cv18xx_risc-v/.config

@@ -1,7 +1,3 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# RT-Thread Project Configuration
-#
 
 #
 # RT-Thread Kernel
@@ -33,11 +29,17 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192
 #
 # kservice optimization
 #
-CONFIG_RT_KSERVICE_USING_STDLIB=y
-# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
-# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
 # CONFIG_RT_USING_TINY_FFS is not set
-CONFIG_RT_KPRINTF_USING_LONGLONG=y
+# end of kservice optimization
+
+#
+# klibc optimization
+#
+# CONFIG_RT_KLIBC_USING_STDLIB is not set
+# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set
+CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG=y
+# end of klibc optimization
+
 CONFIG_RT_USING_DEBUG=y
 CONFIG_RT_DEBUGING_COLOR=y
 CONFIG_RT_DEBUGING_CONTEXT=y
@@ -54,6 +56,7 @@ CONFIG_RT_USING_MAILBOX=y
 CONFIG_RT_USING_MESSAGEQUEUE=y
 # CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
 # CONFIG_RT_USING_SIGNALS is not set
+# end of Inter-Thread communication
 
 #
 # Memory Management
@@ -71,6 +74,8 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
 # CONFIG_RT_USING_MEMTRACE is not set
 # CONFIG_RT_USING_HEAP_ISR is not set
 CONFIG_RT_USING_HEAP=y
+# end of Memory Management
+
 CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_DEVICE_OPS=y
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
@@ -79,15 +84,13 @@ CONFIG_RT_USING_DEVICE_OPS=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=256
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
-CONFIG_RT_VER_NUM=0x50100
+CONFIG_RT_VER_NUM=0x50200
 CONFIG_RT_USING_STDC_ATOMIC=y
 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
+# end of RT-Thread Kernel
+
 CONFIG_ARCH_CPU_64BIT=y
 CONFIG_RT_USING_CACHE=y
-# CONFIG_RT_USING_HW_ATOMIC is not set
-# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
-# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
-# CONFIG_RT_USING_CPU_FFS is not set
 CONFIG_ARCH_MM_MMU=y
 CONFIG_ARCH_RISCV=y
 CONFIG_ARCH_RISCV64=y
@@ -126,12 +129,40 @@ CONFIG_DFS_USING_WORKDIR=y
 CONFIG_DFS_FD_MAX=16
 # CONFIG_RT_USING_DFS_V1 is not set
 CONFIG_RT_USING_DFS_V2=y
-# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
+# CONFIG_RT_DFS_ELM_USE_EXFAT is not set
+# end of elm-chan's FatFs, Generic FAT Filesystem Module
+
 CONFIG_RT_USING_DFS_DEVFS=y
-# CONFIG_RT_USING_DFS_ROMFS is not set
+CONFIG_RT_USING_DFS_ROMFS=y
+# CONFIG_RT_USING_DFS_ROMFS_USER_ROOT is not set
 # CONFIG_RT_USING_DFS_CROMFS is not set
 # CONFIG_RT_USING_DFS_TMPFS is not set
 # CONFIG_RT_USING_DFS_MQUEUE is not set
+# end of DFS: device virtual file system
+
 # CONFIG_RT_USING_FAL is not set
 
 #
@@ -164,7 +195,13 @@ CONFIG_RT_USING_RANDOM=y
 CONFIG_RT_USING_RTC=y
 # CONFIG_RT_USING_ALARM is not set
 # CONFIG_RT_USING_SOFT_RTC is not set
-# CONFIG_RT_USING_SDIO is not set
+CONFIG_RT_USING_SDIO=y
+CONFIG_RT_SDIO_STACK_SIZE=4096
+CONFIG_RT_SDIO_THREAD_PRIORITY=15
+CONFIG_RT_MMCSD_STACK_SIZE=4096
+CONFIG_RT_MMCSD_THREAD_PREORITY=22
+CONFIG_RT_MMCSD_MAX_PARTITION=16
+# CONFIG_RT_SDIO_DEBUG is not set
 # CONFIG_RT_USING_SPI is not set
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_AUDIO is not set
@@ -184,9 +221,10 @@ CONFIG_RT_USING_KTIME=y
 #
 # Using USB
 #
-# CONFIG_RT_USING_USB is not set
 # CONFIG_RT_USING_USB_HOST is not set
 # CONFIG_RT_USING_USB_DEVICE is not set
+# end of Using USB
+# end of Device Drivers
 
 #
 # C/C++ and POSIX layer
@@ -204,6 +242,8 @@ CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
 CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
 CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
 CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+# end of Timezone and Daylight Saving Time
+# end of ISO-ANSI C layer
 
 #
 # POSIX (Portable Operating System Interface) layer
@@ -235,7 +275,11 @@ CONFIG_RT_USING_POSIX_TIMER=y
 #
 # Socket is in the 'Network' category
 #
+# end of Interprocess Communication (IPC)
+# end of POSIX (Portable Operating System Interface) layer
+
 # CONFIG_RT_USING_CPLUSPLUS is not set
+# end of C/C++ and POSIX layer
 
 #
 # Network
@@ -244,12 +288,14 @@ CONFIG_RT_USING_POSIX_TIMER=y
 # CONFIG_RT_USING_NETDEV is not set
 # CONFIG_RT_USING_LWIP is not set
 # CONFIG_RT_USING_AT is not set
+# end of Network
 
 #
 # Memory protection
 #
 # CONFIG_RT_USING_MEM_PROTECTION is not set
 # CONFIG_RT_USING_HW_STACK_GUARD is not set
+# end of Memory protection
 
 #
 # Utilities
@@ -265,12 +311,16 @@ CONFIG_RT_USING_ADT_BITMAP=y
 CONFIG_RT_USING_ADT_HASHMAP=y
 CONFIG_RT_USING_ADT_REF=y
 # CONFIG_RT_USING_RT_LINK is not set
+# end of Utilities
+
 # CONFIG_RT_USING_VBUS is not set
+# end of RT-Thread Components
 
 #
 # RT-Thread Utestcases
 #
 # CONFIG_RT_USING_UTESTCASES is not set
+# end of RT-Thread Utestcases
 
 #
 # RT-Thread online packages
@@ -279,7 +329,6 @@ CONFIG_RT_USING_ADT_REF=y
 #
 # IoT - internet of things
 #
-# CONFIG_PKG_USING_LWIP is not set
 # CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
 # CONFIG_PKG_USING_UMQTT is not set
@@ -301,27 +350,35 @@ CONFIG_RT_USING_ADT_REF=y
 # Marvell WiFi
 #
 # CONFIG_PKG_USING_WLANMARVELL is not set
+# end of Marvell WiFi
 
 #
 # Wiced WiFi
 #
 # CONFIG_PKG_USING_WLAN_WICED is not set
+# end of Wiced WiFi
+
 # CONFIG_PKG_USING_RW007 is not set
 
 #
 # CYW43012 WiFi
 #
 # CONFIG_PKG_USING_WLAN_CYW43012 is not set
+# end of CYW43012 WiFi
 
 #
 # BL808 WiFi
 #
 # CONFIG_PKG_USING_WLAN_BL808 is not set
+# end of BL808 WiFi
 
 #
 # CYW43439 WiFi
 #
 # CONFIG_PKG_USING_WLAN_CYW43439 is not set
+# end of CYW43439 WiFi
+# end of Wi-Fi
+
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
@@ -344,6 +401,8 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
 # CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# end of IoT Cloud
+
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
 # CONFIG_PKG_USING_OTA_DOWNLOADER is not set
@@ -364,6 +423,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
 # CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
 # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 # CONFIG_PKG_USING_WAYZ_IOTKIT is not set
 # CONFIG_PKG_USING_MAVLINK is not set
@@ -385,6 +445,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set
 # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
 # CONFIG_PKG_USING_LHC_MODBUS is not set
+# end of IoT - internet of things
 
 #
 # security packages
@@ -395,6 +456,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_TINYCRYPT is not set
 # CONFIG_PKG_USING_TFM is not set
 # CONFIG_PKG_USING_YD_CRYPTO is not set
+# end of security packages
 
 #
 # language packages
@@ -410,18 +472,22 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_JSMN is not set
 # CONFIG_PKG_USING_AGILE_JSMN is not set
 # CONFIG_PKG_USING_PARSON is not set
+# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
 
 #
 # XML: Extensible Markup Language
 #
 # CONFIG_PKG_USING_SIMPLE_XML is not set
 # CONFIG_PKG_USING_EZXML is not set
+# end of XML: Extensible Markup Language
+
 # CONFIG_PKG_USING_LUATOS_SOC is not set
 # CONFIG_PKG_USING_LUA is not set
 # CONFIG_PKG_USING_JERRYSCRIPT is not set
 # CONFIG_PKG_USING_MICROPYTHON is not set
 # CONFIG_PKG_USING_PIKASCRIPT is not set
 # CONFIG_PKG_USING_RTT_RUST is not set
+# end of language packages
 
 #
 # multimedia packages
@@ -433,12 +499,15 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_LVGL is not set
 # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
 # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+# end of LVGL: powerful and easy-to-use embedded GUI library
 
 #
 # u8g2: a monochrome graphic library
 #
 # CONFIG_PKG_USING_U8G2_OFFICIAL is not set
 # CONFIG_PKG_USING_U8G2 is not set
+# end of u8g2: a monochrome graphic library
+
 # CONFIG_PKG_USING_OPENMV is not set
 # CONFIG_PKG_USING_MUPDF is not set
 # CONFIG_PKG_USING_STEMWIN is not set
@@ -458,6 +527,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_GUIENGINE is not set
 # CONFIG_PKG_USING_3GPP_AMRNB is not set
+# end of multimedia packages
 
 #
 # tools packages
@@ -506,6 +576,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
 # CONFIG_PKG_USING_VOFA_PLUS is not set
 # CONFIG_PKG_USING_ZDEBUG is not set
+# end of tools packages
 
 #
 # system packages
@@ -517,6 +588,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_RT_MEMCPY_CM is not set
 # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
 # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+# end of enhanced kernel services
 
 #
 # acceleration: Assembly language or algorithmic acceleration packages
@@ -524,13 +596,18 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
 # CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
 # CONFIG_PKG_USING_QFPLIB_M3 is not set
+# end of acceleration: Assembly language or algorithmic acceleration packages
 
 #
 # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
 #
 # CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_CORE is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
+# CONFIG_PKG_USING_CMSIS_NN is not set
 # CONFIG_PKG_USING_CMSIS_RTOS1 is not set
 # CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
 
 #
 # Micrium: Micrium software products porting for RT-Thread
@@ -541,6 +618,8 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_UC_CLK is not set
 # CONFIG_PKG_USING_UC_COMMON is not set
 # CONFIG_PKG_USING_UC_MODBUS is not set
+# end of Micrium: Micrium software products porting for RT-Thread
+
 # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
 # CONFIG_PKG_USING_LITEOS_SDK is not set
 # CONFIG_PKG_USING_TZ_DATABASE is not set
@@ -548,6 +627,8 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FILEX is not set
+# CONFIG_PKG_USING_LEVELX is not set
 # CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
@@ -586,11 +667,41 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_RTP is not set
 # CONFIG_PKG_USING_REB is not set
 # CONFIG_PKG_USING_R_RHEALSTONE is not set
+# end of system packages
 
 #
 # peripheral libraries and drivers
 #
 
+#
+# HAL & SDK Drivers
+#
+
+#
+# STM32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# end of STM32 HAL & SDK Drivers
+
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# end of Kendryte SDK
+
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# end of HAL & SDK Drivers
+
 #
 # sensors drivers
 #
@@ -659,6 +770,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_PAJ7620 is not set
 # CONFIG_PKG_USING_STHS34PF80 is not set
+# end of sensors drivers
 
 #
 # touch drivers
@@ -672,9 +784,10 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_FT6236 is not set
 # CONFIG_PKG_USING_XPT2046_TOUCH is not set
 # CONFIG_PKG_USING_CST816X is not set
+# CONFIG_PKG_USING_CST812T is not set
+# end of touch drivers
+
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
-# CONFIG_PKG_USING_STM32_SDIO is not set
-# CONFIG_PKG_USING_ESP_IDF is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
 # CONFIG_PKG_USING_SX12XX is not set
@@ -682,14 +795,6 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_LEDBLINK is not set
 # CONFIG_PKG_USING_LITTLED is not set
 # CONFIG_PKG_USING_LKDGUI is not set
-# CONFIG_PKG_USING_NRF5X_SDK is not set
-# CONFIG_PKG_USING_NRFX is not set
-
-#
-# Kendryte SDK
-#
-# CONFIG_PKG_USING_K210_SDK is not set
-# CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
 # CONFIG_PKG_USING_MULTI_INFRARED is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
@@ -704,14 +809,12 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
 # CONFIG_PKG_USING_WS2812B is not set
-# CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
 # CONFIG_PKG_USING_MULTI_RTIMER is not set
 # CONFIG_PKG_USING_MAX7219 is not set
 # CONFIG_PKG_USING_BEEP is not set
 # CONFIG_PKG_USING_EASYBLINK is not set
 # CONFIG_PKG_USING_PMS_SERIES is not set
-# CONFIG_PKG_USING_NUCLEI_SDK is not set
 # CONFIG_PKG_USING_CAN_YMODEM is not set
 # CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
 # CONFIG_PKG_USING_QLED is not set
@@ -728,7 +831,6 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
 # CONFIG_PKG_USING_VDEVICE is not set
 # CONFIG_PKG_USING_SGM706 is not set
-# CONFIG_PKG_USING_STM32WB55_SDK is not set
 # CONFIG_PKG_USING_RDA58XX is not set
 # CONFIG_PKG_USING_LIBNFC is not set
 # CONFIG_PKG_USING_MFOC is not set
@@ -738,7 +840,6 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ROSSERIAL is not set
 # CONFIG_PKG_USING_MICRO_ROS is not set
 # CONFIG_PKG_USING_MCP23008 is not set
-# CONFIG_PKG_USING_BLUETRUM_SDK is not set
 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set
 # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
 # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
@@ -746,7 +847,6 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_MB85RS16 is not set
 # CONFIG_PKG_USING_RFM300 is not set
 # CONFIG_PKG_USING_IO_INPUT_FILTER is not set
-# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
 # CONFIG_PKG_USING_LRF_NV7LIDAR is not set
 # CONFIG_PKG_USING_AIP650 is not set
 # CONFIG_PKG_USING_FINGERPRINT is not set
@@ -756,7 +856,10 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_VS1003 is not set
 # CONFIG_PKG_USING_X9555 is not set
 # CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
+# CONFIG_PKG_USING_RGPOWER is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set
+# end of peripheral libraries and drivers
 
 #
 # AI packages
@@ -771,6 +874,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
 # CONFIG_PKG_USING_R_TINYMAIX is not set
+# end of AI packages
 
 #
 # Signal Processing and Control Algorithm Packages
@@ -780,6 +884,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_KISSFFT is not set
+# end of Signal Processing and Control Algorithm Packages
 
 #
 # miscellaneous packages
@@ -788,6 +893,7 @@ CONFIG_RT_USING_ADT_REF=y
 #
 # project laboratory
 #
+# end of project laboratory
 
 #
 # samples: kernel and components samples
@@ -796,6 +902,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
 # CONFIG_PKG_USING_NETWORK_SAMPLES is not set
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# end of samples: kernel and components samples
 
 #
 # entertainment: terminal games and other interesting software packages
@@ -811,6 +918,8 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_DONUT is not set
 # CONFIG_PKG_USING_COWSAY is not set
 # CONFIG_PKG_USING_MORSE is not set
+# end of entertainment: terminal games and other interesting software packages
+
 # CONFIG_PKG_USING_LIBCSV is not set
 # CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
@@ -844,6 +953,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_SOEM is not set
 # CONFIG_PKG_USING_QPARAM is not set
 # CONFIG_PKG_USING_CorevMCU_CLI is not set
+# end of miscellaneous packages
 
 #
 # Arduino libraries
@@ -854,21 +964,24 @@ CONFIG_RT_USING_ADT_REF=y
 # Projects and Demos
 #
 # CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
 # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
 # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+# end of Projects and Demos
 
 #
 # Sensors
 #
 # CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
-# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
-# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
@@ -913,7 +1026,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
-# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@@ -952,7 +1065,6 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
@@ -975,7 +1087,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
-# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
@@ -983,7 +1095,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
-# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
@@ -996,6 +1108,9 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set
+# end of Sensors
 
 #
 # Display
@@ -1007,6 +1122,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
 # CONFIG_PKG_USING_SEEED_TM1637 is not set
+# end of Display
 
 #
 # Timing
@@ -1015,12 +1131,16 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
 # CONFIG_PKG_USING_ARDUINO_TICKER is not set
 # CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+# end of Timing
 
 #
 # Data Processing
 #
 # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
 # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
+# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set
+# end of Data Processing
 
 #
 # Data Storage
@@ -1031,23 +1151,26 @@ CONFIG_RT_USING_ADT_REF=y
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+# end of Communication
 
 #
 # Device Control
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# end of Device Control
 
 #
 # Other
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# end of Other
 
 #
 # Signal IO
@@ -1060,10 +1183,13 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+# end of Signal IO
 
 #
 # Uncategorized
 #
+# end of Arduino libraries
+# end of RT-Thread online packages
 
 #
 # General Drivers Configuration
@@ -1078,10 +1204,15 @@ CONFIG_UART_IRQ_BASE=44
 # CONFIG_BSP_USING_ADC is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_SDH is not set
+# end of General Drivers Configuration
+
 CONFIG_BSP_USING_CV18XX=y
 CONFIG_C906_PLIC_PHY_ADDR=0x70000000
 CONFIG_IRQ_MAX_NR=64
 CONFIG_TIMER_CLK_FREQ=25000000
 CONFIG___STACKSIZE__=8192
 # CONFIG_BOARD_TYPE_MILKV_DUO is not set
+# CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR is not set
 CONFIG_BOARD_TYPE_MILKV_DUO256M=y
+# CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINOR is not set

bsp/cvitek/cv18xx_risc-v/board/Kconfig

@@ -66,4 +66,12 @@ menu "General Drivers Configuration"
             
         endif
 
+    config BSP_USING_SDH
+        select RT_USING_SDIO
+        select RT_USING_DFS
+        select RT_USING_DFS_ELMFAT
+        select RT_USING_DFS_ROMFS
+        bool "Enable Secure Digital Host Controller"
+        default n
+        
 endmenu

bsp/cvitek/cv18xx_risc-v/rtconfig.h

@@ -1,9 +1,6 @@
 #ifndef RT_CONFIG_H__
 #define RT_CONFIG_H__
 
-/* Automatically generated file; DO NOT EDIT. */
-/* RT-Thread Project Configuration */
-
 /* RT-Thread Kernel */
 
 #define RT_NAME_MAX 8
@@ -24,8 +21,12 @@
 
 /* kservice optimization */
 
-#define RT_KSERVICE_USING_STDLIB
+/* end of kservice optimization */
-#define RT_KPRINTF_USING_LONGLONG
+
+/* klibc optimization */
+
+#define RT_KLIBC_USING_PRINTF_LONGLONG
+/* end of klibc optimization */
 #define RT_USING_DEBUG
 #define RT_DEBUGING_COLOR
 #define RT_DEBUGING_CONTEXT
@@ -37,6 +38,7 @@
 #define RT_USING_EVENT
 #define RT_USING_MAILBOX
 #define RT_USING_MESSAGEQUEUE
+/* end of Inter-Thread communication */
 
 /* Memory Management */
 
@@ -45,14 +47,16 @@
 #define RT_USING_SMALL_MEM
 #define RT_USING_SMALL_MEM_AS_HEAP
 #define RT_USING_HEAP
+/* end of Memory Management */
 #define RT_USING_DEVICE
 #define RT_USING_DEVICE_OPS
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 256
 #define RT_CONSOLE_DEVICE_NAME "uart0"
-#define RT_VER_NUM 0x50100
+#define RT_VER_NUM 0x50200
 #define RT_USING_STDC_ATOMIC
 #define RT_BACKTRACE_LEVEL_MAX_NR 32
+/* end of RT-Thread Kernel */
 #define ARCH_CPU_64BIT
 #define RT_USING_CACHE
 #define ARCH_MM_MMU
@@ -87,7 +91,25 @@
 #define DFS_USING_WORKDIR
 #define DFS_FD_MAX 16
 #define RT_USING_DFS_V2
+#define RT_USING_DFS_ELMFAT
+
+/* elm-chan's FatFs, Generic FAT Filesystem Module */
+
+#define RT_DFS_ELM_CODE_PAGE 437
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_USE_LFN_3
+#define RT_DFS_ELM_USE_LFN 3
+#define RT_DFS_ELM_LFN_UNICODE_0
+#define RT_DFS_ELM_LFN_UNICODE 0
+#define RT_DFS_ELM_MAX_LFN 255
+#define RT_DFS_ELM_DRIVES 2
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+#define RT_DFS_ELM_REENTRANT
+#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
+/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
 #define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_ROMFS
+/* end of DFS: device virtual file system */
 
 /* Device Drivers */
 
@@ -104,11 +126,19 @@
 #define RT_USING_ZERO
 #define RT_USING_RANDOM
 #define RT_USING_RTC
+#define RT_USING_SDIO
+#define RT_SDIO_STACK_SIZE 4096
+#define RT_SDIO_THREAD_PRIORITY 15
+#define RT_MMCSD_STACK_SIZE 4096
+#define RT_MMCSD_THREAD_PREORITY 22
+#define RT_MMCSD_MAX_PARTITION 16
 #define RT_USING_PIN
 #define RT_USING_KTIME
 
 /* Using USB */
 
+/* end of Using USB */
+/* end of Device Drivers */
 
 /* C/C++ and POSIX layer */
 
@@ -120,6 +150,8 @@
 #define RT_LIBC_TZ_DEFAULT_HOUR 8
 #define RT_LIBC_TZ_DEFAULT_MIN 0
 #define RT_LIBC_TZ_DEFAULT_SEC 0
+/* end of Timezone and Daylight Saving Time */
+/* end of ISO-ANSI C layer */
 
 /* POSIX (Portable Operating System Interface) layer */
 
@@ -137,12 +169,17 @@
 
 /* Socket is in the 'Network' category */
 
+/* end of Interprocess Communication (IPC) */
+/* end of POSIX (Portable Operating System Interface) layer */
+/* end of C/C++ and POSIX layer */
 
 /* Network */
 
+/* end of Network */
 
 /* Memory protection */
 
+/* end of Memory protection */
 
 /* Utilities */
 
@@ -152,9 +189,12 @@
 #define RT_USING_ADT_BITMAP
 #define RT_USING_ADT_HASHMAP
 #define RT_USING_ADT_REF
+/* end of Utilities */
+/* end of RT-Thread Components */
 
 /* RT-Thread Utestcases */
 
+/* end of RT-Thread Utestcases */
 
 /* RT-Thread online packages */
 
@@ -165,124 +205,176 @@
 
 /* Marvell WiFi */
 
+/* end of Marvell WiFi */
 
 /* Wiced WiFi */
 
+/* end of Wiced WiFi */
 
 /* CYW43012 WiFi */
 
+/* end of CYW43012 WiFi */
 
 /* BL808 WiFi */
 
+/* end of BL808 WiFi */
 
 /* CYW43439 WiFi */
 
+/* end of CYW43439 WiFi */
+/* end of Wi-Fi */
 
 /* IoT Cloud */
 
+/* end of IoT Cloud */
+/* end of IoT - internet of things */
 
 /* security packages */
 
+/* end of security packages */
 
 /* language packages */
 
 /* JSON: JavaScript Object Notation, a lightweight data-interchange format */
 
+/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
 
 /* XML: Extensible Markup Language */
 
+/* end of XML: Extensible Markup Language */
+/* end of language packages */
 
 /* multimedia packages */
 
 /* LVGL: powerful and easy-to-use embedded GUI library */
 
+/* end of LVGL: powerful and easy-to-use embedded GUI library */
 
 /* u8g2: a monochrome graphic library */
 
+/* end of u8g2: a monochrome graphic library */
+/* end of multimedia packages */
 
 /* tools packages */
 
+/* end of tools packages */
 
 /* system packages */
 
 /* enhanced kernel services */
 
+/* end of enhanced kernel services */
 
 /* acceleration: Assembly language or algorithmic acceleration packages */
 
+/* end of acceleration: Assembly language or algorithmic acceleration packages */
 
 /* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
 
+/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
 
 /* Micrium: Micrium software products porting for RT-Thread */
 
+/* end of Micrium: Micrium software products porting for RT-Thread */
+/* end of system packages */
 
 /* peripheral libraries and drivers */
 
-/* sensors drivers */
+/* HAL & SDK Drivers */
 
+/* STM32 HAL & SDK Drivers */
 
-/* touch drivers */
+/* end of STM32 HAL & SDK Drivers */
-
 
 /* Kendryte SDK */
 
+/* end of Kendryte SDK */
+/* end of HAL & SDK Drivers */
+
+/* sensors drivers */
+
+/* end of sensors drivers */
+
+/* touch drivers */
+
+/* end of touch drivers */
+/* end of peripheral libraries and drivers */
 
 /* AI packages */
 
+/* end of AI packages */
 
 /* Signal Processing and Control Algorithm Packages */
 
+/* end of Signal Processing and Control Algorithm Packages */
 
 /* miscellaneous packages */
 
 /* project laboratory */
 
+/* end of project laboratory */
+
 /* samples: kernel and components samples */
 
+/* end of samples: kernel and components samples */
 
 /* entertainment: terminal games and other interesting software packages */
 
+/* end of entertainment: terminal games and other interesting software packages */
+/* end of miscellaneous packages */
 
 /* Arduino libraries */
 
 
 /* Projects and Demos */
 
+/* end of Projects and Demos */
 
 /* Sensors */
 
+/* end of Sensors */
 
 /* Display */
 
+/* end of Display */
 
 /* Timing */
 
+/* end of Timing */
 
 /* Data Processing */
 
+/* end of Data Processing */
 
 /* Data Storage */
 
 /* Communication */
 
+/* end of Communication */
 
 /* Device Control */
 
+/* end of Device Control */
 
 /* Other */
 
+/* end of Other */
 
 /* Signal IO */
 
+/* end of Signal IO */
 
 /* Uncategorized */
 
+/* end of Arduino libraries */
+/* end of RT-Thread online packages */
+
 /* General Drivers Configuration */
 
 #define BSP_USING_UART
 #define RT_USING_UART0
 #define UART_IRQ_BASE 44
+/* end of General Drivers Configuration */
 #define BSP_USING_CV18XX
 #define C906_PLIC_PHY_ADDR 0x70000000
 #define IRQ_MAX_NR 64

bsp/cvitek/cv18xx_risc-v/rtconfig.py

@@ -41,7 +41,7 @@ if PLATFORM == 'gcc':
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY  = PREFIX + 'objcopy'
 
-    DEVICE  = ' -mcmodel=medany -march=rv64imafdc -mabi=lp64'
+    DEVICE  = ' -mcmodel=medany -mcpu=c906fdv -mabi=lp64'
     CFLAGS  = DEVICE + ' -Wno-cpp -fvar-tracking -ffreestanding -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -D_POSIX_SOURCE '
     AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__'
     LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' + ' -lsupc++ -lgcc -static'

bsp/cvitek/drivers/SConscript

@@ -37,6 +37,10 @@ if GetDepend('BSP_USING_PWM'):
     src += ['drv_pwm.c']
     CPPPATH += [cwd + r'/libraries/cv180x/pwm']
 
+if GetDepend('BSP_USING_SDH'):
+    src += ['drv_sdhci.c', 'port/mnt.c']
+    CPPPATH += [cwd + r'/libraries/sdif']
+
 CPPDEFINES += ['-DCONFIG_64BIT']
 
 if GetDepend('BSP_USING_RTC'):

bsp/cvitek/drivers/drv_sdhci.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024/04/05     flyingcys    first version
+ */
+#ifndef __DRV_SDHCI_H__
+#define __DRV_SDHCI_H__
+
+#include "mmio.h"
+#include "dw_sdmmc.h"
+#include "dw_mmc_reg.h"
+
+#include "core_rv64.h"
+
+#ifndef BIT
+#define BIT(nr)      (UINT64_C(1) << (nr))
+#endif
+
+typedef enum {
+    SDIF_CHAIN_DMA_MODE = 0x01U, ///< one descriptor with one buffer,but one descriptor point to another
+    SDIF_DUAL_DMA_MODE  = 0x02U,  ///< dual mode is one descriptor with two buffer
+} sdhci_dma_mode_e;
+
+typedef struct {
+    bool            enable_fix_burst_len;           ///< fix burst len enable/disable flag,When set, the AHB will
+    ///  use only SINGLE, INCR4, INCR8 or INCR16 during start of
+    ///  normal burst transfers. When reset, the AHB will use SINGLE
+    ///  and INCR burst transfer operations
+
+    sdhci_dma_mode_e mode;                           ///< define the DMA mode */
+
+
+    uint32_t        *dma_des_buffer_start_addr;     ///< internal DMA descriptor start address
+    uint32_t        dma_des_buffer_len;             ///  internal DMA buffer descriptor buffer len ,user need to pay attention to the
+    ///  dma descriptor buffer length if it is bigger enough for your transfer
+    uint8_t         dma_dws_skip_len;               ///< define the descriptor skip length ,the length between two descriptor
+    ///  this field is special for dual DMA mode
+} sdhci_dma_config_t;
+
+#endif /* __DRV_SDHCI_H__ */

bsp/cvitek/drivers/libraries/cv181x/pinctrl.h

@@ -33,8 +33,8 @@ extern rt_ubase_t pinmux_base_ioremap(void);
 #define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET
 #define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME
 #define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \
-		mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \
+        mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \
-		PINMUX_MASK(PIN_NAME) << PINMUX_OFFSET(PIN_NAME), \
+        PINMUX_MASK(PIN_NAME) << PINMUX_OFFSET(PIN_NAME), \
-		PINMUX_VALUE(PIN_NAME, FUNC_NAME))
+        PINMUX_VALUE(PIN_NAME, FUNC_NAME))
 
 #endif /* __PINCTRL_CV181X_H__ */

bsp/cvitek/drivers/libraries/sdif/dw_mmc_reg.h

@@ -0,0 +1,637 @@
+#ifndef _FSL_SDIF_REGS_
+#define _FSL_SDIF_REGS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE 4096
+
+/* ----------------------------------------------------------------------------
+   -- SDIF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDIF_Register_Masks SDIF Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register */
+/*! @{ */
+#define SDIF_CTRL_CONTROLLER_RESET_MASK          (0x1U)
+#define SDIF_CTRL_CONTROLLER_RESET_SHIFT         (0U)
+#define SDIF_CTRL_CONTROLLER_RESET(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)
+#define SDIF_CTRL_FIFO_RESET_MASK                (0x2U)
+#define SDIF_CTRL_FIFO_RESET_SHIFT               (1U)
+#define SDIF_CTRL_FIFO_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)
+#define SDIF_CTRL_DMA_RESET_MASK                 (0x4U)
+#define SDIF_CTRL_DMA_RESET_SHIFT                (2U)
+#define SDIF_CTRL_DMA_RESET(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
+#define SDIF_CTRL_INT_ENABLE_MASK                (0x10U)
+#define SDIF_CTRL_INT_ENABLE_SHIFT               (4U)
+#define SDIF_CTRL_INT_ENABLE(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)
+#define SDIF_CTRL_READ_WAIT_MASK                 (0x40U)
+#define SDIF_CTRL_READ_WAIT_SHIFT                (6U)
+#define SDIF_CTRL_READ_WAIT(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK         (0x80U)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT        (7U)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)
+#define SDIF_CTRL_ABORT_READ_DATA_MASK           (0x100U)
+#define SDIF_CTRL_ABORT_READ_DATA_SHIFT          (8U)
+#define SDIF_CTRL_ABORT_READ_DATA(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)
+#define SDIF_CTRL_SEND_CCSD_MASK                 (0x200U)
+#define SDIF_CTRL_SEND_CCSD_SHIFT                (9U)
+#define SDIF_CTRL_SEND_CCSD(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK       (0x400U)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT      (10U)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK           (0x10000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT          (16U)
+#define SDIF_CTRL_CARD_VOLTAGE_A0(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK           (0x20000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT          (17U)
+#define SDIF_CTRL_CARD_VOLTAGE_A1(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK           (0x40000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT          (18U)
+#define SDIF_CTRL_CARD_VOLTAGE_A2(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)
+#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK         (0x2000000U)
+#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT        (25U)
+#define SDIF_CTRL_USE_INTERNAL_DMAC(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)
+/*! @} */
+
+/*! @name PWREN - Power Enable register */
+/*! @{ */
+#define SDIF_PWREN_POWER_ENABLE_MASK             (0x1U)
+#define SDIF_PWREN_POWER_ENABLE_SHIFT            (0U)
+#define SDIF_PWREN_POWER_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE_SHIFT)) & SDIF_PWREN_POWER_ENABLE_MASK)
+/*! @} */
+
+/*! @name CLKDIV - Clock Divider register */
+/*! @{ */
+#define SDIF_CLKDIV_CLK_DIVIDER0_MASK            (0xFFU)
+#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT           (0U)
+#define SDIF_CLKDIV_CLK_DIVIDER0(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)
+/*! @} */
+
+/*! @name CLKENA - Clock Enable register */
+/*! @{ */
+#define SDIF_CLKENA_CCLK_ENABLE_MASK             (0x1U)
+#define SDIF_CLKENA_CCLK_ENABLE_SHIFT            (0U)
+#define SDIF_CLKENA_CCLK_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK_ENABLE_MASK)
+#define SDIF_CLKENA_CCLK_LOW_POWER_MASK          (0x10000U)
+#define SDIF_CLKENA_CCLK_LOW_POWER_SHIFT         (16U)
+#define SDIF_CLKENA_CCLK_LOW_POWER(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK_LOW_POWER_MASK)
+/*! @} */
+
+/*! @name TMOUT - Time-out register */
+/*! @{ */
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK         (0xFFU)
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT        (0U)
+#define SDIF_TMOUT_RESPONSE_TIMEOUT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)
+#define SDIF_TMOUT_DATA_TIMEOUT_MASK             (0xFFFFFF00U)
+#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT            (8U)
+#define SDIF_TMOUT_DATA_TIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)
+/*! @} */
+
+/*! @name CTYPE - Card Type register */
+/*! @{ */
+#define SDIF_CTYPE_CARD_WIDTH0_MASK              (0x1U)
+#define SDIF_CTYPE_CARD_WIDTH0_SHIFT             (0U)
+#define SDIF_CTYPE_CARD_WIDTH0(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD_WIDTH0_MASK)
+#define SDIF_CTYPE_CARD_WIDTH1_MASK              (0x10000U)
+#define SDIF_CTYPE_CARD_WIDTH1_SHIFT             (16U)
+#define SDIF_CTYPE_CARD_WIDTH1(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD_WIDTH1_MASK)
+/*! @} */
+
+/*! @name BLKSIZ - Block Size register */
+/*! @{ */
+#define SDIF_BLKSIZ_BLOCK_SIZE_MASK              (0xFFFFU)
+#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT             (0U)
+#define SDIF_BLKSIZ_BLOCK_SIZE(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)
+/*! @} */
+
+/*! @name BYTCNT - Byte Count register */
+/*! @{ */
+#define SDIF_BYTCNT_BYTE_COUNT_MASK              (0xFFFFFFFFU)
+#define SDIF_BYTCNT_BYTE_COUNT_SHIFT             (0U)
+#define SDIF_BYTCNT_BYTE_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)
+/*! @} */
+
+/*! @name INTMASK - Interrupt Mask register */
+/*! @{ */
+#define SDIF_INTMASK_CDET_MASK                   (0x1U)
+#define SDIF_INTMASK_CDET_SHIFT                  (0U)
+#define SDIF_INTMASK_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)
+#define SDIF_INTMASK_RE_MASK                     (0x2U)
+#define SDIF_INTMASK_RE_SHIFT                    (1U)
+#define SDIF_INTMASK_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)
+#define SDIF_INTMASK_CDONE_MASK                  (0x4U)
+#define SDIF_INTMASK_CDONE_SHIFT                 (2U)
+#define SDIF_INTMASK_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)
+#define SDIF_INTMASK_DTO_MASK                    (0x8U)
+#define SDIF_INTMASK_DTO_SHIFT                   (3U)
+#define SDIF_INTMASK_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)
+#define SDIF_INTMASK_TXDR_MASK                   (0x10U)
+#define SDIF_INTMASK_TXDR_SHIFT                  (4U)
+#define SDIF_INTMASK_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)
+#define SDIF_INTMASK_RXDR_MASK                   (0x20U)
+#define SDIF_INTMASK_RXDR_SHIFT                  (5U)
+#define SDIF_INTMASK_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)
+#define SDIF_INTMASK_RCRC_MASK                   (0x40U)
+#define SDIF_INTMASK_RCRC_SHIFT                  (6U)
+#define SDIF_INTMASK_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)
+#define SDIF_INTMASK_DCRC_MASK                   (0x80U)
+#define SDIF_INTMASK_DCRC_SHIFT                  (7U)
+#define SDIF_INTMASK_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)
+#define SDIF_INTMASK_RTO_MASK                    (0x100U)
+#define SDIF_INTMASK_RTO_SHIFT                   (8U)
+#define SDIF_INTMASK_RTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)
+#define SDIF_INTMASK_DRTO_MASK                   (0x200U)
+#define SDIF_INTMASK_DRTO_SHIFT                  (9U)
+#define SDIF_INTMASK_DRTO(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)
+#define SDIF_INTMASK_HTO_MASK                    (0x400U)
+#define SDIF_INTMASK_HTO_SHIFT                   (10U)
+#define SDIF_INTMASK_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)
+#define SDIF_INTMASK_FRUN_MASK                   (0x800U)
+#define SDIF_INTMASK_FRUN_SHIFT                  (11U)
+#define SDIF_INTMASK_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)
+#define SDIF_INTMASK_HLE_MASK                    (0x1000U)
+#define SDIF_INTMASK_HLE_SHIFT                   (12U)
+#define SDIF_INTMASK_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)
+#define SDIF_INTMASK_SBE_MASK                    (0x2000U)
+#define SDIF_INTMASK_SBE_SHIFT                   (13U)
+#define SDIF_INTMASK_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)
+#define SDIF_INTMASK_ACD_MASK                    (0x4000U)
+#define SDIF_INTMASK_ACD_SHIFT                   (14U)
+#define SDIF_INTMASK_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)
+#define SDIF_INTMASK_EBE_MASK                    (0x8000U)
+#define SDIF_INTMASK_EBE_SHIFT                   (15U)
+#define SDIF_INTMASK_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)
+#define SDIF_INTMASK_SDIO_INT_MASK_MASK          (0x10000U)
+#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT         (16U)
+#define SDIF_INTMASK_SDIO_INT_MASK(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)
+/*! @} */
+
+/*! @name CMDARG - Command Argument register */
+/*! @{ */
+#define SDIF_CMDARG_CMD_ARG_MASK                 (0xFFFFFFFFU)
+#define SDIF_CMDARG_CMD_ARG_SHIFT                (0U)
+#define SDIF_CMDARG_CMD_ARG(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)
+/*! @} */
+
+/*! @name CMD - Command register */
+/*! @{ */
+#define SDIF_CMD_CMD_INDEX_MASK                  (0x3FU)
+#define SDIF_CMD_CMD_INDEX_SHIFT                 (0U)
+#define SDIF_CMD_CMD_INDEX(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)
+#define SDIF_CMD_RESPONSE_EXPECT_MASK            (0x40U)
+#define SDIF_CMD_RESPONSE_EXPECT_SHIFT           (6U)
+#define SDIF_CMD_RESPONSE_EXPECT(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)
+#define SDIF_CMD_RESPONSE_LENGTH_MASK            (0x80U)
+#define SDIF_CMD_RESPONSE_LENGTH_SHIFT           (7U)
+#define SDIF_CMD_RESPONSE_LENGTH(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)
+#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK         (0x100U)
+#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT        (8U)
+#define SDIF_CMD_CHECK_RESPONSE_CRC(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)
+#define SDIF_CMD_DATA_EXPECTED_MASK              (0x200U)
+#define SDIF_CMD_DATA_EXPECTED_SHIFT             (9U)
+#define SDIF_CMD_DATA_EXPECTED(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)
+#define SDIF_CMD_READ_WRITE_MASK                 (0x400U)
+#define SDIF_CMD_READ_WRITE_SHIFT                (10U)
+#define SDIF_CMD_READ_WRITE(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)
+#define SDIF_CMD_TRANSFER_MODE_MASK              (0x800U)
+#define SDIF_CMD_TRANSFER_MODE_SHIFT             (11U)
+#define SDIF_CMD_TRANSFER_MODE(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)
+#define SDIF_CMD_SEND_AUTO_STOP_MASK             (0x1000U)
+#define SDIF_CMD_SEND_AUTO_STOP_SHIFT            (12U)
+#define SDIF_CMD_SEND_AUTO_STOP(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK      (0x2000U)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT     (13U)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x)        (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)
+#define SDIF_CMD_STOP_ABORT_CMD_MASK             (0x4000U)
+#define SDIF_CMD_STOP_ABORT_CMD_SHIFT            (14U)
+#define SDIF_CMD_STOP_ABORT_CMD(x)               (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)
+#define SDIF_CMD_SEND_INITIALIZATION_MASK        (0x8000U)
+#define SDIF_CMD_SEND_INITIALIZATION_SHIFT       (15U)
+#define SDIF_CMD_SEND_INITIALIZATION(x)          (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x)  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)
+#define SDIF_CMD_READ_CEATA_DEVICE_MASK          (0x400000U)
+#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT         (22U)
+#define SDIF_CMD_READ_CEATA_DEVICE(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)
+#define SDIF_CMD_CCS_EXPECTED_MASK               (0x800000U)
+#define SDIF_CMD_CCS_EXPECTED_SHIFT              (23U)
+#define SDIF_CMD_CCS_EXPECTED(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)
+#define SDIF_CMD_ENABLE_BOOT_MASK                (0x1000000U)
+#define SDIF_CMD_ENABLE_BOOT_SHIFT               (24U)
+#define SDIF_CMD_ENABLE_BOOT(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)
+#define SDIF_CMD_EXPECT_BOOT_ACK_MASK            (0x2000000U)
+#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT           (25U)
+#define SDIF_CMD_EXPECT_BOOT_ACK(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)
+#define SDIF_CMD_DISABLE_BOOT_MASK               (0x4000000U)
+#define SDIF_CMD_DISABLE_BOOT_SHIFT              (26U)
+#define SDIF_CMD_DISABLE_BOOT(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)
+#define SDIF_CMD_BOOT_MODE_MASK                  (0x8000000U)
+#define SDIF_CMD_BOOT_MODE_SHIFT                 (27U)
+#define SDIF_CMD_BOOT_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)
+#define SDIF_CMD_VOLT_SWITCH_MASK                (0x10000000U)
+#define SDIF_CMD_VOLT_SWITCH_SHIFT               (28U)
+#define SDIF_CMD_VOLT_SWITCH(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)
+#define SDIF_CMD_USE_HOLD_REG_MASK               (0x20000000U)
+#define SDIF_CMD_USE_HOLD_REG_SHIFT              (29U)
+#define SDIF_CMD_USE_HOLD_REG(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)
+#define SDIF_CMD_START_CMD_MASK                  (0x80000000U)
+#define SDIF_CMD_START_CMD_SHIFT                 (31U)
+#define SDIF_CMD_START_CMD(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)
+/*! @} */
+
+/*! @name RESP - Response register */
+/*! @{ */
+#define SDIF_RESP_RESPONSE_MASK                  (0xFFFFFFFFU)
+#define SDIF_RESP_RESPONSE_SHIFT                 (0U)
+#define SDIF_RESP_RESPONSE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)
+/*! @} */
+
+/* The count of SDIF_RESP */
+#define SDIF_RESP_COUNT                          (4U)
+
+/*! @name MINTSTS - Masked Interrupt Status register */
+/*! @{ */
+#define SDIF_MINTSTS_CDET_MASK                   (0x1U)
+#define SDIF_MINTSTS_CDET_SHIFT                  (0U)
+#define SDIF_MINTSTS_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)
+#define SDIF_MINTSTS_RE_MASK                     (0x2U)
+#define SDIF_MINTSTS_RE_SHIFT                    (1U)
+#define SDIF_MINTSTS_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)
+#define SDIF_MINTSTS_CDONE_MASK                  (0x4U)
+#define SDIF_MINTSTS_CDONE_SHIFT                 (2U)
+#define SDIF_MINTSTS_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)
+#define SDIF_MINTSTS_DTO_MASK                    (0x8U)
+#define SDIF_MINTSTS_DTO_SHIFT                   (3U)
+#define SDIF_MINTSTS_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)
+#define SDIF_MINTSTS_TXDR_MASK                   (0x10U)
+#define SDIF_MINTSTS_TXDR_SHIFT                  (4U)
+#define SDIF_MINTSTS_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)
+#define SDIF_MINTSTS_RXDR_MASK                   (0x20U)
+#define SDIF_MINTSTS_RXDR_SHIFT                  (5U)
+#define SDIF_MINTSTS_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)
+#define SDIF_MINTSTS_RCRC_MASK                   (0x40U)
+#define SDIF_MINTSTS_RCRC_SHIFT                  (6U)
+#define SDIF_MINTSTS_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)
+#define SDIF_MINTSTS_DCRC_MASK                   (0x80U)
+#define SDIF_MINTSTS_DCRC_SHIFT                  (7U)
+#define SDIF_MINTSTS_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)
+#define SDIF_MINTSTS_RTO_MASK                    (0x100U)
+#define SDIF_MINTSTS_RTO_SHIFT                   (8U)
+#define SDIF_MINTSTS_RTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)
+#define SDIF_MINTSTS_DRTO_MASK                   (0x200U)
+#define SDIF_MINTSTS_DRTO_SHIFT                  (9U)
+#define SDIF_MINTSTS_DRTO(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)
+#define SDIF_MINTSTS_HTO_MASK                    (0x400U)
+#define SDIF_MINTSTS_HTO_SHIFT                   (10U)
+#define SDIF_MINTSTS_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)
+#define SDIF_MINTSTS_FRUN_MASK                   (0x800U)
+#define SDIF_MINTSTS_FRUN_SHIFT                  (11U)
+#define SDIF_MINTSTS_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)
+#define SDIF_MINTSTS_HLE_MASK                    (0x1000U)
+#define SDIF_MINTSTS_HLE_SHIFT                   (12U)
+#define SDIF_MINTSTS_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)
+#define SDIF_MINTSTS_SBE_MASK                    (0x2000U)
+#define SDIF_MINTSTS_SBE_SHIFT                   (13U)
+#define SDIF_MINTSTS_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)
+#define SDIF_MINTSTS_ACD_MASK                    (0x4000U)
+#define SDIF_MINTSTS_ACD_SHIFT                   (14U)
+#define SDIF_MINTSTS_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)
+#define SDIF_MINTSTS_EBE_MASK                    (0x8000U)
+#define SDIF_MINTSTS_EBE_SHIFT                   (15U)
+#define SDIF_MINTSTS_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)
+#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK         (0x10000U)
+#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT        (16U)
+#define SDIF_MINTSTS_SDIO_INTERRUPT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK)
+/*! @} */
+
+/*! @name RINTSTS - Raw Interrupt Status register */
+/*! @{ */
+#define SDIF_RINTSTS_CDET_MASK                   (0x1U)
+#define SDIF_RINTSTS_CDET_SHIFT                  (0U)
+#define SDIF_RINTSTS_CDET(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK)
+#define SDIF_RINTSTS_RE_MASK                     (0x2U)
+#define SDIF_RINTSTS_RE_SHIFT                    (1U)
+#define SDIF_RINTSTS_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK)
+#define SDIF_RINTSTS_CDONE_MASK                  (0x4U)
+#define SDIF_RINTSTS_CDONE_SHIFT                 (2U)
+#define SDIF_RINTSTS_CDONE(x)                    (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK)
+#define SDIF_RINTSTS_DTO_MASK                    (0x8U)
+#define SDIF_RINTSTS_DTO_SHIFT                   (3U)
+#define SDIF_RINTSTS_DTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK)
+#define SDIF_RINTSTS_TXDR_MASK                   (0x10U)
+#define SDIF_RINTSTS_TXDR_SHIFT                  (4U)
+#define SDIF_RINTSTS_TXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK)
+#define SDIF_RINTSTS_RXDR_MASK                   (0x20U)
+#define SDIF_RINTSTS_RXDR_SHIFT                  (5U)
+#define SDIF_RINTSTS_RXDR(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK)
+#define SDIF_RINTSTS_RCRC_MASK                   (0x40U)
+#define SDIF_RINTSTS_RCRC_SHIFT                  (6U)
+#define SDIF_RINTSTS_RCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK)
+#define SDIF_RINTSTS_DCRC_MASK                   (0x80U)
+#define SDIF_RINTSTS_DCRC_SHIFT                  (7U)
+#define SDIF_RINTSTS_DCRC(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK)
+#define SDIF_RINTSTS_RTO_BAR_MASK                (0x100U)
+#define SDIF_RINTSTS_RTO_BAR_SHIFT               (8U)
+#define SDIF_RINTSTS_RTO_BAR(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK)
+#define SDIF_RINTSTS_DRTO_BDS_MASK               (0x200U)
+#define SDIF_RINTSTS_DRTO_BDS_SHIFT              (9U)
+#define SDIF_RINTSTS_DRTO_BDS(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK)
+#define SDIF_RINTSTS_HTO_MASK                    (0x400U)
+#define SDIF_RINTSTS_HTO_SHIFT                   (10U)
+#define SDIF_RINTSTS_HTO(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK)
+#define SDIF_RINTSTS_FRUN_MASK                   (0x800U)
+#define SDIF_RINTSTS_FRUN_SHIFT                  (11U)
+#define SDIF_RINTSTS_FRUN(x)                     (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK)
+#define SDIF_RINTSTS_HLE_MASK                    (0x1000U)
+#define SDIF_RINTSTS_HLE_SHIFT                   (12U)
+#define SDIF_RINTSTS_HLE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK)
+#define SDIF_RINTSTS_SBE_MASK                    (0x2000U)
+#define SDIF_RINTSTS_SBE_SHIFT                   (13U)
+#define SDIF_RINTSTS_SBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK)
+#define SDIF_RINTSTS_ACD_MASK                    (0x4000U)
+#define SDIF_RINTSTS_ACD_SHIFT                   (14U)
+#define SDIF_RINTSTS_ACD(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK)
+#define SDIF_RINTSTS_EBE_MASK                    (0x8000U)
+#define SDIF_RINTSTS_EBE_SHIFT                   (15U)
+#define SDIF_RINTSTS_EBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK)
+#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK         (0x10000U)
+#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT        (16U)
+#define SDIF_RINTSTS_SDIO_INTERRUPT(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK)
+/*! @} */
+
+/*! @name STATUS - Status register */
+/*! @{ */
+#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK       (0x1U)
+#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT      (0U)
+#define SDIF_STATUS_FIFO_RX_WATERMARK(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK)
+#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK       (0x2U)
+#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT      (1U)
+#define SDIF_STATUS_FIFO_TX_WATERMARK(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK)
+#define SDIF_STATUS_FIFO_EMPTY_MASK              (0x4U)
+#define SDIF_STATUS_FIFO_EMPTY_SHIFT             (2U)
+#define SDIF_STATUS_FIFO_EMPTY(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK)
+#define SDIF_STATUS_FIFO_FULL_MASK               (0x8U)
+#define SDIF_STATUS_FIFO_FULL_SHIFT              (3U)
+#define SDIF_STATUS_FIFO_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK)
+#define SDIF_STATUS_CMDFSMSTATES_MASK            (0xF0U)
+#define SDIF_STATUS_CMDFSMSTATES_SHIFT           (4U)
+#define SDIF_STATUS_CMDFSMSTATES(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK)
+#define SDIF_STATUS_DATA_3_STATUS_MASK           (0x100U)
+#define SDIF_STATUS_DATA_3_STATUS_SHIFT          (8U)
+#define SDIF_STATUS_DATA_3_STATUS(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK)
+#define SDIF_STATUS_DATA_BUSY_MASK               (0x200U)
+#define SDIF_STATUS_DATA_BUSY_SHIFT              (9U)
+#define SDIF_STATUS_DATA_BUSY(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK      (0x400U)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT     (10U)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY(x)        (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK)
+#define SDIF_STATUS_RESPONSE_INDEX_MASK          (0x1F800U)
+#define SDIF_STATUS_RESPONSE_INDEX_SHIFT         (11U)
+#define SDIF_STATUS_RESPONSE_INDEX(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
+#define SDIF_STATUS_FIFO_COUNT_MASK              (0x3FFE0000U)
+#define SDIF_STATUS_FIFO_COUNT_SHIFT             (17U)
+#define SDIF_STATUS_FIFO_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK)
+#define SDIF_STATUS_DMA_ACK_MASK                 (0x40000000U)
+#define SDIF_STATUS_DMA_ACK_SHIFT                (30U)
+#define SDIF_STATUS_DMA_ACK(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK)
+#define SDIF_STATUS_DMA_REQ_MASK                 (0x80000000U)
+#define SDIF_STATUS_DMA_REQ_SHIFT                (31U)
+#define SDIF_STATUS_DMA_REQ(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK)
+/*! @} */
+
+/*! @name FIFOTH - FIFO Threshold Watermark register */
+/*! @{ */
+#define SDIF_FIFOTH_TX_WMARK_MASK                (0xFFFU)
+#define SDIF_FIFOTH_TX_WMARK_SHIFT               (0U)
+#define SDIF_FIFOTH_TX_WMARK(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK)
+#define SDIF_FIFOTH_RX_WMARK_MASK                (0xFFF0000U)
+#define SDIF_FIFOTH_RX_WMARK_SHIFT               (16U)
+#define SDIF_FIFOTH_RX_WMARK(x)                  (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK)
+#define SDIF_FIFOTH_DMA_MTS_MASK                 (0x70000000U)
+#define SDIF_FIFOTH_DMA_MTS_SHIFT                (28U)
+#define SDIF_FIFOTH_DMA_MTS(x)                   (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK)
+/*! @} */
+
+/*! @name CDETECT - Card Detect register */
+/*! @{ */
+#define SDIF_CDETECT_CARD_DETECT_MASK            (0x200U)
+#define SDIF_CDETECT_CARD_DETECT_SHIFT           (0U)
+#define SDIF_CDETECT_CARD_DETECT(x)              (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD_DETECT_SHIFT)) & SDIF_CDETECT_CARD_DETECT_MASK)
+/*! @} */
+
+/*! @name WRTPRT - Write Protect register */
+/*! @{ */
+#define SDIF_WRTPRT_WRITE_PROTECT_MASK           (0x1U)
+#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT          (0U)
+#define SDIF_WRTPRT_WRITE_PROTECT(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK)
+/*! @} */
+
+/*! @name TCBCNT - Transferred CIU Card Byte Count register */
+/*! @{ */
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK   (0xFFFFFFFFU)
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT  (0U)
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK)
+/*! @} */
+
+/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */
+/*! @{ */
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK   (0xFFFFFFFFU)
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT  (0U)
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK)
+/*! @} */
+
+/*! @name DEBNCE - Debounce Count register */
+/*! @{ */
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK          (0xFFFFFFU)
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT         (0U)
+#define SDIF_DEBNCE_DEBOUNCE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK)
+/*! @} */
+
+/*! @name RST_N - Hardware Reset */
+/*! @{ */
+#define SDIF_RST_N_CARD_RESET_MASK               (0x1U)
+#define SDIF_RST_N_CARD_RESET_SHIFT              (0U)
+#define SDIF_RST_N_CARD_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK)
+/*! @} */
+
+/*! @name BMOD - Bus Mode register */
+/*! @{ */
+#define SDIF_BMOD_SWR_MASK                       (0x1U)
+#define SDIF_BMOD_SWR_SHIFT                      (0U)
+#define SDIF_BMOD_SWR(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK)
+#define SDIF_BMOD_FB_MASK                        (0x2U)
+#define SDIF_BMOD_FB_SHIFT                       (1U)
+#define SDIF_BMOD_FB(x)                          (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK)
+#define SDIF_BMOD_DSL_MASK                       (0x7CU)
+#define SDIF_BMOD_DSL_SHIFT                      (2U)
+#define SDIF_BMOD_DSL(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK)
+#define SDIF_BMOD_DE_MASK                        (0x80U)
+#define SDIF_BMOD_DE_SHIFT                       (7U)
+#define SDIF_BMOD_DE(x)                          (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK)
+#define SDIF_BMOD_PBL_MASK                       (0x700U)
+#define SDIF_BMOD_PBL_SHIFT                      (8U)
+#define SDIF_BMOD_PBL(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK)
+/*! @} */
+
+/*! @name PLDMND - Poll Demand register */
+/*! @{ */
+#define SDIF_PLDMND_PD_MASK                      (0xFFFFFFFFU)
+#define SDIF_PLDMND_PD_SHIFT                     (0U)
+#define SDIF_PLDMND_PD(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK)
+/*! @} */
+
+/*! @name DBADDR - Descriptor List Base Address register */
+/*! @{ */
+#define SDIF_DBADDR_SDL_MASK                     (0xFFFFFFFFU)
+#define SDIF_DBADDR_SDL_SHIFT                    (0U)
+#define SDIF_DBADDR_SDL(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK)
+/*! @} */
+
+/*! @name IDSTS - Internal DMAC Status register */
+/*! @{ */
+#define SDIF_IDSTS_TI_MASK                       (0x1U)
+#define SDIF_IDSTS_TI_SHIFT                      (0U)
+#define SDIF_IDSTS_TI(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK)
+#define SDIF_IDSTS_RI_MASK                       (0x2U)
+#define SDIF_IDSTS_RI_SHIFT                      (1U)
+#define SDIF_IDSTS_RI(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK)
+#define SDIF_IDSTS_FBE_MASK                      (0x4U)
+#define SDIF_IDSTS_FBE_SHIFT                     (2U)
+#define SDIF_IDSTS_FBE(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK)
+#define SDIF_IDSTS_DU_MASK                       (0x10U)
+#define SDIF_IDSTS_DU_SHIFT                      (4U)
+#define SDIF_IDSTS_DU(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK)
+#define SDIF_IDSTS_CES_MASK                      (0x20U)
+#define SDIF_IDSTS_CES_SHIFT                     (5U)
+#define SDIF_IDSTS_CES(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK)
+#define SDIF_IDSTS_NIS_MASK                      (0x100U)
+#define SDIF_IDSTS_NIS_SHIFT                     (8U)
+#define SDIF_IDSTS_NIS(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK)
+#define SDIF_IDSTS_AIS_MASK                      (0x200U)
+#define SDIF_IDSTS_AIS_SHIFT                     (9U)
+#define SDIF_IDSTS_AIS(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK)
+#define SDIF_IDSTS_EB_MASK                       (0x1C00U)
+#define SDIF_IDSTS_EB_SHIFT                      (10U)
+#define SDIF_IDSTS_EB(x)                         (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK)
+#define SDIF_IDSTS_FSM_MASK                      (0x1E000U)
+#define SDIF_IDSTS_FSM_SHIFT                     (13U)
+#define SDIF_IDSTS_FSM(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK)
+/*! @} */
+
+/*! @name IDINTEN - Internal DMAC Interrupt Enable register */
+/*! @{ */
+#define SDIF_IDINTEN_TI_MASK                     (0x1U)
+#define SDIF_IDINTEN_TI_SHIFT                    (0U)
+#define SDIF_IDINTEN_TI(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK)
+#define SDIF_IDINTEN_RI_MASK                     (0x2U)
+#define SDIF_IDINTEN_RI_SHIFT                    (1U)
+#define SDIF_IDINTEN_RI(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK)
+#define SDIF_IDINTEN_FBE_MASK                    (0x4U)
+#define SDIF_IDINTEN_FBE_SHIFT                   (2U)
+#define SDIF_IDINTEN_FBE(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK)
+#define SDIF_IDINTEN_DU_MASK                     (0x10U)
+#define SDIF_IDINTEN_DU_SHIFT                    (4U)
+#define SDIF_IDINTEN_DU(x)                       (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK)
+#define SDIF_IDINTEN_CES_MASK                    (0x20U)
+#define SDIF_IDINTEN_CES_SHIFT                   (5U)
+#define SDIF_IDINTEN_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK)
+#define SDIF_IDINTEN_NIS_MASK                    (0x100U)
+#define SDIF_IDINTEN_NIS_SHIFT                   (8U)
+#define SDIF_IDINTEN_NIS(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK)
+#define SDIF_IDINTEN_AIS_MASK                    (0x200U)
+#define SDIF_IDINTEN_AIS_SHIFT                   (9U)
+#define SDIF_IDINTEN_AIS(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK)
+/*! @} */
+
+/*! @name DSCADDR - Current Host Descriptor Address register */
+/*! @{ */
+#define SDIF_DSCADDR_HDA_MASK                    (0xFFFFFFFFU)
+#define SDIF_DSCADDR_HDA_SHIFT                   (0U)
+#define SDIF_DSCADDR_HDA(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK)
+/*! @} */
+
+/*! @name BUFADDR - Current Buffer Descriptor Address register */
+/*! @{ */
+#define SDIF_BUFADDR_HBA_MASK                    (0xFFFFFFFFU)
+#define SDIF_BUFADDR_HBA_SHIFT                   (0U)
+#define SDIF_BUFADDR_HBA(x)                      (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK)
+/*! @} */
+
+/*! @name UHS_REG_EXT - UHS register */
+/*! @{ */
+#define SDIF_UHS_REG_EXT_MMC_VOLT_MASK           (0xFFFFU)
+#define SDIF_UHS_REG_EXT_MMC_VOLT_SHIFT          (0U)
+#define SDIF_UHS_REG_EXT_MMC_VOLT(x)             (((uint32_t)(((uint32_t)(x)) << SDIF_UHS_REG_EXT_MMC_VOLT_SHIFT)) & SDIF_UHS_REG_EXT_MMC_VOLT_MASK)
+#define SDIF_UHS_REG_EXT_CLK_SMPL_PHASE_MASK     (0x30000U)
+#define SDIF_UHS_REG_EXT_CLK_SMPL_PHASE_SHIFT    (16U)
+#define SDIF_UHS_REG_EXT_CLK_SMPL_PHASE(x)       (((uint32_t)(((uint32_t)(x)) << SDIF_UHS_REG_EXT_CLK_SMPL_PHASE_SHIFT)) & SDIF_UHS_REG_EXT_CLK_SMPL_PHASE_MASK)
+#define SDIF_UHS_REG_EXT_CLK_SMPL_DLY_MASK       (0x700000U)
+#define SDIF_UHS_REG_EXT_CLK_SMPL_DLY_SHIFT      (20U)
+#define SDIF_UHS_REG_EXT_CLK_SMPL_DLY(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_UHS_REG_EXT_CLK_SMPL_DLY_SHIFT)) & SDIF_UHS_REG_EXT_CLK_SMPL_DLY_MASK)
+#define SDIF_UHS_REG_EXT_CLK_DRV_PHASE_MASK      (0x1800000U)
+#define SDIF_UHS_REG_EXT_CLK_DRV_PHASE_SHIFT     (23U)
+#define SDIF_UHS_REG_EXT_CLK_DRV_PHASE(x)        (((uint32_t)(((uint32_t)(x)) << SDIF_UHS_REG_EXT_CLK_DRV_PHASE_SHIFT)) & SDIF_UHS_REG_EXT_CLK_DRV_PHASE_MASK)
+#define SDIF_UHS_REG_EXT_CLK_DRV_DLY_MASK        (0x38000000U)
+#define SDIF_UHS_REG_EXT_CLK_DRV_DLY_SHIFT       (27U)
+#define SDIF_UHS_REG_EXT_CLK_DRV_DLY(x)          (((uint32_t)(((uint32_t)(x)) << SDIF_UHS_REG_EXT_CLK_DRV_DLY_SHIFT)) & SDIF_UHS_REG_EXT_CLK_DRV_DLY_MASK)
+#define SDIF_UHS_REG_EXT_EXT_CLK_MUX_MASK        (0xC0000000U)
+#define SDIF_UHS_REG_EXT_EXT_CLK_MUX_SHIFT       (30U)
+#define SDIF_UHS_REG_EXT_EXT_CLK_MUX(x)          (((uint32_t)(((uint32_t)(x)) << SDIF_UHS_REG_EXT_EXT_CLK_MUX_SHIFT)) & SDIF_UHS_REG_EXT_EXT_CLK_MUX_MASK)
+/*! @} */
+
+/*! @name CARDTHRCTL - Card Threshold Control */
+/*! @{ */
+#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK         (0x1U)
+#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT        (0U)
+#define SDIF_CARDTHRCTL_CARDRDTHREN(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK         (0x2U)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT        (1U)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN(x)           (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK       (0xFF0000U)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT      (16U)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x)         (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK)
+/*! @} */
+
+/*! @name BACKENDPWR - Power control */
+/*! @{ */
+#define SDIF_BACKENDPWR_BACKENDPWR_MASK          (0x1U)
+#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT         (0U)
+#define SDIF_BACKENDPWR_BACKENDPWR(x)            (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK)
+/*! @} */
+
+/*! @name FIFO - SDIF FIFO */
+/*! @{ */
+#define SDIF_FIFO_DATA_MASK                      (0xFFFFFFFFU)
+#define SDIF_FIFO_DATA_SHIFT                     (0U)
+#define SDIF_FIFO_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK)
+/*! @} */
+
+/* The count of SDIF_FIFO */
+#define SDIF_FIFO_COUNT                          (32U)
+
+
+/*!
+ * @}
+ */ /* end of group SDIF_Register_Masks */
+
+
+/*!
+ * @}
+ */ /* end of group SDIF_Peripheral_Access_Layer */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/cvitek/drivers/libraries/sdif/dw_sdmmc.h

@@ -0,0 +1,375 @@
+/*
+* Copyright (C) Cvitek Co., Ltd. 2019-2029. All rights reserved.
+*/
+#ifndef __MMC_H__
+#define __MMC_H__
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+
+#define TOP_BASE        0x03000000
+#define DW_SDIO0_BASE               0x04320000
+#define DW_SDIO1_BASE               0x04310000
+#define DW_SDIO2_BASE               0x04300000
+
+#define CONFIG_SDIO_NUM   3
+
+#define MMC_CMD0            0
+#define MMC_CMD1            1
+#define MMC_CMD2            2
+#define MMC_CMD3            3
+#define MMC_CMD5            5
+#define MMC_CMD6            6
+#define MMC_CMD7            7
+#define MMC_CMD8            8
+#define MMC_CMD9            9
+#define MMC_CMD11           11
+#define MMC_CMD12           12
+#define MMC_CMD13           13
+#define MMC_CMD16           16
+#define MMC_CMD17           17
+#define MMC_CMD18           18
+#define MMC_CMD19           19
+#define MMC_CMD21           21
+#define MMC_CMD23           23
+#define MMC_CMD24           24
+#define MMC_CMD25           25
+#define MMC_CMD32           32
+#define MMC_CMD33           33
+#define MMC_CMD35           35
+#define MMC_CMD36           36
+#define MMC_CMD38           38
+#define MMC_CMD52           52
+#define MMC_CMD53           53
+#define MMC_CMD55           55
+#define SD_ACMD6            6
+#define SD_ACMD13           13
+#define SD_ACMD41           41
+#define SD_ACMD42           42
+#define SD_ACMD51           51
+
+static inline int mmc_op_multi(uint32_t opcode)
+{
+    return opcode == MMC_CMD25 || opcode == MMC_CMD18;
+}
+
+#define SDIO0_IRQ           36
+#define SDIO1_IRQ           38
+#define SDIO2_IRQ           34
+#define SDIO0_BASE          DW_SDIO1_BASE
+#define SDIO1_BASE          DW_SDIO0_BASE
+#define SDIO2_BASE          DW_SDIO2_BASE
+
+#define SDIF_DMA_ADDRESS               0x00
+#define SDIF_BLOCK_SIZE                0x04
+#define SDIF_MAKE_BLKSZ(dma, blksz)    ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF))
+#define SDIF_BLOCK_COUNT               0x06
+#define SDIF_ARGUMENT                  0x08
+#define SDIF_TRANSFER_MODE             0x0C
+#define SDIF_TRNS_DMA                  BIT(0)
+#define SDIF_TRNS_BLK_CNT_EN           BIT(1)
+#define SDIF_TRNS_ACMD12               BIT(2)
+#define SDIF_TRNS_READ                 BIT(4)
+#define SDIF_TRNS_MULTI                BIT(5)
+#define SDIF_TRNS_RESP_INT             BIT(8)
+#define SDIF_COMMAND                   0x0E
+#define SDIF_CMD_RESP_MASK             0x03
+#define SDIF_CMD_CRC                   0x08
+#define SDIF_CMD_INDEX                 0x10
+#define SDIF_CMD_DATA                  0x20
+#define SDIF_CMD_ABORTCMD              0xC0
+#define SDIF_CMD_RESP_NONE             0x00
+#define SDIF_CMD_RESP_LONG             0x01
+#define SDIF_CMD_RESP_SHORT            0x02
+#define SDIF_CMD_RESP_SHORT_BUSY       0x03
+#define SDIF_MAKE_CMD(c, f)            ((((c) & 0xff) << 8) | ((f) & 0xff))
+#define SDIF_RESPONSE_01               0x10
+#define SDIF_RESPONSE_23               0x14
+#define SDIF_RESPONSE_45               0x18
+#define SDIF_RESPONSE_67               0x1C
+
+#define SDIF_RESPONSE           0x10
+
+#define SDIF_BUFFER         0x20
+
+#define SDIF_PRESENT_STATE      0x24
+#define SDIF_DATA_INHIBIT       0x00000002
+#define SDIF_DOING_WRITE        0x00000100
+#define SDIF_DOING_READ     0x00000200
+#define SDIF_SPACE_AVAILABLE    0x00000400
+#define SDIF_DATA_AVAILABLE 0x00000800
+#define SDIF_CARD_PRESENT       0x00010000
+#define SDIF_WRITE_PROTECT      0x00080000
+#define SDIF_DATA_LVL_MASK      0x00F00000
+#define SDIF_DATA_LVL_SHIFT 20
+#define SDIF_DATA_0_LVL_MASK    0x00100000
+#define SDIF_CMD_LVL            0x01000000
+
+#define SDIF_CMD_INHIBIT               BIT(0)
+#define SDIF_CMD_INHIBIT_DAT           BIT(1)
+#define SDIF_CARD_INSERTED             BIT(16)
+#define SDIF_CARD_STABLE               BIT(17)
+#define SDIF_WR_PROTECT_SW_LVL         BIT(19)
+#define SDIF_DAT_XFER_WIDTH            BIT(1)
+#define SDIF_CTRL_SDMA                 0x00
+#define SDIF_CTRL_HISPD                0x04
+#define SDIF_BUS_VOL_VDD1_1_8V         0xC
+#define SDIF_BUS_VOL_VDD1_3_0V         0xE
+#define SDIF_CTRL_DMA_MASK             0x18
+#define SDIF_BUF_DATA_R                0x20
+#define SDIF_HOST_CONTROL              0x28
+#define SDIF_PWR_CONTROL               0x29
+#define SDIF_BLOCK_GAP_CONTROL         0x2A
+#define SDIF_WAKE_UP_CONTROL           0x2B
+#define SDIF_CLK_CTRL                  0x2C
+#define SDIF_TOUT_CTRL                 0x2E
+#define SDIF_SOFTWARE_RESET            0x2F
+#define SDIF_RESET_CMD                 0x02
+#define SDIF_RESET_DATA                0x04
+#define SDIF_INT_STATUS                0x30
+#define SDIF_ERR_INT_STATUS            0x32
+#define SDIF_INT_ENABLE                0x34
+#define SDIF_INT_XFER_COMPLETE         BIT(1)
+#define SDIF_INT_BUF_RD_READY          BIT(5)
+#define SDIF_INT_STATUS_EN             0x34
+#define SDIF_ERR_INT_STATUS_EN         0x36
+#define SDIF_SIGNAL_ENABLE             0x38
+#define SDIF_ERROR_SIGNAL_ENABLE       0x3A
+#define SDIF_AUTO_CMD_STATUS           0x3C
+#define SDIF_HOST_CONTROL2             0x3E
+#define SDIF_CAPABILITIES              0x40
+#define SDIF_CAPABILITIES_1            0x44
+#define SDIF_MAX_CURRENT               0x48
+#define SDIF_ADMA_ERROR                0x54
+#define SDIF_ADMA_ADDRESS              0x58
+#define SDIF_ADMA_ADDRESS_HI           0x5C
+#define SDIF_SLOT_INT_STATUS          0xFC
+#define SDIF_HOST_VERSION              0xFE
+#define SDIF_INT_XFER_COMPLETE_EN      BIT(1)
+#define SDIF_INT_DMA_END_EN            BIT(3)
+#define SDIF_INT_ERROR_EN              BIT(15)
+#define SDIF_HOST_ADMA2_LEN_MODE       BIT(10)
+#define SDIF_CTRL_UHS_MASK          0x0007
+#define SDIF_CTRL_UHS_SDR12         0x0000
+#define SDIF_CTRL_UHS_SDR25         0x0001
+#define SDIF_CTRL_UHS_SDR50         0x0002
+#define SDIF_CTRL_UHS_SDR104        0x0003
+#define SDIF_CTRL_UHS_DDR50         0x0004
+#define SDIF_CTRL_HS400         0x0005 /* Non-standard */
+#define SDIF_CTRL_DRV_TYPE_MASK     0x0030
+#define SDIF_CTRL_DRV_TYPE_B        0x0000
+#define SDIF_CTRL_DRV_TYPE_A        0x0010
+#define SDIF_CTRL_DRV_TYPE_C        0x0020
+#define SDIF_CTRL_DRV_TYPE_D        0x0030
+#define SDIF_CTRL_EXEC_TUNING       0x0040
+#define SDIF_CTRL_TUNED_CLK         0x0080
+#define SDIF_CTRL_PRESET_VAL_ENABLE   0x8000
+
+#define SDIF_GET_CMD(c) ((c>>8) & 0x3f)
+
+#define SDIF_INT_RESPONSE       0x00000001
+#define SDIF_INT_DATA_END       0x00000002
+#define SDIF_INT_BLK_GAP        0x00000004
+#define SDIF_INT_DMA_END        0x00000008
+#define SDIF_INT_SPACE_AVAIL    0x00000010
+#define SDIF_INT_DATA_AVAIL 0x00000020
+#define SDIF_INT_CARD_INSERT    0x00000040
+#define SDIF_INT_CARD_REMOVE    0x00000080
+#define SDIF_INT_CARD_INT       0x00000100
+#define SDIF_INT_RETUNE     0x00001000
+#define SDIF_INT_ERROR          0x00008000
+#define SDIF_INT_TIMEOUT        0x00010000
+#define SDIF_INT_CRC            0x00020000
+#define SDIF_INT_END_BIT        0x00040000
+#define SDIF_INT_INDEX          0x00080000
+#define SDIF_INT_DATA_TIMEOUT   0x00100000
+#define SDIF_INT_DATA_CRC       0x00200000
+#define SDIF_INT_DATA_END_BIT   0x00400000
+#define SDIF_INT_BUS_POWER      0x00800000
+#define SDIF_INT_ACMD12ERR      0x01000000
+#define SDIF_INT_ADMA_ERROR 0x02000000
+
+#define SDIF_INT_CMD_MASK   (SDIF_INT_RESPONSE | SDIF_INT_TIMEOUT | \
+        SDIF_INT_CRC | SDIF_INT_END_BIT | SDIF_INT_INDEX)
+#define SDIF_INT_DATA_MASK  (SDIF_INT_DATA_END | SDIF_INT_DMA_END | \
+        SDIF_INT_DATA_AVAIL | SDIF_INT_SPACE_AVAIL | \
+        SDIF_INT_DATA_TIMEOUT | SDIF_INT_DATA_CRC | \
+        SDIF_INT_DATA_END_BIT | SDIF_INT_ADMA_ERROR | \
+        SDIF_INT_BLK_GAP)
+
+#define SDIF_HOST_VER4_ENABLE          BIT(12)
+#define SDIF_CAPABILITIES1             0x40
+#define SDIF_CAPABILITIES2             0x44
+#define SDIF_ADMA_SA_LOW               0x58
+#define SDIF_ADMA_SA_HIGH              0x5C
+#define SDIF_HOST_CNTRL_VERS            0xFE
+#define SDIF_UHS_2_TIMER_CNTRL          0xC2
+
+#define P_VENDOR_SPECIFIC_AREA          0xE8
+#define P_VENDOR2_SPECIFIC_AREA         0xEA
+#define VENDOR_SD_CTRL                  0x2C
+
+
+#define DEFAULT_DIV_SD_INIT_CLOCK 0x2
+
+/*execute tuning register and bit flag*/
+#define SDIF_PHY_TX_RX_DLY  0x40
+#define SDIF_PHY_CONFIG     0x4c
+
+/*SDIO 0 register and bit flag*/
+#define REG_SDIO0_PAD_MASK      (0xFFFFFFF3)
+#define REG_SDIO0_PAD_SHIFT     (2)
+
+#define REG_SDIO0_CD_PAD_REG        (PINMUX_BASE + 0x900)
+#define REG_SDIO0_CD_PAD_VALUE      (1)
+
+#define REG_SDIO0_PWR_EN_PAD_REG    (PINMUX_BASE + 0x904)
+#define REG_SDIO0_PWR_EN_PAD_VALUE  (2)
+
+#define REG_SDIO0_CLK_PAD_REG       (PINMUX_BASE + 0xA00)
+#define REG_SDIO0_CLK_PAD_VALUE     (2)
+
+#define REG_SDIO0_CMD_PAD_REG       (PINMUX_BASE + 0xA04)
+#define REG_SDIO0_CMD_PAD_VALUE     (1)
+
+#define REG_SDIO0_DAT0_PAD_REG      (PINMUX_BASE + 0xA08)
+#define REG_SDIO0_DAT0_PAD_VALUE    (1)
+
+#define REG_SDIO0_DAT1_PAD_REG      (PINMUX_BASE + 0xA0C)
+#define REG_SDIO0_DAT1_PAD_VALUE    (1)
+
+#define REG_SDIO0_DAT2_PAD_REG      (PINMUX_BASE + 0xA10)
+#define REG_SDIO0_DAT2_PAD_VALUE    (1)
+
+#define REG_SDIO0_DAT3_PAD_REG      (PINMUX_BASE + 0xA14)
+#define REG_SDIO0_DAT3_PAD_VALUE    (1)
+
+#define REG_SDIO0_CD_PIO_REG        (PINMUX_BASE + 0x34)
+#define REG_SDIO0_CD_PIO_VALUE      (0x3)
+
+#define REG_SDIO0_PWR_EN_PIO_REG    (PINMUX_BASE + 0x38)
+#define REG_SDIO0_PWR_EN_PIO_VALUE  (0x0)
+
+#define REG_SDIO0_CLK_PIO_REG       (PINMUX_BASE + 0x1C)
+#define REG_SDIO0_CLK_PIO_VALUE     (0x0)
+
+#define REG_SDIO0_CMD_PIO_REG       (PINMUX_BASE + 0x20)
+#define REG_SDIO0_CMD_PIO_VALUE     (0x0)
+
+#define REG_SDIO0_DAT0_PIO_REG      (PINMUX_BASE + 0x24)
+#define REG_SDIO0_DAT0_PIO_VALUE    (0x0)
+
+#define REG_SDIO0_DAT1_PIO_REG      (PINMUX_BASE + 0x28)
+#define REG_SDIO0_DAT1_PIO_VALUE    (0x0)
+
+#define REG_SDIO0_DAT2_PIO_REG      (PINMUX_BASE + 0x2C)
+#define REG_SDIO0_DAT2_PIO_VALUE    (0x0)
+
+#define REG_SDIO0_DAT3_PIO_REG      (PINMUX_BASE + 0x30)
+#define REG_SDIO0_DAT3_PIO_VALUE    (0x0)
+
+/*SDIO 1 register and bit flag*/
+#define RTCIO_BASE (0x5027000)
+#define REG_SDIO1_PAD_MASK      (0xFFFFFFF3)
+#define REG_SDIO1_PAD_SHIFT     (2)
+
+#define REG_SDIO1_CLK_PAD_REG       (RTCIO_BASE + 0x6C)
+#define REG_SDIO1_CLK_PAD_VALUE     (2)
+
+#define REG_SDIO1_CMD_PAD_REG       (RTCIO_BASE + 0x68)
+#define REG_SDIO1_CMD_PAD_VALUE     (1)
+
+#define REG_SDIO1_DAT0_PAD_REG      (RTCIO_BASE + 0x64)
+#define REG_SDIO1_DAT0_PAD_VALUE    (1)
+
+#define REG_SDIO1_DAT1_PAD_REG      (RTCIO_BASE + 0x60)
+#define REG_SDIO1_DAT1_PAD_VALUE    (1)
+
+#define REG_SDIO1_DAT2_PAD_REG      (RTCIO_BASE + 0x5C)
+#define REG_SDIO1_DAT2_PAD_VALUE    (1)
+
+#define REG_SDIO1_DAT3_PAD_REG      (RTCIO_BASE + 0x58)
+#define REG_SDIO1_DAT3_PAD_VALUE    (1)
+
+#define REG_SDIO1_CLK_PIO_REG       (PINMUX_BASE + 0xE4)
+#define REG_SDIO1_CLK_PIO_VALUE     (0x0)
+
+#define REG_SDIO1_CMD_PIO_REG       (PINMUX_BASE + 0xE0)
+#define REG_SDIO1_CMD_PIO_VALUE     (0x0)
+
+#define REG_SDIO1_DAT0_PIO_REG      (PINMUX_BASE + 0xDC)
+#define REG_SDIO1_DAT0_PIO_VALUE    (0x0)
+
+#define REG_SDIO1_DAT1_PIO_REG      (PINMUX_BASE + 0xD8)
+#define REG_SDIO1_DAT1_PIO_VALUE    (0x0)
+
+#define REG_SDIO1_DAT2_PIO_REG      (PINMUX_BASE + 0xD4)
+#define REG_SDIO1_DAT2_PIO_VALUE    (0x0)
+
+#define REG_SDIO1_DAT3_PIO_REG      (PINMUX_BASE + 0xD0)
+#define REG_SDIO1_DAT3_PIO_VALUE    (0x0)
+
+#define RTC_CTRL_BASE       0x5025000
+#define RTCSYS_CLKMUX       (RTC_CTRL_BASE + 0x1C)
+#define RTCSYS_CLKBYP       (RTC_CTRL_BASE + 0x30)
+#define RTCSYS_MCU51_ICTRL1 (RTC_CTRL_BASE + 0x7C)
+
+#define RTCSYS_CTRL_BASE    0x03000000
+#define RTCSYS_CTRL     (RTCSYS_CTRL_BASE + 0x248)
+
+/*SDIO 2 register and bit flag*/
+#define REG_SDIO2_PAD_MASK (0xFFFFFFF3)
+#define REG_SDIO2_PAD_SHIFT (2)
+
+#define REG_SDIO2_RSTN_PAD_REG (PINMUX_BASE + 0x914)
+#define REG_SDIO2_RSTN_PAD_VALUE (1)
+
+#define REG_SDIO2_CLK_PAD_REG (PINMUX_BASE + 0x91C)
+#define REG_SDIO2_CLK_PAD_VALUE (2)
+
+#define REG_SDIO2_CMD_PAD_REG (PINMUX_BASE + 0x928)
+#define REG_SDIO2_CMD_PAD_VALUE (1)
+
+#define REG_SDIO2_DAT0_PAD_REG (PINMUX_BASE + 0x920)
+#define REG_SDIO2_DAT0_PAD_VALUE (1)
+
+#define REG_SDIO2_DAT1_PAD_REG (PINMUX_BASE + 0x92C)
+#define REG_SDIO2_DAT1_PAD_VALUE (1)
+
+#define REG_SDIO2_DAT2_PAD_REG (PINMUX_BASE + 0x918)
+#define REG_SDIO2_DAT2_PAD_VALUE (1)
+
+#define REG_SDIO2_DAT3_PAD_REG (PINMUX_BASE + 0x924)
+#define REG_SDIO2_DAT3_PAD_VALUE (1)
+
+#define REG_SDIO2_RSTN_PIO_REG (PINMUX_BASE + 0x48)
+#define REG_SDIO2_RSTN_PIO_VALUE (0x0)
+
+#define REG_SDIO2_CLK_PIO_REG (PINMUX_BASE + 0x50)
+#define REG_SDIO2_CLK_PIO_VALUE (0x0)
+
+#define REG_SDIO2_CMD_PIO_REG (PINMUX_BASE + 0x5C)
+#define REG_SDIO2_CMD_PIO_VALUE (0x0)
+
+#define REG_SDIO2_DAT0_PIO_REG (PINMUX_BASE + 0x54)
+#define REG_SDIO2_DAT0_PIO_VALUE (0x0)
+
+#define REG_SDIO2_DAT1_PIO_REG (PINMUX_BASE + 0x60)
+#define REG_SDIO2_DAT1_PIO_VALUE (0x0)
+
+#define REG_SDIO2_DAT2_PIO_REG (PINMUX_BASE + 0x4C)
+#define REG_SDIO2_DAT2_PIO_VALUE (0x0)
+
+#define REG_SDIO2_DAT3_PIO_REG (PINMUX_BASE + 0x58)
+#define REG_SDIO2_DAT3_PIO_VALUE (0x0)
+
+
+#define MMC_SDIO0_PLL_REGISTER 0x3002070
+#define MMC_SDIO1_PLL_REGISTER 0x300207C
+#define MMC_SDIO2_PLL_REGISTER 0x3002064
+#define MMC_MAX_CLOCK_DIV_VALUE (0x40009)
+#define CLOCK_BYPASS_SELECT_REGISTER (0x3002030)
+
+#endif /* __HAL_DW_SDIO_H_ */

bsp/cvitek/drivers/port/mnt.c

@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022/12/25     flyingcys    first version
+ */
+#include <rtthread.h>
+
+#ifdef RT_USING_DFS
+#include <dfs_fs.h>
+#include "dfs_romfs.h"
+
+#define DBG_TAG "app.filesystem"
+#define DBG_LVL DBG_LOG
+#include <rtdbg.h>
+
+static const struct romfs_dirent _romfs_root[] =
+{
+#ifdef BSP_USING_ON_CHIP_FLASH
+    {ROMFS_DIRENT_DIR, "flash", RT_NULL, 0},
+#endif
+    {ROMFS_DIRENT_DIR, "sdcard", RT_NULL, 0}
+};
+
+const struct romfs_dirent romfs_root =
+{
+    ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root)  / sizeof(_romfs_root[0])
+};
+
+static void sd_mount(void *parameter)
+{
+    while (1)
+    {
+        rt_thread_mdelay(500);
+
+        if (rt_device_find("sd0") != RT_NULL)
+        {
+            if (dfs_mount("sd0", "/sdcard", "elm", 0, 0) == RT_EOK)
+            {
+                LOG_I("sd card mount to '/sdcard'");
+                break;
+            }
+            else
+            {
+                LOG_W("sd card mount to '/sdcard' failed! %d\n", rt_get_errno());
+            }
+        }
+    }
+}
+
+int mount_init(void)
+{
+    if(dfs_mount(RT_NULL, "/", "rom", 0, &romfs_root) != 0)
+    {
+        LOG_E("rom mount to '/' failed!");
+    }
+
+#ifdef BSP_USING_ON_CHIP_FLASH_FS
+    struct rt_device *flash_dev = RT_NULL;
+
+    /* 使用 filesystem 分区创建块设备，块设备名称为 filesystem */
+    flash_dev = fal_blk_device_create("filesystem");
+    if(flash_dev == RT_NULL)
+    {
+        LOG_E("Failed to create device.\n");
+        return -RT_ERROR;
+    }
+
+    if (dfs_mount("filesystem", "/flash", "lfs", 0, 0) != 0)
+    {
+        LOG_I("file system initialization failed!\n");
+        if(dfs_mkfs("lfs", "filesystem") == 0)
+        {
+            if (dfs_mount("filesystem", "/flash", "lfs", 0, 0) == 0)
+            {
+                LOG_I("mount to '/flash' success!");
+            }
+        }
+    }
+    else
+    {
+        LOG_I("mount to '/flash' success!");
+    }
+#endif
+
+#ifdef BSP_USING_SDH
+    rt_thread_t tid;
+
+    tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
+                            4096, RT_THREAD_PRIORITY_MAX - 2, 20);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        LOG_E("create sd_mount thread err!");
+    }
+#endif
+
+    return RT_EOK;
+}
+INIT_APP_EXPORT(mount_init);
+
+#endif /* RT_USING_DFS */

libcpu/risc-v/t-head/c906/tick.c

@@ -49,3 +49,22 @@ int rt_hw_tick_init(void)
 
     return 0;
 }
+
+/**
+ * This function will delay for some us.
+ *
+ * @param us the delay time of us
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    unsigned long start_time;
+    unsigned long end_time;
+    unsigned long run_time;
+
+    start_time = get_ticks();
+    end_time = start_time + us * (TIMER_CLK_FREQ / 1000000);
+    do
+    {
+        run_time = get_ticks();
+    } while(run_time < end_time);
+}