libs/rt-thread
libs/rt-thread
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This commit is contained in:
Huang bo 2021-11-18 09:23:29 +08:00
parent 8ab19db7fa
commit 2b13e2fa57
12 changed files with 216 additions and 219 deletions
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12
libcpu/ti-dsp/c6x/context.asm
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@ -104,8 +104,8 @@ rt_hw_context_switch:
STDW .D2T2 B13:B12,*SP--[1] ; Store PC:CSR STDW .D2T2 B13:B12,*SP--[1] ; Store PC:CSR
|| MVC .S2 TSR,B5 || MVC .S2 TSR,B5
MVC .S2 ILC,B11 ; MVC .S2 ILC,B11
MVC .S2 RILC,B10 ; MVC .S2 RILC,B10
STDW .D2T2 B11:B10,*SP--[1] ; Store RILC:ILC STDW .D2T2 B11:B10,*SP--[1] ; Store RILC:ILC
|| MV .S1X B5,A3 || MV .S1X B5,A3
@ -113,7 +113,7 @@ rt_hw_context_switch:
STDW .D2T1 A3:A2,*SP--[1] ; Store TSR:stack type STDW .D2T1 A3:A2,*SP--[1] ; Store TSR:stack type
STW SP,*A4 ; Save thread's stack pointer STW SP,*A4 ; Save thread's stack pointer
B rt_hw_context_switch_to B rt_hw_context_switch_to
MV B4,A4 ; MV B4,A4
NOP 4 NOP 4
;} ;}
@ -131,7 +131,7 @@ rt_hw_context_switch_to:
LDDW .D2T2 *++SP[1],B13:B12 ; get PC (B13) and CSR (B12) LDDW .D2T2 *++SP[1],B13:B12 ; get PC (B13) and CSR (B12)
NOP 2 NOP 2
MV B8,B0 MV B8,B0
[B0] B _rt_thread_interrupt_stack ; [B0] B _rt_thread_interrupt_stack
NOP 5 NOP 5
; ;
; this maybe do better ; this maybe do better
@ -318,9 +318,7 @@ rt_preempt_context_restore:
NOP 3 NOP 3
STW SP,*A10 ; store sp in preempted tasks's TCB STW SP,*A10 ; store sp in preempted tasks's TCB
B rt_hw_context_switch_to B rt_hw_context_switch_to
MV B11,A4 ; MV B11,A4
NOP 4 NOP 4
;} ;}
.end .end

1
libcpu/ti-dsp/c6x/cpuport.c
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@ -194,4 +194,3 @@ void hw_int15_handler(void)
{ {
} }