libs/rt-thread
libs/rt-thread
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This commit is contained in:
Huang bo 2021-11-18 09:23:29 +08:00
parent 8ab19db7fa
commit 2b13e2fa57
12 changed files with 216 additions and 219 deletions
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10
bsp/ti-tms320c6678/applications/board.c
View File

@ -20,13 +20,13 @@
*/
void rt_hw_board_init(void)
{
// initial CPU core
KeyStone_common_CPU_init();
// initial CPU core
KeyStone_common_CPU_init();
// initial interrupt controller
rt_hw_interrupt_init();
// initial interrupt controller
rt_hw_interrupt_init();
// initial system timer
// initial system timer
rt_hw_system_timer_init();
/* initialize memory system */

52
bsp/ti-tms320c6678/applications/main.c
View File

@ -15,8 +15,8 @@
void rt_init_thread_entry(void *parameter)
{
rt_kprintf("hello rt-thread\n");
return 0;
rt_kprintf("hello rt-thread\n");
return 0;
}
int rt_application_init(void)
@ -39,42 +39,42 @@ int rt_application_init(void)
*/
void rtthread_startup(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* disable interrupt first */
rt_hw_interrupt_disable();
/* init board */
rt_hw_board_init();
/* init board */
rt_hw_board_init();
/* show version */
rt_show_version();
/* show version */
rt_show_version();
/* init timer system */
rt_system_timer_init();
/* init timer system */
rt_system_timer_init();
/* init scheduler system */
rt_system_scheduler_init();
/* init scheduler system */
rt_system_scheduler_init();
/* init application */
rt_application_init();
/* init application */
rt_application_init();
/* init timer thread */
rt_system_timer_thread_init();
/* init timer thread */
rt_system_timer_thread_init();
/* init idle thread */
rt_thread_idle_init();
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
/* never reach here */
return ;
}
void main(void)
{
/* startup RT-Thread RTOS */
rtthread_startup();
/* startup RT-Thread RTOS */
rtthread_startup();
for ( ; ; );
for ( ; ; );
}

12
bsp/ti-tms320c6678/driver/drv_timer.c
View File

@ -20,13 +20,13 @@
*/
void rt_hw_systick_isr(void)
{
/* enter interrupt */
rt_interrupt_enter();
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
/* leave interrupt */
rt_interrupt_leave();
}
/**
@ -34,7 +34,7 @@ void rt_hw_systick_isr(void)
*/
void rt_hw_system_timer_init(void)
{
// initial system timer interrupt, map local timer interrupt to INT14
// initial system timer interrupt, map local timer interrupt to INT14
gpCGEM_regs->INTMUX3 = (CSL_GEM_TINTLN<<CSL_CGEM_INTMUX3_INTSEL14_SHIFT);
// enable CPU INT14
CPU_interrupt_enable(1<<14);

88
libcpu/ti-dsp/c6x/c66xx.h
View File

@ -21,60 +21,60 @@
struct rt_hw_register
{
RT_REG_PAIR(b17, b16);
RT_REG_PAIR(b19, b18);
RT_REG_PAIR(b21, b20);
RT_REG_PAIR(b23, b22);
RT_REG_PAIR(b25, b24);
RT_REG_PAIR(b27, b26);
RT_REG_PAIR(b29, b28);
RT_REG_PAIR(b31, b30);
RT_REG_PAIR(b17, b16);
RT_REG_PAIR(b19, b18);
RT_REG_PAIR(b21, b20);
RT_REG_PAIR(b23, b22);
RT_REG_PAIR(b25, b24);
RT_REG_PAIR(b27, b26);
RT_REG_PAIR(b29, b28);
RT_REG_PAIR(b31, b30);
RT_REG_PAIR(b1, b0);
RT_REG_PAIR(b3, b2);
RT_REG_PAIR(b5, b4);
RT_REG_PAIR(b7, b6);
RT_REG_PAIR(b9, b8);
RT_REG_PAIR(b11, b10);
RT_REG_PAIR(b13, b12);
RT_REG_PAIR(b1, b0);
RT_REG_PAIR(b3, b2);
RT_REG_PAIR(b5, b4);
RT_REG_PAIR(b7, b6);
RT_REG_PAIR(b9, b8);
RT_REG_PAIR(b11, b10);
RT_REG_PAIR(b13, b12);
RT_REG_PAIR(a17, a16);
RT_REG_PAIR(a19, a18);
RT_REG_PAIR(a21, a20);
RT_REG_PAIR(a23, a22);
RT_REG_PAIR(a25, a24);
RT_REG_PAIR(a27, a26);
RT_REG_PAIR(a29, a28);
RT_REG_PAIR(a31, a30);
RT_REG_PAIR(a17, a16);
RT_REG_PAIR(a19, a18);
RT_REG_PAIR(a21, a20);
RT_REG_PAIR(a23, a22);
RT_REG_PAIR(a25, a24);
RT_REG_PAIR(a27, a26);
RT_REG_PAIR(a29, a28);
RT_REG_PAIR(a31, a30);
RT_REG_PAIR(a1, a0);
RT_REG_PAIR(a3, a2);
RT_REG_PAIR(a5, a4);
RT_REG_PAIR(a7, a6);
RT_REG_PAIR(a9, a8);
RT_REG_PAIR(a11, a10);
RT_REG_PAIR(a13, a12);
RT_REG_PAIR(a1, a0);
RT_REG_PAIR(a3, a2);
RT_REG_PAIR(a5, a4);
RT_REG_PAIR(a7, a6);
RT_REG_PAIR(a9, a8);
RT_REG_PAIR(a11, a10);
RT_REG_PAIR(a13, a12);
RT_REG_PAIR(a15, a14);
RT_REG_PAIR(sp, dp);
RT_REG_PAIR(a15, a14);
RT_REG_PAIR(sp, dp);
};
struct rt_hw_exp_stack_register
{
RT_REG_PAIR(tsr, orig_a4);
RT_REG_PAIR(rilc, ilc);
RT_REG_PAIR(pc, csr);
RT_REG_PAIR(tsr, orig_a4);
RT_REG_PAIR(rilc, ilc);
RT_REG_PAIR(pc, csr);
struct rt_hw_register hw_register;
};
#define __dint() asm(" DINT")
#define __rint() asm(" RINT")
#define __system_call() asm(" SWE")
#define __enter_idle() asm(" IDLE")
#define __nop() asm(" NOP")
#define __mfence() asm(" MFENCE")
#define __dint() asm(" DINT")
#define __rint() asm(" RINT")
#define __system_call() asm(" SWE")
#define __enter_idle() asm(" IDLE")
#define __nop() asm(" NOP")
#define __mfence() asm(" MFENCE")
#define __SYSREG(ADDR, TYPE) (*(volatile TYPE*)(ADDR))
#define __SYSREGA(ADDR, TYPE) ((volatile TYPE*)(ADDR))
#define __SYSREG(ADDR, TYPE) (*(volatile TYPE*)(ADDR))
#define __SYSREGA(ADDR, TYPE) ((volatile TYPE*)(ADDR))
#endif /* __C66XX_H__ */

80
libcpu/ti-dsp/c6x/context.asm
View File

@ -9,18 +9,18 @@
;
;-----------------------------------------------------------
; context switch for C6000 DSP
; context switch for C6000 DSP
;-----------------------------------------------------------
.include "contextinc.asm"
;-----------------------------------------------------------
; macro definition
; macro definition
;-----------------------------------------------------------
DP .set B14
SP .set B15
;-----------------------------------------------------------
; extern variable
; extern variable
;-----------------------------------------------------------
.ref rt_system_stack_top
;
@ -28,7 +28,7 @@ SP .set B15
;
;-----------------------------------------------------------
; global variable
; global variable
;-----------------------------------------------------------
.global rt_interrupt_from_thread
.global rt_interrupt_to_thread
@ -47,7 +47,7 @@ rt_hw_enable_exception:
MVC .S2 B3,NRP
MVK .L2 0xC,B1
OR .D2 B0,B1,B0
MVC .S2 B0,TSR ; Set GEE and XEN in TSR
MVC .S2 B0,TSR ; Set GEE and XEN in TSR
B .S2 NRP
NOP 5
@ -93,27 +93,27 @@ rt_hw_context_switch:
; {
SUBAW .D2 SP,2,SP
ADD .D1X SP,-8,A15
|| STDW .D2T1 A15:A14,*SP--[3] ; Store A15:A14
|| STDW .D2T1 A15:A14,*SP--[3] ; Store A15:A14
STDW .D2T2 B13:B12,*SP--[1] ; Store B13:B12
|| STDW .D1T1 A13:A12,*A15--[1] ; Store A13:A12
STDW .D2T2 B13:B12,*SP--[1] ; Store B13:B12
|| STDW .D1T1 A13:A12,*A15--[1] ; Store A13:A12
|| MV B3,B13
STDW .D2T2 B11:B10,*SP--[1] ; Store B11:B10
|| STDW .D1T1 A11:A10,*A15--[1] ; Store A11:A10
STDW .D2T2 B11:B10,*SP--[1] ; Store B11:B10
|| STDW .D1T1 A11:A10,*A15--[1] ; Store A11:A10
|| MVC .S2 CSR,B12
STDW .D2T2 B13:B12,*SP--[1] ; Store PC:CSR
STDW .D2T2 B13:B12,*SP--[1] ; Store PC:CSR
|| MVC .S2 TSR,B5
MVC .S2 ILC,B11 ;
MVC .S2 RILC,B10 ;
STDW .D2T2 B11:B10,*SP--[1] ; Store RILC:ILC
MVC .S2 ILC,B11
MVC .S2 RILC,B10
STDW .D2T2 B11:B10,*SP--[1] ; Store RILC:ILC
|| MV .S1X B5,A3
ZERO A2 ;
STDW .D2T1 A3:A2,*SP--[1] ; Store TSR:stack type
STW SP,*A4 ; Save thread's stack pointer
ZERO A2 ;
STDW .D2T1 A3:A2,*SP--[1] ; Store TSR:stack type
STW SP,*A4 ; Save thread's stack pointer
B rt_hw_context_switch_to
MV B4,A4 ;
MV B4,A4
NOP 4
;}
@ -126,24 +126,24 @@ rt_hw_context_switch_to:
;{
LDW *A4,SP
NOP 4
LDDW .D2T2 *++SP[1],B9:B8 ; get TSR (B9) and stack frame type (B8)
LDDW .D2T2 *++SP[1],B11:B10 ; get RILC (B11) and ILC (B10)
LDDW .D2T2 *++SP[1],B13:B12 ; get PC (B13) and CSR (B12)
LDDW .D2T2 *++SP[1],B9:B8 ; get TSR (B9) and stack frame type (B8)
LDDW .D2T2 *++SP[1],B11:B10 ; get RILC (B11) and ILC (B10)
LDDW .D2T2 *++SP[1],B13:B12 ; get PC (B13) and CSR (B12)
NOP 2
MV B8,B0
[B0] B _rt_thread_interrupt_stack ;
[B0] B _rt_thread_interrupt_stack
NOP 5
;
; this maybe do better
;
LDDW .D2T2 *++SP[1],B11:B10
|| MVC .S2 B11,RILC ; Restore RILC
|| MVC .S2 B11,RILC ; Restore RILC
LDDW .D2T2 *++SP[1],B13:B12
|| MVC .S2 B10,ILC ; Restore ILC
|| MVC .S2 B10,ILC ; Restore ILC
LDDW .D2T1 *++SP[1],A11:A10
|| MV B13,B3 ; Restore PC
|| MV B13,B3 ; Restore PC
LDDW .D2T1 *++SP[1],A13:A12
|| MVC .S2 B12,CSR ; Restore CSR
|| MVC .S2 B12,CSR ; Restore CSR
LDDW .D2T1 *++SP[1],A15:A14
B B3 ; Return to caller
ADDAW .D2 SP,2,SP
@ -172,21 +172,21 @@ _rt_thread_interrupt_stack:
LDDW .D1T1 *++A15[1],A3:A2
|| LDDW .D2T2 *++SP[1],B3:B2
|| MVC .S2 B9,ITSR ; Restore ITSR
|| MVC .S2 B9,ITSR ; Restore ITSR
LDDW .D1T1 *++A15[1],A5:A4
|| LDDW .D2T2 *++SP[1],B5:B4
|| MVC .S2 B11,RILC ; Restore RILC
|| MVC .S2 B11,RILC ; Restore RILC
LDDW .D1T1 *++A15[1],A7:A6
|| LDDW .D2T2 *++SP[1],B7:B6
|| MVC .S2 B10,ILC ; Restore ILC
|| MVC .S2 B10,ILC ; Restore ILC
LDDW .D1T1 *++A15[1],A9:A8
|| LDDW .D2T2 *++SP[1],B9:B8
|| MVC .S2 B13,IRP ; Restore IPR
|| MVC .S2 B13,IRP ; Restore IPR
LDDW .D1T1 *++A15[1],A11:A10
|| LDDW .D2T2 *++SP[1],B11:B10
|| MVC .S2 B12,CSR ; Restore CSR
|| MVC .S2 B12,CSR ; Restore CSR
LDDW .D1T1 *++A15[1],A13:A12
|| LDDW .D2T2 *++SP[1],B13:B12
@ -242,9 +242,9 @@ rt_interrupt_context_restore:
CMPEQ 1,A1,A2
[A2] BNOP rt_preempt_context_restore,5
NOP 5
LDDW .D2T2 *++SP[1],B9:B8 ; get TSR (B9)
LDDW .D2T2 *++SP[1],B11:B10 ; get RILC (B11) and ILC (B10)
LDDW .D2T2 *++SP[1],B13:B12 ; get PC (B13) and CSR (B12)
LDDW .D2T2 *++SP[1],B9:B8 ; get TSR (B9)
LDDW .D2T2 *++SP[1],B11:B10 ; get RILC (B11) and ILC (B10)
LDDW .D2T2 *++SP[1],B13:B12 ; get PC (B13) and CSR (B12)
ADDAW .D1X SP,30,A15
@ -290,15 +290,15 @@ rt_interrupt_context_restore:
|| MVKL .S1 rt_system_stack_top,A15
MVKH .S1 rt_system_stack_top,A15
|| ADDAW .D1X SP,6,A14
STW .D1T1 A14,*A15 ; save system stack pointer
STW .D1T1 A14,*A15 ; save system stack pointer
LDDW .D2T1 *++SP[1],A15:A14
B .S2 IRP ; return from interruption
B .S2 IRP ; return from interruption
LDDW .D2T2 *+SP[1],SP:DP
NOP 4
rt_preempt_context_restore:
ZERO A12
STW A12,*A3 ; clear rt_thread_switch_interrupt_flag
STW A12,*A3 ; clear rt_thread_switch_interrupt_flag
;
; restore saved registers by system stack
;
@ -316,11 +316,9 @@ rt_preempt_context_restore:
MVKH rt_interrupt_to_thread,B10
LDW *B10,B11
NOP 3
STW SP,*A10 ; store sp in preempted tasks's TCB
STW SP,*A10 ; store sp in preempted tasks's TCB
B rt_hw_context_switch_to
MV B11,A4 ;
MV B11,A4
NOP 4
;}
.end

44
libcpu/ti-dsp/c6x/contextinc.asm
View File

@ -9,28 +9,28 @@
;
;-----------------------------------------------------------
; macro definition
; macro definition
;-----------------------------------------------------------
SAVE_ALL .macro __rp, __tsr
STW .D2T2 B0,*SP--[2] ; save original B0
STW .D2T2 B0,*SP--[2] ; save original B0
MVKL .S2 rt_system_stack_top,B0
MVKH .S2 rt_system_stack_top,B0
LDW .D2T2 *B0,B1 ; system stack
LDW .D2T2 *B0,B1 ; system stack
NOP 3
STW .D2T2 B1,*+SP[1] ; save original B1
XOR .D2 SP,B1,B0 ; check current stack types
LDW .D2T2 *+SP[1],B1 ; restore B0/B1
STW .D2T2 B1,*+SP[1] ; save original B1
XOR .D2 SP,B1,B0 ; check current stack types
LDW .D2T2 *+SP[1],B1 ; restore B0/B1
LDW .D2T2 *++SP[2],B0
SHR .S2 B0,12,B0 ; 0 if already using system stack
[B0] STDW .D2T2 SP:DP,*--B1[1] ; thread: save thread sp/dp system stack
[B0] MV .S2 B1,SP ; and switch to system stack
||[!B0] STDW .D2T2 SP:DP,*--SP[1] ; kernel: nest interrupt save(not support)
SHR .S2 B0,12,B0 ; 0 if already using system stack
[B0] STDW .D2T2 SP:DP,*--B1[1] ; thread: save thread sp/dp system stack
[B0] MV .S2 B1,SP ; and switch to system stack
||[!B0] STDW .D2T2 SP:DP,*--SP[1] ; kernel: nest interrupt save(not support)
SUBAW .D2 SP,2,SP
ADD .D1X SP,-8,A15
|| STDW .D2T1 A15:A14,*SP--[16] ; save A15:A14
|| STDW .D2T1 A15:A14,*SP--[16] ; save A15:A14
STDW .D2T2 B13:B12,*SP--[1]
|| STDW .D1T1 A13:A12,*A15--[1]
@ -73,15 +73,15 @@ SAVE_ALL .macro __rp, __tsr
STDW .D2T2 B17:B16,*SP--[1]
|| STDW .D1T1 A17:A16,*A15--[1]
STDW .D2T2 B13:B12,*SP--[1] ; save PC and CSR
STDW .D2T2 B11:B10,*SP--[1] ; save RILC and ILC
STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4(stack type)
STDW .D2T2 B13:B12,*SP--[1] ; save PC and CSR
STDW .D2T2 B11:B10,*SP--[1] ; save RILC and ILC
STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4(stack type)
.endm
RESTORE_ALL .macro __rp, __tsr
LDDW .D2T2 *++SP[1],B9:B8 ; get TSR (B9)
LDDW .D2T2 *++SP[1],B11:B10 ; get RILC (B11) and ILC (B10)
LDDW .D2T2 *++SP[1],B13:B12 ; get PC (B13) and CSR (B12)
LDDW .D2T2 *++SP[1],B9:B8 ; get TSR (B9)
LDDW .D2T2 *++SP[1],B11:B10 ; get RILC (B11) and ILC (B10)
LDDW .D2T2 *++SP[1],B13:B12 ; get PC (B13) and CSR (B12)
ADDAW .D1X SP,30,A15
@ -127,7 +127,7 @@ RESTORE_ALL .macro __rp, __tsr
|| MVKL .S1 rt_system_stack_top,A15
MVKH .S1 rt_system_stack_top,A15
|| ADDAW .D1X SP,6,A14
STW .D1T1 A14,*A15 ; save system stack pointer
STW .D1T1 A14,*A15 ; save system stack pointer
LDDW .D2T1 *++SP[1],A15:A14
LDDW .D2T2 *+SP[1],SP:DP
@ -139,7 +139,7 @@ THREAD_SAVE_ALL .macro __rp, __tsr
SUBAW .D2 SP,2,SP
ADD .D1X SP,-8,A15
|| STDW .D2T1 A15:A14,*SP--[16] ; save A15:A14
|| STDW .D2T1 A15:A14,*SP--[16] ; save A15:A14
STDW .D2T2 B13:B12,*SP--[1]
|| STDW .D1T1 A13:A12,*A15--[1]
@ -181,7 +181,7 @@ THREAD_SAVE_ALL .macro __rp, __tsr
STDW .D2T2 B17:B16,*SP--[1]
|| STDW .D1T1 A17:A16,*A15--[1]
STDW .D2T2 B13:B12,*SP--[1] ; save PC and CSR
STDW .D2T2 B11:B10,*SP--[1] ; save RILC and ILC
STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4(stack type)
STDW .D2T2 B13:B12,*SP--[1] ; save PC and CSR
STDW .D2T2 B11:B10,*SP--[1] ; save RILC and ILC
STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4(stack type)
.endm

1
libcpu/ti-dsp/c6x/cpuport.c
View File

@ -194,4 +194,3 @@ void hw_int15_handler(void)
{
}

4
libcpu/ti-dsp/c6x/interrupt.c
View File

@ -26,8 +26,8 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
*/
void rt_hw_interrupt_init(void)
{
// initial system trap
rt_trap_init();
// initial system trap
rt_trap_init();
/* init exceptions table */
rt_memset(isr_table, 0x00, sizeof(isr_table));

16
libcpu/ti-dsp/c6x/intexc.asm
View File

@ -9,11 +9,11 @@
;
;-----------------------------------------------------------
; interrupt and execption handler for C6000 DSP
; interrupt and execption handler for C6000 DSP
;-----------------------------------------------------------
;-----------------------------------------------------------
; macro definition
; macro definition
;-----------------------------------------------------------
DP .set B14
SP .set B15
@ -22,7 +22,7 @@ SP .set B15
;
.include "contextinc.asm"
;-----------------------------------------------------------
; global function
; global function
;-----------------------------------------------------------
.global _nmi_handler
.global _bad_handler
@ -43,7 +43,7 @@ SP .set B15
;
;-----------------------------------------------------------
; extern function
; extern function
;-----------------------------------------------------------
.ref hw_nmi_handler
.ref hw_bad_handler
@ -66,7 +66,7 @@ SP .set B15
;
;-----------------------------------------------------------
; extern variable
; extern variable
;-----------------------------------------------------------
.ref rt_system_stack_top
;
@ -74,7 +74,7 @@ SP .set B15
;
;-----------------------------------------------------------
; interrupt macro definition
; interrupt macro definition
;-----------------------------------------------------------
RT_INTERRUPT_ENTRY .macro
SAVE_ALL IRP,ITSR
@ -86,7 +86,7 @@ RT_CALL_INT .macro __isr
NOP 5
.endm
;-----------------------------------------------------------
; execption macro definition
; execption macro definition
;-----------------------------------------------------------
RT_EXECPTION_ENTRY .macro
SAVE_ALL NRP,NTSR
@ -94,7 +94,7 @@ RT_EXECPTION_ENTRY .macro
RT_EXECPTION_EXIT .macro
RESTORE_ALL NRP,NTSR
B .S2 NRP ; return from execption
B .S2 NRP ; return from execption
NOP 5
.endm

88
libcpu/ti-dsp/c6x/stack.asm
View File

@ -35,73 +35,73 @@ ADDRESS_MSK .set 0xFFFFFFF0
;{
.global rt_hw_stack_init
rt_hw_stack_init:
SUB A6,1,B1 ;
MVKL .S1 ADDRESS_MSK,A1 ;
MVKH .S1 ADDRESS_MSK,A1 ; Build address mask
MVC .S2 CSR,B0 ;
AND -2,B0,B0 ; Clear GIE bit
OR 2,B0,B0 ; Set PGIE bit for interrupt return
AND A1,B1,B1 ; Ensure alignment
SUB A6,1,B1 ;
MVKL .S1 ADDRESS_MSK,A1 ;
MVKH .S1 ADDRESS_MSK,A1 ; Build address mask
MVC .S2 CSR,B0 ;
AND -2,B0,B0 ; Clear GIE bit
OR 2,B0,B0 ; Set PGIE bit for interrupt return
AND A1,B1,B1 ; Ensure alignment
;
; Actually build the stack frame.
;
MV .S1 B1,A3
MV .S1 B14,A2
STDW .D2T1 A3:A2,*--B1[1] ; Initial B15:B14
STDW .D2T1 A3:A2,*--B1[1] ; Initial B15:B14
SUBAW .D2 B1,2,B1
ZERO A2
ZERO A3 ; Clear value
STDW .D2T1 A3:A2,*B1--[1] ; Initial A15:A14
STDW .D2T1 A3:A2,*B1--[1] ; Initial A13:A12
STDW .D2T1 A3:A2,*B1--[1] ; Initial A11:A10
STDW .D2T1 A3:A2,*B1--[1] ; Initial A9:A8
STDW .D2T1 A3:A2,*B1--[1] ; Initial A7:A6
ZERO A3 ; Clear value
STDW .D2T1 A3:A2,*B1--[1] ; Initial A15:A14
STDW .D2T1 A3:A2,*B1--[1] ; Initial A13:A12
STDW .D2T1 A3:A2,*B1--[1] ; Initial A11:A10
STDW .D2T1 A3:A2,*B1--[1] ; Initial A9:A8
STDW .D2T1 A3:A2,*B1--[1] ; Initial A7:A6
MV .S1 B4,A2
STDW .D2T1 A3:A2,*B1--[1] ; Initial A5:A4
STDW .D2T1 A3:A2,*B1--[1] ; Initial A5:A4
ZERO A2
STDW .D2T1 A3:A2,*B1--[1] ; Initial A3:A2
STDW .D2T1 A3:A2,*B1--[1] ; Initial A1:A0
STDW .D2T1 A3:A2,*B1--[1] ; Initial A3:A2
STDW .D2T1 A3:A2,*B1--[1] ; Initial A1:A0
STDW .D2T1 A3:A2,*B1--[1] ; Initial A31:A30
STDW .D2T1 A3:A2,*B1--[1] ; Initial A29:A28
STDW .D2T1 A3:A2,*B1--[1] ; Initial A27:A26
STDW .D2T1 A3:A2,*B1--[1] ; Initial A25:A24
STDW .D2T1 A3:A2,*B1--[1] ; Initial A23:A22
STDW .D2T1 A3:A2,*B1--[1] ; Initial A21:A20
STDW .D2T1 A3:A2,*B1--[1] ; Initial A19:A18
STDW .D2T1 A3:A2,*B1--[1] ; Initial A17:A16
STDW .D2T1 A3:A2,*B1--[1] ; Initial A31:A30
STDW .D2T1 A3:A2,*B1--[1] ; Initial A29:A28
STDW .D2T1 A3:A2,*B1--[1] ; Initial A27:A26
STDW .D2T1 A3:A2,*B1--[1] ; Initial A25:A24
STDW .D2T1 A3:A2,*B1--[1] ; Initial A23:A22
STDW .D2T1 A3:A2,*B1--[1] ; Initial A21:A20
STDW .D2T1 A3:A2,*B1--[1] ; Initial A19:A18
STDW .D2T1 A3:A2,*B1--[1] ; Initial A17:A16
STDW .D2T1 A3:A2,*B1--[1] ; Initial B13:B12
STDW .D2T1 A3:A2,*B1--[1] ; Initial B11:B10
STDW .D2T1 A3:A2,*B1--[1] ; Initial B9:B8
STDW .D2T1 A3:A2,*B1--[1] ; Initial B7:B6
STDW .D2T1 A3:A2,*B1--[1] ; Initial B5:B4
STDW .D2T1 A3:A2,*B1--[1] ; Initial B13:B12
STDW .D2T1 A3:A2,*B1--[1] ; Initial B11:B10
STDW .D2T1 A3:A2,*B1--[1] ; Initial B9:B8
STDW .D2T1 A3:A2,*B1--[1] ; Initial B7:B6
STDW .D2T1 A3:A2,*B1--[1] ; Initial B5:B4
MV .S1 B6,A3
STDW .D2T1 A3:A2,*B1--[1] ; Initial B3:B2
STDW .D2T1 A3:A2,*B1--[1] ; Initial B3:B2
ZERO A3
STDW .D2T1 A3:A2,*B1--[1] ; Initial B1:B0
STDW .D2T1 A3:A2,*B1--[1] ; Initial B1:B0
STDW .D2T1 A3:A2,*B1--[1] ; Initial B31:B30
STDW .D2T1 A3:A2,*B1--[1] ; Initial B29:B28
STDW .D2T1 A3:A2,*B1--[1] ; Initial B27:B26
STDW .D2T1 A3:A2,*B1--[1] ; Initial B25:B24
STDW .D2T1 A3:A2,*B1--[1] ; Initial B23:B22
STDW .D2T1 A3:A2,*B1--[1] ; Initial B21:B20
STDW .D2T1 A3:A2,*B1--[1] ; Initial B19:B18
STDW .D2T1 A3:A2,*B1--[1] ; Initial B17:B16
STDW .D2T1 A3:A2,*B1--[1] ; Initial B31:B30
STDW .D2T1 A3:A2,*B1--[1] ; Initial B29:B28
STDW .D2T1 A3:A2,*B1--[1] ; Initial B27:B26
STDW .D2T1 A3:A2,*B1--[1] ; Initial B25:B24
STDW .D2T1 A3:A2,*B1--[1] ; Initial B23:B22
STDW .D2T1 A3:A2,*B1--[1] ; Initial B21:B20
STDW .D2T1 A3:A2,*B1--[1] ; Initial B19:B18
STDW .D2T1 A3:A2,*B1--[1] ; Initial B17:B16
MV .S1 A4,A3
MV .S1 B0,A2
STDW .D2T1 A3:A2,*B1--[1] ; Initial PC:CSR
STDW .D2T1 A3:A2,*B1--[1] ; Initial PC:CSR
ZERO A2
ZERO A3
STDW .D2T1 A3:A2,*B1--[1] ; Initial ILC:RILC
STDW .D2T1 A3:A2,*B1--[1] ; Initial ILC:RILC
B B3
MVKL .S2 0x3,B0
MV .S1 B0,A3
MVKL .S1 1,A2
STDW .D2T1 A3:A2,*B1--[1] ; Initial TSR:stack type
MV .S1 B1,A4 ; Save to TCB
STDW .D2T1 A3:A2,*B1--[1] ; Initial TSR:stack type
MV .S1 B1,A4 ; Save to TCB
;}
.end

12
libcpu/ti-dsp/c6x/trap.c
View File

@ -333,26 +333,26 @@ int rt_hw_process_exception(struct rt_hw_exp_stack_register *regs)
type_num = __fls(type) - 1;
switch(type_num) {
case EXCEPT_TYPE_NXF: /* NMI exception */
ack_exception(EXCEPT_TYPE_NXF); /* clear exception */
case EXCEPT_TYPE_NXF: /* NMI exception */
ack_exception(EXCEPT_TYPE_NXF); /* clear exception */
if (hw_nmi_handler != RT_NULL)
hw_nmi_handler(regs);
break;
case EXCEPT_TYPE_IXF: /* internal exception */
case EXCEPT_TYPE_IXF: /* internal exception */
if (process_iexcept(regs))
return 1;
break;
case EXCEPT_TYPE_EXC: /* external exception */
case EXCEPT_TYPE_EXC: /* external exception */
process_except(regs);
break;
case EXCEPT_TYPE_SXF: /* software exception */
case EXCEPT_TYPE_SXF: /* software exception */
ie_num = 8;
ack_exception(type_num);
break;
default: /* clear exception */
default: /* clear exception */
ack_exception(type_num);
do_trap(&iexcept_table[ie_num], regs);
break;

28
libcpu/ti-dsp/c6x/trap.h
View File

@ -41,30 +41,30 @@
enum SYSTEM_TRAP_CODE
{
ABORT_BUS_ADDRERR = 0, // bus address error
ABORT_BUS_ACCERR, // bus access permission error
ABORT_OPCODE_ILL, // illegal opcode
ABORT_PRVREG_ILL, // privilege register
ABORT_PRVOPC_ILL, // privileged opcode
ABORT_ILLTRP_ILL, // illegal trap
ABORT_BRKPT_ILL, // handling breakpoints
ABORT_BUS_ADDRERR = 0, // bus address error
ABORT_BUS_ACCERR, // bus access permission error
ABORT_OPCODE_ILL, // illegal opcode
ABORT_PRVREG_ILL, // privilege register
ABORT_PRVOPC_ILL, // privileged opcode
ABORT_ILLTRP_ILL, // illegal trap
ABORT_BRKPT_ILL, // handling breakpoints
};
/*
* abort types
*/
#define ABORT_TYPE_BUS 0 // bus access abnormal
#define ABORT_TYPE_MAP 1 // page table mapping error
#define ABORT_TYPE_UNDDEF 0xff // undefined exception
#define ABORT_TYPE_FATAL 0xffffffff // fatal error
#define ABORT_TYPE_BUS 0 // bus access abnormal
#define ABORT_TYPE_MAP 1 // page table mapping error
#define ABORT_TYPE_UNDDEF 0xff // undefined exception
#define ABORT_TYPE_FATAL 0xffffffff // fatal error
struct rt_exception_info {
char *kernel_str;
int type;
int code;
int type;
int code;
};
#define BKPT_OPCODE 0x56454314 /* illegal opcode */
#define BKPT_OPCODE 0x56454314 /* illegal opcode */
#define INTC_MEXPMASK __SYSREGA(0x018000e0, unsigned int)
#define __ffs(a) (_lmbd(1, _bitr(a)))