Merge pull request #1427 from qgyhd1234/eth_fire
[驱动]：添加野火1052 drv_eth.c 和phy.c 文件
This commit is contained in:
Tanek
GitHub
commit
275ce5ddf1
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@ -7,9 +7,6 @@ from building import *
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cwd = GetCurrentDir()
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src = Glob('drivers/*.c')
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if GetDepend('BOARD_RT1050_FIRE'):
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SrcRemove(src, r'drivers\fsl_enet.c')
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SrcRemove(src, 'drivers/dataqueue.c')
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src += Glob('common/chip/*.c')
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src += [cwd + '/system_MIMXRT1052.c']
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@ -61,6 +61,9 @@ if GetDepend('BOARD_RT1050_EVK') or GetDepend('BOARD_RT1050_SeeedStudio'):
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src += ['drv_eth.c', 'fsl_phy.c']
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CPPDEFINES += ['FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE']
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if GetDepend('BOARD_RT1050_FIRE') and GetDepend('RT_USING_LWIP'):
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src += ['drv_eth_fire.c', 'fsl_phy_fire.c']
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if GetDepend('RT_USING_AUDIO'):
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src += ['drv_codec.c', 'fsl_wm8960.c']
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,338 @@
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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||||
* list of conditions and the following disclaimer in the documentation and/or
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||||
* other materials provided with the distribution.
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||||
*
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||||
* o Neither the name of the copyright holder nor the names of its
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||||
* contributors may be used to endorse or promote products derived from this
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||||
* software without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_phy_fire.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief Defines the timeout macro. */
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#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get the ENET instance from peripheral base address.
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*
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* @param base ENET peripheral base address.
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* @return ENET instance.
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*/
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extern uint32_t ENET_GetInstance(ENET_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to enet clocks for each instance. */
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extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
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{
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uint32_t bssReg;
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uint32_t counter = PHY_TIMEOUT_COUNT;
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uint32_t idReg = 0;
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status_t result = kStatus_Success;
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uint32_t instance = ENET_GetInstance(base);
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uint32_t timeDelay;
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// uint32_t ctlReg = 0;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Set SMI first. */
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CLOCK_EnableClock(s_enetClock[instance]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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ENET_SetSMI(base, srcClock_Hz, false);
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/* Initialization after PHY stars to work. */
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while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
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{
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PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
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counter --;
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}
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if (!counter)
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{
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return kStatus_Fail;
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}
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/* Reset PHY. */
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counter = PHY_TIMEOUT_COUNT;
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result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
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if (result == kStatus_Success)
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{
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//#if 0//defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
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// uint32_t data = 0;
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// result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
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// if ( result != kStatus_Success)
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// {
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// return result;
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// }
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// result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK));
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// if (result != kStatus_Success)
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// {
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// return result;
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// }
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//#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */
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/* Set the negotiation. */
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result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
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(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
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PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
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if (result == kStatus_Success)
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{
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result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
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(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
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if (result == kStatus_Success)
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{
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/* Check auto negotiation complete. */
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while (counter --)
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{
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result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
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if ( result == kStatus_Success)
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{
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//PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &ctlReg);&& (ctlReg & PHY_LINK_READY_MASK)
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if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) )
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{
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/* Wait a moment for Phy status stable. */
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for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++)
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{
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__ASM("nop");
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}
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break;
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}
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}
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if (!counter)
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{
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return kStatus_PHY_AutoNegotiateFail;
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}
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}
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}
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}
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}
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return result;
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}
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status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
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{
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uint32_t counter;
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/* Clear the SMI interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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/* Starts a SMI write command. */
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ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
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/* Wait for SMI complete. */
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for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
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{
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if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
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{
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break;
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}
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}
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/* Check for timeout. */
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if (!counter)
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{
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return kStatus_PHY_SMIVisitTimeout;
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}
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/* Clear MII interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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return kStatus_Success;
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}
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status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
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{
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assert(dataPtr);
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uint32_t counter;
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/* Clear the MII interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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/* Starts a SMI read command operation. */
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ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
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/* Wait for MII complete. */
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for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
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{
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if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
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{
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break;
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}
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}
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/* Check for timeout. */
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if (!counter)
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{
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return kStatus_PHY_SMIVisitTimeout;
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}
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/* Get data from MII register. */
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*dataPtr = ENET_ReadSMIData(base);
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/* Clear MII interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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return kStatus_Success;
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}
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status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable)
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{
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status_t result;
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uint32_t data = 0;
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/* Set the loop mode. */
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if (enable)
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{
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if (mode == kPHY_LocalLoop)
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{
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if (speed == kPHY_Speed100M)
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{
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data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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}
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else
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{
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data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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}
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return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data);
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}
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else
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{
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/* First read the current status in control register. */
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result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
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if (result == kStatus_Success)
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{
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return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK));
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}
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}
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}
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else
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{
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/* Disable the loop mode. */
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if (mode == kPHY_LocalLoop)
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{
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/* First read the current status in control register. */
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result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data);
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if (result == kStatus_Success)
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{
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data &= ~PHY_BCTL_LOOP_MASK;
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return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK));
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}
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}
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else
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{
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/* First read the current status in control one register. */
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result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
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if (result == kStatus_Success)
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{
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return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK));
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}
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}
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}
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return result;
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}
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status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
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{
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assert(status);
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status_t result = kStatus_Success;
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uint32_t data;
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/* Read the basic status register. */
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result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data);
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if (result == kStatus_Success)
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{
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if (!(PHY_BSTATUS_LINKSTATUS_MASK & data))
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{
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/* link down. */
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*status = false;
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}
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else
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{
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/* link up. */
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*status = true;
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}
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}
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return result;
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}
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status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
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{
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assert(duplex);
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status_t result = kStatus_Success;
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uint32_t data, ctlReg;
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/* Read the control two register. */
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result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &ctlReg);
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if (result == kStatus_Success)
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{
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data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
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if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
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{
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/* Full duplex. */
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*duplex = kPHY_FullDuplex;
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}
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else
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{
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/* Half duplex. */
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*duplex = kPHY_HalfDuplex;
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}
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data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
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if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
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{
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/* 100M speed. */
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*speed = kPHY_Speed100M;
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}
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else
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{ /* 10M speed. */
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*speed = kPHY_Speed10M;
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}
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}
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return result;
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}
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@ -0,0 +1,222 @@
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
|
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*
|
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* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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#ifndef _FSL_PHY_FIRE_H_
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#define _FSL_PHY_FIRE_H_
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#include "fsl_enet.h"
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/*!
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* @addtogroup phy_driver
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* @{
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*/
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/*******************************************************************************
|
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* Definitions
|
||||
******************************************************************************/
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/*! @brief PHY driver version */
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#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
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/*! @brief Defines the PHY registers. */
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#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
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#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
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#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
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#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
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#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
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#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */
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#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */
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#define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/
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/*! @brief Defines the mask flag in basic control register. */
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#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
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#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
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#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
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#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */
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#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
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#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
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#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */
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/*!@brief Defines the mask flag of operation mode in control two register*/
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#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
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#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
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#define PHY_CTL1_10HALFDUPLEX_MASK 0x0004U /*!< The PHY 10M half duplex mask. */
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#define PHY_CTL1_100HALFDUPLEX_MASK 0x0008U /*!< The PHY 100M half duplex mask. */
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#define PHY_CTL1_10FULLDUPLEX_MASK 0x0014U /*!< The PHY 10M full duplex mask. */
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#define PHY_CTL1_100FULLDUPLEX_MASK 0x0018U /*!< The PHY 100M full duplex mask. */
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#define PHY_CTL1_SPEEDUPLX_MASK 0x001CU /*!< The PHY speed and duplex mask. */
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#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */
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#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */
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#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
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/*! @brief Defines the mask flag in basic status register. */
|
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#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
|
||||
#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
|
||||
#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
|
||||
|
||||
/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
|
||||
#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */
|
||||
#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
|
||||
#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
|
||||
#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/
|
||||
#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/
|
||||
|
||||
/*! @brief Defines the PHY status. */
|
||||
enum _phy_status
|
||||
{
|
||||
kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */
|
||||
kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */
|
||||
};
|
||||
|
||||
/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
|
||||
typedef enum _phy_speed
|
||||
{
|
||||
kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
|
||||
kPHY_Speed100M /*!< ENET PHY 100M speed. */
|
||||
} phy_speed_t;
|
||||
|
||||
/*! @brief Defines the PHY link duplex. */
|
||||
typedef enum _phy_duplex
|
||||
{
|
||||
kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
|
||||
kPHY_FullDuplex /*!< ENET PHY full duplex. */
|
||||
} phy_duplex_t;
|
||||
|
||||
/*! @brief Defines the PHY loopback mode. */
|
||||
typedef enum _phy_loop
|
||||
{
|
||||
kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */
|
||||
kPHY_RemoteLoop /*!< ENET PHY remote loopback. */
|
||||
} phy_loop_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name PHY Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes PHY.
|
||||
*
|
||||
* This function initialize the SMI interface and initialize PHY.
|
||||
* The SMI is the MII management interface between PHY and MAC, which should be
|
||||
* firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
|
||||
* @retval kStatus_Success PHY initialize success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
* @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
|
||||
*/
|
||||
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
|
||||
|
||||
/*!
|
||||
* @brief PHY Write function. This function write data over the SMI to
|
||||
* the specified PHY register. This function is called by all PHY interfaces.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param phyReg The PHY register.
|
||||
* @param data The data written to the PHY register.
|
||||
* @retval kStatus_Success PHY write success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
|
||||
|
||||
/*!
|
||||
* @brief PHY Read function. This interface read data over the SMI from the
|
||||
* specified PHY register. This function is called by all PHY interfaces.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param phyReg The PHY register.
|
||||
* @param dataPtr The address to store the data read from the PHY register.
|
||||
* @retval kStatus_Success PHY read success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
|
||||
|
||||
/*!
|
||||
* @brief Enables/disables PHY loopback.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param mode The loopback mode to be enabled, please see "phy_loop_t".
|
||||
* the two loopback mode should not be both set. when one loopback mode is set
|
||||
* the other one should be disabled.
|
||||
* @param speed PHY speed for loopback mode.
|
||||
* @param enable True to enable, false to disable.
|
||||
* @retval kStatus_Success PHY loopback success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable);
|
||||
|
||||
/*!
|
||||
* @brief Gets the PHY link status.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param status The link up or down status of the PHY.
|
||||
* - true the link is up.
|
||||
* - false the link is down.
|
||||
* @retval kStatus_Success PHY get link status success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
|
||||
|
||||
/*!
|
||||
* @brief Gets the PHY link speed and duplex.
|
||||
*
|
||||
* @param base ENET peripheral base address.
|
||||
* @param phyAddr The PHY address.
|
||||
* @param speed The address of PHY link speed.
|
||||
* @param duplex The link duplex of PHY.
|
||||
* @retval kStatus_Success PHY get link speed and duplex success
|
||||
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||
*/
|
||||
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_PHY_H_ */
|
||||
Loading…
Reference in New Issue