[wch][spi] 修改ch32 risc-v spi底层驱动函数返回值类型 (#6979)
* [wch][spi] 修改ch32 risc-v spi底层驱动函数返回值类型 --------- Co-authored-by: Zxy <1308465141@qq.com> Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
This commit is contained in:
liYangYang
GitHub
parent
dfad527019
commit
26fab3e792
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@ -28,12 +28,12 @@
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struct ch32v307x_can_baud_info
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{
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uint32_t baud_rate;
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uint16_t prescaler;
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uint8_t tsjw; //CAN synchronisation jump width.
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uint8_t tbs1; //CAN time quantum in bit segment 1.
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uint8_t tbs2; //CAN time quantum in bit segment 2.
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uint8_t notused;
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rt_uint32_t baud_rate;
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rt_uint16_t prescaler;
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rt_uint8_t tsjw; //CAN synchronisation jump width.
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rt_uint8_t tbs1; //CAN time quantum in bit segment 1.
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rt_uint8_t tbs2; //CAN time quantum in bit segment 2.
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rt_uint8_t notused;
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};
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#define CH32V307X_CAN_BAUD_DEF(xrate, xsjw, xbs1, xbs2, xprescale) \
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@ -165,7 +165,7 @@ rt_weak void ch32v307x_can_gpio_init(CAN_TypeDef *can_base)
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static uint32_t get_can_baud_index(rt_uint32_t baud)
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{
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uint32_t len, index;
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rt_uint32_t len, index;
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len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]);
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for (index = 0; index < len; index++)
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@ -176,9 +176,9 @@ static uint32_t get_can_baud_index(rt_uint32_t baud)
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return 0; /* default baud is CAN1MBaud */
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}
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static uint8_t get_can_mode_rtt2n32(uint8_t rtt_can_mode)
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static rt_uint8_t get_can_mode_rtt2n32(rt_uint8_t rtt_can_mode)
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{
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uint8_t mode = CAN_Mode_Normal;
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rt_uint8_t mode = CAN_Mode_Normal;
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switch (rtt_can_mode)
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{
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case RT_CAN_MODE_NORMAL:
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@ -558,9 +558,9 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
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}
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/* CAN Mailbox Transmit Request */
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#define TMIDxR_TXRQ ((uint32_t)0x00000001)
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#define TMIDxR_TXRQ ((rt_uint32_t)0x00000001)
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static int _can_send_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, uint32_t mailbox_index)
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static int _can_send_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, rt_uint32_t mailbox_index)
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{
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CanTxMsg CAN_TxMessage = {0};
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CanTxMsg *TxMessage = &CAN_TxMessage;
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@ -629,20 +629,20 @@ static int _can_send_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, uint3
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/* Set DLC */
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TxMessage->DLC = pmsg->len & 0x0FU;
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can_base->sTxMailBox[mailbox_index].TXMDTR &= (uint32_t)0xFFFFFFF0;
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can_base->sTxMailBox[mailbox_index].TXMDTR &= (rt_uint32_t)0xFFFFFFF0;
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can_base->sTxMailBox[mailbox_index].TXMDTR |= TxMessage->DLC;
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/* Set data */
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can_base->sTxMailBox[mailbox_index].TXMDHR =
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(((uint32_t)pmsg->data[7] << 24) |
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((uint32_t)pmsg->data[6] << 16) |
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((uint32_t)pmsg->data[5] << 8) |
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((uint32_t)pmsg->data[4]));
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(((rt_uint32_t)pmsg->data[7] << 24) |
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((rt_uint32_t)pmsg->data[6] << 16) |
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((rt_uint32_t)pmsg->data[5] << 8) |
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((rt_uint32_t)pmsg->data[4]));
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can_base->sTxMailBox[mailbox_index].TXMDLR =
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(((uint32_t)pmsg->data[3] << 24) |
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((uint32_t)pmsg->data[2] << 16) |
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((uint32_t)pmsg->data[1] << 8) |
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((uint32_t)pmsg->data[0]));
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(((rt_uint32_t)pmsg->data[3] << 24) |
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((rt_uint32_t)pmsg->data[2] << 16) |
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((rt_uint32_t)pmsg->data[1] << 8) |
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((rt_uint32_t)pmsg->data[0]));
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/* Request transmission */
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can_base->sTxMailBox[mailbox_index].TXMIR |= TMIDxR_TXRQ;
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@ -665,7 +665,7 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t
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return _can_send_rtmsg(drv_can_obj->can_base, ((struct rt_can_msg *)buf), box_num);
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}
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static int _can_recv_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, uint32_t FIFONum)
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static int _can_recv_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, rt_uint32_t FIFONum)
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{
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CanRxMsg CAN_RxMessage = {0};
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CanRxMsg *RxMessage = &CAN_RxMessage;
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@ -676,30 +676,30 @@ static int _can_recv_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, uint3
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return -RT_ERROR;
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}
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/* Get the Id */
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RxMessage->IDE = (uint8_t)(0x04 & can_base->sFIFOMailBox[FIFONum].RXMIR);
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RxMessage->IDE = (rt_uint8_t)(0x04 & can_base->sFIFOMailBox[FIFONum].RXMIR);
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if (RxMessage->IDE == CAN_Id_Standard)
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{
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RxMessage->StdId = (uint32_t)0x000007FF & (can_base->sFIFOMailBox[FIFONum].RXMIR >> 21);
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RxMessage->StdId = (rt_uint32_t)0x000007FF & (can_base->sFIFOMailBox[FIFONum].RXMIR >> 21);
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}
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else
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{
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RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (can_base->sFIFOMailBox[FIFONum].RXMIR >> 3);
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RxMessage->ExtId = (rt_uint32_t)0x1FFFFFFF & (can_base->sFIFOMailBox[FIFONum].RXMIR >> 3);
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}
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RxMessage->RTR = (uint8_t)0x02 & can_base->sFIFOMailBox[FIFONum].RXMIR;
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RxMessage->RTR = (rt_uint8_t)0x02 & can_base->sFIFOMailBox[FIFONum].RXMIR;
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/* Get the DLC */
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RxMessage->DLC = (uint8_t)0x0F & can_base->sFIFOMailBox[FIFONum].RXMDTR;
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RxMessage->DLC = (rt_uint8_t)0x0F & can_base->sFIFOMailBox[FIFONum].RXMDTR;
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/* Get the FMI */
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RxMessage->FMI = (uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDTR >> 8);
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RxMessage->FMI = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDTR >> 8);
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/* Get the data field */
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pmsg->data[0] = (uint8_t)0xFF & can_base->sFIFOMailBox[FIFONum].RXMDLR;
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pmsg->data[1] = (uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 8);
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pmsg->data[2] = (uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 16);
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pmsg->data[3] = (uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 24);
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pmsg->data[4] = (uint8_t)0xFF & can_base->sFIFOMailBox[FIFONum].RXMDHR;
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pmsg->data[5] = (uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 8);
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pmsg->data[6] = (uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 16);
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pmsg->data[7] = (uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 24);
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pmsg->data[0] = (rt_uint8_t)0xFF & can_base->sFIFOMailBox[FIFONum].RXMDLR;
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pmsg->data[1] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 8);
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pmsg->data[2] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 16);
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pmsg->data[3] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 24);
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pmsg->data[4] = (rt_uint8_t)0xFF & can_base->sFIFOMailBox[FIFONum].RXMDHR;
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pmsg->data[5] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 8);
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pmsg->data[6] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 16);
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pmsg->data[7] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 24);
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/* get len */
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pmsg->len = RxMessage->DLC;
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@ -106,7 +106,7 @@ static rt_uint32_t ch32_dac_get_channel(rt_uint32_t channel)
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static rt_err_t ch32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
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{
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uint32_t dac_channel;
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rt_uint32_t dac_channel;
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DAC_HandleTypeDef *ch32_dac_handler;
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RT_ASSERT(device != RT_NULL);
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@ -13,11 +13,11 @@
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#ifdef BSP_USING_GPIO
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#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
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#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
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#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
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#define PIN_PORT(pin) ((rt_uint8_t)(((pin) >> 4) & 0xFu))
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#define PIN_NO(pin) ((rt_uint8_t)((pin) & 0xFu))
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#define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
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#define PIN_STPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
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#define PIN_STPIN(pin) ((rt_uint16_t)(1u << PIN_NO(pin)))
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#if defined(GPIOZ)
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#define __CH32_PORT_MAX 12u
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@ -89,7 +89,7 @@ static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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static uint32_t pin_irq_enable_mask = 0;
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static rt_uint32_t pin_irq_enable_mask = 0;
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#define ITEM_NUM(items) (sizeof(items) / sizeof((items)[0]))
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@ -133,7 +133,7 @@ static rt_base_t ch32_pin_get(const char *name)
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static void ch32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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GPIO_TypeDef *gpio_port;
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uint16_t gpio_pin;
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rt_uint16_t gpio_pin;
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if (PIN_PORT(pin) < PIN_STPORT_MAX)
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{
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@ -146,7 +146,7 @@ static void ch32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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static int ch32_pin_read(rt_device_t dev, rt_base_t pin)
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{
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GPIO_TypeDef *gpio_port;
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uint16_t gpio_pin;
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rt_uint16_t gpio_pin;
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int value = PIN_LOW;
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if (PIN_PORT(pin) < PIN_STPORT_MAX)
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@ -215,7 +215,7 @@ rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
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return -1;
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}
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rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
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rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit)
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{
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rt_int32_t mapindex = bit2bitno(pinbit);
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if (mapindex < 0 || mapindex >= (rt_int32_t)ITEM_NUM(pin_irq_map))
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@ -426,7 +426,7 @@ rt_inline void pin_irq_hdr(int irqno)
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}
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}
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void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
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void HAL_GPIO_EXTI_Callback(rt_uint16_t GPIO_Pin)
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{
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pin_irq_hdr(bit2bitno(GPIO_Pin));
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}
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@ -210,12 +210,12 @@ static rt_err_t ch32_hwtimer_start(struct rt_hwtimer_device *timer, rt_uint32_t
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if (mode == HWTIMER_MODE_ONESHOT)
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{
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/* set timer to single mode */
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tim->instance->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM);
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tim->instance->CTLR1 &= (rt_uint16_t) ~((rt_uint16_t)TIM_OPM);
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tim->instance->CTLR1 |= TIM_OPMode_Single;
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}
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else
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{
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tim->instance->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM);
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tim->instance->CTLR1 &= (rt_uint16_t) ~((rt_uint16_t)TIM_OPM);
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tim->instance->CTLR1 |= TIM_OPMode_Repetitive;
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}
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@ -302,12 +302,12 @@ static rt_err_t ch32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_
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if (*(rt_hwtimer_mode_t *)args == HWTIMER_MODE_ONESHOT)
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{
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/* set timer to single mode */
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tim->instance->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM);
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tim->instance->CTLR1 &= (rt_uint16_t) ~((rt_uint16_t)TIM_OPM);
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tim->instance->CTLR1 |= TIM_OPMode_Single;
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}
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else
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{
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tim->instance->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM);
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tim->instance->CTLR1 &= (rt_uint16_t) ~((rt_uint16_t)TIM_OPM);
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tim->instance->CTLR1 |= TIM_OPMode_Repetitive;
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}
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break;
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@ -66,9 +66,9 @@ static struct ch32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] =
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static rt_uint32_t ch32_spi_clock_get(SPI_TypeDef *spix);
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static void ch32_spi_clock_and_io_init(SPI_TypeDef *spix);
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static rt_uint8_t spix_readwritebyte(SPI_TypeDef *Instance, rt_uint8_t TxData);
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static rt_err_t spi_transmitreceive(SPI_TypeDef *Instance, uint8_t *send_buf, uint8_t *recv_buf, uint16_t send_length);
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static rt_err_t spi_transmit(SPI_TypeDef *Instance, uint8_t *send_buf, uint16_t send_length);
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static rt_err_t spi_receive(SPI_TypeDef *Instance, uint8_t *recv_buf,uint16_t send_length);
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static rt_err_t spi_transmitreceive(SPI_TypeDef *Instance, rt_uint8_t *send_buf, rt_uint8_t *recv_buf, rt_uint16_t send_length);
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static rt_err_t spi_transmit(SPI_TypeDef *Instance, rt_uint8_t *send_buf, rt_uint16_t send_length);
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static rt_err_t spi_receive(SPI_TypeDef *Instance, rt_uint8_t *recv_buf,rt_uint16_t send_length);
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static void ch32_spi_clock_and_io_init(SPI_TypeDef *spix)
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{
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@ -168,7 +168,7 @@ static rt_uint32_t ch32_spi_clock_get(SPI_TypeDef *spix)
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* */
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static rt_uint8_t spix_readwritebyte(SPI_TypeDef *Instance, rt_uint8_t TxData)
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{
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uint8_t i=0;
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rt_uint8_t i=0;
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while (SPI_I2S_GetFlagStatus(Instance, SPI_I2S_FLAG_TXE) == RESET)
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{
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i++;
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@ -188,9 +188,9 @@ static rt_uint8_t spix_readwritebyte(SPI_TypeDef *Instance, rt_uint8_t TxData)
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/*
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*spi transmit and receive
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* */
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static rt_err_t spi_transmitreceive(SPI_TypeDef *Instance, uint8_t *send_buf, uint8_t *recv_buf, uint16_t send_length)
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static rt_err_t spi_transmitreceive(SPI_TypeDef *Instance, rt_uint8_t *send_buf, rt_uint8_t *recv_buf, rt_uint16_t send_length)
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{
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uint16_t i=0;
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rt_uint16_t i=0;
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for(i = 0; i < send_length; i++)
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{
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recv_buf[i] = spix_readwritebyte(Instance, send_buf[i]);
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@ -201,9 +201,9 @@ static rt_err_t spi_transmitreceive(SPI_TypeDef *Instance, uint8_t *send_buf, ui
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/*
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*spi transmit
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* */
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static rt_err_t spi_transmit(SPI_TypeDef *Instance, uint8_t *send_buf, uint16_t send_length)
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static rt_err_t spi_transmit(SPI_TypeDef *Instance, rt_uint8_t *send_buf, rt_uint16_t send_length)
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{
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uint16_t i=0;
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rt_uint16_t i=0;
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for(i = 0; i < send_length; i++)
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{
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spix_readwritebyte(Instance, send_buf[i]);
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@ -214,9 +214,9 @@ static rt_err_t spi_transmit(SPI_TypeDef *Instance, uint8_t *send_buf, uint16_t
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/*
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*spi receive
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* */
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static rt_err_t spi_receive(SPI_TypeDef *Instance, uint8_t *recv_buf,uint16_t send_length)
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static rt_err_t spi_receive(SPI_TypeDef *Instance, rt_uint8_t *recv_buf,rt_uint16_t send_length)
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{
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uint16_t i=0;
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rt_uint16_t i=0;
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for(i = 0; i < send_length; i++)
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{
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recv_buf[i] = spix_readwritebyte(Instance, 0xFF); /*发送数据为0xff 此时显示为不发送*/
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@ -285,7 +285,7 @@ static rt_err_t ch32_spi_init(struct ch32_spi *spi_drv, struct rt_spi_configurat
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spi_handle->Init.SPI_NSS = SPI_NSS_Soft;
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//device is not RT_NULL, so spi_bus not need check
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uint32_t SPI_APB_CLOCK;
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rt_uint32_t SPI_APB_CLOCK;
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ch32_spi_clock_and_io_init(spi_handle->Instance);
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SPI_APB_CLOCK = ch32_spi_clock_get(spi_handle->Instance);
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@ -311,7 +311,7 @@ static rt_err_t ch32_spi_init(struct ch32_spi *spi_drv, struct rt_spi_configurat
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}
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else if (cfg->max_hz >= SPI_APB_CLOCK / 64)
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{
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spi_handle->Init.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;
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||||
spi_handle->Init.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;
|
||||
}
|
||||
else if (cfg->max_hz >= SPI_APB_CLOCK / 128)
|
||||
{
|
||||
|
|
@ -322,11 +322,11 @@ static rt_err_t ch32_spi_init(struct ch32_spi *spi_drv, struct rt_spi_configurat
|
|||
/* min prescaler 256 */
|
||||
spi_handle->Init.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256;
|
||||
}
|
||||
LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d",
|
||||
HAL_RCC_GetSysClockFreq(),
|
||||
SPI_APB_CLOCK,
|
||||
cfg->max_hz,
|
||||
spi_handle->Init.SPI_BaudRatePrescaler);
|
||||
LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d",
|
||||
HAL_RCC_GetSysClockFreq(),
|
||||
SPI_APB_CLOCK,
|
||||
cfg->max_hz,
|
||||
spi_handle->Init.SPI_BaudRatePrescaler);
|
||||
|
||||
if (cfg->mode & RT_SPI_MSB)
|
||||
{
|
||||
|
|
@ -342,7 +342,7 @@ static rt_err_t ch32_spi_init(struct ch32_spi *spi_drv, struct rt_spi_configurat
|
|||
|
||||
SPI_Cmd(spi_handle->Instance, ENABLE);
|
||||
|
||||
LOG_D("%s init done", spi_drv->config->bus_name);
|
||||
LOG_D("%s init done", spi_drv->config->bus_name);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
|
@ -358,9 +358,9 @@ static rt_err_t spi_configure(struct rt_spi_device *device,
|
|||
return ch32_spi_init(spi_drv, configuration);
|
||||
}
|
||||
|
||||
static rt_uint32_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
|
||||
static rt_ssize_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
|
||||
{
|
||||
rt_err_t state;
|
||||
rt_err_t state = RT_EOK;
|
||||
rt_size_t message_length, already_send_length;
|
||||
rt_uint16_t send_length;
|
||||
rt_uint8_t *recv_buf;
|
||||
|
|
@ -384,11 +384,11 @@ static rt_uint32_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message
|
|||
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_RESET);
|
||||
}
|
||||
|
||||
LOG_D("%s transfer prepare and start", spi_drv->config->bus_name);
|
||||
LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
|
||||
spi_drv->config->bus_name,
|
||||
(uint32_t)message->send_buf,
|
||||
(uint32_t)message->recv_buf, message->length);
|
||||
LOG_D("%s transfer prepare and start", spi_drv->config->bus_name);
|
||||
LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
|
||||
spi_drv->config->bus_name,
|
||||
(rt_uint32_t)message->send_buf,
|
||||
(rt_uint32_t)message->recv_buf, message->length);
|
||||
|
||||
message_length = message->length;
|
||||
recv_buf = message->recv_buf;
|
||||
|
|
@ -416,12 +416,12 @@ static rt_uint32_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message
|
|||
/* start once data exchange */
|
||||
if (message->send_buf && message->recv_buf)
|
||||
{
|
||||
state = spi_transmitreceive(spi_handle->Instance, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length);
|
||||
state = spi_transmitreceive(spi_handle->Instance, (rt_uint8_t *)send_buf, (rt_uint8_t *)recv_buf, send_length);
|
||||
}
|
||||
else if (message->send_buf)
|
||||
{
|
||||
|
||||
state = spi_transmit(spi_handle->Instance, (uint8_t *)send_buf, send_length);
|
||||
state = spi_transmit(spi_handle->Instance, (rt_uint8_t *)send_buf, send_length);
|
||||
if (message->cs_release && (device->config.mode & RT_SPI_3WIRE))
|
||||
{
|
||||
/* release the CS by disable SPI when using 3 wires SPI */
|
||||
|
|
@ -430,20 +430,20 @@ static rt_uint32_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message
|
|||
}
|
||||
else
|
||||
{
|
||||
memset((uint8_t *)recv_buf, 0xff, send_length);
|
||||
rt_memset((rt_uint8_t *)recv_buf, 0xff, send_length);
|
||||
/* clear the old error flag */
|
||||
SPI_I2S_ClearFlag(spi_handle->Instance, SPI_I2S_FLAG_OVR);
|
||||
state = spi_receive(spi_handle->Instance, (uint8_t *)recv_buf, send_length);
|
||||
state = spi_receive(spi_handle->Instance, (rt_uint8_t *)recv_buf, send_length);
|
||||
}
|
||||
|
||||
if (state != RT_EOK)
|
||||
{
|
||||
LOG_I("spi transfer error : %d", state);
|
||||
LOG_I("spi transfer error : %d", state);
|
||||
message->length = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("%s transfer done", spi_drv->config->bus_name);
|
||||
LOG_D("%s transfer done", spi_drv->config->bus_name);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -456,6 +456,11 @@ static rt_uint32_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message
|
|||
GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_SET);
|
||||
}
|
||||
|
||||
if(state != RT_EOK)
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
return message->length;
|
||||
}
|
||||
|
||||
|
|
@ -478,7 +483,7 @@ static int rt_hw_spi_bus_init(void)
|
|||
result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &ch32_spi_ops);
|
||||
RT_ASSERT(result == RT_EOK);
|
||||
|
||||
LOG_D("%s bus init done", spi_config[i].bus_name);
|
||||
LOG_D("%s bus init done", spi_config[i].bus_name);
|
||||
}
|
||||
|
||||
return result;
|
||||
|
|
@ -487,7 +492,7 @@ static int rt_hw_spi_bus_init(void)
|
|||
/**
|
||||
* Attach the spi device to SPI bus, this function must be used after initialization.
|
||||
*/
|
||||
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin)
|
||||
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, rt_uint16_t cs_gpio_pin)
|
||||
{
|
||||
RT_ASSERT(bus_name != RT_NULL);
|
||||
RT_ASSERT(device_name != RT_NULL);
|
||||
|
|
|
|||
|
|
@ -22,16 +22,10 @@
|
|||
extern "C" {
|
||||
#endif /* ifdef __cplusplus */
|
||||
|
||||
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* ifdef __cplusplus */
|
||||
|
||||
struct ch32_hw_spi_cs
|
||||
{
|
||||
GPIO_TypeDef* GPIOx;
|
||||
uint16_t GPIO_Pin;
|
||||
rt_uint16_t GPIO_Pin;
|
||||
};
|
||||
|
||||
struct ch32_spi_config
|
||||
|
|
@ -56,17 +50,17 @@ typedef struct __SPI_HandleTypeDef
|
|||
|
||||
SPI_InitTypeDef Init; /*!< SPI communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
|
||||
rt_uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
|
||||
rt_uint16_t TxXferSize; /*!< SPI Tx Transfer size */
|
||||
|
||||
volatile uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
|
||||
volatile rt_uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
|
||||
rt_uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< SPI Rx Transfer size */
|
||||
rt_uint16_t RxXferSize; /*!< SPI Rx Transfer size */
|
||||
|
||||
volatile uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
|
||||
volatile rt_uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
|
||||
|
||||
|
||||
} SPI_HandleTypeDef;
|
||||
|
|
@ -82,6 +76,11 @@ struct ch32_spi
|
|||
|
||||
|
||||
};
|
||||
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin);
|
||||
|
||||
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, rt_uint16_t cs_gpio_pin);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* ifdef __cplusplus */
|
||||
|
||||
#endif /*__DRV_SPI_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue