From 26e4c368200f4b2fbd8911fe4f787914f389dab0 Mon Sep 17 00:00:00 2001
From: Ouxiaolong <1576690133@qq.com>
Date: Sun, 8 Aug 2021 07:29:05 +0800
Subject: [PATCH] add stm32f746-st-nucleo

---
 bsp/stm32/libraries/HAL_Drivers/drv_eth.h | 36 +++++++++++------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_eth.h b/bsp/stm32/libraries/HAL_Drivers/drv_eth.h
index 12909d3779..f258a7ac2e 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_eth.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_eth.h
@@ -53,24 +53,6 @@
 #define PHY_Status_FULL_DUPLEX(sr)  ((sr) & PHY_FULL_DUPLEX_MASK)
 #endif /* PHY_USING_LAN8720A */
 
-#ifdef PHY_USING_LAN8742A
-/*  The PHY interrupt source flag register. */
-#define PHY_INTERRUPT_FLAG_REG      0x1DU
-/*  The PHY interrupt mask register. */
-#define PHY_INTERRUPT_MASK_REG      0x1EU
-#define PHY_LINK_DOWN_MASK          (1<<4)
-#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
-
-/*  The PHY status register. */
-#define PHY_Status_REG              0x1FU
-#define PHY_10M_MASK                (1<<2)
-#define PHY_100M_MASK               (1<<3)
-#define PHY_FULL_DUPLEX_MASK        (1<<4)
-#define PHY_Status_SPEED_10M(sr)    ((sr) & PHY_10M_MASK)
-#define PHY_Status_SPEED_100M(sr)   ((sr) & PHY_100M_MASK)
-#define PHY_Status_FULL_DUPLEX(sr)  ((sr) & PHY_FULL_DUPLEX_MASK)
-#endif /* PHY_USING_LAN8742A */
-
 #ifdef PHY_USING_DM9161CEP
 #define PHY_Status_REG              0x11U
 #define PHY_10M_MASK                ((1<<12) || (1<<13))
@@ -107,4 +89,22 @@
 #define PHY_INT_MASK                (1<<5)
 #endif /* PHY_USING_DP83848C */
 
+#ifdef PHY_USING_LAN8742A
+/*  The PHY interrupt source flag register. */
+#define PHY_INTERRUPT_FLAG_REG      0x1DU
+/*  The PHY interrupt mask register. */
+#define PHY_INTERRUPT_MASK_REG      0x1EU
+#define PHY_LINK_DOWN_MASK          (1<<4)
+#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
+
+/*  The PHY status register. */
+#define PHY_Status_REG              0x1FU
+#define PHY_10M_MASK                (1<<2)
+#define PHY_100M_MASK               (1<<3)
+#define PHY_FULL_DUPLEX_MASK        (1<<4)
+#define PHY_Status_SPEED_10M(sr)    ((sr) & PHY_10M_MASK)
+#define PHY_Status_SPEED_100M(sr)   ((sr) & PHY_100M_MASK)
+#define PHY_Status_FULL_DUPLEX(sr)  ((sr) & PHY_FULL_DUPLEX_MASK)
+#endif /* PHY_USING_LAN8742A */
+
 #endif /* __DRV_ETH_H__ */