libs/rt-thread
libs
/
rt-thread
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

[bsp/bluetrum] add flash support

This commit is contained in:
greedyhao 2021-11-30 14:38:51 +08:00
parent ccfb3cb67d
commit 26310fe254
21 changed files with 399 additions and 97 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
bsp/bluetrum/ab32vg1-ab-prougen/.config
View File

@ -23,7 +23,7 @@ CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=512
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=256
CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024
#
# kservice optimization
@ -31,6 +31,9 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=256
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
# CONFIG_RT_USING_ASM_MEMSET is not set
# CONFIG_RT_USING_TINY_FFS is not set
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
@ -76,8 +79,7 @@ CONFIG_RT_USING_DEVICE_OPS=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
CONFIG_RT_VER_NUM=0x40100
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@ -88,6 +90,7 @@ CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
#
# C++ features
@ -117,6 +120,14 @@ CONFIG_FINSH_ARG_MAX=10
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_0 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
#
# Device Drivers
@ -163,10 +174,13 @@ CONFIG_RT_USING_PIN=y
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_USING_LIBC=y
CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_RT_LIBC_USING_FILEIO is not set
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_POSIX is not set
# CONFIG_RT_USING_PTHREADS is not set
#
# Network
@ -304,6 +318,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
# CONFIG_PKG_USING_HM is not set
# CONFIG_PKG_USING_SMALL_MODBUS is not set
#
# security packages
@ -351,6 +366,12 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
# CONFIG_PKG_USING_U8G2 is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
#
# tools packages
#
@ -392,6 +413,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
# CONFIG_PKG_USING_FDT is not set
#
# system packages
@ -405,6 +427,13 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_5_AUX is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
@ -422,7 +451,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
@ -439,6 +467,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
@ -599,12 +628,14 @@ CONFIG_PKG_BLUETRUM_SDK_VER="latest"
# Hardware Drivers Config
#
CONFIG_SOC_AB32VG1=y
# CONFIG_PKG_USING_BLUETRUM_NIMBLE is not set
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_AUDIO is not set
# CONFIG_BSP_USING_SDCARD is not set
# CONFIG_BSP_USING_NIMBLE is not set
#
# On-chip Peripheral Drivers
@ -622,8 +653,5 @@ CONFIG_BSP_UART0_FIFO_SIZE=10
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_IRRX is not set
#
# Board extended module Drivers
#
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
CONFIG_BOARD_BLUETRUM_EVB=y

BIN
bsp/bluetrum/ab32vg1-ab-prougen/.settings/.rtmenus
View File

Binary file not shown.

2
bsp/bluetrum/ab32vg1-ab-prougen/.settings/language.settings.xml
View File

@ -5,7 +5,7 @@
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-309903127852947962" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="530397848961880773" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>

12
bsp/bluetrum/ab32vg1-ab-prougen/.settings/projcfg.ini
View File

@ -1,19 +1,19 @@
#RT-Thread Studio Project Configuration
#Wed Dec 16 14:30:21 CST 2020
#Wed Nov 24 11:34:07 CST 2021
cfg_version=v3.0
board_name=AB32VG1-AB-PROUGEN
example_name=
hardware_adapter=DAP-LINK
project_type=rt-thread
hardware_adapter=ST-LINK
board_base_nano_proj=False
project_type=rt-thread
chip_name=AB32VG1
selected_rtt_version=latest
bsp_version=1.0.0
bsp_version=1.1.0
os_branch=full
output_project_path=D\:/Softwares/RT-ThreadStudio/workspace
output_project_path=D\:\\code\\rt_thread\\studio\\ab32vg1
is_base_example_project=False
is_use_scons_build=True
project_base_bsp=true
project_name=ab32vg1
os_version=latest
bsp_path=repo/Local/Board_Support_Packages/Bluetrum/AB32VG1-AB-PROUGEN/1.0.0
bsp_path=repo/Extract/Board_Support_Packages/Bluetrum/AB32VG1-AB-PROUGEN/1.1.0

6
bsp/bluetrum/ab32vg1-ab-prougen/README.md
View File

@ -70,12 +70,12 @@ ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核
| GPIO | 支持 | PA PB PE PF |
| UART | 支持 | UART0/1/2 |
| SDIO | 支持 | |
| ADC | 支持 | 10bit ADC |
| SPI | 即将支持 | 软件 SPI |
| ADC | 支持 | 10bit SRADC 16bit SDADC |
| SPI | 即将支持 | |
| I2C | 支持 | 软件 I2C |
| RTC | 支持 | |
| WDT | 支持 | |
| FLASH | 即将支持 | 对接 FAL |
| FLASH | 支持 | 对接 FAL |
| TIMER | 支持 | |
| PWM | 支持 | LPWM 的 G1 G2 G3 之间是互斥的，只能三选一 |
| FM receive | 支持 | |

2
bsp/bluetrum/ab32vg1-ab-prougen/applications/blehr_app.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, Bluetrum Development Team
* Copyright (c) 2021-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

29
bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig
View File

@ -1,12 +1,12 @@
menu "Hardware Drivers Config"
config SOC_AB32VG1
bool
menuconfig SOC_AB32VG1
bool "SOC_AB32VG1"
select PKG_USING_BLUETRUM_SDK
default y
config PKG_USING_BLUETRUM_NIMBLE
bool
menuconfig PKG_USING_BLUETRUM_NIMBLE
bool "PKG_USING_BLUETRUM_NIMBLE"
default n
menu "Onboard Peripheral Drivers"
@ -34,6 +34,11 @@ menu "Onboard Peripheral Drivers"
default 24000000
endif
config BSP_USING_NIMBLE
bool "use nimble stack(iot)"
select PKG_USING_BLUETRUM_NIMBLE
default n
endmenu
menu "On-chip Peripheral Drivers"
@ -233,20 +238,10 @@ menu "On-chip Peripheral Drivers"
default n
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
endmenu
choice
prompt "BLE STACK"
default BLE_STACK_USING_NULL
help
Select the ble stack
config BLE_STACK_USING_NULL
bool "not use the ble stack"
config BSP_USING_NIMBLE
bool "use nimble stack(iot)"
select PKG_USING_BLUETRUM_NIMBLE
endchoice
endmenu

4
bsp/bluetrum/ab32vg1-ab-prougen/board/SConscript
View File

@ -8,10 +8,14 @@ board.c
ab32vg1_hal_msp.c
''')
CPPPATH = [cwd]
CPPPATH += [cwd + '/ports']
if GetDepend(['RT_USING_AUDIO']):
src += Glob('ports/audio/drv_sound.c')
if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
src += Glob('ports/on_chip_flash_init.c')
group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH)
objs = [group]

72
bsp/bluetrum/ab32vg1-ab-prougen/board/board.c
View File

@ -68,6 +68,28 @@ void hal_printf(const char *fmt, ...)
}
#endif
RT_SECTION(".irq")
void os_interrupt_enter(void)
{
rt_interrupt_enter();
}
RT_SECTION(".irq")
void os_interrupt_leave(void)
{
rt_interrupt_leave();
}
typedef void (*isr_t)(void);
RT_SECTION(".irq")
isr_t register_isr(int vector, isr_t isr)
{
char buf[8] = {0};
rt_snprintf(buf, sizeof(buf), "sys%d", vector);
rt_isr_handler_t handle = (rt_isr_handler_t)isr;
rt_hw_interrupt_install(vector, handle, RT_NULL, buf);
}
RT_SECTION(".irq.timer")
void timer0_isr(int vector, void *param)
{
@ -94,9 +116,55 @@ void timer0_cfg(uint32_t ticks)
TMR0CON |= BIT(0); // EN
}
void hal_mdelay(uint32_t ms)
uint32_t hal_get_ticks(void)
{
rt_thread_mdelay(ms);
return rt_tick_get();
}
void hal_mdelay(uint32_t nms)
{
rt_thread_mdelay(nms);
}
void hal_udelay(uint32_t nus)
{
rt_hw_us_delay(nus);
}
/**
* The time delay function.
*
* @param us microseconds.
*/
RT_SECTION(".com_text")
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = TMR0PR;
ticks = us * reload / (1000 / RT_TICK_PER_SECOND);
told = TMR0CNT;
while (1)
{
tnow = TMR0CNT;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
void rt_hw_systick_init(void)

43
bsp/bluetrum/ab32vg1-ab-prougen/board/ports/fal_cfg.h Normal file
View File

@ -0,0 +1,43 @@
/*
* Copyright (c) 2006-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 greedyhao first version
*/
#ifndef __FAL_CFG_H__
#define __FAL_CFG_H__
#include <rtthread.h>
#if defined(BSP_USING_ON_CHIP_FLASH)
extern const struct fal_flash_dev ab32_onchip_flash;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&ab32_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "boot", "onchip_flash", 0, 8 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 8 * 1024, 996 * 1024, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", 1004 * 1024, 20 * 1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#else
#define FAL_FLASH_DEV_TABLE { 0 }
#define FAL_PART_TABLE { 0 }
#endif
#endif /* __FAL_CFG_H__ */

21
bsp/bluetrum/ab32vg1-ab-prougen/board/ports/on_chip_flash_init.c Normal file
View File

@ -0,0 +1,21 @@
/*
* Copyright (c) 2006-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 greedyhao first version
*/
#include <rtthread.h>
#include "fal.h"
#if defined(BSP_USING_ON_CHIP_FLASH)
static int rt_hw_on_chip_flash_init(void)
{
fal_init();
return RT_EOK;
}
INIT_COMPONENT_EXPORT(rt_hw_on_chip_flash_init);
#endif

14
bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h
View File

@ -18,7 +18,7 @@
#define IDLE_THREAD_STACK_SIZE 512
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 256
#define RT_TIMER_THREAD_STACK_SIZE 1024
/* kservice optimization */
@ -46,7 +46,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40004
#define RT_VER_NUM 0x40100
/* RT-Thread Components */
@ -91,6 +91,7 @@
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_LIBC_USING_TIME
#define RT_LIBC_DEFAULT_TIMEZONE 8
@ -147,6 +148,9 @@
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
@ -155,6 +159,9 @@
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
@ -186,9 +193,6 @@
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_UART0_FIFO_SIZE 10
/* Board extended module Drivers */
#define BOARD_BLUETRUM_EVB
#endif

2
bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py
View File

@ -40,7 +40,7 @@ if PLATFORM == 'gcc':
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32 -msave-restore'
DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32 -msave-restore -ffunction-sections'
CFLAGS = DEVICE + ' -D_USE_LONG_TIME_T'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds'

3
bsp/bluetrum/libraries/hal_drivers/SConscript
View File

@ -38,6 +38,9 @@ if GetDepend('RT_USING_ADC'):
if GetDepend('BSP_USING_IRRX'):
src += ['drv_irrx.c']
if GetDepend('BSP_USING_ON_CHIP_FLASH'):
src += ['drv_flash.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
objs = [group]

133
bsp/bluetrum/libraries/hal_drivers/drv_flash.c Normal file
View File

@ -0,0 +1,133 @@
/*
* Copyright (c) 2006-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 greedyhao first version
*/
#include "board.h"
#include "drv_flash.h"
#ifdef BSP_USING_ON_CHIP_FLASH
#if defined(PKG_USING_FAL)
#include "fal.h"
#endif
//#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
#if defined(PKG_USING_FAL)
#define AB32_FLASH_START_ADDRESS 0x00000000
#define AB32_FLASH_SIZE (1024 * 1024)
#define AB32_FLASH_PAGE_SIZE (0x1000)
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase(long offset, size_t size);
const struct fal_flash_dev ab32_onchip_flash = {
"onchip_flash",
AB32_FLASH_START_ADDRESS,
AB32_FLASH_SIZE,
AB32_FLASH_PAGE_SIZE,
{NULL, fal_flash_read, fal_flash_write, fal_flash_erase},
256*8
};
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
{
return os_spiflash_read(buf, offset, size);
}
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
{
if (size % 256) {
rt_kprintf("Flash write requires 256 byte alignment\n");
return -1;
}
os_spiflash_program(buf, offset, size);
return 0;
}
static int fal_flash_erase(long offset, size_t size)
{
if (size % 4096) {
rt_kprintf("Flash erase requires 4096 byte alignment\n");
return -1;
}
while (size > 0) {
os_spiflash_erase(offset);
offset += 4096;
size -= 4096;
}
return 0;
}
int fal_ops_test(void)
{
int result;
const struct fal_partition *part_dev = fal_partition_find("param");
uint8_t *data = rt_malloc(256);
int i;
int size = 256;
int addr = 0;
for (int i = 0; i < 256; i++) {
data[i] = i;
}
result = fal_partition_write(part_dev, 0, data, 256);
if (result >= 0)
{
rt_kprintf("Write data success. Start from 0x%08X, size is %ld.\n", addr, size);
rt_kprintf("Write data: ");
for (i = 0; i < size; i++)
{
rt_kprintf("%d ", data[i]);
}
rt_kprintf(".\n");
}
rt_memset(data, 0, 256);
result = fal_partition_read(part_dev, 0, data, 256);
if (result >= 0)
{
rt_kprintf("Read data success. Start from 0x%08X, size is %ld.\n", addr, size);
rt_kprintf("Read data: ");
for (i = 0; i < size; i++)
{
rt_kprintf("%d ", data[i]);
}
rt_kprintf(".\n");
}
result = fal_partition_erase(part_dev, 0, 4096);
if (result >= 0) {
rt_kprintf("Erase data success.\n");
}
rt_memset(data, 0, 256);
result = fal_partition_read(part_dev, 0, data, 256);
if (result >= 0)
{
rt_kprintf("Read data success. Start from 0x%08X, size is %ld.\n", addr, size);
rt_kprintf("Read data: ");
for (i = 0; i < size; i++)
{
rt_kprintf("%d ", data[i]);
}
rt_kprintf(".\n");
}
rt_free(data);
return 0;
}
MSH_CMD_EXPORT(fal_ops_test, "fal_ops_test");
#endif
#endif

42
bsp/bluetrum/libraries/hal_drivers/drv_flash.h Normal file
View File

@ -0,0 +1,42 @@
/*
* Copyright (c) 2006-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-16 greedyhao first version
*/
#ifndef __DRV_FLASH_H__
#define __DRV_FLASH_H__
#include <stdint.h>
/**
* @brief Read a block of data
*
* @param buf output data
* @param addr
* @param len less than 512
* @return uint16_t
*/
uint16_t os_spiflash_read(void *buf, uint32_t addr, uint16_t len);
/**
* @brief Write a block of data
*
* @param buf input data
* @param addr 256 alignment
* @param len 256 alignment
*/
void os_spiflash_program(const void *buf, uint32_t addr, uint16_t len);
/**
* @brief Erases a block of data
*
* @param addr 4k alignment
*/
void os_spiflash_erase(uint32_t addr);
#endif /* __DRV_FLASH_H__ */

6
bsp/bluetrum/libraries/hal_drivers/drv_gpio.c
View File

@ -27,9 +27,9 @@ struct port_info
static const struct port_info port_table[] =
{
{0, 8, 0}, /* PA0-PA7 */
{0, 5, 8}, /* PB0-PB5 */
{0, 5, 8}, /* PB0-PB4 */
{0, 8, 13}, /* PE0-PE7 */
{0, 6, 21}, /* PF0-PF6 */
{0, 6, 21}, /* PF0-PF5 */
};
static const hal_sfr_t port_sfr[] =
@ -56,8 +56,6 @@ static rt_uint8_t _pin_port(rt_uint32_t pin)
#define PORT_SFR(port) (port_sfr[(port)])
#define PIN_NO(pin) (rt_uint8_t)((pin) & 0xFu)
// #define PIN_ABPIN(pin) (rt_uint8_t)(port_table[PIN_PORT(pin)].total_pin + PIN_NO(pin))
static rt_base_t ab32_pin_get(const char *name)
{
rt_base_t pin = 0;

41
bsp/bluetrum/libraries/hal_drivers/drv_soft_i2c.c
View File

@ -142,41 +142,6 @@ static rt_int32_t ab32_get_scl(void *data)
return rt_pin_read(cfg->scl);
}
/**
* The time delay function.
*
* @param us microseconds.
*/
static void ab32_udelay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = TMR0PR;
ticks = us * reload / (1000 / RT_TICK_PER_SECOND);
told = TMR0CNT;
while (1)
{
tnow = TMR0CNT;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
static const struct rt_i2c_bit_ops ab32_bit_ops_default =
{
.data = RT_NULL,
@ -184,7 +149,7 @@ static const struct rt_i2c_bit_ops ab32_bit_ops_default =
.set_scl = ab32_set_scl,
.get_sda = ab32_get_sda,
.get_scl = ab32_get_scl,
.udelay = ab32_udelay,
.udelay = rt_hw_us_delay,
.delay_us = 1,
.timeout = 100
};
@ -205,9 +170,9 @@ static rt_err_t ab32_i2c_bus_unlock(const struct ab32_soft_i2c_config *cfg)
while (i++ < 9)
{
rt_pin_write(cfg->scl, PIN_HIGH);
ab32_udelay(100);
rt_hw_us_delay(100);
rt_pin_write(cfg->scl, PIN_LOW);
ab32_udelay(100);
rt_hw_us_delay(100);
}
}
if (PIN_LOW == rt_pin_read(cfg->sda))

3
bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal.h
View File

@ -11,8 +11,9 @@
void hal_set_tick_hook(void (*hook)(uint32_t ticks));
void hal_set_ticks(uint32_t ticks);
uint32_t hal_get_ticks(void);
void hal_mdelay(uint32_t nms);
void hal_udelay(uint16_t nus);
void hal_udelay(uint32_t nus);
void hal_printf(const char *fmt, ...);
#endif

10
bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal.c
View File

@ -21,16 +21,12 @@ void hal_set_ticks(uint32_t ticks)
WEAK void hal_mdelay(uint32_t nms)
{
}
void hal_udelay(uint16_t nus)
WEAK void hal_udelay(uint32_t nus)
{
int i;
for (i = 0; i < nus*10; i++) {
asm("nop");
}
}
WEAK void hal_printf(const char *fmt, ...)
{}
{
}

3
bsp/bluetrum/libraries/hal_libraries/bmsis/source/startup.S
View File

@ -6,7 +6,6 @@
#include "ab32vg1.h"
.set _memcpy, 0x84044
.global _start
.section .reset, "ax"
_start:
@ -111,3 +110,5 @@ cpu_irq_comm:
.global _tp
.set _tp, 0x84800
.set _memcpy, 0x84044