add sdio support (#6385)
* add sdio support * update board kconfig * 优化SD卡挂载文件系统 * 使用通用接口实现led的闪烁操作
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19106eb3a1
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@ -16,15 +16,16 @@
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#define EXAMPLE_LED_GPIO GPIO9
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#define EXAMPLE_LED_GPIO_PIN (3U)
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#define EXAMPLE_LED_GPIO_PORT (3U)
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#define LED_PIN GET_PIN(EXAMPLE_LED_GPIO_PORT, EXAMPLE_LED_GPIO_PIN)
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int main(void)
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{
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rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
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while (1)
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{
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GPIO_PinWrite(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, 0U);
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rt_pin_write(LED_PIN, PIN_LOW);
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rt_thread_mdelay(500);
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GPIO_PinWrite(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, 1U);
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rt_pin_write(LED_PIN, PIN_HIGH);
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rt_thread_mdelay(500);
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}
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}
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@ -33,3 +33,29 @@ int mnt_init(void)
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}
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INIT_ENV_EXPORT(mnt_init);
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#endif
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#ifdef BSP_USING_SDCARD_FATFS
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#include <dfs_fs.h>
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#include <dfs_file.h>
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#define DBG_TAG "app.filesystem"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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static int filesystem_mount(void)
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{
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while(rt_device_find("sd0") == RT_NULL)
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{
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rt_thread_mdelay(1);
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}
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int ret = dfs_mount("sd0", "/", "elm", 0, 0);
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if (ret != 0)
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{
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rt_kprintf("ret: %d\n",ret);
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LOG_E("sd0p0 mount to '/' failed!");
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return ret;
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}
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return RT_EOK;
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}
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INIT_APP_EXPORT(filesystem_mount);
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#endif
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@ -28,6 +28,12 @@ menu "On-chip Peripheral Drivers"
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select RT_USING_RTC
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default n
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config BSP_USING_SDIO
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bool "Enable SDIO"
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select RT_USING_SDIO
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select RT_USING_DFS
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default n
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menuconfig BSP_USING_LPUART
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bool "Enable UART"
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select RT_USING_SERIAL
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@ -167,6 +173,21 @@ menu "Onboard Peripheral Drivers"
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endif
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endif
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endif
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menuconfig BSP_USING_FS
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bool "Enable File System"
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select RT_USING_DFS_DEVFS
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select RT_USING_DFS
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default n
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if BSP_USING_FS
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config BSP_USING_SDCARD_FATFS
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bool "Enable SDCARD (FATFS)"
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select BSP_USING_SDIO
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select RT_USING_DFS_ELMFAT
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default n
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endif
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endmenu
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menu "Board extended module Drivers"
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@ -9,6 +9,7 @@
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* 2022-08-15 xjy198903 add sdram pin config
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* 2022-08-17 xjy198903 add rgmii pins
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* 2022-09-01 xjy198903 add can pins
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* 2022-09-07 xjy198903 add sdio pins
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*/
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#include <rthw.h>
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@ -47,6 +47,8 @@ static int enable_log = 1;
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#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */
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#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */
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#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */
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#define SDMMCHOST_SUPPORT_MAX_BLOCK_LENGTH (4096U)
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#define SDMMCHOST_SUPPORT_MAX_BLOCK_COUNT (USDHC_MAX_BLOCK_COUNT)
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/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */
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#define USDHC_READ_WATERMARK_LEVEL (0x80U)
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@ -59,7 +61,6 @@ static int enable_log = 1;
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#define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle
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#ifdef SOC_IMXRT1170_SERIES
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#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN 1
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#define USDHC_ADMA_TABLE_WORDS (32U) /* define the ADMA descriptor table length */
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#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */
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#else
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@ -93,7 +94,7 @@ struct imxrt_mmcsd
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static void _mmcsd_gpio_init(struct imxrt_mmcsd *mmcsd)
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{
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CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
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// CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
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}
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static void SDMMCHOST_ErrorRecovery(USDHC_Type *base)
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{
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@ -343,6 +344,18 @@ static void _mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *i
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if (usdhc_clk > IMXRT_MAX_FREQ)
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usdhc_clk = IMXRT_MAX_FREQ;
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#ifdef SOC_IMXRT1170_SERIES
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clock_root_config_t rootCfg = {0};
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/* SYS PLL2 528MHz. */
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const clock_sys_pll2_config_t sysPll2Config = {
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.ssEnable = false,
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};
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CLOCK_InitSysPll2(&sysPll2Config);
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CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
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rootCfg.mux = 4;
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rootCfg.div = 2;
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CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
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src_clk = CLOCK_GetRootClockFreq(kCLOCK_Root_Usdhc1);
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#else
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src_clk = (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(mmcsd->usdhc_div) + 1U));
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@ -385,6 +398,7 @@ rt_int32_t _imxrt_mci_init(void)
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{
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struct rt_mmcsd_host *host;
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struct imxrt_mmcsd *mmcsd;
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uint32_t hs400Capability = 0U;
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host = mmcsd_alloc_host();
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if (!host)
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@ -412,11 +426,27 @@ rt_int32_t _imxrt_mci_init(void)
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host->valid_ocr = VDD_32_33 | VDD_33_34;
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host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \
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MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
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#ifdef SOC_IMXRT1170_SERIES
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#if defined FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn
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hs400Capability = (uint32_t)FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(mmcsd->usdhc_host.base);
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#endif
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#if (defined(FSL_FEATURE_USDHC_HAS_HS400_MODE) && (FSL_FEATURE_USDHC_HAS_HS400_MODE))
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if (hs400Capability != 0U)
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{
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host->flags |= (uint32_t)MMCSD_SUP_HIGHSPEED_HS400;
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}
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#endif
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#endif
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host->max_seg_size = 65535;
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host->max_dma_segs = 2;
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#ifdef SOC_IMXRT1170_SERIES
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host->max_blk_size = SDMMCHOST_SUPPORT_MAX_BLOCK_LENGTH;
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host->max_blk_count = SDMMCHOST_SUPPORT_MAX_BLOCK_COUNT;
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#else
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host->max_blk_size = 512;
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host->max_blk_count = 4096;
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#endif
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mmcsd->host = host;
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_mmcsd_clk_init(mmcsd);
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