libs/rt-thread
libs
/
rt-thread
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Merge branch 'master' of https://github.com/RT-Thread/rt-thread into develop_one

This commit is contained in:
liuxianliang 2021-04-06 10:42:58 +08:00
parent 4431c4796f c5a0df2254
commit 233e1cd8bc
472 changed files with 17540 additions and 15072 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
.github/workflows/file_check.yml vendored Normal file
View File

@ -0,0 +1,20 @@
name: Check File Format and License
on: [pull_request]
jobs:
scancode_job:
runs-on: ubuntu-latest
name: Scan code format and license
steps:
- uses: actions/checkout@v2
- name: Set up Python
uses: actions/setup-python@master
with:
python-version: 3.8
- name: Check Format and License
shell: bash
run: |
pip install click chardet
python tools/file_check.py check 'https://github.com/RT-Thread/rt-thread' 'master'

8
bsp/amebaz/applications/main.c
View File

@ -1,11 +1,7 @@
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

18
bsp/amebaz/applications/smartconfig_app.c
View File

@ -1,21 +1,7 @@
/*
* File : smartconfig_demo.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

8
bsp/amebaz/drivers/board.c
View File

@ -1,11 +1,7 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

8
bsp/amebaz/drivers/board.h
View File

@ -1,11 +1,7 @@
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

32
bsp/amebaz/drivers/drv_uart.c
View File

@ -1,21 +1,7 @@
/*
* File : drv_uart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
@ -125,7 +111,7 @@ static int ameba_uart_getc (struct rt_serial_device *serial)
{
struct device_uart* uart = serial->parent.user_data;
if(!serial_readable(&uart->serial))
if(!serial_readable(&uart->serial))
return -1;
/* Receive Data Available */
@ -140,13 +126,13 @@ static rt_size_t ameba_uart_dma_transmit (struct rt_serial_device *serial, rt_ui
static void ameba_uart_irq(uint32_t id, SerialIrq event)
{
struct rt_serial_device *serial = (struct rt_serial_device *)id;
if(event == RxIrq)
if(event == RxIrq)
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
else if(event == TxIrq)
}
else if(event == TxIrq)
{
}
}
}
static rt_err_t dbg_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
@ -192,9 +178,9 @@ static rt_err_t dbg_control(struct rt_serial_device *serial, int cmd, void *arg)
case RT_DEVICE_CTRL_SET_INT:
/* install interrupt */
DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler);
DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler);
/* Enable the UART Interrupt */
NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */
NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */
break;
}

18
bsp/amebaz/drivers/drv_uart.h
View File

@ -1,21 +1,7 @@
/*
* File : drv_uart.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

18
bsp/amebaz/drivers/wlan/drv_wifi.c
View File

@ -1,21 +1,7 @@
/*
* File : drv_wifi.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

18
bsp/amebaz/drivers/wlan/drv_wifi.h
View File

@ -1,21 +1,7 @@
/*
* File : drv_wifi.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

18
bsp/amebaz/drivers/wlan/drv_wlan.c
View File

@ -1,21 +1,7 @@
/*
* File : drv_wlan.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

30
bsp/amebaz/drivers/wlan/drv_wlan.h
View File

@ -1,21 +1,7 @@
/*
* File : drv_wlan.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
@ -27,12 +13,12 @@
typedef enum
{
RTHW_MODE_NONE = 0,
RTHW_MODE_STA,
RTHW_MODE_AP,
RTHW_MODE_STA_AP,
RTHW_MODE_PROMISC,
RTHW_MODE_P2P
RTHW_MODE_NONE = 0,
RTHW_MODE_STA,
RTHW_MODE_AP,
RTHW_MODE_STA_AP,
RTHW_MODE_PROMISC,
RTHW_MODE_P2P
}rthw_mode_t;
#define SHARED_ENABLED 0x00008000

2
bsp/at32/Libraries/rt_drivers/drv_adc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_adc.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_can.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_can.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

12
bsp/at32/Libraries/rt_drivers/drv_eth.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -28,8 +28,8 @@
//#define DRV_DEBUG
#define LOG_TAG "drv.emac"
#define ETH_RXBUFNB 4
#define ETH_TXBUFNB 2
#define ETH_RXBUFNB 4
#define ETH_TXBUFNB 2
#define LINK_THREAD_STACK_SIZE 256
#define LINK_THREAD_PREORITY 21
@ -173,7 +173,7 @@ void GPIO_Configuration(void)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
/*MII Mode GPIO configuration*/
/*MII Mode GPIO configuration*/
#ifdef MII_MODE
/**********************MII Tx Pin Define****************************/
/*
@ -193,7 +193,7 @@ void GPIO_Configuration(void)
GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
/**********************MII Rx Pin Define****************************/
/**********************MII Rx Pin Define****************************/
#if MII_RX_REMAP /*IO PIN remaped*/
/*
ETH_MII_RX_DV-->PD8
@ -256,7 +256,7 @@ void GPIO_Configuration(void)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
/**********************RMII Rx Pin Define****************************/
/**********************RMII Rx Pin Define****************************/
#if MII_RX_REMAP /*IO PIN remaped*/
/*
ETH_RMII_RX_DV-->PD8

2
bsp/at32/Libraries/rt_drivers/drv_eth.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/at32/Libraries/rt_drivers/drv_flash.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -160,7 +160,7 @@ int at32_flash_erase(rt_uint32_t addr, size_t size)
addr += FLASH_PAGE_SIZE;
}
FLASH_Lock();
FLASH_Lock();
__exit:
if(result != RT_EOK)

2
bsp/at32/Libraries/rt_drivers/drv_flash.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_gpio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_gpio.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_hwtimer.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_hwtimer.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_log.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_pwm.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_pwm.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

12
bsp/at32/Libraries/rt_drivers/drv_rtc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -79,10 +79,10 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
return -RT_ERROR;
}
#else
/* Set the RTC counter value */
RTC_SetCounter(time_stamp);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
/* Set the RTC counter value */
RTC_SetCounter(time_stamp);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
#endif /* SOC_SERIES_AT32F415 */
LOG_D("set rtc time.");
#ifdef SOC_SERIES_AT32F415
@ -148,7 +148,7 @@ static rt_err_t rt_rtc_config(struct rt_device *dev)
#else
if (BKP_ReadBackupReg(BKP_DT1) != BKUP_REG_DATA)
#endif
{
{
LOG_I("RTC hasn't been configured, please use <date> command to config.");
#ifdef SOC_SERIES_AT32F415
/* Configure the ERTC data register and ERTC prescaler */

2
bsp/at32/Libraries/rt_drivers/drv_sdio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_sdio.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_soft_i2c.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_soft_i2c.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

18
bsp/at32/Libraries/rt_drivers/drv_spi.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -86,8 +86,8 @@ static rt_err_t configure(struct rt_spi_device* device,
SPI_InitType SPI_InitStruct;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
at32_msp_spi_init(spi_instance->config->spix);
@ -200,7 +200,7 @@ static rt_err_t configure(struct rt_spi_device* device,
/* init SPI */
SPI_Init(spi_instance->config->spix, &SPI_InitStruct);
/* Enable SPI_MASTER */
SPI_Enable(spi_instance->config->spix, ENABLE);
SPI_Enable(spi_instance->config->spix, ENABLE);
SPI_CRCEN(spi_instance->config->spix, DISABLE);
return RT_EOK;
@ -213,8 +213,8 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
struct rt_spi_configuration * config = &device->config;
struct at32_spi_cs * at32_spi_cs = device->parent.user_data;
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
/* take CS */
if(message->cs_take)
@ -245,7 +245,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
//Wait until the transmit buffer is empty
while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_TE));
// Send the byte
SPI_I2S_TxData(spi_instance->config->spix, data);
SPI_I2S_TxData(spi_instance->config->spix, data);
//Wait until a data is received
while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_RNE));
@ -277,7 +277,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
//Wait until the transmit buffer is empty
while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_TE));
// Send the byte
SPI_I2S_TxData(spi_instance->config->spix, data);
SPI_I2S_TxData(spi_instance->config->spix, data);
//Wait until a data is received
while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_RNE));
@ -295,7 +295,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
/* release CS */
if(message->cs_release)
{
GPIO_SetBits(at32_spi_cs->GPIOx, at32_spi_cs->GPIO_Pin);
GPIO_SetBits(at32_spi_cs->GPIOx, at32_spi_cs->GPIO_Pin);
DEBUG_PRINTF("spi release cs\n");
}

2
bsp/at32/Libraries/rt_drivers/drv_spi.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_sram.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_sram.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/at32/Libraries/rt_drivers/drv_usart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -15,7 +15,7 @@
#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \
!defined(BSP_USING_UART3)
#error "Please define at least one BSP_USING_UARTx"
/* this driver can be disabled at menuconfig ¡ú RT-Thread Components ¡ú Device Drivers */
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
#endif
struct at32_usart {

2
bsp/at32/Libraries/rt_drivers/drv_usart.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_wdt.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/at32f403a-start/applications/main.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/at32f403a-start/board/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/at32f403a-start/board/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

36
bsp/at32/at32f403a-start/board/msp/system_at32f4xx.c
View File

@ -68,23 +68,23 @@
Clock (MHz)
PLL from HSE or HSI
SYSCLK HCLK PCLK2 PCLK1
24 24 24 24
36 36 36 36
48 48 48 24
56 56 56 28
72 72 72 36
96 96 48 48
108 108 54 54
120 120 60 60
144 144 72 72
150 150 75 75
168 168 84 84
176 176 88 88
192 192 96 96
200 200 100 100
224 224 112 112
240 240 120 120
SYSCLK HCLK PCLK2 PCLK1
24 24 24 24
36 36 36 36
48 48 48 24
56 56 56 28
72 72 72 36
96 96 48 48
108 108 54 54
120 120 60 60
144 144 72 72
150 150 75 75
168 168 84 84
176 176 88 88
192 192 96 96
200 200 100 100
224 224 112 112
240 240 120 120
*/
#if defined (AT32F403xx) || defined (AT32F413xx) || \
@ -573,7 +573,7 @@ static void SetSysClock(void)
/**
* @brief Setup the external memory controller.
* Called in startup_at32f4xx_xx.s/.c before jump to main.
* This function configures the external SRAM mounted
* This function configures the external SRAM mounted
* (AT32 High density devices). This SRAM will be used as program
* data memory (including heap and stack).
* @param None

2
bsp/at32/at32f407-start/applications/main.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/at32f407-start/board/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/at32f407-start/board/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

36
bsp/at32/at32f407-start/board/msp/system_at32f4xx.c
View File

@ -68,23 +68,23 @@
Clock (MHz)
PLL from HSE or HSI
SYSCLK HCLK PCLK2 PCLK1
24 24 24 24
36 36 36 36
48 48 48 24
56 56 56 28
72 72 72 36
96 96 48 48
108 108 54 54
120 120 60 60
144 144 72 72
150 150 75 75
168 168 84 84
176 176 88 88
192 192 96 96
200 200 100 100
224 224 112 112
240 240 120 120
SYSCLK HCLK PCLK2 PCLK1
24 24 24 24
36 36 36 36
48 48 48 24
56 56 56 28
72 72 72 36
96 96 48 48
108 108 54 54
120 120 60 60
144 144 72 72
150 150 75 75
168 168 84 84
176 176 88 88
192 192 96 96
200 200 100 100
224 224 112 112
240 240 120 120
*/
#if defined (AT32F403xx) || defined (AT32F413xx) || \
@ -573,7 +573,7 @@ static void SetSysClock(void)
/**
* @brief Setup the external memory controller.
* Called in startup_at32f4xx_xx.s/.c before jump to main.
* This function configures the external SRAM mounted
* This function configures the external SRAM mounted
* (AT32 High density devices). This SRAM will be used as program
* data memory (including heap and stack).
* @param None

6
bsp/bluetrum/libraries/hal_drivers/drv_rtc.c
View File

@ -182,7 +182,7 @@ static void rt_rtc_init(void)
hal_rtc_init();
}
static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
static rt_err_t ab32_rtc_control(rt_device_t dev, int cmd, void *args)
{
rt_err_t result = RT_EOK;
RT_ASSERT(dev != RT_NULL);
@ -224,7 +224,7 @@ const static struct rt_device_ops rtc_ops =
RT_NULL,
RT_NULL,
RT_NULL,
rt_rtc_control
ab32_rtc_control
};
#endif
@ -241,7 +241,7 @@ static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = rt_rtc_control;
device->control = ab32_rtc_control;
#endif
device->type = RT_Device_Class_RTC;
device->rx_indicate = RT_NULL;

8
bsp/efm32/Libraries/CMSIS/Include/arm_common_tables.h
View File

@ -2,12 +2,12 @@
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* $Date: 11. November 2010
* $Revision: V1.0.2
* $Revision: V1.0.2
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*

196
bsp/efm32/Libraries/CMSIS/Include/arm_math.h
View File

@ -2,12 +2,12 @@
* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
*
* $Date: 15. February 2012
* $Revision: V1.1.0
* $Revision: V1.1.0
*
* Project: CMSIS DSP Library
* Title: arm_math.h
* Project: CMSIS DSP Library
* Title: arm_math.h
*
* Description: Public header file for CMSIS DSP Library
* Description: Public header file for CMSIS DSP Library
*
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
*
@ -272,7 +272,7 @@
#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
#include "string.h"
#include "math.h"
#ifdef __cplusplus
#ifdef __cplusplus
extern "C"
{
#endif
@ -282,27 +282,27 @@ extern "C"
* @brief Macros required for reciprocal calculation in Normalized LMS
*/
#define DELTA_Q31 (0x100)
#define DELTA_Q15 0x5
#define INDEX_MASK 0x0000003F
#define DELTA_Q31 (0x100)
#define DELTA_Q15 0x5
#define INDEX_MASK 0x0000003F
#ifndef PI
#define PI 3.14159265358979f
#define PI 3.14159265358979f
#endif
/**
* @brief Macros required for SINE and COSINE Fast math approximations
*/
#define TABLE_SIZE 256
#define TABLE_SPACING_Q31 0x800000
#define TABLE_SPACING_Q15 0x80
#define TABLE_SIZE 256
#define TABLE_SPACING_Q31 0x800000
#define TABLE_SPACING_Q15 0x80
/**
* @brief Macros required for SINE and COSINE Controller functions
*/
/* 1.31(q31) Fixed value of 2/360 */
/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
#define INPUT_SPACING 0xB60B61
#define INPUT_SPACING 0xB60B61
/**
* @brief Macro for Unaligned Support
@ -315,7 +315,7 @@ extern "C"
#else
#define ALIGN4 __align(4)
#endif
#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
/**
* @brief Error status returned by some functions in the library.
@ -392,16 +392,16 @@ extern "C"
*/
#ifndef ARM_MATH_BIG_ENDIAN
#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
(((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
(((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
(((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
(((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
(((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
(((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
#else
#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
(((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
(((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
(((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
(((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
(((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
(((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
#endif
@ -1169,11 +1169,11 @@ extern "C"
/**
* @brief Initialization function for the Q31 FIR filter.
* @param[in,out] *S points to an instance of the Q31 FIR structure.
* @param[in] numTaps Number of filter coefficients in the filter.
* @param[in] *pCoeffs points to the filter coefficients.
* @param[in] *pState points to the state buffer.
* @param[in] blockSize number of samples that are processed at a time.
* @return none.
* @param[in] numTaps Number of filter coefficients in the filter.
* @param[in] *pCoeffs points to the filter coefficients.
* @param[in] *pState points to the state buffer.
* @param[in] blockSize number of samples that are processed at a time.
* @return none.
*/
void arm_fir_init_q31(
arm_fir_instance_q31 * S,
@ -1199,11 +1199,11 @@ extern "C"
/**
* @brief Initialization function for the floating-point FIR filter.
* @param[in,out] *S points to an instance of the floating-point FIR filter structure.
* @param[in] numTaps Number of filter coefficients in the filter.
* @param[in] *pCoeffs points to the filter coefficients.
* @param[in] *pState points to the state buffer.
* @param[in] blockSize number of samples that are processed at a time.
* @return none.
* @param[in] numTaps Number of filter coefficients in the filter.
* @param[in] *pCoeffs points to the filter coefficients.
* @param[in] *pState points to the state buffer.
* @param[in] blockSize number of samples that are processed at a time.
* @return none.
*/
void arm_fir_init_f32(
arm_fir_instance_f32 * S,
@ -1463,7 +1463,7 @@ extern "C"
* @brief Floating-point matrix transpose.
* @param[in] *pSrc points to the input matrix
* @param[out] *pDst points to the output matrix
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
*/
@ -1476,7 +1476,7 @@ extern "C"
* @brief Q15 matrix transpose.
* @param[in] *pSrc points to the input matrix
* @param[out] *pDst points to the output matrix
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
*/
@ -1488,7 +1488,7 @@ extern "C"
* @brief Q31 matrix transpose.
* @param[in] *pSrc points to the input matrix
* @param[out] *pDst points to the output matrix
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
*/
@ -1531,7 +1531,7 @@ extern "C"
* @param[in] *pSrcA points to the first input matrix structure
* @param[in] *pSrcB points to the second input matrix structure
* @param[out] *pDst points to output matrix structure
* @param[in] *pState points to the array for storing intermediate results
* @param[in] *pState points to the array for storing intermediate results
* @return The function returns either
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
*/
@ -1665,7 +1665,7 @@ extern "C"
* @param[in,out] *S points to an instance of the floating-point matrix structure.
* @param[in] nRows number of rows in the matrix.
* @param[in] nColumns number of columns in the matrix.
* @param[in] *pData points to the matrix data array.
* @param[in] *pData points to the matrix data array.
* @return none
*/
@ -1680,7 +1680,7 @@ extern "C"
* @param[in,out] *S points to an instance of the floating-point matrix structure.
* @param[in] nRows number of rows in the matrix.
* @param[in] nColumns number of columns in the matrix.
* @param[in] *pData points to the matrix data array.
* @param[in] *pData points to the matrix data array.
* @return none
*/
@ -1695,7 +1695,7 @@ extern "C"
* @param[in,out] *S points to an instance of the floating-point matrix structure.
* @param[in] nRows number of rows in the matrix.
* @param[in] nColumns number of columns in the matrix.
* @param[in] *pData points to the matrix data array.
* @param[in] *pData points to the matrix data array.
* @return none
*/
@ -2187,7 +2187,7 @@ extern "C"
/*----------------------------------------------------------------------
* Internal functions prototypes FFT function
* Internal functions prototypes FFT function
----------------------------------------------------------------------*/
/**
@ -2256,7 +2256,7 @@ extern "C"
* @brief Core function for the f32 FFT butterfly process.
* @param[in, out] *pSrc points to the in-place buffer of f32 data type.
* @param[in] fftLen length of the FFT.
* @param[in] *pCoef points to Twiddle coefficient buffer.
* @param[in] *pCoef points to Twiddle coefficient buffer.
* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @return none.
*/
@ -2268,13 +2268,13 @@ extern "C"
uint16_t twidCoefModifier);
/**
* @brief Core function for the Radix-2 Q31 CFFT butterfly process.
* @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
* @param[in] fftLen length of the FFT.
* @param[in] *pCoef points to Twiddle coefficient buffer.
* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @return none.
*/
* @brief Core function for the Radix-2 Q31 CFFT butterfly process.
* @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
* @param[in] fftLen length of the FFT.
* @param[in] *pCoef points to Twiddle coefficient buffer.
* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @return none.
*/
void arm_radix2_butterfly_q31(
q31_t * pSrc,
@ -2283,13 +2283,13 @@ extern "C"
uint16_t twidCoefModifier);
/**
* @brief Core function for the Radix-2 Q15 CFFT butterfly process.
* @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
* @param[in] fftLen length of the FFT.
* @param[in] *pCoef points to Twiddle coefficient buffer.
* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @return none.
*/
* @brief Core function for the Radix-2 Q15 CFFT butterfly process.
* @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
* @param[in] fftLen length of the FFT.
* @param[in] *pCoef points to Twiddle coefficient buffer.
* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @return none.
*/
void arm_radix2_butterfly_q15(
q15_t * pSrc,
@ -2298,13 +2298,13 @@ extern "C"
uint16_t twidCoefModifier);
/**
* @brief Core function for the Radix-2 Q15 CFFT Inverse butterfly process.
* @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
* @param[in] fftLen length of the FFT.
* @param[in] *pCoef points to Twiddle coefficient buffer.
* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @return none.
*/
* @brief Core function for the Radix-2 Q15 CFFT Inverse butterfly process.
* @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
* @param[in] fftLen length of the FFT.
* @param[in] *pCoef points to Twiddle coefficient buffer.
* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @return none.
*/
void arm_radix2_butterfly_inverse_q15(
q15_t * pSrc,
@ -2313,13 +2313,13 @@ extern "C"
uint16_t twidCoefModifier);
/**
* @brief Core function for the Radix-2 Q31 CFFT Inverse butterfly process.
* @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
* @param[in] fftLen length of the FFT.
* @param[in] *pCoef points to Twiddle coefficient buffer.
* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @return none.
*/
* @brief Core function for the Radix-2 Q31 CFFT Inverse butterfly process.
* @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
* @param[in] fftLen length of the FFT.
* @param[in] *pCoef points to Twiddle coefficient buffer.
* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @return none.
*/
void arm_radix2_butterfly_inverse_q31(
q31_t * pSrc,
@ -2331,9 +2331,9 @@ extern "C"
* @brief Core function for the f32 IFFT butterfly process.
* @param[in, out] *pSrc points to the in-place buffer of f32 data type.
* @param[in] fftLen length of the FFT.
* @param[in] *pCoef points to Twiddle coefficient buffer.
* @param[in] *pCoef points to Twiddle coefficient buffer.
* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
* @param[in] onebyfftLen 1/fftLenfth
* @param[in] onebyfftLen 1/fftLenfth
* @return none.
*/
@ -2489,7 +2489,7 @@ extern "C"
* @param[in] fftLenReal length of the FFT.
* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
*/
arm_status arm_rfft_init_q15(
@ -2519,7 +2519,7 @@ extern "C"
* @param[in] fftLenReal length of the FFT.
* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
*/
arm_status arm_rfft_init_q31(
@ -2536,7 +2536,7 @@ extern "C"
* @param[in] fftLenReal length of the FFT.
* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
*/
arm_status arm_rfft_init_f32(
@ -2582,7 +2582,7 @@ extern "C"
* @param[in] N length of the DCT4.
* @param[in] Nby2 half of the length of the DCT4.
* @param[in] normalize normalizing factor.
* @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
* @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
*/
arm_status arm_dct4_init_f32(
@ -2629,7 +2629,7 @@ extern "C"
* @param[in] N length of the DCT4.
* @param[in] Nby2 half of the length of the DCT4.
* @param[in] normalize normalizing factor.
* @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
* @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
*/
arm_status arm_dct4_init_q31(
@ -2676,7 +2676,7 @@ extern "C"
* @param[in] N length of the DCT4.
* @param[in] Nby2 half of the length of the DCT4.
* @param[in] normalize normalizing factor.
* @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
* @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
*/
arm_status arm_dct4_init_q15(
@ -3318,11 +3318,11 @@ extern "C"
*/
void arm_conv_fast_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
/**
* @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
@ -3504,13 +3504,13 @@ extern "C"
*/
arm_status arm_conv_partial_fast_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
uint32_t firstIndex,
uint32_t numPoints);
/**
@ -4701,11 +4701,11 @@ extern "C"
*/
void arm_correlate_fast_q15(
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst);
@ -5604,8 +5604,8 @@ extern "C"
* @brief Floating-point Park transform
* @param[in] Ialpha input two-phase vector coordinate alpha
* @param[in] Ibeta input two-phase vector coordinate beta
* @param[out] *pId points to output rotor reference frame d
* @param[out] *pIq points to output rotor reference frame q
* @param[out] *pId points to output rotor reference frame d
* @param[out] *pIq points to output rotor reference frame q
* @param[in] sinVal sine value of rotation angle theta
* @param[in] cosVal cosine value of rotation angle theta
* @return none.
@ -5751,7 +5751,7 @@ extern "C"
/**
* @brief Inverse Park transform for Q31 version
* @brief Inverse Park transform for Q31 version
* @param[in] Id input coordinate of rotor reference frame d
* @param[in] Iq input coordinate of rotor reference frame q
* @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
@ -7543,7 +7543,7 @@ extern "C"
#ifdef __cplusplus
#ifdef __cplusplus
}
#endif

2
bsp/efm32/Libraries/CMSIS/RTOS/cmsis_os.h
View File

@ -100,7 +100,7 @@ used throughout the whole project.
#define osCMSIS 0x00003 ///< API version (main [31:16] .sub [15:0])
/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlaying RTOS kernel and version number.
#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0])
#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0])
/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string

4
bsp/efm32/Libraries/emlib/inc/em_acmp.h
View File

@ -173,7 +173,7 @@ typedef struct
* power used by the VDD and bandgap references. */
bool lowPowerReferenceEnabled;
/** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
/** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
* Valid values are in the range 0-63. */
uint32_t vddLevel;
@ -229,7 +229,7 @@ typedef struct
* power used by the VDD and bandgap references. */
bool lowPowerReferenceEnabled;
/** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
/** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
* Valid values are in the range 0-63. */
uint32_t vddLevel;

146
bsp/efm32/board.c
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file board.c
* @brief Board support of RT-Thread RTOS for EFM32
* @file board.c
* @brief Board support of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,12 +10,12 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2010-12-21 onelife Initial creation for EFM32
* 2011-05-06 onelife Add EFM32 development kit and SPI Flash support
* 2011-07-12 onelife Add SWO output enable function
* 2011-12-08 onelife Add giant gecko development kit support
* 2011-12-09 onelife Add giant gecko support
* Date Author Notes
* 2010-12-21 onelife Initial creation for EFM32
* 2011-05-06 onelife Add EFM32 development kit and SPI Flash support
* 2011-07-12 onelife Add SWO output enable function
* 2011-12-08 onelife Add giant gecko development kit support
* 2011-12-09 onelife Add giant gecko support
* 2011-12-09 onelife Add LEUART module support
* 2011-12-14 onelife Add LFXO enabling routine in driver initialization
* function
@ -37,19 +37,19 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == RAM_MEM_BASE) || \
((VECTTAB) == FLASH_MEM_BASE))
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == RAM_MEM_BASE) || \
((VECTTAB) == FLASH_MEM_BASE))
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
/***************************************************************************//**
* @addtogroup SysTick_clock_source
* @{
******************************************************************************/
#define SysTick_CLKSource_MASK ((rt_uint32_t)0x00000004)
#define SysTick_CLKSource_RTC ((rt_uint32_t)0x00000000)
#define SysTick_CLKSource_HFCORECLK ((rt_uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_RTC) || \
((SOURCE) == SysTick_CLKSource_HFCORECLK))
#define SysTick_CLKSource_RTC ((rt_uint32_t)0x00000000)
#define SysTick_CLKSource_HFCORECLK ((rt_uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_RTC) || \
((SOURCE) == SysTick_CLKSource_HFCORECLK))
/***************************************************************************//**
* @}
******************************************************************************/
@ -67,20 +67,20 @@
* @note
*
* @param[in] NVIC_VectTab
* Indicate the vector table is allocated in RAM or ROM
* Indicate the vector table is allocated in RAM or ROM
*
* @param[in] Offset
* The vector table offset
******************************************************************************/
static void NVIC_SetVectorTable(
rt_uint32_t NVIC_VectTab,
rt_uint32_t Offset)
rt_uint32_t NVIC_VectTab,
rt_uint32_t Offset)
{
/* Check the parameters */
RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab));
RT_ASSERT(IS_NVIC_OFFSET(Offset));
/* Check the parameters */
RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab));
RT_ASSERT(IS_NVIC_OFFSET(Offset));
SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80);
SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80);
}
/***************************************************************************//**
@ -95,19 +95,19 @@ static void NVIC_SetVectorTable(
static void NVIC_Configuration(void)
{
#ifdef VECT_TAB_RAM
/* Set the vector table allocated at 0x20000000 */
NVIC_SetVectorTable(RAM_MEM_BASE, 0x0);
/* Set the vector table allocated at 0x20000000 */
NVIC_SetVectorTable(RAM_MEM_BASE, 0x0);
#else /* VECT_TAB_FLASH */
/* Set the vector table allocated at 0x00000000 */
NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0);
/* Set the vector table allocated at 0x00000000 */
NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0);
#endif
/* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for
subpriority */
NVIC_SetPriorityGrouping(0x7UL);
/* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for
subpriority */
NVIC_SetPriorityGrouping(0x7UL);
/* Set Base Priority Mask Register */
__set_BASEPRI(EFM32_BASE_PRI_DEFAULT);
/* Set Base Priority Mask Register */
__set_BASEPRI(EFM32_BASE_PRI_DEFAULT);
}
/***************************************************************************//**
@ -119,13 +119,13 @@ static void NVIC_Configuration(void)
* @note
*
* @param[in] SysTick_CLKSource
* Specifies the SysTick clock source.
* Specifies the SysTick clock source.
*
* @arg SysTick_CLKSource_HCLK_Div8
* AHB clock divided by 8 selected as SysTick clock source.
* AHB clock divided by 8 selected as SysTick clock source.
*
* @arg SysTick_CLKSource_HCLK
* AHB clock selected as SysTick clock source.
* AHB clock selected as SysTick clock source.
******************************************************************************/
static void SysTick_CLKSourceConfig(rt_uint32_t SysTick_CLKSource)
{
@ -184,14 +184,14 @@ static void SysTick_Configuration(void)
/* Start LETIMER0 */
LETIMER_Init(LETIMER0, &letimerInit);
#else
rt_uint32_t coreClk;
rt_uint32_t cnts;
rt_uint32_t coreClk;
rt_uint32_t cnts;
coreClk = SystemCoreClockGet();
cnts = coreClk / RT_TICK_PER_SECOND;
coreClk = SystemCoreClockGet();
cnts = coreClk / RT_TICK_PER_SECOND;
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK);
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK);
#endif
}
@ -206,9 +206,9 @@ static void SysTick_Configuration(void)
******************************************************************************/
void Swo_Configuration(void)
{
rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000;
rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010;
rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0;
rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000;
rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010;
rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0;
CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO;
/* Enable Serial wire output pin */
@ -258,12 +258,12 @@ void Swo_Configuration(void)
******************************************************************************/
void rt_hw_board_init(void)
{
/* Chip errata */
CHIP_Init();
/* Chip errata */
CHIP_Init();
/* Initialize DVK board register access */
#if defined(EFM32_GXXX_DK)
DVK_init();
DVK_init();
#elif defined(EFM32GG_DK3750)
DVK_init(DVK_Init_EBI);
@ -272,12 +272,12 @@ void rt_hw_board_init(void)
DVK_clearInterruptFlags(BC_INTFLAG_MASK);
#endif
/* config NVIC Configuration */
NVIC_Configuration();
/* config NVIC Configuration */
NVIC_Configuration();
#if defined(EFM32_USING_HFXO)
/* Configure external oscillator */
SystemHFXOClockSet(EFM32_HFXO_FREQUENCY);
/* Configure external oscillator */
SystemHFXOClockSet(EFM32_HFXO_FREQUENCY);
/* Switching the CPU clock source to HFXO */
CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO);
@ -293,15 +293,15 @@ void rt_hw_board_init(void)
#if defined(EFM32_SWO_ENABLE)
/* Enable SWO */
Swo_Configuration();
Swo_Configuration();
#endif
/* Enable high frequency peripheral clock */
CMU_ClockEnable(cmuClock_HFPER, true);
/* Enabling clock to the interface of the low energy modules */
CMU_ClockEnable(cmuClock_CORELE, true);
/* Enable high frequency peripheral clock */
CMU_ClockEnable(cmuClock_HFPER, true);
/* Enabling clock to the interface of the low energy modules */
CMU_ClockEnable(cmuClock_CORELE, true);
/* Enable GPIO clock */
CMU_ClockEnable(cmuClock_GPIO, true);
CMU_ClockEnable(cmuClock_GPIO, true);
/* Configure the SysTick */
SysTick_Configuration();
@ -318,8 +318,8 @@ void rt_hw_board_init(void)
******************************************************************************/
void rt_hw_driver_init(void)
{
/* Initialize DMA */
rt_hw_dma_init();
/* Initialize DMA */
rt_hw_dma_init();
/* Select LFXO for specified module (and wait for it to stabilize) */
#if (!defined(EFM32_USING_LFXO) && defined(RT_USING_RTC))
@ -331,11 +331,11 @@ void rt_hw_driver_init(void)
#error "Low frequency clock source is needed for using LEUART"
#endif
/* Initialize USART */
/* Initialize USART */
#if (defined(RT_USING_USART0) || defined(RT_USING_USART1) || \
defined(RT_USING_USART2) || defined(RT_USING_UART0) || \
defined(RT_USING_UART1))
rt_hw_usart_init();
rt_hw_usart_init();
#endif
/* Initialize LEUART */
@ -343,7 +343,7 @@ void rt_hw_driver_init(void)
rt_hw_leuart_init();
#endif
/* Setup Console */
/* Setup Console */
#if defined(EFM32_GXXX_DK)
DVK_enablePeripheral(DVK_RS232A);
DVK_enablePeripheral(DVK_SPI);
@ -354,31 +354,31 @@ void rt_hw_driver_init(void)
DVK_enablePeripheral(DVK_RS232_LEUART);
#endif
#endif
rt_console_set_device(CONSOLE_DEVICE);
rt_console_set_device(CONSOLE_DEVICE);
/* Initialize Timer */
/* Initialize Timer */
#if (defined(RT_USING_TIMER0) || defined(RT_USING_TIMER1) || defined(RT_USING_TIMER2))
rt_hw_timer_init();
rt_hw_timer_init();
#endif
/* Initialize ADC */
/* Initialize ADC */
#if defined(RT_USING_ADC0)
rt_hw_adc_init();
rt_hw_adc_init();
#endif
/* Initialize ACMP */
/* Initialize ACMP */
#if (defined(RT_USING_ACMP0) || defined(RT_USING_ACMP1))
rt_hw_acmp_init();
rt_hw_acmp_init();
#endif
/* Initialize IIC */
/* Initialize IIC */
#if (defined(RT_USING_IIC0) || defined(RT_USING_IIC1))
rt_hw_iic_init();
rt_hw_iic_init();
#endif
/* Initialize RTC */
/* Initialize RTC */
#if defined(RT_USING_RTC)
rt_hw_rtc_init();
rt_hw_rtc_init();
#endif
/* Enable SPI access to MicroSD card */

126
bsp/efm32/board.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file board.h
* @brief Board support of RT-Thread RTOS for EFM32
* @file board.h
* @brief Board support of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,18 +10,18 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2010-12-21 onelife Initial creation for EFM32
* 2011-05-06 onelife Add EFM32 development kit and SPI Flash support
* 2011-07-12 onelife Add prototype for SWO output enable and interrupt
* Date Author Notes
* 2010-12-21 onelife Initial creation for EFM32
* 2011-05-06 onelife Add EFM32 development kit and SPI Flash support
* 2011-07-12 onelife Add prototype for SWO output enable and interrupt
* context check functions
* 2011-12-08 onelife Add giant gecko development kit support
* 2011-12-09 onelife Add giant gecko support
* 2011-12-08 onelife Add giant gecko development kit support
* 2011-12-09 onelife Add giant gecko support
* 2011-12-09 onelife Add LEUART module support
* 2011-12-14 onelife Add LFXO enabling routine in driver initialization
* function
* 2011-12-20 onelife Move SPI Auto-CS setting to "rtconfig.h"
* 2012-05-15 onelife Modified to compatible with CMSIS v3
* 2012-05-15 onelife Modified to compatible with CMSIS v3
******************************************************************************/
#ifndef __BOARD_H__
#define __BOARD_H__
@ -72,15 +72,15 @@ extern volatile rt_uint32_t rt_system_status;
#define EFM32_SWO_ENABLE
#endif
#define EFM32_NO_DATA (0)
#define EFM32_NO_POINTER (RT_NULL)
#define EFM32_NO_OFFSET (-1)
#define EFM32_NO_DMA (-1)
#define EFM32_NO_DATA (0)
#define EFM32_NO_POINTER (RT_NULL)
#define EFM32_NO_OFFSET (-1)
#define EFM32_NO_DMA (-1)
/* SECTION: SPI Flash */
#if defined(EFM32_USING_SFLASH)
#define SFLASH_CS_PORT (gpioPortC)
#define SFLASH_CS_PIN (8)
#define SFLASH_CS_PORT (gpioPortC)
#define SFLASH_CS_PIN (8)
#endif
/* SECTION: Micro SD */
@ -114,9 +114,9 @@ extern volatile rt_uint32_t rt_system_status;
#endif
/* SECTION: SYSTEM */
#define EFM32_SRAM_END (SRAM_BASE + SRAM_SIZE)
#define EFM32_BASE_PRI_DEFAULT (0x0UL << 5)
#define EFM32_IRQ_PRI_DEFAULT (0x4UL << 5)
#define EFM32_SRAM_END (SRAM_BASE + SRAM_SIZE)
#define EFM32_BASE_PRI_DEFAULT (0x0UL << 5)
#define EFM32_IRQ_PRI_DEFAULT (0x4UL << 5)
/* SECTION: CLOCK */
#define EFM32_USING_HFXO
@ -125,9 +125,9 @@ extern volatile rt_uint32_t rt_system_status;
#if (defined(EFM32_G8XX_STK) || defined(EFM32_GXXX_DK))
#define EFM32_HFXO_FREQUENCY (32000000)
#elif defined(EFM32GG_DK3750)
#define EFM32_HFXO_FREQUENCY (48000000)
#define EFM32_HFXO_FREQUENCY (48000000)
#else
#define EFM32_HFXO_FREQUENCY (00000000)
#define EFM32_HFXO_FREQUENCY (00000000)
#endif
#endif
#if defined(EFM32_USING_LFXO)
@ -141,8 +141,8 @@ extern volatile rt_uint32_t rt_system_status;
#endif
/* SECTION: USART */
#define USART_RX_BUFFER_SIZE (64)
#define LEUART_RX_BUFFER_SIZE (64)
#define USART_RX_BUFFER_SIZE (64)
#define LEUART_RX_BUFFER_SIZE (64)
/* Location count (start from 0) */
#if defined(_EFM32_GECKO_FAMILY)
#define EFM32_USART_LOCATION_COUNT (3)
@ -155,14 +155,14 @@ extern volatile rt_uint32_t rt_system_status;
#endif
/* SUBSECTION: UART */
#define UART_BAUDRATE (115200)
#define UART_BAUDRATE (115200)
/* SUBSECTION: SPI */
/* Max SPI clock: HFPERCLK/2 for master, HFPERCLK/8 for slave */
#define SPI_BAUDRATE (4000000)
#define SPI_BAUDRATE (4000000)
/* SECTION: I2C */
#define IIC_RX_BUFFER_SIZE (32)
#define IIC_RX_BUFFER_SIZE (32)
#if defined(_EFM32_GECKO_FAMILY)
#define EFM32_IIC_LOCATION_COUNT (4)
#elif defined(_EFM32_GIANT_FAMILY)
@ -170,61 +170,61 @@ extern volatile rt_uint32_t rt_system_status;
#endif
/* SECTION: ADC */
#define ADC_CALI_REF (adcRef2V5)
#define ADC_CALI_CH (adcSingleInpCh5)
#define ADC_CONVERT_FREQUENCY (7000000)
#define ADC_CALI_REF (adcRef2V5)
#define ADC_CALI_CH (adcSingleInpCh5)
#define ADC_CONVERT_FREQUENCY (7000000)
#if (RT_CONSOLE_DEVICE == EFM_USART0)
#define CONSOLE_DEVICE RT_USART0_NAME
#define CONSOLE_DEVICE RT_USART0_NAME
#elif (RT_CONSOLE_DEVICE == EFM_USART1)
#define CONSOLE_DEVICE RT_USART1_NAME
#define CONSOLE_DEVICE RT_USART1_NAME
#elif (RT_CONSOLE_DEVICE == EFM_USART2)
#define CONSOLE_DEVICE RT_USART2_NAME
#define CONSOLE_DEVICE RT_USART2_NAME
#elif (RT_CONSOLE_DEVICE == EFM_UART0)
#define CONSOLE_DEVICE RT_UART0_NAME
#define CONSOLE_DEVICE RT_UART0_NAME
#elif (RT_CONSOLE_DEVICE == EFM_UART1)
#define CONSOLE_DEVICE RT_UART1_NAME
#define CONSOLE_DEVICE RT_UART1_NAME
#elif (RT_CONSOLE_DEVICE == EFM_LEUART0)
#define CONSOLE_DEVICE RT_LEUART0_NAME
#define CONSOLE_DEVICE RT_LEUART0_NAME
#elif (RT_CONSOLE_DEVICE == EFM_LEUART1)
#define CONSOLE_DEVICE RT_LEUART1_NAME
#define CONSOLE_DEVICE RT_LEUART1_NAME
#else
#define CONSOLE_DEVICE "NONE"
#define CONSOLE_DEVICE "NONE"
#endif
/* The following defines should be consistent with those in diskio.h */
#define CTRL_SYNC 0
#define GET_SECTOR_COUNT 1
#define GET_SECTOR_SIZE 2
#define GET_BLOCK_SIZE 3
#define MMC_GET_TYPE 10
#define MMC_GET_CSD 11
#define MMC_GET_CID 12
#define MMC_GET_OCR 13
#define MMC_GET_SDSTAT 14
#define CTRL_SYNC 0
#define GET_SECTOR_COUNT 1
#define GET_SECTOR_SIZE 2
#define GET_BLOCK_SIZE 3
#define MMC_GET_TYPE 10
#define MMC_GET_CSD 11
#define MMC_GET_CID 12
#define MMC_GET_OCR 13
#define MMC_GET_SDSTAT 14
/* The above defines should be consistent with those in diskio.h */
/* I/O control options */
#define RT_DEVICE_CTRL_SD_SYNC CTRL_SYNC
#define RT_DEVICE_CTRL_SD_GET_SCOUNT GET_SECTOR_COUNT
#define RT_DEVICE_CTRL_SD_GET_SSIZE GET_SECTOR_SIZE
#define RT_DEVICE_CTRL_SD_GET_BSIZE GET_BLOCK_SIZE
#define RT_DEVICE_CTRL_SD_GET_TYPE MMC_GET_TYPE
#define RT_DEVICE_CTRL_SD_GET_CSD MMC_GET_CSD
#define RT_DEVICE_CTRL_SD_GET_CID MMC_GET_CID
#define RT_DEVICE_CTRL_SD_GET_OCR MMC_GET_OCR
#define RT_DEVICE_CTRL_SD_GET_SDSTAT MMC_GET_SDSTAT
#define RT_DEVICE_CTRL_SD_SYNC CTRL_SYNC
#define RT_DEVICE_CTRL_SD_GET_SCOUNT GET_SECTOR_COUNT
#define RT_DEVICE_CTRL_SD_GET_SSIZE GET_SECTOR_SIZE
#define RT_DEVICE_CTRL_SD_GET_BSIZE GET_BLOCK_SIZE
#define RT_DEVICE_CTRL_SD_GET_TYPE MMC_GET_TYPE
#define RT_DEVICE_CTRL_SD_GET_CSD MMC_GET_CSD
#define RT_DEVICE_CTRL_SD_GET_CID MMC_GET_CID
#define RT_DEVICE_CTRL_SD_GET_OCR MMC_GET_OCR
#define RT_DEVICE_CTRL_SD_GET_SDSTAT MMC_GET_SDSTAT
/*! fixme: move the following define to Rtdef.h */
#define RT_DEVICE_CTRL_USART_RBUFFER (0xF1) /*!< set USART/UART rx buffer */
#define RT_DEVICE_CTRL_LEUART_RBUFFER (0xF2) /*!< set LEUART rx buffer */
#define RT_DEVICE_CTRL_IIC_SETTING (0xF3) /*!< change IIC setting */
#define RT_DEVICE_CTRL_TIMER_PERIOD (0xF4) /*!< set Timer timeout period */
#define RT_DEVICE_CTRL_ADC_MODE (0xF5) /*!< change ADC mode */
#define RT_DEVICE_CTRL_ADC_RESULT (0xF6) /*!< get ADC result */
#define RT_DEVICE_CTRL_ACMP_INIT (0xF7) /*!< Initialize ACMP */
#define RT_DEVICE_CTRL_ACMP_OUTPUT (0xF8) /*!< get ACMP output */
#define RT_DEVICE_CTRL_USART_RBUFFER (0xF1) /*!< set USART/UART rx buffer */
#define RT_DEVICE_CTRL_LEUART_RBUFFER (0xF2) /*!< set LEUART rx buffer */
#define RT_DEVICE_CTRL_IIC_SETTING (0xF3) /*!< change IIC setting */
#define RT_DEVICE_CTRL_TIMER_PERIOD (0xF4) /*!< set Timer timeout period */
#define RT_DEVICE_CTRL_ADC_MODE (0xF5) /*!< change ADC mode */
#define RT_DEVICE_CTRL_ADC_RESULT (0xF6) /*!< get ADC result */
#define RT_DEVICE_CTRL_ACMP_INIT (0xF7) /*!< Initialize ACMP */
#define RT_DEVICE_CTRL_ACMP_OUTPUT (0xF8) /*!< get ACMP output */
/* Exported functions ------------------------------------------------------- */
void rt_hw_board_init(void);

1256
bsp/efm32/dev_accel.c
View File

File diff suppressed because it is too large Load Diff

146
bsp/efm32/dev_accel.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_accel.h
* @brief Accelerometer driver of RT-Thread RTOS for EFM32
* @file dev_accel.h
* @brief Accelerometer driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,10 +10,10 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-07-13 onelife Initial creation for using EFM32 ADC module to
* Date Author Notes
* 2011-07-13 onelife Initial creation for using EFM32 ADC module to
* interface the Freescale MMA7361L
* 2011-08-02 onelife Add digital interface support of using EFM32 IIC
* 2011-08-02 onelife Add digital interface support of using EFM32 IIC
* module for the Freescale MMA7455L
******************************************************************************/
#ifndef __DEV_ACCEL_H__
@ -27,95 +27,95 @@
/* Exported types ------------------------------------------------------------*/
struct efm32_accel_result_t
{
rt_int32_t x;
rt_int32_t y;
rt_int32_t z;
rt_int32_t x;
rt_int32_t y;
rt_int32_t z;
};
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* MMA7361LC
g-Select g-Range Sensitivity
0 1.5 g 800 mV/g
1 6 g 206 mV/g
/* MMA7361LC
g-Select g-Range Sensitivity
0 1.5 g 800 mV/g
1 6 g 206 mV/g
MMA7455L
g-Select g-Range Sensitivity
0 2 g 64 LSB/g
1 4 g 32 LSB/g
2 8 g 16 LSB/g
MMA7455L
g-Select g-Range Sensitivity
0 2 g 64 LSB/g
1 4 g 32 LSB/g
2 8 g 16 LSB/g
*/
#define ACCEL_G_SELECT (0)
#define ACCEL_G_SELECT (0)
#define ACCEL_CAL_SAMPLES (4) /* Must be multiple of 2 */
#define ACCEL_CAL_ROUND (50)
#define ACCEL_CAL_SIMPLE (0)
#define ACCEL_CAL_INTERACT (1)
#define ACCEL_CAL_SAMPLES (4) /* Must be multiple of 2 */
#define ACCEL_CAL_ROUND (50)
#define ACCEL_CAL_SIMPLE (0)
#define ACCEL_CAL_INTERACT (1)
#if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC)
/* Reading_at_1g = Sensitivity * Max_reading / Refference_voltage */
#define ACCEL_CAL_1G_VALUE {993, 256}
#define ACCEL_CAL_1G_VALUE {993, 256}
#define ACCEL_X_ADC_CH ADC_SCANCTRL_INPUTMASK_CH2
#define ACCEL_Y_ADC_CH ADC_SCANCTRL_INPUTMASK_CH3
#define ACCEL_Z_ADC_CH ADC_SCANCTRL_INPUTMASK_CH4
#define ACCEL_X_ADC_CH ADC_SCANCTRL_INPUTMASK_CH2
#define ACCEL_Y_ADC_CH ADC_SCANCTRL_INPUTMASK_CH3
#define ACCEL_Z_ADC_CH ADC_SCANCTRL_INPUTMASK_CH4
#elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
#define ACCEL_CAL_1G_VALUE {0x3f, 0x1f, 0x0f}
#define ACCEL_CAL_1G_VALUE {0x3f, 0x1f, 0x0f}
#define ACCEL_IIC_SLAVE_ADDRESS (0x1d)
#define ACCEL_INT1_PORT (gpioPortD)
#define ACCEL_INT1_PIN (13)
#define ACCEL_INT2_PORT (gpioPortD)
#define ACCEL_INT2_PIN (12)
#define ACCEL_INT1_PORT (gpioPortD)
#define ACCEL_INT1_PIN (13)
#define ACCEL_INT2_PORT (gpioPortD)
#define ACCEL_INT2_PIN (12)
#define ACCEL_MODE_STANDBY (1 << 0)
#define ACCEL_MODE_MEASUREMENT (1 << 1)
#define ACCEL_MODE_LEVEL (1 << 2)
#define ACCEL_MODE_PULSE (1 << 3)
#define ACCEL_RANGE_8G (1 << 4)
#define ACCEL_RANGE_4G (1 << 5)
#define ACCEL_RANGE_2G (1 << 6)
#define ACCEL_INTPIN_INVERSE (1 << 7)
#define ACCEL_INT_LEVEL_PULSE (1 << 8)
#define ACCEL_INT_PULSE_LEVEL (1 << 9)
#define ACCEL_INT_SINGLE_DOUBLE (1 << 10)
#define ACCEL_DISABLE_X (1 << 11)
#define ACCEL_DISABLE_Y (1 << 12)
#define ACCEL_DISABLE_Z (1 << 13)
#define ACCEL_THRESHOLD_INTEGER (1 << 14) /* For level detection only */
#define ACCEL_BANDWIDTH_125HZ (1 << 15)
#define ACCEL_LEVEL_AND (1 << 16)
#define ACCEL_PULSE_AND (1 << 17)
#define ACCEL_DRIVE_STRONG (1 << 18)
#define ACCEL_SOURCE_LEVEL_X (1 << 19)
#define ACCEL_SOURCE_LEVEL_Y (1 << 20)
#define ACCEL_SOURCE_LEVEL_Z (1 << 21)
#define ACCEL_SOURCE_PULSE_X (1 << 22)
#define ACCEL_SOURCE_PULSE_Y (1 << 23)
#define ACCEL_SOURCE_PULSE_Z (1 << 24)
#define ACCEL_MODE_STANDBY (1 << 0)
#define ACCEL_MODE_MEASUREMENT (1 << 1)
#define ACCEL_MODE_LEVEL (1 << 2)
#define ACCEL_MODE_PULSE (1 << 3)
#define ACCEL_RANGE_8G (1 << 4)
#define ACCEL_RANGE_4G (1 << 5)
#define ACCEL_RANGE_2G (1 << 6)
#define ACCEL_INTPIN_INVERSE (1 << 7)
#define ACCEL_INT_LEVEL_PULSE (1 << 8)
#define ACCEL_INT_PULSE_LEVEL (1 << 9)
#define ACCEL_INT_SINGLE_DOUBLE (1 << 10)
#define ACCEL_DISABLE_X (1 << 11)
#define ACCEL_DISABLE_Y (1 << 12)
#define ACCEL_DISABLE_Z (1 << 13)
#define ACCEL_THRESHOLD_INTEGER (1 << 14) /* For level detection only */
#define ACCEL_BANDWIDTH_125HZ (1 << 15)
#define ACCEL_LEVEL_AND (1 << 16)
#define ACCEL_PULSE_AND (1 << 17)
#define ACCEL_DRIVE_STRONG (1 << 18)
#define ACCEL_SOURCE_LEVEL_X (1 << 19)
#define ACCEL_SOURCE_LEVEL_Y (1 << 20)
#define ACCEL_SOURCE_LEVEL_Z (1 << 21)
#define ACCEL_SOURCE_PULSE_X (1 << 22)
#define ACCEL_SOURCE_PULSE_Y (1 << 23)
#define ACCEL_SOURCE_PULSE_Z (1 << 24)
#define ACCEL_SHIFT_MODE (0)
#define ACCEL_SHIFT_RANGE (4)
#define ACCEL_SHIFT_INT (8)
#define ACCEL_SHIFT_DISABLE (11)
#define ACCEL_SHIFT_SOURCE (19)
#define ACCEL_SHIFT_MODE (0)
#define ACCEL_SHIFT_RANGE (4)
#define ACCEL_SHIFT_INT (8)
#define ACCEL_SHIFT_DISABLE (11)
#define ACCEL_SHIFT_SOURCE (19)
#define ACCEL_MASK_MODE (0X0000000f << ACCEL_SHIFT_MODE)
#define ACCEL_MASK_RANGE (0X00000007 << ACCEL_SHIFT_RANGE)
#define ACCEL_MASK_INT (0X00000007 << ACCEL_SHIFT_INT)
#define ACCEL_MASK_DISABLE (0X00000007 << ACCEL_SHIFT_DISABLE)
#define ACCEL_MASK_SOURCE (0X0000003f << ACCEL_SHIFT_SOURCE)
#define ACCEL_MASK_MODE (0X0000000f << ACCEL_SHIFT_MODE)
#define ACCEL_MASK_RANGE (0X00000007 << ACCEL_SHIFT_RANGE)
#define ACCEL_MASK_INT (0X00000007 << ACCEL_SHIFT_INT)
#define ACCEL_MASK_DISABLE (0X00000007 << ACCEL_SHIFT_DISABLE)
#define ACCEL_MASK_SOURCE (0X0000003f << ACCEL_SHIFT_SOURCE)
#endif
/* Exported functions ------------------------------------------------------- */
rt_err_t efm_accel_get_data(struct efm32_accel_result_t *data,
rt_bool_t lowResolution);
rt_bool_t lowResolution);
rt_err_t efm_accel_config(rt_uint32_t config,
rt_uint8_t level_threshold,
rt_uint8_t pulse_threshold,
rt_uint8_t pulse_duration,
rt_uint8_t pulse_latency,
rt_uint8_t pulse_duration2);
rt_uint8_t level_threshold,
rt_uint8_t pulse_threshold,
rt_uint8_t pulse_duration,
rt_uint8_t pulse_latency,
rt_uint8_t pulse_duration2);
rt_err_t efm_accel_auto_zero(rt_uint8_t mode, rt_tick_t period);
rt_err_t efm_accel_init(void);

40
bsp/efm32/dev_keys.c
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_keys.c
* @brief Keys driver of RT-Thread RTOS for EFM32
* @file dev_keys.c
* @brief Keys driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-12-29 onelife Initial creation for EFM32GG_DK3750 board
******************************************************************************/
@ -48,14 +48,14 @@ static rt_bool_t click;
/* Private functions ---------------------------------------------------------*/
/***************************************************************************//**
* @brief
* Keys interrupt handler
* Keys interrupt handler
*
* @details
*
* @note
*
* @param[in] device
* Pointer to device descriptor
* Pointer to device descriptor
******************************************************************************/
static void efm32_keys_isr(rt_device_t dev)
{
@ -158,18 +158,18 @@ static void efm32_keys_isr(rt_device_t dev)
/***************************************************************************//**
* @brief
* Keys timeout handler
* Keys timeout handler
*
* @details
*
* @note
*
* @param[in] param
* Parameter
* Parameter
******************************************************************************/
static void efm32_keys_timer_isr(void *param)
{
rt_uint16_t joystick;
rt_uint16_t joystick;
joystick = DVK_getJoystick();
@ -277,11 +277,11 @@ void efm32_hw_keys_init(void)
GPIO_IntConfig(KEYS_INT_PORT, KEYS_INT_PIN, true, true, true);
efm32_irq_hook_init_t hook;
hook.type = efm32_irq_type_gpio;
hook.unit = KEYS_INT_PIN;
hook.cbFunc = efm32_keys_isr;
hook.userPtr = RT_NULL;
efm32_irq_hook_register(&hook);
hook.type = efm32_irq_type_gpio;
hook.unit = KEYS_INT_PIN;
hook.cbFunc = efm32_keys_isr;
hook.userPtr = RT_NULL;
efm32_irq_hook_register(&hook);
if ((rt_uint8_t)KEYS_INT_PIN % 2)
{
@ -299,12 +299,12 @@ void efm32_hw_keys_init(void)
/* Enable DVK joystick interrupt */
DVK_enableInterrupt(BC_INTEN_JOYSTICK);
rt_timer_init(&joy.timer,
"joy_tmr",
efm32_keys_timer_isr,
RT_NULL,
KEYS_POLL_TIME,
RT_TIMER_FLAG_PERIODIC);
rt_timer_init(&joy.timer,
"joy_tmr",
efm32_keys_timer_isr,
RT_NULL,
KEYS_POLL_TIME,
RT_TIMER_FLAG_PERIODIC);
joy_dev.init = efm32_keys_init;
joy_dev.open = RT_NULL;

8
bsp/efm32/dev_keys.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_keys.h
* @brief Keys driver of RT-Thread RTOS for EFM32
* @file dev_keys.h
* @brief Keys driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-12-29 onelife Initial creation for EFM32GG_DK3750 board
******************************************************************************/
#ifndef __DEV_KEYS_H__

76
bsp/efm32/dev_lcd.c
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_lcd.c
* @brief LCD driver of RT-Thread RTOS for EFM32
* @file dev_lcd.c
* @brief LCD driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-12-16 onelife Initial creation of address mapped method (pixel
* drive) for EFM32GG_DK3750 board
* 2011-12-29 onelife Add direct drive method (frame buffer) support
@ -451,48 +451,48 @@ rt_err_t efm32_spiLcd_writeRegister(rt_uint8_t reg, rt_uint16_t data)
/***************************************************************************//**
* @brief
* Register LCD device
* Register LCD device
*
* @details
*
* @note
*
* @param[in] device
* Pointer to device descriptor
* Pointer to device descriptor
*
* @param[in] name
* Device name
* Device name
*
* @param[in] flag
* Configuration flags
* Configuration flags
*
* @param[in] iic
* Pointer to IIC device descriptor
* Pointer to IIC device descriptor
*
* @return
* Error code
* Error code
******************************************************************************/
rt_err_t efm32_spiLcd_register(
rt_device_t device,
const char *name,
rt_uint32_t flag,
void *data)
rt_device_t device,
const char *name,
rt_uint32_t flag,
void *data)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device != RT_NULL);
device->type = RT_Device_Class_Graphic;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = RT_NULL;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = efm32_spiLcd_control;
device->user_data = data;
device->type = RT_Device_Class_Graphic;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = RT_NULL;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = efm32_spiLcd_control;
device->user_data = data;
/* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
/* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
}
/***************************************************************************//**
@ -511,18 +511,18 @@ void efm32_spiLcd_init(void)
DMD_DisplayGeometry *geometry;
rt_uint32_t ret;
do
{
do
{
USART_InitSync_TypeDef init = USART_INITSYNC_DEFAULT;
/* Find SPI device */
lcd = rt_device_find(LCD_USING_DEVICE_NAME);
if (lcd == RT_NULL)
{
lcd_debug("LCD err: Can't find %s!\n", LCD_USING_DEVICE_NAME);
break;
}
lcd_debug("LCD: Find device %s\n", LCD_USING_DEVICE_NAME);
/* Find SPI device */
lcd = rt_device_find(LCD_USING_DEVICE_NAME);
if (lcd == RT_NULL)
{
lcd_debug("LCD err: Can't find %s!\n", LCD_USING_DEVICE_NAME);
break;
}
lcd_debug("LCD: Find device %s\n", LCD_USING_DEVICE_NAME);
/* Config CS pin */
usart = (struct efm32_usart_device_t *)(lcd->user_data);
@ -647,7 +647,7 @@ void efm32_spiLcd_init(void)
}
/* Init LCD info */
flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_TX;
flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_TX;
lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
lcd_info.bits_per_pixel = 16;
lcd_info.width = geometry->xSize;

8
bsp/efm32/dev_lcd.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_lcd.h
* @brief LCD driver of RT-Thread RTOS for EFM32
* @file dev_lcd.h
* @brief LCD driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-12-16 onelife Initial creation of address mapped method (pixel
* drive) for EFM32GG_DK3750 board
******************************************************************************/

138
bsp/efm32/dev_sflash.h
View File

@ -20,85 +20,85 @@
/* Exported types ------------------------------------------------------------*/
enum sflash_inst_type_t
{
/* Instruction only */
sflash_inst_wren = 0x00,
sflash_inst_wrdi,
sflash_inst_rdid_l,
sflash_inst_rdid_s,
sflash_inst_rdsr,
sflash_inst_wrsr,
sflash_inst_be,
sflash_inst_dp,
sflash_inst_rdp,
/* Instruction and address */
sflash_inst_wrlr,
sflash_inst_rdlr,
sflash_inst_read,
sflash_inst_potp,
sflash_inst_pp,
sflash_inst_difp,
sflash_inst_sse,
sflash_inst_se,
/* Instruction, address and dummy read */
sflash_inst_read_f,
sflash_inst_dofr,
sflash_inst_rotp
/* Instruction only */
sflash_inst_wren = 0x00,
sflash_inst_wrdi,
sflash_inst_rdid_l,
sflash_inst_rdid_s,
sflash_inst_rdsr,
sflash_inst_wrsr,
sflash_inst_be,
sflash_inst_dp,
sflash_inst_rdp,
/* Instruction and address */
sflash_inst_wrlr,
sflash_inst_rdlr,
sflash_inst_read,
sflash_inst_potp,
sflash_inst_pp,
sflash_inst_difp,
sflash_inst_sse,
sflash_inst_se,
/* Instruction, address and dummy read */
sflash_inst_read_f,
sflash_inst_dofr,
sflash_inst_rotp
};
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#define SFLASH_SPI_COMMAND_SKIP (1)
#define SFLASH_SPI_READ_SKIP (2)
#define SFLASH_SPI_COMMAND_SKIP (1)
#define SFLASH_SPI_READ_SKIP (2)
#define SFLASH_INST_CODE_WREN (0x06)
#define SFLASH_INST_CODE_WRDI (0x04)
#define SFLASH_INST_CODE_RDID_L (0x9F)
#define SFLASH_INST_CODE_RDID_S (0x9E)
#define SFLASH_INST_CODE_RDSR (0x05)
#define SFLASH_INST_CODE_WRSR (0x01)
#define SFLASH_INST_CODE_WRLR (0xE5)
#define SFLASH_INST_CODE_RDLR (0xE8)
#define SFLASH_INST_CODE_READ (0x03)
#define SFLASH_INST_CODE_READ_F (0x0B)
#define SFLASH_INST_CODE_DOFR (0x3B)
#define SFLASH_INST_CODE_ROTP (0x4B)
#define SFLASH_INST_CODE_POTP (0x42)
#define SFLASH_INST_CODE_PP (0x02)
#define SFLASH_INST_CODE_DIFP (0xA2)
#define SFLASH_INST_CODE_SSE (0x20)
#define SFLASH_INST_CODE_SE (0xD8)
#define SFLASH_INST_CODE_BE (0xC7)
#define SFLASH_INST_CODE_DP (0xB9)
#define SFLASH_INST_CODE_RDP (0xAB)
#define SFLASH_INST_CODE_WREN (0x06)
#define SFLASH_INST_CODE_WRDI (0x04)
#define SFLASH_INST_CODE_RDID_L (0x9F)
#define SFLASH_INST_CODE_RDID_S (0x9E)
#define SFLASH_INST_CODE_RDSR (0x05)
#define SFLASH_INST_CODE_WRSR (0x01)
#define SFLASH_INST_CODE_WRLR (0xE5)
#define SFLASH_INST_CODE_RDLR (0xE8)
#define SFLASH_INST_CODE_READ (0x03)
#define SFLASH_INST_CODE_READ_F (0x0B)
#define SFLASH_INST_CODE_DOFR (0x3B)
#define SFLASH_INST_CODE_ROTP (0x4B)
#define SFLASH_INST_CODE_POTP (0x42)
#define SFLASH_INST_CODE_PP (0x02)
#define SFLASH_INST_CODE_DIFP (0xA2)
#define SFLASH_INST_CODE_SSE (0x20)
#define SFLASH_INST_CODE_SE (0xD8)
#define SFLASH_INST_CODE_BE (0xC7)
#define SFLASH_INST_CODE_DP (0xB9)
#define SFLASH_INST_CODE_RDP (0xAB)
#define SFLASH_REPLY_LEN_WREN (0)
#define SFLASH_REPLY_LEN_WRDI (0)
#define SFLASH_REPLY_LEN_RDID_L (20)
#define SFLASH_REPLY_LEN_RDID_S (3)
#define SFLASH_REPLY_LEN_RDSR (1)
#define SFLASH_REPLY_LEN_WRSR (1)
#define SFLASH_REPLY_LEN_WRLR (1)
#define SFLASH_REPLY_LEN_RDLR (1)
#define SFLASH_REPLY_LEN_READ (-1)
#define SFLASH_REPLY_LEN_READ_F (-1)
#define SFLASH_REPLY_LEN_DOFR (-1)
#define SFLASH_REPLY_LEN_ROTP (65)
#define SFLASH_REPLY_LEN_POTP (65)
#define SFLASH_REPLY_LEN_PP (256)
#define SFLASH_REPLY_LEN_DIFP (256)
#define SFLASH_REPLY_LEN_SSE (0)
#define SFLASH_REPLY_LEN_SE (0)
#define SFLASH_REPLY_LEN_BE (0)
#define SFLASH_REPLY_LEN_DP (0)
#define SFLASH_REPLY_LEN_RDP (0)
#define SFLASH_REPLY_LEN_WREN (0)
#define SFLASH_REPLY_LEN_WRDI (0)
#define SFLASH_REPLY_LEN_RDID_L (20)
#define SFLASH_REPLY_LEN_RDID_S (3)
#define SFLASH_REPLY_LEN_RDSR (1)
#define SFLASH_REPLY_LEN_WRSR (1)
#define SFLASH_REPLY_LEN_WRLR (1)
#define SFLASH_REPLY_LEN_RDLR (1)
#define SFLASH_REPLY_LEN_READ (-1)
#define SFLASH_REPLY_LEN_READ_F (-1)
#define SFLASH_REPLY_LEN_DOFR (-1)
#define SFLASH_REPLY_LEN_ROTP (65)
#define SFLASH_REPLY_LEN_POTP (65)
#define SFLASH_REPLY_LEN_PP (256)
#define SFLASH_REPLY_LEN_DIFP (256)
#define SFLASH_REPLY_LEN_SSE (0)
#define SFLASH_REPLY_LEN_SE (0)
#define SFLASH_REPLY_LEN_BE (0)
#define SFLASH_REPLY_LEN_DP (0)
#define SFLASH_REPLY_LEN_RDP (0)
/* Exported functions ------------------------------------------------------- */
rt_err_t efm_spiFlash_init(void);
rt_err_t efm_spiFlash_deinit(void);
rt_uint32_t efm_spiFlash_cmd(
enum sflash_inst_type_t command,
rt_uint32_t address,
rt_uint8_t *buffer,
rt_uint32_t size);
enum sflash_inst_type_t command,
rt_uint32_t address,
rt_uint8_t *buffer,
rt_uint32_t size);
#endif /* __DEV_SFLASH_H__ */

432
bsp/efm32/drv_acmp.c
View File

@ -30,18 +30,18 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
#ifdef RT_ACMP_DEBUG
#define acmp_debug(format,args...) rt_kprintf(format, ##args)
#define acmp_debug(format,args...) rt_kprintf(format, ##args)
#else
#define acmp_debug(format,args...)
#endif
/* Private variables ---------------------------------------------------------*/
#ifdef RT_USING_ACMP0
static struct rt_device acmp0_device;
static struct rt_device acmp0_device;
#endif
#ifdef RT_USING_ACMP1
static struct rt_device acmp1_device;
static struct rt_device acmp1_device;
#endif
/* Private function prototypes -----------------------------------------------*/
@ -64,169 +64,169 @@ ACMP_WarmTime_TypeDef efm32_acmp_WarmTimeCalc(rt_uint32_t hfperFreq);
******************************************************************************/
static rt_err_t rt_acmp_init(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(dev != RT_NULL);
struct efm32_acmp_device_t *acmp;
struct efm32_acmp_device_t *acmp;
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
acmp->hook.cbFunc = RT_NULL;
acmp->hook.userPtr = RT_NULL;
acmp->hook.cbFunc = RT_NULL;
acmp->hook.userPtr = RT_NULL;
return RT_EOK;
return RT_EOK;
}
/***************************************************************************//**
* @brief
* Configure ACMP device
* Configure ACMP device
*
* @details
*
* @note
*
* @param[in] dev
* Pointer to device descriptor
* Pointer to device descriptor
*
* @param[in] cmd
* ACMP control command
* ACMP control command
*
* @param[in] args
* Arguments
* Arguments
*
* @return
* Error code
* Error code
******************************************************************************/
static rt_err_t rt_acmp_control(
rt_device_t dev,
rt_uint8_t cmd,
void *args)
rt_device_t dev,
rt_uint8_t cmd,
void *args)
{
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(dev != RT_NULL);
struct efm32_acmp_device_t *acmp;
struct efm32_acmp_device_t *acmp;
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
switch (cmd)
{
case RT_DEVICE_CTRL_SUSPEND:
/* Suspend device */
dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
ACMP_Disable(acmp->acmp_device);
break;
switch (cmd)
{
case RT_DEVICE_CTRL_SUSPEND:
/* Suspend device */
dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
ACMP_Disable(acmp->acmp_device);
break;
case RT_DEVICE_CTRL_RESUME:
/* Resume device */
dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
ACMP_Enable(acmp->acmp_device);
break;
case RT_DEVICE_CTRL_RESUME:
/* Resume device */
dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
ACMP_Enable(acmp->acmp_device);
break;
case RT_DEVICE_CTRL_ACMP_INIT:
{
rt_bool_t int_en = false;
struct efm32_acmp_control_t *control;
case RT_DEVICE_CTRL_ACMP_INIT:
{
rt_bool_t int_en = false;
struct efm32_acmp_control_t *control;
control = (struct efm32_acmp_control_t *)args;
acmp_debug("ACMP: control -> init start\n");
control = (struct efm32_acmp_control_t *)args;
acmp_debug("ACMP: control -> init start\n");
/* Configure ACMPn */
if (control->init == RT_NULL)
{
return -RT_ERROR;
}
ACMP_Init(acmp->acmp_device, control->init);
ACMP_ChannelSet(acmp->acmp_device, control->negInput, control->posInput);
if (control->output != RT_NULL)
{
ACMP_GPIOSetup(
acmp->acmp_device,
control->output->location,
control->output->enable,
control->output->invert);
int_en = true;
}
if (control->hook.cbFunc != RT_NULL)
{
acmp->hook.cbFunc = control->hook.cbFunc;
acmp->hook.userPtr = control->hook.userPtr;
int_en = true;
}
/* Configure ACMPn */
if (control->init == RT_NULL)
{
return -RT_ERROR;
}
ACMP_Init(acmp->acmp_device, control->init);
ACMP_ChannelSet(acmp->acmp_device, control->negInput, control->posInput);
if (control->output != RT_NULL)
{
ACMP_GPIOSetup(
acmp->acmp_device,
control->output->location,
control->output->enable,
control->output->invert);
int_en = true;
}
if (control->hook.cbFunc != RT_NULL)
{
acmp->hook.cbFunc = control->hook.cbFunc;
acmp->hook.userPtr = control->hook.userPtr;
int_en = true;
}
if (int_en)
{
/* Enable edge interrupt */
ACMP_IntEnable(acmp->acmp_device, ACMP_IEN_EDGE);
ACMP_IntClear(acmp->acmp_device, ACMP_IFC_EDGE);
if (int_en)
{
/* Enable edge interrupt */
ACMP_IntEnable(acmp->acmp_device, ACMP_IEN_EDGE);
ACMP_IntClear(acmp->acmp_device, ACMP_IFC_EDGE);
/* Enable ACMP0/1 interrupt vector in NVIC */
NVIC_ClearPendingIRQ(ACMP0_IRQn);
NVIC_SetPriority(ACMP0_IRQn, EFM32_IRQ_PRI_DEFAULT);
NVIC_EnableIRQ(ACMP0_IRQn);
}
}
break;
/* Enable ACMP0/1 interrupt vector in NVIC */
NVIC_ClearPendingIRQ(ACMP0_IRQn);
NVIC_SetPriority(ACMP0_IRQn, EFM32_IRQ_PRI_DEFAULT);
NVIC_EnableIRQ(ACMP0_IRQn);
}
}
break;
case RT_DEVICE_CTRL_ACMP_OUTPUT:
*((rt_bool_t *)args) = \
(acmp->acmp_device->STATUS & ACMP_STATUS_ACMPOUT) ? true : false;
break;
case RT_DEVICE_CTRL_ACMP_OUTPUT:
*((rt_bool_t *)args) = \
(acmp->acmp_device->STATUS & ACMP_STATUS_ACMPOUT) ? true : false;
break;
default:
return -RT_ERROR;
}
default:
return -RT_ERROR;
}
return RT_EOK;
return RT_EOK;
}
/***************************************************************************//**
* @brief
* Register ACMP device
* Register ACMP device
*
* @details
*
* @note
*
* @param[in] device
* Pointer to device descriptor
* Pointer to device descriptor
*
* @param[in] name
* Device name
* Device name
*
* @param[in] flag
* Configuration flags
* Configuration flags
*
* @param[in] acmp
* Pointer to ACMP device descriptor
* Pointer to ACMP device descriptor
*
* @return
* Error code
* Error code
******************************************************************************/
rt_err_t rt_hw_acmp_register(
rt_device_t device,
const char *name,
rt_uint32_t flag,
struct efm32_acmp_device_t *acmp)
rt_device_t device,
const char *name,
rt_uint32_t flag,
struct efm32_acmp_device_t *acmp)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device != RT_NULL);
device->type = RT_Device_Class_Char; /* fixme: should be acmp type */
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = rt_acmp_init;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = rt_acmp_control;
device->user_data = acmp;
device->type = RT_Device_Class_Char; /* fixme: should be acmp type */
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = rt_acmp_init;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = rt_acmp_control;
device->user_data = acmp;
/* register a character device */
return rt_device_register(device, name, flag);
/* register a character device */
return rt_device_register(device, name, flag);
}
/***************************************************************************//**
* @brief
* ACMP edge trigger interrupt handler
* ACMP edge trigger interrupt handler
*
* @details
*
@ -234,96 +234,96 @@ rt_err_t rt_hw_acmp_register(
******************************************************************************/
void rt_hw_acmp_isr(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(dev != RT_NULL);
struct efm32_acmp_device_t *acmp;
struct efm32_acmp_device_t *acmp;
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
if (acmp->hook.cbFunc != RT_NULL)
{
(acmp->hook.cbFunc)(acmp->hook.userPtr);
}
if (acmp->hook.cbFunc != RT_NULL)
{
(acmp->hook.cbFunc)(acmp->hook.userPtr);
}
}
/***************************************************************************//**
* @brief
* Initialize the specified ACMP unit
* Initialize the specified ACMP unit
*
* @details
*
* @note
*
* @param[in] device
* Pointer to device descriptor
* Pointer to device descriptor
*
* @param[in] unitNumber
* Unit number
* Unit number
*
* @return
* Pointer to ACMP device
* Pointer to ACMP device
******************************************************************************/
static struct efm32_acmp_device_t *rt_hw_acmp_unit_init(
rt_device_t device,
rt_uint8_t unitNumber)
rt_device_t device,
rt_uint8_t unitNumber)
{
struct efm32_acmp_device_t *acmp;
efm32_irq_hook_init_t hook;
CMU_Clock_TypeDef acmpClock;
struct efm32_acmp_device_t *acmp;
efm32_irq_hook_init_t hook;
CMU_Clock_TypeDef acmpClock;
do
{
/* Allocate device */
acmp = rt_malloc(sizeof(struct efm32_acmp_device_t));
if (acmp == RT_NULL)
{
acmp_debug("ACMP err: no mem for ACMP%d\n", unitNumber);
break;
}
do
{
/* Allocate device */
acmp = rt_malloc(sizeof(struct efm32_acmp_device_t));
if (acmp == RT_NULL)
{
acmp_debug("ACMP err: no mem for ACMP%d\n", unitNumber);
break;
}
/* Initialization */
if (unitNumber >= ACMP_COUNT)
{
break;
}
switch (unitNumber)
{
case 0:
acmp->acmp_device = ACMP0;
acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP0;
break;
/* Initialization */
if (unitNumber >= ACMP_COUNT)
{
break;
}
switch (unitNumber)
{
case 0:
acmp->acmp_device = ACMP0;
acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP0;
break;
case 1:
acmp->acmp_device = ACMP1;
acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP1;
break;
case 1:
acmp->acmp_device = ACMP1;
acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP1;
break;
default:
break;
}
default:
break;
}
/* Enable ACMP clock */
CMU_ClockEnable(acmpClock, true);
/* Enable ACMP clock */
CMU_ClockEnable(acmpClock, true);
/* Reset */
ACMP_Reset(acmp->acmp_device);
/* Reset */
ACMP_Reset(acmp->acmp_device);
/* Config interrupt and NVIC */
hook.type = efm32_irq_type_acmp;
hook.unit = unitNumber;
hook.cbFunc = rt_hw_acmp_isr;
hook.userPtr = device;
efm32_irq_hook_register(&hook);
/* Config interrupt and NVIC */
hook.type = efm32_irq_type_acmp;
hook.unit = unitNumber;
hook.cbFunc = rt_hw_acmp_isr;
hook.userPtr = device;
efm32_irq_hook_register(&hook);
return acmp;
} while(0);
return acmp;
} while(0);
if (acmp)
{
rt_free(acmp);
}
rt_kprintf("ACMP: Init failed!\n");
return RT_NULL;
if (acmp)
{
rt_free(acmp);
}
rt_kprintf("ACMP: Init failed!\n");
return RT_NULL;
}
/***************************************************************************//**
@ -338,20 +338,20 @@ static struct efm32_acmp_device_t *rt_hw_acmp_unit_init(
******************************************************************************/
void rt_hw_acmp_init(void)
{
struct efm32_acmp_device_t *acmp;
struct efm32_acmp_device_t *acmp;
#ifdef RT_USING_ACMP0
if ((acmp = rt_hw_acmp_unit_init(&acmp0_device, 0)) != RT_NULL)
{
rt_hw_acmp_register(&acmp0_device, RT_ACMP0_NAME, EFM32_NO_DATA, acmp);
}
if ((acmp = rt_hw_acmp_unit_init(&acmp0_device, 0)) != RT_NULL)
{
rt_hw_acmp_register(&acmp0_device, RT_ACMP0_NAME, EFM32_NO_DATA, acmp);
}
#endif
#ifdef RT_USING_ACMP1
if ((acmp = rt_hw_acmp_unit_init(&acmp1_device, 1)) != RT_NULL)
{
rt_hw_acmp_register(&acmp1_device, RT_ACMP1_NAME, EFM32_NO_DATA, acmp);
}
if ((acmp = rt_hw_acmp_unit_init(&acmp1_device, 1)) != RT_NULL)
{
rt_hw_acmp_register(&acmp1_device, RT_ACMP1_NAME, EFM32_NO_DATA, acmp);
}
#endif
}
@ -369,50 +369,50 @@ void rt_hw_acmp_init(void)
******************************************************************************/
ACMP_WarmTime_TypeDef efm32_acmp_WarmTimeCalc(rt_uint32_t hfperFreq)
{
if (!hfperFreq)
{
hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
if (!hfperFreq)
{
hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
/* Just in case, make sure we get non-zero freq for below calculation */
if (!hfperFreq)
{
hfperFreq = 1;
}
}
/* Just in case, make sure we get non-zero freq for below calculation */
if (!hfperFreq)
{
hfperFreq = 1;
}
}
/* Determine number of HFPERCLK cycle >= 10us */
if (4 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime4;
}
else if (8 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime8;
}
else if (16 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime16;
}
else if (32 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime32;
}
else if (64 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime64;
}
else if (128 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime128;
}
else if (256 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime256;
}
else if (512 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime512;
}
/* Determine number of HFPERCLK cycle >= 10us */
if (4 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime4;
}
else if (8 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime8;
}
else if (16 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime16;
}
else if (32 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime32;
}
else if (64 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime64;
}
else if (128 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime128;
}
else if (256 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime256;
}
else if (512 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime512;
}
}
#endif

20
bsp/efm32/drv_acmp.h
View File

@ -23,24 +23,24 @@
/* Exported types ------------------------------------------------------------*/
struct efm32_acmp_device_t
{
ACMP_TypeDef *acmp_device;
efm32_irq_hook_t hook;
ACMP_TypeDef *acmp_device;
efm32_irq_hook_t hook;
};
struct efm32_acmp_output_t
{
rt_uint32_t location;
rt_bool_t enable;
rt_bool_t invert;
rt_uint32_t location;
rt_bool_t enable;
rt_bool_t invert;
};
struct efm32_acmp_control_t
{
ACMP_Init_TypeDef *init;
ACMP_Channel_TypeDef posInput;
ACMP_Channel_TypeDef negInput;
struct efm32_acmp_output_t *output;
efm32_irq_hook_t hook;
ACMP_Init_TypeDef *init;
ACMP_Channel_TypeDef posInput;
ACMP_Channel_TypeDef negInput;
struct efm32_acmp_output_t *output;
efm32_irq_hook_t hook;
};
/* Exported constants --------------------------------------------------------*/

1114
bsp/efm32/drv_adc.c
View File

File diff suppressed because it is too large Load Diff

60
bsp/efm32/drv_adc.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file drv_adc.h
* @brief ADC driver of RT-Thread RTOS for EFM32
* @file drv_adc.h
* @brief ADC driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,9 +10,9 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-02-21 onelife Initial creation for EFM32
* 2011-07-14 onelife Add multiple channels support for scan mode
* Date Author Notes
* 2011-02-21 onelife Initial creation for EFM32
* 2011-07-14 onelife Add multiple channels support for scan mode
******************************************************************************/
#ifndef __DRV_ADC_H__
#define __DRV_ADC_H__
@ -21,50 +21,50 @@
/* Exported types ------------------------------------------------------------*/
struct efm32_adc_device_t
{
ADC_TypeDef *adc_device;
rt_uint8_t mode;
rt_uint8_t singleCount;
rt_uint8_t singleDmaChannel;
rt_uint8_t scanCount;
rt_uint8_t scanDmaChannel;
ADC_TypeDef *adc_device;
rt_uint8_t mode;
rt_uint8_t singleCount;
rt_uint8_t singleDmaChannel;
rt_uint8_t scanCount;
rt_uint8_t scanDmaChannel;
};
struct efm32_adc_control_single_t
{
rt_uint8_t count;
rt_uint8_t dmaChannel;
ADC_InitSingle_TypeDef *init;
rt_uint8_t count;
rt_uint8_t dmaChannel;
ADC_InitSingle_TypeDef *init;
};
struct efm32_adc_control_scan_t
{
rt_uint8_t count;
rt_uint8_t dmaChannel;
ADC_InitScan_TypeDef *init;
rt_uint8_t count;
rt_uint8_t dmaChannel;
ADC_InitScan_TypeDef *init;
};
struct efm32_adc_control_t
{
rt_uint8_t mode;
struct efm32_adc_control_scan_t scan;
struct efm32_adc_control_single_t single;
rt_uint8_t mode;
struct efm32_adc_control_scan_t scan;
struct efm32_adc_control_single_t single;
};
struct efm32_adc_result_t
{
rt_uint8_t mode;
void *buffer;
rt_uint8_t mode;
void *buffer;
};
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#define ADC_MODE_SINGLE (0x01)
#define ADC_MODE_SCAN (0x02)
#define ADC_MODE_TAILGATE (0x04)
#define ADC_OP_SINGLE_REPEAT (0x10)
#define ADC_OP_SCAN_REPEAT (0x20)
#define ADC_MASK_MODE (0x0f)
#define ADC_MASK_OP (0xf0)
#define ADC_MODE_SINGLE (0x01)
#define ADC_MODE_SCAN (0x02)
#define ADC_MODE_TAILGATE (0x04)
#define ADC_OP_SINGLE_REPEAT (0x10)
#define ADC_OP_SCAN_REPEAT (0x20)
#define ADC_MASK_MODE (0x0f)
#define ADC_MASK_OP (0xf0)
/* Exported functions ------------------------------------------------------- */
void rt_hw_adc_init(void);

28
bsp/efm32/drv_emu.c
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file drv_emu.c
* @brief EMU driver of RT-Thread RTOS for EFM32
* @file drv_emu.c
* @brief EMU driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,8 +10,8 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2012-02-21 onelife Initial creation for EFM32
* Date Author Notes
* 2012-02-21 onelife Initial creation for EFM32
******************************************************************************/
/***************************************************************************//**
@ -27,7 +27,7 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
#ifdef EFM32_EMU_DEBUG
#define emu_debug(format,args...) rt_kprintf(format, ##args)
#define emu_debug(format,args...) rt_kprintf(format, ##args)
#else
#define emu_debug(format,args...)
#endif
@ -176,7 +176,7 @@ void emu_em4_enable(void)
/***************************************************************************//**
* @brief
* Initialize EMU module related hardware
* Initialize EMU module related hardware
*
* @details
*
@ -213,22 +213,22 @@ void efm32_emu_init(void)
break;
}
/* init thread */
/* init thread */
if (rt_thread_init(
&emu_task.thread,
"EMU",
emu_task_main_loop, (void *)&emu_task,
emu_task_main_loop, (void *)&emu_task,
(void *)&emu_task.stack, sizeof(emu_task.stack),
RT_THREAD_PRIORITY_MAX - 2, RT_TICK_PER_SECOND) != RT_EOK)
RT_THREAD_PRIORITY_MAX - 2, RT_TICK_PER_SECOND) != RT_EOK)
{
break;
}
/* startup */
if (rt_thread_startup(&emu_task.thread) != RT_EOK)
{
/* startup */
if (rt_thread_startup(&emu_task.thread) != RT_EOK)
{
break;
}
}
} while (0);
rt_kprintf("EMU err: init failed!\n");

12
bsp/efm32/drv_emu.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file drv_emu.h
* @brief EMU driver of RT-Thread RTOS for EFM32
* @file drv_emu.h
* @brief EMU driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,9 +10,9 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-02-21 onelife Initial creation for EFM32
* 2011-07-14 onelife Add multiple channels support for scan mode
* Date Author Notes
* 2011-02-21 onelife Initial creation for EFM32
* 2011-07-14 onelife Add multiple channels support for scan mode
******************************************************************************/
#ifndef __DRV_EMU_H__
#define __DRV_EMU_H__

1514
bsp/efm32/drv_ethernet.c
View File

File diff suppressed because it is too large Load Diff

30
bsp/efm32/drv_ethernet.h
View File

@ -1,11 +1,11 @@
/***************************************************************************//**
* @file drv_ethernet.h
* @brief Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART
* @file drv_ethernet.h
* @brief Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART
* module
* This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet
* This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet
* controller with SPI interface.
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -13,8 +13,8 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-06-22 onelife Initial creation for using EFM32 USART module
* Date Author Notes
* 2011-06-22 onelife Initial creation for using EFM32 USART module
******************************************************************************/
#ifndef __DEV_ETHERNET_H__
#define __DEV_ETHERNET_H__
@ -25,18 +25,18 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#define ETH_ADDR_LEN (6)
#define ETH_CLK_MAX (10000000) /* Should be more than 8 Mz (Errata 1) */
#define ETH_ADDR_LEN (6)
#define ETH_CLK_MAX (10000000) /* Should be more than 8 Mz (Errata 1) */
//#define ETH_HALF_DUPLEX
#define ETH_PERIOD_WAIT_INIT (RT_TICK_PER_SECOND/100)
#define ETH_PERIOD_WAIT_TX (RT_TICK_PER_SECOND/100)
#define ETH_SPI_RX_SKIP (1)
#define ETH_PERIOD_WAIT_INIT (RT_TICK_PER_SECOND/100)
#define ETH_PERIOD_WAIT_TX (RT_TICK_PER_SECOND/100)
#define ETH_SPI_RX_SKIP (1)
#define ETH_RESET_PORT (gpioPortB)
#define ETH_RESET_PIN (9)
#define ETH_INT_PORT (gpioPortB)
#define ETH_INT_PIN (10)
#define ETH_RESET_PORT (gpioPortB)
#define ETH_RESET_PIN (9)
#define ETH_INT_PORT (gpioPortB)
#define ETH_INT_PIN (10)
/* Exported functions ------------------------------------------------------- */
rt_err_t efm_hw_eth_init(void);

1228
bsp/efm32/drv_leuart.c
View File

File diff suppressed because it is too large Load Diff

54
bsp/efm32/drv_leuart.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file drv_leuart.h
* @brief LEUART driver of RT-Thread RTOS for EFM32
* @file drv_leuart.h
* @brief LEUART driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,8 +10,8 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-12-09 onelife Initial creation for EFM32
* Date Author Notes
* 2011-12-09 onelife Initial creation for EFM32
******************************************************************************/
#ifndef __DRV_LEUSART_H__
#define __DRV_LEUSART_H__
@ -20,37 +20,37 @@
/* Exported types ------------------------------------------------------------*/
struct efm32_leuart_int_mode_t
{
rt_uint8_t *data_ptr;
rt_uint8_t data_size;
rt_uint32_t read_index, save_index;
rt_uint8_t *data_ptr;
rt_uint8_t data_size;
rt_uint32_t read_index, save_index;
};
struct efm32_leuart_dma_mode_t
{
/* DMA Channel */
rt_uint32_t dma_channel;
/* DMA Channel */
rt_uint32_t dma_channel;
/* buffer info */
rt_uint32_t *data_ptr;
rt_uint8_t data_size;
/* buffer info */
rt_uint32_t *data_ptr;
rt_uint8_t data_size;
};
struct efm32_leuart_device_t
{
/* Counter */
rt_uint32_t counter;
/* Lock */
struct rt_semaphore *lock;
/* Unit number */
rt_uint8_t unit;
/* State */
volatile rt_uint8_t state;
/* Pointer to LEUART device structure */
LEUART_TypeDef *leuart_device;
/* Pointer to RX structure */
void *rx_mode;
/* Pointer to TX structure */
void *tx_mode;
/* Counter */
rt_uint32_t counter;
/* Lock */
struct rt_semaphore *lock;
/* Unit number */
rt_uint8_t unit;
/* State */
volatile rt_uint8_t state;
/* Pointer to LEUART device structure */
LEUART_TypeDef *leuart_device;
/* Pointer to RX structure */
void *rx_mode;
/* Pointer to TX structure */
void *tx_mode;
};
/* Exported constants --------------------------------------------------------*/

114
bsp/efm32/drv_rtc.c
View File

@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2009-01-05 Bernard the first version
* 2010-12-27 onelife Modify for EFM32
* 2011-06-16 onelife Modify init function for efm32lib v2 upgrading
@ -33,7 +33,7 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
#ifdef RT_RTC_DEBUG
#define rtc_debug(format,args...) rt_kprintf(format, ##args)
#define rtc_debug(format,args...) rt_kprintf(format, ##args)
#else
#define rtc_debug(format,args...)
#endif
@ -55,10 +55,10 @@ static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag)
}
static rt_size_t rt_rtc_read(
rt_device_t dev,
rt_off_t pos,
void* buffer,
rt_size_t size)
rt_device_t dev,
rt_off_t pos,
void* buffer,
rt_size_t size)
{
return 0;
}
@ -91,16 +91,16 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
*(rt_uint32_t *)args = rtc_time + RTC_CounterGet();
rtc_debug("RTC: get rtc_time %x + %x\n", rtc_time, RTC_CounterGet());
rtc_debug("RTC: get rtc_time %x + %x\n", rtc_time, RTC_CounterGet());
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
{
rtc_time = *(rt_uint32_t *)args;
rtc_debug("RTC: set rtc_time %x\n", rtc_time);
rtc_debug("RTC: set rtc_time %x\n", rtc_time);
/* Reset counter */
RTC_CounterReset();
/* Reset counter */
RTC_CounterReset();
}
break;
}
@ -118,12 +118,12 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
******************************************************************************/
void rt_hw_rtc_isr(rt_device_t device)
{
if (RTC->IF & RTC_IFC_OF)
{
rtc_time += _RTC_CNT_MASK;
}
if (RTC->IF & RTC_IFC_OF)
{
rtc_time += _RTC_CNT_MASK;
}
RTC->IFC = _RTC_IFC_MASK;
RTC->IFC = _RTC_IFC_MASK;
}
/***************************************************************************//**
@ -147,25 +147,25 @@ void rt_hw_rtc_isr(rt_device_t device)
* Error code
******************************************************************************/
rt_err_t rt_hw_rtc_register(
rt_device_t device,
const char *name,
rt_uint32_t flag)
rt_device_t device,
const char *name,
rt_uint32_t flag)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device != RT_NULL);
device->type = RT_Device_Class_RTC;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = RT_NULL;
device->open = rt_rtc_open;
device->close = RT_NULL;
device->read = rt_rtc_read;
device->write = RT_NULL;
device->control = rt_rtc_control;
device->user_data = RT_NULL; /* no private */
device->type = RT_Device_Class_RTC;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = RT_NULL;
device->open = rt_rtc_open;
device->close = RT_NULL;
device->read = rt_rtc_read;
device->write = RT_NULL;
device->control = rt_rtc_control;
device->user_data = RT_NULL; /* no private */
/* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
/* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
}
@ -179,50 +179,50 @@ rt_err_t rt_hw_rtc_register(
******************************************************************************/
void rt_hw_rtc_init(void)
{
rt_uint32_t reset;
rt_uint32_t reset;
reset = RMU_ResetCauseGet();
reset = RMU_ResetCauseGet();
// TODO: What is the current reset mode?
if (reset & RMU_RSTCAUSE_PORST || reset & RMU_RSTCAUSE_EXTRST)
// TODO: What is the current reset mode?
if (reset & RMU_RSTCAUSE_PORST || reset & RMU_RSTCAUSE_EXTRST)
{
RTC_Init_TypeDef rtcInit;
efm32_irq_hook_init_t hook;
RTC_Init_TypeDef rtcInit;
efm32_irq_hook_init_t hook;
rtcInit.enable = true;
rtcInit.debugRun = false;
rtcInit.comp0Top = false;
rtcInit.enable = true;
rtcInit.debugRun = false;
rtcInit.comp0Top = false;
rtc_time = 0UL;
rtc_time = 0UL;
rt_kprintf("rtc is not configured\n");
rt_kprintf("please configure with set_date and set_time\n");
/* Configuring clock */
/* Configuring clock */
CMU_ClockDivSet(cmuClock_RTC,cmuClkDiv_32768);
CMU_ClockEnable(cmuClock_RTC, true);
/* Initialize and enable RTC */
RTC_Reset();
RTC_Init(&rtcInit);
/* Initialize and enable RTC */
RTC_Reset();
RTC_Init(&rtcInit);
hook.type = efm32_irq_type_rtc;
hook.unit = 0;
hook.cbFunc = rt_hw_rtc_isr;
hook.userPtr = RT_NULL;
efm32_irq_hook_register(&hook);
hook.type = efm32_irq_type_rtc;
hook.unit = 0;
hook.cbFunc = rt_hw_rtc_isr;
hook.userPtr = RT_NULL;
efm32_irq_hook_register(&hook);
/* Enabling Interrupt from RTC */
RTC_IntEnable(RTC_IFC_OF);
RTC_IntClear(RTC_IFC_OF);
/* Enabling Interrupt from RTC */
RTC_IntEnable(RTC_IFC_OF);
RTC_IntClear(RTC_IFC_OF);
NVIC_ClearPendingIRQ(RTC_IRQn);
NVIC_SetPriority(RTC_IRQn, EFM32_IRQ_PRI_DEFAULT);
NVIC_EnableIRQ(RTC_IRQn);
NVIC_ClearPendingIRQ(RTC_IRQn);
NVIC_SetPriority(RTC_IRQn, EFM32_IRQ_PRI_DEFAULT);
NVIC_EnableIRQ(RTC_IRQn);
}
/* register rtc device */
rt_hw_rtc_register(&rtc, RT_RTC_NAME, EFM32_NO_DATA);
rt_hw_rtc_register(&rtc, RT_RTC_NAME, EFM32_NO_DATA);
}
#endif

2
bsp/efm32/drv_rtc.h
View File

@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2009-01-05 Bernard the first version
* 2010-12-27 onelife Modification for EFM32
*********************************************************************/

76
bsp/efm32/drv_sdcard.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file drv_sdcard.h
* @brief Memory card driver (SPI mode) of RT-Thread RTOS for using EFM32
* @file drv_sdcard.h
* @brief Memory card driver (SPI mode) of RT-Thread RTOS for using EFM32
* USART module
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -11,9 +11,9 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-05-13 onelife Initial creation for using EFM32 USART module
* 2011-07-07 onelife Modify initialization function to return error code
* Date Author Notes
* 2011-05-13 onelife Initial creation for using EFM32 USART module
* 2011-07-07 onelife Modify initialization function to return error code
******************************************************************************/
#ifndef __DEV_SDCARD_H__
#define __DEV_SDCARD_H__
@ -33,43 +33,43 @@
#error "EFM32 SPI clock should not be more than (EFM32_HFXO_FREQUENCY/2)"
#endif
#define SD_SPEED_LOW (0)
#define SD_SPEED_HIGH (1)
#define SD_WAIT_PERIOD (RT_TICK_PER_SECOND)
#define SD_SPEED_LOW (0)
#define SD_SPEED_HIGH (1)
#define SD_WAIT_PERIOD (RT_TICK_PER_SECOND)
#define SD_SECTOR_SIZE_SHIFT (9)
#define SD_SECTOR_SIZE (1 << SD_SECTOR_SIZE_SHIFT)
#define SD_BLOCK_SIZE_CSD (16)
#define SD_BLOCK_SIZE_CID (16)
#define SD_BLOCK_SIZE_OCR (4)
#define SD_BLOCK_SIZE_SDSTAT (64)
#define SD_SECTOR_SIZE_SHIFT (9)
#define SD_SECTOR_SIZE (1 << SD_SECTOR_SIZE_SHIFT)
#define SD_BLOCK_SIZE_CSD (16)
#define SD_BLOCK_SIZE_CID (16)
#define SD_BLOCK_SIZE_OCR (4)
#define SD_BLOCK_SIZE_SDSTAT (64)
/* Card type definitions (CardType) */
#define CT_MMC (0x01)
#define CT_SD1 (0x02)
#define CT_SD2 (0x04)
#define CT_SDC (CT_SD1|CT_SD2)
#define CT_BLOCK (0x08)
#define CT_MMC (0x01)
#define CT_SD1 (0x02)
#define CT_SD2 (0x04)
#define CT_SDC (CT_SD1|CT_SD2)
#define CT_BLOCK (0x08)
/* Definitions for MMC/SDC command */
#define CMD0 (0) /* GO_IDLE_STATE */
#define CMD1 (1) /* SEND_OP_COND */
#define ACMD41 (41|0x80) /* SEND_OP_COND (SDC) */
#define CMD8 (8) /* SEND_IF_COND */
#define CMD9 (9) /* SEND_CSD */
#define CMD10 (10) /* SEND_CID */
#define CMD12 (12) /* STOP_TRANSMISSION */
#define ACMD13 (13|0x80) /* SD_STATUS (SDC) */
#define CMD16 (16) /* SET_BLOCKLEN */
#define CMD17 (17) /* READ_SINGLE_BLOCK */
#define CMD18 (18) /* READ_MULTIPLE_BLOCK */
#define CMD23 (23) /* SET_BLOCK_COUNT */
#define ACMD23 (23|0x80) /* SET_WR_BLK_ERASE_COUNT (SDC) */
#define CMD24 (24) /* WRITE_BLOCK */
#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */
#define CMD41 (41) /* SEND_OP_COND (ACMD) */
#define CMD55 (55) /* APP_CMD */
#define CMD58 (58) /* READ_OCR */
#define CMD0 (0) /* GO_IDLE_STATE */
#define CMD1 (1) /* SEND_OP_COND */
#define ACMD41 (41|0x80) /* SEND_OP_COND (SDC) */
#define CMD8 (8) /* SEND_IF_COND */
#define CMD9 (9) /* SEND_CSD */
#define CMD10 (10) /* SEND_CID */
#define CMD12 (12) /* STOP_TRANSMISSION */
#define ACMD13 (13|0x80) /* SD_STATUS (SDC) */
#define CMD16 (16) /* SET_BLOCKLEN */
#define CMD17 (17) /* READ_SINGLE_BLOCK */
#define CMD18 (18) /* READ_MULTIPLE_BLOCK */
#define CMD23 (23) /* SET_BLOCK_COUNT */
#define ACMD23 (23|0x80) /* SET_WR_BLK_ERASE_COUNT (SDC) */
#define CMD24 (24) /* WRITE_BLOCK */
#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */
#define CMD41 (41) /* SEND_OP_COND (ACMD) */
#define CMD55 (55) /* APP_CMD */
#define CMD58 (58) /* READ_OCR */
/* Exported functions ------------------------------------------------------- */
rt_err_t efm_spiSd_init(void);

2
bsp/efm32/drv_timer.c
View File

@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-01-18 onelife Initial creation for EFM32
* 2011-06-17 onelife Modify init function for efm32lib v2 upgrading
******************************************************************************/

4
bsp/efm32/drv_usart.c
View File

@ -34,9 +34,9 @@
* 2011-12-20 onelife Add 9-bit SPI mode support
* 2011-12-20 onelife Change SPI write format (same as SPI read)
* 2011-12-20 onelife Change USART status format
* 2011-12-27 onelife Utilize "USART_PRESENT", "USART_COUNT",
* 2011-12-27 onelife Utilize "USART_PRESENT", "USART_COUNT",
* "UART_PRESENT" and "UART_COUNT"
* 2012-05-16 onelife Fix a bug in rt_hw_usart_init()
* 2012-05-16 onelife Fix a bug in rt_hw_usart_init()
******************************************************************************/
/***************************************************************************//**

42
bsp/efm32/enc28j60.h
View File

@ -197,9 +197,9 @@
#define MACON3_FRMLNEN 0x02
#define MACON3_FULDPX 0x01
// ENC28J60 MACON4 Register Bit Definitions
#define MACON4_DEFER (1<<6)
#define MACON4_BPEN (1<<5)
#define MACON4_NOBKOFF (1<<4)
#define MACON4_DEFER (1<<6)
#define MACON4_BPEN (1<<5)
#define MACON4_NOBKOFF (1<<4)
// ENC28J60 MICMD Register Bit Definitions
#define MICMD_MIISCAN 0x02
#define MICMD_MIIRD 0x01
@ -218,12 +218,12 @@
#define PHSTAT1_LLSTAT 0x0004
#define PHSTAT1_JBSTAT 0x0002
/* ENC28J60 PHY PHSTAT2 Register Bit Definitions */
#define PHSTAT2_TXSTAT (1 << 13)
#define PHSTAT2_RXSTAT (1 << 12)
#define PHSTAT2_COLSTAT (1 << 11)
#define PHSTAT2_LSTAT (1 << 10)
#define PHSTAT2_DPXSTAT (1 << 9)
#define PHSTAT2_PLRITY (1 << 5)
#define PHSTAT2_TXSTAT (1 << 13)
#define PHSTAT2_RXSTAT (1 << 12)
#define PHSTAT2_COLSTAT (1 << 11)
#define PHSTAT2_LSTAT (1 << 10)
#define PHSTAT2_DPXSTAT (1 << 9)
#define PHSTAT2_PLRITY (1 << 5)
// ENC28J60 PHY PHCON2 Register Bit Definitions
#define PHCON2_FRCLINK 0x4000
#define PHCON2_TXDIS 0x2000
@ -282,13 +282,13 @@
#define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0)
// SPI operation codes
#define ENC28J60_READ_CTRL_REG (0x00)
#define ENC28J60_READ_BUF_MEM (0x20 | 0x1A)
#define ENC28J60_WRITE_CTRL_REG (0x40)
#define ENC28J60_WRITE_BUF_MEM (0x60 | 0x1A)
#define ENC28J60_BIT_FIELD_SET (0x80)
#define ENC28J60_BIT_FIELD_CLR (0xA0)
#define ENC28J60_SOFT_RESET (0xE0 | 0x1F)
#define ENC28J60_READ_CTRL_REG (0x00)
#define ENC28J60_READ_BUF_MEM (0x20 | 0x1A)
#define ENC28J60_WRITE_CTRL_REG (0x40)
#define ENC28J60_WRITE_BUF_MEM (0x60 | 0x1A)
#define ENC28J60_BIT_FIELD_SET (0x80)
#define ENC28J60_BIT_FIELD_CLR (0xA0)
#define ENC28J60_SOFT_RESET (0xE0 | 0x1F)
// The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
// buffer boundaries applied to internal 8K ram
@ -296,17 +296,17 @@
//
// start with recbuf at 0/
#define RXSTART_INIT 0x0
#define RXSTART_INIT 0x0
// receive buffer end
#define RXSTOP_INIT (0x1FFF - 0x0600 - 1)
#define RXSTOP_INIT (0x1FFF - 0x0600 - 1)
// start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes)
#define TXSTART_INIT (0x1FFF - 0x0600)
#define TXSTART_INIT (0x1FFF - 0x0600)
// stp TX buffer at end of mem
#define TXSTOP_INIT 0x1FFF
#define TXSTOP_INIT 0x1FFF
// max frame length which the conroller will accept:
#define MAX_FRAMELEN 1518
#define MAX_FRAMELEN 1518
void rt_hw_enc28j60_init(void);

4
bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119.h
View File

@ -130,8 +130,8 @@ EMSTATUS DMD_writeData(uint16_t x, uint16_t y,
EMSTATUS DMD_writeDataRLE(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen,
const uint8_t *data);
EMSTATUS DMD_writeDataRLEFade(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen,
const uint8_t *data,
int red, int green, int blue, int weight);
const uint8_t *data,
int red, int green, int blue, int weight);
EMSTATUS DMD_readData(uint16_t x, uint16_t y,
uint8_t data[], uint32_t numPixels);
EMSTATUS DMD_writeColor(uint16_t x, uint16_t y, uint8_t red,

4
bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119_16bit.c
View File

@ -425,8 +425,8 @@ EMSTATUS DMD_writeData(uint16_t x, uint16_t y, const uint8_t data[],
* DMD_OK on success, otherwise error code
******************************************************************************/
EMSTATUS DMD_writeDataRLEFade(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen,
const uint8_t *data,
int red, int green, int blue, int weight)
const uint8_t *data,
int red, int green, int blue, int weight)
{
uint32_t color = 0;
int xpos, ypos;

8
bsp/efm32/graphics/tftspi.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file tftspi.h
* @brief Stub functions of EFM32 LCD driver
* @file tftspi.h
* @brief Stub functions of EFM32 LCD driver
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-12-20 onelife Initial creation for EFM32
******************************************************************************/
#ifndef __TFTSPI_H__

672
bsp/efm32/hdl_interrupt.c
View File

File diff suppressed because it is too large Load Diff

28
bsp/efm32/hdl_interrupt.h
View File

@ -21,31 +21,31 @@
/* Exported types ------------------------------------------------------------*/
enum efm32_irq_hook_type_t
{
efm32_irq_type_dma = 0,
efm32_irq_type_rtc,
efm32_irq_type_timer,
efm32_irq_type_dma = 0,
efm32_irq_type_rtc,
efm32_irq_type_timer,
efm32_irq_type_letimer,
efm32_irq_type_gpio,
efm32_irq_type_acmp,
efm32_irq_type_usart,
efm32_irq_type_leuart,
efm32_irq_type_iic
efm32_irq_type_gpio,
efm32_irq_type_acmp,
efm32_irq_type_usart,
efm32_irq_type_leuart,
efm32_irq_type_iic
};
typedef void (*efm32_irq_callback_t)(rt_device_t device);
typedef struct
{
enum efm32_irq_hook_type_t type;
rt_uint8_t unit;
efm32_irq_callback_t cbFunc;
void *userPtr;
enum efm32_irq_hook_type_t type;
rt_uint8_t unit;
efm32_irq_callback_t cbFunc;
void *userPtr;
} efm32_irq_hook_init_t;
typedef struct
{
efm32_irq_callback_t cbFunc;
void *userPtr;
efm32_irq_callback_t cbFunc;
void *userPtr;
} efm32_irq_hook_t;
/* Exported constants --------------------------------------------------------*/

56
bsp/efm32/httpd.c
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file httpd.c
* @brief Simple http server demo application
* @file httpd.c
* @brief Simple http server demo application
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,8 +10,8 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-07-04 onelife Derive from Energy Micro demo application
* Date Author Notes
* 2011-07-04 onelife Derive from Energy Micro demo application
******************************************************************************/
/**************************************************************************//**
@ -94,29 +94,29 @@
static int temp, vdd;
static char indexdata[700];
static const char indexdata1[] =
"HTTP/1.0 200 OK\r\n\
Content-type: text/html\r\n\
Pragma: no-cache\r\n\
Refresh: 5\r\n\
\r\n\
<html>\
<head><title>EFM32 HTTPD DEMO</title><head>\
<body>\
<h1>This is a simple http server</h1>\
<br><br><B>Ethernet controller: ENC28J60</B>\
<br><br><B>Refreshing timers: ";
"HTTP/1.0 200 OK\r\n\
Content-type: text/html\r\n\
Pragma: no-cache\r\n\
Refresh: 5\r\n\
\r\n\
<html>\
<head><title>EFM32 HTTPD DEMO</title><head>\
<body>\
<h1>This is a simple http server</h1>\
<br><br><B>Ethernet controller: ENC28J60</B>\
<br><br><B>Refreshing timers: ";
static const char indexdata2[] =
"<br><br><B>Current Vdd: ";
"<br><br><B>Current Vdd: ";
static const char indexdata3[] =
" V</B>\
<br><br><B>Current temperature: ";
" V</B>\
<br><br><B>Current temperature: ";
static const char indexdata4[] =
" C</B>\
</body>\
</html>";
" C</B>\
</body>\
</html>";
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
@ -169,9 +169,9 @@ static err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err
counter++;
}
vdd = rt_hw_get_vdd();
rt_sprintf(&indexdata[counter], "%1d.%02d", vdd / 100, vdd % 100);
counter += 4;
vdd = rt_hw_get_vdd();
rt_sprintf(&indexdata[counter], "%1d.%02d", vdd / 100, vdd % 100);
counter += 4;
for (i = 0; i < sizeof(indexdata3) - 1; i++)
{
@ -179,15 +179,15 @@ static err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err
counter++;
}
temp = rt_hw_get_temp();
temp = rt_hw_get_temp();
/*Set temperature sign*/
if (temp < 0)
{
indexdata[counter] = '-';
counter++;
}
rt_sprintf(&indexdata[counter], "%02d.%02d\n", temp / 100, temp % 100);
counter += 5;
rt_sprintf(&indexdata[counter], "%02d.%02d\n", temp / 100, temp % 100);
counter += 5;
for (i = 0; i < sizeof(indexdata4); i++)
{

170
bsp/efm32/mma7455l.h
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* @file mma7455l.c
* @brief Header file of Freescale MMA7455L 3 axis Low-g digital output
* @file mma7455l.c
* @brief Header file of Freescale MMA7455L 3 axis Low-g digital output
* accelerometer
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -11,101 +11,101 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-08-02 onelife Initial creation
* Date Author Notes
* 2011-08-02 onelife Initial creation
******************************************************************************/
#ifndef __MMA7455L_H__
#define __MMA7455L_H__
#define XOUTL 0x00 //00 10 bits output value X LSB (Read only)
#define XOUTH 0x01 //01 10 bits output value X MSB (Read only)
#define YOUTL 0x02 //02 10 bits output value Y LSB (Read only)
#define YOUTH 0x03 //03 10 bits output value Y MSB (Read only)
#define ZOUTL 0x04 //04 10 bits output value Z LSB (Read only)
#define ZOUTH 0x05 //05 10 bits output value Z MSB (Read only)
#define XOUT8 0x06 //06 8 bits Output value X (Read only)
#define YOUT8 0x07 //07 8 bits Output value Y (Read only)
#define ZOUT8 0x08 //08 8 bits Output value Z (Read only)
#define STATUS 0x09 //09 Status registers (Read only)
#define DETSRC 0x0A //10 Detection source registers (Read only)
#define TOUT 0x0B //11 Temperature output value (Optional)
#define RESERVED1 0x0C //12 Reserved
#define I2CAD 0x0D //13 I2C device address (Bit[6:0]: Read only, Bit[7]: Read/Write)
#define USRINF 0x0E //14 User information (Optional, Read only)
#define WHOAMI 0x0F //15 Who am I value (Optional, Read only)
#define XOFFL 0x10 //16 Offset drift X value (LSB) (Read/Write)
#define XOFFH 0x11 //17 Offset drift X value (MSB) (Read/Write)
#define YOFFL 0x12 //18 Offset drift Y value (LSB) (Read/Write)
#define YOFFH 0x13 //19 Offset drift Y value (MSB) (Read/Write)
#define ZOFFL 0x14 //20 Offset drift Z value (LSB) (Read/Write)
#define ZOFFH 0x15 //21 Offset drift Z value (MSB) (Read/Write)
#define MCTL 0x16 //22 Mode control (Read/Write)
#define INTRST 0x17 //23 Interrupt latch reset (Read/Write)
#define CTL1 0x18 //24 Control 1 (Read/Write)
#define CTL2 0x19 //25 Control 2 (Read/Write)
#define LDTH 0x1A //26 Level detection threshold limit value (Read/Write)
#define PDTH 0x1B //27 Pulse detection threshold limit value (Read/Write)
#define PW 0x1C //28 Pulse duration value (Read/Write)
#define LT 0x1D //29 Latency time value (Read/Write)
#define TW 0x1E //30 Time window for second pulse value(Read/Write)
#define RESERVED2 0x1F //31 Reserved
#define XOUTL 0x00 //00 10 bits output value X LSB (Read only)
#define XOUTH 0x01 //01 10 bits output value X MSB (Read only)
#define YOUTL 0x02 //02 10 bits output value Y LSB (Read only)
#define YOUTH 0x03 //03 10 bits output value Y MSB (Read only)
#define ZOUTL 0x04 //04 10 bits output value Z LSB (Read only)
#define ZOUTH 0x05 //05 10 bits output value Z MSB (Read only)
#define XOUT8 0x06 //06 8 bits Output value X (Read only)
#define YOUT8 0x07 //07 8 bits Output value Y (Read only)
#define ZOUT8 0x08 //08 8 bits Output value Z (Read only)
#define STATUS 0x09 //09 Status registers (Read only)
#define DETSRC 0x0A //10 Detection source registers (Read only)
#define TOUT 0x0B //11 Temperature output value (Optional)
#define RESERVED1 0x0C //12 Reserved
#define I2CAD 0x0D //13 I2C device address (Bit[6:0]: Read only, Bit[7]: Read/Write)
#define USRINF 0x0E //14 User information (Optional, Read only)
#define WHOAMI 0x0F //15 Who am I value (Optional, Read only)
#define XOFFL 0x10 //16 Offset drift X value (LSB) (Read/Write)
#define XOFFH 0x11 //17 Offset drift X value (MSB) (Read/Write)
#define YOFFL 0x12 //18 Offset drift Y value (LSB) (Read/Write)
#define YOFFH 0x13 //19 Offset drift Y value (MSB) (Read/Write)
#define ZOFFL 0x14 //20 Offset drift Z value (LSB) (Read/Write)
#define ZOFFH 0x15 //21 Offset drift Z value (MSB) (Read/Write)
#define MCTL 0x16 //22 Mode control (Read/Write)
#define INTRST 0x17 //23 Interrupt latch reset (Read/Write)
#define CTL1 0x18 //24 Control 1 (Read/Write)
#define CTL2 0x19 //25 Control 2 (Read/Write)
#define LDTH 0x1A //26 Level detection threshold limit value (Read/Write)
#define PDTH 0x1B //27 Pulse detection threshold limit value (Read/Write)
#define PW 0x1C //28 Pulse duration value (Read/Write)
#define LT 0x1D //29 Latency time value (Read/Write)
#define TW 0x1E //30 Time window for second pulse value(Read/Write)
#define RESERVED2 0x1F //31 Reserved
/* For DETSRC */
#define DETSRC_INT_1 (0x01 << 0)
#define DETSRC_INT_2 (0x01 << 1)
#define DETSRC_PULSE_Z (0x01 << 2)
#define DETSRC_PULSE_Y (0x01 << 3)
#define DETSRC_PULSE_X (0x01 << 4)
#define DETSRC_LEVEL_Z (0x01 << 5)
#define DETSRC_LEVEL_Y (0x01 << 6)
#define DETSRC_LEVEL_X (0x01 << 7)
#define DETSRC_INT_1 (0x01 << 0)
#define DETSRC_INT_2 (0x01 << 1)
#define DETSRC_PULSE_Z (0x01 << 2)
#define DETSRC_PULSE_Y (0x01 << 3)
#define DETSRC_PULSE_X (0x01 << 4)
#define DETSRC_LEVEL_Z (0x01 << 5)
#define DETSRC_LEVEL_Y (0x01 << 6)
#define DETSRC_LEVEL_X (0x01 << 7)
/* For MCTL */
#define MCTL_SHIFT_MODE (0)
#define MCTL_SHIFT_G (2)
#define MCTL_MASK_MODE (0x03)
#define MCTL_MASK_G (0x0c)
#define MCTL_MODE_STANDBY (0x00 << MCTL_SHIFT_MODE)
#define MCTL_MODE_MEASUREMENT (0x01 << MCTL_SHIFT_MODE)
#define MCTL_MODE_LEVEL (0x02 << MCTL_SHIFT_MODE)
#define MCTL_MODE_PULSE (0x03 << MCTL_SHIFT_MODE)
#define MCTL_RANGE_8G (0x00 << MCTL_SHIFT_G)
#define MCTL_RANGE_4G (0x02 << MCTL_SHIFT_G)
#define MCTL_RANGE_2G (0x01 << MCTL_SHIFT_G)
#define MCTL_PIN_INT1 (0x01 << 6)
#define MCTL_SHIFT_MODE (0)
#define MCTL_SHIFT_G (2)
#define MCTL_MASK_MODE (0x03)
#define MCTL_MASK_G (0x0c)
#define MCTL_MODE_STANDBY (0x00 << MCTL_SHIFT_MODE)
#define MCTL_MODE_MEASUREMENT (0x01 << MCTL_SHIFT_MODE)
#define MCTL_MODE_LEVEL (0x02 << MCTL_SHIFT_MODE)
#define MCTL_MODE_PULSE (0x03 << MCTL_SHIFT_MODE)
#define MCTL_RANGE_8G (0x00 << MCTL_SHIFT_G)
#define MCTL_RANGE_4G (0x02 << MCTL_SHIFT_G)
#define MCTL_RANGE_2G (0x01 << MCTL_SHIFT_G)
#define MCTL_PIN_INT1 (0x01 << 6)
/* For INTRST */
#define INTRST_INT_1 (0x01 << 0)
#define INTRST_INT_2 (0x01 << 1)
#define INTRST_INT_1 (0x01 << 0)
#define INTRST_INT_2 (0x01 << 1)
/* For CTL1 */
#define CTL1_SHIFT_INTPIN (0)
#define CTL1_SHIFT_INT (1)
#define CTL1_SHIFT_AXES (3)
#define CTL1_SHIFT_THRESHOLD (6)
#define CTL1_SHIFT_BANDWIDTH (7)
#define CTL1_MASK_AXES (0x38)
#define CTL1_INTPIN_INVERSE (0x01 << CTL1_SHIFT_INTPIN)
#define CTL1_INT_LEVEL_PULSE (0x00 << CTL1_SHIFT_INT)
#define CTL1_INT_PULSE_LEVEL (0x01 << CTL1_SHIFT_INT)
#define CTL1_INT_SINGLE_DOUBLE (0x02 << CTL1_SHIFT_INT)
#define CTL1_X_DISABLE (0x01 << CTL1_SHIFT_AXES)
#define CTL1_Y_DISABLE (0x02 << CTL1_SHIFT_AXES)
#define CTL1_Z_DISABLE (0x04 << CTL1_SHIFT_AXES)
#define CTL1_THRESHOLD_ABSOLUTE (0x00 << CTL1_SHIFT_THRESHOLD)
#define CTL1_THRESHOLD_INTEGER (0x01 << CTL1_SHIFT_THRESHOLD)
#define CTL1_BANDWIDTH_62_5HZ (0x00 << CTL1_SHIFT_BANDWIDTH)
#define CTL1_BANDWIDTH_125HZ (0x01 << CTL1_SHIFT_BANDWIDTH)
#define CTL1_SHIFT_INTPIN (0)
#define CTL1_SHIFT_INT (1)
#define CTL1_SHIFT_AXES (3)
#define CTL1_SHIFT_THRESHOLD (6)
#define CTL1_SHIFT_BANDWIDTH (7)
#define CTL1_MASK_AXES (0x38)
#define CTL1_INTPIN_INVERSE (0x01 << CTL1_SHIFT_INTPIN)
#define CTL1_INT_LEVEL_PULSE (0x00 << CTL1_SHIFT_INT)
#define CTL1_INT_PULSE_LEVEL (0x01 << CTL1_SHIFT_INT)
#define CTL1_INT_SINGLE_DOUBLE (0x02 << CTL1_SHIFT_INT)
#define CTL1_X_DISABLE (0x01 << CTL1_SHIFT_AXES)
#define CTL1_Y_DISABLE (0x02 << CTL1_SHIFT_AXES)
#define CTL1_Z_DISABLE (0x04 << CTL1_SHIFT_AXES)
#define CTL1_THRESHOLD_ABSOLUTE (0x00 << CTL1_SHIFT_THRESHOLD)
#define CTL1_THRESHOLD_INTEGER (0x01 << CTL1_SHIFT_THRESHOLD)
#define CTL1_BANDWIDTH_62_5HZ (0x00 << CTL1_SHIFT_BANDWIDTH)
#define CTL1_BANDWIDTH_125HZ (0x01 << CTL1_SHIFT_BANDWIDTH)
/* For CTL2 */
#define CTL1_SHIFT_LEVEL (0)
#define CTL1_SHIFT_PULSE (1)
#define CTL1_SHIFT_DRIVE (2)
#define CTL2_LEVEL_OR (0x00 << CTL1_SHIFT_LEVEL)
#define CTL2_LEVEL_AND (0x01 << CTL1_SHIFT_LEVEL)
#define CTL2_PULSE_OR (0x00 << CTL1_SHIFT_PULSE)
#define CTL2_PULSE_AND (0x01 << CTL1_SHIFT_PULSE)
#define CTL2_DRIVE_STANDARD (0x00 << CTL1_SHIFT_DRIVE)
#define CTL2_DRIVE_STRONG (0x01 << CTL1_SHIFT_DRIVE)
#define CTL1_SHIFT_LEVEL (0)
#define CTL1_SHIFT_PULSE (1)
#define CTL1_SHIFT_DRIVE (2)
#define CTL2_LEVEL_OR (0x00 << CTL1_SHIFT_LEVEL)
#define CTL2_LEVEL_AND (0x01 << CTL1_SHIFT_LEVEL)
#define CTL2_PULSE_OR (0x00 << CTL1_SHIFT_PULSE)
#define CTL2_PULSE_AND (0x01 << CTL1_SHIFT_PULSE)
#define CTL2_DRIVE_STANDARD (0x00 << CTL1_SHIFT_DRIVE)
#define CTL2_DRIVE_STRONG (0x01 << CTL1_SHIFT_DRIVE)
#endif /* __MMA7455L_H__ */

128
bsp/efm32/rtconfig.h
View File

@ -1,7 +1,7 @@
/***************************************************************************//**
* @file rtconfig.h
* @brief RT-Thread config file
* COPYRIGHT (C) 2009, RT-Thread Development Team
* COPYRIGHT (C) 2009, RT-Thread Development Team
* @author
* @version 1.0
*******************************************************************************
@ -22,23 +22,23 @@
#define EFM32GG_DK3750
/* RT_NAME_MAX */
#define RT_NAME_MAX (8)
#define RT_NAME_MAX (8)
/* RT_ALIGN_SIZE */
#define RT_ALIGN_SIZE (4)
#define RT_ALIGN_SIZE (4)
/* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX (32)
#define RT_THREAD_PRIORITY_MAX (32)
/* Tick per Second */
#define RT_TICK_PER_SECOND (100)
#define RT_TICK_PER_SECOND (100)
/* SECTION: RT_DEBUG */
#define RT_DEBUG
#define RT_DEBUG_COLOR
//#define RT_DEBUG_MEM (1)
//#define RT_DEBUG_SCHEDULER (1)
//#define RT_DEBUG_IPC (1)
//#define RT_DEBUG_MEM (1)
//#define RT_DEBUG_SCHEDULER (1)
//#define RT_DEBUG_IPC (1)
//#define THREAD_DEBUG
//#define IRQ_DEBUG
#define RT_USING_OVERFLOW_CHECK
@ -69,9 +69,9 @@
/* Using Software Timer */
/* #define RT_USING_TIMER_SOFT */
#define RT_TIMER_THREAD_PRIO (4)
#define RT_TIMER_THREAD_STACK_SIZE (512)
#define RT_TIMER_TICK_PER_SECOND (10)
#define RT_TIMER_THREAD_PRIO (4)
#define RT_TIMER_THREAD_STACK_SIZE (512)
#define RT_TIMER_TICK_PER_SECOND (10)
/* SECTION: IPC */
/* Using Semaphore*/
@ -134,10 +134,10 @@
#define EFM32_SPI_CLK_MODE(mode) (mode << 3) /* clock mode */
#if defined(EFM32_G8XX_STK)
//#define RT_USING_USART0 (0x0UL)
//#define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER)
//#define RT_USART0_NAME "spi0"
//#define RT_USART0_USING_DMA (0x1UL)
//#define RT_USING_USART0 (0x0UL)
//#define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER)
//#define RT_USART0_NAME "spi0"
//#define RT_USART0_USING_DMA (0x1UL)
#elif defined(EFM32_GXXX_DK)
#define RT_USING_USART0 (0x2UL)
#define RT_USART0_SYNC_MODE (EFM32_SPI_MASTER | EFM32_SPI_AUTOCS | \
@ -165,28 +165,28 @@
#endif
/* SECTION: IIC options */
//#define RT_USING_IIC0 0x3UL
#define RT_IIC0_NAME "iic0"
//#define RT_USING_IIC0 0x3UL
#define RT_IIC0_NAME "iic0"
/* SECTION: ACMP options */
//#define RT_USING_ACMP0
#define RT_ACMP0_NAME "acmp0"
#define RT_ACMP0_NAME "acmp0"
/* SECTION: ADC options */
#define RT_USING_ADC0
#define RT_ADC0_NAME "adc0"
#define RT_ADC0_NAME "adc0"
#if defined(RT_USING_ADC0)
#define RT_USING_MISC
#endif
/* SECTION: TIMER options */
//#define RT_USING_TIMER2 (0x00) /* Continuous mode */
#define RT_TIMER2_NAME "tmr2"
//#define RT_USING_TIMER2 (0x00) /* Continuous mode */
#define RT_TIMER2_NAME "tmr2"
/* SECTION: RTC options */
#if (defined(EFM32_G8XX_STK) || defined(EFM32_GXXX_DK) || defined(EFM32GG_DK3750))
#define RT_USING_RTC
#define RT_RTC_NAME "rtc"
#define RT_RTC_NAME "rtc"
#endif
/* SECTION: Serial options */
@ -199,9 +199,9 @@
#define EFM_LEUART1 (0x21UL)
#if defined(EFM32_G8XX_STK)
#define RT_CONSOLE_DEVICE (EFM_USART1)
#define RT_CONSOLE_DEVICE (EFM_USART1)
#elif defined(EFM32_GXXX_DK)
#define RT_CONSOLE_DEVICE (EFM_USART1)
#define RT_CONSOLE_DEVICE (EFM_USART1)
#elif defined(EFM32GG_DK3750)
#if defined(EFM32GG_DK3750_USING_LEUART1)
#define RT_CONSOLE_DEVICE (EFM_LEUART1)
@ -217,7 +217,7 @@
/* SECTION: Console options */
#define RT_USING_CONSOLE
/* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE (128)
#define RT_CONSOLEBUF_SIZE (128)
/* SECTION: finsh, a C-Express shell */
#define RT_USING_FINSH
@ -226,12 +226,12 @@
#define FINSH_USING_DESCRIPTION
/* SECTION: Peripheral devices */
#define EFM32_INTERFACE_ADC (0)
#define EFM32_INTERFACE_IIC (1)
#define EFM32_INTERFACE_SPI (2)
#define EFM32_INTERFACE_ADC (0)
#define EFM32_INTERFACE_IIC (1)
#define EFM32_INTERFACE_SPI (2)
#if (defined(EFM32_GXXX_DK) || defined(EFM32GG_DK3750))
//#define EFM32_USING_ACCEL EFM32_INTERFACE_IIC /* Three axis accelerometer */
//#define EFM32_USING_SFLASH /* SPI Flash */
//#define EFM32_USING_ACCEL EFM32_INTERFACE_IIC /* Three axis accelerometer */
//#define EFM32_USING_SFLASH /* SPI Flash */
#define EFM32_USING_SPISD /* MicroSD card */
//#define EFM32_USING_ETHERNET /* Ethernet controller */
//#define EFM32_USING_LCD /* TFT LCD */
@ -240,30 +240,30 @@
#if defined(EFM32_USING_ACCEL)
#if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC)
#define ACCEL_USING_DEVICE_NAME RT_ADC0_NAME
#define ACCEL_USING_DMA (0x3UL) /* For multiple channels scan mode */
#define ACCEL_USING_DEVICE_NAME RT_ADC0_NAME
#define ACCEL_USING_DMA (0x3UL) /* For multiple channels scan mode */
#elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
#define ACCEL_USING_DEVICE_NAME RT_IIC0_NAME
#define ACCEL_USING_DEVICE_NAME RT_IIC0_NAME
#endif
#endif
#if defined(EFM32_USING_SFLASH)
#define SFLASH_USING_DEVICE_NAME RT_USART0_NAME
#define SFLASH_USING_DEVICE_NAME RT_USART0_NAME
#endif
#if defined(EFM32_USING_SPISD)
#define SPISD_USING_DEVICE_NAME RT_USART0_NAME
#define SPISD_DEVICE_NAME "spiSd"
#define SPISD_USING_DEVICE_NAME RT_USART0_NAME
#define SPISD_DEVICE_NAME "spiSd"
#endif
#if defined(EFM32_USING_ETHERNET)
#if defined(EFM32_GXXX_DK)
#define ETH_USING_DEVICE_NAME RT_USART2_NAME
#define ETH_USING_DEVICE_NAME RT_USART2_NAME
#elif defined(EFM32GG_DK3750)
#define ETH_USING_DEVICE_NAME RT_USART1_NAME
#define ETH_USING_DEVICE_NAME RT_USART1_NAME
#endif
#define ETH_DEVICE_NAME "spiEth"
#define ETH_ADDR_DEFAULT {0x00, 0x01, 0x02, 0x03, 0x04, 0x05}
#define ETH_DEVICE_NAME "spiEth"
#define ETH_ADDR_DEFAULT {0x00, 0x01, 0x02, 0x03, 0x04, 0x05}
#endif
/* SECTION: device filesystem */
@ -271,9 +271,9 @@
#define RT_USING_DFS
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX (2)
/* the max number of opened files */
/* the max number of opened files */
#define DFS_FD_MAX (4)
/* the max number of cached sector */
/* the max number of cached sector */
#define DFS_CACHE_MAX_NUM (4)
#endif /* defined(RT_USING_NEWLIB) || defined(EFM32_USING_SPISD) */
#if defined(EFM32_USING_SPISD)
@ -288,8 +288,8 @@
#if defined(EFM32_USING_ETHERNET)
#define EFM32_USING_ETH_HTTPD
//#define EFM32_USING_ETH_UTILS
//#define hostName "onelife.dyndns.org"
//#define userPwdB64 "dXNlcjpwYXNzd2Q="
//#define hostName "onelife.dyndns.org"
//#define userPwdB64 "dXNlcjpwYXNzd2Q="
//#define RT_USING_LWIP
//#define RT_USING_NETUTILS
@ -308,37 +308,37 @@
//#define RT_LWIP_DNS
/* the number of simulatenously active TCP connections*/
#define RT_LWIP_TCP_PCB_NUM (2)
#define RT_LWIP_TCP_PCB_NUM (2)
/* ip address of target*/
#define RT_LWIP_IPADDR0 (192)
#define RT_LWIP_IPADDR1 (168)
#define RT_LWIP_IPADDR2 (1)
#define RT_LWIP_IPADDR3 (118)
#define RT_LWIP_IPADDR0 (192)
#define RT_LWIP_IPADDR1 (168)
#define RT_LWIP_IPADDR2 (1)
#define RT_LWIP_IPADDR3 (118)
/* gateway address of target*/
#define RT_LWIP_GWADDR0 (192)
#define RT_LWIP_GWADDR1 (168)
#define RT_LWIP_GWADDR2 (1)
#define RT_LWIP_GWADDR3 (1)
#define RT_LWIP_GWADDR0 (192)
#define RT_LWIP_GWADDR1 (168)
#define RT_LWIP_GWADDR2 (1)
#define RT_LWIP_GWADDR3 (1)
/* mask address of target*/
#define RT_LWIP_MSKADDR0 (255)
#define RT_LWIP_MSKADDR1 (255)
#define RT_LWIP_MSKADDR2 (255)
#define RT_LWIP_MSKADDR3 (0)
#define RT_LWIP_MSKADDR0 (255)
#define RT_LWIP_MSKADDR1 (255)
#define RT_LWIP_MSKADDR2 (255)
#define RT_LWIP_MSKADDR3 (0)
/* tcp thread options */
#define RT_LWIP_TCPTHREAD_PRIORITY (12)
#define RT_LWIP_TCPTHREAD_MBOX_SIZE (4)
#define RT_LWIP_TCPTHREAD_STACKSIZE (1024)
#define RT_LWIP_TCPTHREAD_PRIORITY (12)
#define RT_LWIP_TCPTHREAD_MBOX_SIZE (4)
#define RT_LWIP_TCPTHREAD_STACKSIZE (1024)
/* ethernet if thread options */
#define RT_LWIP_ETHTHREAD_PRIORITY (15)
#define RT_LWIP_ETHTHREAD_MBOX_SIZE (4)
#define RT_LWIP_ETHTHREAD_STACKSIZE (512)
#define RT_LWIP_ETHTHREAD_PRIORITY (15)
#define RT_LWIP_ETHTHREAD_MBOX_SIZE (4)
#define RT_LWIP_ETHTHREAD_STACKSIZE (512)
#endif /* defined(EFM32_USING_ETHERNET) */
/* SECTION: RTGUI support */
#if defined(EFM32_USING_LCD)
#define LCD_USING_DEVICE_NAME RT_USART1_NAME
#define LCD_USING_DEVICE_NAME RT_USART1_NAME
#define LCD_DEVICE_NAME "lcd"
/* using RTGUI support */
// #define RT_USING_RTGUI

4
bsp/efm32/startup.c
View File

@ -10,12 +10,12 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2006-08-31 Bernard first implementation
* 2010-12-29 onelife Modify for EFM32
* 2011-12-20 onelife Add RTGUI initialization routine
* 2012-02-21 onelife Add energy management initialization routine
* 2012-05-15 onelife Modified to compatible with CMSIS v3
* 2012-05-15 onelife Modified to compatible with CMSIS v3
******************************************************************************/
/***************************************************************************//**

4
bsp/hc32f4a0/board/board.h
View File

@ -6,9 +6,9 @@
* Change Logs:
* Date Author Notes
* 2020-10-30 CDT first version
* 2021-01-18 CDT MOdify SRAM_SIZE
*/
#ifndef __BOARD_H__
#define __BOARD_H__
@ -18,7 +18,7 @@
/* board configuration */
#define SRAM_BASE 0x1FFE0000
#define SRAM_SIZE 0x20000
#define SRAM_SIZE 0x80000
#define SRAM_END (SRAM_BASE + SRAM_SIZE)
/* High speed sram. */

17
bsp/hc32f4a0/drivers/drv_soft_i2c.c
View File

@ -6,9 +6,9 @@
* Change Logs:
* Date Author Notes
* 2020-10-30 CDT first version
* 2021-01-18 CDT modify i2c gpio init
*/
/*******************************************************************************
* Include files
******************************************************************************/
@ -65,10 +65,8 @@ static const struct hc32_soft_i2c_config soft_i2c_config[] =
#endif
};
static struct hc32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
@ -81,8 +79,8 @@ static void hc32_i2c_gpio_init(struct hc32_i2c *i2c)
{
struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)i2c->ops.data;
rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT);
rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT);
rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT_OD);
rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT_OD);
rt_pin_write(cfg->scl_pin, PIN_HIGH);
rt_pin_write(cfg->sda_pin, PIN_HIGH);
@ -98,8 +96,6 @@ static void hc32_set_sda(void *data, rt_int32_t state)
{
struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data;
rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT);
if (state)
rt_pin_write(cfg->sda_pin, PIN_HIGH);
else
@ -116,8 +112,6 @@ static void hc32_set_scl(void *data, rt_int32_t state)
{
struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data;
rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT);
if (state)
rt_pin_write(cfg->scl_pin, PIN_HIGH);
else
@ -133,8 +127,6 @@ static rt_int32_t hc32_get_sda(void *data)
{
struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data;
rt_pin_mode(cfg->sda_pin, PIN_MODE_INPUT);
return rt_pin_read(cfg->sda_pin);
}
@ -147,8 +139,6 @@ static rt_int32_t hc32_get_scl(void *data)
{
struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data;
rt_pin_mode(cfg->scl_pin, PIN_MODE_INPUT);
return rt_pin_read(cfg->scl_pin);
}
@ -210,7 +200,6 @@ int hc32_hw_i2c_init(void)
}
INIT_BOARD_EXPORT(hc32_hw_i2c_init);
#endif /* RT_USING_I2C */
/*******************************************************************************

8
bsp/nrf5x/nrf52832/rtconfig.py
View File

@ -84,3 +84,11 @@ elif PLATFORM == 'armcc':
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
def dist_handle(BSP_ROOT, dist_dir):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)

8
bsp/nrf5x/nrf52840/rtconfig.py
View File

@ -82,3 +82,11 @@ elif PLATFORM == 'armcc':
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
def dist_handle(BSP_ROOT, dist_dir):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)

17
bsp/nrf5x/tools/sdk_dist.py Normal file
View File

@ -0,0 +1,17 @@
import os
import sys
import shutil
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools'))
# BSP dist function
def dist_do_building(BSP_ROOT, dist_dir):
from mkdist import bsp_copy_files
import rtconfig
library_dir = os.path.join(dist_dir, 'libraries')
print("=> copy nrf52 bsp libraries")
library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries')
bsp_copy_files(library_path, library_dir)

0
bsp/rx/ReadMe.txt → bsp/rx/README.md
View File

10
bsp/rx/applications/application.c
View File

@ -1,11 +1,7 @@
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
@ -14,7 +10,7 @@
*/
/**
* @addtogroup STM32
* @addtogroup
*/
/*@{*/

8
bsp/rx/applications/startup.c
View File

@ -1,11 +1,7 @@
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

8
bsp/rx/drivers/Uart.h
View File

@ -1,3 +1,11 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __UART_H__
#define __UART_H__

9
bsp/rx/drivers/board.c
View File

@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"

18
bsp/rx/drivers/board.h
View File

@ -1,11 +1,21 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#define XTAL_FREQUENCY (12000000L)
#define ICLK_MUL (8)
#define PCLK_MUL (4)
#define BCLK_MUL (2)
#define XTAL_FREQUENCY (12000000L)
#define ICLK_MUL (8)
#define PCLK_MUL (4)
#define BCLK_MUL (2)
#define RX62N_SRAM_END 0x0000ffff

36
bsp/rx/drivers/uart.c
View File

@ -1,9 +1,11 @@
/*
*********************************************************************************************************
* Filename : uart.c
*********************************************************************************************************
*/
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rthw.h>
#include <rtthread.h>
@ -22,18 +24,18 @@
/* Clock selection control */
#define SCI_CKS_MIN 0
#define SCI_CKS_MAX 3
#define SCI_CKS_STEP 1
#define SCI_CKS_MIN 0
#define SCI_CKS_MAX 3
#define SCI_CKS_STEP 1
#define IPR_ADDRESS(a) ((volatile unsigned char *)&ICU.IPR[IPR_SCI0_ + a])
#define IPR_ADDRESS(a) ((volatile unsigned char *)&ICU.IPR[IPR_SCI0_ + a])
//#define IER_ADDRESS(a) ((volatile unsigned char *)&(ICU.IER[IER_SCI0_ERI0 + a])/sizeof(unsigned char))
#define ERI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) )
#define IER_ADDRESS(a) ((volatile unsigned char *)&ICU.IER[IER_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) )
#define RXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_RXI0] + ((4 * a) / sizeof(unsigned char)) )
#define TXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TXI0] + ((4 * a) / sizeof(unsigned char)) )
#define TEI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TEI0] + ((4 * a) / sizeof(unsigned char)) )
#define ERI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) )
#define IER_ADDRESS(a) ((volatile unsigned char *)&ICU.IER[IER_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) )
#define RXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_RXI0] + ((4 * a) / sizeof(unsigned char)) )
#define TXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TXI0] + ((4 * a) / sizeof(unsigned char)) )
#define TEI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TEI0] + ((4 * a) / sizeof(unsigned char)) )
#define RXI_DTCER_ADDRESS(a) (( volatile unsigned char *)&ICU.DTCER[IR_SCI0_RXI0]+ ((4*a)/sizeof(unsigned char)))
#define TXI_DTCER_ADDRESS(a) (( volatile unsigned char *)&ICU.DTCER[IR_SCI0_TXI0]+ ((4*a) / sizeof(unsigned char)))
//#define SCI1_USE_B
@ -44,8 +46,8 @@
#define SourceClk 12000000
#define rpdl_CGC_f_pclk SourceClk * 4
/* Idle output options */
#define SPACE 0
#define MARK 1
#define SPACE 0
#define MARK 1
typedef int UART_ID_Type;
typedef int IRQn_Type;
@ -528,7 +530,7 @@ void rt_hw_uart_init(void)
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
config.bufsz = RT_SERIAL_RB_BUFSZ;
serial2.ops = &rx_uart_ops;
serial2.config = config;

78
bsp/rx/rtconfig.h
View File

@ -3,16 +3,16 @@
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 8
#define RT_NAME_MAX 8
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX 32
#define RT_THREAD_PRIORITY_MAX 32
/* Tick per Second */
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug */
@ -27,9 +27,9 @@
/* Using Software Timer */
/* #define RT_USING_TIMER_SOFT */
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_TICK_PER_SECOND 10
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_TICK_PER_SECOND 10
/* SECTION: IPC */
/* Using Semaphore*/
@ -72,9 +72,9 @@
/* SECTION: Console options */
#define RT_USING_CONSOLE
/* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
#define RT_CONSOLE_DEVICE_NAME "uart2"
#define RT_CONSOLE_DEVICE_NAME "uart2"
/* SECTION: finsh, a C-Express shell */
#define RT_USING_FINSH
@ -89,17 +89,17 @@
/* Reentrancy (thread safe) of the FatFs module. */
#define RT_DFS_ELM_REENTRANT
/* Number of volumes (logical drives) to be used. */
#define RT_DFS_ELM_DRIVES 2
/* #define RT_DFS_ELM_USE_LFN 1 */
/* #define RT_DFS_ELM_CODE_PAGE 936 */
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
/* #define RT_DFS_ELM_USE_LFN 1 */
/* #define RT_DFS_ELM_CODE_PAGE 936 */
#define RT_DFS_ELM_MAX_LFN 255
/* Maximum sector size to be handled. */
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 4
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 4
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
/* #define RT_USING_LWIP */
@ -113,49 +113,49 @@
#define RT_LWIP_DNS
/* the number of simulatenously active TCP connections*/
#define RT_LWIP_TCP_PCB_NUM 5
#define RT_LWIP_TCP_PCB_NUM 5
/* Using DHCP */
/* #define RT_LWIP_DHCP */
/* ip address of target*/
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 30
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 30
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR3 1
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR3 1
/* mask address of target*/
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
/* tcp thread options */
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
/* ethernet if thread options */
#define RT_LWIP_ETHTHREAD_PRIORITY 15
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
#define RT_LWIP_ETHTHREAD_PRIORITY 15
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
/* TCP sender buffer space */
#define RT_LWIP_TCP_SND_BUF 8192
#define RT_LWIP_TCP_SND_BUF 8192
/* TCP receive window. */
#define RT_LWIP_TCP_WND 8192
#define RT_LWIP_TCP_WND 8192
/* SECTION: RT-Thread/GUI */
/* #define RT_USING_RTGUI */
/* name length of RTGUI object */
#define RTGUI_NAME_MAX 12
#define RTGUI_NAME_MAX 12
/* support 16 weight font */
#define RTGUI_USING_FONT16
/* support Chinese font */
@ -171,7 +171,7 @@
/* use mouse cursor */
/* #define RTGUI_USING_MOUSE_CURSOR */
/* default font size in RTGUI */
#define RTGUI_DEFAULT_FONT_SIZE 16
#define RTGUI_DEFAULT_FONT_SIZE 16
/* image support */
/* #define RTGUI_IMAGE_XPM */

44
bsp/simulator/.config
View File

@ -72,8 +72,10 @@ CONFIG_RT_VER_NUM=0x40003
#
# RT-Thread Components
#
# CONFIG_RT_USING_COMPONENTS_INIT is not set
# CONFIG_RT_USING_USER_MAIN is not set
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
@ -133,8 +135,6 @@ CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
#
# Device Drivers
@ -285,8 +285,6 @@ CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
@ -301,6 +299,10 @@ CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
#
# security packages
@ -382,6 +384,8 @@ CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
@ -409,6 +413,7 @@ CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
#
# peripheral libraries and drivers
@ -471,6 +476,23 @@ CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
#
# miscellaneous packages
@ -502,25 +524,23 @@ CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# games: games run on RT-Thread console
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_COWSAY is not set
CONFIG_SOC_SIMULATOR=y
CONFIG_RT_USING_DFS_WINSHAREDIR=y

8
bsp/simulator/Kconfig
View File

@ -18,8 +18,16 @@ config PKGS_DIR
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_SIMULATOR
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
if RT_USING_DFS
config RT_USING_DFS_WINSHAREDIR
bool "Enable shared file system between windows"
default n
endif

Some files were not shown because too many files have changed in this diff Show More