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Merge branch 'master' of https://github.com/RT-Thread/rt-thread into develop_one

This commit is contained in:
liuxianliang 2021-04-06 10:42:58 +08:00
parent 4431c4796f c5a0df2254
commit 233e1cd8bc
472 changed files with 17540 additions and 15072 deletions
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20
.github/workflows/file_check.yml vendored Normal file
View File

@ -0,0 +1,20 @@
name: Check File Format and License
on: [pull_request]
jobs:
scancode_job:
runs-on: ubuntu-latest
name: Scan code format and license
steps:
- uses: actions/checkout@v2
- name: Set up Python
uses: actions/setup-python@master
with:
python-version: 3.8
- name: Check Format and License
shell: bash
run: |
pip install click chardet
python tools/file_check.py check 'https://github.com/RT-Thread/rt-thread' 'master'

8
bsp/amebaz/applications/main.c
View File

@ -1,11 +1,7 @@
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

18
bsp/amebaz/applications/smartconfig_app.c
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@ -1,21 +1,7 @@
/*
* File : smartconfig_demo.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

14
bsp/amebaz/drivers/board.c
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@ -1,11 +1,7 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
@ -44,7 +40,7 @@ void __wrap_rtl_printf(const char *fmt, ...)
* length. */
length = rt_vsnprintf(rt_log_buf, sizeof(rt_log_buf) - 1, fmt, args);
if (length > RT_CONSOLEBUF_SIZE - 1)
length = RT_CONSOLEBUF_SIZE - 1;
length = RT_CONSOLEBUF_SIZE - 1;
rt_kprintf("%s", rt_log_buf);
va_end(args);
}
@ -89,11 +85,11 @@ void rt_hw_board_init(void)
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
rt_hw_uart_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);

8
bsp/amebaz/drivers/board.h
View File

@ -1,11 +1,7 @@
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

44
bsp/amebaz/drivers/drv_uart.c
View File

@ -1,21 +1,7 @@
/*
* File : drv_uart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
@ -125,7 +111,7 @@ static int ameba_uart_getc (struct rt_serial_device *serial)
{
struct device_uart* uart = serial->parent.user_data;
if(!serial_readable(&uart->serial))
if(!serial_readable(&uart->serial))
return -1;
/* Receive Data Available */
@ -140,13 +126,13 @@ static rt_size_t ameba_uart_dma_transmit (struct rt_serial_device *serial, rt_ui
static void ameba_uart_irq(uint32_t id, SerialIrq event)
{
struct rt_serial_device *serial = (struct rt_serial_device *)id;
if(event == RxIrq)
if(event == RxIrq)
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
else if(event == TxIrq)
}
else if(event == TxIrq)
{
}
}
}
static rt_err_t dbg_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
@ -155,7 +141,7 @@ static int dbg_putc(struct rt_serial_device *serial, char c);
static int dbg_getc(struct rt_serial_device *serial);
static struct rt_serial_device ameba_dbg_serial;
const struct rt_uart_ops _ambed_dbg_ops =
const struct rt_uart_ops _ambed_dbg_ops =
{
dbg_configure,
dbg_control,
@ -177,7 +163,7 @@ void dbg_uart_irq_handler(void * data)
DiagSetIsrEnReg(0);
rt_hw_serial_isr(&ameba_dbg_serial, RT_SERIAL_EVENT_RX_IND);
DiagSetIsrEnReg(IrqEn);
}
@ -192,9 +178,9 @@ static rt_err_t dbg_control(struct rt_serial_device *serial, int cmd, void *arg)
case RT_DEVICE_CTRL_SET_INT:
/* install interrupt */
DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler);
DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler);
/* Enable the UART Interrupt */
NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */
NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */
break;
}
@ -214,12 +200,12 @@ static int dbg_getc(struct rt_serial_device *serial)
if(!UART_Readable(UART2_DEV))
return -1;
c = DiagGetChar(_FALSE);
return c;
}
/*
* UART Initiation
*/
@ -231,7 +217,7 @@ int rt_hw_uart_init(void)
#ifdef BSP_USING_UART0
{
struct device_uart *uart;
serial = &serial0;
uart = &uart0;
@ -256,7 +242,7 @@ int rt_hw_uart_init(void)
serial->ops = &_ambed_dbg_ops;
serial->config = config;
rt_hw_serial_register(serial,
RT_CONSOLE_DEVICE_NAME,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,

18
bsp/amebaz/drivers/drv_uart.h
View File

@ -1,21 +1,7 @@
/*
* File : drv_uart.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

28
bsp/amebaz/drivers/wlan/drv_wifi.c
View File

@ -1,21 +1,7 @@
/*
* File : drv_wifi.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
@ -115,7 +101,7 @@ void netif_pre_sleep_processing(void)
}
unsigned char *rltk_wlan_get_ip(int idx)
{
{
struct ameba_wifi *wifi;
wifi = rthw_wifi_get_dev(idx);
@ -130,7 +116,7 @@ unsigned char *rltk_wlan_get_ip(int idx)
int netif_is_valid_IP(int idx, unsigned char *ip_dest)
{
LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__,
LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__,
ip_dest[0], ip_dest[1], ip_dest[2], ip_dest[3]);
return 1;
}
@ -376,9 +362,9 @@ static rt_err_t rthw_wlan_join (struct rt_wlan_device *wlan, str
ssid = &sta_info->ssid.val[0];
if (sta_info->key.len > 0)
key = &sta_info->key.val[0];
LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d",
LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d",
sta_info->bssid[0],sta_info->bssid[1],sta_info->bssid[2],sta_info->bssid[3],sta_info->bssid[4],sta_info->bssid[5],
ssid,
ssid,
sta_info->ssid.len,
key,
sta_info->key.len
@ -608,7 +594,7 @@ exit:
return RT_EOK;
}
static const struct rt_wlan_dev_ops ops =
static const struct rt_wlan_dev_ops ops =
{
.wlan_init = rthw_wlan_init ,
.wlan_mode = rthw_wlan_mode ,

20
bsp/amebaz/drivers/wlan/drv_wifi.h
View File

@ -1,27 +1,13 @@
/*
* File : drv_wifi.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#ifndef __DRV_WIFI_H__
#define __DRV_WIFI_H__

32
bsp/amebaz/drivers/wlan/drv_wlan.c
View File

@ -1,21 +1,7 @@
/*
* File : drv_wlan.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
@ -151,20 +137,20 @@ int rthw_wifi_ap_start(char *ssid, char *password, int channel)
return -1;
}
while(1)
while(1)
{
char essid[33];
if(wext_get_ssid(name, (unsigned char *) essid) > 0)
{
if(strcmp((const char *) essid, (const char *)ssid) == 0)
if(strcmp((const char *) essid, (const char *)ssid) == 0)
{
rt_kprintf("%s started\n", ssid);
break;
}
}
if(timeout == 0)
if(timeout == 0)
{
rt_kprintf("Start AP timeout\n");
rt_kprintf("Start AP timeout\n");
return -1;
}
rt_thread_delay(1 * RT_TICK_PER_SECOND);
@ -183,7 +169,7 @@ static int rthw_wifi_disconnect(char *name)
if (name == RT_NULL)
return -1;
if (wext_get_ssid(name, (unsigned char *) essid) < 0)
if (wext_get_ssid(name, (unsigned char *) essid) < 0)
{
rt_kprintf("\nWIFI disconnected!\n");
return -1;
@ -203,7 +189,7 @@ static int rthw_wifi_disconnect(char *name)
break;
}
if(timeout == 0)
if(timeout == 0)
{
rt_kprintf("ERROR: Deassoc timeout!\n");
return -1;
@ -259,7 +245,7 @@ int rthw_wifi_ap_disconnect(void)
int rthw_wifi_rssi_get(void)
{
int rssi = 0;
int rssi = 0;
wifi_get_rssi(&rssi);
return rssi;
}

34
bsp/amebaz/drivers/wlan/drv_wlan.h
View File

@ -1,21 +1,7 @@
/*
* File : drv_wlan.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
@ -25,14 +11,14 @@
#ifndef __DRV_WLAN_H__
#define __DRV_WLAN_H__
typedef enum
typedef enum
{
RTHW_MODE_NONE = 0,
RTHW_MODE_STA,
RTHW_MODE_AP,
RTHW_MODE_STA_AP,
RTHW_MODE_PROMISC,
RTHW_MODE_P2P
RTHW_MODE_NONE = 0,
RTHW_MODE_STA,
RTHW_MODE_AP,
RTHW_MODE_STA_AP,
RTHW_MODE_PROMISC,
RTHW_MODE_P2P
}rthw_mode_t;
#define SHARED_ENABLED 0x00008000
@ -66,7 +52,7 @@ typedef enum {
typedef enum {
RTHW_WIFI_EVENT_CONNECT = 0,
RTHW_WIFI_EVENT_DISCONNECT = 1,
RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2,
RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2,
RTHW_WIFI_EVENT_SCAN_RESULT_REPORT = 3,
RTHW_WIFI_EVENT_SCAN_DONE = 4,
RTHW_WIFI_EVENT_RECONNECTION_FAIL = 5,

22
bsp/at32/Libraries/rt_drivers/drv_adc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -17,7 +17,7 @@
#include <drv_log.h>
struct at32_adc
{
{
struct rt_adc_device at32_adc_device;
ADC_Type *ADC_Handler;
char *name;
@ -109,9 +109,9 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
ADC_InitType ADC_InitStructure;
RT_ASSERT(device != RT_NULL);
at32_adc_handler = device->parent.user_data;
at32_msp_adc_init(at32_adc_handler);
/* ADCx configuration ------------------------------------------------------*/
ADC_StructInit(&ADC_InitStructure);
ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
@ -121,14 +121,14 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NumOfChannel = 1;
ADC_Init(at32_adc_handler, &ADC_InitStructure);
/* ADCx regular channels configuration */
ADC_RegularChannelConfig(at32_adc_handler, at32_adc_get_channel(channel), 1, ADC_SampleTime_28_5);
/* ADCx regular channels configuration */
ADC_RegularChannelConfig(at32_adc_handler, at32_adc_get_channel(channel), 1, ADC_SampleTime_28_5);
/* Enable ADCx */
ADC_Ctrl(at32_adc_handler, ENABLE);
/* Enable ADCx reset calibration register */
/* Enable ADCx reset calibration register */
ADC_RstCalibration(at32_adc_handler);
/* Check the end of ADCx reset calibration register */
while(ADC_GetResetCalibrationStatus(at32_adc_handler));
@ -161,7 +161,7 @@ static rt_err_t at32_get_adc_value(struct rt_adc_device *device, rt_uint32_t cha
at32_adc_handler = device->parent.user_data;
/* Start ADCx Software Conversion */
/* Start ADCx Software Conversion */
ADC_SoftwareStartConvCtrl(at32_adc_handler, ENABLE);
/* Wait for the ADC to convert */

20
bsp/at32/Libraries/rt_drivers/drv_adc.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -19,32 +19,32 @@ extern "C" {
#endif
#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
.ADC_Handler = ADC1, \
.name = "adc1", \
}
}
#endif /* ADC1_CONFIG */
#ifndef ADC2_CONFIG
#define ADC2_CONFIG \
{ \
.ADC_Handler = ADC2, \
.name = "adc2", \
}
}
#endif /* ADC2_CONFIG */
#ifndef ADC3_CONFIG
#define ADC3_CONFIG \
{ \
.ADC_Handler = ADC3, \
.name = "adc3", \
}
#endif /* ADC3_CONFIG */
#endif
}
#endif /* ADC3_CONFIG */
#endif
#ifdef __cplusplus

8
bsp/at32/Libraries/rt_drivers/drv_can.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -311,8 +311,8 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
{
can_instance->CanConfig.FilterConfig.CAN_FilterNumber = filter_cfg->items[i].hdr & (0x1fU);
can_instance->CanConfig.FilterConfig.CAN_FilterIdHigh = (filter_cfg->items[i].id >> 13) & 0xFFFF;
can_instance->CanConfig.FilterConfig.CAN_FilterIdLow = ((filter_cfg->items[i].id << 3) |
(filter_cfg->items[i].ide << 2) |
can_instance->CanConfig.FilterConfig.CAN_FilterIdLow = ((filter_cfg->items[i].id << 3) |
(filter_cfg->items[i].ide << 2) |
(filter_cfg->items[i].rtr << 1)) & 0xFFFF;
can_instance->CanConfig.FilterConfig.CAN_FilterMskIdHigh = (filter_cfg->items[i].mask >> 16) & 0xFFFF;
can_instance->CanConfig.FilterConfig.CAN_FilterMskIdLow = filter_cfg->items[i].mask & 0xFFFF;
@ -499,7 +499,7 @@ static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
else
pmsg->ide = RxMessage.ExtId;
pmsg->rtr = RxMessage.RTR;
return RT_EOK;
}

4
bsp/at32/Libraries/rt_drivers/drv_can.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -22,7 +22,7 @@ extern "C" {
#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */
#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */
#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */
struct at32_baud_rate_tab
{
rt_uint32_t baud_rate;

64
bsp/at32/Libraries/rt_drivers/drv_eth.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -28,8 +28,8 @@
//#define DRV_DEBUG
#define LOG_TAG "drv.emac"
#define ETH_RXBUFNB 4
#define ETH_TXBUFNB 2
#define ETH_RXBUFNB 4
#define ETH_TXBUFNB 2
#define LINK_THREAD_STACK_SIZE 256
#define LINK_THREAD_PREORITY 21
@ -131,14 +131,14 @@ void NVIC_Configuration(void)
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
/* 2 bit for pre-emption priority, 2 bits for subpriority */
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
/* Enable the Ethernet global Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
NVIC_Init(&NVIC_InitStructure);
}
/**
@ -173,7 +173,7 @@ void GPIO_Configuration(void)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
/*MII Mode GPIO configuration*/
/*MII Mode GPIO configuration*/
#ifdef MII_MODE
/**********************MII Tx Pin Define****************************/
/*
@ -193,7 +193,7 @@ void GPIO_Configuration(void)
GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
/**********************MII Rx Pin Define****************************/
/**********************MII Rx Pin Define****************************/
#if MII_RX_REMAP /*IO PIN remaped*/
/*
ETH_MII_RX_DV-->PD8
@ -208,7 +208,7 @@ void GPIO_Configuration(void)
*/
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_8 | GPIO_Pins_9 | GPIO_Pins_10 | GPIO_Pins_11 | GPIO_Pins_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_3;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
@ -233,11 +233,11 @@ void GPIO_Configuration(void)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_10;
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_10;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOB, &GPIO_InitStructure);
@ -255,8 +255,8 @@ void GPIO_Configuration(void)
GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
/**********************RMII Rx Pin Define****************************/
/**********************RMII Rx Pin Define****************************/
#if MII_RX_REMAP /*IO PIN remaped*/
/*
ETH_RMII_RX_DV-->PD8
@ -266,7 +266,7 @@ void GPIO_Configuration(void)
*/
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_8 | GPIO_Pins_9 | GPIO_Pins_10;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_1;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
@ -282,7 +282,7 @@ void GPIO_Configuration(void)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOC, &GPIO_InitStructure);
@ -314,7 +314,7 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev)
RCC_AHBPeriphClockCmd(RCC_AHBPERIPH_ETHMAC | RCC_AHBPERIPH_ETHMACTX |
RCC_AHBPERIPH_ETHMACRX, ENABLE);
/* MII/RMII Media interface selection ------------------------------------------*/
#ifdef MII_MODE /* Mode MII with AT32F407-EVAL */
GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII);
@ -361,31 +361,31 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev)
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
#endif
/*------------------------ DMA -----------------------------------*/
/*------------------------ DMA -----------------------------------*/
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;//ETH_DropTCPIPChecksumErrorFrame_Enable;
ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;//ETH_DropTCPIPChecksumErrorFrame_Enable;
ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
/* Configure Ethernet, check error */
if(ETH_Init(&ETH_InitStructure, PHY_ADDRESS) == ((uint32_t)0)) {
return RT_ERROR;
}
}
/* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */
ETH_DMAITConfig(ETH_DMA_INT_NIS | ETH_DMA_INT_R, ENABLE);
ETH_DMAITConfig(ETH_DMA_INT_NIS | ETH_DMA_INT_R, ENABLE);
/* Initialize Tx Descriptors list: Chain Mode */
ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
@ -396,7 +396,7 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev)
ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&at32_eth_device.dev_addr[0]);
/* Enable ETH transmition and recetion */
ETH_Start();
ETH_Start();
return RT_EOK;
}
@ -581,7 +581,7 @@ struct pbuf *rt_at32_eth_rx(rt_device_t dev)
{
rt_uint32_t i;
rt_uint8_t *ptr = (rt_uint8_t*)(DMARxDescToGet->Buffer1Addr);
AT32_ETH_PRINTF("rx_dump, len:%d\r\n", p->tot_len);
for(i=0; i<p->tot_len; i++)
{

2
bsp/at32/Libraries/rt_drivers/drv_eth.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

12
bsp/at32/Libraries/rt_drivers/drv_flash.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -160,14 +160,14 @@ int at32_flash_erase(rt_uint32_t addr, size_t size)
addr += FLASH_PAGE_SIZE;
}
FLASH_Lock();
__exit:
FLASH_Lock();
__exit:
if(result != RT_EOK)
{
return result;
}
return size;
}
@ -177,7 +177,7 @@ static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase(long offset, size_t size);
const struct fal_flash_dev at32_onchip_flash =
const struct fal_flash_dev at32_onchip_flash =
{
"onchip_flash",
AT32_FLASH_START_ADRESS,

2
bsp/at32/Libraries/rt_drivers/drv_flash.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

14
bsp/at32/Libraries/rt_drivers/drv_gpio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -13,7 +13,7 @@
#ifdef RT_USING_PIN
static const struct pin_index pins[] =
static const struct pin_index pins[] =
{
#if defined(GPIOA)
__AT32_PIN(0 , A, 0 ),
@ -414,7 +414,7 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
/* Configure GPIO_InitStructure */
GPIO_StructInit(&GPIO_InitStruct);
EXTI_StructInit(&EXTI_InitStruct);
GPIO_InitStruct.GPIO_Pins = irqmap->pinbit;
GPIO_InitStruct.GPIO_Pins = irqmap->pinbit;
GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
EXTI_InitStruct.EXTI_Line = irqmap->pinbit;
EXTI_InitStruct.EXTI_Mode = EXTI_Mode_Interrupt;
@ -462,24 +462,24 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
if (( irqmap->pinbit>=GPIO_Pins_5 )&&( irqmap->pinbit<=GPIO_Pins_9 ))
{
if(!(pin_irq_enable_mask&(GPIO_Pins_5|GPIO_Pins_6|GPIO_Pins_7|GPIO_Pins_8|GPIO_Pins_9)))
{
{
NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno;
}
}
else if (( irqmap->pinbit>=GPIO_Pins_10 )&&( irqmap->pinbit<=GPIO_Pins_15 ))
{
if(!(pin_irq_enable_mask&(GPIO_Pins_10|GPIO_Pins_11|GPIO_Pins_12|GPIO_Pins_13|GPIO_Pins_14|GPIO_Pins_15)))
{
{
NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno;
}
}
else
{
NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno;
}
}
NVIC_Init(&NVIC_InitStruct);
rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable(level);
}
else
{

2
bsp/at32/Libraries/rt_drivers/drv_gpio.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

114
bsp/at32/Libraries/rt_drivers/drv_hwtimer.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -7,7 +7,7 @@
* Date Author Notes
* 2020-03-16 Leo first version
*/
#include <board.h>
#include "drv_hwtimer.h"
@ -20,35 +20,35 @@ enum
{
#ifdef BSP_USING_HWTMR1
TMR1_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR2
TMR2_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR3
TMR3_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR4
TMR4_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR5
TMR5_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR6
TMR6_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR7
TMR7_INDEX,
#endif
#endif
#ifdef BSP_USING_HW_TMR8
TMR8_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR9
TMR9_INDEX,
@ -56,11 +56,11 @@ enum
#ifdef BSP_USING_HWTMR10
TMR10_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR11
TMR11_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR12
TMR12_INDEX,
@ -68,11 +68,11 @@ enum
#ifdef BSP_USING_HWTMR13
TMR13_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR14
TMR14_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR15
TMR15_INDEX,
@ -91,48 +91,48 @@ static struct at32_hwtimer at32_hwtimer_obj[] =
{
#ifdef BSP_USING_HWTMR1
TMR1_CONFIG,
#endif
#endif
#ifdef BSP_USING_HWTMR2
TMR2_CONFIG,
#endif
#ifdef BSP_USING_HWTMR3
TMR3_CONFIG,
#endif
#ifdef BSP_USING_HWTMR4
TMR4_CONFIG,
#endif
#ifdef BSP_USING_HWTMR5
TMR5_CONFIG,
#endif
#endif
#ifdef BSP_USING_HWTMR6
TMR6_CONFIG,
#endif
#ifdef BSP_USING_HWTMR7
TMR7_CONFIG,
#endif
#ifdef BSP_USING_HWTMR8
TMR8_CONFIG,
#endif
#ifdef BSP_USING_HWTMR9
TMR9_CONFIG,
#endif
#endif
#ifdef BSP_USING_HWTMR10
TMR10_CONFIG,
#endif
#ifdef BSP_USING_HWTMR11
TMR11_CONFIG,
#endif
#ifdef BSP_USING_HWTMR12
TMR12_CONFIG,
#endif
@ -164,20 +164,20 @@ static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
{
tim = (TMR_Type *)timer->parent.user_data;
tim_device = (struct at32_hwtimer *)timer;
/* timer clock enable */
at32_msp_hwtmr_init(tim);
/* timer init */
RCC_GetClocksFreq(&RCC_ClockStruct);
/* Set timer clock is 1Mhz */
prescaler_value = (uint32_t)(RCC_ClockStruct.SYSCLK_Freq / 10000) - 1;
TMR_TMReBaseStructure.TMR_Period = 10000 - 1;
TMR_TMReBaseStructure.TMR_DIV = prescaler_value;
TMR_TMReBaseStructure.TMR_ClockDivision = TMR_CKD_DIV1;
TMR_TMReBaseStructure.TMR_RepetitionCounter = 0;
if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
{
TMR_TMReBaseStructure.TMR_CounterMode = TMR_CounterDIR_Up;
@ -186,21 +186,21 @@ static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
{
TMR_TMReBaseStructure.TMR_CounterMode = TMR_CounterDIR_Down;
}
TMR_TimeBaseInit(tim, &TMR_TMReBaseStructure);
/* Enable the TMRx global Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = tim_device->tim_irqn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
TMR_INTConfig(tim, TMR_INT_Overflow ,ENABLE);
TMR_ClearITPendingBit(tim, TMR_INT_Overflow);
LOG_D("%s init success", tim_device->name);
}
}
}
static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
@ -211,7 +211,7 @@ static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_
RT_ASSERT(timer != RT_NULL);
tim = (TMR_Type *)timer->parent.user_data;
/* set tim cnt */
TMR_SetCounter(tim, 0);
/* set tim arr */
@ -225,10 +225,10 @@ static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_
{
TMR_SelectOnePulseMode(tim, TMR_OPMode_Repetitive);
}
/* start timer */
TMR_Cmd(tim, ENABLE);
return result;
}
@ -239,7 +239,7 @@ static void at32_timer_stop(rt_hwtimer_t *timer)
RT_ASSERT(timer != RT_NULL);
tim = (TMR_Type *)timer->parent.user_data;
/* stop timer */
TMR_Cmd(tim, ENABLE);
/* set tim cnt */
@ -253,7 +253,7 @@ static rt_uint32_t at32_timer_counter_get(rt_hwtimer_t *timer)
RT_ASSERT(timer != RT_NULL);
tim = (TMR_Type *)timer->parent.user_data;
return tim->CNT;
}
@ -267,22 +267,22 @@ static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
RT_ASSERT(arg != RT_NULL);
tim = (TMR_Type *)timer->parent.user_data;
switch(cmd)
{
case HWTIMER_CTRL_FREQ_SET:
{
rt_uint32_t freq;
rt_uint16_t val;
/* set timer frequence */
freq = *((rt_uint32_t *)arg);
/* time init */
RCC_GetClocksFreq(&RCC_ClockStruct);
val = RCC_ClockStruct.SYSCLK_Freq / freq;
TMR_DIVConfig(tim, val - 1, TMR_DIVReloadMode_Immediate);
}
break;
@ -292,7 +292,7 @@ static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
}
break;
}
return result;
}
@ -311,13 +311,13 @@ void TMR2_GLOBAL_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if(TMR_GetINTStatus(TMR2, TMR_INT_Overflow) == SET)
{
rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR2_INDEX].time_device);
TMR_ClearITPendingBit(TMR2, TMR_INT_Overflow);
}
/* leave interrupt */
rt_interrupt_leave();
@ -329,13 +329,13 @@ void TMR3_GLOBAL_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if(TMR_GetINTStatus(TMR3, TMR_INT_Overflow) == SET)
{
rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR3_INDEX].time_device);
TMR_ClearITPendingBit(TMR3, TMR_INT_Overflow);
}
/* leave interrupt */
rt_interrupt_leave();
@ -347,13 +347,13 @@ void TMR4_GLOBAL_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if(TMR_GetINTStatus(TMR4, TMR_INT_Overflow) == SET)
{
rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR4_INDEX].time_device);
TMR_ClearITPendingBit(TMR4, TMR_INT_Overflow);
}
/* leave interrupt */
rt_interrupt_leave();
@ -365,13 +365,13 @@ void TMR5_GLOBAL_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if(TMR_GetINTStatus(TMR5, TMR_INT_Overflow) == SET)
{
rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR5_INDEX].time_device);
TMR_ClearITPendingBit(TMR5, TMR_INT_Overflow);
}
/* leave interrupt */
rt_interrupt_leave();

24
bsp/at32/Libraries/rt_drivers/drv_hwtimer.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -26,7 +26,7 @@ extern "C" {
.maxcnt = 0xFFFF, \
.cntmode = HWTIMER_CNTMODE_UP, \
}
#endif /* TIM_DEV_INFO_CONFIG */
#endif /* TIM_DEV_INFO_CONFIG */
#ifdef BSP_USING_HWTMR2
#ifndef TMR2_CONFIG
@ -36,9 +36,9 @@ extern "C" {
.tim_irqn = TMR2_GLOBAL_IRQn, \
.name = "timer2", \
}
#endif /* TMR2_CONFIG */
#endif /* BSP_USING_HWTMR2 */
#endif /* TMR2_CONFIG */
#endif /* BSP_USING_HWTMR2 */
#ifdef BSP_USING_HWTMR3
#ifndef TMR3_CONFIG
#define TMR3_CONFIG \
@ -47,8 +47,8 @@ extern "C" {
.tim_irqn = TMR3_GLOBAL_IRQn, \
.name = "timer3", \
}
#endif /* TMR3_CONFIG */
#endif /* BSP_USING_HWTMR3 */
#endif /* TMR3_CONFIG */
#endif /* BSP_USING_HWTMR3 */
#ifdef BSP_USING_HWTMR4
#ifndef TMR4_CONFIG
@ -58,9 +58,9 @@ extern "C" {
.tim_irqn = TMR4_GLOBAL_IRQn, \
.name = "timer4", \
}
#endif /* TMR4_CONFIG */
#endif /* TMR4_CONFIG */
#endif /* BSP_USING_HWTMR4 */
#ifdef BSP_USING_HWTMR5
#ifndef TMR5_CONFIG
#define TMR5_CONFIG \
@ -69,9 +69,9 @@ extern "C" {
.tim_irqn = TMR5_GLOBAL_IRQn, \
.name = "timer5", \
}
#endif /* TMR5_CONFIG */
#endif /* BSP_USING_HWTMR5 */
#endif /* TMR5_CONFIG */
#endif /* BSP_USING_HWTMR5 */
#ifdef __cplusplus
}
#endif

2
bsp/at32/Libraries/rt_drivers/drv_log.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

52
bsp/at32/Libraries/rt_drivers/drv_pwm.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -37,52 +37,52 @@ struct at32_pwm
char *name;
};
static struct at32_pwm at32_pwm_obj[] =
static struct at32_pwm at32_pwm_obj[] =
{
#ifdef BSP_USING_TMR1_CH1
PWM1_CONFIG,
#endif
#ifdef BSP_USING_TMR1_CH2
PWM2_CONFIG,
#endif
#ifdef BSP_USING_TMR1_CH3
PWM3_CONFIG,
#endif
#ifdef BSP_USING_TMR1_CH4
PWM4_CONFIG,
#endif
#ifdef BSP_USING_TMR2_CH1
PWM5_CONFIG,
#endif
#ifdef BSP_USING_TMR2_CH2
PWM6_CONFIG,
#endif
#ifdef BSP_USING_TMR2_CH3
PWM7_CONFIG,
#endif
#ifdef BSP_USING_TMR2_CH4
PWM8_CONFIG,
#endif
#ifdef BSP_USING_TMR3_CH1
PWM9_CONFIG,
#endif
#ifdef BSP_USING_TMR3_CH2
PWM10_CONFIG,
#endif
#ifdef BSP_USING_TMR3_CH3
PWM11_CONFIG,
#endif
#ifdef BSP_USING_TMR3_CH4
PWM12_CONFIG,
#endif
@ -97,7 +97,7 @@ static struct rt_pwm_ops drv_ops =
static rt_err_t drv_pwm_enable(TMR_Type* TMRx, struct rt_pwm_configuration *configuration, rt_bool_t enable)
{
/* Get the value of channel */
rt_uint32_t channel = configuration->channel;
rt_uint32_t channel = configuration->channel;
if (!enable)
{
@ -137,7 +137,7 @@ static rt_err_t drv_pwm_enable(TMR_Type* TMRx, struct rt_pwm_configuration *conf
TMR_CCxCmd(TMRx, TMR_Channel_1, TMR_CCx_Enable);
}
}
/* TMRx enable counter */
TMR_Cmd(TMRx, ENABLE);
@ -173,7 +173,7 @@ static rt_err_t drv_pwm_get(TMR_Type* TMRx, struct rt_pwm_configuration *configu
configuration->pulse = (cc3 + 1) * (div + 1) * 1000UL / tim_clock;
if(channel == 4)
configuration->pulse = (cc4 + 1) * (div + 1) * 1000UL / tim_clock;
return RT_EOK;
}
@ -185,15 +185,15 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu
rt_uint64_t psc;
/* Get the channel number */
rt_uint32_t channel = configuration->channel;
/* Init timer pin and enable clock */
at32_msp_tmr_init(TMRx);
/* Convert nanosecond to frequency and duty cycle. */
period = (unsigned long long)configuration->period ;
psc = period / MAX_PERIOD + 1;
period = period / psc;
/* TMRe base configuration */
TMR_TimeBaseStructInit(&TMR_TMReBaseStructure);
TMR_TMReBaseStructure.TMR_Period = period;
@ -204,14 +204,14 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu
TMR_TimeBaseInit(TMRx, &TMR_TMReBaseStructure);
pulse = (unsigned long long)configuration->pulse;
/* PWM1 Mode configuration: Channel1 */
TMR_OCStructInit(&TMR_OCInitStructure);
TMR_OCInitStructure.TMR_OCMode = TMR_OCMode_PWM1;
TMR_OCInitStructure.TMR_OutputState = TMR_OutputState_Enable;
TMR_OCInitStructure.TMR_Pulse = pulse;
TMR_OCInitStructure.TMR_OCPolarity = TMR_OCPolarity_High;
if(channel == 1)
{
TMR_OC1Init(TMRx, &TMR_OCInitStructure);
@ -232,7 +232,7 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu
TMR_OC4Init(TMRx, &TMR_OCInitStructure);
TMR_OC4PreloadConfig(TMRx, TMR_OCPreload_Enable);
}
TMR_ARPreloadConfig(TMRx, ENABLE);
#if defined (SOC_SERIES_AT32F415)
@ -271,7 +271,7 @@ static int rt_hw_pwm_init(void)
{
int i = 0;
int result = RT_EOK;
for(i = 0; i < sizeof(at32_pwm_obj) / sizeof(at32_pwm_obj[0]); i++)
{
if(rt_device_pwm_register(&at32_pwm_obj[i].pwm_device, at32_pwm_obj[i].name, &drv_ops, at32_pwm_obj[i].tim_handle) == RT_EOK)
@ -280,9 +280,9 @@ static int rt_hw_pwm_init(void)
}
else
{
LOG_D("%s register failed", at32_pwm_obj[i].name);
result = -RT_ERROR;
}
LOG_D("%s register failed", at32_pwm_obj[i].name);
result = -RT_ERROR;
}
}
return result;

16
bsp/at32/Libraries/rt_drivers/drv_pwm.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -28,7 +28,7 @@ extern "C" {
}
#endif /* PWM1_CONFIG */
#endif /* BSP_USING_TMR1_CH1 */
#ifdef BSP_USING_TMR1_CH2
#ifndef PWM2_CONFIG
#define PWM2_CONFIG \
@ -72,7 +72,7 @@ extern "C" {
}
#endif /* PWM5_CONFIG */
#endif /* BSP_USING_TMR2_CH1 */
#ifdef BSP_USING_TMR2_CH2
#ifndef PWM6_CONFIG
#define PWM6_CONFIG \
@ -82,8 +82,8 @@ extern "C" {
.channel = 2 \
}
#endif /* PWM6_CONFIG */
#endif /* BSP_USING_TMR2_CH2 */
#endif /* BSP_USING_TMR2_CH2 */
#ifdef BSP_USING_TMR2_CH3
#ifndef PWM7_CONFIG
#define PWM7_CONFIG \
@ -93,7 +93,7 @@ extern "C" {
.channel = 3 \
}
#endif /* PWM7_CONFIG */
#endif /* BSP_USING_TMR2_CH3 */
#endif /* BSP_USING_TMR2_CH3 */
#ifdef BSP_USING_TMR2_CH4
#ifndef PWM8_CONFIG
@ -115,7 +115,7 @@ extern "C" {
.channel = 1 \
}
#endif /* PWM9_CONFIG */
#endif /* BSP_USING_TMR3_CH1 */
#endif /* BSP_USING_TMR3_CH1 */
#ifdef BSP_USING_TMR3_CH2
#ifndef PWM10_CONFIG
@ -149,7 +149,7 @@ extern "C" {
}
#endif /* PWM12_CONFIG */
#endif /* BSP_USING_TMR3_CH4 */
#ifdef __cplusplus
}
#endif

14
bsp/at32/Libraries/rt_drivers/drv_rtc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -79,10 +79,10 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
return -RT_ERROR;
}
#else
/* Set the RTC counter value */
RTC_SetCounter(time_stamp);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
/* Set the RTC counter value */
RTC_SetCounter(time_stamp);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
#endif /* SOC_SERIES_AT32F415 */
LOG_D("set rtc time.");
#ifdef SOC_SERIES_AT32F415
@ -117,7 +117,7 @@ static rt_err_t rt_rtc_config(struct rt_device *dev)
ERTC_InitType ERTC_InitStructure;
#endif
/* Allow access to BKP Domain */
PWR_BackupAccessCtrl(ENABLE);
PWR_BackupAccessCtrl(ENABLE);
#ifdef SOC_SERIES_AT32F415
#ifdef BSP_RTC_USING_LSI
@ -148,7 +148,7 @@ static rt_err_t rt_rtc_config(struct rt_device *dev)
#else
if (BKP_ReadBackupReg(BKP_DT1) != BKUP_REG_DATA)
#endif
{
{
LOG_I("RTC hasn't been configured, please use <date> command to config.");
#ifdef SOC_SERIES_AT32F415
/* Configure the ERTC data register and ERTC prescaler */

2
bsp/at32/Libraries/rt_drivers/drv_sdio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_sdio.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

8
bsp/at32/Libraries/rt_drivers/drv_soft_i2c.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -205,10 +205,10 @@ int rt_hw_i2c_init(void)
result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name);
RT_ASSERT(result == RT_EOK);
at32_i2c_bus_unlock(&soft_i2c_config[i]);
LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
soft_i2c_config[i].bus_name,
soft_i2c_config[i].scl,
soft_i2c_config[i].bus_name,
soft_i2c_config[i].scl,
soft_i2c_config[i].sda);
}

8
bsp/at32/Libraries/rt_drivers/drv_soft_i2c.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -37,7 +37,7 @@ struct at32_i2c
.bus_name = "i2c1", \
}
#endif
#ifdef BSP_USING_I2C2
#define i2c_bus_CONFIG \
{ \
@ -46,7 +46,7 @@ struct at32_i2c
.bus_name = "i2c2", \
}
#endif
#ifdef BSP_USING_I2C3
#define I2C3_BUS_CONFIG \
{ \
@ -55,7 +55,7 @@ struct at32_i2c
.bus_name = "i2c3", \
}
#endif
#ifdef BSP_USING_I2C4
#define I2C4_BUS_CONFIG \
{ \

40
bsp/at32/Libraries/rt_drivers/drv_spi.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -7,7 +7,7 @@
* Date Author Notes
* 2020-01-09 shelton first version
*/
#include <board.h>
#include "drv_spi.h"
@ -24,7 +24,7 @@
#ifdef DEBUG
#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
#else
#define DEBUG_PRINTF(...)
#define DEBUG_PRINTF(...)
#endif
/* private rt-thread spi ops function */
@ -81,13 +81,13 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
static rt_err_t configure(struct rt_spi_device* device,
struct rt_spi_configuration* configuration)
{
struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;
struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;
struct at32_spi *spi_instance = (struct at32_spi *)spi_bus->parent.user_data;
SPI_InitType SPI_InitStruct;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
at32_msp_spi_init(spi_instance->config->spix);
@ -162,7 +162,7 @@ static rt_err_t configure(struct rt_spi_device* device,
SPI_InitStruct.SPI_MCLKP = SPI_MCLKP_256;
}
} /* baudrate */
switch(configuration->mode & RT_SPI_MODE_3)
{
case RT_SPI_MODE_0:
@ -172,11 +172,11 @@ static rt_err_t configure(struct rt_spi_device* device,
case RT_SPI_MODE_1:
SPI_InitStruct.SPI_CPHA = SPI_CPHA_2EDGE;
SPI_InitStruct.SPI_CPOL = SPI_CPOL_LOW;
break;
break;
case RT_SPI_MODE_2:
SPI_InitStruct.SPI_CPHA = SPI_CPHA_1EDGE;
SPI_InitStruct.SPI_CPOL = SPI_CPOL_HIGH;
break;
break;
case RT_SPI_MODE_3:
SPI_InitStruct.SPI_CPHA = SPI_CPHA_2EDGE;
SPI_InitStruct.SPI_CPOL = SPI_CPOL_HIGH;
@ -200,7 +200,7 @@ static rt_err_t configure(struct rt_spi_device* device,
/* init SPI */
SPI_Init(spi_instance->config->spix, &SPI_InitStruct);
/* Enable SPI_MASTER */
SPI_Enable(spi_instance->config->spix, ENABLE);
SPI_Enable(spi_instance->config->spix, ENABLE);
SPI_CRCEN(spi_instance->config->spix, DISABLE);
return RT_EOK;
@ -213,9 +213,9 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
struct rt_spi_configuration * config = &device->config;
struct at32_spi_cs * at32_spi_cs = device->parent.user_data;
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
/* take CS */
if(message->cs_take)
{
@ -229,7 +229,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
const rt_uint8_t * send_ptr = message->send_buf;
rt_uint8_t * recv_ptr = message->recv_buf;
rt_uint32_t size = message->length;
DEBUG_PRINTF("spi poll transfer start: %d\n", size);
while(size--)
@ -240,12 +240,12 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
{
data = *send_ptr++;
}
// Todo: replace register read/write by at32 lib
//Wait until the transmit buffer is empty
while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_TE));
// Send the byte
SPI_I2S_TxData(spi_instance->config->spix, data);
SPI_I2S_TxData(spi_instance->config->spix, data);
//Wait until a data is received
while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_RNE));
@ -277,7 +277,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
//Wait until the transmit buffer is empty
while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_TE));
// Send the byte
SPI_I2S_TxData(spi_instance->config->spix, data);
SPI_I2S_TxData(spi_instance->config->spix, data);
//Wait until a data is received
while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_RNE));
@ -295,7 +295,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
/* release CS */
if(message->cs_release)
{
GPIO_SetBits(at32_spi_cs->GPIOx, at32_spi_cs->GPIO_Pin);
GPIO_SetBits(at32_spi_cs->GPIOx, at32_spi_cs->GPIO_Pin);
DEBUG_PRINTF("spi release cs\n");
}
@ -306,7 +306,7 @@ static struct at32_spi_config configs[] = {
#ifdef BSP_USING_SPI1
{SPI1, "spi1"},
#endif
#ifdef BSP_USING_SPI2
{SPI2, "spi2"},
#endif

2
bsp/at32/Libraries/rt_drivers/drv_spi.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

42
bsp/at32/Libraries/rt_drivers/drv_sram.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -38,7 +38,7 @@ static int rt_hw_sram_Init(void)
/* Init XMC pin */
at32_msp_xmc_init(XMC);
/*-- FSMC Configuration ------------------------------------------------------*/
p.XMC_AdrOpTime = 0x04;
p.XMC_AdrHoldTime = 0x04;
@ -53,7 +53,7 @@ static int rt_hw_sram_Init(void)
XMC_NORSRAMInitStructure.XMC_Dev = XMC_Dev_SRAM;
XMC_NORSRAMInitStructure.XMC_BusType = XMC_BusType_16b;
XMC_NORSRAMInitStructure.XMC_EnableBurstMode = XMC_BurstMode_Disable;
XMC_NORSRAMInitStructure.XMC_EnableAsynWait = XMC_AsynWait_Disable;
XMC_NORSRAMInitStructure.XMC_EnableAsynWait = XMC_AsynWait_Disable;
XMC_NORSRAMInitStructure.XMC_WaitSignalLv = XMC_WaitSignalLv_Low;
XMC_NORSRAMInitStructure.XMC_EnableBurstModeSplit = XMC_BurstModeSplit_Disable;
XMC_NORSRAMInitStructure.XMC_WaitSignalConfig = XMC_WaitSignalConfig_BeforeWaitState;
@ -63,9 +63,9 @@ static int rt_hw_sram_Init(void)
XMC_NORSRAMInitStructure.XMC_WriteBurstSyn = XMC_WriteBurstSyn_Disable;
XMC_NORSRAMInitStructure.XMC_RWTimingStruct = &p;
XMC_NORSRAMInitStructure.XMC_WTimingStruct = &p;
XMC_NORSRAMInit(&XMC_NORSRAMInitStructure);
XMC_NORSRAMInit(&XMC_NORSRAMInitStructure);
/*!< Enable FSMC Bank1_SRAM Bank */
XMC_NORSRAMCmd(XMC_Bank1_NORSRAM3, ENABLE);
@ -73,7 +73,7 @@ static int rt_hw_sram_Init(void)
/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
rt_memheap_init(&system_heap, "sram", (void *)EXT_SRAM_BEGIN, SRAM_LENGTH);
#endif
return result;
}
INIT_BOARD_EXPORT(rt_hw_sram_Init);
@ -81,11 +81,11 @@ INIT_BOARD_EXPORT(rt_hw_sram_Init);
#ifdef DRV_DEBUG
#ifdef FINSH_USING_MSH
/**
* @brief Writes a Half-word buffer to the FSMC SRAM memory.
* @param pBuffer : pointer to buffer.
* @param WriteAddr : SRAM memory internal address from which the data will be
* @brief Writes a Half-word buffer to the FSMC SRAM memory.
* @param pBuffer : pointer to buffer.
* @param WriteAddr : SRAM memory internal address from which the data will be
* written.
* @param NumHalfwordToWrite : number of half-words to write.
* @param NumHalfwordToWrite : number of half-words to write.
* @retval None
*/
static void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
@ -94,15 +94,15 @@ static void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t Num
{
/*!< Transfer data to the memory */
*(uint16_t *) (EXT_SRAM_BEGIN + WriteAddr) = *pBuffer++;
/*!< Increment the address*/
/*!< Increment the address*/
WriteAddr += 2;
}
}
}
/**
* @brief Reads a block of data from the FSMC SRAM memory.
* @param pBuffer : pointer to the buffer that receives the data read from the
* @param pBuffer : pointer to the buffer that receives the data read from the
* SRAM memory.
* @param ReadAddr : SRAM memory internal address to read from.
* @param NumHalfwordToRead : number of half-words to read.
@ -115,9 +115,9 @@ static void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHa
/*!< Read a half-word from the memory */
*pBuffer++ = *(__IO uint16_t*) (EXT_SRAM_BEGIN + ReadAddr);
/*!< Increment the address*/
/*!< Increment the address*/
ReadAddr += 2;
}
}
}
/**
@ -146,9 +146,9 @@ int sram_test(void)
/* Read data from XMC SRAM memory */
SRAM_ReadBuffer(RT_RxBuffer, RT_WRITE_READ_ADDR, RT_BUFFER_SIZE);
SRAM_ReadBuffer(RT_RxBuffer, RT_WRITE_READ_ADDR, RT_BUFFER_SIZE);
/* Read back SRAM memory and check content correctness */
/* Read back SRAM memory and check content correctness */
for (Index = 0x00; (Index < RT_BUFFER_SIZE) && (WriteReadStatus == 0); Index++)
{
if (RT_RxBuffer[Index] != RT_TxBuffer[Index])
@ -156,7 +156,7 @@ int sram_test(void)
WriteReadStatus = Index + 1;
}
}
if(WriteReadStatus == 0)
{
LOG_D("SRAM test success!");
@ -165,7 +165,7 @@ int sram_test(void)
{
LOG_E("SRAM test failed!");
}
return RT_EOK;
}
MSH_CMD_EXPORT(sram_test, sram test)

2
bsp/at32/Libraries/rt_drivers/drv_sram.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/at32/Libraries/rt_drivers/drv_usart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -15,7 +15,7 @@
#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \
!defined(BSP_USING_UART3)
#error "Please define at least one BSP_USING_UARTx"
/* this driver can be disabled at menuconfig ¡ú RT-Thread Components ¡ú Device Drivers */
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
#endif
struct at32_usart {

2
bsp/at32/Libraries/rt_drivers/drv_usart.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_wdt.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/at32f403a-start/applications/main.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/at32/at32f403a-start/board/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -7,7 +7,7 @@
* Date Author Notes
* 2018-11-06 balanceTWK first version
*/
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>

2
bsp/at32/at32f403a-start/board/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

20
bsp/at32/at32f403a-start/board/msp/at32_msp.c
View File

@ -195,34 +195,34 @@ void at32_msp_adc_init(void *Instance)
GPIO_InitType GPIO_InitStruct;
ADC_Type *ADCx = (ADC_Type *)Instance;
#ifdef BSP_USING_ADC1
#ifdef BSP_USING_ADC1
if(ADCx == ADC1)
{
{
/* ADC1 & GPIO clock enable */
RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC1 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE);
/* Configure ADC Channel as analog input */
/* Configure ADC Channel as analog input */
GPIO_StructInit(&GPIO_InitStruct);
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG;
GPIO_Init(GPIOC, &GPIO_InitStruct);
}
#endif
#ifdef BSP_USING_ADC2
#ifdef BSP_USING_ADC2
if(ADCx == ADC2)
{
/* ADC2 & GPIO clock enable */
RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC2 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE);
/* Configure ADC Channel as analog input */
/* Configure ADC Channel as analog input */
GPIO_StructInit(&GPIO_InitStruct);
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG;
GPIO_Init(GPIOC, &GPIO_InitStruct);
}
#endif
#endif
}
#endif /* BSP_USING_ADC */
@ -237,7 +237,7 @@ void at32_msp_hwtmr_init(void *Instance)
/* TMR3 clock enable */
RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_TMR3, ENABLE);
}
#endif
#endif
#ifdef BSP_USING_HWTMR4
if(TMRx == TMR4)

120
bsp/at32/at32f403a-start/board/msp/system_at32f4xx.c
View File

@ -17,7 +17,7 @@
*
* <h2><center>&copy; COPYRIGHT 2018 ArteryTek</center></h2>
******************************************************************************
*/
*/
/** @addtogroup CMSIS
* @{
@ -68,23 +68,23 @@
Clock (MHz)
PLL from HSE or HSI
SYSCLK HCLK PCLK2 PCLK1
24 24 24 24
36 36 36 36
48 48 48 24
56 56 56 28
72 72 72 36
96 96 48 48
108 108 54 54
120 120 60 60
144 144 72 72
150 150 75 75
168 168 84 84
176 176 88 88
192 192 96 96
200 200 100 100
224 224 112 112
240 240 120 120
SYSCLK HCLK PCLK2 PCLK1
24 24 24 24
36 36 36 36
48 48 48 24
56 56 56 28
72 72 72 36
96 96 48 48
108 108 54 54
120 120 60 60
144 144 72 72
150 150 75 75
168 168 84 84
176 176 88 88
192 192 96 96
200 200 100 100
224 224 112 112
240 240 120 120
*/
#if defined (AT32F403xx) || defined (AT32F413xx) || \
@ -143,7 +143,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
@ -573,7 +573,7 @@ static void SetSysClock(void)
/**
* @brief Setup the external memory controller.
* Called in startup_at32f4xx_xx.s/.c before jump to main.
* This function configures the external SRAM mounted
* This function configures the external SRAM mounted
* (AT32 High density devices). This SRAM will be used as program
* data memory (including heap and stack).
* @param None
@ -654,7 +654,7 @@ static void SetSysClockToHSE(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -674,7 +674,7 @@ static void SetSysClockToHSE(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -725,7 +725,7 @@ static void SetSysClockTo24M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -745,7 +745,7 @@ static void SetSysClockTo24M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -811,7 +811,7 @@ static void SetSysClockTo36M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -831,7 +831,7 @@ static void SetSysClockTo36M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -897,7 +897,7 @@ static void SetSysClockTo48M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -917,7 +917,7 @@ static void SetSysClockTo48M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -984,7 +984,7 @@ static void SetSysClockTo56M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1004,7 +1004,7 @@ static void SetSysClockTo56M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1071,7 +1071,7 @@ static void SetSysClockTo72M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1091,7 +1091,7 @@ static void SetSysClockTo72M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1158,7 +1158,7 @@ static void SetSysClockTo96M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1178,7 +1178,7 @@ static void SetSysClockTo96M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1249,7 +1249,7 @@ static void SetSysClockTo108M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1269,7 +1269,7 @@ static void SetSysClockTo108M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1341,7 +1341,7 @@ static void SetSysClockTo120M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1361,7 +1361,7 @@ static void SetSysClockTo120M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1440,7 +1440,7 @@ static void SetSysClockTo144M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1460,7 +1460,7 @@ static void SetSysClockTo144M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1475,7 +1475,7 @@ static void SetSysClockTo144M(void)
/* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
RCC->CFG &= RCC_CFG_PLLCFG_MASK;
#if defined (AT32F415xx)
RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18);
#else
@ -1539,7 +1539,7 @@ static void SetSysClockTo150M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1559,7 +1559,7 @@ static void SetSysClockTo150M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1634,7 +1634,7 @@ static void SetSysClockTo168M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1720,7 +1720,7 @@ static void SetSysClockTo176M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1806,7 +1806,7 @@ static void SetSysClockTo192M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1892,7 +1892,7 @@ static void SetSysClockTo200M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1978,7 +1978,7 @@ static void SetSysClockTo224M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -2064,7 +2064,7 @@ static void SetSysClockTo240M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -2168,7 +2168,7 @@ static void SetSysClockTo24MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2248,7 +2248,7 @@ static void SetSysClockTo36MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2328,7 +2328,7 @@ static void SetSysClockTo48MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2408,7 +2408,7 @@ static void SetSysClockTo56MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2488,7 +2488,7 @@ static void SetSysClockTo72MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2568,7 +2568,7 @@ static void SetSysClockTo96MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2653,7 +2653,7 @@ static void SetSysClockTo108MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2738,7 +2738,7 @@ static void SetSysClockTo120MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2830,7 +2830,7 @@ static void SetSysClockTo144MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2922,7 +2922,7 @@ static void SetSysClockTo150MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -3454,4 +3454,4 @@ static void SetSysClockTo240MHSI(void)
* @}
*/
/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/
/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/

2
bsp/at32/at32f407-start/applications/main.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/at32/at32f407-start/board/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -7,7 +7,7 @@
* Date Author Notes
* 2018-11-06 balanceTWK first version
*/
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>

2
bsp/at32/at32f407-start/board/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

20
bsp/at32/at32f407-start/board/msp/at32_msp.c
View File

@ -195,34 +195,34 @@ void at32_msp_adc_init(void *Instance)
GPIO_InitType GPIO_InitStruct;
ADC_Type *ADCx = (ADC_Type *)Instance;
#ifdef BSP_USING_ADC1
#ifdef BSP_USING_ADC1
if(ADCx == ADC1)
{
{
/* ADC1 & GPIO clock enable */
RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC1 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE);
/* Configure ADC Channel as analog input */
/* Configure ADC Channel as analog input */
GPIO_StructInit(&GPIO_InitStruct);
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG;
GPIO_Init(GPIOC, &GPIO_InitStruct);
}
#endif
#ifdef BSP_USING_ADC2
#ifdef BSP_USING_ADC2
if(ADCx == ADC2)
{
/* ADC2 & GPIO clock enable */
RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC2 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE);
/* Configure ADC Channel as analog input */
/* Configure ADC Channel as analog input */
GPIO_StructInit(&GPIO_InitStruct);
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG;
GPIO_Init(GPIOC, &GPIO_InitStruct);
}
#endif
#endif
}
#endif /* BSP_USING_ADC */
@ -237,7 +237,7 @@ void at32_msp_hwtmr_init(void *Instance)
/* TMR3 clock enable */
RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_TMR3, ENABLE);
}
#endif
#endif
#ifdef BSP_USING_HWTMR4
if(TMRx == TMR4)

120
bsp/at32/at32f407-start/board/msp/system_at32f4xx.c
View File

@ -17,7 +17,7 @@
*
* <h2><center>&copy; COPYRIGHT 2018 ArteryTek</center></h2>
******************************************************************************
*/
*/
/** @addtogroup CMSIS
* @{
@ -68,23 +68,23 @@
Clock (MHz)
PLL from HSE or HSI
SYSCLK HCLK PCLK2 PCLK1
24 24 24 24
36 36 36 36
48 48 48 24
56 56 56 28
72 72 72 36
96 96 48 48
108 108 54 54
120 120 60 60
144 144 72 72
150 150 75 75
168 168 84 84
176 176 88 88
192 192 96 96
200 200 100 100
224 224 112 112
240 240 120 120
SYSCLK HCLK PCLK2 PCLK1
24 24 24 24
36 36 36 36
48 48 48 24
56 56 56 28
72 72 72 36
96 96 48 48
108 108 54 54
120 120 60 60
144 144 72 72
150 150 75 75
168 168 84 84
176 176 88 88
192 192 96 96
200 200 100 100
224 224 112 112
240 240 120 120
*/
#if defined (AT32F403xx) || defined (AT32F413xx) || \
@ -143,7 +143,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
@ -573,7 +573,7 @@ static void SetSysClock(void)
/**
* @brief Setup the external memory controller.
* Called in startup_at32f4xx_xx.s/.c before jump to main.
* This function configures the external SRAM mounted
* This function configures the external SRAM mounted
* (AT32 High density devices). This SRAM will be used as program
* data memory (including heap and stack).
* @param None
@ -654,7 +654,7 @@ static void SetSysClockToHSE(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -674,7 +674,7 @@ static void SetSysClockToHSE(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -725,7 +725,7 @@ static void SetSysClockTo24M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -745,7 +745,7 @@ static void SetSysClockTo24M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -811,7 +811,7 @@ static void SetSysClockTo36M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -831,7 +831,7 @@ static void SetSysClockTo36M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -897,7 +897,7 @@ static void SetSysClockTo48M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -917,7 +917,7 @@ static void SetSysClockTo48M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -984,7 +984,7 @@ static void SetSysClockTo56M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1004,7 +1004,7 @@ static void SetSysClockTo56M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1071,7 +1071,7 @@ static void SetSysClockTo72M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1091,7 +1091,7 @@ static void SetSysClockTo72M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1158,7 +1158,7 @@ static void SetSysClockTo96M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1178,7 +1178,7 @@ static void SetSysClockTo96M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1249,7 +1249,7 @@ static void SetSysClockTo108M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1269,7 +1269,7 @@ static void SetSysClockTo108M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1341,7 +1341,7 @@ static void SetSysClockTo120M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1361,7 +1361,7 @@ static void SetSysClockTo120M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1440,7 +1440,7 @@ static void SetSysClockTo144M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1460,7 +1460,7 @@ static void SetSysClockTo144M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1475,7 +1475,7 @@ static void SetSysClockTo144M(void)
/* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
RCC->CFG &= RCC_CFG_PLLCFG_MASK;
#if defined (AT32F415xx)
RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18);
#else
@ -1539,7 +1539,7 @@ static void SetSysClockTo150M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1559,7 +1559,7 @@ static void SetSysClockTo150M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1634,7 +1634,7 @@ static void SetSysClockTo168M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1720,7 +1720,7 @@ static void SetSysClockTo176M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1806,7 +1806,7 @@ static void SetSysClockTo192M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1892,7 +1892,7 @@ static void SetSysClockTo200M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1978,7 +1978,7 @@ static void SetSysClockTo224M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -2064,7 +2064,7 @@ static void SetSysClockTo240M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -2168,7 +2168,7 @@ static void SetSysClockTo24MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2248,7 +2248,7 @@ static void SetSysClockTo36MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2328,7 +2328,7 @@ static void SetSysClockTo48MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2408,7 +2408,7 @@ static void SetSysClockTo56MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2488,7 +2488,7 @@ static void SetSysClockTo72MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2568,7 +2568,7 @@ static void SetSysClockTo96MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2653,7 +2653,7 @@ static void SetSysClockTo108MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2738,7 +2738,7 @@ static void SetSysClockTo120MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2830,7 +2830,7 @@ static void SetSysClockTo144MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2922,7 +2922,7 @@ static void SetSysClockTo150MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -3454,4 +3454,4 @@ static void SetSysClockTo240MHSI(void)
* @}
*/
/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/
/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/

6
bsp/bluetrum/libraries/hal_drivers/drv_rtc.c
View File

@ -182,7 +182,7 @@ static void rt_rtc_init(void)
hal_rtc_init();
}
static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
static rt_err_t ab32_rtc_control(rt_device_t dev, int cmd, void *args)
{
rt_err_t result = RT_EOK;
RT_ASSERT(dev != RT_NULL);
@ -224,7 +224,7 @@ const static struct rt_device_ops rtc_ops =
RT_NULL,
RT_NULL,
RT_NULL,
rt_rtc_control
ab32_rtc_control
};
#endif
@ -241,7 +241,7 @@ static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = rt_rtc_control;
device->control = ab32_rtc_control;
#endif
device->type = RT_Device_Class_RTC;
device->rx_indicate = RT_NULL;

4
bsp/efm32/EFM32GG_DK3750/dvk.h
View File

@ -164,7 +164,7 @@ int DVK_BRD3600A_usbVBUSGetOCFlagState(void);
/* For "backward compatibility" with DVK */
/** DVK_enablePeripheral() backward compatibility */
#define DVK_enablePeripheral(X) DVK_peripheralAccess(X, true)
#define DVK_enablePeripheral(X) DVK_peripheralAccess(X, true)
/** DVK_disablePeripheral() backward compatibility */
#define DVK_disablePeripheral(X) DVK_peripheralAccess(X, false)
@ -193,7 +193,7 @@ __STATIC_INLINE uint16_t DVK_EBI_readRegister(volatile uint16_t *addr)
/**************************************************************************//**
* @brief Read data from 16-bit board control register
* @param addr Register to read
* @return Value of board controller register
* @return Value of board controller register
*****************************************************************************/
__STATIC_INLINE uint16_t DVK_readRegister(volatile uint16_t *addr)
{

4
bsp/efm32/EFM32GG_DK3750/trace.c
View File

@ -125,7 +125,7 @@ void TRACE_SWOSetup(void)
/**************************************************************************//**
* @brief Profiler configuration for EFM32GG990F11024/EFM32GG-DK3750
* @return true if energyAware Profiler/SWO is enabled, false if not
* @note If first word of the user page is zero, this will not
* @note If first word of the user page is zero, this will not
* enable SWO profiler output
*****************************************************************************/
bool TRACE_ProfilerSetup(void)
@ -141,7 +141,7 @@ bool TRACE_ProfilerSetup(void)
{
TRACE_SWOSetup();
return true;
}
}
}
/** @} (end group BSP) */

4
bsp/efm32/EFM32GG_DK3750/trace.h
View File

@ -58,7 +58,7 @@ bool TRACE_ProfilerSetup(void);
* for TRACE_ProfilerSetup. If TRACE_ProfilerEnable(false) has been run,
* no example project will enable SWO trace.
* @param[in] enable
* @note Add "em_msc.c" to build to use this function.
* @note Add "em_msc.c" to build to use this function.
*****************************************************************************/
__STATIC_INLINE void TRACE_ProfilerEnable(bool enable)
{
@ -69,7 +69,7 @@ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable)
data = *userpage;
if(enable)
{
if(data == 0xFFFFFFFF)
if(data == 0xFFFFFFFF)
{
return;
}

2
bsp/efm32/EFM32_Gxxx_DK/dvk.c
View File

@ -52,7 +52,7 @@ bool DVK_init(void)
#endif
#ifdef DVK_SPI_CONTROL
ret = DVK_SPI_init();
#endif
#endif
if ( ret == false )
{
/* Board is configured in wrong mode, please restart KIT! */

2
bsp/efm32/EFM32_Gxxx_DK/dvk_bcregisters.h
View File

@ -73,7 +73,7 @@
#define BC_HW_VERSION ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x14)) /**< HW version */
#define BC_FW_BUILDNO ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x15)) /**< FW build number */
#define BC_FW_VERSION ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x16)) /**< FW version */
#define BC_SCRATCH_COMMON ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x17)) /**< Scratch common */
#define BC_SCRATCH_COMMON ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x17)) /**< Scratch common */
#define BC_SCRATCH_EFM0 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x18)) /**< Scratch EFM0 */
#define BC_SCRATCH_EFM1 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x19)) /**< Scratch EFM1 */
#define BC_SCRATCH_EFM2 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1A)) /**< Scratch EFM2 */

4
bsp/efm32/EFM32_Gxxx_DK/dvk_boardcontrol.c
View File

@ -155,7 +155,7 @@ uint16_t DVK_getPushButtons(void)
/* Check state */
aemState = DVK_readRegister(BC_AEMSTATE);
/* Read pushbutton status */
if ( aemState == BC_AEMSTATE_EFM )
if ( aemState == BC_AEMSTATE_EFM )
{
pb = (~(DVK_readRegister(BC_PUSHBUTTON))) & 0x000f;
}
@ -174,7 +174,7 @@ uint16_t DVK_getJoystick(void)
/* Check state */
aemState = DVK_readRegister(BC_AEMSTATE);
/* Read pushbutton status */
if ( aemState == BC_AEMSTATE_EFM )
if ( aemState == BC_AEMSTATE_EFM )
{
joyStick = (~(DVK_readRegister(BC_JOYSTICK))) & 0x001f;
}

6
bsp/efm32/EFM32_Gxxx_DK/dvk_ebi.c
View File

@ -163,7 +163,7 @@ bool DVK_EBI_init(void)
* be configured for EBI access */
ebiMagic = DVK_EBI_readRegister(BC_MAGIC);
while ((ebiMagic != BC_MAGIC_VALUE) && retry)
{
{
DVK_EBI_disable();
/* Enable SPI interface */
DVK_SPI_init();
@ -172,13 +172,13 @@ bool DVK_EBI_init(void)
DVK_SPI_writeRegister(BC_CFG, BC_CFG_EBI);
/* Disable SPI */
DVK_SPI_disable();
/* Now setup EBI again */
DVK_EBI_configure();
/* Wait until ready */
ebiMagic = DVK_EBI_readRegister(BC_MAGIC);
if (ebiMagic == BC_MAGIC_VALUE) break;
retry--;
}
if ( ! retry ) return false;

8
bsp/efm32/EFM32_Gxxx_DK/dvk_spi.c
View File

@ -106,7 +106,7 @@ static void spiInit(void)
/* Configure SPI bus connect pins, DOUT set to 0, disable EBI */
GPIO_PinModeSet(PORT_SPIBUS_CONNECT, PIN_SPIBUS_CONNECT, gpioModePushPull, 0);
GPIO_PinModeSet(PORT_EBIBUS_CONNECT, PIN_EBIBUS_CONNECT, gpioModePushPull, 1);
/* Configure SPI pins */
GPIO_PinModeSet(PORT_SPI_TX, PIN_SPI_TX, gpioModePushPull, 0);
GPIO_PinModeSet(PORT_SPI_RX, PIN_SPI_RX, gpioModePushPull, 0);
@ -164,11 +164,11 @@ static uint16_t spiAccess(uint8_t spiaddr, uint8_t rw, uint16_t spidata)
/* Just ignore data read back */
USART_Rx(USART_USED);
/* SPI data LSB */
/* SPI data LSB */
USART_Tx(USART_USED, spidata & 0xFF);
tmp = (uint16_t)USART_Rx(USART_USED);
/* SPI data MSB */
/* SPI data MSB */
USART_Tx(USART_USED, spidata >> 8);
tmp |= (uint16_t)USART_Rx(USART_USED) << 8;
@ -213,7 +213,7 @@ bool DVK_SPI_init(void)
if(spiMagic != BC_MAGIC_VALUE)
{
return false;
}
}
else
{
return true;

4
bsp/efm32/EFM32_Gxxx_DK/trace.c
View File

@ -89,7 +89,7 @@ void TRACE_SWOSetup(void)
/**************************************************************************//**
* @brief Profiler configuration
* @return true if energyAware Profiler/SWO is enabled, false if not
* @note If first word of the user page is zero, this will not
* @note If first word of the user page is zero, this will not
* enable SWO profiler output, see trace.h
*****************************************************************************/
bool TRACE_ProfilerSetup(void)
@ -105,7 +105,7 @@ bool TRACE_ProfilerSetup(void)
{
TRACE_SWOSetup();
return true;
}
}
}
/** @} (end group BSP) */

6
bsp/efm32/EFM32_Gxxx_DK/trace.h
View File

@ -58,7 +58,7 @@ bool TRACE_ProfilerSetup(void);
* in TRACE_ProfilerSetup. If TRACE_ProfilerEnable(false) has been run,
* no example project will enable SWO trace.
* @param[in] enable
* @note Add "em_msc.c" to build to use this function.
* @note Add "em_msc.c" to build to use this function.
*****************************************************************************/
__STATIC_INLINE void TRACE_ProfilerEnable(bool enable)
{
@ -69,7 +69,7 @@ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable)
data = *userpage;
if(enable)
{
if(data == 0xFFFFFFFF)
if(data == 0xFFFFFFFF)
{
return;
}
@ -81,7 +81,7 @@ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable)
return;
}
}
/* Initialize MSC */
MSC_Init();

40
bsp/efm32/Libraries/CMSIS/Include/arm_common_tables.h
View File

@ -1,24 +1,24 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* $Date: 11. November 2010
* $Revision: V1.0.2
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
/* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* $Date: 11. November 2010
* $Revision: V1.0.2
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Version 1.0.2 2010/11/11
* Documentation updated.
*
* Version 1.0.1 2010/10/05
* Production release and review comments incorporated.
*
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated.
*
* Version 1.0.2 2010/11/11
* Documentation updated.
*
* Version 1.0.1 2010/10/05
* Production release and review comments incorporated.
*
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H

660
bsp/efm32/Libraries/CMSIS/Include/arm_math.h
View File

File diff suppressed because it is too large Load Diff

6
bsp/efm32/Libraries/CMSIS/Include/core_cm3.h
View File

@ -636,14 +636,14 @@ typedef struct
__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[29];
uint32_t RESERVED3[29];
__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
__I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t RESERVED4[43];
uint32_t RESERVED4[43];
__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6];
uint32_t RESERVED5[6];
__I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */

6
bsp/efm32/Libraries/CMSIS/Include/core_cm4.h
View File

@ -669,14 +669,14 @@ typedef struct
__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[29];
uint32_t RESERVED3[29];
__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
__I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t RESERVED4[43];
uint32_t RESERVED4[43];
__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6];
uint32_t RESERVED5[6];
__I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */

6
bsp/efm32/Libraries/CMSIS/Include/core_sc300.h
View File

@ -607,14 +607,14 @@ typedef struct
__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[29];
uint32_t RESERVED3[29];
__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
__I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t RESERVED4[43];
uint32_t RESERVED4[43];
__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t RESERVED5[6];
uint32_t RESERVED5[6];
__I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */

110
bsp/efm32/Libraries/CMSIS/RTOS/cmsis_os.h
View File

@ -1,20 +1,20 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2012 ARM Limited. All rights reserved.
*
/* ----------------------------------------------------------------------
* Copyright (C) 2012 ARM Limited. All rights reserved.
*
* $Date: 5. March 2012
* $Revision: V0.03
*
*
* Project: CMSIS-RTOS API
* Title: cmsis_os.h template header file
*
*
* Version 0.02
* Initial Proposal Phase
* Initial Proposal Phase
* Version 0.03
* osKernelStart added, optional feature: main started as thread
* osSemaphores have standard behaviour
* osTimerCreate does not start the timer, added osTimerStart
* osThreadPass is renamed to osThreadYield
* -------------------------------------------------------------------- */
* osThreadPass is renamed to osThreadYield
* -------------------------------------------------------------------- */
/**
\page cmsis_os_h Header File Template: cmsis_os.h
@ -35,8 +35,8 @@ The file cmsis_os.h contains:
All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions.
Definitions that are prefixed \b os_ are not used in the application code but local to this header file.
All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread.
Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation.
Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation.
These definitions can be specific to the underlying RTOS kernel.
Definitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer
@ -52,7 +52,7 @@ The following CMSIS-RTOS functions can be called from threads and interrupt serv
- \ref osMessagePut, \ref osMessageGet
- \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree
Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called
Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called
from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.
Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time.
@ -73,11 +73,11 @@ extern void thread_sample (void const *argument); // function protot
osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
// Pool definition
osPoolDef(MyPool, 10, long);
osPoolDef(MyPool, 10, long);
\endcode
This header file defines all objects when included in a C/C++ source file. When <b>\#define osObjectsExternal</b> is
This header file defines all objects when included in a C/C++ source file. When <b>\#define osObjectsExternal</b> is
present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be
used throughout the whole project.
@ -92,7 +92,7 @@ used throughout the whole project.
\endcode
*/
#ifndef _CMSIS_OS_H
#define _CMSIS_OS_H
@ -100,7 +100,7 @@ used throughout the whole project.
#define osCMSIS 0x00003 ///< API version (main [31:16] .sub [15:0])
/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlaying RTOS kernel and version number.
#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0])
#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0])
/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string
@ -113,7 +113,7 @@ used throughout the whole project.
#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread
#define osFeature_Semaphore 30 ///< maximum count for SemaphoreInit function
#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available
#include <stdint.h>
#include <stddef.h>
@ -133,7 +133,7 @@ typedef enum {
osPriorityBelowNormal = -1, ///< priority: below normal
osPriorityNormal = 0, ///< priority: normal (default)
osPriorityAboveNormal = +1, ///< priority: above normal
osPriorityHigh = +2, ///< priority: high
osPriorityHigh = +2, ///< priority: high
osPriorityRealtime = +3, ///< priority: realtime (highest)
osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority
} osPriority;
@ -160,23 +160,23 @@ typedef enum {
osErrorValue = 0x86, ///< value of a parameter is out of range.
osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits.
os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization.
} osStatus;
} osStatus;
/// Timer type value for the timer definition
/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
typedef enum {
osTimerOnce = 0, ///< one-shot timer
osTimerPeriodic = 1 ///< repeating timer
} os_timer_type;
osTimerOnce = 0, ///< one-shot timer
osTimerPeriodic = 1 ///< repeating timer
} os_timer_type;
/// Entry point of a thread.
/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
typedef void (*os_pthread) (void const *argument);
typedef void (*os_pthread) (void const *argument);
/// Entry point of a timer call back function.
/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
typedef void (*os_ptimer) (void const *argument);
typedef void (*os_ptimer) (void const *argument);
// >>> the following data type definitions may shall adapted towards a specific RTOS
@ -240,7 +240,7 @@ typedef const struct os_semaphore_def {
/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
typedef const struct os_pool_def {
uint32_t pool_sz; ///< number of items (elements) in the pool
uint32_t item_sz; ///< size of an item
uint32_t item_sz; ///< size of an item
void *pool; ///< pointer to memory for pool
} osPoolDef_t;
@ -248,7 +248,7 @@ typedef const struct os_pool_def {
/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
typedef const struct os_messageQ_def {
uint32_t queue_sz; ///< number of elements in the queue
uint32_t item_sz; ///< size of an item
uint32_t item_sz; ///< size of an item
void *pool; ///< memory array for messages
} osMessageQDef_t;
@ -256,23 +256,23 @@ typedef const struct os_messageQ_def {
/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
typedef const struct os_mailQ_def {
uint32_t queue_sz; ///< number of elements in the queue
uint32_t item_sz; ///< size of an item
uint32_t item_sz; ///< size of an item
void *pool; ///< memory array for mail
} osMailQDef_t;
/// Event structure contains detailed information about an event.
/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
/// Event structure contains detailed information about an event.
/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
/// However the struct may be extended at the end.
typedef struct {
osStatus status; ///< status code: event or error information
union {
uint32_t v; ///< message as 32-bit value
uint32_t v; ///< message as 32-bit value
void *p; ///< message or mail as void pointer
int32_t signals; ///< signal flags
int32_t signals; ///< signal flags
} value; ///< event value
union {
osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
} def; ///< event definition
} osEvent;
@ -283,11 +283,11 @@ typedef struct {
/// \param[in] thread_def thread definition referenced with \ref osThread.
/// \param[in] argument pointer that is passed to the thread function as start argument.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
osStatus osKernelStart (osThreadDef_t *thread_def, void *argument);
/// Check if the RTOS kernel is already started.
/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
/// \return 0 RTOS is not started, 1 RTOS is started.
int32_t osKernelRunning(void);
@ -299,7 +299,7 @@ int32_t osKernelRunning(void);
/// \param priority initial priority of the thread function.
/// \param instances number of possible thread instances.
/// \param stacksz stack size (in bytes) requirements for the thread function.
/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osThreadDef(name, priority, instances, stacksz) \
@ -312,7 +312,7 @@ osThreadDef_t os_thread_def_##name = \
/// Access a Thread defintion.
/// \param name name of the thread definition object.
/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osThread(name) \
&os_thread_def_##name
@ -341,7 +341,7 @@ osStatus osThreadTerminate (osThreadId thread_id);
/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
osStatus osThreadYield (void);
/// Change priority of an active thread.
/// Change priority of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] priority new priority value for the thread function.
/// \return status code that indicates the execution status of the function.
@ -359,7 +359,7 @@ osPriority osThreadGetPriority (osThreadId thread_id);
// ==== Generic Wait Functions ====
/// Wait for Timeout (Time Delay)
/// \param[in] millisec time delay value
/// \param[in] millisec time delay value
/// \return status code that indicates the execution status of the function.
osStatus osDelay (uint32_t millisec);
@ -378,7 +378,7 @@ osEvent osWait (uint32_t millisec);
/// Define a Timer object.
/// \param name name of the timer object.
/// \param function name of the timer call back function.
/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osTimerDef(name, function) \
@ -391,7 +391,7 @@ osTimerDef_t os_timer_def_##name = \
/// Access a Timer definition.
/// \param name name of the timer object.
/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osTimer(name) \
&os_timer_def_##name
@ -452,7 +452,7 @@ osEvent osSignalWait (int32_t signals, uint32_t millisec);
/// Define a Mutex.
/// \param name name of the mutex object.
/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMutexDef(name) \
@ -464,7 +464,7 @@ osMutexDef_t os_mutex_def_##name = { 0 }
/// Access a Mutex defintion.
/// \param name name of the mutex object.
/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMutex(name) \
&os_mutex_def_##name
@ -495,7 +495,7 @@ osStatus osMutexRelease (osMutexId mutex_id);
/// Define a Semaphore object.
/// \param name name of the semaphore object.
/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osSemaphoreDef(name) \
@ -507,7 +507,7 @@ osSemaphoreDef_t os_semaphore_def_##name = { 0 }
/// Access a Semaphore definition.
/// \param name name of the semaphore object.
/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osSemaphore(name) \
&os_semaphore_def_##name
@ -533,7 +533,7 @@ int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
#endif // Semaphore available
// ==== Memory Pool Management Functions ====
#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available
@ -542,7 +542,7 @@ osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
/// \param name name of the memory pool.
/// \param no maximum number of objects (elements) in the memory pool.
/// \param type data type of a single object (element).
/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osPoolDef(name, no, type) \
@ -555,7 +555,7 @@ osPoolDef_t os_pool_def_##name = \
/// \brief Access a Memory Pool definition.
/// \param name name of the memory pool
/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osPool(name) \
&os_pool_def_##name
@ -572,7 +572,7 @@ osPoolId osPoolCreate (osPoolDef_t *pool_def);
/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
void *osPoolAlloc (osPoolId pool_id);
/// Allocate a memory block from a memory pool and set memory block to zero
/// Allocate a memory block from a memory pool and set memory block to zero
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \return address of the allocated memory block or NULL in case of no memory available.
/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
@ -596,7 +596,7 @@ osStatus osPoolFree (osPoolId pool_id, void *block);
/// \param name name of the queue.
/// \param queue_sz maximum number of messages in the queue.
/// \param type data type of a single message element (for debugger).
/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMessageQDef(name, queue_sz, type) \
@ -609,7 +609,7 @@ osMessageQDef_t os_messageQ_def_##name = \
/// \brief Access a Message Queue Definition.
/// \param name name of the queue
/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMessageQ(name) \
&os_messageQ_def_##name
@ -647,7 +647,7 @@ osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
/// \param name name of the queue
/// \param queue_sz maximum number of messages in queue
/// \param type data type of a single message element
/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMailQDef(name, queue_sz, type) \
@ -657,10 +657,10 @@ extern osMailQDef_t os_mailQ_def_##name
osMailQDef_t os_mailQ_def_##name = \
{ (queue_sz), sizeof (type) }
#endif
/// \brief Access a Mail Queue Definition
/// \param name name of the queue
/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMailQ(name) \
&os_mailQ_def_##name
@ -706,7 +706,7 @@ osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
osStatus osMailFree (osMailQId queue_id, void *mail);
#endif // Mail Queues available

2
bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/IAR/startup_efm32g.c
View File

@ -39,7 +39,7 @@ extern void __iar_program_start(void);
extern void SystemInit(void);
/* Auto defined by linker */
extern unsigned char CSTACK$$Limit;
extern unsigned char CSTACK$$Limit;
__weak void Reset_Handler(void)
{

18
bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/system_efm32g.c
View File

@ -64,18 +64,18 @@
/* Do not define variable if HF crystal oscillator not present */
#if (EFM32_HFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System HFXO clock. */
/** System HFXO clock. */
static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
#ifndef EFM32_LFXO_FREQ
#ifndef EFM32_LFXO_FREQ
#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
#endif
/* Do not define variable if LF crystal oscillator not present */
#if (EFM32_LFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System LFXO clock. */
/** System LFXO clock. */
static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
@ -118,13 +118,13 @@ uint32_t SystemCoreClock;
uint32_t SystemCoreClockGet(void)
{
uint32_t ret;
ret = SystemHFClockGet();
#if defined (_EFM32_GIANT_FAMILY)
/* Leopard/Giant Gecko has an additional divider */
ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));
#endif
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
/* Keep CMSIS variable up-to-date just in case */
@ -147,7 +147,7 @@ uint32_t SystemCoreClockGet(void)
uint32_t SystemHFClockGet(void)
{
uint32_t ret;
switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
{
@ -160,11 +160,11 @@ uint32_t SystemHFClockGet(void)
ret = 0;
#endif
break;
case CMU_STATUS_LFRCOSEL:
ret = EFM32_LFRCO_FREQ;
break;
case CMU_STATUS_HFXOSEL:
#if (EFM32_HFXO_FREQ > 0)
ret = SystemHFXOClock;
@ -174,7 +174,7 @@ uint32_t SystemHFClockGet(void)
ret = 0;
#endif
break;
default: /* CMU_STATUS_HFRCOSEL */
switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
{

2
bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/IAR/startup_efm32gg.c
View File

@ -39,7 +39,7 @@ extern void __iar_program_start(void);
extern void SystemInit(void);
/* Auto defined by linker */
extern unsigned char CSTACK$$Limit;
extern unsigned char CSTACK$$Limit;
__weak void Reset_Handler(void)
{

18
bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/system_efm32gg.c
View File

@ -64,18 +64,18 @@
/* Do not define variable if HF crystal oscillator not present */
#if (EFM32_HFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System HFXO clock. */
/** System HFXO clock. */
static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
#ifndef EFM32_LFXO_FREQ
#ifndef EFM32_LFXO_FREQ
#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
#endif
/* Do not define variable if LF crystal oscillator not present */
#if (EFM32_LFXO_FREQ > 0)
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
/** System LFXO clock. */
/** System LFXO clock. */
static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
#endif
@ -118,13 +118,13 @@ uint32_t SystemCoreClock;
uint32_t SystemCoreClockGet(void)
{
uint32_t ret;
ret = SystemHFClockGet();
#if defined (_EFM32_GIANT_FAMILY)
/* Leopard/Giant Gecko has an additional divider */
ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));
#endif
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
/* Keep CMSIS variable up-to-date just in case */
@ -147,7 +147,7 @@ uint32_t SystemCoreClockGet(void)
uint32_t SystemHFClockGet(void)
{
uint32_t ret;
switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
{
@ -160,11 +160,11 @@ uint32_t SystemHFClockGet(void)
ret = 0;
#endif
break;
case CMU_STATUS_LFRCOSEL:
ret = EFM32_LFRCO_FREQ;
break;
case CMU_STATUS_HFXOSEL:
#if (EFM32_HFXO_FREQ > 0)
ret = SystemHFXOClock;
@ -174,7 +174,7 @@ uint32_t SystemHFClockGet(void)
ret = 0;
#endif
break;
default: /* CMU_STATUS_HFRCOSEL */
switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
{

4
bsp/efm32/Libraries/emlib/inc/em_acmp.h
View File

@ -173,7 +173,7 @@ typedef struct
* power used by the VDD and bandgap references. */
bool lowPowerReferenceEnabled;
/** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
/** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
* Valid values are in the range 0-63. */
uint32_t vddLevel;
@ -229,7 +229,7 @@ typedef struct
* power used by the VDD and bandgap references. */
bool lowPowerReferenceEnabled;
/** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
/** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
* Valid values are in the range 0-63. */
uint32_t vddLevel;

4
bsp/efm32/Libraries/emlib/inc/em_burtc.h
View File

@ -289,8 +289,8 @@ __STATIC_INLINE void BURTC_Enable(bool enable)
if( enable )
{
BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);
}
else
}
else
{
BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);
}

4
bsp/efm32/Libraries/emlib/inc/em_cmu.h
View File

@ -432,7 +432,7 @@ typedef enum
#endif
#if defined(USB_PRESENT)
cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
(_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) |
@ -441,7 +441,7 @@ typedef enum
#endif
#if defined(USB_PRESENT)
cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
(CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
(_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) |

8
bsp/efm32/Libraries/emlib/inc/em_dma.h
View File

@ -251,7 +251,7 @@ typedef struct
/** Enable repeated loop */
bool enable;
/** Width of transfer, reload value for nMinus1 */
uint16_t nMinus1;
uint16_t nMinus1;
} DMA_CfgLoop_TypeDef;
@ -335,20 +335,20 @@ typedef struct
* Pointer to the controlblock in memory holding descriptors (channel
* control data structures). This memory must be properly aligned
* according to requirements.
*
*
* Alignment requirements are
* a) 5 bits base requirement, bits [4:0]
* b) Add the number of bits needed to represent the wanted number
* of channels
* c) Align structure with this number of bits set to zero
*
*
* Examples: 4 channels, 5 + 2 (channels 0 to 3) = 7 bits
* 7 bit alignment, 64 byte address alignment
* 8 channels, 5 + 3 (channels 0 to 7) = 8 bits
* 8 bit alignment, 256 byte address alignment
* 12 channels, 5 + 4 (channels 0 to 11) = 9 bits
* 9 bit alignment, 512 byte address alignment
*
*
* Please refer to the reference manual, DMA chapter for more details.
*
* It is possible to provide a smaller memory block, only covering

10
bsp/efm32/Libraries/emlib/inc/em_ebi.h
View File

@ -157,7 +157,7 @@ typedef enum
} EBI_ALow_TypeDef;
/** Adress Pin Enable, high limit - higher limit of pins to enable */
typedef enum
typedef enum
{
/** All EBI_A pins are disabled */
ebiAHighA0 = EBI_ROUTE_APEN_A0,
@ -218,9 +218,9 @@ typedef enum {
/** EBI PIN I/O Location 1 */
ebiLocation1 = EBI_ROUTE_LOCATION_LOC1,
/** EBI PIN I/O Location 2 */
ebiLocation2 = EBI_ROUTE_LOCATION_LOC2,
ebiLocation2 = EBI_ROUTE_LOCATION_LOC2,
/** EBI PIN I/O Location 3 */
// ebiLocation3 = EBI_ROUTE_LOCATION_LOC3,
// ebiLocation3 = EBI_ROUTE_LOCATION_LOC3,
} EBI_Location_TypeDef;
#endif
@ -626,7 +626,7 @@ __STATIC_INLINE void EBI_TFTPixelSet(int pixel, uint32_t color)
******************************************************************************/
__STATIC_INLINE void EBI_TFTMaskBlendMode(EBI_TFTMaskBlend_TypeDef maskBlend)
{
EBI->TFTCTRL = (EBI->TFTCTRL & (~_EBI_TFTCTRL_MASKBLEND_MASK))|maskBlend;
EBI->TFTCTRL = (EBI->TFTCTRL & (~_EBI_TFTCTRL_MASKBLEND_MASK))|maskBlend;
}
@ -676,7 +676,7 @@ __STATIC_INLINE uint32_t EBI_TFTHCount(void)
/***************************************************************************//**
* @brief Set Frame Buffer Trigger
* @brief Set Frame Buffer Trigger
* Frame buffer pointer will be updated either on each horizontal line (hsync)
* or vertical update (vsync)(
******************************************************************************/

14
bsp/efm32/Libraries/emlib/inc/em_emu.h
View File

@ -62,8 +62,8 @@ typedef enum
/** Select ULFRCO as duty oscillator in EM4 */
emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO,
/** Select LFXO as duty oscillator in EM4 */
emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO,
/** Select LFRCO as duty oscillator in EM4 */
emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO,
/** Select LFRCO as duty oscillator in EM4 */
emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO
} EMU_EM4Osc_TypeDef;
@ -124,15 +124,15 @@ typedef enum
#if defined(_EFM32_GIANT_FAMILY)
/** Energy Mode 4 initialization structure */
typedef struct
typedef struct
{
/** Lock configuration of regulator, BOD and oscillator */
bool lockConfig;
/** EM4 duty oscillator */
EMU_EM4Osc_TypeDef osc;
EMU_EM4Osc_TypeDef osc;
/** Wake up on EM4 BURTC interrupt */
bool buRtcWakeup;
/** Enable EM4 voltage regulator */
/** Enable EM4 voltage regulator */
bool vreg;
} EMU_EM4Init_TypeDef;
@ -145,7 +145,7 @@ typedef struct
}
/** Backup Power Domain Initialization structure */
typedef struct
typedef struct
{
/* Backup Power Domain power configuration */
@ -153,7 +153,7 @@ typedef struct
EMU_Probe_TypeDef probe;
/** Enable BOD calibration mode */
bool bodCal;
/** Enable BU_STAT status pin for active BU mode */
/** Enable BU_STAT status pin for active BU mode */
bool statusPinEnable;
/* Backup Power Domain connection configuration */

2
bsp/efm32/Libraries/emlib/inc/em_msc.h
View File

@ -88,7 +88,7 @@ typedef enum
#if defined (_EFM32_GIANT_FAMILY)
/** Strategy for prioritized bus access */
typedef enum {
typedef enum {
mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses */
mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses */
mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses */

4
bsp/efm32/Libraries/emlib/inc/em_rmu.h
View File

@ -59,10 +59,10 @@ typedef enum
{
#if defined(_EFM32_GIANT_FAMILY)
/** Reset control over Backup Power Domain */
rmuResetBU = _RMU_CTRL_BURSTEN_SHIFT,
rmuResetBU = _RMU_CTRL_BURSTEN_SHIFT,
#endif
/** Allow Cortex-M3 lock up signal */
rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_SHIFT
rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_SHIFT
} RMU_Reset_TypeDef;
/*******************************************************************************

2
bsp/efm32/Libraries/emlib/inc/em_usart.h
View File

@ -276,7 +276,7 @@ typedef struct
#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
/** USART PRS trigger enable */
typedef struct
typedef struct
{
#if defined(_EFM32_GIANT_FAMILY)
/** Enable AUTOTX */

6
bsp/efm32/Libraries/emlib/src/em_burtc.c
View File

@ -87,7 +87,7 @@ __STATIC_INLINE uint32_t BURTC_DivToLog2(uint32_t div)
* Configures the BURTC peripheral.
*
* @note
* Before initialization, BURTC module must first be enabled by clearing the
* Before initialization, BURTC module must first be enabled by clearing the
* reset bit in the RMU, i.e.
* @verbatim
* RMU_ResetControl(rmuResetBU, false);
@ -123,7 +123,7 @@ void BURTC_Init(const BURTC_Init_TypeDef *burtcInit)
presc = BURTC_DivToLog2(burtcInit->clkDiv);
/* Make sure all registers are updated simultaneously */
if (burtcInit->enable)
if (burtcInit->enable)
{
BURTC_FreezeEnable(true);
}
@ -132,7 +132,7 @@ void BURTC_Init(const BURTC_Init_TypeDef *burtcInit)
BURTC->LPMODE = (uint32_t)(burtcInit->lowPowerMode);
/* New configuration */
ctrl = ((BURTC_CTRL_RSTEN) |
ctrl = ((BURTC_CTRL_RSTEN) |
(burtcInit->mode) |
(burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT) |
(burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT) |

8
bsp/efm32/Libraries/emlib/src/em_cmu.c
View File

@ -1377,14 +1377,14 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
/* frequencies above 32MHz */
if(SystemHFXOClockGet() > CMU_MAX_FREQ_HFLE)
{
CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ |
CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ |
/* Must have HFLE enabled to access some LE peripherals >=32MHz */
CMU_CTRL_HFLE;
} else {
/* This can happen if the user configures the EFM32_HFXO_FREQ to */
/* use another oscillator frequency */
CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;
}
#endif
@ -1475,7 +1475,7 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 1);
/* Enable DIV4 factor for peripheral clock */
BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
_CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
}
#endif

16
bsp/efm32/Libraries/emlib/src/em_ebi.c
View File

@ -105,7 +105,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
if ( ebiInit->enable)
if ( ebiInit->enable)
{
ctrl |= EBI_CTRL_BANK0EN;
}
@ -117,13 +117,13 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
_EBI_CTRL_ARDY1EN_MASK|
_EBI_CTRL_ARDYTO1DIS_MASK|
_EBI_CTRL_NOIDLE1_MASK|
_EBI_CTRL_BANK1EN_MASK);
_EBI_CTRL_BANK1EN_MASK);
ctrl |= (ebiInit->mode << _EBI_CTRL_MODE1_SHIFT);
ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT);
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
if ( ebiInit->enable)
if ( ebiInit->enable)
{
ctrl |= EBI_CTRL_BANK1EN;
}
@ -141,7 +141,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
if ( ebiInit->enable)
if ( ebiInit->enable)
{
ctrl |= EBI_CTRL_BANK2EN;
}
@ -153,13 +153,13 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
_EBI_CTRL_ARDY3EN_MASK|
_EBI_CTRL_ARDYTO3DIS_MASK|
_EBI_CTRL_NOIDLE3_MASK|
_EBI_CTRL_BANK3EN_MASK);
_EBI_CTRL_BANK3EN_MASK);
ctrl |= (ebiInit->mode << _EBI_CTRL_MODE3_SHIFT);
ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT);
ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT);
ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
if ( ebiInit->enable)
if ( ebiInit->enable)
{
ctrl |= EBI_CTRL_BANK3EN;
}
@ -172,7 +172,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
_EBI_CTRL_BANK1EN_MASK|
_EBI_CTRL_BANK2EN_MASK|
_EBI_CTRL_BANK3EN_MASK);
if ( ebiInit->enable)
if ( ebiInit->enable)
{
if ( ebiInit->banks & EBI_BANK0 )
{
@ -265,7 +265,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
EBI_ChipSelectEnable(ebiInit->csLines, true);
/* Activate new configuration */
EBI->CTRL = ctrl;
EBI->CTRL = ctrl;
}

26
bsp/efm32/Libraries/emlib/src/em_emu.c
View File

@ -402,16 +402,16 @@ void EMU_EM4Init(EMU_EM4Init_TypeDef *em4init)
_EMU_EM4CONF_OSC_MASK|
_EMU_EM4CONF_BURTCWU_MASK|
_EMU_EM4CONF_VREGEN_MASK);
/* Configure new settings */
em4conf |= (
(em4init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT)|
(em4init->osc)|
(em4init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT)|
(em4init->vreg << _EMU_EM4CONF_VREGEN_SHIFT));
/* Apply configuration. Note that lock can be set after this stage. */
EMU->EM4CONF = em4conf;
EMU->EM4CONF = em4conf;
}
@ -432,15 +432,15 @@ void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
_EMU_PWRCONF_VOUTSTRONG_MASK|
_EMU_PWRCONF_VOUTMED_MASK|
_EMU_PWRCONF_VOUTWEAK_MASK);
reg |= (bupdInit->resistor|
(bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT)|
(bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT)|
(bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT));
(bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT));
EMU->PWRCONF = reg;
/* Set backup domain inactive mode configuration */
/* Set backup domain inactive mode configuration */
reg = EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK);
reg |= (bupdInit->inactivePower);
EMU->BUINACT = reg;
@ -456,14 +456,14 @@ void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
_EMU_BUCTRL_BODCAL_MASK|
_EMU_BUCTRL_STATEN_MASK|
_EMU_BUCTRL_EN_MASK);
/* Note use of ->enable to both enable BUPD, use BU_VIN pin input and
/* Note use of ->enable to both enable BUPD, use BU_VIN pin input and
release reset */
reg |= (bupdInit->probe|
(bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT)|
(bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT)|
(bupdInit->enable << _EMU_BUCTRL_EN_SHIFT));
/* Enable configuration */
EMU->BUCTRL = reg;
@ -479,14 +479,14 @@ void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
* @brief
* Configure Backup Power Domain BOD Threshold value
* @note
* These values are precalibrated
* These values are precalibrated
* @param[in] mode Active or Inactive mode
* @param[in] value
******************************************************************************/
void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value)
{
EFM_ASSERT(value<4);
switch(mode)
{
case emuBODMode_Active:
@ -503,7 +503,7 @@ void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value)
* @brief
* Configure Backup Power Domain BOD Threshold Range
* @note
* These values are precalibrated
* These values are precalibrated
* @param[in] mode Active or Inactive mode
* @param[in] value
******************************************************************************/

2
bsp/efm32/Libraries/emlib/src/em_lesense.c
View File

@ -533,7 +533,7 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh,
/* Channel specific configuration of clocks, sample mode, excitation pin mode
* alternate excitation usage and interrupt mode on scan channel chIdx in
* LESENSE_CHchIdx_INTERACT. */
LESENSE->CH[chIdx].INTERACT = ((uint32_t)confCh->exClk <<
LESENSE->CH[chIdx].INTERACT = ((uint32_t)confCh->exClk <<
_LESENSE_CH_INTERACT_EXCLK_SHIFT) |
((uint32_t)confCh->sampleClk <<
_LESENSE_CH_INTERACT_SAMPLECLK_SHIFT) |

2
bsp/efm32/Libraries/emlib/src/em_msc.c
View File

@ -55,7 +55,7 @@
* @brief
* Enables the flash controller for writing.
* @note
* IMPORTANT: This function must be called before flash operations when
* IMPORTANT: This function must be called before flash operations when
* AUXHFRCO clock has been changed from default 14MHz band.
******************************************************************************/
void MSC_Init(void)

22
bsp/efm32/Libraries/emlib/src/em_opamp.c
View File

@ -243,7 +243,7 @@ void OPAMP_Disable( DAC_TypeDef *dac, OPAMP_TypeDef opa )
void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init )
{
uint32_t offset;
EFM_ASSERT( DAC_REF_VALID( dac ) );
EFM_ASSERT( DAC_OPA_VALID( opa ) );
EFM_ASSERT( init->bias <= ( _DAC_BIASPROG_BIASPROG_MASK >>
@ -267,13 +267,13 @@ void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef
}
else
{
EFM_ASSERT( init->offset <= ( _DAC_CAL_CH0OFFSET_MASK >>
EFM_ASSERT( init->offset <= ( _DAC_CAL_CH0OFFSET_MASK >>
_DAC_CAL_CH0OFFSET_SHIFT ) );
dac->CAL = ( dac->CAL & ~_DAC_CAL_CH0OFFSET_MASK ) |
( init->offset << _DAC_CAL_CH0OFFSET_SHIFT );
( init->offset << _DAC_CAL_CH0OFFSET_SHIFT );
}
dac->OPA0MUX = (uint32_t)init->resSel |
(uint32_t)init->outMode |
init->outPen |
@ -315,11 +315,11 @@ void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef
}
else
{
EFM_ASSERT( init->offset <= ( _DAC_CAL_CH1OFFSET_MASK >>
EFM_ASSERT( init->offset <= ( _DAC_CAL_CH1OFFSET_MASK >>
_DAC_CAL_CH1OFFSET_SHIFT ) );
dac->CAL = ( dac->CAL & ~_DAC_CAL_CH1OFFSET_MASK ) |
( init->offset << _DAC_CAL_CH1OFFSET_SHIFT );
( init->offset << _DAC_CAL_CH1OFFSET_SHIFT );
}
dac->OPA1MUX = (uint32_t)init->resSel |
@ -370,11 +370,11 @@ void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef
}
else
{
EFM_ASSERT( init->offset <= ( _DAC_OPAOFFSET_OPA2OFFSET_MASK >>
EFM_ASSERT( init->offset <= ( _DAC_OPAOFFSET_OPA2OFFSET_MASK >>
_DAC_OPAOFFSET_OPA2OFFSET_SHIFT ) );
dac->CAL = ( dac->CAL & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK ) |
( init->offset << _DAC_OPAOFFSET_OPA2OFFSET_SHIFT );
( init->offset << _DAC_OPAOFFSET_OPA2OFFSET_SHIFT );
}
dac->OPA2MUX = (uint32_t)init->resSel |

2
bsp/efm32/Libraries/emlib/src/em_rmu.c
View File

@ -1,7 +1,7 @@
/***************************************************************************//**
* @file
* @brief Reset Management Unit (RMU) peripheral module peripheral API
*
*
* @author Energy Micro AS
* @version 3.0.0
*******************************************************************************

2
bsp/efm32/Libraries/emlib/src/em_timer.c
View File

@ -136,7 +136,7 @@ void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init)
{
timer->CMD = TIMER_CMD_STOP;
}
/* Reset counter */
timer->CNT = _TIMER_CNT_RESETVALUE;

6
bsp/efm32/Libraries/emlib/src/em_usart.c
View File

@ -82,7 +82,7 @@
#endif
#if (UART_COUNT == 1)
#define UART_REF_VALID(ref) ((ref)==UART0)
#define UART_REF_VALID(ref) ((ref)==UART0)
#elif (UART_COUNT == 2)
#define UART_REF_VALID(ref) (((ref)==UART0) || ((ref)==UART1))
#else
@ -733,8 +733,8 @@ void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init)
* @brief
* Initialize automatic transmissions using PRS channel as trigger
* @note
* Initialize USART with USART_Init() before setting up PRS configuration
*
* Initialize USART with USART_Init() before setting up PRS configuration
*
* @param[in] usart Pointer to USART to configure
* @param[in] init Pointer to initialization structure
******************************************************************************/

2
bsp/efm32/Libraries/emlib/src/em_vcmp.c
View File

@ -133,7 +133,7 @@ void VCMP_Init(const VCMP_Init_TypeDef *vcmpInit)
while(!VCMP_Ready());
VCMP_LowPowerRefSet(vcmpInit->lowPowerRef);
}
/* Clear edge interrupt */
VCMP_IntClear(VCMP_IF_EDGE);
}

146
bsp/efm32/board.c
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file board.c
* @brief Board support of RT-Thread RTOS for EFM32
* @file board.c
* @brief Board support of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,12 +10,12 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2010-12-21 onelife Initial creation for EFM32
* 2011-05-06 onelife Add EFM32 development kit and SPI Flash support
* 2011-07-12 onelife Add SWO output enable function
* 2011-12-08 onelife Add giant gecko development kit support
* 2011-12-09 onelife Add giant gecko support
* Date Author Notes
* 2010-12-21 onelife Initial creation for EFM32
* 2011-05-06 onelife Add EFM32 development kit and SPI Flash support
* 2011-07-12 onelife Add SWO output enable function
* 2011-12-08 onelife Add giant gecko development kit support
* 2011-12-09 onelife Add giant gecko support
* 2011-12-09 onelife Add LEUART module support
* 2011-12-14 onelife Add LFXO enabling routine in driver initialization
* function
@ -37,19 +37,19 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == RAM_MEM_BASE) || \
((VECTTAB) == FLASH_MEM_BASE))
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == RAM_MEM_BASE) || \
((VECTTAB) == FLASH_MEM_BASE))
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
/***************************************************************************//**
* @addtogroup SysTick_clock_source
* @{
******************************************************************************/
#define SysTick_CLKSource_MASK ((rt_uint32_t)0x00000004)
#define SysTick_CLKSource_RTC ((rt_uint32_t)0x00000000)
#define SysTick_CLKSource_HFCORECLK ((rt_uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_RTC) || \
((SOURCE) == SysTick_CLKSource_HFCORECLK))
#define SysTick_CLKSource_RTC ((rt_uint32_t)0x00000000)
#define SysTick_CLKSource_HFCORECLK ((rt_uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_RTC) || \
((SOURCE) == SysTick_CLKSource_HFCORECLK))
/***************************************************************************//**
* @}
******************************************************************************/
@ -67,20 +67,20 @@
* @note
*
* @param[in] NVIC_VectTab
* Indicate the vector table is allocated in RAM or ROM
* Indicate the vector table is allocated in RAM or ROM
*
* @param[in] Offset
* The vector table offset
******************************************************************************/
static void NVIC_SetVectorTable(
rt_uint32_t NVIC_VectTab,
rt_uint32_t Offset)
rt_uint32_t NVIC_VectTab,
rt_uint32_t Offset)
{
/* Check the parameters */
RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab));
RT_ASSERT(IS_NVIC_OFFSET(Offset));
/* Check the parameters */
RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab));
RT_ASSERT(IS_NVIC_OFFSET(Offset));
SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80);
SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80);
}
/***************************************************************************//**
@ -95,19 +95,19 @@ static void NVIC_SetVectorTable(
static void NVIC_Configuration(void)
{
#ifdef VECT_TAB_RAM
/* Set the vector table allocated at 0x20000000 */
NVIC_SetVectorTable(RAM_MEM_BASE, 0x0);
/* Set the vector table allocated at 0x20000000 */
NVIC_SetVectorTable(RAM_MEM_BASE, 0x0);
#else /* VECT_TAB_FLASH */
/* Set the vector table allocated at 0x00000000 */
NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0);
/* Set the vector table allocated at 0x00000000 */
NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0);
#endif
/* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for
subpriority */
NVIC_SetPriorityGrouping(0x7UL);
/* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for
subpriority */
NVIC_SetPriorityGrouping(0x7UL);
/* Set Base Priority Mask Register */
__set_BASEPRI(EFM32_BASE_PRI_DEFAULT);
/* Set Base Priority Mask Register */
__set_BASEPRI(EFM32_BASE_PRI_DEFAULT);
}
/***************************************************************************//**
@ -119,13 +119,13 @@ static void NVIC_Configuration(void)
* @note
*
* @param[in] SysTick_CLKSource
* Specifies the SysTick clock source.
* Specifies the SysTick clock source.
*
* @arg SysTick_CLKSource_HCLK_Div8
* AHB clock divided by 8 selected as SysTick clock source.
* AHB clock divided by 8 selected as SysTick clock source.
*
* @arg SysTick_CLKSource_HCLK
* AHB clock selected as SysTick clock source.
* AHB clock selected as SysTick clock source.
******************************************************************************/
static void SysTick_CLKSourceConfig(rt_uint32_t SysTick_CLKSource)
{
@ -184,14 +184,14 @@ static void SysTick_Configuration(void)
/* Start LETIMER0 */
LETIMER_Init(LETIMER0, &letimerInit);
#else
rt_uint32_t coreClk;
rt_uint32_t cnts;
rt_uint32_t coreClk;
rt_uint32_t cnts;
coreClk = SystemCoreClockGet();
cnts = coreClk / RT_TICK_PER_SECOND;
coreClk = SystemCoreClockGet();
cnts = coreClk / RT_TICK_PER_SECOND;
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK);
SysTick_Config(cnts);
SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK);
#endif
}
@ -206,9 +206,9 @@ static void SysTick_Configuration(void)
******************************************************************************/
void Swo_Configuration(void)
{
rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000;
rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010;
rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0;
rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000;
rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010;
rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0;
CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO;
/* Enable Serial wire output pin */
@ -258,12 +258,12 @@ void Swo_Configuration(void)
******************************************************************************/
void rt_hw_board_init(void)
{
/* Chip errata */
CHIP_Init();
/* Chip errata */
CHIP_Init();
/* Initialize DVK board register access */
#if defined(EFM32_GXXX_DK)
DVK_init();
DVK_init();
#elif defined(EFM32GG_DK3750)
DVK_init(DVK_Init_EBI);
@ -272,12 +272,12 @@ void rt_hw_board_init(void)
DVK_clearInterruptFlags(BC_INTFLAG_MASK);
#endif
/* config NVIC Configuration */
NVIC_Configuration();
/* config NVIC Configuration */
NVIC_Configuration();
#if defined(EFM32_USING_HFXO)
/* Configure external oscillator */
SystemHFXOClockSet(EFM32_HFXO_FREQUENCY);
/* Configure external oscillator */
SystemHFXOClockSet(EFM32_HFXO_FREQUENCY);
/* Switching the CPU clock source to HFXO */
CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO);
@ -293,15 +293,15 @@ void rt_hw_board_init(void)
#if defined(EFM32_SWO_ENABLE)
/* Enable SWO */
Swo_Configuration();
Swo_Configuration();
#endif
/* Enable high frequency peripheral clock */
CMU_ClockEnable(cmuClock_HFPER, true);
/* Enabling clock to the interface of the low energy modules */
CMU_ClockEnable(cmuClock_CORELE, true);
/* Enable high frequency peripheral clock */
CMU_ClockEnable(cmuClock_HFPER, true);
/* Enabling clock to the interface of the low energy modules */
CMU_ClockEnable(cmuClock_CORELE, true);
/* Enable GPIO clock */
CMU_ClockEnable(cmuClock_GPIO, true);
CMU_ClockEnable(cmuClock_GPIO, true);
/* Configure the SysTick */
SysTick_Configuration();
@ -318,8 +318,8 @@ void rt_hw_board_init(void)
******************************************************************************/
void rt_hw_driver_init(void)
{
/* Initialize DMA */
rt_hw_dma_init();
/* Initialize DMA */
rt_hw_dma_init();
/* Select LFXO for specified module (and wait for it to stabilize) */
#if (!defined(EFM32_USING_LFXO) && defined(RT_USING_RTC))
@ -331,11 +331,11 @@ void rt_hw_driver_init(void)
#error "Low frequency clock source is needed for using LEUART"
#endif
/* Initialize USART */
/* Initialize USART */
#if (defined(RT_USING_USART0) || defined(RT_USING_USART1) || \
defined(RT_USING_USART2) || defined(RT_USING_UART0) || \
defined(RT_USING_UART1))
rt_hw_usart_init();
rt_hw_usart_init();
#endif
/* Initialize LEUART */
@ -343,7 +343,7 @@ void rt_hw_driver_init(void)
rt_hw_leuart_init();
#endif
/* Setup Console */
/* Setup Console */
#if defined(EFM32_GXXX_DK)
DVK_enablePeripheral(DVK_RS232A);
DVK_enablePeripheral(DVK_SPI);
@ -354,31 +354,31 @@ void rt_hw_driver_init(void)
DVK_enablePeripheral(DVK_RS232_LEUART);
#endif
#endif
rt_console_set_device(CONSOLE_DEVICE);
rt_console_set_device(CONSOLE_DEVICE);
/* Initialize Timer */
/* Initialize Timer */
#if (defined(RT_USING_TIMER0) || defined(RT_USING_TIMER1) || defined(RT_USING_TIMER2))
rt_hw_timer_init();
rt_hw_timer_init();
#endif
/* Initialize ADC */
/* Initialize ADC */
#if defined(RT_USING_ADC0)
rt_hw_adc_init();
rt_hw_adc_init();
#endif
/* Initialize ACMP */
/* Initialize ACMP */
#if (defined(RT_USING_ACMP0) || defined(RT_USING_ACMP1))
rt_hw_acmp_init();
rt_hw_acmp_init();
#endif
/* Initialize IIC */
/* Initialize IIC */
#if (defined(RT_USING_IIC0) || defined(RT_USING_IIC1))
rt_hw_iic_init();
rt_hw_iic_init();
#endif
/* Initialize RTC */
/* Initialize RTC */
#if defined(RT_USING_RTC)
rt_hw_rtc_init();
rt_hw_rtc_init();
#endif
/* Enable SPI access to MicroSD card */

126
bsp/efm32/board.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file board.h
* @brief Board support of RT-Thread RTOS for EFM32
* @file board.h
* @brief Board support of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,18 +10,18 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2010-12-21 onelife Initial creation for EFM32
* 2011-05-06 onelife Add EFM32 development kit and SPI Flash support
* 2011-07-12 onelife Add prototype for SWO output enable and interrupt
* Date Author Notes
* 2010-12-21 onelife Initial creation for EFM32
* 2011-05-06 onelife Add EFM32 development kit and SPI Flash support
* 2011-07-12 onelife Add prototype for SWO output enable and interrupt
* context check functions
* 2011-12-08 onelife Add giant gecko development kit support
* 2011-12-09 onelife Add giant gecko support
* 2011-12-08 onelife Add giant gecko development kit support
* 2011-12-09 onelife Add giant gecko support
* 2011-12-09 onelife Add LEUART module support
* 2011-12-14 onelife Add LFXO enabling routine in driver initialization
* function
* 2011-12-20 onelife Move SPI Auto-CS setting to "rtconfig.h"
* 2012-05-15 onelife Modified to compatible with CMSIS v3
* 2012-05-15 onelife Modified to compatible with CMSIS v3
******************************************************************************/
#ifndef __BOARD_H__
#define __BOARD_H__
@ -72,15 +72,15 @@ extern volatile rt_uint32_t rt_system_status;
#define EFM32_SWO_ENABLE
#endif
#define EFM32_NO_DATA (0)
#define EFM32_NO_POINTER (RT_NULL)
#define EFM32_NO_OFFSET (-1)
#define EFM32_NO_DMA (-1)
#define EFM32_NO_DATA (0)
#define EFM32_NO_POINTER (RT_NULL)
#define EFM32_NO_OFFSET (-1)
#define EFM32_NO_DMA (-1)
/* SECTION: SPI Flash */
#if defined(EFM32_USING_SFLASH)
#define SFLASH_CS_PORT (gpioPortC)
#define SFLASH_CS_PIN (8)
#define SFLASH_CS_PORT (gpioPortC)
#define SFLASH_CS_PIN (8)
#endif
/* SECTION: Micro SD */
@ -114,9 +114,9 @@ extern volatile rt_uint32_t rt_system_status;
#endif
/* SECTION: SYSTEM */
#define EFM32_SRAM_END (SRAM_BASE + SRAM_SIZE)
#define EFM32_BASE_PRI_DEFAULT (0x0UL << 5)
#define EFM32_IRQ_PRI_DEFAULT (0x4UL << 5)
#define EFM32_SRAM_END (SRAM_BASE + SRAM_SIZE)
#define EFM32_BASE_PRI_DEFAULT (0x0UL << 5)
#define EFM32_IRQ_PRI_DEFAULT (0x4UL << 5)
/* SECTION: CLOCK */
#define EFM32_USING_HFXO
@ -125,9 +125,9 @@ extern volatile rt_uint32_t rt_system_status;
#if (defined(EFM32_G8XX_STK) || defined(EFM32_GXXX_DK))
#define EFM32_HFXO_FREQUENCY (32000000)
#elif defined(EFM32GG_DK3750)
#define EFM32_HFXO_FREQUENCY (48000000)
#define EFM32_HFXO_FREQUENCY (48000000)
#else
#define EFM32_HFXO_FREQUENCY (00000000)
#define EFM32_HFXO_FREQUENCY (00000000)
#endif
#endif
#if defined(EFM32_USING_LFXO)
@ -141,8 +141,8 @@ extern volatile rt_uint32_t rt_system_status;
#endif
/* SECTION: USART */
#define USART_RX_BUFFER_SIZE (64)
#define LEUART_RX_BUFFER_SIZE (64)
#define USART_RX_BUFFER_SIZE (64)
#define LEUART_RX_BUFFER_SIZE (64)
/* Location count (start from 0) */
#if defined(_EFM32_GECKO_FAMILY)
#define EFM32_USART_LOCATION_COUNT (3)
@ -155,14 +155,14 @@ extern volatile rt_uint32_t rt_system_status;
#endif
/* SUBSECTION: UART */
#define UART_BAUDRATE (115200)
#define UART_BAUDRATE (115200)
/* SUBSECTION: SPI */
/* Max SPI clock: HFPERCLK/2 for master, HFPERCLK/8 for slave */
#define SPI_BAUDRATE (4000000)
#define SPI_BAUDRATE (4000000)
/* SECTION: I2C */
#define IIC_RX_BUFFER_SIZE (32)
#define IIC_RX_BUFFER_SIZE (32)
#if defined(_EFM32_GECKO_FAMILY)
#define EFM32_IIC_LOCATION_COUNT (4)
#elif defined(_EFM32_GIANT_FAMILY)
@ -170,61 +170,61 @@ extern volatile rt_uint32_t rt_system_status;
#endif
/* SECTION: ADC */
#define ADC_CALI_REF (adcRef2V5)
#define ADC_CALI_CH (adcSingleInpCh5)
#define ADC_CONVERT_FREQUENCY (7000000)
#define ADC_CALI_REF (adcRef2V5)
#define ADC_CALI_CH (adcSingleInpCh5)
#define ADC_CONVERT_FREQUENCY (7000000)
#if (RT_CONSOLE_DEVICE == EFM_USART0)
#define CONSOLE_DEVICE RT_USART0_NAME
#define CONSOLE_DEVICE RT_USART0_NAME
#elif (RT_CONSOLE_DEVICE == EFM_USART1)
#define CONSOLE_DEVICE RT_USART1_NAME
#define CONSOLE_DEVICE RT_USART1_NAME
#elif (RT_CONSOLE_DEVICE == EFM_USART2)
#define CONSOLE_DEVICE RT_USART2_NAME
#define CONSOLE_DEVICE RT_USART2_NAME
#elif (RT_CONSOLE_DEVICE == EFM_UART0)
#define CONSOLE_DEVICE RT_UART0_NAME
#define CONSOLE_DEVICE RT_UART0_NAME
#elif (RT_CONSOLE_DEVICE == EFM_UART1)
#define CONSOLE_DEVICE RT_UART1_NAME
#define CONSOLE_DEVICE RT_UART1_NAME
#elif (RT_CONSOLE_DEVICE == EFM_LEUART0)
#define CONSOLE_DEVICE RT_LEUART0_NAME
#define CONSOLE_DEVICE RT_LEUART0_NAME
#elif (RT_CONSOLE_DEVICE == EFM_LEUART1)
#define CONSOLE_DEVICE RT_LEUART1_NAME
#define CONSOLE_DEVICE RT_LEUART1_NAME
#else
#define CONSOLE_DEVICE "NONE"
#define CONSOLE_DEVICE "NONE"
#endif
/* The following defines should be consistent with those in diskio.h */
#define CTRL_SYNC 0
#define GET_SECTOR_COUNT 1
#define GET_SECTOR_SIZE 2
#define GET_BLOCK_SIZE 3
#define MMC_GET_TYPE 10
#define MMC_GET_CSD 11
#define MMC_GET_CID 12
#define MMC_GET_OCR 13
#define MMC_GET_SDSTAT 14
#define CTRL_SYNC 0
#define GET_SECTOR_COUNT 1
#define GET_SECTOR_SIZE 2
#define GET_BLOCK_SIZE 3
#define MMC_GET_TYPE 10
#define MMC_GET_CSD 11
#define MMC_GET_CID 12
#define MMC_GET_OCR 13
#define MMC_GET_SDSTAT 14
/* The above defines should be consistent with those in diskio.h */
/* I/O control options */
#define RT_DEVICE_CTRL_SD_SYNC CTRL_SYNC
#define RT_DEVICE_CTRL_SD_GET_SCOUNT GET_SECTOR_COUNT
#define RT_DEVICE_CTRL_SD_GET_SSIZE GET_SECTOR_SIZE
#define RT_DEVICE_CTRL_SD_GET_BSIZE GET_BLOCK_SIZE
#define RT_DEVICE_CTRL_SD_GET_TYPE MMC_GET_TYPE
#define RT_DEVICE_CTRL_SD_GET_CSD MMC_GET_CSD
#define RT_DEVICE_CTRL_SD_GET_CID MMC_GET_CID
#define RT_DEVICE_CTRL_SD_GET_OCR MMC_GET_OCR
#define RT_DEVICE_CTRL_SD_GET_SDSTAT MMC_GET_SDSTAT
#define RT_DEVICE_CTRL_SD_SYNC CTRL_SYNC
#define RT_DEVICE_CTRL_SD_GET_SCOUNT GET_SECTOR_COUNT
#define RT_DEVICE_CTRL_SD_GET_SSIZE GET_SECTOR_SIZE
#define RT_DEVICE_CTRL_SD_GET_BSIZE GET_BLOCK_SIZE
#define RT_DEVICE_CTRL_SD_GET_TYPE MMC_GET_TYPE
#define RT_DEVICE_CTRL_SD_GET_CSD MMC_GET_CSD
#define RT_DEVICE_CTRL_SD_GET_CID MMC_GET_CID
#define RT_DEVICE_CTRL_SD_GET_OCR MMC_GET_OCR
#define RT_DEVICE_CTRL_SD_GET_SDSTAT MMC_GET_SDSTAT
/*! fixme: move the following define to Rtdef.h */
#define RT_DEVICE_CTRL_USART_RBUFFER (0xF1) /*!< set USART/UART rx buffer */
#define RT_DEVICE_CTRL_LEUART_RBUFFER (0xF2) /*!< set LEUART rx buffer */
#define RT_DEVICE_CTRL_IIC_SETTING (0xF3) /*!< change IIC setting */
#define RT_DEVICE_CTRL_TIMER_PERIOD (0xF4) /*!< set Timer timeout period */
#define RT_DEVICE_CTRL_ADC_MODE (0xF5) /*!< change ADC mode */
#define RT_DEVICE_CTRL_ADC_RESULT (0xF6) /*!< get ADC result */
#define RT_DEVICE_CTRL_ACMP_INIT (0xF7) /*!< Initialize ACMP */
#define RT_DEVICE_CTRL_ACMP_OUTPUT (0xF8) /*!< get ACMP output */
#define RT_DEVICE_CTRL_USART_RBUFFER (0xF1) /*!< set USART/UART rx buffer */
#define RT_DEVICE_CTRL_LEUART_RBUFFER (0xF2) /*!< set LEUART rx buffer */
#define RT_DEVICE_CTRL_IIC_SETTING (0xF3) /*!< change IIC setting */
#define RT_DEVICE_CTRL_TIMER_PERIOD (0xF4) /*!< set Timer timeout period */
#define RT_DEVICE_CTRL_ADC_MODE (0xF5) /*!< change ADC mode */
#define RT_DEVICE_CTRL_ADC_RESULT (0xF6) /*!< get ADC result */
#define RT_DEVICE_CTRL_ACMP_INIT (0xF7) /*!< Initialize ACMP */
#define RT_DEVICE_CTRL_ACMP_OUTPUT (0xF8) /*!< get ACMP output */
/* Exported functions ------------------------------------------------------- */
void rt_hw_board_init(void);

1256
bsp/efm32/dev_accel.c
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File diff suppressed because it is too large Load Diff

146
bsp/efm32/dev_accel.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_accel.h
* @brief Accelerometer driver of RT-Thread RTOS for EFM32
* @file dev_accel.h
* @brief Accelerometer driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,10 +10,10 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* 2011-07-13 onelife Initial creation for using EFM32 ADC module to
* Date Author Notes
* 2011-07-13 onelife Initial creation for using EFM32 ADC module to
* interface the Freescale MMA7361L
* 2011-08-02 onelife Add digital interface support of using EFM32 IIC
* 2011-08-02 onelife Add digital interface support of using EFM32 IIC
* module for the Freescale MMA7455L
******************************************************************************/
#ifndef __DEV_ACCEL_H__
@ -27,95 +27,95 @@
/* Exported types ------------------------------------------------------------*/
struct efm32_accel_result_t
{
rt_int32_t x;
rt_int32_t y;
rt_int32_t z;
rt_int32_t x;
rt_int32_t y;
rt_int32_t z;
};
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* MMA7361LC
g-Select g-Range Sensitivity
0 1.5 g 800 mV/g
1 6 g 206 mV/g
/* MMA7361LC
g-Select g-Range Sensitivity
0 1.5 g 800 mV/g
1 6 g 206 mV/g
MMA7455L
g-Select g-Range Sensitivity
0 2 g 64 LSB/g
1 4 g 32 LSB/g
2 8 g 16 LSB/g
MMA7455L
g-Select g-Range Sensitivity
0 2 g 64 LSB/g
1 4 g 32 LSB/g
2 8 g 16 LSB/g
*/
#define ACCEL_G_SELECT (0)
#define ACCEL_G_SELECT (0)
#define ACCEL_CAL_SAMPLES (4) /* Must be multiple of 2 */
#define ACCEL_CAL_ROUND (50)
#define ACCEL_CAL_SIMPLE (0)
#define ACCEL_CAL_INTERACT (1)
#define ACCEL_CAL_SAMPLES (4) /* Must be multiple of 2 */
#define ACCEL_CAL_ROUND (50)
#define ACCEL_CAL_SIMPLE (0)
#define ACCEL_CAL_INTERACT (1)
#if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC)
/* Reading_at_1g = Sensitivity * Max_reading / Refference_voltage */
#define ACCEL_CAL_1G_VALUE {993, 256}
#define ACCEL_CAL_1G_VALUE {993, 256}
#define ACCEL_X_ADC_CH ADC_SCANCTRL_INPUTMASK_CH2
#define ACCEL_Y_ADC_CH ADC_SCANCTRL_INPUTMASK_CH3
#define ACCEL_Z_ADC_CH ADC_SCANCTRL_INPUTMASK_CH4
#define ACCEL_X_ADC_CH ADC_SCANCTRL_INPUTMASK_CH2
#define ACCEL_Y_ADC_CH ADC_SCANCTRL_INPUTMASK_CH3
#define ACCEL_Z_ADC_CH ADC_SCANCTRL_INPUTMASK_CH4
#elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
#define ACCEL_CAL_1G_VALUE {0x3f, 0x1f, 0x0f}
#define ACCEL_CAL_1G_VALUE {0x3f, 0x1f, 0x0f}
#define ACCEL_IIC_SLAVE_ADDRESS (0x1d)
#define ACCEL_INT1_PORT (gpioPortD)
#define ACCEL_INT1_PIN (13)
#define ACCEL_INT2_PORT (gpioPortD)
#define ACCEL_INT2_PIN (12)
#define ACCEL_INT1_PORT (gpioPortD)
#define ACCEL_INT1_PIN (13)
#define ACCEL_INT2_PORT (gpioPortD)
#define ACCEL_INT2_PIN (12)
#define ACCEL_MODE_STANDBY (1 << 0)
#define ACCEL_MODE_MEASUREMENT (1 << 1)
#define ACCEL_MODE_LEVEL (1 << 2)
#define ACCEL_MODE_PULSE (1 << 3)
#define ACCEL_RANGE_8G (1 << 4)
#define ACCEL_RANGE_4G (1 << 5)
#define ACCEL_RANGE_2G (1 << 6)
#define ACCEL_INTPIN_INVERSE (1 << 7)
#define ACCEL_INT_LEVEL_PULSE (1 << 8)
#define ACCEL_INT_PULSE_LEVEL (1 << 9)
#define ACCEL_INT_SINGLE_DOUBLE (1 << 10)
#define ACCEL_DISABLE_X (1 << 11)
#define ACCEL_DISABLE_Y (1 << 12)
#define ACCEL_DISABLE_Z (1 << 13)
#define ACCEL_THRESHOLD_INTEGER (1 << 14) /* For level detection only */
#define ACCEL_BANDWIDTH_125HZ (1 << 15)
#define ACCEL_LEVEL_AND (1 << 16)
#define ACCEL_PULSE_AND (1 << 17)
#define ACCEL_DRIVE_STRONG (1 << 18)
#define ACCEL_SOURCE_LEVEL_X (1 << 19)
#define ACCEL_SOURCE_LEVEL_Y (1 << 20)
#define ACCEL_SOURCE_LEVEL_Z (1 << 21)
#define ACCEL_SOURCE_PULSE_X (1 << 22)
#define ACCEL_SOURCE_PULSE_Y (1 << 23)
#define ACCEL_SOURCE_PULSE_Z (1 << 24)
#define ACCEL_MODE_STANDBY (1 << 0)
#define ACCEL_MODE_MEASUREMENT (1 << 1)
#define ACCEL_MODE_LEVEL (1 << 2)
#define ACCEL_MODE_PULSE (1 << 3)
#define ACCEL_RANGE_8G (1 << 4)
#define ACCEL_RANGE_4G (1 << 5)
#define ACCEL_RANGE_2G (1 << 6)
#define ACCEL_INTPIN_INVERSE (1 << 7)
#define ACCEL_INT_LEVEL_PULSE (1 << 8)
#define ACCEL_INT_PULSE_LEVEL (1 << 9)
#define ACCEL_INT_SINGLE_DOUBLE (1 << 10)
#define ACCEL_DISABLE_X (1 << 11)
#define ACCEL_DISABLE_Y (1 << 12)
#define ACCEL_DISABLE_Z (1 << 13)
#define ACCEL_THRESHOLD_INTEGER (1 << 14) /* For level detection only */
#define ACCEL_BANDWIDTH_125HZ (1 << 15)
#define ACCEL_LEVEL_AND (1 << 16)
#define ACCEL_PULSE_AND (1 << 17)
#define ACCEL_DRIVE_STRONG (1 << 18)
#define ACCEL_SOURCE_LEVEL_X (1 << 19)
#define ACCEL_SOURCE_LEVEL_Y (1 << 20)
#define ACCEL_SOURCE_LEVEL_Z (1 << 21)
#define ACCEL_SOURCE_PULSE_X (1 << 22)
#define ACCEL_SOURCE_PULSE_Y (1 << 23)
#define ACCEL_SOURCE_PULSE_Z (1 << 24)
#define ACCEL_SHIFT_MODE (0)
#define ACCEL_SHIFT_RANGE (4)
#define ACCEL_SHIFT_INT (8)
#define ACCEL_SHIFT_DISABLE (11)
#define ACCEL_SHIFT_SOURCE (19)
#define ACCEL_SHIFT_MODE (0)
#define ACCEL_SHIFT_RANGE (4)
#define ACCEL_SHIFT_INT (8)
#define ACCEL_SHIFT_DISABLE (11)
#define ACCEL_SHIFT_SOURCE (19)
#define ACCEL_MASK_MODE (0X0000000f << ACCEL_SHIFT_MODE)
#define ACCEL_MASK_RANGE (0X00000007 << ACCEL_SHIFT_RANGE)
#define ACCEL_MASK_INT (0X00000007 << ACCEL_SHIFT_INT)
#define ACCEL_MASK_DISABLE (0X00000007 << ACCEL_SHIFT_DISABLE)
#define ACCEL_MASK_SOURCE (0X0000003f << ACCEL_SHIFT_SOURCE)
#define ACCEL_MASK_MODE (0X0000000f << ACCEL_SHIFT_MODE)
#define ACCEL_MASK_RANGE (0X00000007 << ACCEL_SHIFT_RANGE)
#define ACCEL_MASK_INT (0X00000007 << ACCEL_SHIFT_INT)
#define ACCEL_MASK_DISABLE (0X00000007 << ACCEL_SHIFT_DISABLE)
#define ACCEL_MASK_SOURCE (0X0000003f << ACCEL_SHIFT_SOURCE)
#endif
/* Exported functions ------------------------------------------------------- */
rt_err_t efm_accel_get_data(struct efm32_accel_result_t *data,
rt_bool_t lowResolution);
rt_bool_t lowResolution);
rt_err_t efm_accel_config(rt_uint32_t config,
rt_uint8_t level_threshold,
rt_uint8_t pulse_threshold,
rt_uint8_t pulse_duration,
rt_uint8_t pulse_latency,
rt_uint8_t pulse_duration2);
rt_uint8_t level_threshold,
rt_uint8_t pulse_threshold,
rt_uint8_t pulse_duration,
rt_uint8_t pulse_latency,
rt_uint8_t pulse_duration2);
rt_err_t efm_accel_auto_zero(rt_uint8_t mode, rt_tick_t period);
rt_err_t efm_accel_init(void);

40
bsp/efm32/dev_keys.c
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_keys.c
* @brief Keys driver of RT-Thread RTOS for EFM32
* @file dev_keys.c
* @brief Keys driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-12-29 onelife Initial creation for EFM32GG_DK3750 board
******************************************************************************/
@ -48,14 +48,14 @@ static rt_bool_t click;
/* Private functions ---------------------------------------------------------*/
/***************************************************************************//**
* @brief
* Keys interrupt handler
* Keys interrupt handler
*
* @details
*
* @note
*
* @param[in] device
* Pointer to device descriptor
* Pointer to device descriptor
******************************************************************************/
static void efm32_keys_isr(rt_device_t dev)
{
@ -158,18 +158,18 @@ static void efm32_keys_isr(rt_device_t dev)
/***************************************************************************//**
* @brief
* Keys timeout handler
* Keys timeout handler
*
* @details
*
* @note
*
* @param[in] param
* Parameter
* Parameter
******************************************************************************/
static void efm32_keys_timer_isr(void *param)
{
rt_uint16_t joystick;
rt_uint16_t joystick;
joystick = DVK_getJoystick();
@ -277,11 +277,11 @@ void efm32_hw_keys_init(void)
GPIO_IntConfig(KEYS_INT_PORT, KEYS_INT_PIN, true, true, true);
efm32_irq_hook_init_t hook;
hook.type = efm32_irq_type_gpio;
hook.unit = KEYS_INT_PIN;
hook.cbFunc = efm32_keys_isr;
hook.userPtr = RT_NULL;
efm32_irq_hook_register(&hook);
hook.type = efm32_irq_type_gpio;
hook.unit = KEYS_INT_PIN;
hook.cbFunc = efm32_keys_isr;
hook.userPtr = RT_NULL;
efm32_irq_hook_register(&hook);
if ((rt_uint8_t)KEYS_INT_PIN % 2)
{
@ -299,12 +299,12 @@ void efm32_hw_keys_init(void)
/* Enable DVK joystick interrupt */
DVK_enableInterrupt(BC_INTEN_JOYSTICK);
rt_timer_init(&joy.timer,
"joy_tmr",
efm32_keys_timer_isr,
RT_NULL,
KEYS_POLL_TIME,
RT_TIMER_FLAG_PERIODIC);
rt_timer_init(&joy.timer,
"joy_tmr",
efm32_keys_timer_isr,
RT_NULL,
KEYS_POLL_TIME,
RT_TIMER_FLAG_PERIODIC);
joy_dev.init = efm32_keys_init;
joy_dev.open = RT_NULL;

8
bsp/efm32/dev_keys.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_keys.h
* @brief Keys driver of RT-Thread RTOS for EFM32
* @file dev_keys.h
* @brief Keys driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-12-29 onelife Initial creation for EFM32GG_DK3750 board
******************************************************************************/
#ifndef __DEV_KEYS_H__

76
bsp/efm32/dev_lcd.c
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_lcd.c
* @brief LCD driver of RT-Thread RTOS for EFM32
* @file dev_lcd.c
* @brief LCD driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-12-16 onelife Initial creation of address mapped method (pixel
* drive) for EFM32GG_DK3750 board
* 2011-12-29 onelife Add direct drive method (frame buffer) support
@ -451,48 +451,48 @@ rt_err_t efm32_spiLcd_writeRegister(rt_uint8_t reg, rt_uint16_t data)
/***************************************************************************//**
* @brief
* Register LCD device
* Register LCD device
*
* @details
*
* @note
*
* @param[in] device
* Pointer to device descriptor
* Pointer to device descriptor
*
* @param[in] name
* Device name
* Device name
*
* @param[in] flag
* Configuration flags
* Configuration flags
*
* @param[in] iic
* Pointer to IIC device descriptor
* Pointer to IIC device descriptor
*
* @return
* Error code
* Error code
******************************************************************************/
rt_err_t efm32_spiLcd_register(
rt_device_t device,
const char *name,
rt_uint32_t flag,
void *data)
rt_device_t device,
const char *name,
rt_uint32_t flag,
void *data)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device != RT_NULL);
device->type = RT_Device_Class_Graphic;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = RT_NULL;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = efm32_spiLcd_control;
device->user_data = data;
device->type = RT_Device_Class_Graphic;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = RT_NULL;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = efm32_spiLcd_control;
device->user_data = data;
/* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
/* register a character device */
return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
}
/***************************************************************************//**
@ -511,18 +511,18 @@ void efm32_spiLcd_init(void)
DMD_DisplayGeometry *geometry;
rt_uint32_t ret;
do
{
do
{
USART_InitSync_TypeDef init = USART_INITSYNC_DEFAULT;
/* Find SPI device */
lcd = rt_device_find(LCD_USING_DEVICE_NAME);
if (lcd == RT_NULL)
{
lcd_debug("LCD err: Can't find %s!\n", LCD_USING_DEVICE_NAME);
break;
}
lcd_debug("LCD: Find device %s\n", LCD_USING_DEVICE_NAME);
/* Find SPI device */
lcd = rt_device_find(LCD_USING_DEVICE_NAME);
if (lcd == RT_NULL)
{
lcd_debug("LCD err: Can't find %s!\n", LCD_USING_DEVICE_NAME);
break;
}
lcd_debug("LCD: Find device %s\n", LCD_USING_DEVICE_NAME);
/* Config CS pin */
usart = (struct efm32_usart_device_t *)(lcd->user_data);
@ -647,7 +647,7 @@ void efm32_spiLcd_init(void)
}
/* Init LCD info */
flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_TX;
flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_TX;
lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
lcd_info.bits_per_pixel = 16;
lcd_info.width = geometry->xSize;

8
bsp/efm32/dev_lcd.h
View File

@ -1,8 +1,8 @@
/***************************************************************************//**
* @file dev_lcd.h
* @brief LCD driver of RT-Thread RTOS for EFM32
* @file dev_lcd.h
* @brief LCD driver of RT-Thread RTOS for EFM32
* COPYRIGHT (C) 2012, RT-Thread Development Team
* @author onelife
* @author onelife
* @version 1.0
*******************************************************************************
* @section License
@ -10,7 +10,7 @@
* LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
*******************************************************************************
* @section Change Logs
* Date Author Notes
* Date Author Notes
* 2011-12-16 onelife Initial creation of address mapped method (pixel
* drive) for EFM32GG_DK3750 board
******************************************************************************/

138
bsp/efm32/dev_sflash.h
View File

@ -20,85 +20,85 @@
/* Exported types ------------------------------------------------------------*/
enum sflash_inst_type_t
{
/* Instruction only */
sflash_inst_wren = 0x00,
sflash_inst_wrdi,
sflash_inst_rdid_l,
sflash_inst_rdid_s,
sflash_inst_rdsr,
sflash_inst_wrsr,
sflash_inst_be,
sflash_inst_dp,
sflash_inst_rdp,
/* Instruction and address */
sflash_inst_wrlr,
sflash_inst_rdlr,
sflash_inst_read,
sflash_inst_potp,
sflash_inst_pp,
sflash_inst_difp,
sflash_inst_sse,
sflash_inst_se,
/* Instruction, address and dummy read */
sflash_inst_read_f,
sflash_inst_dofr,
sflash_inst_rotp
/* Instruction only */
sflash_inst_wren = 0x00,
sflash_inst_wrdi,
sflash_inst_rdid_l,
sflash_inst_rdid_s,
sflash_inst_rdsr,
sflash_inst_wrsr,
sflash_inst_be,
sflash_inst_dp,
sflash_inst_rdp,
/* Instruction and address */
sflash_inst_wrlr,
sflash_inst_rdlr,
sflash_inst_read,
sflash_inst_potp,
sflash_inst_pp,
sflash_inst_difp,
sflash_inst_sse,
sflash_inst_se,
/* Instruction, address and dummy read */
sflash_inst_read_f,
sflash_inst_dofr,
sflash_inst_rotp
};
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#define SFLASH_SPI_COMMAND_SKIP (1)
#define SFLASH_SPI_READ_SKIP (2)
#define SFLASH_SPI_COMMAND_SKIP (1)
#define SFLASH_SPI_READ_SKIP (2)
#define SFLASH_INST_CODE_WREN (0x06)
#define SFLASH_INST_CODE_WRDI (0x04)
#define SFLASH_INST_CODE_RDID_L (0x9F)
#define SFLASH_INST_CODE_RDID_S (0x9E)
#define SFLASH_INST_CODE_RDSR (0x05)
#define SFLASH_INST_CODE_WRSR (0x01)
#define SFLASH_INST_CODE_WRLR (0xE5)
#define SFLASH_INST_CODE_RDLR (0xE8)
#define SFLASH_INST_CODE_READ (0x03)
#define SFLASH_INST_CODE_READ_F (0x0B)
#define SFLASH_INST_CODE_DOFR (0x3B)
#define SFLASH_INST_CODE_ROTP (0x4B)
#define SFLASH_INST_CODE_POTP (0x42)
#define SFLASH_INST_CODE_PP (0x02)
#define SFLASH_INST_CODE_DIFP (0xA2)
#define SFLASH_INST_CODE_SSE (0x20)
#define SFLASH_INST_CODE_SE (0xD8)
#define SFLASH_INST_CODE_BE (0xC7)
#define SFLASH_INST_CODE_DP (0xB9)
#define SFLASH_INST_CODE_RDP (0xAB)
#define SFLASH_INST_CODE_WREN (0x06)
#define SFLASH_INST_CODE_WRDI (0x04)
#define SFLASH_INST_CODE_RDID_L (0x9F)
#define SFLASH_INST_CODE_RDID_S (0x9E)
#define SFLASH_INST_CODE_RDSR (0x05)
#define SFLASH_INST_CODE_WRSR (0x01)
#define SFLASH_INST_CODE_WRLR (0xE5)
#define SFLASH_INST_CODE_RDLR (0xE8)
#define SFLASH_INST_CODE_READ (0x03)
#define SFLASH_INST_CODE_READ_F (0x0B)
#define SFLASH_INST_CODE_DOFR (0x3B)
#define SFLASH_INST_CODE_ROTP (0x4B)
#define SFLASH_INST_CODE_POTP (0x42)
#define SFLASH_INST_CODE_PP (0x02)
#define SFLASH_INST_CODE_DIFP (0xA2)
#define SFLASH_INST_CODE_SSE (0x20)
#define SFLASH_INST_CODE_SE (0xD8)
#define SFLASH_INST_CODE_BE (0xC7)
#define SFLASH_INST_CODE_DP (0xB9)
#define SFLASH_INST_CODE_RDP (0xAB)
#define SFLASH_REPLY_LEN_WREN (0)
#define SFLASH_REPLY_LEN_WRDI (0)
#define SFLASH_REPLY_LEN_RDID_L (20)
#define SFLASH_REPLY_LEN_RDID_S (3)
#define SFLASH_REPLY_LEN_RDSR (1)
#define SFLASH_REPLY_LEN_WRSR (1)
#define SFLASH_REPLY_LEN_WRLR (1)
#define SFLASH_REPLY_LEN_RDLR (1)
#define SFLASH_REPLY_LEN_READ (-1)
#define SFLASH_REPLY_LEN_READ_F (-1)
#define SFLASH_REPLY_LEN_DOFR (-1)
#define SFLASH_REPLY_LEN_ROTP (65)
#define SFLASH_REPLY_LEN_POTP (65)
#define SFLASH_REPLY_LEN_PP (256)
#define SFLASH_REPLY_LEN_DIFP (256)
#define SFLASH_REPLY_LEN_SSE (0)
#define SFLASH_REPLY_LEN_SE (0)
#define SFLASH_REPLY_LEN_BE (0)
#define SFLASH_REPLY_LEN_DP (0)
#define SFLASH_REPLY_LEN_RDP (0)
#define SFLASH_REPLY_LEN_WREN (0)
#define SFLASH_REPLY_LEN_WRDI (0)
#define SFLASH_REPLY_LEN_RDID_L (20)
#define SFLASH_REPLY_LEN_RDID_S (3)
#define SFLASH_REPLY_LEN_RDSR (1)
#define SFLASH_REPLY_LEN_WRSR (1)
#define SFLASH_REPLY_LEN_WRLR (1)
#define SFLASH_REPLY_LEN_RDLR (1)
#define SFLASH_REPLY_LEN_READ (-1)
#define SFLASH_REPLY_LEN_READ_F (-1)
#define SFLASH_REPLY_LEN_DOFR (-1)
#define SFLASH_REPLY_LEN_ROTP (65)
#define SFLASH_REPLY_LEN_POTP (65)
#define SFLASH_REPLY_LEN_PP (256)
#define SFLASH_REPLY_LEN_DIFP (256)
#define SFLASH_REPLY_LEN_SSE (0)
#define SFLASH_REPLY_LEN_SE (0)
#define SFLASH_REPLY_LEN_BE (0)
#define SFLASH_REPLY_LEN_DP (0)
#define SFLASH_REPLY_LEN_RDP (0)
/* Exported functions ------------------------------------------------------- */
rt_err_t efm_spiFlash_init(void);
rt_err_t efm_spiFlash_deinit(void);
rt_uint32_t efm_spiFlash_cmd(
enum sflash_inst_type_t command,
rt_uint32_t address,
rt_uint8_t *buffer,
rt_uint32_t size);
enum sflash_inst_type_t command,
rt_uint32_t address,
rt_uint8_t *buffer,
rt_uint32_t size);
#endif /* __DEV_SFLASH_H__ */

432
bsp/efm32/drv_acmp.c
View File

@ -30,18 +30,18 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
#ifdef RT_ACMP_DEBUG
#define acmp_debug(format,args...) rt_kprintf(format, ##args)
#define acmp_debug(format,args...) rt_kprintf(format, ##args)
#else
#define acmp_debug(format,args...)
#endif
/* Private variables ---------------------------------------------------------*/
#ifdef RT_USING_ACMP0
static struct rt_device acmp0_device;
static struct rt_device acmp0_device;
#endif
#ifdef RT_USING_ACMP1
static struct rt_device acmp1_device;
static struct rt_device acmp1_device;
#endif
/* Private function prototypes -----------------------------------------------*/
@ -64,169 +64,169 @@ ACMP_WarmTime_TypeDef efm32_acmp_WarmTimeCalc(rt_uint32_t hfperFreq);
******************************************************************************/
static rt_err_t rt_acmp_init(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(dev != RT_NULL);
struct efm32_acmp_device_t *acmp;
struct efm32_acmp_device_t *acmp;
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
acmp->hook.cbFunc = RT_NULL;
acmp->hook.userPtr = RT_NULL;
acmp->hook.cbFunc = RT_NULL;
acmp->hook.userPtr = RT_NULL;
return RT_EOK;
return RT_EOK;
}
/***************************************************************************//**
* @brief
* Configure ACMP device
* Configure ACMP device
*
* @details
*
* @note
*
* @param[in] dev
* Pointer to device descriptor
* Pointer to device descriptor
*
* @param[in] cmd
* ACMP control command
* ACMP control command
*
* @param[in] args
* Arguments
* Arguments
*
* @return
* Error code
* Error code
******************************************************************************/
static rt_err_t rt_acmp_control(
rt_device_t dev,
rt_uint8_t cmd,
void *args)
rt_device_t dev,
rt_uint8_t cmd,
void *args)
{
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(dev != RT_NULL);
struct efm32_acmp_device_t *acmp;
struct efm32_acmp_device_t *acmp;
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
switch (cmd)
{
case RT_DEVICE_CTRL_SUSPEND:
/* Suspend device */
dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
ACMP_Disable(acmp->acmp_device);
break;
switch (cmd)
{
case RT_DEVICE_CTRL_SUSPEND:
/* Suspend device */
dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
ACMP_Disable(acmp->acmp_device);
break;
case RT_DEVICE_CTRL_RESUME:
/* Resume device */
dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
ACMP_Enable(acmp->acmp_device);
break;
case RT_DEVICE_CTRL_RESUME:
/* Resume device */
dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
ACMP_Enable(acmp->acmp_device);
break;
case RT_DEVICE_CTRL_ACMP_INIT:
{
rt_bool_t int_en = false;
struct efm32_acmp_control_t *control;
case RT_DEVICE_CTRL_ACMP_INIT:
{
rt_bool_t int_en = false;
struct efm32_acmp_control_t *control;
control = (struct efm32_acmp_control_t *)args;
acmp_debug("ACMP: control -> init start\n");
control = (struct efm32_acmp_control_t *)args;
acmp_debug("ACMP: control -> init start\n");
/* Configure ACMPn */
if (control->init == RT_NULL)
{
return -RT_ERROR;
}
ACMP_Init(acmp->acmp_device, control->init);
ACMP_ChannelSet(acmp->acmp_device, control->negInput, control->posInput);
if (control->output != RT_NULL)
{
ACMP_GPIOSetup(
acmp->acmp_device,
control->output->location,
control->output->enable,
control->output->invert);
int_en = true;
}
if (control->hook.cbFunc != RT_NULL)
{
acmp->hook.cbFunc = control->hook.cbFunc;
acmp->hook.userPtr = control->hook.userPtr;
int_en = true;
}
/* Configure ACMPn */
if (control->init == RT_NULL)
{
return -RT_ERROR;
}
ACMP_Init(acmp->acmp_device, control->init);
ACMP_ChannelSet(acmp->acmp_device, control->negInput, control->posInput);
if (control->output != RT_NULL)
{
ACMP_GPIOSetup(
acmp->acmp_device,
control->output->location,
control->output->enable,
control->output->invert);
int_en = true;
}
if (control->hook.cbFunc != RT_NULL)
{
acmp->hook.cbFunc = control->hook.cbFunc;
acmp->hook.userPtr = control->hook.userPtr;
int_en = true;
}
if (int_en)
{
/* Enable edge interrupt */
ACMP_IntEnable(acmp->acmp_device, ACMP_IEN_EDGE);
ACMP_IntClear(acmp->acmp_device, ACMP_IFC_EDGE);
if (int_en)
{
/* Enable edge interrupt */
ACMP_IntEnable(acmp->acmp_device, ACMP_IEN_EDGE);
ACMP_IntClear(acmp->acmp_device, ACMP_IFC_EDGE);
/* Enable ACMP0/1 interrupt vector in NVIC */
NVIC_ClearPendingIRQ(ACMP0_IRQn);
NVIC_SetPriority(ACMP0_IRQn, EFM32_IRQ_PRI_DEFAULT);
NVIC_EnableIRQ(ACMP0_IRQn);
}
}
break;
/* Enable ACMP0/1 interrupt vector in NVIC */
NVIC_ClearPendingIRQ(ACMP0_IRQn);
NVIC_SetPriority(ACMP0_IRQn, EFM32_IRQ_PRI_DEFAULT);
NVIC_EnableIRQ(ACMP0_IRQn);
}
}
break;
case RT_DEVICE_CTRL_ACMP_OUTPUT:
*((rt_bool_t *)args) = \
(acmp->acmp_device->STATUS & ACMP_STATUS_ACMPOUT) ? true : false;
break;
case RT_DEVICE_CTRL_ACMP_OUTPUT:
*((rt_bool_t *)args) = \
(acmp->acmp_device->STATUS & ACMP_STATUS_ACMPOUT) ? true : false;
break;
default:
return -RT_ERROR;
}
default:
return -RT_ERROR;
}
return RT_EOK;
return RT_EOK;
}
/***************************************************************************//**
* @brief
* Register ACMP device
* Register ACMP device
*
* @details
*
* @note
*
* @param[in] device
* Pointer to device descriptor
* Pointer to device descriptor
*
* @param[in] name
* Device name
* Device name
*
* @param[in] flag
* Configuration flags
* Configuration flags
*
* @param[in] acmp
* Pointer to ACMP device descriptor
* Pointer to ACMP device descriptor
*
* @return
* Error code
* Error code
******************************************************************************/
rt_err_t rt_hw_acmp_register(
rt_device_t device,
const char *name,
rt_uint32_t flag,
struct efm32_acmp_device_t *acmp)
rt_device_t device,
const char *name,
rt_uint32_t flag,
struct efm32_acmp_device_t *acmp)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device != RT_NULL);
device->type = RT_Device_Class_Char; /* fixme: should be acmp type */
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = rt_acmp_init;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = rt_acmp_control;
device->user_data = acmp;
device->type = RT_Device_Class_Char; /* fixme: should be acmp type */
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = rt_acmp_init;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = rt_acmp_control;
device->user_data = acmp;
/* register a character device */
return rt_device_register(device, name, flag);
/* register a character device */
return rt_device_register(device, name, flag);
}
/***************************************************************************//**
* @brief
* ACMP edge trigger interrupt handler
* ACMP edge trigger interrupt handler
*
* @details
*
@ -234,96 +234,96 @@ rt_err_t rt_hw_acmp_register(
******************************************************************************/
void rt_hw_acmp_isr(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
RT_ASSERT(dev != RT_NULL);
struct efm32_acmp_device_t *acmp;
struct efm32_acmp_device_t *acmp;
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
acmp = (struct efm32_acmp_device_t *)(dev->user_data);
if (acmp->hook.cbFunc != RT_NULL)
{
(acmp->hook.cbFunc)(acmp->hook.userPtr);
}
if (acmp->hook.cbFunc != RT_NULL)
{
(acmp->hook.cbFunc)(acmp->hook.userPtr);
}
}
/***************************************************************************//**
* @brief
* Initialize the specified ACMP unit
* Initialize the specified ACMP unit
*
* @details
*
* @note
*
* @param[in] device
* Pointer to device descriptor
* Pointer to device descriptor
*
* @param[in] unitNumber
* Unit number
* Unit number
*
* @return
* Pointer to ACMP device
* Pointer to ACMP device
******************************************************************************/
static struct efm32_acmp_device_t *rt_hw_acmp_unit_init(
rt_device_t device,
rt_uint8_t unitNumber)
rt_device_t device,
rt_uint8_t unitNumber)
{
struct efm32_acmp_device_t *acmp;
efm32_irq_hook_init_t hook;
CMU_Clock_TypeDef acmpClock;
struct efm32_acmp_device_t *acmp;
efm32_irq_hook_init_t hook;
CMU_Clock_TypeDef acmpClock;
do
{
/* Allocate device */
acmp = rt_malloc(sizeof(struct efm32_acmp_device_t));
if (acmp == RT_NULL)
{
acmp_debug("ACMP err: no mem for ACMP%d\n", unitNumber);
break;
}
do
{
/* Allocate device */
acmp = rt_malloc(sizeof(struct efm32_acmp_device_t));
if (acmp == RT_NULL)
{
acmp_debug("ACMP err: no mem for ACMP%d\n", unitNumber);
break;
}
/* Initialization */
if (unitNumber >= ACMP_COUNT)
{
break;
}
switch (unitNumber)
{
case 0:
acmp->acmp_device = ACMP0;
acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP0;
break;
/* Initialization */
if (unitNumber >= ACMP_COUNT)
{
break;
}
switch (unitNumber)
{
case 0:
acmp->acmp_device = ACMP0;
acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP0;
break;
case 1:
acmp->acmp_device = ACMP1;
acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP1;
break;
case 1:
acmp->acmp_device = ACMP1;
acmpClock = (CMU_Clock_TypeDef)cmuClock_ACMP1;
break;
default:
break;
}
default:
break;
}
/* Enable ACMP clock */
CMU_ClockEnable(acmpClock, true);
/* Enable ACMP clock */
CMU_ClockEnable(acmpClock, true);
/* Reset */
ACMP_Reset(acmp->acmp_device);
/* Reset */
ACMP_Reset(acmp->acmp_device);
/* Config interrupt and NVIC */
hook.type = efm32_irq_type_acmp;
hook.unit = unitNumber;
hook.cbFunc = rt_hw_acmp_isr;
hook.userPtr = device;
efm32_irq_hook_register(&hook);
/* Config interrupt and NVIC */
hook.type = efm32_irq_type_acmp;
hook.unit = unitNumber;
hook.cbFunc = rt_hw_acmp_isr;
hook.userPtr = device;
efm32_irq_hook_register(&hook);
return acmp;
} while(0);
return acmp;
} while(0);
if (acmp)
{
rt_free(acmp);
}
rt_kprintf("ACMP: Init failed!\n");
return RT_NULL;
if (acmp)
{
rt_free(acmp);
}
rt_kprintf("ACMP: Init failed!\n");
return RT_NULL;
}
/***************************************************************************//**
@ -338,20 +338,20 @@ static struct efm32_acmp_device_t *rt_hw_acmp_unit_init(
******************************************************************************/
void rt_hw_acmp_init(void)
{
struct efm32_acmp_device_t *acmp;
struct efm32_acmp_device_t *acmp;
#ifdef RT_USING_ACMP0
if ((acmp = rt_hw_acmp_unit_init(&acmp0_device, 0)) != RT_NULL)
{
rt_hw_acmp_register(&acmp0_device, RT_ACMP0_NAME, EFM32_NO_DATA, acmp);
}
if ((acmp = rt_hw_acmp_unit_init(&acmp0_device, 0)) != RT_NULL)
{
rt_hw_acmp_register(&acmp0_device, RT_ACMP0_NAME, EFM32_NO_DATA, acmp);
}
#endif
#ifdef RT_USING_ACMP1
if ((acmp = rt_hw_acmp_unit_init(&acmp1_device, 1)) != RT_NULL)
{
rt_hw_acmp_register(&acmp1_device, RT_ACMP1_NAME, EFM32_NO_DATA, acmp);
}
if ((acmp = rt_hw_acmp_unit_init(&acmp1_device, 1)) != RT_NULL)
{
rt_hw_acmp_register(&acmp1_device, RT_ACMP1_NAME, EFM32_NO_DATA, acmp);
}
#endif
}
@ -369,50 +369,50 @@ void rt_hw_acmp_init(void)
******************************************************************************/
ACMP_WarmTime_TypeDef efm32_acmp_WarmTimeCalc(rt_uint32_t hfperFreq)
{
if (!hfperFreq)
{
hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
if (!hfperFreq)
{
hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
/* Just in case, make sure we get non-zero freq for below calculation */
if (!hfperFreq)
{
hfperFreq = 1;
}
}
/* Just in case, make sure we get non-zero freq for below calculation */
if (!hfperFreq)
{
hfperFreq = 1;
}
}
/* Determine number of HFPERCLK cycle >= 10us */
if (4 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime4;
}
else if (8 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime8;
}
else if (16 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime16;
}
else if (32 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime32;
}
else if (64 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime64;
}
else if (128 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime128;
}
else if (256 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime256;
}
else if (512 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime512;
}
/* Determine number of HFPERCLK cycle >= 10us */
if (4 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime4;
}
else if (8 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime8;
}
else if (16 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime16;
}
else if (32 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime32;
}
else if (64 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime64;
}
else if (128 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime128;
}
else if (256 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime256;
}
else if (512 * 1000000 / hfperFreq > 10)
{
return acmpWarmTime512;
}
}
#endif

20
bsp/efm32/drv_acmp.h
View File

@ -23,24 +23,24 @@
/* Exported types ------------------------------------------------------------*/
struct efm32_acmp_device_t
{
ACMP_TypeDef *acmp_device;
efm32_irq_hook_t hook;
ACMP_TypeDef *acmp_device;
efm32_irq_hook_t hook;
};
struct efm32_acmp_output_t
{
rt_uint32_t location;
rt_bool_t enable;
rt_bool_t invert;
rt_uint32_t location;
rt_bool_t enable;
rt_bool_t invert;
};
struct efm32_acmp_control_t
{
ACMP_Init_TypeDef *init;
ACMP_Channel_TypeDef posInput;
ACMP_Channel_TypeDef negInput;
struct efm32_acmp_output_t *output;
efm32_irq_hook_t hook;
ACMP_Init_TypeDef *init;
ACMP_Channel_TypeDef posInput;
ACMP_Channel_TypeDef negInput;
struct efm32_acmp_output_t *output;
efm32_irq_hook_t hook;
};
/* Exported constants --------------------------------------------------------*/

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