libs/rt-thread
libs/rt-thread
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

[bsp][stm32]upgrade menuconfig about crypto

Browse Source
This commit is contained in:
Ernest 2019-07-10 18:40:01 +08:00
parent 2aaa7d066d
commit 1f114ec22f
9 changed files with 103 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
bsp/stm32/libraries/HAL_Drivers/Kconfig.crypto Normal file
View File

@ -0,0 +1,20 @@
config BSP_USING_CRC
bool "Enable CRC (CRC-32 0x04C11DB7 polynomial)"
select RT_USING_HWCRYPTO
select RT_HWCRYPTO_USING_CRC
default n
config BSP_USING_RNG
bool "Enable RNG"
select RT_USING_HWCRYPTO
select RT_HWCRYPTO_USING_RNG
depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \
SOC_SERIES_STM32H7)
default n
config BSP_USING_UDID
bool "Enable unique device identifier"
select RT_USING_HWCRYPTO
default n

115
bsp/stm32/libraries/HAL_Drivers/drv_crypto.c
View File

@ -15,43 +15,22 @@
#include "drv_crypto.h" #include "drv_crypto.h"
#include "board.h" #include "board.h"
#if !defined(SOC_SERIES_STM32F0)&& !defined(SOC_SERIES_STM32F1) && !defined(SOC_SERIES_STM32F4) \
&& !defined(SOC_SERIES_STM32F7)&& !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32H7)
#error "Please define at least one SOC_SERIES"
#endif
#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
static struct hwcrypto_crc_cfg crc_backup_cfg;
#endif
struct stm32_hwcrypto_device struct stm32_hwcrypto_device
{ {
struct rt_hwcrypto_device dev; struct rt_hwcrypto_device dev;
struct rt_mutex mutex; struct rt_mutex mutex;
}; };
#if defined(BSP_USING_CRC)
struct hash_ctx_des struct hash_ctx_des
{ {
CRC_HandleTypeDef contex; CRC_HandleTypeDef contex;
}; };
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) #if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
static rt_uint32_t _rng_rand(struct hwcrypto_rng *ctx) static struct hwcrypto_crc_cfg crc_backup_cfg;
{
rt_uint32_t gen_random = 0;
RNG_HandleTypeDef *HW_TypeDef = (RNG_HandleTypeDef *)(ctx->parent.contex);
if (HAL_OK == HAL_RNG_GenerateRandomNumber(HW_TypeDef, &gen_random))
{
return gen_random ;
}
return 0;
}
#endif
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
static int reverse_bit(rt_uint32_t n) static int reverse_bit(rt_uint32_t n)
{ {
n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xaaaaaaaa); n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xaaaaaaaa);
@ -68,12 +47,13 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
{ {
rt_uint32_t result = 0; rt_uint32_t result = 0;
struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data; struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data;
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
CRC_HandleTypeDef *HW_TypeDef = (CRC_HandleTypeDef *)(ctx->parent.contex); CRC_HandleTypeDef *HW_TypeDef = (CRC_HandleTypeDef *)(ctx->parent.contex);
#endif #endif
rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER); rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER);
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) #if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
if (0 != memcmp(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg))) if (0 != memcmp(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)))
{ {
if (HW_TypeDef->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_DISABLE) if (HW_TypeDef->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_DISABLE)
@ -122,8 +102,9 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
{ {
goto _exit; goto _exit;
} }
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F1) #else
if (length % 4 != 0) if (ctx->crc_cfg.flags == 0 && ctx->crc_cfg.last_val == 0xFFFFFFFF && \
ctx->crc_cfg.xorout == 0 && length % 4 != 0)
{ {
goto _exit; goto _exit;
} }
@ -132,7 +113,7 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
result = HAL_CRC_Accumulate(ctx->parent.contex, (rt_uint32_t *)in, length); result = HAL_CRC_Accumulate(ctx->parent.contex, (rt_uint32_t *)in, length);
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) #if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
if (HW_TypeDef->Init.OutputDataInversionMode) if (HW_TypeDef->Init.OutputDataInversionMode)
{ {
ctx ->crc_cfg.last_val = reverse_bit(result); ctx ->crc_cfg.last_val = reverse_bit(result);
@ -143,32 +124,48 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
} }
crc_backup_cfg.last_val = ctx ->crc_cfg.last_val; crc_backup_cfg.last_val = ctx ->crc_cfg.last_val;
result = (result ? result ^ (ctx ->crc_cfg.xorout) : result); result = (result ? result ^ (ctx ->crc_cfg.xorout) : result);
#endif #endif
_exit: _exit:
rt_mutex_release(&stm32_hw_dev->mutex); rt_mutex_release(&stm32_hw_dev->mutex);
return result; return result;
} }
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
static const struct hwcrypto_rng_ops rng_ops =
{
.update = _rng_rand,
};
#endif
static const struct hwcrypto_crc_ops crc_ops = static const struct hwcrypto_crc_ops crc_ops =
{ {
.update = _crc_update, .update = _crc_update,
}; };
#endif /* BSP_USING_CRC */
#if defined(BSP_USING_RNG)
static rt_uint32_t _rng_rand(struct hwcrypto_rng *ctx)
{
rt_uint32_t gen_random = 0;
RNG_HandleTypeDef *HW_TypeDef = (RNG_HandleTypeDef *)(ctx->parent.contex);
if (HAL_OK == HAL_RNG_GenerateRandomNumber(HW_TypeDef, &gen_random))
{
return gen_random ;
}
return 0;
}
static const struct hwcrypto_rng_ops rng_ops =
{
.update = _rng_rand,
};
#endif /* BSP_USING_RNG */
static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
{ {
rt_err_t res = RT_EOK; rt_err_t res = RT_EOK;
switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
{ {
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) #if defined(BSP_USING_RNG)
case HWCRYPTO_TYPE_RNG: case HWCRYPTO_TYPE_RNG:
{ {
RNG_HandleTypeDef *hrng = rt_calloc(1, sizeof(RNG_HandleTypeDef)); RNG_HandleTypeDef *hrng = rt_calloc(1, sizeof(RNG_HandleTypeDef));
@ -180,7 +177,9 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
break; break;
} }
#endif #endif /* BSP_USING_RNG */
#if defined(BSP_USING_CRC)
case HWCRYPTO_TYPE_CRC: case HWCRYPTO_TYPE_CRC:
{ {
CRC_HandleTypeDef *hcrc = rt_calloc(1, sizeof(CRC_HandleTypeDef)); CRC_HandleTypeDef *hcrc = rt_calloc(1, sizeof(CRC_HandleTypeDef));
@ -191,13 +190,13 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
} }
hcrc->Instance = CRC; hcrc->Instance = CRC;
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) #if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
hcrc->Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE; hcrc->Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE;
hcrc->Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_DISABLE; hcrc->Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_DISABLE;
hcrc->Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_BYTE; hcrc->Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_BYTE;
hcrc->Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_ENABLE; hcrc->Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_ENABLE;
hcrc->InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; hcrc->InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES;
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F1) #else
if (HAL_CRC_Init(hcrc) != HAL_OK) if (HAL_CRC_Init(hcrc) != HAL_OK)
{ {
res = -RT_ERROR; res = -RT_ERROR;
@ -207,11 +206,11 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
((struct hwcrypto_crc *)ctx)->ops = &crc_ops; ((struct hwcrypto_crc *)ctx)->ops = &crc_ops;
break; break;
} }
#endif /* BSP_USING_CRC */
default: default:
res = -RT_ERROR; res = -RT_ERROR;
break; break;
} }
return res; return res;
} }
@ -219,11 +218,16 @@ static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx)
{ {
switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
{ {
#if defined(BSP_USING_RNG)
case HWCRYPTO_TYPE_RNG: case HWCRYPTO_TYPE_RNG:
break; break;
#endif /* BSP_USING_RNG */
#if defined(BSP_USING_CRC)
case HWCRYPTO_TYPE_CRC: case HWCRYPTO_TYPE_CRC:
HAL_CRC_DeInit((CRC_HandleTypeDef *)(ctx->contex)); HAL_CRC_DeInit((CRC_HandleTypeDef *)(ctx->contex));
break; break;
#endif /* BSP_USING_CRC */
default: default:
break; break;
} }
@ -237,14 +241,23 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
switch (src->type & HWCRYPTO_MAIN_TYPE_MASK) switch (src->type & HWCRYPTO_MAIN_TYPE_MASK)
{ {
#if defined(BSP_USING_RNG)
case HWCRYPTO_TYPE_RNG: case HWCRYPTO_TYPE_RNG:
if (des->contex && src->contex)
{
rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des));
}
break; break;
#endif /* BSP_USING_RNG */
#if defined(BSP_USING_CRC)
case HWCRYPTO_TYPE_CRC: case HWCRYPTO_TYPE_CRC:
if (des->contex && src->contex) if (des->contex && src->contex)
{ {
rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des)); rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des));
} }
break; break;
#endif /* BSP_USING_CRC */
default: default:
res = -RT_ERROR; res = -RT_ERROR;
break; break;
@ -256,11 +269,16 @@ static void _crypto_reset(struct rt_hwcrypto_ctx *ctx)
{ {
switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
{ {
#if defined(BSP_USING_RNG)
case HWCRYPTO_TYPE_RNG: case HWCRYPTO_TYPE_RNG:
break; break;
#endif /* BSP_USING_RNG */
#if defined(BSP_USING_CRC)
case HWCRYPTO_TYPE_CRC: case HWCRYPTO_TYPE_CRC:
__HAL_CRC_DR_RESET((CRC_HandleTypeDef *)ctx-> contex); __HAL_CRC_DR_RESET((CRC_HandleTypeDef *)ctx-> contex);
break; break;
#endif /* BSP_USING_CRC */
default: default:
break; break;
} }
@ -277,9 +295,11 @@ static const struct rt_hwcrypto_ops _ops =
int stm32_hw_crypto_device_init(void) int stm32_hw_crypto_device_init(void)
{ {
static struct stm32_hwcrypto_device _crypto_dev; static struct stm32_hwcrypto_device _crypto_dev;
rt_uint32_t cpuid[3] = {0}; rt_uint32_t cpuid[3] = {0};
_crypto_dev.dev.ops = &_ops;
#if defined(BSP_USING_UDID)
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F7) #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F7)
cpuid[0] = HAL_GetUIDw0(); cpuid[0] = HAL_GetUIDw0();
cpuid[1] = HAL_GetUIDw1(); cpuid[1] = HAL_GetUIDw1();
@ -289,14 +309,15 @@ int stm32_hw_crypto_device_init(void)
cpuid[0] = HAL_GetREVID(); cpuid[0] = HAL_GetREVID();
cpuid[1] = HAL_GetDEVID(); cpuid[1] = HAL_GetDEVID();
#endif #endif
_crypto_dev.dev.ops = &_ops;
#endif /* BSP_USING_UDID */
_crypto_dev.dev.id = 0; _crypto_dev.dev.id = 0;
rt_memcpy(&_crypto_dev.dev.id, cpuid, 8); rt_memcpy(&_crypto_dev.dev.id, cpuid, 8);
_crypto_dev.dev.user_data = &_crypto_dev; _crypto_dev.dev.user_data = &_crypto_dev;
if (rt_hwcrypto_register(&_crypto_dev.dev, if (rt_hwcrypto_register(&_crypto_dev.dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK)
RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK)
{ {
return -1; return -1;
} }

1
bsp/stm32/stm32f091-st-nucleo/board/Kconfig
View File

@ -156,6 +156,7 @@ menu "On-chip Peripheral Drivers"
select RT_USING_WDT select RT_USING_WDT
default n default n
source "../libraries/HAL_Drivers/Kconfig.crypto"
endmenu endmenu
menu "Board extended module Drivers" menu "Board extended module Drivers"

1
bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig
View File

@ -201,6 +201,7 @@ menu "On-chip Peripheral Drivers"
select RT_USING_WDT select RT_USING_WDT
default n default n
source "../libraries/HAL_Drivers/Kconfig.crypto"
endmenu endmenu
menu "Board extended module Drivers" menu "Board extended module Drivers"

2
bsp/stm32/stm32f407-atk-explorer/board/Kconfig
View File

@ -294,6 +294,8 @@ menu "On-chip Peripheral Drivers"
select RT_USING_DFS select RT_USING_DFS
default n default n
source "../libraries/HAL_Drivers/Kconfig.crypto"
endmenu endmenu
menu "Board extended module Drivers" menu "Board extended module Drivers"

2
bsp/stm32/stm32f767-atk-apollo/board/Kconfig
View File

@ -245,6 +245,8 @@ menu "On-chip Peripheral Drivers"
select RT_USING_DFS select RT_USING_DFS
default n default n
source "../libraries/HAL_Drivers/Kconfig.crypto"
endmenu endmenu
menu "Board extended module Drivers" menu "Board extended module Drivers"

3
bsp/stm32/stm32h743-atk-apollo/board/Kconfig
View File

@ -68,6 +68,9 @@ menu "On-chip Peripheral Drivers"
select RT_USING_WDT select RT_USING_WDT
default n default n
source "../libraries/HAL_Drivers/Kconfig.crypto"
endmenu endmenu
menu "Board extended module Drivers" menu "Board extended module Drivers"

2
bsp/stm32/stm32l475-atk-pandora/board/Kconfig
View File

@ -251,6 +251,8 @@ menu "On-chip Peripheral Drivers"
select RT_USING_USB_DEVICE select RT_USING_USB_DEVICE
default n default n
source "../libraries/HAL_Drivers/Kconfig.crypto"
endmenu endmenu
menu "Board extended module Drivers" menu "Board extended module Drivers"

2
bsp/stm32/stm32l496-ali-developer/board/Kconfig
View File

@ -219,6 +219,8 @@ menu "On-chip Peripheral Drivers"
select RT_USING_WDT select RT_USING_WDT
default n default n
source "../libraries/HAL_Drivers/Kconfig.crypto"
endmenu endmenu
menu "Board extended module Drivers" menu "Board extended module Drivers"