parent
666d12988a
commit
1e396417d8
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@ -93,7 +93,7 @@
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#define DFS_FD_MAX 4
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#define DFS_FD_MAX 4
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/* SECTION: lwip, a lighwight TCP/IP protocol stack */
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/* SECTION: lwip, a lighwight TCP/IP protocol stack */
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#define RT_USING_LWIP
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/* #define RT_USING_LWIP */
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/* LwIP uses RT-Thread Memory Management */
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/* LwIP uses RT-Thread Memory Management */
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#define RT_LWIP_USING_RT_MEM
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#define RT_LWIP_USING_RT_MEM
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/* Enable ICMP protocol*/
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/* Enable ICMP protocol*/
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@ -16,9 +16,6 @@
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#include <board.h>
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#include <board.h>
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#include <components.h>
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#include <components.h>
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#ifdef RT_USING_LWIP
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#include "drv_eth.h"
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#endif
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/* thread phase init */
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/* thread phase init */
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void rt_init_thread_entry(void *parameter)
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void rt_init_thread_entry(void *parameter)
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{
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{
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@ -27,9 +24,6 @@ void rt_init_thread_entry(void *parameter)
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#ifdef RT_USING_FINSH
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#ifdef RT_USING_FINSH
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finsh_set_device(RT_CONSOLE_DEVICE_NAME);
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finsh_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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#endif
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#ifdef RT_USING_LWIP
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rt_hw_tiva_eth_init();
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#endif
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}
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}
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int rt_application_init(void)
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int rt_application_init(void)
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@ -92,7 +92,7 @@ void rt_hw_board_init()
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/*init uart device*/
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/*init uart device*/
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rt_hw_uart_init();
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rt_hw_uart_init();
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//redirect RTT stdio to CONSOLE device
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//redirect RTT stdio to CONSOLE device
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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//
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//
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// Enable interrupts to the processor.
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// Enable interrupts to the processor.
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File diff suppressed because it is too large
Load Diff
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@ -1,20 +0,0 @@
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/*
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* File : drv_eth.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2014-07-25 ArdaFu Port to TM4C129X
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*/
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#ifndef __TIVA_ETH_H__
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#define __TIVA_ETH_H__
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rt_err_t rt_hw_tiva_eth_init(void);
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#endif
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@ -2917,7 +2917,6 @@ EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr)
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//
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//
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HWREG(ui32Base + EMAC_O_MIIADDR) =
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HWREG(ui32Base + EMAC_O_MIIADDR) =
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((HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_CR_M) |
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((HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_CR_M) |
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EMAC_MIIADDR_CR_100_150 |
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(ui8RegAddr << EMAC_MIIADDR_MII_S) |
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(ui8RegAddr << EMAC_MIIADDR_MII_S) |
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(ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIB);
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(ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIB);
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