From 1d6347796d82f58ef9c5f23b4913aa92c053a7b7 Mon Sep 17 00:00:00 2001 From: levizhxl <31306568+levizh@users.noreply.github.com> Date: Tue, 31 May 2022 11:53:56 +0800 Subject: [PATCH] Hc32 pr (#6003) * HC32F460 supported Co-authored-by: JamieTx Co-authored-by: Jamie <48308473+JamieTx@users.noreply.github.com> --- bsp/hc32/README.md | 1 + bsp/hc32/ev_hc32f460_lqfp100_v2/.config | 688 + bsp/hc32/ev_hc32f460_lqfp100_v2/.gitignore | 42 + bsp/hc32/ev_hc32f460_lqfp100_v2/Kconfig | 21 + bsp/hc32/ev_hc32f460_lqfp100_v2/README.md | 107 + bsp/hc32/ev_hc32f460_lqfp100_v2/SConscript | 15 + bsp/hc32/ev_hc32f460_lqfp100_v2/SConstruct | 60 + .../applications/SConscript | 11 + .../applications/main.c | 34 + bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig | 88 + .../ev_hc32f460_lqfp100_v2/board/SConscript | 31 + bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c | 177 + bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.h | 43 + .../board/board_config.c | 41 + .../board/board_config.h | 54 + .../board/config/dma_config.h | 195 + .../board/config/gpio_config.h | 176 + .../board/config/irq_config.h | 162 + .../board/config/uart_config.h | 407 + .../ev_hc32f460_lqfp100_v2/board/drv_config.h | 30 + .../board/hc32f4xx_conf.h | 167 + .../board/linker_scripts/link.icf | 51 + .../board/linker_scripts/link.ld | 267 + .../board/linker_scripts/link.sct | 15 + .../ev_hc32f460_lqfp100_v2/figures/board.jpg | Bin 0 -> 980523 bytes bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewd | 2966 + bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewp | 2209 + bsp/hc32/ev_hc32f460_lqfp100_v2/project.eww | 10 + .../ev_hc32f460_lqfp100_v2/project.uvoptx | 189 + .../ev_hc32f460_lqfp100_v2/project.uvprojx | 845 + bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h | 202 + bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.py | 150 + bsp/hc32/ev_hc32f460_lqfp100_v2/template.ewp | 1925 + bsp/hc32/ev_hc32f460_lqfp100_v2/template.eww | 10 + .../ev_hc32f460_lqfp100_v2/template.uvoptx | 189 + .../ev_hc32f460_lqfp100_v2/template.uvprojx | 390 + bsp/hc32/ev_hc32f4a0_lqfp176/.config | 15 +- bsp/hc32/ev_hc32f4a0_lqfp176/README.md | 12 +- .../ev_hc32f4a0_lqfp176/applications/main.c | 3 +- bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig | 116 - bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript | 3 - bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c | 5 +- bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h | 3 +- .../ev_hc32f4a0_lqfp176/board/board_config.c | 51 +- .../ev_hc32f4a0_lqfp176/board/board_config.h | 31 +- .../board/config/adc_config.h | 3 +- .../board/config/can_config.h | 3 +- .../board/config/dma_config.h | 3 +- .../board/config/eth_config.h | 3 +- .../board/config/gpio_config.h | 3 +- .../board/config/irq_config.h | 3 +- .../board/config/spi_config.h | 3 +- .../board/config/tim_config.h | 81 - .../board/config/uart_config.h | 3 +- .../ev_hc32f4a0_lqfp176/board/drv_config.h | 4 +- .../ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h | 2 +- .../board/linker_scripts/link.ld | 2 +- .../board/ports/spi_flash.c | 46 - .../ev_hc32f4a0_lqfp176/board/ports/tca9539.c | 3 +- .../ev_hc32f4a0_lqfp176/board/ports/tca9539.h | 3 +- bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp | 78 +- bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx | 182 +- bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h | 3 +- bsp/hc32/libraries/.ignore_format.yml | 1 + bsp/hc32/libraries/hc32_drivers/SConscript | 36 - bsp/hc32/libraries/hc32_drivers/drv_adc.c | 3 +- bsp/hc32/libraries/hc32_drivers/drv_adc.h | 3 +- bsp/hc32/libraries/hc32_drivers/drv_can.c | 3 +- bsp/hc32/libraries/hc32_drivers/drv_can.h | 3 +- bsp/hc32/libraries/hc32_drivers/drv_dma.h | 3 +- bsp/hc32/libraries/hc32_drivers/drv_eth.c | 3 +- bsp/hc32/libraries/hc32_drivers/drv_eth.h | 3 +- bsp/hc32/libraries/hc32_drivers/drv_gpio.c | 5 +- bsp/hc32/libraries/hc32_drivers/drv_gpio.h | 3 +- bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c | 551 - bsp/hc32/libraries/hc32_drivers/drv_hwtimer.h | 145 - bsp/hc32/libraries/hc32_drivers/drv_irq.c | 3 +- bsp/hc32/libraries/hc32_drivers/drv_irq.h | 3 +- bsp/hc32/libraries/hc32_drivers/drv_log.h | 3 +- .../hc32_drivers/drv_pulse_encoder.c | 472 - .../hc32_drivers/drv_pulse_encoder.h | 241 - bsp/hc32/libraries/hc32_drivers/drv_pwm.c | 525 - bsp/hc32/libraries/hc32_drivers/drv_rtc.c | 195 - .../libraries/hc32_drivers/drv_soft_i2c.c | 3 +- .../libraries/hc32_drivers/drv_soft_i2c.h | 3 +- bsp/hc32/libraries/hc32_drivers/drv_spi.c | 3 +- bsp/hc32/libraries/hc32_drivers/drv_spi.h | 3 +- bsp/hc32/libraries/hc32_drivers/drv_usart.c | 168 +- bsp/hc32/libraries/hc32_drivers/drv_usart.h | 3 +- bsp/hc32/libraries/hc32f460_ddl/LICENSE | 29 + bsp/hc32/libraries/hc32f460_ddl/README.txt | 4 + bsp/hc32/libraries/hc32f460_ddl/SConscript | 74 + .../config/flashloader/FlashHC32F460.mac | 16 + .../config/flashloader/FlashHC32F460.out | Bin 0 -> 26660 bytes .../flashloader/FlashHC32F460_otp.flash | 10 + .../config/flashloader/FlashHC32F460_otp.mac | 16 + .../config/flashloader/FlashHC32F460_otp.out | Bin 0 -> 23452 bytes .../config/flashloader/FlashHC32F460xC.flash | 10 + .../config/flashloader/FlashHC32F460xE.flash | 10 + .../config/flashloader/HC32F460xC.board | 12 + .../config/flashloader/HC32F460xE.board | 12 + .../config/linker/HC32F460_ram.icf | 58 + .../hc32f460_ddl/config/linker/HC32F460xC.icf | 50 + .../hc32f460_ddl/config/linker/HC32F460xE.icf | 50 + .../drivers/bsp/components/24cxx/24cxx.c | 255 + .../drivers/bsp/components/24cxx/24cxx.h | 112 + .../drivers/bsp/components/w25qxx/w25qxx.c | 567 + .../drivers/bsp/components/w25qxx/w25qxx.h | 190 + .../drivers/bsp/components/wm8731/wm8731.c | 375 + .../drivers/bsp/components/wm8731/wm8731.h | 218 + .../ev_hc32f460_lqfp100_v2.c | 686 + .../ev_hc32f460_lqfp100_v2.h | 287 + .../ev_hc32f460_lqfp100_v2_24cxx.c | 268 + .../ev_hc32f460_lqfp100_v2_24cxx.h | 126 + .../ev_hc32f460_lqfp100_v2_bsp.h | 80 + .../ev_hc32f460_lqfp100_v2_w25qxx.c | 323 + .../ev_hc32f460_lqfp100_v2_w25qxx.h | 161 + .../ev_hc32f460_lqfp100_v2_wm8731.c | 383 + .../ev_hc32f460_lqfp100_v2_wm8731.h | 203 + .../Device/HDSC/hc32f4xx/Include/hc32f460.h | 16303 +++++ .../Device/HDSC/hc32f4xx/Include/hc32f4xx.h | 66 + .../HDSC/hc32f4xx/Include/system_hc32f460.h | 138 + .../Source/ARM/flashloader/HC32F460_256K.FLM | Bin 0 -> 26128 bytes .../Source/ARM/flashloader/HC32F460_512K.FLM | Bin 0 -> 25436 bytes .../Source/ARM/flashloader/HC32F460_RAM.FLM | Bin 0 -> 13664 bytes .../Source/ARM/flashloader/HC32F460_otp.FLM | Bin 0 -> 24304 bytes .../hc32f4xx/Source/ARM/flashloader/ram.ini | 16 + .../hc32f4xx/Source/ARM/sfr/HDSC_HC32F460.SFR | Bin 0 -> 1625032 bytes .../hc32f4xx/Source/ARM/startup_hc32f460.s | 614 + .../hc32f4xx/Source/GCC/linker/HC32F460xC.ld | 208 + .../hc32f4xx/Source/GCC/linker/HC32F460xE.ld | 208 + .../hc32f4xx/Source/GCC/startup_hc32f460.S | 534 + .../hc32f4xx/Source/GCC/svd/HDSC_HC32F460.svd | 53428 ++++++++++++++++ .../Source/IAR/flashloader/FlashHC32F460.mac | 16 + .../Source/IAR/flashloader/FlashHC32F460.out | Bin 0 -> 26660 bytes .../IAR/flashloader/FlashHC32F460_otp.mac | 16 + .../IAR/flashloader/FlashHC32F460_otp.out | Bin 0 -> 23452 bytes .../Source/IAR/linker/HC32F460_RAM.icf | 56 + .../hc32f4xx/Source/IAR/linker/HC32F460xC.icf | 50 + .../hc32f4xx/Source/IAR/linker/HC32F460xE.icf | 50 + .../hc32f4xx/Source/IAR/startup_hc32f460.s | 991 + .../hc32f4xx/Source/IAR/svd/HDSC_HC32F460.svd | 53428 ++++++++++++++++ .../HDSC/hc32f4xx/Source/system_hc32f460.c | 241 + .../drivers/cmsis/Include/arm_common_tables.h | 517 + .../drivers/cmsis/Include/arm_const_structs.h | 76 + .../drivers/cmsis/Include/arm_helium_utils.h | 348 + .../drivers/cmsis/Include/arm_math.h | 8970 +++ .../drivers/cmsis/Include/arm_mve_tables.h | 235 + .../drivers/cmsis/Include/arm_vec_math.h | 372 + .../drivers/cmsis/Include/cachel1_armv7.h | 411 + .../drivers/cmsis/Include/cmsis_armcc.h | 885 + .../drivers/cmsis/Include/cmsis_armclang.h | 1467 + .../cmsis/Include/cmsis_armclang_ltm.h | 1893 + .../drivers/cmsis/Include/cmsis_compiler.h | 283 + .../drivers/cmsis/Include/cmsis_gcc.h | 2177 + .../drivers/cmsis/Include/cmsis_iccarm.h | 968 + .../drivers/cmsis/Include/cmsis_version.h | 39 + .../drivers/cmsis/Include/core_armv81mml.h | 4191 ++ .../drivers/cmsis/Include/core_armv8mbl.h | 2222 + .../drivers/cmsis/Include/core_armv8mml.h | 3196 + .../drivers/cmsis/Include/core_cm0.h | 952 + .../drivers/cmsis/Include/core_cm0plus.h | 1087 + .../drivers/cmsis/Include/core_cm1.h | 979 + .../drivers/cmsis/Include/core_cm23.h | 2297 + .../drivers/cmsis/Include/core_cm3.h | 1943 + .../drivers/cmsis/Include/core_cm33.h | 3264 + .../drivers/cmsis/Include/core_cm35p.h | 3264 + .../drivers/cmsis/Include/core_cm4.h | 2129 + .../drivers/cmsis/Include/core_cm55.h | 4215 ++ .../drivers/cmsis/Include/core_cm7.h | 2362 + .../drivers/cmsis/Include/core_sc000.h | 1030 + .../drivers/cmsis/Include/core_sc300.h | 1917 + .../drivers/cmsis/Include/mpu_armv7.h | 275 + .../drivers/cmsis/Include/mpu_armv8.h | 352 + .../drivers/cmsis/Include/pmu_armv8.h | 337 + .../drivers/cmsis/Include/tz_context.h | 70 + .../drivers/hc32_ll_driver/inc/hc32_ll.h | 325 + .../drivers/hc32_ll_driver/inc/hc32_ll_adc.h | 508 + .../drivers/hc32_ll_driver/inc/hc32_ll_aes.h | 113 + .../drivers/hc32_ll_driver/inc/hc32_ll_aos.h | 170 + .../drivers/hc32_ll_driver/inc/hc32_ll_can.h | 664 + .../drivers/hc32_ll_driver/inc/hc32_ll_clk.h | 748 + .../drivers/hc32_ll_driver/inc/hc32_ll_cmp.h | 280 + .../drivers/hc32_ll_driver/inc/hc32_ll_crc.h | 197 + .../drivers/hc32_ll_driver/inc/hc32_ll_dcu.h | 264 + .../drivers/hc32_ll_driver/inc/hc32_ll_def.h | 376 + .../drivers/hc32_ll_driver/inc/hc32_ll_dma.h | 567 + .../drivers/hc32_ll_driver/inc/hc32_ll_efm.h | 458 + .../drivers/hc32_ll_driver/inc/hc32_ll_emb.h | 413 + .../hc32_ll_driver/inc/hc32_ll_event_port.h | 233 + .../drivers/hc32_ll_driver/inc/hc32_ll_fcg.h | 203 + .../drivers/hc32_ll_driver/inc/hc32_ll_fcm.h | 292 + .../drivers/hc32_ll_driver/inc/hc32_ll_gpio.h | 454 + .../drivers/hc32_ll_driver/inc/hc32_ll_hash.h | 93 + .../drivers/hc32_ll_driver/inc/hc32_ll_i2c.h | 319 + .../drivers/hc32_ll_driver/inc/hc32_ll_i2s.h | 342 + .../drivers/hc32_ll_driver/inc/hc32_ll_icg.h | 488 + .../hc32_ll_driver/inc/hc32_ll_interrupts.h | 602 + .../hc32_ll_driver/inc/hc32_ll_keyscan.h | 239 + .../drivers/hc32_ll_driver/inc/hc32_ll_mpu.h | 384 + .../drivers/hc32_ll_driver/inc/hc32_ll_ots.h | 188 + .../drivers/hc32_ll_driver/inc/hc32_ll_pwc.h | 628 + .../drivers/hc32_ll_driver/inc/hc32_ll_qspi.h | 445 + .../drivers/hc32_ll_driver/inc/hc32_ll_rmu.h | 127 + .../drivers/hc32_ll_driver/inc/hc32_ll_rtc.h | 366 + .../hc32_ll_driver/inc/hc32_ll_sdioc.h | 763 + .../drivers/hc32_ll_driver/inc/hc32_ll_spi.h | 432 + .../drivers/hc32_ll_driver/inc/hc32_ll_sram.h | 230 + .../drivers/hc32_ll_driver/inc/hc32_ll_swdt.h | 129 + .../drivers/hc32_ll_driver/inc/hc32_ll_tmr0.h | 227 + .../drivers/hc32_ll_driver/inc/hc32_ll_tmr4.h | 773 + .../drivers/hc32_ll_driver/inc/hc32_ll_tmr6.h | 769 + .../drivers/hc32_ll_driver/inc/hc32_ll_tmra.h | 565 + .../drivers/hc32_ll_driver/inc/hc32_ll_trng.h | 130 + .../hc32_ll_driver/inc/hc32_ll_usart.h | 425 + .../drivers/hc32_ll_driver/inc/hc32_ll_usb.h | 671 + .../hc32_ll_driver/inc/hc32_ll_utility.h | 131 + .../drivers/hc32_ll_driver/inc/hc32_ll_wdt.h | 227 + .../inc/hc32f460_ll_interrupts_share.h | 350 + .../drivers/hc32_ll_driver/src/hc32_ll.c | 170 + .../drivers/hc32_ll_driver/src/hc32_ll_adc.c | 1102 + .../drivers/hc32_ll_driver/src/hc32_ll_aes.c | 271 + .../drivers/hc32_ll_driver/src/hc32_ll_aos.c | 177 + .../drivers/hc32_ll_driver/src/hc32_ll_can.c | 1357 + .../drivers/hc32_ll_driver/src/hc32_ll_clk.c | 1715 + .../drivers/hc32_ll_driver/src/hc32_ll_cmp.c | 698 + .../drivers/hc32_ll_driver/src/hc32_ll_crc.c | 666 + .../drivers/hc32_ll_driver/src/hc32_ll_dcu.c | 537 + .../drivers/hc32_ll_driver/src/hc32_ll_dma.c | 1378 + .../drivers/hc32_ll_driver/src/hc32_ll_efm.c | 1104 + .../drivers/hc32_ll_driver/src/hc32_ll_emb.c | 491 + .../hc32_ll_driver/src/hc32_ll_event_port.c | 442 + .../drivers/hc32_ll_driver/src/hc32_ll_fcg.c | 194 + .../drivers/hc32_ll_driver/src/hc32_ll_fcm.c | 383 + .../drivers/hc32_ll_driver/src/hc32_ll_gpio.c | 631 + .../drivers/hc32_ll_driver/src/hc32_ll_hash.c | 317 + .../drivers/hc32_ll_driver/src/hc32_ll_i2c.c | 1199 + .../drivers/hc32_ll_driver/src/hc32_ll_i2s.c | 1031 + .../drivers/hc32_ll_driver/src/hc32_ll_icg.c | 117 + .../hc32_ll_driver/src/hc32_ll_interrupts.c | 1829 + .../hc32_ll_driver/src/hc32_ll_keyscan.c | 227 + .../drivers/hc32_ll_driver/src/hc32_ll_mpu.c | 891 + .../drivers/hc32_ll_driver/src/hc32_ll_ots.c | 329 + .../drivers/hc32_ll_driver/src/hc32_ll_pwc.c | 1648 + .../drivers/hc32_ll_driver/src/hc32_ll_qspi.c | 471 + .../drivers/hc32_ll_driver/src/hc32_ll_rmu.c | 137 + .../drivers/hc32_ll_driver/src/hc32_ll_rtc.c | 936 + .../hc32_ll_driver/src/hc32_ll_sdioc.c | 2676 + .../drivers/hc32_ll_driver/src/hc32_ll_spi.c | 882 + .../drivers/hc32_ll_driver/src/hc32_ll_sram.c | 301 + .../drivers/hc32_ll_driver/src/hc32_ll_swdt.c | 181 + .../drivers/hc32_ll_driver/src/hc32_ll_tmr0.c | 626 + .../drivers/hc32_ll_driver/src/hc32_ll_tmr4.c | 2179 + .../drivers/hc32_ll_driver/src/hc32_ll_tmr6.c | 1693 + .../drivers/hc32_ll_driver/src/hc32_ll_tmra.c | 1151 + .../drivers/hc32_ll_driver/src/hc32_ll_trng.c | 216 + .../hc32_ll_driver/src/hc32_ll_usart.c | 1926 + .../drivers/hc32_ll_driver/src/hc32_ll_usb.c | 1311 + .../hc32_ll_driver/src/hc32_ll_utility.c | 396 + .../drivers/hc32_ll_driver/src/hc32_ll_wdt.c | 256 + .../src/hc32f460_ll_interrupts_share.c | 2188 + .../hc32/iec60730_class_b_stl/stl_common.h | 145 + .../hc32/iec60730_class_b_stl/stl_conf.h | 106 + .../stl_test_item/inc/stl_sw_crc32.h | 95 + .../stl_test_item/inc/stl_test_cpu.h | 86 + .../stl_test_item/inc/stl_test_flash.h | 87 + .../stl_test_item/inc/stl_test_interrupt.h | 100 + .../stl_test_item/inc/stl_test_pc.h | 85 + .../stl_test_item/inc/stl_test_ram.h | 89 + .../src/EWARM/stl_test_cpu_runtime.s | 245 + .../src/EWARM/stl_test_cpu_startup.s | 357 + .../src/EWARM/stl_test_full_ram_startup.s | 186 + .../stl_test_item/src/EWARM/stl_test_pc.s | 147 + .../src/MDK/stl_test_cpu_runtime.s | 251 + .../src/MDK/stl_test_cpu_startup.s | 363 + .../src/MDK/stl_test_full_ram_startup.s | 191 + .../stl_test_item/src/MDK/stl_test_pc.s | 146 + .../stl_test_item/src/stl_sw_crc32.c | 156 + .../stl_test_item/src/stl_test_flash.c | 164 + .../stl_test_item/src/stl_test_interrupt.c | 169 + .../stl_test_item/src/stl_test_ram_runtime.c | 268 + .../iec60730_class_b_stl/stl_test_runtime.c | 138 + .../iec60730_class_b_stl/stl_test_runtime.h | 116 + .../iec60730_class_b_stl/stl_test_startup.c | 120 + .../iec60730_class_b_stl/stl_test_startup.h | 111 + .../hc32/iec60730_class_b_stl/stl_utility.c | 234 + .../hc32/iec60730_class_b_stl/stl_utility.h | 107 + .../usb_dev_cdc_msc_wrapper.c | 334 + .../usb_dev_cdc_msc_wrapper.h | 79 + .../custom_hid/usb_dev_custom_hid_class.c | 381 + .../custom_hid/usb_dev_custom_hid_class.h | 130 + .../usb_dev_hid_cdc_wrapper.c | 364 + .../usb_dev_hid_cdc_wrapper.h | 74 + .../hid_keyboard/usb_dev_keyboard_class.c | 330 + .../hid_keyboard/usb_dev_keyboard_class.h | 101 + .../hid_mouse/usb_dev_mouse_class.c | 345 + .../hid_mouse/usb_dev_mouse_class.h | 101 + .../usb_dev_hid_msc_wrapper.c | 273 + .../usb_dev_hid_msc_wrapper.h | 80 + .../device_class/msc/usb_dev_msc_bot.c | 267 + .../device_class/msc/usb_dev_msc_bot.h | 137 + .../device_class/msc/usb_dev_msc_class.c | 264 + .../device_class/msc/usb_dev_msc_class.h | 94 + .../device_class/msc/usb_dev_msc_data.c | 111 + .../device_class/msc/usb_dev_msc_data.h | 92 + .../device_class/msc/usb_dev_msc_mem.h | 90 + .../device_class/msc/usb_dev_msc_scsi.c | 553 + .../device_class/msc/usb_dev_msc_scsi.h | 167 + .../single_cdc/usb_dev_cdc_class.c | 427 + .../single_cdc/usb_dev_cdc_class.h | 121 + .../usb_device_lib/device_core/usb_dev_core.c | 339 + .../usb_device_lib/device_core/usb_dev_core.h | 82 + .../device_core/usb_dev_ctrleptrans.c | 159 + .../device_core/usb_dev_ctrleptrans.h | 83 + .../usb_device_lib/device_core/usb_dev_def.h | 155 + .../device_core/usb_dev_driver.c | 400 + .../device_core/usb_dev_driver.h | 89 + .../usb_device_lib/device_core/usb_dev_int.c | 456 + .../usb_device_lib/device_core/usb_dev_int.h | 136 + .../device_core/usb_dev_stdreq.c | 606 + .../device_core/usb_dev_stdreq.h | 82 + .../host_class/cdc/usb_host_cdc_class.c | 693 + .../host_class/cdc/usb_host_cdc_class.h | 169 + .../host_class/cdc/usb_host_cdc_ctrl.c | 175 + .../host_class/cdc/usb_host_cdc_ctrl.h | 221 + .../host_class/hid/usb_host_hid_class.c | 443 + .../host_class/hid/usb_host_hid_class.h | 167 + .../host_class/hid/usb_host_hid_keyboardapp.c | 277 + .../host_class/hid/usb_host_hid_keyboardapp.h | 99 + .../host_class/hid/usb_host_hid_mouseapp.c | 122 + .../host_class/hid/usb_host_hid_mouseapp.h | 92 + .../host_class/msc/usb_host_msc_bot.c | 449 + .../host_class/msc/usb_host_msc_bot.h | 162 + .../host_class/msc/usb_host_msc_class.c | 395 + .../host_class/msc/usb_host_msc_class.h | 113 + .../host_class/msc/usb_host_msc_fatfs.c | 241 + .../host_class/msc/usb_host_msc_scsi.c | 528 + .../host_class/msc/usb_host_msc_scsi.h | 136 + .../usb_host_lib/host_core/usb_host_cfgch.c | 202 + .../usb_host_lib/host_core/usb_host_cfgch.h | 103 + .../usb_host_lib/host_core/usb_host_core.c | 537 + .../usb_host_lib/host_core/usb_host_core.h | 95 + .../host_core/usb_host_ctrltrans.c | 320 + .../host_core/usb_host_ctrltrans.h | 86 + .../usb/usb_host_lib/host_core/usb_host_def.h | 430 + .../usb_host_lib/host_core/usb_host_driver.c | 231 + .../usb_host_lib/host_core/usb_host_driver.h | 90 + .../usb/usb_host_lib/host_core/usb_host_int.c | 575 + .../usb/usb_host_lib/host_core/usb_host_int.h | 128 + .../usb_host_lib/host_core/usb_host_stdreq.c | 482 + .../usb_host_lib/host_core/usb_host_stdreq.h | 107 + .../hc32f460_ddl/midwares/hc32/usb/usb_lib.h | 199 + 352 files changed, 270588 insertions(+), 2674 deletions(-) create mode 100644 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bsp/hc32/libraries/hc32f460_ddl/README.txt create mode 100644 bsp/hc32/libraries/hc32f460_ddl/SConscript create mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/flashloader/FlashHC32F460.mac create mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/flashloader/FlashHC32F460.out create mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/flashloader/FlashHC32F460_otp.flash create mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/flashloader/FlashHC32F460_otp.mac create mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/flashloader/FlashHC32F460_otp.out create mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/flashloader/FlashHC32F460xC.flash create mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/flashloader/FlashHC32F460xE.flash create mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/flashloader/HC32F460xC.board create mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/flashloader/HC32F460xE.board create mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460_ram.icf create mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xC.icf create mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xE.icf create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/bsp/components/24cxx/24cxx.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/bsp/components/24cxx/24cxx.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/bsp/components/w25qxx/w25qxx.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/bsp/components/w25qxx/w25qxx.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/bsp/components/wm8731/wm8731.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/bsp/components/wm8731/wm8731.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/bsp/ev_hc32f460_lqfp100_v2/ev_hc32f460_lqfp100_v2.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/bsp/ev_hc32f460_lqfp100_v2/ev_hc32f460_lqfp100_v2.h create mode 100644 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bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/system_hc32f460.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_256K.FLM create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_512K.FLM create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_RAM.FLM create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F460_otp.FLM create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/ram.ini create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F460.SFR create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f460.s create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F460xC.ld create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F460xE.ld create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f460.S create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HDSC_HC32F460.svd create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460.mac create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460.out create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460_otp.mac create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460_otp.out create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f460.s create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HDSC_HC32F460.svd create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f460.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_common_tables.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_const_structs.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_helium_utils.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_math.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_mve_tables.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_vec_math.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cachel1_armv7.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_armcc.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_armclang.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_armclang_ltm.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_compiler.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_gcc.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_iccarm.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_version.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_armv81mml.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_armv8mbl.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_armv8mml.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm0.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm0plus.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm1.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm23.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm3.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm33.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm35p.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm4.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm55.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm7.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_sc000.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_sc300.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/mpu_armv7.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/mpu_armv8.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/pmu_armv8.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/tz_context.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_adc.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aes.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aos.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_can.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_clk.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_cmp.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_crc.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dcu.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_def.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dma.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_efm.h create 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bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_keyscan.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mpu.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ots.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_pwc.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_qspi.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rmu.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rtc.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sdioc.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_spi.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sram.h create mode 100644 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bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_dma.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_efm.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_emb.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_event_port.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcg.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcm.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_gpio.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_hash.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2c.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2s.c create mode 100644 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bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_utility.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_wdt.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32f460_ll_interrupts_share.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h create mode 100644 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create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_fatfs.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_def.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.c create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.h create mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_lib.h diff --git a/bsp/hc32/README.md b/bsp/hc32/README.md index ab297d37e5..ec27b5fdfd 100644 --- a/bsp/hc32/README.md +++ b/bsp/hc32/README.md @@ -7,6 +7,7 @@ HC32 系列 BSP 目前支持情况如下表所示： |:------------------------- |:------------------------- | | **F1 系列** | | | **F4 系列** | | +| [ev_hc32f460_lqfp100_v2](ev_hc32f460_lqfp100_v2) | 小华 官方 EV_F460_LQ100_V2 开发板 | | [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 | | **M1 系列** | | | **M4 系列** | | diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/.config b/bsp/hc32/ev_hc32f460_lqfp100_v2/.config new file mode 100644 index 0000000000..a4a1a7817d --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/.config @@ -0,0 +1,688 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart4" +CONFIG_RT_VER_NUM=0x40101 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set +# CONFIG_RT_USING_LWP is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_BITOPS is not set +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# POSIX extension functions +# +# CONFIG_PKG_USING_POSIX_GETLINE is not set +# CONFIG_PKG_USING_POSIX_WCWIDTH is not set +# CONFIG_PKG_USING_POSIX_ITOA is not set +# CONFIG_PKG_USING_POSIX_STRINGS is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_RTDUINO is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +CONFIG_SOC_FAMILY_HC32=y +CONFIG_SOC_SERIES_HC32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HC32F460PE=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +CONFIG_BSP_USING_UART4=y +# CONFIG_BSP_UART4_RX_USING_DMA is not set +# CONFIG_BSP_UART4_TX_USING_DMA is not set + +# +# Board extended module Drivers +# diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/.gitignore b/bsp/hc32/ev_hc32f460_lqfp100_v2/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/Kconfig b/bsp/hc32/ev_hc32f460_lqfp100_v2/Kconfig new file mode 100644 index 0000000000..8cbc7b71a8 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md b/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md new file mode 100644 index 0000000000..9414adad71 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md @@ -0,0 +1,107 @@ +# XHSC EV_F460_LQ100_V2 开发板 BSP 说明 + +## 简介 + +本文档为小华半导体为 EV_F460_LQ100_V2 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +EV_F460_LQ100_V2 是 XHSC 官方推出的开发板，搭载 HC32F460PETB 芯片，基于 ARM Cortex-M4 内核，最高主频 200 MHz，具有丰富的板载资源，可以充分发挥 HC32F460PETB 的芯片性能。 + +开发板外观如下图所示： + + ![board](figures/board.jpg) + +EV_F460_LQ100_V2 开发板常用 **板载资源** 如下： + +- MCU: HC32F460PETB，主频200MHz，512KB FLASH，192KB RAM +- 常用外设 + - LED: 4 个，User LED(LED0，LED1，LED2，LED3)。 + - 按键: 11 个，矩阵键盘(K1~K9), WAKEUP(K10), RESET(K11) +- 常用接口: USB转串口、SD卡接口、USB FS、3.5mm耳机接口、Line in接口、喇叭接口 +- 调试接口: 板载DAP调试器、标准JTAG/SWD + +开发板更多详细信息请参考小华半导体半导体[EV_F460_LQ100_V2](http://www.xhsc.com.cn) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| USB 转串口 | 支持 | 使用 UART4 | +| LED | 支持 | LED | +| **片上外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 | +| UART | 支持 | UART1~4 | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用Type-A to MircoUSB线连接开发板和PC供电。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED1会周期性闪烁。 + +USB虚拟COM端口默认连接串口4，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.1.1 build May 25 2022 08:55:55 + 2006 - 2022 Copyright by RT-Thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 4 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +## 注意事项 + +## 联系人信息 + +维护人: + +- [小华半导体MCU](http://www.xhsc.com.cn)，邮箱： \ No newline at end of file diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/SConscript b/bsp/hc32/ev_hc32f460_lqfp100_v2/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/SConstruct b/bsp/hc32/ev_hc32f460_lqfp100_v2/SConstruct new file mode 100644 index 0000000000..2a85e43b75 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +hc32_library = 'hc32f460_ddl' +rtconfig.BSP_LIBRARY_TYPE = hc32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/applications/SConscript b/bsp/hc32/ev_hc32f460_lqfp100_v2/applications/SConscript new file mode 100644 index 0000000000..01eb940dfb --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/applications/main.c b/bsp/hc32/ev_hc32f460_lqfp100_v2/applications/main.c new file mode 100644 index 0000000000..3c4e3bd322 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/applications/main.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include +#include + + +/* defined the LED_GREEN pin: PD4 */ +#define LED_GREEN_PIN GET_PIN(D, 4) + + +int main(void) +{ + /* set LED_GREEN_PIN pin mode to output */ + rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_GREEN_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_GREEN_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} + diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig new file mode 100644 index 0000000000..afe9905a50 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig @@ -0,0 +1,88 @@ +menu "Hardware Drivers Config" + +config SOC_HC32F460PE + bool + select SOC_SERIES_HC32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART4 + bool "Enable UART4" + default n + + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/SConscript b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/SConscript new file mode 100644 index 0000000000..ac8a96453a --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/SConscript @@ -0,0 +1,31 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +board_config.c +''') + +path = [cwd] +path += [cwd + '/ports'] +path += [cwd + '/config'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f460.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f460.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f460.s'] + +CPPDEFINES = ['HC32F460'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c new file mode 100644 index 0000000000..e391086b08 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include "board.h" + +/* unlock/lock peripheral */ +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) + +/** + * @brief This function is executed in case of error occurrence. + * @param None + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler */ + /* User can add his own implementation to report the HAL error return state */ + while (1) + { + } + /* USER CODE END Error_Handler */ +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + stc_clock_xtal_init_t stcXtalInit; + stc_clock_pll_init_t stcMpllInit; + + (void)CLK_XtalStructInit(&stcXtalInit); + (void)CLK_PLLStructInit(&stcMpllInit); + + /* Set bus clk div. */ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, (CLK_HCLK_DIV1 | CLK_EXCLK_DIV2 | CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | \ + CLK_PCLK2_DIV4 | CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2)); + + /* Config Xtal and enable Xtal */ + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; + (void)CLK_XtalInit(&stcXtalInit); + + /* MPLL config (XTAL / pllmDiv * plln / PllpDiv = 200M). */ + stcMpllInit.PLLCFGR = 0UL; + stcMpllInit.PLLCFGR_f.PLLM = 1UL - 1UL; + stcMpllInit.PLLCFGR_f.PLLN = 50UL - 1UL; + stcMpllInit.PLLCFGR_f.PLLP = 2UL - 1UL; + stcMpllInit.PLLCFGR_f.PLLQ = 2UL - 1UL; + stcMpllInit.PLLCFGR_f.PLLR = 2UL - 1UL; + stcMpllInit.u8PLLState = CLK_PLL_ON; + stcMpllInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; + (void)CLK_PLLInit(&stcMpllInit); + /* Wait MPLL ready. */ + while (SET != CLK_GetStableStatus(CLK_STB_FLAG_PLL)) + { + ; + } + + /* sram init include read/write wait cycle setting */ + SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0); + SRAM_SetWaitCycle((SRAM_SRAM12 | SRAM_SRAM3 | SRAM_SRAMR), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1); + + /* flash read wait cycle setting */ + (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5); + /* 3 cycles for 126MHz ~ 200MHz */ + GPIO_SetReadWaitCycle(GPIO_RD_WAIT3); + /* Switch driver ability */ + (void)PWC_HighSpeedToHighPerformance(); + /* Switch system clock source to MPLL. */ + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); +} + +/** Peripheral Clock Configuration +*/ +static void PeripheralClock_Config(void) +{ +#if defined(HC32F460) +#if defined(BSP_USING_CAN1) + CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6); +#endif + +#if defined(RT_USING_ADC) + CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); +#endif +#endif +} + +/******************************************************************************* + * Function Name : SysTick_Configuration + * Description : Configures the SysTick for OS tick. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SysTick_Configuration(void) +{ + stc_clock_freq_t stcClkFreq; + rt_uint32_t cnts; + + CLK_GetClockFreq(&stcClkFreq); + + cnts = (rt_uint32_t)stcClkFreq.u32HclkFreq / RT_TICK_PER_SECOND; + + SysTick_Config(cnts); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial HC32 board. + */ +void rt_hw_board_init() +{ + /* Peripheral registers write unprotected */ + LL_PERIPH_WE(EXAMPLE_PERIPH_WE); + + SystemClock_Config(); + PeripheralClock_Config(); + /* Configure the SysTick */ + SysTick_Configuration(); + + /* Heap initialization */ +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + + /* Board underlying hardware initialization */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + uint32_t start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = SystemCoreClock / 1000000UL; + + do + { + now = SysTick->VAL; + delta = start > now ? start - now : reload + start - now; + } + while (delta < us_tick * us); +} + +/*@}*/ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.h new file mode 100644 index 0000000000..e578847ccc --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "hc32_ll.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HC32_SRAM_SIZE (188) +#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024) + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END HC32_SRAM_END + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c new file mode 100644 index 0000000000..50cb97e85f --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include "board_config.h" + +/** + * The below functions will initialize HC32 board. + */ + +#if defined RT_USING_SERIAL +rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)USARTx) + { +#if defined(BSP_USING_UART4) + case (rt_uint32_t)CM_USART4: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART4_RX_PORT, USART4_RX_PIN, GPIO_FUNC_37); + GPIO_SetFunc(USART4_TX_PORT, USART4_TX_PIN, GPIO_FUNC_36); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h new file mode 100644 index 0000000000..c70b9229d2 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + + +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include +#include "hc32_ll.h" +#include "drv_config.h" + + +/************************ USART port **********************/ +#if defined(BSP_USING_UART1) + #define USART1_RX_PORT (GPIO_PORT_C) + #define USART1_RX_PIN (GPIO_PIN_04) + + #define USART1_TX_PORT (GPIO_PORT_A) + #define USART1_TX_PIN (GPIO_PIN_07) +#endif + +#if defined(BSP_USING_UART2) + #define USART2_RX_PORT (GPIO_PORT_A) + #define USART2_RX_PIN (GPIO_PIN_04) + + #define USART2_TX_PORT (GPIO_PORT_A) + #define USART2_TX_PIN (GPIO_PIN_02) +#endif + +#if defined(BSP_USING_UART3) + #define USART3_RX_PORT (GPIO_PORT_C) + #define USART3_RX_PIN (GPIO_PIN_13) + + #define USART3_TX_PORT (GPIO_PORT_H) + #define USART3_TX_PIN (GPIO_PIN_02) +#endif + +#if defined(BSP_USING_UART4) + #define USART4_RX_PORT (GPIO_PORT_B) + #define USART4_RX_PIN (GPIO_PIN_09) + + #define USART4_TX_PORT (GPIO_PORT_E) + #define USART4_TX_PIN (GPIO_PIN_06) +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/dma_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/dma_config.h new file mode 100644 index 0000000000..99cbf373bc --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/dma_config.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* DMA1 ch0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_RX_DMA_INSTANCE CM_DMA1 +#define SPI1_RX_DMA_CHANNEL DMA_CH0 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#endif + +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_RX_DMA_INSTANCE CM_DMA1 +#define SPI3_RX_DMA_CHANNEL DMA_CH0 +#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#endif + +/* DMA1 ch1 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_TX_DMA_INSTANCE CM_DMA1 +#define SPI1_TX_DMA_CHANNEL DMA_CH1 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#endif + +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_TX_DMA_INSTANCE CM_DMA1 +#define SPI3_TX_DMA_CHANNEL DMA_CH1 +#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#endif + +/* DMA1 ch2 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_RX_DMA_INSTANCE CM_DMA1 +#define SPI2_RX_DMA_CHANNEL DMA_CH2 +#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#endif + +/* DMA1 ch3 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_TX_DMA_INSTANCE CM_DMA1 +#define SPI2_TX_DMA_CHANNEL DMA_CH3 +#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#endif + +#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) +#define SPI4_RX_DMA_INSTANCE CM_DMA1 +#define SPI4_RX_DMA_CHANNEL DMA_CH2 +#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI4_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#endif + +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_TX_DMA_INSTANCE CM_DMA1 +#define SPI4_TX_DMA_CHANNEL DMA_CH3 +#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI4_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#endif + +/* DMA2 ch0 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_RX_DMA_INSTANCE CM_DMA2 +#define UART1_RX_DMA_CHANNEL DMA_CH0 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#endif + +#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) +#define UART3_RX_DMA_INSTANCE CM_DMA2 +#define UART3_RX_DMA_CHANNEL DMA_CH0 +#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART3_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART3_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART3_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define UART3_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#endif + +/* DMA2 ch1 */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_TX_DMA_INSTANCE CM_DMA2 +#define UART1_TX_DMA_CHANNEL DMA_CH1 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#endif + +#if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE) +#define UART3_TX_DMA_INSTANCE CM_DMA2 +#define UART3_TX_DMA_CHANNEL DMA_CH1 +#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART3_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART3_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART3_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define UART3_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#endif + +/* DMA2 ch2 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_RX_DMA_INSTANCE CM_DMA2 +#define UART2_RX_DMA_CHANNEL DMA_CH2 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#endif + +#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) +#define UART4_RX_DMA_INSTANCE CM_DMA2 +#define UART4_RX_DMA_CHANNEL DMA_CH2 +#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART4_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART4_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART4_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define UART4_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#endif + +/* DMA2 ch3 */ +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_TX_DMA_INSTANCE CM_DMA2 +#define UART2_TX_DMA_CHANNEL DMA_CH3 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#endif + +#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) +#define UART4_TX_DMA_INSTANCE CM_DMA2 +#define UART4_TX_DMA_CHANNEL DMA_CH3 +#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART4_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/gpio_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/gpio_config.h new file mode 100644 index 0000000000..fe5492d575 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/gpio_config.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __GPIO_CONFIG_H__ +#define __GPIO_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(RT_USING_PIN) + +#ifndef EXTINT0_IRQ_CONFIG +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT1_IRQ_CONFIG +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT2_IRQ_CONFIG +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ + } +#endif /* EXTINT2_IRQ_CONFIG */ + +#ifndef EXTINT3_IRQ_CONFIG +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ + } +#endif /* EXTINT3_IRQ_CONFIG */ + +#ifndef EXTINT4_IRQ_CONFIG +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ + } +#endif /* EXTINT4_IRQ_CONFIG */ + +#ifndef EXTINT5_IRQ_CONFIG +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ + } +#endif /* EXTINT5_IRQ_CONFIG */ + +#ifndef EXTINT6_IRQ_CONFIG +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ + } +#endif /* EXTINT6_IRQ_CONFIG */ + +#ifndef EXTINT7_IRQ_CONFIG +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ + } +#endif /* EXTINT7_IRQ_CONFIG */ + +#ifndef EXTINT8_IRQ_CONFIG +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ + } +#endif /* EXTINT8_IRQ_CONFIG */ + +#ifndef EXTINT9_IRQ_CONFIG +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ + } +#endif /* EXTINT9_IRQ_CONFIG */ + +#ifndef EXTINT10_IRQ_CONFIG +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ + } +#endif /* EXTINT10_IRQ_CONFIG */ + +#ifndef EXTINT11_IRQ_CONFIG +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ + } +#endif /* EXTINT11_IRQ_CONFIG */ + +#ifndef EXTINT12_IRQ_CONFIG +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ + } +#endif /* EXTINT12_IRQ_CONFIG */ + +#ifndef EXTINT13_IRQ_CONFIG +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ + } +#endif /* EXTINT13_IRQ_CONFIG */ + +#ifndef EXTINT14_IRQ_CONFIG +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ + } +#endif /* EXTINT14_IRQ_CONFIG */ + +#ifndef EXTINT15_IRQ_CONFIG +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ + } +#endif /* EXTINT15_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/irq_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/irq_config.h new file mode 100644 index 0000000000..0f1e675017 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/irq_config.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __IRQ_CONFIG_H__ +#define __IRQ_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_EXTINT0_IRQ_NUM INT022_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM INT023_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM INT024_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM INT025_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM INT026_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM INT027_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM INT028_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM INT029_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM INT030_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM INT031_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM INT032_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM INT033_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM INT034_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM INT035_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM INT036_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM INT037_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA1 ch0 */ +#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch1 */ +#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch2 */ +#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch3 */ +#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA2 ch0 */ +#define BSP_DMA2_CH0_IRQ_NUM INT042_IRQn +#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch1 */ +#define BSP_DMA2_CH1_IRQ_NUM INT043_IRQn +#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch2 */ +#define BSP_DMA2_CH2_IRQ_NUM INT008_IRQn +#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch3 */ +#define BSP_DMA2_CH3_IRQ_NUM INT009_IRQn +#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + + +#if defined(BSP_USING_UART1) +#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn +#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RX_IRQ_NUM INT083_IRQn +#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_IRQ_NUM INT082_IRQn +#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART1_RX_USING_DMA) +#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn +#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#if defined(BSP_UART1_TX_USING_DMA) +#define BSP_UART1_TX_CPLT_IRQ_NUM INT080_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn +#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RX_IRQ_NUM INT085_IRQn +#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_IRQ_NUM INT084_IRQn +#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART2_RX_USING_DMA) +#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn +#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#if defined(BSP_UART2_TX_USING_DMA) +#define BSP_UART2_TX_CPLT_IRQ_NUM INT081_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn +#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RX_IRQ_NUM INT089_IRQn +#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_IRQ_NUM INT088_IRQn +#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART3_RX_USING_DMA) +#define BSP_UART3_RXTO_IRQ_NUM INT014_IRQn +#define BSP_UART3_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#if defined(BSP_UART3_TX_USING_DMA) +#define BSP_UART3_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn +#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RX_IRQ_NUM INT091_IRQn +#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_IRQ_NUM INT090_IRQn +#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART4_RX_USING_DMA) +#define BSP_UART4_RXTO_IRQ_NUM INT015_IRQn +#define BSP_UART4_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#if defined(BSP_UART4_TX_USING_DMA) +#define BSP_UART4_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_CAN1) +#define BSP_CAN1_IRQ_NUM INT004_IRQn +#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_CAN1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/uart_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/uart_config.h new file mode 100644 index 0000000000..be463c1700 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/uart_config.h @@ -0,0 +1,407 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG1_PERIPH_USART1, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART1_RX_IRQ_NUM, \ + .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART1_TX_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TI, \ + }, \ + } +#endif /* UART1_CONFIG */ + +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .irq_config = \ + { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_RX_CONFIG */ + +#ifndef UART1_RXTO_CONFIG +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RTO, \ + }, \ + } +#endif /* UART1_RXTO_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif /* UART1_TX_CPLT_CONFIG */ + +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .irq_config = \ + { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG1_PERIPH_USART2, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART2_RX_IRQ_NUM, \ + .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART2_TX_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TI, \ + }, \ + } +#endif /* UART2_CONFIG */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .irq_config = \ + { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_RX_CONFIG */ + +#ifndef UART2_RXTO_CONFIG +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RTO, \ + }, \ + } +#endif /* UART2_RXTO_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ + +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif /* UART2_TX_CPLT_CONFIG */ + +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .irq_config = \ + { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG1_PERIPH_USART3, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART3_RX_IRQ_NUM, \ + .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART3_TX_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TI, \ + }, \ + } +#endif /* UART3_CONFIG */ + +#if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_DMA_RX_CONFIG +#define UART3_DMA_RX_CONFIG \ + { \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .channel = UART3_RX_DMA_CHANNEL, \ + .clock = UART3_RX_DMA_CLOCK, \ + .trigger_select = UART3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART3_RI, \ + .irq_config = \ + { \ + .irq_num = UART3_RX_DMA_IRQn, \ + .irq_prio = UART3_RX_DMA_INT_PRIO, \ + .int_src = UART3_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART3_DMA_RX_CONFIG */ + +#ifndef UART3_RXTO_CONFIG +#define UART3_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART3_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART3_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_RTO, \ + }, \ + } +#endif /* UART3_RXTO_CONFIG */ +#endif /* BSP_UART3_RX_USING_DMA */ + +#if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_TX_CPLT_CONFIG +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ + } +#endif /* UART3_TX_CPLT_CONFIG */ + +#ifndef UART3_DMA_TX_CONFIG +#define UART3_DMA_TX_CONFIG \ + { \ + .Instance = UART3_TX_DMA_INSTANCE, \ + .channel = UART3_TX_DMA_CHANNEL, \ + .clock = UART3_TX_DMA_CLOCK, \ + .trigger_select = UART3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART3_TI, \ + .irq_config = \ + { \ + .irq_num = UART3_TX_DMA_IRQn, \ + .irq_prio = UART3_TX_DMA_INT_PRIO, \ + .int_src = UART3_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART3_DMA_TX_CONFIG */ +#endif /* BSP_UART3_TX_USING_DMA */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG1_PERIPH_USART4, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART4_RX_IRQ_NUM, \ + .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART4_TX_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TI, \ + }, \ + } +#endif /* UART4_CONFIG */ + +#if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_DMA_RX_CONFIG +#define UART4_DMA_RX_CONFIG \ + { \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .channel = UART4_RX_DMA_CHANNEL, \ + .clock = UART4_RX_DMA_CLOCK, \ + .trigger_select = UART4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_RI, \ + .irq_config = \ + { \ + .irq_num = UART4_RX_DMA_IRQn, \ + .irq_prio = UART4_RX_DMA_INT_PRIO, \ + .int_src = UART4_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART4_DMA_RX_CONFIG */ + +#ifndef UART4_RXTO_CONFIG +#define UART4_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART4_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART4_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_RTO, \ + }, \ + } +#endif /* UART4_RXTO_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ + +#if defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_TX_CPLT_CONFIG +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ + } +#endif /* UART4_TX_CPLT_CONFIG */ + +#ifndef UART4_DMA_TX_CONFIG +#define UART4_DMA_TX_CONFIG \ + { \ + .Instance = UART4_TX_DMA_INSTANCE, \ + .channel = UART4_TX_DMA_CHANNEL, \ + .clock = UART4_TX_DMA_CLOCK, \ + .trigger_select = UART4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_TI, \ + .irq_config = \ + { \ + .irq_num = UART4_TX_DMA_IRQn, \ + .irq_prio = UART4_TX_DMA_INT_PRIO, \ + .int_src = UART4_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART4_DMA_TX_CONFIG */ +#endif /* BSP_UART4_TX_USING_DMA */ +#endif /* BSP_USING_UART4 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/drv_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/drv_config.h new file mode 100644 index 0000000000..6594e6b297 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/drv_config.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __DRV_CONFIG_H__ +#define __DRV_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dma_config.h" +#include "uart_config.h" +#include "gpio_config.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/hc32f4xx_conf.h new file mode 100644 index 0000000000..99e4acdb5d --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/hc32f4xx_conf.h @@ -0,0 +1,167 @@ +/** + ******************************************************************************* + * @file template/source/hc32f4xx_conf.h + * @brief This file contains HC32 Series Device Driver Library usage management. + @verbatim + Change Logs: + Date Author Notes + 2022-04-28 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4XX_CONF_H__ +#define __HC32F4XX_CONF_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @brief This is the list of modules to be used in the Device Driver Library. + * Select the modules you need to use to DDL_ON. + * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + * properly. + * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + * Library. + * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + */ +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) + +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AES_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CAN_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DCU_ENABLE (DDL_ON) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_DMC_ENABLE (DDL_ON) +#define LL_DVP_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_ETH_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_FMAC_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_ON) +#define LL_HRPWM_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_I2S_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MAU_ENABLE (DDL_ON) +#define LL_MDIO_ENABLE (DDL_OFF) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_NFC_ENABLE (DDL_ON) +#define LL_OTS_ENABLE (DDL_ON) +#define LL_PLA_ENABLE (DDL_OFF) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SDIOC_ENABLE (DDL_ON) +#define LL_SMC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR2_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_USB_ENABLE (DDL_OFF) +#define LL_VREF_ENABLE (DDL_OFF) +#define LL_WDT_ENABLE (DDL_ON) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F4A0_LQFP176 (1U) +#define BSP_EV_HC32F4A0_LQFP176_MEM (2U) +#define BSP_EV_HC32F460_LQFP100_V1 (3U) +#define BSP_EV_HC32F460_LQFP100_V2 (4U) +#define BSP_EV_HC32F451_LQFP100 (5U) +#define BSP_EV_HC32F452_LQFP100 (6U) +#define BSP_EV_HC32F472_LQFP100 (7U) +#define BSP_SK_HC32F4A0_LQFP100 (8U) + +/** + * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to 0U. + */ +#define BSP_EV_HC32F4XX (BSP_EV_HC32F460_LQFP100_V2) + +/** + * @brief This is the list of BSP components to be used. + * Select the components you need to use to DDL_ON. + */ +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_CY62167EV30LL_ENABLE (DDL_OFF) +#define BSP_IS42S16400J7TLI_ENABLE (DDL_OFF) +#define BSP_IS62WV51216_ENABLE (DDL_OFF) +#define BSP_MT29F2G08AB_ENABLE (DDL_OFF) +#define BSP_NT35510_ENABLE (DDL_OFF) +#define BSP_OV5640_ENABLE (DDL_OFF) +#define BSP_S29GL064N90TFI03_ENABLE (DDL_OFF) +#define BSP_TCA9539_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_WM8731_ENABLE (DDL_OFF) + +/** + * @brief The macro is used to re-define main function in system_device.c(eg. device=hc32f4a0). + * @note Set value to non-zero if re-define main function. + */ +#define RE_DEFINE_MAIN (0) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4XX_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.icf new file mode 100644 index 0000000000..b7ba20831a --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.icf @@ -0,0 +1,51 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00; +define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0xC00; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.ld b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.ld new file mode 100644 index 0000000000..d65fd6b5f2 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.ld @@ -0,0 +1,267 @@ +/****************************************************************************** + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F460xE.ld */ +/* Abstract Linker script for HC32F460 Device with */ +/* 512KByte FLASH, 192KByte RAM */ +/* Version V1.0 */ +/* Date 2022-04-28 */ +/*****************************************************************************/ + +/* Custom defines, according to section 7.7 of the user manual. + Take OTP sector 0 for example. */ +__OTP_DATA_START = 0x03000C00; +__OTP_DATA_SIZE = 64; +__OTP_LOCK_START = 0x03000FC0; +__OTP_LOCK_SIZE = 4; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 512K + OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE + OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE + RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 188K + RET_RAM (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data_sec : + { + KEEP(*(.otp_data_sec)) + } >OTP_DATA + + .otp_lock_sec : + { + KEEP(*(.otp_lock_sec)) + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4); + .ret_ram_data : AT (__etext_ret_ram) + { + . = ALIGN(4); + __data_start_ret_ram__ = .; + *(.ret_ram_data) + *(.ret_ram_data*) + . = ALIGN(4); + __data_end_ret_ram__ = .; + } >RET_RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + __bss_end = .; + + .ret_ram_bss : + { + . = ALIGN(4); + __bss_start_ret_ram__ = .; + *(.ret_ram_bss) + *(.ret_ram_bss*) + . = ALIGN(4); + __bss_end_ret_ram__ = .; + } >RET_RAM + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.sct b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.sct new file mode 100644 index 0000000000..61160eee1b --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; **************************************************************** +; Scatter-Loading Description File +; **************************************************************** +LR_IROM1 0x00000000 0x00080000 { ; load region size_region + ER_IROM1 0x00000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x1FFF8000 0x0002F000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/figures/board.jpg b/bsp/hc32/ev_hc32f460_lqfp100_v2/figures/board.jpg new file mode 100644 index 0000000000000000000000000000000000000000..3a012313dd14990c49c36e49666802c7670131f1 GIT binary patch literal 980523 zcmeFa2Ut^0*C@IH1r-rdK?Ny-1*P{Iq9Pz7(z_5bgd!vXLdOsl6$Jqir3#1$h;->S zA_9sc(mPRl?=2za>|lA{_xrx{|F@m{ocmly_ueyWty!~XP1!SH&DykX+IK;chL4jy z0O;xhrvU)i0kAOu023HvV1EnV7=FZAzk+ebtvDU`nt}NT9AE_D`+mm3j0~JV;~*6S zH?W<~2fXqacz(xA8HE3qSBlO7-~+F>4ANWi17LiRasOXDgPeeEAdJpu1$^j(GSdI; zBHsjnlY4(X&)T7{Aq4at(H>}wBidC!-AGh&tCh)}hNMk#VcPSq72U|^s5K9GjYTG=Amo-m5d3m?+>HGGPmDHlTj?q<9d#`&@ zX~p%OV`~apW)9v#(di`(UE}K<03#zP?Y1qMSeUoVZHaJHYTq_c0yn|^+of+s9H2{3 zW7x7FbL`r8_uG%vjX2>L*~R0`bOBgS$h~U?g-AJQr(q)Rff)KN!v9=?lYfao>jic* zZI#IZK!Le{0_-)&o^sxzd^Z_*AG}u}KRef61!ljA)g!;FyBo1OpC!}2sm2G%c7A3) zJI5yKSmHZ4KuBA4T&a>6rCw_zbp?N3M#xXNWndNu`*;od7mEo73sW#FXA~t$LMa!) zCHJ^h+=JDHo4GC&oncHek?E!Z4*5wDnY07@JUh)Ft&j86SP0}jC~+y;t2i(Xc^AkP834|h)> z4D-BdF_nu_*o%FU0uPLLKH~~)D%vDW1%&2$Q?str)E_N2on~E{S{0U8YH*BVH%R)n z-nN;T{?&+7`_uc7-Ho1nBv?X+!%MAZEp5vJPk;s0T=IXxA5bl0T0PRiVCYz z0y+!R_OfIpK{bd&xlht+$|qM1tutNSUGKA3KC;vmV!A+R@=u@v zHrl1USKqGK9dh9v@vj=5C|SoZz*Zb7oYeh<@Wqs;h5l~OhTl3P1BLwA%Lw1CR-hU4 zl#>%}c(VPN^CX_Vy5}{;qrcf}wweZz*?eihOm*d2^looO-Zr)LQXSa$xzz*`Y`SYI zLnYPo?Uf@fYLhG-(ihmh(cYOWG~he(VkIZ8)4u{*@2&5`jNe^)FJ>k82o=>j+c!YY zO`fDa)t~{xCtvqbI5wJZ@8kGgKG(Y=OKD#09NanPMMntj>ZrQN^%g-%d~tJ=C> zDAk(=Y%^W-!|A_ID#~xlA7Ox1QaGCNUi0?NV>Do>HFrBKqzgBEYc-aj(fw_i+;WSz zc`_h45MM80zK;B8t2TS9^!@FtyF3S|T$EKB0N-@pYi5>G+-YbtmQd3fRn9xt?c6sL z(0=r5IjdJ_%o+!AFne&4=WtIbnQUdT0!?e1#wkQj?C0O+<`eA$wvTv)bCs$~TGdFx z%i)`>wiUb??9Z>tDn>e{%yhZR@dnw01JluU zpBsxhIz+P|U)E>#Fu8e#t?9K4RCE_e)YR5p{g^X7I39F%ThZO@JpuJS1_|Mr-IiOPlH96YmRrA zVfr@%8k;((LFALvo$WLrByREg6xJ^bl7z@!k&ZUjhR3u$t~YNuXhEK~n!?Jy6CI!& z3~Zr&Z6&R*hRCFQdR-fuL6me_P48=nQozX1zi&)$qhba>L3FSkUjDxSHkgME_s82ef4vziuJ>f?20npyV)lmlX6zC)b*3va8noWJ? z7wWbr%F*kr>q*@~0*UaI256IH%X<@yo?R`i5MXzc$>YDeCjcCPC)+P$TNNQXtD%wyiXek)SCwpa$|lB}4w>i5NmDIF~m;&h_z9 z(W&|1{5Oo$I&a`n-MMhVyVo}eyBC|@LIaw^R$9G`)^xs{;h2;D!jz!5hSRMIkzM5; z$W7VjpcAJSNx?M_Y*t4?*97NRGNzkeHv}gVbfX-nnR=H9xa_hbiURIMHvzW++c=+f zIwafV+=Pohe@yQ#~*%Mt!6Xom-n_~8xO<$P3WmT?@Q7i+(=WuuQ59>-)h5O?ZI13q> z$Ca8L<~Dg|$#sDtoyZ0i?sdOyZyB=XktYYt^O6Q=fMt6@fiMQ;P|;pAR{u7%dQ-1l zZw@+9bVW%CcIl30blv_XayjnH^@lg=^Phwj)gHxzGl|~{%DHLqIpw&ESRZO~`{+AM zk#N1XZnbzQM7Qfrn(-!org&bT)depCvZlf@be2Ft+-)m=O62U(o%c**sf@b0yJ0N6 zb(5RW3YoULx+$3x6;h&OxmLJ8v$wN0W;|diFh(&|z-?Ffo)`FwBcE;}?h73)b8|$m zTo*3)^0C*@SnchUe7xi=D4?>QvfeTHLh_AM&a+$7j0@d4Z{Ho69h^SGzI^?VBHN}$ zKxs~!xO4tT_`O?oIeWOU{OEjYV)IJCYZfz3xUD>CBIr$8M4kdXJ^D(g3J&ZXJ83|w z@$S0Nm;@2V^bwMAe$!PTf3(@@C?Peyw*s~ZkCR@;B;4Qvna0zI&=Auj&$g zWv`i7Ni?Q#HP(4mR?Q)z3%H8sGeQga2_^wSSu~(6paPaT`P{3;m0(6|nNchJJ~Up| zVQ-@QA~-arxh!bKi{H7w@3lV?HC9w{m-S_g%%_d($#y+8g@Bk1wHk6P(Gu=vUH!4m@90 zd0!NdJ#TKko2WCy)Qr1%l5g6kIYozuJmle7^rkhwIS-Oblx^>_)OHrF_dnx7@_(%) zikc==h2_UXTawkX1{2q;Vyz&%gX`6qGUZM5OYEdNTqxV4Tu8VL?#%f1%#T=)8UG{0 z$*!2SQZ7jPxvsKR(q$CE@9T%0nZ#rV-NKRT;C!ZDZ`0|U2Rb52S1?tBfw0Y_)J^DW zTcK5E0>*rtN8}Y(RTLx#1-ZGGfPO`24W{5H5nJK6TCJ&{Izp5dZBRtYORNhZY> zlk_eRu|oLgPkX=MEib9?e$jPlf6lrM!N`H6r<)i(XPz-U(U7zue_h@?KXJCBfjCEX z6MR0wo>?j`?%5XH(9Oy>9TL;|sLKUZs>1TXJXI?_0=;pm(NC9)hv5U#=Fzc(m7yd2 z&LZK1mPnruOjz5{+6GLf^LZAoy>WQ$O)prF8N+qO(tsW5=*#u*UiW2Wci3>V`9B-yDtg=ILQ0Nz8SD#) z_re*iB<2f$*fbiH7Ri#o=a(g00#8k?DDlJT#^a>;GwcoyMLy4Ith&?PwT}Ut6?K^g z7&MXl!%0KNAx>@8y;;gVZ{BJj%@xq@Z=JH~l*^%jFES-6Yg=ZUMnBmUA>;pwr+Zo3 z3BJP_oaS>p6O$&fP(1<_940SK9L3~%1Z}^UzbQFiTC%L`uSf%0a4nQ$7cE5(f5~Xh z*m#d}w(R{D;ZWGg8c$^>?~g1OdfkDI6fFwt3+R&j?0iJKe_gkUFCO1AZ+e+oMLAIT z^(lq;>&~;sc8Esteko3up$_I!`%H2VAB0tZzNOK@T;hD|h6{;r;=_7?_i}JHp>VpY zWN;cH>dmD%hqU4w^S7FI$xkFb(s35cu1-itrgi+ZE z#EBRs!Pi%&kzoQ-6+ImPK5Mq z>KBI8rhRs7;??u1<;@E&xaENK<)oD33|Y!&3(`wYJbZR1^&HYkXuWo8T>ItJR%(u&L(kK-ke;WAOKHvLSh*oO{K!DBPEvJ&XnB^NRZ9;E zQ8&EGmu$-3!(%O;>*;k6^0JgW2{h$Pm&{MpsbMPwr~ta4Y4b1p7t zD!CIipd-H4Q*>>WwOe9Jca@LVK0rhF!EFU}54?Mf8rp|*gH3}kd8Qoe4)^>F#3AwY zQ{P61C5y-Xj(+o9m^6EjwK-F8 zn_)?*L$G*svUZSiK0I;Ova`4oRsN2le}Is(3L~%LlY2Ht*~(`>W5rQAHjSC@t1I2t zxEQ$)9cdi=MleICbtGNxQ_3%z6sUYFvt-5Vzq#CQJ7!FH-|?TGUX(tXn4Wg%pWmuL9Ew*f=+(PXW6N+{A;`nS!V1^?)z@6UA@8_8l1- zJA-uaqI48JwQAU4PHC~WQfGZVVh^zGe=@FgyK3G|0Ie3!R7KFD2y&TX)%T25O4=Q{ zj2NHXwcAv@4L4qj@~JI6jVG9BF5Y#p~w45o>ZCCB&w| zq{-OLX;@m<-F9abYf15^MDIdmpOtw-L+YDy%P#ZT@PK+6P=8v{oV|prDg6+GC`D!# zUSh5w-PqgULa}OFQ=$Qr;JQWZh@W+6`$V_o6e7He@VdGI*zP%-O>oAn88;+#z{v9% z(*Y3-{@&Wzo08s_8X9WYxzyfvbre^<-{IDW@tRu$Hv)Wdk1Du6SGXY$_=z2lKjW)4b>I?d|vWLt=PBk++h=^PhCi1c!Zwwv-d}X8F>o%%!S{ z$vSc424+12j;`eb`F(+Xv#+6AvtZxR_|!@R-p`%T+)wHhKO>eObYNEbEe3_rkGQ0n zOKba99`bfNw$<~n@3x&`R~CtHyQto6RHRlKS3rAeb6=rqH0tY_{qycq_2JV7Aw>i5;L@iOqi(B`0TMhGv(1&Tw}AY$W`JWUNX^H zUo^NfG55fQFj<|FTbZ9D)RFP^YYQ7ZE5B3m3eRL~eE=3k;a}@ayo_Lyv}{l+U4QK0 zc?q5=H;?)x;qR775fY&RTHX{-{o3^7#a5-1xHf(*d6$)EyU@1d+n&Y1bPZybwQxu#t7BK+*#>X<#fZ)K%Hb*@up1IBS(xRx$_d(KRh zQVtS%RmD2*UW2z0^b0O!9UN%jc2&gJ8d7BBIl^?MN1Qntt6(%aj}*sL5x&b)*jq@j zl+`EAI=+!s+xq#Y0-G4#E7x~7eVs>5VZp@-4M@&i(H6PfbSVzwTBSVg=VN(D}%Ve*^Od(mIU3V ztl?6|sanf=zv_|}Tq-rx_&s9YF>TuYbXxhKS8>G-XC9IcPHUF3AG>B=e)3xN+wQl= ziyndPpmBq3h6a?uK3&U=p{C#OgtaYXrwhzGWLniFXJOH4<5EQgOssvMf|0wjU~g#^ zs{(I*P)DS7n2!qYUHGTsXliI2h0AQRdKTX_PjxRceI|m5JG8E-rp<;@-Lbu}XQc`< z7@Z6wk%GTyb$-cKfLmP_&ZuvkdoDFrRb17DFeP;IPEuY>^KD8CW2B)qT@e#z){eY9 z!ZL!zR?%j9scCP;Jms%g^3Scr_0oX1R^Eg4`+ADP;fCdv=dVO?aI6r`qjz)oT0Yc*1D#o?q2CkcLn3A zx6Xk**zQ@+sP5kC_~|roBR%oeFA5oJp(M~_GP9ai@ftqu+}l!Ik{?y!>5`umo4>6L z@z4{eWy^hVzj7|P6xr{qfJiKg@Gt2dhqEZ|c+`2NK3Dof>bnTruja=tNM5~!0{5>a zUR^FEcAHGKtuniz^gd$Ei3H>A_te9IgEusbVvV$Px=x{ z0IR~X*NPlIN&{r?-o+Y^z3B>4=f1MkwkI@yHt9u4ISpu^&r*b_pL{jmwsu1`s{*3H zD&pq-dc72xQz7bIo%H1m9^5_Ov547-J+!|2o~-$rY>)LB9&MiZ%bQhF`41^4OC|!M zDcn-B-skUy#wVDhWlF7+Ov}O?eWRTbcjlXtIMpO-~LUaRHyb9VsWq)}+5Wj|l>PmbdP}vk2cZz6l0|JH8l-CSUr?6S|oU*M; zEUz|?bdh4fC4YekNjGtRqYnKF3Y9rr8nsdZIbvUQyEsb5|G}O?7i5%DUm{`QQqc*s zu(=@QyP4oOvChJU>Nw3t^G0t{%@b18y!V^jLNoXj71Kd=JNSBKIIwN{b5)sn$Ef8IDMtZzY*pkn|QD39a?7C_#F!3C2q~weLS2Ffi5BR2R({dpoZD zoP9Fa^IQp%!rz9PUxB@(x~D!FGuYI9xF+`;YB-Kl^OmJX6wP4!yj(JIJyp<61H)d@ zGisJAMr88l!R}AY@K5K9%h)l~Ma}Exvzu6OAT~P-#D$w?7m%Q>GQ?v38&%D&4jB~_ zNQx&Rod#?-Tef+zt3+%1GJ;q;Yj&;c{&x+R`s`3w%AqJqYA6<#I#}y0LPfXak`+j1 zlS&c|6Tap#-9=X6Pfo8&Q<^uGwnb4RItm6nlbX;gRXn(WLcN?l)8e}wOxEn=@5$ej zm1VfFJ_YVZtK$bd`=(u1MG2%`uUBR$JS$ep2}x!ck(&K&tj+=ccaiY;!WjxHk1csD zAPK#}--c6xw`fcZd9ui?>1S~j1sxv@v1~nL`4KghE0#VB{nCNQa$1lHWWnY-ALREk z=01_zOdyanIp4a|Puw}sdXJ}Wx0}V3nF%tNq#{zVf_rI_ zSu0j>c)h#P;!&-qg!DIcz5F1(bkD36XioI`AnzIMftzr#$H%0KAAe=%zgSqK6SC;9FDxhBVwv`kTSKr$p+da&1 zTgZ3sEJ0hrnDM)rsm#LC+=o1Dc6Cx3>%-DWl3{1kIQX{@Z=4Kye3El6-b@?9q)g7# zQ0h=De&FaUih)QB44C$1Ws*gp&y1yn8=8(6BV_jO73fuqOsH@~m*G>K<4HQu1%=Gg zrnF!r0;_wo3-4@Uu9m3|u`h1zgK8VSIc!!;Fl(VmkS*PU(vH$V0nm8I#jAi1upqS}DSBML2S{3+=J)-hB< zKMgn^IHelguN-3Ovi(~e{Htr`Z1$!|Nx&`qbqqch{25C94FUXt_gu37SV%)(@0cXy zcD^aWBzrejy!Z%Chg7eDTY#;;&o&-~JlY93H{;$)n9%@E#f{Rn)$+Un{Ndu^dy0o6 zC(D|Wy6KtGYNd_N3Tzyj;t}!?qadmB0VkKl6UDDnI$7^psTs3=*3qgfDXnLEy zFWMZKHXi$=i|RGEY*0(5@NQzm;aT7wVLa`^MlJ)bW4^j@&+WNbUeCJHiu%@p&GlM* z+@_=_p~fu$DA%QLFA!#363JT|cw=(g1Z+31a=l|_nK-(7fQ>g51HfJ8Qq)k^h^bSJnJT^lMpzHomjYL?;mgfA<<@Zb!7rejnIH6kj(u#+A zqKgQNghl6uR;^i!u9blBTp1R!8F#|uDi3$}r+%;4@XIMlNDWNqx^cMO3Up0eifUaw%nM^-yuaixJq9RuS<6VROFI zLD<-*q*XXIlf0fXS>UkzY5dL;hcO=9fCLXO_!mc74{i4JqrdD$WW*%_#dF%a+vv6? z0Kk5P!4hENIj(gCv`?X%sBGbmZ{hYfHIuNf8mf10clFB2-Clcn3#Yt=>jLk4!HaIG z0RXJ7?oKEVJx>o;PY*CjH-`cAF&;+O&}f$}3T>1J0)g^G(h>Cd))VO<06y8b@)|k$ z&?(M2dC>FF(LZ=1+%MZA5yl$k#vtfNVLvkHyQ9(eMhFj2SG{Z3;UIFm<55S2kZK%? zo*CHX`Wp|Xwlbb`@j(5QVfQspCl?PV)D{yEzjKRPUDrbANBvdkEEvVW+h29u_qRIg zxq3LEQ5X<^kWQ)Y>Vf(tHlXfu&HZ=6&;g_SJE885QvWM~^7t!p>6#1XH|DZ~hu80f z2GZsH?*yp1zgVAxJ3IWW`VYMThFa&;L1{pfBmgk96A-XNdtN(({zgx31ub{fzroJA z{5#z_cROPfl!vB}p$ok=e}{7}b^`wiZisR5*n;c(xSTQkO}@(u0rx<=pSSg}rPp9f zNPP!=%&&exkJE|4CtYmd62krmn|~?R7_@TwPsJL+U4Fpz-Qi~}=p44fUbs8j)yxqA zHZIsFolp+H)VGI@Fa%{fhxYJ5BVEuaho4z?|H9Bk_#2$<7u?Xv!SU}1)?Wxvw%_#h z(ZMwPLxvyLOW=U|Va>$2HF8dD;r9G26nsE${v2;?TQK^FY81)*ZYt zZ1qymCX60-{TvoxhuxB3bqjg{kg&H0F)rX8w95hm!%s+ZY}{{%^cLI_y#Jz++k()0 z{!hpj&kZmQ0ImQ)`;UQXf{y-=DBAxW+?Fortm#t|!&ZtuMS*r~^xIZik{$yX8Gc~t za?>TJ_cf+1{EjWi&r!^H1|$WqpLyxlcz@@`O;0kJfwv!Zrze4J;C#Y714cLi4ZswD z0h)j;AP-1_u}gpfAO*(gaZ^AVeEyoE=o$YCKZhqBK<7l~_|Nb+g5QXrBGc0-PZ#=( zNUu8cHMA$n4)ZVL9_}Fp;8%op?&^uWwAK8qdi^!0b)kGJ2^Q0o^>^h=-lzy8GSMXJi zLHvEj+vNgIjsFJSeQj$h{Wmx(*u;+iO1?E7h3N$WyTOYQy08`hF^&&x#pzx6$GD|a z07tKaH~Qds4qo`HV;lO%HuR5e z=pWnAKenNNY(xLphW@b){bL*Y$2RnjZRj7{&_A}Je{4hl*oOYG4gF&q`o}i(k8S85 z+t5F@p?_>c|Ja89u?_uW8~VpK^p9<5&z4QbQP8>q08GFObb|&OWCCXaI{*z_0}y}! zpbt2LaS!mqY{gtbiv9l$g#e%q7=cDobmNV!5`NfIv258@fo0IXvqd_3c(^J{NT4v{ zwsenX;&3!l!pGKCLP}gx0#JqexZ1*<5gr295TN}KL~y5ra!gNeRfyi%ZGM$;(TL3P?*zNlQqA|K-J`WR>OQm8BH~ zeg;9XGkv;Hfgpl|L4lJgDcyk-I2DS%AJt54hV_st_TM~f!}pk-ZHP!McW}D zf---HYpbh+rpNY9E+FE(6UNoW)>l9uqyWWMR(D5$=5V0ZEQq7K^AnSl6O)!RmXcAH zQ&5(Z5s_2`o%;PC1vxv}`~EvA-Sgi+=)k^j2b$sjmz4DJv!(kBP8iT^*Y{@+H$u4m zjJY@oZ1pc?TR7eN86t?W^+MPQ{scPxC+#c#ciR8K&>OVY{byzWUV|Sr7__~Ix2-$k ztOM9Behpv!U!CxuZV-RT1b4JWIUvAULqbsE|9U0<+b;C~Y9%D-lf;ikk@(m4+QR*9 zLILZ%1p;R&di3}7sP=0b`}6#xfj=7fqk%sf_@jY88uGAtu{D3t8E$dh-9--~k>Hp>tG6yZUY&nh-b(Y6&5rje?7B?LZX( zfUff&r7jz6>5_r#^Ixz)0suhp;Nh!^zhD>f0FV#n+*S4$Ojr>-!^8>zAIe;9-EFt{ z(N798f(OKarF8H#4tRua|5q@N6~&#+ngybG_v`dOH}Hcd*dI4%VGpf%RwjS6|#) zX$B@HCYEh1Y%DBn>}+go?Cf-h-0YxRZ!r9P?EaD30{#1K%OUqR6!Q!d1L(o}FNfTN zphNB#pqMOw_s0!v+s?$u3_3;s;gB1Y{qI=tfWhA!ax;RWfrl=bS-{#cGh#p&>KxmE z?Vv~Qvj)ujZ9$LR2c#pCSvY?<#QrYBb#398`|ZW!>as?UU%Y{1-pQRm8JSWbf6&;@ zqqcQu$BDq5yAB<`^F%}QWua-Ci7@xl@G{*gH^TGo(;tqx|0jOA6)%`O`rMCsRr;ZO zV&jyOwuO`LgV>C+k3Eyb)5;euulohZy)JL;og)2k;LWssJLpt=+YTls46fkxIz403 zotbZTEvL@7_%2RE<)UCpW{ehj1vVZ0N*q~It^1Bw$$$X&s`N#xw{PkzR}CF(+b`ZuZRbx3U*0L6jx$RXSfsUKQgZ}T-$W6+`+c2oPlabOf3k$0Y zogdYUl;&!SDJA{G1>#aI(^P{ls3bXwdY4#)bjs)ko?nkUZB8u~hXlGQR|y3U{-1Dn3xrbDejX&sgI$QJnkcQo$}eL=|> z;#Yu8hi0Fu%QXMOT8m+QHD#(Hw4m7Ql-s&?fNk}aVq#FcWk98iV6=Ru-OYn#cbHn= z2vZdox3va3ldj!v@^=BIEh0(7@42E%VhUdlqK1gkvq&V^XE@{Lr@ks_nolmmz_{-(6(BoK@BH3)m?7oSH z`w~0PSyQk2`n`WK0MksRei#}_dd?Jn$Yx)#p3+3C!nO*-0jIj@bt68>mlE+!y_cAt zM8=uMYaFFq1f{v)TRER%m75_umqD)I>9oGk@bKiF^64+V8c$#ri53t^hSxPBF4)`8 z_ylbBy-d8(lCZ5h>(+%=S^L5}E8s)hznunM-a^FhJUDU-^hTpb1H|$d85g+1pRK&D ze(uD6pQ9*X=Ej-I;}ZNap{;CQkc2 zFi%49*X1ulCSFRAK?k(r7!JSjr;gqa^*1{fe3Av_AJTxQ>7$K{q!GwYDwUm-5gyEO zfrD5#8m8JicU%@&@MLN9}*8bJeP6ZNOs!pOk5wSh!m{O zaApXnP&{2Ks~YAns|oAv(gz3p;{eUDQI{lx68*OkBGy(r))vub@bF-+2ra6+!V*R6 zRMD)w%(pJkvti8_HDQh8ZMZL&eHo8AF&Cxh8@&nXJ{_PQr6z32JLyCNp5>9t&p?p& zACE!vx(vEjzwa;VX~li92(Wsw#65aTjd4_J2=eKT4Sk+TirS0B%xd=<7JZ1@@k)*CvMzN0 zlmvM^X!NAu<7wB7S&e6b>l&enLzQRG!HCVU#yi*YuirkSa(|2}1)rL;5x9#cHs>}j z)Q0vyOz5$VX`5JCuQi;rIXZZ!j0Pm#46xFCX{D|DIG{1cUO&L0O|}L^Dy}~l0Fi;d zK=44;1a7D_HFA8DHB_%m)nMKvi5jqUu$jkZKqzdVSTpznIJjg8*tV`}9-B8mz>ZH^ zXt-znX-MNlJT>6#=*vN|gZggWr0Y7sY!nlReq*JD8rVmEX=shT9T1akq_ju3MJ0RB+)gv+F{9O`(Uv$+TNiEog zA2_*gX7B(y`o&CJm z9oJm1N*>E|RKChmpmTEJkmj@Xl!jd(xDF@97g6`z=}h8~#m>$9Obl&_G$8+mha_0W zy#U1Loh7XvH`{aT5ztJIbO;T&_G|(i3{Ylr+p$x5EesIh$8C!z*+;{1-Qm1U5@hnh z4c%*qyR+IW|!L z5$7y*62lwkX1Ox4hy4@r$&slp+;S}8*+mO8qhiA`>lGoV&F8C6$)pryL;MiCA;7Bz8n@A@tye zt+H#il2H)VJ!Lu4pp^79C^pxwT(J6~q|hT(U1q{%X!H)H4;uYc4AtN2D8A!HLylG7 ztf}XY7x)?G{ps0X<#yYTQ{7pYO)OsGl$?(`Q)xi@H{gTM*^{SEIa9IJ>sQ=yi;2Z& zy4}hVgt?k;cNf|HOeDs0$DHSG4Cn6e=jnmomE1UbLwzs^{Uz!11BR1dET_@BxmRo# z7+?qP%8>`i@6hu%26CX+c_y`{g!n(*U9=k~_biv%Js`Jae>@iYPO){#-u~os6Xusm z4B1njham3;K0=$aP(${-&2WxxSlFQ ztZiZr_sqTC^y#^C+1-HQ@H+?JLnfR+<uOU zb%pnv{hy3LPu6!P->Iq(-dUYLrCC`agg*uP@8cel)GFgUYDAeS@-9uNh-)Ntu?HS- zi#{}ZX19Ce4TgyO>8-9C26K9co$oB;{EuZ7Zrt)ppKf>;?!Ndm^HBKnWBizs@GCc@ z`opAO2k%{S^-03?u>&@Ol})UujK-wTI8#-IBM9|4{-RwsmBEpt2_`iTGM+v8_Q9fe z?#1ulcEyX`%4J}blzlD`PY-Emi6LV9%%8lPHZUlbO%&u|F!4F9 zc_8WjX~28EKKgz};b4NGp|GAOFJc#XO@nD-#6=J2mf!uX%~mO@*Hcn_w&viQ@CSEU>SD3n2!&kV+Aqq`r^xMucuyo$=S@1F_wvhK z<9SCuK>XZ3Sn=&Y8R7`OLZ9NE`i0gydD*z+S5@y)FWbNExe9ebVlPV>=Uay>Jr9la zK!14863L~-v7)KVx(_kQ%;(M1pYDJFk4_L|+JuI}*3`ERCX7xGC|tQoj9yxs>vT** z88&Q7&K}KKz4{{mgVyZ!3`!B`Df}>FA-pMevbV1KT~#|x_f*cW-;zKd-2Yr{=R%ho#=N6xfW&hra*f9e*UG3~X>NO>m={akE6CEm zn2@79HDGym-5*~f&U`jDSGz?_8nZq< zVSRR7Wg?d|#LqG{Yq|GL0u`$J@_9OJpu?Zz@y(PbX0w(xg-G1Epi9p4Kr-$K_YEWI z2Cf2xWLfJ8uZgtp-X$37W+_Kv&4bT3Ma`Z4?+jv=C>4k1z@Nu$dAgiDs$XxpJ_5u~-3wSPH zegJ-LfDU81uhRBTznM5p^gNtGEKp~m_L>rwZTKX^_T^Fi1Fo=>oIRkM_d&n&O+Jfv zQ<=$Ba?!nEut2G?{eCM6&p>QLBo62ch7O-B2Zyw!Z73rImh_hBFnb}t`*dK1xrCe znN;ak#m=Xs#?{)P?Ws**ZUdrb$P~Zg1o=ilVa&!YrxVds4F8fPgT;->Q~)(!R$puJ_T@|ob*^6Bee0!r5*(P`FC>IL$Zx~ z+vE^y1P$P52p=r0pa$WVR9+LCFWb(*s7@d#&Jgt9Jw%SkW{J5wMnc52 z7PBIAZt~4z!$ZEDFZ1!^P@K?#MH+CR7Pe6*L2e5Q|Bx2NPHZN86b#^(s@DonJxOj0 ze7JsKftZCOZm^8p_E;9ZbYq+0Jm@q!{Jwv%uy-xr7V~`6PdTnO*z*^xTHVwmM>Ygo*ZFAq zoDC;#G>??>^JTd5ytTLzu}(5S8!=&^UX=_^Scl0m===<8ZqL-vW{Oem)STwPv=*6+ zUUCW*YL_?^mNIn^wyMW(<~}=E1TH~_VUg3N71g%0wip^<6)!-LSIS{yXV_0RiT<7h z4EUX}n+;v$j=ri-AV!FsYX9xc)cFnZcy~SWdD{$d0Bs9fH1}+>U1FmpmZN$uH@nWY< zpo^+lEaAFO%3wZpe8lEVhIHRlzf+#>>2tV|xxFU`)>48Y)6w+0;yx@Dc9t@9tr&Gt zFMrQi-#!$~ha(aXMuc+}7IbWwhBoWqYS(M|4zIJv`FtPjq8y0-@Jxq?4Kq$U)<)GE zxu>*_&8*{F%?E{RRK5S$y|it${!Zv^rzh9RpI5+Ty?1Y=!C88Bk1aiWp-z&q%srhd zTeF6pcI#pZiu}mzW&^IE^@KmS6ctD2ie3#^D)*B*Nq&6dIlpSs=$mz+x*)%Y_~j*b z(O40#$Q(b9p38}qnFO3^4DM9?#~bFt;KwVpJec9S{MJJ%Y--Asu`5E_(R2i!O!iji zX?Q^loXo$Mbm!^E06mGv8~OTZ;zo76bp1k?D`rm+Uv<+QCXMMxml>e zEHVnhmH06(ntrh3HYzH}8|tIsHvRuKewSL9>fr1+0GnNVZ{ zc|7s?yGKN;&u)=zaec-c)OzU09(_;q0dTp0??uW(s^Ric9DhH^az^;|e$42}5fV;c}Z$?(8$*2SI(b9PH*{O*N<5apU5ZvtE;K$Wc96s~3qH`-gTz zn$z=Y$qCU_{Lkw59|z~9?&T{Vir1>umzlK5W7C*ngUNs_T;!YeJn|a!L=qJv)VzzV z_eiyNiPXb1F9j#ZM^@n=p~ko`uz;(LK6OOjT<$f}Fn`D1cPcU`{iy!jAED!-cxekB z>e;!{lm?hAa-cG@ zgw*A^CF2U?*ZKp(aKe+?N`s*u7a$~3;XD6hVXsv*k9&@fnT?x1$5$_P z-g&6Z;cCc!}S*-al4>T0`a5B0I#e}*IuotZTYv86U|?-RGkDy@Q;K1*qy-nvaz4M z@c5+#5pnhychh!}@0B#*9!HOw6V;FfKN6vkfK!@H$T9u&>3VZVoO8gj4YV3l&l!v; z{s{$aU<2|;^2|LB?&i@8L#W{6#j?3ZdS>WE9pY)B*lYe5e94d2p)vdk!fE|e0Y>`M zhC*?D394sT*}(nw@ml;WY*YZ6&xRld67hCw+00d=tRAT3@uD26$}|3tkLEXx$mzK5 zhvnpY^7jXfAII<~Np>q?R+{NmJ8HqM!bVBH5(whH4s$} zO|PXd-_^iN;$^EpE)$;atGW{fIxvrPV3;9eCzL-5L&w<1oM4xz*NBb+(~~h?V862( zCLY1gTrRe*6N&#k=u;jc4t8NFa=CrT%)V*$PjEKoE z1PGo(dV_hk% z7vNO7to4LBi3DFp4(VR(K+T@3f!6K!Kt`tDyEL&-8?$M^cH@ovZXL3<@1YT#{OYb% zyL+7z=oN-5;kRx@bl9mY#2v*n;pOCPutbY1Oe=i<1LZ&(zgRpBEDoU!@L>D}@v`(EY8Ujkmfzx^ z&Yp3R0Y7HksHe@Q#;|uM#mn9HsLOxk@3;Ob^OT3ZV*dcI*pCPKtKwzuA2nSzKPT%q zmijfGyXOfnFC|zYM^yo&V?|ntb|=K;xW*}(q#T(5v-hUac~i>oufLI|xbvj?%1mG| zM>HplfK-A@kxF;2T5w~!rUyL0v~Hi|k1T5X~gQpkBP)*eD0F ztsAv){!#~`{%&39Z6nCuQrB+v9Tvk%^M%#km{?v$msX_4RPiB&d`7@ly|S+cH$XBv znZ#X&2Iun0S))2{nM)}uPuA^$*wBho_2qnUj?~YKEVl$H{bTaZw3kWq6rMbFHbd4@uM%>Lb62`@9pK|PA83RO=ooRvtY-G_uNshfC|{0h4h&{Ock!WP#HXwSlk z54{CwF{MNz0otVh0GP&=U0#EU`#lK74M)x}1a$(Sf)7eXU;9jFBlUeq1VJT|vac+&p>=O4V+c@%e- ziDPJHMR;Jiyp1N6q!mblZ%JFSwKv-@j*>;ima;K4@x510xUsr@KI$_C#6*cADpAm> zrxpjjM)^UFY+RU|8zmoCVnmK9za7Z`06nl$S%;GRoqOkvUM&Mnk_%u}q?+pOxLd-A zH+de1h^+u8xyeEtMuT2Shz--b&&xeh%Tv|7zj+$lTxiy&^5JG`lMO&tjDbfE47MF(;+Lp-Tk`(bP_zF45&7d+i_2Og z)hzDr;F46ikxd)XKZ>DhJDz|6+}8pQ&uF#$ zfb-m!5NUTBJdod9s@90Pj3t% z4T_dDKM(`yuUtx11MqZs>JQo_<{{SezDO1j}H=8`u6xTXJ-K~wTn{50pwM*yS zZR2CIAp26tc2x(%0U&QKOh_kS`{z{A{H6IRXK$x@_sp7Km#^he6H3wa*zQCMdo#Mc zuTG`dAZi{XG}(J^fYb$tVTZF0LA{nS=06~LXU)2NUT4;>H2rhS7fv99%{m$gWwe=% z6>sg7k;0?`!i8!%1*puOA8W%+d@Sdr_> zM^#Ezn-3G2G1EkoT$-hvfDo2HmAWjtr<*iQTUk>lmaQbXw)(tv7tX8zPG7PBKNo&o z>6MHE>9fSAhe#1cS%3|_2TijT$&V!8%HCO@&YIl%+rpE1vjeaiY*(|Zgbx$U*AnP^2QBWNTBR86NF| z;~?}KyALk;kIMGmYmVYwbMo_5Z>jp%iVmlv+_B;VNH=s1v99B8wFfsHliMRdqF*1! z>FVn>nj?(t`5#L1r~In#%_h-7>~on`@ZkSZ-NT2rW#6N~>Sm;srbAWTGybq;?Er$~T@;vi!xn z(RAA=FLXf%`=PIVfS!Reba5PrzIt*!CZdSByfbHLWRb$BhCB*8~}7a@6>C9QLCz*H6QNsE+S0Zp#i4h*^Gf*#2~R z$Nq9&?^o4)`*rI{ZF>r7`fa~8wSgWo#3WUrWu-Z{COcH-W;_wXK#1s`D}L1eP<~uk zeo6T<+exywQL0@=E;Sp9QRKK~spL-dO7TI^0k-7j+}g59^LPB@XZ+-bq4{EM{Ey^V z2B-Ohslp|-w&Ttl2pjCrIM^2>bc~u);%{*yL6$5gdzZnMACP*#=2zA~HNQQzokLr= zf)RChZjMwSmH5REs6pMEV6du=!Lw7T*YFQd&DlaCB7^D=G=5f(AZfOm4b)baO&yBf zTv}No($+R`JpkQWLIq@%tG!C?Ox90128qANCQzNSf6H&lA25DtK;CJR;y)?*K2lAs zwUi&fo;BN;=e-+$jzY}cLV$ANDBzE%l2%!b&}N#C9964~y2nEPVL~{Nx^j{$GO=C!Of4uJ92w><)5G9{KC?tzjzwcQM0&`%Kq7_`>Tk) z&{ZyR68icLHr`A7=Mme&rQOd! z2YeEj2(pkbXTpD*{{Zuo*E2KdUPY0t?U*!X?w`Mv`f-b>LE_Zq{H0D}oW^{%4Tb_d z-!NR-HP8E;^Q@EHPdNc?V=W|(#PuNjPEU4k!yY)tsv->7eyRD-<)0_rDr&bDHnT(m zEwGTwFzv2XkdQv(SxV5=P>m10{NfeH%;QbkJ$=uO65wTt7U&@^a^DQK^xANo> z>vmtgT`YVy_ews|((Wtj+sZ{x)g)(y{>*$x%!p6x+B-$xfDCk^?B&VQI+le(YfhN3h-JLz#iWcaPF zq6+rcF`d=nkwq90^o$ZbTcR06o@+jZV;{hfgBb&617nqz;8N$&teC1LtZc;5M-XaH zZkZE7luOz?zxi9_YbX-$&PhDi4!oK>WJsezdlO2Uec6LN=IA*wjiCI``CH`6+et3` ziR;665UShWByz(k2XG_uUaiD$v5TG8r zf;!`}Laa*%0s_WUr$LE9DtscTDxg*I^~_yuqEN9)B^xr0FHK6Kv{ z+m=t-Kp1;|yjIa6lx~0qJ!m)ku~x*6m7p8#L(>#5t2bI7Zbb6s!jRoq3N6Z<#oZGmk;ts(e`fvGROxacwjc zOKUW5ZF38lriMUO(br<7PkcNzvoS8@BdCZ_kU_7uM6IWuRP?SjiwI<+#Me-xD|8^Z zs6HU&m_^7i$Z93^2mIt0=0}*kqxp%g`E$#ff@#`iuhqR9Xsw{&s_=&DP?AZ^okl|w zLBrEw6OGE=LH__Nzs`wHK46#+1%}$6@^3M`S$DZVmxpmiLHXC`iRF$K*X{^*RsQM$ z*S5))V$CBUEsU^04o_&g)_mD%cjo;GeC2SrUR|>{R)gx0lX|=r*dKz4#anU>dQ)oV z#Llh67^Ah0W#!&T{Lb^2nYEoa%kz1P_6YB%iYJvLftdra9Khj5<6fDGi%?9dzb*(z zdS(!LtIe}m>Kdirn{MEa$6A9)cX;CT_)jB8>$MW96sRS954L8Bv=I@tG7mIr9&6G( z^=(pi1?T8ITIpHA~B6w3H^i~Xwf|1=07TH8m6(W zN1)ra&Ab-z#FJhjE5VgQP*feqN{qJ@d(l1~i#)gHJE*+>0Co9&=6!Qm)HKQ96I(no zM+~q^@%q9!Ku!3Hq3J_HMn*E+gijx$$K!XNc_+@^V)JE}nI)6WdbN$#nPD~cga}eY zIEl|Bk;3gorB8m@kH%$Xx_HDZ%`Wn9o4nhv>H4pjHD5Dow$>V5gqJSjaaOot#u&cG z?YR}FY>qidi?&%Y#1I)h*O+|42j%^zpDi_iFkIf;u@l_Gbf(_MM1CeIlAMPws`RCH zu4PAf+l*p3$SjxhDRpfhL%7wnePhfPw;ENYjpJP1-4hO=w}4e+S`IFR?LodAphP18 z;*}Sl{$P3AP|_jtwf>K+Yj6!mO&3~-mhs%Qi!Y|_7}x+PN~qZ7IVD6k;DzyDM3?ht zUDmvt=7}_qF8QZlyVDJ&t<)1wa?!}kJY3Ht8v+UN%uPhhWnNB32u4BXGyY@i*B`sQ z*L7(~uFZQV-9b*i8AppQ_VbE8$eUj~`JEKOW36ius}jW_y_o#Z8lR^KoQo3(j%aDW zF?H~LIW^5$x8AqXjmOCU0H1u18D9=P6i=V^w6FV@)j#PzWB&jfW5!twaqd)aI_ho+ zk5tu38U z@m@|p<7{l6tKp8|qTX!2W-%M<;wf4ixrjecEO+ln#~$FaFEZZ4$eYWxUZF+g`~LvL zUst4lP;y9#J0}nd--FA#wj5W zB+@m0A~}2jpKRMzI8)ed)!^DRT5aE);L)ufOPv;NR9i$$k|~zmo`^}UYE<>jaG5zg zt;&=*VSY^VZ!PHdae2OLsBQx2THURzd~PH!9ka|*M4@kqif*L$&5#saUM@_R&R$Bg z)qK_E>3o@QYyKS8-5}HCvX$JjM!-sEui2N0H6O<+%sAz0CqTV1{{Sg;y$ACCM`yG`no>D_m5hI4PLc5IErh{E-3BIglP7h?OunWh~lSh||i(!MMqwN`fG zB0U4`#W^0mGZz^qWw$7(?cCOj)I8gN<||_^h2_S%wpDTi$vcvktG8CE#0=%5`cV+S>$Ipi~cDfu%| z^QFMk{IO`4Hw78klt|JrKbhK!E8BhgWzfQB$)_ZQQa>^2cb;0jZ6{i@`nB?aL~}+I zka{rMg-QLPwh2IuiirtwNzMFXsp+rKssQ_jLYcOgXzsBjRV2}92UGIvk`X~yNtlxu zj0UL`;wlfzvB!XhHiVY()Q}KtX+kOY*L-+chSySMU_cytgWP=>@Pw)jT0`*y2HWmO zTpR&gpHpXz)Hy6wfIsYg`rzSG`aAw|8s(t2@-^F0*}Ss?ZLlD5AICE_L()GT94#s4 z`M>m=MhYh)zU1`GP#o2JOPTNHj?NnMmC`g`RI54S2L9&_F*N#C@5x&K0GIr!Y2-ah z-K{*!cjka>?WA>$*en2ZNeQJ1r5dy+Gob?r(Qx>|k|Xo=uTF*KJDq%8#jUJYR+q8r zET-nD!1HcBV<%;9lsOGx*fG*`FPP2g1(u^@@U=SoW*82^N-L&P6pAlRjelQ;8dptl zTyh-&JA*@wA(Qz=O%1MML(9Ex4vpr}WQudZ|Z-gT(ybHLTk9t#PKy>sdYY?F4}QE}YK(;N~t) z6%lM&DTk^NiQB0?DtcvQvY$!+0M0(Q!RHqur~EZIU^;In`JBqpb1o*Qn0%!JQ4xpQ zpdK~(<}_TySi3~o{@rOs*o-Q@ulWPD0r39JDx}x!ehtR{7^>yImNu*oYeGeR{je(3 zy_=D4ZBfvJwko__$Xc!OF+FR9E1vDb?^pMyZ=NdHm7)}3Kt+6i5z`74%!U>CPUrFY z;;M1n6(OhYy4BHzTKB^~F~;+9MB)(t~POeznC= zHy5Htq<>?w^%x3J-&kRW{Rg`@Jsa4NBRROKmDk8#0EeLJHMQK?IG*ewf`c zkhi;N)A{34^A)F#_$cdOcxO2w}AUto* zTCSz2>$-*Jxid?t&vPu-l08Fu#g8?oQN-;|)XaRA3z>`#5lm8~kAbmSeDNH0A({JcH9+gpESr6SZr^W=9-=abXxp*nER?Gavx40jofK2SM~^ z5Oxbt!-=<4ZWNvvg z($_-p6FH?xsjlBF#Bz$H614pxncnK#G&=n{{WDGoAxK zh&73QHCe9pSe4=cY-*2RgnL&mjAbqD#GXh-#XfTLy`27B*R?$dQ;#O$EE&Jd1_BQ`Ig^7x4wNo^U|JsS)*W# zXN_uz9F^i5xvg@{KT}RqLf-jj`G2C?T5H}{mr~T5&lb8|x~8dh6p1FD6&sPXmB}pS zs0m`-ds8+Op?>EVjLGr3>e9*k*hdv}%AE)YrfTlpfDQe2Sx@f`Nc+DGRd~K}@V#hF zc>NUpSXEJOYtv)*(-lP@XBRS^og%67-vUO<&7eJ^XPA?EJHHtHKrQ z{*iZbkx3x_X7r5-{hma3%^z-MmOM5)z;ZNWibSz5%^%3ULt8q(pCG*#I)t|p%RRKH zR#c5xiUuU|;srSEwqQ#DoHp)vn6q%2NB;oMANg6nz2^NI>LT7*ywW2V$*_dnJ1_*- zZhn<_>;SK9)#HK3E+Nk8I>ICcyhVJ)b+73@OY=>Qq`I!7q3TzbaILDBmg3SPco%O4 zCu;3X^t~`L$M-yzrlTSrHKl%GYaU0_{KaYI#g@|RSiVJjsJB$(Us4sQHDXBlWVnsB zO9<~p{#D!F>6ad2ZA(SfwF}SDQ%36?Mv!`^lSy$}72b!(+XfJB*=4Ps3}GSJUvaS{ z^f`t_7c6pnm*lc7wZEHn#6|Tibb!2y)r50NNl5S<0j@;DiLP>@AFIEezn5BH<^`sW zW2oFq9+w@l`kTi_Qz=EGIPd$gIMd%ajS&)@gt^~WqJ}~Mr{{jH`Bi&i<_k|M=y92~ z#=p1vg$X~rSrwK|w+f(gW7%tiK97b}Iev#_&5JDs?&Dw5K3SY= z+!y`Qyn>o<#-gNFqyRIb_I4yf{@0f6A^^ANtNB;Wx86kh<7sBw$~O9pmy2~HFRyXT z@Jd9+yawMDHzzt_15U8WUG-V#TQ5EN=Tw$oGimos_N#3xY3#*gx3>jEe*+)e=~LFY z2t1Mqi#+`CwAE#@wwKIaS~^Y9^uk`pbLz*$3JB7uFJ+ z0LDsjuJr5lgE8XWSkvW;6e7xP&r`**RBVx~zX%__uE(+V#Z_XrNI^0X%)*=a zcw((e_I7b7xn+4zLQi3e(pY7NVp;%q>Z|)8cw(uvh}O|5iAiErV?s$Kq%>NA)YRmH zze;~7G4n$*J7x=%l>ht z;PND%bJo2NtqTk5NFrA|?bO%(QNNE&>T+{+191K2^WLxZYgx4ybo!N)A6u$`l|}9xj)^9 zW5btUNd+iLIn4H_Xh_Usk9GU}ucf;zaiK~-oZp-NUC}ge@IRN*IHS4q7M*Juh@nQd zv~(Z{ZyS=CAq6Z#XZOJffB=Th-L= zk^mQ}LsNLNQ%gseCZ>D3)WPzu8IOxEHf+Vp5?GwgB0Q`3xPZpt~*KEqg+9oEZqQm7KFU$UK{Fl7-txMn81TtS~l7cx# zrmZYXxOHB>q+~pQ?#RN_=H~`zb4Pfx1eUR||@u@p>*k!lFFTadzsjmiqO zMGTw%(aZR#FpR0;Px;4Zq*p*-03=k?;YL0TKhPt482BXN)*$F zFCN`ePbEVf+O1{XVvVF;`}7-oW-g%AT&#TGrQh?7UP`fT5>G$PZEba^++E9U43}so zSW**4D2xh*B=sQY6WdzpVwVJVcX~V`aU`Pu0Ou<_jph44D8HTsy`_(ublI(V&tm|$ zOXwz;M)1msL@uE7N2Pum4YtRzdqz``$1U%#+yv&Vbi{BMwnBt zo_Su~?=SO@k@Rgl$i83mzLPYERlUBvw7!XjBU28;kGH;KX2u}jk0~;u@s>)Rw)gLp zIR$cx4nM~fTIy5WZBbw2jV-;K^K;AkXO-?ewsc4m+}~(0-A)vmODS@t=z0>nZS%~z zd zj3iC3{L}J&mFHut-050fo{y>MzG1h~t!9Rh!*c|~h*^}-azX**J00?@+IXG$BOYl( z&5Qp4&QktZX`hxK;Y&RR)gv=mO&#UhHAU6TY^9j)M!=d=ZZynoL_~Qv=<>>UZ5wx`&#zSUkF9Q%NDS2-95zZ`m@U@GV+}W0Y$%{#y@; z-)Ym25_EbpfBDGIGx?YNQ+N4&9$Oz<* zKtnHv*|EivS~4U#UgPxsJkT=Nq`ja1a>N(>)YgNVhKj|j{{TkfpT{iKeQkPArSr>v=}WypPr|<0Kn`7p zqJCZZhs$~#w+GJpMB2TZplC&{z=CL{Q&nKcVyB@8r%{&Skb$z(mL^=DnWKJkX=hyX zXPG?Tr`+5RF=^K}P{C;`A%Ub-R4mUy ztr@-3=8kx|3Zpz^8XxjW{<)7C7#nZP9xa~j=P%6PE^0Q{8h@5_ySro(C-U+<(7*IBI)&o?ow+v)=JwLtOrKb`mN>miN+gbB5gQc% zp$pUN+M{{SX?*zx?~)6?@2e=}pTnA^&#_co$c^&Vqy=}1+`;sZ9|5!0^cD;lls zxL~N#N%>9ZT@%W)>&fP*?%pj&O1rYR7Q9IkP1Bbm2OawU7%}D%yJedZm2mV*ZT#ox zc_}=N940q?L+iJ9B0y3_jW|MqM)gxxVs`0H`CpIe;T`ObE0wbEE`DTax(}6aG`lS_ z;CYVz)_p#EzpRsKCA_-^lH2yAPuVosit@~ida(grS|_ICm9fvv56rDY&sP@H&FZba zrIoduR_1n+G%!c$nN&~;zuM?{)|JY#WixGt5s!3l=0BWtk1}aqRqc-&R=l=CM+? zr%)eg#H8$L{o!ASmrTXf041}2pKqx_KA9`E zK9)4^T*|0Rka2;@)$*LYLlus`m^%)n3hW8-r(eS{YMkKXB{ntdWD>_BLr#D0}-`L4*d!C$>JM>=E8MF?_cwl6Gu1ZW#R-OojM6gf`%Y9k;Ga9zz1dEHm#-es$#Bi^um|>f6W^w0%RI*P;KvMZiDTNQ z=cVn{^`5DvY5IPV^*FAA!Dfx=G}lSOS=15;az4#A2gfRwte#E7Oal~y^Gj4+Ej+t$ z$t|i`T3mUq>{uisuT8iz%^0|bikqC^G8%)GU@()Q32I-_~40HLs+B` zr>3Sz>+uqXjY2oy2aO_an7{;hQC>p)+SNRTae6eBwVKxb{YmZbZPsXuf>|5`y1Fr_ zAk(qK9L6OR#l#YAPxA*-)HK`8BK5?Hd8r*vX?TGovynhpj;ggJEjBou#OzrNKpRhd zx%s`SXdYX*@Cf0V8$2_nGxPVN&Wf4d_NV^_iXBg*}J%b79#HDO+S@TWjnk2LO z!mB-vj8+ivLCC`hpyf^K0o>(zGD{}KvM>;4n*Oim4>0*NNkOIvw9hKLk$-IqhUF_% z8C;S!G@$~O+~x8nKzTGnhBD{P1?NxB4>Epb!3LM+S)rV(DgOXRwn&<10*cZV-Pm^6 zcgp9el*bEnFo+vs+CP!C-E}Ue(d=isTQq5>D1?+jxhMK{_Q(uUJcDGi0nELd$(pX0 zuK6-A%k4_!=`)M}0ItD!k-M$uA;7~Y4Z}y(dr;Ribg|-z9Go3VB3IE5`Tcu+VPoa* z%iUf%9rPGwXz%9-)wx;7AOd$Ws2>QgUGf^(@K9x;+>-h7-qPag7r25p^dn%d;ZGGO z#Q5eIiI*oXQW0m9`8UiSNta0T2CJvZ6c;l`Et@)?GBPk=rkx3=LqkrPXN4%yYcq_t zeNUr)Z+>KXyHeD3jUz$PZa+r`ySuf0HWi{qekA6=Ie!WsXRyqeWRY=a5Dzl=k6gZM z{YvvxDk5vCX*J?n z1#6E%OOyv{l@&CvQUwMO3FN|45$2d{9!1u4Z6SQgs@t`#l&|T+Wd$BXLTajaB7<{> z!XQ~-GJ~_+f9ECvwzcv#uppK4xNF{1+`vz3x!374P$057NfyB2oZmF2Yemoa*i+C7U%T>lw|C{uQjK+CC`mxA37}!N-z;VfO%;r+SV$UD8`O~TC!k)R zA?=7{^bgBVE?;@CSRbOUMS-%3uWoN@SL(6EL1}?n8m`A}^2|`s2lFk5TJM;sJ;n>B!5ez- zmHdOFjV|BJ{{Wf#yJ*&Wk~8VaZveWMRYof8(Sp1bQ?FB*I5fgS%T7$BA4s+>`H|$W z@ICF4+ug^1rD~R|eWzVOXeGC1D^`sBQLrL~Pt0wVX2;>0XNxBoFIxWqoNsvJwezyc zy*#@!01sc@e+;`t%(Uuxhsx2)-kPv9MjubV-w+gt|qA~vfF@;(W zP0*9?(*n6=B-HL}TGRF7s{5+cQoRRmxT{Msq27z!4xdgCs)knkHK)IhD&aG&C}~ZP zg??D7qg*#GOw}M#r?>l96>82&pe2a$6hBTIS4$_V>Z&ThcyuQlRT&tN12sp2o}L?H zYM^BeKst`Y^egl|M6IqXMXD$#HRYYi*|^NqFbnD<(8A?UoLr~<{cYQz0f7I zwVgGa+hwHI)?@=ERjKh32OjmI8Iyu0XJ(AV0Y&MW#l5z_<&A4r{JisKuc+x32#>4j zn#(Ye;$!={k-0FC2BlZwZu^YO%@IbNY*L7j0rG47M!f-Vhs5T+&JSMvul$Acx8}vI z&avb@G+tR*NFlh8O%QP@USdB?uwZ!5)X;7QS2^&r5w?5f%?iuQUS71D^DgVmH`)c< z_bsJqx-{ihDWiTfyp;t|k`EQHi+9b2o&*an9%)&i#6LH@vo3>gr0Z7trN*h{{Z;a6OWwS-{{T4Q=k0&X z(0TeTF&E4CY)ljS@$DKKH0{Nzh@??}X{bo)m3WqEkrXZK_P>{&S{j@lPS6+J-#kstO!b_F5}izldVjJS!4r{)*s{{WEm-!I+ymd{uk zKD_G6zFJ$KuL&eS?!Q?LNL|fdpi_L=%=$_4aG*`qJ~I_0nL6%GGhZG~b8WmzK^Z!Kj$g`03|&659vLB zTa(Lrp;EV2I*L8C>S;n46=Z5|10gleLV9gxkeCSHap(4aE#5~oBre`P=TFZ|FFR;c z{z3l$&K>FZ7ptfwk?K1C0HpC-K?{%HI>|2{H1B6k3zMQ-^>=pioCY>Fo5$fKI8TedTw&gF%~2eElng3=Ns)eQr9&dN6Uy~(xtkT z+JY#3K1PO~2dMVU474b)D%s5qHlPwu zI1H)cBU4eB*t;W9l2wVmA^1AHE$#7`sbW~HZNkE^HaNIHyaSG1QtIkr!GHi>+A6`J1iWM|0(e(=DL0WxnAh ztnq;xMqsbnW4}s|49twdaHa?}$ThDyXnt!t@#Txr&jP3v%uF1>U-OvyWweT(cl@>U0(p`e6BIVk+(*x` zSy`0sdL9+dW`4?M8$x2cyq&1+81#7;<`S)OnPh_V%a`_%w6ZZ{ z3A(h8kP)9^CBFY zwQ?^%wYrYA{a6){=#vC2ioB|8)}2455W+#2J=!G%gddT~f`uQ_u^-(>RZiu1KS#DE zOG;l|XC%apy*Sso@SwrO5+b|n7Y3~KjwUIG&GK?H%l zHu;=*f;fBCeyG#0sIi`2B;&*vg?v_uvMb7@(CtIt=)uGnfT_!(L3HL$W0~vmR0?}z z#20|5x0lo@GMbI55LBPP9w59W3^dO~f|TGXRqs!Ko*p2M63Txst-inKJth}F==N_W zr#EV)q8Uiv+yRmjVV7vz^fJ-gNbw<*h+9${W;)uVRTRh_Kt$ zqlhT`Dx@g@cx3WJiX=5d>V9JRm-EwB)%>}oTiMKFv9{4P-L^iUjrmN<0pH_1i93^= ztm9HH-xx0p^B%V?=9@LGwZmL$8btD6!OgxVj#e%LmhV#3`C;7b-vPps>wlP|R*E~T zQeHcl1Gg%MR_MxpL{n|@al^VNFcBY>pYxD9=jCne*AHZx#*uPZwUm;SDD6OACn1y* zP1V$?{{STAr$`)c8sAahf6j3EuV2z;)4Z*v4GY#$6qoW#9M^nz0b@wlh+|rUNeVz^ zUR&g2rw}%GWf@!RKl#8<%k4>yq4}+?hf6ku>GlgQ?I*+3H0r%!MNnEM6J4W9c>RN%+_4yQn5hLISLZAxM zG##RB)1Rh|MU`pV&W+{ki+gQFmS>ipoGgtfkbfzlJWp^<0L^&ZIVLY!(LDEJm&V&v zfZS*j+sS2eCis~xW?k03U($Xr9cn}&;gJgbnLJDF@=(dN%8c~kR)MYr=0moB4&QF%qhtkE7a!+A7*tRg-_l`I)( zc4cN$@YH1kRg+60A=K^>6Z|KqSHa)mn~%!hJJ02*?W2O*S+o5vma&h5-tOJRcTn*= zr9&)=ptA903P>5*X!TLg8ywsnL}~6GRn>IcdoMS6KU9nNTIG~-TPZ@{={DfBL;!XM zyOFq{>N7i~I8xhp<$s+udHnUOK`KMRqqB;}I6*H@Ntjl?LivhYL<})xv^^QrO|_;{?M&H&TVk!jP4yr-0F2WP7*T5 zku-l>K`r6#d?CZ<8) zz#;-VBJ>&6M;L&oQ7KtZzb>xy{VU8meg3~?`a?~E>NlR)Hy4oubW(Px>N4Cl#2T{h z3+t8h$C7-{=7_Z)%xwyL6w>abmdfhV#l0)LKuJh0?Z)*Tq!k@&wroy27F-ID9+LQT zQ@FOj)ioQ-D8zQtUC%5Es#R4P$zCAz01-jkHInA+p~*%#-cv>Iv2PE2izn7TTK@o? zjXG|UG~3@SY1f+k8gpsZddQKMSfe1VSxstIwE;-_GdJ@aQ-Lim_J!2++l_bf_e1hE zorR2dHkY#B$*G-A+`OwGAR|IpGBK#Fd@>nkCdfp_Ru~SQ`8TfWw-M>uXVk8)Whc{$ zJJ>ln9YTWQr`S~cWnuvJXDrpsE%Sfmr=0wWr%mP$GU)PK>DKO|X@wj|$j}y{*mkZN z;xP-4Q5l*KGKi$W4m*-4eb4a9L8jtq_HgpY=AW9ppJC;_M$1N*MSD+9#_stbOW5Hp zQN~h3ZAt@5(>Ae>QtM7gf_bJ|&yhbgHQhGDM%GtBlk{rDwzq-dTeT3H#yw%VKKl)BMOWKbfY{YcK|Bzn$xbFo6@JrGV8^Fys~{3*k0c||yi4;( z$R2$1mXo4bdC(i31}B!+NH9(=BUg}u@v9BX6F{Jow!_0QGUFx4!8qCBTtDX-eB<>Y zsY-0^Jw;O-Gt5k#^;^^L8}>m3l@LLYlx`Ru(%sz+(u@uPM~c$jF}k}ur*zjwNGh-) zEgOi#$>-VkIi4S$e_(O!z3aZO>pIWZ*~l_G_Ty7&C(}>z1Cg5Mgmq=gPg=FR+q-jB z`wDEs7&0p7-W>J!8A04?@$>%TwVYZWEWPT*Q>@G)!g`cqgfV9 zFDJVG(Oll&ikLIy-NZG$bNldc?L<6YOM-anAjHfHc5%Y#twg6GwH8XuVZ2>BsteAg zMp?_9nbZ<0thamg9v!p8D|P-SC-B##OVs}M_hvbwJm}V@CSG`7KXl!7Fa;MtF#2KI z`~w&HHg_ru;4_!=WbV%+Z4r)?{@Wix%2bp-DIKg1orslUvl%ZOMbap zxbYnubO);Wl)0Gd22kGuL#~(euvi;yLhdeMhw`vR{j#$`LPpuPM0|kr)&`s;Uj*=c z2=33AxkyU8Yt^`Vxh^55!5)9f!WuQ#8*3vYT}}&7G9YsUAUEJo3x*CW=Meimmd(4_ z!bz?wzHGPZa1|w(QQssDNZp1Vbof~LauPFk)GCMu{P?^msk4{w4WiPSS9z@~^Fdru ze(!TwbcJKPE77O0g3`=LcFY<&$vLnYEjH8Yd2VC)V@p{vd5uv&!xGAo^rRzP4rrez z?T1ppj%ga_OLSq)VZ*Ik(IX?qp&t$c^ZSAh#ArY1!fJ>8a!U+E+}cz9nCyQFMJ@`X zV@1@h^r00nJ}oszcVt^=e-4OBfAy12?^E8APkxl1Oic+Qzrv+dN7h;=V_ZF0+#fov zX!Yen*onVX%jFBy{&wMY(5Pki$FbVElsl%9UVUFU>@$nBaL?RScN}W#&KHIG*ELo$ zF#tmoueOCaDzeqY=_UK7p~vymoRpP}Jl6z58Qok5FQ&!>Po}#gn(l(CPFAfrKd|^`;+a2s>E>Zd#0C9QB+`?r&ul;jW=`d9 z(9!xBfj3ycvRJ*| zM>0$~YInW1?7<9ZsRjlSyDmtsE#-40+~?=$QGYybWKEVQhLH9IcTW9K6u87a9`8H0 zN0~e)KUCY_=k!KQOJ_-n_1CsB{n;7Qmj)&0z6v0=m{1;GdhoBXFhlv6I&j%NK9CM7-Q5K0S31k79oB z?YJ*AZH&vur&Lb(yvs&zfo1^xq8SeFXNG0zKP5f&ZGlT{#6-Fjd%YwF=L2faV3sxWXRsPtY}+qkUE^Lt4o@P)0{f6F zgJDno7d&Vdf{v8e{v^;wbw{?w0s%WyFj`wyeA(bjWp{J{xGdq zjN}9qK04F8VPg9|6i+B*{S*;mOwP1^yi%bb4uLBFOpO#KqhgG~iK#aaZvhF6l(i4W zwm&6ZS_M%5+OstKy1*m``h!+;%&QVPPqz;tJ$by*(hvo+JRaAg*0xP#s>~~ZetCQ-leS{Wz!B> zb?`O|`fl81Lul0ZG{jR+VdNd~)Nprx=}n4k1~hE@=n8;!u(F(d+WR{v8B>fp%}aX* z59X;4HUD0J^y%?Ht86yC1UnWtkRMKTPzs+NJb4cS`L?#KZCnoO2EV#xx^R zIZV1f&8}Vi_?(ouUKWzN?eAStLM@&1E?V*D_Ri2Ynup`K_Sm}}PBG#oi;y8(eV~3V znm)+P{fn{VqOUbjW-*#r*I1(7ZRhA2XTACMXS zwfsE_e3rv7=gnJx<~a5uaKxKA`2Iqqz$U15!7>djLX}AG~>J$_x$y{cMdB)zHKJd>)g22l3-fBefqu| zTQ$}7O+ID8Qu`wg{g>IFmrZKEmQIDe3G?l6HI>U7u^(P}hpH})M!Fg8O}+DBQD9aR zmTab0sN=}p`S@hnjEvY^p84eWF@hg+I3I~h;!wxTtcZfTw;K!lMK)Gj-yf2+(zW;2 z%`tcSaW`nfXwFqs-_YyXpoJDv#}=WBCGXPoASl_=YHLfhkd4@xW>=TO>@J8vcvi*z z%us8!IMx#`L4}rVPgYeL*$03KJa+l#X^ih_Lhe(#R_1)DZLN3333V|8FU1$U0aed} zs8c>MypJ%k+XG>@q-sb{)7}x=cF--cuG^Cr&Y?L;h0on_IG-Ps!Cnlbc#Mj^nEQ3z z+soB;qnj)B(8TpqXg_%Oz(zN%I((gZP)s_aUi7bIPGEAMFNGG1C+;6To!CNSCy7Ak zI%s@}GxE6f*2c#e`4Cg)k(;Oan>diwEEvd`d%W)LWGXL9evTLXYa72sRo?RC9kUL{ zeik?{|9vxqagsLjug8F}j+f|Gi1+04+>xvjoD$K~uDcdJjqERPGU{S72G8`+lS^}R zON$nmsj>)HzDBnmvs}p|N>Nhsejk1A_!`3x++}4Z2ccK_Tg}#SV&|6T#hbRnfdP%6 z+|VV~)7QNBX8As>-K$TUDfa3CgV{j%&u;gZEM;%Lw757ZxPGsf?(4$#wQH$BkSiPpF_>E4#g^C(i z+?OhnE~-yLYINw2>j5giuP}!kM_5R2DJSSN%FMXm=NdmQG?EVJ7(q(STd`wW{>JA1 zw=;fhl`|_b&PH$Yz!S&Zyn(VQbeJ2z20u`0`E*$>}Gukxka};+qX*+t@=*( z#R}Mkp4t#a(A6ACpt;HdkFUaN=OBs zf|GOW0^#%Gb2aL65Pe!0g{+ZOFY#z(l<_`8R{r1as1LFxUCW-v_8a^z%@Fc&hY(a^ zj%ItNN}+<&&f)MOId(*zbZ@tE(tV#~e^aa=G_Y!pS=-B-truv|TG^#-+>xbdoDMX| ze(ZH*xXCCa+4LpH0k?I8oO1L2vNarQpC!ajECS}X9?#%*q>80(X0ZCl5OPn?QrGEN z)c=lpBP_`g`|-t-xR>lu5|+rtw=?LIdJuH}{wg2d?!{vUUbr%yxCFSmrFTxVnbJAR z_4Ncge$a9&&sZlFEVDF60W>GI z!@~O_xQ8wvTUQr}-P0toH6w5Q%tYNnjG6^an6AlSbsPa#`;Qu7;`H2Nr=j3Km{{&+ zRrXJn`+pqj&&8%i=B`wo3)U_O8$NMT^}h*OskbJGS@H6=AL$-|CQ$0@(Y3cRDN2@T zPNd-ABxb5p?FwdH_C<;`J+cPHEy_9}t1s)axtz;@{DGmoySU;Ck7Df*N8yW}f~SXT z8+t?u-+sjoOP>Lb^KZ>-5+!QcbVjd(GgVpn2Vbq1pqsOM*}fg5!sa87>9O-gp~#=6 zm!kdeR=m6C7A%;An#|h2dOaF7$7r#7+iD6PnBRI3;jxfI<1i7n@jMeKh+dbbI~0+eL>@cBiiqVOS&5EbL94(i*KcJ2p0J5$IuAw2()sl zqt`tVCz!epCp8d?^-8x{}MH(ZvUV`+!6CU_)DQ8QKfT!Xf>3QN$)T+ zytWLm#`~@(=eV2Bp(=yBv&r$o%mH>b^43vxgSAIq=%xGal0pG7L0jcxgWq~a+9q<# z(qHS)c7~trkno*c%i@+_OAH3K4P(Ev@17oSkakkbYdPFY+M%cCA_XS1BJ4r@Y8%}m z+h?Oam!pL!0`94+xyt;BDNH+E5+#b^cq;$ais9Er-s=9`z?)}cTMoWKPg}X3wd$mZ z-%S@)6*|9>3HSidnOLZr^Q)F_TcVbB>UA;G4_R*cd)Eq0Z}ejH_p-d(09IQ3bA3@& z%Lun~eUdWmeS4P1N)>IBQd3o(OK6pku2dZr4aB2u0AnS^q|D@(9X3x5c=fFoCbMx= zRd6n%#6Bh|z+BR6*Y=_rx}p<5Fq9r94m(aWfJ^h`@&qH|mt8Z%IqU3J?xSso7+=iN z20m`P$V_00Zch-pFhgyi2=x=1-zV|Bp(t9{xS5j`5_quHf&QE!ii!IuF%k&_h=vvx z@bl+hhR!_ammVr!2!WNZrDw2pdCl<9+d+UbCSCcWT4qtzdPcfAvLau^H2ab3Vi|8h z3t2XpgYyeX#y*Rt%J9}4suShM3)QvpSB;`fyJCs&#gOjx3o_F<$CDu;f|2n<3leM6 zE5V}w;6b4YV=-ueo9sDlu0a|JI~#jKFg3Hu3u2z@&(?HYN;=g$o&I!&A91QTdj3Ee z`+z9MLl&m;79>Dn6s#muG?f9Tfo%laefJm1mV@n(q^bvBXQ*9ISl+j@`~Va8$_-<) z-a2-<7uUBqUfEfw39rYa0P?iPSIa-1afZ&F(c%#UF1ph6+G#&cZQ>5g{Az!+ulZn% z?JSrgTpqlX=)1i<81inOe{{RNm7n3Q3&xl7l~~3y&N55^^3^k*AR~L(>(E43yfue(4}OP8@12#0p1)p`O4~>ID>9@96Jd7ga#@CngjPK)ld7$!W40RCN`*)kq&3N& z#ZG;zDu~B!@ac0qax4{}n*nKlajTW}fbETIq&fP-QPogBCSC2-ww6i91xs=6E?HQ!7BH zG`!HQ2?~20^S7Q`@gbT2x1x0_47FB0oJ$&^`_Rp=SY=p{t7Z2j*)_! zmdWN}^#&R|IC9~cTRV4$hpOq7URPSmxap#k4mCsryx2|!kft2ut)h9VWirg z26C?u{)T;O_Q6gc?2_dT4kM6rW7Ibw0$ zkK`W<;G_7IBrC+!wJ4r}%+1j8d(1TTOlAd6>%qy0mwJSAzH*59WcGAC-!FJdj zBB~V)?+bbHT;3BYlWbNh2izI*lqkidiWU^B9pk~kf*`)Z!k&CNv% zlzXzatNXK%+>QI&MorOhJ}=ru`TH+>!MEIfZ$KG;Bq%T-?SjhR%_ zKOOlGhr#hjDSDcLmxS}d3H@2Em#G5mJfeG;GJV_&wLU{m#p)*M@No`-XRQ__Aj=$? zFRVJ6ii}J1G~uj|j;z+Kkaj2*Q!S6eeg3o5JohwD)RxAiN@Ux#8+q(z?B+W%Qf}wH ziJ`+Iet`(vQ&N!6Qb^!rPW{}oeyz~#g9}$q3A_nQUQo8)DgapXA(jV)O9ndp+t3H~R!-fgoFia;&F|79N>2!5L zNKQ0({o;S{>%~D87!6FZ-ApjtdMwwFRvGZ8HPDe}PH2vXtd|m3{bXG8tKwB(HCNvF zri0~hXH-|4sQ{Jjms8^$XGT&J`#$vNm=xJNOe`w46OlH{FyAaS56)RE$BQlf`SlGf zR(^yW0EsgySY|iBy9)dk<3x^j)HAG04lc8+C`bq^x=dS<6Wj)tIHP>va+%Ty6a$~F z+aljOPwdB7eN9N+;Dv(0j#t4}Q7qZ^+@=*aeL65mNH=VxFh+uBzmD{L7^Gu-%U6 zo4Qp}vhlRc%zSCCYzXvr997cV1RQ8a6bJZ(H;jQomZyAt>ttB`+H7JtXKubf>UC#l z)ejr23lCki^%xwutt>T$1yZtq0B6hzkIY9ye{h_a5~J*_4Qr)eJRA80DphAF`G5evFFJ54rCX9omn4>H{$li zDud?rhkQ>^Yj~mO+@#*CBx&Dl0NgIy58WU3FPJ2|MTR&`<3lfUW}@N`EBg-w(KENP zM^oE1MxSgemN-ZV*W`pev64ytO%Di|W5L!OD`l#g2G$&FVD)}>1&mgX|8@vLrGe%014#s{r!rdQRCd3~qpWv@S2-^#Yz?XNsxq!O>(MYH z&eh`cewrwniaWifH(J((bFV;&a)M|z^R^A<)aSJ;%CWyctbGOy4Sjz0r55m0-H;q% z+RE!p^I8Uz);|S3jOXXVV3~=7h%}y=s+u~HCH{!)wACOo@%p;inzt478ARn#JEhSy zbd9=1Q)0WyhmW1Cs4$x=t(e-k$d*QgRix1AZ{Y!3b0v`U^`;!@?`mJ8!tl)czN_qG z@+Cc4;de$7m`vnI{Sz_S50Qc=Bl;aMQKlN8(4NgsK7T9B_$#-HW*8jTDxx1C_+!5` zQYU{^GKuOb zM4TCj7kOiL%YUwC*i7^D-<*No0r@Kwn=&~~U9&>Woa+~Q)H4>=9cRego_=XooF8BA z6s9Su0%wLVS;HvZRQTb`b(oNMiWLBNJwI&|FBwsuVPZd%f#4$&|gbT*SaIhHQR-Bcbtn= z=+m;b>R)N0x}8Q6;;$66$$}zlxsQ~B2iz$cvTZ|$Bc(tQSH_qQl<4Ly-}*w02kqzO zY_V#~nyQcTwSKuvME?Jj&K;9vtrcUjVMNSw@Zbz@y~02lHGRyNjVL2e4vmT)BTN2u z*P_mj#}EpsJBs<_5015zFR7OJw6|$U@GxVj-?fNcRXY(-W>8;$cKiv!ileTvdWAwq zMQSN%2SJW-@$5OAWaMO$uB`uB4ocEmzZGb9_6mK{%WQHKOW|t=zA`zq{K%tQ2oE^g zec{s}hYc^5!$hI$Bdd2JRCZ1}m1^byhe~(}y}l+a&srAfoYxAhoLgUNoMi(M3Oyjf zgh$u>i~r%w1H@5k3q0tU3YH14df<9Qb5|EJ-aOZ+n?~!z#DLh>?9T-S&XZo_WAR@M z!YL~r+(GP6#U7}ffJ-l`EOp^EA#EsLsuerWKUgoXQO296mWJIDrH6{lNznrHbFL*1 zY7y_z97xB7`_iJYjjCO1bP)1eb5j$edTR@_Yqo%*GePQ*0#Q)eiKR=g#AQ(abxA8f zHihs@FJ=yfH&rAO`UKi#l|aVh;dYVxt-{zcOnrFfRL5g|(AoS*PbA-n0U14G-)u1x z_`ZiUAzgIu;wQm>IHA9;eg$p|`GV5{5{`aMca-2Ec)1q*LP;H|hoERa&s1Ir4hW~t zL|puokHy0YaX)u_RkYmHx&SAVIc613JbWVn<3#@U)}Wyue}xRL~YO-2L=N zO>cXehSj)}AYMXr6G0=7|BK|WdZREelv1I$E|Ssc=sQ zLQ;~S75hCU1hRG^Y!HF4&Z7%q(@xZEO)bz@pD%Wqg*KNqfoMTbog;*%Xl5*3sW7IL zI^!D`<^;u`8}`Goih;>+L$^C&en78+d~=Rz=l<~T4>mE@62=$#0ot1Jx}~I1yC(qj z89E>wZQz0Sk^Sr;UUG5n)FYX_Wrvq)LLRgFp7>P5wgtwp06t`9J%9GZGY3tGvYIO~ zMUJ6^7q;9`jH%c2A)f7Obo#FbwR?#`#y8Joi@yC>qMA%rwA@=3TK2ZFa1aqX8(Y*ps;X(3R zy6aU~1O8p0fN37Ly@`CpZ`e#+V?*+oOP|-qZdp_JIeSBS-%dQuK7)WI*#}(%@8xFb z?Yg@M)dY8#7fx%LBUmHk@tH;g=Xlf183wlyel^ND-6FMd&VL4HC;5L>;y^ z%KUtECQ<4{@ra~dCE~^&r^9(}F!GUj*NXI+BRU*i2=~F#kbkb1Xm+hO+nrI;D0BI< zYJ6@oymx0~jr~L4fXHDrEQo8#3GjdKvJ5HQN2Sx-!iN4v)<2l=<+Ok_wRkuYy(Qyg z9)K01$-`Cd)XqnWQgtTY(atoU2q|&badvti21H=aM!|a$VeFIo`YSKr%Q?Kb%S>OZ zs!`Rl!@n|(Fob77q3>~GT2k zgp1}wi}&7wog*|bS4jBURe`9Csf8C}aNWs^&>Gr&s8z>HhxZaMKa~Inj}W6}_$dOVwWNue-^^ek%1;ABM5KS9T|*yUt#s>H>9oNBrgn|Mt?c!cHU|@Ql@phPo^6%Bndij3 zxL1tK2J$m11o0P%L}48YI=qx-8}v=N8y9YKoCHan07@<7WTI>w%JyyB_a?VOF6J2x~pb9 z)Y%r?EhfB^*OSU=^{L74#+Lgj8D7v{r9eL=_c_)MGLQP*h^_@zX*2+TFWZ`1s!$K5 z0u!w{YRc`Fxmi*MOP(HZh#AdI;so~ndPZgoV9Wl6d&VWBIkC=OE&GC@=L}6+x;?MLkk1r1xmQ^tM$L zWM_yHYpnw%Fb?3a?wi5b`V%aTnX5xzGd%a{R#M2%ck(Or_aBRwEh{) z)tT}IG;H)nTXnw3oQxO{4ROQ^r<0NQ{x9pX&#?tmYdlcGwzj{Lx^-Y>@<}V+ zoI&HTGD=~xD4u77XU$nc2_P$&wvhOsiapat_RefNmPHG9WgYRVvh)Dk3%sAR7;XLi z-!)>ot94CkvdgD?P8o$vhVAAd`6V8xY%#EFVIce3WUf=FY6vw888qL8w&UVgrYz0v ze7%zpZI{ESAkqR3S&$O~DXwAzr)16g!o|FR-%Aj`1(e&HaI)3oYwvRYq@73UZA~Y~ zGJkT7i{Cz$Thg1?6JA2(S78^x!c790s#|tqx3&S%BNa<3mkok$-_bVP-xAi@1HV;>}Ox;EK zN~r>Da!r33IYrsFkYf=v^?kb(L<}339=2b%kB*z~ooJ4t>?JMxBuh%3qFAPEXw1F( zksxYY6t!o1e3(KIUSIcMzjIn*oHR$1T3<6&`OorOP3qPjq1}GGf@*)@pQ6vUwT>fB zQ(O&xY-yn(5X{kD%^thnFhWNi&4unho|ar}t_9|yq-2_hR=Ui{H2(Hvj8&4Y78fQ^keAI< z)3Z1)#g3Lt)M9ZR;Q{u3jxy`jgpJnhg(q#g?_Q}N`NE9at5w2;nenP(tt!yi$i~|g z9&6-_a-s-(fIm1|{CA@`>}8sc$pfG4;F~{Iu6)HXO?RfkiV*wh`6;t}CA=u!^sHd@>E6b}BMgezC;65_!xjeTINEplRp9>&+ZF zmChvx>nP(~Ej?Xa{gOgsqjUqB^+fq?&xz<@e-e%cpk%b!y4ap`SC`#NufZIvQL*X{ zKUL(=QTI``?zq6y+W7enuPH%(EFbrnGQX>sc|#AmRN&CL3RVirm3GKvymX())D$)? zMAps`xj4==m@B7V5n@Nt@t7a$w}o{rfyEYq;SMV18KdRu<%breiZq<%1b9Kbp>PQ& zr=yeWc%&m%&}Rp(KVlF(m32pv>$B(It6WBZwXS^%b3EukI;gO4^VrnwdT9G<#RNW1 zaxG(Zp<3lA=f=TvQ=pd$M8m%}J9R#rc(!xZHk#v9BGy>?@o(Y=Inx-f2}jK_g)vUV zf;uCeiDr9lSu1l$>b@%XNW3JOlB~%`B}1k2k#P z6Z`cW{n(>D70x3~xwriub&JwMe@$Q+%ON=G%sG#J!tglbds(3M`vjF<7koa1D!^CM zv)mKL>1FgyA-Jfw6(_kT^hU6EeNk6{BQ1}5L)b>hEG!U*_>}8TjFl0*QyzBKq*8gp zGW($2*O_Lt=8g4sp5+05> zs9{o5NnA%PUUOWHvzPyjNNWrtAbovmUEs-IHQd$Z@>%beHm{M9&S`*~6X*Q%7qbx~ zE(`BuH|eWsFylt+mJD31bc5D6*H5D&G1#%%~7|$OZ=Lop}!wG(A|5cqamhoTnOQjw6m9O^X zY;10a?psKqmyfRhs^&OEuw3N{fO-*2MU|Nv(v@)Zhb_z3N&15t5(!mx?0d{&&dG^V z58KB4qulNpuFs@}^+QVq)PHTorB@M)z!)Pg1!vOUHR=r=S>%-iC5zXyT0ll~uWR6?c$e-he40^WOQ0~$Lgo)d3Yim^*TdBigdriYcG0@Fc2pfk!o*k z6+sB#X9uX}e)ZTy=%4B-8o*wlj+cKqLoH?cDYjVlL%d~)UW*%}Nqd(`;ufCyVXEM- zhSZOdCI3PY^5jsrI%j5q^S6orTDog*Mx(8Twj~&-9>$J_~SGRj-KrW22#{j??9Tn=EQk5T$~o(qHnA3XEwSGqzHr)m=S8RGn$U?1l!_u z%uMV@hMRDqe~*lM+q9+ay$nQUG;Q+cC0Bl13CDqqqLN{ppHknerPw!Y4Pjk>Mb`o~M1Ok1TWfiCbZEMzv6RMV zuNB{ZJ({e5ntJ=I1UF3lcahak6okojfwd2P1S1 z&HUP=9*I+2WC}1^k*52ClHlDxBr=h>jKvKOr{!CZRSK60UJGw6e%m6Q z{MkMfoColD5}j?9qhjUnMxnOlUEJX}={!T0pC*D8Q2d9Jvv4%^df<04K>)*GF3Tc^ z{Woi}7ex8V5-rjdVd)XNn6fo#G%%nZ?V*}_xjHi*Afi6>Ib$};oeKQH$v%F`cZ%Kb zvGS@$J(}XZl8u#CsMC{XmxRilKuhs3vPs8&7k2DImn|jVTYpRGBul|$C(_#_X!8}V zjo5-66uie5^N~}m_Ifne3Tw+|vjU9(S=7BQM9wJ0C1a~a9HHG&!LB~Yoyr` zBCx@+qLGV|Xjd%37J}da-xPY7YdhTUN&Q@_QGYr?F>#pDl?)-1?=t`Tr{OOjFVf;$ z&&wJ!^fmTILCcW+-aHH%0k!&On+blM-sCW_R>W{u0gs_4WZS&9lrFoJe^=8`^9$gL zIgHD3Sr)N?$Y7%_Nj5MS2%-OQ%yLy~*DgTxTx9PP%rPov6~AmJtCGGYACFQ$bk?0p zRxho$Xk>oAkUb60evv)LOsAmBK(4$C$!N5u%*5Y1J1H^5kjUkoL_(xzT`L#;$<5AW!Q!{)a*k9H^f1NZ9dL!(6 zu}rKzw-S$jcjg4jtn`YibfCPnui=)hsM{sG%GyOukE#PR@6#Id-_oHNq=J`>Cce>& z*%z?Uly7(owSV>|kEb8pQuuD9{;($O+3d0NDBoZ#Yr18)J{3%cV+S^icfs`5Nbl}4 z>#4;%<@BG>kNX`}oLNURy&Z`0ntTG7 z+n6;>xM<4W=-!rX^PQ(K9tr~_XY^}7qCHTOP_vch8xO*3ilaw)q&n(Vwel(v%j{L@ zK{5fMZ-3=6Q1@bc5>zq+DofG~erWfg_~5tu7#+}}{vVDZY!vyAAy~@nuGyvn(3kaF zZ)-cOmuMQXQA&YyutViBpc27XIi}mTs|Oy91R=R0F^M5_WljzQ? zWx5vg8P62iVN5Y5ZA}^;{1arR)weDx^hMg2g~~yO8%d*@eeJ02Si{D_n8tDLdL)iH z*j+kW%b5aq^Thke3Ea{KcHwh}+i7f~kNm&W9KM12phvH`?9d+5 zG|rQqbnSb#-xT}=@-CiccV)Y0f(+vL!&=V!UxmlSeExqc;N|~+1&kH_%uwp0VlyHI zh`m*&-;KGj)-(P?N6U5`m6rdotj&5q9P#(Ywu-pH!xZ3Av#WkYD23$lywH3UQ^i8@>uFj>2RZHWz%tliQ+4YeB7iar$Wx&}*1mOfs-VUG3;Fw1-X zd2lLQ+X^4NHK$G}R(E*%^UIL_!!kXN{v-by;n$wqm)t-z+iJ(W+Hk z%#|6{7K`Vh&VSr|)~XU6ri}9n?W|wX5XimUW@K=ByuUBRLi;W#A}Ml_52R4t6E{C_ z(*^UUT^IB_QWp91_|hq;;lrE& z15Tptm`<*nCCTPY?t}lLmO`-=I}Z0@Q}(VJMmX{7A4vk1{^PmlBl0t^O^sz}&jPAl z^Y&XBW0A2S#W_z&b$v{6iLe$o5!RogywVyr?gbI#t;$k*O_?PrDT)8#fcI^;md~hDF)RQ&m%JQ=^OUFakfDls~PUGM@nbh_l2ok)Nq4ezviDi zmS#zjyd1<#!XP3wsN!RUanJywyc(@20%b1|x%r+@1tk6XQJ@IFE}bT8!>d!Ao$g*c1iu< zq*0#p%uIvDTXQyYhDEUOYZY`})(^!G#`z~)-?cE^cgvWtoGZ$aK>h^Nk?;<$cLHPs zsmZuk%hHZZ8?Q_#uYsLt=NOSAw{@~?5&?YEQNe)u_e5@G%^Iv&GBZZtmF7Pp4EAs@ z^2KZ+iEJJJmmt#Q>Ld1zb>Bj()PU@%2qFfkq+1@l_Y@H8H>NaP%SXx*ZV`-liuo=! zh_*YrutSj;Y&6*t)9U5^))GzB)n>L;QI1|F)#+hM-42{q-udYLV{;@P(~arVld;Bn zlu2~EGQG^^wupOSeX|rS9wqkZ$uCV&dF>|!mcw%i)pTNa!VM4h=I#b=V!yR}E}wC; zC=S(IUSO>-DwDdlFH*-w(}-_Bn)$p3qdUM{4`re>pm-C%(TnlB2sPAds2+A zqcG#nMOCo5A-NQs$70yJwL-A+sVoO<5@|^>V7l>=?E&P!5T?k2h7(hPY*_i_Q zE?WQ3-rdYrZr(9Z8XG8vY|8Mn6^+w|Ak1Pc$i)QF!HJ_<-9U_oQ%kBn^{R4wkEL5q zNsjM79Nub_8u+s50wUO@F?8ZAr3k(qNnzOFo7Ph)1A*mPaaC|Nkv#1Ze(Nu;x~qU! zu3yD%4F*0h<;m)S)_IyX zPcn1T-O3EAoTs-ywIl@%c&B({Q*EZyw5Y1%blH`&U+#=ID@qtfuLQMdv6oGoy!ksv z_2Y5yBqR&$()gm$*I^^_YqM;=#_&id@Src&jPPfE{K4#v9O<7RZsMS^R5hBTIQpe} zIYCVRh&`qUMOpZsWS&^cL`Q6I9q}KIV(;n&@4A6wmltJ~5|TiNn1sJ$+>C|yuAA34 zYH$Iow~Fo=;HwKHk><}jKO9uA>bTDz7zEqmM$gbLbNfkyQfr3AnkuuW-0ib;Ir{%X zA?R6t)|r~0vSz4=VyxG1t;Tj|&Vx?C+-l2O`9Lgv`hd(*@vFMGaqZ|A8n}PKOtCb-?W_>!)(;q>5jK+IL}+ z5B%q?o%~NQ;z3hTx<8)z?3Dmyo-st@D zzqlF^Wx;aW`IqiEc3kNyE@@KWbV_IPYYtESN|sY0eeTHyJ^3%U=-(3tVr@GrLyJ_a z+3b)w`3UpIQ~v2e{(85q|8Pp)7s{>DJFdKoYErDrC<8iwzhfqzFUd6dNP&ZJ$z>_< z6BVk|EBA`TuJQ+U^wd!jpR6u|{=?B3Snclgx%JJ`ZJLyLd6~pi7f8MX9TOA8o`Esa zNCwSN*(|=&NXqo4uwkMHo3)`S+0rH}Y`i3C*E2j;1M_jGJiFXK9Lh#7B-Hm0_6rC8 zMO)go)&XC8+Y<83TpT!fn54|s*PXS|B61CWh+MwYz{wsac~kVts7-{$JBJ?q+NTJs zvas+VJK1^zjfq+=!K)O5ieV&ZjJftIy{9;tlYEbENVp#y+ls%#nhdS#^piT0hn(Co zLX4seG7zHloB$(Q*O0VA5fr)MX^2}d*$Y4B7+|$x#Ew1JMC6>~)M&rYn{Lw4(V;Q) z=gNONL(K?U@%Ao=+J~!h0Bc)^_?9ipclW5}Fgs@dSGz?FG9an>kjbR?qWLwMkvf{a z%`Bv>PRrF)>CaEOmf>NAgs1yl=q-RMizCo!!;1^} zOoI`ECq5oBgT6jZ+EHtb3X1sKH#O>>aoM0l6s0z*ILqyPBgpc02=+OTT`f?=$+h{d zoDY8aNsiNQkrFMEqa=`lJE3bZ4_<3KoxSh^Pa626FhPSL6VX!{p>lM9ldUc#eienM0Mb=W#f-P zgC9^bAS2nYNI_7Gp3te$>4;@Nc7W$|SN+=5gl~;twlYPmEF`M0#R#xnNrr!AhJm19 zcLwYkA7s13Js7BV+5jSq@9lS2i$ikI&KUsV*z+HlHPM}B=YZ;h*|Ll^3*gD^k#VBm zn zY)7|AhVIB}zyblLqt|>F-Bvfy&3`@`8Q;DL#8s?-=%uM%nj~y{#|d)H#}AkMgO|>a z`PrXoIIy`&SEtZNIWhRePW^EAf81k52IXXVT5Nm&q5B{A+$l|Sc9Kl-y~d=QYusH% zNB8q5q+1_v+>^UBdx^9?{|^8aLF&FyK>6GA>qGq0=W!mHel^W@)@k*WjaC@#H3U0c zT9vQvi3=fGEgO>3jgZeT5GM{F2)rZ9`re`Cso~Y;x_Kl+=}!!@mggD!U<1;hX-V7= zGa5dU-63zLqx0Nv1ZL|@X@d?PsFg=LQipJNp&6TP1Sr~mbI18^XSzCd%6WHNRnzrL z7$s2Bs@6!QRV&AwOe(F{sI3kGki+7}ScXlWGv_}xSo!2ftodl&52?2aT5uvL4S5Bj zB&pfAr44f&i*JB2S>$gt%cI;INm?yJ25(tocIFk-d}~v+8GjL6lua_5)Af%xTij2= z^Gb~zM^M3#4gdzA0e9H+@7pc5hDg8jkQb8qPH)J~M2j6yNV$^#07%xQGER!pLHny# zBp*lt@S&#~&=4pNGs;Y9gmmCbkL-9=o!#G=e7H3IS5UgYmi8u;i7pxc0D7!l7=!y& z9d|qBL^p0XWB&k`da$$Cbh#yIBNNJP%SQZI3x(sgD1OyGoPac2Ww?DEsOi&bx}4fx zvn}%~N+SLA?p8oeC_yy`dV)4Nk{oA?k1_eW^2biq?)8N>GixoUaE&7Dq)-*XM zl->H!TwBDh%F?^3QmMwD5er&(rZ|e_2#+{w+Kq;gFYGSvE%h|Jw~c2m#g!$hupphs zvCCxF5SC~f*1LDB>l%KqsY^RqdK^u$XrdJWmQ)=oI{VhS7?RFWdAFS;VI~ zs}7XRh?@;^8@$KOCtO`;R$U8In#vn(E z=D4_Pn{|$7X`k&%2&n|n)NO<@B8$oVt*i?zLrF?3Z3XNL>HsPz;ywHTJ#v6|awIH1 zl)kX~z1`NCs0ki14C)xj)h+3_#ah>90+h^>;)jLl_kLu#vGU=*)^0AXF8yN_yR%k0 zFhf@dlY)8zei73m8@jS@J6p|Vq;hU;YPUA>FRLRHxhg&qNCa252{p%M{{WR%^AA!A{mtrJj%8@ymsy> z{)rn7cHvNFSL{9`Go!op9V{K2T(`q!&u;z;DWxDc|62SXtW)a_BdJ@Sj)us*5Rd< zYqKYX#SMPT(_1R%WDlkPgi*Eipe5O6-<$- zD$b}`d9VN{?PQA)yXCD$ad~}sA^4@ax@1rZJeim%6+LQu_sS$KwyEo0XwWCK^46hw z6w=1l5XZ&6MglgDMIQ|g%~7xv+-5~kVhxrnq}b{<-ebSA)GzLJ3zx84*`<}-vpm5W zjJ$~~MQBS`#AIoas$?4Fqj_G!@;5&jh{hk)E-CwEH=*h}ZH)Oah_{*Owvy^Maah_$ zWe|fioSf@(%6g!Ot0)z#bjyKY zq4{;9-1(9S;nG;l_fokj%o*B4O0!h&QhL{ZxZNoTf6SS!EM>H?vbcuqK{Sxb=^F5O zK;*1;uKQGN_hbpR0+HXB*2}B;kHi(mP2)AU}g z=A(Bse0;)f646k4GDlW@&uVOU*!;lDDQ)h0hLvcct}og+;*K%v%2vEMCoPw5OnNT+ z;?_5O{pM|HAikVidS)0CfhsBq`%U`BRU+RJv(Tl}TSf9Fp{3pqH#aukyt{ABofs#G z;n7QQXtPU)Imx@dY=)Re^+)NPeilGG+K*>H z{+v~=72Aay#O>D=Snfx_MNNC}inKwf;-rJWLrR=gQIfx93GKCLKKxY?ZxhDt6sp3a zrE5*S@l?jup|>k6k)r}>=<31S#G*=4|43i!P*{&CvlM*NVy^KQB1PcUn@0zD5>yE9xz^<;#z zqQS=8$td+ud_Ji=)`|ehVvSo?qFi)5-y?ai%oA#Q-h;21WBT>g{F7Ws7cMW!f)#Mv zH!70*P@KoT+?v>?o^jWr@}-^Ln`vZmM7euFBBw;+lSr#$}vqiNa?mUP=a7T<-P zt^JHiF$8+Fkd~54^^!)ZB=q||0L#c|2FnSynkhW(<_oK)P`0qbu_&UU5%G;vk3hV8 zcgR~JHe=tJK7Cu+(&pkdjUb4@YY6)_txK>Q6WAWhwh0?dBJatcEywwRt9@f!=5z}p z(oTxNJ=CFUkRx^scYpGB{j3lcQ!~OIz2>VJtTp)-(PUX=^8M_fC%_a5O;i9j6bEk% zvSWvnRoJ(mc^6fWM)LKY)sL?o!`)mMRSNRroJ$IdRcZ$0Vi`IHI6|Jy`8VXhs%h}~?_7{vYZs1-XpX>} zSR|qKKwY`GJ%40v*12Xl?QAkijWEwYmj3_`Yehu@`JU}-K|*OzJa(ZcwoG$avcEHV z!spAWCANz4!sfwZmUSdLiK79Ek<(+wr=sLcwphjT?bnztHLI9(-6dUAQY(1ZxjR(< z0G`7tw)&^oww_S8A`K~(fn~C0pJaKM z*+{-$UoP2xjMC%R?c=f2gL3-12uLVepBpn(na=DaUbuKA z&5syk7d96b7P0Er&`BMX{JyU=sLGRZJV}j+_^5WSTJhZgew(}lM5X;PK|$eZnPz) zVcuu%$8a_n38q2%1*?C~KIvbP-a(7=2hRThQS)A_s6id%aTq69VT{GkjB+D^$94FP z2|Lo6Tyonin9j@ztURaXJG+}dH)vKja*ZAhY>E#PS`Wt-AgiDY+rs;dJk{_Lo2je2F0)z?7KG062@ z`N!lxEqQy(_xhAKT54+gMa)qCjIy?pIVKZOD~X-T$chgq3bj-4k}4}-<~&Z6-3)ci zz9iM}EOhxq7nk%Fr& zM{gs1M6n+MsMz=El7y(+US3r9AI+c4eLM3b%esBHku@DtQPHhxHJNVgo;V<$yp$;` zP?fIzHtU%ga+yNB{>K*vF#~<<1M*|d9$V5P*CN(!ZnaG@($-1d+SXT!7K%bp%Hn}{ z-9>&c466X#n%TQNdznNZm=SreP4k|mWOa-8ySafQX{}wYtu2dG$mEmhHo-*&J9y?y za`A)iXc)u@FP*2k(d3iTg6*2^$oM3M&=&9niX7L)&mz+B$VnveE3x(;=hq~~^-twK zula*(qAj(bmF4pXmF12|Ellw`sZL)Kqk&TxZ^x!)=}E6IdxxCF9oT>7O^=&wUeNwv z+YK+AJS;4hKTp$v82mAf&k#=KjZQ;Tce`#86Uh~(`6KfS&bnTYta*P)zfCJmw`*NK z^4W|5myzb`_4tW9SKDEbgbcYNd?4EYWhZn=DU}+xAOJ$QoV(Rn>&bGl_U<&xoY@rOgf1fL?1R)UZH&P&wjhBjc)p$*Mqm`NJqL5!zf8ssP*3!0 z2J;4`7nZ!LKC^i>)OKrfNLUQA9wkwa+6aErbTl-s5Twwz)_;~d2Albh`L&?`0M0IG zX%wDM^0NMz^Hsz^kJ6X6#4<-SSK>o25y0)mNCO6Ga0F@N#CVJEzt4Zo-6Gq}iR3*_ zU^G1<0juluKi^Y$?aA<<Sy*+T8wY^7Vz(kI5p9q7~bUhi$m_rdfd4aI?mX)C6Bu z4A9BT=8UmRUb!$b;cU@c^2$50)iZ*0FjQP!_rrz)ELkv$$dVw2DJl5?A(3Ht)7Y zX%f=1+}qEq-9(dILwL_{{%WbH6hInrD$fS+fTd7VGvEq*)H6;N(0oe7$S%sC+5*XaKF|`j* zza$c!>6Z?c@&LrhuFQZEC@3j_tMe27a&OKSnqQnXKP=Alm(1EtwdiHtUg`vNc*q-q z$^iqp8KUiNIhUwAj?T?Pht2t4=HU1Ggp*G+jVKC{v$aBnP$&m(nNFH~0-UWxM7gjF zudJhgr=raYk^8`^7=KUWn;coY+zG(+Pc(lt$72w%)uH;{mcfFu{{VR!vG~3ognaWL z_qBpU?!U+n`O5zQJ^n#yOJU{4gU!E|(lITg-X1~#e%iqyt3_VElY<{Bl>)e9yIC~- zMf|k?0Gy5g0GxgQ0Gxq%Y;3gsBF9tosdc357O`7j2LtTF4H48I+eTpC*&-<%Po(TW z=N>;Uq|~7EO`nwX*rc{ZYg9IntZKv%&%u5cVy!@0yYKITJVg)ZPtISI)Cbz^bn9cU^! zRU5QWeTAhy68yi^%LEbwBK(g30Gt=R{K&eu{Mr8ioQKulR(sPPpe-O~;W2O>eMy_+ zVM{ZySRHzIiC%(Y(uKl;5IP=B75N?J| zsJ}ZjU2@x7u$Rgjlx-fMzX(~69wki`mb-!u%sXTOVsTPK`J?0;PtDk%9%`TTSDx&l zTWdcuMm=aRZR6Q3^)*k4%8!OSl^&vs2M(hv%K;{Ma!VQ6`OoK1EP0>E*Ds{`yGWEQ zZd2^;b|qUf}#cMqtZL-0VhSC!brxd#}$OrjMrG-A=}Xl2B0XvmTi!VIgEg z>JQ4#`Nu1UxQku$+r{ZXM54_BF(Dlcj&^7N04KI&#sVDNY?6JaVI)3W(yx5Vt!-yx zVQn?jO?K-HZ^cPau68ce;}m1!b|FB^Mn@W9@OPMe{U@7dZF^m1TbtfZZt_&JM?eG) zy;qNLcICZuDmyh7srg>?!q>h=eL@SnxU7j-;+O&epqKFQeS#z2Q3AT|r! zE`0X-r{#{N<;Z?Jk1#fk<1s(nxQP~Bvz{{VJ#UzV@-IiL_&XXS;3wbq;Yt*T4Q>z4jf(~>$G4lfWU zqr?%{GBN!J-qV-r9`*kKlN!u6ItGq!QHn=4s*CA5$0IYsjJ#QhQuP!SJAq8b)e9Rp zkEo{~nbXfrNlNpTgD~5$HO$RtI&t*>092noExXAhEJK?L?M~hqj6;&8Z#*%& zN?CaF0=1y)k=a-Yl)~~#t+ARyy~Rr&nHFIe=4RA9v0!9&Xm8$oW{O0RFbN=HrCASO zW4~j7q&}1K7yRdE=DZr%yz`~l)f&#$JvtEtA6JmU9>v6xjz(Y2P(wl(r&z~*4$vmK=f;o z54`^X=NdJIveGpBen}h8r)kl|tY}!GKf*kGa_woY!-<6SX7<0DTBN>Wn@6~{DRFEO zt)5o=T7wLhYREH`S_2V^=m)N`} zJb1AbJM_%U>gE?HjGk@p;naCHlljdGLgwtw9w8RK08#kxLT@|aujnB-~X3w-Ucrb|_Ts#s|9-i#eHc=ZFqUpOIgi zSNd<3Ebpznt*3dC=Hv91r+H-Y0#*|^X7oi1F{^?CRe;)rX7W+E3N+w@!goP_d;V!Z znLN9yU1^?LgUQ;(hLI+r7_yLqED}s0c&=07ARa{eZnfE4p&1NV=!-U)9w*Yet?sR? z>AqT3d4=w58Vz{wu+m!}R2^=t^A!G$h%FJk`moC;G8B>dZ^L(HG067Qe{e3KT zjWbmmJi5-2r$v3H>iRq$l94ULTS*%!uQV&pyRhX><0!?s4pHRy&msP6-}!$309w=S zH2n_stY@@QYpU7Bb8|A>*~H<;CyGuHfySYjax~&G)QUSbV?ACe`HlIMFMl)iTb(mZ z(=8S~MJ#XQ(Upa-uD0fQo;0cW#eFFT^fg+LGTk>Nm2-VprG8-gdNS!&eqPX{MX*T` zrnEs7$&xbWJ9(;JM-(;Upe+yb<}ryUn`ai(_@?jkT3t_5zVk(er`6ydS<>~Z6p_oN zn3nxn?U)*=kD87rwMgi4@d9IGy^Mz^*Is%2?epG`qU&;b&rR}Ht6^&t5#G;lYTmQ` zVnjjcvqR|5AumFzd|6J}OhCS6lyY0b{{Sw3Ff|`0{#$vvOF<3H`VXFLEyOpr%Pp2TsMaT#KbT=QTmgq8byjKVy*w+GJu0GB_Rn$MQ}p`!Vo((Xx@PW;J``fgNP$W>Ye zmU7)$Re4u#JGWfefFm8Fj*p% z=^q%>QD{Lm-lH^xmo`|0c^Bq}nJ`Er=h8zYs0QU#oU)C)0RzKq%@U@Cn*Ga5rol8+ zXxCAMGaqz)sqKk2kouGI`L3@&=NxtAqsaswV6ZCec@`vrO7%1YZuHE{{ny37s?B~+ zoNjFr@jkC}U){B64;E9{(=qPc!4;-8jv*S8zyrG-&$*>BR6ia&1_(FpU)PEdX?6>k zEr+Wj(xef!d~1rm>+)mCo@n!iuOfa~T>Vd9wt>xlw6?9l{k|^S9lKEY<@iD9)Y^Vq#r^ zc3C?D4LN-Rp7~3ChCSyEKH7ao!|RPhHj+i`rZp1WOe8B%l`6DQ0N-q`L7Yp#FD|F@ zwd#FVFanZdew^d3>fZg2zqVFIGq=zhN0{LA4wYgc2-Y^QD@5jkSbbHjkTL30kmLc_ zAG1o4lZ#xzNiHKv_1!Yw6=1LJz+;>uIw%}5^BnAs6iEDeM$32^HmN{iaSriU0 z$d*ctir1m-mC3RxKau?2`VOSJZTG=y^8VJsDM;d8y+V`rybk#omU9;NNUl!39ktSg*FsoL9PMh$Exgea!c-?=Uv1UB##hOiHu?)qySDR8Z>eb@ zAQs`$Q1o?H2h>It@g-^eGU%IVkfyHmyGi`ZbreYO}(cHTDB0 zpuF1WNqtvGvap>}Y3$%-g+Z$G1d;(ALyxj|%4XRfX$O$J)gFlRz%kZG91&T%c zHTJH=97Mw681NK_sxf!`*NxPlz|d z!Ms!9`Q%D%hI!V>blZrpru5}AMxsXmk;F%Tn6Ic2Yp9 zU;E?>@kH^S%)b(mzcn;H22UK3IHUZ@Zt}~c+c4uK+N5!XuPPQ^n|7h5Sim7|ts{>A z09#o=K>Cv+sQ@Vgpo7?W{W${6Jf~E+pUbz8Xb;71>m*FQT?pia{KnZ-jW$(>zuaCf zuV-VZr`6KhOL(VAb_akx7@fl*9DVZO&~{1uvtxOx`Hxth!UnmDIbt^`83FX#A_SaV zj$CWV(x=-CF|bJdp>Z9Ki=;egg`*P>Rk!%LQlswMB3Q`V$8Mu*EmGssZ%%mbJ!l*c zvf;f%r_+?4ZQUPY=(@M~qVmsD)O|?hxe>n>e^QS?NU7*6Uy#hGxW(m3ZxZ=G%QC4f z^LeW2q~Bnny)+-jxC>w#{1b1@xvi(r?=7sPkltI})=P5@N80Kn4MJ3dP*>z@ke?<& z|PsrE;%^(QTR9R#~|uUDCWIX6Gl6GWqA3r$;s~j0GKTe?vtk5Ix{uy zrKhCifEep(dAc-L5tg@D))ft1fCFME3hi70mF)3v z% z9rf$fPxV=(D2%*6yKjV7de^39xUU{dYdafH%T%=meQ26%mnOdxNLcat1?l6E1+;T0 zU(Jm|4Pw}~k@3JJjFxBp;RB-(09sS-+PN7PF<@Vo@RQ~!l}wERNd(TMbR%G;Pf~Up z>`q1pc2gGjeQG;RS5or5gfbaSy7U5aM`)0h;@$^vea2ZL!UC;?Xd2^rV)M=R;wQRk zwOIH>&SF*~Mq*jT88$l*55CyjVdTJnF@?PPtUA@5%7nePs#<*rWqQAU58N1 zvndB-T&i25FG&2jdyPBGAMQ;f^gU^v5;0l-0C>QTN2bMo5IR>U9!zJ=7p<#Hpnhar zx)AQ#AR)J91|sw#8V&{ z7q)(2>PK19^$6M_$)r^?5&&AtpwKT`lT(-RUd?gXvk%RUbJhIKn^5xl$EFX^)>iHH zbIl2YHI2Cj8;ME=VejFBJFIsP67!z3bA4@Z9n&hu3mC{%pghMeRP9qhK-dg~_iTVg zep|UoZ?9e&AC>J1moSGU*7vpl|5)#HpX<;2V#}dVh=I`VjtY^C_O%;@ZuS#IW%a5_<6!Af1hC zOk`9>pF4SW(e<5D*4K$(^D9gw*?5CisrSmjXLS0<&2ib?d3#hh&ls9$BNphauRA-> z80JEf5ol;jbsejhTU9+q4OSfvTmJwm-P|Hy*lIFqakBhGi0Qzd!*-zd%L7phW|kv6 zTLQep(D5`OhuQ^u0qun$Z^DkT#;oIdj$3i?=~3=ZDu|60q+%12lkmn!-^5pK{4rN^ zc+nQ==_ymp1=_XPd^-XK0mW2ZXr;D0gH<&Y{urxaHmL-ThNr)_DyphYLi7~+EBf(P z#D+HbH`<1~ik{f2{{U1s+iD(yoj^FNUN|jU#a2k;k*#?4743?tb8w9#5=w)= z>KLomX8gKotbCgeg>fv}rHpv|RnJZ1&i&iAlpc!m1nKLC!@_5p0%9^%KlNhx0dfqGQ0C-fW2k)ThnI&Wo0$#Lcodx zLzG_bMNl@Derefi($6KYm>25&`894(BR1b?ccGxB88C*-m-1iozgU4=%$f$5E}-mv zDDGKlAHqWrq>)g2;DiyACr7mYV)-k~HlA0%^EaC!i%qc8?=AHvH+NBdVktQ-ya*VV zmO^-{^`Io}lgY4LX3NKXv7pcSjdA8*%s(sKSxX)K!dBCMvZ;3nc}oR!lY+9SUCOl$ zMLXp}O_JMZkokwo(_P*!mwx{M>1fA+Q4)U>e1Vln~Az9#!eGBM+)A0)({fBC&EpO-3p!{;lArPcKvCS4xOPln)0aT>Fe zCDg%w5R^P)Jh?N2wE@r_yg~e5wfOKA6;91S^2k5n$kI?)0!B# znBb1(M-UHlPQ9o+GU}%o%FE^d06%MbJ*KOF`AL1K$0R3Omj35jg;}9XnNXue>C&b+ z$>Popc_|=q%DhkulL#8L-_O2Rog`^wxJjUvkt;<~N^t-ZDOyvZ@WM^88z;Y&ACi|E zoKkDLSJc8Ia02Q>8?uh{r`a^|#xVtDGWR`i$gpXe2Bh9+)@(myb~$!&G0w3==8os@Pq2!ot=A}EYX9;e`P4Yu76KP|)8%n}Xj7aHPcKUi@N{aFlLdbqERY?2y#f-KO(9g{+Qc>mKIof%C z;_aF%O*J+6uH{yWIG8IV+eUuP4HVOU`LyB&F0&L!otK+x8n(4-rv6cRmsv5}!)qd? zqfZ(LKv}^oQT`efp{oj4ez{m9fv_Fq8vNF8H(Y2srMKpGqjz1`kn3F{jJmy+sB`nv;+INw(cyA`N)AZYGD5sWpZ&u`61bV`Mx{NhxUgET+GMLAO zm|>oC{{Wo4@{Pu?9;4;^U#(g`fu?Dbrlwj47Z!(`IwX9FRc(V3E7W9S2^=Auqr?#H z{{T6GVR<|k8r7|ZoxIwNH?!Q^HN=y#M^<)@Hxy#j6#{^fz7rWWj8xCO@A=zj`I(|> z$>o@C?f$WsNhVW|0AT!^LSpA=ETOo{+m1dIs;0ZIY}MiSsQ*^&l9lidDjet`1Ut>pgz%O=!x z)z-{WU)=LveJkG%mC^%VUFL#svWXCR>bq1e4xhA_b5S~{j)MSRNNs2aqiKu$FbChQsCxyER z2XOU&%b&{6F?qv6vCyOQCFEDv(Y^keqe5pks~+`fC0&u5b3w2^`F5THth8mF7oC1- zX)onTZFG%GSf5zCw}i&+FRSTWF+0N#sk?x8Ewyr;Osi(xBZ&#*-_0A%FGznTYI;?c zy`sk{nk2dovch|XbtB;R%CY9*XFNPdWQX$y^9KI_&vzEmUR&Df_EvFv7PdAi!U&hS z9mze;N_kA#W5OZ2?;!qT>K;sr??p>XT~9~8DsC*V5VCR~wxk-VBLp%Sa$}nh8@&Db zk9+4tx6_^*T{}aus#E_E&;Dv$i38>33?h6 zJ9*PnKCRQ*+cTCw&hJ*K>9%0%C1u#eRA@1e&cDo?-FM9XVoQmSr*VIA%Y$soKok?; zcFJ#d=#8HV>DuS`XI-?_OESrAKdZSr1_ggn!IW5~j>Y>y{{T3r`Ojl?pP*-)25Jx; z`!T2>^gq)p!9E>}4Mr{@VfW?T@TF2v(vwmL{A=2on|AB!l8NKz`})y~RPENgYRSt}2_!ZK&%oHjQ}-L2S&gGASjPD{=snN^U-M z#Zi-+tv29XUIFOH7>aiO%$2JN{Kx#zvGNv+KCgEn-ZHVO&@;P=DC5?HuGkElapJw- zjQ(T%$MWarR=KZ!SnIM4Cs~?XX|xSpo~oC2@q}2p_NnDjS~Xa8rdT5xju|qPjvr8b z+kP(Lzr6B)n{EE5=6gmW=G~1JUkM;@+E(kfXf;|{;g^%Q#hy7uv8#(`v|1BTcH`8F zc;yk3BNi{H+8bEgQL!My{_RfN_-1Y_t~~LeG`}-yK1`iF!{vA39H))NtfQ1u0o7ej z-y$~|nhT96y)^lYMe~KR)F8H4om?@2%~}T|_8X`k<1K{2*tKxe(EP1)=1ok;XKkwL z@!2YbjbOjJUWd33y*uSOatLzWxIr7F$EfN$(DHxfwX_!((bi2*R=wpsHk_M@X&Z1z z-ldrDw&yIu427d4qXui|Jz)-uCzkZ7kj-;96V6jgQAw`=2Fsa38#s}X zCwKJE`7b)$`3uWZ#wb5T*@}1-g+csAVTU$c-kF6C#a)WK6?Q8B0RPha`HH(0b}H;u z*sHNu;HT!Et!VoH0Oos76J6?lTJssa5JpPQG}#dYm`eWuzM8MZj~^U{EId%Yt+UI) zFb^W7XRA%1*~P6~pVFRP)Gg9`d;3vZqxAJqcO3~{{YGiA>)|;Va**iePfKFrn8B&& zI-Ck@btq+71ws}qKqFzj2qQ9hsi%fRqTM?|hV{(4c+=C<1iRc_2#_j@l6kNcr-u0n zkm43F+%K4~<36Nzw&kMJB6r@iOlZ=IZ^j@`iwroi8ScX*sq#1G zkLP!qzc?>qy7Mi?ztn6%TU$GLgf=#zYe5t{mTHnrj9J^qwq`;RfU?zcmdra!(6yaR z{clUQiCEH;T~rVDDu1S8=j|wB=55Kvqm-Eir5-F02alW z=nP|h+P_9?&uiG^<(|zIW%RG)rk`!)-!M(8Yu9Nnm%lC{lTg$p1hjK%vmyP`ld)*U z5YxG)bRCHi5Obb=9VcnemN@lc{#gG2oQ2l3c{N+9t?ch0)^!ikO>cVbjMVod%#SZ)Kiqcw8COLP3sG$daW=`F6t` zra-jhz%Y-9Rq`L^XOg_ZVz-vxlzvl%eJKjdb1aV|v|#e|qqJ3J9O1uh53v3892cgUu!~@OAFnrtR*qnY_{$JT#89uO=I>>0;e(pct zvvH5uR+Jq&4w`g~bC$%e>Gs(Gb7|DJZY7)ui$?q(6m|iQZdznO$5G(e} zEdcC6s3U4-KszMDnAPW*to2)Qrb49)T*WscD5H&f*9ET&?JxPqZ4T30{J8wpH)yMO z6@Zo*xB}sjh6_{sEJtpYu554t;FIR-^#t*N@!c#5Euz$I?h-)g8dWR-LYq zrv@G~ea}d_{{Wnnjjvl#wY0bN9)QF=!DQe7Yfu>g4eoyI;}2(W%Ztw4{AFU9-<1CV zGiqh(s8`EyJc@dsVD9a5P1qw#RxqPbUIV%CD!G~!haplg8u+6 zb(>!;f6gj?oz$!&)vfgHPR{r05{f0m2~*%S2dOosJ+pn9I|_B9`^sY)@0|R%duygx z=^t3Iuyvwco2dRv8Gt|antlJ*q0jG-KASdkF)kkXlg1n+)Z_c>l2J(Kcs&qUNb zi*cpdT|s53P3MhSZe_c2v6n_-yNdNvIQZpVs{@h|zD%@vJUpcNF|YZ_Zz0`jenykf zy0X*-#-nd;iDx${46LqI3NTag0BCw1o%2nn!^1aWn>diFq-W$kjjH}n`D;&bY;|b$ z9Y^$pbB0$|i9jGFE64&Wqo!?pN*r;Eg{C|+H{6nc&QEztXgsB79CAZE(_Ky>i5`y5 zZCHR6s81oX_>oN4;=@JCo=XW2<%rUJzvRClYkyX~`o+G5tR=*@dUNU@SJdR40t>iN z9itpUr@}gQ0F#^Pov2f-5i%q&&&}7<^;veS!JUabXSSk7MNvd#Mvu@~)o*Us2NI)Y;+s#AAfXCf<`N zKC0DTR0U&T>N0(yv9jXnpiRD1{QmOxs}0rd-oNGTPSZk*MYFZJy_-yvPqc9spsvCg z*q=@@5hYfhA}N>UB%Xh3Ryf#rUzAhJHva&f+9B61rGv`@S-XUb%RkZJO&*%O z527Q0Mm=6?q(+>D30j7lhvZ&QNK)9P`>W97BEKvmsD7FURz z?f4=807xudZVeq-TaYyGc5CL(!#fw0`3lxK{J-YyD&o<% zZ|-8Zo+aZWge}E+Z`>bme8dh-q)T-jtV;8jReKzT+}ONl50lcKytQ)KF>_b|3IvYl;z3 z!wd@EglWi~*1xTe_^Z}`B7EEB{{Sp`+QU`zUZWMQj1k=ic_rf-GeF^Ld`b8~>VC+} zaLa_WYM^Ht38&@f=jD%(e=IL8=UZJv&cEVFF6^x4W?3zl({D=bMYko7=l19uu4ElZ zfS`<+JVF_N<-oK*m)GB#o=ny>xqmb7r@oHvbC%)v7TC*Z9`fwN??TQ zK5cm-Nv?rAhTl)}x8;Oa{zcVvfvswGE}mif#nPQkqcU+8me7%~E4%H;)2=zDICeX( zIFl{kCIo!HwKT6yw!n8}5ne}~Z5#;7Mkd+KY7KS+k3-i4 zd9t4;q00+R<~<_fB%Q668<@kgFy$jwk*41fKgzW^VcDcH-9Jsfx3-cyyDP|;O>*iU z2UcZws49dCgYA(d7Gr0dYdR$DdnLu)yT$5&)S4%bwAlTyEANq}e0KKFBiwO@(P2p> zB!%?R8HGXW2nLn#$;7owW-X@aSDL<$dFA^%S?;x)U1m#%u!<&<s$j7kfI19E9V z1x_~3o#q**zk%X-r@Rf<7C{tIYE~BVTw4jykkLsjV5r-_ZuwUjWCqU}^Hq)A*pKv-62jKZ>-*SQHeWvuGSsLU-PzR;kK z)@#6E59!TUKqLaJLEL*}$)+MUHcKS(XPLaarD@kXhK;D<#1OS#2g*T|wGGFCGC1 zB8^%afH%lUg2-&~d#w!pdF2biIfr1%LF7$XQ^0uTblY|xLiu9q?8F*4By?Eb-Xj__ z5?KzygMIpDL|P8X29aR?WzxK(r)hA!`n{~J8`)c_mR=yeSSrbPYzsb zvEn!1!x#l6==!aN&6?8kd-9PeQm35Cj z-|Ok+eKzmR4R+GqKy0CT%(23w)|xh2P{za-B<<3huC8Idf>6;sveVNo9YOfM!yX`m;xf5UW#D*E=ZECI@8qAG z?!1xb3!6)=O5f3GXR>xN10s5gq`&O}yKZ_B+aVpAB39mV!5Y>!$hpK-6xme=KIXXgsfPtxa=pu1OaOf=bm!nh;G8 zKg4L&RqatstHj;7W9t15@(29jhnT-Mys4>q`^%nX(N|B3>hj80yh+wJYjQnV;+09N zb>sZqYeS5u(Lkr?hn959OJ6X<l&@Ltrf+c?ulV>qdaz+n?oQkBv(r-M#vF^dZ3z$aR-pgCn{qB zW#`^Q*L;`xr*Y<=I(hfZvH43`m6GNiJ*=)T66_+52?NErkTBvzfC>=7zR&_00c3I0 z>u=7l`M@OdPvs4-=l$22$!nWy3%}7fR%(vY-ZF)XDHY8~4ajmE?^jVU=}q}}$pVQ)wfU3hi$BYsFlv@wTDp^3xYcyH?6n`S zT1#j3X99s08QGZdqkL52O*)KaFqp#my=(H@^5@E)der=((=! zv{BotQNzTDYD;n7Y=jQ`rdtP(`BzTzYgnh4HBEO_w$nsT*YbXbD6pYkF44%+lI*nr z4kMdvy=$4Ej%@-vzH#!Op8UP6>v}(y{LOhTk>!08>#L{gBG}JxLvm<7u@bcpBSmf> zWVe7PF{6{Cd51FlkN$Bt$^QV98t>*x>ED}Lg}wKby0UoydZx4L|H_7K{|#b_Dj3nQ~F4HOCzNj0F$GESEe zCz=QHcg!AN^P+1P9&3wMm&}(JUs{?iD%RF$-U2xKpXm;)8Cj@RD^NoohXg0Z%`+S? zy1(ZRJg@%%IO`SPnr=Tn63whb*+ZtMnu0@lB-D14#F4iUfE80ugqi}|WM|}Xe8_G|yH6c#vyKblWW(2Dx*5pZTNtiKpqB zroH8_%NZ_Z(6wl-q10be^rn_s?W^%d=m1cs;S4_3{i&4CCv$XT-uKNfMDhojG)+6q z(EgI;J)BXrYpGepeP|IiUM zHj89dVc4(1$nW-QPE#4~-6+0|yz=}$WwX82H5>SBrh*eBX(g-4G|1?7=8eR0BZy)M z9k$D*xM~Sk{No?wt*_?q<_?GXd3kv?gnG5mf=h@Z63H6+Pbr{c1!$Z2S1IJ$1-_a8 z0G#3f0Gws=ul(Y@jh%t>75=Alt6MzK*~w)cx%DHJIDYUk9D4JhByroWN)uySzAy53 zoh*MdJl!qdoaTKl_U_Nnf=f6SWO-7XI!MdMl7m90?RMW7PkLF#g@kYB2b8pn2^Z>D z*LUWnrH$;w0crL?DBCQWhhq0Cm7;N+O>AQ+apFo_6xPT=LeV)GVhzUbnOsO%!HRRdq8uI7gurAn{;F zE}3iylU&IK6AIsWKl64Eqhmjzg>kjCMsL=*q1C>W3@zdKNWl4y>ZfIPFqlKeY6=!B(M*yRL*Odm|Z`0rT#GlDu$)C+{%e{NfpPKTfogllESt9C% zZoa1sO6XbxyL@$JWnYYfIxaGi=*UEMetlW%mOf5tVe=eUH>;>mE%^GpkR`;$w_Ep@S1% zN-9V8c;c$}R{olXjZYKyi8~XDs3KH1xZ z>Gl?LQtg%rAJmXY?XhQX+Fii!mW~$?4%~EQJT5CN%JIi7nl&q;RUL*~jTbAl} z*b%-$n=f$rnlo)?Jy<7b?ydef%KfiVNGeqP`{hN*0JCeq%^gcs3v;Vl*j-(LLoCSU z&$$7qzxj+7QNS6toBsegE#^%Y(j7BM)AaaYg=nkBVk&x(`@u^4U=tw+2rM7-7xRP6 zf0>rHmL6hgBeJ!T<%$b*Wm6*#CEJrRBn^i9Z{vb;GUm=W#Cb5UEqRXn%C~={^n!)i z8Yv@{dB-9*Rb|?uyZaH445^peerxLXQ~h=;Jv`0Jm0A|-^f<%B#K0C_-}92bb@)#^ zDkJE(1eBV*%|gor_nvg<$3A2sR4n#Nm5 zq;K0xNP_|32p_Kx8Drssin#v(oPzV*mgd$iS)wi|#wa2}2l*@oLH88GauTBu4;5l$ zC8Q*?5=lFfPhIj2k3qNm&+}vuMPnAJA%+OnD8r;|RTNQ0SxKNCCk>QvghKvo`Nas4 zHE9&DPAM3t%8QMa;R#one=+>e=L=-he8;KHb!i)O5fG@QyhuO;5!jm36C!z}02p*K zJW?#sJ4YfA%F1X#8-fprz^wWY%i(~X( z^9SvD*z({k>ZQfy-wzc9xiO8JCa%a zv!eMc&E8D1Xx9Fhv`?L8@I8-ofEDb|@FsYC{*hq{^`;M&8d}?JXc^=dTfZ#JDlT@)p^I)EO^B0)>=cqTCeCr>ldRNk- z+pWA|M&U$Y0qfuE={3*HJE`vO(Mm?r#3Eib`$0fnzfaEurNqk|M0qiY z{GaEKJ873Tzm=BvQAr$#)9Ml0ypcwVXv@xpet})~G|0AsBe_N2Xd1tl!rOV4-dHB% zKyDM$cA)!QXebX{kSt7rSA+8R&t7rRukXBrX?JU2Jv4o5&@Bo#F;r9gM2)^21lmPf z8vg*vUSRUovPiXBZl(zB^2}X(fcBw1Z$HOLa(+|rg)Bga@X8uxMDD*YYNqypTUzw&46(5#$zx?Ju z~zRr3##(@{pbuvUqcP{+T3scQB;#W${7!qz9zGrRNFo#(p? zUo3ub#Vk6#fLOHu05IDR-mMK3PBy6VJ^Ji-!5}5EL}FpQ5pDsP z?^DyyFNejHSGQl+n!NfBv2*cjLD;ab@ji=oj@Eap6R_gTDisVo4Mt)|1matzkQOr) zyi%DW`rWCukdw)tfe&r-HZmciKo_X_BTn*;pE|5^YCdPzWcwC6MZ1(6>7EI%;<`7Xp?0my)7-Iu&^{R z$kf`30v(6T88*fJLw-d60OY*#$??+dkKTah1UWf{>lq|F6?Q7@RoJWl)BE{~yA^gS z>{ZySu~+j``Q_&e&&!|r$e%oGHb^FbYJ6w6V?~-7VUN^|{Krf<52xaO^y;I;0-l5C zi(kp+7Y`#|eot$&m$bPb9GWfEo4hk9sq{(e2T!!U#%OzEvd(YbWBP~M>~tEyJu~^e zBhEjT@ahq+qve-~MRWww%Ngeks@sM_yL*B<{PRJj?Lz~@kbC>x#GpBc&0cEq{+r~9 z;9oM$9sR`W=HA*ZJ`NI%T|O>s6R92sx6F zCr{oU;+y7PY|+9jxLEO=hso%cUP;qDnH+aI$y?20L;I*uRDZESU%clptL-^v^v7WC z@aZFunDE^tTGq7?{F?s%0PQemA88S~__p1%xtxFkG2|Xv0M1-;d3}|^k~)z}5NJ(l z{W7-VS?7~{-KqI2Q#$_um!34d^reIM(TP`tt48=uH>X3Agt%JrLyS@aUp0A-;yZ0J z+Vzsw#XTE%tu3NgRXdR7SCf!?o#~a;meDfLHE+#tIbR!hzszt2xTc_&j(Fln0AlHZ~-L~b;@NfCMVWkR5G9Rcm(k??@z z-QpxSmp)|kt+tcpIbKPvwCA{z*=^yhi}i=~C2|l|i6qc|&p;`bN_#XI?n+&Aq3T{+ zHyTc+Zl<()G%YkzN5O{m9K}@oSKgTpD@bor^KQGXDvf(r)F&>94NUB>!9@{6tqlPB zPji)cQ9Tj6TYPm&C)d>?xTUFo^PN z$DEyu%k;nb#-zGsdyhBha3w%4_ccWax&EDUpAE8EUv7R{`FqPBlz*3AcF@35aAq;X^=(So+1TyGa3;0wwZ_(yu0}+=PeIbSA)zp zK6tf);jP`0NbaU|jny1fgYl6{k-ay~mPp<))|?oc%U(|l{{WR!t^S*DC;6uT09v0^ zibD(*(-~!vq+`eTK#(i$2QJyG6N%hA2|e4)T1L8`lUEu*dEwUVeDe*0+$+3utn)~) zI+s&WO+Y*J>(e$GpbjuggO2=9gT}PK$}cc^lU_bkztpum?SJbZQCJ>HXP26}LKHbP zp|8kqm=UKkPj&pN^Ka(QkTmTl%DaP{Fb5ApA4mmTlfq@7~ppMtyF*&)f?q+%#Y6vGszlk`bU~>th8i?Xss>ajtG@4;ho`MPvH28VQ44KADcS9t*9S0OXbwQ)AdP}W4nc|uU0-w#061Lg%~Lgwd+(dY>R3ou8TDcW9qMFxXn_Q;xhX{|}c~TQx{{Wn9{LbgUPE z^*PODIe`{d1Spb3CPZLJ3fxTxN>;dh5=Hb+h%SrLSMv+a_qrY5lyxiQxX^FsOVy5e zmP?*W;zg~=CCUZ^YJ6mJARGe-8>G*RjK*c&LNyr~mABX|_ zJ`_KGC`k1>q6m=uGVVw`SP{15Y-#WGVytTEAb8&52vEqNAZGYE3U)N3f1daYFve_j ziS8chZ=`=rs*|v*NwpW9EA#$29u=peO>qyFH0U1b3#jzgXNV1*kB-KbJ#s=SoJA$T zb0fl!0RxYw{{X$>!>w3Te+)E&P&cV6K_DPJpBJZJg!I^b{c%8jhxx1j06CSS`GfL) z+x~IG$yWEte@W)@w92H%m&PxdG^R*zm%ex2|~; z^M79Qf99u>zcIY{mpYD>q1^hGwvTjW3_`V3NWnt078Eq7_aM+vbU5Q|Uzw>&F_uW^jpC zr&GA;*A$Qo-aqF9e>!w;$uG>mF>Ak^7P_VM_qu%1J>HxI*HO&Ut2~Sgp^+q7h7~oa zYHg4$hmv3a0697N%YWw&KHdIe`AY9nvC(x&qO`S&C;FWJlo14pq(rKQ9U6j%=Y%k) z&9~ZKqomypPVvdPlaObgb6Hoo=AyM7K|On9*rxt%^B5bg@x?8 zewlBmUfj(LmgOwCIX1*QI1X2r#H+{b)4l*VVt0OV-dXB?Xt%T0HLJV1F9by+c6E>x zRy-JVrywgszm8Z1qUo4vHy&WIv6OjlSG}{mojn5L;o`JkP=V@ERDiplRoOn*OtXh( zHVJv>~Mc0Dr|w{4c;_jml} z2mIwkzw?p$ub1_oBI!DZm+v%&nm3AD$fkLX$&Fc&lA%hf?_IhcwaLU&5cs|Ud7$bN z-D$TsQQi8%{vxHw4O*cBoS4_*J9y;75|8}O)O^+Fzb_?)g4`vBkgaijrjaO=uOmyR z1p0C)uKt*!63kQ$!O6HrG681)0P}=@^N^a){Nv`kdFKmjFVfZ!TTKnUr1u_-G2C2* zS9IhG^C*B3w;@WAwo}8z+a_cApZSk-`QfhlkIYw4M+|;ox3`Sj%+b8|&uhTM@l8rb z11l*5tZl^QfG~Ndko8;NEUVlTs$SixNg{1KQZ}d~C_^mB0rfsFvOxp^PMK^)FfX0| z05a@#YkhX-R@d$>FDATmGTvObDP`mV_|NlGwqxXu?Xfl=MSe$l!}AyZan{anIQbV? zyU--o(QW7SJs0&N6*2OPMRFK!Rlo#SuK6JwUL=0C=L?U`E6dGa&QeLMYVB_ysdsYh ztYL@YR4~RBACL2F+n%Q{oDTdi2UGcH7zZewX>R=O4=m zr}9^owT)-Xo?e`-+*%#JqAu;0DOP~9FkoHOe01YR>?kQ^Fygn2YTiz>)h;ddf~)mg z;CUj>#iI1viC0p>hLqa0r9JVaS_jTQmjVqSs_GF>s9S#a*48_Rlr#z`=&D(Qx{5FY zgNP%oGBO)75=y@+JdJUwLpPclOGuSNMQ$!GOl0$xX!ouGuaY7ik@zm#r=@q_?}( z*4`LhjDKoANaMSssUVK^$$@Kc8vMcXTv{ff6KJ;(O$FSBKT0<>hEYwJF{oCrC1Ot1 z727M6X_z+jy&uZS?sAkbsK(4b)R(k^-1em-CTA1fCi>rxly*YUD96eTUCCH-@*J|{_5K0c?%05}X)2?Td?kO&PC20(?x2p_b zQHUb7F`5y_wL#eAq%0ybr<3_N$hvl`<_FQW-B#KQD|5+ZQ0^|2Z%BfJQ^(@ol<0TL zBOUi_CugyFkMvH1ZEF{m^;Xp(d09OPEtMjMFtrSzDvGh&-+a13tQ$gkYVmKSXTG|c z!U!3DJ5fdo>OuHGHQZr{K}&q~<^KRG-dIHD@$BwV9c^zW63QoJ0Qz#85;prR2G!|I zjKe4u-!~zeSb0r= ziYk3(IyrM*LXKF4`f!klr=DG(MUufTe8prgF6Azq$`4EhG)gESQk`frVN1z8^{4qp zJ#x}ZU#wZh>XgEL9DuYvHpmsXu4;Piya_D#RxNR*MF;zl zw46ky;shWNjTjsx9hh&^8FEZ{zHzwn4dwiwrgSSyl=98QvNg5Mz*?*U$Q;Pnx`08a z+9IpAQQ?;Bdz>>ig<)x+SQm_lxy17xRgI4z0Xxw6bQ^(}fY42?wetnvmQvdG(n+Dz zR%s?lttWeFBRqIjWQ>Lz5)BCJk&t8x{YT8VzJ0UQ*UoKmsJGR9B)GepOS$3U`@qpW zrMLh`#05DHxBy7m^S_ofbeB@Ki&=(21i-uj)T&BO7h` zjDu*=dZ_9*J!{|q#~4J-vrRfz(_w4XmH8?72f_fZ+-pvsMq0!%*!_-(1?;z;7-mk>!zU03M`{OEKIH z$vwIZfeo=N#@2Mx>>z^L-V}_-8CEE~+%ndzdJ;SQ@?&O+b53=APIR_iChj|DY0*Ow z2w4&`LlrHtJct2-+iX@Sc%q8-f2|nFx=4xUltvN6l^_vH4l6<1d_yAo8_E`Xbb4i# z){kohQ(apv>5sZdVhw5Y{e zsQrz*d`ExBY*j=t8!$Bl?N7TESyIhHE6|PcRZ39rxat7KT00V;Z`1v}Ri{I;N!MzR zmrPQIew951M*jdlxS@yYlQmqh`&F-xwKB5EFuyNDYp5@obZgt&YXhihCKx5Vlt&v& z>#Oku_n_&Lix~~W=bcB%vsyhSztde+xCTq5U`Xv=-#(c^4oE09@;<1@ZevJV1+8US zL5x$c#5UUj41r5VhDqcvEWoWQXB|h;k)~Ff-RTyuXKQaA{ivEC{-tE7t2K6@#*xI6 zof0bl0KN9K{{US708DsSiBYsz2VF+f=q`VT4iwu%Mz$ap)UAbRdN=gPg%;oFYa!QE zxBmcvf9a11TUy#ph!r}NC)gvO;fI7Rm67S%dm1*NqyBk5JS)Vh`ZrDjr%_*!h5rDK zMwZ+(?JRC}1}EAE#+Ql0!%C8g=oB2jcRt&8NK7e=Izcrs@*g zeOB3Tp`Bs465iap{86iwCxj8D6d*gFe8(~dHGNz0ju{kh=P{C7KPPH8_t9Tp+-Oj& zz+4HX1}bkM1k#{@p!id^M>MVg1;ep6`G)sP)P<$Sm!@hd6}+n|B1;H%P~eU{>s~cE zj9jqwFU=3kUp)R|>8WGojVDsnbR8xu3rkCQ?U}`r+s1-$C0c^g6)Xo}S8T30@7{n# z?ugX?0Ouh805$yE=6zRK@?Vj)RF_z@w6~hx<4re`z-^J^6T>MB>Bv>tL804f91+7X zDw&wasYx}TK7Mvda}=7Nm9PC|zqQm>-c2PTtoDEeVpfa;C<0O_U%AOk6o)a*1BCJ{ z-^|`>^Us<*v8dbrY3Y*bnx4O`L8wU_Hs(8Zjx{`@MM#JdK8twF7O-665-)R~~mv-@_Np`Vli2D@gRyF!zkQsh@YyTV18P8=gam0%a_ z^82>TbE)AqPD#TaObv&Se<*y$zn*$xub6Z=Z?3Ilwvshh6PtfhITQ9pAE+Z`-|Y%z z@sEiEE>zci5~remU4DG|zs@pSd8b>{{JAcLsU(se8uHWxNS>iWxLSfb{?K8wb*RMg z2U6MLi0{n41pLhMifGzm`M&b+>o=N)tEfT7G5eknNI;S@ci{E-RE?=j&5V6EtC6^O4797 zAXwP>cSF$NwbNx6ldNXqc;Qp(LKSEu?x59+SC;vUk|Giyx8D#95A#RJa{hAp))_xC zbvqkNNHi;h>FEp$nJv_nl3I_qDQ7v&GW0#a=jV6Oy!@s?Nb`cQnhi(D4mbd)jl)!xk71k-t3U^G=)PzsftEUHq-&4=<(N zwD&efmv@&I)#4bPf|e&>J|?RZT4p|3cv3rClM~`ZTiJZ+rv6rbVB6`sX0PUbS6aP^ zk{Euq=my~_0gQ~4W*~i<`9nl^`}&pnb}K>%lz zTb2nU#t$A`MFHu^mpyRj100RE;`I&F-^^VW$MX~PCXMC~IbG`(dU{J8t+}_3E&z(L zKn1Ho(8uCPeeb3F`G?#^Dg47bRF>r(SfT$llvVNHmur@8{f0v(` zujEfWXx?emN}CmttnR%-@J9vE^yJv|3s6t6IRQQsY^NSLkj4K1HvGM)eocAj^q!8y zM+Mi{Y-fx6siJ1)r4Mx@Bdf<|$0FIL%VLj5srmc!BGdCu(%Z~7(IhfS8k>bfx=a>~ zK1%IwnE^UA^m?zZkD3*tq_J~*KT#m^{jXztN{{VFm4NBC;NjM1% zg{%EXUbU^mn4&>Sv%yd+u&sUe!D*tI+MhDr@>@%YBq`U8s-8X-_;75Y93t~l?9;+p zn}4C8{{W3~*-(f4P=vqMp-s0U(GTks#Z{jF0L>7uD~s5cF|cE27hevab|^+^_a11O zgGY9oo}$hUqvkLY834-T)cnV01KnLr5xTT?@D00>LDvzwBp!qLf93xGHGXL7Yvu1J z-0Iq$+XCh*SmB5&0lAh_@W!LN9Jhp3wUbZ1&yYO3`2h{L<$spvx79y9Ji%!rYMRkg za}Sqvr&H_7zNX6~M^%iK4I?)?1OPTxn@(ry=swcpXV1bYJ|g_zxSP+@v_F^jlihhk z$`*cv96=`D%>L+HNWbxPq?15TPT89)mchiwAs3Y1}gG3x@v7y`wRONg%vDvWY2a~|O%jLK=6lHP3ZRo&sBd;v3Lw3lQpC{?B zCQ^M0;#+9B4^<;IiGl26ZMW%_n+=9azo(9_?EYfW^sCtoS)HM1Tc=8|Q-LwrJJF-i zm7~0e%G!HNxmTK5ULaS0vIh7PNqWAG`Lp?p<+xtU$TqeBfD5hH^PP%>6&9fV6X}wO$X|_gulLz$g`4DUQcjb@!Wm^9L$+4I)lgYmJ;(gx&Z`EaqZTq;`Ab@nmRMNs#@)#UYvPA~;O4to*%>Z;#I~~I} zz5f85f%28(E`|BM@dcsSm zYTuLkY?l}QSM$}qgx5@3V{z-er@=!>5h^`_reNxEYciTR&)DSRmI!hyTk})$x66|H zdUmNkuXy5w>GqS{Ng)HLHwXoO?2bOf)n(@%A9|ZSW~={?>FlA7-J5@nk$lyQ8Pn_RZ}8^6f+O2SWV2(k_25 zzahlGSiksnKQYU_#lZcwgrA8)CwBSw-#Su6MGvvm7@UUW@m(^*(*ad}$=;)S_@5Gg z9Dr;km|I4Oy=g)BivIvyoiKV=<)@Qh^Bc?-{!xPJJ2@wgS6SpzR0!9R283;mB1WI8 zzm-3hUzvVJ(X_oQPt|;_ewt0YTw3sj5_th7!o9?i(VQRIW~D!Bo8~di5_+R@`K$BC zQMLa7oSxR3&;DJsv(hzhFZo*HeP-PXIhI&1D@Nl^sZ$wZPalT6W>y$jwiC@n1J#cI z0M0IcR%u_Db@P_9b!`+@a=NXh-H+Do<^eV@7<6MsBfUIw8D+p5qXR9UMCvzQQ~ZFs zx4QElouK)vNYo`(o+Z&^vk6v@;1;5*uOV_JLbFc51xN3 zKRh(+DfQ_5yLEP#x=<6_I8^vOUWO@Aim;_tn}P`32w5CGOCvgX-{jx?;?J2ppQx{y zJe93zm#KB4z$Q&v5i23MQ00+GWvbGgy7dPw$|H`%t)>}#P5jV5^O3s0n*5LD`@hP6 z&G>YkTgsZwo5sUdNW;seTp0mLW8#6hF&sb#;conDtl@~uDv#REM}!jj`hUrLKgjPl zd0{-jA@diPJi+Qkdukw6kr2cjNC(8c<1JNY*f#l*slnk31*b`y$G(rzeM8Hik$y$| zyw|lID?qZgzq<1M^!Bmd2qnI|g^`pz9~&K{*p=eZk++hAoBcV^{vUf9I z%-uIk^0(v^-e2-&xo_qjDqk={vtB}t2@GDOaXa!-1rO3P8mxXEF%#d_uN;i>S?+#! zzNxQ6<|uVYb)8Vn>am`AH4C=8`!q(5Ld1|p&A1|)9KqlRqo2gjC)BPI+ItJD%c*qh znZ?DzOK~Ht(+-nJNvlm={YE9LLtK$NQyLd#jOZGtnlxFjbd4ibxNQqn9Cc-uQ!V*m z+@tiQla#5?VqPXzG~A4%!HkWzoPY*IeQ{?dkY&62gqI$>z-E+kpZ)mCTBc3@+4$;f zTIKvU(-XfE9>+=4H0u|>({FVMBD$18aWr?5`m#6%P7)CQrodFT+mDFgIJ?7X$U2ll z+TP1*bnA0}acvoS6)oO&D$<&<FV%Nq3O=G3oX;FI9$uub`0L0f* zn48&=oU4=WFc{M#D(cCvwViiVjvGB+P}GHtFq?Z@VRI@$91LnxijV@a-+}MG32)DK z0EqHH&vR)yCAH<&p(_f7jQwJ0_UxgXivjIWF%auajIXMmxMuS$z|@#uU23Xh;XH`( zwNwRAO@1mU016x=Sz!ahHrXF*qw2av!raFOpqjeUUr~}&p0xW)q;jAe0x*b>$jZj- zLs`=n{lwRx$RaHfis-)!c4Jb=q|qvOU;yNIJK&d^L9m7sW)SJ@WRCLC89hl9l2M~3p@VE2aZWWOp~%xa+35DV zz3r8Z{#~)TnjIqMSl;5zWImM4hv70V{EGG`apRJNkMO4jZ{BRPgONff-SgOyJKLckWL37QB2_NV3- z{N?4Isit0NzE9MeEe30k-AfE|%WG6{OqEnDpc*k(0C-n0B`KYQnHWO1eo1QIm|BL7 zeQ~DSURzz;rNqqz#I};g(xXVsCE~<=s@8;M_E`8~Du?qj;`-tkHEAu4h?yj1h89+> z2;>iHS8?AY3mL!%>3`)dn(E(>+K!ba*|T-?CY+Gn2MQqiIHM*qCz`zrD>RCR?cJ%i(>a$xJ78~)U@KF zq*ZJ8@AP0~g_;Z7#q=g4gHwJqkK1v-`O_6lQo`O6CM-xqJC1{D63Tkwn?%@0X+oB3 zK=opwc<*{ zPcG)2ck$_g4?OcImcgubEx8wX!>Rbg#Ya$kP>Rs_*C8g@9hjos%-G?G?;2e)=)V6}KCW>spQQu`IQ9H`U0?TEN@VV7v zWJW0R^5fL58^&7owOVuts!D`Thr%E*SxCnwpjmcVZp;kOe9EhmO zr5)R1c1^WSFxcL_77XlS;>z6#1Xs6l_hF~llZRobA z1*Nv=vOg2d7Wk?blu~+ZGO!y7O>~`8^j*wXu1X@1mlZTTN#e$y$A61G~fgwvu0HR(SkzaH zgbn_hU{|E-`aSQKwRtQqf&i|nSx97~j?62z`-9V_O^-K)!=`!=TWg-QrbX3$sv|8` z;HIN~y>_Qefen_-b#?t5WVmpP3QAF^C={_Ie;in+o>Akk$Ee#{G)*nCCD7%uZrpq+ zQQr(h88PoP*u=U#l3P+fcQDbAaU+pE4oXq9#G$mUD$`HYwQWAdTtf<5ls6Q2QfNu& zJCjYiWCU3rN_x%AI%UVzFIWKR9cr}Xr)rOuB>|tqr+s%tvDU5Sf@PTuQoujFiIIpL zfgK1PiOIyRy!*^L3_6AWsWbBBXQf4OiyINim*L;U0l&y(WzCh+eW9YyX=N0pV@9%7 z1&+kff!NaxF{U@6Yu3{0`hBg#G;lTC2{eTb5m@kMJ!{6brVCAM^$kZuj>7)_#yhz0 z64E=RhUPv-JAkOvAdykXb|Yi4$$-}LUn*$P=~MZ0TDFMAJ=Ai^>ejzy_;LflR)-@% zGLbu`n)S-sSvBN<7mj+!2l-@>dS<+_(jgYB3`hkwWh_*C zbll{kvgnifpIo-n@5F4wiHsLwdbLey{(IzPX_Q%xg&caGkEUE&s`}2?L~}n0MUc?+ z>PE+WoKRTSy{0$l-#T5jva;LUSSP7KOisso6Tb8#AtrG=o{6QkwYANJ*CnTot*vKh zz@R124kV7t`tn?ZS$I9ZvX>X>VgWKsf9a9eXP@!drZ zG;`>7chJD8D%#oG%^`Z30z?WDzq3U=NgEn?<*{KtY}m|O;ycvty@d@ZK3OKRwUDR_ zCe__QJ5XYU$mM<=>00*N6-K4Y%G~ZvS8^2qUC)0ERaewj9MBb2+?MNKd{qnT7Ge|@ z+?v;@r@kt+8HFfVclP;jil!D&&vferoNYYJL}67+RGxqU4*vix@vA|Q4!*IMPMz$p zqj)DnNh4({$b1=Egj2%_6rhPAR2Oj?Z~lF7GEMZKE^31DXT$P3^_pT0WZuw^!FP2yNhj3&|vhV5)+opKOXa#aegfugh;Vc_kx% zIB7T9YRcSWd#D)^i0elppGRDgiKP<~%@r5tS0v&5eVASzU` zA!-4wD_n?yJB0X=8yC-hck-3Sk8?hoszA|P!6A-FXF{%yyK!K51a>|067=j@iaeej zt7vmPz(o${rxoAs@EKf~Ag0!zEX6srg zJ69vPNj19_v;3yiwF@`Ytt7T{95YWx z29@NE4Xxq6)$XIThD*5wFrz(wIb=U&6bh4x1)mi%Cj6?3_g{Z1=o+nz(fxeskl#F< zZDo~T)Ac<=_F`t-ITYi+OaxOACL1S{ua;Yg;kKGVZ8O`M5eY*gw-N&YSKqJMq3?-_ zNSN<>j<5L@E`@XY8v9tVYvcph<016peThoarj_5lai%9D&wSJ5D~~MR{*CowyF(mu z#c^-RqnRWDm6D(}DY2-nMm#Ixj;W5P`D`>@BSh7;JNVk~U$=Y6Ep5n=;I~PdAZ`FW zqjqH^DI294v^XhFMos1~$*<6sT5hAF-lnq_p%jlJT1O`+ zghZXg9}$>&ck(w&oAUEf{L0idNSn;@>g%Fed1_@bP6NcU{e78@UNEG9p#ZM@x&vT` zdPMBg%kTdHDD{0iPoG@5c$pxU2z@AtGBKN%78_HF@jQ=Sn`A^86HENH`Ewn_vflaD zc{GhG3wNG3k|yPH;exDCf+%WF#Crg7F(?uR>sCLM-cZ+c>x-QdT}My7F-rEWaY^m& z9v~Pa5UNl~xCeeGa!A2QGI-9T`FE*l(Lr^6Z!M}`DU#Sqgb7eFLh+y4P{WBJ(ztk6 zi3MflBkKrmiBkI~!?k_R5f$QR+6IW0Q!Rz@F_NUmCe&(m2EVo8Eo6Fz_R;zqeU-PB#~Oym{_Mss;E@;@%}j_Ei{c1{2yw&4-$G{M<>(X zXZ(kU%UV_bp<%CE>UxHWWp90~TYXjFSYwn%C|hiD0!z_9IDaJ|{FjeT)9$CZ z{WGY?>x*lPVGuBZ@k|+6hRyJp&f>MhIF1_|tR_jPfZpBP+u1wWK`g{u$uXTk;tGOF zj{UP7xd2o2$Mbj0{!;Q!6Vq8IpE^0BaiOJ<8m^1@^MDmC5!}* zU)F}DaJv4XeS37Pt;eTHs^8y8W^eS-3t5P27t=8gLAce2Q`ZQbn23OtesKAxL$J`i z*W~+c9ua+SsX+Exlyb<|2^6v~HJCM5fL5Y#BAs~Ge2gS|v*8^d2kLOcdjl#;CO}oa zNL%7kIybS)Q%Rn@x`aQKT4n8mNixgkOXwuHd5L(#Dv%UZ09>sJ9flcw1*#Fek8$#) zy}Wu=gk~h>Eg=DDD_%S8n!J7Pe8U<40Gy1un@;?(uxoZ`UOjrDkd+jcE-z3vH3FHR z34ZEd2Oht89@F_}VQVLp^kVTwf6(IU1w{w(%?u6v%e5>!^RmF%d1p+xkxHcZ+JuM+ zsVm5QKz0=r8PQ?i06t;T&-=pjU&wm~)%??Qr(2Qg%c1IOl_UU6R3CkE-6{1oYQCFM z{Gp!O=Tx>D?V8>)=<)hqtp1c1@v&U0K5gtjyYaEp9F4xb(d_ z-D-;xIR(FJv=kXmr|LfUARkEgJ-5r2a=+%}?uf96v=-yS7q6LZvsX_P;QK=9p(Q3%ndJG(Cxn~e>Nm5q}c~uCsK_Gn$61-=}JcJ9{X49 zjk*)YNQrDuR((Eijrcu$SNM#Kfk;$G($$o4Ur_ssSMSJCPY_RSH7Kme zYh^|pg+jK&zyJ^VoE#-QL7!>5mZlMIA=B-iHypk>jcM}dksz`Y2>E=$c+38mrD^m& z5;aHB%;2Q)IzKk^rL1~pn;Mf-!bujs=8wJ}72;NZG*3dY>DB}e{M`NIzWDI35*YcO zb^Y7eX~2=vg|`0yg2#b)lKYGK?vR$Zv;dw}H28i(xh@28BXs+_Thbztts(YmbsdKN z`($`miR^w)u>7IZNz}hN{MfeWhnMKxF4gX5Zv~=|EA-`q47v+xoco_?d2`QtoIYOt zCHW`i)%>^eO0O65kDC@Xx{@+}6J=nZYE}ZO@)oC2nYi%8ZzF!^6DEEhZWh46KG}3V9~e)r~DJM3cJ!id~IQ(rNQ2wn9R;XA^AK{0^3?vuc-S z83FhL6#yRqPg;9r2Ow+^D;vt!JR0jtovx7qER4gE9m0{daEyT_34OdU%O9?_<=tDT zBUHWhU(^5p#*369Al=d+IS?2j-J@GNq`S+JD&5^u($d|aba$t~HcCJ?!r|b3_WAyD z&iNB|+w=8!#&uoyYg`aZS0pj{Ek;;Br&lxgLu4Os17>KW>eHpnGHb@E{VUJYBRENS zm<7@)<)OnY{Qra?=;V3#|C>Ww{r?F;kj8xUJqT3{)1D8XF+m6UZq(fkg&$wBW(U^* zG)Ve0HGb0y;*)i~48GZCXD|zF$zh5{Su{980vbBH{)ziWf2H?Mu-2SHYh&oF4H5dlR(qc2`81g?Ai2JozA#kNW8fZ4^2e0Q-y` zXZhpDPAkzxv0k^X4+pr<-Ksi6@WWm|I=W|w}b*wr3wr6K>FJ4#8`X~SR2 zwZrTO7Qp~Bv{kYLKA(MqmRONSGXsk4w63l}3>DtN<>S8R^|j@EB;5vSv(7rf&`K6j zP2I1Fq2?C{MV6m)wA%r`KJD#nCHYz`Y55_N9WyU|hZvu{{=-o0>1{^b-ekkI2`i(5 zTD8)Pyj%0Xy{$LV9-8GAeV-;+E#;isjK~-apBUhx?WMGPIRSOPfM)^%K_rn0TJc?sYe{68sWj$sO&z zi*;9k9Fy*@c-)k8kLdRw@g!3|Zbi$rq!l#N`uW1uWJLI(@T9?l4{*ONmrWN+Q>kWg zuWVOU06#@(o(;HqW_}z@bV1l-zY&;v-#jLsv&rDH=sq}-9Yk^2=wCX|pVL-EvTX|T zv5M55KlJlAv`E4|Za^ycC~BlW+pje&{(vMy1W?BLKeDVTa0?>+4O()u%E3EAL7;yP zemgq)1LAULKK6Z9>S&?sy`}4be%qqtHdNh}UtPmIHznX|v8jsM~G zJbNowF=CLzKHX3x$nn@Sqw#kg`h%0KcSNVlEO65Col--#w%XUk#5#%3 z0!QRH`ZG^u&}Qj;tDNjLG$iSM&#I}rYoW|1)kWMX|4{7S!MmSE_Uzmu8tF$+)-wJ2 z&BwfsDC9J98dhN39?pl9Q5a|`>{1eR7N~PuJ)zFm-?_-fVqHOPL0@|VRgo2-Cm%9| z)lK=6!G9P8C+Br$2J<#OOyE?#zOEW!)3AlVq1Q*LXJO7_WrnZz?w%nRk)M%OuyF3m z!sClq^gPpodx}r}9R;@^5P*+mv_%qsKbty;)W$w)Zhah~!-2zz$+1sx_uj=r%+R3+ znuF#6)W}j>p#xjd)cJb6qCYmy$Nb79-A=d3#qoHvd!S3XBCmAD;*EtUnmChn%+Izd z2a}lPS6ZQp<_KC_PVv36A3;kMj0s0HFtRJsBepVpLgFw)*Mwk^xUk`SE<5%6f z^!=1tHa4N4R{@6IJjLGJi@#kY!GR^g5Bmt|7GT7sK6OBSz*e}SYT?uOIyr(D!uZSW>~A}5W5xDYb2v;eR81(Jp?!zm4VJnalxy+sr+p1rN$}~-@B)qr-edw1T$jUl0H=h>n`Fu9iQ5px9D`O>=Q?mXi z-zJ5NF?SbaRBVsxL3}f@kb|iD_5Q>VB~_^Iodi~9!N&SN(Q`i=vUV2`dhRoH(@zDz z*UTuYf)q?oaO1POM00<>Qs@l5juwZ_%oH`2RiSp_b7c@1Dj!~)8IuhxG}CPjzECqe z2*CF4`WuUt^*;Ef!dH|*RsVZ+=U6Ha64B;Pm_xh6I&DV@a8oK+C{TRdOVuv@?Zqfk00RE_ zShfPI?iGXUB&g`io;8qtXr_<&*xA{EU727jiXj#7LdJm&U)y$oJGV5@gU@8>({m=A z=dwKQ&hg)sEA~{dIGrAE&^D2u$-LS1J0rAe?qOuCEK9 zAp<-Isk2gpD4Vgv4F`(e;)7l%mNUL;zppekjS*oNZd|n(nvnGW2eA+0uO+U=azE4?xD8zGWLY3C~w|x`YD1x5N0Zu+UsRe4w0f4oK^|m z8=vo&nGEPRI-x1~_B|^Vi&vv8z4Er)TxjA$cs|7XjcTxP*w$#~97M`7= z?hmftZI(?~k^HLJoLu~WqiqmI7i9bx#j+F+UViqgSg?eMP{O-H*>~B(=ODV2)if3B z!EDpQwS*c?e`*%43-&LX5e9Gn2FO6IQ-pIj&uF0@ZthH767s2o zioR`_MD@aVmF)3l+|uA@`U-NIE$lgqU2}BOr#~{pH500tH2dlNjxnH) zre2$$Z_-V%1}T}A1_hSc(S$*Vo=~{?H0(bNU86ksjgFGe3nkylPmS_gx95=v)sr73 zE2i73OC!RP09y~?3gZlvq|Y0}iN3at9g%X!*3|C_pHBD7e6U|d$MBrZ&=;#3?+YKF z;>T4;SIoAr3yff(4n6#;Hl@bhCI|^!^*;e(()gHdUu!xn(sy8gu{xf(%1YMg$)<-H zIs>lU<=E{po@t&%mw67-@TyV4hqbcz9t=M`wf*TM!P!5w!6BNj2(~58%c-xI(E@+4 z=wzk8`Qx)0CO|{49iiW#rs;h)^n1t5#C6T{&(uSm*0KBFT2ij{3&v~=XZGU(r&f2% zL$2&LgTt``!Uu?Bw_9Y*`4gz8V~Mw(mn}&BC1Z4%e`W?V_r8FdeJW(gKFu}T;eNU} zmkVE!gElMS#pbGA*2gG@e6q=TmRG|p+Q6g)}j@>v|(g|9B(i;F-2YVpt42C$JVYmpKy=$3uGq^6FCE4$t~H$`+|enc-Zd9Y=NXL>*&eS1b})oifGyp% z^;KX5*S*>7a%}PI#}QvPy?;LpsxLVhd#;J0ahw2;6WTX?bJjq53BM}q>_5vOQfEj+ zIV0c%wx%+>*{X8cPg*x|y+XoHXs~hvyq;7@x1Y@^k7LzgV2+7~{Qc*i@uBeqj`0Pf z^2bv>N{iDq(W~<+iTvdy&;4@gpMTc|a6)OO@F0A$fpO3B#MBq;q<77n4CzE|c<%FB zWBpA_0HgfSNZHD7nYy}&iL8$N#2ve2K~7cMbz)u58X0sNMaqw#&KUv3PDfBc2@pe0Zx&sL3G_O#mn$FZbAUMT1n(iB*Jj4pDkZ_ln0r1!a*3 zUmEGLPM)fC-w#@@_Z!VpI9j?zmS`Z(hV232(!O|@JaT;^-v*p9lW$d3-s?prvJCR4 z4|<>Iwqw|9uwcZM%>@ehnW@rG21h*kh;L6wTP)qU@`TFo8!SrMtJHbuN$_;rvE_M$ zyB0l4=pO)Q>P%e7X*nWiwh0)ENYsyeJ!dtI)Ko$>#Wpl}A(-}AD|Iu;7uW9s%u%{b zxMF{(v%(h!wGJHnFL-Oolxi7wE_hNct^99nnEXApyISB=NS5gt%A&@c zdQ^XiFptE$e%yi1;GaB7ylJVLW)T7ss~Fc)2*M8cQ6BcIr_eSyv?@o~tSg+CQMFf7 z;;T{XSq;ZZ_Al&Y6V_z;A1L{+QQTp?W6AFVTbq#gvpJ6cJ7&sH?Ye){RFiOZ9ZTli zQ)RX})3rM*O~T_2Jk85UQr_~Of<028T2cLNE%4+R=%YUT-*mbnFK?;y8uiG37$1V_ zevfwdmBSr2k|W+i6he}(QV-4c0Z9Hiol}C2MYII=At90@y$l#aP8%VQ872M0VTkyq zD?_>`C=hjYR}T$NVL!b~f3kAwDXQ|&thlSGZg=SI1E#B*-TV9or|b#5PIBTDB8r~Q z;`#)SZFfSABlBSN!5Ygqy8z(9%gRE>k?kR7d@^A0%i2_J?huo#s)&@_vcY2lzwKSe zSq5i>Wrn@Auaxxnr5$eFJbRW{vD9a}@)+bZZqZOJ*$wFe)IrC}!Fpe5jZ1b1Wriv^ z*rjsf*`(#{_d3ja*~(wH^@0~{@7f%*o{x*>Pnm~#NX_TnOoYtxuhuQ?jUl%<_Z&NA z;go7#-0>g#UpA7qjlV6k_LF7>&ats>eE2B zL6cVn$8>~z|Kx;DhSox*O1eoly^mje(`VQYmFOQ-CEL8%_Rj5uG{W9w-skhDH&oVo zFHFVeGVa0)C&{J6J@bUdWr1Uc>a+TC@h3rKOo!W;AO*yQ_Uj}O%!KwPC06-0U2XAL zKFJWAV3LCc^+n%u3qz7$Cwa5Q7ysvOWc}wE6$s`cLpIW z5kk0SE?!5K0;w5OlH=dOR(f#$%)VNJd;NXmY5xa9u`&T_rt}ZDaoe^`EZ_H-{HCC( zB$~O`Q-bW$h|U7Z>OI3wcnb8ctll*zP!wV1A|BnZ50v9f9VQX})`HR?Uo7xVD^gEl zrDP$@nHLSSNX^)TO1OO)B`)+m0=?<*3*&uYXVoo#6=X??-131k#b)T&) zrp)yOUTCdt5y`)7;mLA#WzCqbCu;hcLb(!=&E_%IH;r^fd+wioJ0n2`&fIT>dZ+1aaAb2&XulqId>93DQPD1_Vt2Wb2f)@AA!sW%!J{nfe-k`+1k+fVlfmQ0l|; z)Ff8@f7MACw*L&scOcQ+dmD*g?mq5xoMI0ecVG&Nq+u>v$d>3mk8$IDXw}r#MVH3c z6RGrjYDqK-nD6At)=QB;PwC_?d~8t+!Z#ib_Fz{Bux18UP@%SpwuXqk!^>=|kcW3Io2;B8F^sREf)5SKT zba@ZSQWsFl2;)YVRhk(I9ng(v=X$XV9qL@lh8cvQjGvR~pWb_>`ux3AOPmkOB3HrAU|dl}jyNI56?VU2b?H>5JjzGA0kO8~Oabj*mt ztCu>>>{yUoFcQC7+b&!yc3Pq(or+Qq-Tq)ldD_rZ4-q$@b?=$=LXj1SnHJOkhtc^` z>u25>EpSUhmUeA|c=oh!HY;s2zMTNcz7A7$f?%&4DK*_&-CM0gF-vw?CEIdv@ywIm3ZN~)6<;}PTBX@+Guww;udQB%F@QL*Ttz1ot2#^% zJT|-}8sPlzZ?<2;*-82zkEk-+3D0()lOMj$*FkT@DWi@VIn|}hDD&7qn|x8?Tsq2o zde%u<7Gj>_#`$KmqZb*7j0*S<cKQsu#Y6*Isb`mi7=#O-4~a$ovS2^nc8{f5$zbGR;TW(@!)N zo)xBpt}YyXq$_a=ykjskZg5cWQS@qhjY>*wT zlU&LG`_@7RrDoQGL~>iD9&dm!v07fIcGf_a=zbh6HL(;be1gqSNqrFp9h62Hn`3fj zUd=e&VQl$6fBZEv2@RP*l@|O29z=YaQE*tmsi_?Nfg8ZukSeo+TVPlzu1Vl z6@BtLf{#z)`P9FnXiGJzGFlc|MIfKJh60XV zA(4HOVfm7~1379OeP}uIm=~=A-Ovs4GR|Bu3~g(!{^q+l>7DivPo4#;}^+=fn9Aqt?D6%z^z~#49b6pgYz7PeUwiCzpVNMzYVT&Amvp@aNa30z?_wn{7lm95?GjT)> zN2&@SB(B7{^S;PNXh)&WD)V9Y@Y>noMX7$?2Ul5Kp)PLS%DaRSXwyoMxr^#4baU}k!M8VW+fb~m=fuvK2w@YaN{Spkh z%0`t4YdRu~W~40#mYJ75lKShTE6k$14*pfix9u9c5rPdfrwuD8H7oa# zVIP+y^h(`rR`eh$30l(CK5Y;#tJWKb7G=W=MI7n>G1SZlVy4oO$J2Z7vl^1?p@mv^ zhZ5f@dE1>RSvZH{RlEnejf9$aO3VQ|JHeYVsKXdoLmZ@-?ab02wY~_rlI(U5rY}Ly z(JO2{;D@T(mrWno80~+2cu`tu0~-(SPMuV)k47J`RKtSM&4!M9r;|wQibuV*T?g0k zWE%Iw;?tkLp2)SR{xI%IMRxqq*N>N?cf(qMQ5so!nhg{_&saV_%HcNONK`l-oVjqEGK4#ecNR)Q>%dwM2!$r2 zj@D(H6{hZF;9omo5a*Bd%FM=)=mtCW4|oWd#iK(Ucrnbf6cSu3<#IF;=C*>Gu9>x^ zfZWq&#dUnR^C41Z5@X_4Xad&I(2JOOW6ILq__Wv@5Pc7q4jHaG1Hu1IF@(n}!yD>@ z$+X<|m(!oCd$ImnVXF?Txu$7fpNgLARTHa|F6l%6Lzbu-X@!*rVb_D;(hXA!^Pm1K z<)o%!@=sOYF(*{2Hs8clNH}~K6giI7fuRo827w`?Rh>`}OgPc-{-IpjDxb5Igvvy= zV2M!aZ-n4AOF_+S4V!wPr9gx=BgAtiT>2#Yp7?xEt7qLVdRs@GXS!E)4L0c!K@%RV zCMjS3$9??w*UaP@_GnhGpi2b3#B6x()q9{}IpC{!Jm>#?QAVzXD-TrE0ZJ z632HqZ}|763)QnlEd+ z`i?A~2@67vWz0S~EryIkdcofo?K-=t1T0M}dR6KBugL#SSdWklRo0Dknj|U4$n_}a zJ_DuMZgJ$XF0?TM&U-9t8=Q-r5PPM>2!~Qnps(_@_hebo);l@lN-bs+3i&2-;p#)J zO1Z?gUoG@x=)HMs5Ejsiw1!!j8LdkeSDFlTQ>-Lrulu@?{s65pF28Ir=o}LJ-X13W z*U7oagt{dWTQerwX)7$l9%+OgFqCu8Q|7j!t0=N|A#Q_4T}`(d%6RTQq};E&b_*_u zxv~k$-4}Ck2BQ1n&!JcOlE=_}~fh0<8 zKKA^P7`M#Dp8Q{h1H0Sy`z2s#pc$&6W!1k?NXfU};LNmlkI{7NWSmTiJu+Erc>a;)gUl!+U!ofWM;I2#dzV4jt>a_kxc3_V!={P#)&FPJE2kn2ATb#RcC zgzMH_0rVfM(DrHVca^iP#FM^!G0a*LHE-B(3=0)6^z_ppk3vm2P*2 z#?tS~)%;L#(iYzA9b@@1C3~ibX>YX!TCRo%xy4Ky8R~{uD zsj6gEH6-5@zt@i+cn#u7#5)X{Y|#ijvQIAmO4bUffoe;zH`HQNZTZJ8!`K~+0ZSY* zXFUKpdL>E0eo<$;yj#kkLTnq64lGEx7?D_*{dss+k=^R$+M1N%k$PJmORH)+i`hbr zlhrDOleYG$UC0+1M|_52dUZ9=KSP8Dt!X1-azi4j&g#$5J#2Hup6pA@>o>D<&aBT! zl7fh-vWFrF^E`G$AP6D0vo8zkoR;hwt~}qDyD%7lGTg73Qp+)Of-G|(X&zcbLSt2b zZK}~IrY&{)mDeh9pPjz?B+D(t&}%QanqyZKf|-Rq#a%MM0prScP9v6In}=r7^IQy= zt~#TU<}G>y$MAi0D_PO)xqW~Cmub!F*M`4{jP?&2_I^Mux!e*ZHaQ9gkLevyHOoq4 zt;mm()2}@UwlYNr4R2UVuzR+n!5C*V2CoNbSi&mFhJrWHr^+QcnVzCm{AnNiDdxYqm5A%_z7{&8gnR!|25m)T}!Hv4}{( zTE2@3`AqQl2bjJ-@UC1s;0RkTgBSIggM46%MXigZ0r6!#z|QvXac)G!45dzjbyU& zF?#n;ZuLYCm_xODjX}blcgUXN8Cymany3@nIfR)xI4fQ*{eG=Ioc~M|k9i=Ox>DqL zMa4o+uZ2wE&stTI_Hta7P$GX|9S8}6QN`2n?rU~O4%2}oO(S31X)*ECt1ugT4m>8S z)yL3NC4dX2jfzy)!a*)Dpiih5YZkjDU@b8+rHt8NJ|XVZ@X5GmaG}wEt*@nHS*bj7 zo^7>iShm7|Y@+Z}CBqxxUQ#%J4le4Mc z54M+fVoI$^j_{NjfU`vJX$I)WB#Tlgi5FFvoF>nWU2I1e1pD{sATRLZ~8*!v)l!eitt{{yS~3n()=O zE&ay4%}}^NNK`0vzV^(tyhD^^YDhSJ4C?sOz#s+#v;3~QlIEp7nHvH=D7WIj!4fK{ zuHdo$vb7w6SgPb?pfj$FsS3xP7l!%`9@OpN4-eD{Wl6`#|89aPU0iki4=Uc zfr+c#%)CxS%$J_f}{r~Lvy`!F6(>*Xk{ea^u zRcY4D*E);t&^BbRE6&x45T24_H0&lhZATUyFU1LMjt2ndN{~5A+(N-Gr#1jUM>3IzhczUE3gnGmAWS*v-|{Adx~z)a@UF z7JXSNvVfn-S@Z0kcT&ArTj>HBW5201#6LnuXz1tVzW8d`I(tG>3PRdp(+TMLp!a8g zs$McE(g@$91*huL;$tS8$3#%!%H6~`N08%7$k(tBr%x);KN%;C4q<;)G`<9Hlv`rE zIbmMD+6_z0YENe4fI^DQg9AGdQ4o=(3MoEObz*DNRIR^qFKyJZP$Q_Hohc^05%A5T zd39I+mZJA*<)SXpeYsu#n0~imSz99U=0gi?={ti{vLr{5?;D&cdy?y&UlrH97%>Vs z*2yPME})E4@%$V!f+0a_)ImML;Kok+YMvHhzZYfSsLqk$;XbIe%0Rr-R{HF$?!6X&j)slLz6(cZc1`f&F-sixK=t_lQ0_@iCU7o-e=!Gh;~ zTNgs9&$JIK)QrQa`?wnR#3g1uNURf`6RaM@bwMZ=ByXRv&j~#*L_}XTKa?~FZ2V*2M>E=%mwDS3%0IsFgp&e3%NC=Z}S zr)nvP2nBUcQE6*NywA)D%H-5@E&sBb7?Z|*YY&|(c3Su0*#{)cX*x3cjsy3lPkN+l z8FP8-Z}HgTt&G`Hs10pYcU~@dE)!9MqHn^b(B0;{$QY&G1)v0;8(S|XM`4vA56y1Y zd)+{(XAMJb`yuuj-)!THC7kvgS3@eKlF&lhCA7J(tw`d;A*!oqX3+X4-D+Uf%wOn- zW$^*es$0hST7IcKVJo02VMi-Vb+{!NC!|)(##BgH>&7$tW*U3gC|Y4Yq^1EJJS`6G z%xm;_b!{bUOQAEH`Wc7&IR^V0MtYVs8jVuft~B<+%{@Y&Vxi;5RGEYP zZpSV0cg_`gtNn7elQsQ@4a)nxwr^?Fu*+o%(PZI>xgd=&9e895U$H-Eh3#XcCbQvp zMT~lK#<=P*{+Ol-yNOpn#jgKc8h1jAj|-2pZmywLLYn^4891i%%gkGp9yQ7m<13$} zr#-~KdPA{n^5pN;(Y9$3u%lIPhF*VfzYWUlQ>WGDsk~M7zoxIBn*U611B;PU7yPPi z9m^k6eC)#@>>)*^hkSR;9Vyxlk963AZz(@@ z3hLHcx~({bl`l78yqEl{ylqWFd?Sb45}p-0+p~67`u(YXd5pTPs;atN2NR^DZCPO7 zRDksg;s~9G1!jcv-?AgHNnEImyg@81lcYL67y;pTEtc$W#U_Kx2fqe}f9(mVC_(Zm zl!06w0T&n0mGHhB7VbX4UjfNUFI9FB$$q7VdfewIUu$WrmPJ&BQ;$coD|M|Joa9^$ z@>nS)?p8L;N*izIo^EmeQ%s=}^~SV1Ei+yAOu_HGV^jJKu-3JDHl*>xoAgUVNo=za zS$bsCKc)aS&uzAsT-hckKC)AMcg86tQs7exS&HquW?BGOFETFG2P@yaDGxwXh!q31GXk-MJY%W#MlO=NC=^ zrZ5eALm634*4M=SmMYe2rSdJzcUp_Ac6)s#d6fNel!qchrbkqge-2GDuy&UlSb8I( z#=nvo_QS`r+yl#yKG1dvY+Xm}4nF+6g3on6V$A4B(bu=_w6ml{z`&1NHn6Ev3lGggbE0TWwex{ zC9MO0N_%*-z2^OKE&HBoU1h0w52!~9l>IG=4;C%-eC1!HUUD^?g4c_D6dVDy7| zjW+;h)aW-SkJimcOIDYTQX(#>BD-xWrntw83eky6u*hHUUmLf!+4}{IxnUs-A=5T- zRpzH8&a-dIxJ~2;78Tesi5OqfzPdRP6=TiTZ!(j7hAFCrW>bb)qqD#8v1Z7IyS2O6 zzM09k@D|S*B`jKgZB}-ABz4{rRDGKLgMma#@|b~zNciEh5!Q@Ms!)PFGO8{56Y-n~ zk=dS)gB`LzYvjDnO_qRv`;JmSGEa@^M_g*#>@UV@zC5|L_s2l*p-1E7c=M{Oma1Pks?~5L)%}0D z;ORGehWHC$VpM5(=mmocw>V|^?AKWOI`c30#-{Y?VV%C-?Bm~Tm>D+HY(I>o>~=Hj zwF#S#j=6QHMu&x;nEF|&_bj&sJF(_yKa!krGyO{N`qjg7Qw^9Dd(2;Pu=GChzJYfS zs-ZqhWv#`OThSaT1qXZoEJ|+Ek!Io<`HQt3vSOCU^f!OVnO`yrRv0q=a&KR?ap#rF z*O$D>&FLlHOk)wdy|=T!pI=VG{g*jLLjECnz-U7PRZXM$>4NI(I}}UbQuZC#e59B_ zX{Fq|LS6N$Q$K$qV(#l{LXaa=GRRBQC%9_~_D*<$*KJDfv=_viI6ozfF-|8s(*F0o zl1PP+ggS%$=nDNX5dDg#P#9And0KwfNg@~cAa709WS~HU@bw`#I3$=bd-p9xy6kI8E17Z|8=oV_XNtp@zG<{^@+8T%HQJiyUu zzHXZ{i=l4?`Y*U_jhw|zFw}X@DT1; zAZsj38QOciQAV6q>VOZgshS?Z6$COmgxNi*gM+6SELS}1cyHY$be0cWKMLa`^^E3>K9!lB*=RfG$dNy}m(zkX+ zKn&_30b4m8S=M1@URm4;`y2{NR%8-nmvJ)SK@cf@87e<)(3E_2PKH5{P9{ImhNE-$ z+&c^QY3$jReGFF`Q(uAsLcCA}CMCTaRzp|^*_Av{=~CkOq*d;|F7P$yGzA6YfRUTV zK-Y8niYrHPb3A%H3d6nP6X-xHX^-p}9<&t(n7IF7KzsAe>6NknFvM@vEzIWDn@-m5 z?sUg1oN|a|zfZ-cPYtQYgGSkJQi(}ELH4FKdY&)$DvteDUNCW9H>H^AFbzo@aBf$* zIQmS`qH-@NklX)`y66>aio^G7@(CKRq>L98Xv%-;VBSLy(sA}lf2FJ=dyF4w%$cam z$6Jv`D@Tt}Pa_BPEPExkci%6_d~GrF{SQyQSo>>Y7Zp~ILR2VxmEc@yrLSqge8F!Y zxVvMjT4`~%uBT34W?tthJczGnYf8yJuiN79mRWIHi78zRZm)o4kSTma4sn@HM_=>t zVN)ucQ{fn(p>2m4>;7maXm0j3M};N0RkIz{1>esG=pEfO#7W&O4Zl_#^*pbAktyZ0 zV{mu1E?CAdml7(rIIe%lPYvHq&hv&%hYLN~nYnP44gaLx9DbclL6s$sPOwcWqp&s7;xn zS#zQMQ~C9KWsPRj{+=RvU}sW!o`0uhM>L`1KZv&88FG24Z92pdSK>7~)0($}JfS0g z%Ya{BfZ!G07M0k(jrhU@_|b(%VpM^9WQx&(RVHKZlQvv`cW#X;hqn9ye`A+*h*G52 zX2p&<_D1#)Z)2_7AwP_yBk}Ld@KoP$16ce}LP~VbzJ;Xv7(=CwS94iflW3}s1*R^Bw|N`@%!#7=z*B|+*R z|MPs~YO0;fwjf=F6B(E`Ptn($)0OV`GLiO6e9`l9H}8?*fWGlW{h7X>H7>q;yJw~v z0w%su_2pgZ{*2u|>P*{raeq->kmt+;cgEu{s!E>Bzz@rl%g%vKCu6E@)2~)eFShu#dc^GfpN^)f`Qqc*ew7 ztU;cMmZDThiL}(Zu)NcFa|8O(xlgIGGx2zArEi7*GUNv58{`dW#*~tZ0dio{y-m=+ zDxDpb?XbvTI}v+(0eEpv-OX&U*6I~rG`?$AK`PTyVbI~2UQl*}AJMzB9^jK}mtEA% zbm%BIWn@dokM-=~N)6oJl3dpTZB*B4$ZVCF%hp|OFw{yjYIZcKxD-%&sOS`X3;SF% z72zG7Hs-PygEN>Vd43!#*&3zGma%B9tt{A|9x?0^4aDXX3}36I^#M_J*`@Zt6+ z8hmt~unf-P9I{wFeM~{MPI8*DJBsmi#s_Gps?l8zg*QmJ?bW85 zY|vY2!I2&7c6Dk!B}hqlFHP5Fu)BHJr=z(L$<0pa^DKaHF{jJJj7V%JrMm#G;QQh) zwcdb(evuhx$U&Bf?nh9eWFFMHU3F{ijE)BUjEzdLkxf#LW8{l!DZ0%HgR{dI38*{` zFYVi8Os%WGLQU}3yMI{YsQ!4M(%q(;9FO0wO7Gk~Rn_c3x<7#qd$_Dy6+iG6dH1Hn zF6Zc`CkfK?C}7Fl%3oEvWp_SrGub(bQa`9)N$Cn_uM2b4c|cTXZS>>*^2q5)_%~`H z{nQD(OJ@6G!hP*az@26YVogo=5tr0G1}AyYnOCiTeD}7C!9`Mm%Pa#R0?`Q{p9|Ao z2pNSHbL`Uf4l*H20asT!+Og&69xU3_wd)9_L!OcR04zZP$braf3uPKLk#{lQz@Qnc zoF{G6kA&GZ%7-bi)C;l%!Yd>dQ{xGpn`G?%U1dz>1QXboH(?D+j)wHCRr%L~Xn%B)O4d?a z|B1HQl~&G6;ku^tDaFJQSSF3BS0S&uvm=Obe5QpO{MZw^sQMqq9(aY7p|XAZWJ-w6 z?Nim7Ou7sr_2C#|PKLD6W)&yU9hjYJcLL7xtJ@8AyXt+I9ccb~_ z?}4%8)ZZRfzLsSMj=hH#YUk(og1eU#u`eaA>7U(K`iUJ4x7KDh`f)E{f^?4_bB#;e zUs;u1QNPsN(!b{toOJULf08eY)&nUHHaovwgJ$u^8y#1H#OBwmSf+aa%~2w#RJc%8{>G+fL)tfU4jSV{o31%hvS2guID(Sa+z zlqX;Df7;O!gl5x~4|l?t>aiZAoDh%S)!UyD!()4X^D3wg)MF27W+g*yU?D@hH5VAx z+)JvK3>uR6E_=B^ViodLv(0{V=z)JaZHV_^#j_i@q^zDAM69xXtWl7tmNYXf?lwuT zgw76$+pwaC%7N+~gr?hc=53$EsU${Ylu%AmEy4M@kS{5o-s2jR7X z08jhR4N*H;2i{m5n~H{q?>kuqz3ks&s|S1E5(`xof^FvlinQT;6-fW@&KY~NQn&Rt zLfcKUikOKlKKg%(%2-n)CNpi%It##zv$TdW0pTNCb`M3_mLlm}&*Qm18A9H(m*UU7 zH%<+ao$+}A*-~EsNFG7UoU69aip;yS>BZd*&0L-MY-MrIu_)}U*N8EjSQFxx@|;_E zY6%=8x9U5KLTX7ZXi$TpUJk8YonM#(3A{&v&6%o&S*retMV3W7vFDj%f^ofP`;y;m zYEJ*d$h9geGD1`@UJ7gTx{zvDIR!lE!v~{e^EsZcnWn^x(g`*Zh_C{t$x_=69=B-* z5LDT~Svte0kVb!ons8S@Qqm1=eP2hw6?c4F6DKc3uU7uW@3$b5&%MZwd8XV-Gh`mx z4T@KZTmWmCX}*HUWZU1`$6e}%wMadqK3ws@7K3mT8oABR=R(PUIX8b)Opi!-@+p|n zpMK3?)7-amgCi7_Z;;c0qShp1wnpL9kZ_-dv@BOnH&e_9FySLLZaXxmRvWWGx0ei@Qx`o)SH(nKP1epCXW*1d*RHc=bCgwg!nx>I1~#!RV|hu{kL2P+p(q%}dMIzn;IFb3vrSwq8^6^CQ`{5+rLl zkz#n*04XB%PuOmwkOw1s1|(5@?R~4*Sbxqpc~4rJ$s1Yo2bu+ywef(Z!G;N$(Oxb! zD8MjsX-$~&*oy(V*OMxJdvRf-zx?FhllgkuWGkg<{#19kv@wrCr1XsbscwrWC*nar zWCq@+D&im%2!1{fmNc(0*?-D~{MGYevUZN=%&n){+$`xCSA)sn;G@qZ|Y>!N|Fj;+S8#{8U(ZKA_W6Bdi2oa7!K;j!=O5_Z-2s?-7O^jt? zOL1DD3(NgcLDwy7T*9>iwfSO%G_bUa$Tsca*AfyRM@gx9C-Wc3zFqSF0H1a1zb_9Ytbalw{35(hV@X}_GlSJFQ&t-Pw*yupTr zsA-ov0@yptCFRL)PIbB;3IGjTdQzg9l5@v~y12sxjJS*C-^uSXAIjUCjdtr#I=!^o zO!{<|#UoxVBC4#%kl`mDKN2vjj)%5s@(Xs>0*SC-ZLP;;Bx*$<((bwLDgEMFx}iNP zNT=hKLrEB&n`fVhGk?kbL-T7&)zi;AF{Qk!!H_Xo!oP)hbN1mZfyjL z@ydmkNZb(Uz|gBH=s^@C$0(|DZuv5=D0yP%&Dy1(mh_m6xA&J3!vY|sS)1+vbtkq} zIV3+@{G$ee{{T4sr>B+tfdXIol7(*dM*)IL-)&$9p;R5Yb#BxY$|T4h1Wa(B zf%ES7HVP`=nm?9)OaB0zfr<@(Lc2P5n=Gy2)O5{zOd)UJx0rH*=}*FLtsazk-n|_G zSr?8tvP&8L2%JQpkRP7^0G5}@CbO<;mXKKa-$Qh7Gg#QAEblF*{^wY+1O3-1_@o1& zpnC+7J2PkBWF$m5NB~!5OI(EU5CMnb85*B;kKVE7#mooi&?&3py)oG-bB`2SM zV_ynoO~-a4<{d{@*QAb3UTJPp1@z%A01CdqP-IIegttTU7Ng~RmcG#L4ZXu5jfhoX zRP_WfBk;k=kpS~%kNK14tLTlj)!>@aa8^VRz&Q^C@Q(OwvET?r*L6K9#M&j>M!;2C zG*xg6Lx%oaA$X%-j6THC7# zqj=(Qp@}3_)SjoMaRi1YAyVhfzF@jFxSBTUu!aye=}&}Vva}FaTK>6rW^{|2mo^OC zngPX7n%1;hci#fgW7fB~8dcI>>C(IxP(LW-jf%37+!2aig1?$xal4G${+5rFJCWAn~p3*Clp0dQ;LzJ%)M~JDW0BKBZJG%3py{H~n+Jw`w+Kv&y z1E*1h$dm|xp>O8BZqP_l`decnn48k$A0#^vcz}Lb*YO%;Qg_XwDf>Xav4T`I+gtf2LCNu~35A?vUTN%gvdCF=2Lw`(ZRyLb>$7@-DJqM=W z(;7isnr-TX{)sDm<8SGR*;S68cxZm5F7>DG+jI9}wNSc->LRgRK=Bs)D#$@K@TlJt zy3(iUJx-PSoyYu&Z|RLKFB*QLp9!>^!~3SLN|u*?i`1#Lq~G!_up36phnMw9C{3Nm z&(myb*4#Y3t0CITaKpwkk>MdKgF@CxG_#*?@(vMdt^OL;+)!A~LGX_O1y+BBHHwe) z8S32!8g$2mt7FQV*fd)i{#Nkyvy`|1kx@_&O7DktR8J=Bj!1hMPR5&$ z>x~t(_sqUX)a}ifx3*$FsUJUyc4618Hm({+6Br&})KdK$-nxDfDhP-P>mbj@hURkd6udCtxaqzi(!I>aHj(Qe!`GEY{XiWy z?T86wqT1CFO}SAhpeg|cVy%zZbrCYo-d)I<@<6Q7BMR3JGWT9vIxIgmAcBB{cjn9SSHX8hxeOY>m! z=aekJMcTYV3%eV+j-s=M{`5%F{h=YD3(-j1zC-f_o+ilQsL|at^GD~dmF8U{_e1=- z@}xdgg7PzKskw`d&B&-Mv9KfvNu^YLz4CL;NZ3`PI8E6px0QeAA|mp(o2TjNg54c!g^jacJuo$&6}MU&69cG%Gy-3PpK~^IJ$dMfaC~F8s9zmm614Ls6M- z9^s_64bRYwHqohIDo1UGN?8X%Nsc3SQGQte0Gxrl@{OODt!%uzrCjP-4ZY2@I)%ZL z)o5lE;K6p-6O)dhflM-KxQ(!wKQiyMzcnYHe4nS-XtShdIc#l}mF+Ica}8!TU&iPJG9f<;^rudCFh}N?DsCm?14f1w4&E~W?pmqyK!{?09kyep%2V? zuc7kRgXSCbgPOwH3TmD_>8m+(NzOG$G#8BI6fVh*Bgj6+F zuSVy{5t~dKV>at@AKrwg%YUBVoZpsOY~PojP}Fpb7<8?KFQdgQiqej9nWbh0q)LUY zH=yv%Xwt_n`~2OEvhZxpKPvwKG`})+{aehldD8OFRMgrnIzco#bTNHa-J>n_n3QZK zkbE`xivS;uMrLWD!Euk;;%bf2d_k!BPVzY|Cx=@W7k^j!%;;_&CP6zifEKM-uppm& z#GxlD5}@~=`NzK`>z3Yb^1qlab!WS^^9_aN)uEnOlhlsdR)S!8ZiOUJJ^GEZ?J*IP zMy_DRnt8JK&7MZ{=BegCEL&MNqYvo#qg&_=)N*pOjjI|d6lA4CSHBb2E!E?WS&nqa zOFDv=oImFxzcxJ6rfA+?*R>l%rfL_qpI@5R!Zd4n4apYkZrr&nhlj;p%tuVa$EJ=s z?QTS+#S+K=0OusF^^Y|9hADj7>jm%BWeAX(LZ(}=qBxXo#Dpcu-f)E|)#AXi#7dTG$d-vvC zZoXdf401@4nS8hQkb+i}?AZq9Zxy}Kbi1)JzO{+gL}4Qpp(?}T`hCVx z$;f+enZM^5yzS?|FGuG;%$;_BE;ge)DGKXQ+#8$3j4DAZ1O|vGs}g{|JZX`L1x)yP zuhqZj8ocrOgXW2Ugd&q1a!0{cP$@L)*QZ>Oh#OlIlpX1N zf6f_4XRN`b=|7n8dXvixb~k^br-`PS$SSDx99x&!->B<|#~Qmwjod!e^UZ&d`k&>e zmm5&JyVNhVsr3^j#;2)TyneOhLF4s4vgDZ@kjfPOs(dvACBYbvNoB@QN6!uLmJsbm z+uw7&GAx&Rg&|~0Gcs`s$70RWzpUb{D^BwJT5C5xV7a)te_w!()rT0Z!ipb?q&0g` z4Z7rN+1RI~Tf^x_CXg29DI7zg_ah`WYrA2dWb?I`m*RN2pqT;UmEK86qDH5=sjGMl zNoD~oPeJo0t*rU39Txr7H0FwFRwYh6xJDRqW4YY#On^37@a*?F6eudFlr$u9*n#{q z%5ljZv&wrhiMWJ|KG5RR)&x2DxUMgoxYy^x3O!j;nafIC9`rt?Re>~$@3%UW@{)3m7lOS$=?h4@QRRFK5e!yqx4a^}m#i01nz z%3t$~K1uwy@&=XpnfZ?`x0`hjHNgbd@p^T&v<^9lpes`DLvfI`Hv|e(DTZDXyJX-G zE~~t?`BmiK%xyPN{KytoR$3;Fcx@X_gOk zz8OgH0FKq$DUqgTF`Mj9`N!*>PxBH}2r`rRSTA>j@f#11kc{&@!tE)BK@;$&i(++W!F0yEF@6M0%n{ z%$9K#k_wZ#B=V^w^(O}rMJCq&0P}&KO48_c{bFNK$B0;?tvia;?cW|EPGNG)EeZ5I^C2fZ^mCTi)Q5@X|C(HwpuZ`jTvFQ5;Vk9V#=f8sN4c;PS}iVElbq=oBsef z^DmRN7aq?RGX@4oB+KQowlg-drP_IbDGRnecy@~!=o!E#*?Tiu0V-mbxX4^EwO z-8iDxlXOp&w7ZYX8RPPQ<&5__Rmg%VFRtvQ32`KnFEbgDgC9;hfD*ZpdpM-q-?VLZ z>&(7bxQEX(&*sRjbvP{b9T&_o$8eL|+^JJ6PE*ylmOA_|5#w5X9q|$!HvE0equ%_O z{K@itx8?7fyvyW0DrqLt^leI8dslN-5C9%DWBY81;R*e&HSdVsowL6%enff8%AQ_N zJL;B@8x@Kv<%$c0lHv$tKMb-%vk3ZCg=t*AT5}O)#~O&p(oOkA=Is~Bo^#VY(dNqm zt7vgd4EEa|K>d~#*zxPfzf6n>2XDA>0@Nmba=m3}njz-`N}NEJ{hWnj_ur^xMv zP~&aEr+ihFc_+@g-{sD;ADn!dA||02DK)&5Fx|vO400*&{H`}s?UID}4Tdv_n4!YK_|IllZ)hlW6Bm=$|7mYye?Q*Zgp=1XmQ>&}{USlZs+ zTCJSW#bpZG$q?F&02~hc{O}CZk0hKiB9;8z`P1fqJZa6Kd5`K++qj8+Rny^)bXZMQ zQc>|LgZnCIM%X8sQ|5?Zj17mBSBc|It6lP@^4cho#ANXqTiw%<Pm8`-iY>DtfyZ-IGC@nUFZsxeyB$OG zXIa0pMvu*kN0gR^U(x=fG$+&C8-LvqJqHR%p-m17BXk)=F#S{Wr%-Pqep>!r+ajj3 z<-JjF{K<9=B-CJrL&hnZzrPbB7L{1G>but^5xGYYFKM>_0Gy(>wfyMwC+5@IES^fb z(B#v!YYC$*9CuK}zKs6>R^|JKox?{XfmKhnP;vkoWyCqYdXMvK%u;?yUH(tcaLecG z?=by%>uT&}TOguPqJC8)lKLDOzq=&RjF1EtJWq4fKj$bS)ITr`MpR34Bu(nfuo46MEp!6w#193TtSb1a(-z|=HDy+S^i(zM%q=zfv4QVsovWTDSLGw zSi-Y|##)8-Tc7PS5xy~w`>-YD&E?%$EE`>IF7WAb?Dt7*?+j+N_?<-s4^nC3a^Vs~ zU5liufPmm_)KY{~#-pwfte452QoQrVxnt!m9phX5N^uNNaA_DV-H(79G*Zy@y`1@~@NiT~ZZ}`03idqk9N8>Q#cZ#kgOOhak(uj}7v}jyFN9WRQuM zm8xpKMbLbY`GKi^UwO9j`u9Q8?nFyAn{Uqc?Hv|K(li7ry9WDPk8DOOG@lrlad*Ar z%6cA=`6v0gE|(33pO`c;qg`tHR5v$~-J3bmAj+3Tejio_4ahhfHznK#%uLbY1-l%K z#l164^S$=J<%=zGQr=Bc^6Bp6xe+fZ65&faur&%JdIeF?Qk!O@Q7aC7F>ta^Df#19 z^8Tx9a}?IbR&t-|kf)(m6!_>i8|-^!T6vh3a)76keqDL%PqqBh)jXf6Y4(>|EZVKZ zJbx6B8%JPdNDwlD$i(sEy+35;)-tyaaHq;&nfktgXZfM6d2`B|RoZxdr6OsH}u@7d(lQrAZr;QBAka ze9f0_j0)NB-}8J;+RemrcUF^Q#P%d+CPTY?N2I>d(R~S0=-q<5C>)!Q z#7AoQ>@YQ_+F1o2&f;k;o=DAQSc5VtJ0Vlu$k=!Tg$ma;rsDUU@hlMnipd7!;Tw@! zY~4qEQ1xHQ&oED-`HCwGic6&nTwCwg?{DPvZ~4iS<=tz`xjv0dA^?k(n#CQyFGT?R`GxMfZ@c-W`n=a~Gg{z%s@yqz?k zSY0}0kJhIiag+{>7Q0ngZI>O0_pphvZ%F?DoSyUb{*S2Hd0j1Z`>SK6*~+tBTZv^M zm!(M*p&30%-K$L-`My=uZmjHLgHYEFmWF5+>7s_%mh{-rQK~_25lyocxu87j%sytj z(CKjWXKk8y9`@4%H?4>n$3+{a}dmYgM- z!YMHE6+J7zOjVni!(6_N6|K0`#ZVJ%NPR#nPF@|b(k*~Lo-g2I9F|&mbtPJ`bRh0J z;7XbE<@A+rsp-JfpZAv>jou+wFX6UsNX1z1v)JJ;V7A>;GbqNosC zSnMhO^NOE-xT>J@_M!<^wA09?2sZvdP6|~Y@y?*Y535*o1O4Y({P3!4rTL>$)^9De zkeYN1?EGYS00fo$B>R!D@x&`Bisw-D&7H#9CafTm;6?Ri;uSY4Xd9;xI$;PZTDO?*E$t%JboGE*&d&*sYjpJyfZnw1M?yMa zl0$kvudM6V^G$BnVeQ&AF`IM;i*3%d=sVy6i7MKbuQUe&VDP(?Iyw-fjEU{Wm3S5>z7448Apd)6b6#I9{1QcJG^*vY1p&^`x zx#dQe>dLW#Hz7?vBZZF=H_y86si0rmTG?DD?`)!(zjmgq)hF!(PnHHjwDT(3+QB95 z`^|GS3owotBiyr7hTRx@w6j9@xA!XxxaP|BDx~f}`C)-+TVWe6^tWPss z%xy)@yb9k0ZtPtsC_y#r)EotnDMIQxiyutSEUC~jVoy$tdf;1TUQ5y<*JijHz0=!( zs8Ut9^r&mo;;3qlgCqs9Gi2Ux(O*r|Ae+lGwbqj}zZ>Z!B1e)T@yGn12|q}~!o(X( zzcF-)>>Ef+nWT)(rankw{%6tb;f5Qxo+Z>>nPiIGJEJHYI3xfMVlg2gu{5@d5*;LP;PvC%w|on0W?x!{ z<=xnHsowz>psyMy{`n~eF*f=a@)u8AZzX=&k|JLFm_8)(bwkoLcfkPhj>-6Hpl`brXgiv??pQi=8=|S7SED(gm_AdTJmqe>?w5O|x31cYi9ogV{{U{ToK*DtRi$#h z`nGX|r%%^)4I>GS>d;4I<=C^_z5N^kSYE-w6&nL!tCx9L4B)ihJe>YEc z<~>^f094ejZzO3xzctLErl{*6ULcXs&~K0#ICf^ue5bGLpO^9dXUmsU!S${%&m`1# zxb#%2tB0v7fYB-Ta#-?LCKHDjH4iQRRO6gPvuxMksmV1I?49c*^$J2U=2nwK{qv1I-6CP_B1GC07ttU zd1k^k(S(v)#XQ$hA$ExTYZ^Op3Z(b|N!uqzO>)Z^Y*{G(0Gws>!+z}B+f?+ej>_(lLe|$Y%||Axl7%%w^gKxvG&|x&b4)VE ze68bVs>#d^-Hivj;cjy&Uf;Af7@=)SkOtlr#Z@9vERjIXM3zL2kAP+XpT`BU$;tPR z=SPzCeFMsu2K)337TR-KM_`&XAunD=05V;%twBnVN$N9c;m3z=ZUiP}Dla?p@zP`R zorL~k(=BwpY-+L_eIHMXIBtJO2+#>GnQObyl&?~HWfG5jICCja=KMB#XP2~_iL~uH z&(0FFwZ@mGagHeT<{!ChmQRE01IMdW^68c55d+P$42+BAy=zz&+I`TvvYOZ!CSO^k zSrrLGL-6i5r4No`faSjQ{Qms&v(;D2eqZx;s+Sthk@_ABl|`XR+(Rb^{gUj&7d7~L zZN68FU{ssttNFY6ho$I0m|k+Tztj^-hV~0Nr-a5@Yo+>>kr-hr4IkAp$PH9{HRanO zBk81Y6UpY5AD+4~^Ddcvaj#r8ygJsCC^FiZqFYN?1YCgdF@vK{3;08x?t5)zN39Hx?s1S%0VF^Em+W`as8fdLk2CsN_5G>HVw2& zL`+A$>z-Wvo&2kx$odDJ?!5m1rOW1Rbu8qQN7N-tXSSB;s5blqdW-1tJeoxu!t+uU zmoS01Dp928^SAPE@~iT%%hx*f&*mnVE~4wg&rY+EWL9d0W)gFE01fx*eigzbju+40 z^N!z}zmb2HQu&uv^WBWs{$qPJi%Pb*(wh1k^mE9FO9SW-!Am>(WP|pP*~w!*t@$!I z>~p8iS6*ba^GD`Ho?_9g{{TnW-ZkWwwxXZ8h^1&Lwj14ectt%2R7s@WSo%Fk9mzDO z%Pj?}nCOCAd#L49D(foNhJb=;PPC>Krf@+uUOhXUEFI0MMd$@L*y5{IKpZzU#Z;Cv z$d_u8cA?l0d{ql|0lv4E)DWe^C}uQWg=&4gajQ&UUrql2IWhTT`PZmv7k{1hn&0K` zlq~d^p?KkeVUJR~iKqlKM;Sj>MH_JnNosW8G3r25afbf@sWm^E-}8v;uFrLNb$xS5 zh2d*vw~vjp0-q92S)!6cr)qtgb*adaE{Pb=RYCcf{{Wl5P}Q_w$PEt1MA5Ca)`%sg z5?O6{ffM@GQ^B_+cy;ZW+IZAX`?~!>-*zAQXXcG}O7idKFXjD$+G;jQ6fbl2P#8rd zZSlzWJ=6g}wcOU3W}NWK(ULX;zazYxsA%@{{%Gr#cGuoin%UxKlJ!^Wk`UZwF%|)< z&;mBDOHVEd5>t{lPZjg$=dPLMKP+h;PSG_P4Xur|b6hgWc>2#$(LxB=iu_CmU50CO z$BIOb_d5zfT$`XEE;0RVGQS#_w)M6P!tb^ z0*-srZuvL~TZ=ewyilXi^Y~47Q`nxldkcG?l7DZK) zop-AOYeCRu`gqyjqfS%MC10H0W6^CieL~a8x|XSVr_VfbM?KuMd5I#WLV@tpt$K{3 zKCg)I!O6j;5gbx{o#nQ*^7YBp1-i|05tVsw!zfWvvQpwUl~3h#ZeFbMOFV|GIhCP5v|Fy;_}W9qeEnspjV}0THpUq3k~uDQ z4t0(=*zjdlZQadB5`K#E$wbpA?q3Q1Yk$sMepmiqw4P7=kJEKcXIj(CTi#vXnC;+_ zb=b3&9KZ&ll>*o7?YYW~iE_AY@So;q=g*$MIJGh6@60_#u5aN*hSe=OTE%Y?)QI9p ziqLJl5?uJ?NMv?rURb+}T+!_{Z}E?sEbnCuv%r`45+b^q9u3aCNT*Y_TL2i!WHMjN zpU%HE{{YT6d9q*3e=1(h=1aA-n@x@lV(#JMnP+5TPsUjt3e-^0p7&``TIsG;c6PJ&o<%?cRn=H#2GQG?B*6eju|0#F+Q>6m%O@oVpr$OOrRD zd9U+J%bGWq-_Lr^qAo4X7SP+CZG9uDF|D~fF=JZS?9lS*km2aYlRqWuV_VWJwU}dc zYwLKgeK)5l)=^L%l@<3Jcwi!mvv*{nSd9xW;elQk`R(L1{ND1+f0i-cM`3n#3tdJF zyO`ari(8Y*H)!g}SRIK3ZSR8Xc2Rt{AN=9Jo^*|0P}RJ*`JHQ{#jIQgYkN;#bS@MM zDmu|l-By^HiE|C7H83Xpl>Yz=`PcM!{N(4KZ?!!iO;x+oBUm15Y3`$1ki|zdU<#E4 z6(+T%F$4}lPEbb7GULw8qCu{CzWOOXx2E^H#Ze6klESE^VBo#w9!%<#WjvzZEFu#R68i@HW0Izt%2%*>ip7EpAZv z+MV3jcQR0q-pb{h;XBZMkUIqf2-yU`Pduq<`Q5K*Hae!Gp=gl#a^p;nDfK^2Ij$PP z1#2Wh>rNuP25n(6DA9FUBLI2s{OtU})O5{5%-XJ_ES86*JwVI=SY zswrN%t;w{FJ3M=aZ}~^&pE>zT4Pwvozsr{%VUpm(J<8i8uJCaMLlYXm1#c1s2-D}G)s36c52wdNIg0Ry1N*u&GBOXcm>pMgr}Q zL$l@ht_9kQO+~`oji9(YEVTWHJ)Cwu^5D?Y>GRW&0*7KMFsk&^XEmr=)|6&i{=8Kf zbgPbB0ISnr8GjA(K&n?HUXdx`)9CBAC@NbHyLkTqW)xcZF6FS5udNYXrBNNlyBbGw zgZ58@j;Q@X_QfEhriR{FlT^}Oq_mge_`woF(q|gy>5K_ibSwDCcL1H81NcYHipzUnLE$3gD-cs_%lC^t1JM!z!Rz7mD zxwLt%9@+lyLfnvkt|%IHz82d zp<&zl{WucSM1b-kSLxe)P^cpYh*VR4!kDYRuAD=}0ViruefX-RamD~dR4O(mw5dA{ z@m1c8cB&NY%vnN`NdlXn3LI6y@99i|huJJW(nQII9yU z?G1()WicGBt1g?wH_7JTmp}83n&;+iwawqr?T9}FK(jrS(d*EAhPjo{wnQSjJFP? zW0kPUfX*~uJAQCYqIoyW?d2J~p*D%;?JrV-`(21?#`YPaxka60w{W~wWme{|)jrD# z)Mj2x@%p0C91;SFPb_~w^nE+?M^gOXwer_JHtr8j-ok5;W`bc5j9et36^R zmlK(QoMMjceq{du&J2EU`EXn7*0(xy!>e+Z*jsAm*dhQ6fF&q4s0BgzYrS({ltw(< z$Yx^RU;hA{HvH7rr-MsDbuHZQ!aH{JJ)I?L6GbRmn-1WNrZR~;GC2h@uPgpUeqjDu z>Q~wY<<^;|YdULlxwOC4D?PZ3i55gQ>P>f74u*%rwrp|Yv2Gq*pc*W5R%!nLGrZ$@ z<{voE2-h|3MP<3WVd%oMNy0UL0H{PztGVB9M{}2B6|+>OVefgA?#0S|m2d?>&0WKggBWHtalWBJTXV(0wHl{TlZ%@6s zOPM2PV{lSZrf|=>5*_y>@0jxD=0lU{-}%P_Zzt(y6)?x?0m__%Ii)`B^Aj)B-5;dB z$%9IbtLM%W zOVb>QMPnk!SdrU{5Glm=-y%xVFGOLc>Y@TdPwK}cY`t8qNwwkI&w?jm;FX*sz2aP(8y)s&lsTzJ?7l&AWQZJe``)li~SJ4Pl zO=5XzYbydxc(o{d3RG7r;I{LS15XI^7J)5}sdHuZxU~;O_zSp6XygN-Lfh@r^<`u? z2_&DP9#4n@DdE%G1t*DC!%Ayws3+n>JA8VYJKP^qUaU#^RM+qK$Wv&Nw7y+xRYiWC z>yHX}neXNA<;|~}u4U8pwlZ~-AyRfYItH`h|HD*GaBEwxsXu}TyY0Ra32nhG9` zgkw>Xli2?NE3BfH`^xj)A=TovlJTyRQe#d6zJmky%X@dpoOHv)HuEnj`9ckISFzG3 zaFE>39B=9_${YEpL8sl7h}ms3**w;NF7(Yl?&8|t%+MLFWs)Txl*eTxaaUT8YJ*RF zk%b^m({IavA)D)2HG2(q9Wr>OBI*f9F06Ge15np>4MIIVtuA4Pq!xZMSN2qb%6sjx z7z9|EF?;_2D{1HWc%&6T%QPG#PW?-LAH}ox*9MqW9zxMB}gVdTXo!JQVoJzJ+*)5 z9xY_jV)HeH)5|leI%&@E^I%8C@p2Ru=qb}I7`m|WSYCKaEu>n>$|a`EyAm);G`R9wrh)lIVRNKeYW{qd$3xSl zQqkWhFW6(Y6% z+^w^T>)uK7HKr-mp1b>mobC&s9%ZU>mgc-H8!W&-y|{a$HX(XHqaJ4z`c_;sPc8Cqmn^Pzoi0Bxkp`ak5evBh1Jg?UMxDU# zw@k+acEc(R-(2#q<(gdF+3D8$)R8Q%i*T0^1d!L^byfhXp1}6YOhXYemw6Y-{!6&i z#GY}zxYMtpxMnPXu%6v|M;TCQA?dv^00Nm5f0?YbO-Dko)pTTAZEj18t1Fvw#z*>^ zkKD+`g*kSp+%<4Zc2O(*pQL#)Jh`b!=Sypgtyo;!HIxv`=@}!T4mr^Aq1^b?3}OcM z!g4pW9rF&4<&!my=an?O%{{H>MwxEzh002bd2K}m9jQT4y0w(}~gIhp}-RwqT+x`D-*unfa+ zdUQFEAsXMCL7c6I#ie;qR@XJnJI;5HZ3eFJJQ~G?n@0_^)0B$VZh3I8VAbjY-zwmu z%F@3(`E$y?Q1ZRcmHf4+-D}N#s9RpcH`HdcghdTRr6ZWr)gx-DA(oZNnAbEyc6MF= z067WeEiN0MEzhAf(%C+P3571yq{EAqqbd6&bR(yRRhAUX6zzomTKRKHj9kaAYj@gg zlFbs^Sz5r-ePyXa8I&3xiWF{ZjyT%opL4%B{HLl}U)tI0_Yt`!OAZ6yByT87m}rrZ@(RauWDByU~KGHfm5AL0H|`ifn-64h}+z>+~Abgx=uX`d3Y z^6YXg2sQQ?@UIeOp?N<@mh69t678%#H>tA-WfBqa8a)AD<`_gm47O(w=zdSq^qpGE zMTbzj)b$H=hTdz)<4E8t;fbQLB#;jIVSoXw62c<#>M>PC6s;c~!xq2^N8nkFrMDPIy$Qw*hlW{#p%ts}gSp(A z3Rf}5Cm^PAf(IVQBoY;(KeP_`prV5fs4Loo6f|mfb3sbbjqz5=;wamF_^V%Gl`01! zXe-v6nq$dHq-uv)+I|E^qvDX70fN{P%XOb6d51vLY&^y04K{mCKT@yNCY=h27L^qF zjnoSi2nW#Y>)Y_8>?Ig05XNqYHap11Ia|i7M zxa*cr1fk3|$24cUrj7Y0=Pxos`ks}hmV!38g+oYz|c{B3vA~kF8tX$61zd0T# z=%bMv1!7G$>N@qwU(_U>gmYNVi#%I1#xlVdC%|j{t4%fGjq>1^S#;*os~)M-<6WJ zRL^rs&h=J|9Q^vL`Q!(NP}wLU&`@9DC9M&Zr4e5VQY<#1#BKRsxjLKWO=Q;hJz7Q? z(|3ixG1(T)6P1Zw*1i4EYFY2tlj16=vdq+%^1aqTe#a~3q9}BKi8vq0i*)k(>atcK z`^nC&@<+yix3nm$MAY+@f)|}Zl1W6ny{|Zo<>-e`#5`{|_^y10iL zapcUcr@8rh?*tQR_j^m;19Jcv->Xj-_x3g{v`o)nQb@y9SXtEESl72`gK&_12F&a@ zvX5j+7dhkMtZ?Gt1mB)Dz0X8CDfdKS$APvKSZ->ZGN%8zH;iGpb#mq=<`XRlj?v}? z9m}RcWh@cgGf$SN)#cRM3fHZe-1qAlMkl|d6W~cv`Wi_!a#X`wKq14Q>puL?8GXh+ zI0*3;T!2%;bIDA|e4Ar;v}%T~&`Pu3WWR1Qi?#f_|H(HR@@LNjHNSqmSY{@&{cNb* zi?qh*z~i?OS0p(lR9?!Ee}vkRc8MPt?OHS)&fhbEcNfdH%jMo#p2Wc+d>@jixV@NF zmU!GdjlC-eCYgPtG3tM_7ymw2aH3nR4N+91_O#At@WSS{ zdR!?ZS5akLV1h7#+3CRR1YGh3HHH`(gt@U*<@1h?zAw*H;XUxJ9e-A~;n8JIDUHGI zlryte!HQS@p@ObhY?i_}K^_k?NDuG&sEezbZS`7RNj)W47a z-beAC1(oJMRCN@LtyAWDI5qBB?C+3aV%gRiCXJ2#hvxrX-e+h#ddPf|Ee%KJqJ1u+ z$dt}wg*S9wF8j8SVCoKMrT8e$?r!xELs`65N3F=U<6qmR1AC#BKtdF{eJP-t9ewY9vfwX$br5<`d=|-rs0yEX*cFHd5$)dvA=& zFi^>uM=HC(todhb4G=&(WNK>z_3n6wU>QR*Tc&vS;A_1|t~Z8FI>wN+*Wa9;!hzh_ zeF5+^3T>@Dr=~3Tp)CEfzhw#d3ygGN?Es)g%2mauo5aJWQAemwii%L;eVLAG;Zbsl zSkvOZ(dOJ3^PONRG&u17GMT*`q=e7_JkZ_DQ3GoY6=0>cD)mC+sM+&3#XWlHDaxv% zTyp+I82yxNd2i>Gj9SgHFAGWmarxwh?QEAt9kRu>#C{-m#Y(fmQky(ol^eToMLC61 zm^AB8ege~{1kt&VNm9K+Y)VVx|Dg$>>VZ#nIi}}##hs$gUk}|HH(7(qg?N!sV${>? zw%dpvgA6g9`#_~A04{|(7C+vHYS}oouK5#r>8~|kF5y9np6fm+GVK&d4yruPFk`cz zDbY@C5c=%spbC7CgpO^<{F;?urE{RrQM-42)|JavqK!$hbTP8I)4wAJJ~e*4v|=t~ z;*il$kCkE9n2`G!zXav-$VEF{aB7%L&C;|I`d@M;D2ajvGO)-M79R? zI=kVep@!Nr5M^eTYXf3#jVgJyn!`Z0A-WB->|sMF4=K~4f}zGm2Szox`}a5H8o*^3 z_>UVN+sg8xM8YG}pD#njLkR8s## z3z=@Z9DpJbO>W`#sK&)qFqE6qLDNzbM7kxxOIrW@-B+AIeM22v+5C)D7Pyb^@6p29 z4q7UU{%F0W&}O>;-VU6;_*G;BZrbKut^CRbQONO_`f--ToyHe|m& zmET87t{S87V=aR)f283-qkdU5v$TBuKBgoqh~9&mf2y3_1a@Ni1?4p`W0axCjDBxOwW8OrWrLml(Xo z8JxzSSajpc`>axY8*he1P3`bn!S%@o)d!cRr1Ox=S+F#lxtV@8Fko);88hmA$~>ta z9DmHn?f~DB)5EJuP6BWg`F>pNd38m?3-Z%jjx8QZ_<02KBizTY>|tvdA0ow_yNsj$ z#F3#D%0#q{!2f4vHma2)b-z_Yf&4RN=plm(KeFuw!~Y>9Z9bT(lwu})Kk6~rpM>VW zQSf!1a#e^#eu|yX5OM2xuQ=&pA_Ed}x;`zik~6>W*DA_IlFb~M4j(O_gh!5vPLzT{ptrq_k8HK$sK;J&aF)kFT{o zJRH|OC=Yt+_k;cFScB0j>S`Z9dJMmIA10$C^MefwTDIU(84XZW5@9uNbA!d1=rwZ7 zUkCo4+UY4{Om00@I6Cr+1ZAUm2c3|s zyI(qppZh@$%^sD;7W~mlxWt>?(>VmH>y*ppNf>>wyQ@`9aOjw_PgN+GN;aL3*XV#L zU)lStaX(__w6Ht#fO8RDMc5qW%j~CyTWiPbdoYL&b zF=lQUzxbYHGWb$qo!@76(||J?FW?<~xtw7=eXBz+uxhpGZwo6fjO`To@i@mwn+9PR1de`u2t2Koy+l+lCap5a9j-R^}rt_J<2Zz6?Y1V^mS z-%50V%}WR40u4-!xZjt9 zoViq#j5l*7jw{kr1!+(!)L~O{m2%l;a97_%-x>B7h__mdqFkdK#=cU3&O5#(BDCD5Y|Wm%R_4WbNEIld+Sfmg$YxcJL9YRx~CgKio=_ z0K`5k9*E#s9!hj*6H&H3GW%tma25Z)+S^+<-{94)DdoL@auAVa!O~X>QR~F={U(KE zqIJ}=9n{1!#coUDxRF+WzdAu)cTbR}?S<0Do|#+LX5^B)?~xLw()y&imgJTGd*@>`UeM8Rq_hkKA%Zm0!-6V2{P%eo8wa6v=gVQjrbw(h|Dru zy(>1p_3?Yplw{+G**0zSx|=3ik9ZO$l<(__@dtE$5)b=KUqI*5y(03c!hO!mH}1j6 z$zG$kl4W{6v`>82ODM=d<0$cII)}lOcy*XJphD72?R`= zA3*|NgAsVVwcN9qroCWub0O6rZ7Qp69>Gulc6p#5ne0F$Q~Kmn@#Gh84&N^z?uEUu zqky262WLk1qGr}v+9{j}TTv>5D;_x?{bvhLBakxye4j&3R*tJ<7vt$(LswV{=Ir@l z>2_LsT2snDon=W&QpKVH{c!Y9ia$2*CuoTc_1Ae&&qVonxP$nJ*Og02=hKe`6*U>W z-{U0p5hv8ci~|)&XrmQU7;=B2P(q+D(*Yo6bTrXsni&q~${tI;dTlc^DYmDO06jw6 zYA6JKM&{U_Jv;^+_z)V@P|kAqHAeX9NfsaSx;l-e>~h87*`|!yH3~Klz0LwiixGkz z1F=Z=d5X@i6ffRmQuQ+t!)flDhLoGuk0Y5cGsT$gGbfo0IU~NJ&%Xs9cSnem_6X(d9%}!LbH*%=04FGK{F3GUFxAM7#Lgtc zlikLxUC+49Ig=Ar@%I=Zy& zQ@p(Er+})m_7RmFeiOi}6C(AoWMU6Cf{Z=K&|QK3{i{NA0EErw($h4JLaBU3jKhh5 z==Wp?4;*eXZw9#TmnYD%+%8Z4i>p0_yZaB=Y)Q{l8KOSR$g8J|(ge&3Cb{LmJD6$f zCe=$KrcJXS((0&ZJb2uj=wz;R+lGEJHiv-76uHQSq7|0%>Rl<^^kh}~4;!N{8g46A zFcg#i-Jt}Hh4E|{pBP&YaSd&^{#++DCw?a29VnW555lpH#r0%wdi=rFLRvPl;=q(d zl6ZrBEmmur7d@0xgI#Xa<#(;1k@C-e5wmdfKQw0P*{Y3S;J_ybR8}E^ZZa_QaI>-} zcZN}3^=r*uo>WV^ei}dmZ6K8tS5AF0Q$V7_qy{Yzb8awO?v5av=3m>EYy%2pq|Xyy zKcr{1a9f`uzP;C#dE(i30@2AKCmv~ZA9A{3;)T+~G<5H&9#$hWx+{$r7us&?J%-^$ zEp+q;?-WA$Pv#enAbp1*e!adm=^;M-hC6G;IM}};SBFehdcq=`*7`<@9M$JI=7CZL zv-IXNbV4soD5O$`iU_;_dy1k!#2sMhx$W143_S3-y7ZSZP$%S`QI1imoT@s=&B5{{ z(TW+NS9$sXx>rW9gF`#3PpQ_{^_5vymzLm^BP{&k7UZVUETQS$*7?Z#S^?JGH z>bZfh&IK<|PkS&AcSJ)neK)?S%mRDECE7d}=D#t{yVeRiR^w~zn4NA&$c5qIXWA#A zIR+YSgjLE1Rc&UxdM@Vj`zW*o+7NE}zlNP%t5ROj>}<(pcia9PxKV$p-nu-X_ z%ya@p5ff99C=ZKl+w~ZFi!ulBg>sz!9ci;R@7i_aUIf%k za6UbRfXKZLIdd@DDN*AH7985ZC6-H5Ebx%`C;Lb`zPFc ziMW(N8LPyy&4>K6?Wg^N_IXVq_tc2JQJ`X(-|xlpz#w&BC^ zg6Y0=%v2MfFq2Qy4D8=3$hrGUT|V~GQH~gTkZ3Qj>v!4;P^M|S99dS^vc6|OVnEkd zILJ(R@7R7BCIt-BDL(9F7X(!9r?d8kRIc#di3rcWV{Q<-_!&(LVlq73POq6Od5)Pl zjtJ#>;Cb&d#simUO;=^cc(t5yI2Opmp*v)^TtpIlQ;jAOQ@-zdr0G=|!8(vwe!j(4 zDY{l_SLdqu@dDPda+SG7W2qiL8T8_V!9DHUh_)D`wccJrQrSvEH2`POf=Z+vvahv29T(-Gagx&ll+Ztc!G&L|4HlQrx znfJS7)1}}bS*>N%C~W(DTgLI4z1!KHf(^thkM|*^<~f?nO#khx3_Sd{BMpPW%rKhi z2kiYq{}g^W%v@C8_kyUYpD?iHA^Vq=ICW4ha|Bt&XXSPw(f(g)bJw#p+U&DbVvW#i zKAZDjY0}^=?HQ#zvx$F<;ResSTgYW}t-9n5wSc}!aF%}v!C>ITvTfGFa%BO>NfF&^ z`@nM6e#6ObtBJ_nnf&thOF6+O9nhN)Ym4uKK zbgdw>siJmclSR8!b99DqF!XK`Y`+$I>Q}2;_Z7}w;e;>ua%IthXFK#B>G*tnZ101S z^d&c!4LpNILu#x<$%Xq+Y@O6m)`#>{YG;G6Wg&CEU)r zuj&&oq@?r&uR1PF_VDRwA<8mrtd%sJ&Kggo=5qhF9w}aSf>g!8=&=m*^c$7@YGfi0 z-@vw4-NaLBsV}=`Ax^cRbjGUDpVU&S#rUY+)+3h7>D%LotZ=99wFcBtr8;eMMwL;H zzgvR*0a+t8<_jz-I)ERz&!5UoL?^cA6+Q61a@!IVZ(#jqVavR7XDFvWYlb7HP(?QZ z_2$DXnqD6%*~Aq&mJVGJSChR!RQGD=FiCDTC4z=l<$k$@?K6o5r+q~7A!7>nzDL^= z?UuA6=}YNGq;WG)0BzfAN+Y-EYyimueL{k+&63y}^?xLd3>$D`oT*{ve&C;miw?a$f_QD62~vzAo< zY0@))qxbHZvrf(gEw9dQ53jP1XT2V>0F3Ew_c>0}L8XcwPIJjV zes{4+&`W9wB0~48egUc9^lzXy2US^tV6#0WFvtENR&i`3tI~aY#oRkESbT@a{J};# zDTh6o*C-0F-stwb(icbn`|CN{APq3^fcUvf_G8PYQJ~i{u?gDA1X5JFjpM_6p=VMe z1yj*zEDALp??1BTFn39V(NfC^)~2cFetc@_k1|Z>>AYd?He42XC+_DoHMEH!$&=%| z;tgOVt}XBCSe6cU@1}lR#Oof(V0lAu)3TQugtad0V6XF9tMR}#i%xlQ;HZ3egP!BO z52!dcctKS1Y?m{abQ8@eOwhB+Z9A1_D}9UnL0!lB$+iXIW(yr2Y+Iw+@RCO8pp`4> zv&xl?;l^h=Y%GluZ34B}Zr7Q!XgJfOSqYU9IrInCO0xy~nbLQ@{$qnB&kk2fx6g$v zbUk&ic5x>tjijDCyW||!iOq`cO1pFKN7DX+;$J{5dvii^aho>z)!XLH~(S|Dp%a)%GOU_1h`&7DBV?1Acf823M z%24c(ED^XIJ1nY_l9L&@II%+D)His?z2due>>)s>%cOLTEa8%(L)M9D7Sl%WqP_J6%3ET^B;r+}tf!2nNLKrQXe(bPgzxE)={T_+9+aS;BbbGAuOE4CB=_ z??qIli1YfUddD>IyYkxrFF}t8NkbUEIl$Jz(B=fQxCI|E1`v`w3uX3Zj;A30y zI9WcDkJ{JmjG+*maGB3a!l{}lN{dr5N7oYkUFcW}yr`X>dgCX&cjU)o*Mo8g^+51S ziB~7YfG9qa(3LX6??*?X^j#|1NnOS;ffi1}kNU2ORTJnmXm7kwKF3|P#6_>n$)nx~ zRJs_Z)bYu1sy&l;G1UH3ZBdf_vazYHJyp|RZQ9?+;ZjjSD)n|BV<--O52K8&0r_sv z(B}sWyYf~}tUUzQVsCbqY;6<_2(2Gv5I-u^Y$PSYR9^2$QBkpxhUcQ642wm~j1PB~ zEJ56*+rL^gre?T2U5ecl#OJ3TXZ6rZi%s&xq;&m^kKqJLml@9{r|Ap)>K9T-sqs_h z#U9NA3s3p@${s4NL%+KZV@P>AyAACJzE{mE0DZ}*lOVH(V7p{K!<+deA52fEXUbSp zty@jbMUwE>$dtnSy{i%JpY4bD&7P=egxD~&I2@+S>=GPUTf4I<)8180I$+WY$C`%> zkpmVLfp)*4J=oLLl4vsQh%^W=yp#-GgRhse0M6rK_+GunHdOLj`sp9B!`MR&HMlgEIXd1HH)+c#7lB0ZF~Nnm1}%E|i6o>%dg>X<^6 z5i4izCf*oEkTGgC*#ZuW@uzS2-sG~?^rfKjB%kNX=D@QVD`kYWQHHc1CGt0Iqf%&K zM4tlk288KwaTmWXeF}o|>dw&FuktnxT>CiDc79a{O&XYK`hGl?S9ZL8cyaSWPdR8V z@9pnvNLfO@t!iGlCUPGVZo3d*%kLuOLP=+)n!!4>YPu}eO-1l6p^~0V4Xs9lPSPe% z?ZWDFCz%}^Lj3fa)dFNWGo;?rHPE$uUD>}R8Ya>)9TeiD{I2|I9{)F|?iNq*QHcT8 zTfrE6Zg!_m*OCAPTg{)q0_FK!HpJuSH!&|PHwGX<=pPm5^j(=;#N_a5u&BNASu$vQ zJKmz%@;Cz^m?h*oAQMAuLi*Mk{bzakBze-UYN3AKi(toNF$0$|BTvX>LEa&|?**|P zDOz~s6VUDW!_Wm70p$lk^*jSP5y0!4H-^l{b=_2mH>dV_eTT151-;dveHp8|K`;z` z!UJ-HMvlBjL>tf}G9&Weh&~n9ZI5|&=({4?)K7_&&WTR9RY*wD_2)C_?fSbmv!ZD) z7Qvzfpk~-S>S(C*SeL_X&mGa!ic|97qr4p6s6N!`Lq7YjFDi`9vqr5^bqvShc=;s( zpDe9uA_M02FF+9Cu0+_o*n;Ww*8D>xd3Y!-cOy)OZh0MZ#mtsi3QAvhh-N6Omy1@p zNz@m%2$F{CHiCjD5!;B|gS!YpuB|h%KV1uFoX@h(#h<^0870WQkiSK1-SO<4+j((V z_SzjOf!#7J@uUwR;o+j|rFWP5jb0V&rn;SNx8GBhoC2uCoX&_a$+jZV4SZ33;pmQ& z<25%#vfG7EzK7eE=^#tR)r*VJQgU7&;#wa^=`>-gEt&v5Yw8?^76P4=ZP72-GeW;? zxt^kctvQi{#WmKPuitld1$X$WSNBa2F3l1Ryl=ytO{z7iE1tQ+n}hH%3M*IZ=Y2D? zdl*i?ZRSBrsiQV?L-MXX0;Vc^bhYs8<3^*o1?sb;L`#5?2@n%hH6g{4`ctyf^=Q9%5S0{ zcyb4=TXdjC28O#l^sLXQeYzY(omZ%+@D)6UNHOlpDds*49Elvc3VnP(Vtb;?0t$f} z>;s>J;GP3_XU*2Q`tA-w%5WqaNuNE>TOjs4NQw;HY0K!+HLiMj)Y{e~oDW`p=teKXrms~ zj}_5p&3nfLw0z$wE}j}N*2H@QiC$T>=x_yMMkI@Vz@q+jf}0Ht{a7PIAX_AbCQkrl zn9Rk*$HshjTu|&r<(kuxL(IuhzN+GYsiMifqbE)iPE1!JhmJXj@aq;Mjg(y`yVidS zn88dZs_kXr4yY&IKe@Ft4w6y7K^``mtDakJZ)Z%il!$Nyk(gj6-ZU#+Cci4ce&9yl zGy`e8$y&0mN7H2Wo{Nt{wdF<~k7yd+mSl4uW0y!)RHF~e@2!1=FF8tY|ikrLi_8B99`tp zHE(n7K>qP1y=JLy*4yRB5KXa;fDie{6$1@M#PaE`uFjK9O8Qn(Ld$BK-DB$+;fKa~ zzF$4L*IQ5Xe!Sbfb%KFUQqsT?y#B*X$V?DF-|e8-ccx~t(}&;n4f?VtKld}k$0hz$ z=|6w331Voa|M4Fha>|wknGBJ&Mwn&?)O#rM3XSTzmAJqE`o|AfAf+1%AD31K`8ot^ zhR4kSC?$P@1Mwway1nifM64LPORpC)8$X=S$BuJ&b9MZV!NSL2=Q)1sS;+CU$eO)- z8p0kCq>Nf!6)lwmu|JCafQOhhLcR5&*-Y_|%ld;7zf`$=aH@xth_bzZBS3g7tX{X; zF7|Xo(>x(>@3y0(7ybf)jKZU1(K$<%vJ?9fmPr1o(poBUPz@ZI%E*YX{_AUL4B2HQ zl7nWbtABm?09wK$-pHMhT@F12OnI499Izph;+!vyNMc>q(<_DQGi?AA zzr-aV1#lk^&jcWJvMQgf&$e>w*6RMWZ?G6pCh0s>DhS51P;i+mI~#(>Q<>g2k|r?w zB7q^mIdHf$YBFo?A*H}dSuR`#7T@I$*zGttHrxp_zzu`}E6L}@#lS&~N zK9T&#*jjeaeH|XP&Z77+Rt7XcANPZgbNRYgq~5VaZ~yw1GfmcsN21h=9wf2FQHS>Z zi9t1uH*L`>ixi(;uS>JgywNE_ht0q|O&+c3KeRxMR+7#uxf8(v)>Z!qIUx4vKbgA% z;}#Z5_t0`(iKI&~{hPZZdEa1gLgIqjdm8$W+nK35e=#QOM|2|kOC0o+25k+r7#^?Pdm;YHrrXE z*F$r)PPZ4^SzFN}8^Z&#_b#$p#FG{Ua}UmzQR(uyLk=bo#s?bUK*xiK=2~oBLt`Rr zGL8?!xq2|K(MqcYe=dew7Yl4;xdLg&WNllPvECNbwG>lpUGCn&`gN5ebzeb#zk ziQ6Bes!%Iyx*4cTSiL2=kj}&4wkrF-=4B_gFU7&Aw%*wwHt7=i68FC1Juq}Ne%kK!%tMjge&0_Lg?k5v0I?d3I9r34=| z?x$~Be(#r+B0kY0k_?`7PpKyck=2eEAh7LFrnc;at4O-VSdo%wuvEdy)65O6&fDUZ ziE&vdct&`m)t;$TUt$J#^F6j2fxZTDK7+@2-6n^oQL1j^sdv7W$_r=^lL+0<^-ylD zARD(?i4xG417`e({g$#Qyqj9Om1$yi8mgZWFspEIe&<`vvZeS5py?K#ygM1@!< z6j0K^t$|z@#vApmrvEJil5VHY-}?E`OX=M12cDUtgOEf!znLPfi~{PQN@Br>=-0yv zfNxp=foW4o-Dgu5nzEYm?bF%19SN!vufqS(SO+qo^J2&dc!kbNfD1rF3(UM@9DbWL z!-;(0P;{Kg0sLK(1-?d+(m-3|Zn;sqkN6nslY_77)lS25G*SIg-D$^1Jp zqF=t5Ujbzc6e{u{Bmr}$WUx?jfxSiLpmNgYWepZRJUcZLc=_4yY;@>4NAaM=zd#fg zB%jn+N(Ox%PE_mAb_Gy<2rrm!@m(?jL8%~!DMZDnZ=hp2c@S=S;b22^S=Dw(?!eQ?7-9BCcOm~8<|G4WLx1KS3z$}(1~J6F~$n- z%LNa^o%@lQeIDR{>0ps1o8hheF}oR3!QgeRl?Lo;wDeKst}V#VqH`IIiuCkeBQ^zH z`WeH&=S05lt%zV;)Zqy@;)KUDw6Mx1+|v5AVoLmtZ!!npRi>s>{2|e=+`vrS6McEp zq3Lx}MoWaJ%zOerZ{^bUwMfXc1$!KH^@}2(0bBD}J%>|Gqs~Q;jIUk8uu*7j1!z_m zJ|4UKcwKxK5Vyq1Xf5<(a?v@Dn3G0*ItAAt{9+ID`J2#PMvVPu5kIs~yG?BKc*Ra5lMs<(FQ&T@Ue`{4_4wYJ3E1nZ@L4Qf?e+)8fNG0(>4B}n`H9PhY4>9*2`ZFy9;N{&tXJCfvt zUoyOSts}$)p0f+x>9bmr_pp!q+Q!pB867F|(<1WkQXX%LOxBa{$Sm9h0WU*N!og~h zXU`e|ma%JBdP20Y=D%APJs#f{jkq%Q0Cx81RX%cEJFjff>*+!wG6O_hsbfgZgN?<4 zhiGB&%U&rf?7yC})Ox<#36M|AXtX}7WYY;xj!1eKfpadG zv`(ZCM%C~O!y^r-xxnx4gXu%tthKA#yes|2CVTVub&Ic!a4;g%B0?jHVuk`xzx(>& zC8b|?P7UYXJvteFc^o?gJZ>8%T8|Uo(oUx83!gQ!=~E8RmgZB*74@+f3~ZmoK8nI< z`IVP1J??64vKqYi+8EQ(B;~4Lvf3s-iet+{-bXlC$c_&gpCj#PivQjJZZg^B^JFNX zeKIo=)tR)vPFnh_IxcYYR!-OgBh;JmdKi(0VC^cer?sD|MhJ-~5;YZ5l=p>@8=7Y1 zs8us}Gll43E@P($x*v2`A=@EsL|VMnsH3@Hcfa3i*Mx7PWQz?xT8X$uiQdjnSYDt+ zPYttw;O6tTq6OFk&sLL&f-Z|@uIJzw#I)mV%vlm?|e7yb-M?8PnsbF+KdMX++*wFl@tTVWh~rY zV#1&#^XbbQ^naq$T3M@I6l?oAwuODMPpv1rLB?yhY6I;N-hUcGdkOj7{h?-xHJMCk zL;`fR2SzNJU!eL)%M67gUZ)7;)aNv@US21B({JTvut2AT?_t; zZUjaVe@LD^#O1?yT|;UbCv!i9gh0*q^c+6> zx|07&5_gg^;yn)nim!b? za`<{FMz+B4ovuaK7jZPAv)IYY7pou8{(jJf9bU;N>Y=DVZP z78mWKcPh!BTV5)IC?6|jP+V`WvuDU@?4?9f5%th~gNefIkjK4x|wg&yUwdaHACCmQjp2G7}b&c2awy;t5T&aN6jv5sI+2E79 z(StphI?@!pn6a`b#g}^?G&k=;!2gWdb|vGt{x)z&|9oz(!rRsd*kJgG?o^HSN3k#I=-j<s$%)n`B!r;hNL|4Nja`jVO{4j zr+6YpXMAE(+Y7@i18w_x!Md59v?h1AVG-J?4@+Lk24|H1_P^$;%JFj;3PP2-kaDw& zRqULCT~a_TMl%9pE3FP3UUqA(0t}6VJDQCZ5j|C7AqfkjsV}KWvyl(Z!Z#n8o$8dJ zBr{Zq=0Z_9W(9wPS&au|->@+jk4aH{4Q0h;4jTS_vwP(DPX31js=XqR6TDq}7}Z&b zaI+fdRsG-=!ohP$ngIK3RG6`<|1`y1ZB-)uE^eT=$5Ctj$;c*|KldUaO!n!IoPby? z->?r)%i823+7jAfc1}XszFjX3bZMEG#-2z)sJajd0GV_OkNMe=*D8Gjx`J*(djpG8 zZECZ`h zpom3q9w7j-x5+YI{bC&Vhm$GC^ecSN8Sc+{^E+!BY57ODOYik4gx)uIE1U3u;JYLz4{3>z%IGC?V2uok(mGa! zovkC%4N(vOr?kY3YU_qy)mFRQca`L=G506fYI;+Jm_rYZkHQ|Az8MS(71Q4DWx(<5`i7jz0~teztjj81!A^A^OQTb>yYo zcOMHK&$8sV8Q7x{{c^!y`k`B&-b(a&4&Bc(Z7&n*jJmFvauJ&wiA~A#5UCD{#aB(1 zxlpU7i)+L8#b z+?=d!7kn?vsbUX+C9l=GIpBTbV@1!wR{vGKaohA)`0d*yl@bGn?UPxWh)DsZ-y2jb#iHKOZM>Y=%T|ZB4s;=yOQVc%?XUCOK*B zt&N}ZeIrnGVl@lIN@IgyP0OlqGut}6dNFax`FaPZl2M6%EY8q~)ZegoLMmHpA!N9i zy%jL!HBN(8XNUGyBSUmLS1q>W6wLNno?QbPtk@z{{v}zLBsGa=aR{ zL)F7g@{tu-)M>e~rO;WVE6mK}(J7;euW=HmuNb`{pvF zdw0@Xg{N5&h-I{c5(VBRUK*S$srotN7|BlE~cA2WzXU)AhY z$-d9!iIDwZ4@+CJv0mz=i4b)aJR?)^b-;K=5zA~a>?){zuJa^eSDzg$oC{9$tVbfm zsy#d^o%hTZL@cGk6xWRe%qBUaTpG>Vo;@##=^j_IZhbR4ZC`yLm1{JN$Z8MI@)D8D zl5W_V2kgz7@SMn=rTuHqbA{hehdbXhxO_VslkP?$YLQ+#JquU<)&%C=y(@g8k~kIa zaO{$wa8E`xG=AkPoYko(PnS1#%z^baKr~ba#a*4h?O*ChAyJQ(AIN=LTAJ9bh&{=X z5LO%Lt~u54x-qF>3LxdAe)pz|{#InjzGWcUeA%C$XX}i^F`!>tAo%B$MCMC@+MN>X zP#@IXB2uE{4=e0iVBQ0G!i_dte!Ho&Ms_g@fBLsZJY_K$$=2~_n?+rK<%_`MPdY73 z_zwGDU5&rE_k`aJ%U$RNi?SfUs6}Ts&bCCS{(d~`Qb^N{twdY-bFT4c`ba9S;mhIw zdZ#7JPoDWl%uaU@Jv-2JK~0pJs~x@WtxILe`X^6qDs(qdb{H7y8gz^_obr2kvRKA1 zXfD(FcNd7;)u zaUbM3jQYpksjaqbz>0$>=1;$W6M8EcT|evLpB$mJD)^Q3E` zjlys9CZQ)QotpW%t7dOa=;U$VgUAhBhQFEJZwraGF&LV}No9_As9RVI>+o?}a{ERc zTdeiQ!HP>pk-~DTp*MC??c9$_#;;FJ(7wt3hvwd|A>+x{{!v=@$@dx}PTdI3Uf9!> zDfk5@A@|KJYc19jC#sR>eSkwgexXw2TKI|6mH3LhZlbEA`QlTazVGZ7kO;mGc+`|f zcvg!g(ss0JLi@9OENjBddY>sIRsYcj8T!ob<%26JT}D^KHji8WWz(ERu-9GP7!`WVA)G|KRKgp)Wi09^vW86BV7bFn5neF7qC;h3U=1->VK@+S8?g%;sC( zBNW|UXMWOXqh0K)olGc`XWw%|%^^%-Z{1u@Wc2TJ>jko(9esXq@5eOO(^j>(8=VZ@ zm?T$auT)0AXlDc3B7-p6sV^I%OhY!qq-uWx;3^rzTo`CBKsL0ggWZZ z4bbINhRH#O`K`^heSREN4?c|7P2-8G_&fj6D@#8Lq`93ddQEY*J2s!`BMUAEMLhX9 z!3))U!gP(`xy9JSRgGSB!$Cm=R+9|Pjb6`EUS$XRwa%tRPsjK|70>81_tSIxmVRY` zK4>P-CfZZ}HdhMp!5k=cBuxe+wk#_*{ErA0`Vv{i7Pw8KOC1PzhV0a2URX)2y#Bk0 zUOGBAA-iiULqP~VVYU8uo3!LWSxGPUX>rqe!H24TFZV7u>h&e)hA@1}dpqe5^U(WV zPMu2L%bb)si{Q%DWBuV3WI!OkM#XK@Klh+`;Zj=uET_& zaYysTK$O#8i{l1po)21!0yTS;b4T6EGFp&({c%0A8@S85z>fk7BjKEdHqY3yb~d77 zDfk)>9ZKYq8g-Nooh(wdwoUqrBKvkb-o_V4{NMtPngRr>0E3WC0i-A@S-Z@w1smx# zaFj@QQjG6Po{CcBilZJVtgNi~drXg}iMyiZuB^)nYO)U0jbQTE3Sy7&G135#1#Sy@43e4dA@+! zFy9$n0dgiuNrn_X^ll_Yqu{S88R~zKDAvqv)i}*H3k)XwXdfl>mp(Q!x_;S|^3q3! zssnLw*snw{-Xp^~Qhi)raMNRuq{OsKtZhy1lG#;a%E!eimgOGiNpB9>&)s=;BmYby zkaKc#5e(;nbYVbN^9j|Y9w5H7G^*AWCmw*`_KKxw1O|ZE^m|#7Ui`kDIZ8FQrm@G1 zb_PY9@S%q5ka1pfUUQ{0*?sLpY8Gn~52qf=wF%gK=|a+;j&d(P>=^E2eUUHw_6^hP zC2AfuiO_`+xAPbC`_mBNYV_JY@aqupa1-Kje3CaZ&@~Cr`+7Ue*?{(vwfH`N4;Szn zddUl|7h*wRx!$p0px=+MsTvDn+;zn*t*{w`|-WUO2t zBQ2Zfhg>Qi5AOSgr;jNSFKZBOZB57is8C^!PC1Q;6Wos3Vd1^bl-QOG$YhNqeqD`) zV6)DUjPT1VOQ-37Z~EfF{sMq!xh{D|EM|;*Wu6`-1O8R8k^fvOJ6Y5N1#J+-#=6IJ z#VJ$u|491kc)H*JZ>Bb8#xT><-QAtj)3xb7W9sO!>FyY&^Dy1cbR2zjP8^0|&S4xo zeD3%6cmMCfd0eh@z2aFNiQ@RGj&@U6-)MZ~wp^iaGM(SBCSHYs!a~C=#Si(ui_&P9 zHzngcwdHG)Nsw24guUx0+Pp~pI^?TLFd|iq*<(#E3+6qnJ37PWb95VbfGYe*ZhOj^ zd&D72^qNUZmLK^M*$4>Kaje@=7l(Y167Y^u#LKphY)nO8d2QG$N|s~|gvftbVM$4Z zR})WO%x5~-hR*(nB`<<>ECJ*dYsSO+(Dv#VrppBbZT&dXCtzjPj{(G z=}m$;3O~@zKJzbfzB@bk#*=Z!KN(eeUQ6NLX-s||FyzLp$+LsX1Ky5~46zRUx~ldx zPL39xATk@~#`9`R|G)o`R*GZU%$~r*B)NuGCT?n%`kO^9Zk%k&!#USMzWG($efOm+ z11cYyPVbR*mGB>y_^N^lo1>mq_%>I~L8+QT+p4~w*BYZX!_%mq%M=ujO&f|J*N@j! z+dqBAJ?5(1Z%+%ywq-ZRK1nF={WBLARX6UwAb*&)MJ{68d($-ZxF1h{X$SuOD)*^ z4^*{=yZSxW+pZTF%e9v;uQ^SnDe&viIVlg5bba<>uXuV(TpJ*9IwLM}y-e0;4buNA z2m4&9rQ?#PEQ_w`r&APk?TKx$C;nFU`+e0oQ!P>_&x$TOJlD|Qa$ONr<0JG=H#KA; zq^bW>Ggz?Vot6xH2I8I*)#E-XPR}hCq@jh4l_q*m>`uN)Hcit!>{_#|9|C-ai22{G{Iavp zKGn)qIr}-f1~zMc@N(=BX4UDL(&RHNpl@aBIjl11-HI+a-a-V~G}gI9JI{eY9*3QK zY+^p7C%B^6nU9E{{ah&H6d(hURjF6F7X>du>Jdw<(RYYMO>j+-03_gkpW++tO_f#b z(B>=JR;p)>Xq<-QfRC0B`SV_MR+00YkXNc0FC9KT*~uvk?VJWjD_34>#L)>Gta5?Wbe=v>p9@-hS`XO=teZ;-{0WX+)pA8p?4e!|!y3+A+FDH1lSD#PrI}j;P*m zt7c=Y(q4%X_N8N(P3Fx$Dg}88dwA0^C$oeOuCccHW%DjFAf8xDH2E(xjyK=9{FYDH zgzSjWmKtf|?=ij1nSsD!6TZiquj1~#kY0zyP6@gxsXR5T?bVNeMak1~}7Nb%pjC&-KZ`#4#V<?}`^*jC1SdkL|!SS4i$#xssI@N`CC=z4?58qQG}=TMEtTH-w_- zQ~Ve*0ncNY1y@#HQDDPlGPM1A*9XPHKMnc|^Me(7v@a4nWp(}s84H#y7xdxL4}oZ`zC zapVpL5tEAPDqlxSPaAEUpHRQwm+frji8P>6=Q91ENt>h|+G1KW>hN3SvQh`Iag_{5 zdp@C_j)g+C{hy8VRFYCNtY^d-S6O_md-ep!cOx^t@&$qfJ;80Qj$$xDJtTYKC0(Q3 zp09f!v9|Eznj4TuIPQIo1^nThLskc6Uaw5EV=e_xcJd#5mn>WwO{|?XnL2G)X*Hkn zPXK;j@ali;-Z}OMi?*uaGm=&oTfcV#b@p0R_-J6UQpmm z^tS=9X~sHnbku>h()!92wNvd~!k8xr1e#_QGEKXsO`pWticx+uve&_1%8ZmdW1GW# zJycKDkmzZ>((A^FVD`=y zRP3h+!P!tzn!gE8QcbtJp4vNTKshkK$%sKZY3>89)||1jDHY21AB8N9)a2B+?@}Io zJ|f{$5AKU0kV9e|jox1P0TM%WGVsbxswfdlWc5(Dmd#f=u4019j1^@So^BJE74C<) zSFBn3QWtfbIPwRviTL{Gg2WipfJt7|`44La1FJaA4=bzab|clKNYEr2d2%p$zj&sw zC7bMc`~l?S-E!0y{rhMlh_8{Yts1@H5;9?5IbBbur9&ZtW{EONj!Ck7hxf#g)+qGv z)HpFLg>#AIM+nRht$jqkSh3{0!{a7kNi)I6_{noK$Yp`jY;>ntY~$Co>%ePv`9!Lv z{(KZPn=fRb%DuZIM}$FOq6XaxTt&0*>1&G?eNFUruO9Eewv!_?5+lf-dCEG}^lMy{ zfzh4By&SM~70;6ys{VEJeQUN_&xN`3ds||-AKSrnpG1U?)Cz9I`m#`I$g)no`+6nB z`G_0Je9~^w_c>sBzEz-Q>?7{!q*$l@r7)^Wz#r=j{#5<#2kf@*2}%6Z)MLdVP3WAD z2pt>I?~&WGx-&#!uUX!f4*E_o$xnFzl8U>rmjcM^GEnFWYw(Pn>G|rjud5!-{IN2ASs*j zcV0>ho=3TDdau6Hvj;`EJg!u+V;bN3j=+xu7>URoYvgi5?K(I?4Mm=9^A&0~w*Xse z?mX-@R61CqvnYN}vC*$hDNK6uKHFPpjTZ$3s8`gY15}X>QHU*VUHH|s5&*n*g;Fn-0t zHGH9@ibt@M1;b9oYDqRA)8vUkMIk{J%e=m8P`*|j&ns=B@Y=A?o!8uOtfyTHL@I<2$%*qI>%rdPFNP?8TCx-iaJJ?yF9IwJxH8 zU}$d8_Ex8pB%|p0D#IFLc2kz|;BATGyFP?pgtP@Ekus?qQA_wrM~qZIzHIEj4G{u! z!bq2-flbC&Tg?25Q~anc|9Hm_;f*L6Ch?@lhB~&+bZh-P#(xHOH9i_-(rZ!zY%d82 z`YVjd3hnm0R#b9yo~*vg$;1?*?h(T2%itE`a;?h*{5m7dQhx+YJZIHftzt9orx6zy z5~#B?1jck>fwx9YOtoj-{a9FuTFb7pG{=aZ?aQ9nrdC$0S`JLeDY=4@rhd0c8A^-C5M z(VsS~U%Jj_G!jD@;~~4iUqJjX2(|KN)_>bNo&jRZ`WrBTv5eqq_Ws6I^)B$7Ag=Nq z3|r{?fw}=zJijRlgy7G^Ojo%FJXj;YOjkk=GrauLLPNb$RhZscS<)N(VElQ+(1%v< zbr}+%CVKDDH1#NCMRZ1a!aq9t^9y~m>uKG2rDlf-XVj)uXcTK^1RFd2yfF=A5d8TEn7%R(s={w{|^ha!RCYis0;MwbvU=Y zAP9ph4RhH6`{8E$1L7UZ|FEng>YJ776ECTM*AuJrE-rcr_0w~jdAzcx%54J@g7nZ3 zw5?wNMReh}O;@R`J3T*&kxicM{GR9W*LVu}t;gf0&uD$(#Kd&pq)kw>+D^%*7X@}L z$m|p3oQZG)pqKEDI_uI>0|YzO^~Vwfk`~k=ev?e1(=7byc;)hsdOWfDDnF(k6T1vZ z6yNtIylrZ;{$MdnD@a*)Co}VMJibT>iFqezSd_tF@OAytq zjl%NT00%{*$5Uf_B;cu!R*8#!+*<=VGUcSK7+T3DE$`Aq^Vcu@FAEyc!z3cYu??cd zyh@=eX)mw7)!_OZlzj=T77;n#5De!OICyZQ`vo|{NF*G(`%n{y!(I$=9Hfubyr2Q~ zQGMGCp!-fIGbWpc?hL4BK*dpGrYw%8!pxP)7WA(E@{%>3Tq!GB|9Q}L#SH6lqnS(} zJ^+`H&km5xpgmF-Z$Z{|=Ntu*QV!v~a@zaD&r}t{XPCF@TY_wSkY$7sN!MMj+_iJH zFQ{l^w5UxA97eM}!bPOxDWFFbN8R`fN7LIDX4ZPu#2e2eKqjQHdDh0k+QX-i7-inwF<)vH#WQmc3D&tl=T zHQ4g`bR&#&@<&v@M6tYmdQ<$oO3rcRxt4ietg)k7@c8r@H!((|kdPPKFcfpwmEI8v zf*=R;uj*G&)=jZ*oh5{N;_R9rea0L6n#ESvfwB0F;A-4snZ6cgHs;LaB2S6t4{N1= zXj0H)JIp1|i-EYO)+rYX(rL}#aV`F={Oz&)=ANE;iAdEY%}CDZQl1qsV)HDMzWKKb47|?v35L|Bt_+gZdB9w zEta1xwe2*&1{_e!gd}iJILqgY%0r~J#*Nes8{V2^kr=>({=Jik3HpjW2lp2PQfcWb zw{EpMXLJhKJ^aPYf=Ezcav(LuVYE;HxwkUx7sbTT^SBc)FpVMo}33!_5qivs_f*f0&PEq1b5rplPtCV zaFclGmSBOgX0HKP*yBw0{RZs2j!eQ4(=bw+NEAsDnJ!cMpjKX%Fvrd&8*jFw*3G3aoWxgu~wDo_N;e*t^K*p5WcK0QAQZT7%zB{XE?9L z1dF44m-g*PIDa@x+r<>Oww{nh^E%oe>_vHar(n%%xCYi(z@rHu+EX)4(e)8S%>KyR z4%4^~H$+ZDGeiSLiC<3p%swj)<^d6md1++Icy=BeSJ~uoy1J*?)2T*ILVuZGcwEJ? zErM9vQ1XjjeiE${yszvimk+Y9o!R3xe)znFJ^LKH#w)nISrZ>-9A>bFJ_6c(N^q4y zH@wxHe|O>ROHxS}V0^4VmHus>6q|ybd!Xu4roitNMouGqCVbKba004oE7n;wdb_~y z*crL)lmbuH_EJcr_2QCE;!d588Pt8c&)aMDJdBlw?mw(#!_Am(*1fkD7d*lLvM&e8 z2>Bxj;ys3-G3Z-6rSz`J%aXNN_8n@a6xR10%59u_V|d(_9E7D2#P^rwYX)8NWGjB8 zsRW-`-j{!Lw($*g1kT!h=}{HFp12B2*oA(DE0V^s%ENhkp5a2hiv`ot1>b-L1+4Hx zc<))WnQ1dhWerU>BmJjrxO@`LeJzS|D4R;n2LfD!P$$c_UD3Y&A6RiCYc-Git)oo= zGr+fcUB^49!k47xV67((*y^{1X+LPX%*JfP*76$ftYq<#w{lK^7OM4MIFD6^`-C%aaN`C7hY9+J&Dh_f1a$G)}e{D);pe5ldQPX%nHnQ9P z&#|+e7pw-8KN8|Cfn$ox%#T$a+QKDHNJw?E;!%g=N!>N}%^80#_Jr=uzAcrl_IAMN zLy%eRF_jy(K;D&=x-+gx6QjZDvT`XuO=kIb$9 z=%)FPatApYm>r}}d$B#VXE>!MU7zlOW zP>9fOY?P6*sbiUn9k4fgY+S?WC;fC{LF*7Fp^jEy3n7onyrFE`0h5IbsKFe334}}R z5^LG?11K1i`|qU>dX!I|wpvDxy+nb=Q`NHft<)XKNv^@Fs+^tsw@$?HoF6t@z`HVk z1jKu9+oN#6HpdM-5KNDF!=|}WG30HvtOiBZmygnly$Ml`6r>k{DHsH06@BqxBj1iK zq3W}=s_EC~C461_&ko?P8}FiI2^QYkqE5$8rbh4VFJCCS^DXT_glTm*TjH*6F#GIZ zd3rA#(O>G(;RR-6r2_<#`eT<|Q^QyR-wuSOm8bp{hIM{e=|fo{6U$!jUW#ho;0Q2J z%)E8lvSL`rb;u>#(`;mNbMM-r;IORPCjzaW*<#1j&!Wc=)8erF`~C#PKTw^5Z_kr; zs($`$O)Nf5(Hi!T7ujyFjjgB6*oWy;O2d*+?1*QjIVRbpZeiA)5f(JQq+54B9TzNJ zUd{Ntstp^2zEg?%1f=~*G7b(Tc`!17ceoXCC;V7)D%c9OId_Z_?L#DGwTdvilX@vZp)9(Ub<@=mQ?jCXRip(^@uvPZg#=&J8X^)yl`sFOF zcp3`ZlAe*X%9j^erz%^56sZYgxW47*FGula?kSTdRxlI-VzE^8jv-2{7_m{+hlHK} z(edQc;YkJJ<#x*xSKzdt-Y--IIX+*v^wUU^^G^*s>-x>Pi36|N%4tzDgRvFMwnK=^ zscS9An{}!-$LB`;CBmIDo%SP)MY6X}VqEjJ9s{TTe%w*FgcQ6ndP0vQfyDy5n#qt##UHYP~4o znwMR-H4Z018dr>wqhvxrb31ZM_y>ec}uXu^< zziMQbxuz)`3P}r)zxnZypF`}74p^*ig3@x1sFnQQG4z*4Tkz5B%ua=$=JtUa4v)Ul z*p0VJN~fwt$X))y>dQ>`y5Jf`zAU#KCW3de?yj90SfaO@zn+|)#n+7m*I*Hu3o%91 z%Ib?fDx3{FdeKb(zXt04k?pi^R~J&O829^{26Mh;!mkozAMO!J>ZU3S!e_VkC+}q< zX>uwzfNu`>gR2{B>4NVm(WuT>#hM{TqXz?A_%RG$3_3l0#pw@p1QG@4k}4>%#foNg zT288Vk_D~^-49+v+2fQ*y|+mkV17U*$R09(kbqrx>f@R*j0_U2`0_h|j4bHwYY}?% ztKCdhlr!z1ULok!v|Yij-w9TgPWzPqQDc}!|SAHzXy?cOw8Z^ zPmh}6roXx#W^BIUf@Ddf(Uu5R7}|GPcbvy&viw?46(i{{VbAJHqukFvgXck+ar4~`@N(<#Mf1#~!nvHZER2>k3^{1myv^62d~ z!xXR3-KK?GcYjT-5@dEhU$aPH2>Q}X^k$HQ`&GvDwsp^%@7j^qr-~;X-yt7p;|Twt zd$ihZ1dl&Lq%IvFa2)~%U7tg9P4pj5c!ezJ`q>Ruc4%7Z(o7z}?Vic`ZwnvRuh4t# z1w)4kmOm7~@9Lg0y4{lx;#ifp(^;IT%Nw-EnLuG$p^FXXR84yvu<=I7S-AG*XnaLv z)G-jPcpFGMoW0?`Fs>q~NSp3&oJffgmk2a}p{KpT-0cANOVAEnD%+=qfa@p;^60p* zzR_P#3=%uJ{!Yyu#OJ=`07Wck9b5RyF}GV$#}^3xQ%5|650STNVSFp(UG}Q!j6&s3 z3RMh4H#H@iQ^c3!SN=95|C5f|HH_H)xAgyE zUE5rvdyAP#{eb(|9t3@wTu4JI{ z?(qc6N;=%$im|fBRtvcuhv*Y+W#DlAyKW^j^u0at(KI|m4v{jI|DFlmwD;N+M$H?O z&Eh`~@q~a_@odcA#j(88(KsMy$ZfdQWY5nd%X;uw*9kso6zogd{JyPRX{`<7sN$$J zn^42gTD=*c$Yl6pV}*&sATVRyaFJPZ=(KzW61AvI07e? zWtvz1hyp4rlh&x}eMBt(7MLp15Pgx-mja}?HIA=WQ3jpHo5>MBpM0Nn%3l8n@-A<3 zC;E~&I5X1!LP62Ke~UQaa>6oM?H3e18jc>jw?*lh0Xq&MnJjd_C^JgE=r?b2 zN$c2R$nil(!(lg6cv-Z&3pa+R_}WVZoW&pnH{nxd^lczIzPY@N!Z5<2MLE_jKCi-3zx z{%%;cTDn`ailBFs&8d+}>6FQS4!(){=>)95#R(W42gMvYE`Q$MiPY%Zd?PKjIU`!T+pnozP0R-T$ev+mSD0shuhbjsjGXhuaQEia$QSo+l(^W0 zrtw|rxDiz*dHVj-mfYiXr~Q)wPo4W_IZ5ZIN@u|O3J0x;0Kmvk)#iE-y;9hF zr<<9<;hC19R}lL>b>`8ev7_Cb-H|=aI_mIG-bmGfT!#B$T`>!~V_M+2sa_1VX07hZ zGwt7@)Wi`HqIJL!r@6t8sXP!ZG*(+<$O24*ubqmg?y?X|J^UFCj_LAseN*BKTu8Id zc+!cW>-}V%SC7t^P0+zpLD9uvh}Frqb&ETlWM#63r}m@yEJ6nw&%Z<7^yE_lh^@W? zV+;!EmaHVmi;PP{DF zdfwdgT<*CJ2e(xWMa!Slfch{s_xAAYJGQ!Nu(eZ20WUcy(YTB}F zCi(_R?hxt3)nCXz!<`nndCy;Y?i`9E{(;*!P$bI8?Qae_#-7TC&HcT}maa=l=1j&m zT3}EYO@Ar6r8OO?v4T z_;Vs7al`4U6HY){guF}0F>-Pv{-3KC#Ob9;27^A~;{$zr?``pOKpO|aFw0%54u8!*<~BUd9p(`Z&~uW$X2CXo0WgqH+CZo1 zDbmOWE&(Oh(H93?FI`b;El`3?C^F*QUaHe^_oK~)*=Dv6F9}a30hIJ2T$Eo_o=*>b zda%Vl*?wtZHBh#7oHj74PpVS_(q1FTT`F%;&&v9s1bc6*LQqn z8{=yHOm+%WvF()69s3@fKF*!vk++5SqR);^oi+}Fd@reLO&cyMcX%Qi?|80RQt|K~ zHP!>XSaN%yWr>PWhstNrTg~-Oe3LG96FA`}ZX0`PESGN8!ufhJL<76Ry-Ct|gugPaKOJn`UVR58t||JTpW3r4HfrlgBTKm97+!1!j1>+cT-{q1D>J0pS2z*j*u|X z3`7ymUCD=;4M?@EM1LcjL6`J@em=v;MBME~<-wunVFt_C`5*YpfoTkOEIHLVNV0_u zq76J7&H~50!TKC*CeDmq+k9>nF>4$Av(flpL!{!KH43I6?FNbMF*x7~@HW4o7CEt$ zHk=$86j`ScJz^QQc$zh)LuTn%lfl~-g)Byfn-s(3f{}-9p|uuSnrUA9AE^A)KB(=N z{A+f4KK9+6faQjy_*%ze83UthzBeQQ<7$Fl*=oLuv+(?zN!qoVmigiQfS?QPtX?n^ zo-GVEebe_@ktENzU+5%2aGgQN-oFUUnpztXn3Q6&=AMmsIQvX;LGKxUP|R+7Y-oK< z@6#GJ)xM(1@atbs?q{DLOLfWu>;ct${PB%ZSML31qjlosSm3)VZ3`p}L7jSMArBn&?+(fhGq zFd_ocg1KRu=sUikqVx`OBKDlC$wd#Yl)hlkyk?rt+nKTLe>=z&*fuyvGhj^qf&17cH#M1fpX)&4zL~IFvYQtlOmvqQT0ArW=3k1l1H$pEKm$+*M`x{=49J zTZa~S%IwglZT{*&T5Hl3l{m0zR34E}Cec)TX&V?yu>uDjM_0_8) zw7Hu~-M3v9`Sv2UyZj{2Rh~!**UwwrTk#JnkUKkJopZyP(Rl$2NfKZHjAFuG*tv6YlV5?;3)pW(kgX7wKW^=(|!G-MT2^%2|+*Fyn}(vG{BJGjHNWQt-uL&KV~w%Qr>g z+5eEmHYoA@aNeKUD=V$=3&-?>32&Tnd%Pbx@Mk49b!IE+*|-k&*(&CaJO6HWfH(rzb!CmeCqv>|cG6HEY0k|1VD+S6zIfIKzHg z&U@L9h(ur;-C}{fpD7OiSRNJ&1=W{Co-V{yJtpEZ+7%_(qq}pcsQxN067?AN?iGH; zvyy`(VWS182*a${M?KFEch5RlmxlF;megE4tMF7Dlk8UAu6Ng<3YhU4ua}+ z{FoN0o$M=5DZtBI40@R4W*JwhS#-FkBd0;wSekangQKm+x&V*^chg`+3cn3#6&f(t z*`xcDQg3Xt$}Eu3q5~AQh0Sqy*4aq!E*~!<2#53aPgWeYA8(((y=WJhmh@Y5j%T!h zA`-*gdXYyt*Oq$R?$ldTe-BUo87zUEx;oPRQom`dk}*B5?oANGq>wIjahz}%WSB3+ z`K%qug)ccSh6^mu41;q3qK#2JQKPU+`gX6QNpM!mQuEXEP_ZvvjD}-5p3Tafj|SR> z2C-{{94s8VpEce&T}&1Q^dm#wJk*DmU%&ENrjUMP^gD;hZB+4gk!HZt_ABJ63q@D;gSQ#K}e|YNxQ$#xuDjYZ^z%;seHMN9(hH z?ZrtGz%7bO>cL(cR=q%L+Oz0e%)F(7X-ks2TzHr?sVd)`+Fa9~mu!0aq~>WGm5e<` z2;CwTnEW0Egbq2Spua%ejNF`PfX-;V+gJR~*V)qLXS^hv%S2E6VdcABtv{Q@(?Jdu zMFxi!%vEGTDTli#_RQY2YO^p;7hXiDzx#+D=SepU(!%nkv*B`1Y)f~>P@XAcUHqq! z#kcB`X-A&T@X<$;_Gs)W#bFu;+t~ zTH$o&Oto*39=Xn#h z!j;ag^Y^&lfb+#tM|f%FROAde-GoJ0Sza!|8EY zJFBWjgSF(?Xw~s5Eve~h%jox+v>J*a^P<7evJs{zp0S&DPCeN~)5*-9A*IdJ=5M_U zQR-O33qlYGX0LSXK91BRiI?YWopuHgp4^V^n2g@ZCp}Jef}iTh0?w=Sfu$@7Ao)>pRo^ra6WS^^oh}Ixueo zbKrkif#(gGrTs^H_+_!xQ+YFHBU@f$Bu_7#Tfhm(Nf;0ZcQ;dkPWX1(Zn9z#lDh6D z9#o$|T(N8PYigzgFH7>$^y%ZuBPLP9ywzrjVYS^9z=cyBg&!()vV%NQ=vd+7<=dt+ z{AaQl)=n*55a^VQ+mSZNOA&V+SojMY;=SnB>Cc)d@U);5di2`VsAt}np9#GI^Y4F) zLX4KVI+wXEi}x3nx9hUtu|4n8M;TIO-BweVl~g@bmh`Y>ja9G?F_T9CgJdpLTqXkn zNID+gbmdb-@9`>I>o|S5D_j&7dO@qUYs@SY=<|*cqpJ7~Qf2f*gEb|}ZjcCN4_lU^ zJ1ju_yMLiS*H%cP6MSZ=*S+LmvbZ1}8`Al7&g4H?^r|wc2r6t^s3|CVN08(D;z()^q=y`?-tQ?Ou;(5-It$FV*bXhS^-_J=PO(e}ER5@9R-|osqHwjEtuXjCEs7W4Hdfa@e=5SQSUJoE0P4UO zQ#oYlMkE~OA7;=RGuL%b1Fq+tdckAYNTcDTOsF&Whui{r;y-qos3&HV`fLhtQKBQo z0L=A#OdUe+@>#LB=zUUgw(d7%Tg4*fy!5cF-lsl-Yn8+isJ}7?1mDqN;urquG}Vu^ zgS#S5KHp$ErBhS_a!9)kj%ey?mnzC~e`;%L64xg?eUZJ z5NDqsJ$!~U{oK~gzh9wwK?Vj6MNG3BSr%$3T)Kw!Hh=g?Tk^SCgS?Il{!ONx3pC3| z-D6J`fAF_>=2yrm&~U;$O;%84DswM13Qqp!`$MW~Sr3Autja8hVT4h~o%rTvF*TH8D2E9PUWT=Tss$@sumr$wtPZ5mt4jx>k z1vosL>^_F7pA?fHK7iR^D1zxC9ZdXk2(%2%KZP2rwwVYo`xb0j;Idn*W~|5fGigE1 zvjacrO$%;_WvQ8SF;@2*U~LNU6{mE9ku#%ulZEnXtsQNPZ3&v!aiN_2M}g;STA#Rz zbw#litS4?=6_>wuspyz{Qgudj`pcz3+@# zOx7e5sG}X2D~r#Ueu7Q7sq%-O`<~almNw?&i7kvqUi8$)axP?`0$iW~P_X^VT=$k| z@XXAVnjo@TWgjzA*$g$6^r8)9D%oqizTGyWxLiPhzt9EdRB+y5MMO3nmfdWwOr%(~ zGqYFfd^V;A=FAwbX zDxTE16}fN^=;^gAbQQ~l2<){>#84z(Ec~NE+0OI_AsG-Cc_7SvFai>;E~T@SiJ`~w z#>y9}{S&11Dk8{4h;x(l&FHJ!6sGaP=-IEp{PIGrvYq||GA8|^l~>55ccCi(#;D6u z@}{+Rska#OaNy3>>)V9heLhVCH~$D0yGG?OtTo8+l{2_$^tq zBNA@n@(Moa`Y0uFC3ZW;V|+2($E)SmWQxCH+J(i9Q%)vg0ImUG?r@@?}~n~og5 zxT(&GP_31kI;C?`&188QH@$*B?eGApB$j7O?5Be(N3aD03zr_KN;bNT z;aFqkQ*eR_59?zRJkj@mRz8*Bre&Xa|DkT(gN^du>>MUn9olk&d7%<#XO6*JKG=AO zzvbV1$yVJ2Uof#SCq30xZ`Z=SDX}Pt9gloA5y4!5WNm2eW7<5XSMQ78)6-NPZOuLu zZTs|v;+-ZI(~0U@iblX@A=2+nsZA76^#`g?icB$^NJI|8C#AtgS+3x@Qc-KuEKTcA zO;&}}FOAH9T`b#8({g2J=fcqw1%<)Ll?i$eOt*2jHMhy!@8t)gjnPhb=j;PDmM@zv zovGZM2mZIQlV8YUS3_9Q+9fg;>^U+=h#IG;DLp_B>z9!a=~QjGej6Wk>0ummW>Vnf z@lE3C*T9*hp@VxZq$%c5FT;RRO>L+}hm{eZKz4PIF#MP0 z6T=hsg`>G{ei>k%jzul!9rig-0fAt(+u#^oBq-yz<2?V7GHx&2;4zu+Ya2bC)nr}C z<L=>~x}vB=O4=R*cqBj?ukNxqCluT<+3(UJBV$|`1oLj5cRmFhv_U_JG>#TCIR zNbVOoI?N)93L$&Of?VKY9dI6Xlp> z6OD6KbO3T^!n9u(j#)cO3c65R@=G|a3pTNQ@9j!%vUmXJT2M4})elSb{z(?g(v)rg zLNUb}Ft&4ju$ybOWduj*tcdF9{$d3T>Ze}}2zC6Jnbmuf)+s8oW1kW;=r7%vG)(gR zraz`&VyDnFU?t3QQD&l&W+mConYh-xZP?{GN`31DkN{qb^nc02`Ek{||8mbs5K_%!GvTG|~&nPUrckXMyI4Yr?GL zzg8hV=v5ZaZ539S7x7~#%ghk1V&yO)Ln)GNf!gt&bXV)|2g7=7&tVFevdRX?=%#9m zMg)H$X1ad%h$xB8(|i{^oF7`z)}2jxgBzkdRT}`oUuv*a>(q3M!;QmU+J~lZo1;w1 zzPS~Fk&XGkWg5%WWyAvX0>IZFS(4jqBe;$1N30A|6#S>m(j{NA>)Yx6{Jt}l!bHNl z?rN$&6%?M!yl8Q#F&_(_L43;k z&R${o(E>Z{EZj+pE4G9!!oPa3j>u=j^FOR;u8OYO3*E7!v-k#!>(x|m<5v;a_PC}$ z-z)B0BU$QJ+MwLFXuuSxajHF^q>6VsCikI_$7;#^bu{Bhhpdhy$2oST^&5HA9gIOM+SR($y{BLrKtZv&WK3)2%7KjHpZpME#s7lFUyhJeb;ro zQZ%a<^NG}sOS28jF?MenNomL3zHFYYgbWTPYM6hl$Q<^#+Ch)%jT;?6XX(c8X>>k<-7DHF`e^{RGM^G3sjxiimnlFL^&a>uu z>XUWpK4o}Pn%t5^{&L}C$&9+1F{eI`vL1p?;FU1#MvC?M%e3HCmNt(l;vvhYU0-Ov zWubm_K#ZZxI?X(O$3~l&$L$mfJim2l&B`##Fc+IsspS$-Wn~oJ+3+)=TaDH$9(UBbeLLg$cOR-low17HI^C9>E*jo=f1XLV5vRLGoiU?Z6k2Mm$anS zMjWE1XPc@k9niG!=m{|tv(LJcAu~|pDxYKeVa9PUNANqDh{j0#k4go%A9QO$Z%qZf z6|`h@9e#TNQ1^@=nt2i+VcMhg@-X{{MDA3+p;CblH6kTW>8^Hc8c9;Q$4ZoKZnQA? zTgPE5UJ!ZAW4oOK0dz1bo@CO~Xwvk#dnmj4ZSQ^-L4ee@vCg;T{F;w0%_8o!mu!h zd5CDA?lJ@SY^`^j_981EKaR1iufZ(5_U*&$8lv6k^&pSf4yhxcAd+*z^ke$x znR{;YE5>3zC#VfC_`Rape)3SzMSP}A)06p994Fit-#5lW^sj-2E-b+P0X)y!TTs8@ z>h9@EE6DQq?B{rgI0RN$rH|sf<*$vPfFO6^kAIC#P#i9U8LLB^+zcUvN15 zQB7-^wo2&m`TgsjCk~l9_^K8EVa)=NInQ2e3*g4v3$NbzWif2ipJ|uO9vr)+5~-=d z(m43z%W40=cqf)lDM@CY8n$rs5B|yHYXfq6yB_P8r{2m`Mo&7^UPTb=|KQ|NmBHS@ z&Xk!S6Q0itpHU2-5&Tt*O1U#`i^)Jh#gsl0ZCIsTxzK!aa7^Q-Z4qeXDsm%H5Sn8G zi(YD-=q2-Ie)cBJk@3f=5!v8z$hP5WJ{I0`^%=gg`5Z?eJYwkP>vqL>3%Gx6_Z9$q zWCmA6DCN-jT}PTIiKJq=nd{#c>vb!wx=9L?-0^rSao+vCgGX(Qgl7tIJ?(HBq*HM| zz{4#581^0<7S0S-M?$ZBTWaIt*J!{dBJXyH#%xHx(^>)f)#{<8-jojLn6Ke8fd9pe z;=_kK>iZ6a9^yQq_TGX@H4!;D>G7(zTC`Vwin@e@`}2;ER^7ezZast3m}<&G8DGD!HenELZ+2RMrm$hB8}~|FCK;qI320R#}v`*MG{UAJ@FPTbO*g zDD-x@?Y0}9BsQYo!SBiQm)pVfO^qb@4Nfd6$@gbF?${cRD|b`*@ie@&#&7YmkCT}6 zsKdp_116KF25ATI`V*?x*I#f6F^eQ~n6E3)cn!T*OpDvfQO~d~t;lGNr!bCUwCNps zMgT%~&IQQ&!^Y{%fFseHnnh2_Pe6QN7O2XC5^&DU-EtD4Ww|5R(tKll>AH`LBdf3) zAx912@(~zig@wXf1GHW~_@tmZ6jsiAhYnNN!Tve{Zv)E(^s213CL>u1>&VkOxjqv= z(DxuE9JnCwjSj}3{PJvk;R5)LM-0=!vUW$)7VR}WaZd$vc_Fw^2FWr}P6{1TO>%vF zr=NrD(}S=~g*gLEA0~dTZ5qcKWm^EE)wA~&tt@uOJvO(Yj&@8qo4EA*{W2sM9+^Uy z^kDgGC+ooh`Ow9m3u#M$gzLf^K=fwiq!tPRW-t9HY8algrwu%Pm(TOjA=9n9Zv~}} zVwyF7f)j&c`LN}MyPQyz1bMzJgiQJomL!3NiNhqj$%eMvecw%7P< zGt1xT{W?7m>hm>Du7Hy@;v(m1R@k9nJWz@xL1`LFCCoM~6W$!t!# zGbpPmf;JWpjJ@e;H5#ovUgWt?bqH)4-+{RXIwlrQTTC!LRT13zR!Pm{S_n2ZSphklks(!LA$n9WL5AOoBLA8dC~+hHZA^5lrBsI* zxKq!RcrBcKaGO&n+I&J0DM3L9(d}6QRSADkj%VAX&A9eJ!7R;q6f7l})pP6 zGGFlO&0EhOa$x}SS!U3YKWY8N{-Q}QL60MT)VPB#XjonAElee57jIOwJ9=@!8i}(G z)z{t(#=m?#{JFS$MP!hYSluf%{e>zwR{d;Ba*(5^O*E>=KL6$1iq}g__GwhcrVZHf`D5Bc#=cNzz9c!0X zQn7eu8Ay7pfG5zN7kifKFb2#4UtTfhcx#pNuC|B|H5d52uI7}7e6o7(iUJg>#HuQt zOIVY4{z=j$@J$jZr{Tw50H$pe(~J^tLi@uRH0(|StG+?bKs4TmZ3xp;gHu_!ObA?SRm z&FWA^lPy?(9@1Pe&*QHhz4792W3Up1lY%uoZsx%(|xSJ%g>ud_2@ zRn6MXdc46nP?PIi?wWn4n zp!pH+W#R!AE!U@$56T}IKR(xKnhh&M;AE5U1Ma3u5M*6tZ!Q?*h2gW3>_=KU$<&WB zn9%l+t)L8mCh(D>*kfuo8wF(O&l(mR9>g_&@L0aK1(lc3)wqfu3~v&}SANA03c zTux#bs6wlzDfd7q4mf2#>zXK?pV6n@WZluUO#!)vH!S!(l|e8=6WP}n?ep&>Xe?am zHF0732zcC4s=N`?Lw`^Z+Ha{2%+Flt*TyWNuYHz4hhQ7>pDOQ0V-h&Jx z0amHi+X3V-8ZG8Dj}=P0w24IlcmM;%DBgX z2vCq*Pu!)@+qI9Z$n?vWHaWJQ2wTeZ0Jfeju^}Q&tcK@b6cw)jhPkV8n0XUwIxR(isxhpU3bt2e|=rd z(l@{EU$3K7G#&o<5w-MGZVexa|Ng?j{`L@`>q#JEr|>P=uUtJt+RX{;J=zjL(awq^E3Qa$ zxaxk{rCV>&*=;C@(TCPht1;F}jBrh?&!$CD zDkluN=7$@o1bAx$I=IcMFKafOd{Dh0DMnjRu7u=c`4efsK59$ce4=-k@|oh%g%B%5 zJ_Aw$<*dIJwAos0YvUy$WIa1?8SvtSNOhhi6 z^V%m+XSMs}+Ea8|fDv+}sPs_S$ICgd?6cV;DdUz*7<=%iY)PKqi@4G5!D9~n4h9rq zRwHQ#V^qEcVjSvqwe-7Dc#$NkHR>0S=U$ z3&i=CqV>#zVL#Dor^m)+Z1R55u#22iHdm>)`6HfEsXMV{)m^6aI8_f4vo_@~BZ;S_ zM&YV6P|+vdD4ZIauJ)52GKl#PNlFWRw%K>K14O@HYJDwIL_N_!>BHtaPe`d+izi}h zwCWI4n3nP!e*++Y34qro%8srYC zgdGMLRS!?C+pB5OQVqWyEtUa~sx%HeK}b#-*D%*XR3r|su{0hF6cOj}PMrd)S9l8e zX9d4*v~2uxqJ?BUIM8F4Fz`@AM2+&ABCG}{B`|=wtPw=gv7)L`yKkOB+xhVgh51Q1 z;>fjHf(3=cGjc)R7KUE^_#8=H zB$p=6_a(9n1lO0a@ES;fL;%DL`?)2Ygi8A@MIYu#@`+joodQ~~DXs&pHbu z=|<&kg##01TdzlJuD{mb zGx0hV=_xS?q9vB>Kv2YnyhvAPXwCeC1Jt3&2s-tJuybrdn*1NHWibT;##;4m%YCS{Ob<8Rn-s-Q$;_y1xaQ@|tzH{zh2a&r&FYuP}DgfGNT(mFb37HXHt;V=1$-JZ!ykTQufeQ|Nsjna>>LjfA7z zOJxv_N9m%;qkLH*{NHi7sW?cW8JNJ!$7RY`q{20L*F$3JIf~O;H zn9rWUbO5hUW2N+m*VBY`CP6QS31lCw{)=+Ky2omdy+5XYxbkIiK9dI;;SzBv)qS|w zRGDoTx;d(!Va=PGHS|r_hcO2N(s)*C(_^lAZ_j)+?CIXIDErm!)K@kMs097qQD_hh zWjl{^`&Ca^4Nh`eEnM=xqrpLgXU@4Gf`aO?wOj}09J8`^JxsHBNl+$eYhkMgwc)R6 zoRpyyKcI|Odz%G*U>9Y~O;0pFz)=|M=VTmWL9Rqv&&hcppB4*ynVH=s}bTmAM`m`|&a0;sm*grk@iKju&+|HcUSAFfpQ|#79lx$xxFN8$6wS&e))8Sa zf^S+D$dOlxJ%?$`xb107=o8@(wAy&l`(mJd$hs==hMQNiX5sd2w)au0J=uEL2ZSyK zR6H+!W+`7?Kc;oK{OWKMi3`jLH_-)%U1#Lp!cu+&;^DvvgjWUindq6#sQl=BL$T%7 zg8y6-Mn~y3%Z9Z(5x!4re>yN#AgV9(;IKdlwNvyfPj0$vXMWrEcuHg#Tm4vX*Q{$k zUwOr9=8+pY@Is%H{qU=UzikTeJ1C$XBt8Os(wQqN1QVr z%ke}+*Y2L~S#~2s^H+HO@yY$MUv~;Gl1v@SRzOajPSSpEqi{4dWAc(p>ko>Hf4vAh z17JuJpN{uz`g?osS;tQKlo<2ERwb72Y-Wxg z^lwI6n_=>j4nX%@{4!1KMgD;vRqLs)9{A6wViv`j@X6;>)eb{nX)oH{k^@(bBphKc zfEF-Z9@>Bx4g1=f`ZlkuRTX^`eA8BM<*L7zckrm3@p7kUpOl$jCw$W$rn}w(8=Wr` z0fXi#^1e|(Md!LYXu3kUXq!MU_*b+=xwuy<6vEzb#lVoMkiOZ;@}Z^rJ#-!_aBk0Z zIm5n$USq0W6G7U3Fe_c0_WC#AlKI@;hMsylvL4X}hP43h zZ=0S~QCl-O-UVOV(;*T?wuw~XH>@vyp4s;OjWC_oliv30Pl|F{XhSzG*ntN-`qspT zdFDn;MtVE@hKqImiK;0{22jDQbaUSLK<3i#uan(Jxi79$DWdtj>~m-H2HX6}MD}}^ILPZihd8KEd1`38kL88I$sR8n2j@@zQW3&dgjV%Nc8E( zdm>0$U*y3CJU3fv1vxW8Ueo-_3i6{H+MC|JFi*Ge^GrUE5c%cE1s|S zrS*Col_|5}j0=e#p}Iyvd#+pO`u=8yHOfcD*{sM7ojbwEdKk=q%@uRxQ>$ zMw<;&HIgt#{}%NtJ6gzxkC0--rSK=?@GxYLYD<&glSP%Lti7eJA`@7xJjA>BP#wU@ zI=|LB^xS~)=7o)7j)F^*%kOQk=k%dll^^&?C{GQQ#za{Cdufb6UT;L+FAP||b$P$m zWFo*Yi6}#*RUWFQ&p#NWB8U4{y}SQq85^uKb!u4dZmA?mZW`Vz7^Wol0ig$!>?^x7 zGI6Y1dPVi%DU|WN8NER)iE|w~dOi=|t2g$5Cp#0`(aFc+*{*P1B7RmQtana+F)^WXg?;p6x$~LVl@o5*@Vg@0QbY6`Kb(Y` zlj`qV+^-^~4MP$qGD$eIG$?kdXHmRvoI}%AtF9!uNnFAwYsibe+j2q`!-Fat(dPJ*Ap&q}h1QIt_Ony#ak;qyJRh#V|8pxjs3UU~T z4gYJ)+HJ3=qHR%|F_6Q}!$5KcNPz&T?E-CtVf)^6#Bz--IvoX?-Lr)<^+L@})`E(X zL2p~w+uyPFW=s>;$Oz6%eSAYqT76FSD@C0!Ut?9beSdNHl|d&;AWIBfqO|{|*-A-P zL`Zn5S@OwOx$oFb#sxIXeT1UUE0%!0({=J@BQI!ICXun{W^ZBkxYsI7=b_;6 zR8v}zeHd#$ZM724PglJ|R0~u<`C&u}x#>9(bH1zz3wi#c66WhjazT%*@~Cl zxUH^dLPW`lHIO5@C^-+*(`#q7Jd5E-VRjf%F%s3IC&rS(XJTct^4@oKp6Lbc5jV(c zy3b=TM2I=woMghJow+J_yH(Q|uY18vl=6+9(_mV2+q32X*7sgj<%9{l8gl5DugnC{ znJsqvKo-a7`Y-oVzouCCfh^5x9I2cJC(UQOl(jeGR4XH0zLV*)MInB9wDXUZ?%SxP2ky%l9=oG_cn9X{qUjQIz=C_paWAGlNzWS=wjffy*=2yXgSWMU3^1@)Xl>_il z6J>rYM{nsO{B0{+Cxm3iO46`?dFE5<+;hI3DYk6=S7a7bl8mK6C;{du{hhN?k5$oh zSxeiKt;m*YWW&-&Orkd8! z)LKR(_GxJ7FWz;(hH6&BUy_Cil7FVJInt^hF=Z#Qn=HtjptWJYxX}Uj^L%*V!dG*1 zp!|hwtyV|udwH|Vz$+>jtaXu95}iSQdMs@_8H`&~)A&$3+VnvPDGJz+Gw&nK7ecm* zChI-T8fmn{<>dQvo&M?IH}HLXtow2P^>~uBq@)Pm+}fvKN>QF*5p4iw4YQcnc1IBW z3vUQ6Qe?~=YaZ=`DE=dyYgg{8RhN0IFycARB1w-(ZtBKzM$RgS=ZTb_RcG^M;GGNq`-l~r8QbMbj$x>5!iZw@~;@_{9e zG9KK~?;`#*E5fC}(5_5Xo`i&wekG>n=i`G=`rBPh1YEtwYRU2a;?vB#2YOjA6S6!N z>B_tD9RK=f(ocG&x3QiRG%J0Vi|nZ*wLO^M$kgfn!By72fx=TzLCt_QPmHA-M`c{O zsTCH_Hy_Ah0+v@<{g5__#k3pMItYe?!dKVjx``@m71X9VJT59zld59`85;;Sc3=`} z1u9nRFw-Qc?aEF3^+DRWK`hd;Plkw!Sc{G*?qly}ty5VeSbuVeLSw{M57MNMK_Ev+UiE2jDP_|#ln{o8_T85IJ zef)A{GW`Q`u?jPOW#A$#yBRId)Un*sWu1?iW$w<}JGI=~e7qnUp)dUNv<`AmhJT{d z7sI^lwr332WLmu`F}8v_X1yY4xb)@wkQv6yoV)p1=wWd|i?ANYCD|Am-&ktD3Z0iL zM&27i4N?ITh~}xSH5K_l`iFo9v2E%!CY^H6Q#)(SzAf_~#gX;vd$&72c59OX2nZCC zrR@PHW_&VZ=1Y$Cj5Pc}HOT>2BEiOruejGPCn`l)pSOKNgRp%@TH{@PSe&DM1gnU! zNpH#$_vgx#`J-rBi!I^PO`l;2qG^i#v>)D}q;eOpm7GhjFk^BPXwY_Qz}`+`nz=xoLeTDSZd;=kvyq19V>oTcAtCzZa}Ku00& zr0`&XZHwIbpzyoPDKoDj>%r?}%O*;DMXW*e6*0$Yydhm_wlm9IaIlL}?d4fPz1MxI zbuW`Wws-q;x(#YpC=uoY`H%=>5Sgn)OW|}cPnaPmU-gGJXX41@XMv1Y23=|LKfb^X zO0)}MZ0P-{5ldbAY{7l3%To%_-sOyK$XxCZbulHqf=vm(!*22^A% zi2sHHvq~)_R+SR;i49oKudrv)HPoyhOBKNRkf z`wY`Ci&dKFvcm#GGM~LaTK&oP%SIb#2Cs9z)T=-(7iVr&t{R@CXX4h`kW!Gzod6?< z;u_R#H!McicDZsDS)*>%g)k-ZwVq(cu~G3+ zgy5)%%teI_ns|;O_qV5&*pB}KllW;hukK9o5)pGMw$+P$>b4gFVm7m1u>!yV<<$?q zk2zAZ0w--Fn>4=Fbe9~wy%ac)j(jY5a8er|d?UV##xYdTq=ThcZi+PSqG}G&*&3L| zz7f<=sz5=ct&(+J6gj2vS7lPlpLEAK<2@=Ug;u)KlIo?C8QwhPV}ce7op=2jQ8QS+ z>Q;YY?`lHY8Z2zS_S{7l@h!bv3^cJFYz~KR)jdV3YaljOei ze$Tnef3BbBTcobBN7<{Q&YXo$@a`(S;v(~74(hF?l7 zv2UF)J}7eME&&7EI2svsq|Vku^%nbGdt|B>+jUO4`tbO_l<_ZjTuA?_KuU63l&Y)L zkfXt;h&}^)Ykkr58pm%y^;1fO51ep&6E$ti!+Hk&}1Hjid+?vNxhb2q1M{7 zKN^)l3(QI2&TlKLh?YBp`wkxgKBIU8#a~x6etGIlul@)X>lz$=_Q7n@m%tXn zXVV`?Wo@`5+64tP(LSol{&=cQ^WMtsb;-6n&QH01OgCl~^AmYLylPc;EFiGCJ?R4q zt)Ju-()4@ePoGY9ptes|))i*X`TK8iqQ-O2xTT{|gg%0-=dP?&Ug#R!bw;4t+cUB{ zlSoSZT|3w%)rCl_{mCuwCe;DS*7v#Bmrh}Im;?8su2Qj27mFzV@-3E1 ztvZK$7r#bN>uoHK|Bht>-0vtFZk9>`m`tS3THw~(8NGKosO_!*k_qN{*yw7ATRl6?cl2SjdudSLT2p>d){^W;ZXX6KF4Wf0zRc0h!1*n#=fwIMp}r<`t? zY^wog%K5sS{{>s4g0TAL_l#P^t9WX`tD)riy{KM`gLT1r1j75V;b5b zD%BQx$7EzJkbBm)YIz|ew#h3QLT1lB0bTHNY(ZAP3VfZ_T2;^MDQkyY2F<3S+Ddh`y7Vh z9AKK1#6?*~WOy}ts!(EGDa^^5o$fv{e-o$TJOOI8I*6l2F4e80&0zL(iVSDdY2iuX zp;w34NLhuoF89|JLF|#)8`0n6IvOaKFxSPZs0^D;blBW-zY|M{8Nu(H23edJRN1zc z`gwed1$!UlN1m zrcm+>M5Q1g_Oa0CR$adeizu-tug><&95TS4`FQ74qLXd78UOYubK%iD%$pVb>Qj4e zkf37yp02a-m+Bq97ECi|4@!uUg+5nQQh>1iknW_d7|;X_%^mSvh^U}U^XSwqdSlP@ zdwVkURsaj{?z?e^sTS$yeSh7{!lpR6$_fFp?&guKxi)gYkeBkh^^@_b**cVWfy<3x ztm%`3F5a<>XUbJR%EC3Jlm%{0r#?%$1=OxX6LKw$C%=Sk0Ikm}Qj?N&1?gC++j-AY zx@2$N(V8~&q@-0ehs6R*fIC#QhxMjy?G8SO%i+kMUWdGW{{Qs?8~+dQP*xzGXI@A& z=J`o>{&;zsImNW-{UZ-4Ai)YvjTTO_c5PIQc5;bVagnj~2n#r^4q?1dE}%6Z{NSio z227xlg-Z*R&SpLyp2d=smVA?+x%QH%HR^0T8VCZI6(X`>>F9|+n6Zu48~OQu->zNu zsgmL9p2h~YQ;1ygENw=TS*ltCgIhiqyN!T_JSuiSx78Frj3Qh4(lOophKu}6@g#$1 z-D0l%^c*A=-&;@zC%RO=qmJW8APz8ypQm zdp~&Hr>D+&nXIMV+n*gsv1N#bP|<}>-78|KMs=CYea~Ny{Igf_=U1AWJsM@y)Kqg6 zi4kXjGdLUd*n0KmY=4g6Itj71%J0j&rO@;`$(+r!KnwRkj^3nA3x@DnAy^$n&;iy4 zMwuy}a3VyRubI5Srex0EG^r%x!P`D3JXp6PS*yy}2J2%o3<9$Z2n|OOErBRXrQme6 zRo3`@J+&{E$GwI^y z4UwLORpI&{B3-$d zQ9l~)R{^Tx9vQ-)emj1D7$VCsq$pG!?kXK!yJYctVJFJ1^_PYun^4omf96sB;mv$XVRn)Q?Zt^YdriQYk+lLLlQp*F;Uk;j9EC_H^S8w+c@=g&+!%(E! z;WPzh=-nScND(m(BPa^i;PVx2pdd(2H@~3Ba{uA1+IaO(t*+NXaFB^qpvmuBbQ?}0o%>_nXC#wRFNx56a=a$wezI0cOyPl@o)zLuXRZ!gzf77fA zKRwlQW&7kXqPy&*ir_evuKuKI^&3w)Mu`gB6T5vGQgh&-UX(^xMoN7Rw;W}w#4NRE zXA`Ts^!0UMVNI=EAF0BnG#-7D#*xGVWxBugWXSj>&vZj9a%KdGMV;p#4Es`dTh6^1 zUvkvCRHSAdA)kt4H9RT2h&|Ff|ICtorauQ@>x%U~;Jsy*KoA_FNv5=Jy&0mrL>krD z5#SZd;pbg&Ap4RaA{brxpw*2ktzdxJ-TbJrWP66Yh-h;-HkVkYahl6SRE zUwIg0Rd=P4B|)8@>RG1AsNe`6-S{o+3xYvf>)ph2!vwQdY|T-2BOv<~gS#rDK0zOW z77hX3iTJ^e07Jckh`Q4@2}(Rs-P*FE^(|u96r8QK1V|Y6^aoyHu3Mff_-yfDekT4% z7bmYpeToAGpHv>3#60Z3ty~2Y`(XqR0Y^^VMMGeR-3#ejd>Y=w0zGM+5^-Oim|Xi~ z+Y2izjg}BI>&FbQcC~PIrSo~xnBL!(pLVF8rZ?ABKO3cRcnvw6XmC9hJmXNy(|(os zXUGo-3rSy;&ym{C0q|)u%WcPn_t3KeQ72t?Rgtm=Nu!lI^5+Y$GFGsSlvabLJ>6ax z1wKpW0W|ib8xdEL@G|+-=d-``Hg1{{gZ?F_+7W2svAwOnpU+mIC6!yVXu&IQCESd= zOnJj9v$CYK3Y4Ow62Z3IuLxe@N6b`s^?b9i*lW2qOgz-rsh*x-FtSSH^-A&VtB`P- z$Kw@Nj{8L;fjM-CKZ>$cKN9$D3;Q}U5V72zFdy<;^>l{%dIC~rX+SSt;b45YOJy7} zd8N+d^MehgpDC&vqAOt!{JK%yAj5hP5ZuLI**EAG%jwJB%T`|4jrH|gN2wS*#HLR> zp7#lFEQ3yz!-EBS++sy+x;xbwdAB&GNVIbc*&5W8VV_9g@@oA^zMoFhF4{(SX45E% zYZif9v?$L#R0MAc*FZ)kpnW1?OM?9GtG)7Gq^iMMo^72P-FeP`yXx-^OaCCeYF_20 zW)nm7T}kGlkMvn?#aTj*fo6; zl|5xtLzyR4`#B|z>(UdVVd9zpV1Oo=k8)oLW|${~Mr1dBf$JLmF~Dy=g)Hm)mRWdg z38z14uIPKQ|Kj`VQ=i}3hN{JH9!UrgeGAeTj?z0Dd4s85UCg^l4V~*y8Z{c!PS#kt zyk=`+9j_!dPoTgat7i=YtlO1|pqb~S3{IyEsI<|--T|8jU64L2HG`%uW7$eTWM2kH z8?72m;zz5?Yoe=gH^N%{)4jjh$WtQyg-R5V7pS$$>%*VDD12tPe;P;tvbe{i(5&Ls zlo{5Kj~$w{c-~)fh)v@~bs2heHx6iw!sqw%2Yh-G;U&t*Lrv(ys*itkrTyK;r-sBI zN6xP4Yij)TCT2(TlGxoMv@X6=xN%_8MFh&;3`w^DZ-DKJ$uz+{B7;$^jTt*_ZLHiC zQq%Z)){jpxY+wH!c?sh|)$k(iuGKL|_7DzacWE3V64wYRi#Q%O+D-zy!CZ%P3lBJq zh4Bv9$v8dR56%Jd7x!e|M20KpHvtEvU!H)xkPH+NJzt`3hxBPX8CKa8gS7jf*r@c7 zDKh&%cjnin){5{Vi?7w@H+;DkFJohfB@=CfY^_2wp%-e=JND=(`S23;B-SOk56GHxN+;Q zLpku@M8Zmj8T&I2LbvJ{VefMN3EoVi>D{?Q|nW?NV{&fsC+UEk255{1i=d~I{o`;U+hKTHJPf|93n(7*9 z==m%RK9A(I8pYikPi32DNXCmyBvI@M74|O3>Bb^Z*2+jf7<*0Y@rYgbN_Vu79ouEy z>$JU|07jv(cQFAMEdGp_Z2D`(S-JB?i1sMQiZ-`{dn+E&o};l zdwTH|ynFJ1TC4Wvq~WMtIT}~0T2}Sp5$AV>X!K3`ye$Zs=(2Xr^J>tKw>O^z^Mx^X zOtZ>@#lyvMcdZ_G9`4p^!V~&Zn?M*0*qQZngEugpYXWV-zZhl0RFGaX&$F9k_v$Cp ziS@8fu~S5FU5G|sguAgzS_XWeme1+_*Czhpau!_}<%IIf8EOO9ZF&|ubfd`P_T0in zb4&ORgAkPLJk#A$E!@KAn;!AaRDUaTqa21y%HRnZz^NQDjELq(=NU^aqzHe3{hjx8 z>si)mL?%Ggm=&4qbW}C!yrrC{q}AU3R)RzsKiHt(F9AFXd5`EqdMjjCsq?z;%}fhD z%;;gy&+?E&m${d5FhEH7s%>%y21bmtN5nYT`FEp;{}*Y1hW*=hRv%dnUSd5pH{Lz= zVOTBJ4|){lAxAa+H!;Pmxak}0E+SUht@+cDe)uu*94m4(C!(wt>}-xfB5w=ma^G7` z5e?U^yCiXu#p2(6Ru^@)Grahgp1>)|QtUwW>e|%+1y6rqr1_zl<=q``fS9n1$$om6D#mw zX}Awx9pxC8&z8isT)#hKK$n%;;K)6S5O#31oAPD|G-u~MfEq2v2E6Xw>1SwPn1w_fXu zcy5Rn0vnizIpZi*L$9_2s$5rf>A6qTHe!Y#*G^ z;WHhlcFuj!+TQi5m$DNfm`E-blR`=>?AtE~J4vMld@9qNpJlNN!8i=u(X-bp5okYj zdo{SsY8V3q5tAx2OVe z`DAv{*|0Xgv%Q@l! zqEOl*jCDkRaF=Jc@gEkeuc(I1r?L{O55WDIHvhdflTc$B$H>`}bU%;Mg*KhpswD7* zo7haj1pmp8Qqy#uKEF8uHgw&B*@H21FCi2ztGD&fSkWIVi{J;}PtG0Fl5eZA9-lwe z1oH6SQ;cKv&+Y+;B1r*xSZ@&~y-Cp-T~-GQi^UyI*Gk*{3AqbVOC^X`B4M{1@vp;B+lj zrmE+1LQ`%Bpu8n6GOy)yBDDco=06LgIa|G@5iN)X0hHVylhvTXIiV-!QdUY=VS%WF z%qy@8f8s>DnJ`a)-<2P!&Ov~AJW&v-dVR$6;i>~(dAxdekn z-#V+8ciQwb6qdijbF`L6>sW|K2H%~_){2y$3Dq^pb-6iTYi)-)dSAJ&jx55RNM z*YOqS(^*{8tMV0xh-;(115KUsHfy{^(2P2Z8GU8;AE?*^PuWk>^#29uB$mEeaIezk zZut8#Ygj#i(mTTScT)O2;b$>eRhIRIQP`uXxT&x9PwKr!OXlGBJci#$KU*dGusd7` zh|FLyDU_dOrCD?SKDqmaZfN}umYB28p%hW-4YRoRb?X}N5^T z=)@ZEz#NKa-aZe&sh5KR%#HF&$wjbbRJ&*|Ga5Y4>K4j9{u4K|qV=<}@HJ9~eaAa@ ziY9!q3=MQ8uVJ;GnvUT|WzxyfDyqW#O=8r2F_X^P?O1f8Kr8YRGETHFo^|XFl~p9<5&{sa(4OIJE>q>g$ znmcr1nGlD;_E;MeK~&E4iX1DLZvYg4MNx5|RedSjSERMd~6ZwqN5n!I05Qk=|e zWn;>#coI;7JC2`|ZbB$T8>4&@ws4!^f2Xc8P&)gYMTNaLw<7y}u$_h?cf@mS=S&x8 z56Ru!-D(+lVV1@@SO~V$-oTpvG9J=E{F$o-l*~x6L>NjUHWZg@S5#-9_A_DnmyUsL z-D$S9hPS}mg4F=Be=qA$oWO}(5cd8e>E(7kdB)CX9+K}#zIEf|+66i;EBQ^H_8rx6 zC)3y)&Wq8R4{oah=e$8J%CjU}C$*Q$meslZm#g&Rr}Yzc z^-~8Kh0kR>+&=_){wOngkIDnqR4^?MxdccwKkQu{R0jtpfLrGm@Hx8Xr4j7?24tV~ z(*KDmN4)K?dPNaRp~hZo3gwk6Uw35{uyx8g8xq@^7s3(F@NDk z&ZT(<^bA*J^_MfHRo*%?)#~Jr z-J{Y~FiXH$6u*o)tUW8F$UM>&Q1j7}cIhn@*Ed?O@YTC&WUP4Osh}X=olc$vikE!s zGGZ4G*M1|{!t<5t#al5Rj;h{7;E zvEGvzM;|3!Q=uqA9@Ad+|A=%Y{A#IGmklYhX7O8(~ntXnefPA1-WOPU1jy^jveh5Y!# z@IMzhHhNHVr5t4sx9jw&@d_0Z{rx>TZ-{e9nbZPWgx&eHGQQkM4V|9NLCJoc1V{RD z0_Oao8dPvxdQq#)8i+ojp=$0)Eot@#GoDjz>NavWBXZF6&9)GXbE?Q=W;xT-9(C#Q zwZ3O#&!aO>o!9gU;nN8q>`0%r66e0kc;fAmb0OuRFp>9-z-!>!h+9ONg5CZYBSUHd zwT0H2Gc=gs=>RE7y{L=&Yt_x%oLo(-6m{-rZXU&cD?h?U6A$dGHuOH)pE@e}oir8V z)R}ofe^LinbYBj)daZA~K--q$=2H8#&VAJCbyrmKApQwuR;`xXS&>Ib$;-i4a4J!416Me-<)5NZiq5Gs30qI?%^Z0 zTviJnV50fcW@AKkFkEuF-Mqm=UabWlpNJPG(JBn4`!Z>ox==E(X<;!(Te(}!ds-LV z#)yBau}=yK4TLxFUp!4qsib0EcMx*%}0_pmdj_w-@ z)vS7Bldh@M#iV6`LK)E`s85oeX?U`pP?XVh6*0ZvYqtp&O|CnxO+B(l&*{(l_|g%~ zj(C1T$rt%vpMm*DdVNu^thGa2r^l;CfQb@^Bw~J!%{&# zeaNk{BLE_#bY||%_P&m-AM8;-!w`wgcBLj^Q65&<#TK~q@dSOX3ijNGg+gw4NLp z)w-8JjKcSi{n#v@XrUh~Qr<$Jyzyt?*~L-YM8Js=UrU-Ej66$KQL^W6&`C=g?J3n7 zvpM2F=%Y!n8>YO%)4CR1&S>XtGjM{vUp@qg%qP;N!_0H~x735(>s0-@Mz0r!-e`QZ z=;&5`_E_tem8*rT!=Eh`JOM0}Kt86^zjDVK9bhZG>)YD(cS7r9ukfIa`UL+@J+|~c zF8@LI&#*EKoT8<9vK2fycXbMsK%-S%h*clw460&2LQnRIq?>Z)VHD+uXD$p7(&Lpq z4Zj+LYTxpQv44MG?(^e6O*oShUSOH=Zhq=HGYZ;|dXJ6oKslh&U0!icoSqucK|OgA zWt22FHc4=-~UaXW^GX$u6gHuAd+E7LlM@Jt!=lvQ=Z=U2R z3fe4x8)vr#thGM2EcXf4%aK=n(Q@tF?6&7UyQ}`Q)huU|$a{W~b!wfesoVad@Tse1 zU*~)KgrvgM-|d8cM(@p#xfdnCvhYKqSHn>f;_v6O57$dobM*{odciAa~&p;J2ThS%1KfQ^k_X1n@&subCkl`S8ule z?a~mKbb4z3^ad=2;(RpkhfRAVxlrzp6I3Yp^N4Ym8a?2=6%0?jn}b}b>_Yv4J<8D8Btc4FPLsr ze8SPcVaZ_kk+eulrd~W>*UZ`HY$F@r>s^nfN>GlEN%}79o>A3=H?IN02l?z#k)Z@c zs@)&$j2T#8(7x3yar30J=sJe9vHB{5l$bw;RLUo7RxyU&`>Tj*?C`H5d4cXoe#07c z*xkV&BO(3@!cKkRdVngJE91o1zZFB*LCuMj`^COQ;65LX0=`&&Hh2#8=s+yoUTTq-p zTfSa*5e(rzH~nAi#DCxZuO=ac8_@4Z&$WZ?KxML?BE!XhxRrU0KB?#Pd40P~o#t$K z)V)6(P@J6;xsdrtsqBSy^rE2+IjIe6Iu}sEV2!s~(WRLmbW)K36_uo+@J&zdkVW?W zo4-xyAentsF3L6|)kB z9eHg8SbzltLTp9SO43N9Ece+b|GuppNf8Rsu{Pjy@z&i!PR9(AgX)(LQIap8-)zR5 zm7(&bN~;JVp$g;PliHGRhCCE;Kb?I)O3|hc*i7AuUNlGBBM)byT$g1!dj5>KueShX z@BB>&d=G5bJW(&yK~t(!{+D*TxY=0aUGM*-@ZwR*9;5$e?uJ;3+SZA%Xe|um1iUKn3qJY*< zbE5kvA?#=GTblLJgj;*VRvP6K)(u{pw=CH^YjsmL>Q;&)q2SM+MTGPGoSHw1JDzo9 zk0;@4t1mS*wPbPgOu_VYOxH&~+J4q3OD3K}5A4XBx(L_vm^qZQnvFl8&GK}c6&W@w%4$zeJz*7PrJ$Q9WFGjGL>lHoyBdgH=hnUt8~ z?yvtzQ*9fu|2ptY=`%Vjg{N2*zZc@H*<7fz$W$BOPNBXt(ZF&6Bz$tB&#-(SoyM=19+YX+Hk~YhAcoP zv!y-_)jD}VrP$8~7}skZ9UceG%q+oylsSzwRpKi4%{pf#B00)FD(~U{Va%Xqo76eI zS(XS3!-F3v?nWz@&L4Al7qV3fbWtkhC><+TM@826q-6|3A=f~3D8St%?>|!qSWj+{ zO|uM1)t0EK8nMpUhks44;_LgQKG5p**!vJpj{*v4{OnLV$a}OxdBCbRmp|0TNjz)k zblq2maRQL*yN}MoTWqgHMbKt+#(C>v}Vd{FY+F z2W){25qc(@!SQosTwhwv@KvwQp6e8;P|k9!T06T|g*_T^t&F8vzfXbjB+}kRLLVRx znc~?{5SvtC*RGi23U@bq_3E#sl;v$npqC~-&EKS1mCD#^MTa6nW+(FZD#{k!+>oH$ z0IOMY2`9A`|G{)dH-L~)gn4_KV)WL%nYDp+e^AKy>~@y(N4u&`2FAuQfZf(oK@#H|&&-ognvweT zT1USYu<0dYMcL7+N6GA(`{rNSLpZp{n8HgTu*$#uYCcHM)Z+j&ao#i_1-)c2oMMPFX%^&HZveR>`c>C4TZ z*h>1G|6Uhhdiz&H`sSnJh1xDUsU{3`>=E(fQVLzxggC-t>J_Ivn*+qU4EhaqP9J^V znPT1-_HORe(p!+q$Ja-gQ6r`_#O6Y-3bv?$QlCs;?}>0TcBbnnR}+yvE;om^}+i$4>|=n|o@ zEX6mJ>D6!|I=S9l*&DAtj3-$~{tsMdt7rUzgDpk!y|!=4&&p?=jvUK53F3L_C6WAG z=*q|c_jcGw8Vx*Q0a!f++}JUx$^#f8dpV*OKWwiaNJ>6w>NA+6$VzCBM8Yr7r`;o} z^w`1>tiBw8C%V41M&E51ClcF^WoeL^=*Xbm@{Lpf^O2*91BER`UTcw;QgOiGzDRJI znqU2yUSV=vucJIvn);24HZcaq^RDl#M12Reon+Yxsk9bas(B>!`U9OsGj-^KwJJt! zm*EkP9&LnS5g>?!BJ9f7(|YwFN%%g1MDo@}hOC7hW2b=9{jW=J}Q0I;d7u>a;R(Q1)*um6KX`z^k=wL%;EFO%*G* zpY77N=R}KVr-@npBr0~Foe@)2tmX08yT;wnXg&ckJ8!sogWOQ=LEFq>>UgqK{02f}&|LPTxNH z7>`;S*2!Z2Qf3RQV%PK84}?2vHZ@8lsX6c3g6X1~#))Y$UzX91a3MU)d_2j#3tkW_ zW#VVwx($kzNAhVrnyD9jzOF1bWuXtcW5_Dch<)K>J<%&>y^@rhJBLe5@L|LXSrf$( zcXkl&P(2X(Gi%0>;;1jP(msO1#FQ6A&~i6Z#W-$u?cgSX4f_w{Hlo)Kq6SF3vyLBR^11^`{+ePd&VSL06Q+-9S972Yjc1 zk*NWjxou0Cs|W)+A#`ejv*pn40z+NPzlUS5JsG-kH%VSw|KV4=;qjzlB{!_K_I=I( z_aLf@s47tySmqB`ny23w>Rf_$ntitB?XXm-gR?X3$bFQg(VVkLcLzz#*SEgt<63-= zhX{}uX~ZiYx(^vMZ9SO)EM-<_Z=^L`R7SVHb)QJ6B~&d+BmCw;8ZPH30|iS>FEyPF z4F9t{E9j}NTky6``~Jl6MThW>?xL@rtd`G8dKjs#eV|j4IZyS7N-}IgZMAHbUxjM@ z$lOZlQ)qC7p8Y+8VnYSOFb^byeO$2mNt z60-MoF{fDH_Z4L?$v*}%j~*Qsa*uDw*8O| zLZvgJi;VjMDw zcAZ0bL7T~8)5vM@f!L8uNOGasl9Stcd4HyzvVoR#FuRb{&$4C_N5x9oyzRpD>ck%! zBQ924!OvYhIYz3(DF>B=)>=$AB{Xe}Ck%AaK?UV`t5_Vqc|Mqf*&=V#mEaPSkbtYk zaHvO!gzOpW$fbf>ajAeY8kYtr&BLzr4�fwXc9rM~-5x0P%{1wOR@EW(Zi0vN1T z3U=^&+iXL(BM@IpWWrt7tHJ*Kd*SE5btL~Zw%_Lcphy=7=&@IvP!5ZM3V?Y3ai=Wk&v)#jFG#IQAQjtnFJOdwMt@sZ~ePwuG}poF1c0 zbPrdaYx)d*%V@P^lm))*7IWnAnR)O{Gir7j@kfHtZDA0i{HRdAgnU6jApNAoFe0U6 zG*iA4$6%O?mmO3yr;D>%01ab$;WClIOp|?FtYwS@m7tVwwYYY&KSj!1zfs})L(FCK zR`_;Ts5aH_Ef3I$SC5j^14#{h7%`7mT5Y=f*mWN6YGL62^U$PpMUYA0$UI7>=!#uG z#VFZf@)Yizdb6LU04YaAEGxLRo`h7PzB*-XSGW6fRVkjF{aPfW?m$PU)g*G3tLD^d73V^t;#+7h-!fxoRL&7&m)-<_`lrAbL^Zq>OqR`-`lNwnK8tw9DzW>9%#bHD z@K)@?sqpQ1(nnK#>Fu_RNgu2k<@qC_cmGDDaXdfY?i~3%;>;4gQWw9AJR)A}wy<0Q zub6}V8ePeNr=$?&uV@o4o*2W1+-p*dXq6W+UA{ZjHo}u{oQL1R+~!egFsGuhd_+=# z!sS;{g}a?cpkUf>rry3N2FJa)+L-4PA2IbhDSDs%9&}lFN2?{c9w0@p6dK%cPR6+1 z{iC+d)z=)Y&dzITNtPeV?`8Y?61$SJW9WgE%-1I42mb~{W8<%%_9_I<-^vXPV8>J3 zrT?Ov$T-f?#;X^|4vrC$eqF67>TMfjQwJpYTWeZcBA#9;keeEx18q-Ih@0PIPu_OQ z>GEOg!gNo-a>O|AUx@~_PzF|v3tcX z4t3_6C+tmbMjp<(XHbZ(vt4h@5-Y*M8gze1fJR%dMO9~{j+`eIUuTf4rLg{t%8Wq9 zrqQLKkaj3FXVQh%gP9hW?B~2E1J8o?=6T?ZXTDQNBt4K$LjGv;yQcz zI~9YXyi;}UagNgXl%rR{Ml}X${QGkct;b4`>pal0U?f{uHB@Uxjor9VYcPww(d^%e zt#{AOBV$aqj3Eh*^Xg^3Njb;j_VDNgPn=TXpCSK|6wqh2g@MGLVc|tcaPe6Zx|ZCsS@t+JQd(I zw(qkw?C@eE6huSAaD%InP-8-& zXdYt@Pf(l*fLtRUN}-iMasRpD@pu+{UOJ>5>&M~@@W}Pt9kFO9!OnXuC>gG^(*oMW zo9{}|LbyT!FHR5y1gR;l*xcJk7|!hL45Yb?jV^~g-!Ypyk-=CgRx;(b%QtPV)DWeW zFL^*)zo4@oM@k#zpb1qgn&qbp?(2?w2Mk{&3_n98%Nq!^B{KU zUzt(|sMJ<&4|INblQuVJglvd2^_fao5h-C(s0-dO81xDEqWmhF0UB5}RBm3V$+k2N zHR%lk1U5ot{Y2PKT(}Pl(C%6wfEigbo@*F50VH5%E?RY-gI}F{ ztu9`w+Nu83`zIC#vLq(z*WXB>p^BgU$5UnI7~kx+L1yM#@RSbV z@41}D>|G$~P7>9-bLTNY%C4+3`z+!Q^fhcoP)?}S5hH9Hj0|t~q=M&5K9hvEWVTM{Lye*p_=wE$Q>m-Sc@!mq^ynnO4FMgZrTi&!%ns0%qkHza5z7}+%?ZWe_;|zwjvsAhMy~2QrjOx0fVSaL*IjyB64LahN{M%mCZ#>?gYBzKX zH7tWP@pA377ni$&YU7^Ex+v@tC0XciG)q%!;^L|qLRtG2a2qoso$BbR!hqA1RW9Jh zGrKluw3@kSZe~zo=(U4Q z>%$Eu^_PT;Y+%E4xcF#+Gl8dmk?sXJ-w#~1EfOgIUSeW(<J{ z7DYwc%=q&;wK=+48ApWfRS(B!Fs(7Iz5Vhk8n=cgS}L$2Hv0e&W4rtDdYCtjK!_6n zYX$EkWx3<|MJhA#*0}msZ&Qxvn2MV~P52a>1!|gB#&&+_S}O*YoQH;hJ)dE`Jo9&M*VKn_sjz@Fe+4 zf5XXCXdQ9?^K|NJ%-C^wknHOQ%-m8q^VbN!J`M{Zmdog{qJti;dUvzXZE7ks z*^f5L;yVMAjNCZMKeNm6p#5qeHfoz-Ik+3jx8Ztv&uTfWv0`f<@j;O+z@Qp?V$6WJ$wUZ|x)dN>_f==0OR{JUv=g482qxWp2tI^N1kyQGy zW{*-dtRtCoiJVollPSM$Lf86`FhZ%^=&TZCE{v+-!{=Nj-Qw2#6_RvGfol0?FrM}*?U7= z$rAz@W3>oJWW^a6$WLKrWhkr2dGnU~$nxNz*^P~muYAO-1)G? zY;S80Ns}7Yg|-9{b_P8gX#YRAbmp=8?)$-N*X%PP=(5tFu@_{^j(@c(Ra>TYY=f6p z@|f)N;Z(g#WC6+>hRO~-dcxMt!sF8mX6TC+HYhH!>M=Mm5eceQ&zw>X6RsWzf_^Bt z4QGmEbrH=SCo`{n$o%o8SU<^|=&8z(QbEC2jw5Po^&r8?QVzX-_gsk-2lMy}Cx9JMTAG8_Ka>nj_$VTkdz{dT8^ThE;QA1)a723~XMZZu z%l?;qr=@L1>-#HZ+i9E56PVK#A=7C#Y-n~RI%}J`>vd)O8c49EJecLoEXxvOso%uPb5WjJ!PrVrF zwS{bz%P{Z{Gk)&7S~E||0K@yjB)`KLg~bYYv# zX!p8}xyLjhUR~UcV^kCH-84r^9ozV;ao4DHjX-h5u}`(xG1d@8Vya=pAez6chv^zw zsO!2C{9szb_;^7!@X-Q5!vY?S(owwp4F|WC(0CQ5i={09{8QhlB5&a@n~(7q(#276 zW*Hhy@b8S^ucjP2Hx|(i?$L$M4m0!VGkShWJ4S@Tf`FH|Pln;Rvy}^4wI|-j#`~6L zU0P1W>aPeY!*eN;U^P#^NWudsnGT64=jr6g%^YB1-FB!#zs@&vCkdx~g^o^TF zz2?)WxW*97?A&a^6JX@LB0^1e(W493i{{6F808$}>o;2dtib|WbWYaTf-jyb`{&|B z{$`H!9OV5e2s;9(R@Sn4DuISSeI-#-b4&i$wbW(IFa*j&UE%s49R+Q-QU1)p_KP*i zLFu(EmEl7vbwvVLKhn7rm?lRzX*{3i`HQ=8uPq?1@=b&NT5F~iF&6$o5r&M+mx5qBTaTj5jmZAm@MR!{`tV5mLS;% zCi&k!*tTWD>c6G`zZ3rUzg1=0Nbqvi%4LgWWdmJ*#|R-u&1>Z{J977PAMX5!mVE(*Bml&d3 zVXJIcpo5kTF(yiY{?8QnB6QnE`9xW`mcIY zY4VdZ0T;WCFK#H%3Lu%p+kMkTl1Qcn+FVuK^J;JMY8&DVc_sOYZG zZzA}`UA~D0G#dGIzujcDZ7!JiOzB0tWcxf`!&a26_`Wx9oI0|&;tRB* zJ@sCXVw!_2FZ6b|D~ZY{FoG}w{_e(&-_BJPDbJL?kDRC5IU}p7Zg$)H*tvH1B&NQ~ z)YCDjr3&402&$gz6ndDmijUe4hucI&o!=b;1FfsI17COT^b82o9Uh$28FAcIlc%&)68c zaixn`y8IR9aY-l4B(aS2xrt;SoEdp=AA3Y8 zIP(uqcRdH_-O#H}mT@ZI-hUQy1HUCu5)-2mi#9sI-1ZwEnAYCz>0)c5pcr<~Tca)X|UlQAr8etT3=xyBs#% zBw5V>LqxAREzvYZ!++aWABj!jk5>7p#%xf}E^*K?QkDuv&dX~xM;JypZ&#y3SUfmf zdPc*=GytQdoL9|Ul#QHQjeP(W3IQb=TkFrUGjV>LJBikt=p91gU1Hc}^KNjjS#MAD z)n(2{|G%ltL(a()hQhgZ7}UJGDlO85J3WfxbXoE}(R2)nuWWYn3re}t;}?s6M^JEeO@ruu^c0NGF^Jw4 zbR`QEidgM(4z1$ru`onQNKy*b$bJ~^$Z_Wm4JPpRch%R3v8gFcWe)tCLseCZ zUm`BUABXk*P$M3lpdd&%+R!w$Gb;Gc=w#A<$p;%aULzf{h%O<5@00Sr7Dv(OU%dQg z=QespQlZ^&*DCjL=r(HN*$XXP;5)tFlFIjglG5q#_-bZy<|n_juk`#Wp~N`f&|fq0 ztlq&YK9l&H&ZwmsbU1JUEb8{XE|VbBlqFZ1V`4&(3UlNwn}(?yLIsKz37v3IppVjE zH`BGtsz}Wr$Lc<$DkRUcv*~|a9$?c|-UG|W9VM;a>$J^BayEhJj^XcnA93MgrZCO4 z?d{3>>XpJguntDST25B7YCLwtE{teD&z?z3Xm3B~Q7Z#g?T12>6pQkPyOa3u7!JLc zsKlOfha;1|QpXZ!F5ZntiR#*UeON~ud89+Fpc?zR;<3K04yy%F34S>WfJCQDaF&{_u?};uQk~HD6 z%vT!Uw0}{DEcd4t3S2F`%{#=7@G6ty0r5DZ14=v4mLOEHLyf^UI7v^b2jf!j@a;wX zw=@0Gc2z79R$5~+oQJ8y)oH%5cm4mCIfLNb^N&o04QC;7-H`2ibt5641s}*~$<9zZ z7XKhNq@8c-ecgA<=oF#pR4u}W-4j;B=7xc2s5^Y|- zZea(nbEZRv%~M}9;0w`E(vhjWw^-Z8v9n}@RZkrZAC@r(CKT>vcmMGokFi$d~_AnxE9 zbQC~HYq5BT_yc<3V^dq@yYr({EFW)3{l$Dk)FR8i->|svPKb)Su^YJIS1wvW2B(Hy zf;a=nHAKO>y=z^Zs%x$OyRvI0@15oH_KUo3*c;uIWbqV@#F;42jPt|y_st(rK2)5J zW^VX=h(@(Vl%e3Q60?mf5POFS=URLZkdUX4{wz zJX)gRc2u+7gV)pHW6Cm>b&em;Piz;!zj%SiSF%ZtY&s#6ffq-%{DKwM}xduieU`AO2 zt+ROc2t6<^@m8Noby~VYhAb|RB8}%a1DWbTQhEA`PX7*XTy8ydC+r>fWBKX_rRPV` zC(hfy0fpgMzj84*=g3v)9>;x5*7SREaQwk(B}JdlIaV-`J;;XjNFmNUY}lX-pQ)0k zLw80t|Frjkz^^h-;(|`EPxEYR; zR)mI@>QtsL2NS=p6xT4;jh|$e;4kB-d|zeHpVEc=V#OQGrv+~au2t?>y~FgsC$lV5 z*OgjD?Z0*#=fjKgNDbL=kNW1i!YQ5D@OS9n!am^f0b;RAhF|Dm)1z|mxHgnA+d0PX zA!}iwvZJprfZt;vr6f3I|L)Q97~K;!36e>q7Z3f1(UL6oGHLDVu)VVcddBXy7)}@U zmN!ef0cX*u#z9GeHM#8&Y)s$w`8rREQ-GQSF)sxs?(ZEQC{UB{?2Buk;5Tw5!#>!q z)=yJ))&C2@{_y&@dzu{2xaF+WF>VtiOQt;d#{}}GX0JPYTg|}-hrfgDk;j~;D(V*R zTeBZM?1dj^WD(Y3DWDXvg^mWu*UGwNNSi-+=Er!Eu6I)1PUna-*sqKC{A#ksZjzet zx5spmEQQjq>99!zWBH!*V=bD8#2Rqg9omdT-RfH4*;}n)Lpj$bP9|@sZQ%w|x}QyS z5mwmNl+Z-A43#(`{18s)KP=w?CX{iZFn5sw_V3A1`ypIGjCL^%!dNW0Ug4oXJAxho zU+rHwK7in9R{4?!O95I^!GPsaPCnH*!9l?d9lo}pSCqLX4QuosgOC#9m^1;x%yP7p z0CY50TG}OoyoRRpm^q7@hopo^RH{AeGx4g`B_dr@CY+?<=Ta^cAQiSbJR1{?e6wg* zaC}rUjBtTS-B1@;Td*0dLzaHzWK6Y}D}!H`WuBiYuAZm-@lLi!TNpZqcpY)Y`G?cb zquk-MAy{)Lz++LMm3DB|V}q)8-c$fSW5i6_2)Xq~uSQZ=bq#~I$k}UJe6WV@q-uT|R(zE1BD|5xJ9VmFIZk2M^xQxJ7MBm%6yS6P&t&Y3 zLmy#cW}&OP);X#>w#C@m>DqfVWK{Xm?_K72%N?%JjiqoFf3cj_B1qtly_kE>bfnS8 z33Al40{9iDc(4rSv9|m2Gnxh0hXE?R{1bYprXLx90QX`>8CxN?=Q<+{b}Y6x&l(x; zn$qrAR<^OR-c1y>e$V}E+4BAdxH5i+&w~cYxm>AK7w!92?;1N>P9CLBRW56m$KQL9 zI9r>o*;;D9`m0>+i*OOf%38zIBCKJpM5&yNIKTu;k12!Z1yN?hYb{rt7v;k}IpYl7 zw8^BpUF1ot&$em!k+R>_;TbMaNf#JZH6l2S|I+iH%Btx-Lw{O0mGa(BvueSgf4uKj z1#fHJYrJb_gI`Rbt$g&+Z^Xw9)dF6M--R~pnLb_z()G5tt9`TSMg38wh-$fg`g!Gx zB-6<-ab9TnlZst{a*Ht8M44+3LwzgD301;;RkdoS3=Mbi*Im^7;^id0V#Y!>%p zaFJ74%XqzgI0tW{k{cX`cSh)+J^I~ODwYG#;p}4=Z=TG3ebRj{11RQ*gH(vN1y&8h zlBdw|*DYv^FF};E`58fQsBG7l<9Kzw~LDtG9n!-93f|gUMtwtxV0S6OZ-(j-Nb_rocmZWS3A;Zcx=Gne)$- z!D^2l0Q?@jhYLbm&`PMuEIy(2Rc{SS9~F*<&T=gEVf#5AfO(j5QvhkplOsN7^Vn`*qK+CC zFNy9XVCEx{s3SL)THr-|g8M|Ip!j!YXk^~dFx2BMRK8b>!zIMO!%S6I$LHM?LoX8( z9xaJQ+I9?Jd_|sCdRr)!JeJjJ^s%OigKP~ruJEb{$tadeZ#<8LDUVLhn*?!Tk z?58Qdl+iW;;uNnHf*KXPnTKg;HImhWR1{N*2eEzu^kp00E$?Qmutvd6N=@7`1NXH27%z9zck+@eLNU z$jG%2{FS|)fPGHSh)isdIy#Ek>chT?4T34;V`14lBXd1j62#_#oay(5o*;%OG zK_#pbPni>Z#c7(6(tC^AYqM{k zy8YIeC*Zc3OQi905Dm($Uabtiy!OcX&No5V%k1F&jOK>;h+USwnA!0kU$z+)jr7BS zhLxwBrgO|64Orvs*$mL_7d@6+VSnJq0ycZO4a z5$;6Rbc0gNH%<5EaLHa<+L47HaqZnsKH)h3UPwS1m+Y;o<%Z=GTV0@aDo4joOd3OM{XdT^j722A(F+f4=INWd&Um?Ggu#XF8tW3JGW?rVstJoR8S1> z%a3r)o|zSsVvsN%I%Xv6zwE!Ssfr|0dt_I@oske+#nc;k*LG7sdvZ@z zh{!|;cV4O=|4kY)?0F^p-NsRz{dwv7TVpYLExfOEl6X=xBKARm(nm88-hDZBCO$0av>AKF_W#ZTYc1%J8-YLnrc zBQX1XAim?nm=t9iQzjvL$Ps70LSf4-Jh0lG=+W$NV$;{Ra(iv!e!yEXi8F&dx}At1 zxa_AA!5p-=BOD;H2W1*Zq-L=GGst97S`M*Sb{{z&M46)$GR~jGbFd%0gms#=PmN_5>B29 zr}AqB&0!mG$yb*a-3OMa12vcU_nA!)ypL%N?~SC)-M;h^o{{}gxR)Xn^Z#D(TpUP| z(mxWhI=Vkf1Z(t8{nu;N_4?r{SS^Ey)0SbaYuew!(1xVyk8-CbPAwLupW#oIY7K8* z@(-I-=5Q?}ln^$OT#n#kkAoEv8n>hgXb1`qE87@64l*2tv`%61paU~ld-O&{PyqWh zUAc%rw1ddJvzw(s0UYjXwX`KMl$qr*qmy5d@Wxfe2~U%pI)sd(DGeGZzUPMSp)U~v zh^J#Ue02P((}HO&@KOLfwYnFd{mIw9EMsPRxLsR;1y^M`hh*9=wZ``u%rrRS7)+hl z8$wkba5o56OO++BH`HSZUL?4ly;>6x5G%OOr1)8)W!Y2m5llW2#O90@NUh|PPs5+P zVxFAqgipVSH-*9Sr#6mEU)9QVoIa;ltd1y?k!5I*hk2}31I9pW>&i*o)0-_);A}i~ zxervux3L1fPMeK(EwRp0WeB{o7kJ+BY-5}CPyTD&_tzE$XESisSQDy?sQFnuoQ%NQ zzWp~oOWnLZVhui@BudeFVoI1|1$1!lqQrBBR=Pkj`{^2*m0LORK0Lm(AVOu04(+Cf z4Nbl1Fn96ZKMTnnFKd{jACPY28~l_S{ayj9@6ML(Sql>_kmUAtNg?{1p?CHolwNff zCn!_+2*{63HKIH8QF?0|Ods$MJDH4(s4`cGsh{;@d&+fAg!00a6xcbezUquhJ(BMy zz6CskM~CwwXY)(h3WsEk zADAoZ%Orj}nEISb+|P~!(;~bOa21#nzz+71cg1b#1p ziqT{@cmb7X9D_gMS(0+sptl4xpifsVx7>m!WR^9N(khjwlGQ~Dx&-8@6wLaH#1K{A zZJs|k`;A_B7dOgMf=GBngt-bf0GV9ta-Vg2?)ZpQJ-Bjnu9J{gtfW$^^#3!rPN3Xt zkwwT`VVn|KAQ{=Y8rBMJWehf5o;oFSN!Lu-7MLDTB?cV$9%sK7IF}vnsC>63@bS)Y z4GjSz5Y5K>ZUxa@h98#H8M>oCR&X&=sPN!`2t@tMz;76^+NdbMPQoU^dl4`t03)2c zfWMet*Z6m?!tmX9A;;xhI^paHcB{%(^E5H`4EX|lQ8+pk0}V9~^|rX~*>}@XKzS!RlQ0mGpGs_W1~ZA?#7Qe z#3efv#OHB@)jJ7giGQI1tSwL~ncx^6>Sj=mz8f&ZeA>eCr6#}fVSRRAi~P+EL1Phf zV!G&OHzKFwS68}X7+d0;4xzg4+yh4cCohNNpOK5>deW1GwXq44FFfBvP7M_>Rs6a(> zyAmm;doUNS0gS^IaI zN&{R4Wl-n)IS=gCLQ3j`c@ZJM!i|&wu0|UDS=BT<8)wTI`ej=}Y@<<`8Pnu%ZstpS zBC{=BN@qj(%=X391d^L18v_CkyTg=sjE05wKb3{<^h<;?P5eJvLhFCaXi`F#o5g@_ zYY~X=e=Ij3LTw`K=YwQ@pPO!*tT9|qPU9P0*~4k>=VH=7bjWmcS=2$8A)>(^Wx;7n zTtAJ@9_+VOB@<<1P~(}`SvSvxEl(Z zTBr!-s$em_W#lk|(YF9HH@xX#sh^zl9P5R*iVBWBbK8s1l&@NZS8tk>3eoM^tQBJV zi4QIW#{vl%flase1(W=BJhNow6lYEHGMvl%34g@J-1kluvjQb=|5ntAk9y7FvbuM* zg13v&J~S#z?#s%C?AJ1taUxnYDzSzt8m{G4f1{UN6^*^uFL`Llxg(HhUP+MyjJbq= zusBF_urHKcK6xF$z}payGH@ip9POS`TP9Z@EG3HYKk2b57_rMXSroumm5^NLGl1uT??ewzkMHuXJG?U!7Y8dBLtPk-Ps*qzVlIKjIs(fu_n88x!_2smpIoX`v zW-KtHxdiQO#1<^;7HcHi*yu`;Tfb(>$Ua3?>Y{uOj6TfS+n9|oe_Wk|TG4MV*f8Rl zoFYADIo_`J@$q&1jXQ^rjq9j`!21OQ+&Lg+6$pq`5U`b7wB_Hcdxr1ZwmmOAbwKuf z{^dccdMB0U`=*S85NNNTjZoH5Dr6sgZqjYV>-^z5?9%g;b9gc1C54W1Zjixt6nzL( z8SINyr{ouwtu?nG5Sfe|t~*6T6I{bJ=Tvs9mjN2SY6-;$Ce1%a@nW=lE#)}ZM&)td zlX?&p!G`=74emldFYu11W0%B#vG!cm6|CoXQ;-?e3yq0zeqXS?G)O*+B_mm^?aI6%J%K#eq=4rL$Z4m@Y5VWXzp4h*z*x? zu`CX*=jv~m&Dz~91h{xIV*lp0>Ylt;z@Y3IcgWcMGD)Q$wT$NSgzcAExl-9IhkdU% zb$uMm7a&jIBDL>hfJv59yVm+W@!Y)DOQCY-9Gi0N<5=KtG6#w$4;BD8-1;TlGVEtS zoOdQ&t$fZOE`5StxYU_;jVj?%@V;hgXTbbLx=c|5!Q;x2V1^+=C#9fHX*_bW5jn zNq2XbG(!xCq;z+8Nq3A$cZa0F%n*_@APx?E@BHq)e*n)j?7h!9Yp?ab?}z)=nk`ZV z^{gsX|KzQu={Fo}wNhyKkj!$+Rk3f`HKvDd7N;a-3Va9F)*b#hTal!6w~TrOnqalr zVdLP!12#AEXU8uZu=CL%tfF5Q<3bh`E1XZ-`Zrf-!aM9l+zXsx|0|Gu5XljUdc+sk z6HT)po~-W0ShF!nb4@p6i|^kBlaqY{+_!W)e9*^{u}P=N;nC9!Vrv=Je1n#`dBhxo zVq`Uw&-!#urBZdd%)C12`^M2Z3>{VP3FwswuZoh6vC#wauGj7zCO5ZIUvn1DZZ-L5 zw2cQaDcjVJ7%||-#dY6P8dPiv3MOkj``E*&_BZDXo`xptYY_72L3Ku#$AwEyWiFLY zbk%4qk%85s;%a%+@2T5(%wZ%8kFvSQ%9Gi~FRYm-i3y&a;>2h9B?bY>dIn&s_l&}N zfk*f*N&-iCk$98OF|u%JNz$l1zzfcvfBX2WJkltAZAJC`hC>_Fz6&K}+Zxvajg+mwoN7rtsE8VpD{N>CtZ z)G(7&t^Fn6;NGE6$Ei<_-2zkud{IF5u7FM$x+H%C2CM7Oy{pHmQOa{vGQyk#zx0Qs zYzJ`jpL!jP7mnd?-?lGKMIa`xQS1jo;ZMPq)2>`2LViON{8&GlV|l-zhuowCI{YJ{`rNy`lNTUnW~ zI3G{v8imkDfh-BpdZ9ugeY3A5bZb0@2LaQgG_j|%jLb^!;c*b-f@}YOpamYMe_E~q zMo&CJwQ`K+TSt8vC2f(HXB&}k3~{x3ooljs?C}-l4)@qV$gVY1wtFqA)-I764XCxS z&}0eHbyedL#*9fzyNdgTmJ(Z&r2I2ASId4LMCZel2&XTW72yl3Cx8q9)V-I;w|}8% zbecR~EJMCYR$|q-)IUyf>MO3$usv$OXN8b2vuiZsZ_4t^iqGd%<6mVrSZupBavLij zt1ucmy(_Bh)HuEF(jkaDG{eK7iM=yj!`7Kao*Kj@IJR25$Ar_4i4b6Ba#ttu+MUeil5wuTVrQ=nagy@?CHl7|9GMKaTwniv z8ieDOmYBHrL5N+4lJ{(0J_Go&cJwfPzSTMMXZS(+d34^`*SQ)&bsy?Ay|OnaWBxPf zrueHof|nngP=_pvjK)ebx?!!PVP7&}hvjYU3uZ1#Z=Pe5qfZuJItblcX@Mptq&@RN z=^;@^U?V2-4^3-KQ9}|*FH6LBj_8E}R|h)C^<{5{f=1V~4}%4RFP`sevEw)0x2Sj@Gv@QnytC!Do5x zic_dgRPE^;Ffg0|F*QUm-yPIX z-h*iVw0iznB#M4nLKbftPs3O9nZ4SqykQ`;XktzA-t)U$e`rL$R5^4uTxJvol80CC zS3_sbLp6SOipH>SbSPVzZJZ>yew5Fa5AnwqbeXAG9m5vz#)ea52vZ<8y;%+rpKCT) z2fMUa^)g8)S&~gPf{f*ZJvApi#`v4Eq5CXiBJ|knxfBOSXHaBc8*(z|+G60|qcY<_ z?JMh76VlD!ehmrIBIQ;#*L`dv0B4fcPoh_0eh5);uheYIzDnJ1>#|=f%~!l$EzPKx ztyqGoG+GroTlc>&*9C)wMFq~buT|RClAHQ?5n5+ksVz(Gfag&%7{JIKJ@;@Wo~A?NIeqgD z4<4+(rS@$(&F0zE*~G?9fg){8<$q{W-+1r6Spde?t?+k$S|Bd(sKTg#wXY|oM0G|6 zmk7C7UW(|A-8OTjG6u~>>F`oSBqt#(~;YNouFlk40T8+b{nNLw?l`l@+XcW--tf4uona|fuV%|hV= zvq17Z8m3`=`eNb+b|#Nhw>13+M9>VKE)1_A6?|2C(yVoEse8Qg?XHoFtT(2n2;+Rj ztfh+Uw$p*03aX5TcKB{IYc7>c#umm0c`kQGFwe~bJkG} zkb!<-tIM8rN|v55P#}XHWQ65HBW4G9+~Lj(_|D#>xqm_|vj^2UI)hg?0{ZlD(FM?0 zch5^KD}YZz1GgxH%km&RAlGC#9S&ruw!-oM{kDWW!6tvuBe|X}>t4di|8wqqpQ2o|Ku6VP#Z^QQIBZP~7H(BN+mz#Itm70_{sF8iJ zVJEMMbfToutL1!A@mO&_DF=7zut)fKBVwS*=5rz)8m=x&@_2!wM2toS${%o5)&T}c zmJ)?;9;|3IyM(XyODTcIuFIv8W@pC3F4kN#x%%JxFT!T3PA|$oW9mA}cAlVa;B+=) zH`9yLyzJhva7R>iM-2(LmWMH&1HF-BYXOagjl<+dzrCVnp3v%PDyp@16LUCveu}5p zKUzpj`}l?>Bh<>yh8^HSRL*%)lg}hQ*|hrlPrr`lIL^qES_to}O`M=_f*gLchg2hta4kx)d{SNf- zEGn83rGb?Q-U_%@N3;3ajgq8^+eki7@un-2uc|N^x@tpmW1KM^ZD!5ECrWH^1eiWY zR_yLl;^<`IJ+Ls=NuwBtp{e@@OUT6v#dqtvL0Q9&x+bysNDA?l?Nif&*`QD7n$SJ@ zSHg|g{Bo`w-Inr*h?Uo4!Jm%JfLB?h$NF2wj9J%8Q{#hS2Tni}R9K#pKfcNwojz(& zuaWhBRl6Duqcz`o<_F>tL{fMfIyzC5a-NgC!gEDLcNs@cQ)&%B-?N}N&19iEo6sjp z*5;mShS($24!=bhyq!VHORQ^6xfZOr^nq`&&y2DW&S0@HP&lGh>arOSHLJ8bWNsA^Ocj+K%GJ;JmZ@Nzj^*G}Tey{k?aS z5=$D1UPgPJldzjFQh&*j z600srm~Vf4CFl9G@dc9qQw0xjar8?{4`KjIow{a0NW%3Nq;cm%AXkadw=H9VR4kjS zwtcaBlyll+F+mKCI9Zwfui(aInZj zC_qdu>oq@9>(~P*Ex4WgXX5Z_PX_$*^am@J}|vm zLd=VM@2(-iq#Y{gL43YS&_*tu0cVa<>O1{aEhyxfCas+>OBn$(y3mF}L6>IO>OX|Z>Jw!a_Jhl$rO zb@L2;{UBL4CIqgTuvyqrHL5?{1q3yo4O{hYw1h2t2PeNAT2q_mS(cfdfF|nR`Z5b@ zF}}?>!pmeK=@^fA2jUIuK_s}=)fP%kQslOjKW3#R=Hk%YOr88@AZPj(Rb)JoO{rY^ zcDf_IK0l7P=^Bo$4x@cY7fv>w>b|a(N&Gfq>!@*U;&#i=usg`DLSbeg(aatKdCcG} zxXBz>sZ%jU7{f-VWz4MSJ~t>plQl1zlB_IU=lJdsRvAqrXkJ8rr29*@?7uQtw&ke# zVjN`xI#882>{u5$lQ}K%t*$>P`|2)x@cp91-lTKA8g^ax%KWXLl6Q2M8`nhFTv(oB z)ecRp0NiOiFae?D=^2VJf3ah6mIJg3SGE?A3qHlFYFktBd^7dE4R?%B`r*`%HF(Va z#}Zyk;{5G>#*D4pCjusPmcOVE-9leW;Hwh!1{Qi8I27xz(e4L+r?iZRzse;S6tE%PVkpEzD~mP6`Az>Rsq06z0?!DQHM}%S*95QN zS^vni_$y-3_$4*{4_w`|DFWnx{$Y$>47)K9kF0Q~w+vuWy=%FNC#<~uOvgQ4qqb`_ zgwWcJNHD=*x_?CMXgReNmwzj%h0c~)vBm_CNqhHJmJ{$omh0I8U_Vphzb2I15ogqa z3MJjqHR?(x&4JuUGcco71z=UnZ9xRaN7z^v4m(7VT^o0O5mJ2Lkjr&D@7BA^n=MCu zVOXj93V7wf7EUCq7k7DD8eL2lxLhJ*&VpUWD#4~VN|ntpV?QJ#X((^w%lBty0kz#e zB5-2oAnxgz*=P>F>P1V@YPN)&WT4NA=u>&y!7J_z>SjKjRD-X7LIFybO;rkkxi58X zy}M{ypMRpIakTx8F%>Gyks`g)mRlvqEFZ6zHu#4=1Cq&WZr~~UCVuk?JBq%NtoylK zoE}e4fAUMjM^8_e)_$x;yn#zON^yqngs(r;H_pYGz6$d(w-b#Uf7^Q+^xX|kn#bw` z6G9hcx$ecQTL*`Fh|MP+qdzknJ66Q6y@_k_yDq7}h-Jjnqw~hT#7t_(0N)b@1u^`+ zVwJoX6ppa^xfw|p_7Y1COl>izhShj3>Rrpq&M>jrXwl9m{*JkJo6UnpE`B0`P#U8# zt86#t5;mET{*}u8pSzOEKoQz_r2RjOkfLv<9C=Z6J38GP)sL}}ET93mNCtUb?L^gG z1H8{`-N7Fl7H4^1)YON2lg&ln_H-*}4=XiLoYojho8r>QafPeQY{0^;JoQNU?FQ+N zNTp)eszboCV%kPl1nCIUlF9jD#dYUUY92Rq-?)S%3#FN1jBN4nzp}FCCWsDXRb&Sx zfgmoMH6QNjlcylWF%^iOhs6+FyiqF{+ps-I2w)K#?W1bBjGQb^VqWnCUF<%+Q~RrwQh zMU6|vr(3~)N~fpPV1w^p9QG>BFx0oX*2;Rg=i1lYX zL{6~(OOJ825&~D%HF~JtzV&1h`L@F1pA>_+*0A;h_!RjdZc#IcXKW28G4W|%*=EZN z)0ShLoN4lv3#HEg|^V^u1L31O5EH{a~Rb4+`2+T0+m(LtE4 zSuRu->Rqr!i}hnirK_Gu6L?@!)S{j@&TNK%CjXvvmeopbA%#Y)CtXm+oM7{hz-;O4 z^<1${^ZY{z@A^aSdOh*=5%X(;)pY679E(|pP?c8@^gpF5aK5?UC|7{dnE;~Z-vWiG z2dnB~tmZ7pa`ZJnt+vI+pUCO*m|H*a$*FUqxeO6HRK<@RmWzan7T+Z#4Lg{7da=2sxTj`t%VVH` zZuFa7Pt|r$ae#*Vw9qA&Jh3a`_LIkf`htEu*=tMS3lro!cS{&CPdc^v^&(>SKeYMq zH=Y84b+(1sHD4(zHL8sMioC(9#JYo)9s3MkSsw%bLPkRLU@5+?FbdUzwLN`8dOs zXY4z%Zk|W=FkPg6wNLi!uYKl@BcU~6+&(8ur#*&9i-w(c!jI|KMnY#fm}On&<{Gmc z7x#g87Y;r7yew>~q~~S>D_JccHQ3?dht&Y)XWvE?A}e=rwetKwv_o$;1*{^W;F9Cb z6n`R4v(D~Q*z}Cj(Rfw08kr%g9Zk&B{({;63%my=`s_PHz%}~~Xa^_}UFM16cK2jA zwXFU`ruZRquI=YEct{fB8-H5Zyl;t`@uOU>VyTFclV(ZF#}-s3G2iw%6I*Y}#+6>u zkE-Dc#V@ONAX|g?WWUElX5T8-g8yFe@yJ2wWh?+z+n2>QeRp0*IP?2OS#wN%Z8H zx}>#;s5k-A0lR_%)-e{VsUB1K?=&YlbxJs06)uls%p7$U*tS{F<%S|^IIqo^|Me-v zHV5kNObnz}zG(dR{ZS>E^m^&(Zv#)pwvZY_+CV#3FSTIXMJSbBeOOsGDtc(IgF7Jn z`@SiL<1WoN zl!W3nWNgzicB@Sw?v^X5&k$Lu11pitdW&i9KOdKW@NL}|AG(pVRwjyS<99G&-nmV; zt5gFzEMQe6XLMGZE!+4XWE;H}EE7EQ(};8?KqUB&*BQjQ%Jp`%^5lyPGA@Z92VjBu zb>}=)QeL@%{FHREnj1+iAA;*?8zjMsU{c$}{d-i4nn(V4nh0nE^xr=pwpx7`OPuKL zi3uBOue(!BJ`ZUM{;b64(urx4G#WlbzzU~89-Tl=asp^Yk)bCb0oOpYXw{p-S>gx5 z?}0D)YvjqR&{wk0GLq~ADc~d+85nb@k53YPPKn%_-HI@QAfVOM4UO8m(KQ{GC;5`5 zK)#bDeFx|8RSJME6|f9_#9Fja5x z*HDQgTXD1^f9lF45QOMJd!e)}*KB6I&O>N{}o(L$tJn&InGaN#@~sr(xh)a><;chIv8p^-+FM zwS`G_E}575-Q@h)&(F_#7SH-FkIL0h&|DvK$I*`_p;o@E%Th7@IpIwwz zOP`smj1qJF8U+RWh6J5Z^G#1|3cm#@n-7Aj`hIjfiN7AFg8!}JF|rGFnpA&>)Do%E zrF)3}A1z@JcAb6KjIHTfrYQ_nE=tk()KO|=2|CFBh25>9%fNW+u^R4JieN*%jo>8D zKL6CU8O=}Oic6JRZI3nNcl+(wX*va~)l&`zH zm$OZdF%D4|DfD5FHhZE;px4WMjoq6Tj?)|0N4$dhjz7dnYHLJmQS%30naE2?p(U_ zW`CALy!Laga^2Rm*o*eXA0KT&(LksL>M;Vv4TAQj(+_t4%C7Zv_T+5wHCV|p3ZEyo z(jtM#wge9S9o!ONlHRxv0R~MIK$qgEOm~UyfSa@MOmt&ABl->+LoPRMtFxji(Y;4r z*%&yUz@FGFvTDATQfl`xa5=uJ)xho5lT3|rwZ-Q@i8i_ejB6}y1Bzcaj+hzs7Y^Mp z6^Tqm>g$;j6YQQ)AE+WyxHz03`&$E4$&`bdu9__G^`>vo?>x41zvJl#E3*HW)&Jk> z|4n58h64j47Uyo%IwCko+`m%2T8wN;jxEIHHO3Y%KHBLzqaCT=4TL9F>k5QWIBg z4R~?>&vd!@+gj7(N0=rJaeGRvIEPNe^bS<;_*DtCQ5pr0OK$CH7bW8EzNW17L7N=& zX9$$}DMDImg0ML-Yn~_$^;qqPn;`PGHe0`~Q!>0I$7mc0BFz|m&)=Ke+usLvlYVOd zz_j`#3HMvD&TaOo1xTVmhnLkj0vc-j!ce{F7(Hxxm00=U=)R8Vzq-~rD62RD-UO`{ zu4%Z^5frE{$893YM5%QWl6-UH|0?S`Xt_Ig-^jdKTNODn=!t6<`+fK92KSvUfcf<# zVY;cj?>TKUmI{j_-A5FyQU>Tw*=402L|=ylESz_-lX_|3Crhc$VrIpZm@az+Y)wbq zdu$Pd&R&n>OI!_MFK1$HkyctQd3AC)boBzY&k`#99UU^5m(%-8b9G}(nxO+tCe+k> z#87k7a^ptDaaFtTu`Tg$jY>nFQL3GV&}Ro)ZWo|KPwU#r>X5|VJf#}Tms*PBHqZK5 zkWaoz01F`v&9+z}A8Ha_8aXudrw!a}#wAuZIJnA^j1;bte!+|{ zGvEn#My903`|{hH+^Tlz<~5=mCF2rhVhr`3@2^g|Hn~dNRaYZSKTV&iv~{4u;P&?FkcyGgn=b&>)D2&q7OxMi@#rM~dq3(`ljrUoFDNzY7`_Bu!r7 zba%J+)_qm;GIq?Le?4j4ah+W(Eix%fRJK_x%OMoOgNmhr^G%18ZT@<^3-N>u>}V2) ztdzTb2OF+)j8Bs21&ZSw9ePftW&W@_s|Bh&t05|9B|InEApb(8oy6=ZGN$XS$Ad_R zjsr|y)SBJY{&+=)uuTz5d{;X*^=7A*${Kn20KU#Eryv3VXRfxWx<)onV(qY%4D*RW zs-rY{sZ1U71=56%1gKvPUd$EF>RZH8 zrO%(6=QE!|Bd+bk*=5TL$l z*`I@Nc)0RWw4L(!?!;Sr_34C@ZCqi~V`7#Nzvn~MJVbV`F}@2Gz#i1kdJStZ?J_Vd zGr^CplC9wYp@Bc^P)ZUDwthf+=t0+78{9-Bm+!dJ!!vUpQ)`Cp3p`%~Y|;GO>E0N$ z(8j#ZZU%VI4zm)mMc?h|bI5W<@ROLWflf#qhKyp4GEJgheqv<#!H1$}?WTX=m^`XG zOFzP1hjveb#$@wl>|o=yNU(=Qp;`c>aq14M^lSc${fU(qGcQ%kygq78WL5LeNK3Be zXwqjRpXl?OWw~SSc|amOp7%1CXzkK}*)0o`flD?c%6o%8!kZO4gk7!3(Y3*$`dw`R zlO{qaNw~zl8l9=ZV0P+c40Xs6*BOOQ$?AT zpEm$0AfVCY&jUC!U&fG)_d|5~!>I5VV`QUqcLCUK*niCfE5+e4O=H$v(MDd|=xAC_$;)sT zRgJGJGl)%UGP5e2c+Y9S1BPz{f~IwT^VOb*6t5TQYDh=5u8{Aus$qV6-NEubP%=P> zI?2<>)`*(l6+&#S;Q}h62;2}w;mTXj&Aejg?Y$smzxq^PMUy(%_gqE=NmKRJtp(<& z`ufE={|LK6ra8lpb%+(no1LAhrjYoXuS0D6GsgLQW$;|SB zZ&^>PncK$q&h5C6;T+>N48!a0n>o63Ah8g=s@o$Ugsm9)6E(_PTrRQD6gg*{XU%dg zSSW4tg*4asf>2$K#f$D|M*~;e%?nsFPLk-pMNMwO=nZ6RBF&BFM%ZD@XV%D zSfXC81(%9}KYzM{KkPm5K@JM-H|;2Lq@Fw6uI~$-FsE@D|E{%|VQd$_w|Zwz!E5rj zCuAr$&vwYBL!H4$xS{Svsp_mf!z#A}n{mNaacxg??ew_>`zMJgx&6Y8?Ca?H$S=p< zi=~U9E=&@@ILZ0uo;qQidFi)yJCVxN`8ah9mn(T6x^-#zlEW&4gy5Ed6Wzd+eVoYX zG@OjX)E|k~Xq-Vi!xmU`I6Yf*ipc#n`YE6n{7sXzY{Soa`ibD2-qOP)&+hNAk;HWt zRsEU&(1dMWv@?0Y+a`n6wVj1Jnal%N;_Yh}3Nf|krvD3$nuOfI|5P`qkyuVYicF|M z+gHJdenIpK#BB_^jq-2SMyj^A+^Rq5qa>!&I5{zFqgb#)dp+b{jp+27L}zd~(e z{$Q1vhCwp+A_Q+f$sYf5EXQ341H41<&Jr*R*ZdESPik#b!m2)?LAVK2<#_+C(x;br z2A@uzLm4Z!A~yeijq+{3HMd4=cd2mnb|qB`EN zPPR!0vKr#Kw$2@X6?=dl0v+a7AqP_gv!Sx{_+D_WVdH)cTn@hBN^hn~=@rIjsHmHd zWb%TY?Y(+&Ea20mbL(@!vo67mH>dieW@?_f^7;yO{!?g{h=l)OUHaaub4MR5PE9mv zIJ1;8I~;m!JLQ`mPJE4+xSrBP$q7|5tv7hS1+cgu)=a;wp84RZTgh`@%Xai>APmia zrt=2V&tpyX4mCtevoacj;n7*aChDCVs|Q6KM*Qk_t2W?eTZzI+=~NtKj%>wR=U56x zfn`6dh8?d;P>WP#w<^5Ib0$$e-d*X#^IX(_Iox9_f!UEmDd(<>CLH8|8Qbi>TH|2* z1J9$=X~C8W;{>$e&0%EQiFi~0FlDV{Vpj9^UUXw7c4{NjT(;aKscjbGGPs42Q zu?jFg1$|O(-J_V4&3^un3V#o$Mq<}D71(PB_^!w?$L27{>%MRh0B`x~EBDR8pf``<*A@ z5*!y^G=~UQo@;#e#ee~|XJmOyTp#V-Nlx|Lf>=qUcLmS>T#aRawo~Tqh>>+YHF*&V zdCZId`mz#Bf!P-?6^3##uc8`>c`~ZqaPoR@nR4Ei`@bwDxLb#oeCIRj(@X}G0I@Rt zKW-wE+9`riV;NU_Nh#xJU))(@1fSlj|7Pa~L${{1qQ2V$m*4N0@@CKrMW5GCsWi35 zM8s%&0~)zW7Nxo_^zg(Gyne65hOD)4ljaM)U+ez!>MuhRzPZnAh?%4+R?89SxUatF zw@IJ~?QLIEKZ6OMWNB3+@=#-k@r|_2f}%heFssq!3alc_0MP*50Vt{*{ z7bs9NCZmozZ^6hR)JYH=oDQn^9jQ(GtuP>*taO8X%~I{{HU`&In%eID9F6@~BY^no zozfNR4@xrvQF**HW;MBvjq`Xqh11+1^_|@<7hl!ys$v{aaPnuA+1AmGk&d>=LR>AE zEgp3xkp^0tJlnaM%~2KbfFHdIygmJ)y&8tYX`)2b>R_K2T|&E1krGiZsiLHnLjp_W zKV(ST%K$G{tv|u}Jp<%mtXg)TRJHH#0QK7Z=zVkGgE`UcJDZLmrK2L8bo_FHYv-=o_JYLKe%39|W;=;P; zu1fjw${)o4JpQhwuYFGcLj$<|T<5rRnhW+vgC4_kz(N}S1^gw6RxzxoWQ|ZiG zlapEE_G8b=3SXJE6kE%%X8o+7gx*k+go){i24&DVp$}`UQE1etJiXoB+u41R-yhY6 zvk-o3aU&(`@8jK7z}l<)vm;VLblA50JJyv_MijN-5vcIx6K%2K&roQr7-J`>wVML>dZA8Vsxg!s2Pe;v*=gnMv-=&OJP>9ZRvVD zffn;iel*=)UQzz+ra(vJyAEK1N?gz&>h@%WV4IiGTW;x^?pzhA^zj!CO-wfQ6u?3Cf@}2xu;|y$UFfp;=kFP*>|**RPAW*Y!|8feXptN#v`m@YH0?t(=R>8mEwf z*{cY?Rt&)3!k92zxJVc5;UJIi9e>-knGH3`D8;?-5wNRL_fUM&5>l)Z>0@@FYNc<1H5eB=EIu9=z{0OA{( z_!16I1W7G=%AQeo5}R|09BO9BzD=LGyuG&W=$lJ|eJ01%!kIa3w?<61AjU6Aj9`I< zh?o-|nS;4{C-P zm*)9sG`oU~SCK>B{ISP|Lur#98KSByk%R3e%VU%&rbH1##aKD3OYLG+7O!#}mdpOCI z8Fs!WTau=GP=)v^9h+uVO!Jc|p0Dy62ZQZwu6mNdx+44y_stZ&T1YMUO)dnqc)(>1 zD4gC`hy4Yu1aKw4^Wf!H>?l>*e8|;%{F?1jn9)a1ja7r=9DjO{O4K|JYJ;Glsi4e# zGi3YH9lg-+B@>sB?)rD*UC*U1MIK249JYe55I$Un`fC|(GV{LWx$&1Bws8c7ziLEr z@F*l?1|oQi1+jW^sG}VnPDLFcJ;R8AR(5?ry`l`QvjOvd0R3$ZDYyBh+PPLo!`-Fd zCOG&qxna~Nh!Mit+}IIZIQfhgFydD6Ao^kHJfwpFJ>s2DmzzdHh28^IPF)}i_HYj9 z6El9J$cm?zaKvnJ&>Z^QvZ>n{cKxSo?(2oM9@0RT7yey{o#X|rN}k#`$%3B)L$13<2HNxfq1 zWs96Mt>Eu^Q3F$ox3A@a=vaYK$>Hn2 z!gHNc7{OjA-$n%jC?}-jMES6a!273wR@?)AR2zC%xM|Y|V6T!!edu z(-bp}2OxYLKwCiKbY}B)t}x~07P`r7ZbIA_X5#lbtAVi|SclA4l0$SY9c^w(TFm<* z%)8d%&)TS(Nnz{RLA}HT9?jw1kp8ctxwH0})4o^wFU_SS*EV`xF6O!5KZ1ezV@d5c z$Ld`=_J@a1l;MP}-@;6Yn4gy=K0~)&J*8BRb|Szhdk|Tv^nt0aT!^h~ni2dTT7hhT zxM==M7T3QI|2T($NO-C@K<+|1`Ioa(YG{sdvh9nV#W2Xqp!ycCt2!k$S3=^-hwTHy46)5*qs-eb4)` zEU65LD-UG@J?xXvwJ0dr<4aS1RFsgNJ$=fnO#(@RP8g8~eka}nBBd0JHLd}%EC)wf zD4ER3*@DpI=2X%{dunaeccya*3CBd(6znym}Ap zISYbp7UjaZRGnOa%}{*qSKejRocxmf|Dk;aOSXIo6F&$v>V=X?$DjO@zQ%1?{;Pa^ zS7M!V69Zq(EVt0n$uBdbJD~VIuhRV=+K~ear6LYoxGeo;MXYjJjgCqCa0dEK3BC?g zUPK}OWCf7vQ1F*II-`{Ub88W!wcUAul&@L(>&SyQkmL{59M`!gc~jWIF5@XW58S9c z2QWpR)IB6Il^sxm>t4812=4QgV^ZxMr&>}bif~W=XGLvWQlp=W zCuL%Q#qi>deb1IgE$riFU`sXXi8dWF*%=Q|9g$pP6nYfUp=*IgOcBgkFTSlrjbq>{ z85dYprDQ|;N`H;l;yXg*zc`QzontXm(2aV3Hg$N5h{bMp znYxZ|jeitwWPR7C^X|PXMNG6HrY_BA_ANK=P;Dpeau-n^n|;gG2(_V^G1k;4y0p?g zc~b&T-%r`qa&vkT&xvY9*}nY;Na|H`pII~sFW znKD&RR2L+d-fBQ7A=UEibNu}2L>E301D*Gq+YcOE7TPgoOw@6gR>ci2)_m*6&?`u; zulk)!b6$1lEiQL;W*^KeztR-px7h9?p*hvx(UGgyqqcgXab~Dk$Eozzi(U1GjpZe| zAo#v7Z-6|uf?tB<0dmP1mIA&s^N^A(;vCk9(ZS%;*T0JBcu}sQLe<6qm;8bRCMB@z zeLYEoND^N>srXn9n?%*mOq05w?ZWnJ5_`13;Ec$j5{}C;Wd$0+X;S@O^skB+}%KZUyPxo&;A;r^vvfR5dYXk6n#5%9qUL|KRXLgy<%qlE*@3-y|%VSoql)FR-UvTwLGZ?YfI=EOtA)#&$xoM>TJX^aS1k zzyB7NSphV4d#E^drPBPmCxM{~ad$+gQjlZj{r=EmvGHk{cS6-?YujBm6_Axz4_>+1kQL9ro$D)47UX#e#|ZRULPeMvU- zQc~xuK&5Me-CigBqlcc(LoV+}b^Kdj`GO{$@phx^+1_!XQPMA~vSP@GDt8HEDE`&w z1{EJ?(bKH7o!z(;L%cyv((Lq@;3WgdTSWIqDgFP2Db~O@imP{AsA_Xj8zP80fGOLW zR)laC=L)zEr%cjf^cIusTH2Tf-keJ_GFJrX0Jbn>801A6F@+S>BYGx zX3cI`cXjny$a;1`{3X3f4~Y=bA0=kr#x-LmR(Z!L!M(3;sP54=w4SbP-=l=<$z3O7 zD~iZ2YG2aNFqsTEgCD88T7SSQj1@1f!ygZ`AvfC?umzCa_pZM9J~n|nV}fDr-PL!% zkK_~ON|MGvMZ)*4@(j*n{4^chw@=v+c{Rs#skirew|Gki(x|y$8TSylDRwLH59O=^ z#9qGaN_5e%vtA?O&gG%!og<|(J_xHEp*7vMCnzo1=K%!Zx&yodezS8^a;sF6auKLB z8sxAA)`o#d2W37A+8JeyzIT_qwQ>cp=j~9_s~QTy8DjstpFc{zQ8;3*a=iWEdF1#Af=Z8HWT-8xS~+$d&E(f3kd2NSh?FQnI8@se*uEigqcerc7IjH8A`z7?Mh|9UIVN_4 zUw`grlvnoiarO|0q|2*x^MBWRqMQ|@7VwrrEO-lT0nA}X&~*cs;o>B`!}MZkmM;L~ zb(FSlPKIKziSi3khC3rTu+i54A%r~tQD4W?*r3Ns7-bvPBeTJVHC$+NWM=B5hT@{k zG@Ch(x%pQYW&J&UUjusx&ecs+aq7v+r5|PllM{i0*ldkJ!0sqiR$6nym5A!cxLt-I z_V+qDGUYdpP@JlQ9ve3f1Jf z)SNL8Z7EXi;8u)SoSFA7RP((?=4y6{>NjT7kL=QF8eW_Pik6e3e+qhYq^(=5;n%&q zLZ}6IU9y@y9efN`)wvk2%9}xfnqTxqYS%ButvoSKbNzqX#@heYb-0shbn!4vn#J$9 z<=pNn2UdM0*bPaoWM;?lQ%$ESMP=l`Z&GKINj{(qsH~t$^P7Qo@@ooKUef#};_^lX z`4FOR9iLZ(Dxoe@j%^W=?fd(ML0w(x_MKUA!CJ>@H_a|w`HEM^E$#696!y->Mnzl7 z<8v;(sIGcz?-EsVR*{+e)?D&9lg`(#(6~4*SB4QbHdcHm1AVsZ$yIDoO#R`em+4mIEtHvNRwgX@liTwir15 zrtm8>pgaz1IF(&>@g-#s4OXNVWq2(t_URB#XRrjei`m`}pB5$p34QY2Z zQC64d4tJai?>5Qo%S>W-rVRQ9g&=27;oYP%tgNL=P(<1^qjM%-b7i4X!m&MxGKiQ^ z742$9^6x5(NK2>%Le>Z*CR{8K20?rbm=%!CW$X-0{q68>4n~^nc78xm6CH&vOR-$& zhvw+G{+&u_Hf#ja7%__oK$Q}J0W0{MTCB?2{YH~>O`KJTDdDXl+Ko)f2s>Bnb;jC6 zna10>xkwCHrra7|Cw1^W4=b}&QhcfxQITp?^4M)7$ChrL>w)+UP6$t&XwS1>#DadR zC}M+PPL}mdw4ZFgCHHW-L|XaPNm~E=_Zl8MF_;2|_P4ZuYE={_MwR(y?~k zr7eKM1Q*uqeAsTMEgrW!IWAT8v-iF) zeK)BF;y(~JSC0cPyg+!hI>QVZs`>xHd5F&Hg$SK4f1HM zGYI?eJ33dd%fe^*yHN1EQt>>-Qn}=Z_mzY`IUtQsk(YCNoN#y3U^1V+O6fw+TJmn^ z`WT9NwY$K$m&=5No~$h6bX%)laLkb(dMnmk`Fx1&;q*@cIii}nM!nEqRXw^jZcWl- z>fT7HG+$d}HQ0SrMn8eY&ej@lPuVu|2AXT-%P!H76=Ha1=-RuFh~)R8R_Wx_vRvJj z`+{;VxM0GYun=2VX8Oi-h|N;d(zV+_LHp~{2yNo#{x=@o+ADRrzlBMVAU;{(nOIr? zuqzV?;1BtpkF**z3XK0o+ZxLzWwbNUJl<4g_*vSjEJb4XX>I`f@RQuh;U(*o>^XrO zgyZbr0iV|K`=%W#u`L`Y=zY(f5Z&IDOPL#8B7#TUqE{ZLF zGdFxj&LcK^D^%5L11uEXmwy~IlxJ`7uEcbCkkzxdY^7bDn@G5+&T~eDo69+l{n&Y$ z8w(G)v3OwU>B7hU>(8c%x>>BqS>^e=A!SjJs%M?+W-mDjbiVhU_q# zpT%nvBCLi}h-vIohzSf_dymHr@qp0GJqJ_`bmvV(&OANr)eI%!#iovT6y=~+BH>{+ zO6b(i)H|Mr_s@EnQ9Ae(X+T#&5rl+Kc`8wr-tJDe*_4vkE|++Z<;M!f(jV%XOj-4l zI%ZK$B98Tzj`+>eO|4(w>-riyzU#A=y$)+9Af}+HMQ7k49cmh5bqJ=W9&Wbc?B`~s zpUl(4ru>7vcfCOula59sRZ}PYTa;?w7}a4zZ%GDKZy!?iR$f;ApYm{ALPj&4X3U#c zunZ%aHHLvTf-|}GVDQ&(W14m_>cTwC(RX)U<|-2TN-2JnF-^&k1%&^oy}DAhiOTfQ zeQGRf25nxt2C$Zarq+e`Y8|rrI^NBD`@eSP??N3gI+&6D*5J`eu5q<;xyi}kj*mVC z?(i)IwFAXO-VL`P$%;!j|5J8!lIGah@z{QwmWxN$CG2L z{B2NvixA1>vjNzHQtS2o4Y(1AX6?{prIqM3Uv4|5aVeJs}hSAtf#UM*wprzCmf)1M5%GRr}4~dBK$*f0Kb~?8j8PNhg$@VD^lS&Owg@ z*a5zS0IDhE6^MM?)1{pdM9oba9dmH4=Y~EPf#H0lta~+Z*GG}}7?@wkzG`ak%ekqF z@#3B9W*MI_7x{&pw2O3T^PgmH5Y7H?436dMI1$->7gYi4PT+eQ&DNaG%f-7o8P}#x zOEFuqq0_zxvh^Oz_%%}ElBcni#%*;1&JR2$J8BJ=xqiYZ|oZ5Oloai|FNIu9wXHiCes1tVV7 zioIS|_c|D22C$Qu1mNP*;B?)4EGEPykaz{-!^)>O%~M#nH{LyHz@lt|E=ooq*RV6j zzx8B$dkt80Z^PL4ylaCMsWTn#KGCu7RykIrZVq~bi!`okIna67ft{fd(!|7CVPWN{ z&>$EPZ1xr|++d7FjGd3}_w(|q+Ko70t7VlA*9pv;D(f#*rO*A<_DZ1%Yh>ue!wr1~ zj~JPb+r&;EeA2ZohnF<*`&Cz$Z}wkJFRDghJHM}64A3KQ@(Y&#I@_?43aoH=!i}+A z#XB$>!05#RBp-3UR5lYiFA9JyWQz|h>bYPO48`R3F_ zmAvz)EUm~8w^sKex5r{a&x@5rQQ`D)uHHCtSM5)6+mpavmoK;pirMD}7o3sd~SuO|}A6VQjq)vZ} z_dC&xpa!n;3Mm-U_w`4)YuoVSM466Z&%O-^J-7ZLn--M+J$)s4i}z!|ke_j6P)0jk z>M%mSO*da-s8>z$=+ZZIxwQkt#YrZ>!l|W}gh>C0whJ~rO8j9e#~Os zAbpbr#)Oy(hcyOYg`%pkXPr95oOHk%4x(%hsdKGACY2vyY~BbXPZQzJlTuOGaIRG) ztFD>m9hwq!TO>Gz#J^wpXu|cF^(krx>BBcEnq%>Pb30qwKRhvtZxsETyv*l9!`)9m z;s?Qo2RMJ%6t8GpEP09n4`@t(Z@p!qW~v_5L`Lvz<*Aa# z!5hO1sYGjNlL%?BMVHD|VAFZGIt~+W%!|`f{FEwwF4YS)2mRRh-r@DL?QCff&^^?FTx*{sa8eH|NMh#9?V% z*;?Lat?ng5Jw(GW<8&hymcS%xrFtW!Sbe!KJ(-pc27T0@go@Ge!eNb`4^B0kJBu#g zym)BB)q{6n5?XP|rd0l|*M?A^4}7=R$|+m+EbPhd#2H2kp>7=_d}5>cRoN2#CHgK5 zc-ud?S4J|%NvQzmMlB+|9R+ckMfs>9c)uigI?nY}8Cff6UEY?iAJFZoe?0%bnL=U9 z_&XTFs6Z0@MLTl|5^&m?G+~%j+~;-?C$24O+*fPYl7DJR`!;6fDAT0!;hveMwI`{6 ziH3SuoXp+O9^!bO%Hpsh0E?dEHXF0-s1xo7C{9{2Gj0FCVR_NQuS5~9_om`tF97!G zlmK5RSQPIdrmu7lhpoB3jRd09L!-_bEylvtH5?;65T@>b4Om6^TfQ$=+IVPoO!)7H zmSZKn7@}t?Hp%MUekNJlWi>zQ4f1@~^MIw1A-I`t4eqFC!) z3ASMw>;V=8{RyQ(ve``r7kx2-{fU~}AR=1id5>%235N@)yo4)#2k%>+4fljXmv~W( z8f5A}xW#k88Py{eoBuC%XIJ{=Kf`e#HvSDKZ?3z~!?j#=3Z!*)Ogc^S(pcBh@iSsf z!@O+&!BGc|Hv8YfQu()w%2LRf?KLXxC>hhZ@VM@hqbJ&egw0Z#v>5L_ToS^tY@jft ztDs>Ora@qAgl(&okcjQUso}6|*X4aD-zcU+%N$*49o|NN%w2~;PX+?Ai!v?FkI$l~ zV6#)qTnGiky$SZ$B=k2Yy={QGu)@|1=LD)y1-$MD`X~g z{Ed3UlryR(XEhv{ZSk59`T1@H9fS6@^~y(fXTXN_4zz1IwGIulTF1K`l1O`aiVq6~ z@swKzUy{4FI{r4Q#n~hoPafOpG>vekavp#~0RF!3o_hMwYLHLziP|iil1BUL!>o}0 zO`N`P$}biwerzSuuq;iI+Ud}=eM%x=`(VlQK&B`{ z6bcL6)BLpOLF>z4H4ivVKI?|b_Jr8HNalS&f%8U+dBE|7Qu`$%9xmBB7B~-L$x#mi zL56KZ;O0*ZD@%}*pLMq^cZR>I6b-T!wshxPhPWC&MRQO~rG>gLf~RRAr&QD$Md%J7 zNXG)dt`(0=&Vy5%r=6CvBRYn}tG4-WTz{d|zrBVgmgc*oXmXIwm8e9!((ufiC1f|U z8;mRSG<9UxVjh7Roz95F-4RtlrnX9ib;2+S?A?r=kJ}DM(1<@>}nOq&%rHtQ~2mCZx)StRPD2 z^gyRdX@EKYygYLf`%(jIolbvRxATo;)IWxOyF2SjFj=%|uQSLCEs3{RsRO{eeeqc+O?pAWzW|iF`M$!r zUjf|o8W75`S=^mzl;25~8VvH}`&x2jQnu}hO0*{a@Qc1GR9!pWG}M}*-JAz{2R;3t zDDsrOeP&hcJP?u7h)#uQaVO&?O9%m4VweB4dsaUixau#mVHM-Rc@wO;`>zivPN`ZD zRWKDyRF%a|?s_R0#x5fSGE09{^t$TO@qA1}F=g}Bv~{pf?G zu3@eQgKBJHjaQo<5GVj)g7ouocw9ZxUpd3mzphsoM-=(KXkS)xef3WY1)n*?cZ3gi z7Sx{y&DtjY1B5*iV*=pJmr#Ruv>YG&Y21FBx~M zbzE0}>lq;UzP{nhcik_;U0V&I4S#K~NoWxK!8kMkjqpjI&HjiL{*W*ilCvUYW~)|a z`kZr}dPROVxHIi)Mg7$uSJUXlPMz$l4QP|CUoV9ZAp^xo&so>?r_{IKlAQkHaX{!f>@WDh_uPsSCO?pT^rsM4ayUZ z=gu{7wY;Kx+{DJutmW)~o+xJhSb0pS|IO?E##hKa>_~WPLhB52oD*l*p{0??5&0Xh zMyMBRc8OZ=O%0Wh!FSk1FlmG8hwYr@fnUSh%q zNQLiKPH7UT5GUo-a#&%LjTa9m)n6=OdRw~8lz*048{Os228=Za+OgY`Q!j5%OC9J*=BzWx?jC;Gu8k_c3As;+(c zTQyB-$pICOa%e~*WENxvDt~wHmg~&cT!}6MuCmdu9<4PcaLRemkeAD7TdLP3_JppA zVKaQ>mPbRcjC*ZAptc{*CM3ozK2sW|wa?aY;?sTpz1_hs+R)BHMJzv_Ctk9Wj!647 zWqr*AK%Edu?U$b7*Q>pZZuj|W`4AUL1-{d@d8wu7k&n4lffmU5x_N+YR4|0G_aKt@flUw?;O<2XULsZ%545h~$) zSRMB623YuVNv^R(2gZVhdh<2%#%FtldDSZ|sQPyzn#8~p)(?|ShU5^rr~HI%^<=OM zHz@MVg<`JA68aOY%wbWzyF)jlf0=a`gT)+9t66*iqK_M^OODGFGEex$gu{`OkZ03f zY|{lAm<_aWpu6sDs26XOLi?_#$@dbvosXT4_yis$VO-Q}T0`b_viGZV?3f*J!$H3x-~R&+BQg!Jw% z`2L#5UwHj+z}lJNiye}@TAd}ErT3ktFgFadwTAr*6KPM4I)4?;PP$OG4h1`4fjLCk zf7rOE1GIQb5MBYXT#N8|&Wk+Jx+HWNBl;r86NmHl0QqF>`pH9cb_uSiMvUnk*YR0z zUmJE{`o2ot3o1@)YAS^Os>x}z$OHZ|7^FSY8I21S%ZeK0<|Y!}6&^Do+f>VD8|JkH z4V4ol3n`sUD}f4LB_%70HK?0!QT^_BxIUivbhVjdLRYE|23{_IE6!v8VrqLazHcQnn<@o#Kp?D zLvM8=-3s?|A6lRsV_3z#qS1#%C`^|6Ef}I#bGhtjY7!+xhW5v1CGW;Ud{DQ8HtL?f z7q>R%e2Y}8an{rgb~8r5p~hS1hp@c9Br8w^KjR_naCA}9Edo3Ob`^!3PY1uZRf;w5hH3Cb z=>BL3IO^CoGZtd&aN|jvZmY1!%|9WiIQqea&zD>yfpvk_&yv$PUEL_m9;a{)Z_XSX zMUL}jLOg@^>$E4A!L|hL2D_vjI-{wq8(h7X87Z6*(`SJ)?_qW)cY{5H!N@TToKO8{ z*bSf41P0=_w2AYUJF2x3$|(h?xsmFx4(1jiW5qBj`fP5)Ks8LG!+RO<_OmVS^v0&A zLpsrVPg1t-1Bl|YrUG1Y4Dfql;*KqxkTAyrMf%gLPpzj7L<->BbRpy51R zn~PGAK#iMLiBzCOg-I`E^DQO1t6-rJ3ou`=z|OB)H9MHHg>AhUy_wYWp(hnDB{d~K z%R<7?I*g$l2Y~<24DSkNgB-F2{pI7|9-z?dSUn`<0~k^&(6XxGNEY__Rwr^9aDH*s zAc}P+-#a-M`{oUxym*ZUu8j%0We>DJ*4XqY4Ey_YPZ_*1vi#eJ3mv=8{budwX8&{R-FJosnYcC!Y-EWqMef;sF8^S&EG(OC4l|C^zuK7 z!%Rqg==1MMv>p#xma_cQrF)i%sud#FW*gjRXzB;+>(Zto(j`ZIsKXrfn&9y8%Jz}K z80X7HWr5wAL%F1fI;ED{TCoTgrVT+JM06uF*lq8ju-U+( zaQ?f0yiT#+YioC$W?hU?K66b8Yml0zpoN8Y{BK$#rD?csX%_iv-wumhKiJAGOO(+S^yW>2&Di`NUfbxC(M6BpPxU5l79_0EV zSarj!+h9(MF8#hIauupXtFq#`s!hHnEC0Rsn}<6%=*qWd&lsELfMi<~@HE$2Dq{R#R^25}!p5B_ra64ZQrX^ZHZw0Z_moW-AhufQTH2K& z!x}q6J(VN@f6+6aRAxom(D%mb_Y$fO-hiI)r$EW}Y>iw%h7d3mk2A8@lZZ_8Ua<~(&9JI%J zxGb1d64V)P2sy3Um^WUL;NYuMHCRRn*SR4~{=g$*3tCj~T*2sR59{cc5}EQNaELLb zMeUSJMX+sNGn}We8N|3*;vY4dA6^c89WxP#!1F-X9uDO=R@W_$kuNnm8PspG=RRmBWcaak&4yz%&C(V)D|hR`7i0> z**O=*;3#tKjp5w`XhSnAmPV$P{hazue~`wEUTn>dg=s&K9OD_94q1V&+rhR9$Y>)y z(NRH&mCDB^vr7+y3tx|b0Tq<647j6`n~3J6AKyk6wU{?K-R5s+6OBNNb2Jhg?6=;G z)?Eq@Z?d5Eqovbst9!ht??iYChIcOpL+m}*O9k}S{8mNEV3^#9)eXjLsIHo+^=6{u z5Xxi`t(X7FVnC!dgBx|-vPL1zS;Vt@6hU2l_pky}D6aCVeKow|YuH}-xsft&guXwWnRbB};^g z!Aml&Mr`kn@U+H(mA`_2c#t!zsm;_9GlCybYdiCFZ8; zSCyL~YL~`$=XY~Rxb{lWeIq2&8cZH-N1k7`H*VoZEM?pIfgyqe#r_La70o<}aZFt! z6*cJgw5PFi9-CMDjqp^@!Fw}r;ZqjKHY8|SQov~S5!-#|@FI2$>+29Tp$2pW%$l_= zI_O)ayf+Cb=inL&+J#=&lCZ3OqU zDT|T2aVV@c*T0MctP|k(qGP1kJD~^AiT~hmyHCGw9J>jKv>EV~ym~jpupO(S z5pVbLF#A1*(8UMoG)W)hD^0G^4?&y2s?p_AXJkh5{av8zxdO}8Q>k+W+5{D)8#%sa zb;JOheIg7w9))@t*hwMX)CaVX>vB5Gd9LTvhrdzfa=VKq@g|}D62^lrsEzuElZu8_ z!Ln~L^RbvcUh0%g@N$CXCE-bPS9Yo49zoWA^Y6&;wbsY5WL{jHV5VySmBoDr5bwb{ zwAHO?$H8aTHt0a4HtkBav*|9@N48{3KS|@?2G=J8-5buy&-UInf=`W*P7dG$xy65Q zSVj(gBC|$@yZ%Z0cuD`%vBemP?{oZ%Z8I&RAithgLuJ9ljl5E^H z2%;r^N+v6O(9LE}o%OB!MbYeV`HI~u(Kn^76NcdUAY?nt*QHKCS}2;vooO^PFz8+4 zxZ(54Q>4CBW^gLs8$)=AX)pg#tI`Le$NBwg?gSpw)^+i7;tvCY`qN;3knaM)yK;mB z=v;4|!Zc>rzRSt4WNKBd63$WQ&0o|q#b8+w_a?fSK z>|Paz-K)Aj^4D7HeY#dSv@|P*a8=>S+q=3w(sSJ&%w2wDmB$b_y&sp_SacP?_PKmq zKN9Qxd`T$4;7n;%tMN8*11((5GeHh2AVtA^ho|wH`Lihwl@&?e>a<~`@DxbLtrwCC z2V5VIeU85?*4`HvboRhtWLPy+OQ#ZA;J=F-i#Dmdk+e=p%tE1+-n%&kjNKl6yiibb zApUSHTMjw4RnAy&Hdiu@$5WqG6nTr zq7=wSj9J<>=(hG^T{rHUv~x(-#>Oyp9G-qq2C2*0s`hB}!_h1X=`8jtfUiS^fFAUG zGT4!AIGc)dDT^zO(H?-(dlG>9W3rR$#UfR-s`n&8c5Zt_7dG;kELG(jzdfJIaRAk$^`oy#1GcU6MCa#$alw>--F1vuN{&Pb4YL|M zeE4ryVL~)Qq`M@wC$`iIww@>@e{!^#Em}#P--)AGuAAC<%3`Ch*{hZ7%QF`b=X_b$ zls-SWyA~-)^!;d`arC&TP37xfc$HLd)F=mEs zt=*X}rlq{<-!nd}EE>%S-E{=SMlH7V8qRC1K5` ziVf3`6V$&_ABYU(>)N_ybxFeGD&EVmrKC1WDPpFGG}%<`%ladBj5X!S3qpnEtNt{H zW0pn-rSN53PCS`t+CMaEnmzN#u(2oq%)T7NQJwV|_8Jz}LHc-Gp}>RUF5+YoV<)=~TZx z8*GO{@aNSqGNL-&Na#WL-F~OR!%Kwui@6R7TBxoFmTty9on^~V%45^4%lCbevXsYv z7(4i0>$grUqk>$@iQ}+>a6ZaICBmT<*F0bot7xO(Ydjb2rF81IOX`&1l-1kcM_seB zwH5pDUVRY+CBwTTfzCzk0HUQHb2>yl4hGT=KO zeg^+^0ex8}A?%ZrIQ5};0C++_G2b?xm%H850nXoVUoGoJg5ihg!6dvw!9IUC?ylkp zdG^i3P{1fc4}{qfZ>!&$uF#82-x>qmoZ=54)%bh%y`Vo^oiorTH>YPUe77~w&cnKX z@ylWm0FG0q6xzMi>C^1CZ?^Gh*(7$D=IBkWB3KNYkCkpHLkf_uW z1_Y$dV^iGxvm9HR)K$Ds4RDK0(dlg$Pu(+8>?X)YrTyWTJaV;j63A8fYX@HHxX4Y6q672>f_0$?U^$aDcDUQAls1-V;$K8|q=_CC-0i9QN{u&gC@_h8NVs zuH$MavFuT>o075m(r^gBp5uT76|0G*PZouZ+nk&bE>ufE-ydQdL!FD@n3I$A?w&ZoIsdbbjL8{k>PZrwy`O^@lsGHIcr~)`!aQb-U`F_ z^Oz_%6@H01Qj+x5J^c8X$X@V43$1jzS|{M!<0AXTzAMP?L=HGu5zq|NzcF{zH|ptz zS=WWR*jp+2x@#=P&`TJ4q{sUr2(|ElQnMVqfhUJg3BQuDi~_3vmnzZ&R!e;l6NX4m zN;rv_PP+x;FI%Sm$@8$u+E=J@OeJ!KD;hQbwAGbmj)Hgmu1%J>GYQ}x7VRjWUKBNh za2tTKQfn^>x}Hu?&lHkKESs4@57xSd9vZ63jZzw2Cea$71-`W}&p_HKAd?(CyRZi& z<0mFZtOc1psAtMVCOEzQl@h*9O)?xZ|U*A>f~5o8B}#31v- zR1QPN-Jr$1paZt3#M6KGY>jJ~4H}b<<`H@up9J$fm^&QPr=E<<$Bs^zrjp3v=ONd% z1{LU40@Qg7W|~YE-*r|WXm%cL!ZZa$aV1({pNMk;qyGHZ=Rv1kzoQxyJF|98G#9Ov z1AK)WSO4NrD38!a^-^3bORwXA_{q;z@{Dma$#)|d)src7+AXwV+F@k|vUpK@oZF-P z{)n)OdoblKFI@Lt9;8;Qtk!x|(ir%%A)>aWc2jxlSG4zj7g%&uPwFU-zkB;vP)pFC z*ekPtE@R&X?Cu)4uJk5K~o`=-+9=c0R(8fz0TY7nkJ>G&#q3^OPvHFH~x%@v4?-r z|GFFK=OqxE+@vL)E7r46tNCOrz6h=giR4x&w+QsLC!XpkxhNE#M^Yi%$3HU@Fm`xcb18@+J86%p-MxpK zRt$zatrqnp6e6b)37_6Sn+vhG?22V5RrK(bM%XQEM?T5e4NE2$b({zCF0&nI4-Y6b z)7WUBx^@Ofs(JA9O!zhDDnEXZEaMAys&?2<%C6c{VZ%Yzj`=BuZK3IOYrHK*2KNVN zMsu4_=J>9qMD##-Ho+m5udZuB#Y8*oDeN{@T#>g?-F|)9%-988vK*3|EH11PXsu9L z9kwIISN;99^5B;Jh9v(3BjL|r1S({|NL*p6Ea_&Hhn4FTcsKaN++zyl?=RC#E=3tb z_G>E&X3sy?+l;4#YJ{5SlSf1gHmsxZ3SQ(xpV8_}YUF>)s1Jyre|W(f$zaa zBew^E_ z+z#(~JYx52poPV@)_+z%2oBuN@IU1Na=ZfHtV>o(hP%_Q*7iOs{^@ly=NCA6d8Qm( zP?Z*qfS!V|aythd!HdKbmCix^fi)F^CfD=lUlq`!QgdiNMn)3anj?MY7dll93NkI7 z-9NqnVG`5$NI_~5C)34P2l|1*;%r^5ZjBvXbKSP5Nn$v6)~UG?cGV9AWQvoDFS#Y zZdX5TVhm8Ou|GZMW%6$rTP7mBSmKZ+s?)wyGSszlecTy-oQlV4S&SMZ$7mp^+A70t=d85648@AiC*UP2P9`GV6>dAQW!*PSS=%w`rgUjz6NAtG zDy0UjSE|`Q&|M#Db-dJ+w^B!_{VR@Ng|BD>lFKHpBDvNj60`Z^gFbwTV?X@Yp=*IcOPfed;6%`oxb*x(=Zizkt3HcrsLtr(yIs|7KDelK7eE#M91B=9 zdZxh4b<=__(qQ!seR~-vN0#b7OKLi4-`q;yvD2-jYiNY zK1Z47Q5#M*401-D=u&^^z?8Y zvo^X>?3?DF=#E4;(RMd(=L$kc-E%UX)5+kLmFRI54$+4bcewO z@2VNOqSZkTtN7wbE5`Msxd(3f_6UQnwUCX%(Ab@qqrVBN>mTLdxY4@ zovN`I3k^Q*8vat?sp#wcDq|hr&V~CleY<-)$%~wJc$8e9rvmXm?NEW|O`a)cgt-yo zY1)a61q(PqQ36g1bf*DR0S`|MOyi%WSbr>>{fPtH<#i4(y*>^#!$+HTfNsm{mAoa` z<_>#3j+jX?-`XkBwwmBRune9R$wBWZ(w;D??E_RA*KVq4hVlYq)^+Wy|5o7O>6PpV z^jaSAyPo9>iWL|}pFU?nH%P`E%BCHvq;2g>utk3P*1(ICgcuG zROS%=1$YixEdJc1AKfsJ_0Is@oDPe18yKt^tsVUo=gpEoPpm&VLC(*@Jl7A`=1iw)d^?MFxKk?@vdqF+UQ=e{bLiZQp4XyqxqF@BEdgoQn z&ue;GJv6N~mqIo^3%MMb!kgPP3Qi%#`pY+AN-=8J9I8@#f!6-?MT-vJ01J!9c$Qdi zGW;AKLicx&yms98;-?|Z%~di{H!+ zQ&;qR*Bt*7h(%w{b<5%;%!F9Ihm^xs^3x@l-RuEv@EdJWzKO%x6=!V;Wrxdn=s^uz zuDDXY9^z0L0J2a#EeCph&i@Ntbo0cB>^GjZhga%Cc)}t2#@#A}XjoiA`bj&9@NfeP zw1b{9Z6Rg!9bu)XjzfD#5L z3B$UWZn^hDYz+-e9oKz*ek`u7B34|ceX{+7Rudu)FZm_ed2&8wGMy34&!-cj2Sf-A zC`>A5Q_Z(i8C)(*uN@bVY6Z%yx|o4Gq+g=o9x` zCUKT}Y9!?ppXYjQkNJ*|qcImnz&88EE&z{xleSgojwt3-nc(l~bGrH9RB^4T+aqBQ zoXjq1tuIP3EE7!h8i(3K@JBL$s!z(6fxK-Gx4>0)Yp#Ltr4$ZgEof2E{udo8FndCF z*M+dvhJg$o@5j()%gIJzN6rd&Erj1ZERBM9?4`KU5+&#uC{1JJ(de@0GtOd0fHSV5 zGZWA=uwX>bJ8NCuye+{a0T(C8QEqHuB98CEc=L*8oWY=!#~MbC8^hiTH!w`p;Sh9C zcOLX`j=SDt6c_{S{UNAV&~>?A$9Snm)=uE3%+GGk`#H6udg`@u#6hq+i-(0}4;BZf zov+r{5;v{sIBUmIKVEJ%*ARaPQf%`+lGVa?mF^0}I<ga&NA*aU2og~uvq%(D5OgRIUzSPE}Qetn23AgX$$QwHq6LcNr$>m_Iq zC4dn75?snLY7*V~o%CIv*ieWCGWqTiAU21=F#F0L&(|WnSm)TMb=9>|ijkOZFc*uo zibWjGt=?)D!>0W>$zCz1!?ohjgE3SK{RK!3y9>pt7k|9vQI
E3iN*4zk*Lq|FIHVk`qS#Wu{5#f9xvAXz3e=#Q_(~I)nMk?*&=ahMek65_Jeg+vlGYKCQGd~W(-QL zu6oJCcBCpq=e6>QFK5#q3wkDZ$~&141p-AJuB9BZ$qfLtvZkfAUYc@`dbYJ_l1wU- zN#Bkt($WA648~c#VA|A>n3bETBxSwV^G&%;m)0_nSexkC^CQkqF@B)kFt=B zN3Cfr+s%rPPy{oZ@~Hd8Jt1%^^D;5KobRj;#;91)^t&box}wCWG17mlpS4$u+A?CzfIr<}55aZidPDTNju{!L_j_=U0 z(vM!0Pa|DJ+aDv4UF!bit)>p|!r|SG3oj{9h$^9iX?4S!lSX^LeAXSA%kWg044G_& zSn8EOq%Q^xWd}l>{K=z5=GTXUvTfV9ltkEc$5cONV^8=zYSi()#8kOF;(QVkEO4g= z5XKccslqDWfZb^iB0eD9wvB<2?ZQo8A0;OtLgeyThC|vkdnV&@3v3rq;#A6_*csEw zYNK$g-#(z18=lO<;>d`Ag&iN81i=Y=@@kmn@< zuwTT}vbRqd-Z9qj;@2XD99!k|JnYgEGSItH$#d|+5H2(S^2P1P=3L%Ic7ti&!E%Rt zqn%iCx~`NgbA4_P$22Jq#E>{!pKs}>S02)z3?PG$Y^2kwPKO4F<^l$dO1xyt@@ZGz zJh2o{P@XN@Fgv?=lEiq=Drp~FSiio1U$M+_q69-2KJWDb@H#8B24(fDtGLIeIdi(n zq}&N4U;ksJ(r#9Ah9&h8Zd!&|}0JBLMdxujb0we&3-zxrB_ z<|oOwsgqoNh!to`xtsW=z3Ebsk5j@P`{IaPwgjTZAkIrPH7KSEU1*$KajluvZ)r84>b;UZ?Jk=sJ|`FNd1y=3kjMx6m14uhO%F7Z?b zJnZV`sOu#TQ43n=8JM!ClBTGUOqcfO(nTUM!N{y4cxW|@%nB(FLQNQK*PkrqK+6}3 z0FuV|%dyHmWjrI@A{~5aPoCuv2K<2js&>rVYcOmeNFG7(+11tGQhd_|*7%fGc%%ff zSeMwhWcWpj)|o-3$p~e^pORfl?FGBCPZ|X$ZqRPoUd!ZfZF)|0ax~NA22pr-s+AXs zdgHz?6gLhLJ5Xg-zSc#C0aMEpT(OmK@F+k|ljrlE1&ECDm9?|i>^p}_djPg!G4JM? zW)9J?lb6V*M*3>Z65fw=gYxB?7#*$2T@gi6?teU>{ym6DBWt;GiU1E=l~ZBTj#-n|Ud8uQBJXvr)66X|n_r ztXB6PXlSsvZE|h~Q+#&IXftG1j<0%74Jvz}VluS69sAZC!Z07=y><-d z8?NS1 z5nb?ypt5&jdJQ1)d71Rl9f$=n8dcwDfpL$}lJIc+|ZMx7Kfd%^349 z6F!D`pJ7d3O?HC!!~E^+d>KgU^$g{BLIJ^Ulyw1@{F}=!biSQ^RlS$OGc>$H*k9179D@K@tasWVVmv|0e9*(fBPFF!6$ z(n9CrFMdp1wSMo-wHUBjwsyv7`n`~<{pM`XP`vUrGHZ38luyHt$U9QG1#$`Hho{Aeqm`kr=4xr%U_l{eTU~QzM(8J+s&=q zu9)}h$)u7<$Q)!x2a1D6C+!@#4f(k82Zs7SIo5UEZf#Rgn^@6o?X@Sno$lZ_mjJ~% zk&K8`ufs;Drc)uil@3CX2UXNg@@W=)d|LkCkNA!TPfh%{{IS*l065Lvm9?&$q*z;+ zpp#O(zjI*ITplr6%4AZ)Nlwww74fDX5?XRhMDNvipMNL3&-pzJHhz9jH8g5o-qk$iXPLD`h);=)FMl3hB2=y)g)G0{7ce@t^%*8e<}X}=P0ee=N^2UUqn zjkNlWs@%gQ7Kq3ofC&8{%;>zHM&`r~lmNX!CSo+!circIlRka1{HWAC)8RC?1xTs<>xyOh%M?eMx8*O+@uu7UYu`)c&&+)R zBe$^gPM#ckrZwaKk`RZAKt}zyY92ohW}Fev8kg*F!JY$f-I(fDznXf?5@`Cr=cb!B zg(49x#9FE&`ekQQAhN<~M{{T4q zBfQ$hobhX(XSw)fx>iP3SS!46)S9{Ly(&p;%gHeTQEI{tQ*!wsJg5HvIgxSsEurb& zLHxD4o^utXHuGw*Sjx6fC_ot7#^aL4KF>B^h=RkY&3}h`x$>3n9s#X+qUX;ZVY>5M zO>=j7eQj>{k*Y{r>ub!-DBQ7A$S7v)H_LcHYQ48+-a-7@z5Kb+FElSLUfyWh)z+Tl0W9uKB_gXia^<75hZ!&4{n@OeAEsDan z%A?Z=rHPhDdbEa$wA(Czq+LAn%HB&@nP!*Om7ANeP^u5|qK~qpwoL_4$_K^rC%r%0 z#RyqvAejwWyMfSRsWj6wP!qTvJ6HVs;;Aj|!zobI;&=Z5Z^Hsu^s*9q0Bb|zzAE|` z$PXfZO8K#)3*7(7~NTuB8DS15@1n43eP}K&YcZ^49SMuF_5+I zrI1;KrJ27Er*Ee$;-)+dXU&@O`EJdwWGW{hq)0z$yHcNiLnP=Tw|FL#1KiHjUO6+f zG_1r_@;)T*lw!hWY_rLqfKX>~aRRjEC%Wd!FyRgar)7PXlr{ZF>dYx+Vnmlr7iVhx zF>UzfB*zhQv6>HDGAyslprr=gJ*krbhF5G4&NeHm>32}DsWCqE%w1e=E!uf-mOt3zs2pIbRNJxOa5_=IOhDo(9y+JVZVA*jl>K`Pkz~EAE~21 z((z9;w;gLyj2%*qte-d4pYx9LbMp1pKtu(rs>u;b~0OwiES0%oTqP6 zQ_0Of;q+#&CTM}Xn+!6Z!RDI3<}LoJeyeUfc5}%&3;{BmeF(Zc3_V3D{PZi zf;jH=aLH*T=|IPF!`tPRN5ljfazJM6bxt65sI z5Kx*9v>qNAnT`SuCQO8sKCLLzt&7J~G`mItugrn?4|9VyULAuh82Gm@N%F6j&VyjK za{@0Wq}NT?~+PI&xA&!N@5Gt57gzHjob ziKqF)&DwOfdL`sYmImTlkd6x~h=C>`!*HcXD%UQQ2phCQa3^KHYW%MAZ;_(Y?)>AY zPii$7)vT6R61h@G6dX$wZN(F6SEfc#Bbzv6iMms` zeN&Bln|^>a|f-)6;%Yrr*5ZeRM#r;iQOg<8z}j2^8?FPTD6VV zoux+<^IXLP+?xw_m@Lc{n~~g_9jo6V$cLvEt0L2 zR_NAO2zkjokns*e_{_q=?)m7RpejmLTSj*Y%96JR-P(mR{sE& zo?^J*QYBweRnwe-c?Ri94napZj(2~7&>$NfPihMw;d*tig zE?A<~B@ss=8AO0H0HD&e8`ixBJ{d=d9*N}-%EcaN)3kpxYClr2mEw|nrHQ05M(fNU zPhwb#P**IDHmT*Yv+i#xenqyW=Ubo3wAK>cV1|3cdvKLzia5Ph2@pTtI3Q4(0lsC8 zH!n99TACK}iJ({?(y7>;&vFem%H>L|EEc?gWAKlo11GroKgd2*v+}zB zXMS!y)RsDv&uOFS_8;H7MfR>GW48q&fon>2%#3)ziIH(LWRW~EPJbwWE&R9njc=@4 z$hQ&eb`ZVHGL8b;-XsTzVfLhVBcRxI%P>cdRp!GsLjV!JPSL!Rta(4pH=34@FZhc^ zvHH|{q?ZJzsVkL^G=yv_0Tngxl7=uzwUnh93VT+c`EmI}qkdd@JI+>?mY!tS{Ksbv z#q@V*fl_xPn0kC@q0gp^;Jm9tn%@(09O*;NKm5G>jQpVU2a+`p%{_m}@!a`}8{5TO zNSq~%QA0PRiiujV3)HnudKyzPrDW{db{x_h7<`T7%b7L5FaBR>@m-`&vHfm1r$ySN z@F0rhV<|<4H=zD~x8>%eWp($dP=0$tw96v(Y2DBy^{6$t~toXW+R z%EL(y%)6`0DQ;!4x0HQqDi@4bV0#naEsrL|Fx#iyl0#day7xG%-#_Obe9x)qy43m> ziRJjb#Rj6QCEOmG`lyjsj3j-LeTfx4GVL|-xcZ3Lx3d0o`M*}xJiT|PTlr^D(zMyG zP|tO%vX4ZKmOD^71MN{v&eiP~69hMTMbGC4<_3@Dtq)JrU-U+i9-k$xv&A2$^@zie zW}*F|(~$Q)^90PqTag?wkv8{BJH1%xcgM{30w}J0ndw-~azwJ+t1+bPMR=BC00h^> z=5%HZZN%WI3h#X9qW)rAepTx;3+r3ko4cJV#@tD#nAYappyb}0$c~^t*?p_9-!!5( zySJ9??@Ro{)4cDaeqmkPSzKCOK9#1dX7h}fQmQitmRS{5c{6QA1Eyu^4H6t3OlZXU zynFK^Xth5k`3p?7MtN-`klb-fP&ZBcisP#vyRS0jX-(uWxj!!ap{#koK(g0#V`udl zVN)5J=_6tW)#7&pW7jp1m;#*X7ta3x^OP3S+R32U$^$*Ml##O~8A%cy!R{;HHhD+x zg?GB_C)X#=-dX(Q*1V;qua$3XtaZH%NYce?s71_0BO0CzH=#eWcI%bHDS)nw&H*ER zUSavK`KPXaV#R5u>QP&1`bM0rmU?Z3d?1XsQU_Y(GGsGt$ACfLcAE9?muHgaPa&Y0 zJu9djRb`L5kan+zRmH;EA{9QMuM=MRSxxSi$D7&{`}=0^LDruv9_GM%()cdnX6I`# zRs`~bUxk#BxS{JzR+)E~yw$7uUSX(cmlDA$n$=ivap3B9BYzA8A?enhdc5|G^gK~1=vl(jq@S`k z>Uv>dlxp9ay56y%YZ`8g^=~fe(Ik;QzMWAl%f#_5G5Cl*z^4A#B?}v}iQWA~f6gvC zx8<&as3;P~(P{qxMzLlFnA}{+htPR@2V$oU!$`5RxAE*VrTcZ#wp zr*pFJO}^2@8Ar{R5HEoL05Sgn=Lx?xKPBz%HH~vlgHh3KgFD?@$bcYFX#8ZL1Oxjn z#|*RB+#tsJK2T{Sv#^-z4qp8wRY>IkfSxq)KRmP+k{L~v#e?YSscI3GsCtWc0jdvW zYLBBP8q3f1Eh$z&%0Pxd8C;GaDe1_6OjU__s`5zg;ebiNdI(Q&O-Kjs$Alhf2Du_U ztND$uX%a~Vh37bxNfF9DNRJ=#Pj8kyAxV8V=1((CoV{Fm#EiX{Vs1)owemGKqjf>bqk~Km|@)jd= zP!^wdPAyVjp-3*Sual~XS*UjasOkaeepsEFvK^nNKbwANi^=xil0I+0DIK+&8Krqp zvIREk8JSmd1xfkl;(t?tf*fL0&$KIFDrpjHU!VT~mG<_Ng%>7k%~Mdiv{~ek66&!^ zDI{mG>DW^(%4$2Xgh@1Co}ZR}cD3@3xBer24^O*}XO(U3u3mLZPhMKIkThDfidrXO=X58_ul$TGch%Ej_f03*9mcJxW0G-bj;3=pI2SQ^q1k zEvh*8!;e!iEcc>Vzzg(WKWcX#X3=c!e8c8FPRabk29b5A>$fdD7a{G$vrz)70|zBn zB%Uls6I#+|FAz8HU@-{|pIZJ{`A5h%TF02}yyd1zII@}2-p`!VM(7I`Z%jF*0H))P zKuFM}V~B~}@n@I+04V&M<}b?y^UeN)CAF0BYS-5q#ki7btqc;k)uKgH>;v)!qjE-V z@nel{;^oaTl7}WA=1<9=D`)XGn&W77g00f)T4Yu;oqk(47Mh}6FbrRVv4Nvz9-9Hb zL%vs*0wHi`k(0u1{HggL=Bq1xOU(Xz^L4+NnM2$%Xwu$C9Gw|NjMb0<(6vbIOvVud zqnLBfJcAui$`8ohMrf?t&%SPdRp}+d=t3CbjCFTX)oOo{Ry`?(hj-e6smaQNBeeXc z{EWA`ir(wbK5@I#?Iq=HA=3T;qhRQ))j)hWgHyg8yO|ub?hIGY7PpkyZoM84?X!B@ACfuOVzCO{{S%Ad6P`@1Hq_Fw$ZhvufropBap1h z4=y8f&KRcKWB8jq1LuJSf)x08@tFi4i$! zlEe}coSf2|Voub=VvrBZ2%w7Dey?ua;DnTjm8Uq=kd4Qxk|;>+(=ckCgG~!Nj|vKJ zwgt6$RZum(xFzJL5XOWKb-dy zY-{l4;}{U)^J?)ub>#Iu8_9lD(myH(=7zcD!>j5y7uQx^yIz}RwN+3fkyTA(JdG(s z(!Daljv^LZe-cui1o!?`Kaura8%Oeuo}YPX=gmXQZ{`T~Cb;DU&krVO9xjNEi?aX- zYGsnsMSN)sCzYZ6-}wWe+J0Dn%D~ZWbsy4p+C+NXn!Ix(>GSfCD_IzUs=9+v-D_Iq zbHF1D>ao;%tGvECw_lAJf{=bKw+Gma!jrHfpLF@R@;A$RXXTpt(CD{TR|}!8q?+?y za!D@QK&xo>{Hf{4q;NE-@4js(4@;?zS#j5!0@gG?D(l~smcDDW^26z#V>+A~O@+)C zlS>uP6z4zgq$CQBim0a|4_v1-ZXwCVBN(Yo#t#!i zxFj6MvRtke>2s@Ua7UwkZh36cfr{EosT$n~=t47aQa7alrZ&ola$h_bT0O*;HzrR; z?Ug6DcO^qN*_A3tR~{o~9dbahAX_Q(7v~@5Kbo)XW!H5ymfKFZHg>Q@XKNjahPCA^ z9DXT<2glSC^doONh|O){^MfrfwD8>Qn|kBp;(HFa-5a z6C(2W{N!KeCzTC!8T4CdiK9mzhiS%@tpIA$xnw;Ym`GbK@~`E2{Oq>Z{{S>R!RC!O zOw=sH>N>ExfX0g*1!YBvLaLKQL|w~fOfZRyap#-EHA!u!{NvWE<{bjZ&K_OWtgbI^ zZEm$2O%bY>lUdsz-p#+mT5stST6^LAu>#OFV(73PZ}PWV(mbc8era8Z50`a|nJq0O zSp!I26qYQ5aJ2*ve4<`~rV|;;yE|$^vF{&CM|cQDJ4k$AC5%DHko->@|#)n^~KGHlpss1 z%UB-i?Y%&>R*Kc*%{F|y@={h#0ZEp?4=TW;z z(FD{fACIfJo?w0^BiirmYp}FFp0#Gv7lh+!)8`e z3ZLVI#B^QYFtB!@?=ZIa8fvdw)L<3c|hIFL{hbEu?Sv zbOXAd_hfw!QNBU3=zdAkb-BF9r6-dhw$(K@nJ2M=R7q{_!1$=j{{Rak07EJ1xY*%< zvKUN&H+?1LKl#c30L?EjdAip@({3y@`6j)R9TL{&+9P9ZLHSz;UIDAYJ~?o8+%B+g(~}`kkh+0EbXZ>w$F)Wq7Q@LSK&)LcFR}im6%= zwo{PVE=(%6Ntvs%`=6dgo9GYAk3D(w^0&&D+V7PttlL7?Zqmo}g~g;-Gr@L?$a);A zLlM@hQm1c=Bmoc)9M?HE(X zi8NAzr(#V8N>Vb7p7uDQ7#*KJT3$z{MAmmm=R;;@Dua}^E`Qyyf%c*&`^dX}r0~j| zmPKQtYI5p!dQOx3%lnyP`jL!>j$-6`OoZ&gjW#=WJ{Ut8Y&U&1sejH+{%vS_`0~D^ zExwCyYj*~pJ(ZT95VNz?qC5-mD8MA-)?`+v?WG1?84!6m=L87r^LVG{J+8fP=dFBs z_v)w2QeJwu?_$c<&m@tl=Mhb~vhnvDhM}%iBW1n7??fp8e?nEV6d|-0wSJ>=8Igx{JS96P>7@4AJm}~z4 zntplw$?`U{D-%yUclssy-Q*e)LfbS0|S#kmSc67~+)z z`F)dpc?6;0#xsBgj8(|K;pj|018~s-73dL~= z`*6&ib~`d3iZZ;I$k6&%{@zTP$*`BEAkhB?GXx#TNry)1me6^%&xTXgMXFqc^n`K_r~Vw=#f1 zjZXeZ7WYop1dy{bFl{>7Bu8GMk%1z;k3)^1htQsB{NVh~@~7o)nfYJli@1h?uj%b| zreB1BOx7zU8X}4~1r4_r0MPf#hEEJ^9AS<#l2QKvIR&YC!F69P+3UBBX=5Lj?9P)$ zgHTttVN(9Ak*k7Od`NbTjw`lDJZeFnoKPTlye)MNZGfh+Ft7Z&TJQIv%EOQY(LX5s z$>&WM&33Z+GUD@8*6yLYvbM8|IAV5th{|(~;y~P!?E&^pJ}t6vJSM|lScwWRp{_iu z`ThBMp~>bS%n!`%L&~<)bb{9Y@g$z^RA25=6pBH~`c(WrJ7xK0DGQJV#)eE_@Wgzd z7$%{rItMzf>N(wkirkP-U)bxIw{Be`Q&HAwL#$p8oL2Sw{X8h)eTV-5IQ_2vdTM@E z)cl+IS0%;om#-$0-b?$F94lumiShbwvFcfWhhKRm9rzbjjL zbMlw`QR|;A+fFYc(E4OO9N@q$5TEAvL-Ky*W$5F9mrQXZIh2F4w>$;Inr2gmr zXv$oqc8{p*R$7gX{im6AYZ;)qid4LflbjT9??6-xc#Y^cBX0OZ8H*3m2e8yU-E({S zjrlF6XkK#j6|$M-)->Hx_S)$#c+k$)GnG>>?E_vU^vvl-A~qdtNhgG!ug+_m{cies zZ?E;uUQ4;8cbZ8q6thTA#9FIT)$8w?^SiVHwhAKWSC9L>b5)7Q*=LzuE8CKBqYn|` zg)g9gD14*mug+~JU-B2_{5Gi*wYAQ7z7+ zcRdqd&V4RV%e@at{{WnP^ADJ8HH)OYlI@Z^M~YBdFWtqc+(>CVm2NOO_<$Tq>6sb* z0*^MmIpZcnlji$*#+p+=*5zpJRQh&TlM~9>tF^tsJNjhp9EWs23vHN=Q$yDB?6bph z1HF?;%KF7=%^$tRxIG*Xw1eT4d(#y~URkV4mv-``_E!n&Tii!bk}rtv2?RaC23VZvVI_PoTj#_a&Uk* z2JPzFH=QqTePoEqN+UBKu9ztThNU{UT20rtKyn{k$bm%0wl5Imzvi;mn^er{a!l&XqR=ub) z8hI1x6wg%{jpR$y{HOVw`P*gYo1e>%DB0(fs)9l8MSEouHe9TD#6uDw zfm#ZJK2-T+TNLCZl`XwRJP!W=ELADHk-2yv+mBs`fyGkEIWEe6$7~5>^DzusFb`AVTvhL$Pq}#i044SGLO`EiMR87{EZK+3jn_6Eo-DfkS==&@ z$mtk)PF_@?)UHUc`lt!dPxf1EQa*1R+n?SKa((Bkr;^q^I8_bZ#Bl>!Q+n6%&Ca_a zh__pUHu-XE9ed1kxQZr@DBY2yZ-rEXK|AL$pN}Cn?lHy~$9g&+FKPZ>0{BjDH5g=# zi63QGkf{FLboyb8i4)ZsbD4@9pJ>=3&obR1JW7I;JCRQQ<2ymS&8IJ{S=n4iX?Hwv z&ikZpdW@JBXepSFG|uMiBy7_is7~YIp#BuY!g{7sr_1{GsNQMRe!QTqlmw(J;zq@f zZ
A*2JqFRE>4V;T-Hl2CzGr+;s!HW=~n@^CWF(+Sz_!b4_^_mdGE2)#=l{{SJ5 zN!H233*G8E9+Mu0Xqsd|I|I&XDfZ+)X#W5KlmSj^cj%U(AOYirSjM*qOKX5l6d@+Q z6wGYnW_bRkFE6XwX_{7_GY)8|I1a!eZT|d@A+tFh-ckPmITaC2J4cXiQs&?qcr-)$ zX9w-*pdSkT7R59~J8}FKlVG}k>vd619zfP_>fmIZY|G+WE35HX%5K~IDh~ZKDr7`k zL;)t3`8Q5|V*XDv+^IIUjZ1WHjWsC0@B?%HR$yNdw>O7`Q`CJ^!_ze^+p#_W0JA0* zoHihVQ{meRr8@QR)a<6anu@Bl9_)5e_v9zZn0e2bS#7+e_7OQH76f|q1D@ml2%8-Q8*z8l}Cwrd1G`$hVa4Ra!;dflBqJLs=j|ax}0p zCf^!rmU7(M&2MdQ8(d2w{{2Dq%7zs{dU2(515GmjU!uT zi_-&OPbFW8fT{L5Oo0rdH$>il&%mxPytSnH9(^svwv`kyM(QH1A&b%!>DQ^QVato7 zc*SPR&eQ&K=4ZKreLl|aOQ`0GSXGKOUN;P)f~4=*WFr|{J^&u`=6}tvGJbMt4S%R< zl4-h?%(jtC*AX`u?CqhHDw!B59Hns~j1BfA?U}HFiE(EkZ#PXh>WCXvlE|v5Rf@q1 znOKe9W~r?<%h;iTPzMn~-n-#c746blpm!ymjUz?-OvkYPII77sXmoggO!4TjhYHC%={v=$ehrwWoRUB!fxw7M?8Px}k4ML~$ZbBx80`MF8zu(0W5pFIUqDuJNZAa5n0FvZ=rxP0*3*k$FqXcD`BGwC^%%a0jxsm1deJ zS{96TZ=h~GX_1UTDUl>TfRoR<4bw$)`Y+&1qda1O{_E0Uifi1r+VBT5M8ih`?@*J@ znhw7vmviPF9bo#Tt{>3>l{t!fow*hMT4Cdf=DY+kZ#Ti^OWXYyO}3J4Q%|v;Q>ovW z_%+N=H!!iT)Z)Jn>c~!yCU6FdVW-XIZ!`JA`&09KTxq&3BPGs`@p*ut_H)N&r7=sS1JuNpQF zbB=LKfW`CG-PBhzOEs#nfuwefzRkmt<6nAp8HtebNRiaJnB!3a1VDX@*`YF$$J7h<)~79wQU?!59(XQXLuA9q-<}#TlC9^x zPbgZqn2<~?uVT276-3HZiKE;<0CxTvJbIIlaKd_HK4s@4^CJ4!$@-s=>}=s#wR_dP zyS@bak_BIa5WNBegT-tZH?}qTjrrSWpm|e8@*bKdnY8UX&em603IQM-r5uk?tSGEL z)?kW{W+j;=Iz;Cv&a25P$OkQzU~wTYId$<2DM5N*J5gV;a7VDN_WLxx%pA~ zqiOkf2C=2;`gE7}nxepcNGA|Y8$wB?PUIf69me@)9KIR0oVd8zx8~31&XxJ0rVBBm z-NUL6O(LFa!qKE?wAvxJBiz#`lUc?os}`8R*+FQ3n_gPhw0kcs{&MKI8k=bmt-hUg zVIYNsH2&^I*i?2SuY86)!m2|1lPm`A9MexN`M%p;wewc1pxVu*S!p^fR`A--J6v){ zx(ym9EtZN1D!FWP0uMmP!Z9NI*;nQ*kLEYzb+xUhl(p?5`&+z;FJ`lX3was=DuN=F z-{RzhsI5FJnwds2?{k7tW3Tz=R?&R>Y5A9Xr_Xn9rC9O$oG`>aIbYP`?34w!0-bX= zK^WsEoLyPmd)SLX zJBf_br8ZIN*<$OtKa%-WecPbnsScXHHl4k zH7mLHsmTC>sV0vup3+{ZySu~%ZR|IqvSin|q1iZzV8 zD-+3yHDW+M0=+(1601u6pgpjm^Jo0!zn2cZ`7P(&G&9K|(68>J1d4}(6Dq3o?vxer z$VxUD##CR*4WcZz(Ikq(M}_%vyLlka$y#j-2S6~gl& z*aB$Pr9r3Dn1#v=Ugisn2~^s%#H=guvn@X3z6)dpy;I6wV2W7RPt+n35TzBIl1ZWO zwRge`5)y4j-dz_@w1v{MO7eU|y8St5Em8_zQ&2AM`JPT}<*4x3(*%o7UQg2>&5a`O z%-R>^R+*$n1K-?9!B*`H!a#vdBv0C1x@PK8yq^njbff_$W<1|*`OoYAUwNio5^pz0 zb9<&(X%D48p%0)9U4pPNs{!z_8*Pqnq^>MfLH#e!PbGO1SM$yEUQP1EP*1L0yTc#W zB=kgW8y-%w5(4q1H?G~YKq5(}X~Y11ap%9wFZs(2M^uvP*G{mvmQ6kjCw(y5$rG$$ zlra()DKJt&k}d~xPPu1;(IY-StTg`s&OU$6U0yZ3(#(WgPYu*5CDJ0K@GltOhRe-Y zYM#HfUb!#J0FTaMk9#xI{{SSv=O(?=;$JwpuoyEveD1taTeiv@w-}NVPU+m7M_n}BXk)YHZ3dV%fX;75o)|aPN|Wi8Bz31vvd;Z-G{j0t-Whc9Hji=Y39kbcmIhvd&>e}}W7fN1SE+d~^0UpK zn2#m5kaUZkS)iemTL9%b9l0*Vb=cCLCu~^p0khJN{NoSi_LFqh*FH+Pog?DXa(Ia2 z--9dDm&(5QOlgmZ81J7y=N&&X{DG(4dArQsSiG{(Z2~;^UZhegE437{Mm3=#v>RXm zq)a?!2$E1EBnRYACNvyRjepu0mT#oLCV%G{FaH2NF77n1EbDr9mvdPvb;Asli2`;U-bCN?l3q`pkEi)H<#BEgFHT#_wre zLy)@KBP2ppBuLEMjXH%i8{$nS>F=MHKbktHl03hE<&96twti~S^$WXeo;sX2CfXN( z5EvL$g-vNw)8D3Fj(bt$(~}<&uxT^4{OGh#DgOY1JoDr`cY&_%@ATeNUE0HKaV=E+ zT(BObYA869^TKm*ia^r?E-OS${{T4=dvWEfe=KQw4TL^pgG)Lhd4@KV>kDG$vLZ%) z5Y1Xvv>VW5XR9PrAIbo3(#bzCJk;Jmf6C1p%gt-2-4HKz8)&Xs?qgQ30yl|w*^2c7 zl*25NFs5D%c(|{3&-1}Opb2vX@HwK^NS;0XHvk;R;XI3y2rry~%=YG{JqD`{>|4t)J#8gg?YeXeS!imyz`8lrYCG1CBehc}}6tMd41nirQeO?S__ zex0T17Z)>WG}E;dxM}5JWu3ovNeEZ%fE6i2zFi^+roW(*OsmgcUDv-c{Jm$VdBgK_ z%R1hdZ+^E4Gd01O&miJ~=?xx&ycVOWrE8T=LPC#5taITu2R1!r{{T2auQlwp`d69k zB-CvXPGN%1_3qjkMOXJ94>fVodVy2hG0BMJT)~i?sqr_Se64w5b9?1KGFv^Z?S%5# z-rAC5ksJ`L19l@~Dh|g5+i=-N80CW6&cf~4{;u)Hf!MnuDfmHd^uolwhsi!qx4F8u z)_nP6a=uKTQMRzW)#D$#vopTLu;|pO3P$4r2AJPR-qwHfjz9B_8kJOptjgoY}oY^d>fGc-BBHg(@C>ONSV#q4svnz zs%iiv1GRR`gh=MXG6$12{J8TjgJq?8zfJR9zo^&R9Jbn8l6d`fToq;m?GaCcyAGsf znDTIf*OmrEQ`2=X&mpGy2g|-n^0YBQuSW&-uA_YLa=MBcPuYS^s3cNrO4BkQR25xAPIW8hI=v7XFt8dJqDwX}J4YR$btjipYJ)U(Fl6 z8&Leb@(O7BoELhW2T}U%nm;)$gUAZ{fc>4t0Pk9jvCA2u7Sxu_(MqL${AiyA*|zT608zDf2&> z?XG0kwHvKQ>O1SVxsb_q2&7XGcX;R)h<|6{9}Orni4EJ}c0$8%zTs26_U zI*c@j(7*GJI_>6*=J@UOsr1y2{@!~_i+yH)M#}0b5Qc_HXn1oQDd}CZ+yi5uHK?y!RkM3$YKWngYZ@!koQ~iM3LMDDL?h`O z+<1D3vu}&lLMq0+M%#O47;~Enej~9I@S(4d%N2c*`7a0NjNVY5Psl~J^}e%RLQ5%7 z>fsdr>=>jp^f_!e4fhAGWa5=ZoIKn&yUhOp=Okau*FIyjzWmU$((L@#Et<9ZX|)ou z=#6-_A!aHz0Mn0LhN#&LwAH;l1QtRMA_&}fp~^#&^smXSL(Cd4oAibJzqC4q=hqVA z8xR3#=Lh@PYDUfe>`H*calToPX#&@q=`XW?H2(lMeBt?HZKV0EXue6*yt?=E&1tFV z*78qn9;D=ph~zHnW166cRvcK?n~ccKE*?R|#f)Uw7r_$h7WelvMX3~qJE`QB%IFRW z5s{01T3yW$6G)!F2%?D|aCKQ=ta=4QS8 zvh$XYrD(I*>hj-R!KT6Kw3jR>C1x%|22)Vu?N+%~qbd4ZH1Ho#Hu=?C(>%o%mFeM_ z&SG=ro4NG+yG=U9CYC>~MKz#-c}ZtEa6`nsU0tcpA^xzT!xO&DC&~ID`K$Sd`HAG6 z8ecQ(b{<66Y~sGRyw!%EZt_iOc4#2FxIBR^QN*9vZJ1LwSvHN)p;OwJvwbW7065)w=Dj{YFt3*zLyOB&M*-Gn^9*837?obJvn_cO%b*=| zFG&(llZUDi{wr1g0Gx#U*7L38+Q;Q5=2fPL3|gPnE~mTE?F27X_)$JWZ=gW>IakN>pRJHnG;IYWd8tjEI8U;H^R5dqiE#pw+cEF{owxqD>0n3 z2R72o?$ETBlRa;&tHGJa`?@dWojZ<>Hf(*${TiFh{{Wa8Pmp1r>RlI8)HMAr+U9Kn z_sj9mdUROLBfBolQb4;C67IW^@pah72Zxv1>WGIIP+tQ1@6LKJ=AN-9o%Qh>UR*;I zN9uY!utX9i;(<{p1qQ_RJ@W!a%dy3bKy1WChm_atEW`fY*B{on(>Kun0P~G@u&0^t zBJzc;l)8MnZ0oI^S4)xYqtnF<-)RD>865-@wcYxei98>bq6ohWHH*l)~!A8=Y?z$E~~NH5T@ z%0DY=H=akb^8T=zUcYg59NLeSJiDvul1(h|uf;ir<~awX8*;He#MZRT+(*;u7CrS& zyD0)xHYe?TU-^gU=JUq6KBwmMd2OiLs@RJ-bg3hX%^)0B2-3d_r%t=|B-b%=WjPI( zHw**?1{{~VN%(o{UFk~){{Wh@4XpF>&&tzz{{YPPK2`Em*RgAomy!u3f$c;>HRSFk z4x}=T#}ml(89ZQSy z9O|yFvczLFWOgJqD03%JXVt;M7|iTx@nknzS}LoJRJau9`aIP8{j9{NXUThCX+z;r zt37*tKz|n)q4lTa7n84!od=ujyx**OUej5;{TZW+TYh5V{cAe(A=brDp*X9|b{KwMnEd14_w3b?gwpwIxn}JFHys>XI)-+f(Vn5~;1%KqGR9uwfLAuw@l@6Aay4J5ph*x2idWMqFpNfooOil=~bkHohcaw-6?L6|Pe zk5xaf>Bs&&wWIE_K~Kg^G@5&dt!R`o4o7m#-m>(!$DFb$Fgy5i|=4 z;L&ajpAi5Lje2F;d~%W5#MER1X>O1I0Gxr<{MF_w`Mityo9Jqn`a1@TP!>N|d;2Cp zQgoAwv!>v@W~~gh-juhgTcW2OVU;MrYK)`Y9mPRAeC+`=N_aN5&fAH$JvKQQ@A@EQkK+Gf`e|u zulC}Hx&HvpHC!dH=5B*`G?B#|4{*-%kgGuho;4%@Ph;5S+GA4%qf;A;>fH~{I#c=c z$Xd^rCbvxw{4uLXph2ij>N(V9m4Uaom5D0;uE@+r+XKF5$b%{-fk)#GN-Q#k3hf%ol&F|&Z z((>~4{p5Ou#j#K;a|C5$aNS29vmJTy1aku!tv%8@bnNv|Ml zxTa=t#z%J(Bo7EaY#;I$&%c)5Nb_HrEwtT6`p@*fqdmQ*s1`AA4xJcgTFB>+^%|q> z_2c7|M8Fc=k`j;w@MY15>o-kmOTca=F}n&gA#=ru@gsb|F2X#wLA#V3nC)JNfAjir zN`n%#uE&1(s!=&LC3jW>r+if@nypo@Q@+&q7^+WlpbFHMBBHx}CjwGyrr;<#(v}<3~&G5P-D>6!~R zDwR7A6P)g=ReJ|nMPbuO(mSX z5BuvCtu>fHCb?$+%5dU^VOPe{_O767Uf-~xd6AMIyDr^QZ(K2~4?M-U`Z zG^-ySvo3W2;zSvg_sV)~k}>lo$STr;wy1XF5!smd7R(DLcVP%{vq%H{O6V19p9Qtx zP(Qra0S@O(-=zcb0`x`Fu_Hwso%+{#7A`D4_l=92^Fl1HetCzFm@biu$mdc|-O(NJ zX6awfJF|{aC}x?H3B)rIa#Q@w%XR7`)*Jqa%`vvu_1z<9(JuMKSYml3=6Q?4T%ndgZ z${osoNJ$TIvz*b5dj}iAKQ8ajeE8fabelFPhu61$QV7exl!|rmMIP*Ez~lxg)Ud+T2Vb1TOLkK?Ut<>tS6>rys2uNFe^&Mu)fRPbFwB0wj*w zFE(&3>j$v1KJ_eqHX3EaVfkAlx|2vYE{IigGo+4AlQfz5;_2ztYK~EbL6}!h;otX? za&@1ax_uRs~bhzF+siIum*o?WE8Ox-PG6h7xksJeMKLS=z6NWug*sGO)@yf+J<#y(nIz6OI&ITJMhP$4;6r- zw+0x34?_l8`xk%M)fqHPWR4tw3SC|@7~P#Nda`&V;d+9z3l|#iae}1j{OA<*Je$In zQ%eKw47~H)c5v1`Xf8E3u66TWKgi@^)T22Wb6psxztMN33CUY&tFK=q4=e69YJKXH zCVlHFsL?E7)?E6%80IEFSDbQJh5GaxtSxVl9AZ-APc7c-fRm`9n4#@$2w*XKO5;9R z)oJ;Lq^{xd8vBMr33+9KmgmjMnr;9Vr8LcoYEfCaenQe%41>bYf2M-8tHT9F#b>8{ zmN6AF9*mgY^K)!4$9KKP2G0pcnI5Wd^Q6VyVr2>;sX z3enizL1lC;v^S!%2aQ=D#DButlz$WW@ORYmNx@?3#RYLB;im{2=Se+z__94q|Cd}x z3~e{_g?Ao$;B#ro-TD8)nsW$`r^Z6%S7)@Ayx!M8=8;C30gi~7!>{{+EJJSxCKhT4 zmV*IJ>^dP3n}?n3qIPPi63vt@tSiZ6fmDuvdRX7J|>~ z06dmQZ}4jWs&1I`?)db_h9S^Z!8-Jil_>A{jFPp6kb93f3?q`|9mSQ=xsqq=KD^^y zGiTFTrGZ>k?{I8V|SWrij8QMQfx!~@3_332IT!9Dm zQzp|MUFC%bgWaqs!(dbas@NYXaf-_9@Dr3U7g?Uy%gV$Zj}dZ;$BV7Q~f(VH?ud)EGI8VW6moa7aVZOa0UhuBz*Btsw8j1W^Pr zetu-;VF7)g;a#_yjDJ!C+y}F#Cgzu$?FsHF8rwR&*dPwaWy{rfaTC4c3|t7}#CrAT z4As7K+SquFc&kmd^6!qd*##`wm?Up#$RIS`h_6@Q4p)=`3TLWyBb@f_LHB%I_fcv; z(^V_lr7_h}KX_2HV*&A*fu@+1h=DfHzVgjXZc&uZg83p>YLl(v7$JxnXh`7>k*UC? z1LvxZb%s14Qr`UXRUp94<4xnFcUkgX#@&p-+HtQ*LnZvHoJJ|O(GD{;++g(LG%KGVl9i}AXj2Ym&Tu2M)wy5k20dJ#xICPYNF z0E#`%air{}&?0XvZ0?g|uwvEKVDIVCD!2bG_RSmJ&%-&sZZ0Hh>YxTGOM=KrzeRE>VQrE_e*U7Z-Z73`Kdn0wqQaJuJ-C7m zW3$7~q#AEiLuzeZfRBw^V(OqWe4ZJHO@ozSN-JjnQIv#DYr;Hio?8lnE5sV(0d~45 z70oOloo2z~ERS7pb9?Z~UYSNs@&movXt^g1FRhS7&3iP9q~NyX_?xW{Qv#5bvb@P$ z-QF}nkKDms?zD|Dqk6BSLh93xoP>I?xae)%)gd|e@ss(E?HsAh!!pt23G)<3B&v0y zj=4lV&0?k-zf!3J11#b{B+)naajgFKhA=v@L}k&5`QvrJ1>nQ2!1@G}Jd35R_#c9W zfo8wI(h1nV*iuzExO|D^HhIxe)kXqK?FO?uQs}`TH9x7uVx+g+#LeM^5_9y@I_CPj)Tg;NdmDg&u3<-U{m-QQpOhgfR z)uSwwGD1*P?mr|E-)88Rg~| za0y~T;V+_0mb14|E!E2VDPO2eGwJ-@ORlW7a9SzMKMy|~kQA3khvX-D0D+AH@3$1E zALh2l4$rXZ?LO0{mFh7|tozV^4eHmhzSj$Mqvpt`K&`c~=S;9pa{nc6lkmmR;^3buF*u{Q}jR#C@!bc;v2rhsfA*5&VTCVgt6EVB=rumFz2I(8|9MH z7-wa=yU6M^)V(iJp)phDD2=##0B&-d9*4TKZz?EFg^xcWP(W@q{1#>b%PCmngq11X zEMBwbRT`(yMXMElS7{t>PLw$8rjj{ZF7jRdIuaK#$o?0KbnvhB)g^5TKT|fFY+v!v zhJMz=&Di5*Lkc&Yui#_zMgd{Sf)~(;Ty5tSsEeS5fKyr#A?)>eL0b<&c@J{=5=o57 zL?K#T$wsb;&#J*r$^-!_I>Ioz;ILo3N8~9hH#bKU=C95RQ#PgI&epS=)Wx$^)OC!) z*kOMvTx~@=|26z(S+|J(^_(d>^Fk~JKNPWSZNskt=dUWoSC^lc&00}e#ib#WuiL%z zr!zCGc4FXY>*YYe2SIGToWA$vr;NiIwMLn!T-3W(`CRM48cxZz_hY}Mstwlf5g_~C z3H0i7-?Dsrj2`EuN?CK5i{Z#Rf;q0%u+7F1nSsrZU z<*U|BT52uxJzk!1wkl&_EUc!<;0c{38BenE0Q zrdUnrU(G;(32)Ds@>6!(6&Blx`-pXk9n!V~rFb?hr9T*2f;@IIjDq;g;{*FwJa%QO z@FIA(iE8iC)qUHN9Hk~Y5;c^bp~c~zdY*{g&t~!8o8VObTdSs)N%w$Y$u>axI( zafzjdqH2t8CVXRugX&|}Ar-#}B3iiwX6~i;?ZwU(nmU02Cgx|?n8ck$>cJn7#$1Gw z!VKIfilTn*+h|%H^krgVL0SR$VF7wr3usn}e8v7B`)nZP88Z ztCmPJW=+b%4$Mb8d<)2X8A2u(rh7vd8~dH-Hy6%u#Nm$PJMO(8Q_r`$)Eg0`@66j>`(P9lx% z*c(c(rTcsHQZ~F`NG~lBKAx+#xS-cQ@BZRKtz8mZTDyD>SabdKOM$en2HQ9JTfbxQ z{vbm(XySHa>h))XGmG8hc34_CC07=Wfj!rD)pOf}X?MHMH=$4^vvBEy-~ONcFM4C8 z>zm6I$hPl?*rX8C=m-vAUg6ZCD8nh5a$T;AP{TUai2FGY#zI_l{^_SrOg(Z+vC8U$ z-=-LE)AG1yCea<8efLFIAQzN)XYLl7xpKp2r*&oJ1C6{x%5`!XZb}^CH)iJ}Rb6$0&qP;#^kx>G?l3rbBrk5pNm5oyDNJ5~xP+=*EZ<9|GQncMBER?i0 z9Y`%N|Jc}Mr@-PAa2jW*6Be|zN}h3Ts~aJwOC=c5pCzsIBp^<4aH{2c4rjZApPDOo zWL*gU67KJ7`&*IsIKPMO&1mCWbmSuG zd$O*z?;cA;rujKD+&;Ph_b~?sYq@US2%Fm@a%uC0#ZjEzQ~!`vl~t;&XlLimjQ;cC z%-;S42L<1?>005BJ0}W>BG$#TkqWBMcHsYxcCdoOC?+Fv`Igzt4}xYkByn~(N~UP% z^3)g&&+ZSC>2@V=RG9C6By?}fLPdG){q2@meTOP-pOkdcVy4yXY+A#)k^Y&B;d&C! zdh9R=wzCgYF?=)V*1Y8EB=UT@pY0n<1AV_Go+eN8PPpYwJa0NP5-+qRlNYHM5CS|D zx&IK?P)epXbzsj%8N%~|?!ZPxC)tFLkH!)7BHvEdWIrC=qNYSPK;VHeoth@@DPGFh z!3=Zu`t`|v^eP((zJ6s+(*+;4O&7lg7_;X7UQ+EzU@+*=LWKz| z=?9T=uLVe`mN?FjIzPN4$$jgf8Muy;%1DlT96+z|LcZO$y~4b$Uh$1m&23yA~u7kQQtiE@~kJIO1VH#C6#UUa21{5YsgffS|N^+I0NHBVV36Ix@B6 zg4x11!t@*aRDy{tWPx|3(+hqI2aS#2$)%S|VgPm?qpdOl4j^YuJI>Y3%zuMB{+LM) zNeZ_%xnMR&nz(WO+^YOQfvpHfSh0jDy|4zLq0hyNHd;tUAnxo|FLuR3`R%V3ixMb;&-jZG>V5BdO5Gvws5JFjL#7lDkWO+Ka+;LFZp@YSh^cN zaEl8`>1ye{lvEWZP8ErE87yw9#qNJQjA_vKCTRo#kcBV@qo#sDC9g(#TqpWosUFI9 zN8>l|h@uw^Mo4E9bYpo&n{_x#1tIN~eqNO8i)ZuOHh|?Fq#~?-nUVwf z(yuwfi%g$z+d9IuJc!Y8xJj_0-%kPqFwy96+V-siePwuXHx^s~PPAbZQ%rLg2OS;t z%}xIf9R>7oc!v7f*+xbzjH+62l~xKqXkTxt=i-R`!!Ry`=^Pkf^C(urqNW_VL^N); z@>cGF6i(ko%QvZh(Nctfh_V*UQg_2XH_YYHy)T$-08oOQM|(VO4|XupW1aBzj ztF?6#|0+_FcjcPYsgp;36dY{?<HLtp5rYD}tf zJsw0GGdh$JO8S?x!~C4e@KbBHnw{3)^g;tiu;SXmILAo?4nxdm%J4hV+LPRat9zE zAcD-uL<%$^3*ZA8UruWtq{w%HL7!`vE^=6_l(;$mBo!~5T9u^{{Cv$T@zYah6;ji5 zLDKj;(bS#G5s4|#4UXvKoxfPph;9-_hlDyx@kv&G*<&%>2F6ru9P4+_8;md^)7S2T zEy=Nrgd34rRlYaY{|+8BBA1X8x!0K0hZ=&Zv9$-?ch-vMf3OW>b9&DR5>siH^_tK6~a$>SbfsV z%W}lr${Fg2YbAUe)Xm6n7rk?a8m3$(#M#R`9Ro!TooA%r{Zv)piEO4H@I5=%1>c{m z)b)n>-Lr1)eYrf%a)5O&t6Rdx?tHXe>N>DI7apGj+)o)HS8te_XUGXl2c&rrc*GEv z&n1ju%OIEkCRJOQ1dz)_cZg2zv*-0a;_vh*-CnfxmVTT3inmaUQ&nSUmXI1u{$~I2 z2wb=%tM!?$OS=fbj27y<78`ZA`cw92BN{V<_AwG7EHv!^9Dd(9rOrh0Hvf$mZPv;L z%6@Z0aI3#BY-MVFIIn67cM(DpMQOV&{6JfDemAZ85WFYn-HmU(H}!%0nypIoo6rsv z!n2;Yu*~@)gS&oXX$c8if7{+RXNP6Gh6_FElvF0=I;9<%?qPF>Vzin|Gwpn57*O!w zW5T6PmXds@5HmBEa)1|>XQ)h8B$R0swM?)PGg0-m*F?!DZ~ZT^*Z6MBB&^VPJMXsI z_+qf2RZS%T9aZG~$ghU{PuMnTt6APo*vz;cFB)R^YaIC)<8-{wwSeo`^;_b-6OD7T zIHUztH#Gm<-%adX#T|3O>s@c^X zCCY3s0QenY3xlDy?)6a51#2VR7K34Z8Ch0tNEl1i!sqCO!7^s2$hRger+829h>~!t zj~}C#<*!pQZGIz9N~TVYc4AWw3OzLnPp!GGjA~fw`o7l9R&iQ~U%^|@E=hts%6#_} zs;z*BB;8?h2WyN+Nt?m1)C?}y;YGL zv0~vJU7rfgaXYH&q)nZkTPCa>en5m%t#oq_z!-ZRa#5us>>Z{t4o_Wq`dwJ&HrOPx zdz`J-X1jlSRm9tc+q@W{yLHVLc(cOz;n3=Ag@|n#Q z;3+(_6{)ABHc%%01W@0fiTJti_BZeq?gH;Y?m@M%Sw^fXd%}!rNGlVFZgM)mV~vYi z{a~W*=m`>!SeL;BDRAhME0M3N&DNh>M3&$^oLP|ni<`{iSYMtceLNZUUm!a=9#Z?e zAx8iUo3!K}V6ZiH4xt8oHTlSxDCxmk!Mh?m;HXZ$9;z*TvgRw~qUpEDX@DEM`?Hrr z3x&w{T2tW5U>eFj^*}9S4+7SiOK}ldShEKt3fd*3!*vg@&vcU!8R=ncwt)VYR^)h_ zaur!Af5KqfZM!bTWvPu)@raD8{!D{hFU+AePERk5<4-q&tMM$ds{7?orD8mnuW`8cVxp&-WpvnT!mdn!jjP>`HS z-pZOq*bi%49z*uzmRTUD^PaB9fY194IbOB~O%_AVYh$G{jO}pilR*Lc6f~^JgiBw&Ol2l-S?`6Jl>k|yj)z9MtVpN z2ggH~CImYY@%_UEk?|WCixnu2ch+s~EiXjfJ~?i;V6i3N>oReX9JG{4C{MEjm-%+^ zll$9B{ebx*p0>UBaamP+R4DhY5wC9kMv!E9P{HO9DI)(!lyk9Fd`$uUtEhr;1nK7~ z;K$T7r;u};x8zL0AHyykW)$G|gjv@Ka+Wfuh~J%EY??_>vP7N_l7@)~espX~=~#4{ z>cgC@P!*Vc12`XIFiCgFoTvVb!r*SV-25-#Z4We*dDTesFzUrQ$DJH2lE#KW2ReL96%nZi# zC17xiU(@{jI66X1vif=Z@roHdv)0Vtv~jlruZ*jGZ*pqB{loNLOPO$~t+!N}5!p4L ztDl;3c~v1Vt2Yaro$C#MSt_`VgNEjF3r3lq0CDIefOfTZ6R6$($g}uP>U_vq&8VD6 zF3~lIw?LgQGETIO8o21J<|>G)1-;o#!`e7)tCZ|95qmy7M#%MBJX@#e(FcU)D^vg@ zf7k2?9cugKr# z^uok#dfcLfs^*4NxwFN>MeH(y%#U=Q{k}tm;+4~gw6-nkAbnkRe0xj^et!P?uTBi# zhK=skVJ?E+^rGeFsG#zl(-oqUei^EmW^{dd>KJL<&sp(ESjoscALH=30+kdnsWsXU zPo$E#fD^l#bO*K^sKDS;WiD6mNe}jMzo*4T@WQ=$+3)rp8S7jNeIdQE0eb zY3wJK(iE?YCe|pg#mQx4TFInD@4TmQvVFJICqefeu$(uUHHF$$0TV{cykI$)g?7s> z21nY?hVvfuh340I$7Xa)N)_|9;+$S9h~<(w=fOvSFm!ux1#JfS=%=F}Xec_u-f4LY zP&QOtU^})Z&&`zXHlIL7$M|(@IoAbdxNYTVEr>m_Z@xaAUu89-s$S2IIfm}xK`-e% z`gK?0I|lnc*TKIo;>FN-S5ssceh2$Xym{5Xbg;tMtd8h9`~joy;%#MRwYGDJ}r#a^e^B59QqS zW}y98`H!t1o660#vYFIkFqzUbsC#alkmLhibn{C+! zAAX5xa^ zJjl1!fXFFi^ljqrAC2X<3JonwX#b*P8l>M=SXJUndnu|@Gcyg#B#4<^GPNi?$U%>L zzDbiL({HN!_pISbpYGhodbb|>BF3(@6JRhe%+P=;t{FEsq15q2X5|zAS6Xd#;{eS7 zV2{*z@(2Il{_=>wKpB{*bX_MRe3|0$fq}*cmPo3;=keL7uQ;5qSyQf`9jEPCS^v_N zGv`*yRC0F*HUs9{gl$Z2>nwABv--SohWEEVrU=!%Jy`XfsxrFZuW@mGvbMoTD)S6y z`16exfPK58Qpi8}dVF&Hqq}K;rLvsaZkEW*_LhI6>0p!SM2#sZ$^gEy;9;qevcDb@Z5*st-YgWqT1;<)LS%hjWFo?tleztEX7CRxX#- zA>qHI$egFxCjOR@9=5E&Z2vnE0(cv|cL{!9p|1<`Uw;B+N=N%gR~Ze*G)0F8bEu}U zJPY|Rn+FKACvCV)UG!KXjB9Op4ZL&dGaGy#a{LtG#RLQ&Ze-xe=)0L=G!sPrS|sHa zw7UIG7M3M8lLYIvXGGu$kBEDzS?-z_*}%Na>Q8dr-Xo>`^`lvCR$?XL=NLIzb}J6i z?tdOD77vh3zwR*nhcweGROFes2?If%=j%_l%akZgoh?i$xg6Lbeg-QDn z9_6^*2&Uu)bJeJPC|;NR(qzDJV+|EPfK7iY>AY!$*zCb6W<}A!?oeD)vNi zrNTyDCJl47M=UQ}5$&=bNDqE69gFnLDgqjd8P69HSU}P+_~__WefbV71hSY+l9@W( zxcF97m;Cj_&yH|aDYP&*Uy|@qCFgtCd7Sol-?4uy58W!I7EzlwqOiU*Mn~==yUBYkr zUx_O|GPTisdSAnaT4m)^W55kfBf0KgLJZJuv&&KxpQDrh9SrcY zpijgUm2wsp?aFiX`gXsPe%>rP0ZNMd$KkHKe9HGCoDUs;o8tIl>~UqdMkqC6qs^f} zqx)~;Hsp$hYa;7+*@hx{%B53D2J@TyZw)%;>T(7}xaug8JU$rQx+5#ct3?23H?jbp+ zHJ@KXxhUY@0!j^HC1^)miA5L`Ppo=xlXud4jBa1s&433!f&}M?JmaF_fF%p7QHDRC zm70no;mJnopM)^3z$ZykzGMfv9&y6O3(-i*%mvPRK={uP&_3!Cr&&7J08WA6hY6q>_>xZdLkx5)KQnJWyVC<9LyqQEr?Tba^<<`V$ z_KL30{?_KA7v(|sA9W(gv2wtkxDFmZuz{C2nfslzhGa>T!ZsEXGZX}C>*K3MDuac2 z9LahfzBZ}kyElPk`?z}_lme0lCa;V~?kX>?Lg$d)^nS z17c!y$o-`0cDe<&mPg zr66G|rPO~Ns!Nn9Ii2rgByzypCnx_QeHnUR-c;7^9=mgwT*DN;zw7a1bMsECU@I=n zP)uD6T2le@Jd){jq%#cDYU~yxytu4&GEWgdR``xA8CsS31}*g%otYZ<<#3H@b$b)@ zKcqi(6cwbLc+?4<)`&7kRVdA~uLobj_tu-3rPY+e`Fk5(jqGNh-aw!Fol?c%{86tG zYNck1Pjs6)J{6-dgtqFBXiUV$S((IqBY?Kmd|BwS#w<6jX zxrEFyd&=YMyp6z@hqC@PaW{O1pvg~$23rP0q^Bd}4^z_SsiH93)@uoG$a+L~YhMT- z>kAklzOrR~A68%k;;5WtKsX?xt$@qTm)hVJj1FSRoE4X_rzB~$165;Znpd;aukAlM zFI1lL*sI6>B=q{%GlyfBpKG=a7)(-L0?JrTuAcq-#RLMIinhaWx~Xp6nJcW@0`aZVSl+;nl&mA_^y{PsnL z`wFeNjbyDJ>cvYp4C|@(wjm6KjL69HkK#B5n=h~Yct9aXtoVeJr{o67{OW!K!9xh7 zSVd(J-h7g}Lr1$g-nC<|k>wIr+0O z&whwFycXWybfdP^ME-pZPzeG|@_;oL&m9kSt^7aIgvuS5{!Dghzr^JHk%rybUdGBQ z{G5T7*2~@%RdVJXa=(+}q!PinA(GtEI@%GEojRoobwv`Xea-(MGr@isjZK@qYDFmq zU+5;kJ(3nNTLg0mogL29z+#oj~L1Fssw<={|sGqdC;@NYBQ;9BquvxLWLg9m&QR5f&Jszlp5LKeO7{qU+t}mH6 zv@~pF09RrX*t@&BS0QxzNsYef5E0H^@gR;f2PpsjhQhL&vL6u~s^j`K*jfR3)&<8L z(1Pl7nPKh#rfrTg(O4|Ytcj1ON5>m6XY@k3YTvZ>kID+k%jCW3doh`~=@%$jY^L#I zY(MEiyc^v8uJAX&+rFew1He4b!rDYDw^jM|h0;1=J{%uSnK7jYu(aEe6(0Qs}$G|}$fah~q0`1|hu zvD^NPR)LMEju;mL@SQ5dk&m+@8tQIPfT~7D>Kz`ur63)1tcXX9=vh%O)j>fb){F2f z-W-oCN45#uBgLjRJtAYO#8K@2i;eKpqLWfr*t6KFjoQKGwJjp0M#hjcv-*Ul+#E}Q z!VXsmDCgc>sdf76KtkyB_X;*9Y{!B(AkmpgO|R4CPx`34_{Ep$&L-#C({^C*K6hgH zUk`SA$g}Yf=|X-)vFd4%`I~Dp*Z^87b(l>fc$%G)d=itOW$a#AA?xv}(@6v*B)jw% zIMoJnhN6lN3Pc!yrS2dj`qduwTj5}B{pgmjSUfADI7&PPqQmWDr}cj)gI1Cjk4tSn z#Bn@wjEfhuAYrnv)?d021V$q!OP&*nYZUAYsW;(`A80i=5BC4!DoznSoGx`X?vK47?H5}&u(Wc>-iUnk)NCXBQ5&d zC%hjf^kNe~t19BhgpC1rc!h>yw#*`kOYsCQ^Gb8Q1=jRdF1kGXi}PHIU-{l42~do~ z3fY9F(}G`IFXdy_WZ}Adk?6D-O3eE*zHs=!mWt(t*ORR8}tC^Tsi)pHBCH`zs!D?mzh_G$WaGUw{|| zbP?uaT=|!-*`S|PhS}+Z4H%bOcREKnUyb~Y?euAD3O?8i^9;ym3ajX)oL{O2S9=D4 zJBgZ{L|$AsGx+NB++rdJf8Uy$+{O~U#HIQs6#`v#z0+EA%@?N=NW7RnI=kSOJAJR9 z2-ox_UU94A9<@E{7h%5VvHUP4%ItJ6`t8Ku6TY}y5^m?I&0>R`F>bIbd_H6;S5q|< z^QM5hHHNcGeV3-y8qXX}r|eZ9R;9es%Xo#*8@N}u3{C{J(|GbMQ0CbdubiNXy?T~s zEW6GP#r_x4UNzFI%}AJ=4(UqP{~+p%HFr{=#hWhYkQ`}+)R*uPFX7Q={#vYMq4a9J z%bS{)dtsL@mxsvSnwbmUS@x17iYSGsv-LbOO*S0m**DAb!d>_e_1c`zJvz0D9`ef$db>pWGP=jQIk>AI-iJx$T2XED-VpBawjUY$`9o|1MvdKDC#JxM^)CVLnZFXebOnAEd2(pE>_t*>k6 z&`5Tyqh=+|<4nHBiDffivE;5a|JYch+-LSc*?4N--@(eCk>LcvVZvFk5=U|;_52S> zU~lleG8kh%y_~UXvEf2v_vzYFqRxpfE^aI8gMI{2y_G5^J@6umea07p5H#@-AJd{I zj|1Y}t<6Ci|JtUUlGqcZQ4l*CvW_Qr`$NCmESQC?PE1mG5C~*4)25}adziZuExl}8{49jB}5WTM7-#@dwF^(xprVW>ldxZ_BOz8 zGHs0jEq(E8oWz_H6X#SdQu)r0WhKF}SLBHuk=%>(SwZ})3%rB6EeDA{S4l^`-h4kj zv9)>;igs?r;c-_;g`xgL@c_mKOp~}YoI&nCyTomZWj6ay0 z$_B)ft`EE`25|PL^Ky)T!224b}Mje3C+jPZ>y%D9V6M?Q^p7+>fae~B{PW?pc{vg zU_xEuo`AXkO?ZhOQFwF`+~@sm(3hslz}tr2Yzqc3s7>?ui{%}j?Po@KLNn~pEHfYN-CLE>Wm z{~?hyHRE7}KHbG{%#}zX$9R#8`o5Qk51>`x+DV7Bs0FJU2$)w9jP{|8b3ZhaLgAT*ajf< z)q)|)`y$iu*10<)lNk}QB@aIgBc9>CI|C){o1I6F42o*qA7|#qkS>iTOh!>Rs>T!LTft1J#~|o?y*`9#Gf6|E zo9oPoq}qqSyej$b&kdpTBQ?G!DBrz{5K04zD^A%~E?R)DP8S!RW21(mA`SYNtt9ksq2I*RtTkQt)5(< zSJXoYFdibAscfPf1ZbG&GQ)hRLRt8sVg2dXs4@s|Ba!q8dK46nd~jNj6r2E!Q1&so zhxjfX<#B_2G~g-801|!u!cQ#!<|rcBlmy0$Ozj(;5z|4!G%bUXx4s%ML6O+Z+>(kH znTP#5$C&A&k`bWWNnIj-wMY@t(40p3dQ+{P8S7WGHJwjekN8m0jC;SYQ{c2GlQiFv z+VvBEmwEH<d#**XC^9a@(HQ0ugSf6d`&*Fuen z9nXsQVM_O@ycN*Vilym*t+bFnRctrLjx2dS!}31N`%-LP%o$LKC`xrfib0U6Z8wDb zk!cMSDl0aTOE6HR4$(@GER1-A^&aJ7BI%8!;mGwNeai^olQ{OI* zBQ*fX8Btt1cG|gvdHCRRreU?>6iqZzCPP16(^3SG4xq5{vMc z!{^SEW=Aq&gU(o6yrub56L~7q7eLvAD>#jWCbgGHLQI(Y=4ezztu;ymiednbAi}=Mdcd`Q-*IqshxKoMkL1$|3h@xEtD;QIhq)_V|XMH1?<$v4$Cj2 zgysh2?LzgDf!bPD2qO-Kv{6*~G`MPPV2L!W`v%!q5M(i--A8}t)Et0*Z5^BmZ$V~n z#25W^PyR#KSq~#|Oxm5?QuAtGsl1qT2R8U(Y{Yg8nfOI8nSZ(>8{j0Aan=sQy!|fO zHG0EJR_*=aoNdB{^VP(_F4uP6cja&g0!k(Ie}(SJHv7y8M1|fh6U^eP(8L;rS3FF` zGMnCDk*P7_fPx$KZrBnL%`8!lJJE@%ZUtd-{Ukug3q#ehHz;&#n-?1e+n%xPo!k^c zWCc4KcaRa*L5~A@oiXA6;K8$^OhVmkh+4r>IDEo_dtsxdppNH}gfhdznwbEyQND>0 zSVvv@ku!ro1&~Vg0;S?Ru9_34EzI$Y)dPY|vK+puFF}7v2y>udjI`0!V4u~#ExC7U zhIv3u##p|NuUu4)c$I;wlrk>~^zclS(28g(C`<=6IoVgqmIytK*yDJzy>qF=j^hzY z@fF|22WM!F{(nf?0`64H6K4xe{o7gLxB z)^6Hnd)5q;85=IZ(7rSyp#qWSigzk0mR9)!$xv>d77~3myVShLF-L+3Qi7o2 za6VK(FoWQV@7PFTn)3Q#E_eIZMUUPB{MrU44a=(qUG~4OsQy2Wt~#u#zi(3t1`-m| z4bt7+E#2LW8c4UGv~)Mp-JL4kF*>D&v~1L1@O#hm{?B#ooQ-dM?kw0A9Sp3jsa=U6 zpp)iyBGwL%_;P@HYPzcM@2-0 zoVbI@6? zjXty~-=s@2;iUD~v5#iZ^*oW-c{orkLf({A@%~7z@TxNW4I{^d$P!+}D z=N+{Ql>}*^mW^ zPBhAEO-NAHgnKaJ{lLJJpb?q-56aGDJ#dz#J)`6 z{=}GGMF%|*Fykr?==Xl4+oSfWy3DG#b|~FsNI!2oYh+lEr&YRzz5lI;-Hk7Z8o5OF zr&~I>&$VHDyi%g)Fmx-a3+y66B`OufDoIDYufN|aw|_E3zKTPcY% zNNuG#zhsKHoIb8-y_7`af=vL<1*mc)rbWL458^$KJzvs6*M|GjX%#Wx26;% zEY7@Fm=GXgHW28v;a<&*e{vghbGgx44Y_!2aCBm8;u^4R>|))r#G)?6j9PVff7NA(Q>PC^!v#D#R$}S2xh{W4 zr>$(F^&bkEC2D@3AZ&1!(hTN$2yKAkOdj_xS-Zvt2->e%clhur$6$Ox<-6}*{_-_7 zY?laNGf4-yd*7VHRvNm9jR z06t+uL`~Kv(KGv2m`lH*=4ZUvG7Sx+!64PsNU+}OwrVQxM_YJrtq%nmk+|Fh<^~TcL$4_)0iU=rD9;9v&Cd4%^hE1Pm4ca z&X7K59snf(ad1J{q(14=(pQjRh*kO@{ce1os|*;O)=32+nkGufBNXUEHZ{ges*)gk zVsNQ!o4?F;1-1}}2e>Ik%FSY3R#La#ef{G5b(|g-R{h5TnCR>zl#1EVpHY$>(V-gt z8~VvOGwpIeT(zof%@`Kp=6+;cICIXErQj#u?m`z2&?$i7LqVse~FI5=g(2op*j6V zOJY@rp$u3-r(Uz{mw&5@C5_r+aF#2s*PCjK^b8}Qta?s|{WR6UIF?@ZHBf>k(Xjnb z-OKpTmGV-=b6yC-jl(oi#udFtjTk=X)c%`+FTwwzykmI)!zAGkj}zR+{-ik6Oj$)8 z1HlTA{JkgZWf1XKWit8q2H<9@60dSw%Y2tzrzQ`u6TqKSTCae?t$c8Y)T0Hf$n8Id zWPMJo@iLD2U%9(O*nY=9t+#y?vAy}c`C@(__XX_oSb9Uj=Ss4)ghKtu(Vnu}}DVy{n2bts6 zx>Ox>EecKX-K0AG_P^yuQ@>`Cqizm}xw#drgHnzZq9;;-nM3#On@F)}S`l20kS9;9 z9z4Bf!W#j4syUB9q9vs#E$fDAfGOvnR@IqDjsos;roZdt-bESy@-XUcBQ&0${TSQY3AKOD9oiw!Na5NhQG9IP z)>w1<=EpVV%M4d%;(pBD+i2UzuxRO~_`XlnshCH&diaNT)g~OVKAA@m* zV~J&XK`J?v-Derxl4TD5;{L{Mj_emW7E1XgNl)=#gM?}{2)4~L_5|BOXJsJ<%gncf z@exB*lOHLh?(NLF=k_u#*!AgSFJ`nnZQRRM1JfRPDuM^>01H@mev=IL>!u3L7b1`w zOT7b#kEq}E`Ftktyz6IJF)lYYGeL`))^8qfEwk<<{=iNNT^Z)8pA zFOXu7St{O>z6)`{JyG(8Lc&Z|cS-D*<#wE4o$uk1Gq;xP>9-8!WXYT=h^N{p5-R$G zD{$?fnw!mSzbJADS+^p|kTIzQ2V{};7Rz%tTM`!Ltjx}u|I`Ep4sK+76^au0r|MO3 zh>tI&)}{UHPw)`dfgaCn>HCIO?d#&Ii~BHivq9rOqIrc?aYvYp?cyQNV8kHC=Eb}?|$a44ra=Z=+{{e8u1{4SfZpO7(N zx$lng%bBS4xXm~up1?(9ubKyZh1ztvLnx)Xlm0s4jQP&GN(}bl)(oMG=1b;1tQ{Dp zrPD>h3JH3_%sz}?)5VyEk_6h+wKSL`l@lAF=NGmy=l%u#_)2Sz#ki5+am0nsbdy4n zPw`OCVDfu_KJ0TSYC-ndRjuOoReoE)Mz~Gw#2Z4u#UkSgE_6RFq7p(3Q>pa3%HTcb z*5&C~QD0skaaSisy6zm~#F1Y3QydQ6Wuk5Ba+f<*aL`_I?SI$@C0$>4-Y2#z9Nio+ zuwd(dCd7U}<@+H2Z?Tox_{|rr2F<}=Q6A}_8=YSqV)k)v!Q{NMk=CR8nVu(-^Z-C9 zZS*n$G8J~l!Gg|{;64y9y&WaWj?;#hy*qs@j{N1%?$DANk!Sv6Yw5Z_1`(T6E76y} zl&ffQNu458DXRPSgr;to8Y_uz8=eaJgt>%|)0MPy%GD$v={%W1ch_4@r}L-u=E*4e zZOIR8ZQ?m(3Ts`+_OL&_(s$`SH*%I|`jFoDvk8*AU(~p#&T&=8#Fh|Ohfl8sV%!Fl zG*p6(M?G}bcFvxe_>2b}-L2M{q7kBXRF+4xUF3AL;B`dJ^iEcHMdjy;D1yT zb5a-oGF|@V6-B;8^RJzHAS$^7)LcML7LOx^v&~yfCbDNv0vsrqd`%ifs$^OjqK9l! zbf5DRh8*$&y>IsKi0f``&zYtY#}5Lt$NkOXh-ts&?G8fv8lFAO3t^33em^%2oy>gi z`|x=T`^)qGL(v!pq>eesSiQeI*koep@7P|5Xxmc_3U;G6dGKKVcvjlvT;vz^8)TdG zB={cc5FrUD(T=qeI)7*riz2yFuw_ZUVQK@nJ{}ZBzFEI|I^Oyy5UdTs|~*V zA8`qSOB=Ut6~9uCCR6E)%2ZTIN?1eRLYZiN0+5zCTzb2^Zh3hx-AW60lbdiy4Cs_d z+}=Xt%;~s~co|o1c3n}(3fji-Q}iW?+~sBUi@x>+H#e80vd<$Qp`jdQeDR;`qQS>w z{tcT;Q`3^5qhHr!kf_`iKE!in9Bkvlo+~5(F{~dR=<9YiSLbOhUb1+XnEI8|!D~BI z;6hRadFfX^?~M^}h$|zLk9_sAkUMF7BPTC!IxzL!AjD=n=DyU2>!iT9M{lu#u_pm_ zMwz3`K3@E;e(4{fa9o1UqUxeDI6E>eK#KBcF*MU$>j_t)i^g83*D4Bs8aW(l`!1HZ z?ChL-v}e`{e%05$&>&BpP#$$PlOmR{$BY<@g54G$z)Dp{!I&0HIT|3zVaBr_y2tx| zX9K!@rjUHzv9H?+N<~Wz)R>`gVIpZDWG3Y6<*>4Bo!@m8T2J8K7-w z3-prf*g)hm{rXAeNN#~}ueZO=;F^6uqqoGjl3ZO~&*_EJ)@PaZ!@+SGNqR)Vz9N`w z9b~YxyK3*KejNRzWw*-p&WC*tUvjCzg`7U_wJmBHh5qC;YcZ&yX1Gc+1HrYB;+uLh zHQ^Zi!e$7?xpM>It^#-!gaQ~tlwp`T-fIrMu!3yg>XU~c#*^K;xvcB^gx#D{l+o&s zPy1&e2m_jm9X0+m6>MjQGB_u&k4a&XU&-}=cPhI6#8mHlOJU2HW(U!u_$So&^Gwu< z0@6%ry-Rk7Rmdgmh=Xmj*uQKm9+A$57e=7RA_0fJj|(4*pHkN7zC+$|sZJ~}%cq`p z{0X-5kt3^>O87cF>v?TU_LW*bPC5F7G)9YEc$6&113d)1d&aHLS0gdNvSY@|$HV1l zzvCxOLEFA5WPh7zf5z}EL=^G7n8u`hCr*2{>}hpR#d5JLkJ z&IR&t-<-A`mTgsMFmdL&Z3b=iKc$hYq=3pLj4w($E!fDO2n)UWG`aBK@ddcMYA_p=f;E^Gs1a=zDEm z@ytc}*uSVQ{u;19Xpc;`l^{iKEZtBzPd_ZzL7BJr^>VKIo9J>fSWw8~yS<9ajS^Gs zHqgSi@(91R6+&j)C7XH`B)Xh_{^ZfB zP2H$vjNO4gQm}Ppux0@d8%QlsTnQSi4V{sG{%pcNUGO!~p#(&<61_0WSmoY3nYBt- zYgw!~=Aq99jnIV(xa7`#=2on^-GP(-rjS(5o!)ln%faRuA?oalap0~lj*XBheNiD3 zc!=(u!Q&gEhv_bD|8 zkhSWDNR$GQ8AjxGyU~xR$qv@H%|vmF1a1^x(HkW{0dO*Dbh`-^au)}>ku&*YB5o6{ zyfEQj%=?eLJa8QoMAUtJ!KYod+VUl2UxxcC)(_VU?X2X4MFe<>+fnumGk(aA%V z@iaglWZjEC4MUmZSKTt!VE)_QVVqDysJ49D*pr2pKQ*iINyPWycY&~%U5jo6PcF`6 zzK#Ckc~IG5C9wgV0NG`9oKkmIHKf-kA6uP9mTC+TqYkE!4=K0KIEbObX<rYMPvSDx=9eIOzuAmf%lJ zE!~jj#m-BYTRMAv)ia>Q%-jbDrhfbPEu;nEi}>Z!QQ(eT%`}C$oVnU|p^+3QBW&QXYHRMx#AV*_So~<@Pi;nfZC^l9so~mv|xfz-mUEuA}q4W^{#e*^R3%j zUQ=Ox$J_x9-Kik6LN;NHrW^{z6E*lyEN6BoOHf51;ujPvlrxmW)XBItd0epM1HV#9 zg&=(rTA8Ab*-t_yL0&Nq-1z?K7QoUL8e%iH-P(R=_T{B4(ZRbf3Eq#e20~iu=ht?e z$j3=Inw5bAsuG{7SLG%}Od7ZyJ!Js}^U8VNdCjpKwQ{51+l4yp9(4I-2s$*mt?6{<8GO>3_Ma@Jx~C z?xUHrP`bLrGvF8hVoHNgCNYFuj$!;d#_PnL2C<$?Ax;uHqGOE=aP6Sz1ne3oFE1oA z^uYY^AOR8j*--2SiCk`(6ymobG;>$Sofj`{RQL|Cw_PhOj_*{k`}T;W7s~7IZYHK% zUR@;DuWw+XnaUZ(;LA;!ST)iOx~)pvd@Sad6mVQ#C{MQIP7XUbf1N31sLRP-ttcxk zogvpKH15z%)WX+HA>#L4Q}uoN=YXUhogI4Bc%cEk1LScxG6Pux*K_R!IQ6yii@{Q)jH?<*; z>lI6qfO}h>V1}T=!fl!U9@6p#K-)2yn*qmZaOw_DAN=M0p&(RCTR_)yOeY4_$(N+K zW^H>23n-#P4pYICjkn8+oW>F0hQD_bCJT}A6{eu)?uj|wNPh`R%90;@NSScv#$OcT z*xf}Z-1&9T9J0_E6@)%qW63qB3@V?f+8_D6zJ0-3Q==tD7t5E_rdKI2j?HaBgjust z+qN@{Z7_`q!~&5`ke(Tw27;?RTROU0I&Q4WLcIyxFc}CAMa8< z#QY`4lzI|UD=xJa3vDDfaq-$88p(NkH>!4N<~yocC1wd*xP;%BlW02rvqaF zl$k3)=CL+RsN*vw>}xI8x!th-zDWo)VPM26!Sqnv8hu5 zqV{gH@)A!QSBjZ}mN9(hY`V8vl?RoCu6@TjvL8lt&$(?n!&5_)))D(tJGr+ZAmmuA zXSEZTGpuw${>HB~#l#jw`7tdGRS{QZ#R<&`$m>bMORZV?`R{z23d^~1ybQrBv(ixF zQO;3Uv(7(3ClYf^7GaHA!Jw_*=eSLhnAtZo+#5GDn|JNEEt<__`(22pfa&!R={#Bd z2V}=YU3T0OpgDNou)8=Q)LZ50cp{h6`dw-Di*lKwwR3g=)uqIX-%G&^xAX(qAxf~N z(Hvys!*<&t4*xWuglz+sb%)XV1)()<40)qtva>evIlq(V$CGb99yYPsB~v;$@X(`< zG(Ju~gvl(WUaB!18ya6~v3AlOKjg8oZKmO&A)A$4`I}3E&Z2n(U!M29LFxzr`4+Cw zWei*q3P9dKDMN7WL=OG!3a`d#iK5tNYH>xZ5{eMnoq9{fS23OyT!3-go0Hcm!+_KI zEgOjt%pm6LOF9o3)Jf7`FV@9!qOvYk`DzFm5&Fqa@?w*>fovNXS2oyXiM7- z#}5#Za{b0P%PYEA7$5tb@706{=zdRC7|NZ_xbA@5XY7JvdrniTEbyzd+`=cgHzmsd zO-x12n@ihZcrr>k0?Ya>*OePlK=Qj_)xT5|*cx!sP};vG6O!4+1*x7jv%U^L97kSs z#}`ZsKe+OJX;qQpE8l8i{q>Rze(5-#^hz(dAuZ?*aSBw&G*$eE@=cOYY|yt7-AeJE6lO8euit`fKrSqU&)b}7_{+X6YgTWp z*96$Ij*o{KRHFne6n)`k;t&e!5Qv^S6otK#gx=gi`O~3s2*AuPOnmgDus^YF)6xM* znwRObt+an9D}T^sn{P6g={0WK&bEj!@oi3!X5a6kxWqxOA?sk5hlzRb$8H1803*zs z_gmYem`gdEW9T>2ee%BhtBXlYl1Qa%w56U{zn=M zH%zSHK#p$(d5@&p3gSQSeF>*hOJm6UcUHq{3gt3QfGdtQG9E^*zfu5NK_W`ktA1a; z7+dK{?#-Vv2bKS+D z4G(a!zteO>o5{FM?D{s15mORaX*49AfAwS4PfV$y9D|kKviiT>eWPjKbrKgV29b8L z!6I7vJXFm>ZXc3DDBJ2@8vRz7pcigDon@~t^puFJHdc0J&vnn3@tfe&m>U`UiHm72 z=_6OFGM^m3^zNr7iU3OBTd|c?UKmblJrYr6jIdFXx?9OC7K(AB`H*}?bpEOIw)}%^ zG~{i{E|En^zXF`2#WNU;AU-VQHbitU@cPnDLeIswH&xvvgwE?_pKpnrzKI)DZU}t+ zfbMHjNEa6Lq?^Q*G*KG!Wolq}#b_nH7 zjAniOjECt<-TauH0+YB6dY+|^Nrwyb&iGleS#|m|cJf9xG`^_v{W9=+Me|w~JF6hp zITQ3(34bX^kfKn=KXaxr#Kzxqx?2!XDzIM!^@Tbu_2#OC+3w?W9}ynPq^TrEkG$Le z-IdI&_${GcXvk8UaR+PTukTc~eA)%hu!VXD0x#7g(fY+1@{Kdda8Z;$=f1z{4 z=eM;-4M=NOSQK;4v-z46sYbR}pL{FmhK6EF&E<&^&9WBf-A=<>|H$3}<&cOFOaFdO z#?f+Tb5B@9Zr!={GMP?CGQS^L+_;KK_s~IUpr*o4Uy`oL!a<@FZfjv|%p=U)^CLJ@ zmbV4B5eTwjazfm)Iqa64BbU;_f${~lBAUWE2Q;R%>iZ!=4kMP6{e(J!D3jpQaJ_%y zfQ-r<*q9vG+jcT;8Ycab75;U9SA3Vd^BT*h+j>35-G(YH>Ts(~3**8LNX)9Z=e{+*_O&{>J<3uJog664KlOLx1Q*(v zx1p_EHN%wybT(IP8j*WMp)squHV7tsls}f2$cm?xC&iGrmm!Qs%j+&cG$doJ`ea4C z_TM)|6yE;nF!noE0`3pkrf<(AvVbiLEMZ@WRQ{hLh@-8{Imc;Zn+FzTRSmYY!%}4AX9nNlX)ru7 z*TxF2up5-0mdoxOk9_r(00K|)T;TRy<^I3bC0HGn?H0WrbLC0B^p_3v4_Ey6bEGE1 zq{L#1eoS7sGVY!12?5+8q75<0nKV6{*%mBl(gA;2cGxgalzB%Q5&6TJp$dE{R7{W+ zxz@3IU12)DWQ#|6N3344x8nw$t-N8kCooLa36Dkl4`ozfr-)Lx=G}6Yr&GXS!)TSX z?B+3$Kmegs3i%$QhS-_TEX*V-hD>IXHX9k4uaz=a8XeyT)Upki>$S5m1}0Fw@*6MF ztas&Wt`w=$=Vpcn+o-pB*E0e^OQjmJSSq{esXHfF`)+Yb-CVuvtNy4f40X}P) z$j$nFu9nH~UEM)JM3e$o|7a!JsA%N_zgLX~NFLmFKqcAyH{^h4;W*cZTSSIl2Re{1 zYoF-Wy#9i!EiYYpYFZ%SYV?y^%(PI=KUaSNps#MIu0}I^Q{NRrr!`G;MGsbVv>`4> z$tqJcxL;(eto>9*(yK6e;0j#CD_fu5(XjQrZ`mzDM;(v(Jk(^9vO&Nzl-ts~AMr zeY&2?=L7rV=>7INJ@_{}Z824foLyHwCjvSisYd$7Jq(A#2 zMk@FneXRY@sl9~#+%McC_Inlu1|rw%a_0`E(>CR7C$M3UN*Om=J&da;cSTx(s?+nF zBYV71i>HrGP9Ac}5A#vnWise<>GeqEO+WoC!<4%nAOxApV#PbK0@(+P&*(cM^P4kt z>i9L>UO3)y6A>(o8ylWtfXMX7CjGqcRMw8n&O{zOR~@-(??|V@1*Zb+kg(EBfd`Jf zG&3;+h&}rdTD|TUY0^>^p264xT%36glP7_vk2d@MRXO zqiiLDcjyrMB*=DqiCS0Bv><%;_5{NYThkFchIPV3fP67794HIM#?GSC0?HV|~p1yJ=?=zB)}mGt?2@2Y~}qvjTqyGQ0g*9@@@)U?Pjr#SNEs zmXdbb<^6o4k?ThsxE2)!UdYuJV03PVOCk?4)6W+a8#^;6o^>NKn%0brW^eeh2Ab~- zUeUwH1l{R$G)sh^A+yZT4|I)3oTKoN?Su{aa=g)z5S&pns%OtjI7D`3WoD(oq2T(} z+Y}=um7k}^X((P~n%E=yULU$pP%rB?I>$oh{ENYyA)fw$llq@cqWK!8gL#zC>xL}L z3cA2(n~EY8N<&xp%~$tE8KrvT!hI2Gvxx+W3!LZ2ciqnmgS+}tNFlh1f7CeM&;v#U zM5Z^iMq#9Ue2^f8FE~qXq?Pb#3p58EF>zU@e|HuowV!VG(pb(?^!QY8Bf3{cH>REuU$E?b2(DUENZNYZQ z-h0ON;+lu==h_?LVxFGKE1&%xvRiL@!&RNL#uP9^wny)wH73z&!VfML2BWNu8yIpj$+1G!+SP$q^ad9b2b?J`leu(p)5dTuNmYw0g4Yr)j6Z|L zo5$?Nk;g&n4B=GMRP^n8(0$zygO&H29p9UILs}vgbfC(2X+v0_Q3AvNrc>(0Qll}W z18|Y@q{pZaFa4X~_Xh*?inUYT%zJii)cOi*r4;}}KJo6r&9ew{>{kHRspS9tATjdM zg)Vk`o12{VUvcpqt{7&AXYP~OONmb<+`Ixt>?wS5;aF?}64XGxI{lu`?*YlR?>YE7 zwFci`?c65mguaCrx=tTNb@n;5SeG!(a0um~>kJ^CgonjNHwKOf4)C6Bj`0PhZK}{a zY~GQF>U;{V*n>ArgT&QMQ@Y@OkMH-P zoTbt&2yFikC2H@+Re{Gat%^eVj$~na4)SubE`Ko7xaKwVrL>!z04D}KF;jxG!3fE# z-Fihbb9&v@Yo6QU{WE}J^1|PF!nkq#pK^|}`cCxnzIzqkYnCDO2N*Y9^%x&quQJLb ziRU$KbqR!g$MZRGFPwe5qV^YY(W+%xJzh8cSkVLC&4n0`bXW`;q{d7{c@854qXxf7 zuk&4bepJ832YdmK&-S?6g<2s72t2+G`Nhjnzl9emLV%|*KkGjKIbm(!Y>PVKpc~t* zXsSP~^;`0(c5*eGZRleK;$|lG1A1yX$HGmYs8)V$EhlvWApY?ti==+nx?RCjBGC0( zA5d(Xn=L9^zHR(c@`Jwl96l}C>VPB)Ig)G+9f&(p`umafy5P%yC~7d8@yqb;XK@ea zH$Q*WJTsNK^OO-XC_r<)hE11Vt5E#)TM5ADBIw_OQ^p)k2aZb^^dl>HO%UiBuuIW# zc8(NL+q_7@@V!zZYo8Jvm{h%;dja0>(>hohN;DY^Dk=6KfMdcMW6InK`nNJ zc(JrX=V)A6Q9Hesi%foG5!tJ)-ZQ-Z_#MJUEQdDoGjXoTK; z3_aQjF@}FN*-}Nc)SniZEDTC}2>V>u34Pop&=ztW^ddL#X#Drn4txDDm&sifNXjex z9AY>;@*j#8^7oS0qrQHM9>y$J{S8MfQQyWrl&yLH@7Ck`L1u_MaDk`yH-Tl!se@q` zlHC50^p4B7X4*Csz1Diz1Otw&M32%+4Qjpa$t}{8tXpu&!;WOmP@dk!eyKSZ@CB*k z_wI=03^$Ux+7e5OZ6S%(gP$L5J~@n1J14tg3>gOA0s>DVD}>~sV5UkU9CNBWC?^Jw zzqq7CP1PlZmd3t>GO^#>k2ZMQl}>Etnq;^G`8W#8Z@o8{6$3>tUXYq{ z72|5>{3%A57q7Eo#3Jk2EOp%Yw&c)N;Z;#zV{%Ep8~qIj>ItcijsmOfO1WHe;AdOT z>hdTAHX;>~TCsjopa%=hs&6%Ed%t16vGJg#7F9BGVUR*u6n1Ybx8S1`G=7lC?N7Pu z)gS`u$g!K#{4KgV!OJQ2Gl@m~XGP?v_3?Hb!hyxL!_Fj@k7DuC7^zKH!%09wa%OAc z#18wj1&AtFGPk3;&xs&>rhi=v1GG_!~HtPXCgZ;UaSjG-DpfZX?lWu+U5xK27}P|AJz^3aLLhKs69!J5yT{ zT$50($KMok`ufPuWKCg@BFs@%JViXK6-jtnXby44Kq*_>+FpVHUURVVX3Egbfo5V- zgPItPU+gIuF^)5BWaV2p&4Jb(`=q}qs4^EsaoUd;O>qB>ad`)xVv!BOG!h%Rdnt5a zmq6x-jvs5X$CCe1%>7=pWQcQ09AKi3rn}XD!m)?%pP0mEJwV{ka~pz}+2Oq&5j>hH z8a(nEYAumj1plGHYD_wS4*H$U-Zg~o{-kkhp-Ed;k39Y;JrB$Cg_7j zQ6?&^ms9)J8w69VcDEgEyyFFL2!8P5(%_KiL&QkbUCvp>(1vl*p}A0TNzOgUB9*fDd-Pd{ zkD6#%71}oLieVc+P!2aJR>#(i4t98d9a@NkBwUfrb};CVmzh<}eSjU;Yii17_e2-> z_qPN#EF{l+qDefu+-pt^;JqS{OCZ{>I`D{tmgdshjNA5Fd|C+z;deKM>jxfk8b*0M z58&VCJt9$T+SwC&y1}H!R#wvbNp-dPAHA;SA0-B6xFA#!$_brK0}B0)3tV#oA#S!t zQ0`w?nOWSdJhUmO82DHyNg8Ttba>O>%eE2kVLNb>8H?1y97-cVmVHEfeQu)6eMI#fcU z$-Y>y5jvystZRl#3wO(S_3YmnI`rjt?Io~&azZ}Ad&JB&SFWd3l%^@z-S*N~0^F*H z5=(8IW<3o4TLKu*HXWe$T#vbX<+_K+wy&=}BGm_9E!N;jn>l&!6&?dlIif;g*{Edx z=8Z|Yc`-@yF?{b6Y7%7?7Y(sHq^*Rc)Wj&98>F3p`))t!$HtJAAP}NHKrDH*53owf zg{eE)=6c=8{JFY1L5%B-khO-Qnpd*1{=e;LmPpc&3RQtbkdQRXfmzVq!A&a$xG*%oZXR<;nMoUb18xEWZ{j5~+ti zgswI-eIsP-xYehsy#kq9)!kpD}C%%Vm+a>H)SEBgf)0owC()iqsWvyd$s+$~b zk&WX&JDv#6`D4m8RoZt(E*ohDzp-{CUZf^bxnl~jCr`Mr{WMN-bV!wT9bhMxoL&?UFZ{=*l8Q4H7g#3Q{&J#=AnD z7kTjB@rd-qz}>%>Q$`dXTJRem7l4+7cDyT0A5PhCrhmkqsQSCO73dtRn6vO(+eiuQ z)PtmpFNVbVp77v$m$^l7injdB0_3zq88)W+A`N!+B>f6${CILO$EOsO1RK8UE1lbT zZsat2hkn;?j99uC)eM*qJMdFm7aW{z`kcPNZr`@Zs2dAzka9>_`|dt^JdID_V0>*U zy`A+=+qbCVgQ&?Vn8w)Acp#g<3VB%Xv@Ebp3}e&Os5AZbM(S@bDy{CJzCG2ut!72$ z@=i-MjhRd4&>2C0$r)q&4#1ZsE<^or+l68L-9U*3Qq-2Apx!NAzWwx)lZ&u6VERDY*TThX7C!7P_{3sQIbUfg<_G#M98 z->%4=TrzeB2Tz6~M!}-bPKN5xosW}m1r%)1X8l8!p?j9XLf?7A4+AUiFASYzRjzQNLCAk# zQo?xQLh~d*tzAGz)`}O2W~+i<1{&Sv)7FT0&e@aV7>Wy!-vAg!qY#e}3;!0Q1v=Pl zT5V9bZ2<+#OZSyq!4|1=L7e#2F$rctD9U;E1IXRz#76HE*aL z=h|3g@fOdx6HeK}#kK*94PumPR%5b|Yu&$NLc#=ahmG}3cbh%nyb57>_3?ZNk}k7y z{yP44{9duzCQF$NQCJ=l;t28waPj0rb#At}iWSaWwXX{@Lo6*=d3ZXD*HzouB)jN2 zZ--0%L*cXn&W5=DCo4|I;oKa@R#G%H6)}o?csoF|w+(5Awap5Y! za6H>PiO?cO)nH3Y&~N|5*SF;U$_}M-{DoU5l`YibJR4*>xT{!SM930v=Q@FVV<_piAg1uf=gH!e%N41pXnD z(~JMc9vY4*hf!TB6(sk9S|4atAMS}kmxodnEE9L*9NH%q`>$_rn|CL->_lvwioOV0Mt0-xhbRZz+Sgf9lEo}FMXks3gQ1XlWatwYKPa? z$?!F}OI;l_FMV!4$lyYy2}}fhPIx=YP)^Qc;@j@f+%}-+`P#qURG!{#qgkFm)C-pQ zt?|)>!|vF|XYV9{GT%bkOr=w)FOARTnRUfO*5VSM+a%Ozr9~C=~pH1WEdKx7uwgT z0*4;aiRJ$I*>4WhFZ7UzAl)`)TA4S7zRArR!`tWt;0uK_4Z16?)weUG^P7M2NyN2C z9gqi6X<|D?#{RN!9hGZsagKcrVC4N2X6)nZUCh1 z5m;n(x8>#7qOB;+*OoxM{>lpn;9btBxR|Y%0(D2+ytexShgQQs1^q24y1j27VU6om zpN4{&9=U2l`2ULD44dL~{%A7;qI|T*VfaGwa#HdLEmQlBrj3eXT zMb#%;oY24P1`fpO#&N#(l9zN(fuSo@*hSA2V_z*e8A{KkA;a z@MvbfYJVSvThWI&eg5pLj2vCy>}`UAIUH~CwloJN(w#l+*n5k@%MKJJDk)xfn6|)) zusm!^b_Kz_ush`bKu*w(9c9zODOsQSuan|HVS9Hh(MZZ7mf+|K6b|Jvx+eern!`u- zm$&~yJ_3Sa-N93`NdWj;hsn8UZxzjJMEhcBDTrtPmQwU%eg>_E-RgMie ze)SyvwV1Y1OIXe;$&byO!U?S0PLpv%Yus?69$>AJku|%ZN}k!+$eB0My7EF7#ON+k!Fw+8RL9dqq?(zSJyV2G2nWV#8IXPw zNKV54GH5m3|pPfo*r#MU}HRn5i7{vzZLHp}Dh*zGU%CXt^(ep`EA6>QurAI9>94 zV0~rjVX)9NZ{nsF(ts^<5QzQ~?F^$%Yw~9fc!iDR-~~U05a-8UxURWJ|G=Wlb)2)R z8}{d%kWA`$*I0Ht6URfQKkjcH82*x$^RSN6`1T0NM%n9?J{vn1*ue-pj{2jV3jg%f z6jmwnZ^jTpHc2pKg#J|V5V@v?QP20hMG2oe1LcBL5sAPxbh4^Y(%j$Jm1p6E*(*tG z@HHPXn%BVS~9=@j1eVd~-)92;nLCTY~%0f3DpiO$Kt3H=*1>5nk(79VLiVl|X#;z%#sl9IzR zNVm^UBt@$J;~dszT_IWY?~q+&;}sqd1|}o^n?FRFt=U8%%7JG zrP)-;?^s)7Wb%CpN#6e-075~%zLNJXn6YpQ=kI+BsDI8R{$ksCeZMeek4kL@D|2}~ zkEq4U+T15F@|E~l6`?|fxr%HFrYuHip7dAc2jzdAbm=rt&hN=PX|>-%=38c&O_Ey0 zKOQo`%W&%T0jbESP)I7rrZCCA&6CB(DDo^vS^of>v-1|AV{_!qQ_H?ln@5W3c9PTd zX#p-6v~ozUj6N~^>ORn~Kr-3ql(#Jy^l`_?yzBD6^78xhlTwe${zf*duT31YTiM)P zG8y54L6St3lqoCz`#%=Ng+^oZZ=ARVmRtFq`6;dbMw?5I&4#vtua-x)w6M8JE+i4q z7HVxARWvR^-(?1wGZP+cFy|J0Gx6BxSP#zYu-rI{I#atrlOi}px5^a zbvZ=>H<=VWFD2zpB}G^flf$l{Kn${JBQg(H!rpoO-?{w6)dsibEgweH=VxPZ`c1FY z#ly(Nywe)7l1lWc1Gjvvv*JGQ@_fg$>hef{)4y9*t&e0}-?qRC__lc-1 zegn8)9DzI~vxAI#-s^q;069(h%9=&p@0k3%r#^+KmAbmQz4F7QtlZ5KM{*P}KeF}t z9I{%DJ&RxDA>Lmx`FGLtUZk2^&ue1$mr+A+$T!u}TZsayy+J5|uqxC%dUndWw~@jh zNB(4g&M5i6@|#AN&3=8q(je1ekV30#aA%%LSnQFY1Ae5ELa5!cQi+JOZZtCqnhz%Y zyz`%%7hQ|Xzmk#O!>ixSf(vUq$pqI82rRt!NSJ|BLI|eW2<0)|%J2lm7GL@MuYPQ4 zf1vb#`N$m(D+%r3m}#=yTf~=hMbG2sHM^fsAz?*ewD8|2EZ!o+0K_OMeoX#AYu}z` z;@8MG+G6S!w&`;u7c&(t8#^E=N}APvC2AD~N$Y?yohCe5)HE%BY)6Sk()=jUPzb|zr zwS6R8o=I%en2eISAzs==9JU*78itjev2eA+DI^Z?oB2EP@5mpSo=4TZ(Pw$B=zf3l z?Sz`7^0Fe>Lo#d<)rhR|$xw`yEVcN+6vG@qi(@>pjHqr8*!k``6U-lct;7MxJ*~;9t4LxbekNmXT z9)e&uBkat(9q4c+?|<`+dex_szcl=%=5>@^=$DsG1UFG0JkoVBQir3fFb^AUr|8LJ zH7}b+qv(}=hL)>r@$!&3V*LJrS_1Z>-+v7lL z%GISgQ^6wLTA-&S>(8T zb=`zk+yx{fZ;iOA+>_i6)W$`QeL4O=8`Eb2bTAO28j z_c!{5-Mfc|IUs;Wv3j)#{8liG;FW1v)oK)+*>(n$L9*1;aHz@8OaNRO zgEL7V=KlbdJh!HKW6Spvd3Jv-Yq!#+#+@?Gmon>`F-0?9T&j|gT&obufPnn=6xngk zG0^pAhas0YmVSKsH%9UYo-aJJo$Cuq7m%lFFbH{jltr>y*i@t;Qi2o~3z28)UtEim$oyeAf)4Z^*@cj8yO*)vJf0=zB(jcUX>%$g$T1*`F#!_NG-?8ly=%5u7zo-kPL6Am@!CZ5Iw5xviiJ_t ziRcDfh+ihWz(;av=(b){ODh?C!F4o#g^EXUaH=YlcM7UoyBh2VQ`ArMY4SplK zeJ)GH)of!^CB6DD3X1XE4#&1zj$~|!fKJ;y`}68nl6?d)JQfSEB(BAo)}!VC-#8y^ zWpjtPy-%}|^vUzIjl|Zy0nRz-i`>8G6j>MZA4wB3qWwcq1DA4Q`#(IE5$gCgXZn6G zF8tJ%y3CQS3a!?m#Q4_bx6RIrk#S}jpX6IJ9ai471JQmyB$7J*tn2-rKB+wSZH=P# zo9MX`5}d%TE4TYu)K8P4t=?yAZz5b>t>n)&*Af`kiC#nO4!{GL1|)NGO!&3}o@3_S zdri^*0MYNJ272&llj4zUxFmKNpzS`>!>07i@7>SrcNz}P%b(Q|w|V68yX%`RVsiR( z0LrEKNVG3b!|2Xz>hb57p!_4bUu_Jh&cDEH!E582#Mn+;?9I!`K6}Sj_ zmEXNTj#DYpcrCZoV`E3;K3Pol@QI^rh60V#r)#+u-o_@9L))b??LMGqH5+Qp4gqp3 z_Rq-Lt6xK=TtnzdHz(#O-@9Ge!SCQU>zgckS;*6^$*q6{^RK_T?3S7wzCgMs17R4JrqRT=Y!_bCVb{1RCDnKRz)D5C}EYazXjWPql*1+fr+5 zTU|2N>Jbgil2%{=_=}VuWPOvlt$Ai?J8a_9BJ-LFG%MA3`7nq%KHPz?u=n@PUvC@I zPu%79UfHAXeB{!J3EP6PJXLxCPfhy{ndF0$=m0duR0`EckIxEe5g9`ufnKr-5~JcY zK0X+&pPwmA*8f{PNP|2p-&2#D8FlMugNd$7q zU74c?fv58kw_I%;BbsXrgUQxUKA}6@UxaIwwrO5Vdti4`%U(Q*_=3`;{7f(sYMBFN ziRn6Z&Z8`MI;@l2QbR4Ji^$HAyLFVMO7kah0Qg5-2;l*oU+QPdu}ZL9%N5PQF;65i zGP4HQ!UB=XpwOOxR|66+n+?+KE$unq$O_9X7C4ed2^#bY6l~0T6GBfxwn`?sGACwW zV2??Q>)MoVuNUuPf^JJ3XZhMT+P)i9;gKhs5k-zHR~p>OdwP;OJ93I96=@r@$UovM z)4oNLeSN6KqC(Llm%L*~G4DcpMxHI$u-J6PQ1(_IqeAOC+N<8O*52Ey#;2ig<++Fw}v55a$BaUIc;87`naRE#F-C=^cYZ_jYt^{#hd~a z9}Hr($C1(;YiRJrS zp}YFg!89QdJt(|L6hOeTfwAeBbD0(gQr%ozvk%BG&b=E(@-)6n^A@zW(aCvpIf6@o zkaB4`hM^+6cl+}ecG(E-%Jq-U{{YMQSjRt_bhJ{mC@vI}^a67L;*l<7qzFrYHa|Wh z{K4`Du`iMgx|f!0&Y2YQaFHz~p4))JApU#^dKhMx=cT$@PwCl9E zwrjTx5beism{~N?HuyQZx{*4nvl{RhtD@Sp~h*~=Ez_z_V1Fv=O$+JrjzCG z%DXLk4HHPywD_Qk;^tFsN?Jy!qDdk=ox+YGR4Ce}r!cbt15Eh%z%pU~0Gu90(0uK6 zbLU?$dG0NK<{LMP*4brwCmx!!fCCS)TJGI5FHS~NO?f7Hzb-uIuG-n@cMz#jF+!uD zA&*b!aMf(v7tY$-YI>cvp9So)T-sS#A&MZyk_2)~ZP9r)=fw5OWw~z~a#7GFYdLwx zL~&3)N45?WNZZzC^F+50t)!%gQ~|`&yLge;Bgud))AIiIJGn2Ux~p+mf~pO=Z!pTK3ZeOJIEcRMPCo+N_ZTqP;3<^(7r_c-SSW7RAWxl zuA1GNK{wRF3s+G<1xVk1^d~E|BALz5xYAa8OPGpAuCpIoa#yd~2YU9&gji>OQnawM z)TVtXJeQJbvfYxb#wg=hn6i`8mrl6#K`+f8Cr<06Ld#RlSGx?MSlTlrf}4W!GqP{DLy=kIFF@6A zf5iIQYBv`G{s}GlysIy$fG8v?0kWvtfobA*!Wcb6%szkA@BaWMJm=+GtJyB}&(U%N zZ9Kww<8Eltyj+Q7V1Jf^xMLmAHhz0t>Gob?w6%s$t!cN`awL7K;a~H9D(Y@ zn)qQYmt5IYf1cl%Kb5*wyk23kvDdt}X5NSC7)j*etLdXuheEWb;*=jwLYWGa(|m{d z{p8Qh3GK9>FukRgp(B7~xnhxUUBYuCl@CqmJ@PzE%qjHNlXN`4dvkZAM+BO6;U+lk zR;mCUsZy#J;vO~0HAp<4^RrjfEc~gcK{L$IL33v|mlU!W7Hq_pXaj$AAAUh8P)%^w z$OCuAP;0k0AUx8AB-9Q@l>Y#4D&TFjXRUoJDkF1KwFB++8q*{o#L1E9o^jVagRVj6 zPb1u$9cxV?VU#&!e(fBKUye8E%lB`BSnN_n_kR9=(CX-a@}WQIVko~^`oGowr_bX3 zBmLi@4blwN6`lRu*(zkh|f ztAKxG_r*5A{O(1yo|+{}(pl;VuE9psJqLVM=lW1dZfMB9ok;?l^zg#6eOLLHFoQ_^ zzMAq6QGY`-v_#KHVj_Y1$zpCI3BcHU>VwDV@1wvoXURyLQ= z{ZJ%JLV`0&t8dD^ay~T#3{tL-m%QDs+G<+vrREds6ZQgHlscMTeGv8eXtpW9%(0B?SnF8DbQnp57WN>*_rI?ay<5Pwyr>1Eh za`R21EH=9KsSGFw1xvXUDDa>;b+pPLvSH?3M^&2I5C@gBB z`_PP(W=7~R52o}F`N+)+%6HcK_mh7te7mG-)~2?X>34YV1eBnXjMQ!SDn$-o`J+_g z{#f0ypUT}!%(Ln`xA=2SxAPvU=7^-TytZd$V)qjneL=@%tM%pZ)3~K`97Bo8l*C5w zRP)c7{{ZJB(^RmM9Uo27F6=aa&^&be%T{?KR`^=JEr-YG(WvMD^aQG4A#Ab;W zlqZ(I=P7k2h8yiJTcPUO%$Bn1_T)(=qVcz8jT{ze$4}Znx62>P2=YkH7Fj>#$LHVX z3*O#-YWZO`UUv|y8*NhF8RL~06-oj^sbv)bDoCbR!PS=>OBT>S=Ob>srEb1kzR>NY zHkzKNHTAPeB1b8>Qxul(AME-@v~It7IkCm4F%;qC(uo^J=pXZwR=P%s7KwG`%Q^L{ z8yk%;PSp8G(p%bG0wfIzo)Q(Q-G=!o>m*vvkQ1?Ym_I!3H9sUx`Fm^S{Xg`z?UXuX z{$qikl=^f}>Lh-c*hx?UB!CC(Mu?={{WY2j*XwhLfae zX7Wunt)W+2nI>Ft#r+<Z&e5?!zY@wpq42H|E*?mfLFWDK{FAi&z4IoG zrf6F2o|^Y^!wZj6>HTQhIG5t(G=@el>~;-L@^TW$OBmw=qw|ygb7~>v{{YPmQ}VaV z7uQxkTKyTPUN)WesanBSG zHBT>#IVXzFX(jaIkz_zv1z@Dmo}iBXcgKv5MTDX`)AgbM03-hZEj8^X<5bf8zhJT? za{zft3Ob=6R5&WY(9~`^j0YhdQ;b>V_x`u@XQ}yvUGss0^UV5{=BqRaVTN1VhntLb zuM}n`icj8hLdz?pPO;^Ecgs>+LFQd5_fDGbHI~_KV0g^PPRx}b5IwTP5*YCbb!L7^ z{Fn2e=0(ixlERp4?yCqxWD?@yOfc-}R8UM#FC3hlKp(`7x& z{&C|>wby?zJhh=}s~g$g>QN-?I;%z@A8fE~x>Snyp~>O;nlqiAnSK8NIkkDB+~0YB z%fFYtOSjW(@2@SP^)&Mt z$ev1j)@2GCOB5jZ1!2F1dgO+nmHdeBFS4co0GwUcKR8oh(mcCuqN+`GE}5nN zkGMlTVZA8`mE(FTuGJOl-LlE*!4(w4P9e$jC;a8-{NhiRKj#~CT`ynqznHGIOU*|2 z>f+AzA!!y8jNYO=d}x4$UDx8S#<`E;ne%dXr_W!Jo=4DsF}%$WmAu<~ai?3$6w)N{ zKrTgN3V4{yDIu%bff)%JVNcWvf9Du~C_g6!hvpZSwVSrPj&+G`HAY*TM{+(PHK~Z6 zJ$58hpl3K=Lor_}xGa z$6^l0!|u#ZZgX%FB9TvDS%K}?VWn(;DXI4-ag8fP^k%2hIst-}+YQfswg(L=s?gGc zgU1zb!;fEaineG?0HD}ZeymlZ5Bcqis;p`Ol2+pw6(ze5o+|Yp$&WetN64OHUpRhn zS;u$fNUfeDX(S%IOCwW&3IX8en=u;>xlU`Xn=uXdV?UW+oVq5r=Bu4|%9a+B`C{hM zI0l(%16rgL0$9Hl0P~?$E(BYdfBDHD%YVx6 zC+hlN<|egwr1_rWV7AbU2e^h?WeNkVh^z#FRZlW1DX}|>BuFjMhQ2-mh-wE+wgl4|L7n+-&q4EcnRfO!w)T4MtW4jdZ;_Ts zK>q-id4VYGPTUU`_Bmrsn3tUBT8^dVd*OelDj86oQ9NA2k=>EH(Dpw(1a~tuUu}8+ z0RD38LDv5OB_jN;eRlfi&e!Fn)HLB7%N4PCL1bxWs_;;ulY=(x+on+~wD5<<^ZCJb zOPF;%Ldq6E0C%=T1giWXxaiH?otWjIqM3H1qWwTxd80^ceM3sPguKEUkr6cpDWj8h zWA}FlCCycQiTRta{#U%y=_cmh#<3YhZ^CuA7YQL~m=Vd=hlp>0ih>Re`Y#AP-$(xd z&Q*WTT`jCiBZ0w3b&qM2kial%(*;J{ImM z!^3<^y?@Fd^O73xmUW*iubN}kH9soo&jZb8r(Fn|NUhzBW#f?gPb!k2F$0pIuKVO= zl2ulL0d|#se*XZ@L}}lhK7P3K{{WV3uJpSryF{~f)TNF|=X%xTm_-NP=>9)CER5hB1zqzJR$?q`9Am0_qzV2sCkC>)w(yDjn&+yX*tTm zc?*K_AB&v`spw8lJ8aHDI`fZ|t~4=YuBnvRYPRC)(o@Mv@gEmbhq(GO!WzLt=|7sD za`L^LcAiDPySKTHcl6RL#HeztbT;EClYJbjSd3(&i zly?6B^N&7I)AfrP?X9$wyKPMo)$XlbUUIL^iXxS)TtG4dLqV0q9;W{u488lJ{Pl$B(JwE(UcTfDw`K#xR zTJdc)32ra69X9gb@grNI9B>GgIV2DYMvNmISBinXci#kws#t&xy>I?h8#(k^tSl?~pZaT%8AIO3s_FWtt`^iVq*SA3@&ICpG2ys`8dwVy91nPG+6 z?kOMZM6v`n;c6t0eb|sgDHYnIu2@>h-Hmx;&D!UcqrTO=qjx=x{8rR5+f3=|KpT*b zK(qw|5Jh)hqYQTBg8?pYbNq$>0Gy?d@-xhu&znCvJee1oq}8pWQ#5z=nih^;Y~;wU zt}xJnapZdJ@2Q z04V4-!yS-D%xlehYxzq50R0Yd_R^`E-atOwe5vs%6$ffINq|t3&fafzi$wCR!y8w# z5k0iml88ic$?%{`@nj6uRU(VqCB}IqLOjdr-}%Si`Ocj;{&DB>?r+PzU&%1*I@Y5- z&B@gb<40+5(l*I7Tnql|?0}|>0E!`SMqL=ap${h=`AFQU)PdYiDH0D zB#i8WwQ5kBR;1IvT*wB)QAuH&PfQENWAjIwq_V&BRoqW)Jl=@9^&RerUP`LPi3+3bQv`{ZG>FDLp7Hsa{{T7T`KRaa zFW-Jr{$XEf^Jx=^t*&IX)1iWSQWC7Cqy&&p1+M_L0-FPr2r}5b`^{P$(Aik)?9f~- z#Aqd0oRbrE0zd@^F-^yMjL5B;k_Gc8m@J|e-cz_X5>GIQ!k0575~)-6%CM zt{wZ(U=KCAFuc@azp~ZJ3y4yJI4ZElg(@gM(eWhYL}`=lFF$|IYWZW&ACtN_{NwkQ z7gV{`F8=^VMXF7#60tySJup($#Er=+l>miMJ69-%IyRCvd}*lJohtI;(s!s%JMs*Y zM!*%Xb5Xys`DRNLqgB`Z(|r}-hfzncw%C1R)RJUSio`8X4eLR+{qdE{nt%rM_5T3M zugz^6@+Zz-U;NY7Y_4?}G|8oTZ6TdvmCVpGDOn%kRt33sJ8VIwLP4BGv)|88`N&N- z{&JI3e=+HiYBmvas#>)8nz;x@iy2tv@h>HLi(c}7 znsje7ep*c9%+`99vuVaUk6qqH0x1v>S~*wYbgc+JIgu7J0z-G(x4)QrSCKz4yv^oc z%+D;xsrmBHS~`ub&7I3d1-788Qyh^!OTesDg(sMy6*+VW1;dszDA0LkoB4-hb>(k8 zY1++%_x@}1McfywsoOYPTX~?6%D-4Z2{Am3RIO=Flwn+v%1a{(Aao3$QvB2MSDXI; zEwoQ5Y1(GHrRzRi68e_WUqZI9YExFXGay3qB!JL#Rzphi82GW_;b1UGOq<#B!l2e* z7j~TV{a(PVvc!$a?VR+MB7WQsb|bJnTQT`LsgbmQG1*+pJ&6*)0^h?NY+!YL)@WQ* z0MxGv@U&)WiD_hGSEM2f|Us1i_w|bFJg%pVPjs@))>t71i$xL)u zV=_EbdA)|I<_$;4)A<`o((Y#R<&Lg3tJ~;OSBWMOdT6pR91sq*>slO~Cn}&8aU55B zs(IVa`q$)$=3y%4-NTzw~%)qd&`ZGI7;A%dvf;;lX2l#O#r%Q>& zLELUXj(ShC{{Y<|d&qXl{pZ0x)o95oFsUfwqq!qDQVzHD&2Y><7#J=cGi}7b5SN& zR7>bxm8p#JSdR@|fyt8UeovCcB-3ZVd�a6^LOPGWGQ9+Phb3_-6kAA7;xGeNwab z2T>l?86*ge544XqC#h+w^o}Lqs-afCBdI?;qb3V;aO!&VN}oySiOQV;=xdnr!ay!a z)c2)2W}S1YUVe>93OFa5F*F=a4rw&;$)6_xCCts1IHSfx*gUP|YhO`+Nw3ya5L^;P zMR)moXIZ7thzcgl&gwf(Qa+uY$>k3&+xc)bk)pE7?j+*7G;OyUAM$f^gG@2}T~?=1 za-G<}o_{LsZ*+ZEU($68q?Xt<=(CkXcD|CG)dhBCQ}CYW;qEg@+g+8#jLb;b-mlY6 z)3bX|)*-?-+lX`cqkka0i(zr4Mdth4o5^lg<;)ha&FMgeC@SDrlQ(g&E8~`XE7{Q? zW+dJ0FK?3{Xf@^};sA2rZTIf(eJ86$tJ_YRuA5^8?wWXgV}cnaVE+JZI9H7aPaN(B zN0RWuwwOt>8}IFEDm;Vo|=XJU}{Z1$RoaA5o`&0N9Wn4&W~!uh5EJB zls@t*{{Rg0?`*%khq%38v!6_#J4?jTRGRdu?c$ot%RmSy=1#!J0g7eDTZ4^D(g zYICagesz{Z$px@}uvP4tQL@>FuE10fsulR!;{{RXm{E0N^ zDcYNoa}siGhOG#zluw6#4!y(N#5|{EV7fAWO(JWTsh!UgCq98{cU1$R9ewhi%E5;oD+FIt*4g%+ zY^N<7;phkHORn_D&=r6vUPX_@0jd80KA9=PEwIlc&eGAOMoBJFYeGX6-?n3zM00Wm zqFpVC`HI%c8>r&bm`lY6uE;@7Rp_VKb@$B%w+v-5!ON?)(oTFnu6-W&LbKC~U7QV?51Bgz)MxGCbh6SxI{uJy?t z-qXW=D?Ugajh=gO{NFwKPxDg8OZ>&X{KvYsdwoAqlI$`?PH?5bATc+J2s1*4O9?8=HurE(Lgcjux~%XEgIH?JnqbtymRA3UL;>6V&y zopS}WH%$i%*=2qs>lYVCV3HQ8ufxZ_*^{5q=>y{8;XGF&ehioMzw%Dc@}Kg;!Qlka&D;i}gcagNYs$HugNJ|u99c-2Qy=KNd9TlwA)>B zYZD0NZ*g%iDQ={@=`8M~28a@|pbOgs@qq%OL`&k5Lvt)2lKSPIuM$J8=(5?YYT9bs z+z4fm)WvZ?Weh&s4xI}Tm1BtT$UV%=kBQ{@*Zy(W%eFpX{K(N^^DHr5tcK(L9!2E} zD23QY0sBW`$-0xU+c5NiPGA==Q$7fiIio)+uWdY;=RH5pI#B4ViEJmI!>qXt&mSMCt|AxaP>B z=|uxcRjoT$;@>B$1B${lvZ2CXKI)gTXn~=IQzhZ}CXzE<&fb)MC$VArvlYxzu(BFg z4O3W9*X%#h?YjC(e`x;zok_x|X(oB(Y36QIF{?5B0REU&LB7k=`9R-p_^R+KtY34< zO@Ff#Gw&e&T6wGULP_nvFLaspSGACO#wjC>P?g%H$UO&Oeeh8{kWDikTmEs|^B+Yk z7OCayxZj^13C283rCSQmu3HFY`ak{-iJD?Mh3^0UUf+jYzM={HeEa z4RCleUm88>6#oF0zHZSpXY)Uubh&hh?d3?Nj^LnYG8zLH7CeHVv_8qWY*UCBstzoZg+OD4?0L=x|Fb66-^%d~xh|tHqu3e=r8{aM~HszW`POh%i6s<;mM~Mg@oz#M>jWs`Da2;JL`7-LXT5z zDRocXUEU!)RyFweGL48Vpny#|Q06!Qk#1KP4)0|17ySE?BaJSse8+uu?Gq9tMNrRL zg;Gs-9ggQRj)p(ZWBIZ=C6@mH^X|(ybhOm^cf92cyd>o=9R+y-#Y$RTR{5b$toHr`V6{mXBEz%wt+g4q{K;C|D zeouK{Lb$TfwEI0?(c?&#Khd*GI!MF!(#>#Gf(Kv^T-nM{7h>E&iy=Jz*TNoq*8HzN zsdYb-VtBM!B8g)X#^_lN=ixh@>qDB%z+TRLEOU8QwdM$7A{{0%8&Fk>^sitKj#D|- z&CrJyEi*h{_IXZyIuX zv29=eax(K!Mz*xmqqTxs*{jmixH*2)Cu$-0GUt^F^y_lbJ=0>GTpfqJfoQdR8=5 zS_<|XWa`TfC*no6kLSHEwmL?TWq}>Ixt%C#Yqd@u65Fv<);z`MFDF`!cg$K1x>+NH zJmw@9eZOU^fP)>d)0` zEX;Qtm+f@o!*N=SvJE*lFI@9?mX^oz_s&jiR@+h3H22_;p;#aV)P?6tb7MirdQ&Zk zX)>bxvDAMteBb1u44R#-p^jAalB@Q(f!B!}`;nCrPes-Nx)6EMl}6^{{WnD z^28QCPSVoW;_f|42t~cc-BMe2asB9zZdDENawqW1a0_V6X@~y+&Q-L!f0gd<=Jg0o zOH7U2r2~^8Gk13ta)ko@WhBDG9wgTWFC|teV=TQ#v0C4O{e8U zxb(E*va*k|Kp%mi!{LN@ick4Vc?65=+wQ~R2cWP5sQ9=*8P9^Q$Ccx;qR~i z0E+&v>i+NRK9|+HQ|$8n=lb6HPl4;dChr^5@qho<`}vBy6;h5AgmH**Ujfqq6sm*< z6gz{3UKjbP`5WX9J82r6{$=vsmveH~lQ_6*Sj5WegsTStFd+A@&nuKgGmMM*DT`9N zyR;LMv56F`B8`dYPWywGN0VHFM4HUj!}Mgap;z3o>AC7@zifDs!p$_xIBxXmB8k=K zw^n{p14G|x_U&AlYa!?UX}4?33kc){GD$3kq}Pim1Fy=MRe@;nR^%R}@}cpiaIBwP zeref%&bRq;W*f<*+^1ds859lvXJMIoorw52nsd$X9$fzboItSw-HJ3WQAc5%=1oFPYk;pp&?VJmcgYOH8@#!YDZa;>EMddE=^-tqhIeGK<+8NCe9iTXZ#HV$y@V4fG>YEN?C}F}PG+Fg^zWHb(#M9&N!5~RHP&r> ztK^S7&7l5K*-xZg+1ctE7Nl0{R5#)jMrY(0@M#n}KMHai&}KGhfyuWF`1!pb^T{+@ z{eSXe-g^xg$1j&&JNR`t)x4v1 zd6Ezk2%smES8C)T^aj|*i|2nPc~49H!_fTA=e=V{(e*Q`dAnN| z?;}TVd+4V(NT6vrj(k912K#(nb8(6h5gc7c&bw4+83H*l4<>$7`76vnmsTrz<+#SF zu32gqmMuP|1UL6W-mH$2rF}GvP?c}DLObP?z$uI~ONxu-&ot>?UT?|ID*3}m(VD{i z>$f%2G1E$rDV_$Hr)-P~2Kb9SK$d{j>*?b)^moz{QMm3GNsQTFmE)MJXq@ruF?_jzWtr zAoL0J%_~RpwvnvdT0Pz7w|}TWX7x%K63HSUMgXDp45YU%$N17>TfYX1O~U-OKA znA(SyJh!Ur*Cy7|dp%A@MVwn)JdsG2=tly~st>5c;oU*rxg4ZG&~3#NC|T;Q=a2c! zCAQQxD-R@jlUmh3F0X8bo}+hs%MHku=#>d=XrW4?fS}Acx%iim2Dwi*&KeIk{Js3G z@@$`zx`*a2g!jw&f#o@3mipRR16WJyP00~bmEy_R8iw1ZZ17_e7VD*)iSV9JeUHuF zZ}YF1C)B?(JcFugo?I(st;J^)!6(z?DytJ)+%W1UWqFPQwdUOm+dt)5Lt0 zb-($^O+Qi4b=xn?KQrs6Pq@;x57M^!oObOKKrNY2#~@NspfeCZz6jGg%P{P;svGV8+;;?a-!Y4m5kV!B%y-^eial$~@+x0Na|l4o$qwgc zUg~>{F-z=CEB<~P`Kzz%6Kh^}wzRj7Rf<1K#v=?fM;IwyGcy<8uKhOK34x{?62reW zKRYkKH-*HyycaRG#MU!FX5gs;S|o^Lgex)QA%14Rv@k*h9oBoXugf1jFXh*nE&R)S zZ6)=za8Cop5k+R_VKve! zgHnOG2Wn&z(GzPytQoKKxZ_si3CSso#86 z%QA*BRZN9Qr$Q^-Z?VNyRMT#>18V#D{{ReCao(Nl(-mFcuZ2fkRZ(M(B{veVR8dk- zLG%6?ss*kCAk;5GiqbP!LI8?ZXuyD7|!4wh_8G>Nf!3& z$spFexeHXV2p&3)B~-S+NnKjmbHc$+RRUp5r0jiW!;50`S23hlRraH|sYZN074!rep0E>UkH0l5SX z!0Ys6OCZK{?=W8I7r$3%&H5!cg1;3Qb~P0Tz~JJd%ZA?RsFc_KrE?3TTg3vWD83#$ zeU|0FB{i?MO|GdWOBc1<x1<>Fp}Rti^;YB5D~9IqKMN{G!={{VJ? zPr`f;xX2bkmi}D%vhoY4ZEw}Stfa`Yv0aZ63K|{3_wd3BWEoVRqD>v>EIn!Yd_)oK zO*_-ROfX}wKP?v0Igy?Ye2S6qmJZ-=;yikcNM;MpFD@>$JD4wYsT_vnccBCPgWQ5Q zsme*B%!_+ZmhSF6$7emo#D0xZFtMz%$O{5VBs&!cwGxBw%R#oHDFbtCY$UWvswHdm zJv(|$x4slGe>EVUS(ZIC6rj-mNm=BKC|WabM;$@*;mwRG;%8f zr5F%EBvAWT1+yXVTD%u}&D&nZ6d(kQd=KzZ7L^3{J*)KO+L-d-St7NCmpV0w_snE!S~v{or;%qt@bRzNC#8E~iKL!Psx3O{^&iq4c*gR)o6t2Fleimg zlOcdCUf%LirfI3n3wCvOBy=a2Q}gUFGGQA0hU#eUQ_?qQl1<3`Ex*CPjSVuQuW#~( zs`{svr9q&n`&;F(=G7sy^sia`t?Djz;mwKi#(S4u_); z@`fn|IkndAbuBXUNYXB5(@RSY&GnQd6CAOBcRY37;3u&E09EiR1epB5liJ=v8frp1 z-dV5rbI0CzKgsUP_M>blLfhS_;i2oZdXdUKD;w#l@q^OZ=e2tyotSLf;;JH6(Mo8# z(-qTVV;#N3mGvx`^omC6VXxU^x>lcO6sxjNpj}SuZt~kqz~5N{0cHbhi*h#5mnf323 z>sl_ecXW{3`JY1aj+tf2rHz+SwVk6Wvi{sm0*Y_(e=Rc5Kx(Nxv;J~gEniRa{{ZG> zKbQ+7a$b3d%PpYCbtg9*Z5P#RalaKYf*gtpgI)6%Jb@hCjUXamKR+d@Rw={d>Ierl+Y%XI$T`GZE^ZScl6|$6!B^@{h|RB?laJP4^a$wh$I7dyUKR9 zo>R$SF#iC}zs%{poh6ESbZPhBS@peTXEKyAkO8VN02=L>J+18o@XE1Kw==VQ8X2Na zOAiaV{P^=21)dE&6R-vrV^3)MZ+?^|2eW%VXd z6?iB`MH_`sv%Wrl-GD{;pdVkqnASvxmx*8P%8t5coi@iqjy$jCl*{Hzx|riBQ?Ouz z@XdZ+)1T89B04B@Di#t?V=CTTIZ4#=58l4@>yf}tFHk%8v&aO+9$n1(KRfHCJxHar zjY!|%RVJP3@0&>WrcQ)72eWZ^ADSTkZuzR!Dz}h;HWZ0JrWtm|XbZ9OVml`Z=zeT> zTl~oLADb;dL~D1=Etzp6Mio#o9XW9Vpmm|zyY0pf_=U&@|+ z^9PcaRr1yEp$yC!;$>Gt%h9;7BDC70GBo=9nqThD$EQXbtqwg+af|c1XSQGSl0JU0 zoo-{kf=V6Ht)mLS_=N(#*_R(_HAAScbA$YYr|v&8`s2!9o<3XiHlGfqtm^jmH-K@L z8`%o7w{pF9Jx2N5X#0Nz;d79Wee-!ePh#iCG9wcq-X2%^&#&p8WYzTX<;&P_qlZsn zB#{zSGt0RgI}=Sj5IjPOFAu&fhKfymJAg;)&Uib* z9{c|QIDu@^eqm|h4L{sQrM}1g);{dB2h`K39-oT?{NA)HeC*tPQ+sr$!mBB+{^aJ< zMJll23xuJe|Wi49ZjY{@jT}#|KuhCrNa%=J*;+M_pBc*`;5%LL3 zP8|A^NY5ea%u64<;D&HFJD)br5;hH+sMr8O+qH7<&4hSmalAwTL=Ae9PvMnISO+Ud zg?!L&Ih58zw}8xl%#wF)5w1$9bck!lw9J930gRwZCG`kO(PFDpa>u?IYezu9VLj+J zx-HNF^2#NtGHei~i9Z3b-^U^{(oAhr>uh!zKg~&xh8b^_Jf*1l+fujDG~*0X&c#+s zsTL@O1$SfoE158#6IA9QyV1Wcto8i^RyV#(xca5!T#`wpE9f$A4>W4>9n^g}mxoa; zIpTq$;AO1ihF}r+>iQl0!{&Wj&f>?+I*7l7s+k47vOyXE-A@ryQ%%m^*>hj(X*cPOTi9uTKxS_~N8n)bIZQH@xet`FbB9>iV&t zLyZz5tptBqmMH$hO><9DMNioT_7$x%&lW^eP{9!^r<<;+s!gO?d0DQcZ6?-PXNKL| zlySV@-Zc+Wz))AF^vcO3QDiZWjN{FpnI2*M!MU~7yy-L(>K1luWp4KN$!?KbMo$Iw zCZEXg+V(Cc3nS7~o4`z#>BttZ{Nx4B&M&JGSShCm}mpd>}Uo4uR$kPs;k0pP4+j zaBVd!DMYYL0B$F6Y7bh1MGuZfCxqBj4lRo*)xS8r=dEk-`PO}2TYYlOM-&&9sU5qb zflY*J2SY+w8u!T@gzsn=gmz-yX!Aa`=1a!&2by&ooBc`3MAugm7L=uF#2u+$05T+* zb7vTc@?-WQ8(DuyI(m}=Rv{sx#z#|5r{BlrizGys5>F#sOvYIsa_!&!tW`*W2n5!> zF;(>B7<&)bg;&rODk=deyAG8&3Ljs7MSgJ)BK}QY+G%<`QR|a=gH#KyMd|wg099Gl zS_fuceF)$cxX=xO+~XNpE=K@;A^!k4&-t3G`EBO?Z_JQGsOnPdm(fS4+_^U@ffvwF z-^&m`3aJ#|t#YYM#T)~ZbOwGk)i!MCJbMXVrx`vi4 zuJvoknte>#&2|0Yp_9`uS`NhTOvnL%57&=0er8ze-<7^z^4*<;dOoK51;4L#V;peA z{A|R7jXotnO=(`eE7v2Ab!?yGt@W5;h{tfT z#z1#tRbG`1TKLRlBsEJA4*~qj(<9S_K5n?Si;UW*md$P)NhA^rgjXvod`v%N#05D! zGjgD!Bv?Wtx$VF6n;vhs@^t=k({$@iHFZ5&>qJE|TQAomiG?0mpJEl2NFa( zyXr6b$L}*+Yrc8bZZ%t&^%)yWF80@8N?{K$qbEJNl^+{{>?krqW<{$fq&{QTHQiHH z6KVI_q|({?k4tGJXN01;PwW*k6X&*Z&Q>q`8Y*LA4Ptt@=U9HM#c(qG;q zL+POo4Nww(1GNd;e5_8TchNBx`OC_Gn0l9)e>1%4=3g<#XEv&uR;CrAkJE-9O%zol z?NLG2wcL}E(#oV6>P1K5@gK|iKQ4bRbx1tJ`GcnFx7HIz)0iz?qf*W)D8h_EHK_+M zvlBTIJKV01WxV|3{GI&Cg7;1QwDMifnrv;1`i0!rQkq(`1t27c;$}T-(MHEF(M0iX zP>bzpDeKla?%8kA!YEl z=4IZG{vl~RvdtEY#eS&lq;iF8#grb+xgObtoQv7Z$93xF@XM(U#PUwV?J+dW37y>7 z>=ks$3^#DMN;voHfE3Gc`it_)=_Xx5NII8-CFFPj?aOjW0<;}IjLF7#aR_|}qgl;( z_7Uid9o+Y~Qd&TsqNI~fDj8py9-6O-pdcDoFKZ!*c`yEPYs&s)zOuH}Zto3|~*__dl9-KDo@0H22 zauF8#gUC8`S|^-*&E@?i64J(5EZt(Z9+EG>2Ei%Q`*G$)u?FLBx~zP^Zzh?nwVZ}i z9PqM8>_@_@{LFlMlbLlyI`WDydXU{-x>^V)w3;;`gUG5OYLq=kBld{N4T>%KB?L0Z z%Gx;!kO`nCpfso9lN+-vS5VP3Z!+HLdPkowFQM|4#;;@gRjj~kg|%q{NMhy~E2uT- zenjkJF|lmND&6khbNqn(xo^uKI3LSDFY#L+HCWo|+P&kKzWSu9MI~}a4s@xFR1W5Z zvKlr(oISio){(|pKxInQg=11hX_ZL1 z5H>CK-{oW)EOs#7>yyuLjEt*kY@|gSmNlXvA0O+kWoh|1dZ*4`^PBKXYxz&9hxOxj zzpx@XNl>6kRA8Hx6h1w7%V)@yz-+L8`Cs}5wP|nlvv8LyZ2*&!9$ui0K_;7SYtw9F zlv7c}Z2&(ve76k3RhDIH?h+I6SFcm|;qgK|B9Djjzsur3tBZrFW(e6}Q7RPyf*S`HHM!!IUTkO?evh`a9yQ z@mFG~YuiZm3wdlVK`_r7MBo|{t|)gMHaL-L4L_Uz0Qt+0`M@tT{{YTBSl#|${#SyYJ6-D6UaMO)7K*%LO~K-OvGG0eV@Xz( zt3tO+Go*x9by5jxifx1-@_o1Yon+S@QT(@+R#s_r>wy?5M?Z~eLEO~#%W!DX`JeuBOY*Y+09Cuyf5cG) zox`Z~WLnWcsi@ngbD4CLy@R*MmLPLVH4pj8zaU-c8kd#yZDK2#Z&o!zs(7Fh2XjM8 z?7gd*+F>~CM$R6l0$YcueqDZPHSdx9*W}#_`Y~m$Xt%8MLpWI>5nD=VR=X^Og(T7X zDA|r|;mBWmfpqa0tUUO?m9}?YX!6IGbt{W~Ar{9_mS8n2D<%Su^<^Tcqjh2`y>n+g zce{rf$B5Dc%`pCVc}w#8+f(y17V^d2-KEr54|5&V(J~6euDqF&HsTM()Pb7b1DetmU!gktQI8M!bJCq)Gn( zIDd5-E$ly>o>yDsqbf&mR#a;K#DPT^b|B#J<7oW#{{RVQUQ+ym^AC|8@60y8n_ga? z?bGW9OPiINNg4oMLYXW3(tgQm{8SagEKnhob!JEDFBj9lIsEIVt(3OfoPt{mtLw-b zSka^t-xKwRYN-wC140Ni?M!@9HXR!$h)bGvp#F3Dt4Z?2{{WW|d4k^COTJf)W4Kt% zv8;#UNG2=JF!kI5I^*NXkAV@rJM$yV{$|p=x1)YT`GRdC>qW9lKQP-pglcYLd&GA1 zXPs&L)l*3$W#pd+#6>bPowJNZ+X&DuEH8$PcwPz%>H$b-rvre)$XkYpCfFSa+w4r{?SVGuZgZeo7|=_5#+_fhoBpK zdyEX9OMXy!_Go;ys{U5_o5|XTnmo0r-9vpL(qx(osOE?Jzura}Lf3xAz9TcVv!PBN zcv-uqUFOd}dA2ybt!3o@04nN!T8qoNtk)V$*RjiSKB08z2@mR^j!BVv#G;Z4?Od}V zB(Q{FZpwEL{NxAx(0^NhN+u9^AEp}o@><^3wl8`I&dg&-5#bJsI;1Pq@C2UtBSpYxD3y!_qs@p#}3 z{vo*)kUat6A5JGQ@_j|g!L~U2o&~JV-%+`P(~SzXxh61otAaNtrb;~7o=?1gC3P)c z-}1-vIxQXvq|_smO_B)$@?wq;5Jwlsa#h;V~J^PiZ!&828Mca%Kw z=bKc&yVRxgMZA|0Lk;XvT(pQ{o;zvTVU{?JLMsp(?PdF=m-^N2g>gICkm|cFBv%eROQ5){3BsXoY`fl;|>m-5t3Kj`H$2wZ~6E~mi*J_Z!>wz%RXP#t)SFxtfN@& zVu;HW(2%ZNM(&{;Zd$diGO!tuZxH_goaFPZ$DVKW4>R4{JQlOO;t5=pYmktrGAwKb z5lP?}3ON}pT-eA{;R|5GIVnmRnACR^9kV5ZwP<$Vf7kDdxQ;ajvWbR@AoXgdS8Dv1F?nI$0(cn0egQ$vt8qiikCmkM{;`% zRRB55BI-Al>NE8WNw-|*24rgT^ z3N{_`VXcBnOs%c6Dku6-qJ^i$>4EeetA$dJGU(CWn9aKW^^i2cHx50)>Ai9?48)W? zs~6M&=16czEaaMd{{T!vkk0(os6;%!s6%R^K2Q!tejwnLuKxhj31F3K8hTvZdUIE3 zO*&Sj1F#gpmzru`TQS@PT98iWriPhW7Fmf?*L<@B$82J72(1d&y*mE@T(UfvNZQG2 zy8i$W0dLXGKnGFk*KeaFhA{e6cQz_gKTsZ2?7)^aAdl6NA&_Fac7!zhhdc=X09fzg zx6Zf}m$%rgchN%?IX}ZyP)jKuz*O(P*)YX{=}|G$bkT4LMx3mXxTeNe1Q328d~sB} z%sx?p8Pe3GpcbJ9y-&lrrbLTmB$)X!8SPnMbz?>jP%!}0;i&^^fzWrt5KX80^9e7s zn_u@^>H>iE;#G$K06w@-kxQjRJ?-pQvC)H%L`hHxD^Xf+LObHDIzKC{7jfLAY7{XA zfHVbNIRY7ih4OxowsJHsNCt!rhaxGq-WXyLCV%;W z{*H-tCm>ysNm1Ia2W`82@rx85wW9LX5*K0n*gg;mBv1~%6|UGzAoE>U$zM{R)VM}y zi5$v+#3}iBWN9|_k1T0|&J>c;LWCY%9e&B^DtGJm8JYn(`L|)omnKg(>k$ zI#eA9+v6dhX29yNWzfXsbDSHDL zt?gQPm@rrwgKf111%FoACJYkZ&MEXg0?Oq+DLo}%7j5|-OngUg91Ma>t9dRlF?L2V z_=PkBxX5s*W}a2kp|_9WtXvdqM~Lw6zDyvd`lJGFQ%0~3tXk$%RW%>nx7r`W3K+NO zHMyTuwYpXevs=0<9)QQc-~7LZ0-=uo0EIYS7m-T>O#?3AbQP{ekdxMQy(%bUSz{=I zfEMZPy*uQC79DjAvgx{=^kfzK^x?yCulHyHCA%6^<%Lq6bII#0g+3nKxbD3LdU#|= zWDO#Gt>x$zc1ffMg#ahGsQG=^Kt!c%=UulNZIj>H?{g83Sjiv)=_)b-U-E~1lLGbM zGWo;Jzn7nxTJF83U%r>-MZb5ueKKR|`m!ptij7J`re!7-z(_%9%a=u`7D!MwYN)oo7CCbWnQM6)i~7sp-jKWu|za}P{u%mv*dj? zXtYaMw5>sj(Nk!qp)X+M_Z?c@k5Rv-cN=Cnb5WY5z1EF%xAu;)YLKWAvG}8&C*RY0 zZ6q(-y8Wf!3L7aNvWu_zaoWoM$@si)yq1zTSl_e3CqQ~PvtpZH@N3bVyKYuGuAah4 zB8dEU&(qh0{@e}Gf$8>J#}q3@WAg-a+1^{CU#b?ovt8nyKi}~8Dt~E5#T$EKs7qU= zRZSCGlt~K@M$YzciCAr2zi8 zr3pQ1L(;ofZ`V%@3WR2*YhFEi_+qF@n7H^z2A_3sBqg%c)O6Snd{r%T!|p_S}l|1ybG< z=%Vji%g3tTpY}_Sh?*;XZ!Zt`P2u9-y$CrEC-JkYq zKduftS}mKuF4BV1==|jv_=Bp^P;0#t{nu$f{EfmgfV5P;wWR+5%Ov0OH~TU1R*Eaj z_9IukYkO4tDDom5$>aMz`H_n&UP$cvm-Dmo;xEhZDfvTL*KIAWyy2|HE4{2LIKgWj zIJ2csIar;|0x0-JTBk0_kdd>Ch}k2f=bMW=$kGEOtu@=Bf-7++#~e!4-iKtV_(|$X z9kULcpp1gnNpD_OONf>+Sj^j3m)cTAK|OwBECqz0P=C%PUB#w;VrlO%EhM^Dr5(ER z0m&-XN5etjCkH7U@&r)5j%~ zQgPif#itTBUo~4_K@l=s+x=ojH6}+t!!W#i+`0Tc$%^ZiYP?37ZcmA3IRh|Ol|RH* zgY4;+!{<|j#PVJhHuDX?>}j^3)4-fQCG=hoHAM3)U>+KEr8?7z!{RRkZRV9A1k*49ZIF#JX(EnSig_x{874i*0G)|6AUD(WU<{Ro zI!H(zI$=Y0t939C7}>5QaIwOm5=$N`gT%3*`J7O8d-vuKk^H6kdkOO9qpaRs`TEe? zuCHemryV-cr9kEsxc>llNfMFjcI0R}Ws;8$#ikhy_vnV#KPE1`spS6vE&1zQyAWM@ zmFF5TgA!E@J9Rkc!XX<7!I;dDUV{hZ7L%oU2|UHkCOD z6ehvev^6w8vt9AefJPw4;?EvqDN%U;0OfCyQ}Y+iR(?>qxqCQnQsPIRFd2uV6G=b` z@5YtNFvE^wC#!B;oC4kXbNP1v0GR%D(?2imT*8<4WhA&9YaCIjXJ8EhG+KPlF~xJ? z^F~aZG2%@B064snruh?GIu3%DiwrEM{m60k`ECh3ej0a5e$QO9RfoZqHReoQ zFY+7BI^MOcd0x}%w$f+;ze(L+POw|s@jC`{T9)lW({oH8mz~oisE8Nd^1WM3Z6fO8 z##v*QOL}%` zMRf~bOX|5m?y-_e@eReeuHAAm!N<#+GpG>e@<=?D`TqdrxNiKrq+BhHjl-9?f*ZSI z8?z_{i6rkpHx$aHr;+H}9Pm4?(Z4G{JvGai^x1W5J9y;yT1%VDb&Lb!#1=n5IalN? z@@92{Jzs2jW6B?zzmQ&7)%E+|HFD$3vRhT^>spmM4jzH%}+;2w_6>r-wmYjW!3-_J5b(nqQwjUQJia zo^0~&pQPHVX^R!?pHz@X3`&ZN8D=4PiWb|EsmWu($H}gGfsF17uDSmJIN|x#=a13$ zetG=I@{3#O)=6Pz(q4dLf-yuv>8kPy006PAJaWUMBl{2QLDysMEOY*Z&(Aiq$8!gt z{FG&hmPqIN!3`XW)mBsD2&g_dMwIz{kLy9#K=dqw^DD_dZ1Syy_kWxIf6~0)f3Hag z)-J6IU0*U;uxO$6i3TX@f0Xj+wnlnmjBdng22-$kN06q!lTn|`en-8u(IxX6TiQ-< z%`KPFV)465Nc8xzC67j}2hT7p}SVp**90<1&q z$_l7zdsi+xDKPxxPcU9_{{TX9td=oP`KhENW^QodtbHM`{+^Vsd!2XR8@&0sa;vq<&>v`76wt&aPrQ z&Bn27b!mHX@W8z0K&sKkwHyHhYVHnH4~H$fE=c%*JkQLYe)ATkrHv42)_S<>YRfi31QaOGILuf#sr!@1j~GU8g_rQh?78XOka_PTwgi(ECWz1&X4 zT1PIeDv|Q1)0lJmzD%Ve13mu$oPF}hwbLF;xQtCLg~3&d10!uI>PEny!>$<*QY3hW z@0|Rqj-Gt;2$&UmS}7gD{{U+$m(=BB-Y>e~n%e&F%sLd2Guesl+xH{YX$wbD&-oOv zG#(k29eG0jgujSg#36>#57G1bMUg>v^w@D$>O4n4CF;l%nKe>+_S@;n zMZ5+j<|(7K(+q*Rk6jtmP@XEmfv;mx^x&T)fcu-tP(AnL&zd-b^4)otL%If=(Sz5f zRgCU^$d@qjPdXqUnOY%}?L%d94MjSwN9xGs8+==I-CslgRZVlN-CIL@=t&gr(8?Mz z4(5x=x^?V3Va6=A=QQ^J06b_nR^CGMb)Ka<+*eALE^&@AhDTDU7rTlYoXX)L#EG-< zek#o!)vmRsUS5esx=#nB%t;CsWvvHog=z1Yhv{~4=KYcK%wp!($jcRyP}*y4>JUp+ z?rX=xq3x8w+)G5cm&j8u{DzM>Dpc^()VIojVae0p=3pB>ll-~XE^PE<(bC+_7p)}l z%NqTcV_LD=l`0_v-0vCNtQGLn6zpm_asJBPl~-b zhyERKg3cj-_@ZA|^mnW|`dq%tQ>`o4rVHJbKmXDD`HH(0d5`8d=LeO)D{SS|eA#-D zn2@=J2x%wI^L z-uHbs{&E-c`&zS~QqlF>Im9tEzMrg!>=j9(ha-Kl@xpvE`~v>~oRa?locQz4{Nzox zqvV||ua`W5cG6o(XA;u(@(|Re#H<^Fy*G_1x7uUVE`}~ItK`)w_dX!DwuaklS+3&R zhK{Uh+xB{8#5FO?i&&axx|(Z=OYBR@P;0e1VyPadpi1_wJ*C1dF4S122kj2PjlS?P zRtICC%#yRnRFDZF8<%bJDo)R~KQpGgwerv9-mxX*_b!@s#1TMfv0FzIsia_2bNftc zPT8@}c^3-?=2Z6ye<`#d%$w~m&)=3B_m<$(g{`r_)Aemb(zuS|Gg*wWOS6ZiMLt<0 zAjJ2a)X}gv%zKc@>=|U=WyAQaQ&Ywc@A=`DPwj0$i*z zmk!Ctnm^|oKO^){GhF#f;^WPB)5SDUm}0jVp(U0u=#_>tNnmO^pKK8vOw8sxmGpo4 z#_z~&XHm7$e7|+(Oc7br!g`Z{AI)Njf^!w**J^h~b;-#jYeKZnV+FK%VET|z;Ly85V>}!H5LfZ1` zG)s4nW>|!rXiEZklV1!*0?1~KFjQ9!K@^37p&Usd*KxK|Lt!BS`X<9svYstdOS_X( z=SypZjf$$&)ff zSfQJq=V;vY`Y?#G@j|EQtJ-gGF%&z9oc{m}QYH!km2H_)aLFTd5(1xfY1bMlFRT9m zAZGl;vGV@Do>TL*K1%Xa`faM}7tDzY$jU+@F;gIsmb4KSCvNo2%`PJ?z_$}oD8$r( zQuEvXX2`x-OJ6+A=Uo`;KDU?k4LasYy*)uF0`QSUvB;p+L)A@59rD@YF*HL6P7>dh zJ-1WUKQu0N*)&@Z&UJm_ItwNXhw)kXUh)J%ac5R~G;A)z9Tunv~uZ&4Z`yxOCv$dm?Zgpk z7f{>!ts}}I^%y5EENM|**^i4K6o7K4J`hVA)%3CD?N?Ot{4+Z?o2cE`iGgHk1+>i& zb3^-FYfAUZCMb~E6JpeKy*}4jxl3!wy+2ZT)I5v;Kj$30gXLo{ z<)`LeqT2q6<=8Fntu1e;MABbEWRgUMe$5LJ@E!L0XFT$dqsgpe0NduT`Oa_4ugOm* z`F~B;KPz;(biXrQ+(kvVGA+AX4ne(SkhK|)*eganYH9{X1(d6!Y!Q^k>y{tK_&PBD!mN14SP-<09_84@!K-9Fn9)JY1h0WtR>A=?K=#c0J4i6u()HEBmmw zJcPzoGcolGrq9Zyi63ixyc^xFt7aGZm&Wf;kJBnguWlKm6cyxmrroeeqTY?>ugW`5 z%MT`bJM#z2TAkn4{LU`Y@+14NOv2v}7eWaKaKXNe$jhe~;tzXH9L8jV^H>GJ^o88d zIEh&!GBdlXvlgc&Ct!MIQ54%FX{EaX9Dr;@rl9r&447i74SEq!YCXPV3b#u5kCynW zY{Tt)_|p|xyHNM>Ki3sSLKQr(A@{h_a9^8>;DAzKQj12h27X+I)!^4GqLi z6NXkiiH+!KUAa@(;tld;RK{e|7UorfM21Nf{WXb0Gct1;FH>6b8R7uN8* z)U;O;!WQ5wDfJ_AI)G?*=tsRVrRL7OwfSM@@63@M_mQ+~&0fz=yG6W`(G|S|#E>}h z1cEz_fxu(}h}P*$nkCPd^=(hfTJpB7 zLUlVC#OW%eazS#u3o`%-Pz`Ih%N4ZZ&gEj7Yd@&mSgpLR8yRj^VwZR1azmiSND@4`lPFO2aHcL_XmRKbK@|#pvM`qtO>}v@mX@o^ zTJ$4{2Y$IaV2&J-l52Di0@sYOvE{fFS=Tl~rLj-#yVT86VWpA4~T32tp7NtJ}5 znk5Bf1!|~H>%LV95>2)c_|aj4E0!^=WHf-Hg+C7ctKu@i)?MbWM(aks3$ZYQ5}phX z>+gjD>)uH6B)^(}nHpb^t+fkHCGMu^Hl!;msgk2YFD=Qw)anQXpbC3&RB5b{{RqVDnnPkM;y3?rRSDz7WUl z0s%j?2_DI9bIM&1pw#<6bIH{lV9_TR^EO5o0Ic`V;N#)Onf1^4pv5><Y6QnuemTkui*HDp!PjLu`6e ze;kbEK_EVu{Mr8ioNU*>Cw#eY`HQRT+8y?ps4cv@d{(mD3%iw?m1K@Y04!(i7CVlE zDUM4jMLaIjUtZZ(21G>^b!t|%uTk2)^B^H7ytG;LUocB>$JG}%FIA@l`;@NT2t9F8 z&FUYMzD2kE>eX#OFYL8zEf)CM{b8>4B$c766;DhE{vyms;x-2=$vzfBAf}(4Uz5>( zLV2ut3sl!M{d)23lKtOHiP0_Dn6INM$jn3S%AB@ZR0ER7J|sv1$>sXp)Klpb%&oL( z8Th(}R#GZE{TX8r$b9QDRn$h_sYPcce`K21jwCUMB&I#tOK-&2 zez;j97DEZH$EaZ42&Uq`;}kEno;wJaOTFZDMnAcbj#5}i$6@|eyB@37Gq~FoT_u#d zb;8|g(xf__zbMi|eMqK5_M()2+)ekXqb&%GU$rLo+=5T6*Zvn#ZgxG4QVUIX520B>SvFtmS5W+%IBdYsOyTM?jBX*EdV>w z%X}mc9r}z?v4B=-4FLkRI}Nc^p6X6QU`GD{SU^v`KUVmmF`0svAouCl=Zc`8Va0Ym zd~hWRAOIdaG3b5qR5XME%Wg_K^uUz5QAS`+-G}kTQoDsKDU>m(S_K1Y*R6YEsXfgJ ztv>Dc7^)Ned#`yxSE-n2vb@fnCI`Z8OHavRdW^Is-?(mID{^wM< zYu!deEbXyl?eg0(Cgg+x9vC-EL~VlUS>~(dcx^P_(uk%c5yHtSls~HOH&BChr&{Hl zJ6bI!xUjWtJ`G49fu^6*6msK=kBNvojq((bspefa&dyOTgu+_@L}Fn4i#;p2G~@Ea zAxH%*v$BqRE8EBZ^4vwhSNYzD1t!xC3qbuoj}5D;-6V=wF`y8Tc|ZFerx=R}B{GXj z)1@##id*Zq62%nUjZsvEQ^a+tH8sibqS$nhv@X!URAQ&*4Kkt`I4GtHLeiNaEh&YE zs~oE|9K#dD7}%*b?NOG(EM+I5OQ-pZT)11^a(ON;I0*fFsf?_MyMUyUMLN^I`F{&V zfyptn^4ywyoUN{hG8hx-)}ctD-1qS9h>8r6bH#Y5P|XyT+v7%B4EJ@08jhu{SC<7>Lalo%h z({zhR(yi_#F%s6-Gs_u_nOGw*46Fv+O)~g_Ob<3Ur_gB^w-+dkimMb=K~W>HB=VJ-k{}aA`l^CA@bxPVw%|EdW)1)UM0l=aS(-mhU(MgM6yly(;(0@WbWX zd4zP;0Q%gbzZrqe1y`s8Vh?<{M`k4MnBD16-CbSV>hL;Q+5KD7k~9iOGONIvZ_2+h zOf_35~6+|cs+{oUP2l&$zBW*4lPPl_ogsZ)@(Od;%#1@IefKO`EdUVB% z#}KE`zIFV}{J!%o$jTG+;+7C7w|HfpH=vl?~kNy@b| z6Xe;a#BqWPKG%Og?QeXmapY@zOXH-?<=Y)D(kUfT=wCrHyptMzsHCSFbsKG#$5Fy5 zgml~6A=f|WBD}w>c}C+wu+Z<|)-UbS$?YV%U(psT2~v~WL_Q-k(ydx2kqTOvAL z*uJIto#gF5$rAZH$a*%ZZ>{R`+exavp?T}tNA+`1ZNTow#4i!HK~Mp5A`OY?j4Di6$C>o?JK z=F;>{Hr^XsNM)1OxMe_oDP{emQ}Pk`>UH6-|EbY;R!oJ`T;F&4@{DnB)i%${|R&i8sw zkFM)_g_ZQtYPQn6657VBliQ?fE6s%hme^DihX!B`&8IdSsK=w^&o=8?Kbti@O8d)j zy`7BrE^Q-kh2lt((S` z8p82p3kRb+!ebIgGJIT?tO8TRDZ`w`M7GK{Hf7(GACx{#{M)$KwF|uq%i2Ykm#$jS z*pYhDPbwgnk#jLY8C|&0n)`LM>uaMxz)w`a%~}`bf%NY5&o5{iVgxTb%@y2=zz>8( zu{c%QwJb?HQv|j2HfQ-h@|}6Z{&923*P1l<78=ftrd>&-PpewNr)l%Ybs)BkJg}K3 zna~O_-;XB!k=F<34nai&2!XfeCaa{~TUy*|kljP|7$TBl>_@6nH7s_mD?ve(nYKrF z=&Yafk6umuoBX-byzsX=Uz_z!YTgUBj_TNRNiHH+QOHVPg7V`=PUDmOM6dMH}Je;+LBbp(K*8Y0_Oa5PZ zdq?vX#;i`5X4Xq4#5oYgAo9=o z#81dyD}HqO%T&`pFtydPeHPB%`rgpP6qfV)(lVb|&G0Z@1K_1wm1{+&W6LRt4Y9@! z&!@C+%bzWIyUtSi14`5UzhP@_1ouyP+Coa#UX-gCjRLZW`BtUHXfrTtC2kSZ^2r!rGVRRNi#g{K=+% zUfo<;Y5GJH-iY;7;i_E07!1ZJ6+o!mo{9$^wahc?Hs;?5vilG72mWzC{&Bm=T7H(A zcB`-Xr&rXiBDgS?`4TIG3Q zV@&bn;<|Zz*vBN(29O|9{6~6%cKUl}Ifb{0wV-LyUEf9}sf9y33T}Az`c6ZKc4k{X zkMb(o@xRlpz5G0^grYm{N*jr<({@~Ji+Db+lw2otToJ{XsRAwWE50jz!qU%{c|38tlJ_1 zWgb)i0G!kF*N`;j(!96i>uKS(x4DM5T7*&5IV@Z%{8iszPqscCn?Z;?-!aGe=lPv& ztm>Y0v+}Kpn^W{yhar^;4}hpy1#8sx#&}0JA`$>o^soML7tDTl{NM84vH7#-I|tK7 zp?4LOaar25QCtgD_}vNWj9ZSx?g*|JxVhpZ$@Gr3<>=GYyt9sUlv>P>8v{i?n-W^0 znQR<);vD{7U3ZqVXL}S$D>_H(KJ`;WL_Ig}ggFd;{{YGJ$740Ej-g`LEb8H&W(wR$ zJV>U(f|bHWrRbVB=HHrhkITJR@~SJFH+#GLYsHyof9`FnRxv9DWgwlrMnFclVnvsp zUU}os%dE%ejaN>xy-O=|8Y5mW6CXpxkkyaMry-IYLCD5q9iOnD^NU_+^4I2Xk+jdu zZz=hGG<$+3wY-AzU#y3_gzwKn zDles={{Wo2^N*HvKPl;YE|H?osQG=bZP~8pn8$Q3<@G9|KnqXujyUlE2w-TP-!;qm zv*({Jd8=6b)7A9tF8TE!%Xw)X!v>BjSBfwj1?)&~d^s_L$hkO;KWe`y^sg-bVfiaU z{KNdU((W{yO=8U?dre}EB5^%Y$M=fnrC+%4=qHDhuFic_`JeuCzsk~Bep_4_qiH5H z+qW?8%l-IMKz0BMWtk7|%Vv_T_=hdYNgbK@B+wqT?Mh}GLzf`2Z;Mb6H=qKW{rxgb zX%LsoAX=?B)k5{@)9%Gq{)W{4ss8{g1CRTN`tRs(T85s#rR(vpO4GJieyVM+OaIdQ z`HH(0d~^Q*IRpOyIMsRinQwY@8}Hp}5(c`mkSgy$3&kxer(saQgTCXT#-1V%6kLpX z2O{_zU;hA{4D;rizge(or9^7+BatdM1e7HF{t=Qn4^Y6sbT1Uu{{SdIFuc8~Tx*(+ zjPgSWGCNzZuL7tP_<;b8#c51qk|Zwy50N!%3(KdvyS<7sjPENJK}wU=X;GO#_c)|e z7tl3Wni(GU&N54p#T0@^kG9xBMF1E<=e{u=e!>-zr?ZH|Zg=3#%AL;QnI&R6)u^7z z)*CnF%2^4n$Dp96--IEG+go}XpQgkX4aStEM;~kjgr8XcX4x5hk@;@wKxr*6)Nfyi zN~3ezwrn%T>BG}YhEiubkNn}M<~@nF7M3;|s$AN|c8?w0G0|le0Et;xoTTGz8o0}w z&UF6(D{4Me*RTA!<~ww>)bzP+O~MvN5pkJ!=Bz~kJh>?}8H+IG#$00GSb5{~V?vwH z-gLNI`G%XU+}XXZrKYl7LIhfKTRhc`!&OsIe!uS2Py9;DRC_F1cTc8o!!+GAShdkCqF)56PZXvUanu*Zjri2fe?r^x)KFx3Phx zwv5i`^g?J@0a88@nEB)|#@nL6T-QrcDROcnr4P=(KmP#Eb4RboYkm1cWv_W+`gs&im)G{1g__%XWYQaH zVj(5v#D^51SvHJ7K6(7-u|8AtF0J`Fa9(XD>&aTqr88<$evyBy#NjREf=QFqhz_ivkyF^M zb0-E)FhS_z>M-z-LF>EoU-I+w$IhRZdINbkN{dgt(dM{Y#)DDQV!U5jR)L484M6># zwCXTNJfb#l$)yrDZ8_Gz=O=$K?Fq(MuYk001rw5yfR8?Pkh7=&s;&l@!8d!~j zC(FN>-b2;DC%nn|QRmsOG`}>|+)ZEi8W| zKQerq<&V#OLR*M@z2!|mQMS6#VOxm4xiOS+P9$@Rh^oYWwq9QOm!rxcc$^&ZGXyb@ zJnKGE{OH5&95wTKxsVApQ$AqtECQ+_vU&^n{&m(y= z@^8)lMQHUm^WT}CYcT=0RkDU8xHM&zPwa}GByX~=+vd(Q;ems#o+BxVcRU40psKES zQBC&)?#yB>$}GMwKlz^44KmM7)^6;VM;9xnHNOQm=Hyaxr->xUHezeHN@S%YAw`IY z2EtA}*XCKIlHzS<^l}nMD~600<|xQWK~-RWA=Kmq0A*;uGx?)g^R306q2|lSyq3b& zD+@x(7tyzfd=aXRs62X;*CtJ|j6``dpUPKjZ#L+1+sGrhOZW_OGSmk31qmJLmuZbm zTV8*lq#yH^UzR>|@-OC3oF?*aldQLv6Io@B@9NIh?KQv>I7cAz1=)!3>6p2PsJ7{* zB@u6%to*zAgXT8+hv;oq?lQqy7Tw9%^dK%&V&oD7>)$WS=da2Q4#QdVCzEgVF>yLA zhN*Eq%9&-2c@?DG$ut~>>Z*28mUvq<_>sCv{Qdctss3SJUuxRttu*?C*0QrrIgrFH ztHn`h7vd~S9=(Q2IO#GwAUu=jDZGuWMdphb7V75SDdUbQBr%WQrv_p`CZS2EzUOR? zOlDk@j(iVOPdr}!WL!n%%@WsL)U|7{VT#6CY^IJzZM`8-9gz23kA3oyq>((_ld6q! zr^#QLzmmV1o>IFnd*z*LO^M`X^u$w$)t6((kHQCqHp}G$9gB+@#!NRr{J8wZ)NZ1V z-$B*x0B%$;&eS7tXle~RWNOnX3NO*`&#ezp^7rL0<$jyy7$vv9ifi!kPZLJyID!?G zw+DLuIkD8p7=Rsio9Zu;)psFlTK*Y|9I}mo6-N%VKCMN2d^_ZV6}o;u=U$jqs?)7& z+i*VfinM+$j{g8ncBkQru1+e%NJ1qlSe=K@8cit4cMPCiUoeWn4N^8DvNupzd;ZA5 z#1@oHjddu$yc9iQhiV`{v}yZ9eb`XB%SgniEaz>8`f**0*8cz} z{L??=kDIiw&CfS^a`#cttkz~!`oAdTX(KBeuc^f!i+n&A6{g24%MLNJV<7V{&o9k8 zpUuBI&H0HenvdwHto<0)^$HtCXD(F~GjNEp1R9ZDyJT_1#8GTA1&e7K#L-?`Y8rIq zWQEYjIuZM}@vR8lY(WOOV-kp()(By_)}xi~Zst;5?j+|Thkf{!GywPz57B{((0q&k z067KbkI9V}QS#rD?QO0swfnnscFam#kssNK90FAwkB*sC@o^hx8Cat6-G5t_J$mLjZ%P<92k%Rr<`EUQ4iwz-Y0uWZ&xXe5g2-gky{H5B6D zkaypv-Ht42O6nHSZl6e$yTqY@k;yFFx2qFUNhfnsPAd8v&wrnKcbtDJEWahRXtfvB zY&5m8mS7Sabdb%>qhsn5GO__iqW=IPQ`a%XPZM~RzChD;W#j2Y;iOJnk;tfEcNG4a zkQ#_)aoR^dj{adS>A0WK;2JW8i0B6|R<$3?KsP&L#DtD5L((aEaS)kph`5p?x;n`|UXxeJuG+OzF+f*U!9LXCpt0hQbUmoLatCoU-nQ9RxopBkpB->7gM5}Tj zlSW=gbM0I#+Dh1%E~S^lhp(^|@8KpT-_6dpeo=&GxXc2anl&VzAptfgYCh{aL~ zM4U=Bc^$V5Pe2d3$pdUiYR^+J-TING7)S$-fQ2+Wc+;rDgzw1z0GvK;{JPUFbblh; zS=-y)O)EK^P0Wu`fsf#Dk|VFeR#k8EX`^RBUfs_C}L8(KqiCn#d{qY6bdPmCxu6L zQ(cZ%k~~bHX(RKW=We0-yXQ&#)#vMgnzp6sLo}%vh9I$ms)-uxgMYk|axwJmo)v9K zL!(J$b*D-~+zA!O+eKs~bUxjDGRtczb)KrSY9d+RlQogg5jVPpAs=PL^+^c!o-Tay)v zm?dPih{qHyGZ`6UP)QW~F4dtMWgyXJV|%cv^-o&iuXOu$h6#f-5t&+2k-ym-$Q<_D zkpjJQByQJKjJnn1lT6hJZP>hIhToBi2idOU-kmU`tA1Jh)W7_rx*lcHqb+#wHM}qI zkd!J_g2)YMz!6RM%5ui{W;aG$er;-Bo7$V}-e!zk>N78)BWiSs=f~?U3UX%ybUjG2*GR~|i^w;N(m+AgudA8=pQz9;@A(3PpWr&cp zEDu#DV8d>e?UqlQP7`qtH?y`f3hl^Oe$)b|<&kYgDxfq_N%819efU*E>8o!jioT&o zru{`Wr-AXs2!h4ECL9=qPODK`3Y=9dgw`o!U_ZW>as_BlN{#VVSy9N2>e<@f`pmSJ z)5rFZQ{rEAVX;$CaaQkc7VqkJ{1qfJgGK12*WwH8d@)t260WN}%6ON8B{gHjQH^N5 ziSJBR4W%n3qQ@-(63Qwn2VIW-*s455%4pnzR3m?@xdU=G#ZXmv#~GxOW(0!ILQeY% z0ZIWVAOSeGWdUG%5CX`5v|Q#aNZ(vqve6 z!pH&pMxQEmLMge((>9GML*F1mr}utg zxxGoCl_KFfLW}~?FQO={wCHKqEVNPv>rmunv&im_sEi(MCy9! zzqd_3-rgHqWOFG*4nQMy1C>w6;~P?$>HciH(=8*@;ELUh9Ly6ue5HuV_KKR) zz7-o}nBB2Tn$?LU?n&#Brfc`?D~}4JBeZEMM?fo<@#~g`i5H;T zsOX}GyZrs~VTvL^8i+^2c0IfF+X|&O0MOKJxY+DGa1}^z4Q=O<}JalB+{b?3R5_>JLp7WDV;uU+Q<(>84y<%`K`BQYLa#Q@uU0q=J{**|WF=ZOWK9P-L0GV>M-t zCK1W7LdJrpr^gTW%HWvQ?S@@k?DLp~osLP^uYmv5nW~weDss8|V5PU0K zm|$6Dn>Qg404Pm~>t2HhVpCOQ+<`{$J0F%5FJcllVhQ899ry6XP!R)rGTlz9meG7F zq*b~6`cuahPF7JH6=o_|asd?``eL-ettOW9oXY&q7yDymCu;4~4-Xs)%y={rB61DF z*+A{|;(3?uF091!fnO3Z7Yp@YxH7b>}SOVk3^VAxPp|pgUxvjL2Ir7+o@N%spGwzbzgx|E^Xsv#oI}z^^uXdt zWgrqM(EL6*MA@8Vu-!-ga?8q^m9)0fHSl?2XwUjO@f?(jia)+$$`U2MFb{mT{{Wn! z(R|~gNu=B9y1L(u2JX;YPXURpE-oMuqCgjwRF$D8hzq`EV!}r5EWmuPta(#bxYF({ z<(Aevr?!$cvks+!WGWD_=y&g#4RP7@Z|2YZ{Nw!MgY$X(#UGWdwUxKjHMnoI<-NBsuhrA-Jf^?9 zGysJrr*4@ujK+y$AO_uDG38G+NBL*^TU6EMmRp;~)6y5Tg{MzS-Q;Oe$`QlufW9Xo zC|bnyWPVcr0G#2s@(-IYJlh_Td4Fy7cC&)ahDKCo2bVG^4%_Xx$dF>$;qg4nQvU#) zo%5EZEc&&-lIP)bE6g2|;HeT4)u=!T-?rI!GM4+bojh-w(ma9x068h=yZ-ATsiNzT8XTOzl-D=)>^QWBeWW7nQ zw0%I?z2PS4#K@=~brqojKvl29Out8rae&dQ`a{V-FMsDE{NLq$YTo|<$T8dLv%<4L z(@s5Bk}d!+U?>-r0VEz>vkxvY#BIorAoOoFf6hhu{{YW$u9xP`O%mNBo=E|*8jP_xk-~zqG6wiqY)6J> zo9NICIU9Hf=Y+m&Z!kx7=Vi5nSC-xuoowAohTK$#QXdH7!-z4^|`8uOL|0#TA7+>CpsTx@Dycp>gAnXwH+xs*7yRN+=I7^~ z%pPL3(~s2w4HUA6wXlsz+^noBYU3$@%tiWpZzj2FBMw`>)}9MnsG@?!A%jnX6oSs$2*8dQV*yq; z)j$*gYyhCkVmMqW%*fe%L;nCd`E2q2R$Y`?Jt)#PW?)nbTqP^~GE@3#yG!*yoJmoH zk~jyKG6DAg06z@Ix^@Iwidr;n%XX(hPsa_QK@x4{iZVhoJA5(5pq6(gfj}FQNuUGA z0gwq0e)9hS(2DAR^eLb6ul}$906Tv#@g+8|=`Xj#{a;W0AO0GY-!UxT6OrWq0RPkb z`HH(0Xd2XbVyjh{k{M__8ui6iOB8I5vLdoLA;AEK6rl&lY*qYfd6Y#Kt*F7I$34B5 z*6tc88b%^8(>+ujwg;s}aKP-djTQxb_aanemQx#TN}i+K97#Y7yUY5`En7yqjU`45 zRomiqByYcbkSHN0*X^FcEiL(e@r$)izzwpHh#K{{S!+U2{sbw1)mOZ!ofwRJaP! z0$ex7!MK>}0Y9}&!I%*{xuRsk;`+Al{&4>Q@)|iNx1Y$`&Ah6?UK6ZBDc`7L_t!9w zX=8z+TSg4Wc&J~0&KQ5rJ&QZtdrtDMr*mzkLM|`jO=2%zD8Ju^H)^sD97 z&98Ys@;5>9hnn;w1s1k5`=Rc3hoUy!5u{TT0~=8 zynD;P^N-$l)$X+4E`EDi>z-`UW%BXVG}O`WZX`=dpMt^a9xdt7d3-b=j+Lb{%-&@f zYDd%2KJy>sKjjaUJg4SMjdM!ZG!Hu4=#yP(QC?ooW0G<3t0Z#;R;!RGz=Ame@lz?X z4#w@c(B{XqPx-_xS4oodPV;}1Z~W1IE$n5re=lk+4Wun7W}R*vDSuT!P!N1Omaa=Q zgf<7}fs~#|@5~R&Z_2GJ%HCtsqw>C|<$uhJ1+$M%g6C15;yEOiSksKE^gsxHO;tYu zsd3;F{^KUsJ*8HL8=(O-2@@*KDMN$IL{6O~m3fuPsH8}Z?d$5>FJjwZk zrFpMP^H!tf{bNo#T)GvFtR&o8nJz*{C<`1;6{xc^dTOd&7l~t=06;DjV=LV_v$?a> zywBtrG_69$`rZ81dhsQsu*%2}*BWUVWBAn?v5L3DveO*dBf?uSg7?oMerQGcapv7y zP?gWDZf3M+FG34(B#?GK)%r6E2E%FCpnp9zSZ}=in%k5y-HnsBw;BTtjNijyLF;00S zicr?I{4k&^+-c#X7q(Sva%kvkS~fqj-p8|l98=XTk{JrJ1gIc@O-KwnH3s{5cfdum z1@?xW{{T6L`j?nt)pg%1eMnnai06=AtoCv7>EIun z-mXZ{{X7Y!A)UTxJb7VniKF*=|VD?;*d9OvdhHrf6Lz?x0?LRrs!Io zw89-%Qvz`vVj(UkEa4e|0H|sWz3G|w2ONMd9$9dL_kBO|FUzdnZ#RNyS3>hGj*)KC z&ZSb`;^4;Y8 zY9j5f=e8A;l^drLY2bQ;n3{}YHBFjq#zcueSBx@>Ola&&aT}`p45SAsSSLC#sXK0W zrZlOlXxE;QzJ+8_84j`~K~fDv0yh-wMl4AQ-n03e=k0KC)I8O!JcxodR=RE_P*Fp# zLr)X&dz@rAxu}R7mf3!3eqh?$D(U`f*6k*@Z~{emRXl3675CilgM>0r^JnH?o&NwZ z;)2)n7tDH|xfQb)fiI^nBP39eHWjCSzWF3qRwKmFaR=Z1ya+3p0s%Dn;io#nIemA{`rL(p4a)XIu<1}uKI{i{ z00$(NAI$GR+qWxkHS0*n`EO(&#~Nl3eq!^Fnf&C|@_FA`zSZ8;GQsuPnqN#Fyh%G( z2{+A%0CGuy>IkRLr90qCD%^ZBQnltO_j}}m6%S4$V0(7Ltyj3Ghxv?E$sI=~G)3Q) zXaMhuzMKC5oK;UG>;7tgF8*m~iK^LN+q!A-$j+qQQmH_sRLS-hyDfQTm|_gKXw+C1 z9@qJ4<_!za-g~(6H<`aDyuYUXMp>c0TZWdpZH=`{$sr6-$xXu#m3PdDL`c`_Xv=Yp ziEdvDdHVN3z4I=ud*mBmsQGE{C2JT97Yi366z)j^g0wz4hcmmEj_ZDJpg-pszc2OA z@g|q&jYCIy{H|K>mGh`;XxcbhrbE#<^{Z1a)8aDR@@mhLg>^&f$$hB)L`@@U(S1_K z%}7@DBBbO>tyOlX*cDn+>B}<;iKJsbu$F3`an>}?$p+H(3(2l6HO*CY>quslvPA`& z`jUEU(JI_Qr);E7vHQ>m?;k5_QEDDwvXW>bdF||inIi+4RqoA7RekrSQ051Qd73+& zGFWvD8Q$8U^5RJq?Ow+#o%C#tb!6HWu4AxkdxJ~Mru8LZup|Hn(?Nt5B^5p5JhpK= z#;+~REgHLk8G}-SyLBS9!^KJ?)sy+7$@+(vu8qH&w0SHZVd^M#Q&lwsi=iNf>-dU{ zOpqmS7t!aw(see5-bYI>Q1gtMsY>oQ=xMcbuuEYNRg=tO_U=ob4H`-CtaYz_j@wq5 zWwp|ti*0@8dG%X;1z?@i(+?Lk^(a9Gio^z?9zQ&Ifk!4E=RF$o*#!QKw)4aQXu@zc zr8#ZVp51Ur*Cufwr9M!aSGjFY_Of0^hA7L@yhx``^cDBW##`>024#P$C5@fK%BmC6 zWh9ccE(idQUF*qV9zA1Q0=@*T)gMNT-hZ ziYuEPQ|nrPsc-P723n~Ef1iA=K!$J@H+q=YZgmJP*QtkGM@cDGf2C@~j zhdQReW##2~;nYlXgpNiC3p$2CT>LwMwMgEWc!HShi}P=l^&Jf+(fq+`hDl;F+eos< zG8J>N=Mys29;0HXsKUlCB=SC`cjepue0iY-S_dbCA03FJ1JLDBu-`4-jScLQq?eb0 z)8aD8UX)Q%N$|^fngF!R%NjM;m^2AI!=cY;$raRsQ7p*=##HlALy!q@ej0T(9Y!KR z@@7SIdC%qqEq0doLM|>j8Jl8Q)D7v}WqAd*K+<{TonBPZW3XubQY9|z?0Nhmh@^M{ z)9%Y7$*x@0?sZg-dn+s3fdXD!#A@U0sDHFiWe2ae2~L-S+19(|`~Lth&n%ZuYb;j^ zssuBmo+-D*A5f(9uHAAx&>uZ5r21~OqCjI|HGTpB;>NVwY7w+AaS8zyx2i!AR&{C+%7hM7 z-h>()h?p$Q2n=t{);DIt<41E0jS`}nA(}ZOV-f0(4&e6N+X)u2lL_)&{oah1aa&Y< zWdgNM%R)B-y=k}0BORGfc2TWgO=qRebu$4F9+Fm^i^O4Z`j6J;Qi&oh3Y8+O zw$vnh<#OiR1GCXrQN7h5w2oSsp^u7Cf=1LVX}K-qmIk7jc~aWnRP#D{VXsow{J`rrAe1I$EN?a9W={#^kz$eD|z)eA*=m&;cg2)**{we^OkrZ*E@S<3t)EJ-mikyM96 z_PUP(Mj3KMCDr9VM!LArwHLU8p0J6c;@hoHO{=*bvbghSDO*2DWmJ~(?SeyX8_Mt1 zSLaUcT2O9s!yp&|Y_G~14X>Jfrn;T3wPR=cIhskLy7iiFQL!sjhBqp*14U!7{iBc> zFOwoGo5wukYdzO0`kA6M<To6z`-eifsCEm_ndsS{u#a!TWYq~ z?R22Q7 zY+CUUMT81|U|ksHmd4`75f}~W+*taJbyK`Rs01?(hw!ugjNQRaZ%a>ru<62LAwZkQbZLpdwg0iDEysPL986di2FmkLJxo zL%Tz#8I$V29h7m~diM7OkBw#>J(xD!dSaCgaAHdpK1&!T6ZF~V0Q8U06!cFXq85(Rd70{>JNaZ z-|od!lCZYowAh8N!r-vLnipH{Q7{JHXOiEri4EZSzSMP_=;XL{60CwRKLw%kO#`2kkfu>>UJ%0=DWL_OT@cbmQiJ< z83Oz$riGjk&(!V!!x#$P5X@yh6c^_|mHe%wepV-$e3_)_H}-9*Y1(dycWZdfbvLa6 zd#QB>2WcK!@Qt_>103)GSWcfLr!oukzV%w`lbHBOu2GaQU>J1(j-X~Mm&xh>0Fqu; zwA5nr4b9=w;JUYh*h6=#C#i1`l3TbZ)8IllCe`m;kH&qBpXlssi4^E zdiI^BYtl4&eD`t3I||e(G^X3{(`-a+sg(wMtUJxD!Et+HlX-Jb)EYRF*3d#8IA3_w zuvTU(L&eW6_v@44Vkd7vv+|XnoIJr}=FKwPJ)QDuA5+t=Vo1VV+9xH9s!%fb9w*^B zIKU&1XPtgwXpvl6XnOIE2(=r_IU4o|5m2OwAyMi^KEYwQ29+5Mk?u?-MxImpDe2O` zF1Y|3ElBAPTGE*Cr-@cQF^ALF9u_7^-L;8~R$)XN@6h|?;uuOyw!++!Ze;isM#7r_ zd!L_S_vDx|dvx1=gSk6z^4}y7s^gQOsQ{s+JDylo4?G=f+P~-W#aR6ItYRF6XrFa^ z5D5&N|Dm;6fj{s%FhB|Rlqo&|(fWR*jztpJiY4Ghq zgN00yv1zrEl7$vqlf~WDrOC8f_bY<93_xJ1V zk_aW%dPrgmAKP>I;W+u!Yj;eu?JvwA1qecJX&#*ARUq=M^-%Aoes)8N$fmu zt)^@Hn}kTwnT$lyR;1Cp_QDWTXfEz%XJ4wwiWaLQP=;gFP;}c06IHq)6|NDZTAps? zQ`(g2jjbVPy#W#^4N-wEd}-VdY$!+C4^BAbI{{e$?@#JZDu%b7NZbpmdc93oer$H3 z=tobMDwJqt8WC)R?H(;qc>oxbQ_%0z6=ZsXJAKCXnPq7Yf zc}vV+m2&=CX?|UO66Vh8+*w=2aAjBOW}2W-c#y}F7O31|IqM$?QKuq&MXxvcyGqmi zk3NN~`QlH^4O>&6Pq?r~h0(Nhg$m5FNZ=94ejWm~rG4e6}eH(YP)e6EIN^l5Y;UtjJT~j zyZrj{)&BtHf%5jJa?gm)iwQZ&;CfUDQo6gW3jTb zP~1^sZ8_tEf&GwX<^iCiH@iRDJU?#r;HSf%D)&X1k^t*LoWP@hHfJQ7%H zR<6<9TinLT@w%}L7&r#C>*9J>Dbr-*0=t~fD(3x3{DJ(v*S{p^Eid41@*dUnl7|& z08rYz4RFXKQdJ_{apX?psX2=S!sJR9yU!uizfUV`_nubMtZrHTJBPZrLL{AsGw8wq zF`_L70Zf|wFs!RDX&$uBy2 z!$OnF8k|~Hy{xSpH1?KB6zjm&f<-l%U$o~M#y&K5im0C~cKjs8_KC5G^TgQ28#xVDR?odc#otoi zV9p0eA3hlqV7)`j5a^y`((S)6{Gn$ahoT3X!s_K>wRMt3YEczWtFsOy@d!>_J4YDY zhL6hSmn5rD)IOtkB{cWeY=SK=BsO-{bJPT5%ZltOPUPk^`)d`@ZylGKte4Jz^Ol+? znMREb-luJ*`EngL<|rRdiuOCJ$=2;lM?VNuC`u_-V#bHIS(i~9v7o~S6OKmS1OEUx zm*lwo`}vn9lXt0D>CkCbAEeOgDeA>ChxE*0Dgk}T-0THFCozQhT)9TUed!;b{Ee;o zp3BJgUR$;=aRjDW+DKw((j`B=4pV}XdM@=lW>!sHW6{QjDHPLH)_lFDq?Xo`>a$-% zL|7%3-Z*MMnbBKncrV?QOSIrQhGRoHax5!W^OuM?vBJPlCVa9k1To&E9Ldish$*JtFcmER-f#%#5J?_9SLj zidT}_HE|IEH}xUUrhbMMnF!7d|BS*1bqmbv+L zYjdr^<=tb>+T8wlDv_zRhGT0Sw5)M7SNJxj7s37f1*DVraVxIX+^kklO z@=lwmt-bY(-euDgcqHP>G(uXGk$0*w03Q)ikjW~GWFr29^`Acr3d{op$C8x|f zc9Sf!X>i)Zba|v#cM?ZdP-)1XUl+GZ_rYvvq>=f$(&p|xCJkQMwJFh(IU{iFC6!8! zAPQG{(z!TEkOlnz0O}g$j*F=3UR~8MV_WM>`>3Z@ARaYtdm z63I8264uH=Btt{fzjtgPk$4d_&Iys6eX+M4{BRt>%#NRh<{y$DntoT(e>FU#f98vQ zKKDeop5o&2+Gi%*GDKDmby653o@%8?EUV#|(k@J4)W3Ok&-uuoFKU)?>bkd>ZJ^R5 zQRzWw7}Qg4K}~q=)a~00XgHZck*i6U^Oy4K;4GJV)t{sX+7bm}?8($+oNYr+dIY1+ z-}9AUm%c^v<>#Dq-BmRSYymMwC3JN z+uW5%^w?u%v{kJ_s)5c%4N9GXBf|*}d@%67cpsOtMkyo|Akv(6`YJZeLgawH56hdI z*;30*)91Xpl!Ztwp?8sqJp!Vfu2Q6c{Z0P>oG1SPpL^ZIuiO4>esv!d#`IH%p~ZbJJb2Jjl%*-sl*=05|J3{Win|qd zD(qFF0|KX^+ZBFy{{YTj{{YSic{B5i%bKT}{GDSandj>(N$xBsvXg?{OpD24ogS$E zp&WS{6(^N;!Su5d;@H0hyvz9$d*vx?w9h!j+J!unmdC7m1bELKr2zYF{%1C!^FhJDU$YRuM+kcB-ANDQZ%TiaaSM# z?hZ~TW;BPe@_(5%>*W6c4d|DulFHtagjPHL$HGZ(Y7Ceb)jgkR{%!d;SMsmrx8=^C z=Ia^s`+@pFLQK3Eufjnf?lWPiozU`dwBJ;V>OU|40M093d4tK?ev5ss`GMjV(Q54# ztcx|BIaEa)EY&ji@XVOTh4pb|pM=#sOUf7H${(8^W7TzEub4E;OIxXvTb3v_2_cD; zH5Nt+Tq&xcKW3S#&P|tTfC)wKnwR|Mr{v7nb3LxNbf~;zRhGtYQABIRh623^@#&n- zqd_@J>DuGS0Hy`zU-`{X%CFFR=9lH2LTjB%Rkaq8$o9_^ajOx{i#QzzZyeZZG}Fd6 z4mO~1@<#sv&N=@8&Q93gKCk54{Z`K3%leIl)w546&_;<24N~FC)H`fAlEIHkX2xLC zf-#t|AIa~{uRHl~$vQTZqH2N*OK6Nx#_%JR0+c0)sqq*y!p*ZAJX7=I^MB0O+U4~A zZMiy#nG)HaKio=vNCKebDmW!8$ByEnxZ;lBd7?t!cK%>~W%a_tZG(RxK^qdb6D9_u&-|Y zHqCB)hm4OmD;5DLg80Awa!<~_V!QKPpIE&zz08_$FX^Ci?(wW(8c+qGpzH6MeVr~T zk9$U^2#7DeJozu5{GF($oIIDK+xgn&B$rLR(AJxM`~v+Pta9wY#HR8u!v z*bKKGmg=;*1~aqcuRG}9ojR?asC`(9{1%YpDnf3 zgeeM1Z+0P#;}XiQvmq7O4b*|y<{*%Aj_7k5%nG*4TCF;R;xO9<_LuV6IWaqWojJo_ zh<{&fZIDL(oxLY%ZcBEgX1}W&O7W{|0lg+Sf>3Bxkb_>mKhC&#f+-uN->$7IY1eWz z;Ppm7y-EXC0MPB$uepx6?#MogtaSDB7WBH||{%~GPt~csJuz4v94xf)c4=H#+DKXyX;_JoSLqs=WDqC05AUlFMO}3E`g;_CCoP-U9!1o z?&Og|8CGdgS&#umP@})v>y+v;i5;6X_;`0b-W9I-Gt53y`oH+MN7OWy*Y}xa^l(=vsyU04LL+mS#~>BT`QL4ZGLFt#VvJjlB}z^2hThMAD|! zbuTD+iX@IeqUZEv#w6uRa$qV4u@o5|HLH2NI(7D`Ig3uVl4(nEDH@kNt3oI@>$i>` zFqUOMsQtFFDz?T_9RtqB-7^+8f-@(q;}XIxI9H*MVLfxf-!_pmsKQC?Y%m9 zZ-gO~>Fn{;ZP%vvmiRK&Ja*g+RQhf4BU` zD!c^(gnc<671SgEpb_8hz*VXpitam8V}Vs|ucgxq$r{HrGjS5bIVz09?6@O!Vd6UX z!WA>To-2?zz%6c&@tzM*O&F-Ev~n+1Vc6~t*(E|p9>t_$pbCg;;Rd&3 zA;c;5pXRscFO<_u)HN^5FEeTBuKCKw-rLOf9Lq~>a}lhQ$2x+hImXPQyV17XW<;}X zvxN;eL(%aGZ6eu3ZLL{VY5`T1>IY5LDZXMm04+YzeB72geb<)lyv-~cMd{}~oDFhe znfeb>C7?TakDefr$$UPkzMtmSpHDtXgUz=CLY10Fu~=t#iKSV%Y&n`x5^`K-sU9Bo z!9J^~YVa8}QE{m0@ViADq%s6YJFxWJ21YwpqNbY?G9z>u2(!N@{!ICY&3aC-@kKq9 zu-Ti-Ws)~Vy7bK&5hCoeQl&wyNTD0oBp^>Fsb>)&K4jK(>zE?0t0O@gu~2R!l?@lg zN{#ZO9GJ)+Ok`?y*0tv+s5&T(2|tZG zwmUsj$-ZpR#ifmpn`P8(g|x@ldqwpgSP7`%%+N9omb(G>WQ3T?9n5y)RJe&|@tHyzJZ=ve5dEcZVn41@HfTEp>f327XP7AAwB*bkqMS0c(H zlMg9*u01l&e=qB>Jl1df>vl!`>@tEkLV79gKdHkB(kB~RsOokXtgg=F_%tjI$J)7P z9iT>+T5Hz2d}Y<8nU~^7=;{l0ss8{!40zXtgWO!*+}$>#BRgC(`kti?d3C7ycFc2k zZ0YJ(f0z*KP(v=MYb;lhfEnN)yO59pemel|O~@Pfu3R!-Hm?qtp}DX!Gbx-`s4<`6 zj}tBwR=egyb*GIdO^!uZAk6HoRs*DCuu;_aI}X_y%F`IpL-`xcx1LPBdBwNZ?5jPqLpcja-)nZaKf1TJxfb+p2_lx_3HI32$1XWTSB6@LUXM>@TWF_x z?p5O}$Papxh{%ot#dX`;y=v|6?jmIr3aS;jqA1x#ciZvnl*p3WHhK=9`GIu$R5}-# zEho7)hPIb#52}%oyiLe_Nz$AAJ+e@pFfhJMYE4E7rWY@7Jwe=XJv;_k#2197H@|q^{)?8{dCw_hj1v_0;o8zv#F!b)YDPWQZ~~~V^%&aSP4A1D zI{n*LYCZ>iDt9ME9K-9Wa1wNw8#*eoEE;@Xwl>Mhy_krkZwD#MII<&rVOyu-1gqu# z9r9|63s4%tgJl;S*NlQ!EOSkFr@QD%;J=Xl9-B34Q!}2@=v70sS2~KB_L{n?4OJMm z%GnsaJbYYZ#2w9X9)2a};yX6<9zUugBzoo5aU|k#Z+Xe$mJ)`@{7?E_gK&oHXOWf5 zmpO|nkQ&h6-dDakxczcaLDo-J)E=y}l!uQ&o5x(quwIR*RaSLX#cooH%^{rTZwxf) zTBcp_(fD)$Cb#Es<-*WY&Kz8^SO||E$@djuo{8d(EF%LSJn=d7e*Xv`vlI)aRa6_5 z4#(2XH|YQ7(q2e*jWnJ#i_(X`@kZa$=x&&$C>Ed6pt3kSXsmiB+gFcd5rBW(l=2Im zeh0he4XMjreEqDwLCT)F1BtWu9iKS9XhWjL_BTT9z-7)O4sn51p+(n@k0*EZ;I(?; z{NFb6oZFAOM=QP~jK>|P&(2^Wu-tqnqK4Z9a#kchP=5~BSh_cM&QMB@|Ex1EOZ%ce z5R0R@}%Yt&;W>sY&%R z#HbVtltuwE**39V)TjmvNP`~9`U^NS0p4o$q&B&(S3}P~?rnf?=&rZDtb|;nzh*|W z7Hc5n$8+p(t8;u6&jz5rR+qs~V&01_AqDbKO z@GbG7jwe`%=fm;kqJt8t_g>xU6Ko=a)dUR+9+K1n)r@!2FAU!YhmN{*QxAw!f%(%$ zUFl4n2sLK``^j<#vl+ny#N|Mlzme^rlYqsVme!K9Gq%YGqoGV{Fi?w5u`1!fAnV{z zdgt2!H>0d`Xv1x$je|`h!jk4d+$Kt9aeb)h_urpRRy8-bW|{occ)0}E%i0W$V`CBG zS0XqOt+*}G8$bRCjj_1gW6QYdNH|Xdx}{>q(4A|_yA!r{JfVwyi4iTUQl~sE-#ZZ(tpr!;?`xv|JrC$uOhIPGmWjGBCOubTk_)8g4Zt2ypwc~ zg6Xei6w+whIK;(YA9ETWUWqr_=WQ$X{@JrnCKkPk2Kn|g-qArEu?lk{nV%CYOG*pT z9}I@W=EZqVIAG!=c{=!mIqbFv6fQPEnw(J;wk_VPt}kN`WFJwxAkE=jtkh&>VC$q8 z7UL%K!bz&Xmx7Koe}V!4{jk1b2$yl!^1XLk{|X2363fqC-6N{H0c1U_sK0lY1$-Bh27MXlb?NhN>*f`u$Y+vc$^NpZGgXgx6MXqL)xsU!X|*PW%xc#nM&cS(h! zWo*bpjIYKFn-vh$I=n+fXP<*!OanBUJGyJmmf~m>pXcbP;Hoj1_J7DqL#MX%8tiAk zg;3jk*Sq?XN$^HFn-`Ki*9@IN6a!VOg4gp;I+3*5v$bgDmgzKUnh>+K=Xn~D92u@R z6_kn_hwrTI&op5A1t19xS)R`(hP%9y*oIsY|5(pL$G%ejne!(iNcBrL<++^6pixZX zw0Dp{5q0)5aWPv80;>it}W}Z zHs3;Q`axlnND4;MlM!hjUeDy0Nh}%E?qDMD!G9 zW3Yj#EvXRi;{Q0oyW8&unV)I23!RkWGy;B6Zdu|KU#wDnfJ_IL<}~SXY9d@rY0%W15Mio=g(SC?;qVPlAuiQRg{=6yMOyLk-T+e zzC|B;3D6O>o5~`;| z7qzy0=N_gEyry;33ih_gEp2xv69E=YwJnq7FS*wI{5({0$IcO~&Uy)T6WXr|qL`0T zXC|x@J}NUD&!0AB4&_>?9VQo$=63X5s~ z5MBk;ec~6Ke$gkZy3YX0tCYgE4I;nsv$H|25>kp8^Cag^WnfPve=pNC25^10(N0%B-~=D3HsT>t!0KtBg~X0x#ij#!sgvhX1a_x-8yk63>c5T zC(>%vQ!DZ(2$sq-?}M0^`n)T5f*;4w0$vd*ot@i&eyQ5RG{7<;kh)aFR&C7^&bo&n_#>L? zT_xPc!A}sB<@dmQPHndQK8n>XPkBv-sS4yGU*iOj-9CN6o)vXGz~`cd#X$tqk3l@Z z{8>qd!SInOE-qsQ!Y*5YkWjl#q5;fxbT#~%Dcy5Y=>daMJJMyiE3jgalmt zp>yVco}*HIN*q#qx6NlMN5+>F8{8zPa-E#sqkLKB9F9TIZdu;3!(tGIXgjUZQ!I38mGbB_%w>)GU@0e8MPyY0I7=QMxI5%MR^?Xra zK=z=rXJE-9OC>L|5Xx-@Nc8HN8e%MBMpDLO4>nBR5>GZlmdSzBxcytWs%`mGRzBc) z)bX!CK*;)Kj8lx60k7Leebe8uqbR=ak|#fr4N%y4^y0 zFrFQwV_JS=vYmpM%!%{@Wz|F`nlJ~ymlpj~F4(J@ zep?HyZSk+!nn;I;&x>M5x6ixAFcp;EG#o6BFK#8p$eHTbC~iEfhg86oP)_mO6E4m@ zX!g{WVrjFJuin-Dbfe^!!=Wb9`jVnjp8m~DUCI8}jE|byTid8I0CeykVriU7RQ^+B ziU`%Rs2_T9t=ByAK4nE@I#|YEO-T_=7+vyVO&XcH#R|Tbj|QuVi=) zGBxMn{&scBWi6TMk<3mZWOoQKQ3fZpCHLKJV~oDpiklA#W>*#GHI)`MeGkRP zLZ0u;g39UQ#~3jBJp|{kg&b8iknA01nOH6%5}Gt}2`LRA51W1`_nd4zEc>z+dZq#3 z-M(Hj-ZfQDxJDZZ)~%289Yy^>?%EpItN}Hxn|Us*PN7;o#=ngf$UP2w_o9p4|43Mh z1DX7oKAYfz>nPFLb?kqmMGn3ML~W9Rx>ww?>`J$N>lWhHN`6=5-`IBzTEaT|mfT$U z=cj*pH_GZ%2;E-j6Z8X&qVR==?uZEK+26$^#I~wkhE6t50a$_cQ~&mzigS!YB58c- z)~?rD7mBJgV*kA~Dp?O&o$?!wZl6)lb0NrQ?%eys_Gedg@U^***R!)7?fo|XGc z3-p;;mvIqtPyWTeAPmHsApxbYf%46f=_cn06jC0xEH~X$bT6L?(VCG>V)L?~>&)rA zqt7P0Imq$%idDwnJJCm{efF&SBg&M2{QNpzMbn!{4y=lpbblYgudJV%yBbRuZClBQ zr~5t1e(%`gm%oGe|Eu-XKiS5io{_zjTlo!2n$qAYNGI1*uuY+L*hyO19woDVEfBWD z%g51Ei^cm28-;asBmN2hzQ~2>+d&&}R`VMTptCK*uLX8)^vkd3ixELn3&~vzr|bG2 z*+k2Yi%3>V`ahuQ(y%!2O~$>c{p_BaJL`^u?N`deLxCN(`|lqJbzXlzUCMRS+`9~m z#KPIWzC}Kz{sdP*tiOD~V!a;le4hBQyX)CLr@13epr1Q#heYyfMH)BF2eC^= zI)#8mubJFY-%okv$bo3>P8i3fzE<+<8E-L*(Yngu?T9!_H+wx<91 z%0!V+dcgwvRzG$qnf~yFn=L2A8Q3>zG;uOJmv0-`s21WQLA9;h)zg)C$okXM{9BgX zREOzfxxeiu#<#K&f)B)^lG(6mSnC?yN>JmOhO^rDIfT-Jq5pX|KG*iSRrXDEchi`f z@RNc}KDY7H?`sXudk+=47|?JInI*-zzSTJ0E3RAiX6?wXgzD zk@S0DutaMZ2FFOCq%iD%dM~GL@LcW5%Z)hHj#?5JYPe9Wov@7&y=v>Dg=PA2O1ODU zfn3OS%nO#||L%iAlZgD@!C5m4Tp36`wRL}1EXDcvPQytJqkNgMGwzDQq#au~21p+L zLFpLdNv3AXnn1(Y#fD1dBosP!=}vF6A&Z#hLg zAl9|~qz!J8J~t6_p?J6<&>ak)29wW7TEn(i8aU?4?`!YWqIFF*+&F%+dycH!Gu$&A z_UjN{{yN=fM-@h+dOPQM)eJk?%PtEsIj1t~gv6@E zADOD0c;5iU-Xn$h0jp;hq4_g;*}3g4{O@-IFp2e0<<8|}Z#|iO4*^C`1+8x)iF+V& z7tI7)6QW|ztqtDhx;fz5dt_~7!ma2}W9L$7p^(fh5G1kd`R;iy*0bKwiI}*hZEL52 zpoAS!?&=<~7J)nPkLaLlH8j;6QqW5|o=8<(t`g`%JJ88%xC?N_aXnNlYYAXuu|g_O z{(+S^t~&y3=!>5NogwmuXUxTrwae+l1#yh3*_zOD8D3Rl5n=(w)YKSWf@)8N(nHkM zN!g9*5SLU56trJ)Nj$RKO#O;{z&y4l&w5huu%Q(|mY0x_`7u0T z+eC%01W~l|KZtfZ#QucGoCkXGqQ2gqpKbHpS5R_C0(SQidZ zoSfg;`Uxn5-{3bGQDl7b(DqDXzA8RnH|fb)BWw`h3$GaG75*XjD}$)U8r)=aI?6LX zttj5F%>xcD4TSzY4V_Npe3>sYUg@uH7`DDJbJFV#o*$#}LbfD&oAk3$XRYj;|0()3 zX`UNCk07i7w$%#$wE*il+ojrjX1n2$ESD@lH$u1g5FaI(N8d#-MeZx7nYk}$$m0=a z62!}pVn%(RD53bzN#`MoH57r?rORsE4Lf(O4SE$;I+!QaJ_xQZ>U=KlzAL4^9c0rq zZWNRoK3G|y?26(=n~82>?YlJcpwA%7dc~_GVmXu)J+j17-*TzbR@2Z}?5&M^BX#J% z)#g6UMYkPdaj6BQm(DV!yErgBbp91x@mG}PF8+tzA3QSutIT;Oq)yLoY5TKWj4Dw5 zQ*>B*^To676}0{Nj9jHi%>zheaGD--xJp!sUiHLdcSQW1fFKx8b=gNR4j{C%-~L04 z+`s)S+##B$$LLyIh+5OwMb#R3Vm|%ixV3f+Oi(eptt?yXOPrkKIZEe-wZY=S6K7~S zQbW|)|D1W9$1ykw*y^W+>1?I3f-JZjarZ<>e<|e)->SsG9ib?bpfs|_CpHL2hnlOQ zmTj7tSUv&^<+RkssKZnGr2N*8)SR5&(X}!Aq~kxN8~&J}UlWPGz3rc(2L#1nt=pZP z;iW%J8>v*>!kXWE-f};YPw?{CoF3W^(J4q`KtN|_#jsWPdsj96z% z9NKuZ{?h&*Ql1AX;lHTl!j83_J%Z39icp9qE?qkrmG`>RW}g(8L+Z4^KW@P+=)PGy z>ISYd@gEZZ(P;Z3WPD)3?7jFK1f?^XV5!~A0U|I(%5jn>zeB978?{|Ha`3hh6*N|4 zqpYys%-q#Xt-oj{@b6?ib2P1=)_czmB08F_PcZibUpKWBSy>Xn?-mv^LZ?5Y^sF_W z;NNlScs1BGGKKT6YmVI3!s|j2;HmJN+s^)WDbvs=LU@ksfj0f zCs7q>JYZkWfBzrLE04xI!0lka{SeZNR@#>DN+sy~deqfGp`v zWzC-u>hl!VMMzTjt9wPwAK&JEb(zYqzzI_eIdfGxpPf*3!8j~L<3P0CPxld5#F^D| zMwdQ=**Db7IHf=5j4oE<&z&>?fb(R0BNyPhnNcPv$Lms7s!CkJasSBF|9<5YVtQ+% zqH8Cn7Iu!d4&|YIoQP?B_aD*`rO&r7p#pfO6L*L&Q0EJMz|216Ng37bi1wB%=D!5= zneVK_c`5$a{6$V{iv#kY?qg9Z8w8N-e|OkF-1X*3G2a2xML;BY4%uX;&v1O$etzyI zy1dOh8rAy_8r!-8hNSj3!)#m-Ph$=3GWO8D#|js9rycHH+P_t7>v~D)+4$m!E7m9& zwAfJ8^@s)!pzt#?gnwEi8qf;$oQib5AX~<1e8+QYYBF)}8R~hy)_zakydOc3hj}&| za8Uh{*0*h`QV>d^mtM>{e+uF^uSza8+nx5Ku|wKv4Xa}vOvjAWQ;qSp?Blk!9iXiK3fMXDyb=`<>cQ1&hS#J7Q|O; zoya6!$Bv7&ik=N4E7a!rE=UCIJSvBL^su)2PIVNoIhA*CxBG=4Li0v9IRfO{rT{(A zO8ZNq;==`VQ#Fw84O_HwY+^Ej4kk{Gm>tEbOV{Bz5;trnYB)g~szyUYfDb)U{ znkAgA<^5ij3BBnKLpJi`0`5$Y@Ch$E4M~Qx(dubUtHjgiwz;Kld42273vi3$$8?Z6 zf#-p$WtsE(bH0MDtED>=rW|S9+c=KZJ!_0G3VNO=31zA7qXH3o8W+NL0Z6v&m4(C`9m-y(Tnapa_nycVR#j;Pl z#aeonwyvEnd6Fy$gF>~4y}~suA(c7SswWRXF?Jl zgUOLS)<%n&&L6f;o6}Q7@fJ$dgs1HA7xGKH*bj1%09w|iB*Q+p4}rXyXKrn3?*O^yG!@mNLFCv$G* z(bbdcz3Zq@RQ}+EFkyDtWtMrtF`Ka7c=%O|9j~2GSpeHai7{C;4s8v<)icM$MVBjotZD z>>d7Ru!302`Ji_pl11pJy*?dkhZDyLzxGbUKqx=+PA<|jS3ev%R! zedcF0ZH$>1)$bTbjM+eXxR=;uUgJ$+&~&Zo*a_4PR*#x%@9HO}y8hwkSMig~j9(hM zEAOn^2x{ISr>4^;d;|GBf<*r7wpXboeuYDak?(>{T0)JD9M z|5&FW!*Ug$f{PmrDr|toB3QE;sLsE$^RoKTljcPH`%^10gY}X+cxtz^HO-(HKLgzp z`I;F+=aixLO5h+#=@qU|Nh>+F86Rz}7-Ki<6>2PYVoPs8CZltVG}5k-D2|0)uw&|z z*NR%9^=r&VAiG`~DowcHr{c|=4Udoc9O>EbD<$+H=2P$xcOj=|+q(cAUZ7=z_od;- zST}ol9en1rCbbp@|Ao8R0vTM|L`l!i<&Z{qqKb;PF|u*h#5z=H#*!Am9UI+1!XLBk z^8%*(`cE?11iigJtoR6VWDW{bjAlj8=V-U5rK)dE%u~DY;%Xv2Wd{eOnyS&YVqeyz zNC#y6r4AyFshm39X7=p&jd?o)d2{^=qs-SbdbMv^&<-DlIgLLt4e%{rRmW|K0c{-P z@NO7hG_DnVnSP>c@7@t?{p&6cbR@);&Co;Gf8g%MUd0jFFAw+|8EcCm_ul;u3SQsu zWDQs2UpY*X7T%SwP($H)>(BdCJNDUg1M9__vG(o^;S-R+to7|ezxU-gt+`C-oY*;! zGxbql40Pg@&7Jvz%M~+?-ixrsQzNJO?|RR)_cp;|arMB(o;>Vv6~rpuTmlT7>fOtC zCCpQZ=z8nKtK^C7|Gu?dEA@8W_if^YD+FC}I+q67-~H6@Y;AzJ7cmFrQSN2eUUUii zk-6Trbv4ps)fjycoFmPtt>&CTqfu01FqHp$TSyH-Q$nQtUI|Y13^^?Bj^AoGgjRhd zvt~}KMTimO^FCf1{CbBI>X4l6WV@rc4hVoHBYIy{53DYZ-Wh1I7UVXv-JUuo$}tnS zB%B&c0jJ&tqeQ_)NXJ)XH|NjJV8;bgMR~;erNiuQ{4X)bNgJX&8Wf(}$_>GvRV-#? zzDoDUR1H}~IA#RnNrNB0h2mx3fo8VPP=0lWn5=NPt7jLK<^jp$WLwt#>?K%q=?dHI zsWeN%8BNX1o$VWTLsTxZ)1K4Li6x!oBh94s7z4HB6`D1bN*+bDB$MN_DXael=nXW$ z%@v?*o+n)N&gx{8s&nU8)sf}heIRccHV@Y)oIm^azfqW2evXvRHsNPeW>0+O4QK&z zBg^#=k`JJnjN&@Q_M2&1+Hr<0EaiV#fAOeO?~JiyrQ=Oi#QvG7eE!80UZ5-3o9AH7 z?q_erOvqZlm#+tkV$CqUXp;y1xoEl4^u`$dc}t@<%(Bx zr3!FyINUf4+IND@qFT+z0+wVX>NN`vlZ5yQN|9QFo8wAczPeM~zHeqSq|oNofgqSp zYX2ckIVaEJ@$KaJ{D&kUQB~|*!SO3=3%z}_J7Dc!TuxSunv0N=?UyOWWbX-zh}T_% zy}lAqN+`2CKZs}NkE>tJMW1N!+KyXFu|z+Df5t9~t?d%V4WuKLlc1ZekiwBTE@YKn>-)E4W zt~@*Tp|;ubW?Ntp*E`Y8Tz)G=@p8~;V9~lAf)iDI)+pbSM5bV+ncv{QD@mt zJA~@@-OPsLv5?0}ftr)R-ZMZBHiQ@ki6mWSh)LnSqsOd$FjXqw{`Pju2W|#l*U4!7 z=}eYfZnXMD`s6}MAK2|;|89sYY!#8+7GTQz+hm)y#kTEd7ombtk;*QQr~G~0J+;dE z!t>+J;?&Xp?DlbWUe(=BgE$bhCy`zT+L~qP;qmk{tr_ztG4}3R; zMXka5d`>Baw0k=4VJ(DSPHzeHA1mJB`&kd3W>727G*3;ILy)dN%yS}+?L>EWhW~QYGW{V@&AK`L+;BW4{VJ0YYtSofaJR^?a9i z2Tq2#2xG}0=IY2Go`C@5L8$pjGLayFJHdq}C>zR1U2t{nGhG<4EeF2i!!izhRdBqY z{tnocBTL&C6vIs5UQSb1)KH4<(ocs@Pp=oLfch8j84r9ct`n!qD*ezx@j=r(V5P8s zS%1HN*pbW!N5c;NvYLXT@em35$IOr#0doGqj+MNla1$kOELpvey`ssn^|wT{`Axi8kHUTikB?1K1K+}Z6?V5Qc>;A$BCO?4%XrZF~mZ0p3Qa)zjxOGrF8 zd|w891f2&@$hQAjVm~Ddsr))?U1*nmi2tk|avMT=Mgr8vDe zt}9v)uC)V!RMZtq{CSpEZ7$7hjJgU6?=U1qvVv$#K2lWIA|P`Gy0H50j*eUg@P^^k z^9UP`q9HwD?Pqxl;+NVO;efU*_3vq9Qoo8PO)*#IOC62uS|R4-=$vm5;V6G~HA6aY zU5a06m8vAR)}d{-(AinR_f03EfS_rDe33n*l*qgFB_|iuiL)FpvA?JKfwMmDs?YMT zv@}ryii}G%qeUa(`Nbb%2vf$(x(SBpKFcQD=bWlZk2?~QwFo@vd~ez2t3<}R-by0} zP0b3<4d3^;HgULGH&dGxW-`U3YWgiU4yAvx`6&}HfB+mDpjB0BoFl5Lo zD&5AUs)sVUm+V2yaQNm_8y&r)nB%($4GqE?Mt#W(-Y$U@JMf^756w*`CTeBCX_eOY zNWY|OC4-G`zhYvV={0_x57IUqmqF)s5UQLUG(qM@2 zVz0_Tu^#Xs&EMoH9ApHsb`dDKy-{q?Rd8~^OAbo4i`;#%lCEOCzhQFJ6D`W7+$$kX zTMOO$IA)5Hs#kKU*?ui*hg!}OQP7~(JqUuFo$Mc9N1otuL8GVkLIDC!`X_^+N@0iD zw0rS#ri_rc+&jt92Q$N58r>~@K?n7J;Ce;lk26L-$)y!WBYGks47|HMWvu#j%RxW0 ztnBDX*us$ehUmI8-~6EA{#R`>@2Og@#xe1eFAbR~B&YO)5B_rouaaKFc-T`MHh?jC z1&+wMv(P$-XO}dT#}|rjZfNJXBOC!J>d|YW{ub=TX8mwj?_}LWRJ?7}|F`yX%U+b0 zUFw$4T)Xp|QJ1^EML*VA(gR`^e@eXAaAmpjH0@0yHBTlp$ahgKj!r{K-j@#RH>9VvA5-#?<;GN>Hfs~F6u zk9ZN~OMipvgK%T3&mYx*lrvsq?DKSSo@@)8a3-`!yJ^~5Bo|0M0=PPkW8297*XGBv zk8%7*f?dw0!qg|4s;Lg7f*;WzPXr?urOqh(kIK!4YtD(EIWouk>sjA3G8$@*cMPj! zTronVUl^>ilPen&>(PRt^>nL~8+z1Atwd2q)Ny$!_7 z%?~u!=!M{AiPzU}O;DEzV0EM0vrctnB|dEQE+_2<@v(}=tO`R$ZQS;`fYop>J~?o~ zKO-}^E>!lw&5}<}T(TYkFqXoz!m~~zh2lm0)i6h4VjDWX!xLkSQ%WA0_aj zCsJJhRM(1*s{jGz2;8t=4yuELo9g)wgE@R`^T-VpMoZ6Zc=&4B0%2p`p>~0LDzBF9bX3%5;{{}&P zcSYDfVz8W@VgUso^+El%OX9W9lGl{H7?hF!EQZx!)NdB9*?#j0eaVj5aQumfyDzz^ zaZK9igVrnbke%#s$a4=ob*#26do$-mC={@$sFm~1XA+O!#S3xvCfEk^dq^%+bM3hyl}ug)YcnQg@rDWBzH(kpu04=wd8}}Be0d`f zN6vUxnZEkv7DPYnfH$UTs3@i4QsCnDD!LBhc8AT^Ljh*6j`jO_F2{hR{JIU3ea8oQ zMZBk_3#T&oVnQk#l6lzKct4+QT|?B|HERB&l~O(8p!1BrfB1Ca78p2V=CB5vsM4r} zCK+TKw5#c;G}0%2iLfQglPAzUexW9aU^<-P#P@wC;`s|8)DAZVh8T0PLRGg-lhlA^ z;DjAL8iJ&_|C?6@h?ui9x4(AjG+*hZbsKd;B1NxqDdjjtL<#bkLf z=oYASvAN;^RR#{sgL@&fgQf_e3OlSSX0mn{8oqXjVXu6UOV?#wLMGc9V50oCw_bp? zj@4`Ckcq;*M_5C>3vt3Ac3Lc80#$rbg9H}{rsM}s88a^Jm7{YUr`oDSc=m=*u@*>g zAJmA%M)B|w?QQez%!&`6QuF><3(d@X*PJ8Jh^M+1RL(Y&Ctr&-|J5mG?P8X$i|8qt zeuYcMWW)JTcwmkyOMdgx{T=LJU3{dM<18CtxyNB`+znuHB6;Mw(8pJ!5UTa0aC(3t z`QUtbk2v<&NMp ztUE%e4aR@3zgjlaprOgSDeiLsp7;^9+T ze>L}T%G#av4y9Cw7gE=luK7sJ zlqbk;*zb;3DiM8vlGL08x_P{WjJBXcnst zD0Ot+&m?}Bq*EjQjjC7@`YrM+64~w)uO!D`^;?!H+OVr1d~F)+DUGYY8<6fC5_h^45D5~Vi9R;=I_Kzgzz z^)BP+?oiajLR$l|^f#X1&1@G>98waMfQ~2Ozl|BOhr>F#Z17Q_P1nK3$PzDyky!=fS+B6Wj_m zg3$bD#-3W+Q?7)IdC|NhL_MCuBrCiCn7a)Bi=dcev$(36uas7k1|hTB#RRcS`k;19 zzWGibz;yyT!>z4AsXFfxfA3YeAE!D`VbPM<6GaQS!aZ_HNvA@Er9#I}0kpuh%Q-V? z!RL_5V0V7Tyj?TyR_fUDF97w0An^cy8{UZ+-qZhawD)sflRIglotmUS`A zfd2-i$TrqX!?Ye0CCgp1Ve4Y9-Am>?d=YYCkisFu8if2d(B`Kh@r+9-Uq_(nr(luh z$!5 zsO8*~193GEa5I;=M`^ zdA|fd*eR)@6_s`P+dJh8^uNKaCj6Z>yh=<#?-`nu+dP%afz~iehQm3tD^jv|07UjvGPv`(?~9++o8wO zUSt?kEONb3c#smJD$PHflk($Cln&a#=E^;ynw={sB@R2|WTDXSvr?xx^O0;Kt8T5O z!ll{IQ;&}o>U7pirW-?3@^OxuSNkq>EJv7$r6NS7)JfDhvA^ComQCRZQ7hu%q@}wY!jC|G0K_(LUrFHV?9VSX zaksRY;t$iKNYbU4sfjOH`wZM~CdLFO#m}JBwxwGFb7?*`RC|bMQE}xjneeG|80+Hu zcftZr4I#7-nvzJ;bK$TRSgQGSF8`Bj5!}+Z^|?9J$yM6n*HgK+3iIk#-_=2szdSMN zQxV^%aEGOEVup(=X}m#QX4E-0?POI;)pz^VtShf5_ZIldX%>0xiMQxSwzvCCL*GAD zEHHRZ(#HbY1jW%0W#HesDOte#R76LCf{9S2(|sl-*Rv}%nZQ{Z>2>6%So(6Vq2G;8 z!!hCtAs5Hx35gqO%woLrGg4ED&L+!u`!j)UR-O8ylpViPDd`<6j&+)=@&hu(zAY-A z_OMuY3WM*0uD9Os7?jZ-+a1YUuJ|Ao#!?RLvs7I(HHPRLpBH_0zTpFYS0!s$c-z&{ z0*r8_p9%T2K~`5&DVpZ>ORgR}BFna9`dEtnGQ?WLTBECb!Dz?)+zL29>=iqGF{PtB zPd9~3?(x*R_kKiHDV=iJ+no{kDBGd7{Q_XWFfyK7cMX`x+|h3Falj`8rviSCrfxS| z%I&1t;u=@EpMV%bEY7n+>=*A%`DD6({0LMl^Ca5x zPlhNm?683)_n=B>afPAzp5uD&XrkBz(A7I#&c7(XQBKKBNIqovMKLkuuq>AvA*5bC zHs)VKd-PJUn$wdTFw)~^3dN*oh_X)q&<4APbfx+z-@qapc7R@BG5uEFKT938f!4HN zFFmCC*(WjqvdCuqQx)4(>f6)L{~%mh)y89)9i(oRS!$cP$3kg6IKRGLm;bglogeku z06S;RcpFWUHMkKA${NJhg~ffYWKj(leH?TB0$3p)R()1wV4Z3$r5)tx^ACQiQM==s zFO~r6Hutwc-J47uo;7Rfg5A(5{`ETOhXG|!JBYTcV?+qpJN0Iw&HA0sx0EZR^c^y7 z9BGkv$B$QhcJin;Y1UA0`lYzU^G}*3okHYb9T3KP@_BBkvuxb>GwrVpdRFbpYV{u=1-Y=-DR3R#iIuUOz_ zmDT=N4hg$yjb}n1vWF5U{m*5oO)4LjUY3V=8GmCNJRBo*z40ehz_(TS@ z9t_X~7sHN@_k35gcKf${TdlKft5pjX!df#Oim-oZwfhVyj^Ad>oF$D} z;Rd}V#G^1lA#uP$bj?F4H9O%PFP=ZF6zq2lI$hp?vdu~wBJ6-h`|c|Tdw%%S{s?EN z7oYh^d_Wf0hOZ~)BVxzSGud)>yqNt-JusZ*Z(cR*F#Fg&tMSI>`(4vO%}>i`I|)gw zxetOl4Mf*+9=dlc*D3| z>`qdcs~m;j$GBg$>(e9&h+N6no0D`50n?vl}?Yh?R*GftHaJ>YQrbAjlTm* zF5-;Y@73te9GU*iN~h_@jW1zJC>d0K(d5PRV1xXs6phkEE@PPzr2cq|)@&A)Q_3L- z{?pWEw5CP^zpB;Fe@&ChZfQoaH7{R$GSi+Ha@DXyR6NtVKfVHTtg(7%b+%8h=0>RF@s|}n!A8Mfi5S8y2OAK}_oC+esA@x6)l8!o@ z)5radT7SkBOI(_1hl97&Hp)BIy3-nFN}?sj61PX~*uQ5m+TJ%KvPWkqXRr;};6nc^ z)O%m6=wZ|7V(<2H$}B3xn;K0|M{6RMe65-j_9NxTp_<_^E4x)F^r8CnEmN?u+F__; z1*?>q9s*h129=cmTXl36jU~{L?8l~r?e_!^N?HAY9+d`OQ)*Kz(mWK^r zYS%32h~vwwUc6-ES9i{0it3AVqQVA(Hs+_i&f9X&|Bx6~yqQ=s#(H#B6drOJ2pIcQ zRGI9sX{;`X1YuKx(`F^NwIcR{NVt}kojiU2N6}SAwbdz$q+vF0-7v zDnY56i7qAX1#ht0r3)5coe?+XMbgxmwm_Q85q4i*JXx=36kW!WLJUie@s?^mucJaD z)~=jhV%KlxH=%k5)K?=p!^)~*Zt7tdX%XDbjb@hEm1gll#EPRe^RXp`bV&4* z=l2Hc48n6OxM13prU$m9b7I5kQhVXJZ0!CGkhP zwV+MZ^@2kAN!8%q`tFrS;NricX%ro_mHu&~*A?M+&= zmv;U4`m58RYSRK?>+e4#(t>PN-=6pmKKpQA3>zs;WK05H8tq%p^bWElatPC*)fcK? zF13npme*x9FTy{1v}`*vHSjYD%$n+zDzA|57IM=DI8R8hx`cuBpiu!E5H#i9u7v6J zfQ}dA9fhj3GrTz6+FC65boZM7PKy^6n`^h*rY-^T^68++OdmGfU!VyYSg2GwVMlTH z>1F@T@xx4t-^xDPQ8V@ZT<>+>(rUaH{EV>+f%m!~-KhYOOG5yy350s--mUgLJA3>4 zc97n&AupjTnpR<=#)mUO9qR6wer{8?gq{9^o?)_TB{Z8^H>uA*Q$_ye7E?oDGIPzMhOIXOko&?O z@-J!L>a>J-=(^yCOvJ-~2t`1iW>_bb@%WZ4AXdvSMwMb(*_h}2LT-9r#5I)O4E=B9 zj>RX7pGCXz^7}P#bO`gbbTq8; z9xF^_r(A(MAOH$fg%IX-$i^DA4s>@yViIYM<@k6|XuP#x1U%A>7|4MHdJLU2fpo5s z@Y`T=qjHs>Qh>fnPY5Lt; zAEa@fzK!Y0?=`#Nyjc;#{}uA+}qEK>f{ipe6YI$#ssWOF&X zU+C=~7V0d{ME*85jZT{CI^hR4sQ4dxrYnstvG8I<9~TDSC4I09^ZK1`s4)Z#dmLtGk1TupL3_JQv>Xi zfxhOdsvd{_X+x;`a`TMFab5nKJTKTiKdo9St|d;Hf^R=!BCbvOxY`iaMhGWh5k!5? zR7Q~nEa?95o%&WS4UjvIAf5!1 zA0waGso))7+ujd{s$zA`$#cn|Ab;C(G7i3DPXbbC?CGoWWFSYy3AH2Gz~Co`%#0UN zy0lSoIxER)n4n5LU+&RiKx_{1l-}EoYjZ3lAf(2@v*-1?xeSoVLYX5^@zL2`UZv_= z9zzkd1vF^&hSv?@$l;$Y`KVz$`Lmro{CGU``IDkjN_fB^iE+c^uYbE-mq3$L%i$5% zn`V{pffNm;8rpjsB|BQ@ulnmYT}k<1IfFQUGg+Kq#oNqzmkL}6=bM-Ltb0H=_z~(2 zp(03+uf&N#Gq|C#&^1_buhg*|yVz3^GRK7iwK~=YqTT8azBG7Ms^jUMYffcbkB%eh zF?O=9a5|;RhMI=TzS%-Mn>tl7Whn}H6w`Jc34FV$kPsxw_~QOJI-*ns*)9U;D7lQ< zJUQEdVnB(9uxUfonSmp8a|?8uDBe4b043AA&>)LfY^VW}0+TVGdZu@mk~Y6ocF^*5;q zH=r#qNtX}>{5cjymr(&fcJg^R>ft!3Eq}TBVchyJN;6#-MWUm;<2LOM8PCtAz0Gbn2dtR)wx_-ybPtL<{m+vH5b)=i6j(rz01PCPwN|@)J6Q}xA zV*dYyCwZuxqsXWB6II%Iqbq#^0^D7yRZvH~Fbyv=^Ler^m9Ep|2CD$NmbGZ`({agE z3j9`Mhl(mePETJPTTP)6t6SR+5ZNa3ZuDkU!O=6dRnnw(5g}Q*snP6!+0{TEW%X&! zsh1|1>0-D3&NVhbV&hN^{wQHi$xvABxG94InSDEnhqRM2%<jS}M^G8vYxDJawtQE)#&9{!QR1<$nnD zKn6JPhp#7uUE74hp$~h)t5nSeI#4#m*j0!@|NcQ+UYrj>leTBRK>n)ix*9D`uBrOn=e{WGl_c5LGOS2qYAGwUR#ER?#8F8|OxE0= zpWw6q>~m-n2o47k=4Vwk!M4S6{W}XrV+`?Wk1n!3Sy0F%5u&RwEFNQMCqk~DP5QOr z$;PwBw;UI3oA%qjb>yQ?l_pA_>kO5)U1dM8sD6R%fulG2)kMB@GeECnQ{U<_7IZw9ni zY?{*-S2fKAU^LV<7uf9&_DPYBG1FDn$|+#^y_h;>%!w1B*(Oj;%S@$*dbi}e@i`UT zikxjzWR#(iOMUMX?{=vdonLRlvp?jDmPA*)KmpjR2me}`r;$uN-Q8oOp}x-F$mTDZ zog)ReYk`5e-fpb>4&vIyKD`^Y7kcM7tIwK6-|NNsU0b^eF7x(kawWn2HKYpIo=*dW zkQOk|46KlG1DiO7+tK*VbMKsO^vTu!C={qxT}>3c#jjmq$vs04^X)7x6K?sH`$ZA~ zG%xD>`~eaKzSV`@gTu1COW4ef90uzGu7t@soQ;K=CL?ws1-CYx^fuwSZ^xX|tS=`Zt<^C1Ev{e-H z2wyumZ8;`i_%X2Og2=wl52Tcx7tLQ8 zMBLw|TjfD%!AP?u#m}Je$m4=Rp6zSzah|R!wlsMh;fPxMr77sUc)roW2JpH6-o>5gm^)2Gsri9rjw9QU~rhOo0x9g z+~>5FZ?&=M>C+R}IvZEVo=11qrjv0MmieLXVe=|bR!9shCCeFwv9Xd(9~xblR*+nN zc?9M6*xn2AdCMeDl=itko0TB3zJx zr7fB)j?U*mur23C%EvwS)@=&?#BDZg+M%&}tpLKfK+?FhFIB5xS%1#d^`xIVXzfre zgas2VR{4$5e?RA+7FYTq-)iFeL4x*@GEH1>C5*ppbv)MVgj_>%J7g1%J^0z1eyCuQ z6eiHq0xHe!=^R^pG*RKApnl?-F=YkI%y@1)nwhLU>=cR=52e%d#NS=WQGoo*jkiO&1sD3r^ z#lPN|9tWrWVmbH+L_f9%@++MD0e3>q;@z;4=WdbK*Zs@xm({he(vh23RU#G!A8h!J zWfOy+pjjuBoX`wYczUo2Nh84%S+UPL2hNEXZL4EE7HZP@p!$$*da(S?-Orzz>R~Kl zd{wX?Ay$Xe%t^0rCG<^|e^r*Ad6cAP?{*jUQ-+i=v=c5H$a;FVPC;K!&Ei1?V!kU7 z8RemMLOsRa{p|~_on2Y$P}`Yq2D{qLj1BgQhD@WcRXB3+E;U^QH(vNy7dLaqssa%Q;tY^H}iPTh!9S1frIe*4fP3lmZilA|d z{F_6YcC=f3Aaa;f@$0J_OF`Z{{SP^);g$ZFHFVJsL;e}Iv^JiItv<>coJRB6zOU=n z`k7woJd)HAcw$|X+cHGp=gDp~H%dIcKn-nQamLURU#w}Vvp(nwtfAWUeBW{)hFwN8 zDvn0i0r{f_@82fGK#JEG<%E34{Y&_GGVmyJo6o_14;AxEoYw!rH)+7+i71Cm8a!@e z@j!^HeU6#M-XvAdT|<(E0`oe(tQJn0-o^K%^Cg1d76F=I(gT;B)pvytT$;D1%9s8=tB*o+at0T4_ zil>>$N?FE-GGFS(l1q=++eYczkJb4?;hL=J3d-uI72tClR? z*%*pAeD%T<{GfkDrE$|7faf0EykUE=m^o!v5_@HeQvjMAfJ4jRSgSF)`ulf`-`@nM ze^&otl}!@8#K0l?<;RCwERJ^_pRjXlJ`IG9DH9zs&I_!sTw?Di)S7eDxj$~pXSi@R z^_v4MX4prEt4R%Fd4RZCrVw2H#+X!-ZpPA+y;xN-g_W7Xvu8KZ)A3s`FVuRb*aDo~ z6he!ayrKzS+s|{Ntt-=ArRm8w5WUMf^jPeBm{SSz^bpJ-#(s0pD#=I>5{+|VKj3@w zfh)Tfj%Sn?_@L6$H>~6=ibv~w%3E4NNka3&3Ovf#%pMLbsg}LT^_T0>hWcgkF^cg& zHzll_c(`*ucfnbHIq((uo5ETL_esgDi`|iWLWmUKKkIhn{dgPpi-k!r_TxVVBT(xw zrT{UIA_+>^2^`Z%1G$LGK@QRw21xYkpY)bEY8$34KOoqs;WgsuC2F8{2NS!;AxLxE z@$hL-W>Myt8N+_A7N|imhW3r$kqA}#i`g1Z{jEj)NNKW*E4(jH z%Jkq{p3XA(NmbPMNTmDqtek9t3Z0r1)w$ufL`pI$OOJzer!B$g3WzACJ>?PMcb(Ci2$q`BjiJMgKZGupw zC@|p}onT>VBmd*btkI_mh6;CZWBAVYEEZxB)B6un(yMGtpVSy~4H)7uJiN zen8+A!J@OPbJZ?UYw4O_Xhe?B{qCJEtra@cJF<2aQ*n0N9 z={My(pX!xnTlxH;f<=UT1Kn3#U=7xpQ6@RpX}faNJKNiRY533jflpJLPIDkM`y=X&4V#klBgnJ>ktH?D3mPcL zA2=5I)hAm-_LGoi`bHU^HGWQdv`dH@A^vpGo_xl`@Je763;<%{_!(Yc(_VjmnGNPdskbu>COC+-wAmOENT{Xspy;rYgNad4B=V#)pia8^yW1UFDps*vf9YhS$gKz6plpl|y;pUgvXt6WL*> z^b#Dfj(uH7Q&FX!QU$dG-;AtQT%YZt+2_aKF@5O`fQ%H4c4j2*M!0?EUmy%5am-f& zN!s_7$k~2fx$L7qrZijR7geHpVC?!z6?lP8U@*yaTA?A5z|XTeQ;s~iS#tdKI0e?U zC;uOUDa2(pKP)4-|Gl|W&K+~MZ&IOrc30ioRd0_cO}v7>V_|O6&9L^LO;>fs^T#R> za0U}PF@xp+SmDtYv*ptGvwW^_`rui%!)}ClMdn(7&8uJ6AbUbR2oGVG$E8Rz1L*zORcvJ(* zclsIHs}{uC{sOYic!Up^@_Dch>=Rl%!VB1XeEruzMa3=N91k8oXtmrCE>?!h%;FrZ zG6yu)&WDD{c_%?dG`KYr)%#|~Oozpl^0X7Kr8ul6sn*mE(G$ftH@-RYeF*vOd{$CF zw!_mpJ z8YHVXDDd=XF$iHkzdFC+d7xf5S1~%lTq7IO$4^YeiCMMyZt?MT2VMVE;;o60_q^B= zAduL(@XcKPk$}KkGS`%qB`#t{zRKuhn>6x1!Z@456R`Jl8Akof+F1=e*^kAOJ@HfT$F$$ z8{L)+{5du7R-Y*{8c`nnHh*{+qQz;b#cHozm@xf;H~=H{?%%w54P)Y0QXvG=5C>=u z2sjIG7W9mJ+@-h7IUKp;J|;)QZWl-_|ot4&jkg2o5G8!(};eY=eGw zqfb5pr@4tCseWh1HDk0~-o4vSIa>C6Om;)Nr>+@`r?iTH9poepWU35)nR;`9&A>X> zTocU<#ACkp4WwMMVhUBJ{bnV>`{F!+Y*l$xUOKBBo1;gE;$^XKK48w{px0e&-|F(^ zk^g?EJt!!McNR%oMi3wWN?;~xMl&vjD!(hIoQWO=td1@PbzG}keeM{s)mBz62oWLt zv3!5&odmgG-IZt!pHa4 zuvM9NwjCB&WH{n0{xW1ff4752BgE5@0c<&q;gt~?R<A|BI{6mP`v{FSZC%)VVQLR z)3SUhJ|bc2M;w%0%fdJ-%9?gZBiC-|L}jRUfZC}+J2)B?JzB@(_#|HEPtAcvub8A% zTFQUO+Ud!)Kt-gijN5_W-@3*Y-7Yqgyn6I*(YL|b}Suj}q1bas4 zPBy%oshwSF;@4S%DyGi?T5F*>I$aPpk(=JeDL>HvolY+`_T=jJjR!IYM}LT@6;21* z9?|=Mq&D8+f;fJ6EKsAKM4E(;f9oaLl!t>t=Y4{CjXtW@GwaWtuU$#r-DNkXd$#G; z!Df00wbYUC^_wvMO>nVSkRyt!LnmI@2L`{^Z(nwAh!oeAnL;B~W1Qaq2r=49(lQRW zZ=ObDvS4xSY+@~ex-|VFiS!Oyo^t}z9La*^Zi{`;Wt(fdS zYnUEOExRVD0RZkph;yf^M}4Hc7y?-dTW3+fjlQ4`l}}`uR#axf*%&s*zrieKm0M$ zc$n2PjFf^r!9brPszc2kL>7))Kx0YkRZRw)Q({f8LrnnRXYm}@;ehA?lYdxCsf|SK z8>ytWY10Axg$NXkzl_N5p9IoO`y|su5GBtq+O@s`vH4pLGPH<`bE=iYyzm=;SsJ2X zOno#)#Sz6e`B>icFmc>+%#i}!1CjGi54iw=9ZKsjrfF`RV(k1b*Uc0JJzdFs|7;Mr zS!VU>l{OP(#wzULHioG>>O+=)7xdR4Yx#tGSUOwWK})wEFK8 z5NgKMP&AN|U3ku0+%G*Y(8XoJPoPf~Cok%}0qM^tJ1UES>V)mWZna@Ukf-#B8y4BF z%i{w6-KEON-DJ0C}S8j;&=)u2w1Bh0jX0NPu`u^(RXa%94J;ch|rmS;QF2Q zVva9VTGvJ5#dOCl{1YH%E(A?Kz5iaD@5!GO-4Xg7)vT>8Tv&-0qxpVMVK^Mo95)WV z_Z@wE7A-n{dv`Su^#>ohAi|$cHRtM{J~HaxHg_4JRG1V{s=8G@75(BmDxWVu9`JbB zk-VN;b(+!r7E|kWT1G3WDT)s|Cu$$B6Y9?|1?s$AIV+Ne!vkpXG+TG#A8S-wb>e33 z5ThF0bYrljp4BBi^uo~V2<@&~c~#xWzLu40_7asz6mmwU(3OZKQ$62>;6vr0SjCPj zDJQWfwmbIbIRwpz#={O`JM4-HOH9f*a>RX@Yj#5B;%Xc&axUasQjk;FQ3BkAs0;x2 zi?Sn$N>{#5B9Dd2b+x$5Z}Dc+raC5*)ie;pN3a^GRvPh57;B}@#|*ms7evkf5NO6Q zQ`|l?@~QuQZ5mOPI2FU33=IMMtS&k2%fK2pTsY!vjdx64N;Q&NY3y|Cx&Ah*;ePk4 zw-n>6WSZW;wJh5Vbs%bdprki*^jm7Zujtue7*wne%tNh5UDV+?qR-GL4rm>#_#;Z# zaAppP?(=OKJ~CS2+ha!g*VKexG|?K67yr`tI7^I6>#9K`cB{P%JVgUUJ2v1wi+<^E zbyLAH>eopP#Q5h3o#gx;_>rO=j`mnXgFG}{N;?}8?tD|S)O)mlKtKBt?;#ho!KjBxCFS~7Y6dOk0#7kf4pt{}FBf+7Leoi}pa@2Lfas7rP)(kuAS z6~PJjU~L7|%W2f3%^zs?wT6WNm`E-n~!O;w}$N4xOwci>pFZ!%n2km*CFnp?|Xn=YS4C z7cJSry7N$1Mum{Ac^!e5{W{PBbPNtNu^a0->|f3X&K2#o z@9h{n=p7z9`8!R#ibi~5{OBBMg>if$xiTD_vc2e&k-S=P5tdE~NeZL~uC_P>E}ta{ z^aK9*p9QX>XL?+rNT_`YRDAcMO|GZCn|(%^^&dj&f@hyw8V$tdH1`HOeI8L#d77XU zrxDrwL=@Fl=uYx_uo5O8xw@EferDJpIU)RJ$tZw=&6KVt&k# zdT_+&a;@r)n$c-Tr;Q;!8Fv=5xGIF^S5G=#9Jh;P!8FAW&6~?8It0mxat7pa{~pBYUnw{z9ZZ(7)Z?Pv`4biI6$OGw%(?(vkUR(G|ghj>F}u?+jU1(l);Zx^=r{ z)6s1Dw!65IkJ_z!Fx!zW`p9z(f(v&(+_;X0NWFGImC8dfRf61ZRI`AX4~TNb^VDzIv=e!uagz8U=te@2_>?eOO|O3h|SGf zp6~jZhr_LQ0%RL97WyGz{w^S6e&tugu9>41%Iy`2x*FQwG2-bZN8~;E3D>+NvEAB) z;FQW8$07Hg-h>HRV6VL(&(5~0NIUt$aKabV`;R5Dtlt$~aX!Dygvvo29kb9repW-{>LL?V-& zz2!lbfv7Th|28c?ak_P_Csp;Gs6Ijpwu(6`)C&@30vlUmhX*VhL^oG4v--IaTcwG; zd&l}hhoul)!@+^GPY0L6@igX`g0G>umG|Fd|FolD$mtC_9c7HPe=ZmZnleu<)_?=H zPesAUoSgixN=D$}^=aR4L^LVCaqy@!Cr<{0K2K4P^M;`NRA34(*dEsolsQScll)Z_B3=BWe>~kv ziW=1UE}0aah{xt|PZX94Z{o8dNFaqQzE@_x0#z%408ZH)oIovUFgF9A+2;t>JMY_E z;!>NFxNtLO=o5U{rEh?47y;LUS87IVzXp6{`g^V_-S8{RpaD@oHRDd~(_R-bz!$j# z=UoUfbOKZ|bMvH*eLbm} zy=b<=(!-d6tOJAf)h%!y$J__w#nR-j`SWAVvh7^o?{q4y1D6XPhN+2ezR=fZc41RJ zwZXgHF}UA4A3>l(9^YjV@7#VzBK`f-t()UrPVK)V>I#c~?Ix!?+a4Zduw|}_=U!x} zJ9GkEU{<0CMsF?&vn;h2w^?;{!&!axTJN@3VX>nB)zI_VuMAG=;76=%xSSx?}+X4rK?&|#p&jT;9cy%FJcO#3?qL}zzIahe`2<~uv5CzZN+8r;s> z`H7X^!+kOoyz)p2YZ$klgtmiCK0*fwMrMnphj6!yw;d^s4EE^%AhvaAaZ&5lAE)~M z>k=1ENI}!9p zcpr=+Gc_;>3Xo!Hg7%TBFsFlz<8Js_T|&y_rTu@AWod+R)!ThYrL-t&$dyTHXk{37 zfJUASqRomcg1=@1dR*yU2=7ySAC8b|32~8!)TGzAgW|=M8dp(ab0Z6kHw(#tU^8XOX zp(%=lJS=iwhnM{abrs`(H@H?#P7CLE3Ji<=BWc_t-}R3fNT z&=|miaK!a%mQVb^9Mlw}waPKkZoQ1n07nyjW$K=Z zX_k|EgYrd|B<5!3YoEr`#&gusH?H5>2dFmUQ=m}1^oV~ zZ2tTG0bxz`TH%$eAJgL)6mq#!qtlqMV={$l-T*XB@LNIflbM}5w@Rz2$YykkPdBo# zNU6((K{~>XnmLb(zkvb~?qNXDZ3#ywX?tC0(uxjS^pO<%42xU$wFWG1`V)(D<`#T2 zQ7otpB~*je_bz%*S*-X>@gEN!Ux1F~Wl-yH;_uS^-ZWL)zGm?whr67R_~n0HzCnEG z(2I>4YV=S1@ zT0a;*8*j^lz%P$Ldht^eHC%Ep3DI}w^jiUHtDXeLQOJ4Ec zKK^& zV0J%R+}5hPeP9cXwgrv%PC*gR&8Hr2WGy+4@tqY55$C`oyf1n`VYeW1g)ajnKYjbU z2D7#}@Cf!h|7h=Ggg;bo5xSl zYG)VcYQpaN=a0L>Pn3#(QoGngdI8;|SIu{X{8ehJKMUmTpZRZE zgD@g1cEpaKqZ&Tz)e7^@zEDdFqMHHd7LW8Ise}ig?O_wpAoxFRx(HqdQ%f-CAO zQ>s;YymHk0RHM4CwZw5BD{38mhd-^3i$0evU4&(sg$}N8HiofD@ZDNEa2#ouLF1>4 zO{GzTS!qk!d6K$!U$gh&$z<|5QJcO(;P>os2nv#Vkh`xr1m6d;!K$p?By!ol)op~x z6K1FJLi}e}sqxxkQ{wg1N~77(|8e5VYaTiqe1(DZLErQJvb}+`ZnMZ&)DT-p+|@%8 z!J%j(dmz&)@#nKlfhRa?VGdPEMjoWWTg7xtxHgrlsqDrP zr?U-C6e-01jjQ-i&&nsEyDteBJno}8%OwTdF@q;1lP!X8miE%xzR!Dm4}T?9(&Xr$ z*3f#$#h7&A6c%c=Rs4BnO-@`B**;IG^SwbVMlSY7!Cl+-jSG!^XNZ6y)j)JqnkuPg zR?GuZvnxFX^{|O$*X{lS8#Ll%70#RM;1n??7~BB#2UYJGv)Ks8Jnjo;6YBx@CPewt zHvC@|&?LQZw;FJ!NVm_pu3I&c8jdihOQvpTnp`+1N?;oVSz(oCdt+Wzil1G)K7NeC z`Vxw>%yUOu`?uMLdjxxKg)E&cU43p4bGkd!06b9$OGBK`3i6@fE9_(2nDZgyk{a+- zSU5~6Qq>9XJmVQuk$j(Lk=BN)4&{dWfXu~A_a;s``M06U#?ckVdaE=%M!P%9Z4=ZV zS-sEf9eNH}$FTft3#enMoo^we>R|J{ffAonN?Nvj!Q6qSx{0c{lnmYUXTk1*ESn^T zy62AX!i<=afmj&knI3X2_~Vikau9>=`j;=P#tJUx4(|LEW0*21$qA`HaWEWw^{jb0sjw3yyoFPA1}p8H(XK zIzAMy4%Zi@;B(q50_}11yd6StcFdO=lE`Ag|nBVV6^Pcz8ZR#ZI*X6kqou!N6 zVPC((aX2kLE2&={(jj@D-7XR`qnYsrC#<5@0NOv3K4%?bP48V5mB!hieoN#{m0T8K zglkloxIA__z_;$pS-88w2X z6g@jK9m{MPjv$0}>XGwUo)>j9@K$&6j686ec9B%JGkHaQ@lVETtlBpX;!&+8f`G4l zye28Pbz|zN8_Er9h1D^?HqY*lu!d|PoXKz^wZtiXX9=@I6BMcZg0*3GgWIGsG&MU! zL`|}i>kG>iEoE1|5{rMnUS39Q$Wl5LVFcW8UQZS3RqY^>a^l*~zi~1I&v9#dw?-%8 zTS)NZ)lOPjfi0_klzA+4vDq0Qj{UVDir1q=oqFvl40hBRT^)bSIen?hvlsRa)8&OeCHp%0^cG8_-I!#U}@lyCa8jE2auDb318+i+51P%Hr!OmCdAliT~ z!bbtYd_WX7?zR%@#tNgAYy>pzMR!iYcG90V_VBusZd&EwEhM()QlBzkBx^j)ej|{+ zEAvz{zLM+b9BZS8JQzW`Bce!0`|w}Hb}z=pB=vXP`A6raM7jV$=#2f46D$wxJ49{3 zc|T}v1io&c*3Cbep7-@9ECG*pBm*UPL|~^0*y3v87-ZuTgcr<2W0vpnwVohF8 z#ZSAL`Czv;#Gvae%|o}t+88IVYN+qNabkSStyRRagQ;~_e7d-TdlT(F1=LH?&d9a| zRC(7vQ}49#xj?YW#Zf1shxTw2_Bb-)D4Rjtu`t7GNU{%h<0k&8{nKbWm^!;6%hZqm zLf~nbmI6Ey`UfIq;;=6njr0kEf}>M=e>LWCWpexcSA#6WHhM56$GT6?Y4D4vT2MS~ zCy$5e1ri5;OETY#PmuL>kzIb}1n|)gE!kzKD2y7B_*+}%Pd&jIs?Ms|dyKl~jsc`SMZ!R|et3p?1 z%wCv6_v3#Eu38|PcSt_xKu1emIuxSA66cWOhQ*ibL>xUJ>P9Nayj`YyFwiPdgMD<- z4XA!a)Q(I{SD|d)=Bl41t}s!}lBa~pAYMa-QbrY_9@47&;ey!`FF0WpYm})LPHn{N z6OEhFs2>gEz3PM}zflO4eTNq4WO=`I@$yq+7TPDzNGUcg0%(USeGLF@?3~60vJ_x>IJbQeuCg(AgapM=y;uA0^ zEMx5kFvxh)o&OLvI~aItw2ZfNo^co5aTXQcVN{uEkcqMMm!cvVj(gg_GW}tP%4!yC_yBGxHXrDh-tr#;1K-YO&P-r|9Q^?+lM0y6ne=zz zw~MG+N))5!i9w5buI|PF?0h%QbI8+eEC9Cjc2_`chS;keaorU3yjuFz1p&4Zk{!#gsMd z&3?_$D>_O34`I#vG5wE$yY=ECdY@MRPx&Wjwp(=wQtoxBcc(Hp`z=bf5@YYbT^xn+ zN{Y(-WT?bv{!LVpLN6z+rqg^`LP7@|Y1~8qBiXw5Z8-A>*bS|0@_V0DWHD5fIw0UD zGxHgBzH^Gu<@?pa0)?Ve5`QmLlM=Z_W?S^JSdqG;L80Q#_nJQvgWNLUy9W_i#A%2q zBt2|K%*>L!=)!PZ%bmEn90jk@pFE?51j7+dQ~&P0OcvoRT&8OYl2L~Dj0wQDNcEH% zGmBSzSI+e9O^+li_*>&-aKJl2%Ox7*b1*S#XcvPelR8{IH7ETOX8; zh7=AX!(}x83W4Y7j_9=j=7#M|)FjpI!n)qMj!xRx==C>)J!nw{(qglXYO`^BKT? z!Pg|WV|%(sfmhA-{@Hh=w@-(1)eMQ-aBlsi+utZ7znuFIjXO#X73b?-05191wFE3i z-PEDK9p7r@gwbDCSh-9m7#D^DV1Ijn`Gx~^wHJZ54|{`a$>qXP$@UxsNu(ZjWQt^p z2rgMzAJVWC_c%LXCoA`RVtoEr+d7(e5>%|O;?~WIil5rQ*BBw4CWu!!xP7(spnAw; z@8GDai&;yW&$1GuIph;GiDVwG^QwRDD*wP(cNVD5Txq+&h)U4Z zdz%vVa~=>MC{Z-<3z~9TpeleVVsPNF-W7PAbu8G;?&9EL`QhE?2| zD{J;8=JDj)S_uhwM=^5_IBz<83+q{Hav1=gps6~dIf;5u15um^_A4|k^lXjv!?qrzz*ir4gh(f{N;ygXUbOcPKm}xYcdFvWson|3{kUTkyAxH>Iyi9ZMyjXlAW+eWT$%R82+N;YqqG#sM@$W?fiGEdXB$nw9y@4(pJ8$7IO2E&SEyyC|As()M`LQ@CZ1{c`61e;EpwPNxv=QtFhO{5YR-QM zm3%Lg%`qj_s=nG6$}>;V2aix}T_fiXQM+M7B%~a#NMyw?5qqb7gz2y>Xt@pS7{U=( zECc(oT=|W%-k2c&NWbr2q8wT$^WrC4q_|D&UZQcT8{=6Jdh^W5?fk)fhzz9sf|40( zM7g*xzbs?CxhXlZ5`(3RM*>qDd6|&7Na}-!1XD6x5dkDLPsRaR$Aj8)eN83swb)+d z1l6H`lzi_g8+2XWp!ttFfAzk-IaXWF51=Up!$?}`F z7@mZ5@Jc<@>&@e7DnF;Fx>ccT+2VO@mJ6RpLqk((vv;QnDMlWP=eTlzHXAb6O^CI# zcm7Ri`;e#-p~;4#jkP{wGkoWb*xAEF2%LlB&k5HP(%hE_h1x(9!4yl)1qR^Pl#Tpz z28yg-3bIAiNQajyRej*eOrO9CMSxDI(}_?sdn0T)g&?PiSjK23 zu)nDzeqAu5JpZ+=yxL}PbcXLpkKd~C;&2vFBzB)3Y%NFEX+!kTHFiKJon z{w_XE-rW-WC%x-q?PS^)F_fogBoj@yGPrsTuyYEeIny^%02N2rdbl*1v1uNdIGoc} z`a2H7kJgKBpi&9wRfmFd{{M`=dMytN>;HKb}A+wb9Y z{67!Vwjd>-uo9n?88@yZ>lr;6t-fMncAIu?(Sfv{3U}^rXOgc~=ehosQXd6vM;S?i zGKT^;oW19?7Qjc~Lx_BdR;PW-ZL`+N+4K9xG1m(6}$HZ=^-gGe3|u5c>m+*Dg&DOzdne7h)4-YjqdJdgtTzl|TD-7r-lfJuH zA7xfDfG^d{lZ5>>D8!-E=T=iCP-t5#CHAD_?OoZ@cqiqx9+s(qKl~=ih8+W2F_<86 zN7g#|q%l11xVlz1C)ulpyO5RE!`wnV;>r8EK(&&uNwGQLdWA#N8+aV zwyH(_)u|Q(_Tf*gmM2^}y!l^T_cH${76&Jt6?tdKPW#pg3KQl+T}X3n>S`4$W*wR) zh|EykDJqF!&Rj&b=epj~WMI0FiBE&}!u~nGb@38OB$y3qte}3m<8hJqWQ^%xn25(R zS&G^E`^=2nxyNPF7i$%#;VjMv$!a@ZbxI}$wdO8o;A}XI8pYrr1n|D_nA*>W^y~Q% z+^3Ex>fV{n2tBZD@9}%4aUB+xvWU5EB@^Rl9{p(g|269XMf875{~rXZ=+4}|oHjx* ztycVEMB|-BY0q!wZP8DWGK!SVz;>!){0Lb%~nj{^h#WZ>B(t8mlgL{ z99={a!bKo%nYvx`xOJtapNr^pYG~(FUqW>vM1*FsLyC1sXZ3b;E=dcoul}@s?!{f! zRQK^U+0h{ z2-JN|5SJKv?7cwm2IL&fh7t0;ywgup>l^6pE0W?nNchM_$jm%IqJl3#-#w-LI>{-+ zaPP(Krdm9!D0=q3749D~V9F?hR3zy-1} zvr~Y_18}y7IGEyQx4UhIP~^!~f5$W#(R$p%OywDRRg7^+(+4i^^MGXP! zB8HfIqn8v!_j}QdT-!-dyJ2Uy@vNl`K)Ml$Fe!p*Wv=K0MEe=WC%V&1er7Ebr@=}+opmsg z@mZEqV^xmxE2-GL2#%mdBydguHGV0!>3#tdkZ>=vS=<0u_l6G)tY_iIN`1*J1Ll1iD?Wo&>}uZcD%-Q*nU}Tj>-)Avp;Xopd50WwXrql{k?(pOYd{m zr@p*Hsvcs7DZ}|P+T;wu#W4Bj1e_xzVEKSko^>I&xyW!Y4Er5pFSEykidu(+?Is?L z2>$Yw>q1L6WC^q)nNp_;o)8fIxst zyNX_@>2)Mb5?!pYrW?Dz>Z00*O&*;34gM?kf|^nA-^JWpQn2{{psSry*;NM3bYGp= zA4$a|g9@ub%{q@6+B3MnY*KAKjjtt+@{j0j3)U>ki^Wb_SeLIqsizKSVr4xBhdq_g zdT4x}rBSyll?{TXfP%>l>m|z)Q3Du)P^|Y+F0?fwAKbM%baT;C&Kp)@zp3s#V51)= z#;6xrwbj}?eYBiVTD0HHQM~edH6!?=Os@s0Dxp(ul}`C-$dm zAe`^K7Y<=$)f9GQlw;7u$O>AKrQHpv#M*5)8tqRs@2m2QaNJLOC^tX3YY&){g=*6l zMX&~LMYf+8RFg(pIF#w8TtCR)zoHT>@ZiSg);uLswB4*cefjf-`h(SPcc^lRddj9- z>{i7+WCc2U@J-7z>{QznvaI1>4e_Y4k*wD83R;>{xO#6~>nEK2E}L)!NmWi}_w>pg>S@*q+D7SU*&cbVmF3;Ac z=HkYgyk#jr_;(Hsk6g(z_m!Ml-Tt5-DxQj%E|~2A@FrfT8>wAd`tKL{uW}oe&{kmZ zi$$J?zUWwnH6C8I4MH%y_A^NSeML&dGgq&aTXe#ETlWyuzL(*n{tfi-P z-rfA$E4a_do4JKg>UMR87?@sLs1%62nKN4;nQYA56BXXrN;7GYFNV`Pr}2QvUZ+&& z*whX!`vZ8U5?_Lc|0`XxTilg>F;Ofr|G_NCyK-BW?fpK z6R)}?J(49I8qkj+pT?!8`Ku{^nZGD8?k6*WXxq+{3+ac!)m-)n2iwJ7cScr~H{?un~B?Tl^`|BuNASTwcmoeOSx@(zKWh7&iQPjK6 zIZx(ZbCa3ho8lVPPqJ9I&FQfkKo{Xo=4_+W?N}NTm~;K1=5DCKGVWn)#eu z=6C*S^f1^%6>AT!2y{&hXDwq3R7&ZgUw?j&pUO=@q4`mJLPK>yXt_%UqAj7<5vTVq z#G*|zncGi$=|e9g#kpEyi)if)G5R261$xDTfU?}u8M5o4JzV(T)qyFS)pL0t3diWOiT7c$9U*w z9>IfqbRufER)7&^nY15d_xK2|>q4)<1wM@ibJsGrm8=#V#{I{lX`AJ*1t%L2L`(d@4)>f1TV~`giL~ zrYX*(z)Ym7(=)aZ3_rlv6eDiITuV4%3za^eJ36ClJ z%(5e+ue8@j{KY|V<3xihiX<$1%Ijau$+a?4EZG=++Uqu%j`Epw;C7Tr=zt~?UP4j! zJ<#Q4Nlv9GYg#8(b~nn?>8lrrSMoqD{F>%+E`JZ1YB5}Sd?CFmyMz)sb`aZJYd*L? z5}Xd|?Cb9TlmVdT4rSurd5(V9uzI`h2oa6*RIR-YFWH^H;4BCcp&JelmK9(BpNvCp zv5OrEkA+zlmpZePZ@CHhh6ldu$TqGWY@qge`B>6^?@(F)YL2yYs4{!m6=%i2b+Y&i z*(m)vx~#Su)nQ9T146?Y;DLh{o}}grb)lwO16Xpi%O7yY#2b{xkDLGn8|3?X{Du@h=`Ra(n6*E&}=!TC5tk*>8qY=m%pE;2E$zycS%6q=9*Hw+$H)@+ZE#?VL zR4o(D$rGJ;g*J*Odqoc9)Mdv}dajQ~m|W+!BilI-BScT37_MTadw*ii);C$Q_Z>75 zq%-m)M--P9-XF0OH?2eYeL219|801ej|hN)T!UE=V0d4EoZ12g3o(e4k7N!UDB4^r zAG9pY$ngkmq_AWC;xKDa$Xk{^2 z>Q|ZvtNfhR*A8!^Z(4ssYN*~(3wU<%{(wJg{KanPn;R1~IYoLkha`g^e0LpBlL~CR zN8N9xu|7*4x-rFxvB~+(j0OG;20>#QZ?B64RAS?GQy2_WL#K6rV0r5Tj-NeG{#!84 zG6sOHKTs}dKjjXSEyEuR8r9r988OQ;v&(8%kA@0hi}~-0wX872F95hL)Knt*Gnq%L zAulL2akzP!u!1PwDM<3UuRoRyKU>}?uz)LsOtg)WX>hvMEXM#!eXck^%Am{8u(c7s zn+J}C)2fMoIwf-Boi+u|vFTLWJ#-lvrW0|+j=n{lkOWP3fyGi~qXBe!k*zo?TBjE& z0E-%2Hw~hRD|amVB!E|~@&0rRU6`b!i6`9z7lk$Xt{tIl*WjA`*5jZS*?DE0l`YDk)a zfBs<-o8iC(Yx8(Pgo2Ao?KgUUdD7c{BIlYjb}ZQ5Jp+vjD#9Ki%TV~(tX((RtWh;u ztNMHdO!I^-bAF5_Q)lJ3&fA0QD~T7?$?*pmn~vyt;M_47Z)^6VwKlJ>1&o%qa$Y^s z0E`pPy>D+>gp4t04knXMrIg7@B=EIZq!AcLHarf&i*4mlGD_>RpavUd)JGV_eF2nN z-^-)wE9lO{>&e52S$%kMw{zC1sbkdhq{7xYe!GQ9LPIph53XbyDPIZuN6%maZSjmi z29jGS%91vxG|m{?{17}EKdPuUjb$Cbau$Rpl57$9L`lhhU(j3z9+UE3puaVJS{sqS zd8RVeJ)qAEuqOX-U>?h=6*i-2?C^)&K)lJblK7eV@tq_!tA7!Lt_||&4IpJsP=$`X3FUj`satzl+w}6nU_$G0aSieL>4Z$jh(KyLd|K&m&a})`TU)Y|nx} znkEYlHvstqyDE1cm@CrMH|9xQPT`kuJ=xB#VDSmAwGU|{*i}Rd-sYL zzvZX(7ubU(BvwMg>tVNcP-$5NzTMLD$zia_>|pVu@4?K$I+8Y0#H@b#u6sit?I=Ww+0lVh~RtdDBwJe zKv4wzHoeYmJ=$#L-EdcUf`jpkHl(ItrcL7>G4r#AN}Q(~qb^Vk(+PtVBeTje_NOH@ z@%f?x)4c&6s!)?tj|X=`lMm}TQ>1zoiH>%Fa{{6(!#$Q)^Y_DIk;;&L6K&<${>YgD z3Wx7X+a{fAM_I742(nhTFAEc%XDzco7*%rCzZz-x@>lY z6o^MK5eC<`GrD3ZiP=%41DX_fwY$CjM`>tP&#)^Q#XCx6=H5>fwwr3< zfiAEn+NMvT%cS18>M7H#g9fQfu46?sP?0y16Wb@>^7IqTVQx!I=qjDFIRkH%({gs2MYb4e5=4Ijag`w?Y=gIGYA+l|& zQ&X&{-@C#Jbcvfa*ZL;Rbvdv9)cNh(CrEK(60LW;zGjfj&zZg~%X$(*@-3N98hRV0 zMzJ4m+=@QDD{Vp7GQcCm^T1Wp9(+f7wcEB<;jRoH=euvJ0@x#1RwzE)UTvH%#wg}1e&scUf(1K~sAouy7z3nc z%D+eKS0gMucW^;#sqI? z-bRH|!Xf@oKxO}+_YA8^4eAOH#|9qC|BL{P>)587d&o3^-jZzPu`P?oqYsp7_D?8M zV|8u)ZEPNa=W#~{*0PAK2b+S|G`73uhf|>v9icHIey&Nrk4v|gaNGObPW^Ew{0$qB5#i3~55$Enrv-qx!PTtvNzatg&)MfVQ3FTO(> zfBw_Ed>%-07Xdzga!SfaBUl>*mSPd^*?a}Yo(AB&#bi5L{<59&#(*8Di4loVyK3|; zQoOc0G|e)(z@azpR?CCSAvMM%g}M7*TEs7c4S%|+K9ZK^WX#1vCNpG6i>2J}YbdNi#H^VUC2}w zv0;_jW}@M6-3MrqhJwg{L=Ey%6n=ddV*FwK-L^Uo2vELGp)e`p!>dN3%Ppqz8r_W+ zGENL2{VJ28LXCak0lk!L!W8!77eGEBCs0Io0qh!G?w?(c7aKrGEkFbYkEJYAKNvjE z<9YL><&|lml!l|zcfc8J57IhCSS}Qru7uu!Va1`q*WtA4NB1RUWZ!HMrxZV>D<2LU zi_q<42(J_G_wDE!OoXDq(?4){&frm6%e z-6LxbB>8+lM|Kyz)vvYw+KnCw9@0Fs2J#`LF9b@j(%!mCL){%j-n!pLCG27HN&trF zQD`(XdH_5LJ|WX4is{eV-6=j$XlshFGY}UeW+9uYH#bhy&mT2Y@Z|ticdYQDw_w&p z{DULMmRq#Z!W$aARDNu=5R14U=k&b^-a73qgaShJPoM4%|0Tx8F$WDgC zw8>}6e9`f}t2f%>i&75RQaE*H86XY|4FycR*xP z|7s$EKZ*438X8Aic?Dp()0dIj>owH*%NC=s`M1QujSUclK3p zcdd$oTv%y4<(8t>>~P>JP*6-xYc|Sj$n|_vx7o(sw4~N8^zN@Kzy$R5Lu~hx1cGn; z*O(sXP##mfCOUro*l5mh?QXgB@Ze2CP`OhU*<%s$gg}#sV{!4YW@7Z0Je^lL?#qfY zSzB%Own-f1vFcB3wh&TmI$fz4JX+tQ76cLvFt-rrqm{$ELTo?37+XJ1>Tv<_VlN|1 z+|kMzhm+e6z#v{tdEd&>f4>fbOU+0e9mYa_OQZiV;fwx0Z!>M)OHJ-? z$NOU#%*SFQf{cC0L13L0?oqQt?#eqD@7?AyaCzjKFs|G2eyOfUC zSKdq=-~qu{Q>%)|?Q9>+f5&@D?IgEZ?xcYGqb!Ly%$d_a6sXzS>^X8wjs`QpOtWD` zsQl(Fw#g!~S}ZNk?C0P?>!l;Z&9WRL(Ad|b&<4>fT?jG92pmHu8tm<|WUXHKYP1YW z*h3|V-M*eT8dLda3oEt+a=RtEIjLt!=80Qi4~bjfN7B;u0JwK1OZJ2@xUz#f;_(d% zsn?5bM-yTkENfDyQt|ZeT!ayT6*+tT{Rr^Qza<@V$tnTIYpL`Sjpn!5DP(YUbOp2Q ztBNta|2X7VB8(@t+7dFI3lwRUO~=IBPUc4QVy=(CW!|v2^vb$Tpi>id00xBBoLtUX ziT(Bcn^95t^{Y>}9dJx)Zi&6}=W7reR+sLN8p3d`Fe1Nsu3tTQVdAB5Y=J`4SwFSY z>1SU+&#v#Kx$+cMIWT=B)8Mf@)A)L}NrsR0mpzE3w_vF0qhH574SqR#4C5eSIJNfk z6mOG9|D<_Q7_aA3jtP!4OT*uKp4>z5Fnmt2cdz&x@c78aEt>by?u2Ho2>m-+Ve=kz zV8c!SNWr6|<*5KTq- zd`&3U;M^Jndi%p=_z9g=gs_Y}5Mc|a975SO5lf(W3@wS?PO`GQq&gDOmAg`S_0%f9 zViD7m<)82&du5Xfi=OkIyPVZZ)q)fe7qx)QJ^5XRliV^`EbE(da6PO~{y>E*MI-E8@(4SaFnzxuzBnIX$;cX4Rh~GWMF4({r8}aW9^Mqw_Cap*txO(WD z*`E=t0EJBb98Hd-QP)s7KFi7d&>P*KN@&NV?dF4wrz%X+Swn8JC}l@;BD#?q%Q)P28O{ zS22U>hUu@^q;w16ZQoLq#I>%oA>|n($V}-^F0;eI=*6^2qXL$3H+!i~)gUHy&c@YW z>h*H{>%x^4_RiU!;8b>9mga<}oEb%-8q06*Xn;d=gQOUyGMr zy(yx!+Xke?iqBaV1O7<+>By|T2#2dVjvxpj(zipfNIPDBfdB@cJu6uobIS&bORwe{ z+|b%k3dSwCqbAb&Xf+ix+(AI?EYwUfD1@@ zd=Ppe(af5q0(>6xBukzqc0YqjARAM#1yj~;@89>lYRUg%J=Ug8+fI_z#6^KO)IJ+A zs-t}yVG8?uERm_^BK5fs@7Mrqw>I%n%E8FtEeEC#bMxU7l6`z{6IJqHSgqOYNuOrL29!g)>jX=P`N2UI1NCr6lUPC_%u`CfX>{=#%4T!S;(xZDS)&fW3!CNt8vgqYw^4jC^TN-&edR(ypg({_sNp4 zFTniyZ}btvz+c_*KXA&(hS^DS=VfC4voe)+(cnIe3&ag)#BsQcTJXKQY1V|6NlJYt zo1)oKLV(7r>W?bi8&-bBw4Sr^pvORStI#twbl;+Eb9r4L5pd>w-Di`de(hJ5|KGn! z*rQ=<@hvW=P6s5)$saiA_ri}yxI@V;k-2CZj-2c1%Nw59f5jnWEov6fQO|KWY{s59 z9Rker^N8|FM(oW|+3thiObfqVzy1A~m_(Huo2YJYCP1;9`_2bjHE(wkGgQvl@{f9U zxRXprvc{TGmsDz|ekHi`&L0ykth?RID>KoxJPYHNg3EDR&s3*M$b?^fnpheelf8lI za)ladWt;RY*_#`f8RqmrbE>5AAMEH?m(QiD_T9w7XWRi23@0fj%-?fwr*F;>5 zU2V=RZxbAm6i%`x0IXQ;<=0v0rBmwsaIzHT%!y$=7?>jex_nkw5G4Wu1eNO-D<$nj zZ?i3|T=H8e)NWwgH)piHS26F_*QNUr6bjysG*Oafi$-RYXWmQXUI!qZYa2ZD&8NY9 z)w;n!J>@l0Aol*`#Cq45YMkL6RonWEeD-FkxBYSg+URbCO(yKY6e%$SER=Wag?66d z3tMeYITTXoa3)sp(||2}4|sk+*{IX#H=T-1jgaZ6N#f~J5sT#-q;`eJ0)xO>%6@9hwF_U2_KH1*jt%I#RwTc}~CxcP=IeCEHAM%G7`TP#;C=W_7dI?1_ttnn++MH0Xq8%M<6F9u0au04{z z_VdGv>7#MyU#2X%3$It7n+nA-AsBrCsoeT|D^I0}d!V>iXD>BHT}OI;^v-(p`J7gJ z&vKL+qM6DzH!5H-T_^GPMJ<$`l`;wOnSAkcMpAucCD!Gh@YVOL>=nwy`5K(Vrh)AKihn|4u9Vv3MGTiFw%&kKJ9O;#;R2s}@^3qN zQ^fDm<2?xN-ZYSJW7j-1Z|+9U27Y>}m9k~6?0EEA6YI&FQaxdj*Ht%^xgifmXB+jtr6Q9YKs0@qQ*mn`OuSfRG`7mm^*zxPGydJzk z(Tk{s!sMc-Hfb;y)vP2x_*UEPL)sC$1NygK`>T#R&q+=FtMkP*o4 zaxY(4W}|R|96*A{8R2W9nObP{QAxy-AXezozq#Q2fqMm$WGTbIL(gD|_?+7=7xfrCSiAN&^0$0TfK1H5&L=}7_JgmU0YYpH}o~!n&Q2q2SH7JxY@>Z zDjUPJk_;MuOEg2iHMuS0dPEmv2^)dL9UiE9wAek%zaIvR-V=TQq3cDw(!69$*GbNQ zc}i5Mx_VX|0!zsCJeiO(B*nl#WkV}srR;mNj_ystHK;}pr>=GTBn{Y$!I&=Yimv_) z0z>^FLH8O6_3egs?kHkT5^ z_jyyX!7|FvV>2rCg?~$5tuAoX^MkrWZ|4yX7SLZh_isWa3^{A4s?try%s}-JiqJJdsV0jY|jX9>MxAdEzBp7jd`eq3x`!*+nTn8-<-y|=F zH&GX_>KlJfka;=j-UKp{hy z#jy9{Fp;v_(b0|j+b`DnCEl2O&&dSF$V!V8_gsN>Z+>tVf#-KE1LI%8*4^M|TNE|& zrOl`7zI-`Q;mv%f>rk9F+9Ev~F?_>MuMByh%@$f(aJ_F?RKS=2a9P*4CRx8L-u9sP zcWN$MPwdwYJbWJk>kN0Q?()MK@O|hh2w^%9dxCOt;%>s6?1(7R7J562)EN&ec)QSyS9bU7Nsao4e zNjyzjp$P&`(wMG2YN5}O!DWunh-8>HgSNM>_1S9kJL17^)xz$dV}xbE-i_(=#zqA0 zb`k@i`1Wi38pfWGrW{_L(FqnX#6)AZ^&v(I#l)A7mu^Vdx^L=nT@vHJ(**>IiOx1- z_4ZY#sn*U0hTEfBwGnZ}p~qgqiU>e{z2(l%=866|?&{&L)z@tsbvyi|3EJDEDtN%G zJ%5QJ4*whIF@`=fCt!=5$oEEJ(wvWz$>GTZD!owIu3s~jr%u0Op9s{xC)OM3#MPLk z%RKPAQYX-(+BNSviqDq)d=zOrYe9T`nO!_jGbkQry_S*SA}%Dh?W|0{q{$5=1Dl#W z=N_^Y@>dvzzIUen@#V&LVTAor4b?hrVN-}Qg~`}*Ji6GP-Ud~zZ3C+)el&kj0zo-v z6e$!LMMV$$(q3n|`8!o0N2d3t(wR_}CTjrtg<7Q8AURZrw6;W&qF24joiqKWWtd zwJl3tqy2tD|5WvvqbYqz*`Ti8%b%WMcA8cV|9V$d4-f@SwYocVHgV@qaKoWAMy9|1 z75-d(?^Wf-+~IBF*Y%fFfvsLv`tQrXTu-4(vM`jyu`QdcU+C7XH0zQpX1N;B!>qpW zG$S{CO%s_i5b(09i&`YQ8TGhfgO~k)$TO@$`spQ z5-!0H&br%IJlqHajm?qEgUJKFa7GY-P%GU(1kJG zXMwO_E4_^oN0&^CSls^!N7YkSUE6yGLF z#4O%2eWqwGbuGKW>WsuKduVkqv!G~y6`%R5NoCe3)Z6HJL5+~2vSNJL zSd`z|U>iKrRI7jGhDb3kHPGAht=5a6IHQMC$`^DMl@#`4OK#KpqFRzxUzt)cGuhim z-Cx7z-HWm%d-=D+n#h{&&EH^OUuOv0=ZCHoKvk7K%qgIiBxQu4^2N*~TLQuE`H>{v z`RU%2ZKkwu+WIu+318o}Te{@qGdMO`;qT&bwoh7?C8kl&ykcEb;j~K4HRU85+Mq9^ zItDU58n``1SX(0QRQgBI?MtoKGG1C5Mdndm!ED#$5LPZ;P$|wEoOHb>mAS;@g>?9F z5YyNFkvA~!Spn`)YCKT$qrOe3Lb8LJra`vTbq~R2heQx8M_x(1N+@7?sAJ@7_x0qUb<)wusP^{zdZR(R0$-)7^5>toy6tsf zeSW@wCg06t$lHPC%(joVm`P*^J-!kc$$y465M#~z{=-^z?YtTMul*D!uI`aKz>h#J zwv}Cq;7V;E$QWtpv#ZId}KMmuO3kRLYRw}HoDLjuSbsATIh0{(_7SHo>Rj!lDQ?bpsM zfksE$ilR6S&*R|PbVsEhsgRfG{kYbnRJ_XthP;l`N0*)@SX~cYf8L>vkz-rm3Co#4F^Bc*NGDA1(4uUs@Ma6?4w3kY1RmVlVI@q%Jur%-yWA zxA)*@#Z%_^)&<_Un$o`BW8L&qnc$^J-A7RbKKw2#px9d~6f_@aZL=v;F6bt&+tvl; z^>Xr8cAw$f)Sv{yZX938i$^D?>6p9lJc-}kB9e8OvK_i|IsTtnZT8>*ydeUNnGjd` zyIOzs>%`p;ci+z{QJ;T$ixXqPNyzbJguu`Qh$A?Y;=~{A5T$JOBN%;XB!p3%6;NVR z)TB1IY*1j=15Nw}h)xbaKHI65U;6unSOV#W`?H~k`HhCI_V!9Z-B(9q@%1E+I|<7C zC*N#Wm3FJ*Gul(@u_`O-6!Lt-7IH;hF?nDsds8gEd`!`Aul_#6`PkMnQ4VFJ6yYs9 zyK`)~c5si06ji0?UOV5})LX3jmI5U^$ z7QlwgTG)<9{z>;UmuVTQNYn1o5U_If;Pj7}OYpG$Jn>2l}CQ2P~ zO{3ikfBX!)a9*?J{Z`l8QM*|&upa=BC&_E-!BSBW{S}sym{ASiHWjGV1h=7&nb{2Fo$Z5gml(qX-=4O+4agSyJ zEX1mr)w^{`*ss9;qVAFoitCdECFcnE6ng2{7Q)jCA-<=Q<7%-%szbfRe%u(9fWh!C z!e+$g1n6O7EXQ2;yXGJ4fyuFSRwa>?lz+Dhj~=L|>HAq5mvug|gqv3J(2dT2<-F?c zU$SJvN#xt=PKBcTYtj$YSI{D@RB0)7?Q_`)dM+PH6Dy(R=Mg@Ekxz8A+5W@&H9cK} zVQlpf@$yQyikhh6bl~)!4cp=K=1$j#`ds?MUmJy+@0twtT=zVLxG~R6ivc;=G>}%@ zz?tPPmcRGP!|XC5q;d=1NbB@!JB*i}QQOK!SAz4GZsaS%8y1$~nzUmbjVYDPjH?@d z$$AC~e5)zQX~L5c)7wrreC*P80n`+bGs^x)sEgiu#E3xYZ*(^+QG+ciem2aeq4v}y znCL_`Pj%c#n@4`x$N9Qx{Ck$jOPnMH8sKw3ZIZ9RWA*^Z5HZpOsk6#b$j^khjm0M@ zkuvCxd8NDY{N*<<#3TryEma-mlIJ5k!5w!g$PsM%+ z`#_vN9M0O*lv9znb0d+%sLmbH>R+CeOM&_hZ@BpBD~*Q<@tw&g5q?Z zB^x86&mXg)c2h<cF2R>x^AKgnR-4t?En74s-*H6z^ncQi^ zOvC8v+i6Ai_@mrV3lN{3lYZ}lE)OC?JyosDSA@JGJTFoI<784E3u3@k)9pY&c)1dI2Q9XC$M~JH%->^SzjtI+@7xJF$9givrM-~G zxX0dKXNP9B=foKmbp;+0P;9 zjZAXwk#m8pf{X~c-s>z}PAm?)?svLx9ld7b^hw{Yt6*MB``w+;Krbo?z-pycK#W!j z%w$sf)YUPunjb=0*W$beK9}t^lR1WA8H3y(z!f$n}D=4L<=HXGW1RXsjODJ zvE^E1T_YQ)Eq?l={0-GX4X<%?35sXYuuZ}t$2}Q4<;rW78e>Ua3Y+srv|E}EEC({k zg?>2G85}CtC^B)e4A&uIo0-B&(@8K6D=NurVidw|(vH(F&HqmJWNi^=XO3%q#Ae5a{CPCC0^iKX^&U#}u-j zEsU!Y^vsp&rRj(&sO7hp#`L!fgc?9>>7~i(&Pv-fxz*1!@r@6~^n^RG;aV^ls05kSld4VOWyEB@Oc$G-bV?zey8JUiFgm{U)Kuam z7j}M$5_X?A~vs>u0r1MktHV z#G{L-4<}_Y-ZLXN!WY0tpF@PhY&u6ix*G7g!TrUcq^tb9-ef&hFyT1;U%`dR{(Ply zx^eohgo`(!WpC#{azqZ(Vs2#2ilfAB1oII^*yJVwuK#5)f9u8AeLu9*wfz2FuV(HG z#TP9ECWgjyEo8!zNqCdt>0^rfGOyxi%aLgxA-kFwT9Vj4@-km6B(N#L%d_*JO5aV* z058S9X(ragwB4x)ckGai$uB!$Dz7N{8#TvCq}roz|0Uv&m3o=Sa>TcAkhZr=i>2F= zW^(PeRgnr^s~E*f5n2nHOx8L5XqBvAqE+dz8-e+S(Y*+~&u+&|@ zEi))+oq!T0I_1uC`=|Bi0Yz=cXu(oK{>DIJHaa`%9l94PYAYBDe|BEI4%UX%JpWdk zMza`JAN7s-({uW?e?RlciDo7RGb^r!f@g24{qjsz0AUm!^Eb$M#FG@x45m$898& z?S4{ClyiYtYt`ovDnsVSrMe@All3}W?dyS0<2)O{0VEH2{R8)_mGSYHp?=SU8%saSn}5On+LIExj<7^5%p+`2 zt;k|E%e9`)8-AP9(_fYae0epU8jQ*N`aPotkyqvHAt1&edwElI1v&*ikMK>N?p_ec zY|+#v+&VQ~8YMSxlQnjZ-f4eNNBU)}g8KQvtBpy{nFVnfSSbYMYN@nh~ovs zZfkbSF^&Cca1d3d>s|JkX%6$L(AU@L0At2W!!93nz00>k>Hwy>ONIg)1@uTiqTqjb z`!x?wD-Y`Zk`04}MDghtOVuX@^tz3m3e`W|yCpppro585{6Sg@OGN>D4lZhbUnIEv03%y;|WR2nuhfKg}>JwQ9x zI%*8&bDt+Tz;MLTSv3>l?j=o=C2GWTd2f}@{X;--P}T+dA>09_fx-q<-czZ5xxfCh z8)&^j`A8ilMOXbvR4blhsskf@6qpf!2ta^rHlguI+S%Z?&=LK< zzU3QwJoeac9$IlfU+|`(L(o>!2cdeH(9kk2gCkN1A+8p(6Gd*bEIKDMwRVRL%{S~z z)=b+)u)5l*Zi>gLC^%GB)Ve7}2%j96v~V=p@RCmU(;_$?ef?+3FhLXx4Cte|)wS}* zleM7rAVA4tqwb41oe09}M20NfXLvu?KCPtie#w&_Zn2TgoFZbDg~H1r>HMzJH<;lq zpj>D=P%PQv506P(w!7e&->~y zR!(#cgqfm`;!Dm0hBy!-5b2)3mdan^ZugJ6ReHml5?$Ovr`lQG4>l-%(YNVKr57X@ zk;&TO9l)B37;gWj%*!VHUs3!mSZ$b%C2`NeG z?(XjH1_7zjNH|hKy1Pp{Mt4oRK^UDMx&&k+98A8?{d@l7oUwE6d*>b3b-juf8b2ogo~$j(q`T)Yf(m+b zV@YAZSUA)M(1tH=n)I&-2IYS_?o@N*L{Bm!Rl`V0{Q0Ig?{byV9V7m3b@~AqGOTo@ zgw6GXNw!>uEWrPDr73wyb8AhMy+cho2Yqo+UJrth`2_$+vlyLp$G2(~TytWLps#Jx zgOiv?nr=TTR-VUHjyi$o<5=F|B9qTIZZA3{FHJmNGQ_eSL8HzS`r!MUe+|S!{mo(2 z<}0cY;dx}74?$)dwZNtO%grk)mYOyp|9%&n^VJo-J|{+5JqS%rGOpQ=?xddquGqW( zT?-(spAani5oSOdU%R_|ja-?f%!(%G@Dkn(>!ESmPW#4>F0JKqRkf!=&yxS+ik$~q zn!~r}U0fBV^95736wylFklPrdZ~a2e8GkZyXaeeG(NZ_CDLCsHdvibT_*QsZUAVYp)3pyuABlPP1pnj?A!U-X%frV>Y55 z*Y!cVaA~zaxlunC5_M?GKFA)De?@pAN3CdeTNZ_$@cBUZPRg+BtArNisA3ys=5yKK z#4$PHvQqp?YW;cn&pyfU(W~*(OXKq^`JDoNxk^j%ZjYjL0(ShQbsEeCmurgTv@6tQ z`R4g!@T&3sT&x!goaH~^jH;iQsR_32zXtzjb z3y_j{_KAP?ejbLKXuuC)&mXl;LiFJW@f%$M8qPFW(rrGm<%V^vXaw~?)AHGd-|s3j z?G0$a$#S54o)wFdWiDZU-o*S?nwS2hqNRyofr;@Fv=FgRbfc4X%yQ_xi$b)>v3a32 zuyWW;e%-X~oA&H8HbH<|zVpu@MUR(CRQJw2)v|4$kJQ}0HdgRvm+jf+qBv)@xJ)v& z!UnX_6sMN9BgT-Y9Lsi2^70!~;0;>VZ~k!0l%QNg8${x69@CCQGX2Fu&H+Fnax2G) zC9fluBJ+r-`7;swa;qPp%?R(n3=xVO)R4rYGN$9yAQDJNsUJyyQ|i9MYt8S!*o5}6 zPWYQr`?JXm`drR{v?SVW^W>xX{C0efPF^=F(A;_hqC;g+`D=oR=?V7Ws*{iHo?nq0X5Q2Et&EXi&-hgJQhxD z^0mC0(v8fEw0C$zaN4b9Ar7J6L}U7k`UPNF37>- zL{-2)Y1**4CGH;0vFHs*1FYy1G5RSMpZQ06JNcV2W9IkD@@Lo2y1;Sfz1SCjoXm^- zJog|jk}J9T!^*t6!`-3&BcJBCD{iMgW-1g*MA3Ou1QjNf`{RAm*r}!wDryVs@KX`3FF=zGVC#auzuK=AE{)zI{RfBnp@BT`>B=cld{5`(0R+L(JVsBtnRrG%t@%Q8xUFM*>KvC zMIjWA47(6aJJCjvFVozR{Iq5LK^{%95F&J8t!2A9$o;%8t?8^>|CuJm%Dk=!Kyy9c= z`W4r^2$Gdj!EDmK+7PxcV=ul(D8CAcFkl-5FroA`B1jPenTt$Dx1eKX%V| zK~Kp0+8fS$RC0uXUhH06CENXj@zOgRlL2LGr3g-rR&V4| zemv#Ygs*y8WBG5A0)y6L$Cq3rWaU<&R10trf)L>n;4%MT%X+&~z?t{Q)*DW$o( z#y_jEWA+HWbPl9-qaz}vwK&@tKa#FF#sN;swts>1)4IyPwsa1!wJ)Jy9IDdJ43;Xj zR}VkJ*WJD-Uva6r{n42ED%ekT_T$*EY-+wiYJADNLY-(P_FCb?O9=o$`Pa%E*d zF;&;HV)LMhzjl|*tiQf$n>V^ee)_8QK1w!0g?00i1F)NkP^Cv!6`3PebNZ6tTVN5x z9vEY;l$iO7aYB!Ah1v_6E_((V)eOb%lD2s%aPf3NHpN^7#KsIHQa$vP^89jsd!V3qPtXOEMO=^HBQs4i=b-wVh>?_l38EQAtETu( z|JLZ+h-Tq8ACyxEXt;D*bkvL1F=j~lJe?lpPnMd~#NGjHxoYhFVfrkSy9*BER0_q{ z?812h>b}>BwHfAxF+bGUy;=5YTCV>dfUWDUI-`Win2iXVH$Q z$`aycp@Eo|A8I>upaKTU21oxxP5YCQ zwQ~RR#E759jHDd~sKVJ->Zn%E{%yI( zq{y7StX#fwgrOFycXoC+(6To|BVY5}v5{lgclULrNtjlaz8IoWBMzy+W}UAYuiB+6 z9}~!4Bpe6=_6||Ba(y5vB&6I*+gO6NZ+OZ(DVOQ&dsIHV zq6Sc7@TA15P{&T(A=iBKVb5i9b+_QWN&_CR(JY}FUvbUA7`&f;H>uI z=*km;KUXA+T7p3&w~ynu%~$8L0)2&P%iP_5t1m^Q&7o5NLy>H;Gw!^r|3XPs;1_@38}gHRxj_N z`Jj_z04A0|CR?M9;ACfYrCiI)v&D7dOw#1kT~W;SyUxGTObvXT`Jd-z_p`)j=n14x zy3WnB8l8~KmBNX>D~>iiHaFdIyy~;=pO<{g^k!WSa;^GP>bnEe{5ykwHcOaudo<&DVUd>PN3NSN)Dh)w*woGv z=asIwbbN)S7N0ef(_=<(O6s5HBV8B7`+=ovnFz>Y>hKK@NurAnGx3X`6E1tY&f5Bv znRX;b20-wEYzU)Wt%IuKW>`ZUe(IN$eSGN(pW2u^ z|Fq~~Vigjldk@Nvf}ey+*R(}vCl?m9Ghsrm+0r)s{Rpyb z-z@yU<&<(9)E+lm2;RHe#!XU6zxxgyDt z2%5SZI<@!_Gv)7Hy7zkNu)d?JXD4TlH=Tv32eLdeWrT6m#!C7{|Hy_LyiYoP{+zX1 ze-Mv>_f7N7;E+5v?xEOsz^Yc-0|DgK6pNnzI$z}#g65-!u5k3hlL5w{Z{|%LI~lY7 z9Y!fn5zT`HAEjn25E3)M7i4l#wW%O7^UN(8OGHlWivlyk`e)t(CDXjsSiph$G=}jh z=UnA=DBZmX>Yy{f4^|m!h@{w@ejMp|^jhF7M+Mo2@Wc!)q_DTMN&{CGyvl9|rmHCOiVEsthF;N!NMOX@5;w`c}N`Xr#+lKSw zCqg(+v*aDbH4i)M?m~;jFqJbYH;iEe*OA`#td%%LfOmhX^iSik=JLU`56uI|5Iz-L z=2*A}83v5b0C3W?YPRO4bCteV!~eD-4lkD7Dar8#V~iF_Uc1yqVdZ;6IjMPxY=R;+ z{Lh@IBh=KYP#D{E{TA5X{EOt^4@+~Q{++5fOTzxY`m}jIwI?d3%yLhC@){_Sa0pEJ z8lfrJ^)=Jtcz5zJesV{4MMfN;<_AHAoj2|at6c2%3BB)xx?NsmW0AhJ$kC&6sIA>f z6f@xCC3uPO`5d1TyGHOZj~s_`Y$D4P5jwf;5hT&Y!LyAGv5vGVWV$Y`S}e8j{%$=g zHj(v1(MMPPw&|vWgH~p-ieXt&!b2V2ab(z`4F3gfUe<=ybw(vcQa*K=Ddnt!DfBi0 z#C3K2=FDQF^BND!S|Y+A6UQ4fgiz}61$e+4Rqnb6^cWAvUADc>d)YHs`(B@JSN1uA z81KkGGvp@bf?5B@xVP%NscpyHd=BXa3Y#$G^_;)L zmE<3!nrGxFdB-uS*XE05cn=XafNkst&*0`-dC7jJk@U^^H}kah-b?nkLp2|o|Hfmm zJNsXxWQHV`SXls*=uw%O_)B|4{M2Vq&q{ZVc!;x5on$A!s`;D|PW>(U zA`x-WGQM0$74W`*2dtRJ@%)ESb91nWVpGz_%FyGZ5aVOO>tnkaSd{Y1+Apc?qA<=P zLVmrpPkvWmo?O(yG5!ox`q>@{o8uQXlgxT_t8-qyQ`D=gZ+-Qu9t0NPH9D;|ixgm? zdhrq*+R;}PqYNBO$l_;j?I)BB00{vFTB$Ecy}kp@dEAYRnvO3vcVEzPS<=* zt3Ef=_x~e?bcoyJx9>880QkV%=R9C##gmZjXWJEV1}JgzoK2yhKUXKvBZ2z^lGm@T zuib@{x$hgzb}o%b$G0gG2_6RXJll$P#m)k(q*cSLI(>cey;l;2-zFn_Prr6W9cQK+ zWfY!EF;epqyKhC3u4-c9t$+F3$ENV`U;AdawNRHVgLrs(bcuzt9IX~dTqwR0JgmSS z1tnkPv@3eD$a`3Pysjj%>j=QisgPszd4=|ZP%l0D%$ECM6^h6luvzFUMSc&iIJ^xC zA=6rD+jMm!5sIoU$DP)6cJ)xRSOajr^DBG50r>lMZd+myLfn(@ytuq#h545+OK&?2Vt;Fwr6D^z zTjj@B9OJEoRXFDWdafc^qUp|ko*uSVOchr&z2z)b2iz3z*z_SOFXVJO9wqr z)lvr|vxIX){i?VcJ+1L1TW!W}y~*KLnH3p983sRGq25g{`X}`w+4-uCO-kpq^^xEj zK@Ut3mMw3t&LLJMEuZ87;W?J6`)nZa(&?xw56X{1FlS0bD>TlX)oONL=4wV7{IYNe z(|2C)HWJPFS6M)JGx8u;Y zbmo$CW_9>@x!~H>;^63ik2t{i(!Xuyfw>%90~{?5$j?ZRV-B0CH>wv4yvAJvk7e5G z@07U>GbEP0bww(CY811)3w?uufr*#^^2crgZLWB75yhn7X;l+!#J@SbKF*Hi`?s%5 z)+A`+;DRtK}v&uuh+XpsEb>=FPo?BeV9xD5l}| zo4021P4SD1HUKx7XZ{4A$Av=ko&t>VsKGIc_5PFh8E=BhOiA_eKcj((%1<9x4yLx|Nl43)78c;7)f=_MvWk5b6ZPN7B2lf5DC{9g zgFoD-nQx&W8mGbGfNVF5#%cLBXkN@YPiT85zS6RuY&HHJ`F?8MAK~RqsO^*Cv`3Ej zw-&i7u!5;LY3a$d6!Wv7K;#o_k zD}0!;lPXx@k9PgdAPj)ql4oURtNmn{LbbL{Elf{a+7F?o`RDM~oi25_(A(j!JDEmn zRG8X6J`Tul@%g7VykT=ZKZYx9cE#H8RWPrRwJZ<_c7`-A5;Uj6+! z`(z~+StMD8e=5TYHkn=}y=ms#26fn2^yd(^O0-6jRLHYOs>4F7XnONw2R!SbCj>$q z#WTAz(TMB3{U~Wsthyz0)&jfw5@Bk7Qj5R~ibR zKL$L1&Yzm%nfDN7>%jL&mY(}3;wL~IRArT%%wLXW*x|hwI^B91C znvTFW4KbP9F$R8Mzn*yqWYy6G!zx2p;+y;+Qg$PJ0a$G>qH?cvW-(T+CY* z5m-vh-hk4`_qQi~?(jg9lWf%CQSym(*N(!k$gEhTdl1B8XM57qaT;8m^S5rtn&fXm ztq*&hR#(!}u;jipuBN)Uqeq7U&`deO^axI~Crs9x)wd5nn5Hw70Kd?Q|+PFN^=O>$lTryy^LKFSe->MvEME*Ih#j53!QGZr)@dQZ2>r#m}i?4_RwjJ{5M`+u)^%cUclZ?v%D+JG#CurePS$)^FUhycrK-h3vLNPX9@#hDh~K2 z(OPORI$;LY7)B5BVy@(%qG~yQS~( zexhzo8fq07WEO&yuMv1UI$E}SC8kk0!h-z9UtuMir&E4*HBhbF>|?ZLO6{Ix!*hKY(iPp>Y7Sq_3|eIMsTm>m&Sk%;b*_qcGq}` z_ZjA#dQkKqV?P4)(a|@Pd31UWi`LWE!QX)-gNtTEE(CUpj8NYhGU&vU*Al5dH1sfo z$6WO;wCL?o7F(9=ezBv%dE|@BasIm|OuDzy@6PazQKNwAR&icKUoSE&AfOWTCa7NN zuBMHHOzlI_x?+@IsJ5CAeWW35f0H4cetkN9DC~q!^12bMGTWmxnmUkrRsZAPO7)C$ zv+A4z&!yr0Db{-KM)-(AdPBHZKVdy)j+Gl$;UMeot-f%LpL;%HG@hwKUsAA&yiK<$T@Iz z#ZNBy*0De?S;n)&d3}fXy2772kAqVoY`XMx4?c&?P%jPdFrZ2q{VbTYySMfwma^on z_Ri8-G~2&5+wXzX$9|yHe&HDr&PoDRk}ouytK-agM0YY%4`%JL^a1P_9y^6-LYzMd zp&-A>k#?XnR%Se8$>GpVt45ay5WK$3vM{Q6cof`7$`7bmYY{Xd6jZ1E&+fMbX4lXh zb6Oa8D98#-u5>g%W5E&c^1~>R+iqLE_A4%C$XD7=#aZ@*JBQow5d5P?anp+%%0lkn zR%m6(<8zsm;pM-TF;d(`iVd9F(?l;16Cx(dNzfu-A6-*8BWN=dI`%nOe-(}@fqM-+ zQ+}om_3f2#X9DVIUY89}pVwx8t!MxV|39nuNY8y|NdabV&e?3B{{tB1ZTWTXyp%P= zqm14WHzJjTG3KzJm%ANABh>3GSwK*`?;C%ywoB{1dcTct6q?~o{9jZ}-Bi?%9409F z&FV=v4^m=T!H;J*bmk!`Z1QU7K@P@iXTPy4&HVAnQv{VOqwVFzc~N}rRdp6;GFf4T z_}E!c!M5Ii3^OBv;$iu|IKR|nNPZ|)n~4!lH;Nz?VfpVj>&LvQ0AQYlKF=hQGZN zD#N;z=l}6OF}DU5BAyZ}=;WKqN)UJTGqLkw%AwVs10HPNQ0VKYMRd;bmiBeU{@YjY zY_!`LLJ#hHFQb?eBBP6d5=9P)XWG$&$Uai~y`zsvZ21Q|kjtgG*6h(UPIHxrLxhKy z4~oz|u`X3wyuY<$RGz_8MVP<-yE z;gds5;*jECm~0rl71jOx7NBu7Kg#c-1n%$`Wvq{-XceNRgZtQS?<@R=N82GX|6BV1 z^ai^c* zv(8^+O=#pE)+R0QnPi~d`enLoR2Z=;~)&#A5HYGh=jzqTy`J-yvf%t~pzfsfAsE}Pa>T^z+~uXZ^T`uTb;b^I(k<8Apj<7ayts-`H0bK5+d zl;9I2&!HzQ&n8bFp}4@{T4tA(n&YrPoCc@MOYj$Tk5&M1h(ARkm*4Jp5|1JBA2cKBb9hmSYUNt=SnS`g<$jrTXhst^?F!UDzg;!3I=yrql|@%l|Mey4P=j><@L4Qq z?Jz?XUnDM@PiDZnd{i#RB-bYYj3p9ncV4roW==6={eG{$dWy}@o`cy7m?A$bAVdBl z!w?E{6yw?ZZ7Uv-0@Zn;3_2WKenLHy7lcjK4Eq=OJAM%}L{_FU%wMwfDMID! z(Ru}@s`mBGvI>Lw>-EIm5Nf3gB2^G3@FZq<(h2--bfD?dY@vYm9k`%om%_wNfs%H3kdG4mnDu#Ut^63I>4Bwq63;aChO1oUKgr=ZX4K}2H5SkDp&e8(d)r)w^Vrt%RKri+$f6*S7 zN~y%`q8*P!w>n3lINWJ-g6oix=jX=f^l@Wj91}TMYbo&XHflAA`}e|Wf%>G6i|%Gl zt3qs~a5Ym&1evjq_Fw^zj=j1GMLXq(z1HY>(gca$n7!#r5R1LaL)85cMq++vvc{6; zWR-R{(I(-=xbf@nd1xRYW9@_KpXx+0jf_ZkwS5vb5@cA>Ut9;{{6Rp}6Tc&z9Yn<; z#|SsmY))bcguWt>_MM20HxH3J1gf}r8|hQw0au$D9yZhbBB%3!03~kvS0nm{6-NEZ zAcqps#W~w{{!U<>^F$I){0}X+Nc&YU?QNwX3QHqmh8MN)?4s8Oe9F?h-2X+g>g1Xg zw0i$X!;ACs%B<2aR-=;u+Z?~FL1&QBRBnZ)neN7@mx#P)VVGd^ff|}TptmrI|0@|e z<|$|c#)qFEFz1SFdOMR%T3`pH3$w3gWf#%UBi$2mOB%LntXf5M{;f-m{#;Ut`$$u9 zr*pKL4n3iR@(OZ^%&y4f3|Pml>bEDIlYd(1Rwo&i?gh;PDOT7)9}qm z5keUOha4uxn0Z%Zaw+>aXjNI3y$)Q8R~vtByjn&ukx^W-YTDWdH3pQN0)F@t#j{WW zmmWxubBpC9S4Tlg;FznwuiT_!+=Y6oIicK2iG$q)e?0o|%16QuQ2L_W& zXmuFxP2t2cKMz#3Al&m;Kl1dbQr`-%>Ofyzp3d5|zdt3vJ@r3zCyp;#YfAg_gLn3g zbgNt7h>o(sj=*}auV^WK3gfrT6oPHJE1AXt&TlG-7W%pb)>Bip7>}t#v$Dc}b2TV@ zxAtqB&oT9E9qP$fOe8<{uvS+jKQ(;(%8Gq&UFa|RBfGrVkhZkFL2qLOpakP5Ehqo( z^pAgLSaOde=*&tpQ*}Slr!w%{R+Yk$8vO0WRf_+0vtg~yt@q29{qJm4p~+N6_#*3n zdlE+jL;h}l$VAJ2(_5{p#+Vm*!$P0oU-$!Gusn}(qdzIz_I2~tL{CCev*u7KD~WkI zhAK6dkgM-XE7H}rYV>>)7!3rpcxduU#@*6hD54`jX&QcdnQ$hp-nmS>7_`m2BRAPK zRj-P$akovgWE|eH_($e<*ZraX8l<%jCw@4b85z+ z6CA?7L^<`nks#Qx@P@ZT-uDSGv>k?D?P?*)MSQf}r6N}{gWoIEbR{XpEI>^CK*2U| zPvy?5_;0;`{O9Um3(vrP)VFA?15%~l&0P|%%@TG0+yC1|d`A%QH#)d7cse~fMZtnV zY51K@A~@_PtkF$gotu|*XFG>f31@`+w;}bZM4ln+Rb_ziKm-St*@sNDC|}(NUz@@mW&)5tI*?>!_t0eJ>@GQ(sXA*F@JO zQ>?U%ZCdD2@B5dvjua%}-+#dyH=(FM8g-XpvpNi?#YLpTKpCLfXbldy5rK@oXs~1qI@0y6J%q7~XLq00VQ6SHu6F@~M@`KO}P3@Y% zuQNOu`eP-BYx)dEL%3RqTIg9GsB$RAp1xxbe418~3lo;dlt;y(pzw~wpktkx&5O+g zd+Ng$Q`3<@(}LbT_54Z_;Zh>TC%=}RIaZmFZy?p@Gl|&Wp1qKi(>7T>w_&Asu~qPn z3VW=&Dl19GnI`q}M}3}QV||=MVTR!0`Q%}`nNa~csK_ZmglAZxovQ|zv3aK=Vq~=4(I0#c=l*Ea9p69j}O+h{Z){NHe2>fHAu}-Oa z?T0-7LV^BX4I&!S` zCI1y?JPh(HFUWm>y@{2t`aHB(UOF|d-3LwMr;A(&HTEK(Nl&P%-0^%Pve6vXwMr|u zucC zw}0irNJ^->#SryX&orci1bCHVi}2%P+qoB^oM8ye2@21{-QvFZlUaiq6EbP%wtg5r ztfZ;+HcLwy{%7=yqnZZ4_SXe85P=-Y4v?>${C(kkwPtpd2%BXn^b2f18KGbZL$yhl zlCL)EubbsH3#hAd&Zsfc#>Ps0W?{X{D&ViTdn)>O5+)jI>k^jpY>6sEjUW>5A)ck+ z+ywKsjewPR7fM==rnz$6Mn_7@c5K#Sp#rQ=dFPDgWU?&?U|iM*LuNLBEoL7Gz|qrW z#Wn*)D_d|GEU!xVJKvqgxrw36B}shPU{w5s7J`cmItsxf7IjN4^NXDfsFi_S}h>S#MfIVA5#+;tY(}L!dxtHjX7&A1a<}r=6Ouo zvw+$rD|?gsxD^Z`ORgc-SCgG7uXAIC*idC9c%{46bPx3n?*KP7wcqvhX7SWDn@Y$D zxjRc6th6&vnDks>{65ws*VMQjNUg5pj!05Ob{|;Uu|sZXfDrK?gSFsI6`0UB;mA7V z$#iyr35S~|p~l7JxoD5R{q2Z11XH(_^mqC3G}RZc98vyBh7^kH5QP(n1$@kk1{pTy z6Jmb93_0Q*2mP)*_%9o#n3C<45W;Sf{!55>$@S*!wJNvCG5%+KxJ|Aflr>ZjkbzHs zSvAt44jzBA2+E4*>TU}6QkZ=YA~RwgG>UmWtNyLf5|?~HM=BkF*lnyEX&1xz+UEf% zEjbufS2fw-8mOVtcymORvW6{dy~Fp%yH+`IB1`G-S0OQLF-xtEd170Il&2kUq!{*b z)VJ!;TvSQ>veIQC9CEUxtBU!mO-<76RZ8e$lr@xK##C9>AT>krpV5uFTbO7tvSc3O zdLL>JZ5dd-su1r>nLO)*3sB^;H3@C*l~QwPHF*=ve4av~c`{U2!Me4%{PzNQ=sjd|@cC zT|8^X?{dvm|wL5F3laKtql1PSexEs28ZT0$cNRVutK3aD-QVB zv1?F}GfjxB>tiP-gJfJvy)vGARymw8`%F%~Ac;%SC!o?hLoDSc#0HS)0Bz9hfGmP6 zKRDr0Bpcv16x-1c*VUiDJG*bieF-Ti5Nse4rjsUC;Va(wJ9)5n)brV=iqaGtm!}q3uvB3uw81cB z?@`e1ObCO)V*RbViOup+hr9ljLcmX}Hd`juA09lqL5mrixVf>C>xZL3eVwx#Ku-H% zSaFz;Wa;q=nR!&jA>kQ!#_|3x?BKrAr&>2jh=h16`E`+u9?SGy`-}+=A~+rR2@AdN zbfl4V4Wurm6iF92uea3OWet{p?TzY z#}o@9tf0;LLxf(GM$l))Z%$EfJX0~s4Z$q^0L14aixr7(^5*#KUTJcviPg_k-6_!>at)vOord#n^61UCPL18?W!Gk#i`;KaQmYczYJ5TaM zvPjbU8N`?LOGUe`T7{GD&j^JHn&=Mwop;r@vP(qUrZp08O;r1X`7C62H}D+!gtz?J z)v!r$B^vhI8LAepcS$TpzUfv*{9FyAGV*+9UTW7?LA+ATw|VnZ9kS0D`T_Onde5fn zl}Se?6YB`Y7x(F-=ODW{4dxC%@Av3h?C5_(5nZFY$NZ$xA78R9y+d4lty>eC7X~xT z^pIr;;`5&dChjAHl$L&bgn{uG&dECQ*ew<7hadDJWiY)xwB#1c4<+q#Y-1yf9%9b} zO)|!c!C1*h(^&&qJE|Y@RR1HWPkV(6jykT-&qUY0ZP2Gvns~=!irPSQ~mgIz00%J!{I+yV&d; za@C(YbdxyNmev+T_H#}PW?j%#l`iOYq`Its6Dqy5UKhskQUpyJ60tU7u*n8tV6n#@ zw$sbLVDYcgmpv7Sg$orn+ey;pY$qmM)f{PzCKCPlMI_&u`erCZCKCqLeo!nSudXLQ{CHw zxK#hy9oy-X<5dtDf5abx$SbkBD6C>>YnFf)KmP~~a|z3S{=9Ve58D9Twwd!Y?#Qgj zx#9(uA9jrw0IBP8wdgkM_~bu-7J;AN?^`Lu4-A8Pqxm&Bvm(;P&b6rSuJhb_#3nYI z06zj%8-cJn7bLw68%SFFm;TlM@$;7oleBjfHLuIzc7bmt3&=R1puK<;nu4q?o>)gk7@UAJBHcN6QWdHW`qmmHso@vOUBX53zJ*AbAa z9p3^N4&EuyiBGfMK7|Owrm}jZQ+o6|y31EhW*Hz${0dVMv7EnWZ`ihu4fjQbkC!W; z??M}85LH=ytB0NwS^?8xxlNmO(sh+qF6MC{8Gr@z&n9jZ?e!oL>m=7$eDh{-?Z?0V z+Lu2RMoVvknOJFc+l)VaqhBnqII&P8p0U5B50_w!Rt!%g`rB!(L7F`zYBGZJITJ zUyWzYH8)%YW?rw}1$-+bQ@Si7FUP5{OT~SWyji{5u})Vl;t!MJrKZ&ZUr#;02sC_L z&o)!LB+Jlx`A|7EXXL6IUXD*y(C!2OD0onJjCT+B%(+5MAJNVRsr8LlS%CfS-iX8W zdOp_q;j^nTuqidFPwaJh|CwT{&WI#MeHj5`|Cf0bd0a<*oiA9(@7#vNV(O5`=pVj( zR1+nVlSEg5K|u8WRF#~8+4r&c*^2}5c6w?jvOIW zjxLb%t6%j@Kesln=wsifuPQ2MJB7!M)7Px0I=~$j0$_fA{7tR64%BlM9`_vqD+@#` zCLIA0X)5#_)p&^KsShnlEh59o({ds~msS&ws53FYG8APv6<%V6-i>N>~&SOsLkWR8^M2 zb23=VL;o?Zcoo2M1NZH(sJn@Y`6vT;Z=}P)*l?ApP%_mlDR?3`Hbav!Qk?>>C%0M2o_X<7sjkF}_Q97r01KMLo{=dq%isDcKF6Z+*60Iltlx_r zZ0l9yQ5stsP$KnkGgKR9X=6nGRkWKbulGv(`7g;Mz@HawuCxG!rHLy&H`ay7(J%WE z*yX-2b(ZdB5Fseb{(wncXP{LVLHQoxuv-{bMEXCpGMV8=?%EHF6j!1^5;8H7cMALG zBXu5G4L9+EDqVl4?;a>XD^gH^pg#xZjtv!_UzE!Ki#J>JQ{mUm1JV^8O!qfgde1`b zL~PP%baF7_9fz39{BNfWzZf=HylcgMvqM;Y5j0-ZCv;|z-j4qZiX7z;w-Ao$ z`GPye8X@LkWnvGrZITK^jlDM5OSg7*`$zDr!MzbuG7#m}@w0_^jYvgnwUqkoKH3A> zme5t`O+3LZ*;_j7hhHo?NSz=OXeeN@0eavd4l~w>!zKKbn!&@@ystnAqvJjzo1k-o zq54UN!F!OlDrjGmtC&!c?oF`{eIj`e+iqK0O3S3wfgLHsI?1i zZs(s+L#gXCHdIj_Btq`oBsY;eK9`8peFE)4#v_Rc?QH($+6Sv7DeF-OL8j4$kV(7K znU0spmtx;}P)*m0+HdAC-;5ce!eag|0q9yo^QBBj;r2BDseNHB^Nl>GrN8M zL6U6;ZqM?pLK)bCt;X1NL++~2?rAik?fkCBCh6OQg7VbTjxHIxLRyC2lp*V$jxO`@ z9z4!R*woVOSicM`l^70UWo4%HjdOgIMSD_=eHrEIF$ zpe%Sgw|Ift#SX{YnC9@toOXA-`4w}Tb0nX%^|%W|s;Pffkl>G$93*3n zV&Wgi^=JdZ?vCCk&E|9i=0etLC5ypz{)^d0zaT>t*DBSOIy}F~Z6BvkiY&3VmF>jZ zVmk_2y#sxR$S0%>;JtC+uP-=>Ehf}3+O|A(?6Z_=dk%seBL7&9Ahz{9DZhzDjb;3Y$Dsa-3r;lLjlE$f zuTbqLp2!IsejBi(GtraM;_XRKH}u73HRGRH&4f0l9KJOVk{Z|t1vZWE7Uwbo&&pP( zouoUlk4If8pOcu;LG|o?-ym#D`yYQgH2q~kY?{N`0Isx<*#&>S(ULUb&AUHiC07#u z)A#7r7}k~p{=dMS8bL~2BNMp920KOTG`#5;Mdz!}nh4>774iErC$N9@PU68klA$IN zBc3Pu-e9AV6w?uP9`4o%6ZklJnB)Ge_#oeJup;#zTpd?5Gf&0mS-ghRSGr6wGIcJ}}*ZM79ZtRiqp7&n) zlNh3HFtJtKMLQOHVh;NH*59Dz(g`l=*Ke?d8P)osts$y@*u{!>dk_1+G}BxoU_GHI z-9PVtXwNZ}?cvc+Y!CXmY!f%ZjP_>DurO2t*|9uv{Z#wt=6`GdZ^Yg3VUBP_qtAa) z&Aul|Ifrv4zG37gaYEc;h^uOGC=-A92VlrX>5b50fxuH&Y1M@F=WlZT0DdIyO^$?p ztH!^S?LTkmQe)=F1xg7etlD4~Lz&=4z=!51>!nlo|&uL;wYzBi*X z8*(JC_OMYaksF;_*Cyld9=+OQwEgdH(f{WCL8xpuWd~#qHoWgx+KDmy*`>dfUX|ppuZ*u)Fj&}8~dY3vf%sTXS z+Os37B7YCAUkDLMMYZ1xWLv9%X4n=vA8Nw8IllAKZUo}1J(X{KO-f5%rDM(6z5c9c=e9RI??qzIDgftDr-w zw5*=F@4|Iw&-mFHp>Mk`8(053&J-Rt))|w03tMP9eP?Zj|6aLmo1}J*XtbHqu*=nh zRZ^c1CcghG?I4uusJV9P%ZS`$>MC==ARbo2Rl$(nx;`uNTzuWvcE;y){CeB^!H?yo zNv|SF1)k|rTV#IeYTf49xK|bx{cr(toykI170NbSnAZ&5%YE`{WUJM z+0@bfFmz&?N>Y?O^Z~vHHHQY5gtp5kBR+p={24P0;XCV=mYx8k$6^}&VNIjHxDLb- z+r)~Kp=Tu;+kdu$WiJ#oHwI`+F?Z)cp>%2`e>&dbalVUZPgi=$H}n)-<NoL5(v1et0E-jP8nqMt8RKgg>wJzrMQEYlPdN%=EpbF3h;C7QVAAXeJD|? z-|sd`%|EV~*ELw$k{tM9)foHtKb-NZ$T|Mrrw#MD!p)i?2p@x?ICWd)+XiDJlm*JU zjm5=}o;aRJtV(IeEPD!@)9i@>7KeP)+AwY@wOdvY?kF5Z#fWA%++5~5&OP`hRP0X zlT|fL9=_hBhhnsV3f9(gh~bbiuPzz#3u-kd!X^Io!{69!TnIV@6wtjof%qn(8?jct zAU&`!Kaj}?*&ocLHXaqSQ*!eofK%MCE7PjK{hCNR81$X!cg{j<#K~T;GV!eQiqWeK zo&fDJQ`Rc_@1rep2*MQ4ep$;j*ppzloj#hpPaY-jjIfj92HD2;A=_(+z)Y4nF>21w zSs@Z``0RXo7veHrRcixW)Ihhcl`nYc6x0pjp}@b(`}2m6zMk~HXA^7I`UW!DCmU`J zTh9dX*=S&{=NQFHhFKcsys8W^BBl_l%UrL7LIfKefAk*e`Gv_;_YHM6gTrYCrjCo1 z&vyT21*8CtKw$J1dL2*w@2^VRl;kCaq1X5{2Y;Wg@`&0(zo9OVGBu!Fl{Km%vrb_o zeQ?IK?)TNjP%cNnUX%ButZgb6hOJD>(^aGb3SPzPggl1xhnuej0%ZpT!@GSccGia) zj5NG&I50#oj9Zy6l>O0tnJ=NrHj47i$Ptt_6L`9p^Q;G_f@)+AY%}bbiRaQbeeXo<@oBki&#)lGhAn16c)AnV~crMI7bcz~2tOqG`_t0aBb=}v69A`ObT z*vIEu0ZlH-*y=@K7c`3yb=2#WJOzp+|0&Iu2erb3S}Vpl#;dBVP%6(cdWGEq0S-!+ z)NqsXvKk!0sp>4OoSrlOp|=3G4AJ+KE)G+gmymz1uf>lAkFdbpvN6;Qch8ar#vlPD z(}P%`997(YXP>Vf#eZml+Q=ow!l%+)#ZPK$@o7{1!ql#@rIuairhw#Ut``dr~kRf_!vaK(ekpcNC)&aHstuc{Mr|ZPgQx8E_f37 zBc-<`<>RDnkA3k^R95;4W5*Lt5~BrNHe@~Bp+=+JBY1PUXeWWDP%w*ka49jY+VWc)mzHd4(mNL$)*xwz(ti6>Gy^(kQ;V++@_oe z&AWe&oBOjO+b5uUx31i!oX9TbXw$bLA|=1>q*8WouBK3)Barq zsA5=U&{)WifmVF;6*A$z!{W&>`yM+HhwN+R!15Wwt2j0qjx&#Fr-|j~^U> zDP7yB_a7R*;E8bCX%(ZM8H1{;`#{{YU+HYP=8D*7TNxOUfN((kL7J`YkM4%do{U5^ zZyU;Nv|EpY8=9Czqh~Ho1IQd@$-9EtkZ)e2Wuf-{HSFGaXv@9tL=&A+ppp*IeZa;a zBTy_aiM4FHALi9!ftQVV#{=E7uQ{A;sx;d^pK8b*PSnVl3$Z%gFx(ov7|11kawz?k z@STM-x>1dg$EN-@yXQ29D+^)?k?D1kDr|o)tyd}ZCFgN9ai4ryU0;*KNCXWR*uwmF z?5(iy``g`Sf49>G{Bg@<&0mf7UkZ%{53JlE3(wk_%AgPDpxV$`^RvbA*7#pZgzsyW}a@5y;N`F1Va zMFrqBy-g&95va}p+PPQ}32;0*?~HRBr!A}>&Pwr3^N_+YV@Uo$ zKT#@jGLojg%?w2O`Anv{WtFVR2B6?s`zmCZDkk?1{GgpXtAMVp;qGqO?VPR2jXslEd zs|XK(sVFD61#)G;-sxU#F#Uo#+Kw%9g1^lt1@ZsTL}fRCP=zoGU8B04U;@QG^rWN%9G4Z4I`igBSGAz?zzW&&f%-tn{!4%?NVvfnU90kK zBWMz;G;i@^Ur~uD4x2kiMMtroLF?; zcxqy{=Ns!}A)WS5BW`>#4_S;w(W{ANZ@NdZc=Y13{b*B7 zjlD^~b63eL55ppIoA@J?tIj412D4`XfnL1XnpK1>Kqgm$FOj;mgDK{TjP?9}#a$sN zr(i@rG8qvA?H3Y0o2jw={TFBz(~tlJo=xW(@5Fw*#tfA&wh#*^SK4?Zb~45mS7DB7 z7?RivamF0QwXO2Y_Ifq$cmz`}kAZIcxzq?0E2yB#iI;0Qp5J512y?~3#LRcZD4v1j zDI*x}j^aA>J{g=^nTYU}>ydA7*J)GZw6#=yxNUNQ=8|^f6G*;b^byU@+N(^DCCxkL zo2kK$JDn~}`zxRv#f$ZOuZws2f7WIX~I;QHUd=$qTn|(>ojdx>~M9EMFr>XAy zzN@S&mz7THDJ5SF!|#2*4ueWq0PKo)nvzOQIxa5+K8qlikT=M0$l12O71_}RFDo1wNM7+=6aTf5sD z0M-=kcmd2{`EDu$nwK>yDsuqlMHg`Dt4P9!unLXhN`;&uFIZ4=?WvuE+j^52ot(AS zU~kWwLx#G=#U*&&1n%PO{DY+;XOE~TZ+cpciaSlZ9sxIRgKLxomWsF^AFTv37~P%y z{HfK>o?;0wUR;hXRo7=B6JJZj7A6%^hwY(&fza5PvQv4T71=QnpqY7wu17Ng*&GJ8 zD`U}RtZ9|5yg+2xsLm&P=1cejA7aEFmQzbyB->i6@6_}e!TE5cZ>gODCY!TUIs;>4 z_gv@LQP;WIxgcS1NQqBlv%>4Zgg|`m&VIW7&w(l2hw{-?78b|O)&Mw8Vq zB|H>|ZYkI%yh@@<+^mB*Rs;=>Wo^^izvtNC2xRe5D$nmBbyfw`yfL=Tr@Vmu1JLsp z8)qd);-4!PAAMAzfdSNaVT1%D?$`BX=2RlM0=|A_)h$h&g={TDxCkEP?S?0G?u#wA zbFhG`+dV)%2M=+28OqkLbqfd|d_3?j)IFJ)5G+&M2_TjMeaIp`3&X zy2ZNGtGqNu!YN%9;VZqupb2bpOqX18)D|{7%znmb2Jg@fzk7DtVClEE7E)Iy2LuMw zuij?A|5#UP*wyst`hL%i(Qt>-4Ye!58!f>0^F!uvNM3c~%*-9|jm@sE;c0EmqTc}? z-5<%s4T#OKo+_8i$m&E2J2n`>03Buno2zCTtPLRiUD!9MGN#Hbs%|pXS8Oy%*I45} zQp)omwJ=ft=rWg_VPC+$1Tv;yzU?Eve!Y=!*3KinDzLjJ}nM*M$@mjss z=XI=KS>8uiW3KNEJ*6JE<0OD&d7GS#nKoFbk1)qm103&c&r%(bWkC018n!izUm1-OGu+GsM%)6M$N5CX;yK*1LrUe_vhq`o_bn?4ZbvIl>?#Iwq3Pgu@N@r za$jRR-tjuT?TB?hMbCJ6SSrfAZ7NX|dVb_ZWs87(K6>PJK!g1c$kA{uhQB3TNo*Yy^YM*M(%;k0(1G zJGy&YwXvBjhI7~HozsuLup1G{;s>z5PO(Ar`u9)VaX|zGLciDb9DpD`AcBwN7-Y{; z*h8uz;7ZlNl3?ZFjoY$7g%e@j4yN&|xi``5{a9*W)ZO{A7pOl1X81G3CgtsVqO?W+ z>hQ=qCfn9&=>K7BGCGRe2)9ON!Nv!V@rCC0^nN3Pwv|_1*MY)DeS`hf7Z-=#GkhXs z+#q!dn*3BfPJ!<^m7{s=GSRK$z^vDe>!biGnse zeC;1i7emeNrVhWH>M*o&${T|`jInJT1^Pmt`Qz{99m0I=GAy=q`3Zsp4|ul!+=@=q zL&~4+z#?$C(CmXxn(UBcoWYu$J>U{V4?0y{ZuNTs`3~u}>y>@?MwD955q*Xo)_vqw zFz`r~?F#GPntA45zv{4le;lOI?Ink?AX|p<*lCrndv`xWRMg3!NOhEj!qf62;yx}y^^D7WDjd3eeXnILHKk1Uzq)rhO^pj&l){tt;F(qv$iuzd zPLREzhgrIZbZmzkt$MkvD^-_vAb^uwlh^X&i%6rL50QDBtb6E&&mO2Q$P>(Lkg?GL zs?Y15+gJ6#IwLD>6-|Hr5~nNQqHpzb?aGMggcrLoROUT#7D{!+K9J9p7P{wf0=#Mp zook>`%T5YPpRPL6*8%XieXOfNdrN-6&`ramwec}UzobJ*21t2FLgW3(UzI^8)H
FsV_G}RP_D&r#+$8J*y34Ep~&ffFLMC#L; zpM0F<8WBPn$4Mhj1U(f_=w*M_BYJO6J8czgyA$zSeH1FhAP}B(4nt;PO{vb8y;gx{ zI4o})%0SK=^TY5`azy5w`L54rm9C!N;&h&OMXIsF6RQ#RZBg?$<4XSq{A5jLMtH_Q z|A(ePy&iBWLF<+in(r2bK8=*2TrsfR5b1GL9V;&?yh8zGGQrV7=Jw@w=FDO~TCEFfT(iKl{4D`sTHZ$<1K` zNIS>nfd9~%J(f;~K9Bg&yVC-T8kY{K#hA%xi`zN>Y7*T^1XsCWJqG zE;?Aphxyda`S{|o z$rJ~hQ(^B~aE3`MLvlxnywUy&WG#f&c0KjZEr`BnC;;QD7jW7xh!3v42{*{M6x z$CA0P<(4X=ptvaNRq=0bk@8r>-;>92Mt8l#3d1LY$UV$mYeu`oSN-&i`b#rR4Ci;n z(7C{isWSuLVE z)@{bEy>j6)q36i|ManUVc=mWnRou^Vs^Q(@mLjdT1AFV7tV@o$U&t3%TaQyt7-T>_qRPE!N$8$}Jyw1+uZt{mC$6>JRhMf!?V0isL|RB#X{SPV=`{c@0lh-0=!#IJrlvo~@aU@Q%ql-y zAsIOoBB|2Kx7qQ#bZ~)ev<#rpM8uCkr%<#2z8i27P^(Ljfd3HWH zjT(NXsUAcnJq}CTS$gccZQROfJ?gykbnDNG?GE{KI{IP;*|=3`&T&A=MxeYPiP)ZF z%DWGGh=Yo^gBusz=rlYxni!nS#6-*JGIy@F*?4ID-KcS4Z?R9Qdvcog$kwPbJcGsV zCfkf!ddc)WH}*N`7a6*$Z_cd(zSsO))p*JI%{1uxbdLf>AbRYM!NpY0pp+ATD)^Tf zX{4S1N#$`*do4GEh+|i`=1(HGBI6O!A%%_=3kF-h1}LnYRmV$x#Rd$aLRFK>Wt@q_f{&LznN6Y`Nq3F8_kv&y!?OmgcGgw?*M!pFdzrH;?q_Q?F z;LYB+o6l!!UFD(UbM1A2VKzkZjog}l!i=Pw9o@okVvFH?@i++=rEEFEDcMk7eXj7I zjNz!jMOsua#hZI9Ugpl8gttChfG24(PS#Ble-mj<>)N_^h+h#+3a~R z2=+A=`gih01UzMS0PJ~zbw4QGZ2kwk`=XoMwo$aM&C4_IZ6OQ|P(pjR|G216k z5^FGO*`dsoP+M>Na6~uE$rjn%zEZy0xc@}UO1XYdGM&jME#OQr(=Bhxui)A-dkQ>` zN4McVp#eBYq*)D>R_uWbXK9aNzz35MtlO6SG1Uzb0hVO*3t@g;^xG??%x}UpmcF-d z(^ZP&^3TIbaazlvzj8LZx|TxBmERw_W|avNR|6FJl!l!2Sg+>hu=Qw;skXSLe;1R{uc?G*%9-qpdqXE&`nN=6O=EY zJ5?*&v4E;>MrJ32JX<H`{jh7X2xd?oMnqZs>*P6TDO8EbX$Y82z%ylMaUpu)5@bXlG;2xR=@{H&bpD zBooBz_LA~PE7cBU&_1@YZ}&9ZwI39Yqj5XyV;kwtk}5nlGSM`C=8RR_lsr}c9{%EW z7|G^*GnLh-O<}d(sFc%*(-y8DG0z!p|Lmm!@vwWl8u+19!UKL*{ixfe8nwG|_Gg@| zjUw2W)z@c}E_+rdL)KaxFTH&VnU1=m6+^&~*@EIv%QkA2zzxTrS>0E-qQBiG_J+hf zks6h#LAxxNTmvRiGO!1+2Hu$)o$Awz8=aZ8+KIB||I2nEC>pR%?K00e*i2oUd*nDu zmGcM>fJNj7>Pu@7o4tSiWwns&>e0hvYDY~)qn4xGyPsvtFd!o%)>;wq?KSN+ z^PlK^gUoK-XWu*$a$erDeqJZds7QWErhfa4d0OP>Z3*h>vuqpQ`SB10TMDM9KEv zpC%s_oL|Imx;}iFnPxPAi-yD%4zxPdS?YdiP#lwO5n(a}`!fqDVt5s0?q{Iyyw^!C zO(sJq3yJMA37vWoNUuZcM_fEO4bpQ;T%|_xn;Jahn9rLne#j7E-QqmZN_4B(GUELr#zWJfI;0C+z z_*S=-Cy_{FzK7~&Sl!4r;`N$zB;lyNI4K#h)2*dd@R!$8vv_{k}s7jzf@Bl0Rg?+afrlV~cbcIcSPm(ymH zs*O#FTvz~jiozQ<5)AU{d;imX@liatDkip)p^0uKUxQOoeodP8MlSRn=Okcwq|Z%g z%epY8D? za&_R0xn59RhCyw*-=nRuMwJ_*jGx}Sq_9uBUWYW>mv&E3*8N^4%5f~x`xqxu(9XaS&c@5>6}gYH0nvsj@vI12WQJywL` zecJZQJ2ekNUw)@IJ|{9WsZ~?WsNPe!9l8MTh)wT9kw-Xgh1-#X{V}dpWT>=P20XMW%ZBWT?{WNG!*~3CODj&W-gH&mrcp>qe(T~YU~ot7ZR^y{Nx|ifE#K5L z5LVI;)wM@4ky0JPYC4ft=Y!ct&EK5blJO~ud;r|?45#@tDXUmGR77urO<<{0S91}3 z2y58x#w=5QX^xe5`@5~90^s{%t6$4Prc&5HYOPW`x2uRiBC6}#GQz!;dj`mj<shu?Q?2r`vF>A}cF#~v1R>r@qc)eNi!&BN-u$~Fm`#Z~63yT~w3+|H>3PH#~ z3GLwus)e?&S~z9y+4i>X?`h5#NrFwdVj2~Jr&bp>&C&PDD#fKav(5Ke`9ddG$5aIl zxzoehLl!7LHq=Ws#EdH1>}}UQ!M4_PhDpjm3@)38kIh(?2;me8dA&CkA@44}mpNqE zjY4=AJ^Slw%t?<8R+qXvTH4+AVg(XS@{L(n5Z+(p=U*FO(r#AJKRE|f>z_o-mU4ll zZSap%XP(@qLz>qw1-!(1n^`j?ojVgCJs(AlCslk?-g{+b$%bKoCN%{jjU!z&~Z|!@qtzzNY~Q=|T>K#I_8di%Qe3`;EvwWJN|qWPw?+Mfh$Ur8=it(Gy{dYr zY3%Ich+LF-2x|u}>*7e#0tj9(j287%8ln9Nu9^HqwYLY4XM%rz_Us;792N=Cf8CX~ z)wAm5)YF-RC#mE)R5Vagz&5tPTT9@M1+;SMfxmYyxl8I99iv)&_C=L`45%J=H*CET z8fHIdwO$e7hR65)a)-Nk+tJXmoM60^JU|q?W4foIo!NLw;pFAzVd2cP(~8e#MJ(z_ z(jn_B5g7gX$w2OV>G0m0@(%pC0&$g_IJm@Qh)-@=N3>eY6Z>C2+>0wnmg;|K)W=hq z?^ZeEr1aM4jVbv9FN5U@AA8aR^8Q1MLJo#iS#&lQ<$T?-Vb(X@{^R@iz@>-Rs?*P9J#3B&>jT5s&H25!2W zBZbu)sag(|V5q*J(oup&PQb$JUF+W=pRKjS8n#af-AnCxze@?`JNk{qm<=S0Gx)AM zlF88eERnkYz=6h{j7=1EpimrOkp(?@%R;pk=T$MR)(z%Wuge7P*70Sl*7)laBPm*j zg1FbMPG5uuXJ<^?1=nwU#1JEJ{~0qorPcZ3rii!z7wwFFT$65&gl7lc>8qJeP$7T6 z{_?pKvvA>Fa20r0Uo70gozZbIG@;oer+X``q5aI*L*6n@H5Nt4MmFR0PZEgKt&8vStPYYkw-9|_=w3_USznln-KPFHY^ z1a6s1QRf;@)4*muB799}2`mJ7qIK!ibTZG-R+Q2l3+F_O{)SH?eLLG;E6y`YYluP& z!`+Za8pn;r$WmByL!kDPkR_bJYPa`6Z%f!>-=lHB7p8#a@pu{HjC!SXZ$;bAzD39l z%OIN((U5I0+tiBv-YH*=egvonl-}Tfnk*&O+HEi!UbF3ed-yk|42O61ga&)|=D|Pd z(q7VfQ;(%&`Ai&SZB~zo1#K5t`uDQkI`gh)BL>tmYc71QkTG1q2D6^c1Q*<`Rrgra z?;ILvXJ+AnlpNF9AO8=8)Isy@39c|_HKia$Ma6B>XxIw@Y# zl1b?w_oKcbxj%P?FhN9oJ$iiN#hh1YZy+H!$fMo33Pe*_IBd@_dZq=qc-m!VsD^41 z#(NF-TUX`o*JoH35q~NW)C9fY4OqtT_Cb}U!m=n(1|QCBUvp8x^q#(#mTTtOUshID zH1x(-ST$%SEB<*jF3!1cUTM+|KoJ52UOu<)wP{0ba9CjS2xEVeWvUy~e|E3}_)?J82-3aimLg?Zzvt06J`6e^`^*RbTMdUzCPD7xiH=i z?W`I4Uz{9cZ>m1rJU764ij@l0A6!SpT&SkSfIP4{0I#;4Y-Sgqy!)-hIsUF4iHMC? zv1?ff)+%U4NVza+MeEa#Pu((oC`>(NJUYs29$lrs!-m7m3m4ztK#{B2=SVrmyjpR>12T8m{p?cZP zlZYw%1w4%c1+k7f?P>5Ws&1ot5@_+Zwau){I z!cREYmktj>?Fd4Ic~FTvtTU(mWG+O6aV@Y@JZK5<$Z2SvVSrm}rxfZ-mLhNOcO>Qa zq>7V^+6PkSBJziPx={_ud@(LtU9JRy=SB;*ju=8SN##F@G6oyHV&6rqoZ^*59}gB# z@@os^U%2j7QDA>w!&}%)??BWq*+st1@`!rcMZior-|(BOLZa7Fk|GnnM<~w)w}NOO z@vQxVEx7@55U})R*;*sx;JP9Q`oQh**0onAlFc|AyX>W3qhBhubIt_>FNIeb^(Pnq z2JQD^GDBHyj`6zN;B#^L^4$$N8Pu+s0L!Qu8nEDOo6h#rlJJIWW;Qt1E~@1L%fw91~qhrm#l>uas$4m+MgV}BK*~bRs3R&Bn}9r zBYRF0tKXbHcdkA->7)Z{d3CFI$ftLqQAJW-W2t|lSJ(9Z)knvXpZRX(Cy_SL&S!Jo z*L+;meZfq|hZ0D2J0*5Gbb#DNx6fk=HG1d+=8VgfwsxVzsQhq?E1Dl`M0{SGzkm5J zR(;w&@9Gr!8bsxr{A7{(c&)LW+J^)fCYFCu%%waAb=O`zDy&d=%uCVTg!)E+*_T
y_XR3w2irW@8bTTD#ivPP%ByAn6!9Uo7hB1w7K@EB^TDvs9>1-!EwH-Og># zD6C_^9BTJz@mq6mI#pbuz7vb8SxcwYN%ne-u{Xccml+93k)vDy;bH{>H}Y;KOpUYl z;YIKalxW7Y6!TIP{^n0N>h0)c!Q51&P+0ZPzS<48#|pYH+H4fB`QW2Df1#|dbwQ{- zC~t`Q7Np`D;##&Wtd6d{E8k$?J$Wony=su83w8VH+7ccQHhhLFk@Q^ZC1~dM6IZ(l zl+BkVXP`-p+gU^6hE2r5&zc0PU^X8fl2rE+dhS0z0L+~E4s*O$1TX)op;{o4AV!U# zs?w>>3Vy!N!ES>BmhTGyn_AOu3=K7b-Y_#R`~tXQeB$PihQA@EPCcSgC5N&`eff%Z z-=>b3CU>w4DtQbI%vTNuw5xO2zU0Rf)t|yfisZY#D0YAS?A7?*PItWkpSl>&Llcu_ zQ->I^o;&MnBx#?n^$5jZSCmf4F0>qqP8KM^DL77zDQ%@#a=$0W45GeNqP1BL;OBEe zNdQHrvh;_tcRjANZ?=(zBxxzv;HeQaTQtYHk_N{xe1%sY8&+C3^!da2mMJQ4%H(7v zxBWzS^1)8Ux_haSWgvZnL&ZANW;}vLgRv0=6=A+`Kf&?$RWnrZzTo<<>^zybfI!58 z!N7^~ZXHt^q`^Ua+vaH5nXwz>dP6N+?(?3Fo{Kk>+rFa1xPa&q7MVGk~0sr1@_ z3*~Yo3q~?-Fn^|iJ;UF=eurxLsvJ!3s|c#WYNN6zQ_A3I_jl{vG!{C9&tJ6NS`!jU z4HyN}S}4Lc{PjRU)Vd6c1m-i4CEgXG!rbnZYBZ^Sm0e}V|3?d?b~Q|?tKWNBgrb{X z??@@zg8Z9)9by8>n#q;+biDk#0USi!wFnADb#nfPg?A-OWsl#a)!(8Vs}vKT zxvxRM?td?X6jTYRFh*BSQiAr|J_0ufvY{4E9#riifxH^&AI>ripaxBdrs~TU=wXyZ zs-Nb;;l$E3r@3abY}&nmnO_PerHwg4QH59@T`va&Qc1bst5ZE;#1C|_{X=b&3D4Mu zaxd+T*}L{ii~kgO7jego7pZ&70ji{5zw>zTke zkYp6-{_(7nsX7neWRG3l zoD`y#g?3#yIkk^)XrxC^)Vy|z-Bp5&Od|qk3we0^O87d4ESljhmhRAo$d7gN@*6Fj zgyG0vB|96$UysE02I}FqNV3eJZXoffLWDGMD{KsycfKNK3%A_eMWM znx@ITNH`s#B$9S_-nz8cbwDRyumidmeFMy^9WyXmE2Qt&eHjPUzJ)6pF~#M}RreB7 zeQ9@k{q%wn7lT`;`8;??qrk}ck9o_)_wPi;7EoUEu(@y>^M8vTy_5?VQ}0Aibjj-v zoqMrdI_?Dw5tW$Tkop52!tnuc>=Bs5*r~Sq=oMN7GvvYC=_fXyC^YImm#f6-PwL)R zJ!=osc*Tx{#?>w*+pSDp%p8E=XW4SXC2 zN0OiyPU`woDY}wRqmuk9k(dV&>D6Y@kfm28Ll)Z5D0RhR{%ZBg!{-xcb+Rv*<>7vw+(pj7+ z!)dvBovu$9Q|Fa$Bif(oqDDBqO`HCV5$%>?ga@nGUQ$Lot#_4>_PM>^GJniOO3h#c z()rT%AC}&YEP0LOfq|-BYUo^t%hX!GNOwM`-b!rZj{xl7vDE}RLgx?hosZX#g7k@c zKEH2Ypg)_x{upv(T@~0BH7GNc+6H>{)R6)$Y@H`qv@ZW=^{=O1O!sS8O2g0MqTa{! zmp}^b#Ei(pN9VKsB3Q4GpGaRw|JGsyV@F%uJ=#-0JEpcL2g1f_SY={gc0IX&`G?uBTV822 zXbpg>+To@eoPU4`Bt3UI3mvl$vxD%OzIS?ZU#Gfk>}vPOAl`?Eta{YzJGL2AV}l3~ zSVX>tucWEjj3aBnap}aS<0i8a&r2HIsdYG9SG@2@9nN;T5gnWZT-EvK`vy|Pq8pTY z>#rpK9P)AORmrQ>Xp!=0USiGq??$w%#F%Ukw@fHYum*T(Z7o;&dBEjtgUM_5I*pjF zc;Ae8P-*eK9$!mZ)Bg7%C?u_eb3+Z;m1)9-SMx2m&IYXm^LXdD%2CYl|@{17Ac8kE6|0H7S(D_TcRjK$gz^ z_ZaOF>`_tX+eD)y<6-#d^b%uBY%zs#>nvS02Xu8Gn zO30Z;6L`Yh8`hJQ<-vE^$mr~AXkaoNZEdVEp?o+-o=AK;o$_An0fi2-Dp>Dfgz^wxt%4Um;nJDF@#6cygKtFz(0}Z-^_Mq zh$W;^efeqzhH$_1U~%lJll59)P5t+-tJBxTS+c31L{C3P)cb5X8!=PsYaI5AshKt8++gLNR)au@>>9{ zub#Yh4<9JY+oAh)nb+%{g@?zYVMhT`Otn%<5;@H2`p%!-du#T+exuxKrGn40F+Um* z>(F#L@rF+@b0$?|-k{hNBZNSnBe~N2Q~%$-+~kHg1%8_gLY~?2VA1%9N;)oUxzs_a zqzSoc7i>;tuTNVXr66qs<@y=QDrVv*ewB%)WlUj_OO4|9d$?!8+E?ttE~ZQnbnu?J zhhYKvcCTQtvvH&+gw@z)ukNxMJE>jC*@|<(-S&^&ZcoswV_H}BI5`eS6Sp4pos1-y z4<;i#n@}FTpZHeH$RRC;2XS%GN{l_(%%`rMp#JNIKvxs_xl2?K`dy;#ZyW z3jd39e5g7q4+fdYQg;d5Cp#-`OT^-`)w(`^mIt4K$vnIKypweowVhYtl55wQ@_bUoA$fvJ8jGw~zxrwMDe*y)!y4R#J9@uYp$<$QwIpy@{54K&$A&q+ruT5kVXm3bBr zbGA!4M1bB=yl|4%QKXSza<3gDRNBkWE=AB~5c!3fIOdNk(pL znT*}}KpXUGU$N(OHQm6xnE(;23Y z{BBW47{4lgnID#xS6zxnT`QBScs1~$bSyA(0TT%iu8Jqwus z=>0`V1J74%H|Xi8tm4-b!%T3oG~3cG#`Vw94}sgSdjx%#?WsS0Fw6>G9f{q^LiDx0 zQnOE)W9!{VY%AZjt6ZFXSt?kU+}@}kR&#E9Q5pOIp&za;3ePr7W-Lwob2egPzEs=H z_$4pNdAC;nk(y3?SuA0YzM~zU+jnl!>h1k#%Ajhg-3HcA}t;qL0Q+%8Q z_tNMT+>(t(SJA3yl2oIclA5Hrp^Z1Z(HZSwkCoJsE)Tub&lRV~StfzL;4_A5L_f&p zPi)nrL2}j2XzR0XYGqe_S7%iNH4JxKNy(d$7rBrfgZ8Vn%{!~e<>D}z-czpFvd$DF zmtay%hLP@Y0@CWqhsX0kJCEV&%UgY!HXcT#yOO*3mQJYwR-D zzwDE3$ZDPTT?-B&gO-XOTbgbah1ve#Mxr!m`HUrWra6?qO`*uJ@MhfPs;w!rHHVwI zPq33SNVeE$$q6dDkCafE3K}e8x$DII0(3ikJbZnE1AX*+!$y|JTSSLACF}YYGW~y~ET)+rw8ymaYpeGc|6UWY`_y?X|PC zi^2`YN&M97-cAZPEp);mUZK-^kRc@B)J;*wb|9u7Npo81n4-pexgoheLtRBKr zxSo(+?3vKh3Yuw&*_{jN0TB9@`n&#rSX@E5zx++vE*Jc2I=| z6}#+o$h7g)e)+mkT}3HBoJtSsn5CCTx0T4xp|9Q>1JkLWlfm-GwIMWUpR_Z2LMvED zpm%KY-#KfBtkf^eV&K3c4Rw-Ejog7$n-^y&JEpj_xV(o*_HsPL)$8{^ZS?Ey5SP%y zfWBV7e{<+}`%I@iv%x#P!^b@zi}D0YvQV*yfNWY+x?19j8B>5vqkDz-`0U|$jK)!J z=(-f?MK^2_hgL-Y0kYdA2;dxYd~)1S)}R>CfsRxQU9D6qJ=^%GU-5H=Uc}#@JRVNP z5{H@7mgEcTNbiAlA(aoFgp<%hTE$QvL}(_h5|X$4<6-CP%`v62Z>+VFc}8lLtZ#Iu zYQzv7*0vLbY`o<00eyV1BGl22@L}hpT~+DwfEdn+<$(Tu%<|s}yxcpr_{W9~2bEER zk*vEzfaV%{uw9hn<`-DuxUGuRHThm-)Y(0EMd7v*reh*-Rcz}eZFF_^p+zYArWwfJ z7pa#!>J(g6$4QnJY!iIOl-kq$M(PZ8_BA&mX1&_rZf55WCN#kn?L`teSJy`K()g{xd^k&Z0)yz4!04 z4>5W*F8Z8!V#8u0RKc{jBuuFWUqTcJRb3QM2?sb^;KvD1u$gmHphU_$m%G)U4clyO zsl!T`h7CvGd>&y-G~DI<8o&p&1V!<;=yT>1*8EToMu4)SzbEtX(I!4b5-jF^!MVKt zF--Qk`qeaJ{j7diJy&OFAyJg0t*YgrJQmiojh#`vno(-bu#`!k?QdnaYK_t^6CxW; z4Wd;tChJnY6xN>OOX>`#xHJR)#N-3{7xmwUUO3yoFioykVJbme+FpUjz>~e;3A#xr z?}N2V@?B4G!nkP@HV?HoN5Y;-$ox}oS-o+a3>8uehEZavohl$bP>wZ}v(eRuDpcf9 zvMAfOf3aPLZBo=K^OU?nKbz%W+6Aq~2*hW@Di3lHBYI@_9JXNUqW}S+R*=0Y-US$) zIkat7dZAjh)u!>TU1fRK5swAt@iWzjaJx;0|G}9p$A(9GR6Pj5#3Z!gU>;**G#}D$ zA|PM#?||k4RZTQg(plf3RFfqSr+CvnBdfK|hW~Fz z5cI$K|H~=C9zy)eH;;=_4JDOwzHiFbR>G81Y^WL2(sDb)PPV%ZjP*s|z79D+1veNY zwhie}%@)BX$4N}CG1F?-IFA%T<}(^dPtj#$-kB7P<4^gpjzCLWpKA5lXmMk|*QYNc zEJIs#1}Bqsp#?EJ8@IZ+xOOINnT;ZXt?SCf@<8#h*%O?vWpK2$Tdfg!H2;#}*nCTA~A?a9hcd12|8g zsG-_j*>aERJ3cy4M0?E>5FTg2^=*p{MAt$Phj07-McMJlmjt@PsiEp%Lx|ohJd%X z%z*;*p9|{31EqCHy{=7H<(OL9GI$!TcUoTSRJ4rT&|To;E$R0a=}PEl+f`)8x_!UUA=(o4wFlUQV^&btQE(OEEpM$}hix zg;$*@Kl}Ol-jI2sK5M?gc{}9Mxza8M3wr)kR$5uO5*3N0n<`2nqm*eZdRoA+?6#N7 zR0%r9hkO%GUAERE)Wn7*!x7Dnm;E$tT7doDZELS-L>(j{*y@lLNH(i2;p!cI71~-}?RT_G(rlu;aShKeHVZ zAwCfyhPPq5)dU?|?bH71w~FMydTGmMn>h->Q{9W8Ygr zEQ;_GjHf>PH{9>l!rJG^O}-eK+SqT}sUQPE8c0nW@5FmK!nVhsgsFCG9AlVXs*p#o zJ{s!SdbwKjJ?_;vgZ?Q%rr#OcD#wg&L5U7UH6^)F2(xU~IbP(j$WT&9bDXIQVv->*p&4 z2K6BKz69()Uq{c3oW>F$C;K<_J|5^v*grynoKWtz_Ic?zl8nr(JKm42Gu}4NaBWv) zyJP(1X4ieOf2xwEN$Vs(C85UaZvSTo4siXI1Bb$^#wiI`#sys+M;&}}r=Q#S{==Rn z^z8On`q^00LgW)SUcX;rgV-8r5`53UPr0T%f6UbU>-(2o6=A045iJ44x#^1Tg`FLS zXnMET;5%%PKp41iTcb_ZtgR2zXWICl;)a-cD1R zRZ~!zKN?ey{Q1=ZSgDljAb~o_se-9WM7`Sjj(Uo^yp!HuOPQsoW#mV^i&D2)ThH$l zujYs+l=zj!4jxMFnR*xh?!}J?I*WM*=y46EHT{YEj5J^bNr%#w$yatXW=fI{E zour8=lPmzbAXC$wR>Wk%P4f@+%t~)`n(jZcoyllvPC&5L;H=g%(@MEwP{StG{jpGC zIes}V04H@QH(h@)mk(JtFHG{Qq>@SyMOeX!HPr|P^_|I2%=?iuFR-mf5_Pc2dcS+f zi3V*1qS4lTK5@a02+Hb(I*0o=9m)3=kkCNl;Ry+ya{RMdA|-uW^{6Q#TH4KRL*NKq z;56z}a(S|jV4-ok%5t!5mct8APZhV{BwEEjn~Q17-BH<_`Stw2!{pJAAG}7V=+bjV ziZU?$<%jEOh(_)^x9JkM<5g}?BkWhN9cbjz8PeQ{f@~|XRc^U z8I_~0GNr9F<*AdcpsJ_Wi9xEN&Eh2$K}$6)Q?IZ1M?6U9(k|QYm?ysfnDA{lkYYK! zeP0`mA)~O_4H|V&x;jxVNs7_smeDKu1zeFXtJFuDhQ*I%67w zn~?Y?&*(%mCAzn&LVO+qkD$3N>&}2;UH}m*e3?>PX3Wh!;rKiNubmz19Bs=cW%m_p zbo{qif|Df6Qns8yhJ4LfpV8xiKcjbhrdf{bpL1DD9pF?rpEuVu(*~I>)TeM6O9zNt zQkli0WP93ySI8D-C~c`FQ09?CZ*p(@bPhgqm#s!`*~LB`R$XCR~QF7C3{1Mo z{kzimb*nP7<>FK2)!9?&muf=%+pM`> z!1)0h-^oz)IPh?Ucq51)>NC^4!ecacF$~SE;o%yi!@Udp9|U0>t{SDZxPSJL?Dd!9 z;%2IE4u|X*mI$b<328^^H>>?WJy28F;bCc&E(kv^=dU05g1o`N4dG-Nu7BGSNd1Qm zNO$L-vn-t0=FL7G$Ws|j;|bu{*bro>N>_aJdq$Ol%Ac+Pv*U>lZ`g(`OrDS5XG7WYVAl1}{8j`C3VUfSFWvL0BxSdc z{;zMG$0$kQL7LnFXWz*l0hb1HCX2V)q3ju{Y)63$cgi#CVea_Nue$R&K_Wt7C3?I2 z^Gf#HrsxcGf*-oEUMyewFfBOvn~G{%TSw>n>e+Oq5^ERT70&edsY18&u(0Am38w@L zE}*=earf*2M*5+5%px!kxdLuOji%Z5cP#xsOucnj6yN^`iXtKiBHbY&4bt7+4bljL zbk|Y~NOyNigOqeGO1E@_)FLgr)WWi#JKx`PpXc6x=AU6_m@{Y2dB-cxKo6c|rS5V` z9N#OZ4Wg#-bRuY|2g%VCBo=^Os9+Qh$>9%7X5AUJbLOJYBPf$^wNzKH_{@WbG{_-f zSMN5-ozihg%Hk13kB>xhajkAH}-3T}U3aqWq$aCFc@z`)LXlc+Uc2ZB~WXyytRT+=P*T zkw=UFp$Yn^fdvqi>(g%a`wvZmzOl|fUWRBe4rB2O1O?#MrDn-VOmYY-zS99IoDUf# z7~>Pwu#J$s=hHkjzZ=u@GO?XJ&R))|{fV()JWKT-nqilwyR!BoM;xmG|EAw%Tx!tv z#*rmrTx-frY-`egJ!j5&3&-VC8C^^J$5jtH4lC->fXghZv;#GDcX?OXYc>792N*gg z?Eu;%R>aiP*2Dca#(Itu_vz^EBzjYVaKklY(pT_OXhxWW#KAF(3Nem+T&wL@B1hMX zp5Nz}5o{K^V)m$J;YNB{MWBW8M_kL9MUC0_3!my{h19E(5}iL~O;7%{kAZf%%Pbun z_Ly>U7EcHPAhLx+rKWfI{uXI0eC}AVT5;v7uWvIQoY`1z4c$~DyN)4li?S;{TLkRZ7Q;hRkF{nCKPqYWFH`0 z4d-s(2?n(xZJjMb9B^G18dE22%@o@{%RS)hxeu{dyS3KbrNev|rA8>XxHA6m2v z-184T=U>uAgO^_iM|b*JS|!d_e(o;1aD~)U_b@J>5|F>1a3uSn*Yp=lO#49Xot7D_ zF;~2_+>t=4xVOizTCsXWYpy%2BY!cCZ{RA07f+=F-C9x6Z_XOy0>H*>iC)h2%s2YP zkLrK^^u3mSNaYwy$!Z|E-M;UK&I>R3v{**LKRS*hC2pg~h)=TJ>K)j@GP1bj0hcQc zY@2foO1h*4fi?84SC~V3fS!w!0L;_ypiF$*tHX_ zQYKa5aGWE<%uzBkvDWa1`UJkyS(^X?M>oyffu#Mq3}3mlOeUDgRi3G4y0R1dd7K|3#j{ns9-_p2Q7S?2Ysp3q-o%Oy zY@MHH%IIK6>-KgH`t_U0uEf`#_lMSKL{FJgZ5Nt@mBejo$=otduLPr(ojm>1U4JeL zZ+a3D@joKnO|V~bzQJO|X`irt5oG4q7$fYf>UQ(7RLZbJXIPnAmSxCoI1pb?cUyvo zt^D_@cu@hV(&; ze);rU+qJ$E{jBizI3k|Iz+z|4fFNLg#}ki2d{+6@rs|YR=|u@e(c>r8=jNs+#sd$i zQvRhfaQXNZT7auP=EPTe13YlGW2#x1`PLRzCOQ7Pon0bjwc*QNt#dSczZaj9CWemW z9Nei0r%i!<%LzkQcT17bg;jy7OyKiIGb)Ez;P?CM!V*rME^Nw%ji*%^S-+nLw%4aq zG#lD}#FymS4l!CuSqY*;5tJAab7OGzQ?^{|^pBK0V5hRk-MRy!+w z765osNhOJXdR;Z19Axn3o%knDIa)>Da-$MUfETiDfj1N`goxXVKuw&^hj2g5@uS)# z@9XsFq{mKVXg?>F6faBky07<{PCzoVx-SoldJu!vjxEPm_C;0;-pPvWKAGyIswSZ6 zk39a_J~A!dmu4L_3?H<-(9@%2B`*Du3&hF`f*BJ}f8$P%`XP7ungj%*BBm z{o+u^Pcd6@x>4SNZA~mKWXqT$Qz6LcU1j`rkVLfoZwpm{bduI8&_5h)oH2Ks1V$kG z92^kK7!!AHp0P&-`s=g6%PI0@Ji`Ye)94V%YBmG#ge`UG)g+Sc zw`Ug9(aw}#bBjG)uV1_U*AGOc&#H~Z;tJlQy^zn9LW3Ofw3!AbPi@J#B8Z(RUs|rS z;CwdFIweeQmHXAD&>zIhe+VDfQ)|F>rzRZwGVww1~x?%eg zmkuj2Jqi=&>B$iKavw?;*sw!0%jzP5Zv{($&#?YcPA!rPV4t!!{D*eFmvT3Y7!*F} zMb6v+`o5+)-WQBqU9R zk##hlJuTw}&97o{MFD~>m4@PkXF5%p?H0B*BkOf`<=64-)m$v-dL>2hUr zUv*yLEvDmh6+lWt@_xQTC@YnFh=}58@n5BUt?Kdx*+jg|{`qd0&Tr}GJeYUUH30mJ zdp9!0wn!F6ngbRPA9On4rkC!Z==;q*^92i|6{|OWmRUX)bKM4}Z4$bFB7pyskX3Mh z#Lm*eF>42&UO<8S0&HAgvtE|~QAvvu1lGl}x`pYIB z@%C?$z4CZQs8+>`;aRlsTeWq;?trm#uHmq)C#jD@P?Ik8kH&{dt-R;^ zoXGQ(4`MntMIdA!iJXe~nYcVIdCQ%6u-mu1hb0Db;J zcx_6Q;Hk72E&Rcq*h=)fl5&@x-Bj~LMd#OBzf$xK_EeYW^DRCcndqNCHMxwVmyVU6 z>4|Bn+P?OnK*}R!fQ?+#N0LmoL?H4=>eYZau@b&UUlWOrxvMa9p6&Tu}+lzowK{)R%^M;A7eo1JK|zWadVUectZ%HvJ`Omi++ba;ug65AF9xaw=G7 z&6E27li^zUf9vf(gN^|HRwJFlDWXw3YN^H`rbxGAoaDO`Y%CXT;seu_5tJ4QeP316 zo9B0^k+-n{Sk6bn!Uw>-rQ$?*q|BQ*5#`1s&;F6-0nIM<-qLSvBYjW^|1cDf$8^-^ zM9#~3J+W3|0D(NLQ@5ZtmI`AwDGpm$5HhTk1Gzny=Z8G3{gXW_td+ zw}S2}t@3n=rKRf%e>L}_8OaC=98{>X-PMBS&~k%i|77l)pJ1L0zH6TjS% zw+|X<8mPSMsme+Xs<*513I(6ogwq0^p8Q5~(vs)MD`E$+t3Cc*qr07rmnNV1p8344 zloj%k@U5Z&@Xgt?SnPu#?7ARdVePDOX;#$>EzQG2`$y-s& zX^+`yCj8$`Dl>+>v>({v-SX|oaoox=ZKbMXTWSsLrXR^37jO2N81x)RxM_!v^B~9r zA?WlzB>Tov$np8bR+$xnf4L${NexcP+yFyq=_Xb0VJg&QKZ<8-zq_)z1{8IBYO%ys z*|Y3wCnS`}-obhxVYU#%c&DR2%HxU=6aP^q2?k;c%=UAjdoDv|{u6g1f;t*MX3bzV zV3$Dpf}oTr>mA6|KPkNLc%}b&+2`6*4PGR_6{&0C6YM3&o;JF&eNG0hT>D<%8>Pq} z3zQOUMzq}~QkKb|EYC(G)r&n5CbX0Pp-s+CJ~__M&ZO>~ZhJLnlY3&Jt0wChMR)KsXrUf#61JlQ`;v)FKMJM*PdxGI{^;pnXssb{ zGo4($3p`yj_Wz-{h+SG+`;qNDm-pqJ{VpG-9XF7*k0WvqcEpqp^Ib5f0_-65#*U%| zBO0tR0CuR5NU;UIqrptO7)>i^aAmb_V|%vcO7+DmND8^HRTxxvD8=I>+EM7kUAu0E z2-I(m+`liZ>g-^rK+Cjxt>bjr^}Om`IX_;$YaK0d;EpdCwKk2qfvjo;ij5aHb<;+aLjhp?FvEbVUHrDPk!dl6cjB^D$R2o-0dp$qyCjmBk#MK1h%xh1@?$)3g*-W}ow zlA78!UgEgnAr4(=&9VszXF)vN1$x++RIy#}36)lmC*!wok$xir^|RT&{ztgr@&v15 zRm>-`Q9yV74^4r`Z~{{{?F}P-7x5-axOPCMUO|ILpXVT$Keuq6V1(c1U#V+3`h4G& zzJinD&KZT#Xck-LwE4{FfZKUoV-iVWCxd@FWEXZd>@f6jw9tV%a-X*B*q1~0GZX8k zY1*9pBX~zCR`Y0i(AW|CQ}tUdp)VQ+^~-^08#F5ImgV-6*1Zw4Wyhk(aSnP@+G+>F zS>i!L2=nzUBfFkHGsDPp>DF|Ud2Vm9qxrTC%6i_X=dD>C?XV5?uu&$-jM@g`=ru;| z+i`SfUB7ahoKwxh{sgvAKQ3I{SEsxCaWyZuzdF){Uej*Gb(~zIY2!veeyp`69=*6v z?F&eF7prdwbn&VC6Id(ug$S1 z$9Hz+*|g{bKbOwh^+wSJ6l)wqGQjW*8uRYCHp{t}l#QHT6l~ikB=5!EPLD^}&j5UQ zkyLpvk0f;i^+rWx6|fJrE+F@V5u=rV=YAf=XF8O3Ih?JV78@7}ezY>F5PqXCZWMQ> z_E`b<){Yq~zz@U^B*xLS@D!t!JJFf?LvrTDMlQzQA_uqnh%_|@5@vzx{=lqP7|(pK?HZ8h26N8?truNq+`OxWaOg4|4zJ-`zT zuK2Ly34>BCV2_Gm!x7^fF?{NtYYv8L-63Zc;-6%i;%Uqgaa)O?(J@+hhNS1xnfS_) zf9vs0p@^|JqI~f?-L;CV{I}=N0)E3buSdg;g7t86N?1%MFCj-HQWCv8b(`Be4($O+ zeP9MNEpyjpwcLUWvnuY-?r@blX)d}r!RdQr$_ zook_J5?X;(O-+^0E1c)@M8pfcPFK znIfqrJqS2RqBy;6LLP{tRNEo&h@C>du@;jJQ1GSzh^xnW54ejs`p#|1sRsfX2jE3y zi4jnl>}$KY8>VDj3j!<~T?GtY8x4l>*p+>1fK8H(a;Jq)xXa9Ydzix&42y=P z*&vW1;P*fQtAGxtEJ~$CMn$9HNml!{LPeIM=zT6>1w$S8tTe1O1?c8*fYz6W zc+Ek^j4t6FIeWynwB41@zCK9vQgq%C$$@8BK+Dn)p#A=3Pp#@ciecbu8}^7J>tdc; z8?TL8P&p~w%kRMNF!eq*KO!eXs9YRQ8M|gnQ_f&)9SIM69hpd z9!TiH%BGBpWZ)NB%MV*I2@}m*u?(M6K@4U8hz+R)F`X-QKCE`R=j1dEpqgDQ@4{sz zF8)JDLj1*<~6OQg@@+{#%s7G^+M9RG(#VVyO-RdZ@}Kn>ZR2q_;n zRjYGrZ&$~3yY5Db^B4vrJPtT5;a{eFX|pX977Sgybh!V1zuRQcPgE0Y`B#no@*49n zhRXCMVNU3eJMaf!Sl%HV&)}eJx57A!@2xNRns`8=G=-3EAZ=#kANUWA(5$UF`9p}>h13xSn9n6; z%R=EW|6{fnW54yQGN`)#(6Q5f{|G}XT>x$RGoZOt@Ci=cHo9nO04tl(B32d{|6&~+ zVR-%kYl%_14|5~`xgAGxiSnqMCPAaDX$=uWss(%7V_M$d4eg44&D zPEH2kZl`+G>`c*hB%iLR;$(23^KC@xNc%Cr@Q8JB^mGZV+{v?q$L-|oq>FNdc)^z= zT_5J+kt5l@M%5=fNUgZ;&R@j9eXH0W zUgR)vmIWfXJp9{}Lg4N#R#oFJAYt~86VYD+10#2%p|eH&>{8;0z)APYc<{5Xj;te- zsFyrG2V-NZanJp>zXml~Gy72ljLHAYhj;=MAK6?)=(W?wRxE=^IR$9GAm*idlNFp+ z0J#{1(qKmJ(LyN4 zo2lT%u>wZFpf!{yCgflQm?k6;{^CDH3-Uw)Ouav=7EqctyN~_OQMHm_#(gE=Dq_gp zr70!3Iq!3WqEDE(QpPQXW!7zntcvUu&z5qKVS~FAeW{3Qb5}&8Zfo~Kqw9A8`)y9e zWd}}IdJnnRL&L_HO$^nK<^i8yRnakRhFocRgy}vyyt*6LEOd@NQ6h+-VaD#Mcp<8x;KOm z&1Zb6%gM5lP{B-}st_k9BT}UdBPR!O4mKssb|5^)B0A42nxfl7??&C(7CT5*$da#DGPk@|Co}hBU{aqb^z7}asZ;Lv@V4|(x9QH_Ly?%T zAsd`;mLByn4`Y?fy#t2kqqI32-1hHDbz+E=h=^??s&NL+sID+;%$r|jT8w)oD@P=! z5{sqle!TctbZ`*P>CaRR?H{-uX3yhcVY>C$>O=Xz-L!9?&^!x;dHNlnKST*eFLVQ- zl9gf~r&q|qIvFQGH1J41*vH3oyla57R`@x?i-*LOXl)^WKvmXQD?K*d^c96waV{iF z(i&L-*Q`3==3CE?KbK?(JpEWUNwgd!5}&dDjY}+TaewpBYsA_CLNzo>s=bl)hL*i*VB+Yk7a zXVmO8%DQu|O@q>SF>M09^!u3Mo;=fAQ&H3ofh4BO@xRN|i2HOFKXD~kG0e>zprqk; z9Cl=e)H~H}Z>VuXjzwtZh48y%@%w~0hBLFmG*1Rn6nV$h<=xW%(oXLn2Dqmi$06*F zw7Dp^Ck(;l@BVg|peaUDh3>*cxd?ukNh1R3v|wSZm>Tl5-Q<)doYjk&l7! zhb;-Y!yXkXx)A)6+hWIjt}~%?lZBmk`=$&D(IXbl^W43$wL1v(ndQpCkMpjKZ9N@! zhJp)<9MavbmEKYdYH`jd1rCD=m! zeN1R?s@!EPxcq&eC{?Ag*aidP+#g83R7SrwGH>Mq%mvKLbNV04yHV@=;S(+L|E3%h zsp6Z_iI5Pluxqsc;K>)rXuFAk0#YSH4gRv2>qoDCpc_u?T z!?IZFh!VmF=I|y#4gjB1NL2;G8f!lsY8v}aiQY4%=G*4kz@4NNN1R1GHkPcJ(k(THWN~(sN*p9hyrK~_sYjy=Q_K$h zellxl8c3$zU+?t$_^hlD!9=g5hFiX z{zD6ftUCIYR{#4YL$yqpa2MN7NcfQYFD+h?u0G)LKQt^G=M!vlk zL)*IO7At*WRAbRPjJ({_WU6h>?3n#4`5Wb^)UhzD3_ubFfl%^o~KvabKHh;qqvVgk;( z6qx3-fNNxKtz{@Le@#d+&f?glM3zA`TG(mqrHumPJk;|UJ=c=JGiHF$g(b?zG4Y6d zVq=E~mDX(+ccir(VLiV*M;t7CcAsYRB94d_SExbc$B2Pi(< z`Q||<(t4kh&8dmH$1>qxH{te#1k*j^s~TO>GaF ztX`Vr@><%&Av9uo>qRuHrJw5FzIu6Wp@g?>54 zl~}Pz66lMQ9pEc9lA4^xGQoq@2o7k$0jQ|YV>?&kU_ zagL$~Sk}+%D72u;@F}A_!74Wnz4(CKY8*R5%w27vDtGr-K{Cj*QeLjo+D&2`g6(li zwV{89V{;(yLzITo4lC8>*KzhGAM#K6C%zXYEC-9|HGhSUvp!Tj*p;3jdGn^*v;t^~ zHP`6Ei(WPyxd$nT`tQnq6VPCDSP1E?ZKPKr-uRVI^`dsd$D#xcpwL(3c>6|o(W&@!+~ zUM@WtBU5t24dmw1+=_kP*HW}RIWqO`w^$H9ek4SayRkt)EY=5CRxt}|$IZ}OV<(|9 zokFxv7+5``%n-d^&G1ZGtUm*o6JLaR z7$q;hCsxHUpW*$!t|Jmmd)va%xl8p?)T8o@T^c--v)jHyc-XiqS?- z<0s8(3s&M#q7aQYTO7XdxwHgiHb}RoLfN{9$J3e`lkfshJ=WS1s1LzUWGoS5r1dK1 zZ~nTWen0{9Rv<(8y#-in$Q=Ivtu+=OFZt&-%Cy8@Bq|u^{Kl(##$RGO9(0O0Jd|P> zl7x7>a+`yczBpGLecB&wy5lFudrPA}^m-ROWr>(*6mp_zno9^VU+|;(K3|=|-6Mdn z)p-yM>tVduWO$2QM@|7FUIVMju1Y<>u!CFlyb~|{ESW5cyr8J4`4f75n)Qls+%^T! zmw*6&2}lYEqinsJ7B5hB6-F+SGtDyRGtn6tSDqop&K`O?V`_u%?bcMP_ctn^LjT#-`zt zjh#*N{;*+H@VJy#6uYyf_T2k-F`hgg2JW?kFJ$dLzS0eKf@(d>bcLWK8gM#IAw)cd+& z&J*U`I!24vnQ^U^)CbpLnEMrgDN#mq3TJW*S9dRLP;(La^B5I=!zK3sCKxA^rXKo~ zn-j-kN0odQ*Sy}PlPRS5qCbNc9zk2ohcqlQ06Y%ph`XD*IsmT&nkW$)>ju2`HFC}D z`0X4u;FW42M$1NDJLO5V<#u7Dt;6-&!}sC>eu%vhIPV&}FFe!KrnwR-=7hXIcb4Kt zo+3;S#syB*gujk+&Mr56!8{vx|Bb2d_h|MJ#;{jHUWluJTcF;plO95!t@6LPn;?x4 z1|Cl`>iR<4!0S0zgPF@ImBDZy58PUW-HD(c{645cuKU5O_UlHk9HZBW*_}=W&mnzM z2QW3$V%LA5G(n2hwh@LhmDmbtPj zV=fGr+^lfCN~5l8ifU~?Fu36}I~nv>D>q_5YP!$$kHhk}ZS20=ha8iu12{ibi*4w2u4 zi}rM=c#>dh?;44yRT!KZywm78uTQ}<#E4bZxnU@nPMtWW78FalM_n`MR#jklOD@^!Dl3XV1u3g|C>nO%QUXCsj@sF8GX!Y<;< zaE~)f-7iNt->;xvw|3Ww|jTcWr> z_=cm2YL(mzJf~C8$;7uuCmyiP#c!o@XzU4_IqZzrSUxUZxh`F*ej<1G=8O`V{r6I? zdi7YyV+iOLLrHTRme!L?NC$dKr-!u|eDWMASH(S4{ujd`*&^oH+G zF6sFCpCRVA%20$CoDgnf0I#g^DBs-Cs4%yOx8jl%&deX%YDJc5U*|70{+eDY-d)9s zPMGi?Wu7ZiLDs|XkOyuD)5(XLVKolNUJt=Hl;k&oxef1?Kk3r2VfbEuB{V#cmU@L* zO|XbgaWY6!pctfX37|=e)ll{y*9EIE3y^Kc3eF2=(cvfjiOUsprtw({=;tX_$b{i5 zWv>Vs654FhGb0NVxM2k%80___deb3&+SToP)PeI0kB@y}rW)&+YC=EZp0!O|En6;5 z>n2(>*g4gzBj)zSxmFQ|h7>!p6k0qpD`6UghYF5FG#;oKtuzEJ9d=z;mx3yb@2+ayF=EOZRoy09uLgKYm?M}h z^Z|k~43feD&{rTF+dClZQSE$Va|Q3mnB6X3y4S1(^)FP}CX}~(yPstxZ1CSp7ctLK zFeCTx^2Lu!WT0B2C(EJ=<^P^+KdJfW&qvhDwYH)yy1_)aC{KPFv;4-(7oZ)-B{@T- z=FdKK4-G|_a`JBT8#F9x|5-qmbq(-_ZeXdy(4k9>2g_m9-%fCkX8Gdfm@8kK4prnB z_Sz5_e(jok`K^m}l%eaHHzX6K>M@Hnf+lObOv%Y=CEr!iPO}Vi{b|uaM#C&~8_&IU zj*59q)%@tfa1ZcvKtgNKscC7=9dXSP6?G=+WWTYRcHr)_!|=Cku!m@CFuEZ6oI`ak0o zP`0X~XG(6tSAbRm6b}gn7dA=>^1C?6!;p&W%fFyA26<35-?rqqXj?Qf2{nBk2iSH( zZf9cDM>;xTwF5WAgd1W=YzHyC#iiEgHXESW_`Oy^JV2d92!B)U^%#C}@hAb?a#cDu z05BwfmecVn+~F!IKkz|yU94S(+*K8@>8vS5_(P>Rm?-#js`rF82`zK~4ab>6&87dE zc3S8#D8dq_K*)s1+DeW zE6Q8W7zNn`Ba9XfCr_ch8R5ckY9*Zvob#w>nX4f(Ai&H?Zz?6kAG9$=A#wH)uw`O= z94=Ctce(tMTSv(tsp`DAhdEvdr+#$u8PDK0j9rQ;#A@8*FLSn!NJFEmg<%(@Jy*YN zs9C9a8poGkI=w3gJB9HNadP!;Kp(5`O6n()y=2<&g-5;oNVFJ9kwB4ZG{)4$ zXnH=i3ybNuDVg&MjGVHLHg#b6wDDS~*9?mK^>@U#S%L{UO305HJh%L+;BVOeafF`rD_Z z0e!u(#O>K$?3-9mils?BvdFuQjwD_&0h?4NSXGe}7er9Jv}BwaY7t%Yx5&gn+NtK< zhjOp6{yd&M(I5H*rQL3tRXk-MaJxJcd3PB9qQhxn;3=uJY?JfM$P9|CV!yH-3oW03 zaUZ^P<~P)s81&yMlevmW50~_vY8;ZdEeXJ008lI!zMWp81&BGrUn{kAv~>iIPi3t{ z(sv}{B%PgX*4DC1R~_YiW#y8IL4s{yqq<+OnR73ZIX*;7_4S{fX|ft8EG!c3ensK=tk`TCF2zm zm~DihVYaBi^r(dXrpPCbYUyvRnjDE&S?@D3xyaA-v_};OG{q}03w^d^XJufwMgLSl zbOuKhL(S=n9dx*8x6H1&`hF}q&n_ebfHy9?#C3h_15gA;RTi!T$<_mN4}Vw@cD#2# z(ZE{ulW3ts6KNY|PX7gP3y)}#*;T09QFx#hW1MH)wvSXqofZ|n2UTt^&4E5RrQagu z;VZoKV5g)0;mIr~LzM$4W#V%m_+{gSq@!FIt7R~k9>!nxGb~AbxKi+ke9J?aqTG+g z=lm_l04rw-pRJp2to3(}Xa3Z+6Z5nYNj)wWYi6M=B6Z((X7I)VyAw^*bw}OT)OI81 z>%6yuRRy}Z_c_xa!$t8e!BpRWr6&cs@xY9rcsW4mKUfiBB`d(md#O^`5E;QU{vsg3 z9-W_$Eo?gE!HDX8oaf#?(X|!;Wtd?Iu?Nqnfp#pAYsl}#(iA`;gtj4A(P{QN-XK-~ zU#5JZw#%4)P+dxq%i4bE^CF;QCGx*iBoGk^94ii|#bzx$mxB5NUzU2h;1-rI1e`2# zka5Hm{0dY0EQQ6eTiWm}3n6$fEvfsXQ#7&FNVP{jZd1uRFc{%3ND=exp+)OQ5+En_ zIJvy?wq@E0kpO$iqV#Ggs6ya)=>7R0KDzjkx%kJ03#)Cf`LY#`{7Fd*EXkTW!}aYo zG7^w+bw1b@N(j|+2rp$NMuNGOe*MooPqH{=IHt% z9h3BNzcU}~9ukU^U35gDUH)@6F3jbeAOUM`|_neiW zr`m~>mth^SY82ctGb-EZ{>^x07K9t*%Gg`#Ekk{zR$ja<%mK3Z> zQ@YmzRUhX6(C989BK(C;Qvu-I-mb&P;1|ERY*t*0SgCC>_oYja*a}!xdb#*RU&hM> z%YOY;6Uj$;@QSen_3?vqP`W)XftDS=x4e(nKiQ{8(eDmsGCuFMSEBfVGzVzX4EfSa zX(8G5Tfn&E9n-kO^FUHCxhbRU6o-JZ-^c}r5PH$5;vwvl4;A`qF7FSxKTf~g=g2}6 zA>mnmEAc7j|JHae&`S++}2jIBY8tt3eI6 zC#5HHl>IM?6H$!7J*4G44N+KX<>r|!3$a95Nq_0+Sz!Q-Fvs@58i$1h1$!x(_8X3d ziA@bk@5zSFjCUtlzuI`f0{ozt$X(`aDHica5F)=O#G2_ZA)|?RvoS}O-}gV6F=V;< z`3vVSzlC)UO0eMfI1bnGWxv9ShgAl9r#p3mgRtBq}%&0gh5$vkVJ~|A)T>56g^upW zA4g7)1EL9vU2oM{T|qZs&tH*!p@q7k@RZUX*+njbNS%sLwvSD-3EoJh!*MeaI^OrowGOpv9F* zDrgl}oJfQl$qvy;ImfMN;gnn*9X_GW?YHc2YKMh(`Ce!q4TwI}T`@l&Db6i&=|^@TcaS}9tZjX*9RXa8HXK9DECy}98D!&s zhwB!q?Wo^42P)DF-T$T1oJ#$}4K%k4(!pYgc-SZ$o88<-t1J9bxjRn{A54{atUv}L zwy}EUF#_l;d2e^skNCZDX6}=;MZ#A&f~v|ve6tju<)rN)PV-#z9>a{^i%deX+i=Nq z&>xwnjdZ(7 zK&1!~aB2dVf|{bftgZ_-0@jT03z)HN-kKpyY$z2+N=FIExUOCE6V~nb-KDU79@ZAi zRFaXq$;DDUH^mddd=o_<^H^Q@AJy!ax1Clw^7!2@4&uJ-WaC?^=lSv1^Xa98F@Iub z(t^`Y1^{;A(2Cm%M6;8NKbLr_eS0=8qY=GQ%kp_wx~3|b*K3{IjK!z#Yq#DuDQ??; zoEU97rBTvO{Z_5OfK?rm9%gP;rj}LZwz1BAzTTH3{a{;@lJw3zMw8LmfBq}aO>=^6 zOLmeG{)H_#FGL%@T-J!Pz?+Jnqy~>KcNdk}8Wafeumptuh6^wQ&;-&A_8 z-FQ=%h%v}`q3R{vZN?XpUS!hUJ;L_P3*)*Tg3HgZiL1%J7=J)j6msqAyAG!M2uQcknNaSHfW;G~UZQd<~1 zHu>Tk_cxCd8$L^JLE1y0^2j}P$uAkj59ZXOPR`*t>}~4q&3)GqsBDt#!QT9|XkC(| ze;}l-s3?5MrI9xM%8SF#0QeMq;HdbcEisttkuv%;5QZf($zQeAZ|bHQespzY@Q=~E zT5){qx51vFu0i9xFFYY`lP(IMMecJ$R}T4&j4b?MNo6GY&p7UuRk@w_smIfv?(;<~SwU&mJ@E-O?h4q&}STIBW;Ne2U_srnBs)hQ4Wz6r<_&5#5!=jEp(qW3Qez z<0#WyeGgtDQY){s6186@EsN4902)2;KH23mcLm~Pt*TWj?D*KY?l_%{n`2ef@28KoAJ$tx!|0>yF?jUFs$&t@?v+cY zkmz={9~WQa-(*zaoet|;>%A_YGl)wGa)KZhh!sX(5OV+BX#ev*wY;OKSE+iWmkKqB zx8_=y#E~v+?IQcB!ZBj7HtL9Y;GV)zX3=|}cj2jcw%YPTLVi&V{jkVGRZjh^aAkr! zVdTk)R9+^u@L|`|6N4$*GGX@lcfTw2(*cNW7G!%wtlp3Pk$HpYoeN$$_R616syCM? z?_umc1q&u$#ub;-%gadp3+&iXY>?X(3-#mU<6Z{aTVMPXeG;oGuU!)WvWeTeXD>i4 zY1iJ>;gdz~htp6$ZtUQmTnH)zB`su3vJ`Y$IN?(iE>jt)yAG9vhhocz zN{~gYSLJ;TNDMKn=D@OEteOjr2%{AOgs{_h090EsxS&X{1^F9>fy#RjIG8V&>@UMs zrNP|WEPL09l(X7cXnQq?!(05mx4Xb!gEBx9(1H-g1)^0-XnvPKBY%H#aE+=_!Da1G zf&md5H!G4-fe`3cq4bJ3G$P4_iqdu2YbKtx|zm(|fL9N=H0?#c8;Zqb){aO=?{|#Uswlj}9U&5qBL& z!(FuS#*fXH8iwddca#ycC(4f$gkUK~-0d9wZbY6MmK*js8tzv`Di8ke(vGM=;54fS zkOQKSs0@tgiCbuRM55~E%Fa0sZPxhKZ56z;2Q}2aj|x5lhU10u(P2zy(PXtL-u(^( z!a4fU=>N{cC&2JX2t1uOyJOzTLJNj;H=lLAO$S#PPc@>a7?V@Sl+sy=ntd&MS3f*4 zUpzHCfrkJRmq~6;3((4}D8cc=3r>QqNpxxHx*(2m%5>?#1-C5uy#ham^DnrHta%u) z>1=3pfpaZqL$K-%6xl8jh0sXb8K7x7ltPSMPUF3Q*9+Tv`ZiAA>e^z;p#7nAD|WkZ zWWODo{TGc#En?(IyRBnkov9^^q;eV4fdQ102G@bO#0s3k$HM|kdQrO)#t9kp<=A;{ z@J7T6hpdo%#HjmB8-0PJsD9y3gmvpQ5&Y3W%ooWk6KnBZsSO;(V)C)M_F7Ub(2A|0 zC(oDBCDkzV#2!GC>;oFjm7 znZ>n@kwrIp!L?25GyZCEP=lUx0!==G>Cm)M5(E$c=C8*n6yl&_lMU1)uYC!Whi+Fr z8e_@hYqMYSYW*A=a@6|YvKqcrj~qWbchhga|3mtk;KPo825VK~tErjk=rR6BRW^cd@SM;?DC_Qaie7-CkJXRqARq%M!H3_K&&sKeM0On^y14C66%~vUU zsR^HoU^pfB5-s?zb2L4w;Kwr8u=)Q>kNR)v5s)zwp$2(Xg&2V#It!n9%s2k7q|2W! zSqM*}-z7A%G|kcq!TO-!Sz7*+05ejl@~Xs!H0&HLOwIv<*Yy-d)W_McLUZqWnWrq= zmTq2EQABRu5t}q;83q(VTD3GgW1E?_U37J-^b8OrAymko!IZUta{fl}Py^sC&NCFl)2EFXg7ezvKkNk9nhO zWI6MiASP_Tk%SH@S1q=37>St%sxf~N!oQ|mxivN(mDWD1BYl!2tpiYIVZWkmzd0_q z3(=HcmB*^S)iJx=j&?+SHz+{l&lG9pPr6kc_nSuw99O>Bo*I4@jZS()3e8h18rnKh>itm9R5HF?@@0~o?Z6+f2cZ(fVR4> z3kOwio3hJ1d6*Aio3ffIJ5~CNO}K!!+(%LMoDh&x##S? z*Lqf7M)({vUq8u7ue|-;BG9m)C}($j!;d)i(mLUpQV$l5DAghUGu#_6Mo6dW3NU!j z^}6x;w&^eh(@GfiHq)Ap&Qj94w8;dK+Occn8%S#tkN#)@P2AIl%;((}Pj_aME}cnO zF1zNdtQ>(pq^bh)3{rIii3BfoaB52l_gQD-zfX^X$@e7B~=Aa(fl7| znEy})n}1v+mv2-?%acP@$VzlA!W%L&R>h_{`x?;S;^3MY0r@c{94tk;fD5TcMA+*x zBi;TFZ~`rSwf!Hb4Hjk!RShwiPOuVejxxaYWm)R8Q+e|sb%teS|IR8RHHpeQME)Zj z&Q)2u(niVkPli&5ST5C3YZyUio}H-6B`J8b7_hw0IufTX+GtLB7@Uh(;q)+Ym>@^n zX4|YCrY|SMK=o;a z4U2bfkOs}OnmV?ebw2!+dXCHlHGF1}d!G@&xIq|{x}wWFRz~^J+y{F0CwXdcmYA<; zrdSXmdV3aJT>9%v;xoMz=jIB$xsf;1mo_?K*)dv(#N6tR%(B|)^C)?V(CxM0gjFj+ zqVhw&mIvDQ6_)Lc+gFC3&DUK#CR482*~rqq^9Zq0zQAPRvYZQ0Yk*eak1^wy!&=Uq zgA}qGoy@H|@7mSh?H#Q>fNp?^zfWAn*4Rjpz2fLU%(28Z)|jq}d1=kseoyw6L|9@) z#JXYbuBX?iQ>5Yp$zXPUP)lc@BeO5tBTHQ=rhpM_g=N`u;xo(q zx2^?IC>7HVbia$LJblmCd)dTmic#)sZ(!fv!G>mR>y%0RFu+hdo5jY(-GX^LIlO9{ zVUNJmA{zg<^r7aHpuzbU49pK?yXd0%#fT^kQQq^1wa3uxa`cX~;l#kTN(uZ9-E<8a zG^nd^3^&w9GUe5F8Bu}J2VaMrihq<3V?EFFy-xhGyh*#KUhky6#Qzc7Pz(jV$+efm zH~|TB1B^Nfp!_-o{|lOD-bOfe0%>OljF+ripdX)FE;U!(jk{;Pj>eDc@82uwG~el< zAy*WP7fEX3xQx?y5f@#)$b!xJ#Drc#h2=W1ltTUkl&FLD8N%kc`m^Fo9YvzSsD{-q~!kLD%0(Mr*@3OCOrAWp`K@|Wbi05c*p-%{HW2mhK# z*gETkIve~_2HvnQ&W@KgzTXWmQ`oUVHzn-1;KdA6jndpLNi{`z-IhOM$+a?pJ~JAEyu&?gs{eD1N#+b@_IwJ} zg%1>~H7}(Z+aJ=`&C;rh<}zgN4lw$ADbw9QY}2VXg`+YSUhL<;dapL!z(;B?jzUae zKeF-ZaO;(%js{z$e>8>Qzmj<+2+bEyI;$ifQ#f9S5$KB%x$I2eg=gR9-{$pul- zQ(cxdpkw`&G{cU8RGm^%u`x_Y1XTyu=}CbjsT^W=DcM~2@d&Y1@~m&TIEy6j&age{ z+eB-ng}Rawtzi}cGSZWG;As-e!{B;YWteBcmR(5;@jWZhoG$IIY*NT^1T|$sUX}lA z;T+6$eX>fcdVNnF{`^1ni^Td(U%flpN@H0^_}-Z60~&$B&4+|x-B_MpJky7;52NF> z;+sm#n}fWFK>`myrN~)Na;A-uOGA6FPkUEtzg!km11m!(*Wn`V zkB8W~W#Q{k45O$CBzN+ETZ*Gv9@_FHe`rglEoZwZl{6L~(??ls+lE-HF}xU@NOJJ% z*NRS`zpzXVo_@R+S5=3v zBP=fnob_ta1C@EkV=VPx2bLPgu=bE3>)~O69KIToI@bq;R)Z5Afn)K$b>`~TF{|Pv z_IB~%%W*%>q)JN8(~tOajy@1QKkbygVI`_%H|uE9)x-u(B}`{0@qG)B!{hJsdR_nq zOrQuO?Qhe%oSPHJ<0{x%3Ggxg`93Oqzd+HIJN`cHUepO?r06>jrK{JcBUPD_2H1n#v##Nruo2(N3x0{BDEBgXLQHQ|`h>1qErow)JfyKX z$J_nyM7Q@5Hp&0}ukB$p4trmg+1OvZJ=Wz$T&(DS6io5*Wo(BdnZRp5=R~?3+ogUg zLU;s)El!301Mmjdf;GjQCWWAUi4HB#CzLzSap+}rbu49nwWSSq^Mik)dwQt-9TW?$ zAysD)1QJg&>aGWOh!qs{?Ztu;c{NsiXGImE0`)|ZRl7UmzA)%1&OHAACQs z;@e`|krqjKG@FqW&F zOWjLc_Rj)d4c}cC1D2ebJmh*3v|Fs);Lul`|23al{v%2AaYr;IX@ zAic{9UxTmpAc#wS6rrgR1I6w(Y*sxOUesBu@eK*2b#vy)DxT*ZHd4rfmQ4MkGsV!{ zuzU%ZC40y&xYqu|M{eRqy3Q88jB=M1*I(&-;R6J}xWA32Sx7p)xMc+q}M{Qx`CqYephJ?>w&z0P)R?wG~&*Y%)Vv6-{m!3DP1{` zsO;M};_;xvQO4G{R*#`d5Tk-RahJC;LZeUT!5_iu8F`FFVk3cHEBX{O^WQHqS}#o0 zl<;Fq1ySVRB2GdCY38gT<@Cus%EG?=3L;9~wKk=#9eT@Su}`^A$&c1tw3|*r1?4(U zo)ixo*E$CdKuNLRN%kJoK)nutdXv#?ny^lI(Zd@+uu zC{Q|Dp#y&?cl(lpy`VWu37ZlBY5?zFfdlLJfxEx9hB;SPWfe?zf<5a!L7FZ1cD1$= zo79B-j8TD{GdiKBuud8H?oz`wBa|cG(bb!vGnMaWDtnGJB|u85ZakiI6b)o@I8H&; zvU#TnmV}=oQvSdUnXi;YJra3UHu>uvo&FhoHawa4xm|g$3*;=U11drjR{p`;;Q3ie zkyk5YY);sV(bsEsI^)-dW;!MaQ(5)_lE;q~=B-}Pnvq8ozzVf2f@(uM=!;G6P~s@p zrySf3tJ)ue$?h*d32VDQlnsKp6;Z15ICI?Y$Q3AgU~YatS6yS7y>ZCA$l#22Z(U^d zJ{1_LUAL9i2I_e1Mt8UvIz4=$?aWu8ERq|rZ^p_hKm!-JaqL_3a zej*>47!8)lu9&o~R9iP#kV+fdYi+_ZZ<6@p$w#e(T6@M!e0+E^lO+ran=>ARuH z*{X3&`O)PrOSO*WQc;;4f=*acSR-^OgbCkI;I|Ms)Z{!1vb``vTZg~xy}TFgGM&s2 z>m4$F0@T|KRSy(2A8hVkzxo27>N8E0@Uz$-bCqDq;XV>ZTDV%NvIvceam_w>UWZ!G ziU?$ajETY~yWw5@d#aTe*p*wq{_LdAXta!}rM95|WL0^%;Wfjc@53VB#|ZUeL*VVQ z22)$M`1UHEvC0u4>^J#h+oJ~m0XB{-@8ybSuG`|GC34427EHQ&%j*~7_A2ZK3|3!_T`Pe^4lnv zS)qN9p!?!S^+Y~UP|raO`ou#-X36`;@_s%u?DWW@ut=vhS)pT%rmG_|pt^}t06AZ; z%Srd=Th0zg@2{fKjI5L&S)tW6fr8+9ILIC>d1@LI>bquVDperg#xeX!C#rqt-Tt8o z);8EKzs2)#2SeiPzXl#>TWVSR`S3478Dhv7GuH>KEKb2D zbvitMvF{RQ31d7}XPg)agPf$o@TY?Y^W4PxC9D1K^JDL7Bzsrs6|Jn&bB@3nT2m|A zJep{OR~_q}p|^}pp%xCs(4;+U=!sP0aU3s==S->U9v)-#dE|rB1wZN z{&z7T`x;RHlrV01CkUZNanhZj`MJtZU>EMom_}TYIBNgUReL5q)qK6$Ddw5pr!1j% zJn^awWlSHGC|eyA2p%qjEy8C(;<^Td-9Ni(x;vk{V~=Cc2pQhDtNcw|(X~$IyppRK zu{4by*^^$p6|1MqQ~m8<-O!kg;YycCHt8(M%)a}?kIl5HBo5UUq2HX@2tmx_g>1q# zg#wQPZ8ewBtSjUx8{w5k-Q8XlD}QPTt5&OA?kJV9I!z~nEhx3lB|@PM6iPk4ZHwU5 z+r0gYR%KFEQuVQtaACksbn`Y>`=?p|?o>hCkav5ZnoqsmVJfe za_W#8_i9SYARyHu($5UiA8-#R;{zXvU&GuDcmjK;crTVM%r~oZ+BVI1tL+`>jGf|y zJ8>s}!4mBs zo#Bw06I#MMe|%N=~&5O; z3TaF+y?*td)qc@`fRs+dB2zO}`2}Cqe7dB-l_1@}hIgknC{YJjsM2}D-hNQ`4YDomJuz1|aW~b4@J4=l{vM#1mN-O@)c-gce$LS-3yeIJWWN12M4?3Y)d1-iS@8}5&q|a>bT&9?e zc%vGq($=dt?=$Z;qETjcUZLf|eL;fI}*e07DRFtN8@xTHIK|cJBYaOFyfYvnn>~{SE&0ZMPxq=h{LPk zi%`T2O{^DuJFPjj%c}E_vEIUHcklB#_dNURj}AN@0u1DqKdBwy6*4VkEbR|ziR*@} z9878vv_DUZL%m+@UxNa-CsWS;0~9?gRC|J6ST6$)*7(iPfH%~+-7M67ObrGqDSH1J z3!~6TaJy`gFlq|-S$5uL;fY*piMZe9JZ#}97hmFhr+QlV)+n*6G5S1C6||s-`TRw1 z>o_LUmhO+ZW)w?qc_dOw-h!cfu)cStvQC@X1nrPjO(33tW`ZA0$z4+vOEx;R-gPRx z&QUh5mNB53Q1@Zw@s;c-!U$pA_unR8#Tj%boQc}Roe77|j{>ZKA*!mIM{BO%Z&c5(oLc~~|q2RKD3`Z)qVqF;R}^aQlqqQPX0 zi@~$t^LsKhO!KW{U1J(6F}*w&u1{$xWvWaE37Fs2(8vauB7BbTb7n)YTL?Bs zfu7Z>05o_0f`skWM(a1AZo(1ecT0AV>*WbMp3U@yuqxS(eTkfyn!PAnd9p&_W zPQLpS8%tC5x&Ke@ga)a?jE2AK?oN-tbvqJ%g)mEF4(vW`-%fI~YK%p@^#;ISjY>6F zKGkWAS8a#cA=gKww3`>g9lTh2S0pX{x1EBU^~lnvo909Raq9w{9yMWrP_*h~C7Ez+`?b}~fqQRkUHOf1g#7vyAqkMILoIO=wJbhI!Vgz z7P0u}&(lV|gnlen`u~ei`fu%p5V14z4TmuYU(B$)`(6_^88rog*eB;dz4Yh*8{I&q zDUs{--2_Z;Oy}dS4slJ>3x!ujbi&rh3Ao;s-46C+F*&4Y>K=A)6Nc0yF6uDir3=P} zP3DsoTB~QI55+)i3~XcWRT{aiN|-elTLj{F2q$RAMH=1&*ttTg$AF-5Pk zUsrLBcza@(k*6#c739X$YpA=TKxLH4xzSbxXHNsU&lFrDe z7ouX)?(Eq0lox+@47t^V?AAb03tafgMJ8?T5;_girExN|^Tx=BK7gEt-<`Ot*t}Cp zmufkz!mWV~;{=JY`DnLHGQBIh=x4ogPH&@I%af=DQZ_uh{mm;j&}_Xktbu)@cP(=K z_|73g3B}4+6LV~wfq0UnVfwt=YY-o+h=glNM`$lU>ghXjmsTD|Y)Wjom@?J+_P|D+ zwm>QUA_glj?$4&s)rUzGS&SOOm@b{M-jzEEGD{OBUt=m?h7ADL0oI-n$*4pr{P8*S z6s%C}-oQ%dUI7bHt7inH#M|5(Eg1AUtN1)ND*XotI6h{KII@rnb$}JWdX5{e-H5e5 zqyGocXkA_+b_pH^#pdQ|pVxYwQ`5*0=jHj{=98%Gs1ZY;WG@Sp8HWB3TejeAm}(uc zDBmAE(Ez*`_v5~Zp=(RcQjL@~cd-C!{fHqTlya0(&G&G4Ik{P=5uU{f2J4hP@4AZ}jJTf>MMZXD;i!@+S zMoGq3ha!7H+M`+ER0$Wt&8VN5ne$bzNgk} z+{U41wcWDH3oSRt1R#i8Q_6QW> z#=ZMwFtr*g_@=4u0!7iQET$I@`Ly&b2=Rtc9P6a3Km{79R~d~-1{LOM6zx)(IKEc} z5(rB=W@t;1t+N(c67dHYA@uikPFqFofuKMRzRkOTB08y!ae5mO7GQY`?d(c_!t-qF zVw?^JI=Z~Cn~quUOgE9`N}iWQegfE8&8hAl_Sri4pz78J60ZGmdSA9+0dAFRH{hE~)w%MA*WHfJu>&B*M#e{tc zZZisoyp7e8G~4=;5t@bamNmB`cFmbbZK+T1PX!X{n)4RkrXK%;;y&oBeF>IJ|8r8B zqnbv`OyQo2sICT2KQ%~F^Zy6oZieP`Q-q|2>|jhvG6PE+WvAW&HQ7wYus`_DS6 zXCo}Qf=uNG_B#Di7G6?>lQL9=BP2@S{*kOnG6Wxj6Ad+?AF~EesoHpJ&qZ({cY-3J zNr+SnVd8XxDk6^|{J%;ow4*klZ;4$F2ow9Yb5<2M*=zAiSur%h+#Pa9RAiO^>h(sw zNL8@a6BE>{=|DPH@A^`#oe<6y3NSo;oJpRVaHD-5q$K*@^j$0mT#k5Bfq<|P;}tk! z+QoXQu@b!Lg*iQLS*o;C6~~2tkRVuXPDNxieA_+oDVWyN+)v`t{cpL1MfJU;1Ygsf zCU0Pvayw+UqxKn*M{20c;S&&&&Bpe&;3tf=ToG|hcU5?L%f~V-H)$ctaC+X z(X(rL!9A|Q&-A1x>qOdptt7Ij+;8NQN|UCTFiA6sv2+4U4#*4@GbUm2weltMFlq1F zx4nf%h0kb|R;z8r@)Q`i)nGJ#q<2R>z)j zrv+1aw^%QGebz}3YC3jInxpPg+nWznPB|Z_C>V2u#geh3(_K(44+r#3d9WRzzc<{c znx?lZLon@UCMVHOROMYlS#Xy!OT>9*29>OT1kHCtuSe6yrWTcHc#&19Z3zEfT8wkc zhPXUezj_pD*1r0}B<|5t!C7`s2gWMGD{L1%OyAnFu{qP@8!{WkxKT!R=E1dZ){e$d=gZj#qtH^-O2z zm*wF8hRcs1O=J}Qvge?u*2EDRt;GrGm++A*)$TK8I8Kd=a#l3Hb^m>oD2rJ)et5a= zwrQG?YNoC;RpIeAe8_hKCk3Y_5<`f<#LW}!WSVcD#Yqs(fj;i;Hbj_pKFXr_(|RH~ zWoAZ%Ems)%2()%QKGTn?0w3VvPGZ+o%TnM+=MYMVumSc*c;{{GD1RLmt&IgDr2Nz3 zhKdoF*&Q=Af`(K)sXO)T3Ra*cRZ6bSc+*b>@l$TVJfa|?x9&2|`vaD^8b1CqwAhM2 zzQ1hud6azU3Bm>q-pgTz<5Qw6C?o__XO0Sr^LuqK6gx3W~VqJnRyjQG;x*?}@Bg zJ-z>|SBDi3uw)yHBPx-5f^~R(m}lh$SJqu4+ld1x;b-Z=g|tbybm@c&pf%zA?(sx1 zxBZ_#T)GaHt>3%qCbTt1aiL3HPgJ|_z2LrcKlQ=co`x|-JniQE7vD#=n$LQK7w>O8 z$n)R2vSu6E+T01HlH%$NNQ~cuc=A(;>DS9QXh$6y* zhtOT)S#{gpmE%-|IrRxQ1ijN^EhUug!S1>3#na+%6rqox>r00L`!)JiKGlAiUB!kq zys}h6CB9PBcy{u@U`94>yp1lMNrhs43DSykN?4)*22Yu9a%d(03SWx0 z50O*UOIJ}w8t}bXW>f+Ge0!Of-)dyc&r|jlCVi@x3{HxPj)x4J)M9rt)Tyma>*Y+1 z+A%=i^;2o^GnGa#pK8t_Bv|i;8CNV)Qf3AWx(9mmOtV5%lrrX2xp2q6F)^0#H*%A8 z;P2##eUDE ztz4OKr0}jVL_Gfn6`zI_t~j?V6^cU4bK}|VjmnQZLJ^aI-q=W!im(k`rE@K8aH=fH2lQ%{vow0&{}HA?yIY$$+G-jB>^Ks zp1Nd@Gf7RBB~6VU%!DAZd`oTV>y`*JvzXD5Vy}Q=)ma^nfA8@sm8#nQN5VxqNj@Q} zF1Xa4uiu|#ntv{D61dTuwyO+O=DYED|1CZ3L6Z*QVvLbeI8kZb#SZ(F{+3xsSP9%9 zFU?p|9i8l=pRi>#TRG1Ujt=qu0;$D56J^)S`%8zbZN7b*!qpKRLdc(JYC8DC#KKt+ zsz^$JY#jT^NGtA*2}M-*8&Z2Ti9yKf>h5i38!OP{NHrhUc6Q=uBd*2E!uj%6UmG$p z@?}H4POX$_#&N^Fd%p_CDnqZyxyz46a3Pr_(2y*@bh2Wv>dfaHpNob@pkg*jX7DXk zNZPO)u^YkCl(LN59uz#6j7t+GPY-gUEc{Ym z@{dt$g)(TJ=$cG8Hx`g0P?maxI-o{0#4c}#3;5_;O}g?XYQb0`SA-g;_3A=E@*|Dk z8>fGpHiC}%BVj`D)lpCW62$4wVqw4H8oA_-O0g!M4In)naWc|TUff;^-WhNH^sgGDk|dKTN6qG zup&uQJs*VqP8RnOluwTsFD(6Bw| zRstM@pVbEtz@vgl_yV;4RbMhqZ1d#WNt3;OpwQJFywANo<_07PvcGH@|0s+DeKP!l zO-0`Oso%zlVPGziRLwfRco@d%Ew&XAd!sLIfSRt*r$51mIbL!iSmn&TkZfj4OZmWmfaH11O0SaG7!0lbQ!NjcGGt<1pr%vAH=qOz@jcWbsOjyTEdR@` z!y5;=dPA}H{sUYHw=(A9;KG)g<)fKW5GpwN zq!@IXdkxR63;kjalbn+HvI3v$G58r=9QG+Ixl);g#y_D5XDSI9f}9c5aqN=tGod^6 zdF!uThB5$8Y}~MI>s2$5*K}=pqR0vo4GKvH9r(8+e8pf2kr^$83igRiC3fZ#JB15n z-Oqf0Qj6qpEM=t7Mo#Y$gqJXkKDfL(kP>bRVwGeJJf1b&%DgXFfYs}%@-4Ho+u20_ z;HM~`D-o60=2><+k+V#Am2?){1kt>0KtIDBK={rI5a|G`l3f1**!gBX?=09kbJMjX zY?kR?a2P>S$S!Kor`w_VFoT|D0@|nWt6`_a z_mbkF<}k{63uy8d{eCV2)$o!DWoj?96WIEheW?3}@Gg6~>Huft?^qE{pd0AbiaRx- z=>NN?Q>fj&xt+ ze@^3nmFPxXqR_?QR>bK!-l7|VmFijL*jc2vbc>nZ+b-^0CLJRx%8~*2!%*k#yg3SR zFMjAE9g?DW9H-3u6UeH$&aZ9?ZDIGm<1;C0#VVvIQcAKhU9yR@PvC3*>!pN_N;7^$ z&TE!sUViHx;74)rOtX(*=qE!JA^Rrqx+VTu0dbXOlP>1ES+G^Xs7~EM7n;X{;V=7(XDCDcE9OX$ATU^oV#3$F!!CE0J z$aYB9VqS8`jn^(j(Zn)7Cyhi<#IwcPE4TJPpXXIY0JohU{Nxc76?WhEw&;RxJSZth zIwZ1Kx#?Sso{S$`{&8oA{B)lQV|bOj7?6UJ!7LP4`KGTKHBytx9sNU?lJs?lIm!#f zOcwG>*yZ#fIIB&bZ82;M&FLdigCUe9?t1P zgieC?H*S;4)Cg1w$Kgj+O-<+0|AepaRlCfh4g~6KbY&N?u}4I9JRA5=&N%K-_r}B6 zgOg!`z;oS;S9d65E>LW^Zqj2bGPBQMp|W6}Dm8^IZcJX%!JA;;vcuuTMp%@2EcZXa ziD34f8N==TvtkBk6Tdjcx=AP3?oLUZxq20M3Qq|-dLH^WVb^@u56NhqZ;bCz=fa@L z<_3`Lg0>jnra5(g!v$adrE7Lz-rjqmoh`W;_Fc8Qk1Rg%%E5UR_pzOJVmsf`E6mILR<=-)?c zL3YVt_nBh;;u+EDYfa8l5aSnDtLb%KDLvg=<~+h#>nduO?UyPMQmQk4rNMk3QR8O8uIJ==d3A+kH; z@@?*We{K<&G&UHwST-2rc6xpm=xm%}VeHI%CemKtki9H(uc@W_1){DD(vjv(co1Z;qCfaOjv_deweMhO$Jy z=m~dDljTro^nRN0#B2)bEAj@rQwhYv&@ z&?r>03J7yNMPG1#WUBsP<#k< z+C($A5{k0dZEq)*+z>;llC`u+8CNfb+=h*$Gl!yzbgPzRmgr?0?!nE_e|(R?BU)sM z_$9&;`HN3(!FKI}r;OqX)PePZuFFbA_eYjq&E14iilxX-zEAZ7riVEG|BCCc9kRYi z{bZfEeR`5WcpMANo8dF<>td6qoYb(6{fQ1wre*j@!v*SU=hxoaT+7Y_!gxgI)FuV# zS7m)amKfK>w3Ex+7aFA2n;RR+qO@0!P_sZ$6L>%T6h8iQ&8Byt^P{(s@Xth^5oHX|1*Z&pWtxnK3UZ^;1iuo8FuqMdr9lk{ks|Qqpcnc3kv>8sC-J( z_c`@1X#mo9oyYIec(o-!7Ddmvj(t3+$-BMsZ9=y_Ynh}nBO4SmvPyyf04`P;kR>o# zn;D}qe`HP8BM`OBw`dnMa6;bBp5`;F30qHiu)sRt4-e1Xhp#FErDwa!yACZuegUu79@nHZ1;uwscbZFoN#T-&4fT)LiJ3kR zA~qVM>6|0h&LQWH2}WmfG>9TPD=%2ynZo zA|3*=jzzm?tLYaT?LcDL?oruEsK0cFmW0t3uXse!s~8obVfIbvf2S#Q!VYGV_4)MG z(8*_;(C~v)>6xTCGGUdSws!XmzXXLaq47h9wM7{2ZCv98Htl-tU)WJ&$o%kf3}W>r zu|x!H2s3Y2cMd*SWmFy7x7iLX+XQe3zEg@dplxy+)Q|}n?d~{E{giGLeAu|l`RrF2 z401vf#51hKTKzMDDJB}hn^U@Hknw(m8@1;4uBbY=gB$l`#nw5zFj8YXX_rUoGu>W+ zllY)T6w5jC)X;0W11e7vqHt;&(4$;5cN`SKFl=(9ScwfwPBc3$ zLN~UmFdRRmRklnuH@_vyzB0%pd)Rk6Fudr5Ka-dZiu$5_k=Ep#o}k2KNrX}&Ok&A9 zn-uc@`2QbmbNvM$F?135-_YgC;_CI=3M=G}jCFdlNW%TNQOZKKneZu2ZpL}};0@=+ zug^>3=4EJt)B*oan_nP$zrRV`orF?9)PJl0jQ_>d`tZAjL#QF5GyWT<4-1h@@!1t{ zyboNu;Ppul^88aM2+!lg6PTpP6{jg0Fg`BmwfSSOKMobIKesr=teUQ8mcLEcRspChokJ(zy`@8k zPkwN~+CSaKz)Sit12Cu44SFiR{*Crk|Fc&UM^yC}9%)07F-#i`HH9JHU$umXdI~IU z{Ad297P??om z2TN9M>15R4=?|5T&+hc>pXc)snXgtP%uJA4 zkw!y4&gol2NM_d~v$LU6Y#gZh>Xoes@9R&WeKyPl^*-;{(6sdqcBay39pwE&s(qE( z_McIEw$5;I96*8k7yJj{x<`2Sxt)rDBA4fh} zA*XV%7$_@a3MUD>pE-fa)6aTqk3EsIqdGf#avU62;mx)ZKjh7-7$aDJ zm`rw%*k^p-FH7)y_J-_3+2PHwRPYNq!+gP3R!Nq&x!RRYg0c*4oXFj~AK0l9BuZl1 zMDqcV;B>@br4*FBOrg1^L(V$oZ}NM;ki+NeWfQ*~shP~m%*~pIAS%a|tea4#Q^$$j z`lq);PhG-Qmb5p)i=cnJ6M}mN@S89;n5m|81zk3&KDgGO@3vZ&d@@GSrT`=8`|C)z z`dRg1%@ioX8#PVsL@0PO>?ADz`UIX1AB&hJ<%sqMS#UZ;VfdwM#9y{LiDdN2Et}z3 z6xc=p-d7S}<#-Nxc>1;>3|=v)dx(mNcWN&barXv5?X&Hdd_*k-15LKX&9}CGt=X;_ z4b_n8baiDv(CbLYh7zftVR9EBC9Yk?a!<}%J+biE$Yo{HDb%?;b*tv<=EclIr?N708vJv_qhkS4C6!_a~sm(-+P558^ma*_#wv z@Nb=I3_WY~@2<~GiYY1cJ3s?65h7Pc?<6uHFdhM)yq@T=CEH@#yLpSdb1lY^;ZU2oLQx){2tu03v36gM!17QY|E)g z*y$2y{mYrjba~sn>#=$*$f{3IGszxxRvzOr{{!f)gbE!y6brZ{u`cCb@8w#*l?mY9 z?iQ-6E8NT656^pXk1JWNIh5MzmpG0qaU=6<96~6?btsiyWob5H{(6JE72PW|$;n@+ zWquW21m>-C+xdI_^$MzluGOuatXdBo6-p#j*-niU@CoRcPru7`C5^8oR=}nSY;|K* zfk*O`u(wS|d%cW6;vqrUtP07V#J%foL@m=}mCi4?Pb_zgwW0+ZR=;T2ddw6`PDCY! z5Rzba`-3JHs%kmm0P1l@8`PY>l!qbUsB~85TU{rA;#3!;0E=R=@{jp0W9h(!9R>7F z3$A}B>Y7o)*ak6$HT(88Q(jj6BdO8C@z8R^jcGj0{er!=vs*gdQl$>rG8PThfX*z;WVq?s|+f};-ujLXIm)pI%vR;B@ zFEpJhuOIx(sjgK*#JN-LaWYKk9ex_3qWSjky5Fw$tAUUNu6$2kc--70Cp(07aN`0?(=S zc0{nSuw!iZ(E!bFqbDp1EV6)LXTJi4>d)Vu-91)hJt7)-2`^SC-xOXpUuJ0Vog7a+ zu_yp0&#&q*l>zQ1I>n7$(R3p309pJs2u@5Nbu6a<9P&H|bOya-Yj~df`Ew(`N1^8Z zuET2Z6jNKZZOE{uGmlVSN%FmVn0$5`(0*<)*>V!t@*Vk%SC6`e)B9OzNZT^fFyqH< zSIP8WD_$%CHTb)DdUzG$G3~oLDEO|(Ck;=8{+9hq8ItR37+0xk2HQGXLO3oFXrG`w%r*;^TZbQoHzH~DJV zh$7VsXm@Kn6a6PtN!zOxYG28E{QOfj&ARn+pBd-X2(qykTQ$}nl&pRExX$8*-|a}7 zrGHdX#5^$MxBst?Ne$jzY93gw)3M<5O`_FfN0zdcG;wpjCAsf9E?skpa@t~=m6P41 zF}-wbcms)lY~QG0xgmMw4ZL3d4Fk=hSX0?u(^O`6bjBZf9f7)VN2oB>8~H4HFz0lw zPerEd`f^O1n2mSrILxzMFS-0}2?jOe>H4W8s3O$FyXnj`h}0)hwO+f&w3ie$uJ_p` zsOd^j^9Se)G1QA2bOyW66b2Ay)mG!SW6y{DjJk1&+Y)G3GEOE)RVG_XGyy2xc%8MW zLlK^d(J|uo$K)Pnk(qvDyRQr=_}aU=(=br6o*1_Dems> z?gV!!R@^nX6ewQYt+=~uixb?7wm?Ghl0a!7<-Pgty+0t&WX{Z-v-jFd-lin6A`^4W ztNjiH`aW}G^St)vBK=ExA)d#S8zk=fsX)z*imVGfBqO(AW4HQ%i_d1*hQuaY4%xlr zFMrLBW56FTxKd+KSM62fZje#n(`nT6hdOJBIAoPh+Wg(p`cUf(G{(DFH#;42+AFGy zGyr0eFJ+cqiP2p5O`4iQ)f4p5Z2S{h0c?V`LB}-X7BG(H@(eTG1Dt(p_c-jC7~(eB zCpxOAZhIX*q3Ns^qQlYQ{#C#fXwmYV1rl})z%+&hLu|7j`n@X$vCqFNT@F&d&-PYe z{Nxwp@GRrn>pVk_-AB%=&o!F54P!He9f9*RrI#Uc(l%!B>+n7BKe>4h2n`WZ5keJN z=>5(`TTFm+(@U0=i%Z{;K5J9rgMx3>UxX!|$RyXZZHZ7g{+M;V#`W&N$9I!lvn2QX z!AvAQ7yMF$RXzmX*HcDX{+R2`-UCwG9>#uJO3z2_M?sub!oJ$>j0{dR)Ax^U=^Q;R zp5Es~_Ig<7ngN$c-W}7o-kqL4VIyTu`OAMk6c)REn|5}0jIcX9+nE_UJcdvOs@NDb zRdv=1x_l4;>RUVeiU1W{C@FQ5@IjU`T zYDN(^V9>YWb#*(Yy>kE{t3Ispa>(2=yl61RdpHH6Dl{Ap9donB8xYQgzUH5Z^2_@@ z&G@$P^yHm`&s%r-ikI2(_msY53QiDP0eB>^?f$@9zi((DL7ZhE{d`NKQpw2R$4y*g zbkLmgZ>R&q)FKa6S@S2zw$VspPL}Qu-JjN{(xrdoT#JL)T9qfs6jh{Xyv;;!e%pSOJb8fL_Ks(q&3*iIP1(|KEEkXh%SZ?K)>2p+0Lj^E^Na{$ASa#* zn1^AJrz*_7F2n8o`@Z1hsn6^w2xs>ZVp7S7ro(UcINR; zN2)TA^Dxpo(*DvSvJ!j{wHVs+Cp#D``Omz0ZdHG3QHCBmdj97N9rup;ew5Q)mi;eB z#fM?(YukXh1&io}uN7Gf{(5%q0bG=-oa#TSW3G?=77CpN)Pf3*QFgQg@Y{5{Gdgq^_hzx{VJUKy`W!#;(je=pMzg zzlTKWZx9XlMJ4yNM0BxDeSamaoY*P4dc|8MD$^~>p7E{T7s|o+vTH5EC z!7^Ior;API@XUU&cX1uFl(ZRBK za}wT5%)djW{Dox^-3~r=HbSl34$W4Wi({r`e~ir z*K)E*XhE*f0kJx;>0m1~VPB*-l(0qtw}>-NvQt5dIQ&pY+1OGGyr?=Ih{PdHA;@-C8#lL5xdzoJ) z!lS4*gSpe(YR18vxC%s>2BO#?XTe4t`_MyS=PODkudeTC7`3DpX>Vf-Xt8$dDBc56 zbnn%=s~2CAb)XV)1iecnRx${qDL~5tF=ZFO3z?MQzxG~!S}yP`*BK>q#m#BkY(Dvv z{)R@LK3o0=kz`SblWzugFR0fx7>?ZNQUW1+V~Z*Hk(XL9)k<&t8t`<{w*%H>60GD| zOsa7D7@Z8IQCsd>Rgm5!%Fkazi&3!8V})hG>%7uUX8_>~i?VFL3V^pipE$U(9*><% zX;hYbXeU)5Y489aT>iiJqmAJ_=tU1&Ui`piO*@BUvB#Zk!pxSB&P+T>?r0v@%za!wp0 z9jth>r<+VYsvnD5I5Vjirz;}>s?P&7_`auDS}r?N?2fFat@03&un#9~fHY=u>5OK`b#jAZRVJtVz2V)IQI;Iw(XC?LN#wc1I8qwU-R)RI z@m4P)okRQTrfN7{hRKp`l`Vc`;$=}%jVZ+Re^59HOxw%z1~0`mk}JH&4D3c=#dp~y4Ot6G++PRHzI*H6hVzG^$tx5# zV@(gogy7DB`ex#oeXR1fgX9qa6aY0`perkLDxS45?eAUhVOjUOJ%0M@`;hI0NgZO^ zG=G{L#ok1dAgue92pKi|q_$KJi>3{Ls^vUnh#pZe9&b#We}JSNH}q3b@ypvMWf+3=AXHyfu7kKqn*3b0KiLN%bb zr}q=BpBBTH7Tv?s(&+t@sr^x>2b`!Sg2;gU{@%g$Zjd>B+O9~kQ6EphYODp9PyE0v z%7Kdz{kfli9fi9&wPA%RQA)r&$4RlUd3nAX9|92(Vd3lWa;a^C_O@VbvaO#B{ z`NcyUzl)n>Q&_JE^+kJTAS^ znsGhT&_6PAT_iQ+eY6dnoMb)pe`wi`NOifJ*Te}sKkK+*U)p^9p`iQf-%<6^K~Zeo zSdXAWvLuIo?01_EryT{+P0UV-e`+|DyhK_i9Q5>Y{ir>%D8Wah`mxYMKYiQBWWe|l zZi{4WoiD&QtvcEC*bKEXSZaHsR=HB4VDgk$f8YqUHQndAvB>+Lu8gxeV=#|SFbJi@ zxWNHE#zZQ_TQBsu9{AqW2CpJ+K<07}M?s<32-68Gs;HX@sT`7g951$Nny~A?dl5I{ z#5k5Eat9QO*SNeg;$R9q9AOW$Zz*H*vPz=%{JB-eL~0ck>e@~p*ZV+8)S%k+Doo;? zL1y$sNBxZ~BDGNElg0PK56U^Y4yqrd)~CxEaz*cvAA)_t;Roj?cDzy@m0+|9W<4Uu zzu%QG@7*m7y+1$s^}5Ch`bp`V^jPRorH`E*k(zn3lz)t&UO!WzH>nPJa~iSJ^f2=h zfyQJN8Q@N=?auZW_~aosYE{LyAuH!E4&^%!=2q%3wQv2urfX6Et^8jwUCa=!b*5LU z8&^+Iwc-W_0!8g1FOqpI8S0%uQr*6K1P^MFrGh^f8?Dx848}}-BnjQE|6E08=P|^J zz0$ijgwE!gY4*42?mfON;8cWeyi4Np()6>q;Yu|YGn;tBIMTGoV+1+UEz+F9L2)&) z4?3z~HjT1NA+m|7+24VCF$6ap&i2uxkv6|gC`=r1m=mT}j&|xRk zAwA&dJ**e-dn!v5W`^8jXTqe!h3n|6uiN+WSMKN9=&0E2K&mW-bHD_1LeJc* ze$QwV{q{YiEd6^H9`g+D(|eP+(3JorL)#sf?9gFyRz%~y}2Wi z`Wgn0Tl`Z|yccN2@$BJdJ0ryN@E?8oi{BVDVfiw7x2!kTT}vxMaO%Flu4nZ_0)MTR zqZ}@o)MqzoNyx%k47KEbkw>Yl)F>5<{EW9aumV^&8?;Te)WlBwZjl{uJ>a|`Bo(4W^iRWH_FlC@0qb!vaUq z8!NPXwYfuML=4Pm+s3vRQJMS)URj1qaTUm;-|E<(q?y3E&Ka)kS7Q|P8o~|r!R4uC zhK75?%fVXSpfr;xRySF_LFi~7ipFXCXd#Qs&s;7_3_&%r{aEW_H{y=3Q!Zb=BFazs z1R~wsI^b%vTVu9cR2*#SD3>%u{J7|+^57Nr7F{J?yHDoY4wEi2GtfQg%>0YK+9t9= z5?Nj)$AUKJ^{!Gk#S3&8&ZQBS$*1F*IPBxYXhRFtO#~wEe4FVnv=q{}fkma@9!F%#BORF&q@0 zpeq|@tPORSgJVs61q)QXd8kRA-!GXz6(c-)>^Xiayy%ifBqFoKWZ>AX=Xq4qEp0YD z_aD_kQhQ%t%aMQkD5!oTR>{1*$1#_qz(i6r_c#W|JVm=#?r(&N6D*ff= zICzset&&=CnXNiA!CPmUXj5b_-ErbW19kX^-p>n%AI0>fQvv9Dmxe!ZQN-Zj7JxFM z7-~{^mLcu(qOo?v$IZ(J5q%^NB7*_~yQ>+7Y6)*;dUJw0)ssE@2O zBi0|>=j>La&KP^LgFPLdFhcTGJ_}l?PU%#SW>9e!C8*I|I+eYyS-)}13rWB25gbJR z$Z&9-d%CCLCDIM-S=T)zNF!4FNyqVvlq;SHOA+&z8uv-3I30%d8+WRo^I7c3cAHjs zOww)es5F3J*_Qv}#XrR6#bmV`+rf^rjWjs@K*N|tu}m62Y?~=xgB_PKahMHerP=`h zTJaJNES{sXDF#cKxA4$u!U+B*ix%2$OXe6W+7_dI8%|MGW1NJE%+Lar-Y>Hj0Q?q& zkwJhhQR*GA!(7iAm#p#yUx}@o+UTcx=Tpmz`D#ucv(AQke5F0Msl(2%ph$oS9n#0- z&@=^V{h`N}4PQY-Doy%MqX)OzMxbY->NsRAy4u$H^QpT+uC)g>hCuMp1_CKfmoPlL z6#|O#&4UVsFRgia4CcdTJ;yg%TkM|+7kxLrWF*8@P}sP4_LKZuM1IKfpKqn2b3fZn=eYd2mjV~Ga+K~GaHpcr#T5~=8Jk`tR! z{%rdctZ#Lb_i1v_SZZrIrS{zJ@0J&O*4zmw`FIPQk({(v3ZxhVF_h;1&QxR>D^b#n z$Y*4an2Qp39W`4Uo@)eDeWwm83B`5+S2t(+SeK4h5z49w`2rI5-|Zmu;NE(OS=fil zsHkSqjtG}P+__t-!`%zV1koZz@LMI1MvJ&Q&C?}w;-G>bsX?_&K%jpZbAD*)XnvW&@8p|o_sYi4o)Sa5Zq4 zb2RoG(zGGRQvDM$`u;zZnfNoE`Upv|gjK01_}ryv>IJS7AYuvHrny<2I-K zpYLUhoY}6GF|o4OgI>2P1EpgDkYB+|92c?H5Nt|BM{^~Kl82hk6T~LJd~sqcL+d9W z*KFquW9^2S3d%)DQTYUSA{&uif!ewcm*ILF2>jx}{XR+Og<(YPC&Je_U}r@1nRH6e zx19*>D3dOoGrIrpe<)iGbw|lc=NYrxNaGTV7eRHCjSS9^Q1@PYCkW&{_|AE8cJ(iR z+9=_vhwBE~Vd?q0z|H>bh&xnHM@MauD_9a+wgx*-SO#qWmR+iJmKOej;^xHNNx$M> z2vjVW9MlVvt$4M;@~RfiC$SUl`shf=a|0S0K;Ahu>}Uwi!m}J5h`kZyHP(7FrYqVF zuUj_B+_NG<&1~O!E*-<;0xXU#Q?myk2Zj6eB$l8MFWdBo&`{^wW9$X)FDaet^T&54 z4VNoac+p;hc5?<{&1ya+KD+qL-MEhRb0$gSs+tfLJJSGKJ2j!y zDLmQ!xi<a+L7w&V?V_(a{e*-1H2Q2a!OM^qpjK~1F=3E$L#-&(Sb5|g^{1;<$DIUSh;U^ zv*~{7c73r*C`s&W1C%ipn;7=U8IAFUckg~E$DgjiDzaO=+^P!=k6vj1vA#`To}8gk zDE~O2nOt-=tje*>sDM&d#hAD#S76~N+8MgQvG^@kiniiM=130C0UQ8tsNqe7l$tEz zV1WY$RDNN$O3;1jnb%zklJLa^f(M*(vG@I`>HM{G4B5&egXVb*RW1Bn$*vV>qH{Iq zbT{XE$or8^FaJyAIbC*{>UMXFmzMeIHe$vO{rcnA)XsCiX@}uV#bkCBIk%y*@5Qxq z6lweTx=a$DtEG|ZF6H@S`Gck<59J_$6wqsCna#Xx0#tNVKxJX^tHzDBSCf{QUs}1l z^`KLUSzZ{}KIN>2{IIz1I%wa%K?fwj+@gSkvBNU=IRXe~#YPTCXYo^*M%Vo= z$IJIvN7>Gjc^=ddCkYv-taXs@+a<~8&R(v^XmW?@6bZxGzy9$p3?@q8v2cPQ$h(wz01Knq#GtO-;MFjZ|08vF2`KQ`~ z70wA&%o8(;1iKBBV#u07M_1$e>~t_!EfYKr93_4(2TKi|j)6~k)~DHO4X(BcALzck z;4aESzL#Km-gi;{)%@m4e|LGUJyYi=v)B(N&R>u8CV@`Z1XjE#!?_kLtOVvn^WkMs zH1@xi8@lgw#84h<yG zxNH*=A^w)BP+HHGDHU*Vd0{>sEJM}=@ny5^UR)$_D~h*AMiR0GOx5POX_bH`D}$#B ztxU$cdS^s|g1?m`B~X5b&@!JYoZ3(ZA{XfGX$Bvh7|99EkIEg(&vYS|by{Os7r|X# zdn9N4G(QbcX&jy-C9Q0zaV>x@PI5MkidQqUFzNthHHJ{dc5pmgI3p4D5?G9pR9h*q zw#zBb2o)q_jbW6tqPlO2?wbNrMrf+BM{(NtzEK7pUXn59yQ=D;hZ_~SR>G#Ar6G-3 zvQz}#$jV$GA(#C3TGIad-uaX%*)b+xrw(8?c*?>QkLyQh`dB1q@+U81FF9$w^k^PT z2Bn|dq$;Qi=X$D~1Lld}g&(O?Ig_YrN>lZB-JsPbO8}gQw6Q`pgX({kJ2!&NYswmW zy~DlzL@d=EORI6VI&p7CW&d>$p=+y~2R5FMH?JH_oX@{9=267jO(lrgxlyIIA!^{c z7mXSn2uO36UlZZdKZ*N<{+2}(Uw7*lchFi@XGQ(%tum>YzENq7pE@lM2dujct}=sw zkmhSHneAE}Lh)!!#UaFHS_=!=;rpKcvj*2|W^7z4>H9AkV272sm5h_<+!~{;D{oq^ zQYvrVpX#6KkK!tiGWdEwK8HCfx3IF956>~}iyStIbP~miCh60EtkYMPCm{-Mkp=SW zt0&d<1qoSn&b>}n>`|Q^lk9W$3n^|%Z*|3ksU)=cK1QWHUQ+p3zVzfLC1-pytx zl8H;cahB@9Vk@$&f*U9zAVC?U>t;4uMR zTZi^pts%S9F-gS3>7phd576&SV?7@<7}Vf5=fDE$_Sa@{edRD0IVTk)1^#=d#{8*O zM<{1XIq+h!`xZWR#2IM`EMAbzKT~aia4pmCxk=h&R8F`-r=+tl1+W>iOi$5ya_e2Y z`p=(P_1DlA+RGXZND2AczJgyAk$3AO2knyv!vo<-XFLu{>tnpvUOk2l-#6Pdl`q;s zL=T43D$d7l?h2aVNOa9FVQB+Ii@%PWMv+oE2wQ&mSv^or4|aq!agpK~zCP_gArdVQ zYtZp*=zx$^c4ueua#{HO9da7*n7nnk+dq+?{xu%=N0v59;35iJNAn+HwCg1;Jo<`V zCIgDJtKWt^0SDEGC!#(`w}Hl&n?a!1%Gx&2HioI9Fi9>9@+} z_t3;lIW|PxnG`_i<-N^|9XuNVr7do>a49l^erK{S2GzWyy2gBNmZ(BE-iuV?DJ!s< zxr4fw0aX+6vpvE<{}Y}2Y#>gMeysDig1|u@J|n1Xrf3tTK-WvA`jpY6oE^?*tE@>f z6tsc2i0=N6VN;!XwTz4oO_Op=POzB*#4~tA4*Kt<15$r8bx^b)kIL4Ee$dEnu4$U} zvbI$We*07`=t=CoF(wP&hIP&7{l3hKM1tjuWF`%P5w$=h*IdJ&ruiz~x!>%tN91t`$bK%x_(gS$&Y+ov&H98v2HeG1P)lOU`!y8kIBWNt|%al z0Q97@Rnt1tAYX3zaqsH2lvk^|RIKZ|pwpM1`S{&xro6O_5?9b$q}FOl1`e2$b%BBp zTh4G};5v|E@{Q)edXMk7=6Wl;-12nyS$p^m*H*2e1`;$$Ug=ez2r*9XTy7Vl=Eac? z21vWC;m#MmB*bIIQG}s!_i7JrkY!W6KcMMAF}8_M&ARtrg{zWP2L)k?M1omanRn0d z9P$YL3AP12r?g;1&{>T2j`j<=h4Kzz#dIHPOtp|&q2JH+&U7r6bSg6WT%J_rOC7)o zAcgl$|5Pvapx}Yt^|LZ_&z6km2AW3le;Efwz|ucK?XU4SrMtj1NcROI*FlU@-v*l* zynKTRZ_3O`fj7FR1Uq_eGmPA&*-YQKyKEVd+JHKknkj%Q(#F-h!7YK3*P7(hnz)`` z*ARm12d4izce)UhQlUeZqEud>HgN%_qfB`{!s>dG%ZaL}l!s#uOewKgseBP_1^Ny#mwPNF}?!kSF8 zP`gBeP~w?7{vaZtMV{R=dO6a(jV|aURGwpo$sdJv%T3>^$_KJsuDq2O#5?#^MD8bl zt`{1Y+}4$+&a5i-gwSu-A{%qg2bqj}0I==Y0`w>du5iGMkH?}$eMnH11B-bh zlZe;EA@biONK3NsR}eGbI%I2ceQNNn62O8<5`r((1@{YX`-&Z-^jr#MVGIi!(d?-Funi~ z5df;(wsBF5zPs=QPm36HhkDzLbSU)zIQIA0%lL8bh3V66sDq}={!JG%GgebYZn|5K zbh>tDxlG}|I{Minxs9oRYZ+mQTs=dVJln!8E^(B|=+%RP0L+VIvFCQM2rC7k?)V#` zrONFvw8)cuo=Uf>MW&O|@{^1^O***S18` zioHCV7=8c%>ABav@=JxE_8={48e^+`Uc)187CH{~->sLO0`WlIri4^l!oHcsESXE3#A|3Zh@=Hm z;d27}M7EF+TScTT@c0q>1wOo5Nl|W?cW7qpXb{46HB*1=BI>pgM5*iHKu_Ncz;2%i z(vHeR>~P$WMWKDztsDf>Vod5Y=BEnDc7 zJf`2~71zDJ5%Z`4QuhqV-`dk!@zR^{WRnUx?a?5m=ur~;=5Dy1&u}bQc#=BMtEwtp zwigWVIvXI*FE9}uW|pGx$eHS))Z%{66BbW$cM>c9LxOn;-ZA36v~62J(Z*@OEccetr_e2rAGNKxwTF&FqsCoeMmD>;ugHU&Y2az` zXFo8#y1^JSg&sduz|Hu~ewJ{>6-^ut(yow{xdq7;2bXCf#$gzlb#v|{gQH)1w~3xm z2+uMwP)O-?oA`u zj02?!1?~G3ma!eLUq>DK(r>;p{C(;-t}H~!((~}ob?nr%l+1g!e8CQK%j;5cD5uU z+x(HLdNJK5^t36Pg@k%GGDiK-Cd^_IFyHk^|H_s7x9j^AN zq4M@KRS4{#JC6sDZuRMq9KMG0CQ26ds!_zX0%iTZl0l%Rp}lr$@~&5sZ!2&!DH3)W5WqDHsL>% z&8#0%L?NU{6E#9;qPm1&`wZeU9bMS^DxS9dgVV=X`zv|Ea6@E7fU95}3T;(;hf!*Q z<8KX5A?CAV6n?bY=Zp#Q7xMbCtLCbD*NJz>2x<9<%V!7rwUoLa`E6C3(P$Q38!B0M7&{5`wqm{JTTiYu zd>-Gsc{pn2j2U|0tVBz~Gq6+on^-$Kf*j7l#>Z_dc~fOjgXw#YR!|u1&kqgt*o~iD znW&wA=;?J9KtZYeyqP2uJdYPv62rDb2aBh*u{K<^XdMY6`C9W`^;gS);Ou=`VrO#c z^E%%YIk{0#WYLTdE|KIr(5o$yDK=p)+sk-^%ffHoHg(|)N@siv2ae1QuCtgyzf^yq zjT%l33DT8B6+i84ORxK%6WVvBOCejY1(ViDBOdK4R`B8kEg?+w-KQ6ejpvBJlR|=a zwk2;PoI#-hjOD{y?{)r=x}2hzdJTkIg(n!BeLUU0 z*wo(YD)T9*QkJiDppTVDtwr`sYXsRSbkwM)6p~~w?tZL zws0PQEUo7{_G4i;^r58Iu`JldE-&Wbx)Z!M2#vYouzK}5tvAXyp6|5#5+bs)Mf&N`K8q`(dr>p!(u&?th^NdS ze(c~L#oL|QxZqun{bjuPuS|c1vSB2tCM@#d$&pffErc`W0tJ;z4<$%ef_^6Hf0*hbbj}syQ_Ixp z=7|YvLaeF=8^nrx}B=PBg0BZqKx3i^v0ouTi<-A z1+b-y4X{A+G_)!dfgR3z>45#+ITuU(_sLEZp)(ZR6%wm7KwQ8uymh1bVK4tlOu!mwWRc^TOP=GdLg5b1!^+ zCX$*GDRsS!VA9vz_{}SiU9W?L;xC@=EAeY*G!$ z)@%nKIs8kU!1*#jlRFOH-zIg*OWpi~g7Zihbw8VHtVX{XjWH%ShGq0^=eGUI9q=|D zJC&U>9-q4P=HcEI66OTIpjllxKIHqvoDWRYICnm((FT5zUDHqCF$T z$Bpo>p;X9hg*#-PQx$vOH^&ev_T!LW`?;AL<+~*3vD74S-fdB5?~v|{QB2`TX7!$& z;305mA?U@OihX$VOAJq*aKZ&6MK$1c)tU%7(+ayr?``ZJ0B} z9MO%K+;|X%2IV|u_1u)>DPC9h=BVK{XJP7ze_lh!8^`#8J)x7)5OpRnc1DPFJ&-%2 zl^*#5pMVZ6>@M{*@7s)*#or~E;a4}RC^7qX^8XFV`1Dp!o(T*66a6p%%J<^i1l@+w zZUY98rITn+^@U_<*a(<(N8>XujE7$z25DYgH!%`CDaSKS1W z2=#_c*NBdsMF|}M!}PS~#?*4wvR+o2QMj-t)N5={&@qXIOon?Wm1nP(41Z7$55dZz z!D@(Jm_Bm(#7(PB8**a#!;&MfmklYf|XYOVK#+JctnsG-q`y-?O`LgoB zjho@Jd{QoSg{JNE#M$PyzkFvnb-0G#`a2e^2?;xj;C5D?O$MV74{3M7rMX^wonL(S zl#qY27DkGkE)0VqQNNr2^!B>GKQee)@Lv{iV@`Ecp!n;8Ek{jDzZIR7wU3Tj6SagK zUN2Gn?~2~MF+BN2asb&L(o1WV2LZP&$af{xam?&2fe#j0lt>L2MUF=jq6T>h94Hb? z6wAID-hE~1y1}Vv2O41Fj_IF>KAXUu(eme;cs%|fZYPl zV;H8Q8)QO{6AFkF;{g82Yj2w&YGUuO<1@Z}RkuJqMT$34sY`^*ASVXfZR^q10y`)7 zUKZqZ?>A^Su4DAY8owyWaJI59?ud=`k2k&7`{f|zVP@!6c0y{qgoY|1}FMP8vkcO_y=3 z7bAsHI<+XFGl-KuNMf<{&oH=tB`^pazE@{S-Sq6OB|2Z%;v$ znlwZ2lAy+HFP`-Mv?#rlwbb9Y`Y1X-FMG~g43kK0iIsETis+qDIQI~3l}FM}C&pUn zZ+mmy86SM?TF!c!AeUccQ3~nq&bF*vIGXn4!c+qzXopsOkRz@u8okj`Nh> z*`gfFlVFVaDmH4&S#XdwDwvp3^FPx5t+|T&JXW&$q7AI&6NJa^8EoB)u6qj)H1qVZ zb!Ia4>s8Efrl)B7viXEw=Q-rR>Mi*@?D89W@sPn5wWJhj1xH)7nC<{0_XJ?_`rP23 z^g++1G;at8(N8BL@`uQd4#&!4qA>#fjnq*}CNzgagrA+X;2a?~H6x+{{ts>m&W0SI z-p)tb4?x+9?Au$5$wnhwAYCG0?$lR4liS{%=u)Q%k;J~2i#hiYdFp*u$tVOQFukMY zQUg9$dr4~twccDzsH}EbaZ_b$@9%IM$9pEnsvxqwrfJB4aAmzI8t}io1D@q0^&?0> zWWb_Sv8UEdg{cJIbh5GVll`^=N-lcsMyY$%N2v<^}ZW;-P>37;a!7HJd8V1cK|CjwH;(kZ5E zoC8`G=Tg~8*c|QFN54nX3usQ*r~|lFU@AbQ4I5Mnv};?8G=@TeA|NTZ92bLA83h3& zn(R!L4XvI?*$fUk6Yq~QWxdu1lexQ;$5w6sObi(w+qolH)}hX3l<4p?yanFI@{(H% zESDcx6TV-+oueH#99-rYn4^A4 zpBd6Qi~S~DO56?F778YU91@R#0K!wJa^k??<-X5z(p0hyo)O$WdQvmQ#<^TQ>UZN3 z@t@n(LLwTPB7I*p&dZCR)DWitaLY_#QNYHBkuaAv&Lny??rXp z77}kL8XR{{i?fY0x_$EpA0f#h^Pc33FUEa?i3Y{cles7DKNciuC|MV{18UFTxj#hD za;aRsx&O+e4166z{6$S@@wf=7GRq%MgU?jI0O4|0Thid#o!ND(xdyDCqt02Psnf9~ z?87nEBZ=t_;Q7}v@8Tk*Kj{6GV(mSGm5deT2j}x2nOg$ubcY@)-SG`oh32HYQ}^S)T^8LveIXCmZ#B=mBuwIlc`Tj+q!2Rb!F%D;nSJay zkY~OZA63f)#GbXBPAS8{C^CCQ-9pU>@0NlSTlmQB+6MliWaBH$w`Y}&b~yrhrkEmH zVb0)0h-on*4jx}!;2r4At8;EK6-+^n^?{irhxQ}wfsh=DxZfSHzi2K=$?IVZi9O_& z7f?APTFU3I8M)Ggmc&GZh|li;A-Erj@^ppBq)=2`A|w13f&_^|JC+>SXIh^-Z~1|y zi?qRrU)``7a29Jv1h`m-l}^aq;)26fWL>q=3R-X8FQRc*LG#=Boe`$6noH(-)l8Ih z6#o@+`x-lAUWT-+D@EDW9kEO;*kq}T3%|1vHT>O$^T5WrMRAwm)5r80ujB33&f*LL z>Gj*J6;%aqQh+`d2Vmc{GIv;;jQ3163ucLP7`GADIc$WSO22>ewIrZ~$$xAFN>;%{ z{$@p$u`jc*N}2f!6IFD4-?1dltwMnx1pK-oh9R1i^~)$58vTfZ9xg&{{Lhpyq~Uek z%62W%z~uvbO-$?t@tEe@K6t80o&W=o<9zf*cBkgO!B2!<{az>nxDUQ zqYl|O9A(QfMUHfZYmfj8ud=X7k4FFby?cG{A@p{qbZr1J(7flW2kecIgvwxCs3p)S z9Q%4QC%eqI=`zPk`}mXvfIj&t%0rBg>#JYpJU`JM%1RLBU$!COivUDRn?N4PNks+P z#AB5}XN1G?64Gp67o_+9jP{Xqb=&{eo~e;V06RjC6Y*oF?w8ine<-tg^Id-Mi0guZ zv2^wmOtmii4My?V*MTf3bl2dMVtvR=kMjLB^J@93DoZEc2f_}PMP&|@41m-$R zhmR3#+B3$?VrbqPTA$xLrJ6x2!I#<^_HLW@W{Blcb%AP~ZUgJi-APWXRiohF6xkYe zTV+wm&&dl(LuNvhyTkL(0QDm^R}G%1mTsajUFQIvi4{6JQhk%i=oLfXoC$r(BD_>A z2pl;Srn%{%?`l`V(fEy3*$~|J!K-$ZM(}uwM7ksJ%RIw&RT$7kOI~eik_y%J*ayvR zPMADRe>Ir%xt!n?^hJVyOEaS0SAg3C_4D3mB=%HpRba10o5hbUBEklK{Q17b+&V&6 zHQ3GQE%bNYGO4Y9^SoBIU#_Z*t7dW#MMcgR>R2;Q4!_XtQ62PDH*Y3Q5M%tY7)cGj z=yOMgT=IQ{6!L*+h1oSkI=W=Mzx6W&?K1nT>NPw}(tnzY+-8{Z-CyrjPnn$|><_nf zkMw*Ag71NBOxF!2peI&Px@{4B$uon^`y2U#uOFhZmaD7N-PHDkTR4S$1qk2a`4CAJ zBf^P}c;We=^3vU?lJNB!11Z4pHe- zWF`9YY&tJjvTd6+DsN4V>~(BRH*Qz+vg!q`tTi~~Mv8M1%x$B(HO>)3A6`$D=~`() zotL~J5^|g^(sK|Rd#+MG3s~=$b9=%r+z@u+Ml4yT+rK34jFpPu20r* zTjYx2y#$y`_aK>6*3?GZSne)ueD^=e8|4}Kj6ZsWtl+fU6hmk=KBe$l`Od4r|3~K* zJJSi%gSEC)1JikE$9J@7+WS@*jn^yxzB=*xYBUR)Prs5q2*=PTFu9(Vmg2viE1%T~ zgT4HRqQ4^D5$sgQlZq|cLMas3$wEJeA*-y=Z(mj&~TReOmL7}R}hVm)H^&C;>bUOoR6ZxL3tmfG*-RF zt46*RlByncVu}2-!Q{(e?fe!?dGK30%zg?ys5GE`k}-Q_;W;on zyS8_a2`z@zX>SBvDnSU?zJJS}qWllVwBH9d6)nFTf(!QM24RsYJK?Qk=-@WULkw1C=C5up*u?-Yd~ z`BB)^ei313o`z6@MQ5$P444p%p<=a#8qlG^!y_NN(PZd1nWYLg`QNVbAn+mW{zov?Zp-8gGw{J z8WDA7EBa#h^1-dlcQgrfSkp6z`I&DV&z-8?BL1%%CWzrZetvR<(&;rWjBBxoHG@2_ z`#@1k3+n+Z&@lP)x*Rg-mkoHy3w1r^i^xkg~3)-2!6;+i&(L^zKck4w1lyQH@|TKFY;I*^Z#G`~o5*2~P$e8CZw4innMqTx@7P871t;FC ze4vc^Wzat^Xp9{H{WVSq;(@HpJTNoL=aM^1*Tmaqr(8u(IfP!{206HgFl4gKM%Qxq z;BEa|CjF}ud_GFJOPdYHhNuhM3Q=<$eWc3m=z-{9)&tnT%A)teOAel;nka-q2guF$ zsG_JzgJtKM7>+j^i>UslK8P7F_pS7N((D5KZZ^BajX@LX5*IYJkoa9?*0LULtvNo!Mu+cpVNkRJf5Hzrou^0 zuZ@jm(!$aPopDp*y6M?v4SaLApUonjr+~8j)`41|^0PkQr)V;D7e-oSSp8@8-iWd%ydQXRT*_ z1Mmk{&EwDZNbyyy-E~Si6ae6>V#*{sB{&O-c=9rN^7e&?D)h822{|>jA>A9}sXTavTvz~&(24DB*9~N1t&AY19EvO7oMJA9G5yLB44UZ-*{K^sb2jr z8U+O?CQBJA{vVr5tYQ5;+-DP>W9?csuob(v?&vEk7LB7T>&zr?Ky;kwW0;++Zk z-V7l|2#+mz6>)L;tX>~+WIV%gd2*X;Xan&bHEX(g@V-ajKcm4()#f3O-J7o)PG$Ob znvq`Srdrbv)FHlD0+%eR0Cm({uxItFO!VGrz@lc|%-Y$WFWntJi}+X9>8zjXQ8-$VOLbm;!Wiy-7UIHqt}6stH>L zw*3#;10rO*K33Ul4)*#>n6@A^k*PemEw9VXVuoCu6DO>mNp#{#dwa>Cv(8E`~Nk|45AL}s(a%rDOQWx4EGqyB2gU}c;elbl~L#S4R zWslQx#bc0HalYy1qXnFixu86etSZB__@Hw4v$U!Y zmNNZ()Owq^n|XyZ{9g43sh6mVjS)`leW5z8*LLOFJxQu`4zQFu^K+>WH98AsE3GMr01 z+!8|f%-s{bQ6Txg1!Jc+B3l*_4MilIk7iy0s-2bQ1Z7zJebE>FF~^=xzoa5p`I8iY z1HaQ@S?`f4h%btOAam`@k9G=W?0|R|&wI(qIhVk+b@PoJe>LTBAseG40w~g$cJnX+cCvDB|?(p(MHNHnF^MGP>p2r#i<2T~qf*m=DP+8CfxYW58@T+vK zTLN`oA!?_|hZ)_L?*gwb6$VTn8@>}1-wL#sJ_5DIFNwef0xlnTU^ZYF16~7ORHbWp z%|;8hn+(*ST9-RE)|rWDkvr7Lq>1lYMnXH$3t5>qu}rxfEbgnLs~)F@a#L=S*7To^ zm31+b{Fu3%&1_-qjGN9mLJc!t6`QF{N~_e`HY8Es5jF5Pd2Yf<6Eyt1rJ>omVagpjRo~|A(`aY?JMaHuvf7|Qtl-pZ{}vEtYx;H0U6Kz(YJiE_ zO<5SQooaURt2~bsODrzDc=Yj$Ye6!>4aR`u!nV)C6?B>k``o|Jct$u%H`6F*QCv<< zMato24SNY5Eb=TbQ^?{{ZHX-c@edz4gg=3g9HE=+u~LNZuISQw_4cKS>BoU z=14bNMobZIsWS4J=1Y^*xI>^?BmX))G4gK@Mh{2R{a$m8w{HjhIzN98mx*eWcbI=s zfVm`$O;MJn{Givw`OpF#fjWU_=VqCOK|Gxg z9$8w+I=XvSI{9kDsdt63KE|yb=;B>pNPQRh_>%nFKQ*ty3$UN|xFz?`*hs=fzYF-Z zpUR9ayTpon%*$uUP+LR6G1Id)eA}T%S#Be($ldCZ9=CwYVJnu`*e4;sz%qArZ*HTr zRM5i*XrAmhNX z=~3yci~zl^(lP3+*^f71An;dA8ToKvYTvme%iDPIVj|_!#LfC?>{3M%an6e%zk%JD ze`g0zz_Id6C~6+nGiQeyLQTQ_XX47Nw!_V-AQkbwf;3qqxDGMaS;k(ZvuitqStS1q z7G)1#`fFN%rfD<=Ex+Gi$1GxF*%&I-(VG1Bfz zE_6BVJn#LJdd@WUUNcFCd|Fj8g6N911*I=~_%NG@h~0+g1OM+I|AS>z#{4-fad&VE z?yPI38un2==#RgrlK$tqq1V&$LekA2k5=-Y2ZGJOTEniQsQs5Sg%E7Ai3h`_Gsi1- zEBj)v&jvX|Q3n01_@e9u_#M#0KOx3R)ksV^T2t3G#*QVXmTSIOIq8fLhK)xLnL}nv zHzLVTfRX#lOZaG7*b>t3798Hzm1#tV|G`y=Pw5$R_RmYqv&1NU4rN-&AyW~mN-LW$ zltsh9q9uCf@P(>DR%21QSqO6}5yz)NZ@$96YMX)rXX`EB{48>+gf$p6DVzJYBb&Fn zsBEE;w}B{VFQGKWKbbArh=hyjd+c_7iKDgvk}Bnl{6Igb1ND%k32(|1#@Vo$66vxC zrBQ(I?wpJ|<0d9B`+S7Hx@0Uuab>Mh#iFtT_)4IMZ+WLTAn2caMq07odHpwr7YhhHwU0r1O#GD~9l>sX6nT4Wb zJv4{jJ}|kx!+Na`L;VBp220m<*iMbJ+8;bfh4O2gzYGs9XP|>UJ?+!jvoAOJ=D_R{ zefs8p^oZj+>99}J!WHr|d-dBPO{cvMtZbO7Uo*Dg^3Ap^BJn;h(>;RM!(UrhY+0B~ z5>#(C{k*L#XM02}egB<=mh*UbQDu>#6&lvZd34ok?sZIGMmu*PkT-vI zuKdGUaJ1+Y}(w-5Q_@`n`+WE0Ak>x^6GD%(^dT(EBZF zXu->{fHItd_N~bvgFYgPJ8%xA@iX$N35xUPxkJL&+6Ve`eg)bY2{n@&C!L4u^}M?5 zVQ9s!&gd>CEFzW@b~+VEB2;a@TYHgCOAg>SYR~hT5@~$3(<{?EIXO4k7^gzmsWLlK zG^BoB@y(y&iv%-{A_AX$aLf_OQd%a-#P2NK)mo=(=d0CkfYa`{65KRv$OeDax*OgNLCsuY3gzJhiAw>@& zrb?KR7t`y9>F&8boCp6MiOe=FjZ$pYiD z)P9jo+yS;8h*a6EC)E|Ga9a}#^6{*(b&GY@utfR$Qj<)zdw8&?C>DL!7XpQtt-=a2!p!Ka0N?!I&C}NrhpDK&4{5zk`;xOFPXPU7@;2mbB+sMG%oZV^E(H0g<66Ce zc)WXF$*JCCpKoSMz~{+Ej8~;%1Q_Q-4)xkin>2-5X|oRB`_r}TA#+FjUAK}>XOTZr z$LTo1{>ag(n}`B);gKHCuTDD_-xo^rzpAr1i!CK)GcPz&N7gbg=S#gME~3?uY2qKI z!fzyg^8O#%_;;Ym?#p`wfq4PRl0iiOZVzl0o~LSJv$qcjv>p5SX$e;_;1f;=g_4(x zSzuYy0i={P%MIJ;IO<=%6R>BL&0cS;bgp#WL8O8`=G}P@O|5UQ;%cd>r_skpd=&7m z=v3s6F0ay%;Ke6<`klm`m&n5>??z_ek49#~(cyJ)SFT`Ty?Y7R!B*Ax6!ypWj{bM~ zU@;Do3z_Y+?_D;GyOr={Ubf9;d22g#xl z+k+q8YR?XU#1vY+3=uG2r!WYp1I?JT_J<80oR+X@R*g_C^|Xpy9($`}-Tg@$Q%u0V zmAs|M@tR?*5lc@IoY~2sbyzwN8-Se1*!8Mq+!}TkYb%g1GP?_oX?p8@yMt)BBc`nt z)VJ2;bi;urB{4H3T^Yb4pVXi0eekU{Uw5LkU8GOd2EQTdkfGb=8>&F>pzXsRKQ48Y zcpVI<_WpL?xCbwU3r#WiEkK1|4=F|G&UL5N)Hc0&-pV%Uwnc5!oaPngTzp6e1ZjTf zTUlN}XnTD6cb!AEz(#j)Fw%O{$VMPL^k#Vck?bmBJYtM%T7P+F<;mDF`+9%egBRT3 zPk^C)o6hj@4;KJ1sT1G*O-H#qD`-||Tf?9!Ccn=2R`8yc=K<1XyEMR+a>j=o1PLOOlz&Bt@<{bTEX~Z; zk@{8&V#_{^i4nTbPbw}=7)#SQ11QqV|LkrJE|12mZr{Hdqbt}pN0p%BQT?bvK&$oS zg>|(cSXz)^!V~#g;lXaQuAMsKn^Ya6NiT;h%dWudTcQ0yjsr#+i(7s^PEBMI(jFK! z8^JK`aNf3A?%+bDzV>+`9vQ6lLCx<)lYM9ViKY4SLK=%7Z<0easn4a9!qDA1KV(Mx zQlqwyVQOuXC6i}56G5$Ovdpsw4Kd4!^YvUF-Ct{Xh6>*1v^9+dHky6I%r=lq%Q^*f zfhpz9^eHC1UqrQUg)UsbkMHRRtu!GKJ-(cQqD-wA>D(WO~m;Br)pJExArjZTy(~v=qK;nCJSkn$m?-W7tw9JH&`{v zUb)EgSQ}#Wh1~5M)h)ECy6iUD!EFu?zeMm|aiy{b>-@7g?%+N@vRB<&NeV9wU^;3v zkqWbD$Nm*GA*u45gUNe=`&}Wkn=!=PLlHMkLE`7%hC-~D5 z(~ky-ll4LMC3l{Bp&mNW0vUusNO>2VSIt^Akf~3Qj+Wtbhr{H^ze04{kKWYnSf4b5 z$rR44)~Mc%Hb}`$B{~}-Km{xa-b&u40K#goIakuU4DyAoD$x4pG=ITD#JsMzWE2o-t8*i7yQ{?5)OVybT-1Ve-PeAglgV zH(g8C&iJ@?^Ah53J3m4l()76=@*N?wOQ}OxCvxMe1tBsJU?Ip^9?pf~=lFj}5w}g6 zxaZ<*{$2l7KwIOYt8p((P*{Xqd2sh$K0*+v*RV@1G&aF(GEk6)4W6xJU>-AF+mud{ zi+`?G%TJ&Cyt4N4eOPtars?mYmqZN}B_b|l1>4EUhOdfm@~`>CkS?x|6la~9UQNdG zM=C)t9nD)(`erT5#YyshV21x5Q=loeepV*Ei;Mw(p{Wdw$>d_O#t(Du+ zNBS|@mvp+o($n3R7KK40xxgFK0}MpHvUNI%qbDoG3;udLwF{;ddb=9sU`~oUW$Ets z-TsC^osKvvFwvFP08x^=-;Kb885NgZ7mlB@oGnm9se=+*JlfcPJUB41!(ZoyR;t&! z2GGl9w{aB-{O*P}c$`OH9=H6W?Fq7HkDAVUZ$IwXkUjldQ!;Z5C~-eg4_5=TgetvE{W94to#`+soc!=|NL zYU?v*?9V5b@;HI+%!)vx7dX){@?YeqvaN1mnY z8JlUnk5R`Z>p^qPQIY$*YzO~+P)F{Wvti-lBJQcNFnIJsBd!)~@uUK_1N#j4Mj(w2 z3b$M)=0O^vd7t&sE13CM7i_QJ4Tl!Ao;Glqw|Iz> znWU3fDulR&)SlE=q=u0w^7Av;`&BZQd`V{VQ5+g6TD;xq^P10CAVVJIs5cQ3zT07O!$VZ%xm{v&A06Lf4%(;Ad53lTYKlx@}0%Kz)xKDlZ7L}iCE0F-4 zS>+mS{V6LG-Fu4eH7Y61o2qV`7D;C(hW;mg%ItVLgu4lF=V`%Ljkl)}`+TscOr+<& z74ZaRM3GdVg!%C@sz(z zBID7rfP%`TdsAzQV%v2Y#fCb*8{I1{qjL_bWvv!jw^T44pdRoR7L?L^@ry6i3V?KA z+>h!aJdzJC*fxTfJcJ$|BXq1>K=UTaucgTw>G5nk`2M9l%j#HdMCOO_qXoKeA*yZI z?XtRxJxBN?T-KWk!p56|tEX>%PEMJ}R{Hzbnqz6v#!QZdt35Jxdr2BJfsxe=o2s_* zpP9pK{``ArVacwmf$q9M1f4BQf4co5RFG>0?o&mzYpoyt;m5LfyMdJ2zV z(t|0y;;;DYw=}*@e=nTxF!5{(r(Jun_N7dpR?4iOz+kI274_vuGr1=ijx((y{Kd07 z*a>*S`NtvDx0WU@s~7}K34&1RYrZM+*&I{{&N0}6`O%>V-9HG3?_Fa&*8{JdQM!MD zIz1?JKPUp7OReF_)UpO+F&o^n`Z0ZCI}bk#1yg>MJVSkr5<>cCj5i0Q4Ukg-uV0VQ z`wFy|_zK~D-$??+Mcvj(u1SMF4$<_4Q@l&Up2%_Sw~Ly*e~ps(QcK!8(Of-XBB=e3 z5l-{QN9{=B;BG9ra}AU5CH^7ZEDio-e`xbkZ$pEH77w?ZeGY7^;$4O^dD9T)km29O zDQ^1Msf>2_nur+#BuGE>;;oB}UB;nFS1Z}%>7XbnHIhh8-}3rZ54%C1&if%TaefLP zaL8%MXKQzNO@ZvPEhf0c-i<}mZKXV$R#r9l-*ImtOcG><%nQ>e2BrSV{NuW(>U3YU z9aCfBYR*0V^11>dB+&F%;7XQ{n%;myW2e$4=RfzKDZ=vYI_$9FkqSk$IMgc23Uc8Dnf zZp#n9AHBwTt4hqD1u1FUB%^kipJQt?b>OII=u$TS!`xs_a@f{JH06YKz z?v-Qf3YvV!N2H!ZN4sGcC{dNqU{lne=^$q`W88SCHnZ@t%$jMWtpW6HoZ&Nan7OMZ z(X^cBSZ%Y0lT@vg`M?a_LlD#iWrrRz_}S1qOQ>XvRN~j-<+L9dvpz1){56$)OP`HV z7Aa*>WltU0JS$9dnwlC#;D<; zPW43b4o{+RwAnykg6@^Q8p}22!5h^6VzGK_2fPG^E4brKFz4Q6dsp3VJ@-v^TSXE) zpWHFf>A>a*X#k!WlPvdP`Z@u=oDlN|4BJD zl`mXh$1~lmH+-V_c9Xg-xqD{o(J&Z|lk#JipHS15mhqZwVej=6t!24Ixx=tdVB*g+jj~Og=%hcaav1xWT|tFzc%M9gTO1x3g&3_YFJu^@|$43;(-MR@IfRj%7#^r@3!lACAo`=f)`FfDVo z>3pPx+@jQ3(`xXWiKC8!rzT&Th6-%~C6)s1Y|TDWl`Zo~Tt`m3m;DD3$eWVG>=x;z z<>cy-_{yRU<91FG5A{lIv{P+(S$1x$;*jhiIqGoVlL2h|KeTvRAtu`oRc70-c}?x# z*cdGt{!6@=m&J{JOHqa^witJ+H8E_tzk9OBp;Eq5d{K%zMy?^lYlAVTpX3p;Fwy*8 zgiLeQ|Io@58=S_H-T&)^+ix#uI5tcX09wm5(zW`{%EZ#a7sD7eDq#wSFN2|iMccX^ zM5)^ZZPoD{#F^`B{wFCJ`UPnL>_;1+4JvY3E(hvE?NGY4` zxRh<<+76;I-~T`d%&#Su3C07s0b9q-!VS-Mo_C!wf(0)3Sh$StK-O0q%+KrUbky#m zA@Y5%N(S9trQVe%>~w0-+-}+#0RqVk+X=C=P2P>@a^umdr%zjQ&5#7C?VnCI`{v`k zd0s2G#|zXq;JqmY;4O67!mdS5nlLIFCcVUY_UbP@W3dqlmOizdqUNu2U2x+>z6NO? zmLMl=kP{TLhs?c2bx+m}Nk;`N69Zm2Js{C0>WPW{x7O^f4*)D@gsRHB)+eY0_51MP z)i^TlL+HEqm0aUFk|m)&jjQ3;D-gHK0bq_~PCLVEH^&wmR%#IFS<|Ml5C`P{-) z^$;d`FnDasIEl#l3K^wH)QkI=nG#oSr!VK$8Tae-d^}RLgQQKLs6LRPsT?? zPBs}P?IF-yo-Ju zEi9GexH|^|dq|gF`rPDkcJ!vGVAs@EUIT4{bF(vQxth2|>8?E-y#e_K@N1!iJo%oS zkS2O7ekFR2n!$b@2~6)?Cz|zQA5WoSWW198wJ7E4a3qlq^iv`y!~$6I)6^YEAE@s_TTY<+{VD zDfZ*GWk+}bHao>7naUGlbYTvZI6qM=3nY8zoA`{qB#VZJvaTY*MQG2Rq{ln*cNe{ zB`i6uKd$6e|8{%*C!wQryrcYBvD--7Kax?qyj9#a)JA;>U72d`6eatea*L@|#!Ctp z8i;~;$4=}bW(rbryukAS7k;vn8zQ|_`8f1^-Aq`hyUX}9fiiLYt~?dthFc8*jzfo5 z*jf2;Nx@C~a!LNp8|`Z|=KPnRKrT3HNmOsR>p?&31l|WuM^f`yw4;8``)N~zl~g0G z=oge*1Ilt>cWQcQudXG1S7{A5Zw3N>jO=i@0JBuF>C(mdwUbWuQ?67l{_u%-kB{#S z{uztRymOQrldtDN|| z4|}%3(sbk7a=&_qxpP8R3eQ?K$k&u-N|>wuUE2t8^DpN^*4P-}2WZZ2c#FUEtzr&8vaAFsxgU&~eEJ#Vr@ zC8FY%B4qtH8i+>VJL+&)x|=6zu+iGnv)T-=QU1ZF4=a(Ohi00Dh{?GdT#ht>gPy$i z;JXu4?l#JE?o6+~azVv-maFTme4eKYSN05gz9-kqV6$h}7yl}3@)i+LEX5ir(0H-& zAU(Y&pP_KTON9c9Kg{n;MIc9J$7H7h~ zAL~Q%1O~lSg4JQ=8Fz4{;sT#^(^VM$G=#N;_t{Xm;^igE2W$)WeKH6xhx1M60`1dz zUPIlLb=bDWI}b^az@};`hZ|`Mos*w&0&vy1-4*PFBz#T)a`2oJQ{ybn;ZvHgzg-|* z{6CpB`bG=?_b~Drl#90lkt5b5>9b7V)n9jE-^k>h0#iSU*BN}<*$@B5n$4P-N@_b_ zvKHffFAdZs5Yn*!#OzVzK*O=9@4D4s?RuS%07VIOdFmbnj07x<`|J===2b9cyTTzeWC|2iLz?Y~aX|CC?Z*naj-*{6_qc`RG6B08uv9K%sxa8_&o-h1EIaPtcszEor zvw*_^8X+AbyTBwvmaA<`V__VAoEs)|x}_0%bbgq^2r6g(Jd&)VBpAk`X457Qeyvr_ zr{{g0hE72*D_RPKg3lh_7WHlbTdhfaUQ1V#ZllLR>pFE@{`GthW-MmsA~bHJ+M%3M z)~pHP3f#EujSAYdu(aa;*n$eEBUJIPL(~9j2p)5ue{f2c%k-sLGdYv z-gi$RW28MV17XZ)<+2Q9Z!Z zB_E?B2=MU#tD72IES_8TCNmJnqB9=x2&w@#)Y$(+V-o@)CuEs=CX@lO@0$8!&DAxzbk4^Li-6UR_geX1;$;U)8F zr02O-@P|X6KuoGA!XqRbVs>nO1+}*V3p@x&McN)V3ELcl-!12C=(a6g$kD3i&rTXW&Oxy?zj&t@ik zz1VoY9gSDs2x`S5N=QYhZjLI5U0y65yakqilP5Q=n8vV6h?IWprzJjTXUkqC60XT?>B1g^#d;~D_CpqU;htHW~cZ9gy4hGR#r@32fOz+ zonpSi#``?1hSY~jP5pg@d+fU2M$&pVM;wv>5wiopW}0t5nQ!X82^LrKw+&fvcoiKm zZyv6}Kz%`pl{8}GkM5%l;)$%HxTz>-L<7DdC&moFhVID=Iu&qnG>V)%G^ti%ohXNC z*E>@onGGkEhBYG*2mih2qjch6E3>1LyeEgHda1!ip6s)#Iv$IRPnBBkuU?gh z$uD(Ky^}ar^T9!yYOsA6jX-2?hd@!)z(|ViMUDKTT=Ea6g>l8pbaJ7;NlGejFnNy= znNs9){;NoX?VbUmj3<^hat%Vx9;2o!H-p)X;UBUag_61)vNjm}K-M;Gd<0-tw$a)# zygB$ogre;JZ_zND5YoyV51G8IX2TOS)?U}MJWO8?wN$)WXvE>>o80w?BGjK+Cm`X+ z^Wf9pnJHU~0;HX? zKEov<&tdvV@gbqlm>$n{+LV8{+@(;M@;f#GT9xUQ7rn(fP*W01N2a{W0r)g@gg2eX zH}nhZb1`Sl(>{Sf*#byxwrUl=eoiN_sU%uaeD$6g>7jhnYzx(#zobk{XL z8yo)tX>op9VyymCiwVy2&)jAkr)2lG=hx(uJ(P6!Yy~RtTrSWYXT0RvX`bo%`rPzo z=a;x`uVg-WXV8?bCe zL4coaSoh4H?We=Z=-)=*Ea~yQ#=z6}geT=o2a&an=#oB;N7y0n53J6ri?OHa*E$Nv z47Z}`(8FyR-=(K&Oju)Uzxg$jE5z#6ym*_H2HKTWMO!QcU#23{hA<_ zJ10Iw%Q2KHdiW-PwxAc{>5nuz1l+;+a|`&lIDy<>$xWMW)hzy$v6dz$yXGOjaZIFQ zU%%oGO(45`v=dG-LPL8UQdB2nrb{xFd#Z{;HlRN_1=oI*#Yn>6IvV>ZKc~+k? zp3(&tB}oG~|6dc<{}vx!0%Jf40B`s1P4*{*$?hjPnstTs-%MHVjJlXy8Rb(w?MnCE zrH;Dw`nqOPEv9mP*eUfWXH_I4V70wu;SBHf;jEalgomI0No><_Pi%#{v7c!38(uTA z#>QZm{wqW7uV#!f%ryYAwmP&}Adyp@`Bh435GwY$p@6v5gTEu;clZg8>6Tc&28R#6 zHD~b4+H){p4jz@Go4>nb@!M<crN)r#@=eI`qa>X9?xOuJs#7go7`Q>w1OQGa z*qk}FM3&R(kA7<{`)_yT$|u20{nbk-+LeaB__bH>g6dv1zMlNw0KIf4z_!= zx0b^$9v-{dS-C-9=~@d57WJbfsJ$rO(O8?2>#Rcap{yvt1t<3KH5f7jwu-Y{B08N+ zclssLP(Go*d|hR;Q<(6~G>WhfZ8yLmPvVOdp~(Kb8K1Fd7r`aDP_d@4beDDiC#bV8 z&0U}rQ?DoLoNLR5c{ zxPgL50qb*SCzF?iE{xg>otL*!SpYN!op5JEi2K({&A~+AOU3E-rxy2Km4ln=oeo9; zI)grKj9tbZM%-v#Ni8#P`|CpR4{^YTH65thmX4OiviH~i;&)acL2r7=`@{jK*Fn!l zI-e}}?`H?>w)t|9%aM-(DHkSgMA^VEA#iaff>KXxzb47N?#i3lAt}WnVK?< z<(Gf4o_$@}o0D8Ev_fd9-~!t=pkV8U({!WY%Pok9WK|GcFI@`iOt6TC+Ywkoh2ewG zSrkV*I!X$AP#psnuZ&?w=W1lfRDt$MytwSKQfJA67aG%V#)^e^F9qL7sqgRGeg-Yx z+mF*B3c2SV%%^8VkrViGRmUP%*nV__0h(DN0$cLrhOcTW1?W5 zMIczj5oqd61wMaau_$b&yt`(Zzt=&iNbMB)m_C_c*NkEZQ)XJO?zwbKv&4Yp^#KE& zb4{yQKb*+WeYvPzcx?O)Xc07icil9TI`N1(N$ZV*E?(pF1cwBd&o^CZyZe!5TgRI5 z>aB*=Bcu&|g>Kn%ckq`V~pIo9Hh2e{g93L>}Lu5TN-& z$@^kv{R50F7fI^;8mKb7_Mr-GV1@s*XNg(L9@f}OPG4D5b)hrz+$i z)-7!Vk9hKCn%ee9MC64P!5|yj0y`5SQO<$6&StxveN^=UzrDHZOK7wyqhFceHfu1h zj^c)Z-+uhr;`y%2Q|G5^ z8k-5gx0L(lmMlaGs00f&I5+Y%9`xLA7v}~7AP51gb8{C;np__V>ha5)wVK@lBDs!( zYM51H*Vo|DDWF`i!Xa94))rcGos`KrmKs8LTi>Mof=HPiGe%_Et>|+g6+hOw`#z|i zxo*xQ_&L_brU^PDM?e|*e1%gRtEuH%bHQ4w$e+pPl%Mcc3CjPC7=G6!{`c#et)rh= z;FVylV|blXvaV`eyGlcL6|H&-R|LOv?yFL<;9sJL&kfSnLSgIpvP~bzY-|A`=&zi3?lSaxDkkL55NmathNS2R);TME_})kEDUPVV(cd*2BXnWfsiYja~187j~K zOqaG^xuzgRaK&);j^4IUk$e1RTNbD|tLsUt%$M_uK6{tVvM z5L3tgd89$RW4o$foSuTHQ2vFN5mT~B*RIT8q4os5p*E3H`BA8rZj_^^UX83v+h2ae zsx#8j5pl}DYEAu0vG4i<;e<+*%cV?r_Bm6}MO^IfGVvFn0XF&YDCFp%%X@@cXTe&aGd`KYSHd2^A;HO>)P&Msl!J)IrW zAGI>^8=Lj@E3R2;)X#m)n0`7pfds`iyLuf|vi1p|Nn-4B-37gSHm0(QuO5v%HEv$R z(SSx zr-%Xdmlr_TV7ypx?AI(2rAUeJz8EPllK0`H%DDB|zWdWqfHBp)oQ#{F0O>Kf+ue7efsZAu&FZN{xgJBk-)@=cZI z{HJ~4?UO{~4XjZo$)4Q&7+0%gzr$5B%9DH=C(6(8?jTc8q24yYzsK%s?YHvbyTt9X zQ0Qx-IY$hy^l_%G3481Ki9cZ8(+({u5uReH!hijaNg!n-{q$`2X+0;j(>?)u5u(%- z(qxNYa`h@GRlTS1Z}V#=9{d%d`ekvJy7f~t2|tK7mCJl=F!GkBMcY}jaim0t!|pz&3?dO}_=^y6iQIRH zE|AoXUdTwP;3CE7yBYI}UO#g0%shT&0!_gqm282K59y_GO%$4p_FE7{77Y@mn;WuI z1>F0nJGNtxc3it>XY5OmdKkgjgNvofiZJfV;DNA|7+T0-gX5o%@81VeOmjYa%V4`= zZ{4LA@AHQd9Y1x_I9-E5q>dRQi>We9_4+3x$yn8^Byxv%6z72|Z5A!39_yWrp0}jD$duR9UN3??dK+45 z+3Rq#W0PP;lrAtDdFxJ0EHym`l$1NW`i&=Vneiql|6g0ZmJO?k!C|}jE)<5H`c(LJ z4YGJ;%G_!-#nmGC0@ji4P+(1)$>d4Z@i%6}N7Oq1-6(*=vzTfl-&<&X*psQOoT7Qo zxp5M(pkXQ$sSEQVkZeB@3+_9aMHJ3b%9M*h%aO77(mIZ&)!nL(`*Sx$BG)(@xoc;O2Q%zr z#V$68bh^Ct$LMbSJgMQp@XD>4lwF(@+{Wx$DxT1w-&9oUMc<*!V6W{bz2L7q(=w(a zCLJ91-pI|y)vsGh?o`WCdrX-76rq+UTLFfUR8}EUG|2}FGh=VkkbI&QyWUFN? zC|Q58DW&Nc z*o*m>8X|D`xD()=^2J z``l2I_fI#P>tEN%L!3XsjW)>XSxGeoOQeY=ht;Xn7cgSsd|+>0iWKnpi9=uoQj-uHzrM--y1WJfQ+ZHcYo$^q)sI~PJ2cpx`PkH z^j19>J2wF#C!JT{7Q&yFI_Z-2VMMCnSSi`O)B-8u{huhH3L*XmsC0@Qtvs15hs8NM ztlZ2i(i|16ty5s#(I%0H#FmjTd9SeHmgZ2<%Y}9Ar@nRGRzzr7yDj@Av))U(f^^nt zbc7w8ncuOb)w}Favg1&^3wVE#9}Gtm@&2aj>si(WwBLuN*I7)y*vYlF$Z$?8@A@8J zqmSjXOm7aDxnP0>4nDR27EF&!0!$>7x}{4hy>M~(tp(!O+SyMynW@lzoaL%=IQ`zr zeKHHKI-I$oM6DQYjg#i*~vLM#g2*OpJ;O5TnUtAOZ`8Jh@H;jzehR zljWy$l-BFtTaDp0IEq7*&wiEC(dq37UM3fry?_EJf!{fS7?YFcU;fVX%;iSUyvpxv zFjqEE)HpK-ivhq1P(m2gYr1@dz=uP{=oTZ+cke7mj#tO2Dy81hh+Y(V0iQ&3RhGTb zZ|E`bc;x4-#GQI}RhZ<%<~e%s(a^D{aQE<%ooc0N&eG^UA4yl)bkGD;RI_nkX&=Hq z6dd&Ty>qGB(J^si@bu8b+}q2$pNz#;1M@vlyxS4OtlqnVN<|#cSC`l+_8lC^Rsm?QfpZ1E%#v80=&Ne&8f>U1N-$#b&9<> zNqoAtHpYX8i$p3Ei%TtNRe((IN5QWkgI6T|jabahhvv_vp|fEc(d;}lEF=vfQI<(8 z7C|xl16IonJw!YE7xLSkkSkI6v;U!;zJW?O;Epgax>Mt?JrHJgn5VBCO>NQ6m2^JN z&{l-}et3BD(y@}+-qD4FJDfjAoD}#4`aF8OOpC>H>(x^I<1boy%ne)U639zAxGIXd zEvOf|6Ox>)WnK8oN-dPokYjY;;>I)d1KSDn=jWlcQvc}y>&4%!!aaq!XdfA^aga^O z@G7JY;y)i;?!+>+|5k+dQoXP=D^=vL^$M~R{R7SLjE~2hAC0AelmwlJ@187b-Dd&v zKkSI4=@7i0qI#F>3Fh3AUInr@$i=+|5~@g8705b_aaf3lV8u@6+z z7axGSZRm4<(9~`l8d5qkyj>U!mHICKxMvJKro9D{v}axgLrme@aR;ldT!ry&Fm3sZ zv$J%wsz*fhf%Sx;!C}GXJmENBXmie=`*>Nw*2RQBi)BT;7Rg3=K5R9+txR|OP%(@d zA-{@q6cAYYrRUR(rwrKW^vR~P?|y5iV2@~BCy1Fl2Fq#V$8~j^G3!iZ+n?Nht?ezaBSDMjW4k2XqA zG3II%mI_PF>Yc1O;Q@S<$L3kxMW6q{yS^oRbd3`;W&{=exV`t)MSD4WsRpKa3VBj; zvdN}3fwSeIzDqw?BBQhfPXbo{RxflX+%>1h-^odmGT*HT`Z#yevr3fwT1pkA{%k!C zXbWd)?NDS!yqZ9;-ia!x^~VZ6a5IA_{dd%E`{RLMijP?C*xw?SpTDANYj5k%xRI7O z3x*qIuM7MiqQ1f_s_%;z1VjWxBviVQ?vA0mOB!j1lx{{qy1TnUQc7x2x*MdWyJiRn zhWWnxduzS*{(-yB%sqFXefFnXANgsJvUT7r5!8=M4}#4niCj3-*tN~WRI#uSee~1Z z$0U@DIs`9iOjdi?b&3Enu`-bZ_?7e)mpZtgaH8zmHEVdY_S;ix^lFJzxG~RV*8Du&3F&ooN?JE(H*mOE?JU6u7Iw-mr6fuBp|qFT*l$Y{ zr?M0|#>3Ab@Qd7NT6keWal;y{Y>So6S$B>74E{KK`AP^(uz@uHAH7+#9ASK_t(pij zQgkm!A8Z~wYB*MO`y$KJ&_Q019a*1zZ6m(kMHr93KC7$DYw#3lfU-II>8y{*e zG+e|5Hz*ip<-qtI*f5&ohpdPBtv>(Q7QwFcITS+f3+>xRX5Zio!RJ-Ff3_CNF5ir{ zu5l=+s2$o4Me9%qfg8{$&yY<8V+hNvLhkz24z);)!>rOk>)7!V+&7``d5QmW%~Z5YCn_R23z8|ps`3V=TZL6o}+$8v(Ix^vz> z8+xGmturQDounObPkiQ>(;+8vAm@TaLvADM=K|CBrx_8oN=APdy}APWYfMJgOO#7G zSmhvNq-jN~*}182@r03ohPjBN0!NvJ#}i?rxEh;OD+%kX97-hXK7fn--*7SK8;Gfv zK}0o;PU}{WxSLj+lKxjosz2py87n18*A86zx(n10Cw)TlCgPwhr$9;Hnw^Sbi?ao< zE6TP(gH~-Nje~Sbf?n1#gKr6y<^GVu`I!0yy74;)sXt2*y?<)vN2LypL;ihYeR>IO za$=aCq``dmIM6m2)%O#_Kf@IFFWD7EBMlb0D77n!sV|Cl@==St&rE5i5hW;fBMCWc z>cM--dE_$OHCMbCVR1kpb|kv+z*wHvC{58MgnRC&=ZBtSR6*=sQxVg;gN25Mx3`~k zTJOH+FY$^}{0kxaB+O#}9=V5|4dJEmW1IfC>_3=3-@eG{V(VIGq!Bx!jJbFaSEm17 z<7THXEK7UJGcrc(qtqGSQE`$>Jh0}{mM}OJ_AS`w>Orwru#0O636+m)vlNJL{Q zBKzQQ_bQ+2561G-A5GK2@!P~$CqGbWTKXJHAtp+j2808w12Y5^`kdXg=-&L#!MOa&RS!a^6frcrC!$F^#aUG2mOQ{E3 zm}I0tdkR7xX5mT=fzEhd7gXDE%WD*l!isiv4^`!g(>eg ziL%=tID^_)(AgbFN#b8%yPl1t6cDQ!r_F{P7axmKqMs98eFJy4j3f9?b9deA^X1 zFU9JE>>cnzk~x0UxXZ4dJd97>M}ObM?bHkZ$vRYc5~8B(pi3j)X0i%6-sw5aExZ>&n>0+p-Qv0%Px!!+T=yr4|D!X>qGF{4i1mr`W#vux+VeRWAXaJ zG)ZYmTiAbS?@r6X_aA5F%lOBB#cqj*?9}fnKXb`y` zY-1}QnBfcZv%DEvFx^<|FBKy(r>F`qGw?7A!5z4*n)EA}>K`OU+#4f{8o_>FBWKDO(lmC3QEJpY3Z z{Vfr3_;Z9Q+XonyvIY(x!Z^fhE5<#D^?0McQk@Z}h;UPejHrr#GQ1)cIOqZC%-o6< zGOhn!YOofGfT7dzyy3txVu;Ruhvv`r`W3(d;VyjF#%8!G7XjXjSrx!iPP&raa@W{B zM%ZL!=4=kW&GjOg3oMB^xbsfH?oKLH;4x<#AnZ)I@Ydf7RH4>8E`(ne@~D$^sUHNr zQr^=UTKe-#9M#YKwJnu*nao<{vVn`%~oi}ss_`X0UJloSh-g5hNjo?Qg-vN zEGg|T?#J7FHkECi(|PB}aUj%hihx#eKZsct*>Q6&UW+#zd(^by?qfun>uex(+!JixQ)#pS*P;;*~Wm7s+Z*SgN~M#vBj#cs<5Uvt3I7p6tO+n%o4csb1{&232fW=EI`rHRQkMkrA-pH+U2v?)*^0p48y%qpl%xB) zy1DPCt_Hk*Jb+9RtRIgGxt1Ra->L^Vv-n<;xZvrK7@a4UQ`CSQV+lHL?*NUy!0j}0 z2P;m}W)ZozXY$U-W*J!rsbrlZvo*-~t#yl5)h3G@igcQqd4nT)Xi+cD9}wRI`JZ=9 z(G0+0fpFh!aeyVYMbnqlTiB?X$j6U2S@sB%>8GM}Q?R{h4I)#n$18Ieq>+9C`8;`e z4LOo)aH3I2)}{j-x^LH2IlXVY(7jxNh#I- za%UHSW1%^L*Ov71gxUf%EvU5Q=LRn`&NWmV(D=_h4EWT3 zrZnCZGJ{vA59AXMGP3u56H7L=VW>!o`-!F&!n)HJMN`VFMDU}^Oa-sVt^P*R6#SbCTgi^X9?%tRx!w1vEmw*bhz0Gpi zYFOLr-`+gsXQnD~MbwwdF+oWuiFo+9J=s zRy{-OgRLh70nX3F^1U(qTrv4H z#u-}(t6VobSZi6xopsfOZ>|d_T8;M6gw2DBQ3i;B@fpaJG(yZ67M`~{oPN&9G)DzC z2LmaJ3vp{?`Jtkt({_Jo|2gnxTRj)V^_y^^hvsevN!|%2rhV;xg&`sI34E8inXec) z=$`9SsFp*1DpXpF!?7=IHZ0rQmq-9bCrtw9fT6h$OX>EW_eh$Ug$HS41aSD>qR-n&eOj zPnMMH24A#{bEqtgX!%p6G2)9RD^LWR@$%A_ihDml#sds~sC52fFSgQa#QvuJ2OoL! zCk1-wlTI+eAs|`+#RI_&WNj7Y5s3YFyM%(d)z4mtrw!l~RXlDJ|CTCH%jieB2aLA4 zMVZJftfSAm&}k?RB;izF{=*v^&fp=IjTe8D+~r4dh}`qZsdugCbfRww-BiYvCmKA- zDm@~~by=X))CoST8e98@DT}k*y;biwweNzQ4q_aOU{6|(<5@<~Q@^;n9+i%Z{q9Vg zkV<#G$6~Ane1CW?t!uQ=p$TR}Mc5Uu2g$lk&TlG%u4+n%4BX~p64EYvStATb)2hwu zjBf{Zq8K`sybJ@Iii}Mi$hu)smaQ%EWhqAFC3GCB)RyVlUsq}F>;P5t4a@Yljc&D=A(N8RWH9|X)n6+cQ95D9fbK-#l9m?%H@(vV zH-j@&>U(pioOctnTM0-{pohH*Yuz;Ye%SEkX_QP)sv7Lm+;)Vk#=~tZu4iY^(${PT z%&%H#Rf3N&q!FGmpLJX~Fcn0M=97O!t|1q5fwLagTU))dd7R_<$p}pJyV+Ec;Bu@; zy3u;LP*$UoIm7DDaT6h#q$?S`a1XdB?-yip<#a#pX>x-_*(ucSGf8zA2qQm*Ed(vH z4xsC>YDn4OSHAbF&-Twu=2&d}?*6eyIJpfWh^g}^|GmbY`}m2Q7OUn2P&8WY z+?Dar>UlB$xmiQ!ACb!}Mo`0q;9_tM;>GT;Ju`^@e1+Ea`mo(8#&Ac?n3TfvZ+e0^ z6$b8tc&?VnDr6(zqYcWN0Z2W%6QY{wF7%#@5@wv+$=^P!FO^SnSV-<);+gLeId?;bWTJ^68lP8A7ly^SN(8H9HX*lxX@dvLNR0GTs&s> z!KwL8{UbU)a3GTpz(Sb+p_O9sU!a$IQ65KhC$2oqaW89)bT1wd@L3$|fKeLA@5}50 zZ~rE5PM%E7G@SD?W8v++e5Q`&DEoE8oqdQ#Bnfs3nQ~lVNR@_TrGl4L)O6>B&kq6H zMUX!(OV#>33ty7c)v#hQqHAj03&9+;2NiE^t2_v)0WWu&m*c$-Bpr-Sq1J!as`nCo zD1Id8Jo`&hjreLH$bzV!18D0&+%8m8xDX~pD3~iW*Nr4D{sicqgOc#Qf%%PEzhx}N z!gqVvMY-QTgvV(8xN|?Q0ymeug=Z4;YoN-A5Ai$9U%F(vDJw3IbezU0^EnsYhL{Xi2o}=8<<&quE;EtAAyh3Stn%VbO+#$?DN6$-^+i zb+qNfNLOkYH*s7QMNWEA#UV?Aj#02FRf8k^dHWt$ZMJy3;LqD{Vho*(e=(^hWGIK* zENp9kNm>ZyY94UB(F{5K8Q#q>@2ZC)B-^gFaw9Ik?IGx1c9mW9TpJ7KiNoEd{`Cb; z8bdHB@kb}%c)9R5J2;U3AA76{oH@hpXAHgu47T~ZZ0s8R@jFrxmZ;?V&@4@l2gTxs zM;_Sk7ktf_K_~?2>OsMYOXr&_=TE|Vp4K!5ctdGLVg^6ok3@Xw^DpZ)Mb5wNwVtC} z;K!o+*!eTW#XjRi%CbF0Dupj=P+Iz0@8cFGgC@Vt0NMe-ZWZ1B(E(&z+h!(l94?6W zc81mcF#Mjv#yU`yP>;^ML+Rh{#7DQrGmu2(_T5pa6X%KiP?+=Vknk0bM5-*C^Hqe8 zz6-<0;GcwordTSAI=6C5gQRrb;~{d|8Qfeoo}L93h@sl9_7p>%arm<-b>ZI!g11?$ zqio4tZbxBvngc@blklyPJ}twKTVZrdP)P`nL+kzz87d5kQEcqAPOv)Cl7{xz!Jhpn*}5wCIMNc3uY)>>e`V(n<`>F zA?CArr)Kx}bk6nf5=1N}5w-8_{km_MCXq)U`(K+|n806~o8&zFTLVQb{Ia;aCFd}?^>g6zUcQdH zm~Oir_cRXe3^%L14<-pe&6z)8+Bjvq@ApfTLHhwsI0r!%C+6!9deRgUVuel6dEJzf zMcJQ`4x6q^;?sWil0Sp*g$$;GND1jA0wCVCy1MEo>R%q$=o*qol#{p^cTs1u|>ZfAxmq*@$kWtRy?E}y?Whit4*$t_dRj0 zZd#(Y?dQnXMfrn{+eq#&%!8&6(eq;u^Y7nXYIJ#>Mi0Fm)N(fV1a)O6#-u1cP7PDz zF%Nz|{Yaw&{!HxTN2p0qy48k(88>$AC}f(IJt_b0Im0cL#Feko^(^%c+t0lBjO>df z>tE&ly)F|&iFVVK#eccKucn_*>|3u@S+2So?!!fdR@yh14Kov%D`Gm~tQ}Pb2EHDL zW0o+(DMzYej7XKq(kQX8@X?Rk{)nR`zGo`9t~ab(Ybhw1(bMAMtYn~}n`cR>#B+S} zLs9BuG@E$=il1tQ*Ez->BgL;(^JRiePo!CATs$9Ea(UkG59hmz1%`*;lJT5r(Q}=X zh%|%$=>W3O`F)ClZ9#ZaCi%+*3%=wEYx_Juus(;u%mVLn zk|eW#kcjY0YkKf*wXWG6O@T!75Zfr`Qe+TPY^Mef&8olp>JPBVPe;;K%NU$?cP_Ox zE4Q9mlmRTNI33U-WbgJKxjUTFP||{&hq<(%9AOi0c?l_z%#S13bl3`>tRJu$t(&Zv zKj6&>?=N3TQd0PhY>)8b57Ym9)Z#mZq*524dqSoIa5pd}JEa5s;(LA@I(Tc8J!D+o zM(suHyk6X%lxvFl`dMj8!{1CHE}78!8ur8`$1BUd)4H0N4P^tkrR;x^JwQvQHtQ-t zE#a{3Y?)$&g{t)Xa(Hj27%!(iNGTGvEsrM!*6h!)p0`~{-f_P`dLm7Ta)jkWyHM_t zs*xzSdszS27Cfe6n-e)>n>w-SRKR>t@v!R^*_V!#iJ*2AZ4MMS1(@hx00WAn)J)oJ zq@U!QMgBt0@%@`6&&LW)ZW-&_5^&9r+A{;;<3=eTdY-VfcW1fOS~*oGEKNn_+~stT zji7q9d@Rxb(ApzrWbS_^m4xFF$B>AHE|MqWce^o4srmtTRCRImBeu&Bj#2VgEliP> z1Cm~Y79{{pry#Eo9t+BIP^M@VlXo)<$@xZ&X8}&dW zf^sg9TLIo&PKWcTVh{3nWzlF#T1Dl;->sdiz&Vf|_gi7P{u@O&+H|R3#KqXK_Trx7 zaq;tW1}TngnQL1OYHFsHc5=H{ehR!LLhRSnN*lb$Q&`-!#pllb%_>*=Sfj5c-*G6K zx};fuzTvW?{!E#$`M!5X)knDi^Nj_70>HB*4I?0v>TiT{2s91m`KxRn{#rX#3FyVg z?eKn|y|$iUV z*VqejKM@c9L46X@!*p#6gR;^#48 zoVCDt!62HI@QSo8snLiMomYAKtm;(10#UZG|E|I}QBmkQ{fB46kVBfl%zzpMkt+Oo zbFE^}hTqFA#C`Qc?@vSqaZ=>Cc=c*=p6jKId%^U> z@BhJOKL`-_>4U?$;*$r791eU@9Ni6-iawuaY4#{DluMV-U-o!dR11LoJod@aABGXR zfarb0;qGx_HEy<|lGtFP&ELs~BzZx5M68IxWqf|X?uUMEs7WT9CWi2;B4T(iw#Nc? zw`IJ*+}!g-PFX(92Y#0|PBQmmPw|8Tzc)4a)#UgN?xokmh&JOD0H!LW`*R}O>q2WQ z3V9~&eH-o)mz+;W2+)T;)`V7%iK2AtX3puZq0D}}aF0n*=laqrzj#Q}B8X)j9A_ut9X+*`8Adqri2orRy4FF~_=R~4S@Kl* zb=@B5BdP|iZd#Dha>WGC&iw0VJ76p_u0rwjy-VSIT+KxYFYv*L4;P;ZX)(^u7qvKs z9jSBQ*u>}o`CY%qYVco91an0SpcUlhm%+4@Acsu+0q5lZ+imsuI)BY3J<2yt-yi8H zODK=-(@0PxwxaYsKrG$#4_n1U^C~dqYrIl#351Jd+o!?F4_}^j=t6b1A7CnLIu$)E zYWk{Q_XnTvr4Zbn$JD&FZvCLByG){$!lm^}Hq{ehRjV(^Mz!1Yu2vHVuS7lTA5||1 z7_oShEp0CuoaB;OrM7hQJVp zfvp_sJpb~DJa+5!GtXMbZv`@aua`gS(DIahF1wPNm_QL%$mm|TCG0bEi+TDzAfj)$ z5JP~gdBa2^_fXqau$^BBcILTpiBWO;GZ4_j5nnR~8y!nz#`gVI>s09FdfQMKTRPK>H8z21gh6Sqv-b!NbzcaffAhZ z{N0=9@Hh zUzNZ@D^=^ws=o&fuW)QMK0~Dy^rG}mUE!1EnEQBef`VEg!ML=wSJjwH!%9C-?I@!v z(F2?-q+GJ)M=0^<(tk?-Vkt)}BO?sy2GaVa?6|(9iRH|A6^R8u&t{+#fQIVJ8fR&p zd0#dS8ZOth{fB1Xzx80r81e#aLs1nlA9Q6bC95>p%lSJmkjJL%gLDyp#inr0<7ZN< z10zyKIWX%`coaG7ztj{U`3U!93o$Y}d70B)=>6#?8ChL{$%ydKH^K_4?x--yJaPN- zguMw1q5b@gb9hc>P|urV3qyzs(?3~wUGG(;OW`sDamjX0Be^+Y1CE4+7T3_4Zip+I zPla3=on)7@U5RSXp8{4k>3gemrCTsRzK=58)ce#ogKwB^kZw^WAuQ3~t6a=h7e9IL zp&d32A0NrV?>9!&-=TJuv+elSBs1xxIk&pv$3*w}@nz8gH)*|N!zA0gx{Is}9kQ3YWe!CFKwI%M_hoB|^C(@(j-KQhMI1Mc{h(Knaajn17>->n%58{H*VLnVL-(_WV}a zNdU`PP*pC4n}u9cLAD3O4cIlLj0e3o%PvlIKVh43p<^q$_qCr%dHbz?cjXV8-S^2* z0h0#AXsj!+{%uId+`RBH4{AI9I)inurMw6Y1tTfh`Wn zT6^(jPMup-@gTfs?|8xaBWz7!LdGa|W*3;Z5hMHPn*nFD2Qk-;r5K z;p-uchR8_vxKOBcAkY~KKO)KxE*Xy?861afiCpFm$)z+4b!Upgml7bqF3$>!eyi@;PhS<*ioJrUVHsPnC#va*9Ept;*vY#kG2GhN zCbwIf>k#60g2#U0o1g4b6|mWl0t)UsOr3CdVfEtf#k%!%lsw8EVR7T0>)SnAe3E+d z%og3YD`MrFyySd3YcOpaB3H&Rr1#@}ME1)O5angaHxAl((sWi<<+b3he|9W_`zenW zs4r{kaH1{0lX=+P(5^O|xL2nqbSMBPL*)D*DUg7?;Jb+neQ0-ukUF?rQ*cd|G9wkM-D zxXFCAyyx;c+o_2Ra!#noxI}26cDI-C2L_s7GbJ0m7S1K(V$7T;aH=DdxUs2h{3?y9 zrP9GRj6YJ(SNnoM8TcmcVHr?F^g)oL#(XQj%RMWX`Lo)EeFo)#9npe8C>ATYSj?()3*yurcX zKQyD{@^FeEbC#{0Lm^{=<`0v13Loi2@1LNd8>!#WkmvI$LTw3-{5*Xhw{;xGN-Ygm zTdps&IE~b{|M@BOr*U*g2?>DOda-YJsx>N0d8xHQ0T@Bq0Ysa<*yybNm;63%qYiAk zx_3Tj?mwSvv+%EqN8whQ4_p7+V`-1(e29zmB3bRi1N(;cmeUkfpeSMDxC7l_*lT6- zR~=UkujLiX#Avcby|6;o11t&EOV9c1*@I-B&AYD!i+qX~c+VVN!6H4-EV%fpT%AAx zZLTJOBF!)r{N3OT8{KSB^LC4ADD|@g0oN*a+vE0&4+9hq8>IQY0oyW_KA29=3eN}4 z$iI0d_c;iB4hY%(T4e`?#{wbsbzwpLDFexC4mygrmO4{3R@Doy%g%O;$EQR-K;4F|`PGvcOp$_#y4!4`Zgkf%;Mt`?*cN+jI5n`xe zbb2Bm7wHGI2_%Tf09!R{p)xK=`eh^~~l=*9Yqk^WW)P4DJzxv!OyQbdV{zlZry4nU+zUa^LP4 zkO9HFhJCaX?JLNXRPpBH*sN&%`O${pmhULuIKqP89p#VEo?loJ&pT+rSEfr#3d(YY zjpBv<44E&u@03PB5VnU;v|RP#(29*?pXBA#H90Bsze%k+Jx30&3^8rqVSLCu1b%#> z2g=FeA)>MxA*-ITHQM0CpJTDKp>{C9!-Hh^3o2|fTk-vOfb(a*nbd*}VYj2MIF+#} zlQTS5V6qrv5)ewxNNk1OSQZ5>ZJO`xunaDkj{Jm*G#{xrS|1!jFkbN6G zdrUc?(HD;PhVBeMsCtVvs>SRrFwZCi<&iZUROC0DP@5(5Z-{9ojB$uEd4}V)6K30_ zd%rpei?(cAm#Q$PTc*fl-dj#>Z^YSJb}8xk%tuGdcQEQ)|54MmZYm_^hcjIPvrF3L zQbz_mXqu0+9KXwWn5>caP1C|ll4^c|HKzt%B17!XMZQ}_|i2qvyI<{A43l`++cZb zj2)MaAp7%=47k$6gOgYG`we>*`wfQ)#SMOkD0kT@&HYKab(7WO3}dhoE$Q8{oI|(! zGxVC8S0MXT_x+aG53kl#8iIrr!Jqv(q>lwOZ}(0ef&7wh|TdHfU+ zvF%m&Z3(4c?3%JcULk*FL7T4~}O-V{U#RbB`6IiY^eln*jMo?mGf;d2jELM$klaU8`?QhAt-%u;Smi`De z5N_Salwo;_IsbTR+c@3-L++*zrdAJO1=95ZCqS1A2%!4r=?20_o~+<;1ojl#YwhJP zSnE+`I&k|sKNezQ9acVS_Kx`Wo#DO@nZKafkPK1gB!P$yWHbL|x8i=)I{iB@MQu9bc?lK(5;+JlR>uch1@ZW~PLisu#((Y3n8Dt`A8^85 z`{2-w{|^TG++YT$z*WD3;y?t&*MbfkCe2)@P?nX)_?kKe2Y){lS!l}>e{2rLp3VHt zuDl|>75+YWrjBhUhzgOkpe=K^{_9BDm0WqC+S^;VLu`i3XN?5?lo}oy{CPn<9T6^+ z<;m6+`@SfYZW^-~CvKgY!T;=NtEF;V;?a&uRzvr;7Cw*im{K=UdO~+CTa~R^{~0Q_ zME9{x@!$I$S$#W5Gx?nlznG27Z*fUZ*JubwU>(Bjz*X?{e|BtnH94qLc_^1ePj43G z+tY919BzG)GzziDAy@7Vtmmm4QO~%*4~NLz!oB-!&uKA~JlKD5AW7CUliDbXM43t7 zaD^dv2ai~INAO?mGIOkT7hYImDh_f7`5#&@vM*&>4Q91|)Tu|3;f>d{uE}$Rqmf*6 z#MVXmU|ZomPeCWX$trN}{RLd>@I3aX5ElR}1OCWi+73B;_KUgNJw;4;mFxsA5k2lw zysxn=ZthwLkY28OA4?|2&>naym}oDy(x~A{^doo6{%;FuI~UnEdQ42xcG<7n&lUEM z)a=g*_QgC!KI9xbF~(78%KexD9g;x~>Acvcg@S!4Rh6J^32Xt@FLOOaKQMH)c8*RY zHWznXYj1YxW*B%o4GBNL#6mZ>Q=$Y%F*`e<7W%gRVU>V zO4XB?AX6t@3CPT0mygE<)+f2#3SEG3R?q!kFh{$v zRE1k6VX%~+4oFu$VeWkH#V)(y*cQe!M+3U9mp2tQgY^NKt6Lcl8)?+3UykAhHhRjS zS#3+p{&lUj>TgRWYW)kcX&QuQQdOQgnvU!|tz5dPL3|~qD{e2xxDdlfH`NuuT%xd5 z_*T_$pmANDfq-I;d64V{o=ib8I+{U)*JLoS6Q3X)ujsGqduYZ{ zEA`GgF)Vrp$&TgZcbE8;l(SzrYfslC2ok8&y6^x2s9T9m_3y11o0xmIGTl%x{^Sq^ z*0KiUH+;sFIixoF{y)&6@oeFGm{N5LyNBWWgnAzgt{8xL=Z?Xt(u?{(Br+z}19RUJ zGu8B2)8Dzu5Z|BQSfw*#1=AWAg!Mi(=|{!vg&8jxe524epdHZC9d`ZQQ9~<8t9Q9T zojG048XxXJ)q-&s@NsQVqRC)CHX8Fu;0|G<^7_t7={8>A*FU??kQYV8bW#dW-lxgp z*~30Hr(5aC;9k8YkPv^q&1$~T#OtHN;yq>_}WA$YVz7Fhquj8j^9EiNh-a)#NVd0E>V2$FkXg7oKT2s#sD`rMZYcD7DnSn)w zXlP;UQqfLT)E>_jrq-L{)8$9(aXN#U<}@P-zdnX!jr;)g?VFukspt~x6Vase1=7{9 zMu~(EjQH$xJdAoTB1U^yc5nWg=tz%{dURmb_|LClaWo{z+hT=0|B8+bHk?}>CC{R3 z#njqW-Z3ShKM}y?@F~aQ=6X});H0RMkbkXSD;MNkCiXHZ*tcfWa(U;eNROzMz^#q- zyClQE=wrYdfQ6C;6|hsMGO2BrFjVHO;=8L7MZ;pwEtHJ{eurC&?hY7oLwC?uSb4GUsl$j?o+wWr-nWpQ{F56>LQO8wi=q;xd7ypC@Lv zbh&b=)`Od6U;o=WnX03w{PUy5s~Xg*o819Z%#G!tv%o+F_$jKuV4ph+3ah09>Zk6L zEy~M$o^3i>@;K@=@D_uM@n+S0uWVlQr5Z0W4w#&T_1Spa?G2UXBZHt6`8=wte@xUk zzoPvV&n$;b5970THA=C5FfJ5lZE;fg4-MzkJnUJEsk2$6`r{{kky*Q!CjAZ+FK?zt zsK>X&5kS(7OD;l0%+N1WgQGhBorU zUndjyOB`eGEHVx+zu@yc+dEe(h_%{*ZOf?S;a=gvBESX&f=L~vkn;)K;=8uq zpBB{DBaFy&JJLiRm1+JZM@&?d3W(q^jkgZb(XpitnT7sLk!Z(6p9u(TZX41k4mBJY z*Qx9uW+0LI(yfApNm+$$x%)L-_3MYe4`{ci>b>UwNTddu8mc+`|K-!dM( zRyKQ|PH(IldZ6@m=fLVe!XtH*_DzljR6p3eFUBX!Wc8U3`UwPE^Lawlo(2b}pU$W& zAniJrbVZt`flj|5ypUFj{ac~Q`157$kPS8IUM zS@`!=Zk=`_|E3JAuCTFIv$hILyQQducOwUl1HR&$0H3Yg)KGo@-Q{8r3$kB|@I=W( zL`f|0N6Bn%ve#;|_67nB^hqofIEZM$M5b!j@|7*HzxefuPa6v0tdM4EvJ(lfe`ANf znW-gne-8osE7=1;i}HOVNc1E_(q|4B%pW#PtJYafJp}j_Y_zo6fGvN5cWzeRb@F5= zyd0MyNhjzl_RxDlDY-0+CMxcT@^J8;2WA+zY_I2p9XZ4!@={rw+H_`sW1W;@z7)}8l82D~hIkw_N{`%8+(AHS4dhjumTU9>*k^XKc6Jdiiw72V*pO8K7a zjh%jhqSOSIyo2Lhfk@@~`=~LxkROXsb@FIzhrK?a`Q>-4)ui3%XLltjF#{`wV^h(e zCZF*ImD9Y&s9V60%RGQ0_est&L^qR5$2})4gMz*<+6v&hFRjyCn)mS#A1O~xL7gm@ zy?t*pu*(dCt-zZmZ8Pjp*0Xch?K!KKSly1LqC~BTWA^aQ4O&ha<%#Fd3O9m}4sr+I z_H^mKY5)O!O>JvW8xo2HqB&N|QXb~zeL3G)iIg2JWO}Wghjpx`RoDaa*|-0Lb(jb) z8Gt0lDJ+G=x?r1$xl!V4gx-S#)H1}5V|?9N)5^UE`#vP&e{!;gLiokGAbF4A9BOlu zWWnXe#P<2FYxCKz=?x zrB-a~t6eLQfkT(-H*LE6iu3pU^7F*V>zVo%D2?N5cHVw#Oz(B6suxhhL`&G@Py*c> zH1{taE0~#w*vP%|Q^lI2PO9o)7yj5fgM+``H}&*i{k9GW3M*NTtM$*wJTP?8o$rWI$j;8td&($Y_uQWse6J)LKt1*JiZstaCmAx`qrEj5 z9NZD1lQOt3a{N}`zuiERZS64av+{fFUq38v0?mQmK$zUJ(sZ)q#6Rep+iA1;hN7Eq zXv#Y4#57q`{WgpA6CaT|B!J7$*fSPaeN!m7<$~|#$?mPHO>$Ca8|^U z<{qkwO{(mmAFsAhIkh%Nb0kYeFo#<@r=fSaM(Gy6ui%ZpIOml!83f4oj0&v;$^W6T z-~5NhKlQ^x+7?1y(m7&9w;jt|)g^467iqd;L-UseK*4tYl4NMcmX&f<6gCeMJDz2yGY@$}fxDG3Gyw^j%as|A!XA+F8yvpi>Go(9;#HrBa1xRcJS$WfJ2H z3wOhpL>f>xlyJ@Bvyw2|VnpF_ObyR1tBpj!Z3Sz~xk7`+)-s7sT5W-oWj05fnPWPFv)>Iqev1`%$4POLATedXwb6 z*L7VlN5<~H{oY#f?_gfFrct1)V`!t zml+!$U@eH;Zs^?i4<3%d@cQARF+UF2e!iUm!BYU{@oFM+kEyca*grV`e{^mxlP3$g zxw>!?dW!Kk~iGE3#;Wzz@nf z4yVOOq=*}vsBZTbC%{kE>n4%RHv$<=|Ic8}s^P!oM{=N`Gc$0bKKiu*IXy3rIzzlA zo;?|z1fSIkG5I2(@gwsI@y;V!qB51OQs##bc3O@sq;)9R1kS(kfPl+?mey+IiL}df zI^}aA8Yq!x`h>TqA=nH3$*=xH!`BRk2Fr`f*=vk>t^Uj}fHxV4_cyxw0f{$X$6*Am$ z8WZJw%z0*J!zTud1J@UFX*5A-G0SW0DqmB;tVWt|d>3Bb^gF45_y3aad~v{jEl&U# zdY)T*S6y;{@S{r+b>oS7oF^uwQRws8@(=#56_JteO>gskeV};0dzRT2~zsqju zKRDF|Tuj@V&wbn&D)KrSE|NafaxIVL}{S8Q@yEhFd3t69=)xBjitc))h1V zskFi{!HMH0w@}QCZ>mgnr>&E&VBN^L008<<4|JPiz6UqtHA3V?pO64rFv4{#Ma=eeBo z>)sr!P>1oWk(JAOGY}cyjG|dP`99Ya0>V)wgLNGX;i(1At}I6=Thh19iX6A71_*y@ zrp-FPdQ*nNr4cq68WE z#p>(vZ_!(jAGaNwpmg92(LsYu(Ia?Hsu74%cZR~4-^Ooz1SBhNFWi|x@la!w{R0Sc zB7X$*&^gq(Tz0Ta;6#(??yB~S5c6}PYkcS$Fdb?wwieKX@SvrW&t+*48KB>vKdj)P zEFdR=cqmJK!}Eg$GuLnPvg``(QlE3f^-wd`Iug}cNa?Y1`Gxwj2Da*dG1bpxml>6U zs)3Fm+4^vctG5o3y$|6+6zaqrs&qHcxwedK>;{}@WAG-aIjr%Nqfbl{OLgrZj`l4t zd?kHgR+#NxsYeAK7v=)_(c+I4eqesX=f&(9Z{KKie)Fy)zLx!!KfrmI(mdnx`MCv+ zChHSEH&23SODxK5Z44mgQH386usM)115A+k&BpdS|AXjH=WZUhL`{ZNLJr008W)Sj z0uom{QSpDUgP~#nE;LFRll;#AU1-4orS4+p-bH&A;5)B7x(ZC{`RimJ9!=YFPJl*3 zWtr7L#6AjIDJnu?gPlYXwVJKwrEmEIHWchSQ5(d5qM+I%`tH2kk8-b7S3mBD-iu!+ zX&~tdjLAQX61y;67*_XxXw_ij!a|pW83SyJo8+M&*5L08iRZXz)PPzmOI$gPM&JCuW z2v*B$?_k4VHOLgpG$OMK;i`=sShN5Dip))0Gx@q(Lu-Yf);6V4wx6t}8D-tktI#ny z0P$X$F?|le^^-jX(o?6~|3hPHQOCA`GZbd||H)Kr>iijQC&=RulO|H?em!hNoPgC3bnNoLQMlzW{?fHX@vjQo$9N$ZOn0{J zY{Qm{z*Tqqy3$Pml|>8~iT~Iu|ocu-81lD`HIFnQ!cVm1e0pOtXvHup_~U zRCt)t;8R~am)gr#7Gs;r1g(Ri_oduQM~^}%_jc5mM3^Ql5tgZq9Dy;FexE)_Gtr-W zbEyq}`j{cVOD?6S9mKmK1$Zuf!b#`l#k#uR2Qo{{;-_;0$M->q5lRD1wl#!_qPoEe zE@^^EZlXSBEQQN(yiB7Nma=Q)7N48t&cXKnlvKyXc;F)f3tHb|+w3!(U2Sc3nBSMESgZyr@c&`zEgRZsyKqso6p9xs6nA$h z4yCwTfMCU1T#LKAyF+n@7I%uf1u0r2xF%R2@SME+eAxRJWM(q=nzhztIl5u{j5h1d zwWu_IGh4-;Jw7CY*-G&e)2ZK{wCluHq3N*tpi2jYoIoB%v=b1v-dYf$wpYt}LRJPk zU94ql?65diq_Eqt3}vMAEzFgx8vi0#_hHb?mW3Xas=(6Tu>vUnK)8;PAgyyU5XxnY zZg3@6UBUo1C5!V)7`}~*i$YTjWMbZH_=i`C&eOt^nogjrn@gZ}65&Yro4N&$P%Tj5 z$s$gjlk<|1D4v(IZ|g?)X?qm1_Wq=hK@;RDxfU84mac&F;WQ1k$x@?x%%O>g)#B9M zsPQcqQ!Hbxi;@XG=<2!}X_Z{Yug(mb`X5pr;ECOK-7JS|Z_)hrJiMrjpPBJd5149I4oE`>rB9ELtRlR4DnidhBbBzUNPH*r5|r$;K}CI|hIBs@O;4O%~SqrE*v_ z-OmpzQtyF)GBdB&&1wRyO8GmncAuIhKu&(ve>i!g->fxeovY_LD;=BVc%c?EH^Hn1 zzUkFxr#8|uXeEv8`R#@00hh9LZx6K5nlld!9Q3*!Q)sifHRprGdUnAxe3U3ti$;Fl z7OmJlA*p0-dfx#xv7RO|n^zf+GATI{n!aO)rnQGbJho$}ng#|GwFZan?YV};Yo8vI z_&<-ft|3YK7&kAma4Tmd8GI2z{vdeB%Rray)S>yWv<@J*3K?%{?$WOk3WQ_!h9ynC?f|5OsC!l03 z&0If=P=oMc`2l=eP$FWWO2+C@#ZN5`wI9X`6&H1cPUv8g=vNrbRiBCmw6;NkTSJI6 z$jsY1gnRv(2QB^$m6UjVX)~1~VdYGqGyJ+^S^VWtLj=aPVpPO++P*a9NW4!*y_mjI zxg_Q$Xu;-tz-u8+x1r|Y<5cs|XALD@&10*J;(8VlTl9FJxzR_G_r zoczX(1<{uyQzxp0=HC>Dl7-tDl#;p$3m)UL+ep#C+JW%qzV6;%&54k8$R<#=VLCs< z#9BMCyA}llVX?qx*|xx$Lz*uoVhv?@QhkbyyOUdLFwY-v=Tki=)I2B6MoHg@scO*M zO`au0zVo=R{ivU%?-|3ut1(fW8mvJ$?!(O}Xev!EC>h^HTOpVJxljiro>I4MN1lIg z>e&u5&r@l_&kTk9P3MR;R2XDb;bDj%qM$Mo?D|sZ{ppQi+rJH5rixw!<(fffIL~lh zjh6*Z9J2qp%t6jR#1O5EaD#7jl|V%g5GbaZa_@CLIHJ^&2-UEet0^XCu965eq-A0# zTP$V@4K47&^Ur?UY9e_k_O7bo=pEgc-B{rZSJ;K}d`QgO_F~)Iv6F;vi+&#a>^%fc znqg_WD4&s#zE{e$x-l4-k7yJi_6uScJ&i|ZJU+GROLty{D$nERW}pOyc702#V`NiZ zY}}*09rk!3r(~rd-XI|+D08|~PlRRpnX=%!TEBAAB!jGZ3zKE($DA%e3rdGK*??Ai zs!dz!$;vh6o`xQo(#d#!TD|wD%gPd}4>sB}7d`ujob+GvCZ7QHk_E+W6}d}5S?+h< zSDLPdS{i?8wB(;JR*{q6?r#4@Ox{OQhn%DN0um}Sq`z#NuRS8=LSr?Tv5HiZtU3Ka#$`hUs0IgV98cNr(EG z9-8y8%Bk8)@kA`sW4<0qgnLi6VcZDK{XrDGj!yeyY`$ug=7M?ww&+OsNwp2B^T~#t z3q8j-X*Tl=_3P<3heD^43>@8u>f$}du$IX;tSYRs%2c0&U$!7C>!IZ7l=A{WOCF8*!XsMj*Hp|N+8D}vRa1_e zwfg6eUKg zhgSEBTSH3UM7`K~h{XD~8?;CrY~Bld0uyV&wcfYSA`KU$r>@=Ow1w!gpD{XOmZJlr89W4^c#YH!I~g$3tfb$fmTWZc z2iKSL&2bEfkCtZc+aUm-v)vGynoYhB-kL<`811T7B20|3e@ohIqzS^eioYi^v(4>`Fs*z=UY1j8?4?DzGtPHtX+>0!KWCrDwD)EKRUU)*f31LOh z+YtAX@vwilS9S2@C-X~A9ok{Uk6o*c zLoa-cfNFuNwUw|$w$697=yD&ts0VU)k#%P<_geN%TL$#5sG$hR7?-azEvma=RYO7Oi%%3ul}M&VN#^-V!Fj-0^{DL;Z# z#`|n~mjCx<{11uK&_JQ#gdi~K_p(*&xky_ovDRnW19F9P8{wI758hE>A>;S4?!x2D zk~Z*ZM6S(4`?7fdD;G#S>rLy=E}B%4(C-`=)=Jsf-?%jV&&Hed(%aZ%CX&|ESyT3OpCSGS+)Y zIo01o!A#+r1{yEJ(FK!Tz~(E|&-CuP|C*!u}* zo}^CMmAVsWIAqQHYLzxk9gjONP&}&kGzmdVQe%gbzPd3_0@k_Og)+d5kan?J+X~#w z_2kz2Y5P-tlo<){WTldy3!d-iV=OjuUgy>mj4fFnFviRZ`k^VW?$9^g4L*Lr)Y-!s zuEGT;t6vFR742;q!%Fla?f72h>^uD3vaE&5mo|%*_=$7*{i9ti_g+By7EDKv6M+aC z4ejPnsgm3vt@QWmEjv7eKfy%%h(IrPQ~2sC#q6thChJ{gBnx9ES-7$`(Z39>R$I`+ zgw^;rho-T3OJXXG4ymIZU!Uc%!DCv0hWF|sPhJ23*l~F zOyiS6Z+M{L;Gs1li}|t|?AL6K(>rq>D#M7Saz>ei^5HEJiyi-a0gMk1o%zmy#s84R z5u02~rVRj8ZDTTh4|oc6T&bhJgu7Mm#dk5NCaOkFQ|I>QEW%15QyN-ac=w^62?>^raC)CiLUzz%aoYE4X%VS5C1b_FbcFj1}YRdBcjfDfA|#u_T@VJ zcvP%8Tt7#i;y3?p^&yD|rQ`*8nzBSc$Ay%P8TCt^!}q`2pE54D)w}9??{ij>n93<) z%WQ|X-ppv>j+_PMQWppnVl!xv*JNLLv}k=MXLuX_KLKsP6tSTFuGU%!IZa(8x30b*pZfW@Pe#r zBETLg4tV3C2E%6d*F?Xg#4j}}Xeazw9HCLe4bO>xqY6p+jBj|T3h)rF4TsxR zb{ZaYv7b6JbWwX1fyk;qz4xW6fC$AQliZQi%-l>mD2Ve1V!_H|oafAE9|S1iGF5WC zG&iKD?g2D%RTNUX(_`)mkslzx8AAZ8N8CZY@J8^}r%j)CP|@w(9o5{6eKjE-vb=0P z3r`ELJ^6n+#WNNCEClg>$6Z@!YN?MRQb%;HM$Fzu(}gyf#QI;%>Vg#p^n?YAb!2b9 zm0g|>@xfQ&Fa&@m1W!9K<4kjVHHW;!H=VYVViBo`QRWM3NXoheWgluy<5JwmyoQ?YC-L*hE%J$!Bq~N09kKkhdhYAEnE!zjhI9tVqfP zhB3L~wf>`dV~b*{^Xqp85iMG5WQtgV?5>_~hKyHSx^8dJO<{=0OLu7=S}4i z#>3EMJs$q2uRU(G^??2}C#1r{Jq>(^sYJe{!J{B(c2SPyl%!`TybJm*#Inl7fFn!! z9@-`Qah2pX`$((vvkLm9@8OY2UMxZMS$EZ<1urA4)wwZG*rM&T%wV!xcRHtHB@g@B zC5GziwHN`-t%gXT-PDl=2TW?*i-cgkF}<#E?u?yYY!hk+`6~TxcgHus=Ro`;mFGS} zz#8AZtpa343S3yDf*BC4|B_VEqD7hC3;B^qvf}Vwg zu|@wJiSh+d4}4l&W)tjRNLSNrgFI?@WlOzws>Zyb69u%9Yll^m3z7 zS4_oAwg`ge2FfppN5HDxEf2ONS5=m{Zl5W36f~+@Qy_J^LQzw`MBNNg1rgyt<-NLLz1&gCjtke5ecsky8Ys8%o?vNszNG-e`YK5^#-F#p z9-UBPq6OuQZ&=hX=eLzhNLS{TR>@^tS@Z?q}0J=-X|SDH%T&DFax+P=sC=cCw9 zzq3Q94Z30=G&x#SlNr`4#=_Odnoh$f1GPFn^3w*F(n~Hw!T1@lNQE5*_tZ9ryL2sUMc?Z zX@8i`(=z#{2~RxGR_btI>9(=vWIeE;LX8sySaDYquY=HNTcv(u>_Wj|zsm6*(#OMN z5|-Y=kX3sQQtd2X7C;I1c2w2N_IWp@1sj^~63%o6caV@rmO45Mc+QQ=>$}tsRpH9e z2(opGyY43^`C(N zQT^$K`14S>1{Ae6?TzC}g;79-Go_BG{Hx8ms*n07cBUP%7UyYlFCi}_+km}{H@>>5 zM6SRe4Rjymh$ugeXA%^ZB} z+~g!^^~A?#6JZYa#<$MJgmO4#))Y}3Hw7HD;Wke+7`rS< zDypPmH>0onWacHA*MEfe5z2tbk2hP?jiH7Pt{Mp2X>+ z^98b*iGTX8%0vNYw)Dp$`RD^5x@3B}0jc&hT=C?_s^dU}FgjTU0eR)8!T&*=YJa@y zK%BGSowX;VC!VkucvW_iK$=W?WM_fU~0VuH~HSxNeP9R`?YB z9YM+^-X)wm*G+54riCB84??Ls0#(}=%0(3pW-_xX*Vk;;omZJ|9V2?r7v-E9QpBpU zzdHGE4Km3;syM3FlKj+S_Uw5?CNb#GLM(4{D(nc>U_qZD6?uLhRqHmO$bGX!DWIRb z%R6#c%#WY@Dqg!^FHz~k@}#D(6CPX;<_aImsN~>tzu?o5)m-?};j@7NMLnsZkvmt> z-BEY93+MoF5ucp%5nVThsH%|%_pkAtJRdQLUsQ(R_lVTdzo*Jf|B*utCbK{jn-u`$ zRH&U~iFns}_A5a(L(E^pcBYI|cS4#%CtW-7LUu0<_+DFF#R&$W7m6_HG2~pcC&~0p z=wbct7LK87NlmKlLv%X@ry-%q{q}VLZ~w|RWs3V}pH#`+Dj59%j6ND-?Fiif?$A-+ELA4 z+csbSz>@Bs4w~W^qG~p2Yqf{c_ieCN(0I!4hOs^+y8qMt3yGK3!mPEI#(hU)JRAi< zLhWAF1Z~{5s564)+Db@)SO$*IVjl+*wl9r^Sn=RBh%)?YwehNRyp!$dieBHJyl&6V zUlo`@nrJPpcjP$mc6dIZ=JDGeFQG>tN6D~-DD*2eG>tk%QXbw1?_RNj+!uC9v}Rm{ z9SifqQX2b}mCw;mI7=-0yU}jGwiaV#%Ie{%IHifCN0I7&2ah(ISJ?JvtaMeTF+<(V zU_nMri|4H5r6%Q*#!7TOEy@gvV^zf%yzVdbSB^tHW&e9{rSQElM09rA)OuFh9Vce% zTduO-y_xn(^&i)-ZC8XsHum4@eVTW$&+dRFJauaQy)A5)N=AGIY{)AQ;e3C${`!0# z#o^m>Lc^v@UeRvY%Ru9{d$eBPpZ~P3n2O`o_XY7Az0e&nNb5vW3I3}aBuKb=e`uZR z>IMLV-xM~Xre+Ya%64wBEryL^x>>PMyV)P%P0g_f+9Oy5uy$4W5+26#?S-U~1e;2; zCFS&qHCg${lrx#0AeQ6;Wp$oRB3}mKnR%+_Fa!Ffjs|R;dYpSIiT>62^xe!3EPFcKXrPfiCRXDGFCJETj|jJ8%f1%HfV zmwP*`?c!pC#K1~9V#C8u18L7}^k4e%b+NRDwpNMuk-*Q*e7hh*T__K)z9$c+RcWi7 zW{>G!)r-uIW>4gC&!IwHN#|I1fP4|A0`YIA;FQ(K9WijhqkE%qubNQ|+oSVsy5Z>a zN7$|X43m$y>tg;;x0a&08~MVb;E?^7p-;ZAopudL)rMWY^d;q(&vPKXm$HOb_XgWm zZ5(wBiz`)Q_8n0YWJ5bwFVS$rc!@qD5$qj#K-}$yqt+A=^Xu_QA$ns2BV3Q|2DDg4 znSjwoBKP6rO=+*8z8w!!coMn)bvQkJE=#URg%u(Kj$_MjX@{ZaDPX$o!PWE&y$|ua z9BxTk<}F919Ugc@^HB8Memrgbv9NW-k<*uXpqo(W93x6KMy)YlG3s? zr_O@Ab4GGb+9zmB7!Y;PI8n>~X+KLd{#3YSCxzFD_FB&@=45Z|cyKrUWBP-i2D?xJ z=?8%XK1Ew)0XOE&ft9|;FJ#z_ywExDXu)B0tnIu|UX2rdq@l==&=!5xZ|^tbDXQW1 z*Hqo*N|nZHwtQq;*1W$Yr|Y6z++4K{9^+F+TdK=3%&0#$yTPY}~G zvotb92{Aov8KnJf$UWQ7y-}B`MJ``%aWH+9ILW3kozkZ2u)}2w&%z{(%+%9jL;+PD zs0k5^y^xVLb}Cvv^;gWWi~E;re?m(uJY@wTe@2W5Y+ExvZ`ZdGYb$EBV2`u(?LvE4QwvoxAnrscr$)GSctlDzT>a8{5^W3;u zDo{P{WZMqmpQVX~DzP91kf%(gQJ}%|5_`1#GnH6)U#QPFB4b`oc5+Xl-p*#fuh+OA zHH02Ar9lGSIq1*2yG{MlqK2SS)flfu3JoVN8Kv4tO~!|c;{sfhnI~?c-`$-7 z!2f>A^iNy-(Mat%Lrd|go&LO&+5?;|`%{4Nq>^&6LjrL`EjP1MR&{svCUUzy5(l-L zv_IOPyIN!`++l{KfjZg`ykt<7k*{t-*~BG&@u{5S!N$zkecUIXOp_4pE3MCu2d{O~ zLJoo7<=aL-*EfwcP<_MM-6U%=55iMX(N93CU-=UvQMnt#_FhWT5S~1f!0`37LGZ3% zJjuwgHgIqvyZYG!sNGGu!Rs&T_(3K}JkS@ynUv8}d5|P^^1!d;aYQD#5jW+9Mbj<> z42fh64ee1biY>e9s8pSqiW}Oh5cw1z`Z1{O z?!bIKfp%p#*Cv$if~WZH-PF%8FO`!<33 zZ^9T(AGw3Xb&Jr=v2-r}X#8n&=F*;5{v<)q7?3Trq#1KZ! z;#kMucj+eXgR6+H;%M~U#7YqJ5HoS>sho_qo!`r+`i>^1Rw5nsDEO;)eH$5|Wz+HD z4yI4sF8s%4s8UnIHFo{6lrPhOBE!yKh_cGn$e^ylCq(&qDaaqNjERM$bE6;ly2k3L z`$-V!K|uieXiM|6)Ll-d?T*IliHB(Y?%)1{eoN8{|A(SZtBbsyQrd!6tKM7W7e1F@j349LLYU zzu`;m_kINKwmt%^2bQ`F1F~x%uBfOYvE_z)S@$~^0qBUc!hA|Dxl1J!#m;zA3e_Y$ySgfF> z{+%R-Ut|Y_ES$@_Zm@?xRqrA&pT|%7wR&xL9MIU(+n(L7mVF#`UITd8Ffll1$f~QV zC|_>$kK5sUc-aU%`YvgTdpc-5Xl93h5G;1ZYht)W zKjs5cu)={peE&bBTxG>N!S<^IfXQvP>=(b7R>@K0P=|2iRf@I5iToPi4VXdEi4%6%Y6@WYUh5 zba6w?o~q&8JOclhs+!&4`2GM^z08iUEadl_wr_qa)ULi789_%F|5M4f*B_hOL8%M< z+p9JZiD~uop=tm?GM%!>liVEf*Ro`EHtC5#K)^I(WBgBP46mr5Sx*^D#DEiJYC?B* z)}}tb7o@8+{R?RaztKOj=SG>ii=!nhQsA*dO@fZY=RLwDPjwjA05dZm+iroS_*7i@ zW`uh_2zGy$klA>&BLoXPJbkCKfjCYR&fgiJZ^x>pbz=!da0UfVR3{dvB0cx)EnPk% zxM`C6@TXXX&{g34*Y-P#C>+b!n?}tZ&qkotFZ1*mmc(DEmJXk%UR~b5x{*8csvZ1g z`mOZycOs~&dgP#~l$y(J4kNaIlt$9X zXZ`7jya*`FUltrRD>~BA6 z@Oct(Iwa?|Ua=(fgVu;z?=Fi1H<=d3vht z=U!wPPVlBhgoqDE3TQP$>4{hGfR!PF`k?UWnU7JoEa^N8Nk5>=&-o(6P$9MFs4>vw z%+u5z!nki>55QIBFUQI-A6XbYP38VGwHr>S)hu_?pB)5E+4hEyE#GqUZ}n!Tz8V!c z{pdDf;>YRXe{;APex@%GlxU@)&x&OqiHu}llZZI2BE&~K9I!DR_)<%6EEKRR!i8W# zl6AE7#3TfWSekd0Y>D$>h;*C1;rqz(KL=-p>7ab7uN~0ULZ(Eu&x(s=dl8>x(RgDS zv?{HQYnfz|FXwP+E@6?-B2#UEHgu^E9Ssah!%ppT-jukNKep zgT^fo4vzkR^aBe|yNGLY`Kd8+B{I4JS#XYmC;K;Yb4P#2b>6?gilg|f_Ms%caQ{41 z2yq&7B!F>L%L$Iw#mLn<>aS~hA)pzTfq^&CSEkXtZ)sV&pbWXwUaUW6$ck?{_ZkVOeY;o6LN;Ii z3b>SM0%wl%qCw$A)s)?iP`Ili=5_{nBSAS)+F(AGg+51et1pm@gHfOlRPW!Siu$lx z!}>?)QLo4NYH1*lY`vK{_rWY##YJ@%FCaxyws^!)J`NSAc&&852kdul@!F_&lZjEV zFE^V{6kS@ZRMvO%dhIYEVUczYi5w_+nKSDr{&CNoV1ep_gAw61;>emxSW%{#@EZ77 zMv}@utnYYF83@;2RHVsaOp&cgxu%L2OX}_;m_ffMMeMfONwdW>%`1xw0nOH^_d03w z0UrX*sy=lEDs0~?y(k}zuAe`Wj+(}QBd&k~YuZHIY zR|xV)t0}W5EA9N+T22JWv*KFj=!#P9SQglDGy$uSWT1wSvK3lha4OJXXc@=nnNK`t zz+7Q}?Y(|(!X*Af;u5eQ(u>4EYVQET&jWi<~Rby6)_N0_)zVShTB`-wb79M z_~uGN$#H?rf{B|E=gudk115NJcT*T#=BKYdx}}vyl|XP|c`!hxbMkvu_>z?Xr0_wb z0UmK!G-1Zj?UOW1&cSmmTBk-t(*EQx%x`9F)Wpu9NkBhbC4yp@LH@IsJvC;}Hibv5 zUn1y;zXxo8l*C~xX+{36pyVX8(4wz(>Ah@IYqZkjmI=vjidIeWjYV0bOY39AT4~p) zv2>r1ln&}XsUQV8oz5M2Wi%6$BORjUB7Jhr$^Ni!!)*#r?+~W)M!^2O?d_qQ_8JkH zJx(^Wk^<5!(k~51d_RJ=$8Hu%wQi~1Z!K&u&k+`oL422vUsm^TJ+mn-0N-!dS!#cU z-Pu8bY!k3^>&pdi6`t_SZn?qefO( z9wZI0Al^NCWc<5l@u1WEU8!`%35s4e7DNK6UjBv8fF9uEROeg@(y~*Og%6%CSkb2qdrNNGcA<%ZL+Mj27?HQf;H8#_ zM%1i6Ly%RqE{I-3=@E|dlxCP-(zNT4W2InAU+EZSH+^Tq>1Vyu0@&B9P} z#L9M-@6|2P%sy8l1H1}`139;&>=~O@{>PenO=;;(WtkyeR?I0)FIa;cCn(SwuURB# zSL)Y{v7^R7=Q0tW7G@|Z82hQAnDe3$;RYN7d}nXn+7cDcX{OFttUcsqI%5h;s3WG_ zoYvgUrqW=5kA!%f;mv14Py@VE2axrV*tyPa5CX)q#4y1d0pp`(Dm(bXQvH8Oh+0E; zXVx%bNtJc@wtnV$jBV^~Q^N8=nLzT-T3z3u55R{82S_YT^jxzi0^FZllwSyd|1+VQ znsS@7_pz@!O=%5ZAsk2>bgi7OcmUl|@w`LIH})-SwO3w!8^u4wOCccz4Gfyn5L$ax zJMAyhUq3K4L_~g0edIkM_z$T}$rUq3PZ6p8y|Uh$Ta$t6nQ9`;j|hiF7ncvXG-5l9 zu-WHV*Bw1bVNFri)AxK1@e90?C)!pDa8C;ch^l6q2$@ooV0gJ!`Ny8Q^poi@STptv;fW|Jm8xdvFLh-U2*O@Qrk zB_fUoEt*~DKI8x-``C%iFgc2SUM}mNzoW2qENkKvkTZ_7NI0wFz+%~7h&ezS9cJ0d zOJPZV;(v9=VO;H51+&!CcJvo&u*rN$FI6lz3s)XSLAO`7USB%J<%&9yd>BXU zjX3ABEm!IBzT>4?x34s;*n1_wWY|)ii0ZWw0zaSN61|woCiUot&i7)Zi$O&sMOjo9 zh_*Em8nAkF{(DmSCi}gk1BG|^2$8Ue_G`lRc7yM6~FT#$qmS%Fw)=;Mrg?NeYyFv)jl@- z@oZP4M~WU1Z(UvmGlzrgeF((6nR3dekU?J|t1ESaei7lLv8fEk;fVtP!79skj{ayD zs)u(>e2n^YGmmFM^%{pp-AO!lB=>Flq>C+!8-}0Tu0J2l*L)F*M|~F4Tott1Xx-iY zixRk{@E50*hYj~6u22HUURvz&9~-qypv=hVn0`k=AEMRYx+%Ij0fK5eYHyg&(B4r zoCLNh%wB80%o#0P5?@?pKcK=QG?t9BajdzZ+^KcW`?homdIP6O6!1s}V30@MHUR-ebKYwpHHQV(Q>p&d|sLBJdq{5k(bv2Dy#kH#3%_ETp z{EaEU)Yy8#ceCL8Pd=67+n(@sC=rQQpzU(qof@_B(j~S`J;UCPK}U+w^UuXXESpb1 z?*_4H{+h^ZzeP=hihXG<{AAwtqi+5wdE5ufT{-e&7rEwqVrgJb7}bR?en!N$CUSidPwguIBd_J1zNglRfJUtZ-aIOQW4mRwhmXrI-LLY)rTkA{m*JQM}*3P;VX2 zUdNrAzCr*-?AhxZvn1V5iEZsa3xGx4o)1L-#`?zShtxs=)IuD*?s&Asn>b0EfrdQ8 znL4FLPhKo4Bo?WZE9rFn8r_%&!HB9li}z{>qlV&5nSKQY@vHSXSDgB)tobg0j8!)~ zfWNPvI}i2}^V~2Rtp5e4d)ckbYGzLVMx3dmNlxklcnB=cy5g8B0E*l4qk#L&mu?5R zX3T44?@_P%)?h(S9^}CgpD9i!pX*_$Y7;d?ei`8hmQcQ$^!-P$b0SPiLaO}MP7U?? zYvsUV=|%%A;tM%fApbD(m9*Otwq0N#h-wJaDl=2so`;ERSN%UEIs4!ejLKd?HHl3v z$zJ;=rgVNTnS3)ld(VTN?IAIgKR!s3g9&_Et`kan6iGxtVlnTckIJFX`me5I6Z0oe zMzF~{nNHB((ugXyCVE$dm7`$@^YI|ggIeDU#4Nq9pOQ~=Xq#M z#FVZ5${m$U*Mf%HD!IGmR6Jw~*?s;$KjtU1bmPB(u!;VA<6#|CXIYDh6Kf zVxEKte1ylm)^~EHph??`@Za#F7Wl<)gH}o-BgktOdRzX(D60c^gT|Ghko0ok7ngri zC!qoNQ`a&i|Aqw0C8-6>jw<2%nISMsm{PG_pibMoU=Uv!K-l-b-MO|Cl)feSxxQUW zb)(RN|2oo?CjNs9^1F{qQJUZR@VE|%!D^-t{{uZ;mYEleL**CydCs{S3xlE=^+<@5 zU@?s&>Ty?L1iWEVkfF_Izv&`qj_9qg^{v)1x&0Rot9bdFFXMO>-v1$W4Hk>N)Exfe ztri|$f_6h2w)f@WneZgPOSG9XpIGln!m;?()BUWz=ff#2Nfx}QEyquLUyiQ)1L}+m zBrnw@I$8)KDjDfokuvGGyT7rx1*`v%kmkrQ2%`mJ#fF_rTu0ExzFJZtaQUb#yqeKg zv7+!~cWNmixN(YE7H~AJGVhF<7dXe+x=5pvXX`y}RvPtkk zJk+|(+36`@IQBuPpRy-TlR-i7QD!F&FB)|oWOYP=%{v*lyM*t8N!W(yw5AbG2iH1y3V^eW{JD zJ4V7cF*xY`MQkGt3j4inY{h)1;)|#o5Yo8Y##T*#?tKLWbnEXB>p^Zq#OJ_6?Spj& zX}88>OOFRCR@6GMT9v+)+oGwRsa~Ql?Ya4+53!6+ETQ{)-8nfM_m&BydDI6Oy?imb z82_efb{IB~e~RsJ!^rnSQP?TlReY+zgL5UT;bk#*xSC5^Z4l9xJ8PQP-H_Z#48E@uXDd^K3 z(Y6>&`V@n$Sg#O#`Ua)e7{a)oSGeI6)PSz@mBRcMp_<4aV2pm$aLTT=YA%ha)F|N9 z*Q5+a1@An&>hZOj_x*>Yp{nOAbbGbk{URmLR--|nS1#)Kbh1ILpCIG(Pdm!#sDUGt zMIw-gwN)6-$H?|m5!l!9O#+#M92=|a@NG?_12{P`>RWxFL9GIagE{5neB$tHqk~@B zU*j@ z`+ZP$(&|;LEQPIV{#OBmh1hD!8ZW^CLngqcYJvl%weo!1j@QjFo9I_l9tvNo!oQ3< zHX#XGM*G?ti9>BD#GF!H2aF|RP1id^bTy08X>21rNR7kn>cx(-v0ZBn17ePJO=#rW zQRRGZkSZ2LBZ`wAn(+-{Z^S(Zhm>Lh5!%(ce$JkLsx)inLyTm2^&vI)DbuO#og-j< zTkZ3@HzWIfg+9|8G!`VJI?=}x{tS$epxGdp*VKws_RZ<5!lFY@zipL~RHJ#Ne2Nj^ z1GejIRfw)YEV2bsqgn1B!uDZqiy4A08j!ycRVjRwWF&wDWw{_4BkNBuORt(gFSe5U z_m;#T1YKOi!pgDtVpqmZXu#VxbpdbC<5h5^KoqDL5K@_9bDbzXPww2_>sq1p_bCJc zHeei3PvL#CnYS&KI0`TMBspG!Y6raefs5h0MyiiKNn36F!QD*&&PkLOozpn zwu_yNTImE%e=-CqyzfUawQXy~T)H)Ne{8t;%ba3fla&i_hP)RW?p~B1MgUws8ta9v+Q7^b+Ow%LrWxgI0nur~NdXc;wYkj)Aw81pq z+ClMMNqRRI8ObkJ~{CdE6WB^J_KD6sMlym>1f(*n*3VtXBzDhcDEP zQLnnV;Q;UcMpvv;dke89vV09(tI6?j*On=%VsOA~?_*cZo5;luv|mNo)^MAV8>-N& zc@NCT+2BtJO0CsP=GO{5qF4DKjA8P2pzo%=w(a`Xmx?NFk*W;p_a7}16wa$O`KeIC zyf{-6xNJSxqt7qWyXTW@gplPlnvguEK36>5=e#>vd{51O{JA;(+@^BRq$`%Pb~jYU zl7Tv<70-}qp3&60mP3m7KI??yg>0b0{Mg30rlcAOLfz=)rxD;vSNhX@DTgD`^M=?? z1g&;11{;qM^Hd>Z1aPTPrKZGayI%MStIlKh`c@)(le$n2fW)GBwQH>BEg+tx^VFT)SD`_WSdJ#Qv|@|KijC_@}`mQcOL^|K<}2|3eCT5_Zi1gKw~RXW$`1 z_av^t>?iVgPO(y&(}neD%`YbX3ycf||GajBmLq6GmhA3C2s0upE6@Wv5yrWB2Y4K> zx|=?}*TaQ&nH!qgL+Xi$><5guIp19r1terXx|6$Rz2`xfj52CH=nKJY!5R~raYW&-EZU}#nxaMbzOv^(4n8lxb+&)a^@il z4&GW#7Ow?ga8LGURD*p4W1JkzJNxG2BY#AE{W>4XDW|URP^Z93k$Br+Zrf4Lp2c*Y zg6cI0B+cUFzLG0!{lUq(mT}irS;LR{jXqnYbhW zSWDFM=s}SI0AC|(wX;z#t7geFQr5C{f58cmWFV(}kZ8unl5T?9T@Du(1iy-~$qGV- z0q;fE?c)F7D~KTPB(*1^;On-YvFmnJlv*?9GW_UK z*+xa&nkh;olv+RABpuGmjz^_IEB519T;|Cox{=TkmH{iMf?a7YQN0Sr{74YuWW%p? zM^jaX(0714uT=Sj9O`KQP!~5L8hUykopCA+v)Q>B38yPl$QbAxr!T8aiHOvF%Otsi zZ<$e#UF-R~Z~P4Tcc6!M7xGb2t{F6L#Z;{WT6+96ys+kDroQA+b@45J!u`bTSIBpc z;8?|AxQ6m#p0%M%_B%J;?|U>J~Zol1!C1CBf`gOwCsNML7=ImmH)<^~uruqHG-i+uKrY z5+WZuUDYyl6GjhKxhKMgP@b9-O<7%Fl766R{IRob!k=_x!sN;JCe>FD;5X{Vo&ho^_out4(-9)po+k&_EYR%@gUUB)kAKUif zVRvdlgBgTnfSBqv;xtD8MtC=DoQRMmqvNV#`W}H1N*#}*gV%%xn3(kMmOkORBFMf!~J5aHr(`k_XhorK?B{#G0p3?q|#B$(=Jn#MO%iHJ*<{ywt z$d1griWB(vJ}>m6WH-f=zq$cG19vlJJ<)L;%QIA8OYX>06?Im@nLIv0c`eV~Dq}4% z(+}?b?0$Z3K+CpiJ^NwQwacvto-)27PFu5l@~Jvs0U$J8IaEoSwQake6>^rGZei%! zTNkJuG^;#OxxT$&Q)t(*bQGjb(JiJ!uc)gT!r-5qfu^~j#@=U0j;%)Jzzh|e*vWmu zsVG2{;(ax!WKo5h+m5E_0Shn0ul zk5acy2f6+~rrt6vs`d-}rUVp~kWgB>OHvx7L2_sYNok~ekcOeVyIWdvM7pFwT4Lys z89)XG?sxy6_xbRA7(UH$FneEnUu#`!o$Ghjdbq-`J6gXg%dHGNPf^}mKI4Bz>W$mh zu;3sf&Pe**ExMOcvnkhf`7`3MP}}4+Xv}B+=Qv!Z3NP~+R&YjVV?t5(m(G+y9N)q` zbL3^d&d7LyA+62=lP{0NWO8puU0!*1oeP6S7gP}k0EjoQz5AjTz|FsYUqA@#a=l)R ze&PsoUEk1;5}m<@cNk<=6(d3aVNm}D%F)~Z@CaHSs{?)$?)v}`?i?;Sx@lIL_n;Rk z3_EZpIew(!I2>}leuq`oK=1P@mVnb>*X6@kpL$$jEv5d65qjs-U}S=HvUD~;;E0#< z&qV@s$1(rj%1psCj{B2Wzx^o|%s-ZWOOPEF!e|kz$2*1l3Ph(mRwYt{DGumRWAd}f1 zcXrtQdDuZH6ZRM@F?{er6*#=9}==0eIF9JeVyNm+W&V=KiJ39l~yZ(EMmXs@omb1+h`{9G@eQo+-a2aw^$xg(UuK&AwL+Y(pBrcam&uIi%RtE1ppbeU z9R~clQHZ=yT?8u+SR=4^NdeA5u-FmG=N3hXS5{nj^HF0vI6$ z!uQPHsmwdoTh4gW@VvEo{*CP#U*F-K@*5arx7jhq0nwB&ZYQIA= z;$9zH7aX*s0O~rO8u9|Z*;MQ|fK(k0(tljsrBrArNS5c<)vERAkAb%j#QNs-kI<}D zQYxbxQE-%Vg*`+iQD#JhZSaH|ukBH`?jA z`O~ONCq;hnFC&OEiU6oJIhH+w{F;ehceZtP&YT6puEm5nhp4T4yLzgM&0DKgy|*}~ zl9Uad=C;!atLXd_lcW#cW{yG35EL2c>;rwo;zn;l_2+%Dp;YOjPz#|P{W!yS?{dn; z5ocLlF;74EiTS?$p~963tUYo75MBW9W#;?Dj5g`X{(bXz1VwjVY5M$wiKO&NHhF_A zEONfl6A?6qL>&B=F9t*}y19`Q=>5ouy$!hmT|_~BrGu+Trsu8895s( z1Z1UTq(Udzl%<2-_H#RYIJD(R*8`=4Ep(&uFsvFCt2hr2o8dds-?3-yxng?q;U6Zc zv;M8gjc}t=%{mJu-wapnp@A1MFOZT0ne*qo?{pcTv&D;tC+ol<= zZ51x=aOIlWlF>mo2O>vs8y<00xVJRz#az=s685*gs9NMMGIz4i99g-Kmn{L`qcY;^ z>8^1g^s>h}`YA`FH+q^b;Wsu`4Ms(Xxlz3Yvt5V@apYSoG?(WW(fRET0{A}yl zQBr@X24N&QzIeXuT)Gg}_o~24RFfCg5C!oilDd5}9PT{|1^Rmyt97(Cuo&?>7l@6* zm!S%qP=CioM{p?#&g0S?HYK6?J&on_#ux>>lR4(ANL#ExZ3nj za!G`m(ORKyF8+{oRQ3J?7LC;W#A;f*@T%lhPC+(Kpq$CZM2l*-i?X1Qczm;*wcs>S za&xA=d6v}Y*#;rW&#H?oZLp={@9hh=aaHyuT}+c~uxEGS1s|UMBmK#u#85!6-+#uP zPVD>%EPU9iJvtYzMf2~b0poXhjTF6sZO!BYB0H^TiX&PUZe#i z{KE>i%3clTWq@!tChKoex1-KW=u#BHoRZel6kS8MHtrPqH7zKTfvnj@w5S5ymwp`@hO z-AY?3UP+5fnU64j>Kq;evTRV!R`ef_S@UUi6uMltH)UDGeL#v?Z%7t@zj7FfcTcM9JsQ_sX6|_e?r4d zYQuTE3)bG8conhHTMZ{=QGJG?M;Sj&9e0f@m-<4`iiiG6dO}iu;x1~Br@k_+bHTGa zQOZ8qYz3EmPRCaz91mkA8|0v5v%_w@x7{a{#mIJ1a)YncmHIVmvLZxY+*F&S2rp)T*JGC5tC0cF+$?fy{{(O7AU(ct{M>ZM=+P{8^@ecIXHalcj^tj8oz zUV>v$-Sie8=ilU+y00Y$;yyXnZ{pAGi7sz_mP`GRF@f(Hyc+12<`(p=M7bEQ5LS)} zCwo^MX_nOyuzg~m_mWJ!9&k`7h4J(LS?2k)(7I;f{HnGp<~59{qNH+gA+MI_^wMbr z{XIpVDLk}J4@3DVfvw@A%GrA4P5^-}FgU$|{ixzV*j35%whpi4*Z|x%82`Jb1bPF) zDr8jM+hG%8PNr2X%W>Q66FQ2}PH>Qv{RV&$x5(tXJg7U0X(a5SI&(dNobzP59C$;T zZ8NveLG9*=Q0T?X_4-crpxqOSA~KBmziVW=c?ePl7{2%|`ciHK*BF&KamazOSm%9N z|C4SzDc6>D3H+tAbG8S*$Eopt>qJ)p-r8aEg=3EU)WDgZ_R2#u!)osi!c{tT0L0MP z_LfAhV*~>&L5)oLw9I2z4qaBm<_bM~WNB6qQSq)0O@OO5EaA5?=|NeYh1W`^ZKE!7 zNGr}_@9c)O$~?-g!#MC#ZwRjcWLq$G8^c)@bBj!w*)_3HXRWa8>PIcMegV!5-3gSt zW%-fxHaKgDyxRf>2_tJ8ET|Jc32~kVQD-*&4mQ=_xX}W%w8{t%x13xKc+#mkgQ@= z(cebR?XNXGuI`jQ**8pKvNG@UKthTb6v5wq&}2|xe1!N)P@z@`8!33U=^Os5=or_A>c$8QM;k7Do9ZipU}!aW(i@NN^p zpv&I3Ge3c{6GbhxkYL*+f{v8X)PKkqcuN4Tm#YHfwxo(T~3#_Y5afMV_%UCE%33PS;+@1IlF_MObl*I~;@m24dCSUvgq+t`6{24F?jF>-xeDs9^_W;Qt*Mvl$aJNzN?4 z8XU#8s~-aT2x&UprrJ^Ih^x=&Kdd9+rw+RoYirW?HUmRf{cyzE{9G`$B2B zSEXqz2pI;#()u_0G};Y_-`PDJlF!U;1f(f{UJVZVYD%^Cc}L9?p?j@_b5mki0& zjTLtI3br)%vWT(hm{Tcd>pZK}(FW-Q>fi&)9XW1bsNu76nv=O^+^K{xo`5u)STouaWHsiY6+k6+y-0pl3hVFFiK}ogma!71@V{zpO6&m4LkW zd0<<^BlwUm7a*f#jlp#rvctVo3~TE&sN)KCZt_ss#ro}ohX32kNZjY0o(N_^b(s7Qw#l__ zued*c_xL1*2=lF#W;CV_zL0D9Sw_gvSk>qciSvWUFCz$)l|bk1_)g1gb%}HK{Bk5czOXROuxHye{`CWZOG4baTeo!rf%oeM)V#QWcqC!l_ zW=ZMI_WpPj`VUPwLa6J}1EtT;Y%u@FK|yLt4Z1wQJ)ejfn%OwfVr-UZJI zCrSfVqVTKO&pF7Zq!(5*yLH)VU-n^JQKyJvXMq$aHA^57(*u6|6c4@cvqy}C9e8J> z>|N_+;bsCzwRc7il!)dJ_PU3qh3$UNxRn|EOf80mKe7Jc>H&sf|2a>!c(_glvr5zL zduaAor&7LYr3qB}`;Bl)8Z{&g+=}4Eo_Y_|#Qtm7p4i6D>uXKkYCo%Z(j4uRzuzh^ z$XkuiOa; z^}XwOrT?w%kE5n9-?hh*^2cCJmyPg3^dFy`V1b?kU6_`($ForQWig zwfq8{h5^-SFn?y$`{@Nt+jg29zwe-F>nnkJV!JW%B%Ku2JU{upmStztjkDaNC z^-Oz^L4;?#hGH}QUgWxAug~+hv07X>4|5|H5|4(SRUbbUylhmD*Y$eG%f3#4U*3oF zw7l+93f>RgKLM$!u}^!0<(35{vB>(C>ZH{-O^3MLR+_M0%NLu2rX0>TUbS(!%a(@s zeQxSW)#yyPTbNTe6)2>n+f8%lG1|D&Gtk=PFk5pYM~)mf+(Y9ZlN{Ky-Gr$v*}2<; z^@)ymlkH!975YRvLn4m7#uQIG?B2 zusU_ZcE}`s&~Bi(wjx!7%64EHEj+xQJoiH8CC49Styd1vf(<@$Swbd@&8Y3F>dQ5T zUh|eMVp^n<(uzC&D1P-akkAGO*gr5+@jR zn&Q3xorLI(R&POWYi^^Ti@V?t^0ViC4%5>ss9dM5Jp4DIRrs?+c~!@c**9co;K#jX z)$L$MwBKUhGwcN|+Wap9-R7yRMcGJ{)eD6-;Q`fO?QH~ zM3uad`e?pn7$jf zaXVi5uY=hui|7@xMCVamg)~SnEW7u4oz_eWK{3u3@Qu*bM{hqh#9?+xqFmDgPk*Ol z)#*7ySqD*UsNv|V_*d=@?CB2E=l?D~CxFZlxc?Jnrl0VTuwgiX7hjy*?0Xb=$V$>%-_=# zReF*RFN+LN>;;8x;^-(}lXlQDmiy0yZ0AgNg+y5`j*UfYpdt=}MUHbGCOeGl_m*`= z`zg04{8Jfnu!=iC^akrTP2}@>S&!zAS`J&;+RSK}{K}bX8lr*jXiu3}ndL@LHIixV8gvBLU?~{3s*d|&UX1lNPXcmo_>}Dk;$F9XsTFGOaPp->Ew^RNG_jRU`S;cOGK)9Zbyk}7 z(aWxDFRy17e(yL@reMh}G~i6~>Rz45DL|*K!2+Ha#d7K!Le-asz(d0U-H$MGY_Fb1 zy(_d%N1msJdzF(>PxM-olvJ>i8NP5e(KI?SRiX7~@Ba`?T9IBCxe~Qy3Ju3@j>aKK z{bJwb2agj0g(riiw$5Q9D9U0Gw-3Q@M$#IT+Kqf)C=cNH*wk6x!C< z=PcAS1 zp^a0HGpEPT_fA~wsPsj{R??+|f0%vyglo`y(cJmRM;Q!a_tOBIGmN*+J!AW?@l)ot zVfz{wCSwi(uRiMSUPRd60nka&f2i`};9nAc(i327gjA<=HhQ_9s&LMjQUVg+gTTBm zs=}^mdFkb@VqwUcuy7ZMDMOl zYvk#3#uuH{*bcbZ_1+|L_}x}hm#Lau<9$7i>{@u$^v^CdS3hye1wi+zajLtX64g>Z zP|^G?S!euK=0o0IPlhN;Pzi5~NuvvoKKk2%q%3r~MODTai?XS4`|(%1M1HStjGSYm zX(%!y;A$E^97W)H z3aqvnWfT>5pNl^SeQ9Gi5BFla5uKB@=MJ|D9mYz*6g-K4+sSx~Y4Mkx<7rj-OOA*P zUad<;n`2G+M~LX0K8L>*^dZ$ajUVRwL8|jNt|uQ4I7jV-W$=z!^Menlfh_H{OI=TViC-dG&AG;y z2DI#;`RS2BS&BgtbqEu&9J{KGw(w$=r69KTy^tWvcW)r>4*5STZm2oGW8bIT z`!yPVhUkEGRcw)I=={-7D*F2y@f@GudEc1A9X`tJRMZ4mSn8Zqj|o|Akr4u=Y$2}( z<5qvlw&$N0Ga>z&S`-rtA?CNHNZNScybvPLWZOVTePLn?EZ-7q5Pkts(UPgE32=DTbAIhXQft1r6_{h%ycCW>=BU#dX zJgpi&hLJmPE{53$UmelBlEx*lwa#g2GMLJV!-LYu$NlB|jce(BI`rL~`PhUldafCX zg3VuHUjK{SRo&%mwMwaE+o$JzDEJU4gcr!*tb_3VTzm3(y&N434TF@lzDdEZ7jZ5X z83aLdh=3Hu`v@@@K6w7{9{3$D-HPb;d0tau$-(7F_lh>Vy{i#4$5(;6!1d)B@(u;N z4ez5&p)}LXKv|D(l7EZij=R$IZ#qN_aH1_ERj99S_1wjtx*Nbh9}wn1S}J(bMjjY- zvere<8DD@J|47A!`&hiw%#E%t{%v6KN6ODpiz{=YNidb87KbD%yjw4PkA1BB%y^ek zHc7nFJT(}3wk7arKP{CCcb#;`th@S4?kdOb!W3N?&8DiPt$P#ZRv-9|YOv^3srqkX zp{HZvM4^O3VaBp?9Oa-tXfGq!EL1q2i9^IjfAi~tPURqpz-X?ee8WmLkyi;?uTt08 zs}h`RQzTTU#}h;OP(hV&Py72BAS7Ush;TzKAK(W@uU+&jK!{#gD&WED0esr3azD#RL&H&J~|{6S5?W*)Xrx`6I? zEdnQ>9Ay}|5=rjRyICNZ!qP^y-7l#iu?l`VDo4ifIwl|WrISCT;&cO~%*YM5YAT?h z7N`c~(Lx6}h|OB>6IOzbc?(03on|%1Hyyp}a)+QueT|&Yl3_?cO;Tko_ouJpRalA$ z3k;u#mUTG)Ts4GS=u#DzB*2IseA5Pd<$yPu5E=Yy)1lB9p=M7Rnb}x47kQ}0q~gFs z3M*$62&$?fhf*ci3uJ5j`bt7520TGPlP!-KJqG**BU+_`kqx!*?lXzeWPfsxUp#8! zPfD1Q8>`6MEGxIE_7v5)3#fL3gwNVI4PAHZbjbIgT`TG?&@E=PDQj1@92Vw`D5JYz zXrMm4PFFK;x#HsUtN`YflY>!lk2O2@zFrkXAb(g(~!&hna$ z!82f+NTrw$nJ}~bvRzfN&EJIa5E5A`nwHnk_E!1zZ%{z@jMg`H60C**oTht=L(SP6 z+HLX;b+oI^VrH?fbtywBdq3LPj19jYre-SmH|5{+&QKL;obhbS&ft1qB0}WD8eM{g z{9A|oDMI51F(RX+8=wa_g*^ebn>*)j3#ct$vgoX8Q%fe9B50V5(HJN4%Q?kgWAtvm z0@hgg$h!d4Lw-}9@?Q0|;IPhu#mJtWeMb;t)M@Z8DYdAAQnsU=HssgN`}PqWsyi(<(*J z-=@x480!g)R+Mg6i^UcmvJYQQqej+Loa)fi2-1@xoIjKBE!`R4-HmcB=hSIO@eX7UF*} z1)G8hY1lZ#e7$Hs;*ecgfb}Gmu7_UCcI@H*PEtO`XyE92CnM$*bgBP??(-M_XO^`; z_I&drIsWwCc}joe*iaB%ECH03pZk+ z|3)i%QYKlkdy}#(;3_l>_u`*q>>O_}w)EpTTpZSVq+4@L44zkh*{=Q0IwF8=Oj49& zjW=IUNU4Vg776FAEE)Ji{0+{_Zs17D9^;^w65t!Kr&>>n=Z^si>N6x$8N*0{yfy36 z#ph@PNGP~x^x_W^oB z;!Jl&IUN3PPwe`u?C__e`(*MvAJ?|_cJm^c+(KXsuX*<$CV*W{G#_PP&lCx!?7e5J zW_IKXi~d^~X}~AVqj{~1`A8Hr{Q_~YA8_P7UFlHm<8S%pt?vOonRI%3dX4Ob84@%$ z@iy&fE6Z4-BiVfQ$YADJzrlr}OKm8A$KRC!Mm$vArl=Vs!+wzyENqPw@IbO2#V)sP z58I#r$uHGk$6@xTyimv0?_my|IFRPq2+ibkhoVpu7?hDE#CUT zQdA6UftT9WcrWKKut67kYBqeC{B1o;M|Y-qA z=qUjD;OHu#B)H743bN^lB&jER^0c0iYu2RM=FWA$FRapGNy=*GV3}K}_6-5Raq@Q? zjnk_x)+fbrTANAu?whejZa;(tDVb64^SPq5DuLa$ zx$|n5s|<~=6$lb{)j(Q3y|h~E?T-_6SEen#y2;>>_uYi$d-Z$ym*Pr&Ay9`yen|C?fR z82HCyla&4>*tWOZR=6xV!A!*CYKE3)4H^i86HZ3Aj;b3^HMea549XogORgVRTqgc! z?e>G!D}P(e2$Axtv)5+glYQV!otCAmiN^Ys^?q3{4_7dg{?}0XmvK+=aK|wTf#Ldq*dFt+Np1_&VQ0#G6H))JfLrZ+;Yq>&M=|F$T=^nJM56i0OvRtSl+P=o0}I zN8W*58A9DPu1oLzB8v7$$H&h{Qm*K1ba&`qpqV$>PxFCpbn~jNFR`+lO5s1*`6Tei_7_mHm1Ak{0F{0F9|!s z?_;)DqUHS$bSZ;xY^!~wR1w3a@Z8Z&X}&t)4!+)}$rTT9f8xO$;w>Qvvse$IDdM2; zYMSGCl`to;sgZzNX(IFI<4_K(?`~@8ORh4aA4#$&rXeLO6r})x5QxYMDnRz~)}vw* z^7)t&G=12b&OK;%^Q*5EOOsiFiIOn+4O=p;s?Rf8Up&X0MwnRH~B}Kh1-OE|Y#ryCTDV$Y~Nuq#%RwQ4M)p z3)@NsNTUz=Kh=J2v+GhqJi)P*D>9%rTY_9Z$yBy%SUEHkz~B>eP@nG+@?4Z%o$ zpHki(wv-JKnCI`3R=a&$`cT0%qaOun`#X^{?jYKxSCD&M3EN&HspT|p`9_tZxb^NL zS%2th%>wJ?&5*H$X0(BYIr4Q)w%{RWXHh+;W+3Qen!^lIQrvls%!mUo-a$p&MRsch zQJRN#Y3g;AKTg>fuphn7pmNP%da`2f z&ZEbGfIrqy=y|->k0+bq&S%;oTBjenk~_K7Qxs;nDYmIxZ?~VT+SIIZFt?*)J(#`% zWiFQ2qy?+wMmjPtCkf}FSOLs+PLlQ}sU13)^ue#f>C>p=DX~)c)@~FJ&c~YMB!BW_ zx#%(Ey=vUug*Ls=QY?kClb(S4unMs8^tFTdfm|^kh*<~F0b@gTaoo46?G4i zZTuf;JK2#Hy&E5ud1Ws#^Jv?H^qesOC5VNS&nQ2o)(L}zex=P#&2_SJbhFt>J*o+S zr36mH&9KL%vzGyt>6atN!XuZnqKkj}oT+ zpQSUlkQc5K)53o4u2QC`p{qt_S!y*8pFj(dre73kRg61i!uQYo_)lNDf7a%aA`2d`-EJ6pMO0Tq`L7|zBpZiigBgja`cP^Env##zjQK) z^XY0z;hXsETu2J&(R5J*hydOHFz_IsjHreh?QFp9p%+o1{A zZ_TuM6E=2p0Utqc`|NMQ|7Cj7iK5J>H$NiaZ4aST-^)_8nPy2F-(Y_j*yaLhu$fdQ zXlGK}ije;n(A_l`el$LoQtdP6^~<xH}p@3jqLLoN@JR@vKM> zGlX}n51fv1Q>F6AXO80g6?Nb#aeU* z{+^QDvhJCP`f)MYE4z5DW(w+F=ji~1kfbg`RdpM5=VQz0f^m6kw+OMJk0*?Jm)xdtz(dF zH|0IwO7g;@W?*fqlXB9xv0#pRp4_QNb7v{uIrHsQYpel*s2@wiuF$z>ROFZ^yo zAPXzOzqF3%(qP#IzUW>gUdG%BXwEjs?P6$vBf9Zz1T9|(l}*KIfaja|nsn!xR(rvp zGS-Z4i&R#?E7r0X^j@#812L4v=BKESP-U-I!2J4HcW||ly1n;~<@8iMe_um3%^q=q zhG!mR#G`sqx(6R-bMToXx76wMnj=9`^LNMMxamI*7;+Fyyjm3RpA*xcpMP8N4@DQt1iceE4`Zz`CqjIM7P%R>N;$EMQW?EEwl?BD2`+ z#dR?E=4dKK>J_Al$@t6m-;^4kW65TTWa_Wwls>8FyhI!h{??S?dFkOTyx6+m3>1F{ z*YWR9PU0;AI(1~^ds|oy58zaKV9qm8CfPQYu%)?_vGhmnNBZ~lY2_W)=!lIYjR^O{ z9ULP!f#dJW7%t|dtc`9?cQ%`)9szc#qny{-kB!n5aD7*eEW$X9pCx6~iTLi-bjKcg zvV-_P^uXg1_B#Q4SxI-;02Bz&-_oki;p7x#?zbZAX4j3UYwi4Zj6XQLyr5)`NQR>6 zo}P~EG=^eWu&b3)g`ObXSN4E_YcM6E{hd^;9`YXg%;29k`%#B!R=(4Zafo`R0@7#i zywJ+6NCSTHo+Z|Ee3=r|nC)vcHS&e&BdKdenWfFEsqh4Fcwm7MDkNY}LsK964-p`@ z;7P-09DQEjrlH^pw?{3!SCP?|5_c22?c@Fi65icuG!UjIl;I$3|6SIoJ&F)Vql22{ zm;S@x02*Z9wk*UK? zP2kM)38_>N2yk5?>VEQivw;7?hgQcadEH3GyEt%;dkUHJ%ASg}rz)EIcyZ??>zk*S zPt5&U5dn{GK2vmgck+HUTcEjC8jgVFInSj9)0Si79B8azsm2dM=^p2(kdxHEYG7xX zVbp>49B(V<$rcX^x=}A=CVXtdx#mruRT%;8GU(g2d=I6rg1X=kTU^j(0AeoaBLuxV za|P@bC~hZn^#$+^lfZa?spH2I8O+^dPx-zFJArk7Kg}<*si5b!WrZg&WE406QQq2h zkaI4$MuR)|Yaf9G@m#n%UfWbf{7g`^H>^>td7)B$l!`7x@g+3lr4qLSSMPv~Sn4kI zW6jUmJSi{^7F;7a{ork3c;`We9T#4uts4LDA{kxRke&ZQrriSdzfsTP;5}*1b-$XC zN&T+Awo)U*WALY065RN!6ScDvudF5#BIW0;M>>3ab9rvf(GKD9cvGBKY;TriO_=jLDmHsafdF#1u=jJ7kUdx)IKuz;3{Sz<*gZH$8Zvf_&O}f2yD2*C!d_M%I6N(qt@`4T+ zMX$8R*^z6>e;B-VUpwm8$eOq^<_t~zsgXs3|5xmj6WbWiZDRN(?Qi>7>gB)@nY#Yk}!se1*qj=Jndwa|*Zt*ZK^e(DcB#Y<5HdOXbNh>*iB7TWfl2LxW z1}*M68g4y`QG`4kQy};TIyx1%9tiP{E*76_-FoJ{4a++@cIZ=^KkqD~Fv#Ruhb&|N z6y7~|l)Xr|`Tc6|;0Pr(k1j)QCZo(zQ32Q+@_>!<@m8r*rB1y-<#0J%8eivy@bTu_ zJ`bkl1Vr033x?i@9Sr@4u|JY21c!A}v~!bc_dnAzHd6hZm?Ee7FNH|7wP5c>3j@Ce zb>vn?pON;FYSKgUJIrn4dBDv$> ztfU8EE-}v&DO?HP;yt7=CS0s%`8HSC6Hu>|^79ZW5M6@tiYdF zP%a2biw6!h8fNq?{Ho~CDlZ>&WUMC|#bkN6TG5>l=9DJe-l;{!=eV5o9jXsM!ixQk zK`5Jxr^#bSq94x39MAqSENJYq(e=3&on7!RP85ROi3i5byJvV_l78NLm*WpSt-bMq zhQy84mt^i-D%ox#iV+_Uxybc(woFg0BR@lstRC%DjQ=>CPCFjQl3v0ciT zefbgf(E99$Df*DNHA`O+K3p<%Z8|Rp_`dSEQAq<`TyaVf^wJXT0$HS5E8B~w&;Gt8 z+flB%$lSH{qvyeUDlCLmlup<7AaE10+0svBmqt|5og(}fZwph#HW(ReyzpMJWgjv~uMm{{~pXNoK)F+{F|r@>3qFtDvsYF)t)XEX)Vu$}+%2mxLlM8j`x zZB!~?wr9$}->Fn!b-h!iN6hb3Q z6_!HP{*k@aov195$*V#oS`FTLZJcmI?LZ*jSyB_CGwF|kiz2a4iic4Ji=fek*_+-= zfxFg|t4^sw`UAijC(({nF)}|a$^7VzsgizAb8o?yD$HlzX!qfCHEWXTC*Ld?{j9+G zv6#lbJAML$O+XtBP@Bvu&6 zSJb5IbU$jX$Zrr8s+ci8KKGLbU#Zp2l;E&e|I1p3s2|2asZ+qGZ3&skQ)^u$<5-E9 z;O__b2|5Nm;<1|dGl7q%<91_H|3vlxySqjXl{VjlyrXLWZ~N*V`=z5pkXJ-HMMm#EpP&{iPC~9;%?2icCxTUV`?p0 zzFvq##jRNPZ^t^m@vUV0Cl&a;6}PDBQ=sCNr2ALyLKfa2`0eM~VHmM^5}U}6Pj7~; znKRx8u6j-gh~26^u{qQ3B}{C8NvU4xa2IZSJ(!6xif1_-#{4scL&?6$-8zn#+Noc7 zE1F4f9v;pvJO*ey_GO>QGW0R@LJGbckAEs-WA>+`qrI&;p3!Y;7$MXCeZD{gaARso z+sQN_w0g(>`Q>vvnGg$B5NnIQdC zV9}427mdG&Ix~%n7l;YkErD1DkFU?8BM!_bPgoZu`r%a+O3i(3Jt>QOp~IF-`+6Yj zedwSEn7ONoyU(IfyW+@Si9}ouu^$6}>*fr{=b=xyaji28a`>~}GRc9t2eM<+@Ln(I zw6+>(i50ta(Y2S9kte~FkRg@)4?|xi^h!YRt13lu(fSNFw75LGf$8DT3WUh#>?{PQ zsPZbClrdzeJE(>>{dIjYdH8)Hwbu7QoJ3^tkap@M3&^e?lZZ3Wv}T~1mbxo>t(~K2 zTtC-ENqe5mJx8xGs0s8Z@{mn)-aLb2H9>y3vQpKucG;y+x`3lsnd2#q3YjRGn=N)q z6O(s6{=XsT4NaLk%@}Ewp(G`IQ=;_{E%sAKXge63H(rQ5i)UHx_XMfC7g;+GV6NQ@ zFbO=ZZ#EGSJhama)w|+Q_`-S6_)G2Ute^K0Ch_Y=eBEU~T$9+^z{qKQk+)A1-4ujS z29*;7JPyyC7yk_}YGetdJ%4)q#6KV;oP#jAx?bd19D3_(fC(ZQL^FD= z2fZfys3Hpa8(-adiA`og;9vfgDIF`yT=UIrH$kCbc<# zzL>PqALvFb<(XNhjIF;Lv@3t1hfZ`0C)3DYOC-KI_P)Ws-b?q%2)y2>n|N@apQe>x zV3}*{6>TwD{~`0~wN|li3oaGW&nQeGn4a>}XW~&aeV#y6SVjLrK4yBAI2ybUids&c z>&aDXf-VK5AL<)vx!btxblNW|KeHPtjTXKxltgKQkbvsK2Tl|2{X@a8)?DEgdr9_d zRSUcyO*#?+W148{LcTcdhs!`->fyPaooNGk*DuVaihrtcUZzb_b#M(V+I~J=tj{r5NkR)^E{oix{;$q$ zVA-4C#lSPv3zU)tO-s}wFYhWlcG&R*r5b&;bC@`G)5#icsaOFmg5!E4D@>^38RWiwUrW&0>$`hR5on3;11uB_s_CAgp**(3G@y{brUhWEA-0w)( z25ZR}vYc%663 z(N|-ZB77*r5bpD)d4PwS2^EDisKynd!3?Zre=F1$*(03^Hvfj4jUQY+EBa)tLRy!C ze~i_FJ+th;ozMX>X?s*hv>1$0pz3V`4(LV+CpcL!U4_&(RJWDM;Pe8bRA>4XM!6!i zjEqa!pGNw#qJH`dCNxR5m#KT;5-3U&F*;CQoaIznsPtu5mFNFai(!ltpw_|K^K5%N7P})j8&my0>K}s-q2T5-t2NH_OpHd~D*-Qtef2!siNT`aYd8FskUJ2d(<8yi)86Pz9_4!8yK z3TvPSDE9MmrZe{EnZi*YZ&qrExBq@7pP(M4l=?>*Y~CNf-Ufz3Xw?ZX8x&g0|5+BzIB&JHSuX!^XVS~T5S>3H8&yd&oSK@b zbNysD;{hLhoCp@UHGm}s7Ij2qkiP?$J}6TV=giEf2Q@v*vG4lU{KD1unQ9v;Lu8ag zfNlekVX{5b6ieAmM56C5F;?l>lX}8mxz_mY2I^b#GjRNPchP?BzeHl>XRworPn2*L zFCx;?2dL+%z<#;*hbNhz02Qd9#+(XobM^2Z+#Y|N*GtBoimwagmoTt|u- z)?rTfPwPQ%DiGFtE9Q1*-u1?v2HO39K_UMw-US0m+`$)a*xSI1w}L>|&z()`?AxgI z19w&@ER|}}%@M=vmcoXXl*WTzbdYburqd|I7;R#~6-Hd?akWQMeMAy*=nDmP1HOw1 zQHgHL@DxnlSSoR&gAf;j^3LQB5xxsA;f~uE?W8n7%9VBM$reuD#o1z9g1DYkJMMZ}ok3+GKLn0eFFl2v5$Z z-@cqGUU9O@Bp^0bbHy&*8x^^A-aq&TqkW?&->AGmue#_~?>`L6hu@)fQ5s1a0eIw0 zygY4mE!!6nPg2*Fm}cb|o=*~d#XT6QP#2;wsa%-JHhkA6hV=w5=zf`iwCi3+FD2TL zGLXKo)jx2E@9QXYD4g*an_t>4|1mC=Bx@CHL~7Fs;lXr{ygtN>WGflIj_SyJ(t?+o zz@tpc+Qz4UTH12RJAD&t+JWxL80uA`)$2%*3onGeDZ>f2>rcB20kHS?Tg995=xtz! z37VDYEki+W>~z(_G-ch&*X;;IAD9ewJNyVCpJx)Se+s;oYTY?A2<^`f|Mea6x%N8&s_?H0jhCLb`AD(;Km$epHA| zD$r`3Ymn%ulK=mhx~j0KzPC$=2#9odH%Ll%Bi$gNl!SmFEeu^F-5^~%C^;K1)Y|GV#k=iy>bpZ%V_*IMsdwG#pViXk)4h{E(-c3M9Dd{@{U(|oxq>N&*I zd^iWvE&1P|PP0Q^B7+-{lB+X9NL!mL>XRhPjKurRGTYc9p#}~ag7xFoH_6O;WIHFV z!s6vVUuA`XYbilBG@)`)qb+Ulf?mIdcL0K1xt*_S-`UfWVZXsu7Jp@{7>(D2D?j5~ zLdzQSp}a7TP-m_W@b&RY;tH8nP^q#Sfl0LV*Tkm6zJ3Scu}-%#+4;RRb_#qYEAvCU zYJxW?s{1vwALw&HzkzCBf74>UHmuOi`^aEt4Cr!Q37(Hpy(p^M3h>G}E1aYk9PzMDK z2bKXr-ALUb1!qDPne+6^n+oldmqSUz8XM7I$(P;mJj+bt0LP??z!k+?Z~uAs8UE#G zt7*c1wt+qp=~$nZC%BhN7H?o;6vww( zK01Hy-WW4iSKZ2DAYmvotxz6G-o6bmh@%X!C2%luP)X-D+d6l?XaGgBlLvk6w5R{)9p zEBp76(F@Lb@(1?~h;N8Ds)&%R>jusMG1%9UA1iFj5a%?N`SfX~?Y3sD<^CnqFCc}03*$Gt23oa|=#z4p)RpTCERB~%{Q z@&018=m{Gqudi?Xc|(}~WVjO>v|HR0rj>6y`oT+sSnYTc2fYi6xpnGVwOMUv$OtE{ z{&2kzkwO1ywVzM!kVSg)P=;n|@l+C2USYPWMcU?PV5ymeb|5iO1}2oFEj5n-kvPvo z=^0)lZBG$d`f9%2sIK-Xg0U-5dKi(}JlczYGErYB?dtDd&vH~EtC2$pKO2N!hDV41 zklIL}@X?>p>fQRfi_kmGrj8W7hq&P&7f1$An@zks^+W<97!xR>^CgSGqCcf+>I8u4 ziv=Xgz?1vGld4-^>^4#5*StYIzIqjZMMW_fsMnNvLAq+6i!W9-$4m6k9EEvHTtuuh z)OZr;*wI;hr*@!=`nNhGhe!pPM$82YWP9gRX!pSEntH*OQyKEZJna~9s*n%zuB*%r z8bs}5a^K}rQlAV1y7f^#O9H&Dev7!O4^ffCoS{(+u?HBTKYN$rQ@8v6>LLfGzB2Irgy{+foGJm)pM3iTbd1h#gv+V~i1Rp1 zv9d9*LJKkVEzdENsA!(85hPyJjbuPCzLSQ3aqtmsuZ^8defVS~SsJ8CiF+lL7{f~N zl_oe0DFD1XGXUHx2@pFrg&}#?z8&y_7>6qUd|KbkDo-X`#Tq$AZL6fgYDo+oGr_{| zNirJo9rDe9_8~(J*ml=TrSChk9VS=DWlmNB|0nXcrkjtLarr}YqljVeD+>`|-yUbm zKjylx5X!qx`XRIY=AJ;)Nk%*DyIC12j#%tSMr@VhIY!lo-)}0Am@$2QAx-|UK#=UG z7zLnMy+swH=I48c>Yp?~E+-ZRRYlHUPPARWR;ZRJN8$OD(6c78)@i0ii%Yi58FEr5 z*P#5e3RI9uz^Nh1keK6bAZNJRecH^gW5iQ-NAzv5c#(>}IIx zpuII(d~hb0&6fAe^hS^_BTkQ=SrF^$h^Foaw3`w$;6A^5tUuQ#P0oaFctiT&+Y~=0dBc}1-(kMM{ zlbqSgbjey>wB$Ub%3j_e{H<3|dbTJi?6B|k`Z&^0dY4MKiZz{3Z3GQ6>_-EWN>ABo z2^W27`AdijBU2hj%4^@kKy<>%~Z z9rtnA4o4Ny6b$AVVTpVc_z)Kv-jqBP{BS+>&bGe*CFLhK^zSpL$b-!|5be2D#})=#h>uUuhX&?8#YxBhw%?~_+zgWgjAp+HZ*8>Va__^ldV(fl%*4i3=nZ}g5cc&01ax_`R zCsxYa10L;FSN&ad$Mn4dch6UR?3sZLa@=D|+XKFjcz!vxYhcY_u2h{1$-coZwx8uXwU&#!c`%c|O_I00*)diG@?1Q7h)e zSNx25aqAkgnD#=&f(x*6PHB>5SO*t>TvRQ6Hn}HA%BpQnD*$4Nz5J8HrTHEJ$+lEJ zh6G@>7~#==5emiE9c*0-YBW&J**zG80@N66uHZU^xxPx~hqZJT@w?dtt-lt<*`ckp zIUQGIB4qW_VmWh>va7;)6V$$F*tSd0!(+Z^{^9S=r8nmG1?+O+3b>!GwCp6UEu>Vw zV8#)v&roURh7;(=ktaJ}XJv*QzV_KB7imR+vd9|;jNMt%=ChNqPiljYUMa;!1Htms z04bD9U4H&U>EIlfPxd@|l_K>4MF6fWl4A)?H5_H2ait!G!01#%1d-7vmfI%B$SF^* z8v38|N2IU7VpN>boo_RoDpKwBxhhY5F$#S(!Ug#XY^!kLUOL-SKD%VTHT6~jJlb6d zhj5OSmV4!tI9XOvM(V{%#)2FwFZaPW1aUBgZ-0%eDd%OIHGn2W;b5C27VkIlnXC&m>4<9Fzc|tq`hx;qz_lJ zI?|w*={LbBPEdhpK(_FU!paot>+;3rydLwJnazqX|oEPCIXgyzG3V55Ram%M`|)b<(A*Nw(O zCuZ1jICyF@u+JtK*Y)mHPPg`FBAflBnI}cml|Lw6i9p_Sr8z67?e>1%tNh1~^TmTT zv^lO6jV??&3LWC|M7dlkfQwr1K#ib!Q9ltBnL$&vtkgYzr(b+Car+`#j+(118ssC< zt!~F@9i=4Zlk?nQ53qh19cV$DLvNW{%X}~=Yf+v)X?k7?@Sez z0_Id!N;KxLk|~U=*`fiB*dBJD z{r=7~YJ)*pbc>?mSW!JAwqq3lP79+w>ze|mA!*^QLr4|83&z)=-e?v%so2wmU>{&Et?MivQR_geo-a`n!B>t>v(u?F~Q~oa`^3s=2UYKxK z1ypw<+z*DG!n(9L1@ivU+10jq)27DMK(sHCrfuN5Re&Qj9+g4eI zf5v@xe)oO63DB!IbVZlA7x_{zYAsErn7!Lw>=azhQEX94VyMV9A8%|T1RA0S65Gz)w}OnmGlZ)j~7Xs@u+Ia$!%YB?L-8UGYl~sAQur0v90hk zFQeyR6fu?`$#WVIl_P)s+fHdT;`6`feeV{?2GD~wc&jxH!JW7l!>=TWrKsMIs)dXuOh6dJb-8@4c6Cpv`V4QJTMB9m2298&;3s zlK1Qlyu99bNq#P43D_!;e*fBVFjgpv6m8&rvOKY9-9$>_8=g);$OT9Zc-^%|yOaIc zBRaB>eH%EGLy^eGrX@1-^aw!@0Brh!obEYxPK$ATBy8$v zrVT;QNSYPUZxTz9#$^^qU1uBN=1fUyU6u@5i%b>2)mdDkH{GA8n5dnFn~|jks0oB_ zPET)10L}Enx9uZpUS97_gOrj@gvFb6%oLf4-QiVU4i{S%)it&%b7rDw>121AZrXTr znIZTtLTV<}3TXo`HC|@xgeMkOiJs?|{z~XB^OC#RJ@>2-+x1M$(_!N0r$|w(e(7c3y(MZx-vUhbF zzB>Lf{2q2R6c59_&d_|EGouwP!q3ag;_` z71J}@iH|cH)0GF((lQc_;$viu>nx@QMW#T^kYe&J!BpW)gV5<}pCKw?^}@CjUY}4c zvr>4X`V7#hbo+9$J~Mt(N8K;oAZE*GyB?+%!WjKfLVUi`tYf3r8ztbCzb!L!bVTc=DmG*O1BuQt~F+w`XG=Y zhuQobt9R;G6wdoX9M%x7EqiudRmDPWfFPI!^l7R~K4J<)ZA}GExc$QmYE(Xu*rFlg zz?QtQ0}~+4(;_LSC!rW*ZDVe3d0b$fd7|aamy#M#*2&Nl5XUMg<SS5jX-e0QnQ9ZNk9%q~xl&jOr|NjRuV5Gwk+1$HYgLzFyC) zb>1EAq|JE|gS$UM&o5h>HM5)HE4hCHa{X#)=HAyJIxYVSeOfaxN{ZxdHH+hfy5$}Z zpN^B8qV`A9=^iA>OQVbT`0N8a z<13HS-@te1U6yfUzYT9@?~lc>tT89IXBAY0`eT()F?~*78MBIMCgpgM^ zNvuaUS-u-?fNV1#2s0Di@|s}1OPd8(Xh?kOe}Tq%_S|96nA$U*-(-j*A!6is>|gZ{ zDbwOJ*^hYaW%jV-RO)Up!N6V>)?>L}oGgaI@#-NkwQQ4qup5W2=_lUMIcH@5Al7dA z`o&(UQWmR92NKea2EJlPtXXaou}yQ&N{YT=8SG>v|7E91{%goOKjnC(C>AH~HG-hDAVe5VtLCHi$;*w)(tW1!gkqD4*i$&?p z(Hgi{?Ny}$QymDplFq?CzeFLsC{5)ND#Nx}#3w>jb8!Y3!9${vPj`PF-ZjbyY`z<} z{eM0YD-VD|T#h8C4p?W=_nZqECO7HvJQ;!e{jonqc75Fx1bQJetlp0uDbaN>RH%C%X9e@;wxlN8M=n+J-JZh##+Vc8klAE^E5hx2CE~yJclyu z>eaGLFY0wPYl&jy2ZOSPb4-i0jlOlp$gl0h?7nCjm<}|Htul%CCdr1wb<{(`p=kVQ z(p3mZ5SBj36mDI9h_k`R&+N8Gmg%@5LfSAq8XC;O#QYrEOw^|foHw8$V-eB%7Qm6E z-i1(Eii!1CQu#7VV0-O_Wyif)1%jBXo<$LCXcHc6 z;TVX2@|JVJt#9lwo29*J8&B@})w+bl+5H$I=`H*z=FsRD(Dn{dz%MTu`|Mp4SI@U` zkSUKKDwL5FqL7QLgq8Cga$Pdv5IuWFA?TjbIDJiv0k z+`KbYMKP@()X8m&p~BbGOrXceW1uDM4g#&SNwM*_R7#nm#&*HvqY{KosVzniDwLZGb*VNjcM4Z=o56RJ6jp=cqi=_3{ndhdvQcVxpQ@_xO+Krq|$866*>dxVwo@0Ixzm!PgjVU?UV6WZfh|5kqr+- z?}(>ao&A_*KqMA;!pBl65D_MBGM~!K+{+fp_m`ITT5>wrw#Ko^;#I-!Lh7h7&p>VejT&>IcR?GGMP@R=Vi5G2++Jo{5tJ#&6 zSJ>^J63{!fA$>NeKI*`+YL`jMIUcq=@7lEH!n=2hwbu;Jp}z~n9lm#B;n&I?*DNo} zcDs_A{E7FBGa9ayOjHiF?zIeo`%b8(k&sq6lc@8sm-{(T<0k5FvDRYTb1xOTH4lvD z_(4DB$#Gt@2LQeGJxw97IES1v7u{o4&)h5ZU*@{Vx6>}V+R-{_#H)h*2~V!4g_%2c z%X|X;EIkc=&;&s~u#M7JuSKdu=nvJXJVxU+l(7eXvnraGL*m#HB0K%djkBV2$LW(D zM!Kz66=U+N-NXH~Zy2U=5WG<;SR9W5bIOuw|2hjRs}en7g!%&0prA_Ck#tByqDn?{ z19$UC&6>7UwHnd@ho9=)uCCR<(U1X;N6W>6v-4G@eQZI~X#HFgD#|6Kk+2$d(XJcl$dAdjqwB zQNRG$VKuk5pVd~@x$#%gA}rJ2U6~v%P^M2Cmrb4wer~mP#nx6~^McBK|6qdFZV8bj z33LL2{E;80?w*_x?U^673En2uUmQG~|9H@kxROJ=VG6Ek|0FzYHxteGmfeMYx4F+4 zZcp8QP@_<{t5kOKuoLcf-QgkU$CRmTZalhE#LBo=qvC!uZ9e;b{1QZrgp5DEk4Hif z!a9qGU2qvlPQCZ&iXJ+}3TtXCmBuSfhK+L4WSnR5eF+%)w#PR<%!Pox*!1miRR(Gk z0-<)-(n;SPxYUIR&Hjy*8N2lS@c7to6T;g1PfjMlRUt-u>HMkR0kS^C_oF&GR*leb z#1{=0m+?f_XPTwcgB9aJbAQrg*EoQm|3h;D$*J-&cXbxtZ5e)JgLb#yWChjm=2Z=x z`M^akcNdZTP?n~~`{OvUrmUJ28%k+A6pI$IhecEWNu;Fs>a)-8Aae1^^Xrq>n{i+r z9QZ1x^2y=JdSl1RN_o*78E;v$v&HzHPH$HHDmGCL{h8r#-gptnCVWai7TQEI4o7|Z z>wz5amjxhMlDRB^5#2FB$dz6?z<)i-JJHF9(L)n#jyF>c`tUFH<{t;>lGwFok&CO{IXDKas&si+$TDC=; zn({B|%@Faccg__~)+$=x zkyP>AJ~SPj)wn;nQeqVP?%y`~k^P=|xA?t(s&HJLVx<$+fwj>M%1cN4dO7#0c8>7K z>;+72nDTjv+#&Tf%~6Y+CA{t7NqN2P=$!T2T_nAwnj+;0eK#mBQ^?ni5}w$G zC`3+Nay;oGT_-^5s7X|knKxwhWB)h(MfZm3RXq`&9N9*Z++?Pe1lvD*-NF-$>3p`*|Aa9#!xqbh`d-KV7W$f)f0#fF8+Y}6W3piOFoiBS zDc9o?B=Vqu^oRj(1-xfEYR}avhAdtulr>`BYT;JVf#%oF7lXbl#NoVcT<<=S_gyK!2W>-jr*|hqxC2^mto)Q#65Gj8VXb&>@&K3ju2h?jYwRzh9Wmc@I)^3c z)RWiYWS0l@5LQ0>9daUMV|haDURcSS)h^pI&K}=Rkps{{FJAUdbEQu4t-jPqe7wxF zTWLXVE`rs!Lxh|vGXG9J+1j^)e%)a||hAr2olo?7e z*`+OJl)AsXepwtPcA|>$P9Lly_^TpmdX+6r{O5F}H@>kXTQEPvO&27*t#3t%&4H5DCroN5MdL5@^ZOscpVX=G! z^r~fNsQ!ZxF660APx#Il(1ibsPlJc8cywHrkinq-GxBue`rUBa>D%Am5_W9rIXQSN(NJvqK`&e%jG`J=#irl?niVMz1_z+RO+fAjv@<$(yDn z#eyEJf3N;e-iQrlfT1X;2@0hrs*XXfmaXI~f?ChW?~>d9U8otnjeIQDANC%C3<~i> zq?_P0uji0ck9bqEhNzLkafYlPt^^gx!0k_EF(zGaG(1GfrhS_Q`Htqpl|ZZO_g+-D zqFZyC8VLms2svgIjVcx{FEWgnod~zkr;Zv0f0R;D#Sodt61Fc5>OZuX#y{j`1(F-y z8f$NnY!$vVeorQai{8Yr32t~{>0;7RW0?r4A9As+H{J?IlYv3GmIC7mEbe`zOpmXowq0J?PIY0}eCAroE;pfE5n*5$`xT=EE>~QE zX;AgbDkNaNAR~hWnJlS;q%y2aV@WU9Y}*z_-K&~Qm{B@GvR1R)b)g!uo4r z=@6NLJ2zBs2{%e^k?frvkE#o&49}KreN8Y+-K!n(YM4QpJ9SA(Aqen#yk8@lsC*&w zFJj5Ij+}=01^X+-t4Y{_v*Z!r>}+c^l@*TU%45$NV~#Ej7f=Fu}A)*n$)?% zLFby&Kf^?-PVesDYhIeE?}^dACp}m6{X1glw7sz*Kh9l*B~oKJOutSgM35&ZIWaqz>tM)JbTKd@8i;7YYAb6nA3&%i&`n{!WLRCE3{gTw8%&c1-N5>A`Y*rr>8 zoHZdCzD0f;iYv4_OU&f@xb2#C@x5~!mJ@{VS^6_?WYCo{w&v@KB|u}aSM!LbN8R|m zJ8_Im-YQqkgn^1yMbd3g$_-o(p0Q0z-YB9=ypc(2BaN)k7GCCUG+YXc;eU%2K%Llf z`X_}qS*R)Pk=Y<1T2yJ?ZGII<3sgQBQ2h_>gWAwe#38t*WZ>$DI;AH1-cZF*@!g0q zWI^E5b%*r08^5VWXRemNdwKk$wRs8J1hovO6()w7-YYz9X2#|e+db0eMpKdV$=2OX zTpIOs;z&XF3|U#Jf41Ri(!2>*b)@-sr(mT_wS-hlKmT%@I652?L!F|8pW_)VN62qh zY8X}~SCyO+x*Q6d^(uVFYg`-?5Fh__U}q- z)wKdd%&hL?Sr*InMb`}thaSe_laxuZuXo#)FQfboBq%30(F{a=EW9D7gOR-6#Bter z7%I-2|2!4>=`>-ZaGDuObH>hgFWUlPRaHiC)p?WXXzHX|cF*L<(~p|njy(ltn-)sL zp^i;P71rl$9&WVEU?=q=!>8cSp=Bi^+2FULQXKyLB*}?p8}aC;I=dig&Xxx^8}qy` zUHzRPm+|4|D(-=3GCj#~*XZO?Ubls%xo6I!LgND-9mjodS<^o|n3Uw=t`r_VG#2CX z)z>xHu8L6g)l@1NB(+=U<=-ARjcba{vWe)*1#GNMob0}~w~)~Xp3UYkZ5-#HmxkKE zK6He>o1+O*ZnTb!c=D-GP4gZ<&pg%Y(l%7>aMcmqfHC5dN@#8kqwPUx5B!pWzxZT*3Ps+X+q3D&Tdd>B0qd4VIZ`wuHilC2_``EPk zxV>#-G)(~V)d{+nT=}`Iij1ZFjkwF=rMXW%7G)!&fb$P5dnZ-stMs@@%rmNR-~ta?J-v7q3HiBOv*d8G@Q zV$xt1-ke}H_?%AW`M0ssVLi&}YkXWNcZvc-S&8@&nYUktQrQ6_+qV!^y&kMSDWjK_@>o02F!J{OO=#w}czoF=RyEUB z$Tslm`LzFqA7pBG3L3c zxA3h3Rqf@{K*CKQf0gjjZ`|u=3B5h78#+Ae^JE% zS`qpg=W|z3!AAerBx<@a31ST%-ta| zN!g*X&~=&)>csg>s{$-WjE7g4;Du0=h_PYV5!&gxy5XzkSU|aXjKMu~rvu z^m)?(e^VN}t{)@Rt(r-J;50b$LyKVdH;!EIM8=w#!SKUatORUh0c+yaA80jxvT5CdoqgAFzMbwQfo=V)Pp_u`49y6RP)vk8_DkYkFYo z!#f-|^H^tUZ`Qy$&17eVrl}&{MH3gn?carkzSQIy$ZypgsRfI_h%7|s7dJDiZ7Bak zTObyaCC2pG*MA4$L~DDG9TjQ$dRhPC14F+RRN=Q&y+ST2^%X?lg1%)KZh9Pp+UGbl zNjk7$a;7)#pRf0kU|zYf@9dAzD!9B3lq6jn|Nrk7+7h=_r*Kso^=yD+p>E2;&nI_hBNN&N0ZmAUm3PF74Kh!l$o+ZjV9_& z@|;?QD7mR22+SAVuEjGK)%!H+e#a((kEcI~kD`lMEd4U&5Pwk85q~9Qc-k)=z@QV?%<98+n`+-r$xSjx1qnD;&qh$yAH>HcUUJuLcLZSXIP<`^n$(xE7iYz(X&-$EKQQx4KT;_#>0f+Ei zlSS{24OZt|M0f;?z6;*!m-EcOQ6&LFms7nQ@S$19KS3Ethbo|#&=i-$d+CJv(84r5 z7F}fXOXiE{PMlW_#VrgINgUd|zIJc|%cY7GU+}I8yTw99k&GDq^PEq1N%<`W!b>vP zlZ6?Dh@^-9Lhs870+}aWmmL!X8A?OwTfUjpMhSf z7Ujq6rwO3|^<-ZADnOV7)o`SsT48)*coI8W5yuuHt(otG6}84D^AhCix0}P!y?8_a z$_US;1W1~8!8vkm7wh>6`L>Q$2}OEzho-_Wuyo8{rpB=6?C-<)1eZfZeJ;h#rb+@L zW=$Rv)A(eYFi$9gSkac1c=&(6uHy{8ozM~~d&6rNE+~dZP$VY?)KpRFV`NO}QJ3K< zbr9lMGNBGyv^cLKLZU!roLP=Ni0;uh*{=4gJ zT7k8xYUV8*@IyRO8qQ#~$$ntF%$2T@I$iZ8w%k%UsU;-M^oR=9qpV*l$!%A77g-ii z3oH~}B699G2mG^Gy=!%nSm(tEYj| zyYL1?76Kq(CPFfI(|0p~d}Th~vevE$?In-1y~0!d!7W%v)~ex+KXX;>H*4?dL1z4a z*$0v0aVd9wg1}LJwx9;OP=nC|v$5XA)iN0!t-bSqqNQjyb(DGkwrJKc)fqLF8hOh6 zFt6Is@y(84(7KJ8d}u$A4MT=hG#pZ-v?zF#9M6}x{#xXlS^D#y>=g$5;7lC;QdefY zVI=n|Ep9qf$Xd55WR~ISJ?N7lkeme1$_j!&&y{qP%AKi$hkdm_+H0grxDOU^gNaPyC!as6HLwjQcSGLQ;Wa_nSj z*FWh`s(Vbi>M0bzv=f0OE{~1A)WHFy;fgX^@MMf{NH-^$RONR;?+c$>9sOfRC3P22 zit0|?w1;isaG0-8y973>xa8W=hSoL_O7!LYkEU=$l_kzpz@xLU`f9#lKQhfmHx=+)Wb2yfQXRG-7%iOArL(=`TI?Z#-y`5dgo;GZjfm_ zcA@CGiyrP{ea4z2GU0vHb&V7^G6Lv78w5n^V-@D|k<*YfZ{+or7g$0PvAaj8$ zD7FG*g7Y#1=%on54AHL)@n!2pM}= z1&oXiP4nFvP&ZIHMl+{e*`{ObwE>S$`-yWpW=~|VjXE+`?@~dVB%>LmQ!LyHFE_^v z5z$?$Y0$48;sLueT~*!wpnkTI-l?Ci9@x~CM4ha^{G?+*OkZAqICUolCdc^FqptX( zYkd)wNU)`$jiy$Ln~DCfj@}o~+>hr0&NLOj+z(=e($3#4l6~ z04$RoA0FnX4ladl1hSdq>kFxWVh)LLp}n^al- zh1N@9CAoZCVP|&#!zHE`v^gQ5KVqBx_ww32z?VOl;L?rpWwpH1g8RYeo;fm8I{mvVYDE~x}-A@fk35EFBfNfG-?T@|U(u_XkC7*uPZo@qIfz>#D8LqTH_@n=I^~Y5HA&I*uI_ zgEVExsO6Oda^Ion)|S2OlTT8|pX@q2ZrJgsHCXeqQ$rk_2f%2q*+X6j>UwPyz{vN3 zJQ*HKW~@R1{OeJY%?VLLHep4YKe~0Vv z5;;JC9JkStx|C3GC=U?Ov4^!i#QSkMV-ix zsOE)N-BoyN_1^d6!HP5!wjH?!T*^dU^PSShrbSYB(<$-zTT~~k!E=QdsNRF41848G zpjGtxk(&>EXt#che~MPeg4P~)vsyYQoGzv3s{;)lnC|BHHChrwc+CWcJ$k0)|1M#H zF0#28oBNqTHps6tUDL8AeXBt;6&l{SBdm8PcBz_1YDPyh8@+)a%J(4k0sBv%=Vp8# z^poI9)7Ew!2*cSD8r8nE$bFEeANmUhib`EF%)Qg(>|(c$k6tAVq#)qY%~CvhKbaoi z*<}BR_C1$wygk<*Yn}y*Xxo@Av8u{j8F$*%n3?}e6;Zso+; znKD=Z^|}Q$_4wKgJ!0MAX}{AfCAahfCg&j99H%-3eMR40XqIS0dzZc6E0@}yeD%{c zGFfr5e2`**(nMf%%R@{)Gxg(k55=7+wZlLrkNBUs62hrd#S{3COdp~|CVZ;6<7}k# zR_u2gIaldYBpEQ#@;S8O+}J&RGG4q6R&@1!7?yk2lju|)PdH+;vPIH$p>Q|ZDYOL# z0qb5MH(M8ejYSPFDfSi^V zN_Kjgh(niTsCj_<<^qRoq&|v*ie)wElw0g%#w$Y(bWga1sffM5f`SqLhc@+FE_B2? z?Z8!z-BmK9Jqv48kz~^{8VU_4wrq2TlQaeG*8{hT3*-+nITkwY0|6I- z)ZG39tXh>^8RHh@?R?GX))-~%8D6k@vD6#mTzhfQ)g6cYFA{neSUn+9tlb(rfdLpU znE->-j&ZY2`0(-~21ZySB_k$NI4|(Il-h8n)0+2bnE*Iw76kn9KD~WX2ngKUh0m!k z6|Isl@Ql09)=4)G4nmpzH>iw<5NfO`%*_St>1$)L5nZ+lAPc06TF1g(fQI9Zm4=;x zQ%JM}rrQ@%>#?#Yd+l=2yAy`AhKiq_A1jgJbCzGTGKP|>m){1dE_pV|bRFEcRWx$H zdkY+0#!3VeIu%Up&p(Exttj{UMEbtQt2lCnMIW#(9lFd$u{9470`qbq$5m8H5$GLX z>ZV$Wi)1UpniVdRnxGLOqN0IrXW@;xSFUpaMPw0HR1TIoEcN|wqT&w6PA^0C(t{QV z(r!Ygzs@LHT7DN0-+eT}7h7Rg47L#cr^{JN^=hw$w7A|KEEvm*@bod*NfO{F1a65< z0MC@HRTsP=H>gwg8%2&!H%}CTJfmobW{UG;SSZ;4;QT~j&~(_8b7^e(Q_C0jpU_`d zW5jQya$!>0mA;q#yWpxEQo@L%Tfh@LFPr%J{^jXDxWldGYlHr|&dz-`6zxnBFhlN| zpAXe`{&TlieSL#QwsqNAE@+Zq_G<*>Ukx=-*HaLwYM2TJB+SAbIcI;qUk7>4@cz8V zQhD~nB$VJwvILr=VCp!Hb(Ug>nB;jhATu*cdGB99T(6>5S!Ps4S9O^bOXaWfjqRsN zG<=WBMB2kYB!e5B!(>ZR0;G=3GBj0Q})_5JL1xiZ*_t$89|Y5{@vCRpa`E}rlG zu-9O;po(*~`8%HU6npwQ96im@z`{U>izYq~eHeEc+6$(td7$_hAeocp*wcx5#)d=O zxwCO_M=eYq4~aEced(HvGOhW>7Ap0y^}*HEYRvGI(EWMSz?*+fCM%rfn|tR5o3_>R z0vmpi=(Xyly?!ED`hT|7d3Tjkx0{V4?~06`$yB>;_HlQo!tc?!T`m6k+g7ecE^wN- z@B~R+Hp&pRahDw*H(7)Z6x^IIl3AE{RKwZOE1#ijqMA&4V?tKJB|pQ(sbSYztYYH} zl8Q!Bl}FWueB~J;hpq4xIOKp|FkB<6My|Wc5 zl>SWz&qxQdmwhI=hfN&BOsNYKYlk3{w1CdOA`LBp`rYI3ebaaaqI^YlREqf#;cJUD z>+6XFL8`{dA{5E<&`Tb_1$exiO zU9$p~I-vyaJ^Jp^h@}_|?&?a!7umL=3c8mAtsE|T4uTAZ*a zkrXt^378eWdsZf=CU-~!-01a7!lEP z^3XojkBF3s!cIkXS z#6yboK8M}D@ZnSB9B%M%Kf@facEZu$Z#><^79na)*sZbfK>eG8PfqE^To*v917dWR z-9P#VP1sdhDv@W|H?43vhNiM%^{oT=%QDrEn2%;#n{{->{KgZ1lc11;m)gP5Lg|1l z%Ts#AW$C$KXj`I$eXDaq7hzftSe{7mK8fN$JmuZbDM&iH%=X;a=G@Gp+1L$)keevmmR0sC9D@)Lf#-!5CG)N${}OmQ4}S?q4W`vSDk ziW4CPk8G`!(+CCLd4{hRn~eGZh$Je)%o!? z+XX{9LmDEW;%=hP9+6)&0Z8mm7mrkacaSfN{Ng0LdBMbj6$btH&RlGKlJy%N)hlj+ zEdlZW(B=SnGs`FMZ|U>=H+8}$(a%$*Iz`DdaO8C_iBr z;*1=D^|C0V*82N@1=Yd6;j0GI?`!yHI=j~%7+*UCq=dhcUgNGIXXG>K#4+0viZ9WY zg(5zp9(LhBCUW0o3wQ(}>xQb$Ep$b}Te?mu4^5?#aU?O9n1twhdiS)2IP0~JagC@D zgdem&2Nm`FTQzcY?4<4C5xncXO4MIP`zv$LRnyZ293_+Zc6cn;j)`9-`u~_Z%cv;3 zH{4SKqJUD;As{W?-6fp@f`}j?Eggd*-QC^Y9U~n>x70|?P*O950|W1Q{^xu-Um0dS zv-aA1KYQQTb^op&+^RT7+-vEoRkFSoL~va~r?Fx>3=zPb zFqHN^Qyo^u$IW`r@gH=*;r-sFY$Usy8Z1(*^>CU~usdX1Ww!MgNocpaBoCh95jD5vhKpmfZ;Mp! zV;+|m!ZvZ9Iql*sZUPCc-~-ZgkgU{3G0J?Jy2Z~)X|?r1;Z~(Mjv))T zvx-2VO1ZGmNn%>ajPUYJL6+>ng1=A3w`t=?;^`ObadEwi%1=gf2$-epEx5tpeQZpP zN*3cn`fx_|geWYhh7putou7^sqOCu}2YxD|N!ivT(!W^FO)Z&8J}Ic88cLvhCJ>nV z!jDgLk1-_@FBH?D4>Xm_c{4i!ngAjSrh zqE&jvg=K2{9&ZdMUqi0HOo5Q_Gz$GK2iZ&{r1~{Ul~=h^V#iDUr|;FVw;yLa$4SOrn58+*G+f);IY7SQ7gmL5#EY>bG}2l`VXDfoB<8!JwUK{mH9uy z0i?o@bJhqT;?_4|Mrk(pWNET9QopDJe|_1kDpLdcF+Jw{p%# zdigwg;)MwGeZZ&sxTt?MdZ%~bdd|q$@XaL#hOb7tDZ2P;x2MtdoFaI2q9aBW(dBuM ze~paZ;5$Hz=w)T|35?|{W}^SYU@*|&KivzdSwfeUZ~F}yBuqZ)HWiqzz7f)tq>N2Y zdel8E^lie1zW$+j#=r@hdFI!S(gO1~Y%bmq;(<>cSOEAeR+kp^YtPx~BeD z{6_yyo>vbDTJ4WMI#Goe2u{;+((_Q@N6a6Kv7Jqc-<0DcGtq%Gvb>py7?KqrkGtQ@ zKCcdaUAb;a;HKrIyz^2Prj99u+TUpy;y+51O^|s15kjgWn-JD-f?fblzOv{Egml83Mg{Yp(5LsP- z?GSJxfYbi}5I+CS-Dv@8CsF8$Y$Cl!c%ktWsb#A1bC5BhcK*EtXW0M6_IJi={FLL` zr{nr}Dsi4k{ow%SmHl4fE~=}0`HU4lH!><2;G5(d}D7GGREx{v@S7CrK@bdp@km&eG11c_|Hs=Dtj1I5%PPXRg!F{7458FN8hh63X&~3k)+j8XwJQsVb8p z*S8NK1Y9{dj1$Db{j+@h^!lho@k1tYd2vC_3y!aCz#sG1mYMr9*`*V8clCzLp=s@x z>|el{hO5568uq^XX6j@~m3Na4c#$n@j6oX^YJ*2J(c7# zNJ-ujp|MSx9x&;NE5Ilat#AOGq1&Ea;2hP((%#tNB%$U4zKqDbq}I@=yB2;S72F@W zVYn7vFPVK95bo0NMIsKM{KwsPp$9MF0d>N{<|j2ymDfD#XN>LU-i*DudX9uL}XiHE*ejHAOLd@6g)&U>YfF z;X?X3-k4`dybikYvLgN` zRm@f8+rM2Zfwtnvzd`4==+>^Kz%4jL2V(8xPM_w^rFJtvZex;2usnI@8y#(&6>4lz zCFjXo-v%U)6!2UmyYkta32vxhQ}HUQMdGP24IFA4>)^NZGybJKK-cK7`FSZB#}%)Q zaXgdE4sDrzBzxtUhQuv9?v>;21^4T+(2O zmj5zNo0`MP4dCaEMkm2z;!GYri8hR471EIo?jxSZs-^>`zb9FPAw+W6S?ichj;kQ= zU%;84nXUbQmT;HFgSLFy>CJ{s@*Io_CfFMJDB`{u)407!tfd zazkwu7L(W-u>)5Yn;H!^fQjI=uC>*kReMO?R(5*wq^&)F)EC~#Rv4wRJllL89*s#m zXMAT|=2zK~{`Cri5+32MtKcaGn^%$xhbBlzbi6YNFrzsc2HvYK z$u_n6U-3P5s_@rOaI-$j0P-6oi2Tg*~}$lJQOF&2*(-!sPAkZNCY)zw=@F zdmj$5k?M%xFwsagZM^v>ua5{PbZTsEe&B)?(AhQf+0svRLcs6SE#$&c#v^<~uX#Z@ zJeXp|-SKlyz8lb;NfpEYA%un~bALHYHLTUXI?(t6P|zSwTB3@`y!Z@3O}BoPmEg|L zR$CXvZl*PgQw*&RI?o3prC1@;Gi=kyQhj1|)#!xM;M%db8b0<;uB6<-WxOfL#y@}L zyuB`D!^WzCQ%UPoZ>y7(BK((d2ri5d9g)%FPUh~YRY6V~rgb0>wsji@jflD_gPiwDO&-2M@&hAWa(fw}&N&Yv|0d47){&oIP50{o zKeq(=7>4@7us@pQ=}aH$Zoe||&APtG)m4nX^@Wbrch* zA-56o&nO*1L5qW(HypN&7M)#oVwBpV)$Ou;+on64$j0)*Ao8o-ANsIrdD{y4Q{)70a^zjk6>fsO8DW^@ z?yt1=U+Wrgi)h~hB2q}c#!#np^T)hzxvxC^9550}7ud`*#*hh*q&}R-U1}JqUi$!}~{ldHNUn09W%81;E;QqwjX~s>Ci`zqLtui+tWss9D@rc_p#Q_bN?8nsVH(5%=tA?#Wdq=HY?$cNCC_fXJOGLSoY#zmm8En`%(d_Wm zD*)rCj1ye^>fU9a9XsQ-Q{$wt59R4L+!}C7WfTT4;|Dqj%^^bSM^)Ul zL_?K~31E_$CpWxF;DgtJUHf3}qjrkhRemRa2mZBLj8;Ep^%qITjM1xhPkd;e5C388 zqP3<$k=Co%9Eq-@NoH7rJ}ldQGS)SE+2yr{5T;qO?JVB=l7C)w-7p0fM5QksnYDLS zTdaB33`tLwS&VvDr!#(E3V=0@Esu(8KFMPCpl#_QW6o)D-R0DQrVEh(LDOh^eua*u zsG?ntB?B5Ye22gE1%eu@pbE04nivl*COSfSI;Rhj(vg=#Y8=pXDOdwa&?t18-fZdI z*^3<~iWZ>aFsijW$Gq&^aC4*FV4sR80^A3mQ3tdBLHz~5;u5qx?hX+1ZprrfL&+=5 z-AZuvH-Pphe+O-8M&zTjfFJL;j3E-s-xzGUe2piN#5ggq<44+hSB!}u z32eyS!47zPi_4ZBw`}zFw@A5}uglvfM!o?xw)*D_|BLgd&+^6av`=Nxo=pbvqkn%n zaFsl^w3*9Rv~|0rBpcC*dTn}0RuHC4^xzOKwSiw4L#Q`QmjU*?g4I&s|4wX+A^g0x2M4RY;?O;-jsYe(%y^7Du`(f~Hyr!lFQ6fA7M6;Yo0;Xz zu}Krp!d1*%s7v`|wZ)2@{i7C75`c=#jDE0_fr$yz8g{N)mnrCbBiMm`b?fWo*l>a zWM+Q25!@FvP~#9?&hznqNo^eGKNi|gbbKqpEo%iQVfvDljtbq$xMM^0+y6>ZnCAmw za5_A_Hb7#ihALLR*JzPvTPgok-*;#hF@#AmDahCtF)f>C8H^rAY&bkRBSne=zKE-{ zw!Gb;eI;e|tGM%dPZd3#2NnheGBceVULdrEqTpq6Y=5O^HsM~o>7PNm8DqM-7%v;M z{E$siBy@zF^1~iB{}UuK0G!cS!2B6A`IboRW9qWHs~GaWwyYm#;$0M7vExQBuH4#S z+R*}m6rzqJ$usAXfwd0hoG*>umr7n83;aXa3fgAKyIyCO^1q;?u9cwY>0}=Ez8N&F z6b4t^=?NMAI9?a9>Sc z`ncml%Z6j&nnwNa+r6Ryr%38;CE~fvO)lL<=c-7u;%>&@;eQB^R;wmh<)g1(|IAM2 zH_8oRMkTcWtDgA?(4RavS(sNky&{bZNS~aXM=Q(+VY8=d1;9IoJTl`6f(6xzZw7|a~ZPD7!JIv_8FufKTNasC8T^1X0{cw zwsDA?diP0LE%q3(eTXvhN z!xQ2pri$`mPGY58pn!T^qw}>%m3vzI^>_T! zUD1<{z38HeYjR`7#)dg}qmZI?nNY{aTB9~Ey$%}%T+Yty7aDxRmDPFuzSZ5SMR7|t za~MvR*A)UiZkk-wbJjDd64bo;i>IeyLaun+n6~J0@Kc&%U14fz*Oc#`Y;(^0Bqc&P(CR>k ziQD4}yO-=ie!U!LZjUPCOlE%>s+CGnhc`>xL$}%MQFzOXf_xC20cC%gp!Z&G z9rA0?gh`4u$f~ZBCmG}U&bu(h2A_Q{QYhu%`W5y}KJ!vUhNsuOH)CR3e?_VQPRP+a zQNHES;8`?vS+)rv32~}y@hVa1s`NehsK**u1$;mN)ONufvf=%3qf55c zmy)`x!OIZ$$+a1do!1I-1U(qOtNtKMl#|)-w_4dOhlZIOOL7xdk-niTq3-7)r7Ztz zr@RIWM}8H4(1xEaY-J8z|9EOt0V2T%uISj!i)PeYj)|KVW*b^U-h6kru4FDJI8r~N zK7VA7n)rcmuKx9jVBz(_Qv6fu89?!DIt!RF)5=0!0!-7)p41 zA*^w2t?PK%UK2chT#X8w6CAX@EiQi&LJM`<#2XimnqYTehPKs%*>v2He?NiTx|_It zFbinLga$MbQ1u1zp+2EX{nb-y7Xcc%H_@+TNmZH)wo;ay4boI!#LMBm@%zGI-R0Q< zNP06*0XhIj@d-5Jj=sy*p`6&*?iFH!TK+_1H@Y%5NG^C;hCZJvrlv^1;$MQ=t+Wmj z4?>*)oWfqgwQJzdv|P6D$Eo2_>}}cVO7^*S+A2!=BtQQ}FXSOk@#@Vx&6=MOi>3pQ zp+#*xdYDYC6D1X%bnBm3YKt&f%zwLoP}yEIq}arWR|`#HmTP-rG^T;!|9o=s*_*Mk z8smIUF?s`r$1`kS^Pb4kBb4vncUWI z5-WVrjK=#T%lGJX#6cRms50)0ax1dGizmM57dwZL<5{JA31v5k>-gr>_p-U8Z^ z?Fv)fXZ(Q=P*yVPzc~~vEM;AHfqcpU7wHCW%EO_gp+V3DRD#z1MI6>4l4{aq`SPzF zjnxE*>rg_r!4Gx_67Z4?5Fh_t=mvSpGe@dzr9Q=@vIaZ%rc5~h{upzt!}aJZ(+10- zQw3^58UA(4ai=8{u9J6b{yWdG=2d~1k;zSEvP40>Sf#IiT`9j24QSY79Yq6x)VHZJ zSGqLc)~dENW6Apz{$-zu9%5A?5-!`_w7ug1?n^mhka_&<@TiHNpOYFp7_aDDtdlAz z!E|+{$=9EHr~A{0b4egk;?#_;St9f>(xxb3N!8yAwTD_PMGZmx;Yn3~k|vAS&jM<+ zgtpX4$eY2*rVmdtxnuW|uzq42v^iy(#;J*`Kz3zOv!rb3dP04~MXQP3GgDeIMl{8t z8juOx|Ji9oEugMO$(3R3s$ZtZ4Myg`aPgz3eD; zY>cvSHP(QtfmnCIrA`-SnbWQnqyV4-p83`N#qr;GNoN+OZfDE*vp7cHx2OZN^E;pJ!#{w&Z)-eMsEX*`OR461NUT zj`{*SGLKF60~^NCJtdscRw7YV)LVsRb*fR?o)gJRf$>(Kq8?B>bw?BuKG|qwjcV2V zVIE!*)y|z`1!)lzV-@2fazcZ>%$NPP{U+b&>42R&sOr!PQ44xohHmY1ile8=Qy03= z{H{M&6%;Xe}*p-`X|)d3!na_x=-(&tn9G2FQ=? zmuI2g6qaL6ABdrXFLz-22Ab~m{x$k1y0fu4a|1ed5Tv=7{f2|ZbvVsG4n?pes+ZN6 zaHj5l){JKG_5)0mF_ZnS^Pdp6SwI8ob&&pV0OcB4?)S{?chVR&LH>jMc_tPM9wV}2 z7=%n0rM68-0`piSwC=3lvq;peTMQOby>`k*ICluwd6(P03qE8JrJ+X=fKVX#mX0bg zIyniD+kz6|BoLf~r@=<*E%{n@65}QpBV*{2bCTFOU31jK5pko`D(d&X>=Yfrxen5# zK#5exfi(^0lGw$n(WdydbfqwX4oOYIxZyU6$2J5-rd~MQtoy)%;v+cwGrqtCX$=TN zhf@+`gC@_arg)W6JCus}UL%@z91*Fjy({u4# z4nUY{(XqGy4-ledVPy7{GNhJ$3x7mUYKWw5lc=EKwNbxZDAlo+>_)vv_4g&BHp%mi zeYY^BF?`w&13PV;qGB~iP}JBtYV>4w<~nCK*r_)|4&AtDclFkbeWk+$2^5rAe^4WW zr&-x6%9Ri;jmN7gY?wRo`v~H`-Vs#8J}+vtj(!6YY>Gg4i)8Q<2%SpAcuB;!SbbPs z%DPV_*4}`3`=?ZHQ2g?gt(qArr3`u>mw!<1_X-J~q`rQeqQCI=YdtfJFmAZR%%JFk zn9gX;hX?IxUiDX&#*^7a_mnijezb4u?gXhiKF7{~luj%%?1>bbeQ}3TZ%u65@b7p0 zTGC;#ju_JQfH$N5l%8S1%s9buV^#fbWO;XS@O^g34VlIC;=LrTd9voyn_L*=G!S+G z_&_OJ?*U{G7i0d0d0Povri+U&w2Zp!ox=!ARJVXc_oa+@|47Ur*|UamBFnFWW=Igs z2fe@ZfdN^+vN~aviFgt}G}Fy3)ZCd`aCXh*wZ=tX?@ivoekk92w)os*>Cw zAI3BTgqJ^9$1nZ_ae~C!Vq9XxQe%y-bMa5or@qpiu)du^b{NsNZRJY;v@V!1%r8r$cXd5;goCRN zGj7hGYk7ahs%#*$c9bycBH;*0jqJUHDc8s2%(NvROOV+6lVG4=-mO(RI*;J z6X&fl1(G9sK|oOe%h5FM*G4-^yZp1#s>qa05Y!{jky5Cwd12Vu*50Ofew~^ls%}lT zLiwnX)4QtP)1L!EuWP$~>cvMoCjaL@jC>i(IUrCj$KgN=q^@N(nQz_t!Rg9AXTije zjH`lA)^=RzeDjMP?9@&Z!_fyo= z4vQoEhK*x~{n`DmGbj;w=P`OQK>W~Rc6PuHh{4cR;%KFJ9IC2v*T}%?;y1mfKQv z@epFzgEu+w9KLZr#Vc?^4_YZUb!p3)c)QNhK$$lE5)+tK&Z?J7mdH+{@}U zTA}m@?EsAK5a9O)ox?%-QYmm(aX-)m$f{}SYwgtsnE(!^_OR*P$pr*Sr}sySuqDx9 z?SGL^`6l>qkIF+u;WttB({LIq2!1k^89fEKj9i~J`c)LjZ@jBP#EuNFd9nV(&PeI! zXqj_JL9W?<7|CD3Jgvk`+rjzNc_V*2ocx@~3!X($ZINf8mJBi10&=5xjAnkMJuTl6DWd)5~w%JEMujI`c#x8oX2-GZc>Qdm2aDu0NW zZFD*Ml{_`C6_Kx@I*Yw0D7sq5)u*;)7ATKPYW4M)S7*QEOo6J@S3zbIZ16ydl3zs4 zBal^H^XT&aa9w!qg$AARE){vC9k~lP(IZt&zMv%0ux5z)mANiDcR59Ksda-;VfWbl z--?iC-j5dm-%Z++!c37e$$JdxzKfgbfG$H0Iy4;y+poO7ON;AG?u{KN6FK%H`>i@i ztdZ>t!`5MMNiSzf=C+!+0Ox}Q>v|(<24KsEy`n^`&)X5)3DhYAW(wuel-~8I&c#qB z7qZ<;9oFA#P~ZaM=hZq<($(HGZ`2UY4v#ZE1S*@!7Khk#kgA0gxxsw zVtZ3NIt_7}OVOW~fUXm_@y&~^<96RxSN^mNv&_d65g!@H-lTnpy%aRUjpR)c4q|)s zI9r^u{D>GCssA2O_gm|u$T+#pGD~|vVUz!aqRzTeWu4^W8ztWakD;SPxP*)~@Q8WjFp%DQ zf|TAG6mqxMS1dFSchQ$HEu-4%Y3UKPt9T2WT2%Z&e+${{LR&Ssf-wju%T<`s*~Iy4 z3$2dI_Uv4pkHVvA&YEW%`9C@hT-DHJ=wFTK*40uZappI%-icBR(+>`}{uT?F3-)Iw zF-GC{-eod=>~l0tx$i>C84h^){8aV(L@o6ZpAOr#7S^S;9n>yZ_jxwhb5&KQyq}Qq z!oaBvNZzSExkbjiSiavDAG*~}d6~(HrZ9w|UyFm&|0%{c7fdxw)<8KNM1#Nh$p`o` z!SfrvpH16*mQ2Ry#>Wj0@3iUBW7LcQD*R9Zl%z(_-9dI>jZc*l-Yuw%o}6<_nH)q7 zn~(Ff7E5Ui(mJq0O@LWWtkV4p_C;Y|V8isLP0RJpE^l3#m*|aQu8c0qloWQ1x<-{x zJlX9c$%qF=<8v=B=@T5$nMjvBn9g{Nm7pUvsNzcr>OTzio+V+1+7v#ePJJ_WjNMJu zA#H^|kADTK(-nMD-^3TMW@i|(WYdDbb~LvlgG;Kmwgz#^@<(ztFYl7Xv5IT-h7qV( zSb#ZBi)(^Q0dY>--#u==s((;d69bR~05ur-#ty7hf0QU<^hChMWGg z3>yq|)m!^91ZJ(Xxr^@$mJ@xMC&B6=YUmxTLF}SLQ1Ep)r-0LHRb|G zHGgFP8=^&y?N@fR2bn`!p6=kJ$C)SEGPDva?*02%F2I}adez13gI)b&N*myXpPc@r zXx7gRWu^-sa@#`VlKW<$_X8yS1g5_*ni%be&~a$88~x0^+TnM7s}e&zQ&ZLJB{b-JUnZ5fSRD`ah7z0?8hww&!fSX z7G;ikPxR7DD{abc9~22Y*nNZ1xl?7k#s+0nxHWRL;TS_cK&#}#FC{E{LfxkmYCElD*(`?Yd*^+j=fmzp8qb9x8M4bQR*A`6unm~_U7 z`1TIqH^h3?gg!XBv^lYc$LieL*Hze1GPZ3C#MVLP8DV=0W>R{%ip|Ii-xj)vlkrKz zN&b#`OH*{^BBQR3L4{^vE_Q(n^OW(tUJaA(y8U= zI^NN0d!OSvm#Y{#uh!z0lECpx6Bub+pG^;$bbAunF@$cVFH6g{=qOUlFz?g{YsA@w z%*e3H%u?CNHO`$sebi7A6CLS}ixZ_6x`1LDh82c0-DfVFR&Da?LF?rcgG^B3Uz>uh zRHemDEWk%*m8KoPVOMy{4 zv4$wdTqAD({=T@ln0hhFMH=__301-_TNwsR%0kIt$j+MlD{B zb?{+z@jna>*#nA(^$%EM6WdlV>q;#6L{e?_#rZ%R2H*q;pW_Bv6}bWEe~>7tHdq`R zQe)-#_mvL+iP=hyjWvOI`nI%;K3PlqFy9)l5vKZ^uAG5ETF+D}%4=f43c(1LMyKub zvaZVq?Dr|$BcCZga8blHm~JrF>RSQ&Akbrv#oR!U*wrOdzPrp1b?>=Dg3`->+c9}yHt@e@+k7BJ6r_Kf6@7GnbTjw!84uR(?nDHo zdQ*!O_&Cw^6}{fguiZ?j7%x*)lasY|#Iso2iH$#_nqaqyYU!Ek&DeKkIRfR=J0n(M z0E__L125qC9ph9pZD8JIU4jb6E9y60$|t$>m>@ni)C+#$(G>aAL}zU8Mo_$L=aN)8 z1~emK8f@&>f~=V;NV&Ggt4|BS24c&COn0i-0Ruy|BP)*<-Ce8q-FJyL2*Q;F5?IZb6s21F3 ze-X&t(GeINO?3Zppf}5@JygmzT}41`Gc%jiszLx#r8q${Wf-E!02jva{bR@{+w+Bh zkn3u(oU{BgF?Cm5UB5QKc_n|Xx-P9pF21xzlHh8SXoy_-L#H7j2@_7}QA!&Jc$Qp~ z#Yv$~mqcNppR^65Oy={MyAl4%Z@tnd`DqxJW!juwOS5Cgm%6N?(pvs2;Bd|;(`$0w z%?JXl;*!H#v1;nWO+fKi*TolRRoM;glXz~VP4zC?hOyZT?^pg>O~4C@`6pxy)Jw5O zgDi28&JhM3o?Rp6pU8cGNa=(He5y%&A^y_xo+KEg!dX$LLl>V>C5kGw1$1m5lNzO`bAFaN2@_REsIN6&j!3pWC#5?uf_oR7iSTcyc z#WT?S+#2+5(iBOg`kKSQa{ps_vZV>CbXUC>Fp%MNtvnMGmfTR%KJXB!6PQwfu*W>D zfYG{Z?c>I+v!)XZ9qV&-43jR0(T6Ow749J?Tb$oqyw^Dx*=j9FzP)w-;hNNXcwnIL z{eAA-ZPnTXin1|56uz2Vr0}-bFPjQOS;_IjT3e3V=b~XgW7k&1bb8#`EWZD@Z5#iz zrm=Bdbx1JJ_{AgMYfZ*v8j&vh^g#}4xxGZa=}h_%OnvP&a?!cAr#z+k3+oOx@fT!i z|^Pl;uU+MR-H>L(0jx%F~sJsFK$_F zRxUPV`Pvj?uO)1kI>&DGQzL_~8$an@&RL*fiRDpyc6osp9M93Kv!KbpQ-0Peap4wj$W!cUZud86M2U%ldWlVkdh)tJ~UOsrprsQ*Ig zw#)!Na|Z|dnXFB>5<30@Fhq*ucS^N)UbArAGU1vo?mpw1@?d+EqH-fRCTDUGmYa)+6hweh)?aA#F;9o;d-Tgb9 z*ss4qnf?4h?`iB_pE4{N1A#SY$$xetrAyXl?0^5m*u5>20eZS~e;_C-5oRcJQ)8rb zcw6yy8E{abY!m6|iS58+Sq-U4(32Ocu=q80Bsve_=LKF#xff|(ywm6WR#gI7^iTU# z$hgf|Sr$7WLxNuSl&eU^gkn)F9lv`h6^C)k9yy*(zqR_5Y}uXQKA|?C=q5lK-ssVt z1#SfSkbWh2Fv;Ry9XV+{$-2G|J$H+^g+6he01G;_KWfi?bGET+Ts*kut$SV<%$TF2 zc96CLKv0$7t~MFhfH{3_>GMS-*KQgj`RAm1h&A&zv3KHjXZ-nT8 z8D`gxqkC(xO5F>U6sdL^>He4Vos{OnEO-#XCSHPs78wo|YBD#g+K0WX54SOkPWY?S6 zi18KURI4f{Dtf2`8L|0i=kd-Gt}J}r2Hn5i@5oqTrT*z$`yon>{K|;cnEXWF)EUb0 zvepFt8~c8DLY6CVv5YqPXkG1kF(?Up{P-3|j{J;)R-3pT8hx=Lp{>-(`M0eWDYGyI1~I;QS}Z{7THs;3NgPf(VGp ztW~2)7%m;$tAnT<+% zQFpAiLB2Cu#VjbL3hR95?)lg~WN97G?^pT*P?opQT8w|wc z?>E-l+SOwMeTqdRiwTAg=V>_KMajy<;%-oI$;2w!aNh5?c;Lv(!8%zAa*a5keeNK- zige&zJtvpqp5jh)P0spqaSU99p2loe}e39;9s5d98!c6K704mJ${=}2A6C5J$3FHTBX-%ReWZCg?90x zDKA1+)S+-8PD)$-LHV-aVC4F+b6%>XVG03VKbmm&KXZh`52I*2(QUhU5$`q~E}y$$ zh>=Wvd41pV7&HR7k*ACOpp$nQ2fT2R0@vD&O-F$>dkT}7V|iNR(h+yJ%b;|J&-*25 z3bh}v#Wbzc@D69{fN!Osq&;2Pc-aoq?Q6z2S(`_V^Rx`>@TL}DsC{Jlj3S*XNCP9I zEzNuK2miw`Gp#qcEtjOCw`AY=KEa%%(?;m=#(RxXlcBL0m|L37UfFbx$UJ3gQ(HHg zP|USkO5cnj?wOkd1eX11!M={*p)<>pa%+Fb%Q5DzvLKMUw8&qsj)Zun36k%`Z_!)m zghddrW%6bqqSu!O4xCvwEm4-caCvTCD%z2@vhnI(K@1~93M04HGKY*YR-~Jwf-$hz zXNx}h24=y3=8HtjH+;a08+iVcMXrWu_=P;mj^l2&YaR6L2Alii{}d_VN>e_?L{=8O%Z z*k;m-Uu;qVPW(S3U`9Q*D&=Lwo&depHX(1g*w zO)aB%Vzq=Tg}NQv@&6~z|w=%$KzL*lSME&cr=13q-d z6A|VM%>>vC=?tmh)O-VEtiKK{E-cnN{brC*VPTzjbI7}X`QgBaOYX#AAU!-zm*4X< zzvL?}vac=-Si$yMFfi|(j41*h=lT}xVU!(ds#5Wn*RrDOf=U;{+{KYDcFV8zYO>qR z^8MkX`*NK#uj?B%t526^5ki0^t;y&_X@8qab~|fZE<+XhrnO%}PY!}gTqZ}|WG6{r?17*mllR4U~`+v8S+F0Flk<=83yaYdd)=)b-%|^T*1rfpVuD zI=bztm7e{CrIUtjCc;XjxAUJ5aV}UumRT5(UWuoA5+HGJ|2j%&O{v_gEa@x1KG)$M z2vYdTo-R3!$EFB@Anv{{e0!@0%w%nFdCHZPGP^H785jkN$c+ zbZm&LgRzB{sQ<=@xSm0n?=|*gz zQsz#jYP4hB)ZMk;8-=sdCx0ddDt{j|rLp5l4nB7&i>J=(BF91301zx02B8?k7v_#g zMUs>e<}N0AX?yZY0R_WV_Rx8GG*sq##jZ|Ec46c2p*B!~>=WJiniQ1rWx-+wZKmOW z80DRe|AKl075Z@k5?B3~)Bcv<{D+}?w+vx7;2HUqbSUXz_a?OCEAH2DiT!Z%4XWxG zPeSdX)EdPd=#yI(ykoY4wprAe)vOL1ihgJoSPVYd^j)w#?%(6>BD=bp-^XA4`GLvs zjHpE9_cz3JufwX%rCW+#&&Pf>#KAru%)7(+zzPDLsnZ`bY56p-btgf=xKLo59?|f9 zlIVvXd0qjlNwnz|JmC8i-C9d^3M~gSylKno;Qx3{GxKklNtYd{hmx zconIt)rDv%06g3cGco=@xFUJ3U_U1)h1p?P9i&iy(NpYDM8@LjyXI{)FDuXq$pk)l zRr0e8dLUEGBE&N|$XGGjRwc6xVJe+i=w}h80|qJkreVSv$eu_*NKU6SWUe#7r_YMq zt&jCrc1MNcP<34Qjf5ae+m8#{I4M@5uZ&XOn9jw#1b%WQu*sEyCLcr*5Jc#-{z-Ne z@?G{-vLdc7A86>cHY>mj?5DpZ}gNrlrSaYRZROeKR}vy9gv1f&VYl0NTd)lgG%IHcC2x zxQCztgF*^#WCt2(YTq#{hjSATd z?}oEqLbo`y%+&a-*C6x`IByZjHd~M*o9TVYt!jukeSj`6qaszyMr`0BLIg7JTNaak zDb}76R>8NmRzSi)7(8oW862Q*=$ z8kUblLbp>N-fxN?as6Bkz(?&^h^70p}^9@fSmBn z7W%S;*}wIlZ6e*ia0NvaKAQiGIQ=nJSz(0~59&m~Q=J~QoIZcLTp~yps*?d?E9nJ2 zpWl(HwO2e)DBiEtT;$alUC5xGDxgIA#nJPv(R81_eaDFFoY+|+eEhcJyrb3_tnFMkpGm34D^**$ZC4f1 z#P1Cak@W)`POj&71D%z#@h98ITa=_t&!}GK&weEOsRXac=_o;auWE zCmV4x$N9Aa0({4T@_4^izrJuUWpA4FxtM56z5ql$TR*9a3e)7Ng3|XTa$G9Dl=O@y zp6$lkXO?M5iaal&XXLN%`Cn^NJ#oZ10;}K^-SKy@^k@Iy{4y^j9=tycD9x0gefznT zJ*(T3y`6sNRqJr9>E+Jh1v`pf5jM-~fLO+7R4ixYxs#f*P~QnZE7^-|*L-}GjO#{VCx&N8ma_YM1i2vULwh_r-& zbTG~G-6>Kk&FEBW2#gevjT(&op8Y@1^X7T6*Sqt&uk$>P^Lun3 zSPQSuxw2~c(N9PxQ5vz^85EaZABoAWaWWTX3b(DJ^d8;tnw)IY08^RYBePB1tEJO- z`#{s=BrywjJKPa}Qzo6rp%eGMqWhhmGRvrfzWzd!FTX;VBdEpiBl;GToN)Zun@#p8 zhE*5YS1#PI3S`cCS$7F&IZmcSGd&R-*qkY1o7+lop5`JPr+YJe!#8=!u-xl_+eb@& z2_|Fqg?kkkRJ@*o@ZxLpZ>Ev95)7>E*|2bG4AEEFz3;mL#?#>ZVx5fXZz0*YPYd)r zt^5O6QEsn%aAR(=hV1$pg6WzSdIcLuqki6(wqLnVFlSye%AaMA{PM~&#KH|sMvEKn z$stnLG{9n+XS`P8MkMdfDGsU&L7kPD9l6>RY-aMu1jeGA1x}->IanEZ9M8TMPU?gd zNV&$M%L2T9N@c$}{1oeD@<(^_OC3wKbprN;D92<@go`6%78H?0g<;ScGuYFx7oL^3 z&R<05Ir|G2^hMNa@Bg!DMS8w=_>d_ViKI6G=@D81Xl485Y-{1ezpF&l_NR=ewdaS|8p7w@9{}*;5 zU8v%G+?!B-B`$^M7BrMR!o4l$EK5z<9djIUlz{b58@7Koi+}dMri6pS&=w$T`7)F7 zvg64qW1Y3<<}6O08zIY|dHl9r;Mp_T6QkLs}7H1Tsgf2mHuQc$KG`BDg_k^>hA)GkDt zL?~X%bZtaS2Krz>cJ`FAhSQXooF>}J_n+JvVHIOB>>A9C6kN&Y)j55&Fn%)8#?D!u z*upOLv=)j_(rZG3gJ=;2sR0`%joMH0BSqoIXN@F;s~SMHQ00THj}Ek0i|@M#Km9gM zqAKr98)r(PVYdO>^&GV9J7S8Qw{BMhDswmf-8UG(f#OTkEw)M1GMyRXKUe}X&%dvB ziaR8Z=fBAp+P`XnSlVDLGqY02!TZ2dcgMpEzHP`zh#H-PD}r|Z2{fcozG;XqH|0X5 z?|KOE7PFp3qUzf6%?}pKvz6YPe(%?a_?H|ep4_z^^XFd31m7o(rU#>G9E5nMV4RB( zE~HI52VeivK|!CD3w|B$jDe5(#WHEO+aWp2&|X2xOJLPGW7(-32I87Klutvj(%-gE zBDkgtXSP)GX#|7{`+J#9sXTqLr5>2Wg+6_lXf`iD1cxm&B&u%h4=%!Y&>;H@ERcHRB;z) zHGSuEef36{OLR(ff8aE)lA#a8Il3E%a~`udnFXHZLTVshL1Y0dU6fsLDIohywtv8) z%0YLwsspo+C$Z+6ClRlHHPCohUqd?oF`qT)i%*>S6HRos%+ASTZk^a^u|2A7MVREN zACZjv#h=c;4)ffrgmJn7OPM|vP9sIDu;2r-Wjg!h&{@q^75=C2!KzT7CYM*=Zfe+@ zz+f+)mFa@#-qWzH?hQ=9eS4nj#BXn`GBw{=m9fktP-47E3~V_={*Yck_=0Dy{hnfz)lVIZpw@IHzkphW#i)!$CW9|+Wz{QVViryHULBq# z*F5^l@R`nh?V4t1y{&s|Ba;PdBU#vL#?k9`2Q< zEa~w5#)cac0}p$K-mynY^=*c8bra`)|Q$rehfpz)3|QGor| zi?+*AWAjOhkA<;7qo_JFMi)#>jJTz_)JyXAs;4f&C7u;TAn%( z)Lf2I#U@k#N|PSp-Sn@m2`VYkBo6Owi&7ae5vZ$`!p7w4C~%Oq)QHHR1e3J3u@N*L zH8mgI59R#z;8}Gy24qjYD*R`Vt!zXW`-@93s>Nmb%;IS#n=+IaEsy*;2Vb&UljD^W zJe$put-iTA*xkuWUOZnZi7g7K^nUfGl9v7FGKWe0bYt)Dr%5HY+Zzy%vzqO(1pvYB zWzj85P+&NRJS}F{lih~8cpNXKGlQ{vAzsiJfH+V)@3jGP?veL$i-}m<1 z&H#`M0U1ES)QXY#z%<^+16lpT^q~13o0AIhbkmNDR4)k5+rN zTh=^&zZb2(8$$6w>63G)2}*$CVzN`PDR( znH)`B4$Nb1ip&W-tfrkp(xd`cd%H$#slV7r7UmwZaM4+AYqGA4CA;5aSx)xZok2#auZgpxKsIj?yc`uesH%b#-dcDNi#`vD*_jttm^s9cB>c+3ch5O_mbFZIa%zh=JtN*~WVrUD+a=1H= z9KY+lbNdW+azIzI(F@urT7uY?clxC>X;`)_)8Ybh1FW~QVyF@XevWk8;T#XL03kSG zjRa^fSLEn*2Zs7Namat9ln3D@jSom&%>)X&^=9CXtjVUV4)KF$wLm(q_l7H(R_@(7 z)7GZ>p^T<|@J;R2&#FUD+u5)P@qYAuf=dV(=KJmeGKw!^eEEc(UZM?wic_z?!HS|g zs(>51{e7V$ZRX#olK-q0G$ys5X^#)usq6mR$G2Yn`#~mP|H=9_DRO4Z#B!je3Rd@b z{?gPT+GO{$Bm+(b_<3Ga^31-~1!gXzuoN}2FeEs{j*9jj>#!D7;;r$kckZ?eU)PA! zc>3qJx!q8-TfgGaG;6L{06*t&F^X#((%-NX+YqP1Rn+RN!j=MIKG z@q24cRhf$nUPIk{7A5A)mZ_lzw~+%_&N|3)jR%HNvM7RhYaBdVj%m;hKxQrG?8Hmi zlG@0KG3_w4L>_?=GpXM03scX@Tqn$}N2>>|gQuF|odL!~Cl=BOmc|V1%hmvG#S$H^ z?YyRJ=73$^59OF<$stESv=liE?||>=!V8UpfDS{>oe2_8Kq-#t;k+`2!SRXfCjUN! zoDGjXn^IE~G2i%vYDU!$!pF*NdhYEdD=ZXQzoYMZMv3d6ah*IFi#eJ)6!^1NU@tnM z+lux_3VKQB3}vAWlU2){>Gk&Fyc4XLIJR=*-E*V0b*V6~^{kbvnMYL_+IaiOj{1xh z{&Vu$iB3Fh0u>&JqU6HdD?f4u3YGD{pM}52P2>#cyb>mkQo{(rUp(9ghv#`N{H!Of zAsYbhIk#_T)qPFcdZsI?SVAERrL|uFl8b!UkHRLf%;QT)B5jYW2ta+^n zabb12wb?zXv*^Ey2W;0oBbnc0p@qBvCt5pp} zDx$AwOcn3#pR{S0D7*P6w|)uUdQ4`>mln$SqY|qV ziBn+;h_o~;*G1Q zVy{GpYR*}sij0>HgtL@_+(3*Wt0 zXE%YYmC5R-H`Pkn0AC(%e%344UsF9LVNEhqj<<}h3B%oCeOfuv*u5h%{c>br-6YTW znAK*FpwdE+mWYW3R^Dbv<@J(x5yy(ESd zJ3tlnOFDbXEgTu^BsY%{c9 z%L8~io2*h%7s>fh0<)e=VFS+!p-qvBlX5wPB7gAm$bS$ke^6Ki137cUY1-lYVcsp= z?;F3el4(y|7Po z18>Pa<8Jb^*E_43^si%yp{OTN@WF4>HnnfYloaL|NI0qOfu*?RFl0iC!xyw$!X<9fY^|F|Zg0NI%~t{u^a zxiCB5OXalszx#i3RLg%$56J&V!TVqO7eo$`V_l$+)<@E~7BTP0H=Lwg6TPpD15Q;p zNBZuRrf+qZHS6YoaHGBYM=mu)#6FZhCAv4ItfS#0(r|q)#(FzVS0K^lNfj~Gy~gqvwi-_2eVtTSuS)~EA&BUC_!Cm zw!)}LsL{Yc@v7EK9WR-xO}7(P9V^b4H(7PMJ5EYLbTg4nKOi)G8Rz@y>n4q7Me*4| zZ6|FUBJ2lvzd6;@s0k>n4=mv3XhV?Yk@xrykD3)fp*e5hS3>74=lKIGeH-!Im}aGe zZJi}deBfE*0hR)3?MV>7){*O8x4uk78ree)916cfPQguiSp$6&l<@pxYtz+e`t9^K zu(c*@wDZc(WEW7i8+ra_Jk+yJ@F109xp!CeFBN-NLx$d#c?R3zwvPsge~ovV#11cJ zsvunUYtj7icYAHJgemfSIqXzQR=mP1f43x0EH_*M?2Iaz`(BIQ;(jG}XX=6x^ z2eiu_Qgip0?1LxgWI=(zo~a;kzDUu#bB=N?E!_Gx@{0Iq{8-%OC2+`ZyAfjX{;f|w zoc1s9x*g0gBRAY;S5!1PIdV*>UO(r$tpp;@KOK4*mU`8!pJ-FX*h|m7|HQLJwyI0L z79znwR}JCgxo2RW>mlU$9Pdz`=MPcQ?A24bRTVFyO1C6+2J^6?PGv?sxwkLA9| zdo9@;S_=;8+jkSGm36|*?d1w8?DmhPVPEp(vJ(Kfia^|>9sj%SMan|TJGr7Z@G`rlS=opR3=NP^5T>(UpMz8wWDd3K-0ugR` zR+3qQNMK$9AF^G|@tbX&NaF9yCWSf&1by@CzqxU`g!un#cvcB^OF~I&TasGsXLp3_ z9*XKWgB+}nWbHap-&ThX8LoU0Z1*{xof?7r*O{T^&9TNikKfXUZ|btgUdU*?cx`yu z3jUvtpoO%alq@VZM#SucqN-h1cZ9QVsV;F0^6?m-z9u1|>D&-FEc~#N?e#;#J7YnP z2P|QY@bcut)O#$_4M2yQvjCvCyE~7aaII0k!87WV-+?2X_!2N`iT&>Zn& zNPt^}=i?M(YO&=?=K$rl)M@Tc#Jn1Lf4bP!vCzD4O7_M+ES3QrWKT@ucQ;+~-(jx=2JWa`Z%>ZXAs!@A2J{8R#g*l1ONc~An<&a&H z&zOZa>w*s>+h@B@Q*%8AJxGJ^T#-mpf3J{`wV<@j#8cLl!&b=Azy z{L-xW!+Q1nX|N5`c!Bu-OV~}TmekZYbQkV=c2v2`x2QziI1lc|>S9(VgJ@qpYzE3< z&BlPL3}>36?&59x63rp4*Q{idwIYq-EB0@{$k>U)n@5bBe`Vo%clLUeix5J|>Thux z)_mHkl$88`xWxIUzrpR%(IPf}XSKB-x4>>F%=1zl=RH@io^#B0DqqHt9C8#2;h{xX zBgn@gR^IWhNzd2UPj$bxceB~|QMKja5)b<+GbbuPEDf56GrXx`G|b$K-kdzRX#y*u z+EEirV4fkdYd$u)EZ;4S8Dj=a{8bVado=BXz4YFT4l>i_a>!MLi9%ame5E z_tWA#?J7QQh!=@3XNTw+DO|cEv{w8=->#^eo1Tbe&o_{dl5^%6x&#R8Jk>_ZQ@~U{ z%S=#LQ{Z0Fp5517M3h^%VLpB|z1EXZ5vL#?3~S*Hg7sS^si)^bxNNz+j>{2f<-H8v zjQYWnrhF{^%*si*X7Ld%f_^A~=XT$m5yqc(KW2r|PFa^mO6k z&kymWBeHt@BjrW!#L(Uca~2pQ3U5>YT8+uNrn{oq)-NW5Wm|6N05pDl{FAQuOKoEzSyZKb*k<6>g=SsG|5lDp zpkIoZis#4I`Tvs1#>%Vmx@%hL0o~@2=Gv9>pmn6&1+nnD$&#a}t%H==h52(NS* z*M*H>hmYr6-TEudo^+pZm#QD71r5fwF{2C;G!jS;Djr4ptv=qBI=i1S!{aRMTu%;2 zcvhvH7!2ho)sFX|zxE@TOT48T!!mT&s<(pdB2{fWxV(i$=z{b;D_AKj+Ao{8RKRZU zN*|2+up~+579IuJ^bQHzU)&hV0h>Mb2xwIgZb9jX5ebf0T&e8ETjh+<4RTXCO6ffWG!|}5pjz6 z^xIu}{EhD8b*IM&nEy`xp;qus1Jl+)7UB3tw_0hxBHEki*2=uQ|L*4ov@vqT>C~k1 zF7pc4ZwgXSO)G1ojH%9@*|P;>ud@?j&MSS!P!h4pTgQDq)V^`{(7XOPXQby z%hwMHE&S^rBtEPgqD;x@ePV>D*8yv6mUko^cTPWMe%+)jV#u!A#%w z*U~tLH(}EBNHOl!uU26x-_bYh+1iHJ1>t1c*O$MrF(MXmSm*$fn;OWdL5@Sp^+j<# zLoQi`Hlcw6M5^)NL2#V?)qWrV9xlGyx9kVZ6z;xMBDVAwG%UC%eNDahW_qZ52yZTV6<1Sv&NC6`#K$-bhGa*)($bKq zeM-5Jvb6l-Pb!PQMFc`)#>}a0O@x*j&BSY&^&agR8z$?>_EKB8x2?6)dqB!}lAmn{ zBX?;kU1a|zU_25FPMTo&76|h`II!I}y+G}aqxOaW!%EvWMmRJTu7Rt&3W|iyM#&h` zqS^n$Qa>1WfH8jO8hHLYqXt6l^N`=MCxjVc+XtieU%?n*q2u|x@GNvMtcg(kjd{Oa@4da;?bBvI{sqM?P{XNGY+*$jK#l2tPD_e2~ zxNh6>_lEjtJ_lQ7JBye<6zrq9rfu;d^)C|#Zoz7Lq{>uH=)=A#8)E7^*>}(NBF-TT z^~zg^YC`Ny`qTM`eL}^Pl8J5WKU7~-*+ew5_WQzK>zv&NjMFOD-d`=~ruJQF~kpXM14X1NLwcC!$xwCT- z_qPq54}D*T;wJeykQXe4pVJ8E$%1!V3jV_q^|g;vZg{b$K=BanBxgnNmI-q`4nSE9 z2?qra8bPeyk-a!Y`;26a+Rv!s2>E2cyso@{)#a?a#H~n!+WlrC-3v=VhPRsoi{i*} zbU=UT6R>-6vRDoiNz{hOS`{}iACjHp8G-(<-P!GI%{7i* z-)HTOH*;Uh@BK?=4)5>a1@ab#P(Nq(tcM~Ym??LbQ(5K3{$7}+iuOtftl1TEK<|C1 zny%>9Libb+!(6cI53eU}mmjX5B6bp3*yB&@iARzyF(Q&NolElUD_+z}`3Q`2Iyw-k z*Jl*ray!+AVQ{~Pa@@W(ORn|+wXXi#oN;kKeyQj#)WSx|o?d1dc6pjVk$lS5(kKY&Bs~QR^QP%8)tJG!_a1eatvhvo0!p2`wS(fI#csk@0TR;BeD@xj85=X39QC z6r2vtW%#g!8m&6MFB+?&YYO%G1c!*7O}&wOjkUBZTuMRtnocr>D675rC5z319b>U| zVLsphW0;ZSK=Mu9U|517%{_6r0$Y;-tl>N1#w!K8JDfTL5}s#ShjY8_!;yQeMQ4cK zpnOh>jiafE;1B79-7D40=aTw_P05^Z{lY1ESW@dN>ex#e?&=E@?e5+)Ek{f&<4CSi zhGN!p@gK;F3QVK(?AluL(bkv5Rb^1T_5p?_8G9$p3w~$ zjEI2u!TA&-G~oETzI~X7=BU_Wg@;Gvj7vQoa{6VeYoKdA|2}=i1>VLopzOv{{9>b^ zaZ1o3hbJXpY8qNlk}g*aQtXA3#N-=K+C3<@7dxFdvAH_&e(X0rOlH6e2ja0N^$<(J z#`#kROUlHr5aUvOahOMk9n9b9IRls;(4PgVrt6o5nhgUwiuZuL(UcyEUV|VIiWG?Fs+$%XT`zC@l)h(qo5_N&XS0D*ATC|-PdS`ui=IuKDu}y zr~dA<+9^jO_rzm?N4`U%zM2)bmGkwpyeh}^7^|&N` zm$AC6hfk@AuqOdRV@{^WjiRoQ983oKsM&YzXzIwg*M2+oRk;FX?6t^bq}ewCiZP|K zKg50%Cjj?0gO^e9;^(GdH}@T>ls-xw!q=b=2n)V*EpXjaqGijiG)2>~sgp=TrYD%raLLgld{WjuNETQvc$k-DRm z4NvSpd+|Dr|6vg%hK4)21T9hMJLvGS*(mQ8L|m;A5{-cm--PtlxDFbCMWM>deboSG zSIQ}D)6(3p0yBHZ^VA!)xGm~>f=RuS&Z*9sXnEJ5}{b-C+-Tp1vmMtW?Gsiq`?fn=g;2 z7Ys5#QLu4!YrjcMFEaWgPxe7$ER4VD9d*9{zti;h&q5_vcpaT{$rB7){Mm;fl-!G} zye}GEzDH5uWR^9PMRE0h%)kGo}%(J0y+(@I$Za*%hya!zx4R> z&1J3^^Ob66PxV6O41ddFq`sNN5qAeEPI%W7~(q)T2l7&C3?1`IVCVU2Y@m04A;L)2#VzIN3 zq4Bz)`pKd73_ut-b$>Co^0!bkSOxHPh|U zZ}7z2k#Pr)%BHqp!IKoiS_dHSX2!&Pd~w#)dw1+Om*UTB>`N?ght&!{v7DXE&5hq0 zEYdo2ZyJ-R;0Nlr&p{XKY17X9IpPP_G0JB<6fU;EjmBpg1n02QV0x}Yo_^a zG&(tvim}NnVPV1{Drn@jxSRFo;}}<5Q_tJ+_Ku?%?Q4Q=m~O{XQ&J+C!mxanlj;dB z?(3pgSDm*t*Q9?32s3CbT=<#tl-;i^I{%ZNA;-jKJ`=?sAC%qyVqOUeCiV_h*lo2K z3#5kWrE}8D6Jz6d38=<9Qds3bn{52lM-tZ3EuBSBTl%@m#X5k_>XtesVt1D4vIsKO=xp0-D=mwV5PQ|7vaT>iM zRcl73=4HB(0^veE$y5JZ@V*`KX@tcpmKqTJbm>YeHR@v?L5tfXnp!`uh?Rml=#c6w${rEq|R-4D;9((Jx^ zbg|}-$2NKc8+8xIkDvAQoi^J?U#hWGa*i>bt0sj|&}Rk{lZ(yZF!AiWIH@*cR*jFOM=t*Z$W+!YgmK=e)Pu9 z?$eUD=ANvH6yA;o6e$^0hWY~-Mh|T5wdV|$9^|)WlOEAA?7pbiKOU2IyvuiU*W}cn zd{CtQp{VXdz&BgFP)XY(>BU~G@Xbo5=UM-r97e>or--?M(GGSNh6#UO8QMoIn-JZrhUm%6jO<>GE&a5vDLTqon%&7?+hJq#sE10Of~6iv11Eb43+*I?UuOw=i z+~swiF*?^udnYd~1-3;3@};==f3gcLV^U%!5uoUAKolmsXT#bl$n|xLhe>3HZogD# zqsm_#|0f&6Y|m6EJ}6{xr|)vNpuLDxlj&U!(cbveFUQ^Tfud#OlM(0V_4PL|xmM8_g!vHphUFMqy#~efz)fRM{^1prS)+wk1D$ zNfQ5+`C;}tSJIVm|5tGMZ~6a|8xCKgP>vc|{R6N8AVnvc%V6Rl(aG2kf_wjmj#s)}ulTeEVqn&J zXX?Wwg&$t?vc2G>j{tKZ17<*O$stTxC;Un31R+&b%1|SLu7Q!T{P}pYnl97wf_(Ob@~jGNlTN1$LE_m+=WrFJz4^A=pd{0nt$FHwX@J)L6zcK z1$=IT9wM>JFxWX|T~yK|b~?l`YJU&Yz;TnBOip+bZ9w)?ulg9~uk;&1+WFIaq29jn!z=u-5#Wr1XU@;}aq>e+NG8D!Rz4 zvLsd7UvD1p&vy^ktBDX{kpG*Y0~n-!E}=)HZk7Pf9o??FH~K>so2ynxiEbbQD4B{wry2;UYErPe1+C5 zWAC=Ci6Q7t($=b#t$=SA1$e@S#4+ci4kXoGyzqPU)LEI$aBgrpb;Zl6=_9+9GvZPC zn(AwGCch?hD6lZ{q8*!nzG~M+4v}J&b7***c^*>cS~lyeddB{-ZoF<{WY|F8$Un$9 z49nB9y}wjd-)2l%e)tj;)B^+OUk&h0VOYw!O?Ww#z}noajfdVBEU6<35U%=_1#Ibh z0p+YmywClG^+#y5dPLhRI=8BC8IsL)m5(C!@tkIdZ zY$P~Iqdv^!E<3E|yD7+-zCIoRf=KOa*Vonp!x+ed`AMsD52I;!cM+S%3+{?f(prGM z`~jyr6MsqmzyK}jn1h)o?=gCj7h*8(z##erVX)%P^Oqa;)d{-B^#~t}$#^zuk!IcXFCkJ$Mbqt#Jt80GYeW0ua0l#`rItw||R>3RozbpC&o&9^-UpCP*m4bCxa6VcQLT1%5`Hc;z zueAudl!ETRGyKahCA{$l&{h{ej*!+$n2XV}@-fqS&?w5cNzTie!tG5;?62p9IEH;j zH6w>o_Qj3|SLtI|oA|%bN~q&S)MU*t3_9K5bb$#6YHJ+>BKjNwRvn(a$5ay)PVCL05fv+78C-~K9cPED+$iriQm&KmI(V0 zey+rE()r;1rb1js**7gV7CLYUGDLH&jn4+(^HA%l@3Fn1}$6TRMIde@0H|9sC( zyI5)CS2^UxuMiU;$OkPosWm8j`XF?EC4sIgy<+|`rBF`b-0mAH8kIDF(2mSNf;Coo z&uYkOs;+;%C)V90jLuIaXufK(sQg3q%m+`w;SH?gXb3sWBl`0J?uc@(w-C?jAFfK_ zc1|}-056DsVjy3C|DDuGur&KK2f*sLjK3_F?9%o^8SC66(h|le;eu9J!8GGxT)#UX z%~p`(BE7rI=S{!r&PjE1$tJ(MNg%!A+^pr%HsD!%-~~cT4?fm=&=AVA3r|{G>nwQ2 z6KF=8pR%o4ic)b8E8Q&a6{uzUbuur!^PJ&^{uK(wo_{tZ`adIdSvo}BQ+#?CptxXb z-^fIUM*vClV5xIidyx}q2o$|D;zV3vX75|XT-RF){d}Wo&+Oo?$h|J@7X*&pb3ge3 zly$#6Gbet#Ck869wP6u?m9d69ab6V?gkmFKA&qO$o}0ktVXJ|!9X*(OA={7MV`IK% z+{Ys-&7up0qcVb3H=W4O`f_uj7V>8;F9?A8bFuG;A%;r|mxv*U=FBWtyI$q^-toG3 z_GxL$2m`olKHriXCp~rkYIePy2YTVvhtjud5g2(-Z)%(heg|e3!Ng#>$bu2dF$c67 zTE;Wo+lCA7JR*@m;nh42hirvH51h%to$$^lz0+~FtT;p#h}pMM0Z^4HkQQbIBsgMl z>_!xq96lrz8Dl~iAwzt>H-B4HWr`kb^V;1;gnQ7XmwuP@)b5%nl3-qMKb>HS^Z|V) zF}iG89W&31FwY53o4VxW7**RP5o7KsUR1 z>DaUJ-b}>&VlYRwA=qI(*>)KSn$`7fPXUW{s7b8HpKPZJbN^4tyVP6x_%=uC>SYfc z6mAtMu}eH zOhqb)I)+=d9awX!)I0k(-UquHnYmhc>pX>2Ot+mYqw}+y#Ft#w+#(B$WO9-~m{Imw zQII1NzW8T|_o{1Urag{sT|N1WMLr&DeA`Bt*;)gkK2|}x&CNy%^0o!FU({TDe|?zc zwinLv=y=`bN}c<>Up3tjE4iRBCANfER$|GID%%v}Kf5~r_$et<#K|DjR>yf+=SCtV zz$MdJtmVab!k4;VA6nZ?^m9humAac5=;abt(l`uO9GrR2O>Ub;i!OV57|mh}LuiB( z{khK-%9CNSPwFHrs+oUNZ=AI-fsBDE@c7va1;qF=$!eM8=1*bBgX`UZ_}UU%RX6Yj zfbW+bO~GQOgb{bRdr{;M{5o$0s+pDG(0*|rbh z2STR0;YhG{`uY6Hsmr3lv*`qP?lW4N2wm#K*5j;+rIKpfVk^v1(qev52x41bPv%W& zo%-;(0Cyb0tolnq)&3}HvCG$_FCaVJuMaTO5!N$9Y|h_eazh|6MTcsq*1T(i5}kJc zD8q1}AXfpO-Y4-53|Bt|Mdo2EyWL`(ejYsvSvCaf%kh4cmynkRxhiBnM%=ISBk9Ae zx<)B7t@}m4H(rdY3D=C8`IkNh5>$rW03eLWak*IxVqb$)7HtX?JTzRaOjmQazb=#K zE8nz=V~yR%3A%*V9%t_7G8cTL;j0m5&>!5HB@Kln`ufY0YlDN(>@dkTLnE zUyLkQzKGN$YXBI?{+t3RGW@(dU6w)zlY4{1t(K5PPU~y=JpGlga*hf1(!Lxqhf#T} zw4Pn0@han=pu_~e<5CSLI=524_u%|#g}dojvk>)+wxJyR4$u88;Dg7)Jq18`iDq$GsEF94&iui2hj0t}T zICLm%aFBzo<*tI>tO_|W*>%7wob0 zw1`UEvvO;m%a`@uuiD5v@*i-Z0`8->+zH^GaXg?U8jw6NM>@uHO|V8)#)Q|VDb{D3 zg})Q6t+D8!Xc}Enjtweuc{dKqbN&pOAL8{hTx{W8i8cD#CGEO7rdE1e)~uj)M|52< zK{c!iKhL!w)iZahdIu zRw^@fT^M6I0Esy8_b(2*OY>v$KIL!qQuFM7nLM9*2etxGJ52}Jr2U+bQT@*IZ>?w1 z`{#Flz|5)ZqsEkE=wN}P%-IOY#+leCwZF09T2F#3UP~}fy%Od;E(UoemhN1?W>yrn zHP9!bIOERT{2!M6N*L|Uh~_Jn$a43pngvA{v%vNp81|qr8525Fc}7v4IQ+(V=r(HWG?^SaaoUw zitFsw=#z3fd&YQ7_GLQ4N@>{ON$bXQX&gI<0YY1_HX(56U|o5JR;iirNQDfXi;Jb2HU%VmRZMfKAWV?|M(J&EXoDJQxTxOHwxD5IV=h zODX`eaWy)vKh7uF6Ic>15>BOpKe9Zn$(k&G&ozM(rZZhE{5`}iUUi4^(yChKisfA*poVx)x-REmk>2Z%`S4;9T~?A zCBPo>8~bPL7ncirL-{3$q+%r$va4?eLt=G9bs@7T8*^?}{W0yu(>9e$)dY``g5XMe zL$woXp)nvY0+26Rd#O^QdynehB%aSs{lc>wbSw9kDXYpV#7s=ju)=}gOf7@`8QN-@+t*yq<^L)>ke`y3 z5fC2Ld||?oGltL_5zlQa5>^;nCYRS^>}GWKqInu?QJI8>0WmQ)-+USBJx(l$%4jFP+kn3j2c!6ZVJ7g z5Db$RqZb_&JwlTa@u>czmn|e9T3YNah#5)#*)X7_5>!IR!N-d_H%geuPoL2STP=0} zRgri`jfqG;C_yV7*SRCTD(7A^ZEd@VY1e?#8#MqfZ{H)l1>ctBZfA1AqL-PS&&&;$ z)ArPe-PBsKbfb4M>DWW0EdOi)B&!!R!|(@rlfCGGgqi!l#YI1T;(q>kMtEwL`B%wX zh@mB29>`M0#aBy}E;U4r{u#4bPjXc1d-GG`%~LO-(J6mgCVJ40%)heu>2vz3J;P5G z*vq8YSG(DO>ffUjO3SGx;VKc&_bAx;$?68LMC#TD4_PTm>E`EHMC$CWDOq*Z@Jf<# zYC{=y7Isz~yH;=>jm%9)N79$oh)X)I{jqCzz9?$_c;_To*YU(Y1JdI@1(!99{K9HG z$D75dt;wvqk~>2!h(*)4WTU!0Zx;F4!Rp);G z0le4^5isHc<7OiyHwn2UJ_jX@pN{H2pKyLrBUq$jR&?TJVAJ86=^D9(4685Cq@dgw zr!9)Q3`rVh}arRmiM^k~glh zcJOf+D9x)L6GnWmzF|7!$&vUgm#(*1VK{{}A&%RCq-VN_SDPT9^Kgt+O!x^@PCR53 z;~9EVi?%qq87c+=<~=%N%i}z|o}D!@8gwMKzSt^JN{EE@)Z@>&^$27(rmn;)oUkFs z+OZ0aqLi;s2rlJX_}yppGi#$VBa}-oMUZxNDQW%VXiSjNmxH-l65Y;6?Nu)ugWle& z%@@=-Lod#H)~kui38$prW47^a4;Y1-OA+Ja7?HKH=0xskWT<|udo**}<%f<;0L?WE z69lp6v9v(I#rQuxh1o1GjVJGH4<4Gt^wzp$Tot-qWkm1KU2}QvmKMn+Jm`Y>UUo?Z z`_B6CEju5zrl@vqz%ynf0hx0A{T&CS!p?%OW`4;PFCn(%uW5{!{t48a35vWn?xh~i z9lX(h^>X3ibuHQp>f9Z4je$R8^{*Vtaac&NtwCCxk8!gXqBlY~+kp(KAEo{!#qE^*Rl@U$$*T!a3)vUZGh)S7*Y`@7;$a6V zuUxfoA{*W##B!TR&`Gwn8y1%9p%u(r{*0aSWklO~FN_E-RQMHdtfv`ssqRI~0+1z# zj6%Q+J=8!R>(`8_9JDp3i*1&8BdLUCnp%^S)RO`dRM; zsi6CSdqFPEIXGmR20tg{0@fl7vie|bFxoL$$hsXgPoiM_^>+BV8@oN3 z#E?=3f*lS<0A|k)uedF`48=t7#LKK+~i2i z9UGf`U@RE43l%)ISn-sud#yzt{E)|O6zSFDY*K~2{Y48u+69jFeAZv;&#ReCwALwF z3qD@bKXhO{`>e8LO7sKNHg1yL;+~VF(;)L$#H-tg`k2!}@wkVwm~XvY^@o z7m|~p)X)dJ#$ouuIW0is*!Y!Z+sI2Cb zQ_nhER=vWRd+Ztoao*e3b5%brRI6=l2d6FY<2QGi71iWD}}L=jaQYZmXS8-_K`z5Ho+cK}w8MJG$^mgg0Wbu`;5Qsk;JkX;$M`Bee; zjRgILQFW))iZJqR48D)wXNrNrK14JPF^I)s`L@I7gDhd$2WGok;-*zmO~s;D<-XG5 z(c`1N{?YhT-UagO#}=j;N#%jnZJ2{j3t@sAM4nBPE$O4jPuhsXoiyV~DvF`FNg~DDWf>FXcOJ6(xdu9 zh&zQlVtu@pSlW}7-=2Uy@z?aEGr&9EfLB`7UR#lCq3Dv+$-HpQPMpHy6YQTSLP;6^ z2_|`aZ|WXwptEqgZu`fc$tNX2wMz~g8$?JJmajrOHT5pmn#Yq2N$Hb0rlg@VrSqM! z#E$M|ib)J>c%uu-GZ6R6m0CTe_;C%`=&E!t@`5^oy$uIYnB6@tqc(|if zP=2#6vnENWrC9j>t@|t4C1@T_Tc4T)UEOBq8z!G*^bne95#&GHl!W%wmBY$(UWkD3 z5(2CCl^N?4@s~xcfW<(!#eX_{%{UcIfx(|(CWmv}hko5IG#IxBB0wx6>Tc3KTyW#< z4>~^o7R0sP*XpgTN0e3sjFYIE>(_jLz=B9qLbQdCuPv>9?j4*QniAsfpNNw+ZQNh7 z&{tbA1Fm**-D|P<*&q8Dcj2@g%^Tr|*>>=FvU`kF#3{FP`dZ1yTwdmDqi<)UJ-%6p z)aw>{%`AVNV=vz73O0tQC+nM)_^;@}|5$I&$ozegGKIljeJqhQ$Y_bjBee(-xT)8E z?QmLN=gj`}W$zD=dyx9A-`hm9Pfbe;cT`6D_~Gi^ep^`HsXGAi(oCl$}6Yi-ITii*nhsj z`11}&!S98-gRDZiUWf7k zxBjKBIrBUt`qkNhs761VvIzMBfTC?1{a+(kr9c+&q*TdihtDi?&JEi~y4`+X zUKQuO`Rmm58weh(taPTPxe%M+&I+b2sDR9{Jz1?(#m#F#67}oIzL1aD0bdsXqxd@{GcXUo5#dPtg@R#IH_ z?k9NsoJS)HZWR)F%39;$c-|BGH|0FSsyTQx{sv31XH5#xh}vsRs~hCATt?NGTbvkA zXQq`qb_U#xo(Yk|x4RVEqeN(nc&5dYqFtA!LWvcyUM;37AO8TaRVV=nu(*`dv8itnVAQOYMH)2R!{oH243lIzJM z5bjDe0TQG(V z&~++*{LqI(U(N@z1oSInFVCNiKe+M=$FM~pFN2w`-)%2WF~ubQ4FkT_4q~b&`sh=x zP{E5mT(jD8X|P z2%hL{K5xL)KU=f3O2ebJeEfM@6?4e^wdFhN@172_cJKA9#$Ea+E<-s!HcqQvUv{eN z;elVG2j>Ix{#-D$QP{*}WAj+YaiM(^ z{9<<=QIGF7;#FJ%WvJdI5f`2XbEGi((&)@G0R^rdV)|sZ>PV{(G(297yUaYpj+JY( zcXv7|8{mQVq_}|8h4dl*BU93L&pwMVpVvA|TaVgbp+@M6_AucNJzV6<3r}yO((s8f! z+T|P!&VLdPU2J(I>w7*s%$(0iu;Dhbxe_^y6|TNxYtY=Zb}?gRt8^n^z=af)F1EY8 zfKF0MR#Tl)J{6pJT34}@R(mM;>N0yZIyW-xk{z5#S1v;kF?9Ls5WpA78^U@Tv*Ny$ zR1-z)ZpG8*tk;!GFZk=(d>*fjoSo~(V?nxUA|#YY2?5n?g8S4u^0<8Jb|?$mVvbk# zo8MxFsaPjnHLa->pJ(B0Bybq8{oYQJN=&LY*Qlphme#HdNyV1zx5oVp*68(x+OVD| zu5FBwz5gCQR;SEXs#7`eL?LKQ!pr>X1%GNSJL!k{;zh{N0khF4GpZfSLc+dLN;&X1 zE}Dn^v211H2GQ#dowuza0=?H*-}RTbcQo1y9qOOEUI}%a;1#;6>3lgeMt_ru=4biC z*gG#mPQ@a!=O0XVZAH2gC@+unXVaN`S%$|Mi11lz~neyF%X6WyIm0oN!CV z(h)nTzb#_b6iwX9I?L2F%d*OG+)6z@m979d>&+!=K>|iyGauL&zPHDcpjg3oHY>wf zKctm7F+Xt5UlV);NGz&+NBcfn#A`Va9h|GHGmE4lfyt7VpjN`KT$+Ao?U750s zc!Q9BP1`qLsDs3DGo*#!>E{)O3Q{AsjD;$+;*|7yaqWb-SZydls{zxs_f8Rdr6Skp z<%Oi!p766s0!=ab=n_OE=({(-cKxPsema&yAFo*boNE+Q z8gZfd@wbE+Wl1mo4JiFQt4rac2=M4_)3?Y8FwK%@FT{s>*{rKDGGNau2nxC_6r9{U z5U$x={n=?`rH(k{g}UMv|8bX@Y^PU4^NC$F(Wi#zA54mD)J01E>}1mAzpFfG zXgqY2dbC-XJI}qHG0dK0iTm^^#ZW(;K%B4^>OH0Y?cmRK>HJM2a>8xu0W{msrG%h? z72HTv*>=6!sXMyUQjOCV<{BckQIg!KIu`su66=bJL0z|Jjw7^BImAsz9o($VmAKDN z9*wX?Ts0JGA)=JYl7j9+Ce~8iPS?{-w7DC@e=$_KypZsdOyZ%@ag*kvU3(sX!WtFQ zyK)cadO*g5h&Om^glsj+oN=(SDc*r+Qcy7C(Z0L#rjMI1+;=Xm{VV};8Uz%dfPu)` zArYt9K#A~jvzzrHgJ>c=^@B7s!TDrZ=`NjQL^}R~h4>RB#B1lqD&ca84aI1@q%YJYzci-Mr<{grLSf&Wp82uhV>yt{3Z$;Z^~ z!+gWjjSBd<-x|wgYfrF&=6Ab;_x{-8CwMy84Q}UDByzms^2tSba@~~a``M@<4l;QX zhbdAVo6fGX-XXht=0ZPzh1CS$MU$fz76IeZpz`WA0|XtPse_2N@w&n^_n~)>l7Czm zWcL4QV-&`BZ%|2<>6 zux(>$uM}{h;Pd0Vd`&98mhO$P)Ja?o_THju+;YL_i!FYVfqI}R+5ZADN*BF5#9?VlHmaE-7J+*IhgANZ7G6JiuJb04K~SY=!~r-{bXzITMGKfawSW z9d+@s6pED;t4-SUyNUN6uXvRj8uj$%Viz7^|*C=1!UkZKmQIOHFhbuFlsr;{OCKk^cQ@U;e$SWHDfX z+dFxG#N}`YkyB{U3b#0#EfNCKvLwhBnfm2rNcAomR7~-lrA3@~z(oTEnnlM%dC{ZY zLQ(Wq;#f=)fU6xa7b{J(n)4VW%$5 zky!Yh-UVG{hn0<};Gtu5v6Q)&UEVLV7~=;mJF|CfgE9889-uxNr)#2KMm>C{sYT<*uU z8xEzeAB{hZ6pPhV3&?*zFYpV6dd^ptjOvMJXEg8}pgsM%1iObO>!dB&y*T?J$B9Ey zh4lFm1|OU`ZA@;bFkQ%aDrzPw-9p36-K(6&BGc{{)WBX<)yTfMjtF^r}w?^6ZF=V#x@R zhvqv{CMN!%_kXo$SrJOatuyQ#&5fjcQV%+SeF-s3k+uqbb5vlXEajej7{6`uQ-kwLr}^sdurfYd@AbLH zHxIgt;wjP1#ayc%tbd`<(UdSBZ?Keh-nCwp zpRG&G?opcl_RYN83=wifO(Xt%Rbo+?5Nsk~IBYkClM3L24dIj>C zh$+Kw%1=0@uT6q91o5i>$Zm#EI2$KUgB+wmV?a>Dc;t zndZb{PmO&MODOkDXuIFtpc^n|^9Rzfi?W_vbNAs#P=tT|WgTl2Rn+z9AQ&Dfk6C>VsjhW%Tlh7Owx$d`BHsT*JZ!-qag1+#dlqMjYILta#Au z?nM5OO5;jNuUb{TWt_rpG5ix6Y2c*T(#(!v&v+s@p-*%c@N6~eK z-+pzQ0&nl*biYMXcPEDszoU+4W|Wosb4V+evi+#s2~2d~JC^}(P+-m)6($rt({UJ$ zxP0lq82$PSw%E89k>*-2YE=U548m&DAARst?!o8Q;A(A-&)lN=0SJx#>W)!W!X`8i z`(rb~;g;k+IH15CK2hibfnEyPhXjzthIqLs;I%m*=D)7#*Tq^1qd^8G6|N9b3Xg{Z!(XZrsdU-z z{`|GD*mCR%!gq7>6k1S156;$C;yFpW;To@WUOa%Am0>=AfDg{sBtDp37a=92RzdX|AJ$a7HEwC2J!V@!KZi4od38PzEH&M-W zH6Lu{2m~6*q*K#=CWeb*=)Dvn{|kT;=^1PEAYL~q@yftFp_kv8ddDe)(-UGjOApww z9Lk)ttX|1-TTdH5EkFELV}TRp{z1jUrm<(=-9!Xb6qH#E`+M86Yq!cr@6nMD|HRP4 z?&lxRCGZPf!zn9lpE!!Ev1#+S+E@4k@Br`PPsbl(E*P)Dhnc6#Y=V(~^2nJHfe zgd-X#2ONmXB@2*qR^IkPNmDP}w>de#7KfIm6Q(y&)#@}3ScAzfl=B3-QA_Zs?14T} zH&4N&FtLoa?0Ia zH)g%n!g=~q7}i2b?ke_Kl!-bd$Lk^SZH>?!2}f;a03nOnHtp}mBW3DubsUP901Y=^ znvR`IWC}1$3C;(6wAtyh+SXaznCMBE?!Q(!-V&7csc%-&d8kfK3=iOEDw%#cF^17O zERBBid?`(*o2(^C<$P?ncdoOs|1B?pr&`Pg4QevB3?78FJZO-3>cC7NCd-V~2woGW z)5QJibTBH!CrCA@swk=Y#ZhxJA_(_(I%rqp8(0Tke(=HkSaAETNZu#sh3DArfTWAO zgti0-d?44DOL~0Ht(MvPHKD4&(*wxY%a#y5YE@P;PS6Ts2)xAWE@C)7&f?l%bM3v zAd!71^zn7fa7|shbp93K@`*0X7_-Z|__B;>xPFjTk>GO${tvc)FF|t9{Mo zJ63{Y%k}_~kw-v`)(0txr52-4Nl50L_`1PAYAJc9LE(|SZk7|x|DSkg`Tsp|(Usb& zGx#;}$tO(NRy(n>M4Md^okzCvuo88ch1!3d;+C8^{F!U=vy>B%PbSrV=vCYn95-%E zT2Nm+<^P=ZsbUJXmN~!2L|am<{1i*7cp%OfBYdWDD;_E-aunO7VS2VQAzbi1!zMY| zu$;@nyKxsju|KNe&*H2Ko*Wd|Iob3w;T)9+fx}>aF2kJX%FBv`s(1T2^wD@)TgJ0M zlBQZK>1<*98}l{x>T-v&CM^l5IGXO=?>9-*P3q4H^lu-@q0Ors<5uMgH2wJ?0o5Mp_G4-t~&G#oRl~BeKG>-m01`n#h1;H1<7yfNTRmmB)=hYrqbg_8@&=SQ7g5hh^{#h1ss3m(zW}&mD0$P3isuuMf;Q2PqWrHKfhtg;msbDPF$YG&N7ozQ$5!f9GjPK7Av;lP49W=ZALbU)AFL`d_b0 zpWMGf0|tu*>Hk9$lFU1Ra(MHY8}U%$+bbXP5tnhMJ;-xBQMAoZme`bdzZ+u8Wd8Fy zryQ7X61tcBhGBk#T;6^aD?*RbV>rV<^(UOeLK(3jv75XH^8j_zCD|sbHip&Q1MZd| zv{kd_KXCcvKDO&U-W|2C-=A`ry%RGqe=j-Wo&$3D(lE@4B^s2<@~ZP?WwD8WG{ORm zP|Eb~mw;nvg+rzFQ!g%{DsLrA&wRPYmyQ_d10YSsE-P#tBcn9}iBBcA2gVI)$nnbA zBfwY)0C(7g&zVqe*4zMk?eH;5(PKgVP4djFF`Ba8c}n_iiA!<>rfD||U;*oZffT0{nYpSP>s~XWZE7A)c;$83GTdm@Vk%)sRymwMXgb1jZqBc7}#)g8!Hh zDNt{Qyd4J*%>R)bW=y#WbXu0Ksqc5VHJmTI9C%elo$4-ARQoA6#MXWXkzADHiL_Ay zcF%l43$}+zTpLE;-6~|M`aJsk@iiE#sB`mNQgJd>lXQIhUhiH8!vv&n%+7lNd3 zsN95)A*tK;bEtW#Hx2E$%&GfJosnX7)|@qLvGfL5jye4cm353=;Ue&hTI2)~jAalO zRgV;hQSg+&`$CMIsPw$;bj?{UbaR(Fs~(G}d&JMOK{op8AM*YDqD7M+GqOk`L^whl zke$Jg4vDh8q%fdOs+phrJhn{5^TVdOFI4Dtc0VjsH&{Cg5=0GwKApKND2mD6V1EH3 z9@&o6K(CPgFu}!R?gXEEPs${Bk03waq}++YBfterT#gjrulU0_Un)I}IB82h6MF}@ zprzTp{tpdxq?u8DOqafs`qw{hCXh#UdmWB@-jG}t_g%jvt4gYs&w}6nNn9*ApI6)Z zKeRL;;)&K6k(34i0!Or7QqR z?_?1)LzC!6q`V>QH_#Yb=p?9+RyR-G5=zi{h1t!q7!Z%EJvYpFN$MQP zL)`03wV-xz>KC=)$L}63NVu_27yH)pq**RZqNm zjQ_<;5M5${ad~P$nn#oL%2C2hiF?(w)ZycT2E_O6rs<|ckjFF!_r=nwVSd%j1{2=e zt=AwTwNUmKh!3Es@$DVc<-!oyo>Y2=^w^X>!>(Wyy@Mar=CvM72!+d+f^}?ab^_ zfdq-c;21RA@8x0>DKMmnBE6@OwhHLo9Yy@X{I;`w*`h)5spLDG5%Nfn?gx6CkvGXL zW#RPZs-@NAF$~24A`kz3Flg!92DFr)^&|{f?oSIv!cO!^nJU2uLcU8JK}+A2GPcs;9po&=4A778Rb6pIA<%whVxrG)1rdomB;WpK_iC~X0jng^4(lF z{r6n#M@+;HKNlmkN-Ok#;s<;3mcR;dHvHLUbNdsUaw}ph{G;Z11P{yzrCBnTxzsY5 zQZ=jPY`8Zu@N(0VN!I4xw(@vVi9IVQV_rfsjRhjs_#YZGYV5x3Ww6`( z#aAvjRP>v{%HL~RUf+IEhvF{Rit-5LF%|A6IEu-1Mcw2jr9MNs3#kPNtBgVr7p#-Yw`|=U}j*h9B zU+pz$Lw(^XgsLTnE1AO#1g2=B6z;^>O6evcF8&=;?aNs;W=dY|9tYJDe@s3r1U!>9 zM+)JTtxHx+KAd&5m~wl{=S0bKz5?DiO!`hz^-!9zWl3w!%YCGx^wNdT$pAYmC>N8Liy{bTIg*y z9AA}BHsj?wp>!T#5WIlkE4;jHo0V|%w77S#>!_yJiqZR-{-qdALur2dUguQy8YO9Y!dYNl1~ z5nVnGxhOT3#}q0_xXI48ulks246LBJBOW$J>QBb-Q^oE*44UY}{~erTB1Dghj%JFG zwl>mf#hasnu!ju$`rnbm^;rz>C8s!_X@xw0Q0NrG;7YH5z5u`7+Ac5m@fWq8ax^Tg z3sRBD2f`9lSfoRT*$?c4Bv37uRe1R*j)X=$K2_A#JcP@;pVoqZL&Y607@`G0W%0~v zME^5*`&Z_2a)ri;sXP@dFE%QE57Nk*p)9|H@g4NNJIb-pS`c!ocKyTaQeOy+EvMiQ z%mswsdQhJkT_htz$T{;~tH(xTin`;L4_Ki7Aber-J0TW8D8-x*5vQr)rbgAKRFijx zC0JV`M1YUiQ<;<`6^*T*T}7n%3)L6opnSJ|vN)es8;(jbwg(#WW+GOQabd1%g5pML z40`p#B<{Kb$z`MRkrL`anVHuxPNLHvxoBWbu}?e%BY#oN?9y8LN>S%Fv-H^(lbsFU z(OrJ#>6vb8Pt+vN1#If|>-LEF&O zSuc6fIy;wdaR*8?-Oq*4UY7XE!PK!b^dFkqg4vIWiI9a6q7B7Uj-G3=F-^;4KBt$a zoe$MZKTqD9W<*xTJh_H=*hA9)C+RatalHwPth-)a6-osu2wm|m@6HG_RBN^glS-X*pp!m3aFcYT%goKc zpNY$C+0wATbI@=S`;ls~+vAG}mXyeeO(-mN%#Rf6qnr7TXJu9rO*QhJ8`~JcLbUZ3QcBNXT zmumbcw*huOX>XVUkX`TUqRs-~r{6(GfIa4>_g1 zQ;2lJq9dAs(3j*1Rb9W!jI-t#DuQbd*1Zt2fAMCG7OM=A%BL@^u|+b29V=q&iK3$i zXQ>p#c^7Hl@9k8t7s-q*V!G9pl+srzZHChyfh z3W|)n(dVq~FhV6nr|SPOxiM4}K+;eMh4-rk3H zHA=O}$hGmdR)%B$mvy!G(#4@j6+P`5dNQ$-T9M9&){X)-c~=|m>f0O)^i6QWvkJwv zFAsT>6)V?dQC=-SzE=zc0{ji9(@S55q^v<=uI=u~uV=i9jmJdtsULG~C3C>M+<`j9 z_aN$N@3^_z=T%xa0q!RY))3(IKA!RDE+(Ipi9wl5-|-f^xdQXO>Klx=h+-NQ4EGIZ zJ$(1)WGFI5UW)a2tOH7C&XCi++QWfw!A8W&8?_v3vX#*TWGuMO^QLJ80?{&DW9h|D zVkPpub-hY@tF-;2(uTF)s;rG1gK+Kz^qlOUPZ4V>*OhUUt5|hy43ioT5F^YTa2D8H*Vi2lqx!lyEdvj@Js$E?^D5~N>@p;bB@q=%!ouLWoOJ_mLSzS7mm z7s897QTF|$xjDkWt@6xL*mWlMrXYSi^9G1%>@#E(9|H$ zCID4u6&f$7Tc0{*^V+-yRm3y${3MgYCF~H|h%;qfBhNfc)0k`Pf8i0o9vn~BLb6H0 zXe|1A)1c%sEYrx>1m+?L7G%v{2GY75I>}!*<-{??)~{2dW4x4Q=y4U9*cS>-2@7$s z-_{1Uca14RjeOf`kfUe5HD>;y@u`n8LJ?Jot72wz=vW`kc`Vw-ZLL*Ux<2?Nr3FR9 ziX_$Vlaj9`&h-~m23u3%YRUsmznDAGlx7(8ZG|Kv=|h&VH0cY~Kk+|%zC62Fu`GFV z$Om+~=^|-+Y3nqoMV7JfQwCqQYulqB6|`RN&}HASu2_@sJx5~=Cuu;+PuTqD=U=3b zb{-2g`wlVQ^iQn1sSO?xq9zV6r;YlCOOZxGTU1~KQGPqkd-Hi=9+r=ZM@ofsVKexN zlCSn8v#UAAvxXM}pEGgoQaA4ZlfJE2FHh`h%v`ic8u-|z@mg;Y)oFEQF z7t3N9)qh&76SO!(%^dB9d-VmZMf`Q{W{s!qM)G5KuGo9N52yS(noE-v_QW&j(0eza z0a&3{;Fl?0TWs*G)9MO`0D1n^wVt#Y3d10U?`sh=YH!^p^7f=SqF=izn%WT=0e{hr z%4$LVfRFT`=EixZYexBV6+X|sVw^XWd!>T&ZICl8FHZ2%Rw#Vn5@v&Fo$QcSLJX9Y zpYTx`t9Y`-Wl8a8t?isY?tqw*dM+t#8K?dJQz zYAf+FdJm)AA$c}AA!jfA-Wd4!5Y$pQ!bH6YN^5y2QsRPFzNv#!_;vm><+6Ea=z!5B z!4)x!oGzM7;ta8T(mh)z8>q_4B*|0Ea?_tVB;gl$JxGS0*pK&c7;cM+YUXbJF=(32 zZY|f$*!xWLA#^_rqZJoq3hctSb8jjSF0*)pE?u7U!RQ3KiMQ3mQ`b!fhuvP&HPu1< zc7P;`2gYo8nwO=+L&+i06wO-%#(Qb&U$!P2xJ+pG!o*w!g`zrLwwLD%FL~n2!ADe2 zo(u3nP54;7+fl+hy?4-A==s+>lmarkEVjQaevdV~MUsghW z!!skdg-jyZp&v`1s;2M^c>)9TCEy)FX}z1nwdP&dEPLC#^}JHqPQ{8|2HemnA_d5v z52jm8H?kT(S@;hc!9!v>ic}JRPgM328?Gxm#;H8X{te&6%kSXvfWZMrMR8}+>bs9~ z;8NgLk+mgB?D&t}O@Y$4t!cF>Y4cdNtLuIeG%MJjk0@TDsrPLZR}RZ9H5f%61|8iOo=D zkyDImJnKa`zNRcrVsL)E$=E!pg45%rX=IZ%znTcA)4PeSn_0| zY>Cj@E=5~l<9%ga0A>kMEXG7jYerJj=q^zmJSro!fhCiM!#yAYS_W1a?+9`o`;w=t zmAsk^$K74=`uOmRC1>TZbp~7o#^kjyu7e7+-URKWZ`&_dB3{%6!=z-!_!@aD3eVal!<{zb7;IT4b4ZZm>Us*ReBTKH(KjxeE5Ue zb7#lYbf)=B6>F-TDLoY?p|Lj-)?o*2jVb;K;$lN+6cq{q5hVB|OMOe2>$A2W|JF?i zfMdIBgBav4p^n}SI0$^sQn$rkK(RiEgi4W5=^zu$u%XE(2~JWQZFU={=%n$nOh!oT z8wCy-UzgU8whVL2|K3#ivhJk3HvhWpv}8LqBzA~kocoVBrL z$I$?<+01m?RD;=GY%EoU>1_nYw?B+Mp;4RZT^!0pn{ctNY6}|~~e3cnEEig}2Lvz>}{H=?0d+?(34sQ#=MMI+8kG{T5 zV>c7bsH#FZ<-8wKcCOwO5rz!Aow=JdXna0M%s}n?bR%2L89YPM`4DmQ^O>6{>GvVSS#>q<0l z0+U8`y~GKUUy~RqnzHVEEkY!N5DD83@E6_Q4M>qG$AI7kiVLsR9Btzjf0yo;)UR$! ztLU$%_0{dLzIF^}3X(3tb+`TJgpeAAE%PTU9|~FVS95Vm?npj!fNfHC?eytHkUkgY zA1r==DKqpBG$aZuU!f0;N;fZ(Yh~15FLrlfqCIZ)ox>|hY`~ec#Bmj$>iu7v_P4*| zOSwK*DDS!6dpFbU%FV-r6h!dIdE<7N_2*~!Q~b(Pjm_`En=5ROuaMbV2yc%PaAffCX$)eTG5%fZ zY%lSEqzG|Z#At9wetSH4I~kvLeZPnj_zMpBSK9poaK`3K+m#OSj0JMaMmO{E(qh8; z!W?o$GAJCg2NJ%}bI_=xdzy6rznAmt9azco-+v13uL`kObMZvx9l0%BevHo?G+#J$ z$MMwP!(63%h2H;&pc7F!fSLT=kK!xiZv*(;%Kk1`>kT>DKp%G}UU(|S()rGNdm*sd z4mz4M*F%e55}I|pBjS6^+}+JWWX1c2NUN4=}Wuop~u?5anq+{WH53SnmY$Fb-|DjP0r|xF?YeW+vuR+PtkK8VU7gRiu zQ&Cz9-v)qAcI-x;YNR7v{ZL(}K*F0E|=x$U@@dKs`NOuh4_)s3XpXdp|!3NuG9dt~Kw+9N3;T z-G@g_=^V-x2>PAceIr;*0rKV~2?z4g-a^L<}kNy-wSWVIbK)DAnwXYsjtWyJ*x>)X{bygT+%U zKG}%bi5?vsQ3Y(c4L2WF!nl}$i^yedOH8wX!FQz}PIhmbyYEWF*a1ypk>q_;%g%}X zHTLo%pqY$1318YSd^4c73^}540lFtOgug+uzHYU>jpKP?VX5;S@y2H5v-jjRn0~#O zsTseA!anb%?0p;mkXT}cHUIhBPpy^h%CYdbD$ka(GlcVE2#qhtfG#YMP#S6EYTKFO z%A*oyKW&rprndU(Ic0bxT7_{mEIO||er?k~TsJTzfuhF)=j56IOCh5P=c2^;XI|P$ z=0Op0KvB^1CdQ@R9(@qj(J)Th>*u??>1d&gsiHgXshHI4k@iQ@$;sr>SQP^pJA@T6 zfd+@ss6C6qLGhbjqN!QVRr{4(i>&>^g}LPeE0Ru4y)ObdJK6EB{%GQ)XX*_`e&E2S z1)IIZOC8i2a94anoI?Da{zKb$n-cov%BQ`~#m>~W#MT+b&d^AzXJXBzts<^y8fCYc zZ5@w^ozI852Th+D8=Y9v#893u;rxeI=G+*k-X-@9D4Vjr9phjfO?eQsar3Fv(S0xX zZ!~0%3AGN|BE#OfJ|925Z+O9hz$2N<&-yfb#es@6^{YJSdxrlXntUk2 zVe8w%-QQ(^pV9I@43_c|!Snvf{SIgV`L4N$p9A&_mCY&*^0)9dfO$nCgFh@vO3=^A zP61xW^O?#gmNMlr71#e0v^Atb(457Zu20(dg#z;OvpU!#O(#Q(GEIhE7Q2JWMga@a zX9_@gsbjK6FEebVIfoX5DTtGcW|4zOfqo$s1GY;el78;wU`=N242dVP4a*$==HA!J zE55u4O;|nilu_(eHFN%Zid6rKj_>(cdX5ESJ1fq4Xs;g(!VC=Ks|uM5^Q_v-bdyWP zm6;7NinR$tyw1bpIY{VKLUckDP61v7T~>$>oIGnRqufNzvy!*8#$2Kd(akwQ+)rWi zigUhP!ygS(L&0B|gy4N%#ezr5XW)VHJ8}Myg*my(z_C|C+8cqWG8i9q{wYq(;L&tI z7c*OK{ZfsZdqLt+FwlIlgBU$q?B7cm^V3o(G zS3-Z$HDZ%weG#w#?869wq_cfB_}zhYH*ZeJ`bToghU52wROkuX=w-9kK#HA<%4z@N7fP4L9t8n)>RdoTkmGnIJx*m(=!CrRD~Cl}GB=HKvz|+o;O}DA479%+ z^@N&BKcd88;Gc9r5VEZKF|8)t*<+$s;YFoa@;FXfI?ffg=fpl9h8DVs4}(F_$fEkl zpFcwGt4#pHA%=m>a$!z+id%U!-LuNy<$$rAs|_mE@VTTU&|x-3aqTBNR0& z{y*(~XH-*Rmu{pNF;qc%?@gqG1VnlXy(%b0Dbhtcp$JM1y-EiG6%gqvMCrYTBB0bz zr6sgLi1+x-+`Hz^UElq2XWjWT^CLgb$yv#H+kT(@?C0J42>tUMC-e%#`&`tJe+lpH zh>>%1%{yohZK@(XzYfX0+Y`zFgvH;0aT5-F26ErK68NgBXp&U7P2M(j5z@)mwZGe~>cV7uqDLyH0tTb%CT*F2$c2Ju@ zvEMjGugVOVEr{Z8)+0&&fbMuTa|{RF6rdfupdK6JI)sZ4YBg1y*Ig;CVd2~zEQ)_m zwY{+fK5uYkNZ=SeEbCP6!u-hpse9l-s(sv?B1^a^Y2+<=x7Hwn*>vcwt9wg!3)ok9 zKb{>7e>IAY`O+lIlzZpSmhY|fx7}nQFXmMH&|$c10KB~yZva<<$c+Fgvr=K0ELee* zNVxNyTkuyOZKo(wMshDYHh3ktlmO|mmh(dqlQr3{|l3)|9!sATM+SUO2nY29E0 zAK2wFSlM$CTfDa)=CI&vL1^EV4kR%U|0oETx+2tqTRz*|lZW#xP1Sx!#IIo^H__0S zQTcxd_yk*pmMya&qU#<%Ui!VP@cqCzjvRn0qqN~6+w;Bo)o$!sGZw!nhXQg}Tb@2< z?pL5L_R^^RL6h~vTcvj#vB?OL;+*nmgoy_^S~*SZd+wDn28SN{#Z(6IIEiQQBna-V zW%jw+_(jV{4FBEEZUR%1{!?AXzI>D0sP-RFlKc4+=xbIm$-~iCcpn(XbJah7cSx>z z;%g)`RHwj*_L^6Wjxfn3)z!yaF^3h4@kq$#O_*%y=RC5|rVwS&A#JZzaTj${n6@NU^HE9*bo@E2Hm7zzqY<- zBv~ymm879e+ADcP6nJMJz^0>j!o5^qpp$DRV^gY0@vO_Mlq=A->#$8`gdBU4KzdVz zTHP6?>6t7IXA#N6{%GKjRd`|etQp0ULif>_<5KWeXd!t7p@kPGH7pl zkC>i9jSmiD;_Um9`^kzIO_yo~8;w|1U5QCnD+xL6=&)x373J8#lwODpmg!wqu`=0~ z(sEqs2HD(?wGM6E1O|*Mti%i8+Gf0--?g1|f6>;=cWVXKm`En9*%^`aISD-~ylyP& zU~lx)KHDAxK>Zy1%=Cv4)Ipy3^Jzq`r8oirM$|D#4Vbk zG_8{G@Sw3lExQKvSx&9Tv(P?~MK`1Ss>wm+yk9(0*TKJ_a+^J# zPHrJ?$vMu^==OPV)%G?%h9HZGTAOfn%T<5obq=GmXqRZf#$`0%OT6jDWEV6RC=CVg z+VU#yTsh1i(Z%p`$1<+fs|k2=ULFm9Z}msdA!uRJCs>KE-$OsQ21=CV?$tid?T|dW zZ8{qq81k6XVir}m!Hne?CjanZmz9wwhfh$AjGS191;-T=_DKOGmNQ0q0!BmdzS+a! z#z;nE^z<|!1y9l7>3=UgLiUsT;NAxfpp1yswQ&@U^bf9(h9&G^5w`y-WTeBUXxK!c z`0!nivbQhw1RiX<*&pG4?7T0@g1B|UQl+1~Ej8}B+s_<`>&41vq(Vb*#klp)=;loJ zXnOpI7uT1*oI^YJ%pV&7k){_8sE;rFBu8Tycb)=35OtO(tt1rM@K!9F#frx%a9K@s zydB!Z-+k!Vq{ZppE;Vc|kq^&Nxdrso2qvq#?x*Y7{A4Og*{#%y64pYxQ=z3UCOu!K z-M>DwSd^G11&^2Z`xwlY*$i>oxSbm5M@Ab)j?D(NkheFWD)U`FHH!JmF=C7N>yxFZ zx`g44N_l2f4g3nMLcIy-Xp9tk|7_UggV#y^YozKRl>u$}INJqss!NnO4y)-*(t1YotW0~-eeV!FFFxUcQ;B*>bXnG5n#ozm7M9p~${H14Gz)P3{;Xyb zlCC5wrpS+2@%w^SRDBp4WXKb$wxr;EdTDaQrM@nzcVX)Y>7By+m>c<t(^d5*LGL4r6%y`y3BQ%2{bTqP)c?J1)yiaBxsCfGD}uQJm0S*})-Ur$8O=*D%byA19Y4Qzsl0b{sVP zNt9sjWwNUpi4#Mmqz)wcN#P`~@r{nVxzx`Xdj{*6Gvna86D_;5n|bJmF(&m=!m&PT zdo$6*HBxn)L4a@%_YtF#icLV3M?KWj{LCnOv?z2N(P17&y!wNQ@}5l^3}KyR_xwgxn1I#5zW)%e8#JVkn?(O?Z%3Wx@fmyh+Z$?cCid={mk>oC z7XD&-EKW-?NN}&nGzdTfPliVD*3h9nKlG*k6)Ejv(+9mEMNyMQvxa1WRj#Cf`L>*p zdl&LN4Xp-I=eE0vjdOw(E;k+(EFKX@Z4sJ19N2=w{NfMqcnvNMe?bhwlw4qW!FNAc zp5^gPwCY*^$mCm3OsvQ*DSH;e!Kzl~lBL20ZIFRuN0UfLm{~hC06Y8R;Z4`g&w+a~ z2{GlfpjfvwVPQ9VoDAC?2boKA#q(1y@-LyFhWJmVMY@%-SBxLeis#NZ$Yp=4R=y9{ z#C!b2YXq$s;wGmW=bD~;N?yI$kY~!2D$aAeiPa+U+5#WBcm8AfBLbx*W9)mppO+dY zJCg_3GL4Wx!S!RriMYj{tOO1yh+1XJcr!&^s~TP!jaQQYI8L@txg04*myq`kDIxZn zu+k7)(<0rY8S+ZIQ_Kx&^Bj;WuxL{dSdb*^RA?vxy5)lK!1>I#YE6Q=@h3GK_$nNb zZa|)PFl;wo=$;cJQHqNj6pQ;vUu-o*SJuU&?nf8LoeE~uGUyUwi8ijUB~i8A2@@Ep z4}a0;72+2{0>?JIz0VcDZ~ycAhi|1(3KxW8vfBup=A9na((+zfdBeq=zAW58KylDK z8^p3cMCr$)tkFxuH%2mM)20nP;Ch6OsbtyP!$kzOp7-&Bb@n|Zop!vv$)HpG#$<3P zl+rR9Ou<|R-XNtCh?AcQZDY*k4Dew^<&bF3iCB6HEQQuS{=~PL5+v$^9=eh1eb^w? z(sLdHmWQ zlQ4VLDgR?D|9q=jb751Yk?w3A9pK^KQq{{B?C(n_Z^h-H4c1|nhzXBcN48o8y+0s2 zv6Mre#j(EZ;F|39gVf^*1IWwr78}P&FpX7;eVd9 z`G381N-gi7&@D-gw6I_xVlR$fUApfpnY!*ZI*F#T$>%ZtKV@Iaw;fT^nj~ zBbv3fq|9Zo!6X2|DZGBo?`mNsRO zXw(?C(|)i>)a7)ZaO=~~q&f$=_(9!%m@C{D$7W=SH8)q?OI>-k8pgAZ;MwBH&U+AU zjn*vis@V2vP+VBxyuZHW3Qu5P-}jEx=KrA^-R6j9XEOR|+ucs1HGbP%6|^N3-|~-c z@51e^gT=!gx9d=2%G+7Nn|EXnNzu&FV(Sa20w?MGa8kKWaN(Dn$%vXUL-WXOU7MBEYkJYr=+=Jbo4;|q{WXJe~cxhGpN?$4WP2% zjg_2c@|uYcgFi?~rMlC}ivc{lBA=b8(gmA_L|SdCopzBq+5*yNJX~&yYQHjd0B3S) zro6;U(%Q^lnRjVJey!IOYy7Jm7#GC_&tH$GcK7HJ7(-=en6T1>>=I@#%z>XI%nzEW zE<)33Ud3kVycM$6Ya-p%zC8=Wyj1MzN#DMiwj~?KO%`UByfQDtACn;oYGqh6H8c~r zmMXdyL0S&@*eVyes<@k+dDW#cVkh&r=QDXZ7cWhD3>E@Z8qiv4jgX;s=7m8!gNFD% zokpWn4K_DzdePr*qkFmy^`d>gI-MU1nMzxX89u+`tYJ_k47<2)Zd(hKfO>b`9Ldh~ z-au`(W9~hGHKbs|Uu&>mDk`%OlE>@FXFR#$JQe{-Y4^8=c%Ria5k+gVW~8{?5I#!q z!gkvazKTN6fCbf`Li$+cXbnUV&{(Ub=_d~_!m<{8UJI^(2>_>3%NRpdw*BkbbYsaO z1=Q8qo7eT;R4$b~rD+>Mo8WM4+X`*y+!E$sY`EfTvg@ssdGzgRtE}H-{Igz}Qg%W< ze?a_7A|b%0-C7Dt zJKna>zqnc8jyjDiD4#sJnYBFpl4%l7U?Qb(lXIp->z*&aQ*$2(tlkdH5&v+rpE@3V z`EE1DJpu}8zqaXzi=QRpbNy}h!(>f@ExGj1N&R*qeBtIndguedv!%c)X*V@YS-l@( zGW57pBg8w3E3}*o^}Qq86&8CFs@h`_V-y6scK68qANKOSwR%+YH4{O#MVk1pn`4NK zLQ~w(Wd4wy=TuqVa6iAjcB2$;r0y%r#P7Z$r~pyCR6ru8>Ld9<}%V@@x)F zBqDwF&X{h8cVlVIad%O6Pufue$6yb^5+;fxeWY!oN#epF8}I&oH51op1JEu@13y@h zVT>kXx@Nxs5?p3&H3M%WyoUF-MMpf7_RxOu2NVLBp}fQMNiCGa&?>MP#c}Ur$BrL% zWJ`M=3K{zeNP_KOr@0@bDv&#~(p-N6#(o12ymzR(k@=i0d??J<3os%+%G7kbl85r&wl035bzP~ye zPpv1uV3~FPF5e0u90EpF^dWDB6QU$Eh@5k`FAd!ch2Q^Q&AknGafItZd@BWoe~)dC zMQGS|e9KXY!@uOc{5Ly=S)J+RvlFYl1+$jeou51G3ai%U8K-3gLh)Y_!w`T+Eqn^t z)T*EmsBJhg%}R?lN;kRWTQyHzkFj0xs;r|RxgVhC2LR_70@sInQuF}#G4*6bAl1hu z(&B;>s>Z^Q>`Yj#nFIuI`3H_#(Nh5`Y#4!bnK90#0@6{%=ckr~giN(OPA@FB?zK{> z&+S+C@$*t9i2BAkHV{MF;b|crvkUXNJPm9MO;eQ!ele9>p8OP0VpE%Ircra5X7N^P zcX|ZtY|6|+Pdl5Hr*TjMS?lqWX;1Kv*;)6Afc}z#i z?HW>;Q3qbS!nfh2oDZKC-kT6z^?Tr5>OlyQ*3)r?cvT&!Yl1)t${aUA-u~t|pW^$L z%s+;^oJGIf_wWZ_=yG5*l_}jh@L?FNN|X&r5^M=R+)U&(FTsY3_!yzlC7Ty zo#-k24CI}`EVNL(I4_Z5=X^s-Ez*rm7%RfOx)@t;uB`asGXJ7t6C&IfBy(EeBATG;8lr1tk?7Q;CaR{g~a~T4dWwW#SD6j$GX*aGN>cdI8qKjaq+YD z*tW_Ml!VMftR=>fGKtdKsv_ES%AYv1rq&@<{vwtB9X-UuwJE@Y`xPli2qDEHL<7MC z*<6HVsraG`V>XNA7Mph5@|@(TsJ`Bu;2sj_X-rJ+7RK=z;vyYjPE36xsnVywKDRk% zpIV{!qbtP2yR_bbb!NHjMiNvr_Er4?T{2R)sIUl=W{*kia0KRq-As)#>g}KmR2a(L z#a?B^sm?z}HE#2A-~3hQH#6gC!4J`d&$jeUuVEU3LPjoRma=d&rvugV?+no#{?BpR(MY3A)+CmA=&X=(13esJZHLXZ}-6X7r1v?S0A z<>%oD*@a*5W}I<+bzhRW1CQyT>@C?Bv7deE6Y%yQoOJAy8u4T5u(ZSQvZS&07secz zErOF1&ttV^qb2Z~e%QlZv&1W9thtGg$VHek7tp{pw2n4mkAkOd z&{qz#-zYiW)F8o6mHvSG-zfW`wa84oumDrY6#EBsYrz8#_#M-%e}Cm#-39kqPJaoe zrb$^I2sY(f-3M-V;X@G{#-FgikYGZ}B5XFCH9JZKww1{Klr;N%e#o<^6?RbxXZ@NT zAqv5ufL)T%4ATyu@)E#J0FOop0YNZE<=H|U>$L`EG!Jyxm;t*Uxc-&K7HEhKCX$1(@OTFh9`a^fSsgK~ zP{OtnRD29dF~9OiBO9{8tl2Mx!C3Ucn?9(DYjhKF;+HU)zGS`5n;bxM3zC=CMx-+K zoFyKx`r1(g0tgJMNNMP6Vb~P->edLHKE0C~4)m=)rYvP??Wd@u4C&4tq-obGec$UE z(h3Cb0*;Y79i-wJE_^ZW|9Y?bBqZSrONk#D8-Z@!kmFP)v|YB-2`WQ#O%J1o4;$Fr z6Y0-0Z%VE#+fjKkzFx@UDmD`WtFax`yYS5-O%U;{X{~$2w4p%4zd&*jtF?Zxsg+)< znO=jXvu`uHhH`%9Nn80bmE7X+SH?G&Pe~0!&_U=(4Rnno3-9Fo*yw3fG9*)7<%f0e zJcS48I_ajyw#zY~&4Yi0K0>p5h? z?SmZ0?$K--ut29f>c%E6P8v-wLcdXU~?H%E-WgSgyx%wMr?3GDJ4@cWE-6bgXrv3w{5(Q3H)` zeevQ!vv3`2c&;bJsn9mf0BYA>Z*C+s#Skd52}F|Yfr#Z@@#CNN7=rH`9aBufrr$;G z9WVqj@jCx3NIR*${nI1|C%%@tKa zIf3GRU$Y)bS=o^WH8u#6V~RoVq)5zF#bN3RdIsU>9#Xz2LH=R?vCgAZcRMi_f^sv9 zm;Sw(hn@|BMVnO6nAYuo;(REjit=dr}lL_OqP8)0XkQ$2|OD#q_$NyxtvlP z|BY*^TyRkorJkR&x&N{2I?d}f4P#XXMrZaeae}-lQzmZY65fW)-iEtAP_15H8&KUeP|C-vzh%_ulO8fuclCl3Y`QOX+pHX2J zRX2oVvqo~7g g{^@J{yBg&GMR&meDB1kKSoVL~&;OB*{qy6006o`c#sB~S literal 0 HcmV?d00001 diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewd b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewd new file mode 100644 index 0000000000..5f58df5569 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewd @@ -0,0 +1,2966 @@ + + + 3 + + Debug + + ARM + + 0 + + C-SPY + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewp b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewp new file mode 100644 index 0000000000..ddeea932c2 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.ewp @@ -0,0 +1,2209 @@ + + 2 + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Applications + + $PROJ_DIR$\applications\main.c + + + + Compiler + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\stdlib.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\time.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + + + + CPU + + $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + DeviceDrivers + + $PROJ_DIR$\..\..\..\components\drivers\ipc\completion.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\..\components\drivers\spi\spi_core.c + + + $PROJ_DIR$\..\..\..\components\drivers\spi\spi_dev.c + + + + Drivers + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\board\board_config.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\startup_hc32f460.s + + + $PROJ_DIR$\..\libraries\hc32_drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\hc32_drivers\drv_irq.c + + + $PROJ_DIR$\..\libraries\hc32_drivers\drv_spi.c + + + $PROJ_DIR$\..\libraries\hc32_drivers\drv_usart.c + + + + Finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + + Kernel + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + + Libraries + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_clk.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\system_hc32f460.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_icg.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_utility.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_fcg.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_interrupts.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_pwc.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_aos.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_sram.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_usart.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_efm.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_gpio.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32f460_ll_interrupts_share.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_rmu.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_spi.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_tmr0.c + + + $PROJ_DIR$\..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_dma.c + + + + POSIX + + diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.eww b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvoptx b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvoptx new file mode 100644 index 0000000000..9b0935a9b1 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvoptx @@ -0,0 +1,189 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -FO7 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F460_512K -FS00 -FL080000 -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) -FF1HC32F460_otp -FS13000C00 -FL13FC -FP1($$Device:HC32F460PETB$FlashARM\HC32F460_otp.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN1 -FF0HC32F460_512K -FS00 -FL080000 -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM)) + + + 0 + JL2CM3 + -U261009725 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFF8000 -FC1000 -FN1 -FF0HC32F460_512K.FLM -FS00 -FL080000 -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx new file mode 100644 index 0000000000..2d95bacb11 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/project.uvprojx @@ -0,0 +1,845 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + HC32F460PETB + HDSC + HDSC.HC32F460.1.0.9 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM1(0x00000000,0x80000) IROM2(0x03000C00,0x3FC) IRAM1(0x1FFF8000,0x2F000) IRAM2(0x200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(8000000) ESEL ELITTLE + + + CMSIS_AGDI(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F460_512K -FS00 -FL080000 -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) -FF1HC32F460_otp -FS103000C00 -FL13FC -FP1($$Device:HC32F460PETB$FlashARM\HC32F460_otp.FLM)) + 0 + $$Device:HC32F460PETB$Device\Include\HC32F460PETB.h + + + + + + + + + + ../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F460.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFF8000 + 0x2F000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x03000C00 + 0x3FC + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFF8000 + 0x2F000 + + + 0 + 0x200F0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, HC32F460, USE_DDL_DRIVER, __RTTHREAD__, RT_USING_ARM_LIBC + + applications;.;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;board;board\ports;board\config;..\libraries\hc32_drivers;..\..\..\components\finsh;.;..\..\..\include;..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include;..\libraries\hc32f460_ddl\drivers\cmsis\Include;..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\inc;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFF8000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + stdlib.c + 1 + ..\..\..\components\libc\compilers\common\stdlib.c + + + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c + + + + + CPU + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + DeviceDrivers + + + completion.c + 1 + ..\..\..\components\drivers\ipc\completion.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + spi_core.c + 1 + ..\..\..\components\drivers\spi\spi_core.c + + + + + spi_dev.c + 1 + ..\..\..\components\drivers\spi\spi_dev.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + + + board_config.c + 1 + board\board_config.c + + + + + startup_hc32f460.s + 2 + ..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\ARM\startup_hc32f460.s + + + + + drv_gpio.c + 1 + ..\libraries\hc32_drivers\drv_gpio.c + + + + + drv_irq.c + 1 + ..\libraries\hc32_drivers\drv_irq.c + + + + + drv_spi.c + 1 + ..\libraries\hc32_drivers\drv_spi.c + + + + + drv_usart.c + 1 + ..\libraries\hc32_drivers\drv_usart.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Libraries + + + hc32_ll_clk.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_clk.c + + + + + system_hc32f460.c + 1 + ..\libraries\hc32f460_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\system_hc32f460.c + + + + + hc32_ll_icg.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_icg.c + + + + + hc32_ll_utility.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_utility.c + + + + + hc32_ll_fcg.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_fcg.c + + + + + hc32_ll_interrupts.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_interrupts.c + + + + + hc32_ll_pwc.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_pwc.c + + + + + hc32_ll_aos.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_aos.c + + + + + hc32_ll_sram.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_sram.c + + + + + hc32_ll.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll.c + + + + + hc32_ll_usart.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_usart.c + + + + + hc32_ll_efm.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_efm.c + + + + + hc32_ll_gpio.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_gpio.c + + + + + hc32f460_ll_interrupts_share.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32f460_ll_interrupts_share.c + + + + + hc32_ll_rmu.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_rmu.c + + + + + hc32_ll_spi.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_spi.c + + + + + hc32_ll_tmr0.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_tmr0.c + + + + + hc32_ll_dma.c + 1 + ..\libraries\hc32f460_ddl\drivers\hc32_ll_driver\src\hc32_ll_dma.c + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h new file mode 100644 index 0000000000..87f5ae4621 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h @@ -0,0 +1,202 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart4" +#define RT_VER_NUM 0x40101 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_SPI + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* POSIX extension functions */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + +#define SOC_FAMILY_HC32 +#define SOC_SERIES_HC32F4 + +/* Hardware Drivers Config */ + +#define SOC_HC32F460PE + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART4 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.py b/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.py new file mode 100644 index 0000000000..b0b7b6a25e --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:/Users/XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/template.ewp b/bsp/hc32/ev_hc32f460_lqfp100_v2/template.ewp new file mode 100644 index 0000000000..79e93411c7 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/template.ewp @@ -0,0 +1,1925 @@ + + + + 2 + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/template.eww b/bsp/hc32/ev_hc32f460_lqfp100_v2/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/template.uvoptx b/bsp/hc32/ev_hc32f460_lqfp100_v2/template.uvoptx new file mode 100644 index 0000000000..9b0935a9b1 --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/template.uvoptx @@ -0,0 +1,189 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -FO7 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F460_512K -FS00 -FL080000 -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) -FF1HC32F460_otp -FS13000C00 -FL13FC -FP1($$Device:HC32F460PETB$FlashARM\HC32F460_otp.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN1 -FF0HC32F460_512K -FS00 -FL080000 -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM)) + + + 0 + JL2CM3 + -U261009725 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFF8000 -FC1000 -FN1 -FF0HC32F460_512K.FLM -FS00 -FL080000 -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/template.uvprojx b/bsp/hc32/ev_hc32f460_lqfp100_v2/template.uvprojx new file mode 100644 index 0000000000..468c5b4f8b --- /dev/null +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/template.uvprojx @@ -0,0 +1,390 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + HC32F460PETB + HDSC + HDSC.HC32F460.1.0.9 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM1(0x00000000,0x80000) IROM2(0x03000C00,0x3FC) IRAM1(0x1FFF8000,0x2F000) IRAM2(0x200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(8000000) ESEL ELITTLE + + + CMSIS_AGDI(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F460_512K -FS00 -FL080000 -FP0($$Device:HC32F460PETB$FlashARM\HC32F460_512K.FLM) -FF1HC32F460_otp -FS103000C00 -FL13FC -FP1($$Device:HC32F460PETB$FlashARM\HC32F460_otp.FLM)) + 0 + $$Device:HC32F460PETB$Device\Include\HC32F460PETB.h + + + + + + + + + + ../libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F460.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFF8000 + 0x2F000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x03000C00 + 0x3FC + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFF8000 + 0x2F000 + + + 0 + 0x200F0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFF8000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/.config b/bsp/hc32/ev_hc32f4a0_lqfp176/.config index 5df70f1e7b..7c2bf8a245 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/.config +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/.config @@ -78,7 +78,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40100 +CONFIG_RT_VER_NUM=0x40101 CONFIG_ARCH_ARM=y CONFIG_RT_USING_CPU_FFS=y CONFIG_ARCH_ARM_CORTEX_M=y @@ -274,6 +274,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set @@ -313,6 +314,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set # CONFIG_PKG_USING_YD_CRYPTO is not set @@ -352,6 +354,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_LVGL is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set # # u8g2: a monochrome graphic library @@ -428,6 +431,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_CBOX is not set # CONFIG_PKG_USING_SNOWFLAKE is not set # CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set # # system packages @@ -459,6 +463,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set # CONFIG_PKG_USING_CMSIS_RTOS2 is not set # @@ -502,6 +507,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_CHERRYUSB is not set # CONFIG_PKG_USING_KMULTI_RTIMER is not set # CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set # # peripheral libraries and drivers @@ -656,6 +662,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_CONTROLLER is not set # CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set # CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set CONFIG_SOC_FAMILY_HC32=y CONFIG_SOC_SERIES_HC32F4=y @@ -669,7 +677,6 @@ CONFIG_SOC_HC32F4A0SI=y # # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_TCA9539 is not set -# CONFIG_BSP_USING_SPI_FLASH is not set # # On-chip Peripheral Drivers @@ -690,10 +697,6 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_UART10 is not set # CONFIG_BSP_USING_I2C1 is not set # CONFIG_BSP_USING_SPI is not set -# CONFIG_BSP_USING_RTC is not set -# CONFIG_BSP_USING_PWM is not set -# CONFIG_BSP_USING_TIMER is not set -# CONFIG_BSP_USING_PULSE_ENCODER is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_CAN is not set diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/README.md b/bsp/hc32/ev_hc32f4a0_lqfp176/README.md index e914a61988..4f2fbca867 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/README.md +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/README.md @@ -40,18 +40,16 @@ EV_F4A0_LQ176 开发板常用 **板载资源** 如下： | **板载外设** | **支持情况** | **备注** | | :------------ | :-----------: | :-----------------------------------: | | USB 转串口 | 支持 | 使用 UART1 | -| SPI Flash | 支持 | 使用 SPI1 | -| LED | 支持 | LED | +| LED | 支持 | LED | +| ETH | 支持 | | +| ADC | 支持 | | +| CAN | 支持 | | | **片上外设** | **支持情况** | **备注** | | :------------ | :-----------: | :-----------------------------------: | | GPIO | 支持 | PA0, PA1... PI13 ---> PIN: 0, 1...141 | | UART | 支持 | UART1~10 | | SPI | 支持 | SPI1~6 | | I2C | 支持 | 软件 I2C | -| RTC | 支持 | 支持外部晶振和内部低速时钟 | -| PWM | 支持 | | -| HWTIMER | 支持 | | -| LED | 支持 | LED11 | ## 使用说明 @@ -79,7 +77,7 @@ EV_F4A0_LQ176 开发板常用 **板载资源** 如下： 双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 -> 工程默认配置使用 J-LINK 下载程序，点击下载按钮即可下载程序到开发板。 +> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。 #### 运行结果 diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/applications/main.c b/bsp/hc32/ev_hc32f4a0_lqfp176/applications/main.c index 360d45e00a..ce4baebb8f 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/applications/main.c +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/applications/main.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig b/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig index 890ca05996..54cfe142a7 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig @@ -40,12 +40,6 @@ menu "Onboard Peripheral Drivers" select BSP_USING_I2C1 default n - config BSP_USING_SPI_FLASH - bool "Enable SPI FLASH (spi1)" - select BSP_USING_SPI - select BSP_USING_SPI1 - default n - endmenu menu "On-chip Peripheral Drivers" @@ -223,116 +217,6 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_RTC - bool "Enable RTC" - select RT_USING_RTC - default n - - if BSP_USING_RTC - choice - prompt "Select clock source" - default BSP_RTC_USING_LRC - - config BSP_RTC_USING_XTAL32 - bool "RTC USING XTAL32" - - config BSP_RTC_USING_LRC - bool "RTC USING LRC" - endchoice - endif - - menuconfig BSP_USING_PWM - bool "Enable PWM" - default n - select RT_USING_PWM - if BSP_USING_PWM - menuconfig BSP_USING_PWM1 - bool "Enable timer1 output PWM" - default n - if BSP_USING_PWM1 - config BSP_USING_PWM1_CH1 - bool "Enable PWM1 channel1" - default n - - config BSP_USING_PWM1_CH2 - bool "Enable PWM1 channel2" - default n - - config BSP_USING_PWM1_CH3 - bool "Enable PWM1 channel3" - default n - - config BSP_USING_PWM1_CH4 - bool "Enable PWM1 channel4" - default n - endif - - menuconfig BSP_USING_PWM2 - bool "Enable timer2 output PWM" - default n - if BSP_USING_PWM2 - config BSP_USING_PWM2_CH1 - bool "Enable PWM2 channel1" - default n - - config BSP_USING_PWM2_CH2 - bool "Enable PWM2 channel2" - default n - - config BSP_USING_PWM2_CH3 - bool "Enable PWM2 channel3" - default n - - config BSP_USING_PWM2_CH4 - bool "Enable PWM2 channel4" - default n - endif - endif - - menuconfig BSP_USING_TIMER - bool "Enable TIMER" - default n - select RT_USING_HWTIMER - if BSP_USING_TIMER - config BSP_USING_TIMER5 - bool "Enable TIMER5" - default n - - config BSP_USING_TIMER6 - bool "Enable TIMER6" - default n - - config BSP_USING_TIMER7 - bool "Enable TIMER7" - default n - - config BSP_USING_TIMER8 - bool "Enable TIMER8" - default n - endif - - menuconfig BSP_USING_PULSE_ENCODER - bool "Enable Pulse Encoder" - default n - select RT_USING_PULSE_ENCODER - if BSP_USING_PULSE_ENCODER - config BSP_USING_PULSE_ENCODER9 - bool "Enable Pulse Encoder9" - default n - - config BSP_USING_PULSE_ENCODER10 - bool "Enable Pulse Encoder10" - default n - - config BSP_USING_PULSE_ENCODER11 - bool "Enable Pulse Encoder11" - default n - - config BSP_USING_PULSE_ENCODER12 - bool "Enable Pulse Encoder12" - default n - endif - menuconfig BSP_USING_ADC bool "Enable ADC" default n diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript b/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript index 03d0c9f875..d7b3e516ea 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/SConscript @@ -15,9 +15,6 @@ board_config.c if GetDepend(['BSP_USING_TCA9539']): src += Glob('ports/tca9539.c') -if GetDepend(['BSP_USING_SPI_FLASH']): - src += Glob('ports/spi_flash.c') - path = [cwd] path += [cwd + '/ports'] path += [cwd + '/config'] diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c index 152ae9b123..f6bb7402e5 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * @@ -134,7 +135,7 @@ void SysTick_Handler(void) } /** - * This function will initial GD32 board. + * This function will initial HC32 board. */ void rt_hw_board_init() { diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h index 92b2e7b994..191ae0aff5 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c index fd9fbe8d48..b0ce1e9c7f 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * @@ -46,54 +47,6 @@ rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx) } #endif -#if defined(RT_USING_PWM) -rt_err_t rt_hw_board_pwm_init(CM_TMRA_TypeDef *TMRAx) -{ - rt_err_t result = RT_EOK; - - switch ((rt_uint32_t)TMRAx) - { -#if defined(BSP_USING_PWM1) - case (rt_uint32_t)CM_TMRA_1: -#if defined(BSP_USING_PWM1_CH1) - GPIO_SetFunc(PWM1_CH1_PORT, PWM1_CH1_PIN, PWM1_CH1_FUNC); -#endif -#if defined(BSP_USING_PWM1_CH2) - GPIO_SetFunc(PWM1_CH2_PORT, PWM1_CH2_PIN, PWM1_CH2_FUNC); -#endif - break; -#endif - default: - result = -RT_ERROR; - break; - } - - return result; -} -#endif - -#if defined(RT_USING_PULSE_ENCODER) -rt_err_t rt_hw_board_pulse_encoder_init(CM_TMRA_TypeDef *TMRAx) -{ - rt_err_t result = RT_EOK; - - switch ((rt_uint32_t)TMRAx) - { -#if defined(BSP_USING_PULSE_ENCODER9) - case (rt_uint32_t)CM_TMRA_9: - GPIO_SetFunc(PULSE_ENCODER9_CLKA_PORT, PULSE_ENCODER9_CLKA_PIN, PULSE_ENCODER9_CLKA_FUNC); - GPIO_SetFunc(PULSE_ENCODER9_CLKB_PORT, PULSE_ENCODER9_CLKB_PIN, PULSE_ENCODER9_CLKB_FUNC); - break; -#endif - default: - result = -RT_ERROR; - break; - } - - return result; -} -#endif - #if defined(RT_USING_ADC) rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx) { diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h index 4e86ac5eeb..7a74cf09c0 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * @@ -34,34 +35,6 @@ #define USART6_TX_PIN (GPIO_PIN_06) #endif -/*********************** PWM port *************************/ -#if defined(BSP_USING_PWM1) - - #if defined(BSP_USING_PWM1_CH1) - #define PWM1_CH1_PORT (GPIO_PORT_A) - #define PWM1_CH1_PIN (GPIO_PIN_08) - #define PWM1_CH1_FUNC (GPIO_FUNC_4) - #endif - - #if defined(BSP_USING_PWM1_CH2) - #define PWM1_CH2_PORT (GPIO_PORT_A) - #define PWM1_CH2_PIN (GPIO_PIN_09) - #define PWM1_CH2_FUNC (GPIO_FUNC_4) - #endif - -#endif - -/****************** Pulse encoder port ********************/ -#if defined(BSP_USING_PULSE_ENCODER9) - #define PULSE_ENCODER9_CLKA_PORT (GPIO_PORT_G) - #define PULSE_ENCODER9_CLKA_PIN (GPIO_PIN_04) - #define PULSE_ENCODER9_CLKA_FUNC (GPIO_FUNC_4) - - #define PULSE_ENCODER9_CLKB_PORT (GPIO_PORT_G) - #define PULSE_ENCODER9_CLKB_PIN (GPIO_PIN_05) - #define PULSE_ENCODER9_CLKB_FUNC (GPIO_FUNC_4) -#endif - /*********** ADC configure *********/ #if defined(BSP_USING_ADC1) #define ADC1_CH_PORT (GPIO_PORT_C) diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h index b2e90e2b0f..41a7106422 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h index 66adf1daa9..85107b83e0 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h index b129864bdb..e2c3e534ec 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h index f5c400142e..6da295297b 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h index 25906040e5..fe5492d575 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h index 5916f917f7..b97ee50c04 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h index c1cb687e20..dcb774c614 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tim_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tim_config.h deleted file mode 100644 index 83924088b4..0000000000 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tim_config.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022-04-28 CDT first version - */ - -#ifndef __TIM_CONFIG_H__ -#define __TIM_CONFIG_H__ - -#include -#include "irq_config.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -#ifndef TIM_DEV_INFO_CONFIG -#define TIM_DEV_INFO_CONFIG \ - { \ - .maxfreq = 1000000, \ - .minfreq = 3000, \ - .maxcnt = 0xFFFF, \ - .cntmode = HWTIMER_CNTMODE_UP, \ - } -#endif /* TIM_DEV_INFO_CONFIG */ - -#ifdef BSP_USING_TIM3 -#ifndef TIM3_CONFIG -#define TIM3_CONFIG \ - { \ - .tim_handle.Instance = TIM3, \ - .tim_irqn = TIM3_IRQn, \ - .name = "timer3", \ - } -#endif /* TIM3_CONFIG */ -#endif /* BSP_USING_TIM3 */ - -#ifdef BSP_USING_TIM11 -#ifndef TIM11_CONFIG -#define TIM11_CONFIG \ - { \ - .tim_handle.Instance = TIM11, \ - .tim_irqn = TIM1_TRG_COM_TIM11_IRQn, \ - .name = "timer11", \ - } -#endif /* TIM11_CONFIG */ -#endif /* BSP_USING_TIM11 */ - -#ifdef BSP_USING_TIM13 -#ifndef TIM13_CONFIG -#define TIM13_CONFIG \ - { \ - .tim_handle.Instance = TIM13, \ - .tim_irqn = TIM8_UP_TIM13_IRQn, \ - .name = "timer13", \ - } -#endif /* TIM13_CONFIG */ -#endif /* BSP_USING_TIM13 */ - -#ifdef BSP_USING_TIM14 -#ifndef TIM14_CONFIG -#define TIM14_CONFIG \ - { \ - .tim_handle.Instance = TIM14, \ - .tim_irqn = TIM8_TRG_COM_TIM14_IRQn, \ - .name = "timer14", \ - } -#endif /* TIM14_CONFIG */ -#endif /* BSP_USING_TIM14 */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __TIM_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h index 32b6936af5..86d3bc24cf 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h index 326fb6bcdf..f7fd6ce270 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,7 +23,6 @@ extern "C" { #include "uart_config.h" #include "spi_config.h" #include "adc_config.h" -#include "tim_config.h" #include "gpio_config.h" #include "eth_config.h" #include "can_config.h" diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h index 5ac85f3cd6..a4dfcda0db 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h @@ -8,7 +8,7 @@ 2022-04-28 CDT First version @endverbatim ******************************************************************************* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. Ltd. All rights reserved. + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. * * This software component is licensed by XHSC under BSD 3-Clause license * (the "License"); You may not use this file except in compliance with the diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.ld b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.ld index 15541a04e2..718c7b4a58 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.ld +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.ld @@ -1,5 +1,5 @@ /****************************************************************************** - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. Ltd. All rights reserved. + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. * * This software component is licensed by XHSC under BSD 3-Clause license * (the "License"); You may not use this file except in compliance with the diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/spi_flash.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/spi_flash.c deleted file mode 100644 index 9934418c3d..0000000000 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/spi_flash.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022-04-28 CDT first version - */ - -#include -#include "drv_spi.h" - -#if defined(BSP_USING_SPI_FLASH) - -/******************************************************************************* - * Local type definitions ('typedef') - ******************************************************************************/ - -/******************************************************************************* - * Local pre-processor symbols/macros ('#define') - ******************************************************************************/ - -/******************************************************************************* - * Global variable definitions (declared in header file with 'extern') - ******************************************************************************/ - -/******************************************************************************* - * Local function prototypes ('static') - ******************************************************************************/ - -/******************************************************************************* - * Local variable definitions ('static') - ******************************************************************************/ - -/******************************************************************************* - * Function implementation - global ('extern') and local ('static') - ******************************************************************************/ -static int rt_hw_spi_flash_init(void) -{ - rt_hw_spi_device_attach("spi1", "spi10", GPIO_PORT_C, GPIO_PIN_07); - return RT_EOK; -} -INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); - -#endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.c index bda2ad7df5..489b3ce901 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.c +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.h index cbe44c5fed..532c691372 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp b/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp index ab6696c72d..77106d8d33 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/project.ewp @@ -180,7 +180,9 @@ @@ -1161,7 +1165,9 @@ tXe<`HiTM2 zt&PngkZ-lB0J%^_TQJzz*b)phHn%o~T3VV~11+fHb`B(bVGT`9B#sLvurr`EH#Iea zc0$tF8_+_*woqGhOR%kJg2Ww?!`{fM>_%y54TYLpLZLuQV@sf|si~p4p$V1UBcR*t z4Wp|#!*_3iJR^!9C~(dl%=-!g7Z}q&D3nlc%g{bhpjy6L5&mF-VFkb$=#vGm9RwBo z&f0Uw`$IBfb_{gbA99eV2miwk&bgZ4VF%x~;WstJA4|Kt?RIeXKeW@MHrr~C8T^mg z{ByU;V>bT+8|6>!0#;Xabml*^c~)SY4e)WBd5+fkgw3=A^XnVu&s8j~xXkSAPZYS8 zCDX>jrwZ(IwbQ2yY}=aO)J#vY1O0;oaw80(N#qy1QpO_m2g} zbSJ(gqLHm;$KcK#kxp4?Mz8$#G(O5YJIX6y?hDI#ileSth+MCVJ)J!rGQi||O(Pu3 zpJ)X0bb!QvXcT&_Y4J_52b#`h$y*j@h7G^usJ5D&e9uBA@ir6CmkN~sVhW5aP=3V} z^cYDg%;sGDxQkt}70O#4$R{MZpjOlGko1CbP5(VfFH~XoO0MH>7pmZfwd%LKj=aaq zmb^!nKd+2zZr4-T6qSyU>$3p$?H4OlxhCPYhk+%>f?a*v`*!Y;Az!$&ud^r8&*akZ z-oe%_kwGJf;{d=7&5ShS8v`JXK}N7TsQ?n~j~KXREsBOa2X_vbeY$BI})6e&deQGGrIkU?;pE51u~&X1#~TOjSIO1$Z9JNl=_`QWYd#!$%v-A;IrF zIbR5334X$Hkq2L6y$$FEWGNxvlL2BGz$;3AQHnKKuZ}QtDYA>I@DW*^#gy+)FzY>% z)rGa~zXCdiJnc0C;8xYO_(Fuw%em^p@jLUcKz7l!SbB5S%$F+ESu_hM+Xu^u-U7w~ zg+p29tKjuis6#Eb!8*re=4Hr;EItuC14tXl2Z5XnWQ1jrQqA1y$7mo}_DwWrh`LI>v%;()ojdOW^5kuq5=N&MO zGygRQj$uG=*|>`spR#c`@%Mf@dFb`CJU}?H9?TQ8&Vn`G44fZdeHMRa`F7Cx$&VA4 z-+`-cAI5J4{ya007*FE*6^SYQ2;i3-_-%l7`>_1|%(LRl_=kb&_%r?(aNb$u#5nf_ z-YMn8_~&ue?ZG$?0UdwFxo#bA#=iqx$Cq)QPjupVO#v)yBz^KVn%`pDg-5tUh79HH)xxK4qS2P^m-2$|yw`OM)`?%qnft}!ow{*1DL6BW(ghrw%OlkblEZQH1<2tT-qD)VZy$x0bl#6;D>~cI zYC)_03a#g8yJ>e-M!1Ozt!5E)n_0^W9&g;ok=n6+qagfZXkFyTPS_PsCC3k0Z$dQQ zNciNfmkI0F=g=31@&Lx-8Agwd9Z08gfQFOtgXn0P4Bm>*ZES06Y^dvPZVWVmHI$jy zi2ZjAhV?r_!1+_8jrB3>uL&NlSE|wz`OL&Ldi>}JS1}aN=Mz~J7>s8RCi3+#4dmqb zNO~jQ1sRKHkL8lLByx4?H=oYOQ@Of{@rhhwxbARbJb_Q$=2K)G%K6K_F?{Bi+kg*h z`HQ;@zHCUpTd%*ZA=Z(RpJT*&(?ju8Y%npF zi79XSc2Wq^#k!6W;rs|xp>U?H4c6o`sU&7ye5IJgRLbV5cnkqNI6h&lPuIr^RZD&* zF+PkgZd19N%#4hTMIjW<0PGB~mRZp@)<=GqAE(9!2E(XgTTBfPDxx3@Q9Gm`1>$HbL4zvWDo9vd+a zWYb4-31{03Wk-x|o<8iCRAjRao=pB{`jM=9RzG6uTt9keo%46qkGO5@euPTY zOI-Y{f3OoXHDBddWMFmWhO$&Irw}uK-~iT}8XLj4w+W5#4N=3mMcQ=SfHZk5KID|j zOdJ@8f*jT3=97;fz%`$h*YR{7<%iVW668^fA=eTidu5^4$-Gv^Gh2YyAH3G61Hd%B zhUVuEkPPNuXktB_`I&(e*I9T*RL>Sn=jRfZLv@m0i%OjJXqcZ@SPn~jX&2kbcIl+$ zcyoc}bb1l{0MGNokd-uV4R8%J>m)WF_Oo&;X&&3HVP;KYcjGgTvv197pCR{n6VY@0 z5NjnZ*9%<3%-X*RFLbl>R?@sZz%|UQsSf-1t&ZTx6lx5xb;=rYWE4RTL7 V3ThrdV>|0Tc>~&)3s_0Z{Wtxx4K)A& literal 0 HcmV?d00001 diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/ram.ini b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/ram.ini new file mode 100644 index 0000000000..4984db95e2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/ram.ini @@ -0,0 +1,16 @@ +FUNC void Setup (void) { + + SP = _RDWORD(0x1FFE0000); + + PC = _RDWORD(0x1FFE0004); + + _WDWORD(0xE000ED08, 0x1FFE0000); + +} + + +LOAD .\output\release\efm_sequence_program.axf INCREMENTAL + +Setup(); + +g, main diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F460.SFR b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F460.SFR new file mode 100644 index 0000000000000000000000000000000000000000..fc5ceeb8761add8d9fe5304028e5397ab5369694 GIT binary patch literal 1625032 zcmd4437DNlu{VC+eI}Dhf|6X^BL>BVIA`W00k2+}%uFD1vN&f5sAyckD~gDM%XMKu zR2ErW5k=W#Q$g7T#RXgtQ4mqtK@epTK@emUB>$@3-s*n)?e24C@cZZap6|I1{noF$ zx~qO&-CcFIU({$c9=-GOJLep7%(=&8zk~mkrZ1d+aij6@>fNJ8W7FQ9x4&;}YFMcXI@iPBQ`Ruv8fEXhc*WACPWg))`^Q-$O-c+C zVjzk3U*K)xYmf}~r&0ftn>KC2t}p4&@+?l1Vu$zdx#2B)H3pKtD8bc$|CS{Ea|Y9a z!Tz~h^%sMK$-G5LJU@!gY~Ka{aZ$3S1DbmgA6?Tnx?!QcH60jS1|2K-;KnA08nL0j zfg*|u&?@`4q==KjBxR#@f8!IH3}$JRJt0S%Sw^cs#b~p+TV*iXV&0-6o*T6cFJ~e>I-x3vpkpL zz<5>&(;Q#5rZmkJweqoX#%9BW0k5d5(b|Nn z(bj;g@p0V)=xUTssH(=O|6T1zVQh=~rY3g)4UWP9U*>T7qe6|MHH?vY{sBgv_{Yh{ z97CD)zTfi|4&2>j#{Pew_FHiM6wvdDwK#T0c#Et4h>RN=!s?+NE6gEhMWIB(^4Zwl z9KDiI@yb%g+u7U_fr1HHDIF69H1SZy$_F@@#v>zC;hTVQL2ZpCHuqE|+_Gz?d-@zV zU#=_E3%B0pvWoc}0-4w|p{!*pQo;Jm^1-{C(lDws2*ro7zd^2dZN^VTrd6#AGAGE-)M zn;dP-HH|roqHNP9SkBmsEKc^H8}v~?qy8l7Z#141D=W=lNWB|5jN( zXHgapOmEk@4SLci`mT#~<55Nnrs&KP57M;FY*Pj{Oe^R? zDl@yXv7q~zwSHvItff(JGy4iUvp8he%<4m)#4%&MrOm9RXIWI8S!=TZSv`$1dRnLb zAS~cTeXt7^TNp7;`_#$}hG;J5b{?}@@yE%==3$fT{|d+LYt_@hr$5-a6UN=Ix}3yI z9hTcP#w}g5w{voaeS^qwyXuwJ(@>+$k8JOZbDVeJ%m8=dFX1D#9U2Tv+huJP(TOh? z8}mAS8#@?}Kwa*yQY zMDlV?GJN?$Q}WM=I$MW*D7h~#ZOlD8$2x78%Wms^{XFC>z;^GM!~ zNZwA93}3$3l>FWHu4sb=TkmLu;%vZbgmM?i8-wh*{A>^{2flrYDSRmvj&|r0zLNC2 ziH1mo!?!Org};~zM^khOmpdHRbF@Vw9KL;-DSQbPj@IZBK2Cd%=17FYx7(P)pGSqG zLAr!bP~m8iL^yoA)D-?qDjaRnC43bXjz&p@!?!Otg)b!Q5YGi2eszR;>^6wzfdEbb zd^u!F{#YB&jw_{8M6XcXH@jm^@{d0Sv(AbYHBI~TdW+rQWaopPysu4_4TrH z_Nw|s59_>A!WA;VJB8Gr!QR?_mQ>F$SC8BgLQGRR#-#ee=3VGVo*MEKgQr?Qn_$JT z1!+4qP~d98)Snvsy!~vcpAoJfv2$!fMBl6&{ZR#B`z{nTmswDw@gGtUte~zGB)exG ztGu&wE64#41EXd8O}Tz-CmuvStU0I$BPXvHi1r^0Y8KLndla}KrQ@e3AA=c0{KcHX zVgSy5=cX^(`o%BVqV%IJz6xA^R1!M49Bd7PtoYGp;}t#mQR{c+sBMjA>_^Wn{pd1H z1y(;wRDi8*W?<`O_kPqWC0rr1=0|@~`qAZFJ<<-Wew643n|Gm~F8$~X^)qXJ^qZw0 zUBUI^_M=2W*uDz|Nkl!F0w)sI>SR`sLSX5j`D z?nhs?&C-|OU;5E)`6_VvQ5jxbHPnUjlhWeQ`Kl%;jN1Gy? zar;rCpt^v@I5bK(N!=;{sOV`V67$ZLRdREb>)vwSHlCOWR>AJ;q`7V#KCKj zXO;jfOMs^NLm3k zk)XxbmoO_SOm(6N47T*ZL=nPpkpMF#CJVddoGgj5dd!?G_|zPXIa&55WU{OcW;|K{ z^XhBF3#-oS){e2c;t$-ab0v3OydmgNT#&$b(6^#povlL31TFrky%3LN*`L;ogC@mY z47^UM9O$s1=%JW&>q~+>D&d~V(SE!mAd=FlY94?R95F527is`8A$kGkJJZCPo<;cy+YB| z_jt+Z%CSA#>tV2q(s4M1kId)S>u4&tJ36<|A#@R~`&bsh_H;O4!=*ddxh)<{_^Ksm#sGg2AiVddFuPLD| zpHO*sI?mpA$ey+u#jd8%qm|HQKB4lIZ+vnY>FKgY@p@C}Axh|SpHS%$$0zYshwSO{ zMzNbI^gtzag-@v5|BX-LgAOTlMWc9=DfGii=(ZlA%gc4TEfKnHqj<9^^iU;qJD<>U zo#HbN+0*SB#am6GA8&WiqB2;;Xj0-t*8%i$N)!R+EkCk%Ku$*$s<=TWpkFvjDTJJFBK2XX<+j7b+S8NlFOZ6A5>z$_D zzm#&(yqt2&Mcc&J8cHr0*j}dGn@hQ9VNSW_x^1F~DY;-{dz*5vDdnP(x#X@Wmu?fS zOvwc^+sBl9d;3kW&KBmQyNr`Gs0u@kN|~%32<1;d;D6zs=>$V6h9N>AY?&S}A=r+I z$2pbV5{1Cck_RG95dsAQ#6#@`xc9)nbUHw`LOpOAQ%UHeFrALvcF^INqhVXJ9JGZ0 z_?ApX4s=WAk%1c%cN4xLd$nsrrhv(YOm@xOkZmbaK0qlvtl&H1%2teOghv&$o7Ktf z>no&4P<_l(4&X0rnS@XW2eC8?)$LNq7sXi=`5gKd=PFo2 z>_1jh4mRwv>+62b^7$Zxa+h)3uef(~qtYky*07rSHcfn7oNQRk^l?-=-oS|iMY|%U zXJ+EchjsjaHi}bC>0fH!10!ShF}5QJm$PJhQ$H%*9Y`D75e$Spsb_zJko^n;V8E3u z;rIyVO*~w$ZPe34Z34O%sh{D%1`QVzrtddX`)jU* z$^aY>cqA*>rgbIp;Bd&pXI0rA%;{NSbL#m7$Leg-+k8fy>tLYFzhf{Z)~|Io=|Ic5 zboNQkq^HqSGqz~sx$TE>7K`;ejE+r_+-%!B$uT*NyfI89NlV1PO*SqzClXWA)w462 zlFr9l`xT5=FjifY8DFGq?EDGmmCIN2YIS>@)E&tbk zh?(gQqpLC1T%;#kr&mS@*i=p~rw-5&CY}B?cy@iC;q-di%y@ne@7w_+$CZtJceC1< z96N6fqi4_aJY5u1>}%EQV1p<5ZRfQAjg#CDy*sfqQwq!Qa)=hH`Z?gtGB1+Xm=xz?(L6ov-M zY!Fo5HS88w14EzcHp8A}Jyn zw%fO9I>wEnQ^y1n7A2mJaicPDO;`wdEbFS-u(Ye_*w%`#D^;w8zl+vQOKiR^3BS?* z{&DRX=s3f34G8zPi~Hux-|XoN7yZ{3&v@pup8cHXK5y~!w|v2ptzP)jp=Gal)%N2P zt9ICN^=o!&uUWfp{c9&XQ#-%@4ZFSR&2QcP?eBQ4D9Hf{3sayud$k;>m-FIEwVYv5 zEhkO4hn}c^Fg<0poTI|3;UM;5_aJ5=aUH>XC zJ5+Dzd4g+%s^mx=1Xsb8-JT`XUGBUjs9H{`3tBCQcd>|#x!0@ZEET5dtd>*CC)IN5 z#M5dybHl6Ulo*h(yLJi;R24s}(=|+|ekrA{&1QKzXRTV!^8>5pl*%xw<>~sXhNN!tpWD{y;jS4-+f(F%V`bCqjyWSoZ*e4T26Hcv`iSOl!oD&<0~AvyUC3G z{~N=qD?Sk!6BHS97n`a`t=w2R^ug z)>QFS%V`bC$dpy-7!`3TI}8PPg_S$7T8^=@9S6Y9k6`pZ$-NyIzL3^b!6A!S+;(JW z40#gAtZJ$_yI6n$anT3)t-OsG`BXi7_M!n7Ki|EXH zs^u6%)~n^nDYNuU9th*nzO&g=HOlBC*LG7ar)5@+k#mc2{_sXsdS>&m$@PDQyE} zs^#!L!xUeM6$bDPHWg!Er<6RtL2!IFD8=R z)pAk$yhDNl>7rC*1cZ|D zg;l9%td?U+KAT8(SIcP)+p6X8K4Y~UQ}P+KxC$DfxLbs`BUMw8VGeehy|uz?2QHgc z%Q1y-MTMgsx`bP+YulMVD~7sbf7yTO>V)Z(n8#e-;&v*60#$t(GHt z4&QEL3SUHpqd~fa%Oh;obF@g(bNF_tDSR_3++8iFHEgYxBYKY2a!lcK$vSjb%V}Aw z<#5qhEyt9+pUSH9SIcRUQWmT=(7nn|#{CNB!9cYf0|UcB`$e$a=hS`&e9!7+xPu}{{%Sdz3e4nES1&7PujR!pgd(z1`7A1A*0SoZP+4_D{%Sdze#~k)9{uPi z22ZtqW-Y7kY?W0v6i_WkQ;?aK=}}N%cCu4SxJAuccJeOlyd$hy4pk5H3L+-ljm=(Ex1qR&UKD}AZAVoqyBlDeg0jvN8hsp!daEO>Vwx;*v87v7pcRwHR1}HHD6j*dKmIo%+d5?R?P9}r%PXI8+sS|nKfVf zrP7xMRLs#7WLC`aD5y(cI#UI~3c}lUYe9FlddcHz**)`d^{c2a#htw)Lz$`veW`kd z;al_;Upm9_hx^hmMn^|qijIkzr7!hX&1sFuFvC(cN3H{?Rne0#wSH&%Qd^@L`_d!I zeW|x$YK~h4-TG47SS!B5)@YV}=?Q9I8c;Qd>ZejQ$D^MveW`8eUFc`ld?~5+ z5KuKoQ&3%CV;x#>wFjq~!!2so_NA|+z7!8KoW8VlG3ZO-D5I?Q;2c<4?ZMeBeEi|Q z^efS^(O09dMGKTK^;gbmjmU!!OXVCn0;pHflP|S?XO7&~XvV(uaOF$=m2)%|)P-oa zUUnbjTcw06WY+ej$Ctj;UpYt9k6Ag#y+n)$OKRssA1u+`$qe-~Yrga#wJ&W3RL;>9 zR2SG-ht{<(wMq$JK(ppcUrc=|p4&QoY3X9nmui)Boa?9ROJ_L#a9?_SbV77ubW(I* zS=`1^J*TBg&tSzB$a`W**TWlG$(mJ$@5HoK){NzpZdL-UtgoJ<0jTOZbpTrRoPo|w z5Q%uJ=adLW^&Adj4#IdZ%&O-YdE-NEQSOp{hW=d~q_vwn^SL+a;%9<4A&{hXb|bg?wo`X56rQH=UI9L5}sIb9&# z(u7QxwZV+1>$K?f=w9*aN>;lOKM_~C1=C8muqs62Mn+c9sm>RzpmSb$1)Y`#rB~2_ zn-q@MHsIK!H~Eg)Q$fci1f91wuqqJW4ISlrWUZb8lQRX`IrB{6zHTb$=(;f~=(xsZ zK2{cmU8)syTtb4CGlL2`k97V9{xPV6j;@R{x7;&-BzJ692HR@|oo`0piq42OQ*}f< zMRZ!0B0BH`+i>GotT&8d`Ws59r-)8#nS8BL7STbWSVYGZdXf_ADWcO_CZAK3MRZUo z7SS<<9;<|Uis-bK$@dOr5ginYMRZJ|Ur<6lMRZ!r;0jw$p*N~ouZPHUOm3YJB5P$(ABF@?TY z3H21wfuCy^nN;KKi3fkq4*xe4(J_S{poDsg=(LuX>r@ue!Jc9f9aHH4l|@rLMRZ!W zB04A*o^=$vn{pp1<$8+fw3e4^RTa@;aixKis-=0#Tp2$h|WF1MRYWnj#flRVwt01yRsawUf`dnh>k-B?mMW~sxW*{ zHfu$6=7$y0(KJ#P(UBvmPOe@==P_0+5T~0(7vedTtqg(&RBm+KI?*x_I7n4->}cFA zhwHZ2B03jE7e_ydei~)8)QzW*PRm|Mhv}7VcuqE~X8Ma%I$q2<3hA^)rFRCU@NEy@ zG4lTjg>+2mM}`;DY3XHU9AD^lX_Ozq$*ppe}aQ` zHtB6b|IV`1Ln`TL11%@h*(W)bo<>j2*rH!X%fd_Pw6uaUQ}BC+WhtHEjZmWjT=B)` zOxC`jdBb3blB{&S~|hg%V`0|RP!0mucwW5;IyJ}l&FEL!y;Og;Qv@=Oi(SI za_qdz@{-ikMeRIf_6Hk0%a=#3Zi?x&j8ZZaXv9p#q>8QbCH63HVA*9l) z>0GZV8F!10YC0NZrJ4@GHDMw4u_zhpaCAs?XmnWg>FDt2i0H`ZsOSsPm!spN zuScgw--ynPz8!rhIx9LmIwv|eIxqTebbfR}^u6f&(S^|uq8~;-ihdmZEc$tLNpxv+ zS@i4Zis;Jds_2OJ>j8LS-kBO@1$b<~crmo?5GlX|?cg$~7@g=qMTSP!IH0jTNKpSU zMi#;#M!vee3;dUb*_w6Z6EKy$ypR4X3RF5aa|(|lAqr$ay>l7JPFQ#*E`O?9U@Be3 zW|{20*?HLO^Za2)16U9B-{S_bEOL`(S)BG4JG_6-4R6`2G0cg49z$;r|OvUu)luWcES>w(s zvpf`rr;t)+vyp9X$~;)f#AiWHndNyHW;cm`4mYwbOqm~5GVyxcDYHDY!g|s|=13!Z zwkh+SLgr4O8MjQ8#|cfPO#CWaY|7kA$@J-SSn6}9Nu^KtKO5N+Q|4QgOrJhge%?+j zbCZo7{?A6XwJCFhlIhduu+-;HtoXf<3Hp4QDRX@7vtWIuu-L#s^q@Vl(h7i|wP z>K}L$E)fsh9_ic-|6xwqJdR)fhLwBnx9?(M_cd7R1F`3VOk@q!1XW(Z-wvIDuNC@) zk{K*MLDg9!J|Vg#n%{l`hP$Z1S}hZ#25F^sA?j7GH{MtTPT2w+==j*qtlrB+8*0)R z`sIfkvdVG>6<>;!y(9_x6i4reU_r5}U&zK!ww*;(l-s>N`~eSeiv!>m=T0BgegX7s z(VVe$YhYL#**We|IpHI^XQWzCUw|U8R#ZSQpQ^J?5`X}zAfZPQB?>}-3ISjy08(+M@}0VZuIqPBi2tX z8nCqM*+%y1+D4=nd^Td~Wp6fO6%?+P*|CwEO&dYBb=rv3Q)wgeVYBH3tOMlxNW(^~ zEyGpOy^Z`Ox;;9)8yk`P0jG_OH0JhdBi2tX8nCqM*+w>WZ6i_(J{z(0vNs#C3JO=t z?AXZ9OdG-7qtiyDo=O{$4^~YZu@2B`Bi5GTs_5QE?u_n=-r0qXsQAliBdx}QUTwts zsYL^pc0Jq3>$1-$Qup=x{x}x7mTL~H@HYhtl!#{U}@O1xm?<{xkyEL&BfBq9?iunsSC}_j=8id z=7ML8PIHmEBIY9V*eg!ZI!L>@SetgCkM7Oo{^%dkN4hZ=x$ktF%W&h_J)4X5TbmLr z4SP11GrKkysR*yRSi0GxxmYE2p_$n+muFVY1p|7gxkz0Rb5Rk!Ng38b+Req`OS(1} z=eJY|j)py(%c)(Pi&R9dxj4GnrMWmIb)lKrF_)(+b1D1fF&C*TFcgbFqGFQ-Y;o&*t*^uFXX%!fP&;ZuV#{ zR!LoGW_HY_Q85=^?4sT>5Ob--F3zQ6H1~ZXl8cIWwkPwvS04lWkl)<%td`;#xCkV*p`lN zF3zT1=%agc`DFa5_{lD=@>S7(-CWqc?9`gcR^`2w!zjC@+qpo->zp{Ik(%Z ze5Hkot@wKxXeuFs!qqZ6hO(Gn< z<|1`fF7*-h#Mm$w`yj36VsF}oKDsxTFT`Jr|Jg-oqH59V<|6l*qcVJN2U|Fvd zyPj?3HQk0LN(&WR@%J*&R6+!Wt7Uc!Bg`0_4nL=~oW+DNmpzE>NuernNxrCrZ9vZh-bQCjfXh^3dk*@#t8xLRh% zMlLjM#23CRJ(V_63E#!aw+_&1Bi5GTs_5QEz7iiBU)sJuIDA(nk#!rHi{bmaDG1@A zG{ID`efU1Zk-OXUY!_c@|5tZWyBc}LF5Eo~v^*i%aOCCmXQ9Hw3ooa zaP#~twehOjg>|rXMr3W=m1ep(qOZp%$7{PVBK5Nbb|Zox z>QPMe=B|y%^EFk4vuV#pG~BHbDRtBuk+Y*+8j(jPkPeV?;+-jL64C>Ni(3BdRcwXDQVg(abf|y%BvQ{$@PV#aV#*6&Ia} zSV+egQnT@nVC(UHhRed;re}NEs&gwGfb_{eyW?FoYSCPJO?Tg9B{*NJo<>=z00*Oi zN_nILTy#eKU^g=>cUiSFJKWf-mzlMGW{la=rstU*pfii91L6lotJQDeBt!km51(0; zH9+Rf(l^V@T3hur%7B^uc6@bv518(S#rpBplS5d-^+gzkE;ip(Y^N%U@`g}Tl)aE( zcVX};)?97$SBi=%u~1g@a*Biwk|XI=ikm|Q68OXbq$uJ@AQq5*L6LCcIMVPN7fXg8Gw|g90|k%(s>kVnL=9TMp_nxlw}+V!~)W{DbjLNsVF!Shy|pRDAKkHXf;2hvJ@M_s$?3nGO)PalQZ~o*f^*F@BO; zEfd;gEmf5|pdr$-w;9`iG&W%!5m|uPU}pB8^gY*tv*NSkbK-O3^WyKu=f@Ys-;2K= zUl{)&{$c#1_{Z@@@dW>MwtW5SwLsfZT>hW{Ed;)uDp<|hfkCn=+DwnD@fS|Bv`X4S zCYob|py2O4auhVidK6@AFADq|IQEEJ;=c$A{`w}9-dzL*ers%Ey(oQs425&@ZwU(inkz>^O0GviM)sog_cIjE$G_q~SB`%H+Kl8z8tJ$e zhOx01X3iWT6pjCU0)xgc_UlgTXH4vc85m$N-1^TVFlhY(#%cbHg}pFy=Q0>>{@)}p zX#N7mY5$CYy)c7=42IkP$pi-NU%)sW0ApV-%)EIFhC6`c2n;#^0ps)ljCs8<^XD@d z?g5VJ9005}r{s&s_$i3G1&6eY1QW2f7yKmtY5cSJ=kX=+FXBt%U&fckzlwhyUmjl( z|0cdN{%!o6_U_OL2vOJVJmm~g<-Ia*s6nq|WY6BLkgz+f?@kM_w1;ULd2deHnH6We!YJd_5PZ5YO z`!gvJZaXBLt9gwZJi@r8dH1;R}y2deHlH6We)YJe~}MIgTPPozMu;8X+B z>8}O|V^aj;{C6w`a>b?^kj{WLKp2`L5U0Q|QXp4ossZUFSObKSDFSg8JcNN)FF z&|(b|#-xbE-NPFx61oS0O z1*1_w;YRmGf`T^3QK}|KQ4B`5qhK@&DBR$VA}Gkm9Hn|#Oi>IvwxeJ)3Mib74<#r_ z#vG-3P)tz_F1Dj!Gzuu3iVq?v$iy6_dPq!B3?jCpU^EISoQFR~P>_Z>O7(!4q8Kb} zN5No=m&b#@qxMgfLf z{~HMmTEBpCn!icDb{LFC0fw9ZE(8Y6U%)u+-(+4p3`U~>!|ngI1P1M2z&IU%NxOC! zj79;5JAj=C3_1V-5jAPz=hoqcF0In zBPjP<1jRwQ8j3-=c9aAuw<9R`6oTTQTn)vbTssP*+>W5!;|Yp`ay1l#a_uOLayx=@ zzf4dZl&hf_lxs&}l-m)M`+0)mpj-{bpjt~eP5tRGC1ja?V z8cdM+Gs^7<%6$ugaZ#=Y6J-C4ayx=@-#}nol&ir6IRHkv9YMJ}6BrleYA`__fKhHo zQ0_WPxwvH9lv|=P%7qUsl#60a*0E7;O*?~ft*v^a+<(Ro#Sh1i#E-_0#s7*QkDrMD z9X}awiVsK*Og^3*lne-+Pp)=Tu6z*7+5zR3SH$oaCL96q_0P6~&03*!~|Keg@3WHYXhXL9ZLIFma9sb2dyA%ek&JP2; zD}(}!G&}r@i+3puTAd#Th*t;&m~~{Oxrmp-Ao2QPfO!#y2fM2YjEi|G3^K1D2B;Td zc(gl4U|iHoVUT+LFu=VC!^7QI5f~TuQW)f3KMasB!ti)^Mf+`R;|+gtlP|$xv5qI8FklIAN{;7#MLtD&Pzd947-)oG@Pi6pT0^6>u{0_6h#VIM`ABY&-Sye(ctk zeIZHMT!AJJDHaZBsK0&U9jnOejfX#(d@4COIV3qWIV|~fa(Hq?a%6H;@|onb$>);K zCtpZjCpOuuM%&KNS6;=ic3|k`**N?KXm|??4GWo|_pJzui-swRzWJ>|0TxCSZhg-q zC@vPJDEi*F1_ekMQMm0rgP^!bn4;)g-x?I)U_{}T_jH2d;$VuR?|f@efPxW)+ua~R zaZxZu(Ko&|D8Rso!mX|#C@u!3D0=8yg8~GMD4c*Jg5n}zilT?UH7LNph{E~zaf0IF zUy7oKzBMR7zlg%=_aTDfqF;)lhrTr^z`lsW+4nv{^4PXaSE!ygHwlap`qsbz`3j+6 z{5KL9C;3vCAnOP2MHp`VR}&Z~_fnW3^9Slh7;gSo5*R1-QkWq72j)c>ZvU4N7$@^m zm>>rL#EUT80sM@>IEk0S1bG19U4-Et;726%#lQMOUx~(O7eA1!YtW9#I*N4t?ex%> zb*dt*H_AOa`BHLB^5x_!$+5{-ldmPmCC4WxBqt^(C0|cYPEJX7m-p(PG@+(Cb7u{; z-8DYL9&TjMuCgwB>Wx$mmUk>gBBp0P!qSoSeQzC-o+k7~id0%(<*G+V(s#afNP3#k zQ52~(z{+ipj->B>>yQ#HO-Q|nf#xg@=2tP53m+Xx-~HAh>1jd-(J_@~Sh@4jk@Wp< z9g?0V^f8KrT+GK*x%t(R^l-QiNlz2{AVoqx=17&>UmZ!0i0hE_G@r{xO=u?yg>rh$CiH3wgW9d<|ykEBCj{zJ}o&t`9|{1r-jP!iW^9Kah0_3nYiHW+X;#zO-Mu0H_J6BcuTC(gl-`yjx-?+Mc*se zpx`Yrpzyu&^#sL{CZwV0Tjd%Qyd?${zE%D`L2;xBX(;+mxdsJqi2;T0l&>Htjx-?+ zMc*jbpx`Yrpzw|Ir3A&1CZwV0p>hoh-Vy@}50!sHP#kGO8j2n&*P!4nF`)2J`3D5W zktU>}=%I2A3f>X}3J;aPOHdqXLK=!5D%YUkEis_*Q29F|PJ+KcsH}2CDrrI##t4;b zVDOfh3FRC1xAKQ5@E2E_kOmWE{dh~vgd)rr$!J_@LK;kv`Qt4yz;N?Fiom$igfy5S z`^Q^ifZ_IkD1mXM3287v4ghb70fsw(g9wZ(O-O?Y@&I^C3^3dSe5`W-ECH1!gwykK zy_jJQ+aT@Y8Vg{Y1>Z})pIn&yAo*ePqvXfQMajj03}+Q(B~)+ZaaA}QrUItK>E6`0n*ci4yQnl=u`*NSAGqU zo+k7u3gie*bs(MoYJl`KA#Hg(VpAPRXTTaDJx%DtbVQEOR0q;Yum(s^6WWggIU-XX zNaw*CAU#cJZy5q(_J%7k)sPG-tU=P#gkDdPTyd$66yzK9G@&VqPSKEK~ED}Ns(MJsg4xnAM`Y#SCUg?wuIads7gHcfQnJ$ z{;_`U%fy(}q2kf<6uGWlh_v3K(aVxwCBIHCPp(LQlU$knHn}SKUGn?n56RWZHOaNf zb;)^h-wVkDXoqDqs^v?rKbvP=^yU#+r~9)VIh5YkW#%d?|kGzuEyyV3I1DnB&l z^HODHb;SW+8dhgV!DtlQvXlJ-$?T)eag@q2kTw>>;_N6GjRFeai++TlARlv-%3-mF zV$iW2g}qspX+rNOC`iT}rE*ZLp%`3jM`3T4Wtz}?2nsSWN2weVYbXX0+fmq?Wtk?l zCqY3P<|vf|VhzP$VLJ+YvnRHl60r&V-43wvUFrS(a%+^5q=Dl>73g)Bf3cuos5C zS(a%+^5q=Dl)Lh#(*dxvU@r`NvnP-@?F`Dbw(5;?Z%A%TZc1)W{+Qg7+?xC;xh?r~@|WcHYfDCiL`KhT?a$emsu%SrU`wDprF-p7g9Akieea@9feV@OcOeQ zpx~@>l&Z~96oYc@D2#Gtn$U*{3fde;shS)`F(}uLlF&4v{Rj%097m~I97QoG*N(y{ zSEdQ=O;B8vOHmBUwWBb~m1#onASf=%r6>mF+EEzg%E!uYB`7Y+r6>mF+EEzg%D2k9 z5fm5YQWS%7?I?_L0El!pk6lX59cko_~tm9LavLSUSfOJRZ> z0Ha*_NO=i?aZ)aY3Gx7pa^)N4=TgeWx%5!3LSvK*A6O_C#h9#PquiQy2IX2?^+vgW zOYTYTP5z$Tm)xKHBY7ZsF!^WlQ1Wo{Nb+d%Sn{uAOQCak6YYv}N92#0vv%4`DSS;0 zoI7OUTp<*8x|0OP!MPd?a&CEHT?YfCi!dM*VA=%6LAn|YTAd#TSQlYHD8Q^DFb>w$ zV9@IPFhIKq14032djjL2T@41U&JP2;i!dM*U|vCB9K5T+pw;Puygn0rWV8r2`;9-K}B478z5pl~ zakwwIo4kF3zcLPXr3ooKl_sP}*j#}o4=EN7XoxiIZPptPKau=9c{16Q9FQKEemp%W z{Y3i7^i%1<=^^Q%>0#-oQyG-PJ835m%llx~4h+5Amcn0vhFcaI7Ba#9=7_C4{>4SZ z6h#kxYfylNg-k$635tt_DGC~&cPv1{h{A2}NrK`cVTz(}eQU-79E>R3@*X89E)J$B z`p&lo1t=I%xZOQKP+SyDQS^;(4GJ(YqHwFbhoHC^n4;*RZw(3%Frsh*zJs8+2$-Vi zp>GWe@Gqip{=Jo;xcHZ%=%H^73eYd2aQeN0pt$IlqUfP-4GOR?qHy;8gV;;JU)YT= ze`ioVZ5|;oM(A4u1LP}&f>~ZnV4UPjVS=n5xEEnK_g+X~oZL%cg3KSN7h$;hpGRPv z)JtK4>>rpHVYvN&o4`1km%;=&03cq3;SS(*0^=lJ3KQf3fOipwdw`Qj=nH?v=`r3u zX?L4y!O1is#kz*8Hd#lJuD_ig`m#<{r1eI*N2EulN2Q-hKbw9o{e1d`^o!}y>6g-D z(l4i9NsmpxnjRtV)!~sd<6Lfcl{Z);>dc)r)OOeSK6<2)ZChnsnkIBGMIxqWrU~gt z`o6agNlz0xkRp}VS2=dpkdo+k7Wic}h4<>*;Q()Ye~Ncav5{+pm+Rn8Xw zRN7$W_*qBNcfWN=dYX_bXNyRs8CLFmbR>QMTZg2l38`|nh=g3s*Iwo3S4Yyr;W{Ke zO-PlqMI_{7j#Rn*)sggwxDH8A6H?`D5eYe&BUNsIbtF9~u0zt(gm$584|$m*Rc?WG zBt0&!L(wxj72_(+esLqaUGPNCiE(rdV)?uKvgcLv{A9MX}|62X+kR~6nY5( z<#rS7O4tvjrwKJF6uJok<@OWoTG$VzrwP53LZP1!P;N)Tu7>?kdYaHy6bc=MfO2~Z zc0KHe($j>VM?z)3klblP5n;&`=MRdB-a9dgJZm(&N(;(i78@ z(yyl{r>CT+rl+N+r{74wnSLuhBRw-cL~P38NjK1TZJN-CI=9DmT6hVsxPi1^StV_J zCXQPH*e$E)U+@=4nvjN~ZgD0oW@C_GgD3_)?E327*Ls9b}Bx5R+LL*>H=iX%-(L(xO!8Wg-G1{5AD ze}bSm(u6b=Jyfni!CPWL;i2;WB2I$8K&V`wCPZP3P`L&MZ;6>uG|P7q7+0E*1`}lc zcuNd0JXGGDz_`+cG?*as$6I26;pYD)0^>>((qMw@A8&~PhTH$H1jdynq`?F^0K6pz z814Y%RU-byl_sRY1bG0wC1yf#3A8&}nh@&E2$i)op%M*g7uQ$-<1F}2dRBUNdQN(7 zdS3e7^!)UK^n2;|(+krdq(4l5l>Ruqf@U3*7c-UJXG>ns+S7!9?6$9x9ZeHDlma;- zR2@iP@$iJ(2BfD69Ylc~0jdt9ulX7vJx%Ci6vz>u>OlIe)c_@0n$QO+kRv?Rf%J7> z1Ei-3y_W(xqEj76U->madYaI?D3BvK)q!;Ss{zu}g!Z67j@VQO(iyM@NKX^mNP!%o zsSc!*U=5I-CiFTAjtqf)X+j#3L4`F)dYaIyDUvHL)scdHgPta| z9Yu15r8-iObI{X-MktaiD%FvKyn~)5v<*da1*JMtkbBV6gkD6ETrsJR6yzWDG@<8{ zQ)IS;+^5JT9(zE=sL_%pG}16RO2wn)DKdkzw9`+K?X7x?MlVi(lKwRPS^D$zlJpnp zrRguz%hF$^zfLbtuSkEBUYXu3_q~wRfeg*x##R|x9^7N{haQc>FMR-Sj#mkqqzUa$ zP|yZBO66#%MNte3w4<;$%Q8*qLj(owkE2vhg)|hy`s^s|&9Y1rdLKbS+v6ye10fB? zusl0TLeqryA}DBg9Hnv=q@fsAXGg(kRHX^MouHu2ag@q2kcMJdoE?R|S(a%+Zzd?n z#~h_{SgfHKbZkdqZZl*$3IhGMX=9fiGFmT5ve%7_P2QOezU_2QPom=tV>VQ-dYnvi@s zhZ!$qZ|<~yb}mf(rX7a8S(a%+^5q=Dlsofknvgb{AoFK$mSvidd^v|O<-WX{CZxdx z**|-;EYpPK%Q=K8cjeVIAq^(T0kAjAGEL~&WC@ge@@krp1{34~*qddUCbWoBF3zQg zaup9S%7qW)8L+V=OxCecF2Y&b8I)^n)f?qrmHsaMefo#=>hzlQ+Vr~g`t*kM#`LE2 z=Jb#0E$OZ42bBwPzFBUmds|zY5K!)pR?3xWLM2T(f7w7oF(|i##9l#Rlq+8>mo(-4 zVFL}tusJ&lqg?r5xuhxQ?;2<*hRNAc5}GDd(v4QkmxOI4PIFn3QXWVU#N$Dwib1o)n7< z=4O?0DNK;{Gs>0kluMFgFN!5hb;nI%g3O;$u6(9kk`#MTEMcl!ZVD4*|BQ0wE9FIs z3)y>O2~*v3QOK-YECB^v~&E(%aKJ(mT_;(!Zv6r+-WDN$*Ynp5B+-YR_BKS z)BTK*5N^eZlw1+b8%d<6u{sP)p*eG$BR8<_a`ge+*~haj#U>lxNxOJ>nY<5X z?ZD8>upj;cG`!wI!$Kz5#eD?DLBkq~zWJ>|0TxCSZhe0xC=M3ZQ1rcT4GNGjqHx>$ zGeL2Xu!e%B=hYZ+FrskFleYl)7Y7GxDEiK~W-LI#LMHQz{AZN$FAfUUQ1p#&4GJ)@ zkjcDaiQ-^j4Mh)qYfylI5rq@*ugSbP2v|eWL*E({;9o@H{Cf#OaqzE(qKCdUC_ul6 z!s+)Sg5scG4Mh)qYfylF5rwnw_XWwrU!14S6vhaBYhZwUg;1FOQwWTUd^MOL>j&;d z7;gQ?6BrlwYA`|O57dh=-2A^xU|iIz!35bqFfYPz`~N(FaWSt36XXDZcoBvZ?-2yX zMZ6kJkOu(XMHtSz2b0hj{)&1t-act*LJCc$2`Sb!oT$kCr?bPeBeEm2qq5IrpUpm(eLg#1-mAkSXU4gF_g1;#U8c_5Swn4i zjqjsdjclsQx-?B_FN#D=&rB22k@S6U9g?0V^md9=T3_YdNk`ImzI8}?n$VjmQfYvd zqbD5+4Y1sZ)gj?KEckDNf>k+N{8MRzmD493N#Fg}A?ayCs+=t%m1bDE_0^H|{cjzT zo+hNq*&-5hF<*O?n_nGC4~OfJ^fVz=&K8l7k2zB1_E$&JBjP$FJxxfJvqdE2WR6t1 z0oIZ9ptuf6PZN42U3sLU6VJ58uu9e7;LzL4kD<}xu^OR;u9 zLp@aH9jnOejkmv;9i4qCJ0|;b_Lc0|?5o+=vg5MjvlFrtvy-x~XD4T8i%mH^=?2=a zO%qzC&h4?C7Wly{ZkXd;tE7$3#BnPCyX6xIiX%-(L(wX}3g0V#fuK0jgftX=t6YPEx5R+Lx5`Hn6i1qnhNAD3Yf$i(7*P05nI?%j z(u6b=eWP51g15wg!Z*qvCu4D>327*Ls9b}Bx5R+LL*vUe{rP=X)r<7kGI53DEb&x8WaBFN)ysxg3KRpiJ4G@c?}tjD@{m)39^5@ zB?cI7|KkM4l_sRY1UUe_B?cJo0RD%-xYC3)m>>^;x5NO$J;1gdElmgqWQ59Enox;` zw2NyjfN>U_nw^%No_!!+ zulgFGL`xG|MS)!5sRpDkj~XC7O=x=x8}PzPZMfU zAXjXv0qG1_1Ei-3Eu}!N&{PA`Nw5Y;PZQdj0=Xhn4M^v~8X!GQXiFIa`_hD#Q6z&3 zYmoFbp?MU^8JB8ELB2sx6Y8T#&ahNN3UUs5novxUoKdNU6yzQBG@&Obk~1jPkb>NU zo+k7#MRLZZ8d8vd(9?wOC#T4433*PD6&`y)#i-GeCe&(}9HrvX@)ViDS=#BR$o5vf zMWYvF-^;$AU6}nK`(gH@?8n(f*~QsUvY%!@%YL3+lKmpPU+#O|X+q28#VtHrH=U!X{MnmjnI<$y zV9I@Y_05z96J-DF&9Y1rDhN!uE3c*rX)r+!fW29kX+jZ!Dfi^nG$9Qp$OEu9%Q8*q zaZ0&3mu|`}(HP~z2l5QqSP~}d*eDm_EbR=+wYKVwa(|g!mi;RGb#{4nMfRKQ%Ivq< zRoU;d-)DcwuFkH>uFcfZET;b`mlF&4vlBS$#LK=!;ads3&x$?Pk zNmI@=Aq~YaI6DfXT=`nLq$y{bkcMJVt{sI@u6(Rq(v&kzNJB9w*N(y{SH4x=Mv)`k#a5VKG&fiWr94#Ox{ zK2$DA%AF=eXU3#lI}D>-`A)ecDR-KX1`}ldjB@2O<&vb_X+j!Iko_~tm9LZ^S6t{$ z6VhOU8~~$S`AGR80^_7yx&(qe0Ha*_M)^KUxj2^|%2jBLa^V9D<)Rpq4{VfM)6Sq= zYpdQU_xkLH?8fY-?B?u`*)7?v*`Ko8vOi~k$!^c?$nMPU%041=4sW8Jlq>ICSv&2m z55A@bHhhPLbA?d2sgP!ee{qGm6b3oBys)l=0n!yh0Y;h~{>2sNQW&&4KMb(05DGBT z?C>wHK$pUx)%jt7c7;%Yk!FW~aYecm2CdEy1H3DQ0*o{}{EI8pr7&o9ei$HLArxTl zBP-1n>rxmbUOx;lFT(Jv*S``NSFlTAka_(uK)ndV?_U2*U|i8Ig+c1|!vOap48MH6 znZUTXm%r82S2ffPDc+T)+N|q@g$iUWyau2Y`MN2c*Jy zenfDb5ii9Fa|FP@hyzjq=K_M`40$O|m?r=NMjU?TbvD6q#=I0K%oP9wBMwM~@qCNm zI2oAYg!uxXV8j8bfO86Y`viYw9PCOHS}yTanvf!4a|N0_q*yqhq5k%XcdR0>Hy*w_ z`&)KTc5n9g?7r;&>>t?!*@M|Xvxl;Wvq!Q=v&XWl#U>lxNjrI19=Wr2VCZGo4}Sp~ z-pfM6LMG__#{|Vi!xTjieQQvFg%O2Y-}eZLi-jqQzW1#`0TMYyRws{F@GmX~rYL&o zTY~}wEM&qOlP}-!FD?S6D0=8yg97|3WCDtO`G$XS@h?TuL*E({pkE;qP~^)u{ELfz zDT*HY)}R3U3Yma%h#-0Ri~F>hz!;%#4GfU45DGB+5f~@=QkWp?2ku1}ZvA@`7$^5q zm>}~9>O~lC{_h|#PU@vFLG};Ki!j{&-%4Pd%u8W{8~_k6!f*$$8-Z~WFNF#60KmHl z!#%(T68gelaX`k~CoN5AxkQs`LW*?__hzz=B3*wwJ@jRrsz~dNav#s0$o`!@nQh7r z$Pdgvo*$HdBL8Imsr=ylko?g6uw0h%S-WatZApfe)8-ZOf|s?^T>IKpW0Q?+9}DFQ znP7GQ-F|x1Xe`RdS8wPb%1hp`a?kztT|B&WY2}(nA+fe_%24RaVQ?lIs5(jjf&E*W z#YvPU;(sm4(rhrv_g@euCZrY4#ABN_Z9)VTpT%iX?C}0QH@s!9#z0a;iNa3$`UlfF zgZ%?#@3zV24sMm@^A=_C{Au~qcBrXxlTf)XR61epLbMMKT*w6NFK%zHw2vq+<=Sr! zEnQlhBi{|BtAD6X?Gy^~>IA>OWC998?u?pOvd;r4-gMME?sGF#U7) zc~g6#(m%qyOz3}GSpJm@XoZCn0IoWG0yg`PP5{h6R}&z6r%ix-iHv$JiDkI*jzKAf zH4K@6Ew*42z=`EoWC9RIOu+E+rAvn^uNf2;P5}D)U8daSDnkiF9;U{&W) z5Hg2R8}qDgE>yZvAAo-15TBVv`_Bz)7t#tn@T2gLD4<_?;Qk`&hX;}c`;Yy7{orlq zfVUm!J3K!kKQccm|4jbb{B!x|^JlL82((E@*L5Hs-|p7v&(R&xU!!}X`=SS;hoVQL z$D=2s1LIG`2girSN5r3rKOY|*e>whYe0+RTd`f(J{H^%R_&f2%@m29{@q_Uvk}oEw zCKn{XOs-GvP99GVPrsIaJH06VZThG5f%Ks43)v~z`Prq}b=hCDe`TM}zmVV3o&@|w z+2qQdSHS~pL5d^IrAv{2%LmvihFU|Cf3YpB|NgPjwHw)Ypsr$j9IE^`eY+4lg<=)g zO0nhM2E?iqXlyIRvhT9>rq~1cu}HCU=gzuSDA@K|8)S~kuJVQ;br3r{wrYosovG2O zMsk87IcqeOP++U4@$9p{snM~i)f*;2F(UoU)QJKTEd!9ENQuQ0m|+1mX+YtdFirgm zO0*1sisL>h7NM54-v|@5Fq`UhV70|tAq6bfUxiWKVY2{`BoP7u;bRhEJwebtsfGZ} z0ua(Pn_>b1;UIy~Ub$wq8iVdXDFQYNK*+L;3j~A*N`wi8pwqE|FcE-|=ZF9T0paoX zn{giU$%)PctVQcHFbcui1z_O0I2Q>Zmvx>5kp6PX$J=nqU%^dVvq81CWOLzC6Wwe~ zs~Jclwx{(s0}tVClnnN#QGYHswf$MHZ)*FZgs}|_Ye~{SXD}TY?4P?;e=#_i%v+Si z^ZSm;znp(1KQ{kr{>UvXl7QvUV)o)j=XBm@)^zd#a+vUSc*~&!g z6a!9t68QjRe?+LIGdi{tSPoZ9)rU*r*v!}SqR6;35PwbQZ=jZ3bVNo=R;!T^tgU7> z{A+W1b*rguqpYT`1-F_Pxvb_o7z6&ZT221#{5$zs`Pun7`MD4sz7E=9!~oG&B-B|6 z3`ga|ENlkqWHd85wHh4c$%eT=oW+IVWGxhAK7lR8BCBqpq;P2EksU=T69uA|s*W?+ zd>vGGPg3?&$16OJq2nkFq;Hba*AwYg>sHdCnWyU*L@{9?Jrf&|$xHR@vNOk zKE5;J;sD@{qWhCvK37ha!<2kz<`EC^6Bh>3Um&HgBg(0gmy!<6JklX{nqpI?xFFaLgiVg7^shxt{)`bJmdK}ub8v`p|Jv?8+vUz}34?39TD zO|DReU5c(6wiG?#70nDAM1kn7rRjB8x9bdB$_A75^_v?um;RWPzMe?08n%)S%{*G+ zhRvmKB8H8MsWWUT9xc`D?UpzN#F8w)D`Z^-LYS>CTH1jBj z8#b4|NvxSkCcMtDm2j_YX4qWxeVv=YD$uY|E3UvxiHD}9VXtbKOCAk-9<^I*6JG;v z*o}I_9!&cO`{%$x$G~7R7Y;fG`+l5XlwX|xB>!ptv;61zCHb}OH^2ZFW-Gyz)VxwTeV>-+r@0NQy+0FRNlK=j)mZVQNA zMkm)Q2xRUW2yEwtfb*3JCJ-U^>--Z&QOFf7PaLefb2SpS{H3YW6>A!VVsTF+G`Z=X{>%Kb{8#y}^UL!q^54M8GHzTJr4zg0xfQ#q*mv=W?U;9k z@Bq*f#++hbS&-gdy=L`P<21tuz>uS4KI;f}1x{J;0fXlYZwo&B`(48?F)hcu(`U5% z@G3hSUB$**`tz#A$?;-S7;x_G91J)W16~RPro&IO{h#Ll-rIr?e|~qvFMG93|KL2J zg875V0-%D;rvJNhHS{;<6X-t2k;-6g<&t+#Kc_c$o4^rwLvZnL^Q-cIwr|8$-PhUJ znb=_?zSt30=2nB2?~+Ap7+wY)%leSxIxD9dr<-dVUh8D+^#Fh@f!8{NNy=}BU7xr` zve!{^Vyka*2GhR5Ox*-ef3%(BG8W^*H!W?S*O*w|2vw1umGDb&;c0S7R>i3!$UdTfFtA^fjP$V-p(_xT_4tMhB}XSUx7 z|7lS=+8%>_k6>po@yapUO8IC3TEegxJM*0c{9$x`<1EvKAw55j^-9n)UV=Qc{b7X5 zc3L+v33w$tR*r8K9ySF)#*SVB zd1JNN+|olr$9U$0fObx zE^8|Vix1B=1;4iaF!s0@9a}XzJ_%hGFCT6Dvz78-i8q#uU@npv{E1yaoM!;kY|?z+ zfEg#AHZ$I+eT>)3>VtdIHKQFokLRywDv^sCw`d7E)%up0gNERxlnPt__jc|DCHF}k zIkyT5Otcmr#HS7M(n0H&*)5ohV7>lUZWL_q99|Bi!GG5Me|&TP$NX2~qGNP|ZH;(H zUJ3bE$~Xs`$(0J@o><#R&Nmhk9?f%UpwKN#@whXoiTJ5_OdMbqRwo|zTOb~!f%s>a z;_)$R%_$xgKjIUQ@&3d{kOtxxmEv1Ud?nte;#)rP817GO1Zg0CK`9#K(r6yd2Ya*QamOHaq(4~AybRFK~C{tFCd=h<))>0%nIV-E4wV(`xQR%aE=G! zc|PuwrFcvS;^HeO^i=$|KJjn^2jY1i?xUSQfnDTckvaXpQV_0pY2`#srU77t&yMrl zZP3DO4#cjN2Tr@a32G0!EO^yopIm~y1!|-Uk zYU*-ZOurEf!Z&oFv&Q!fqsOF$3_KCrMqn63_DVJF)dtY|-&qXQXxs|jmm5H1uOz|9 zUTOM7akM6=UV{_f% z-u2ap4FAfbCARyl{{&6X-Gtj-?`Lb%m$Y|<9>JTzl{lCD8lvhP%kjcA@`G;C>%<&s z2CoyCFjyx;N;odVnmdk_rEpw>bi7sJaLX~Z5`>{}cFR%7e#m{M?X-kI;Ot1>NTJMO zDCg*D6goxSxX0w){O|dF`Dub#rlxTFBABIW#H-|5gl3>W=BlTr;9+YcxyV?B>@@*m72sk{4ziF3N4%6u&v+TwdKrDP6EzGq=VQc<8{SfxCoB4VV`zS6A z#P3szFYkP+`zRvbs~p%zfq3pM_UYUL3lW|+GQ*J0-RdkP1ZyjO1yNIV8Pa{!Oc!%E zj-vQS{y_d<{?GiO{NenO{9wL|DkdjZZCnixy5#|~b^kObPhWUzL1Gz;_wY|^Iy*Ej zHvC7;?#cHJa<;ooZ@Z{VWhx09FRmJP`m=bXa#d>#7FUkeq0Ag<_PpoyamDcE^XJZO zuzc8`P%-N4+In86p+R%8hCDiuyC1D%X1~M^$lXS0^Udga?dNx!HXYCYBiRMTkLCZ$ zH?<#uzr!AA%DV>|lV>-qEesLw9}3p7smUEM^{DZ4bNLkT%MEH1RPZ|pykhfy7SJXc z%+e@RJ0Yk)QOTxI&?1{6o4Zv8*%ZaRMFr#qpC~eRr>0)V-tm)+-OB9*89X$G!Q+{{ zcNFA)0tO%PY&o2xf~QO4b(>d6KpU=#O^?c}3X3WVoPPKx4_vajW#_iZ;L0t7E4N|+ zC}y+iJKLM#Mj@S=z`F|hm>BlOMj>C=CX{-akT(_H0Y%AN-j~KwrWJJ=`qXFzZX(&h zZ3{#}s|8Ya&eX~c{0L62b>$J7wt%733pWkn5xlzDe}2GpV@%|eB&?%P8+@VCH;X`IGrq*sF|1eN$5#rzTeuCukqCJdO~}rOTCH z7r!vP!}Jf?lZi$B&|((>Ag+V#05Uk1?E!(MZ^{4ND1K=|oVj)dj4*}sWe6eu>*)MT z`3d>y`I-57`H%8ncBtJrA>AHzE&mOmXH+&xJ)`?0oOx#pKJVZO z>KDC&Rg0c_#S_|tX#Dxa_zrZ`kj1U;?-GiW5-LEj?SG#p;{B99}Iyl~? z0|l#eP4Xre(5V6MU7(qZr%JVbb}*kWN2T zI&0^X4|OSoJV3Z!yi0-~d0`0rY{>BB6oNJMK|p~VArK%A5K;f?wHv@pco1b2W2XSn z%qMeoAd>YZgMhr`;j zvx^g1UPZ=yf$}6(FQ<*8Oh$5>e8fp(R*Ytgd79(U3FA&YFN1$o!st7w_(bu^;#0-J z#UaI^#bL!4+7CfP$hzOaoQSxjty~G>c-1W?G?kunE@-Z~aRWGBNdAd!zEd$b^_{-Y z&~td&aQ~?uZ-s3dsQ=u&{WSES8CW18jV8Qrs9LogI<}SW)6+k2pz?)@bNA%dU$7!J zfhO3Lhbf}$oascj;l+uvu@+N{+-t)#0gEeAdV$8_deL{4isdM=_>>#27s%SH)r*2A zgAivF%)8{s|eoi8l+x$YtRh74DqdK;T~pf==UF>4PAE;^QTcOHW!f`UK~*z zSv<+FDzbHJ*5NBzP8PVIDql{ZQ;@MHHUnSII}eP5Ulpn05b%_f$-`6PXST5m%>FPd zS4JAjd{y@#78NNs<QJ-F8<_2p%>l|B7%b*Ov^hBa zDmANotg>`hC9tN0<(;g|YE8#wTrF09O{-pqr_XAsSu?JVzF4%@ZVpP%aDM|E!|c<= zQN`zqFBC@?ec{n&Q=a5jqRn9*Z7#4)xMC%`W5P{i{YR(|XNws}n|p;vn`+dRXtRC* zWl+aAODgQ6n*!$u*;$LT1=qo>MVl`Pi8hrk%4kz4p)lv3Mw=IfMVm@G*qDlDYvpUv z=B0trrh)+0^FwIS=H5ZkrUEFV&Ds%=X!Ers6m&(KN<4;m{9Z~KQgsTnX!A@0;fgjj z2pMhGjzNnyj|z@9OAsU46hP)`g6%;WZPvF5bR4}#o5vJiF1}J6TYRHpVmdRsXC!W zo2mzu!N#W)rxt$?jW(My{qjjB0aMz2Mcoptt+!??-V&hcq)dc&uXdJ%B+5~_?wD0F)blGp*XoX zt@uXqt>U=wXmhwW+8p80=3?7~mxM@OePA3_{}E2Nvjv~*8Qg7d8y;<{QCFhP`T+z- zoAn|Bbuequ=EEV;rqV?jZHf^T=G@b0^USblQ%MIKQ=wq3d@b7iZeX;jAZWB%3!z1u zy9Gs?3ZRTOYsHgj^VK92bVZv=JdHMM0kmlISOVdSHZ=$tZPr3)(dNg3qs_dm_)c+FadvS|ac*&5aZ_-#Ib0WQj>u?fOPlX3iJJIMyaI83 zhDz|XvF;Jbk7_{uVFj(OuISz78R5~U8ai0D7Hzu5;JaH<(WXmCup(wH+PtKTXtUId z5pBAL6dY~3goNv5wxZ3IT|}EoFV$$%HK=m`>}nM}^j@RQ^NS0L?-g4FMVrHxXmdnG zn@bFbphcSxhew+V1?*3YHWieK6c}wbx`;MaC$wl&^`J1j5MNmQpg1Qq+8nNlHi0O3 zl=MPFm+olO^;x-qYDLf3xxP!qCH`nr4V`y~#wD&{P;03jh>A8HlB|Q(;}XRrmDi=w zkBYB_Mw`Pj0OQe@y1!<9!{}>k+Z>lMkr8dWKGWvdE}9R!t7!9THLEDn9c`+?!rbuj zs`nkPjvKRT@47y#_BPhx>9bmDwi0b#RGg%uP0UiyzFU01_+jzm;^Ly!z7wyqv+>a> zti@lJ>@XkFHq}E~Y)a4P$0j$9LwSj2qj93;C2iR)W5QjZ$q9F~v1)|wn5viAozCqr z)|_`%6~mBEKgu7afZt^xgN2b%BX)F&94@$8^*XrV>HcZ) zW8k(nJE=?@TK2YpY%d7d)#!FAfs{S=^?5hb$zPJ2MeaZjek*G zTAbeA2+n39>b8TqI{f)~b+Y8IYqECYi5X1Rw4U0PcS#e46%i@Y+k9LL&0)Cora`o6w_}ILxNN1+`ENcy^*Al8d=!5M^=Z&q| zd87JkW5M>>_Bb{2Uw!1^{}7erZN*o_44$p;*})g3nj*yS^;Wkob(&zV)7w=+b^dm} z4_sd#j!5LnV()g$R>11vPBUZ$$eoO8FIT`It^oKe7xJ{=1>pS-)!=J1=IQ>KoyuEahzMjI1l2llQBY(jwC0r?x{#oZGZO5Hu_sp02N&9(HMI%y0 z(nKoR9fpqh2VLkWAje}Cbu?=yp?9_yOC7bOj)r(mCv+o5s)wN@{zVr`k~tOsnT50o zRuZmU3*FimlI)(jkdElw0b=@+m`XuG%+Y%1fB(S{D`5u%K3UwqH0oKH z)%`8z3>E|MqI+(7Rq?yx_r)KI=d|yIp)M-ckF|Fi!k^?6fm0=i7M6m#9O8{(n8>Ud z+z9Wyu`{-6hsnlb)2U)@FLlu@N*uHLuI`U~VzHb;dCP41>2ZZA>i%N#w5aj=vUWdO z02^_Wj2QA~D_&F^aTDsz^Gd(&&X*2~{|30~3;hXpw}_DO!ySNF?E&M*pI(<i$-LZCWiuQYXR)gDml7(sQAg4k8x zs4b6?V0}op^OP=+P3n#)P#>~anm#&2A1$g6{Lyy3(vZ16TEY5|g{YreeZT_Y=XR=6l>$C?zAC$rD@|#p^Y7ZJg7GC z2j%O1DQg|74Oyo9Db~iOM^WY0(&@@ykrMKdvAC(&xxEE*kvn%*avKmk z23r)Ot`~V@7$_@I$0AGiC$?)?V(uESGNWXxy5GR?%K()o-d4O^oeDv0lgd&h^HN58ZHE!>X=0{>)r zBJFptqdyk!Y2O3?6|#DFV#kBx2FbdOl()jz6b77P7umYTKTI}WXj=}Y6_&pN1KZBp zFT67OkkuyAHt{7U9POGv^*wzYF9XbbpiZ!@(@X~}Pp~~BmcMiJ|8$Jet;Nmlx52b7 z>|3+G-ChU3z$pu;SIKTv6ulHJ;pCUiDSU?~{4X&k7492KnQ-vCBiE*AEtA5n+LS=7 ztuz>dWkO-yQ1PolpiPcoX`@z5T?@Wqo|M~e+lm3l$o|=l7u37DgIB?>99qoN+{^`Sgupq+@(_u%FwC!-bB-NTHi?N zw6@8Nb$Um!Yx~W(PKzBU$GA%QZBNDMN2F)t4W-S)|3ZZ>uPRhY1bq&0lNXI$CQo5X zZ8DSRUzjDz~+$Qc46>KFC!m8aq`< zU<_6AuT3Ofm9=e@D(hOzSe17dkBQ=@LQ`<01tpn@f7vr_Y={wMMnnVZaZg{G#%avatPX19mP&`=d(~X_U-7X9YjM8Rj!;Syx-p;HanWMHf znz5Zdts6Tdqpz_uTOTXOG39EPzZyVSfK^1eE@sWnei&$HL@5cDjsuqrfW2NQGru)2t7aO7X=JOOwEL}f`VUNu-Nt=k16CsFEBoR?IAl}>F2gf)dx;eQTt&44#7VAGk zZ-ZP7H*Nk=#<3rt^YjOz`}zk{{!13( zG1exLR)9xQllW`n{Gi#~N|i(A4Z)POK4s>3VHZ_Mncxdgu&{{>&UWn#wa4T_H#dfeMjNM)=bWby!4S!D*9d z&Y}8YCEw!P1P?!PXl!xsHn9nwtO-BCnwG9Va5lu-WE(Lp{V8n1ydl~qvS)@(j_5xG z9Zq2;Vf$CL-**-IXg?9+U=>#C6LNfB>=TlTn=ke%wU~v4+GfGeshc0?u|vK)HhO4! zSbBJRM0#X;RQj>rlkoI{Q6%+4c}bPCpe(4$@)Bc)@M&hQk?6z}d=9k_2yIDf`VIdW zCsRC_GpOe4r0WMd7nwAItwh>k0BNJdZv38xKe6O}fC+6)cL+1WE61Y3!<$v`s4 ze-g8VGY2(`${az3hKA(?{UZLdd+(%qKrx8MI(zq}=UGBHKEWNb;%lnDp56)9Gi@H}qc3cw^jWt(w83 zK(UU17mn;Q;Ysxdr;vupRG$Un-G8DC~gVAaMG-Z{S1V-e_qY zE*OCWJ1yBL;Jnnw-RA29s)tPkMyxy z%+mZ3&%u)osfiM0Le_?js>r>dm|^LhwzinsJ2|~XybjJS$30n0pN>-F$*yGglstGC zt2bsx9Q?1$Pv2nKoAG27FfjgXXC6cOA45xoTj#deg7V`x_n(KJF-jlIjhv6~Sje^n zJ|KfF+*uKB5rTgj<%d3({;pTToFd$R9g^wtRjuq{wr+_ZlHKi{Nqe% zdzTmJL?R1p!cUPWEw%{o8D9x7g{`=U{tPzw41bb?;rMcGnljuEkN?Pmf1>V1P zrRT4zoa`XsuaSKk#!|93Zv&%0%aqqiPbNI z=JZNz@s#?-^dsU#1Jn$iXiRpOYjc7yn3J8B$VcC7*>moQb#H}X8Ugwkj-+0DUFD|A z9hJK(zpdO`xxe!J%7c}ME1N1$R-UcAP}x5{Fg++eI6WjiIz28uDgA8v`Sc6vsp)BH zr?(pp^)NdOcq6{5zQ{a<9bY!3?&(6~|4(IVW@;mdC#9oGJHxZ;2Y1}q427O5u`${-hSJab zw}4f_`B6D_wld*#6=_l?EEXUE+sOAGeMX;${Y4vt8w!FN*0c<&f;zRNlMrlbm7KnO5hQ5)$ zq6Y_p{Bp-}{lQIVv&&=w4cr4b4((RaZSnt?lKrjT&n?rIoNJ? zN8K#iTAYKrdn;dNfM(IuvbWt*a+uxhpX+8PLe0u?gk~p5vlFG{D7)D)-Rxwb+2zEx zlcd?nQgW=_>}z$ii$l#4+b$-}E-od<+s%^R;W!h&9KX1#_&KQ5HWeC74?Uvs{`iv3iZJF8`Lr}F0F?hAz@@sU<-B1j!B6jZ5 z7=$O2>+F_yCM}0za22t0m&RZhV(>=0<;A4sPz_QCQVz>O4q~%Zyt|E5s z(irSQ4Bl?HypXgUiot1WXBvZDh{3zdqP<+|?kL?{MV6FX1P7=$O27wwjxTelvU-LTjNa^Q_$ zOV3QdnVyw?EB$u*o%HPVyXiUU_tJCI^V0Lv@23}}KS(c3f0$mB{wV!%`jhnH^pfCe(j)63G!(<{;|)1RkTrN2n`V&9rrkgnK$cGoql#x+4Hv#Y4-n;strdR{RYLL6qg z=BkyuOl_2pC#6LrcS9%D&)mTV0DP=kGN5h%If%SLGzkR&tBlwH|78GlLjZCtIRMU1 z6aXfu)CTxSZx2vs0d5`lKm%Ecz%-B?P$mqG*O__vqe;VV`VX8QNw71}^7f23BGd)9 zx;kt`G1cLDH>K>S;8dK$6#04~=o zodXL+BfzTFs%{w2US!AqskDVZSe0K2amkeMfRb(4?y1rDp-kK8_35wD8`2xoo6=vWWl`HZ4S_m?bupPsB!qS4%)|x3whb2Apyt$Uuas<+ zjlzm-6Ab%_-uo~zQkV&5SFl^dxyNL~P~r&5FwoGDZWWN;Aif^7Y7J9|&na2QlrSh3 z#z@nIw+8?(u^YtTeQ~C^DwA-|=juDLTv~dFVLID#%0WU>=pTL=bdML|Esb3F7?uUl zgi#y5CA~HMO}eVL4~|%MdS*p`dS)73g9l!AewH~!iYj}qUOUB{V`0`gNV{OuqbS%4 z?=)?IfoK>EW@*+l)-HhENWrFO;HW`pMh+H)(;HwQ8U`zuIT&jfzz*WxA}kT`7753t zO>Yq`*rv3+C0|N=OP&mRi#qFe(e~=3oqEgd=^g2v>At=HL~m(M!KAQZ&zapfaF1c9 zy|lJM*i|kQs5sbmOin5AU!L5z$$E~30XF`K4bDA?gJ)-$3^@0q2=JjH4KBUud{#?S zhX9wI9xjW!n%z@^gx62VfzI^6)?N*Ej3f?tSdL8*zOx#2uucZOe0TcWw86tD?eDp2 zHs?wwKH931Mo7Xyx8*>?gKUOalpSZ?FbwfMJbzRa7Ee=|!BtpXFbZmDNHq&ccM7DL zS>slv%-o=mxL_1gxm=OW0@9a;IM&c4Y!6j^MyRyP%I;W6Wl%d7%A}hK zplQ;~&O%Mr*yCvb+-4gFsQmLe0yt@yG_&tD08uu|q_2A&1LSRkNuMBqiz(nlX1#9! zqHGl4>tD|RdD{T^Gyz;<0D9+`6(}18xb3zKkhcwhoBFSU-A)abUC;t9I#em9bDgHN zR1e5yn!R|j*Dh+679og>w4fNS(Jp=~d#k~{%YW;|oA@4&tkJf*H@z>tKmA?$`}BeI z!Stc@;q;O8(ew}LW9g>!@$`@B6X}!bQ|Z&`p}iD~G;6anE2gH`u4gw)h-zK4Iz$AN z+&L?GunQ}>d4*imv424eZ)dIQz%oOLT2Rt2O+-D5#)=ShENRKNCM)#nn9QrrSMe)8 zxG~o7o4>@=V)ISvUTCH+%7R;FyO-ETNXli}Jb31t`*;Oi0~}3RZn)gx-+OWUrW^zE zi1f~E59|&o|BMnXVD!S9$MUo3bLl(RVL4cW&I4CG~sC3Ngs;S*O8_^+4i>x_{fmO7;O8MKKTrxlwCzIpji;22Y98_j6etUX{^_4OP`TJP% zH)If-!=vmTW}kiuzOvyHKm+{V+*FzdP>AGxZ}~UlJ>GG?8>>#OU%O%B>+kya58P-}ATN4$|UXh3qyZhzMbI?I|ih+-I?a%&^q?nNx)0fhh)6MBA z;{I_~oe1XvL*hKZEWSg3l@phc1oPEcaN_THxMd9zyuvNp#B+zM__;%s{jJx>gLv)@ zI7+(mE&~LjAtWFPRjUZ~R}^Y`Hw}dw5)TxJhM<5VWKh^DLQPSqU1l{DhPwv}L_<)+ z!yF1*MW_yi>h@2=Ru8HkT>WJA zkm{k;eZ+|?PU`t5u41l`oG}vyoH~mq{wN&gngIo;Bm6KI{~a{SIm{JJOQw9lCQvvLNGOBR%ZXO|EZaE#o5JQ8mq zP&mCvD41S6P<(a?K>@>vP}nSv)g}Uk6M=++>BR%ZXO|Gv=%_Fthq|->7|bs$=|K+w zNi6=vIw1!Rry~%TYXuY2_Ib5l2#VpFAs~b+z5UIVo>{ZcRurHTJ%FwpRXw`;sp>J+ zW2>L8ex`c5ID&=+6-Kw?2%67F9XZu;L5S`Ki*EQ8Z|+VOI)Yoa38Q#`ID*DMVQ|Z$ zh0F@iz~R9i0D{<7tpbubtYCj*K`5pX!eu%%;;|h-g3v}J8QRYiomdPCq|8Ra(20k3 z00|-+kz`~)K#(x9rS%Ad>ClNsb^r+in_G{E!0iNyMWE1$ke3c59@qgSh-+>=j`So! zVhLU#5!TXy#N#@E1Yyms$C2*oy#hHF_P0IRt8C(O1^7ZAp)4I}AT9TF2BhumNUaQ4 zAkgr~v#kp?f-&!x!H}ObiweS;<{}4OBcJ5ReMasWa|E`82=4PlWSxx>LjS$D)%7Ti2y#EO#~U#y;5J+1ns>PwL%2V6HT z!jtVB*W+mgk{sQQY}c5K*n?z|9GCFbrrb?yI>075EFiv8@gmtI$DdOuTvJFoz$Q5? zD85wjLfIt8-%u!AR7fbB4us z`mcm82#_3;<8tMX8DJc6kS^%rE3d$hB&iipa|=n+kZ65O#N@b(s$OenlL~G3h2b`0Rpv#$+q2WsBtaICmtmnbvfGO>&q(n&j{yStQ3z z1PZ4YxpB5h4ik#cF1YdZL0KfnqXY`47YSvP93~W>T|!V6$#ENj!s$gq*(8Sv#b=ig zltpq}OQ3Likx(|tVM6iQB?M)W9KR<}IK4pJ{7;B*(X_->IHm{ciP~>i4SWR=*NQa!eW{*d!$j9l?z| zO(af$diYPWrS*{*p`HVO>&q>JhlTWStQ5f1PMc1BH1K|iNr%Y zfCQ0^#$&C5_3k1_7}*lZCOJ$b9@zmTi{!Y0AYoujB%9Ea~E`PJ`NFR1>YdSUg4)r+b>s(xIN91yB=l`mJnQT=B1tm?O_=T(1PeKD5gSe8q2 zOmLFpP3BhDPjciwBX^8B0$W0I{6!IxL#yi|IdXbefaJ(+A;JKIAvtP%9tx8j+7uSa z!F5PV*2rf_jx*v&4vj-ejyw>9Pea^xb}B*&joC|s$?jk8U1SWtYaf*a>tD4XOk z$}4bDA)#!N!-C>#6)%)ca%@Yr!nKNovPljLiZ52YP&Uc&Dhh>*6$xdN92OK`t$3kq zlEbLF!PSa{vPljLiZ55ZP&Uc&XR#!Q2_;C5JeR0kR=vD>MfJ++&#PBee^LDep$h^e z$1*3$F`-BfE1>3RxkZ5FSmq=-c+*I7*iFAgdL1A+mN_dqc+*I7*iEN#B*!v0$-%A8 zNe-)Ji{$uc?z2IX!vxYKhY!gjIj$y9IK9Y?vrTfCP<(d5ji(RFA~|Sz1x_y#$|gBX zC_cM{pkONmhE-dkUlFZvdXZ2z$zekA*(C&JksOy3D4bp-ludG&P<(a?L0KdRt-8VK zMMBvmhY7`Jmk^Xia$H@2O=Gi}X}8>%-} zZ>s*f`sFy1W0{-en9wALr6>kBAvr!uwzNKy!^F`fhX=?aIj$o}7~695Y?B-&5|3@% zV0w@&l7rS)U}#Guo8&N&cxVTZAhIdR@oS$tF2W zBp%oSB#Y#r6*m~y63HexOe7xH0VIp$xUK-nVWL?ihjNXDma`WjIed*^%p1C8fCfi$ zd?KFYFpOf696oh4$>EcVQ@S|GaZB~q>TjyIRd27}QN6QzS9LcMyI; zRIjbxT)n&6j3qhrmDqMA$0R2?-cp3*$bClc7;^-+gyd)xAvv_VE|MdscLhj}+!i7X zFc^|!6QA+IB!@PIMRIT*l9Dy@8It4VIFdu-P?94L#2`7QBS{VoVUZlU!=XuzT#<+o zD^7CUQ@yu(U-ka##gQb3zFgd_*oH|C3rLe3xkxt2QKeA0Qjr^H zo8+*d_)-No&bd%F$?*mXg-aC)Ws@8h6kn@&p=^?)O`&kDBB5-O!-C?A6)%)catu=_ zT&zeao8+*d_-e%qWs@AQrBJw9kx(|tVL|cbiWkZzIjXTFhY2M}jy#vB{J#1?^}*^x z)rYH(R3EMWH=zpxB*&DKhZRupg@)+YRi>OI2X7il4!h|`Nz(z6W6DW#@TQUE zu$z81j^vnflN{XYoaC@twn&b5az_f1943$^IebVK$#D^Z!s$hBoNbcBgyORcZajTZ z7RhlVfx_uULfIsT3B_lZ5EN{MD9Q0t0)^9ygtAEv6N=9+At;OFIG;e_^dg~blEZ}J zvr7odA~~)hP&mCvD4XOkq4?|)g0e`Ciwck&8qPs-X#d#C@_B>g@QUG@!R&vgt@)80 zf2=-HeX{yg_37#})n}`piz7Lv+$6`OCOIrcEs|p+**yD54iiU{93CKxs z#=N0h254|3$6oOyhhY?poYKWfj_0c{R9~#VRDHR+xw?PtfZFzo%8uYO&Qc|6IFj-)>%|5T67ZHUHnyi{SO2{P%yvMXJVojzb66 z&h7mNsI#ClJF{+jW(HRJ^7d^0i7xW?GN>fq8{oq5mJ7R9r^U<$lN;WMIbIsEY=@DQ z@VkNV>IV3l)$quEoA)oz9osvELBma)99q0e+F8ESPS!`J(4G>Ui_2GRBEW~o#QP@h zk2_;mZtVXf$W)aMLuKo0%5FPIdDxCv{YY#pln<#LT6<^jBdGE4>=YQ9-QNN4=DQ3n z%gJY_oJQ`H(pV$Ev9~`$j;v&u;y!>J3rkdxb(+@=8)4on4D;fC(raGX4`JSpZC=QX|ILEsRg) z1-TE#NMS5*GGp0%fl)YSeSBkP}+D$_xd@ek?{?{#I1T za%hvyo5d|+{O(`BO{#U>JL9F!H}oF@FTq&ndTAdqZxgeeM9PDYuopW+9hToH49mqB ziMxcMzWEw^yTqM>zQ$fYs&;hkwY_IBC`QrA;r=RhC5ZhAMhFPSA~0EJFmy^|^9u&& zgBi^oQd<%XPx4R3S3n<}|I|%Y?nt2OyQV;N7e@z?|MzE@Y#2D3iM7UH!eEgR2Dn(a z=44}*P__|a0CTb<44i85C8H4rPPth1H<`0QL>L@XJGQo<_ae&;z^;hgP*w`FP@p$g zKq$!7hLV@z(3Gnk_?Pk0R<39OAoe2{J1jK>pF{lvLR%6G@94dTB?joWNDO6p4Y&-4 zd=r?7A<)ZgKxl)2it_%pU@MUZ8B92A-@hMviCc6wuD*Lsh<6Ba84N*{cq|0PA~i1_ z37@GQS39EjBxt%|6g_(ixHox6lq(A4N{q?6BA`=RIIjqBK4+`#5ZaOmxTm)jMgZQY zgxNq1agO^F-AOi}W9R7KJbd5TN~9?U?WmZ zd>oCvy1FHq$;yG`&I%8+k9aJK8B3%I4(fdXaN#3CQ>%C3$l`WK>kM{cT)_%a*ut8a zi4B^x+p1lBQSx8<8vzTx9K`!LWCbO?Hju(`@i1KZbG6UcE)XXL;MOaqW+f-VK8Io& zQLcu#Ahg~Pk-$HKvYll>JSh-uqAEKJUKnk`arC#9+&Drq3DK;4H{v4Yx@>tHhsXIDlx7u1dc&p|m%DS3-y>|~>0(I1PmI{Z_w2k-ET zE2ykX$v_VZ1d*qf5pt&RbUtC)=LFZYHZci zKrrb7W-ek&UTx;PsBQtivNuhdSj zeYN(r+Ut6K5Ll4FM1W;aa+Ty-08Yvq+fWv!ZoaN#4<XJ6EeLiNwOLFs zjGn2C?AOG(JoH#t2FI&pe(JJP+2!9qxW{`xT&heHr^@(5MGSxt3Ec1)^T{V(?K z2K6gq#8h%~hNaS;JY}5j?uQUV7N~iYq(A<7A1czUQEWwA^(9_H?;LdEWq#36Ct=hM1_w*hH)nGvi z&@1(%74+wo(xK~Y|AfZ*VKgvhXcYEE$xC(G4EL}UG2cND3LQ%?ss#Mts?>@Ws-P&Qjr_sC9 z{`%Fc`_njIlggCLLS(U8I&pDOas)fqW-i`e*Pq^vtwlCCC+^MS*cKQ=u6D#@QLQsy zFL_RkH%n-etL94L#1y*Cmm`D<&TbyG>P%d^dV~r?!*Y$zH{qf$Y`RsmctktVrcm1Q z+5u}m7sTy$xH7}}Ty}29gv{rE-v2GQMNN-r-uKz~&Waj`yMT262)*{JMQO%!S+G6s z3($G^$*fzF3S_JlGFG+xz1q38@AdFoU*P=f`m5IT}`V+J!%jBk5fH46%Pi0n(V{f!x>+CnI{Bd8j82a0D|C}K7Q$}E`tC@R@E0d zSL~T6Sg95`F}m?Mh>?u90!9J;_#)x_+V^Yk5NTjlTpCb2T~``drP9D`ku>0aOwSM= zvH69;{}E{b8jeW=N_9sX@boP*2Ke;mZ713k1Bifk^E9CQ6G#KZIIc9H+i`dXO#@!R zXajK9_dEX&Y8S!^pQiypjY$JUNfbBJfb2O;77iVU5cTNi25im7eX;=6i5R;J^4x?42bs7_8v(rng;f^QEQk_EtZrdJO0{l6#K$=@$iT7 z(%T&~|8Q9Zq*w!N-pn{%?9+a%Y|Q_B2mwcXSRiEdtX9w!1R!hzhE!*EOloyl6gFT{ z*qpnYR}nB3{4@sDUuAi}0({Tom)T+^ft2MeI@#$A{iOE&-eWkhNq@~ctPK?->te?j zOMV7LA-D&w(buJa~3lHG1S&CgM+G6a+N}>5zm%~|D;#vuem3=jyCni2JkZ36gWN@XxOupUC_&Xn`l>pvG7Li@{~28HYmKi3$iLvdA&I z^%ma5xb^@h2qzgv4-OZ)Y{Y;@(~`Z*4saGcs}6 zPL`OG5zGX`hOgCRlVJAuiuw|Gc4qf=Fg=QrolM<_GCG$G!_?~)*(l(2dwZfX!)x$E z(%a!D#TRw*=b|<6X{Au)H5#ljXnV513EGA-95!7k*4DjGmB!-I;5_7HDSx)6CrkNK zadUd3ruOupLSo6!-CI)v{ zRv)Mn3)|W zypr*$fGml(@zTefww9zmo+qFq^?FAjdVi}>SW2MQ##Co za3&wS49WSJUPCXoN<_NM_%o`Y4vk@{>>=45|3O{aE$5n=Od+moxpM#HbFgObZySV{5sjk;m3@U1=O! zuTf=4!C6v{IgYS&YQGMYzsvKB7(I&@YTQ-3yLMiD8Il@e^yihJ9OLkGjY$!Y4m^eW zdPU~#(+i7~At{Z~sZnFA49TsrJxfa$6MGX@UFTJf^LJhm)PDeu{gf_4LeG{L*SH8= zWeYTga&2!X<#ZhoiX3bsimjc!tH|!2+P!dFOp!9A6t$IUMt_-2D81w_;^TRDD>I ztI0mxy~q-bn1+`*;Ew{G1!8og=g)p`injuf1IG%UM8X5L2WxLB zRED%%?Q~sfKyKALrQ?gF0qMvFAP3js0>M~?nnckzD33WpDw-aM4Ms&5pbee zh7?Q#$}dDEnw18;deJoC6^u4OjPpNSdjwYaMaqz<2V~QL>^Y=?Nbl!Uga0`l@IJZu z`TtSH%8;n~*)-tmUStRi)*b^0f|XVoQZNnJQDCP5zmaGf@Jkl)itvKy54Fc&HxOHf zv|Lh>aLfwZKC=v|Q##o(^Q+W zRVu|4;Uv1I?AhotB&Bms8Iq%8IGM>}pSUt4XCrYI7)%+`yCchxlr@mWvg?E3EW;ju zs|;zU$TB1a!)uG+AjWWoER0!(^!C^?B!$D))G_*4Wk~W4dNvvR%8(S2kPNG2l_4D- zUxuWx^2(5$?lv?mi+%preReQqNFRwTLsI5|+z>OwMj6sJv1LdU1qznJ<7<{7JsMMn zq%iC2iHGZ zs0?YPjK@$JQm1sb)7JDn0aYv&Dnrun29uL1`EjF1RKeV&s$e9Whi3PcA*n8b+0`>( zdqf>W9{!EL4WHQqEVQGNexF+^7NAzEByGhIbEu-2A%HBL?7kH2}J)zyL^# z;M}4)EIk0~kEO&mN%`>l5%pK;G9>)4k8cM#rQCnTOcw^3Zww(3!N=4tw#+^Egf2r0 zwkvgjl%w0lUrNcPcDoCUlp#&Ynb*ocq}Zfey3&GhCLg;F$N89ENwEClkYR+ES?=yB zULdz2{bzg`l2V!^zM#VPd~9XC0jfW*GNdXgLqd1*Ef$sjd=MZP+GR+NfiV}0dBaEF z!pW22L!852v6stSWk{c@A5(uUx(sQ`mF#&qLh|dDu8wwT|3m1|K8bm|^A`)0At`0) z3d7ecWIDzKl`fb&Yk9%yHT+G)s6K#djsK_0kb<+M9CI9D>C}E5tTH60U&QEHybS5n z_0QDj;>(cK5a*O3IeQLoNULFm&nL+%>vUy`^C{HVD>84N{`(?jNJ`_JG9+i;quko7 zoLz?GfIhDUm23J1$g#K<=O!~xNir9A_u!@8Pf6f6YAR+DnnYOmQJqo zXSs6jmacP7+;rREC_{2ShN_#TEDkZ|>xIjZ{<%;Yl2+YVGza?@dH5F5PP8coaP)Sx zS%!qJZ&3qA0R}Y=D??K5AE6gLfA+div;ktypHHfvT;EWr42de4J%5%xU+M5q@PXWG zF#OM<%2o-Bqy72$|3Ssdkf{3E^Jl*rQI&XMJ^8dBmg94Oo4J7~p|`dt{NGCcE5Vjq zWk?tWzA_|gA$|>p3WIQ;Vdc(l1&fg^;uSe7cv6P+x%%hpPZugfTBUZnt~4OG>fO?f zMbd!xF&+9IvH69;*9w&(Y1JKRz|*%vX~5e~v?&IV2Cg*Akb-GI`Gufxl>hTI;MI$! z0k2@R0b{seBFx- zfx+5i0739^s|+ca2J9%%n}HbJXd3XFvxrxO)4*xNq$FKsNZrycj+x&o z+fbJiL3N3B8hYSv?QmJ4W(qBfGAt{}6%8(o#!^x~z z8IrS+I13D>4C$E2G9+aUR~ZtVW!U3yl_A{|S%#!wTxCcu7_$ti5nG0&aM%{bu2FFT zS!GDC5=d+^_LU(iBq0fBONMu6EoYS>{cU_1lETU>Lvp%X(J~}wBXK@Em@=f(BFm7J zIUHq3t|2zckgkg@L!u~|G9(v_S%&nbm@*`VVV5Df+Sg@BUm;~kn7e!@OA3OOA*t+T z_^KV`t}>)8@Q&hTNMEggt^W1;8TB*k->84HepdZk^>4$jmEMNb4b)alOY#yA`S}s8 zs;%Iszjs@iZLY2X*g3Ahcw<^F{O}Ol0^rBM_t^mBMaqz-<(kVn2IiY91jTZoZs`FF z#d#8pbsP7@mmw)^avB?hYoB0Q2eR0Uqs%fS97c<4G|G@vPn5zi&)Qu{Y#Wr%seiBj zchO}?(`pq2WWK8msatv^*2*szC__@X^pH?_DLWK(;o4SK2TJYASwVba)Wk}u9lTib3ccC&Q4euTR zx%qXYM-0GuY5;UofdP;f!MR0qSlKcp7y#QO)$j-QO{}nS6vt|IS^a%aDTYN*y5O=yvg!QZiz<`?~^VNS*PV{6ng8CQ7LV;Y>bu9gg!c zz0PEL%^|}GulbZAT^e16q?IO#FQ~9RA6r>(fa=ey3~6^#hJ^0qSuAS(`5?%OjgSdw z&3fMOWy+9phnUAg{B1}V*DtBx6kCSW8JF1(H@q_0tCEz7QX|@>{STo-`y}S=&JV?x zA!%jl3d7ecWIBqJAvx_8qxt}p^svj29GXNbTim-ZuU}EG7b!#Pbkx$xb^a_@&J(3E=fq97 z4URG-=VR#Se2?jAo%wpI#Q=`pZZ*r0(Df~9fR-T{ z#$g2*%KansqUX<^LFQo)Y>)dw&boyZU;Mm&Reed3G9*LE?D@0o`AVl7N0cEspTjY? z3R4_%^Yi~}3zZ=m>SxcN1L_AhjjWzJtS5JYupFQJx3~=HlU5lLMuDdc$*>SFLsDT7 z?sHBVl4G=sSb@iZ|2Cwn>%XkuUZf1E(@{HJR~nG}_leS0Mbd!xF+KNr#O4Nmh{AhHap(~*>5os4eFS0Ma3W z-oK?~NGGW>BphT<8IqyDn&o`m%akEGRN$H2*Gf=HRkK6OkZ!8)7F&kY=}3MirwnPL zw2fnIgJnq0$8bo=;kQEu^;IerEJON_*fJ!ob50qOqhmOk6)Qt>HWFun!IUB07FUL( zt>G#|g0l>J{H-#ibK=U7G>oeZ$pvGUA>AHXhNN-W7R4?@asgRoNcTpTA!#I*1!It` zGNfj78Is1zD?@U+ThTHkXCrYwJD4)0N8-wmv^gAQNUk9^%8*WrEJHF-GG$0E7_$uN zUn9zpG=^P<UYU8D8 z4-c^|0DcU-oel7Efik2{SFX9dWk?gHH(4molVGgdI48OcNn?}KSiY%4WwHFpjccD^ zSqHM%i+7o2NH~lZ*GS8dbWap;rVI%}#kN8DzWV+3Gh)k-I$gC2A}5o|Tkz$ zQ5tvJnw}@1BOO_!42i%SOirc@$&DT$G_gB-sVW#rj-uH;Wk|Y9V0QJ4s|*PSz&1(w zq58x1?-eOS>P*P_DpZCvQJRbzfU}E~ArW}@07x#ujUF)opHu^&n+gnov&}3kc7mT3gii;r|77j3+L5(S)jnN2zIIaWv$a!dr`5h*JEL}H z?X22&YUk9>t6fn0VeQAYi)+8AU0wTS?Yi0xwO`k6t^KBUTkX!;Z)^9}eqVd2_GoQW z?T@vWYA@F|*AA?IvVK_o$of(BqwB}kkE@?p|7`t~`l+X- z|55$N^`F##TEDD*W&IcRYwFk6Z>;~i{@eOJ^?U2Tt3OzOr2bg_XT2Hd?AF7qwEm6k zBeC|^ZYNc-6kE=wpjdY!$S0*qvrsB2l~_CQeb`O?tDsrlD*L>x{<(=HMW8izp?1z2}cIff?MDIV~&kHKEGwY^jW*~y)8F2PH zlau4pf4HzLX=yRDtywqQpIrf;^Bl2k$MUmyF&Zv%hPz0HN7z>;5A7Yopl7Ccag5VhUH?6#9hKr-<;mtC2o8= zy_cV>KVN@K?->k=Q4ESHLi;)bLe;-8S!XbGN@Md22Iqqr%^gx(5)8i;ho7Ji&VR%5 zj#PIfQ1x9?Ai9gAgUFSdg^b}aa5fWbjlqOL(+C5+V%nOMjafq3MuY*($&N5^s>N%- zj4*J@#j3x_oCPAn;Klk&^&NWnNz4Vcsospp4P~V;3xz$66t8Lkl)MZF+^%*vf*Ign z#!Fkdq5*)|k6i4q)DV0Q^$!SbNi3}Hy@n+Q=(b1*{rjPpsT|j`oGQf4<2j}g;xZV5D)CqdibZN(JQ6n7_iwzW_atb#U=%%j zs#I3zfUYQzD={YPihxdO;k+Wi`JAn`LugAP;M(3+7y%Vf2D5=0;vDxUx|3``$Ij8e zdHBAwl}J+z#`j;KzTeS?ar?fs3-^7M2!e*m`u>(^UflN&Y#h|sulFGOeloQyV+G!9 zY{ATgCpQNuDm@?1uDcuA!`ryrUMGIO%ViV4{~;V`pTw3pe1o6&3uQg${gdR(glWrG zxV~=5)vaG<9?IG2oTm=DsvY`dSxERiPoMDGKDyLCDqEHmSS@m zqm$Us8S|Jr>fwUgG2l5k)`FuB$Joh6!J_B&-mhF9PM=|$pvNvBh?PxAkIzLCgU6Z$ zsBiVQ#{A3%6ii39Yp^k22ELMy2jURgj1UxICO~cN*Z`W}OwyBfW^sykKqEO?(Fr>}NIsUS+-hGEhL%wle0X|b8&a)QQ&lk1^XO<_5nML-^@Rqj< zv%pz4HA@$wsGB(fQS$?nE?}0exK;i%X1TVQS!CY~v+UM?6uQi37l>&^2FY(rxr0bV zHyDPkiGm|dSGl<}1E)L#ZQ=Cs;--tK=H}vPxcyc(26S;W`l-e-jbj_1ZhWS3T;pT< z)_`%)SFVy=H0Pu`tzI!R4oQNq>tF^MFC{x$8Defu-x?5XS7tYeI^8b*0>_AUyQdep zHDGd5?nA6{5uU$U&Bl0XR||rjMLF-q4?Ttxn_mXUt2Ccm1D=n*H9#v(>Qwx_$}U*w ztNqQ&=zi+ffbPb8tHr5Ln@-9j^m628HPtJp9g}Je`1m^T@r}77$*lqCPM+E>tv~On zjLMJ+cuEXrCzj4^BB&1 z2(|S|%-fw8#orpBm8AtizFs-p*{TL&FWdQ>h*5n2FIT^$ZVd>|l5)&(u%uJ_b>J@T zmxcf(JrQAPm;+m4rJi=+YXV|woMh|Mny-c;n)0HV4h4S4z%83TNJ^R^Rh ziUCBx-3wIju>P6FlS1{TD-1QyXSCR(4*7!QC@C)1;V0b__4alBD8i@3M zJ~jBC)6)U4E3{Vz}LOV5E!gI1`q^KTek)T(|{cXdNUBC8%+a#a~AQ6 za2hzX@eSAwMBW-OxmZ$??D%WHQS1xfp~D}>OK*3~{MK96?pp)88}ptIA)xoG;}rga zxkXrQ-poj3+ym)XzIRM&b>Qb3z|S@3eyMH^z(Mwr$W(uo<^2YrG{*m$lIj(EdTYR0 zjq_q}4VYXkcd_=Z0eA!s2ZZCLcR9v3|JDHCV>qOosmyB{2UV$5@YaB{Vs8!5I@`Af z_&Tp$$a7le*N$&#{4!{P!Q2|~invesza$q&NRp}p=FVAttXl&ST^~)vUz? z!-h9*4S0LxtpVETfTC{=PzKL>l6h;unlm1C8W9xV z-XAaRW1%=tg0Xh%L(#VeXl!yC8-r_AkkM09* z0BtPZK$RsSrj4cgU}JtxCkoue@1?}nzWn3HPa6NX$gKgBOJzJdZVl*e1SEZ)@G+;Y z>3IUGI924<00M6?Ie2S81bTqe$L=gtFRg1uyf3ZmE>Y#dyB&Q>Y?G8PY5cTtNs(Iv zCYQ?j%5iG|GlATGj+Z_jH30h*xix^my9dCJ9x(uas|G+f6&L_%5f}jV3>^UV$5LXO zq68w$Ae_m^uETLYrgw*VO*6u4K4nM~@nuL#X_EMY3fuEBD{SLL zq^k^R3)H6xHM$JxQc{M5?&Mo6D*gE&n2W`{fsyChAw$IuaSnS`t-u+-s|@MqjjI}y z(Pc=>WVWNpUX`14N=HSzwErQ^U_nlGG&^s1en){aB&94}VfgzURj=W1B1ZKARBJ3z zWk|tUQjR$eg>-7a4wS!h4c%e{m&TVNsUglOLvpwtaPx_?R#aD} zIG@6C^@_~fr;{RONJ`_JG9+i;quko793OA52=|Sp^TGDG zFXXIS$occH8aFgfC{%_-mCT+$%bu@vx^dpeOGv?q^En)ItAxcNH$VUXyJBTXRQ>Gv zb3pyTrjb?Rh4thv5SHU}Kd<%^rD*gufuV|+iAvj5(rU9>(}jXNCiMm!N;ct8vNiXl zRfdF7;44F-7UE?{Dh$GXhE!0C8|@-i;Bnxu#JH*P>&E{nRED%%?Q~sfKyKALrQ?gF z0qMvFAUyWs0>M~?nnckz7ZFue?Dz{^`dFO zD;RBn80WvGaVxCwigw(k>1az2LE$kflCzOG3k;?V>F*=Ukd!rCWk_(AVUNF6hO~WT8Ipo=l_9xc%rd0)v1LdKhiy^R zCq+bYhYQFmL)s&@3`rreX*&kVDnr^oz6?oW<&_~h-7Wg#CCWPXV8f|WoX-xX4C$Sb zWk|{#jxr?I5F2GkuZk^0q9~a%Bo~ZXhIC&{8Ir=V%aB~{>oTO@kuoIAUA~hg1;L7m zRQB@E#4>+{q~g4zcp1{&jo&uzY24emuW^6lca7gS9%ww+c&Dxsg1RES^4V8gu|krU zc*xI>XjOp+dptSK%4~CMGyprt4FJf6A0A>`0Q?yEbQ|C!Maqy?$TgR@45?E(!$NVM z1Y@DZ>*LFi6gD}H<(oQG7R#U9xPb#%?8TL484?bo#WflwGO8yEI8%lMp<>&h{AlA3 zjgjawq!nrv1Y|y}ZxeKDa18R|4o51B!x>43B$Oyl^tbBN7FK-V5ms-!N#a8 zSlH}DVryUC)OfscM4>XIl`165Ax@ryI{ScG6`?-M|iVO1b}vnJz6u z>Xwp=EpyL3q|1+?tmr`=6-EO-`8PZfv{vpLC-O`m7gfscrWk}A)^h$!| z7l#ZZyyjDe^uG8qB&9S-d_jfn`8ZI93yl{WrRXxGDVgn@Wk}u9)zL1kDo~scp+oy5=Izc$7AQkf z%F-2vuUE))j2TRau2&)VX!x6mQGEc_8vCd+q~I(m#~hY7FiY}__xw6oWk_2v#6=4= zUT$n|92;MTq=q=B49VH^U>TD0DI8Z_yy6gKiS+^s0@iJnLU4&JzweYPw;_64@!BMCp4=x z#rYhn9G07(|9`Al84^`Ld;T0yKd@AKQ@+^Tm=Hx@|)-p6$4d&K4!2FDdDL(-}{ z(txLLh0=hxooG`GAOg-a%aDR;K>3BBaFqY^G~m^XrU9>Dv;ktA|A^+1%}*67L!us# zO#`y$kOm^X-zrUUKBv=wul@P?|2K=3AyM_SX~5UL$PgH;Jq8d2@3qR1f@#2x0=*fC z(al+gw8dV*W5IVl&(f^8^6tkU;O> z(lVrFstgGS*;j@{^;ff;uX}Q<=a<=HB~{H1EkioCxiq>AX_e$>a>|gprQ0228!SU| zK8D(oV{L~F4ysbAU>VY@qsx$#&N*dBj*j7ER;&!k*+`rP22+Og-;rfV${MaRBsj~k z$KNVLx;3&4Nx`_vkX$fk8PafU8IrXjN?mdpx<@%4~CG4ZzNE{bfkga^Z)E*cJdk2ENY* z*r7-n(zIN2dCQQxr3Wk&=SeUYO57S>hNQ5`X)NE=p|V(p&hd}{Nw=AO}INYiQ+1Z2Le45?dsB-YAL6(~bexb%=vc_|*5 zIdN?(JIauDrDaILP?73`jrlp9QHBKewY4vQx%rjm9fit}R?Bz{l_7OYo1C_$=LzUY z=M*YK((ne8lPN=TqX!60?9QR83PzHnXm(#2lIjweT|MI}LxKUYO;Y}9^J~q2EL4WH zTFzIYGNf+l$*2LixlkFBhIbEu#59(u98pxp-W;|B9IjT81=HN=l29oh5sP|DC%)mmvk)l{!Gm(e2_drDViz_l^Q( zNQ=jF@((FVnJA?egfscrWk}A)^h$!|7l#ZZyyjDe^xfz(B&{?_d_jfn`Pj;O15|%r zWk@SY84|jaXR)aD=Yt?CHbN%Ilp#5WFH?r(kl{njV4OTCA!&_s%8(o#i*#$Ra&{S#0|xaUfMf5a%aG8sJ!MGR7U0<{m1_s|;JzIY ziX7~s-u=Dixy{!UDMMP^QA;P+`LkR(Pn5=-6F1#9ILeTmkD=;jDT_ml`Fi0pq|=L( zAraM$MRTxkk%w;)?L?bm07q|^n`KDo`W7`n%a9D?umTL_{thTI;MI$!0k2@R0b-p0qUMiag|Cx;e{`w%99pEM#`RWI^w-|s|;zPw9qm0TV)%bG9>5o7z3Oq07!=fdjFP|AswvBkZ_PaWk`npYL@eLPafm? zWwuyJRkK6Okbc@+A6tgBxFh+QoHC?|(l(B<4VED}A46@)v9?172UV$5ung&+V#|=U z&N*dBj*j7ER;&!k*+`rP22+M~Wn3AOwuY+=3C=R?@wdv5&WtNV(lD+vBo~ZXhIB(@ z8Is0fTNJxE$OUATA^j$@3`rxgEEt1il_8Bpmmz7ayfP%GyA>@%ayAm@vx6x^x;3s0 zNt?q_hU6MzqYUY!$TB1YB~ymvf-%dG_K7G%(inCblB<1PhV&s)hJ?Axce13Wcvgm_ zvX_4*mia3r73Uqr%aAT@Ue>(4c}4Te=Fgi~HGk2(y7|lIy}C*W>WC)%Wk`#=lDx!2 zettx&3Ov~3$s#MW&0VJf*g3AZ3~6y!F8uHi+XCRnz}wjXPZcObTHKXuE^isqMCnZy zit{8G3nk8sE<@7TQGrMLvrKVCs@{jEcT*rmLcIVT3jP7L()A_z?m{62o>7~ z&R3x_q>0jG)Bt?F zNEs4=cMpK%65Qw!1MuH!0CZD<0gx8KxkYnW*)k*;0NW(x-!yM)KD_P>*l8#DVZYMw z-1zTEg~cZcJkofq@yEtfjb|IrHJ)$0 z)Y!jyQ1g)H;mxC($233PJf-=C<`J=MiW?{`B4mUfCciPGP>TPFyQWZ@xVL2n# zrdO}s$R96_4DHNG2L8W1>8R{rLtf&Zb91Sh$8^^Kr2=$8(fNeW*xsKVC_ zYI85Mq6Aw#`4viifaOxJ9O{Q$4-H%!`wC}nPFj{QbSGr8cfjAbPFDA4H^9hk|IU>k z{P?2mphc-$yFAUQ&yW< zJ5@^3tkq<5V78lkWq@9gtnTfJ;q+!~f8Rw*ciL&v_shbu$F3UL^|ATm;GR_nS? zJ0^`Lgk1~5u08jEdwW1vw;t*3u@!cXfF-L@r-0u|ER;3<)@cwkBjkug81++-668o_K7{bEA|+729e$wsVDq8o4!!rF z8NtQ&oSvD11v;No&}a3w6XH>oK5;=XV9K-UOeq<2x-4sN7>xIt-rfjN-7pR7EDpkQ z!=jD{gp2xNhK6*T2((l0y$FSey&N1^p1fRg3lzVsUSGwAjeZs&{}2IwQJO04aatkPxvYZ29v3yP)Nf)qV6_ zvEYykTzBgr>TSL9Nb}L=ADWLfH#Hw`{;|2T_d!0`EIg)qGcx?Mt4&oE!XpG^0f;Y; z`}kn8RW?j&N|vc}aqpvu){v3H@ferMg2h;~6FeR)5r{)WX4_!G8+#u{%(@5~4#~Dc zi!g3-AbH$GAePHU%K&&*@81xxsp5x2vWwhV2<1VF5Q+dD9=2Ks*hOL_x$ARG9=4g) zjk2tg4UOc;NKMJIk-SNu@hG5Z7+7u%m23ztNoq=#q20#bs~BC){7h|RWgxiGn6OMx z#7%84ReKh{45lcb1SbBA&BSl+^xg_ifj=}yjXv3Ys`+&DndY<2=bGZH95Cg>Jhf&P z*H=7^WY$;ea9)anLHW`VA4?Wy2MgSg3w#j-0FaYo`m}frP z?}Kad-$l09cAGE4(B@{^djQ&9P+7fU?QDNf@Mv*v)mi4?pws~lmxe(ZL4(%WI*d24 z$Wj8A^iX=s?Y3PaZvYHD5^NO*s#JP5f5E9B$w1Bh8+(@^qpQ>Xvbr)xD$sH9Hi6$D z|2x_Z9nks_8O-V6U@GPaMs9k~%wR$T+Z7y4_alb7E|K{S<{5f0sjlw9%;;(krmI(S zU!+FdE%d*m-Oxd;$Jv^7!RYS0tywh=6N>fbixKmSnQX8|aqdadGJYSz z+p@GAHijSNU@4aUQc7m+mLDW7<163ZmgW48jloqMx@CC9`0aMfclI7(^VH1rTF#Zr zdCI|+>lci++X4dxC`~xnp zg#S!tbJ1c&d~;#f7*EZN!=O0Ecv~D`_+eu_JhETQ)+*=8C@~!4yUjI($>S+Y!|p;l?%2yQY6B(@MqppXq~n;Q%Fu9w+d$CS zn>TZY26?u@+XD`Y@8$+)SJK+fAfO>t>u&9s)U;iCoD?3OUI!-O+xH23C9JK%3cqX{ zfL^92B-?Jw+JnW_fApV#-pN=)iv?m$PKqMd;0af(<(QtY5$yii-Gj*}-rd@zy>iXF z?WWDAvVSBiq2VK1N4Ab??N=n;vka!x$ds7+6p;2aD(T!5D5`UEiOAb9^!?7Oh55 zq-X#qNl2rBbTF^uPB-kiw$F!!A0}9btprF&25_LdS~UqU=Nm9MG8|@UuGRR{p`n4& zY9Yw%cD4b7gTrC0v$Bjfq0vcG0mFyq8@*9nL5;3k-Jiw-Ik8RXF5hXVZax%~hABmq z0Z4zd0|%4Y@HUuC;m7j{X6;Rm7I2pF2w*yc)#J4YA&M)^<>N5^3;b+H&L?G`j52@^ zij(wptC^Sblk^FTt0eYDxq$1u{`CoO4gBVny}h6pTUXYs+k=~$kEgvZBLG}70I}`1 zszm@v`u76J2tQo4j#qL*dbTHXgU8Bp$Kw@=7^$(Bc@3nq4Cb++(kAG=K`7UcYaQP@ zp><;Gq}Iu;&$d3-`h4q@))!iz;0K2lh?w3UdIru8mRxyqL9k_=&5rC>C@RX%^r}g) z=4}*3&%xG88b-`O!9e$;z)a6Nz-Qr`D2kqivopPcf^qIgfw`Wc@Ib$|e+QU$lq;@w ziVpV2R!4dV1+(o2fi9UmoC`RJLkK;@+YUx^aYFgj)@iLTwJM^Fr@tPz!hF}0bqKjM z0x1<)_(YOsePM((1&*+|kMj%v)jqW}!^&u0R+phouqhitnT>~4j))E`rvRF)cy-xV zS~vCn33P(9ceY$w4eS%2kkDj=ECY9t6ugiGv(;D-^=DViLitP9ZmLaO0E~$eC~%5C zqVRduswAK&C>O#Q8bVKo_7LF~Spv0o0|M}q1PmXy8nDO;wqGtMD8`x}<8Q%?tY_U9 zyXoB4K`PYw;bGPmcKw&V_v0Xlbi9_*4R>1(Z4;wF5#N{1^krCZ0LfuBj0de>^ zSXBcQ2keWLVqTCWVdDUmXMphKK31kA%q@IpE(8Q+0~n)UZGElv_0}1!Gh5$iZO_l! z>%tZBn6}JWFFfAg(-?4F0K+|;A44~l>*B-7Sk`-K(fv3W4@>ap955jXW(?^DbuqG8t{9sED&VplNiF|#khow35NrWN zqlmM-{~-89iet@j%um4QfC+J#eoWo$VN)|{Pz-0&fDq28n@mR1WZ>GM4*t-S?~$`w z-)eok^_^C)_aXQvs5W9=2US3jjQCk}CK;)+1tkl%<@s^VI(#zOD(jxKVKDBkytoOS zh(99_*)yvYjV45cVB9xFvw(H2zyc>Su`+8Fg(XFUSmkn6%Ca~}c@0{+9$xF_MilF1 zdz+=8gk%tDcvv?IN?q2!3&v|yqF6^TMs`ncuq5urmBrgg~*5sa8)w?w~S{Jr{*t)3o zqt=gGKWSaux}ao`b>i-TMdjOOC3$7ys|seroiwP#Sd+J8?PjnhkCNTGhc(eCxQ7g37_7;8QLKpqfW=s_ zeaf0V8pE2X)-`LAYaqg!d?T7QQ2=}t6rqueVzVX}ka6&^CK?CEK{6V-AO>qP7tNX| z5WD#VmNijOCTo(fmBpHTIi599P#M-lqS@o6{F08U zLr5=-_*i5_=I4_)wSL{YxphnHJ&HBKgSye5wk~g7*}ArMW9!z|L(#0sq%1Y&-l{e~ zUCx^9oOM-`HCap92EAs_tfm!?!J6cun5@Z#6hp7rGizxRLvGFUFih6uT#BLB>lxO> z#E|>)JPeaH`F1pGqEIZ>BoD`CP5#c{89c0s0y0^XJRFNP`IrIYVNEQU(9l?{$%hOW z4{Kt+aTXTlci? zZQa+pzjZQY8uSdDVNE6tra`hMUCElP%FgtZH93Kz=s7q$&l@O`HOWUYS(9TZik^kD zGrfT#S(AJelQlU!o;5LzMp+XHX4}nJ9C(D};viQ9qq#V1^83~Utp{80i(ySBjbadX ziqU0^MzU+x7ZhvqSS)K|Hm_L|j$uP6v+=M(Qp6#m!^$auCM(XGJPe0Sk*vw2yVe9$ zVysCoYd3>6xr*%8J*IBSw=XMR5UTX+CTsGSlx@&!_RMNp;TWt*9*W7DoJ2A7iaoQIHZkPZJP*TUO+HOA z^m;wRnwS`JU!I3yvL;7HvnC3~VomaJY}Vwp2G8JOO%#yHn&jbFtjSsf#>1LeFrlHb zSd(207!PY=!GuP~Vog>QVNDcNhBe`~vjYd_jA+&*w*|Rr$PvKlWH7AB-^8&d#0ZKt z$#Wgbnw%NSnkWE+HOYf8S(8&@SrY|fu_ifIrmRV>NW@4LXH7P@_HQ51KCpdI`{4E` z+lRCdZ6DS?y!{2rH0T*P!k?XPG9g)$y|XhtWljE#qUbp|JI@;^k~PUkFi?MY1OOC?;$2{&?2JG#X`1B$#bCV{zaSl8b{}5sc>ItjUq>quNKeUlGHa zEXlGa6Pz{KC+iD}HMu&LH8GpltO>`kA(YvWHOUpxVTG(orVTV%an|IR_77rNlO=A} z1p3QZlMiR@X0Rq-C%bhIYobvIYm$p$uqGdkVoekPVNG(|r>x1>V^|Z_x@Jvs8z-#E z-qEay0)g7^9zVf2Mt0`}p<=?GxKO z6<|%4nyY+LkHMiBYx1$I_u8zxhtVuqS#hSb;o;6WW z8P-Ii+2f`B5?K?EkX{&Z)+E!;{Cx5Y?Ju@ZZJ*Zum|{)fV`y`uN3=iHKDK>Q`;_*V z+TGsu@bbd$`jWOAAQ<_U%HPuYxI5H<9b z_Ksqhb`KAeoK!&67$$slq}VX!Jfc)|{(FI8dXf(lHluvcJxr!jdYGI&For2dqOcAT z!}QhmA9^1Fzgv*NXW{S)a`tBCzKdiy=@*F6^W;thW#vFsF`n4NY0OCBceT#uchQ=N z(uh99|IuKHjW+c4cC+_RPzAmZGrNL)4vD|fZSJs94Y@mDa=`kt*yw}$NyAbBKB^;I zgEu3m_}HUlVC*#l+DVT+K5ApA30HN)A)&_J*#i1+@eS3P?VI_1ucK>Mt=XdwI?2Je zuS*1@sh7u@tTFg&r>15~W0vLEY&y&*Q}dogHimi6pq?H9RCK;y6K;x+`>dUM8|o_Z zM&{!_hOQtAs`6WX(9iR_tv{sW`?!ysC5O!V##|L`OfV;rV_h%^v ziW+l9o|U3L<*a*ZcN8Yr2s;nvBhFWfBbVt_yG)}UV{9}~xM;s1*VN`Y+B`EBzSLQ?R(Wq1s-Wat0YW~SQ7;0QMi#4Wu#UT+; z7G@5%aOP7WK5UP|`|S(bKWOjGxpq`n zU$%vN4r3#uzSxdpFgg{q9endC*(U49yeS+P@k;6_dR^W@1iF~qZZJ7->u?Ie8^h*b z=*@y|TaSRt!Oo9gE{oSD9VfIZcHb1&PH9|YiK53O}li?q> zFKYj&{W3pwOwokMgqQUNZRAZuXja`yAS9vNY;VQr^F>*Ms}`~ES8*1v%FM)JT(?_M z7%A$<0cuhTvY;E2Uq;)*xNQmsAV(V*0O*e&1Wr)77=t*me;tg&2+=|fL=FZ6ARAVE z)V7!kJ7rXd1V&x{zhlr9KQ#SG`{MQ`?SEPKT2u-G2z0ET-u_zqjP^I$-)f)RzOen{ z_D|a%=XM>1E1AaeyB9jSXun=Ou}t52jB;Sr`Ys#Rtlzj{&8nFdrAld8vNNElA51U2 zLG+Px2?TxsgG1mUdp-m^WA{Sf2_f_aPVE8W+XMo?gux-q=(M%y2DO0vf)HH>aR!0F z51Vrc+(G1PF%g6q9%c{|4C2cKVp2hvclp^`Oa>uFMi|5-gE)miELITaHGVe4;vfW` z5`v)?Gl&xj#1aL87XsxQYDo}cbd*6XVGzd>h@}bwQ*b`S(jWxvWl)Qy4B`j^u}neW zMkXI(Sr8&k8N@OMaWH{ct{|3sA(jUrs#ONDoI!{$)Z$+{7~NuFXC_>0ygT9WuGK_~ z7<(V$t4H=13~zzqjqgr4zUy_-B4X@KFfhIahBv@F;Q((m7zPjU_Ye#WaDm~C@J=|w zn@xtnBmC_I10!5uctgAs4)IotVek;2As86q0>c~Qop6k|+YE!pc(4EOFxkT&aQast z9?H_-rfY$4$bH8yZC}>DynRLc%J$FOSG9l9zPkO(_BHKm+t;2I03mAX=)5Mko(`<4W9{;bVFc|*=#yofZ(g+b z`}X~(MM9FK*J<1kj%L%VZWKc7vjz}}vCM>F0?`cX1{xX?Ks?BfGk|oIWrNHFqDj^b z1hsZtc^+m*8$deFvSDTd(LC!08XguvJkSm`fOMo~1I+}Ysn!iNG9rL@s2yMc=~&B# znh8X+ts5vw1P~9l|7QSUzU5w*&9^2HO}K6#e6xqSGS9gGZUAA*juJi zdl(Q;x*s)wFza%lY}Pe_XxeoH;oCh7i09o88bFwMIZ!t7nm{!3x`C=y0mM`9KXG=Q z|BdBdLGuNs1|#{pk!m&FDohRQ4J4cz1X4Er8af&I*Ns%K3nV@_tTB*qZV*U;$-zj$ zZlp#-Ao0mz%0R-&K_CTY2O|r+k(y0`#Ak=UHIQ(25J-XP!AQhzq*hBH@#$fyfrQh8 zKnlzcMlN=r4SjDOeuefxp- zgYAdf54Rs_Kid97`?2<>_T%k8wx4J}*?y|MNzy~>`z#e}X4YJP$Wx#VC`S@;9}{t! zO~j*2kZp7KCJ-2Dnwiaqpefi5fy^xQg$LPt2n2?hW@hstX!3PKATtXPJi6XaATYKx zGn)@V)2llIYc(WQV5z}-4Mvk0t8R4e?uTJwQ`7T zYNZe~vAQ9UnFR=*RwoGrCRGlRO{x@vrc^fsGP3}|6Y5TqrCZ-;=~S?E*>p-UjAZJ@ zKxUS=2&wcn1OvlcU}O_1#R$hYGP8ie<9jQDf$=RcvMH2egaaIzS-{`{-Xa(n-~uC? zJSj#v!jYK;3?AVr!N3R?7~T*!lBRn+keLMx9^z$!fgvt1yfJR1OE(5Gvw*>4{6(28 zQ8th)iMg`L5}&uTMP)|z_EkI z4j%jD*db$e6|pnkWVu4^TS1N_%Nb0THD|J94MH@%n?U%IC552DJo^k|l+pq2z`b#$-7olI7b7gfCfA2%0S25G+~Fh-5iUAbiP^ zLeOOChG5BZMkLF(5(rM_X8j4bSwyk$#D$= z1C|K#?cQF(V5Ga1K=vUH-GPV(3?>=#vk}=ClylBG=bUrSIp>^nmQFeRx@P88f8VRu z)o*8)|18(M?{#fef3~OJcK3e04S)5dM!7{_OU40~OB|Lfs91IjCc7zRrhBuq{~L7p znJ3$!6YJOW{I<{9})i6i4nMw^oTB&-GWI(%FGgHTR$Sa zvcw3)Qjh3j*)5nvq|7XFw)G>zD@%+(EcJ*kmfeC$#6Q5kh+&Blh@~FU#d1j>%a1`s z3`>kaEcJ*kmP`6rcKnHRNgPYaU|8xIT`ap5lbK49S>kA;E1Bs2W?#_i8C@*96_bn< znI(=k%7|`o_SLMO(Z#Y`G08}gS>kA;jOY$$U&`tkT`ap5lZ>VC^N3=JKacz^-oO&@q~A0<(jdzs0LzRB)*$;UI&tPS$YKU!nUTR7WU=Wp)*#C=^7l7u zkj19YSc5Ff$lu_sL3Sa`RjfglW#sR0)*!n!WW*X|Sw{XAXAQDzKt`-VmSyDcan>OF z`NhBMHV}2!N4!B6ViGIT%Pf6q6^||+Q#`hKT=Dqg3B?nOClyaFo>Dxucv|uF;u*y= zi)R&2!&baVgRK8kXV*`FVkJFGiCEQ8tZsvp`*t-Ui?w^gZ-BCYho``z&Pd@6vaH=R z{T(p)6_BUEvd&214YI7=GyN?v_$831z{1W*nZ_DqS-WTYdth*-$5UWwXQc23S=R2E z{w5e)?C}&>+!-mnL6)_9y6e5(os8gmkEeiP87aI$_KUcZ-6dZyCAj3{DZp4p3U82| zgDLK+ua^?sPvj{eSw;$PkR8Dkcj4Dd32rI!6u>Mag*V842D>9;4YDi-JZdZ^Ap2pQG`IcxG4cJ+t^)NK-XJ?2 zW8D7l$HY$n>=vUQ!y9DZ#~614=*Ps*0PHTK9>W`C-=vE{H#mMV2#X*YEPHa?=cP5l z#bCxDycpDnO!Q*#oZ`8~^NQyeFDPDEyr_6_@si@D#mkD97q2K@S-h%vb@6Ac-!9!@ z!FQ)4X(Lj%l{RJlYil`P>mjebo~ORAyvq~zSO6>!!ab%3i3VBT<(clXaFg*ML{<+H z4YIt;Gu>z5Hse9)tR6ItH^}lX&vd7S8;u7cwR(_fkmX&T>0S%B8V^Ek^&rt8%ey?C zx4lgrddq_lTs=rM$o`luZ%1w~C?uB$p}BgHXpsFr3v%lAfQNHoZPowY-{Gef@}GUwF5@YRzfcXsF}<(wWE#Cnowko_b}a;JxW zQqK8-S*$0C2HB4i#%^>D#_5ts21|_H=cP;m#uO8f5)f*vWCZz152dw-!bqyL!Yl zY>>siPq(Rh5#gS~2n1J;U=6a^_vv<1FCyGb7=hI45v)NL`#vMLG1-bjWc3KvAiFv& z+Q@B87Jv( zIfb7$!&J{;4YJtu>9%)2Bf7sCqk0Bwkj17?x4-)t(GAW3)iYRw>^m@5ZiDwTqC1?? zsb{bT+1DV$?eKm^bc-`I^$gY^`yynxE#A+F?s3MYp1~SqpC&Bb*c>cjX@yw2&r3Z5 zEHefnmimy1VtHTj{^A402a69CA1*#pe6;vj@$upl#V3nT6`w9XQ+&4gtlzQG2H6p4 zb7EMo=df(6SW<&*+K|)jXYHS$!_9;dh@~FE8f4RkoNhmBKO)>q7=c*o5v)NrZOG~N zv-Tsxt%MPXr5@46k{V>whMaCcYd<2~Nf?1x>Jh9#Hf_l1_OtdQ!i|Ixh@~FE8f4Rk zoNhmBKO(#)#R$Ywk6;b5X+uu8pS2$mUX5Y|VyQ>42HCVBr`ylkj|i_rF#@sFBUpoM z2ew`eON>A)^$6A=Tk|K*c!Ml%Z-%9w!5U=Kew=PQE1jI9`&J2&Po~4 z4bHICGgyOc+K42HBLE zXoD<^KrHnL)*zcQ6K#-X5s0N8(Z!M)WK(9M4YDi(vD712gKWx7v_Y0dAeMRrYmiNu zi8jcx2*gs4U=6Y5yKKA5KBFRHOPL* zpE%G_0L6&9Y?{L;2`w09z zqF0viGiO-pKM&R*dmm&(vBZr0J48<#dIZCcu_w0UWZ(w3#IN?Vto{VT0^~!q6%jmcBt2 z`#vKLvMd5NQ_@MLMX&~0?E8!~$g&97OBoTYK^FTyBMq`F0=7~{gu^nKsN`#(q%8~k zJ|hjXECR61h+qw}*!LM}kYy3DkuoA!gDm!aMjB*U1YnsF!5UFp}#vOEPO%Sho3 zvLD41cj4E&_Y?H#@D#u-BZW7}wy-AaV z3~!Kq4rAO2pdS-I1F$bn^%&kD`vhGKy20^_L0AOIVA+%7J}<2aE(S9O;l-dnWTF>? z2bB&k9a1{9bXe)|(h;R2OGlNCE*(=kwsc(S_|gfb6H6Dde!Fysg}SDVNMVC)0^g@X zURi@I@A8B_768kGaF4C!gbjj3gDmgzOm|th$#@VVs|Se&S>END?z3>4@gQ_o51Pgs zWO)X+}~`DMq%ZdU3^qCu9oc)D{#KPl(rzzEipM1$-{Su?3SIrNiq z&JIjrJxMgkwpfxoJM@!sP7e%XJxMgkR#=idJ@k`u&JWCDJxMgku1FZW(K#5WOClL8 zF?OGqU<4Rv3_^_cArr;;Fm-urE^Q?mCi3+P`a>mQRz_n zdMMr?I|^-1>^A0N=i{m&#Lys%eV=Zp^_nunjfN3OupYr0WU=qlZLwZNxWh04@zo<( zgDm!ay1mtl2)7nSAiH{m`)0P+ahrTIi+!JNQ}rUkJ%tent{%Y}WU=ql?WSHtxS22l zsnsJ`gDm!aMjB+Aj=|YmhBMMC3Lm zi$GHK2-YCGJbe?G(;$l(3{yRWHOOMqr`z8BhRo>xW{m0?tU(r=KHdKAXGAwR160po z4YE(eT)7S2&xr1DMyH;^8e|`Z47bDk8PP4y(9|pvBq0Nb5xt_!F(<+wKAe%PiL>pvT1Y)U2um;(*At%}(%OVg$g&8;QjcH_vi`1h^4QuKmiXgFEcFQ1Ae%PiL>pw; zQ6QFj1Z$8@8*-uzvMd6z)FW7fY}$|$ZIERVh@~FE8e~7@vFtwZwf~Dtcm;|-3&c{7 zU=6a<{E0K(Ad82=u+%eHgKXN56K{}Z8TtF0HOQv@IPnHqmXW`~S%Ylaj}vc@Wf}Q9 zoHfX%{W$RkS(cH%#aV;w9q==cVhQVtVX6PjS%d6NgryssgC)d-Sh~+kJpwE<1|gRE zkcnb>Yw5Pq?WH?Pcb4ud-Ceq;bZ_at(*30eN)MJEDm`3!r1V+8W1|hSqtNEWuw3G> z{H%&4HOQvSL>pvT1a2lhf;Gsd%tRYxSp@DSJ%TmJrp!beWLX4mB|V~xB{j&V%tRYx zSp@DRJ%TmJrp!beWLX4asYkE|*_4@RgDi_cEcFQ1Ae%B1ZIERVh@~FE8f2%zzKC5} z;=VvE^$6A=`z}Ppt}HPEvD712gY4`6#2Igp#hGGQ>KUv-Hbo}hAj>lH_cv>hO_7N= z$g+(54bB>5Q)J=|vMeKihqDIRo8adWy|RR#IlHpde;%ws_8Q2DVu=~~dz>}MUPf5D ze@_mU5EEkQJ}>nMu*?{QSn5M2isfUa$4gI?o-938db;#X>DkhArRPg8lwK^oRC>Ae zO6k?o^0Z^)4YD(5(7Q?8IM(JgUKpC8Vc9Jx`#vKLvMd5NQ_@MLMX&~0?E8!~$g&97 zOBoTYK^FTyBMq`F0=7~{gu^nKsN`#($`;0WmvIxL3BZ4)^V&7+^L6$|pM#_j_ z4YJtx8EKGZ5rAbz1Z$A}4lLR^NrPVR%jDn*vMd6y%!ptOvP&Q$(jdzs0LzRB)*!ns zL_`{7Sp;C25y2W{zd|R@oCaCUKrAydSc5D!ea0GOSw{Z;W(~5~^cicAWf}P!oHfX< z3Ud`}kYyS9JDfGhejGAl4YDjFe~YsQS^sQ`oCaBzk-x`TgKT~A@2Ej`Jf}exVv-Yi zo*c#3O0SpRD7{&FtMqp1ozlCd_e$@VHY{&c-nhI;dDHS{-J0pcR$g+0N^f$ra76VU##hsDD8)R9#XQV-vr+{G@DZD|p zg)2GIAj?yLv5XYnAX~wdNP{d-0m(8_c!TVUm=bA_FoPS5JSKnl^9EVg>*;oXKPJBY+08}$B*PnIpTJ3T+rJ+Z-~a6X zq8`H=WFNv9xBvSw@e=^M5Y%IMgX}#R<4yqmnD`lheQ~PC@CMo2=wi?fj$aJIB1i_y zo*egiX-#l3m@x=12K6Bmy%^l0yk&W-^48^T%G;K=D{o)kp}b>xr}EC_UCO(bcPsB+ z?y!ElbcY39a5K|Jq_9CYfp2!mD{GMDU7oPV0$_O%?y9chpiL1?ZXBpPJrv7ktUtO!DO^&rt8JCg-P8e~Nf%Bu&7 z2HDTCcF0(REKg$i>PezOmbZAiQ$xS;GUS)7JJ#8wCy54G-s0)b4gI8?lLI4IPZABX zE3(;hCx?Dg&e?$}tS5;E*&&wX&JO*goYMn?SWglSvdgd}cY5e2<(waw#d?xxkbRpl zcB6AJPM1V7SYqrxFTn^f&KQIk>q91r@t)aoEt(64YJtx>2_N0d$e$)VFVJaN3aH2?E7?E ztQQgPFpNNa^$6A=i+!JNZ}lR=t%VWDt{&mOne`2_*!Sr+RWBmkQy78Z>Jh9#7W+Qk zZt6vZn+YS3T0Md_$YS4Tq(PRgC`49|U=6bVc0w|Bkp@{7fxPMwtU-1;*cXx8m@EQe z)gxGgEN;EXZA=z{r0Nl@LG}&$CNQT#7Bd*8dIoEd#imcUz55NB(f!RB)iYRwEH-_* z{oT)qZg2*up1~Sq?}WK>8@!(p-QkQ*J%csK-V7OThxaq0Tb!Y(XRrp@YazpJ@qR{h zk25ay4AvlfIbrF>=3oh@k`PPxd8tQ$WyT=HQXeu=ERQN5T|TCKZ27qI@#PcBCzekt zpIknrd}{f$^6BL>%4e1j^e2UAgX~Obb7EMo=dk>|iX}D3rVTmK23Zz?Sn3h1K{jp3 zi8jcx2*gs4U=6ZqLr%0omPH_zdPEmXYLHDEa-t2gECR9ABUpoM+K>}%kYy2wr5?c= zWYdP6XoD<^KrHnL)*zcU_+jAj={UOFe=$$i5C+FNP&r8dIVTz3_>jR zArr;&?D9F~bIa$I&o5t4zOZ~z`Qq{=WOKOl!nTa;Y zvIyKsdIW2bO__-{$g&8;QjcH_vMDps23Zz?Sn3h1K{jP3+91m!5KBFRHORgM`yzH_ ziTeVv)FW7f>@yG%!xAG9OFe=$$Uf#zobd)(oGFH-p1~SqQ)J=|vMeKif3pVJ6q$H~ zEX&B>;H*J5MJC=L%QEtJIBSr-0Dd0PD@*v9vnxye=fN6e&w`97mY9*h$615yDTJl_ z_vBy+F(H=j^HPrh%Zx#Yr9Nb$SYA`UwtQXr`tl9s8_PG9Z!X_bzO{T?`S$W19++zCjlIJ|hjXECM!D(xj(Fum)M|`;0WmvIy8q84;{O z7W+OU4YDi(wo*of!_qg%V&7+^L6$`TmKhPOK^FTyBMq`F0ya`c1Z$ARzRyU5EQ{npXMjB*U1YnsF!5U=eLqw!OmPG)T84;{O_6raZX^>?RfMrGmYml8yC(fJ( zS3M}l5lxeI%mbH7PzXt|47zuvu{;4uO`1u)A<;SI7&u{$zt-wPXLSqyrX5yKl~S+A$t z{QV}(;Km}4$>06FL6-G;y4~N8iEn>)b5TFZ@CMo2aMIlN@5jXVKfAxE$M6Q(8!*Q0 z|9(vT1i&r?^%&kDdlkmG6F@&Eeg==%jH+fua=jVUn{>}exv+m`K|KX<#)=Pv3|RBhXoC? zV`(E&*dUw0w|2-YYmnt#p0LLPV0jSkv9+AAL6B&W01w|TUMG&&92Z;vRkFg*JZ|{5EF5P7VFW%aC7oOsum=?8;vD=u7osVA$A%+H7?E7>(t=E(pZZwQQg7pa2Ad7vUZj1FI!X1VY zh_4>O8f3BW)9tNZM7Xsu0@>9g+&8nnK^FTy-KOeAgnJ4j5L`WiHOOM$r`t`vh;TDu z1X8OJh9#_6_<@Gu|M}B9K=-f;Gs#3=xsrm@EQe)gxGg?6VLN zxsAypkW@W_HOM|r-vs6~$YKV=RL@`yve@+Lws*fFGrGSSqk0Bwkj17?x4-)t(GAW3 z)iYRw?By_5ZiDwTqC1??sb{bT*$W}V?eKm^bc-`I^$gY^dp2aaE#A+F?s3MYp1~Sq zPbDnf*c>e3R1#w8J}>nMu*?{QSn5M2iscTK9VTp2PBAR4l1MHf_j>HpsFF#8Qu74YFxNPP9RmMIe@X z1Z$8@8*-uzvMd6z)FZlBQiE*TkP~f?Wf6#_9>E%9(}tXAgDi_cEcFQ1Ae%PiL>pvT z1Y)U2um;(*At%}(%OVgminU1Z$9ez@Iqd z4YGI`3`;$OHOQv@IPnHqmXW`|S%Ylaj}vc@Wf}P!oHfX%{W$RkS(cH%!&!rD+K&@& zkYyS9Tbwn>o&rDfD3-9U7?%3aoHfWEM_9VCIaoqWh^70y)FZ$$V-RAg51A;I2UZTM z99%i1a%knS%HfqGDo0k1svKQ8rgCiMxXSUB6Dkk-9UEWOKOl!nTa;YvIyKsdIW2b zO__-{$g&8;QjcH_vMDps23Zz?Sn3h1K{jP3+91m!5KBFRHOM{y`yzH_iTeVv)FW7f z>|GEM!xAG9OFe=$$ll^lobd)(oGFH-p1~SqQ)J=|vMeKif3pVJ6q$H~EX&B>;H*J5 zMJC=L%QEtJIBSqS4t^fdD@*v9vnxye=fN6ekARFQmY9*h$615yL4>9I_vBy+F(H=j z^HPrh%Zx#Yr9Nb$Se{flxpGS7)XHg<(<^6G&a9kOIlFRB<=o17mGdhXR4%NXPdhf= zAUi9&LG~+!p+y>&zCrd|5D{sRWf8EMk|sSZf;Gsl2N975Sr!3%DITe8gh z!2;nyxI)%)DuH#@y+doljm=pTFj?W6aG#eG7OaVkLAWOLA(LAZ*H><++*tX8 zpUvnu$Ft!2pRI}Y+?x1~x+dtG<7FTswk9wF*MuIyzBzsyB4TR-BXCXV5$v1erL-p8 z*qk*1G2xnUpO+IBtci?4xF+-=lUoxvS8l1?TKSQm&FB{-v*6cUwkDRiHSs-lP0$x4 zOCch*CNKimgdV}ZAb9~IVrv2;a82kD>5CVw?Jj@1%`O|PGPe5avN>}8+Vl&k8=4?F9sYrf7cE$? z@ajKJU&H-2L;p(-beW-#_W!R>3@tlt#c9j^wP^TM{*d00KgfT#n&yAEn)bnErupD$ z$?sOneR##`DOCC$AnCBI&+{I}xbhm(KU2Nrez;nAOPdfeT?;wN78ixwn5-Z!)#@5WAMT5>AFhv8f4FBXTyYt%^e+l2dBl5=g z{I%(@-QeV?hjRaU%Pcc(rT$T`o-FERhNk&BSZ?}?(?0Oma(;>25xqHh|4Z!RfiG|$ z>*pZ-hkb7PiYq0{edQI0ipg>>{cZQf4D`~BUj-wxV#~mdrNtioarLj4;$w^l z{31VKzS38|us6}+)zY%}R_?3()56!2|9{>6;pv+0RMubX>Op$Q-B?=dEA-a7`%mi? z-qKe4mwNwz%Lb?xC-j9Q$W``&|DC zvxE0P zW5%qR^Vjy(7l|{5i;xM9!D%1tubkc)qyK*->!^3e=%NV!N~HvBAU&ji#wcW-F;-me zLn}^SKK-YBZu*BAiSzpB2v^?k9(@JT@h?ioigSeikK^Zvj4{STe2*U@UpdRX-3U@nZ^U$3jJ`OSv{fq>uCG7k%R!ezs?e@5Iu{NJiz(_6I(&T(?*<+q+Zob=FP3 zS?>KPlatMQc(Q@w>#Unw{DU7{E-|3{TC!XEOMRVnzv)(DZ>h^aph&B`VY%f$^r7j! za>+mbfra1eZl!hB#g(4D65Y7mfE89q0$jZ$;FN{m?k@C&-TJ+MfAITTdH~6=-0~}} zv|P7ZQhnF{KYx6DoyE!Y^f#*PSxn2jak=$ZUU_=2UJ`Kq;#ZS@{s)o^qvWg+y~0RC zx`XM28eix9Tk39zvgfS(Wy{YoHuyR94>$MrZFo*y{?W=~mB%YjRGzFnRe8GdOy$|i zbCoq0E=|VQr}r;8`d5_7uVD*jjP_qo=!PbT-Mymh|Aw*lVmEKgij!^kk~016Ap9*X z^J8u%a!OD7x3K@$U$OJMm(uBeULSsWNDn$0l`JUsZyJ)vJ3ZOZ-D=5#I%n}y$-E9N z>K$VAcf2&DH=33d3zJ#N-1e?o^G4aH^1aBa`ceXo`(L=KmVKe}V&!Kxsp&fj2RhrH zBZZ;m#NuI6pJ0?41NaF>OJGvpVUn5xq|{n@kor-x)D)mfJyMXfG;yib8vM+o4Vhx8 zwJF2r9RpwHPx3= zYvn=eZH!V=`9Nx|K1zLADz*E{`ZL+r&I@Kxh?6?`-kRM{cK=D+PVBqDtU=cOGN{xq zS6->ST3K3ot@3*1jmn#qw<>Q}4zx>6cStj&9w~f4oNP@}s~;1*Xk#WV_4iCt(?JJP zCo4)GFG_tfNbOcs+Tur>jq)aoevR1PThyOsAUvu#q-_pE``qlKXl zip9gEKHMlZ25_mh1Sa+MCaEbvO0AU#sqZmMO#!OZqXjuj6PH@8!OuL}kSUh>&nBs9 zGNjbnY=hLBQt_zNzPONDD-Kd$WRsez2U2V0QR?fAQl|kzYApbzKFB6D)t6Fhqw~-K@HK zb&Kkj)vc;a?NZaX`x#P?7M2$$Ta(o4#{@6hm`O`L-y}61bRc!IqU7eQYYV zd$d7RY6@{uCx3(@rPkJYAhkNkx?cvBdi&}Q)g7xlRd=rLQr)$>TXpy99@VefrCuxk z?f1;WO5$W|l3M+k;6)oVX{rCwBsCp$Aa$~$lll;w)GUBYttBw2udzt&1Ekbid64=}tJFR~ zm3pioXKCV6t2OwUM;kK5QvaARjY;h%LrSg9Hb}h@6^}`s78g=$#X;)xO;Y>nfz(=g zl=^C$)DR$~)&fxK{Y_H)`ci7GJV^aFo7BF1AhlK>r9LZ_+Wi@4OllwEq#g^U*4B9- zwK~YUUj~(W-|BwV{i_F553C+kJ-B*E_0Z~J)r-wikL28^9xIf^$<`#b`Z2+aHfGXN zk6NVm2OUVAtSEWBDD~kWwOdg!seMRSYQLmFYHb2Ssnt>TsT@%1BdSMMPqazx?;FW$ z>RE-Ms#rWs>b;FpV*r<0OJGu8Y?7J+q|{n@kopF*)D)mfJ*yyRY2s3=HTaoF8#2XG zFCt8%QqyEeskPY#ssBjDqf-0gLTarzNPU`3YN{Sct(8ZqFEUD<1_-IO0F-(+o77Za zO0AU#sef;jn#u=KYxPm;6H}?(!w{lUQ;3r~c_4zkrq78Q*@-D%8cv)+Dw1F~N&AX3|oB)Fd?>bRc!IqU7j~0jkuq3v!kwF11>NpLw()Q!Mot3Dc<5G#OHAZMH$` z|3}56Qv2dUYOOd(eXLDtsvbzKl}D-1G)kQY2&uIIlzLm6)Kp(et(6C<|H~*fl@FxW z>Z8<0q*A*FQb(nx5GQr=>@X>{w$1~o)j`(%GN{yNR?n)QT|K9IZuPwC`PB=m7gjH- zZfKX9?xto)J-g5rCtH)$>c<2x+L%d8J>4WV9dsadvZCbiqSV`g)NVyZrKXUs)P6~U z)Y=4uQmdovQ#qj2msBsUe%U6qzi%X^o>Lea7K?{Ty^&FB4B%302~6svOj1*Tlv*nf zQlD;?ngUd*=M>~DOb2GDs@GRe0;m)N>0%tBA$Jq~6{pH4ETUYY9y1(=Af_04cRr9;Cj+Dzy(#rJh@mvovw3 z)f)WFqYas2sXs-S#-#R>A*I%48>Idf6^}`s78g=$#X;($Oj7&mfz(=gl=?KA)DR$~ z)&fxKtxQt;`ci7GJV^aZo7BF1AhlK>r9L#3+C9WNCbbW7QYTNcmQri$Jdj!)WZf@= zN_}hfw(9NGJF0h9@2cKiy{CF_^}Y#ol#S-xr=DB*xH#FGq*gyBc+tj8TI!`1sr^9* zQYR})9xqD06G-h=R7`3g(v{jTDUe#5fKY06lzl1(l=^|{gVncfQv3Tx@|t>HVdxWL z@i3`3GfIsCTxuPxA$@*wq( zj8aqiKx(Z%O1)1iwR;ytRB8%wQYSBjkWy>wJdj!)WZf@=O8s#4k?Nz>$EuH4pQt`r zeX9C&^_l9i=4F zsHoHw(v{jTDUe#5fKY06lzl1(l=`{q^HpkCjX$Go)ZaJiN!>rdWE+hn4=Gz!tR6=7 zV*gf+=tIg_f}=Vof?55){RNRIoczEto>Jx$dRFJu2duYTxU%grWj+D0W-)T2tXk(4 zftAwxk%U20?Db~-8BZkkGafvt%+E*9Yjzajq5-f+sCpD^zb3n2=Trx=f9*w$J*&+B z=KAMKm~RQnf;-%Ji*$U&T(L2^#A{s-M1O>VQaaKZDFY}U3| z#=La~rTfL|OVyXFuT)>HF0H;+eZBfd_08%(FMK08ddox0M(Oq{(!FBu`Hk+;T*>5p zTAY2e?auw2n~c0clh*sI{k5C8>`xu;IfU%FW&XH(dh>tOkUV7M`)iAzPv-W6U68v= z>vNGO?D&}ea9UeDPsSxP+N2|xKicXVE9LkhEx5} za4i50|27z&_u#2fis_0kA3WuB))stdxH`(bbp|#3z3Thb4Qm_KHm+?_+qAY>ZS&d| zwe9VO(~Z|G!$%6Mi?grIaP@PN9Bt5~4gb8!a60bL@MLMpLq@~bM#J6GiW*KaJ;VLl zLY%cpPz+axO<+O?G<>Vt*0r5YhR+oDw&8c+Sb#42KjFR~fV5`^Je1T*}P7Q=l) zV7OKv4ByOZxKGdxA1%m<8o+S1h&T~xW2V^fUz4)2>u^6Gf#KSWgW;=F_1JZIT3s5h zRR_cW(`2|W9~!RJN5lVMGaM46;aUP3{;wv(eL!HiRv!%itj%y=KQvqmK*N6uhUYz! z%ExpKmye`!hHDExG+Z5J-a3OCzHM#0+V-^_YCG0;s_k6crM7Erx7sph!)IzYyHS|Y z!l*d=+6-4eC&|$UP1^7;S`7Ec9U7i2EqTaj_+m8NEv=a0KBi~5Ut75|9A1ZObJhKp zC$Cn2LI*T_kJ_HKKiCZSccFso@Z_m9V`3FC!@q1a9211$S_Ctk9xEUHE`25?1cqz% z!SKJB4W|U%@RYFhTpKiL!#`~@oQ^v*JXu=ukkRmeLBrkBiW*KaJ;VLlLU*-EP_Dz(VH23p z0S!N_c6e=Vo8kVJRA6}WyqdXU6*0sA*=RT>2*b4qX82G0=lrR|Y{ZH80%&~U9j z8vY+f!_x$5xR!v1&$Ag$0fFIKeK5RjG@R;(hHC+6_!2NY?=e<0DW+?PSgN~t3||#NE{f;3!9K*LwF8BPI# z;aYt#e0ihcR6jIa3qZri!SK8XT+O7IuHo_lSI%&4!H0&cqs&`pP{U8Jol!fpc2@1| z+BvmzYv+I^r^~;0iG7`;vFvzc5iR`3o>85Z+E;r(!IC;-5~nzYzXMm9S=acsR0{4dCSNW%8~8PqL| zQOb4_Z{$oultI@0GAP-X)-J1EUb~`pW$mik)wOGC*VeA99cumyvN7%Ucfa{4X+uvA zX}&nwW{aKoF*g%AV#nHSUy%6_ zr**odSeVR8=9b-%$@~e}r*c54Z>Zf^yW1u;-QSXLYYteQ-G9OD-Tj1V3wK!RH;V_a+W48wOWIpd9)!@EcNAtY3w?Cj3z@$t<5$_{S_)6 zmD(2dkCYQ}sY=GrZ_TWhz~Zm-=@yR&vz?e5w= zwP|*#=`Ji@T!SVfg|)@W)+Dw1F~N&AX3|pAQ}p9f(?JJPCo4)GFG~GiAa&lKFpN=1 zS8Bhc^5!;>TAL>PGeoDkHl{z714?~g?fx1)R4V>=Vq^aHQtx~5bUP#+e_s)che`b- zqtqC{rPdOd)LWUPrT{6mRvx6@-7GZ)s8Wv>kL+a7Ozlf8qNow_DLTYWyq@|{ZaKxpigASxlR+Kzml=}N1 zb>1H;j8RBeYQLmFYHb3-Yif0reJTf(`kC6Zwg0hQQ~R4pQtG6yZ=qN`OzN*2rN#g* zwU)r7{*y^+3XoE3b(flsMItWQfh6sLF#{` z;!&x6aUr!<9Hjo0O=_whNUfDessCt{It>s~YXKYt@jyAI#j^V7yC#C`ki`+HMiwRIj`Q>%ll`(;q6pRc`8d$IOX?d94lwO4CPYp>N_ zubpj|n(nA(NIkQ#t~lA6q*gyBc+tj8TI!#hzWt_y4x~<2lssOPdI?CK_vZ*>6w;O2 zFDZ~(n}ASib(DQ72bB8F+FP|XOj6Ivyic8U?=2FGhe`c!HmO+vms(3;Qg3dN+6PFf zweleKE>@|1fGYJ^LC(^|rB-Y3Gmkc8ilyF{FpWv=CqqiD%{EB=1u7nsIxQ}w){2AF ze=pXbo$W)M z)V_;1m0DZpfz;|C>wXzj>UV1I*50eVU)!+0QGMh3CiPA0o7Gn{OFb*+KJ{2(J#n%% zNv(cN@S=^GwAA#7rsy@bKj=W}WJSs2MX7%TQs@2Afe-0Q?UxittxZ5EwK~c^l> zMSaWq-`k|7n^VDk>ZC_+iC8>L>TejO#sDt0mcXR`KaRAOj zOB0t`t-;Sc+K?%hn(j3u2Ky$F;2Ed0XfmYK+H8Z=Gfh(a;zDYzI7t29HmRw4AhlK= zrT&Xi>NG$|tp%Xei)>O;eJQn89;6;IN=@YhskQnj^?#;PyKddsHFdgv5~+Q!ZYs65 z&I75{LDu~;sMK56x2bPi->$xWeTVvv^_}WF*LSIJYL}Ysre<7I&nkRVoNP@}s~;1* zXk#WV^|vh7)U)WI1F4f0C65=S{uW4`_ooFuq${;wQXsW90io3DDEm|nDD`gj-Rm#g zq^6rwfz-+CO}`};50iSKQECj}QfmoJ>ff5ArT{6mRvx6@$SgGls8Y`^$XS}W)M^cW z=Fx^svDCjOOruiMWJsyC*#@aUO~s?v)V{coS}P7x|I8*eRS%@r%A?d97^O}Fgw$F9 zO8sS<)Kp(et(6C}x>EZk1yXAh5K66%vQOoJQXf)3w0^ctYJcBI-ltApZ~8s4 zc$m~*FiMR9TxuhL+H8Z=Z7Lp>+7}m6YsEq8^=(p9^+0N^JWBmzqtt1DkXj2sspr_FrutH9tvpEG zG)hh71F5z8DD`@&)OqjDo<$)}YX73+RBCOV2U4qptovn9sSmFoQ9rVNRQ>4sG4*5X z$JLLopHTlNyVP_yHACt-g?|$#Ta(o4#{@6hm`O|h8I#m>(1Fy+ijv2RQhy1g&U<(E zEDGsL?UxittxZ5EwK~c^l>)51b0bFV=fl2*8 z7O8!Jlv*nfQvcN|wGU9Go?DQ!G;yib8vM+o4Vhx8e?XYVr1p~`rPgK}r2Ypg9+NsP zE~M6qgVaAUN$sl#QfuW=>i@P$4FN)GEdZq+H%aa5OR2T;AoVA0Qv33O)LMO%`Uk1h zdGF5lAx>)lqT^I*ZJh^FtAnijWl*V4t)Esuy?#dh%=%gNv+L*7&#j+VKhZ4p?40}5 za|{12PPQhg)sG2Yv@w&GnjW2$80>GA1@H9o2OUVAtSEWBDD^^+I`7@tKBOzPUs52o zHUXj3>L~kE4k+~n^$Y92wnR6L@XXA^%_R0F@Q_0B`~RfZjzb;q|{n@ zkotFKsVP8}dR{@!(!`}!Yw$CVHe`yWUPzcmrKZV{QfspfQh$VsN2T_~h16Pckovne zsi}G(wN@Ub{+UtgG(bqL1)$XbWRsfeOR2T;AoZ|OYAPQ{t<^`VznMy%_wMZ36yl`z zFFH=8*4B9-wK~YUUj~)>;`$}^OY4`_FRx!wzp{Q+{p$KP^_A^X(=FSKYwCH0pNf;M zNow_Df){Pfq^0gyuBm6!K?hPND@qkLZw zjrE)AH`i~e-&((|etZ3n`knQ=>Ia#hGdi1YuOi*)Q!w4+{ZgELv+d6PoI8)?4Vtvx zn_HeU>W{mpH~&Ws$wNlImrtKF+FM$&=ZyN8uHWg};(0PInc?2w?&l7hz=RHH_&xP| z>vQ`jv>e0z9i_nVR7(nPS5aC1s`T-Eg|`nq~M%;n(8qYcpK^oFqpZG-<;(Fd0tA z9U7i2EqTaj_%djC-n+ABQ%uirzqSx(Z4wm2)nOBu&;bp9s{V9+$Yl5&ac>)b2TqF~dJ>Gn^#|!?g%z_)Lr8J|Qq%s}F{+VKv+*=!TCLkJ~UjbkA{!h42J}1xR!v1f52q84+sp` z>Vx4=*bMjeL&LQIH2h;=c-|wad`#DH`A8~fxVGR!!_`sdtuv_M&(@!-KVN^L{$l;5 z`pflK>aW(9CbucyC=?3y=?>=PONiCJJO3BI-C&hjtFJ!e`>U+C{wk}kvC51;j?I`c zYvzJE+RbhhX0-4darU(tu6|CEqYaw0;lH;S?vFb(JXu=ukkRm!(D1x>XZx6*;eKu9 z&Tx1guFaKrceY!o@}K_Uq5gypX!z^(H|o#Y4EJ}Tg6r_)sWiV8tB4uCtkG~x5Qb|J z%wT&oU-|DDZnDjyoI)kniuGa8;INW--RG@Rahl;E5gkoD$|ITR2WuGI&_?>8Dw z^+Ut805rS_hUY!3${$A8aQUz*XSlZDL&Mck=B+cR;cwO7uD?@%xBg!J{rZNDjT##_ zHfdaCH=OPWXI+QSEc{-aeQk!TpOc1bgC=eGk4=WtafgN{OG_Ry8a^EjcS|ewUHTk~ z=^5_V78N13w7o8ju`BstokNgKY7$#6RE(C}nw$wNlNm!jc$@6Mh>F+Icm+Csy%Nl*+|hfQEY z2Q++_#;%QxY=-+=Qi0*glWhJXRuMD&DWl<-APmV7OXDoQSkBQ*8LpNZF|2G#`QC+KhwYS5Wn+;l8>wT&oU-FK08H%7=z)_0jO6 z(eN}u8m=Xv;g8x3r+~n4tv(ojnbB~n9~!O&pyBU>;du|ZnnN*N!{r06oZ;Gn4-HpG znYYfMhVS0kqp@dWug2bueH!~V_G|3lIH2)oyWw=hHtRZkR^hMW>}xYz{hTC68#HOd zXPXSC;|>i^mXbvVWJ4EJjb4c8_?FZl{soy20KhRt&XU#d zoEmPG#D`3=-evkDubAF`GJ1OBKQLS_fcFYiJcf5#yo-0dIM}_8=`YB9^}gNl@<{hL z{O<N5l44;pE1BEgn#vnxpUMHHKA~}9He1dTki!)FW{zP z@i3`BX_OiRxYSw#llrSBsVP88t(6CNpLw()Q!MrSglSZ2 znhYtmHrpWeG%6mI+7}m6YsEoodQpxeI5}_h?iJ6Iy+U)TdLXq{9;IGrlsXL%QfmPy z^(r>0slJq2D-TjHW0ac82U2VGQR;t6rOtbIw*MhGseMmyDz&!G`)AdhLDu~;sMIGn zPHCLlIIVGdLe3Q(mUEy!7#xYTM5e&*4J zOtI9@5~fk9X)>hL+H8Z=Z&C56)V{coS}P7x&#_%oQ}sYfqxN$op-@vNh4CwWb+Z3h1C>;>A8-hLTW z>I)keH7;&k(zvv7S>y7?6^$z!S2ZrPOHKD$Go&6ZY%NZ)F-bedC74jg6ZcH#cr+ z+}gOUaeL#A#^2ecraP(`QqL@GFHW{5snw4OUbHcjmii!*)O65+)X9pH$BR<03{vO) zIl^2D=}PUF6iBU2Kq$33%086?N_|)3?#3x5spnua8S^|@L zO^eh%KuWEZ2dUS!O6>zwsmBU(mL@K>T7#c?v>{V0^=*V{Olm(FQfh6sLF(73cueZF zxR6>a4pNVqr1sSVskQPb^%^#*AwWp21)$VblhnSxlv*nfQZKbh?aK#JYxPm;e@vy$ zdv~@EaZ>v(-c)LBod;5@gRJ{yP^s^2+}F6j@j&Cj#zT#V8;>*|Z9LZ4*(~+Eocq*c zg`LI8)+Dw1F~N&AX3|pABbpL}v+q;;gASxlR+KzmlzJGX&ikVSAJUcDFDZ~(n}ASi zb(DQ72bB7W#*>XbZBoNpLw()Q!MqxglSZ2nhYtmHrpWe^He-4wJ$ED){2AFpRq|z)dQ)u z@+kEjqtt1DkXj2ssXuI!n(9lbwelb}J*UA5oSas(I?Coz`9Nx|K1%(mRBG3)8@s0V zAx>)FtD8!#t@A)?b&z$x3@Y{0jb|FqHlAxd-*}<%V&kR8%Z*nWFWIH0yQvx1)Uyh^ zi<7NMYV~7+7j4X>rQXSMO+AkeI*>Y9QSx|E>Iz7m_ooFuq${;wQXsW90io3DDEm|n zDD~3DYYlp#aQu0u^Zb1y`R#Y|dec3{;$cz`8KuSmF141xr2a>f)D$44*2;s_UocBe z0jkuq3v!kwF11>NpLw()Q!MofglSZ2nhYtmHrpWeV^lmUwJ$ED){2AFAGb+O)dQ)u z@+kG{Myb;PA+;8OQZH+hn(9lbweleKBgSiLDj!I#)kmrSE|og(-P!5+CXw2|=s1;H zTjzn)>LBZW8C2>w8gDkAqs|FsWZRN{s7|a+W48wOWIp zd9)!@EcI@LX;f;O3@NoX+aR_7YCS5oFD|6kii6Z;o77Z2kXkE`Qh&rKbs8X~)&fxK zmu*s0eJQn89;Cj-C^eN2q}J-A)GMY^=e;|79)-ATYX73+RBCOV2U4qptovn9sW)$K z(cH4RRdeg+HqC9D+cmdu?$F%dE;Zdv&5(LdVSjP5HA$_0Oz@(OnY7eDF-c7a9Y~$5 zD0#dn^;;ly-n+BsQAk&6zobBFZ3056)lv4T98l_=nmae&F-g5<=6&kq^`-}k#lxh2 z*CsU!;8JS|OzKZsr1k+)YOOp-J!+NO2dGldEy!7#xYTM5e&*4JOtI8ES)}%pA*I%4 z8>GI6ipQi*iwmi>;vjX?B(<*|NUfDesXt+p8UlpWS^!G@hDmB)UrMc&2dVF}N$txA zQfu{5>Pjkg-n+AXh?CmC=s1;HTjzn)>LBZW8C2?Bo4Yl4Z|>3Dv$6$PeMnbozobBF zZ3056)lv4T98l^5ng=%TwnuY_srntDx|3@NoX+aR@XERRa;vn_P zHmRw4AhlK=rS2G|P6LG0S^!G@f=z0wFQwMXgVZ+~rKa+M)LMO%dihl9ymx1(>nD-g zzvwuXT3hFV)aoGXei>BigPVsm4{aXSJiK{C^T_5=&7+&gH2>2sHQln!xTc<0I9!}; zO;W2L6TE0+CN1?>O;XcA2T~_1N**st{W?gU_wMX9DWog4Us52oHUXj3>L~kE4k-0; z&EuO#_4jA|KJ}V(bE+?O{{WM1Wgj98D$BM>YNB>_0#Ttd!o5Bn+BjuV3uXcp|Z%@!;Lrem;6$v!e(X z4S;d<&Zv*+`kk&Vo+smy8SeewT&oU-UuQF%%7=z)_0jOVjE1KP z(r_&S4L{CiI0XcTYxTkK?Tv<0{m^hN01dwq49|P;)S492HC#S;%E_xO_|R~5lzHn6 zYWVrh3z`=;FKS-gyrg+)^RnjU%`2MUup3S{Ub74zDI71(zBa?v&q;E$L6bK8Fq7eQ z+@ayg(vpXahM$Ip=e;|7O^WFm?$;LLtWAPqxH@bC6FQ*bS2eG0ZeTKezPPsyh9}RS zIZ>=4X7~j*!&!nbT#I0aKVdQ4Cj^FT^}+C0t%myq-SE+ZoTvc|SBr=fkv3+E4Zn+& zjT!FeBQRW>aWH&8sva{utu77Ms)ONon+*5mL<DX!zqc!y!Q$t|g%1XPXT70fFIK zeK33Qv5GhF?gBu5)GX~U1S819cdG(1^a@{rN+i_!4B zcW3*Up5cCN<<4+;9j?ulcz3p2sPdma*>`8((Y&+yEt}zVt1J92J$Wk4sbUo|!%sIF zjtRnWErJ<-zsYb)2n^TigW=DZ4W|U%@RM48BWGo>z0GSVhe6R|YlHp8iWXt-7%4ZqcBc$y#$*Amchx|T_BPR>%jcbbfh$(NeUr+~n4tv(pOmCdFu>n_>;}2nol>MX+GP0uK9fPh31RR zmzrDJ4bQtDK2|teoPBMEtDlqPXoDtg`2U&=r{fL{PnMQEWHkIJG(7L!+4Cu;XSiQm zXt*{Bis9<82~6mKhQHE$wfTb0aDPiGFg$sZ&ADO~F~j#W8jcCVa4muvewoQ|N(cVx4on+>M~-SAljIZ*=`t`-p|B5lkR8@?AQ8@&#v`3MZxW*iLvU#cE8+*g-|Yt_N< zGi`=b`Ot8!J{o?h(eN}u8m=Xv;d|Py!zmyzT&oX;|H)`L)ejBV0?_bN!0@~WT+OGL zuHo_lSI%&4!H0&cqs&`pP{UtqzTSMJ`DXL2=G)D8n(sE>Yrfxn&~7;0u+6#-pH(^g5hkdWQS8g@$XBpct+Wo4|w) zX!u60ja%oM{(@|QxF7ESmSa3=OTSPoB1ZVbw!a`_0gmu^0uy|B%U_WBfS%y-@&I_l z`WIwA0074nIZIZ*b85I%5+5?fded9g5|@(=(t90l(2?#Zqo+6i1H>>f6`v$sI2baG&4* z=R1&-pKR8XPJQ`4-0}M8_8a~$$da>0{7I)iBw>3ze0O&8d1X6^_k8Jttovn9vNvsQ z*4n(aMQh8}R;{gD+qAZAZP)s-`7g*8Xt%%n%}2?*9+N}5Se$IL#m@Vfn~9t;llHpO zU$KeA{$w#%eqH1by5}|fHx0?-MXn!9|AMT$qGIpP_90H|bV;!=nU&0KZ%yTmvQOoJ zQt!~(v2~VBYJcNNJU?wb=>@!0EFLEHT}G)ffJ?0jK3Q(mU zDacuxxYTM5e&*4JOtI7>glSZ2nhYtmHrpWe8B{zfwJ$ED){2AFuiB)h>Vec+d6c?f zlsXL%QfmPy^{qCkslJq2D-TkiW|W%B2U2VGQR){`sq@~Qy?{cT)V?P;{iQ%#=l!#4 z&LHc48C2?>Tf4M&ZSB_Dy|qVc&(>b8y<7XVF1AZecVY438k`s@TrN(wCaKkr30|}@ zla{(*l9~=WkUCjW@_13|dqL{FKVeuvAzi8clFFOgKx%E8@Xrw4?*ZDF{!|Vq^?t4W zTU*+srn^}3sVw73$KRD=@i3`xG)j#DTxu1L@ZK$Uv5AZKaf zQmZxinMWHk#ZrHSFpWx0lOd(nW*ekFo{C4M_Qi$NT5*v28JpBpJ&;-}k5a#GlsXL% zQfmPy^))uBslJq2D-Tj1Ym}PG2U2VGQR>H2sq@~Qy?{cT)V}jKMOa(sfz;|C>wXzj z>H}K`wGM6_(mJ$tSnKfC5v?OzN3}j?mzwUiW=K6+xLTZSO;W2L6H;qqCN1^jCaLM5 z1F4f0C65=Sz80j;`$L5V6w;O2FDZ~(n}G0|S{-Gd$^oT5rgdyiECw+a_ zip9gEzR)N&25_mh1Sa*9CaEbvO0AU#sh66irT|synFTpZ6PH@8!OuL}kSUgWIl?q5 zHBE+;TAOWU(TbQ}sY+IG?O;V3%-ltBw_ihx6he>^%O==dvrPdOd z)JrW=`v57mRvx5Y)+)6RP^BI#$XS}W)M^cW=Fx^svD8C^X-sNA8B%I(wn6G+sCZ23 zw78I3D-KdWX_DGk52V)0qtvh3q=oviYdvq4 zdOYVo^;qF%ak4c@t$s}KqK%of)bxm^#Nh1v)c&9Ysgo5Yj~AuB5v0!hqXQq(mD(>U zkXoC7P-=CQeJTf(`ij<-t>tV|`};=nnmXyxyHzY6CiSI8sWE^{ttBw2pEXHM0a9wM zJV^bfS!xPUrJhxgvovw3)f)WFqYas2sb3{bqf*mkNU62i2B{CG;!&x6aUr!<9Hf50 zCN)(Lq}Ix#)Xx~DP6LG0S^!FYflX?vFQwMXgVYDwuBpeVd?2+}AEmxKmD+Xd#;&P- zh?Cm)>ZVd_>pYNJ9c0}vgGzmM>zdZJt?OFXw{B?N*t)58bL*DYSM5^M-PDY0>RE-` z#mUwrwfZr^i#BG`QeR@ZrXHt*4x~<2lssOP`U;Rb?@tSSNLOmVq(EwI0z#?PQTC}E zQ0m)Sx3_MwN$u|&NvV_9o8BoF50m;FqtqC{rPdOd)Q^~?rT{6mRvx5&(JVCus8Y`^ z$XS}W)M^cW=Fx^svD6O{rctSBGNjbnY=hK$QSqqMzPONDD-KfMZj+j-2U2V0QR;_{ zQl|kzYApbzKHVlY)t6Fh6$P$0@`~?O$}9O0BK)Kx%c6 zb-xTM^_{J|T6eeZY2DkpuXTUxf!2eqhg!$lrKY>78B)(K+$~PFCaKkr30|}@la~4@ zlhkz3fz-*0lE;fup8-B?VGz6A((Rj7vQm>VHpE`NH>4ReNFsaY9NzDSd)LH_Q`az4-K0r#Xl?SPxvr6p)RH^3{lR7Rve_Jua6wT$qBRfG_ZN{Wa+C1 zQfuW=>IZC6Lx7N43qYyqVR8w<{@))y&CJ)AQfuWw>RoM8`|^R*T78uI`c&$?cW3($ zC$)dkaVoX8&I75{LDu~;sMN2vmbPANz217G^=9j>*4wRjTJKJvqin65`_yv_4~vtn zNow_Df){Pfq@|`uCnW|aE4KIWh2Zb0{Xqv(Co4)GFG_t5NS*iYY#-8<+Ak@PTAP4S zYIT%-DhHJM{nm!<>uplg&8gt8w364GJ}MRulllas)EK~}))JW1cbKH604cRr9;ANM zEHwqFQqL>MS(>=iY7Kto(S}U1)c#MNqf*mkNU62i2C26*N$raZskP!D_0^_p>b0nP zAhlK=rM}%Lbs8X~)&fxKqfOV;{s5%ZT6vIq8>7_p&kv;5>Z8<`rBdg;JKGIm0+jB-)f}=Vof?0i7e?cS) z`(NFHcW3*Ap4B<^0qc{k&l&XzfHjMe6J^ypuL!J^-j5^(6*1v7hnaNo9UM zdS0`m2p0{2{avaay|nggvI}-jbr5?`FKYDKn#%XZ&Z&=NA8LEfsGpv7*6os=lYnOb z(e#{AAJ8*9r#_(lZQFB3ef>V#IRU8lF8(>A?hF!tceamlY^U!xW@+Jq=O@{$ZGjK1 z$QskzI)l=^V|%Ce&h1^=yS8_0@7~^{y=Qx`_7Ba^8C{ERuOi*)Q!w4+JuS|@*>>lC z&Yef{22EP;mn_d2^~c@QoByMRe>JS$caGyK1dhGT*-T#I0a?`ATb5(2}u`e69MX2U5# zH+-ZZCu#u0)gr=hZOjxKzA`BrHJs)nFkG8)F#KPsdem@VT^g=c2gA3t8BXOx!?pTo z_^w97(*$X_mVk!S^OkeIA*X=AaIHQVzK+pwsvjDz1)$-ZfZ=%$o?44yx`xXKPdRzD z1s@u&jxukZK@H!(eL(xb_Cf7~+lRCdZ6DS?ynRIbOuON9cQ?!Mk;3!h>}xYz{hTC6 z8#HOd?>8Av#~m7;EG>D+X!w7l;d$@QUW;OShWoXJhHI0c7_JVRz=RHH_)+bn+mD+J zUt8SUhTnmcXV1JSRuMD&&o;wZf-qc*V1^%TG2ABvhHLe~@Dr?t`vl$a(Sn?)0Ss4* zh!c@EW{M3jld>_x{d@$5Ycmdpe~YTe3{R^|!?o&Q_--b{efiLEtv(ulkj-#NkcMjs zX!!3;*Wo@OFkGt-hJVv$xUU}?t_7gsJA&bPkEHT3UBl%gshr{3f)5Q>N13YFRM;kP0!ymF3?vFb( zJXu=ukkRn}L&Njlo$X_KhWoXZJHz31xHebf-PvxT%76M~-<^F%`^@$=HpA&wmwb2j zc=F!bp;yH!Vut^Z(Qr%ZH80%&~U9j8osB|@H9aht|g%1 zzp@!l0fFIKeK7p1M#HIoXt)-DhHn9e=RK^-Z``io@?llZaBabdhO48@TW3(i&u*X7 zKDT{d`~3C=?F-u%wJ&a8(%#l?xON*Hg_&7+O`LsghO3{GhHHZ+ZTR&j!|Av~!;_^Y z4;c;rEgJ5YR_wdr zv5J`CKQ|hV3BqtKf*HPJ|C}E;oDu@VwfbQAerCfdK{tG?ASY@7!_^|Jnu19Yg0_uaQPT3XSlZDL&Mck=B+cR;a9e=YG2*HrhRSu zy7u+$8`?LvZ)!hdH$3lt_*mgBarU(tu6|A$t__;B;isAmr{fL{PnMQEWHkIIXt-Ni zQNt;wXSiQmXt*{B%6IANunA1)fQH}FzP0`DHpBfbso;Ki@+6yg#42Kjf6Hh%CJ4i| z2xj<(Cc`NqFkGt-hHqy!oDy`yXBFf`4PdxhM4X7UF;i^#&7^G9aGH<6aBarH@Yz&7 zYPhd14cDrJ;TzZtr}ClUT75M9Z$`t@1ZlXIfQB!&8BPI#;aYt#e9UM#)ejBV0?_bZ zgW-7(xLTWHx`xXKTsgzF1s@u&jxukZK@GpXeMkGw_Fe6}+xN8ZZQs|vzx_aaf!%Pr zVViY7d{*H-arU(tu6|CEqYaw0;Rl%vr{fL{PnMQEWHkJ{Xt-NiQNt;wXSiQmXt*{B zis9<82~6mKhCkGPxIJR|3$pPU;(oaQTaLAow)Damr>~Jbb-@3R5q`4iFUWX+BRrnK z1i#zx7i4KbPw;qo0Q?E#Uy!8%063<|S+e?_Q^T#2_>d{qdq?^suZZ61Wc2jLe_*&= z0B>JBf;SZJ;vFvzc3)@t3$nC&-|l#Mr28)ayFu*T*%;8JJ05^?AJ_lYCLuXFH}(Ej zJ@{Miw0=+SczJ+(`~E-Qft-}jcz1SMz7Kc2KDvFS{|mC@tPy?EX&RESy;k_{?Bw&x zcIth-WyWf12yz4PJ z?q$WvHe2kxkGYx188d0Gf6!mCiNwiIT>o3|^q_lQvwzc&JYMAbwDd2?x+^O3?(8(g zX`L=97ACWjx$Ui~yixY498l^P+Ap@(v`J0(x8&b?ua)!yE+-Zbllmy5)EK~}))JW1 zH<_fS04cRr9;CkCEHwqFQjZkmEKOW$wFW=)XhWu0>i;uIO_L#|)@B=|-hzrprS`>z z)LLsj0q{S}PAyZ)TL5$_G+w^-<~zQmJ#^ zojpE-LY&mTCpbk|Tj%|=YR(|*ei>Bim)ozjUu`dKzt(=e{YLxE_FL_@+w<*G(_L7+ zxCSRi3Lg+BTa(o4#{@6hm`O{$&?Ge-bRc!IqU72^pu{yr!c50m;pqtqC{rPdOd)K{9M zrT{6mRvx6j%`7zqs8Wv>y`9Nx|K1zLhDs|4g zv&Uyph?ClP{^D6j*-rABTH6fWlWM$9Z@&yG^@g2|IvaO3>1^8Bth0G%i_VsvtvY+y zrKWqW8B&iHmKP^mlho?Rgw)!YNlQIyl9~=WkUCjW@_13|eL?D+KU5f>K_OkK{gMKy zwFwBXsnt>TsT@%1Z93a_=#>i5r?QOC@Hdg9)Jb383S#jvsdqF=jR9P0ErCgWrb%iF zkWy>qLF&uQQd58`^~{2trHM{8Pm)eNa; z7FH4`Ta(o4#{@6hm`O|hQIphk(1Fy+ijv2RQttv%=lnUs_zVi^O6`{vNUcpkD78Au zK9vJXy;o=N&S9o&>XFR*)JgYVQ7j%N^?o*~Spb(>OJGu8W|7(lNU62*Aoa~wseOPd z^;kj9(!`}!Yw$CVHe`yWUQC$Ar1p~`rPgK}r2bzj9+NsPE~M6qgVbl5r1sSVskQPb z^`$ncAwWp21)$V>nxyvirPNw^kor$HseSoCYOOv>eM%~|>*I|{?L*u(weR9hrPkJY zAhkNkx?cvBdf(1|o&7rpbPnts)H%3wNaxVbVV$3tr5?$-Pd!#Bi<7NMYV~7+7j4X> zrT(}@YJbpy)X9pH$BR-Q2vX<#(LwSj)2prWlmFP@$E$Ru_Dc$+)+Qj7S{-Gd$^oT5 zqH|Z{CBQ-CVJw~IQ}sYqe!f5GS?o)lH?=)_EYcI>@?T z29^5g&M}>1JI8g7@0`#%v2#-ARE-lIN6${RzD_q(Z)<#YI>Mr zVsLgx*$5qUAa$~$AQP^F$-kh3&#snr_%%%csN zVyQnzm`0_h$&gZOvkg-Jf{I6__Qi$NT5*v2aGTUrJ&;-}k5Zp(lsXL%QfmPyHNA@= zAvihjW%YiKP<<)2Rvx7OnNeygA4sj$N2w1=rOtVG_P9R=C$)dkaVoX8&I75{LDu~; zsMKe6&gz`qIj3`O=e*AOoeMe_b}s6C+%7fUP0f&ccA+g!wkE07j|pD1F_V^hsp*=U z4myxJSyA$MQR*!~>YR6HkB?ADS8BhcKx%CQLaEhJ_Ng3D>PtG8c0Oj4nr==7z2C{} zO^3zeVN(CEQECj}QfmoJ>O)LYQ-G9OD-TkiXqK7+RH^3_E7Z*}%#X;)bZBkS9Kx(Z#N`0_V>NG$|tp%XezqegeQ++A5 zRvx5Y-zYVe52V)WqtrX4Qs=xodwhgKoYekB$EnoXIuE2)2U+*api*DnxuSDr=c>-t zoohPRcCPDO-?^dlXS>vNH#I}*IfajildVZ=^<#n;ZOo*le%K^69dsadvZCbiqSSu{ zsdL_)Jw8GqU8((&0;#nL2&Gm>*{5g4sNtBA$Jq~6jdH4ETU zYY9y16D?Bv04cRr9;80cDzy(#rJh@mvovw3)f)WFqYas2sq2JkOlm(FQfh6sLF%7U z@tD+UaUr!<9Hc(PB(<*|NUfDesZX#;4FN)GEdZt7#3Z$^FQwMXgVaBituxbKadj?n9i^{zb>B)Y>`^q*e!6_sgJC-`csYb9?8G&YhjRI(K*O>D=47Zvq`< zqjWblL+ZJOkBgJ7Now_Df){Pfq@{k$BDFv0Kg$>T+-w*jeh-km+}L%LG?B?VGz z6A((Rjb-4J zQ}sYo)LMCv`nyJ{seB-{Rv)F_EtNXw-Pz-#6yl`z zFFH=8*4B9-wK~YUUj~)>;m#wSM>~&o9`8KSd9w3V=jqNfopsIE)T4CEHbd%pg-?l- ztx0P2V}ciL%%r8Jha4sbXWysx2OUVAtSEWBDD}o5bT zsT@%1=Q_`K4(;#H_+M#_(#@&W;yCiJY%sSj9hY<$jWngCd{7&%c^t@Db&O6mPb!k{Vknr1wa*w46pcXm1- zJ+IkOgo_5i{!IVpxhM*@Uz1(1bE<>bKlh?W-kqKPkLZwi=CG`FLz$)yxLjXd9Cw$=Z(&rod>PY866*`+p9=-`V>qzd7l<%-)y^c zKj+RPd4ndc_ZJP%8BLG7r#Jsc4aq}BzSl{gGum5Pk>`x2FX-;bi+pqa-s$>TrDCD*Tzh-;ol`?qlVLb1cqxf4u*HAdem@VT^g=c2gAQ*Gn~qY zhHLfF@ShkBPZOl!S^^qA*Jd~c1cqz%!SI&RaH<~~t_7gsi^1@`2TzSsOxJMv;3+4s zw%|j<)lufHGpOP3b>8o6IK0vD#>1NoZ#ul$@aDr?49~C|PB&h&3?C`1F3!F-!`078 za4EG6v;aYt#{BKsneS&WIXhBZY z0EVkY#ED27GsTAg8z~zz+|Nf~xHjWp_^MPrW_Vg%8m?6b!~er%xGx_XuGL4w|Ho!H zBuK-x1T=gtli@xfFkGt-hJVUtxUU}?t_7gsKLo?`9!ce6x`xX~QaQu51s@u&jxukZ zK@Hz_c)Q{4hj$p>ad@ZUoriZB-gS7l;X}-Z&(v;qqcEd|QE~RQ8Loa#lA{fpwBet# z819cdG(1^a@{rN+ucF~O@6I0gF+Icm+RB~b@H$+ZEAieH5Jv5J`CYZ?v51Yx)q!3_U}$#6;t4A<&|;lDQ~IN@PWez4Ieyw$ndgu!?oMsD9p^lY;pFr8Loa#8m zfWUCAJ{Vp#8cy{?!?gf3d|fa+?=e<0DQ1zASU$$8``@&k6&S8<3wb|W8`Il5gBpJ1 z@KM7@4<9pp?C^2J#}A({eB$s)!#}bco_9Zdtnhhp_O%(Veoh*$4Vtv!1(V@)+@ayg z(vpXahL54)Iq%LMpGh%2!~NPq!?j6JzDrk!O<+O?H2jp|Q-`0l8SZaM1%@Y2viX8o zMa=M3jfP`_FkFjZhA%Q1P6>hGT75A5`)0!_K{tF>K~B^FhW~%!-UQ6DqR1aTwcJ{I zfu@)0g}YYWtGF?JZ&h_wkB&pr3!nwvQ`Ica=-@h|GtP|j#5c}+YJ(ym`zGLmprRlm zf+CA7A_B7S`@Sl>fPl#Q&phX3W<+M>a*}@E>+hTKqdPKw8TreM$cPj798!rE!zr1~ z9K)+3$~yCKu^vVYr&b)q@IIm48N;P^J%&@-K@49V7Q=;lGlo<8VGLg%7{e8U9>XaF z7{f=xVz>Y>VmPHA#PHt07%udiF`NQ`G5q}?hWlP{H7a1z7_PtIipOwj!<)5qQY!f9 z#K!Qm%jcBOEuUBZb@}}A1?3CN7nOfgJ}*3miwCy0=i%eY`!(+y7Q@MLddQ)K-f|3o zIw*zLt-yR)&m$*eXbM*e5_>q?@ddtPgqBoqNxm`f;-bpBT1#hK14c>0$Aa?H;^b0bn zJ&)aP^)PfFDenf(Z)XF5G<3TGVC4Rn{A$BOGV@Kg_oqqyS>$%B2Z4KseEK{fGxfG_ zXG`^Y;CAbWaeE*63o_<4+;2LSAS`U}Xns4JjVF#%mUzSY5JI8nB{pPVTE47&dHMI{ zE6P`vuPR?%zNUO_`F+8^ARD6|f9K6d>|2k_?(H>aYmeBzVSFV#GH*FvADQo17Ks_- zmTzZEqqBI8=G3p-3&Zt)s$Y<$JIeL#Yze}nwc1h$Ovhqti;6i`2EvyzGE!e(zM*_- zSfm!uxAga??Z|oo*JzsuMe2_SMrsIvBQ=G9BK3hmky-%gk(yEuBK5Jsky-$dk-DAe zt5iHvlRB{Hp+q)wq!#bMVKG=9KI6AzV`4G%NKLIah}80h=gvqim1~ijQVt^Zm%}2p z&~8L(NQSMCwC>Beeh^BXuXySE+cUCUs!XLy2tWNPWCWd!3P5EQTJbsnrINdO|37 zMrx^Ci`0~I5UKYHi_}895veKlFjDUw7^xM27O5!!7^ydgMQWj6kJOZU5UIxlBehU( zL~2SujMV?7BDL?^*<%8P=hU+E7kVAyIO#bxbr@2o>eiE;m)J=CK>5M)L*<9dkCY!R z|DpWH@?+)4%ddn-YVoYq5~(}M2Q+6J6sgH!TBN3A-g2ZCKj3xe)WT>ZQnMYU+Y2N0 zt{_tTeyA`eK+;Gpw-kuf)B>0}H7OOol#!A8$?{X>RlA(rl_aGdHte)M>DhE$*DYH< zy5&n-?mzFic|V!=>v>ntyJz0h^WK>!=Y<2Tik8JhgR{PCAcK#{z&zpbM z{JZBrHUIVbhb}l_!5IsFyWp|~S1!1A!Ho-UU2x}uyBFNI;DH4XFL-9ba|>Qu@aBR8 z7ap?kxP{+Y_~V5?S$NjMa~58*@Un$BEWCN)eG4C4_|(EbEqrC+>kAK9bkL$>7JX~c zNsCTi^ovEmT6FQE-z~as(T$7lS#sudCKB#<5`CH|a$|sk9 zQT|o=;_~mx*OhN9-&4N7{6zWb^82$;(>Jqm)$~SLpj`fu`tn%QyB)ze8S**DoP0e{$~N@&}(Y17_QA7lTvXkgvU#yxkK-oOyH z`KRqavsb-sMaU)H7+qaTBSZPp%ry+9hfOEf|M~i8d)sa8W~`pBCtvAir=cVb(e0RB z>iWtYpM?A02Yb2(UwiY-H~H!`OTDF1ckf{T4qy1pZXf$>GJCMUYp{p^3;WX?92jhs z`eqH4x@UL)sr+pDs;Ld^uZMbfoaQe^eg|JNi%IfBlT4JY*E0&h&<-0)Y zW!qp!UGE-BFW(1Fy<&BlUcM2eUbYjabiGqbFW(9-z2m|~GrfE-NWE+`Y|!O?f zsTZs--wskQ+YcLcy?f-FY|S)(`J8K$jjQElZ=TCH86Q^KLsxp8RLb8y>r|@Nmc4jZ zDxFM9AJ&y#B9;0)>WU(wn7HpNCzcR#kb}HPg()eo|Me%=dZN6>3eD zhg~zxJnW}+rB}+C`aJ9kwWi9$u9;@1>$AGj3#C$@hn-MssyytPX?CwU@3`neX$k6KYMBhh;}BDSc5_dZ{$u=V2$*nko;wW}2O-FX>9p-Q|7E z!J7(jLE(+qdfEcQ36rlvQp-9x%1RO(FKtz-kGhPK;vUGJ9!)tmamV#D z(8MtpWG3su>+R(x3bhREt65Q|w8QGuw5-zsKe~cT$;CVneSNtyrv1ZHALk1=Fuhi! z64^z6!fHq^>A~plS1K9I--um@@|8&|h{#u5dwO61BrLDzt2DE5J^<`^n|&|$430PqHxUyRiI!qOcPcW|a*FU&%OSvXt@;-oxz_#rv$?ZB zFxQ%WQ03stA(cZbhgA-*98o#4a#ZE$$~P-l<$F2ZJUel}neAnhC=qdTNwAnK>hzk< zb3m$O%ek9ya8s++Fz25Fr8hAxJLU^2frP9Fs;g_(j1XmUW7DQl1l9&%rZ>f4Ox6R& zy=e-Ts%2pB$$nzc&pg_i6e-(_rXLkZnV<)zr$;Je7+=aU_}Ky&rsEVCnV<)wx3^y? zWEk5Br?zg_si_ns+X$xD6d==?qz9$1Zy*;;x!H5-Q*2`{8r-;c=M5V_l;Whf+`8#J z1&$E)0QL6+rOcrB<%_mzdTKpbG}FHcoJ`PzGC0^T6f%sDO?{MG)4vPzUSQ4I_I;K~ zdO+sPks2Au$EQBQK?XMN%%1as6>Ho1&qX~jTWq0pGMtB|KErWl?XY&2)vNM7kbX_P z-m!ZFDeS>oxDe`PXlGCTUmOiw6jIZ+O+9%B*UXStkhd1^SzV-SXRz1hM&|d06f-x{ zPMQ?<7&$Z~?jc++L+dCsepiENb_c=GGGPze;>F@(m!oY+OYbaZIkN}2m`qfUS)D}p z>|j z^25qWmB(_2mG1TQnrDk#BCW|K!LqU>Y=DSdQYE9XlDm3 z6f%q#bBrA^hPfdHMkeUN=skl*&&k^K&1} z^1t0z?ZmH~S=1sfv?AZlMZp5HI>H=%x6PV0Aa$}8e0t{kYz3XA3ci8@W;HJcXZ3w? zWgJU%7-I!V5x9bc0AIm3Uv;ct(#sDpKEho;t?V@Q6#L7ef&7xj)-La}U8z5|V0OtG ze=f~zEAe^FN)z>&DONa`r>!9~uB-HB{(PZX>h77_-}{xh{y{zoZg0Y#X{07)k2Lz_ zBaQz4u6~KxKQK7AG>bjen9ZJQ%-M9$)W5MYESt}6rRizQVvKn)(CtkVQDAIIx3)BA z4phwc%onEqmBS74oAu7?*T^Dgy=~+}5>3dm-RT6|a!a6=VSRe$4u(}qd2rNHF_F`( z@RRLOfTi0dx2Rhth_ufl((rSrH;>|c;!WD~v&!j}pI4qi8vv}x)%rU_ZlDOZxwyVlH%=!@$eo&cK6X-ampU7oL=W;wq&qc1rxUu=xupT- zLla&~1r>p5j52iASDj@gslKaI>%eos3SWC3a*JNMJ< zIk&b=S&3fiV`qN()F;_o77gZcmxJWDH2t!!K(Y|M&JEMm1#~i?xd^DOfQ%cv2GsTd zb$91LTqgtS&s$b_&4{C9zo|1)M~RZkxozp`>C3e-{kzGQnDrZ!ext4+_49g>$AsQq zR$)%HG5y^+>1hRs17xI|hgaNYGeNfneSQ5xAA?w#cim)FB937x#!Dk|NjC_q#Y>G0 zWhh@LUi(oCWz>=+Mk?n<7#!@&wK4tg&1?NEIh$7NWM&r%fD5_-X3gr$)iHn-IRLLe z0Ra1kO$FTmbLRBr>KK41x1}kpqQNXuNfR6unJT9G`}wmFmW+K!9<;WR9m~mcIk)nywkl=HnD(RciEo@o`A!#y)Rrl+pTb}tn^aYjaT842}3D3d3b1drzSf9J8h{*wWi?c&7g{@wn< z=8Y4l`R7*7tNglhe&vG7g_Vmczo}eY`EBKr%I_+dRxYbtUip3HiprIhJH+FdH1e;W znohd&Ey{xb?(1dmCA+H1ZnP};Gg-E_d0B&vE7i>lz$_`6^0;1X(mb$daA_XLA2r$F zl(Yx1t80$9UU1bsNWU9Fw%0*OwoRRosk8^OyE})>RCCC;$)_mnUXbBsHyyTFEqH0r zXQCdko*woTC0ELkz97y8kLeJJT@oxvY54ae_4W=5$#fYT`8LU7dj^$xGUnkeP*T=o zRbSsMDVl=qG4=0kD=(Uz$M_5_tI;r@Z$VSS9=QH~sF*L~c)pBj#D~kst`HV9A?m>z z92^vqsb&8-^)KAA!89_%RphlN3zU%cK+Tz>v~r{VDSx_=MQFH&JnCDpq_78Ui!EkJ z(bTZJr~Zo@Hb=yy3@;Bqc25GtJ%|ezBHi4=pHF>}V{XYDxCnU}>~i^-%3>xS;Xz(x zAaL;C=LR!XytO4ieYwGQGJ&`Uc4&yla;ckRzDr@I5eqG{-MKI|LfnJ7crnKm!YQ#k z<&Uk>z>vBz84)du%Vs5#TooMj*dSw~Q-lXahd>$?3qQ8Hx^hkB+RAm6>nk@@Zmir? zxw&#n<<`n=mD?+KRJNPCoo%V1o;4d;7);Zl&(|l?LbztEC`+wjeJfw-W%KOG=DCLD z^Gz)d&hBA_45l{y)9mT)`N|gF0X~7Axr4o|04^Sx43_#>;i5+tzij54E1!+-SoEfw+X#`hTY5F1$omjUJU<_f)2)9^=#On_C=_`1h5~Kyjz=a`f#O|?yI~K*wdS`Ax;fF1{^C&fFG*|#Lmhdt$>}?-_;`# zd)T9u-dS@?vsp1|4l5?j-E{L*Kl{nmQ2z`s@^Nd$TU$EYZfm4e%G^|%*_+k`-S+kj z@GQ{_mt+$WoxkoTZ=6> zeQv6kuSIFy^xA)5E0JDcK3{K7Zo92nAeBqOg##A?*GBv0HrSjC@#f3+g^-B(HsA{( z=7bhvpP8H4kjk+O4Y1fmD3$theGK8o?6Ffi8R>`3-{(QXxUATT07$n)UT54gAp~86 zJulvjqvDW*-|6){RC&1aNag?8rOE!W#LMyQ;x_k~%8x3iR!*y&Q8}w}PUWh~ot3*Q z_f{UPJX*QT--oY$X1PJMTz2w4{70;P_=BP&+S!M%RI{7rt~2?C)TSNv;V%-UitLJ- zZo|BqraeMHApANjJIHN7Mj!r(Mf&g&p5BLVgQWWKfr+AFKCi~;Ck;VnvYxdx`tbiZ zqz_-=fIfViNw5!pMzpMY`tTJ1?!&iXXnpu^6T8mYhp#}=f|O^aP#^vaA$|BzzwE=e zSpfU+uMg?NSK8V00ngk)AO03$efUay+OY4@kNWWcC$JA+L1=yW*%Bq1Q<2`32X?E7 z2<#StG&wBXhyTaQW0l7%PgI_)JXLwR@=WDVm1ir@Rel%Phd-v;I2bUE*(}vW{!RZ~h07%FJ-Y6)e5C5GA%+-glgQ-4zn_Wg9elzcH;qYwXQh5GOnAiG=T*AOoz)rWtX>Wt@Ci*#dH`tT8EChXZ9 zMj!q=6dJ#)K{UIA$m^6|^Nc?H9RmCCm0?;Re&+OaUv9)K)@HA{dnN*779o(vtilD& zKUZF;yjXdu@|ViXmA_VAsk~Zwt@3*1jmn#qy{l7!efVRt={r3Y=)TPR@HJC-Xnpt@j82KM0a=^9#+tSP2?4$Vi}&GwwfeQ{zSXZ+4+`zW zACnF8ECu8(`@m)JK74K7C9Mztk-$ED1*7%h^A%)0^csw@f}{vM!h`@{!Qy@R`&U1N z+M9WsxV^o3Om>RrPrG4Fsk3L+hi@9^=)<=U5+w_p1h+S;5C2Nk-n`t^-fY+_D@*yT zO7k>pReN))nALthi`$zWefSDZ>%+H#srF{3mSOEF+nXhfd}xLWo(hU{2J1|=<%aFe zc9|g33b!|Zqk3TVpz0d5QF;HiYop4$cABQNjg87WxHan7DfDerauBkakci%>XQ7Si z?86@e?dp8zxqH~a7vn%0MJ1ydW9*9bRlnvok- z!q_&dA`g-9KzEgRhw#HqyQ`6@o zL?1q17xFW=%_yYJ!S&?@Rjj;AHIFo zst?~T6Jl9jwigc+RZ$=G;U7^wvij+;KKwD&znQk}F(<=&2iY8XAHKFtwLbi}qxSga z{K*yFhYvvV20S;6-iP0dfE<1JI*{zcx7efi;lB~ohp$l57CN^rs1JYVpgw%1KW&_I z>qmX~e+}!yR{&YJoEri6;V%#D!&ex2JDnRu>%*TL)Q7Jy($+XP0_wx>g!SPA0MLhT z*-WSp|2<)S_zEEH&2w9T`tU`$Eo+_=4~^?aAHG7!B;63W5C4}TefSDM_2FAq2=w6} z7u1KZbb~&8i*ne9e_%)-zEZCG@GZJQAO83Af~x2@WGkOPIn;mRr1T3}_uA`y`1^}~ zV_AXY9@f%_ufSBnjx`9loH@~le}d=&&f5i*aYk)K#f@Cn4W{?u_b8;aNl+mfg*u3o z%DR#CKKw>lA3j(>`IuftLOl@5JE=>8M|1nX^Q&3$KK!Gr->e=}J+^vW^;^|%SHDyJ zZuR);_o^pUPpp2w`h)5Zt0z@|RDG{_9OLc7AG7x1v$96ohi_g0v_AZGVw2{9J!>ST z`|tsrl4fM)&*n%#q7Q!rLAv|!bx7EUZ?lo;!>`DvD4srig_m9p(gs$ieR?1MXT`bj z_2DZd(OvIZNxct$Nxn@~!@T&phTey-prot^%jm;jAKr(r(2PEO8)If4{=4&Klr8h! z`PEeK!&hiR)MJ|7hyM@3efSDW>%+I1rT5`ahxg$ttSsvLH=@ype^Ze@e1#`sogb0t z!~b!?K70iWqMjd_?!&)G^~Ce1PwqZ^ge=58TZibwA6A%YXk&9{E!BC9*Zc4hrV#gF z5`FmF1@_@9xO7ET4`sGr>soA(F;Tg5LWBoJhd>$?3qQ6xxq3?VC)HD{Kdqit{aN+& z>d&iZRL`vbqWa6~S=Gg1efVP?QI^7e_?%)h( ziMx$+DqX4%-!@zR{L!hSxH(;CS3eQfhd|_TeiK zy$|2cShf{i%b&I3xFk41#ryCts{W>WarFk-hu`6S_|I4NsqR-jpn7oi@aj?3A6I`> zJ*RqJ^}_0Jt8@H)_><=Q@JI7L{Ku?)_=)Ib)$9^3`|xerQ6K&sQL6Cv;Uf@! z_mzD`HXx%9|JWjZ_y|w$!?!_FefYpco+f~w8tCn$2r`q+Zz484qYwXcA$|A?2lV0F zAYdQ<2Sm%Nrw?BN;68jChSrB)5xdUWhp#|jAHEF&_2EAm(uWWA%RYRYdf115c}O3= z(ysdOZOTC(ekrUEUulPZ_%{8h5C1;{`|uTn)`y>=B$`t}$)Qz51a^x+nj9AH!~b3N z(&}Z^%d5YyUQxZWdR6u6>NVACtL?x({7Fk6KA$3Qj@Rte`|#HY2bUE*(}q;K4<7&t zS#bI(D5DQwyjdfEQzZb?tM@vX>ch9$W%S{1o%c}kI%kSR_u(s~OweN!?!*7L9K+Lx zuP{&_zReWehd(5onx_w6f#5!T8;aJ4zq70$d;0Jdj@E~71Je8O-P^*~tG85dt=?9>y?RIW z&gxy&yQ}w9PYUeApS1Mhb7Ognyk?5thd(=aBc48dg@XFVwsR&_4W0OCLVBjQ8Pd^Va+D?+)z4S1?*1euksN7%Rxy?6sL_D@X|N6)fI||8VsQ z)ZXmw!=H5Z;g9Bh_~y(V?alT} zPvG`u*&uJWH!C!)58n!=+MBaJ{M}@GvxK4Bn-!Gahi_YM*oSYI2_mge8tq(t6Srbfc)T|Hx19GEE7~4h_Q2P7u?JTN-s9h$Aw89(p@#+)R zC#$a&>BFCN_2KjR^M-kiyKJZ0`ta?8pwX1tbf<>(;s3l?A3nBH@58sxSbx?88|Kmb z@a-x>jD~81--o|8v=3hyulM2GXRZ41?J^;jh4kS+U45o{d{`g;r0Q~nefVsSyboX7 zrdl6<6}87Z`tSir-hjtaE#9JNfzkW$UqwKUK71WW_TgKA^gjF-gZl6l3a>4RZdVHg z>cd|X)Q7M1!#;eAe$e1(Dg@GT%(AAWC8AHKp!o9Nt| z3iaW?BdiY}0DwMxiwUR?zZuqtuK-{lz6AjF;fr#cuMb}#pgw#H1n$E>HKY$;0jNHF zi+0e5e^^i-zS0f)@GZ(=AO1ceefUbb>ch9_27UO)So`^*(&1U&y*QsNRSF z713`T(uc3WRKd>UnTS68V?-CQw+|oTrG1EQb=JtQ*SF_@M_|I0Kt3F@-bM=Mli`AE^f2qD) z{cH7=>Z{e)s;^hysJ>afM9hreZTAHIUp`|xd8Mj!sV@IHKnX7u6P;LJY!k$f3Nb3NOW*-u3EK755H zL_Hf)@5A3QxDQ`JX?^%Mv-Cdvox=O@6_(zIZv!*>@UJY=hp+HNtn+Vuq7VQ0f_?Z3 z7DPQiGTn#&E7cR91~l#gWlubNScTr7j*x}8XX_As_)8UL8U_)j-iMDcg}4Wk=)<1~ z?88@Z>58g8{A>%=wb&qIqH^bi2oH)5fix->er)x%+P<}~*Y>OJUpt`ojoN{=gK7uY z4yhelJFIqi?U}GX{7Fk6{%F>RuiI+x!?zA#mZy#DHi6=e>zk6WK744KxZ60V0{ZZ6 zvz2}LHi6>ibRAjyd{`g;q}hkhrjhpHYea2YAJ&HtHHtobi^{H}YkLRx;ZNH8@YyNi zE%Vxh(@LPV58pZl94ksGKUT4Q_&+PqhY!p(`tYrDSMQ$p^x<1I1X#a$`tUyx-iNQ2 zLhr-3nxWT5t$p}b4IvA$S^Dt*DXeYil3AeGoU5w|Uzn_`#0t!+&2;A3m}aJcP>o@HIPeAO3kkefSCi_TlFi zmzL`Ys1N@)p?&xYMDN45EiHaNnwqQ6g*odGf{ORyf4lab+IMSjlYRK3ybu4n>b=#6 zs*hA3t3FlzQ}wI0BWg$0zFGTL?fBXqdF$`SJ=U^1N;Ca-6s|_K*DjZh_)Lmj8riOz zY45puap^)Ys;yf zJ(bP0G4wdulStB!l? zp>`(an|g0=Z>o#wzB*r)-FKdmjNYDssvrn#p3j#FZq=o zi3vVVBfcDjK2EdO)RyUzOsgfyKV{x#pJ?LWXga*77}{z010dKS%}bk-|Q(`SUqvLNSAT zGkf+{npp#ma2xk=LnJQe16i;jSI6}KYxV@Oe`-2+64?i}weJZ-giO+hv2dYO$xwcf zTY(&r_8DP_!R34iix!nKbxi-)b1T;Dx?yVV9*mLP3j1lxBz+h|L;XS}L;05+W%bkt zGv0F)dlbtgeJG0;_Y0K_<%F4+c+^iX1CFl>q2*#12j(`??_0UgylmdFdO~@NvPy7Y znH-QnU#VU|IM~k|>HlQSGw>5v^G~RqSo?nM2elv8POAN=_T$>gwNq+8shwK;Y3;Py z&uXXFeqKAHcH7h*`SoV|RqTs-+4Y9soz(aDxY?p-iA9lBY;D)guO#fd3rFA`(Q->a5I&79wyXywde&&+#!`Lf`dv%gR?=T|4Ia?i|5 zC9XW5`3&DJ{M*{{p}GYV~N*%#+M73_Kp^y3%Y^Sv(gr*dxn>_@e^Hl}}BT8->s6Omt% z6N|IE{0KJ$SSyN={4pszPi&-afh;P!B=}9s{_jMJjD3ep%fT1Py3ecqy0&rZX~yiIk%vmGnw%eLYj;R;YW!Z^&6bq^$?lNKe(=f1Jf2uogxLRQ z`~^C<{rsbkVpix5xqDu|SiNJm7}N&?A@!*oJ1}7WC7pF%Aj$QyBlArDGlvbUcb@ss zF8m6a#dkB+6N{Zo`cO)x0jZPWTt0IbTk=x64?O{10C8C@z*`7G0p21LLfXZcG<-<^ zKHW6zoh0Cp_FhoCuy#@HH?^Op?LI@y*KNP+I`+&iKc~6(0nhCiTk;1FsW4l|*{Scz zhL+}Ohjdfc0yV_k99P|?sm4J?wy3AVQgt@8v`|-l`qZ7wsMNiz*=aZBUa~J5Dbwu9-O&~S=YmW+|fWOC^|!+V>TgOr3--C^ zu__1kH!*c*{S7MjPaW3Z#ME8&H>F+G->g#y^|wm`>TgQ7s=rxvgZkS{K>bbWR`oZl zZcu+aBM({b`kT@Y>u*;5sQz|mq57LbVh%Q~*TH*2j+kiMzexSfu0n(yn*?`fo2UNv zv10W%wI(bw6j~Ee>GIUyY!<6L+a{5&$!4j)eKV~7rq%-1-}32|^o>zM^|!r4>u(AK z*Wau#TK(;n@cNsAVv!=NsrekHQGa_WsQ#vqK>f{X5v;%cb71{VA)xx36$97bz7zgaPG{p}-x^*4or>TgyQTz@+zwEhNQwEA0)q@Ng>Kl7Z# zE)(J_i`U;Sul>GuMeWMkRkf>Y*VL}9U01ulc0=vP+D)~aYq!*Ht=(3;y;f3%CRHNS z>u>5qhAfJ#Vh4)f5VKe2_iC|&J-Sr&w-2a7lTxnN-;{FZjy=j@{cUG8b5+IC>u*Xq zo4KfBS!NFFZ<9*7s$%K&H>6xtu`J4A{jH;xMa^8VzbWNxSv)g`^*1qdHcHK0ufHMX zo|(h?TPLjkrqs*&8@()jch>Hz-Cet?zbOD*e@h{B3#9+ZP8_e$X*Mzmkv7sAh-9J0D=mY7uOuZ1dtsW~)gv+U=eniY zENPy@lIFRaUJb9mDT~een|<=C(&eeY*;Rztzj^9!Yl7-;Y9V0#EuTO85T|w|QT^@F z!1|lQ!1XsPidKKSFtq-rfb{yCoe))jv&)2#R=oc9aP5)WqqRTOUJI|ksqaOm6}P-d z*4Z=tuY`RC6VtWn`?+csPJHz@^)bOzSgOv3vhNmZs(%z-e^Vb`W9~((zjgNH#WYPh zPhm^4l$1LcS%0$)QI3>S$sG&(Eq|(&Xc*DzZ`Xy@-;`yz{$`t^s=wJJ3LAl=fm}2Y z4Z5DF?YoPpzjb*1?T*_0wTEhdtUXqHy!K@6FW&lFr$hC>u@2L${#NhaE&+dF|J#(m z{)UyyB9>J$)E)IVtlU3!Sbq~!x7XjGc2$3~P94TggxtiM_Hqx##K1?q1Qi8)xK)|4YA_3rJ! z?oYV$3hjThs}Lc_CXv>fHcS88g+=Oba7|cbD6}Sl^*5Wvs{Uq^NY`Yu)Zd;9slUOs zfc3Y0dL?~h;QHGhVf8l%g6nTq7_I(xQ)vASLa{)N>TgysqyBbXK>ZCOf%=;j1lHeH z1l8Xl0;<1RF>w9uzXR%T5ChcTtO&6FwlS#w1`$yG&5D8RZ{tDrH;97jZ&nmsfBVm{ z`Wu4L>Tfxceqv<)%o9<&Oo*>6UVnSK_Dtu=m_qW>*>RYtECJ5c>?SQVO-a$J9d%9%S}l^6Fc%3=Mj zrDm?GSh)TMm4o`5MLDd$%~Q%%6${tjH07d-Wl;|6Z?n|0sF~yX8&uAgMbzIc%3=LY z%$$uLkHr2Yog%laEV^S-_7`_#W$|5|u;l3 z{mtBrp#JuUfchKM59@Ch{iy!-cu4&X0^s^v3NfHrApHlgzu6>2#zp@-QIEnIm#jyD zjH`S9`T_MfL+fwcDA6~>=Bd@+nA=MWWu|G4`kQ?a@Rg)m!rtKe+wP(DH)ye0f3r_M zxc+8W5n})5slS~VP=A990qbx1{7Z8*)^Y#ag+cWGRurxN_RX;R8wAqpZ+1dd z{mm{DLR#_q+ky3i>Ic^ksh=BKe`5xc{coeP{-)8j>3>7(Z(OywC9v4DD~~F?wQh9J z^uO5qN_Ev=4z0g&)xzmBjavO}G_AjB%H8!h+YseQdHqdS$sJ30{q3D0^*3l4uD{u) zsOoPviNZ$UXh7EAj;K%WBIkgD3aY;;?Xdo4)sO0LrxdEcDI}`? zmLn$G_AgR@v#Ssx$0m{1nl?-Q?bKrRH?<}#G8pwY+jMzNGO+$;R}r)(o2CACUs(N3 ztp%*VqF~r3Ix~RtT0;r?aJ`_n}TA28r9#dU`GAzvY`5#LIU+SD+sK= zy(h5#rVvp5&5D8RZ=VjTzbOn*f3qUM`r8Ks>u(AH)!(cbxc>I;!1|j)LG?E)3a-C> zDzyFvV6^&Mj-;O$nLqRTn_VWvFBGr89bNxs{h0c(_2cT_s(-uwo%(m{$Jf7CKcRkN z{rmMF)PGn%ss5w-#j4PxN@RNdP4zReD6%Rqk&R`)Kh9zf!KMSbF^pDHl~Ni*i_h>r%_2X0F%YlybH#Yu#%O z>u+M_Y?PY0UVlT%Ju`>(x2~}In^G_9Z}hVCom@Yq{*(Ht^`F*Ht9J#}-&Fe;tiO$A z^*3`fg8JLNLG?GKAJ*S2`ceJufw20U0>JgR6k80}f3r!5jEnwvq8^1aF0%f1 zdj041?}gXjRNoMrr&fPsZZ9pAnWj1FZ}vgJSCVQ8dxPt5Yr^Yq%3`zrW}kd;{mrf- z#Qx1we>)_o{-zcJ*5C5^m*!}!*WXl^7;`UL{cS9* zziGC^4aoZ2x%D@85%sq*UVr;> z{b%(v>c6U=T|cLOUVTcuG<^3p8&~bRafba)IeQfmxJa`8H})7;z65S27iAZl!JSs` zuqXS!$7m1VkNX^BPr=$~$desk~cO(RqL@Oh+j zTm3=4uIZcYKVN6R(FPYrVj4_3a28_8vsrAJuRm|_oZHj)6+VkIr}mYrvHO}08`(6( zE6>{5E6?o9!Q}%dBHk@#pU4GMpJfwSG@Da3Gqqv;I)1~=-}Mh}{={-*(ww9&b!2Ws9tsgvWpoPSq1--7weUFvQACNC?De^+m{Re!FL zgFKXNY7U(5X~E)3_LesOCNC>gflWO>-$3?F{lRQg^QmQfIzL(+ezxo$BNGqYOAFB~ zs7?K(S`ECXJM3(A?1zg@qrjf#PLuz!@9A3pQhlaZZt3jhY8@vfK|8u!o~88iJ@C$% z&#>8)Qg7SUoqmyBeI}2lpUb*;^PKbR7t}ATUsV51{o?v>>zCAjSHHA=S^e_*3HetS zcAQ?#UqZ~^AeO(uqHgjm9^NTofXco%*ee`Wx}eO6B$=&bQ@8ze9v#?U^N&(6uq-;5 z3kkruqz7qWU_hwki}=BO>ukS%de5n~yD=DXkl5BqU-5@mQh??1`W9{{x@l>2n3vmW zKS*P_*I;_r?8JjZ9t-W}W|AIj=g;rYHKsczKdm!6Z(yZ01|m)?KPILd6t-sKfu=6= zn)*a;>MlF)v~hX|X)19$lZ!um322P{1}RcM#%*tNduGm%oj- z+12nJ^-q54^Pi|^f(&!^PP=Sey(jxm_Thq3GOx59Ly>=2kbxeelRbPL*d_OdJ>ot- zp54bSP}mtlKpijj{K9hD^Uvc6o=1mQgy*u?+keYt{z#O+q)f~Uy`=1t{5ezRgz^_y z;y2KuWzResoWHr~{r$?Py?y3h#s>GHj34<5JoCkV2!so>*pt2;6haZpoh8&Bp`i8L z1+OPgtIy206nuYJ&z<$V>UY&_8dmyav;(t9`6 z$vpP6S(2XSk{OOlo$OFKqc(Q zE0vIL2Ki{dFQ(V#aM`}#w>#RlOwbQCFwie_GMMZ0HJo0%dNo`_{K92uRxarW8XO#u zS{YI^yPgcNZ)xtFA?4Y$eXHl9eyCZqlv)OLYF1e0IVQBJ&F?|<;)U+@*|VimhV%8A zXV}43M>j9e(C$fW3vqrk|AY>)euh~*$Q+bUihC%x40riAJd1w5i(S;;gNt9#mL{DZjdK1GC?m$SC>@DP`dIf19vC@#q?4FB@^_bba(d)l?>(c3Z(;3 zOb-Q6n4lM>r-!4YDjCXuVVwFm>q;N{m(tHmvHI) zeh8joLI_=yC_Qmr=#TZs>W|l-s6SbMs{VBSnfjmV_o_=1+#V)xBEw*&X4^x0Nj|PL z$8<#8o2NS2qIQ8xQ-))^GzlE;ih_XhOOrslPhDl&5Xp2$0*O1BAf)`#B#<^Jqz*(f zT@pazl59VE7B9av38W9;OH&4ByEF-~+|vZ%sY{c9d`VrJGC13%Nx(6W69koAngq-P z;L?=gWc$K&PYP#s?w>qsm|vO%(m1#@Wk}XblYrumhl%>>$}dd<>U?!+%8>HCZn`Of z6uQ^5OOwDkMqZjS80V!)K#B9KU7ENC{R~TIg;tu7LYF2|Q=GecuKs-e&-EATFVxb1 z9nkNS@{S8o&KDx~LvJTc4W-`)TDy}ho8(1gs%!$R$8{608LC3zsGNAU1TMzrsh%8| zm7Gg!c|o|xRy|Qml2uQz4Xi6$D_XJoNv4oRurp@<$aY@3@%XOk5%qgAMNvT6CKELj z45;JD^X3%`T-zyECFPgQ9R3HUDLt>&U#q`f|DQsqOr&FuQ`SxvYHJ&I%E)oL@r2M@ zIb{bIJ7vmx`za%4$bSYQ>VSc#jMNgi7@Oym{ZH5_lS^WrGWPsY-w7pn%1(x-jJ=`V zeaa+Iddk>Cku0de<3lc5RtoTn1+H!JQ}$+k@5VljjfGB`NHrX%tdlH>I%VWI-FQOi zt(>y|Eq2P3_4ZRn%rN4Vky-*5WAmJ{PllZ`xg_Q(>#(Ou+D<^H?0fK(b$q8x0;Q*{ zL!B~m(acjuiUqE1@l*D-#=ecOH-1s*l!;riQ4Vi`G3H=YoBE2nJFVy8@5 zZ$D+k3?oh%sU>hRHqR;hK-ejhOJbff_TXCI3Fwp^3QrmPwY58zNuczUu?OU4EF%}q zJY}R<;Mx{HW&1Y{Xndn_V3AYS5zmetr)(^#N1ZZqoNhcJ^j1#U#|xb@V7>j65i^W9 zWu%tC#n?QjZ0Dd;rk2D!Wvq`w-wEiHeFvU0)>G{~WeO-gWvpMsJZ0pfnWu~t3tZdc zr|h7{!Hq*2n+lyWcspjb5@xGW{TNT0QKyU?ryEZQy_Hk8zSt>K*4s}RF~f*cMrsLM zjLmb({x7J7vmx`za%47;(x-ErE-%c~05e!%mr8 z67!U?E^!>cSoHva-42FA@o*G*>JH_rmVN0GGc}ir;OARxEPz~l+6u0WpYW(Q^uNJ^__rD z+5f^*HsL#E5-2@othv@aW#ponr;HQ}T-)NO?AXR}jc+v;6**<20eRVEvOMaPk>hmZ z38A-g%36g^8L-}d%7__8oH9~N;9_i^Q#LQ?l&K{#PuXNr(su$nW&6QXHt9KK3Mf5g zlhi3A7tK6nq*&nE7C&X*X?(YFd}CIjQwDFxmRPnj8H+k)8QwdX+t{4($CHg|}mH%C-Q#AMNGIWbiTb59H?iq~6Lw+jnYdf%Xru z0QjK!rWknA{AxniWAmJ~|H@ivJsluwRkE|DSy9sW13GLUoOz0Ez(HQMUOmk=PmlP$ zD%k^~pmKR}+%!xbQg(s(rMbK*!fq3f}EPTa0xCr+*kapG7zh`t}tiF+?Pal9WS|Ajbx;v`gd z;$%YzI!WZpWf9IV7rMg5Pu$6kQyM>M++5_ujal+FWJV|1F7CvU0}cBLskd_C{-e-| z0}J3dal{m3P8_KwbUilDiQ6OS#Hm#wP8@3u(f0#7aXX?D$9qFuCr&|SCr&np__rW& z;@;8<7e8@7ZJgHlS>uXACl21AZ82^%Srd2S$brTVBc$HSiTlT5Cr&MZ+=(Lx8uk-XZ{@`8Q0&C11#p}=Vu~>*j#Lx69-HUHb;3@Z zTovNPv6c~iKcEx00-ZSCGvYjP5-K}!vS|dJICABP6GzI0u5j@a_shmvjbAnPD|F)E zE!r02#*?YI6Gsj->?fq&%87eVu@k2jz;WV;DaM>QQcdW3Y@QRhB<#e=RUu9sYah|~ z13GbULnn^+k2p`9gvw5wY#>1=j$Aq7#F28LD_s1&}o>5*A ze%2E9i6mwMQ`}oBb@%r7@9>4s?DnzGCbRqd=avRqrM|(TQunM)r%ZjC2`x(B@R=K$ z{a!wOf7|Z$ZMLf~{~~)`DSPjQG?M?cH#0JSnL%b>NjH%FAPeYazrmW$!T2wBF_`h9 z90?|5<&VH^U|Vf9C}h*$=3lD7IvC9OeLe(BWxZhY=X0=JFSG2T>1l4DXHHxZOXvac5*)`r=5MHX-XpTexsg$fhefmH&KsdgJO< zQvxn~-Dt=7O{}y|NqYeoEt;*QQ^*SyihlV($)XkRkn0!e$ z?mR6R%uYhb_(8Y?6tZ5p#ft}pY--;R#m}?%$ZgAhV%#y_QX!$HQ%Nt-(xv^GWD2uz z=1F$C`?4eBerc2hN`*zO+vABcckK}hbXUpiz+K@tvap{)rtb)bKXsgSe&d41g^i0E zziC|D_-*5o#_t-JHrC`nN9QH}b?L7>vvoBcHcZ2qBwN?)N7C8Iq_k0U*6amn>2F6< zt!%fH5E8F!=06hG-_0_Pk@%bcJV@+?2-z%{R)+K@LgE#je6M(rSS`ng#9oMyAu+8C z>8}WhXR;ZRx&N_E{B3|9o7f8xG9;#zA^jO4@f&=G#9udyofk&pF9`G?_4ejS{QcaU zHa(4y_{}9lG7lO?;_nRfAhCDrXErgd4C#*uiFf~HNc`QPE}Qsk1U*Q7eK``-%8(vJ zNW23oLo$OXwu!%4(1X<9pCd7?4C!u!#JfN;Br}3yB-Q}pLt^ie%~p?TWk|OoB>p5k zLo%Z$Mq&@aeMsy@5*ZTH%8;(lUNoFu?bc;+{PAL2(-*^%*ANjapY(|&(RKW9b0ZG&@$iAKl2(3e*M`tWl*j+ zfoK6mL~3-f_2?y^N&BRDtai%~xrH9Ac^t>@C75@4}OL zD6ht7Jfdf4W<=M}cu4o5_4Ns~ET~_G(RftP(9Ec=q4BWpL+kGsXjx$Y4MyXUJwr1i zyN1R?yAN$(K%iy8{XC4uqkD#CMt2R3hj$;^;GjUu0{kzh{)79HS=^g4Uy?TZXH#d-qM`ze3#miyPQVnR$06HC1(G?;M~$IR&$-r zYOZrO4b0raW>QKgn_nx{$4BsGM;Oax1>NphXC)c8OoV0H9Z#(0;J_d=YZfzWcGqK# zT?_EILX^xcJhqdM7Uz*1gsdebqIsMxdE^d1O%E(QN@E$1%-?4}L6RI1a}uvRcFROq z7Qo{Z?9E2u=W&I|BP~33l1~=rksO4qB_yJGd|C3y!>E%-VJzd3MNy4MVonB+q)dcm z0X#m%exq4{M-f~sJdP%xF3ux42w6)=MDzHl@l99(i@i$)hlq@hE>XFL@;9WbjDJL|7KU<4cV@i|{By zhK0w;SMWU(fnYoi$+?UN)*00E4xk-alVR6}UPD`-q5sEP{ zfX~+&w-w=2gbo{@?c{(6KFLwoU_vCC&u0~%vY2nF?Mw=TIiIq)qo^XLW%5Z1#h4es z=NpaR6yZ~Z5F4MJ>Q#EPP6XIiIrF;HoKINWXPhl|Qvm={+B%jo@3_fY081n-7Jbd`H0(@@oiJzTzaz+H7 zfZh^GOQDm>0n3(Zfd<;ZuYY8=s@exe0n3F~eUj!lwu)Ha^Fa3nKU=M`42rk!U_g6`#KP z(DuS$&Zk))>JZa1`6Pv6%nRW2xZynu@VVL-KgW}cBlsjoVS@>gXg*gcK7I8eX)x#0 ztPgdFX_8lT|76x-Z&H7M> zn3l;WDHLN~0H5C--k}JeBAnRxoJg*S;FBDM4JJgQ`JAWt^woz}3xheIW__qbOv~hx z6pAq~fY0v@FE7HU2q!i^CzER;_#{VRg9(vnK3`IN`szcgg~6Opvp&=zre*R;3dNWg zz~_m>^9%5~#uq6C%-k{#Ehms}D(oIiF^Is6$N4^5H&4>Pg*F(yZ}B=8h(2b zK1DdO@!3x9h~SePg$*V|qWOGA@#(7%tq}%uKF#{jC^0RQPf{qxyZ}CbJUp)mpCX*t z`0OP2MDR(D!Uhu}(R|*b`1I9>)(C?+pJsh%l$e&uCn*$TUI3q`3_o9h&$XWTIXap= z5Wy!o3L8v_MDuyO;?q|jk_K}=&H4~+uU5aMg<{ML;Pcc%{RwMDII*42vE-2mKFLwo zU_vCC&r21bzWR_fnDc4YhenBMndg%fiZL&M&(ntQDsnzWII;0Lo;()8CpiimOo&AD zd8XpiS07p{4CZ{A^`TK>S|*>QP>gv2e4al1yCQswaAM8lT|69#iW&HB(N zF)fo%QYgl}06xzeKBNerBAnR#?aJik2tLVC*kD2=n$NuypT7FgI$<#9)2t7T64NsI zB!yzk3*htY;s3h`pCX)C_#9iFyjGk~dK5C45{c&X3zAQ!)?FW3Ck$qMj+yl#YFY-L zv`~zB0eqf2{Pl1?+si%ibF7^tTa~tBzs8e)>@R?lT~+ibY%rlXn$Lq2pPu@VGMMve z)`#esYxyTF6k}chpT8bHwg{ghoY>B1C+UsglN^N&CPbq7{G#I1Qy*$C7Y1`a&HB(7 zF)j0al0q@&1@L*n@ZLrE6ye0i=V&qz!6!Ki8%&5q^Z6;or>8#DUM>vge46#4F=ARK zpQKQXc>#Q0H2j$&e2Q>l<8v&T6Tv4r3L8v_MDzJU#iyq})Lt$O=6ss|ss%=t9yLu16WOg>4W81n-7ykhu`0(^FS@pENT zkKmIWg$*V|qWRoP@#(1#wWYzFPqRKWMoi1(lN5?EFM!XhhF>qjrwAvO^EtjeX%^>` z9)%31M56gzD*0q;o%Nx1M;Ofb95?Gj)U*sfX`vYN0{FaUctH_9ML4nX*-o~J;FBDM z4JJgQ`Rr4C`sza+VKC>@tPhP7(=z!ag<{ML;PblS*NX5d!ikN~PV(*uKFLwoU_vCC z&!-fhzWPu{7|i)J>qFzjv`jupp&0W5_`G5Gz5;xXdgAB!XtF$lPjVDCm=KBP^G}LT zUwud#%=t9yL$tkG{gxJrF)x76n}+W#!lwu)w(~ibj79KCj=}~LBGG)_qxkgIhen0L zoKLepG)_#*JfEacjClck-ZFf75k5sYvGF;cOh)iYj=}~LBGG(asrdBOhen0LoKLep zG)_#*bkb zCZD8GjClck-Z6Yc0Y1lk@pB^CE`m>T6gHR;iRSYcicepCNE*!fH0wj-#I#I4Nue0? z0{FaZ`0yfpig02(pOeX&2tLVC*kD2=n$HsypT7Fgm@t_0Y1W6viD{X9l0q@&1@L*# z@c$O!Q-l*6pDU9cBlsjoVS@>gXg&{CeERA`W5Qt0r&%8wC#GfcNeac77r^Iz!yhlg zrwAt&K36PHri$}Pk3t4hBGG&vBKc%$-Swd{VKC!!g;^h>re*L+3&ofhz~=+Q|6PDj z`JHq9GuX_qAPjVDCm=KBP^UI1)Uwue^|C#e?)`wOQ(=z!ag<{ML;Pa8;4;A54gcBQ|qsbl- ze3GNE!GuUOpZ})#^wo#tS3NnOW_@S{F)fo%QYgl}06zaPynPWqML4nXIhK4lf=_Z3 zHkc5J=5vGM(^nrF7Y1`a&HB&^Vp=Ajq)?1`0en6-+$_MS{FJ4Q&++7=5qy%Pu)%~# zG@mnyPhWjV8qE1L>q9GuX_ND)4L@pDD;$p}8lQP^NYB%06d6raBO zko;gN=hLhYtstgl@<|HCm>0n3Q^RwL@ac=66UnC|_#{VRg9(vnKHsDG^woz}2!lDF zW_@S{F)fo%QYgl}06w1?ez6FjBAnR#?PT)V2tLVC*kD2=n$HD_PhWj#g)o@&Y1W5U z5YsaGB!yzk3*htF;oA%FDL-{-<8x*5xd=YVQP^NYB%045#iy@6Bn{?#n)RU-#I#I4 zNue0?0{DD>xWMqF9D#^;1tAEKsZ@JS2B zm>0n33&T$pIiDh&SkC7}JNaS+pX4ZPFd-7n=WNBNuRb&(4CZ{A^`tv`VliZL&M z&zFX8EyAY=CpJDi$(JJdBu8O`36W?%pHqDL>O&L4V9uvmADSShWu8w`D8{@1K3^U_ zrvRVwQgXg(iQeERA`@cW+=W_@Uan3l;WDHLN~0H3c7pHPHP5l(F9b38d9 zf=_Z3Hkc5J=JPtmr>{N)zyCR5)`upDX_g)`upDX_0n3z9Tml;nNpCS0=|r@JWus1`{IDd>*0r^woz}3WGVH zW_@Uan3l;WDHLN~0H6Df6!^YMKIu`&U`iyK&m$$DOs%^O<0C&Zk))nk1%Wo=;LJ#=HPNj~v;n z2%jRH*!WzLoE5<*ISLz0h(z=Ge#NJ+J_Nu2Ice61CW&d8e3C*j<^}M1^vFkw@F~KH zjn9eX+z39&QP^NYB%056DL#GmA^82zNwYpQNleS+lN5?EFM!WuM%ESKQ-l*6pOeW2 z5qy%Pu)%~#G@t5yHIu&j5d8k0n3aUO<0C9zV_c&?GS}^L&y*G3EvE`R$Pc-@9td&tY2lT)8~Cv^byi zC}c1t63u5>^2yY?>qF9D#^*}2K15B+;FA`LF)x76?~eRkk@M+^pDWwR6%l-rqp-n* zNHm{=icepC2!8)_rCA@M?bZA(Efiy30H5C*d0P=aJ@Ip8C%GnqPjVDCm=KBPQ@yW- z&DV22g~9xMn)M;tUY$>3?xn66^8)xhab%zXpYn5Kos}I5Nf37s^Lo11Cndg%fiZL&M&mWK6 zS%gm!PHg^mMRHFBpX4ZPFd-7nr+Qz_N?&~le*bf&Ss!BK348VPNeac77r^H!Bj*?3 zQ+^K9#^*%xKm?!UC~Pnx63yqY)cN$)hor$gewy{6mBh5n^GOQDm>0n3sfGFz2hMDR(D!Uhu}(R}_u@#(7%NrO3`W_@TSF)fo%QYgl}06tF}`C*as>5HE$lgA?X zBu8O`36W?%4^w>l>O=7RpDWG!&`M%jCZD8GjClcko<4H$)U)i`Fw~zNIhBu1ZoBRB zkJP7kuWz$mefby1mM(B@%fy?{&V%7YzwpRLnTiI6Y3krO?JyfQ@Uv8K4x@( zKINY7cmLD&pV{m4_0hJ==uEnve5KnzGr_8R{@FFxEkoEC!0Q{D=~k=4-+zkjRCx#J#s=3Ug`W4m^hZa7Q-t! zOyiZ1A#4uw!*>8)c@4?Qt1vp{RThzaMjN~m^EY@UWC$Arcs+MypKx9~mhXfD6UUQe ze&~lneZw?f3DtznVZ1&Ac;&Su2d~QLlvi0y^3C4hm6*T5D~m&0)OW4S3}>B`2>azRIE!;FXveac?4}qHGM{^@5Qv72#Ec z8Y{08$v_ORsNKy?A7Y0=&x4YFc?+ znaqpfl^mwoOvps@dM4nN*P2|sN~2R=Ww8nHO3aMlm6VFIF@V=gSifL+e3hTqwDH+QFnUIO*^~Zo$Pra!Fzb)Es6ZNJxF*AZ!QYy;E0A4R2SzClx5o)Zwc9L=oujDYz zW9<%mDkav9>Xg+OtYDg ziRSe%z^kX;)R9K>_}V7wO>JUk1h1r2l#KzrUd8$e3-BsJjg{B2q#462IZU&ekcsB? zOMq8Ty{QAgIm$lZZ9dOw6Eh=tC8eTl4B+*eku8hx>W#1C$u=>(lEXBc37KeKKLdF6 z)tlhAN84?p-qa>$M(|2XMcEj@>vbb97va?#UsojWj^ULYrrAu$MDw~H@an5K!EcbZ z+eE#oP0Wnom6VFIF@V<_M(!%WtNbjd)elc3%VT&YhiNtwGSR$F173agCTVmUUx|8C zo0u8FD=8IaV*sx=v3|qw_$oioY2|e?8H?eS9H!Y!$VBt{_kdSly-6CK@=Da3+QiHV zUP-Aa8v}T~W#p0~yn5s7%49NzS8|wUGa(br>$?H3zIqebKip|2+r{uo4%2KVWTJUp4tVv|o21d)4|m#To5Mt)F) zS6_VXj3ztA@JbHTcqL>Ao5P-~&jP&q>P_(5rR@$;Z=#JhcqQg<@Jh%KHU{u|-^f8l zc=g8Dv1BTSS8|xfDxhI2wq94C>sNKeQ4yfMR@hb*A>ae z7+%R?n$3hvG_MZ;UVZf@_)XJxhp0Doh?x<*l2TDN2JrgG$gV|r^~TqUWRDnL$zht! zgiJKA*8*OB^(Odj({_ibH+6`a5xkO8Q8otf`iGJCPkoI2RAo`$Zp_W_RPJs3rz&;* zr#T(@rO#BZo_u)==8ISFx!X+YohFmghc!M+Ng{M^+O%mqfWi}t45h9800^V7l){hF z)s>B>+>ohaL#$IvL6~0EGvn3}xJj!a|WBrBq5$m`;W=3{bdx%urT1QJ7=& zqxAKqC`>0qDFYOKSTmFfCki{Jew6VLBPgtf^1&v)|9pblNwxO?vp-?$ghEhWtRYW=XXS>7x*d zJAfR?;{k$P!0g!>Qsx8x5h8IXkR!Rh0Pm~t+calRhLrh%jSz`Df*i^13HXzKKhoT} z8B*p8c7aIT8RSTAZ@`~D`;oTTB16jj!Hy7#JA@p`?GgCXP(RX^TV_a^PuLzJai@?Y zxxE5^KIcc8H!nlV{KESn5_b$alG`)1gIvQ_TV+U@Z&(45xO2#n+}@!bbQLbuk-qm7A{PYxLW2T;ND|ZL19zJ z?IU>Q(T}t!b8=iQLxOvc)u1Gj+eh$Pm>+3qD6=W^5peIZ`iewy`v_j0@gpr>oFQdC z0`5JQ@k=DPkKpwJKhlyV8B*pW;ND|7s6=x6h)$4?Sh_Sr%6tUcd&)<2+&+TmRDPS5 zEz6KHAJK%nT=|HO+eh$Qz8`7ptuv&|M^qt_@(~@kkLU#Xh;lhY%6!BUh@^Z($L%9J zK|Z2V$&fN1F&`j}@+2bj5uD{)M^=0<|E!Y zvxL3xXiz3NJ>A>df5ZQw>5*qf{xtIJ$a5plkNkP$g^?FWUK;t!$jc*t z9eHKs)sfdmULSd58GxM4e0; zS0<&8I+Mno0Sf0jy966lBNT&a3I!#NI{*|O3o;ZV6d)8M5>O~8Xr*HwX&eD4+~;Q~hRa7NhR3H+P|{cdDBRy?D2BU7 zD2BJEP*Bpi7&v=p(ui=(q>%!`N#lP&B<1Ye9uE-Y0&vp!uMkOH2-|KiU?z=}O*m=% z7(`MR!nWHJm`NjrgpO$Cddj>OUq>ymZxEdm<3t`*s9n7SWLc&So-$5jGA#A%ngqbu_ zNH}Sn07%ZH5%~x+X{3;F(g^pSGik&~K|TT}jd1TdlSYgbbXCAfBiwt=q!A+pT^DfD z2=|^dX~alDR|cFk!oBBA8ZlDPwE-uMXzwW>VJ3|jDd_5elg2jO<;q8xNh3xIx<25f z@m&x}`3N&<#7IF`2%I#wAd>PCX3~g}g02xbX{-SxXVQp}%%qX>5jbgtd(W9PVx%A+ zfs@7wlr-|?b0v)cE=?NQB4+P?L&@OEM9-4wq>+>}l14%*G->=s^T6go&4ZhVG!Jba z);zp9-)tV!JhpjU^IOetH^0;TZu9u&_nId(Pi%g_`Ge*UnqSA8WB>EkBChg5mJzkh)o(1Qjm{`O&SqWkdKH> z8WB>EkBChg5mJzkh)o(1Qjm{`O&SqWkdKH>8WB>EkBChgA(D|al0G6fX+%gtKEjbS zvYC03Mg_-{MsAv!G%_uEmP96vw49zaQc|Hw*o2*3z`=;FKYg#d2#c%%}biUYhK#Cta*9!_suJsS2o*$Nu%gE zCX>c?Qu?$rX=IwIBA4?&;6tkAqDveoHW9{=YGEkHAUeHgK0K zA3;26L`XqC0w;~b5J~w6;z=Vy3i1&+X)Hq|1w=BF zM#@Lvq!I2t_mf716yzgt(zq>r(wIUypEN4CG-+gjMAFz!^el-^8c8`LX(XgVlg6u? z*EFwfUe~<7c|-HY=1t9;o3}J?ZQj5uzAgpF%-N<1BDqTuCEDF+4tnf|ABwfZ|FTA&TMcDHN16 zz5$%QJ86VCX3|Ij;iM7${?C~-BBUS}fRje_`#)#Wh>(KZ08Sd=Z?M?=hs7^Bi1t*3 z6yyqU(g=Tp#omZ3k<9i~gcRfsaMB2WgT>y_Dv`|gRD=}d5^&N8e}l!|8Y+>@_Edxv zzUCy~tdRD=}d zB5=}(euKp?2)5reu7F5p(n$FToHW9{=S~_CQjm|pNh92Q?xYbR1^Eb^G{U{-P8tzX zkdMGgBiwuLq!A$n`3Rge!oBBC8WB>EkHASI+Iz}J5J@9K3i1&+X+*#OQ$B)78WB>E zkHASI{QX}?`3NFuL`XqC0w;}gKy>dYA3-FI2r0-%;H0q+Ai0x9h-4;>l#jqkBiwuL zq!A$n`3RgeR#DQ(FA~nAQNg82BXbo*(%4D#EQwAUNjW2FB&0%<#;2N3H=k+#srhX4 zx#siDKQ~`!zSw-J`IqL)&A&EZX};Qgt@(QMjpm!py<7XVzS{a)Yv0z_Tl=;4ZynJ3 zM(e=VL9MgE_0*9xPPl&4I69h?KIcpt;qL$)Nh3lrn5Ixr(g=SC=tvq7iV+DY6qGc= z-vK(3MucKS0SW~rjqrDXj-(Nx7!iO%K}jS09iSs=L@0*$r%+JR2!99YNE#7};rS^P zlr+NM0XmXKgkpGo3I!#Ni@|wuB#j8g@c0x8N*cEUD2}8Np%~ttLP1I6Y~bvjNh88B zlST>%CynU$f3BnvBL%qtoHU}}|GAPzj1=SsaMB2WgXK&bF;b8#z)2(g4VE)$#7IHz z04I&`H(1W35hDe;1e`R&-(WeDMvN5X7I4xCe+T1C8ZlCkYrsh({0){fX~alD?g1x_ z@Hbe_q!A+pxd@yzqTgV-l17ANCXJMjz)2(Ad(Na0BL(>goHW9{=S&(gQjm|pNh92Q z&ZH3|1^Eb^G{U{-Od2s#kdMGgBiwt=q!A+p`3RgeqP^!z8ZlCkkHASI`u(3PX~alD zJ_09=@b`btq!A+p`3RgeE(OuunKWXgARmE~#svV$nKU9KGijuJ1Wp>^-g7367%9j{ z;H2?gC~4&Pd{@#4;L@a#9bh7998L5riB1|xIU{K#q(YO%Lt2Nn4r?9WI-+%C>!{Yz zt#7uDX&u`-uJx_fw_D$7eYbUd>wB#eS|_%?-}*u8hpm%ZKWhEBb#m*J)=yfewtm_= zt+fxhp1P7o)wIjrvZ}o_YIH0q?d41wVN0hgX@n>S(-aCy8evPPD`|u%MkJt6P|^rn zI$cR4L@}ZOg@Tes*wX1r8X<}i0VoudG{TlnSJDVk4DU~&prjGDbh?s8h+=qt3I!#N zu%*+LG(r@^>r*HwY1{&w7gy2D);pLJD#VIBA3}P41)-AqBYxoHW9AI(O2Dkb>L;P8wl5ojYkn zNI@(JO1Wp>^-g7672r0-% z;G_}mJ$KTGkb-;!P8#9fb0>`mDac3Qq!H~sXVQp}f_wx{8c{2!GigLfK|TT}jj)x| zoirk(ARmE~#(5yRyOTzQ6yzgt(l`qsxsyhSWG0Q2kHASI+f=iP|cC3h`aV*iZBsys%<&30}kP1y2PjCIabw=yV)-PJWY@OBmRqO25IjwVB z=e2&_I=^*6>%!JWt>3gRZvD1(N$Yp5OIw$W;mTi3L%ZB2pesViwz zO}j+WIG&Wg=u8^nb2C@c2vH2CDHN16!slkLq!FSRk$^%$Nh5r2=1LkNiV+1U6qGc= z=Vq>?5uz9ofI>k@BYbY=N*W=G;r%HTlr+NUX0D_Wq8Of^LP1I6Y_OAENh3rtygr43 zlExB1aV3oq#qjtP3Q8K^1Sqbg5uzC0o`mDac3Qq!I2tchZQEf_wx{8sXk^CyfXx$VcF$5$-*A(uk0P zd<0G!;ofs6jR+~oN8qFp?LBAGh>(JO1Wp>^voiK+JlTY8w6ISgq#z%Glg7Cq=DL$c zgcRf>aMIWhkzDPm*rp&Kfs@8AfaFdZp-pDeNcjkyG{U{-P8tzXkdMGg<5H9~^1HD! zX;g4&(#SSDku;7cdX_{djij8BG!jywN#pgc8(KHEZff1!x}|k%>$cYItvgzGw(e@( z-MXiBZ|lC+{jCRD54Ij^J=}Vv^=Ru4tv|LNYdzk2qV;6!sn*l2XIe0Aa3zhZX_rVE zS0tq`Ig`d3xCFbBMu=iCO`)KqaVbD?C5;fphy)Z0N*Wgc6j#y+QH&@+p`fI3EauPcPEVy$4nY2Ae=P*Jw$RQjR+~o1>mG{ zB}8&2jR+~o4dA446e4j)kp0@r{7vHoLJD#PIB9$jMB>gMM>2lXh>?Qa0Ztm<4w1M+ z$dQcSG-9M6mw=PT21HU9Li0s97%9jt;G}VDh@>ur=8JGJQjlxFN#i1j#GOOFdd6=W zF;b9wz)9nl5J_DK%@^Tdq#zf8lg2@SaMB3(o;ztoNI^aVCyi+DDIa0} zrV;PGARmE~#vZuKm5(rg(}DC>kwNp+(~x^WL2I*1Wgpy)*CKdGF18f8Gc4KAiW_ypQL7GVjxQ>*lSWw>H0f zevkZ~`MvUc=l99)o8K?LfBt~{f%${-2j>sTADX|53{M?J<2KGSja#R(Yn??S-O}kO z8X1bw(l!)UG}0}dj-rvF7(Iavg%yo-OQ)k~WGF^2U_)U=Bi+*JC>j}x(F52}SkXwg zbUKPghGMY44TTkrbW5kBXk;h`^V?8Z(MY#+I*LYyVz9mqg%yphBwrjwBSSG5--g19 zMtVJ!qiAF(2HV?ESkd?%A$w=h$Z*V}(FVkeMz)pHRWx#>APV3`BiqX9DjGRb5DoC6 zk#47Rt~7F_AS&QRBi&BtTxsM;L3F^2M!KEOxzfmyf+&F(jdVMmbET0Z1&sj8bq#%yqMI((pXVJ)!f;fT~jWqV0MI%QF;s{5%p0jA=NI@LIi^f^3XvC0k6^#T=6pauVmZEX%RI*C47mZdqqiD29 zg%*v6=a0xAnLjFjbpDw9vH9cj$LCMTpO`->e{%km{HgiV@~7v|$e)=%D}Q$Wocy`@ z^YZ8CFUVh*zbJok{*wHq`OESrkwLJlXpA@QT2>mjNoDtP7L9aEr>khBC`L=$P*~AO zw{*ISMv7we1U3{_G}5(MSJ6mOj9$Qo!iq+^rPEb3QWT>Hu%WP`k#6a96^#_dV1FA5 zD;nvRPFK-LQ4Hp{p|GNnZs~LtjTFUTeH#iZ8b2iY;wl;`ioy6c6jn68O;B7#BSkUT z-iE@8##c$V;w~B~j#)I?fOyf!wsJa)Murqb0la8rTRELYBSQ+J0bVrH?R4&7w@oz7h}GNd3{;6)?d(&R208B!26@S>4! zr*jvL3@L~nc+p6=)47XAh7?2*yl76}F)MKX&<8%OY>k;b08XkV*qLId)yJ%!cK^(!0MizU{qLCp5aRe_K z*;Yf)|Z6 z_S{7yLki*uUNm;Hq7g@W&Z04f6GbC5m!)XjCY7v`>_wwh&L|o!QlUlT75OXkKgs_z z|Fis6`K$BSt?Q^k)jyP zZ$n{4<9j5MT}2~BF<9S*!ivT>2#Tv{q$mdC+fZ21_!2>J6^#_dV0#-1D;l3AWbZB- zDUMk*+JJb`$kxi7MI%EBq5xhr()9}GnZ|7xQV3W5`XkNMp}k zG%}-jhGZ|2|1 z(;G)!MPs~a*DM+r&QE0zau$vB9H6Ucq$tUjwxY12k)8u|6^#@n*%Me%SkXw&0lJDt zijwRFtSGE#q~`!#MI%K?_5fBCRy5LcfUcsEq9obhio%LUdJfQ4G*Xl#^IK6^(MZn$ zx{5}Ml4N}=3M(34B;}l|Xrw4f#V*qLId)yJ%!cK^(!0 zMjCtWqLCp5aRe_KY3#X+Murr`5xi(*vF9ur8B!2O@S>5O|8uT1GNd4m;6)=n|K~0m z8B!2O@S^c$(!0A?8W~a$NARNYIfCRa8Yz-dG+H@=7mYOb+(jcp3gQS}G=55pMtCz% z(HO&F(YO%4FJTsqpe0!)S&K%yT(W4iNre`T@8sXjzn6bM|3Uu4{73nZ^Pl8D&9BR^ z&#x`)Uf83sXJN0x-i3V%`xf>q>|Z#baA4t}!oh_@3WpXBD;!=pqHttk8X2BCipFhS zXBrpwrm}}Qi$;15&`~rp6r-hWD6D9t>zR(Ck)aqpfenQfjdVTJQ8Y3XqZhEDu%eN! zXF7^ThGO&pHWXGg()CP7(a2B?_P3$1qLHp=I*LYyVlclAg%yo-J=0M%G8BXLZ78g0 zr0bcEqLHB(jBi6>MI&9$bQFyY#bA3I3M(34B4qC@8X1mRG}?f8(a6sKxr#=P6hr~M zXk=@euA-461AI4$Xyiyi^uUWox~}9b8aYxBMew4L z&h0xd!eK~e(P-lcUNq9!a~6#pDTpI@(MV&@Su}E_AdcWgBaJ<0(a4d4ID!|AH1?cD zBS#A22wpVO*mD+*94Uw+c+tpW&s8*Xq#%yqMI&3&bQO&pDTpI@(a6>`aR4D1*1QOZ zBL#5;FB;jJrfa2`f)BBzw_ll{1P)i&SXQcy!^I!m)+p3da{tD4bY0sc>@Pl)|Zn(+Z~- z&M2H&IID1W;he&`h4TvM7cMAVSh%Qgap97}rG?81mlv)mTv_-@;n~2VG2XOmS!wJ` zWshRqLH4#a;`LTq##P*MI$|fP(qLH1!a;-G7h%k#r z8%OY>k;b08Xrwk7x2G<&A@QP-#-6)qWJp0A!HY&3d+wrnSX0##Uw z#=catO0pM?Rym_+v`B>(jXx_~Rk*rvP2t+Yb%mc7t}pzea6{q7!cB!=7H%&5s&Gr; z*1~Ot+Y5IT?kwC@xVvyq;oic1gAF?s+S z3M(4vx|yqJq$mda+fZ21NY~9=MI%KqnBRuNibi@4&{Z^26od6`D6D9tlPs>Hk)jxk zZ$n{4V*qLId)yJ%!cK^(!0MjCtWqLCp5aRe_KY3#X+Murr` z5xi(*vF9ur8B!2O@S>5fl{wEevR=bD)40$U<-BO5=l|SABeN-pBY4sHJn7xtMI%EB z;s{&s{V!q#%yqMdJsoXvA^8vuKRrM9~NdY$+NSq>@#V zy=b(`8AYQ-Dzs>PsPJ&%k;0>e#|n=Zo+$jj@MPhs!qbI66rL$OTX?SUeBp({9}6!Q zUMjp?c%|@a;kCl+g*OUs7TzknU3jPPZsEPcf7QQ{N~LDDHC7D|x{5}3tMOl>sq9IXicu+Cvu4dX1j1D@QV48jHw2W62muNK;xq!`Di)DikRMvc4MvszihUg#d8~fpArc6awkq4FM%0 zLV!Ym*pEQCN<<2QJnx2p`Vb*NAwcXwAYAn!g}_0e8v=?$gaCyA@nZtvDh??GGP@fB zDno<-g#ht?2!yLLq!38yZU`s~5dstf#IE(f!R*fAZ`@@e1rcST8wF}YtrK8wr7+H# zkiqzq9121KBeVQQ3WI5`Hc$5b_3Y7Avy0o$p8p>U=g(i%+qW%)@h3V|g91io`n41W zQ(eI!5Cj(Mau|QoLlG!o zWY(WYVd4Rv`Q1eh<4=6300oT9{4*#_yd+?LbdkgOlOM`I0VA{jBnpG+ubgIlagoFL z2>@z80V5gU7z%?FpkTIjN1C4mpzsqgk_8SUFzzj;G;c)V=Vk$@`Va_%Z?7BD}k$gT0S0F-tDMzX+v5Eyr9N39X1otp)q zu0t5q2`oS(&0W_q7(WX@Q72#|3mn$yXi25SP-hf~v+}hi-~HhaW-sXN>6z~&&rw~@ zQJa$WOH|8wgs_lviiB2i9~3?;d{p?j@JZp*!n(rx!rJ2Q#XX997WXRdUEHU*Z*jlk z{>1}|2Nn-19$Y-6cxdsk;^D<3ibocYDjr=trg&^|L=7becN%k5af|gKLm?LpCGlTS z#hqrU;*>&Y*Xs!c4)OBn@!7peXETVnQJXGx9@Omzk0&h=h@vO^UoU}U!6MPV@A6^uLId;JLyRh)p48Gj3f!IW1p?ws%SCp}bg z0!C*24HPCGznN7Wk2HVcLlq}rWaeK(VdC+dS;cV}fAT{WCtzguUrAx&@msGu|9kxe z09BlTkqmG#g^9;+y>1TZ^^*WpaRNrNz_|p*S;aA@ktz;#*}8eC;_y$ZildR{tl~I~ zp9P?b6EKnmXrwu-I1b}y0jS~xjAQ{CY0fH+!}wVMsyG27S%5~Gvx?&|einc#PQXYO zppoXR;y8?-1)z!(Fp>pWq{S>?R&gB0&jL`z2^h%&r_+FrS-`B~IEn})ct-Ke;#tMBi{}*2EuL3Azj#6M!s126i;I^OFD+hHyu5ft@yg;) zia#y>taw%N>f)c*cfr~EEUc;FQrtXIVHxG@V!f*s#h`}k5G!$F9quf%f>X+1c=xSX zI}Yxoc5`e;v}0?!w70aNcG;3&i?!pJPHH!YbVNH+xl4O%D{7ZCzGJK%hjLQ8Ig%sV zk-=Ts(`nQ$*?VQI9Y=6dyE%X(+L5?j+A|r{E=hYh){X-=sofm65$(v=F74SYYL{Hy zA8SXZmfFoSjc7-jc4=>GL+z5H|1#E&1TD3j6&lfw?CjE>%b|A3%v;CWk(Z@*b8tqq zBPqMIx3{BqNyxpicBEse-5iq2$;MI!I{0H`f?#mohlGy{(hGrU;--yX9kPH%Y`s)nm~{_{B44O zNvsf@S={SOLPO=Bs}X-f%3`X8|l=8C1yeNG_AoE{|6 z8t1g7dZGxvoZey!fgp2wJAx4Bw54#O2)-`*^Pd+8GN-pC2ysqZY9@-{>!!c(1%V)Q zdO?gJ$|c#-3!FJEswG!DeDRBjph_hYOQKRz2+o{d;LGVPw-g96r!&oB&kU)DS z$4VD14fHx!Y)7&>i0UJ!2v$c9fzaCM+TwM^pBJw${-St8@y6m!#a|Y0F8-=`OYzp? zZN=M*cNFg|-c`K2cu(=(;(f(m7w<3rruabd!QyX=zbigee7N{X@f#~v!+Kv9YaLi- zyrAXr+0V~@WA;b0*UjEz&OUPvm~+USBjy}4=Y%<@%sFGuIdd+UbIF`5=KO5VwR3Kn z^Se1O%z1In%X40x^ZJ}O=e#}V-8t{i`Ebt1b3UE3e$MV)dv@*JwQtw{T?cj@+;wQz z;ax{|9o=$<+{ zhOV2sZtl9J>$a{ty6)<_r|Z71`@0_K`fb-kU5|7<*7Zc!lU+}DJ=67E*9%=QcD>y7 zYS-&sZ+5-i^={YuT_1LR-1TYK`mWu(_w3%gd*AN;yASL>xckuV!@G~{KDztZ?&G^p z>^`~s)b7)}&+I(f&%1Zt z>+=rFU!MO>{_Xrxg`XCFS9rg0T=AOXqs4!(zW{MIt7F;VF2gHe^D9J~+9}(+$XHjM z-#=fkCTe*Ixh#gu6!=A>fANadjsDS8YD#u{&>H!$T z85xXH`P^(Kn{CbHay$I!yE}dBd#TB}TxYg@Ubd}cR&L+0C=X!cDh#bY>=Xc1(`ntd^b93BH*MzL~b>%K9|)O6fbXOCKz*CkI2s zFG4!pCz~*zr2mvYxv#lTB3$AV{btN3C)a19Pddg{*Xx5jiQM=z;tvo7Z?yW;JlnF{ln^PujAYB(g=dwy9T8!4 zgvlHVgFi?-&KnkW; z;;sQFp)-lTA&WjkZ7}_DQsZIaLeHRwAy`}pk0()Z+>>yjU5dNVCW9_qx1M!4+=ajy z(!a!oEq^E;ReuwH4OP{Ofx(@@d1XZlMYBa|ZrPFQ2jAPvuHI3uGRQtH& z*!m1L(jqXCIDUD&am=i?#j)iD#}mia#{(QN(K!CMD31Glajabcaom@TW9#elIJSxe zSQrw=uNGe`o;1!l*1PSS#_@vGlyS$g^%-iUMPMRveE)dkm|1O$W6KMUCyuR;2RLA& zalCUB$GEKO={{y* zYWle2*!m1L(jqXCIDT-Pam=l@#j)iD#}mia#{(QN(K!BE6vw!D?~3Ed1rW!u*2m-6 z`uaSMts(&yhQ#sP#dnH78fP5qVNz2*UXs(@`B@u zW9#Dq4wz^hFOA|Dw}?37Si1n?7*>>d99v(X$FWr;z`~F?ey{j`@vGyEV?9i28pm6u zHXC;wTc4puS_CE%$Cr#Zj+xcAIJUgtc;eXlcz^>Y8pn&GIL1v2&N$XCfH;P|NIZ_M zug~MyDiUB}NF0Ay{HVCyIOA9klbXiy)~U~rJC3c-P$Mk@6N%%a#v8}XYFivzUT{2d zY<)by0TYemEuuKatuf9x)-HfJhTSndj;*iH#`nag5vioN=sO0CBu+GLEgU&*RuC5@2CS9Pd%uv-ENOZ4eD!&+F5}BqNS- zMG)8X;P^l>IFQ{Bp_wj;iG=cd_1w6Y^tjK` znc>!uw!GoELfZO#hz}+j(%+6l8dvz5-=_m1t=)hj9WC)i;c7J@5z+<+k+t@gRwJ`vIzY-UJEA6Po5^vXCxT92cev-E=0!tsZ+^&!@r7Kw?3^xfkP zX=b=Jq%Chau8_7qAL4_FhIAtiX7lpLdghWVNWkSph3F$*hhnDUi zXGr_U(hF1Dj6bBU4>3C}5)%pOYsMSW%y4T+Ti$S7A#Hs=#0L`%>Fwi?#w9>!NNYD> zNJndcQAk@&NQAUiCdAB;kUqS0MCoVa3~4=)b5^B3wtv=oHh{>qMixXuK2Eb~pvuyZ%k2;2P+Bp|C|ki;p< z`5a``h!3QtMS!420QpaK7!+R+_hDOa986%q{t~wxcx}AY2M9-MGkTe?635^vgb?&$ zw72IPN+W>$9|A&rl{g8X0P*{(qeFlwUwud2Ylyh$E7|D1#@6k))ltxA2;6(16oMT) zDu^NGE92;0+~z{i2LTr!D1`v=ZVW*@mAq(bQFeUszrvdiB$`B96$c? zkJrO{n)}G{B+;IG?uma(%_V0hI*u(JS316QLg~cPNu`rZr<6`DZL0&@$259uYcfr5 zDm&n2nmq^zjR}75C^Q%a;W1$Y;Y_n@Ak$C`78N!K#xw_LGZZhV1T~o^f)Ii--{4MFg_i89TnG1K_w0HfqUrb*5L!f#T^Bs7`ED#Mt@BC%mib9(8F(wU{R zN@thODV{2(={3ijSF<~$b1>rGa1K~{b_km19F<4aC zAQ;o^uFdcujSYh{&36b0@s-Im6vXc<&NQQ;OhZAu&SFf{AJc%FX*7hvG&Wx` zrgXX-W5Nc) znMPmBq^g~!)f2^FQDK8%O!KeW3?I`(5C+rOFgVkU5fI`llW8c3-&dSzmV`151@StI zG0lRQ2HZ@eAq=Lm`HC^k12F{gl!a*sgx^z)X>JN+8iL?;6J?rbW2W)Vm@m{A$TZ0r zbNEdvnS>_OSY;T~SR^)#X?|MzS?Q|M)un4n*Osm;{k(L2={X(P9;R8;e4Yl@gGSs; z6U{vU2#tv((=ZSo6E+aeG~Wpu(=ZGc6*dUQG`neEd6*`KFqp=M!I|b;1cdm?U>XME z_Z4TFm4QsdK)lXkOtXDV15T!iAPlCl`HC^kQ!xbbl*u#{!tW`@H1~!v4Mp&}i89Tb zG1K@KG9nCQn&d(T{3ex5LX&B%GK^^~5*x-eHE_a}O1G45E!|c+NC&o$ zX>=uOj%gO9vSV(hiRK=BOhZ9`O8qIp&(voF{bH>X~4}i8p2>2o39wt+#5p>Pg$6T zK=?hynC9n!OhXX7ZlX-{WXv>p9?-Rty+~sq(?kaXqjjaNQpqGVnZ_!^n8qTpVNCNt z>A})(OTQ~URC>7dNa@kiW2H-UVEdRxSBWOmY@Nz}-OV)7+=Gv4CO#xzfqeqVaB^i=8T(jQ9Cl%6d;SK3Agwufo9YCcZ`n;gICW}0a3!NW8R zgvW#pgfq>`Fs5M`EGldejA^2YZ4cAL5C+rOFgVlHb%VgOB!3L1VIY2Aai;lFAk#1q zud^7_RAL%%GED?wFpbSujA`zQA&93;rlAmiPcf#sCX8t)g4a!yX&#T62G7*Gm?pwN zril*KMohC!Dw%{P(^zE~(^w=njA>pd{jv07>7~-krB_O?mR>8pUV2gowvTCam1vG> zwoPTf<7S#@?!m`26okiw4TLkzP$1J#3>FnO2*xzu)V}gDO$1>ujSYh{O+Nu4`C~E- z1@ZfeGfi(O(@+qvvl!EK#Wdh%8VzAEjm=k#X?__)5Kmc{hCui|#hB)@K&BxGUN=#u zc_3yQJoW5k8jXQW6CHbwm}c8lG6_wlvC1%}u}Ewf)4W-FtMqp1ozlCd_e$@VJ}7-y z+O_^I*xu*gBfOQa5+kOWERR9Mo*~#I{10xb$rBVB6v@RWh9ZK(jl#KR6P-UmXz`BD z#J95M&u1VQ7j6tjHa*%9AK66i(q!WX;cPR5pb&SNY(r53+{Ni;eSI}Hz24W`bfa+W zFR;b$FUB`-C=5X(kVCyVbvrzVhuA zj$8#0eos-#Ilb{R0OXKGAfMRB7>xb;5sH-7+l8silKB|1jz%@3asU;x3bSC`y34IPbh3$~zRr?=QwXPsN&O1{H3UQagI}9bjU7UA53FIAy z;`bNhomXQ{aPm%sVe*d6U5s}QjxmU{Ox~dw0nTE)^WR~-Lm~X0qP%ko;T_yb?BbmW zMet6vm6#@EG9N9x)0eUcao(|rY#8qxT0X3Nc=?F(k>#VxN0*N&A6tH0hq#Y-bUkSq z@4&XtAG&$xa|DIPhQT`&B@r7o6wW*CfxJUOcy!n>81HmxLwvjwVVJyQ1L3@rB`CyQ zCht&`0C#cTc{`MMD2m@-jCY=mIl;|48pGrro4XkA>=k1WXIXfMU<5de@y@>m@(zLU zdy4YT(S&z!U$K*SG>YJzXk&5AI}1|De6;Y6RfzMBMP$Qx=lJpoQ?Q!{i+s2Sxd51vwJw z?@$mP9X1TcJ003xKHiBiOy049aNc=^ppaBDd559|xQp}7qoKS*QT+a5ymME~32xre z7$)!7+{Jk3pJEK+EDP@ti~wgb-q|IPcL;>vQ&G?I0bnTwfyDc z{xN96n*8SM0{BdGa(ucnp8!w>YCOYtyfsJD$g;ZTe?y z*0){XB8||<*Q)jVurD+3C^r)1M8n4S+8C>Q+y$5{`sK_<&E+C>;Ob7&q`fqBjH@{q z28udS+S^6zNtJ*zm*J4mF?cwE;|ZOP4uzvaXQO%>Ui>V7DMLqn%C#3h<=SgZ?{c)z z;F%<2=T8+p>mhm&!TMQmTkz=jVZrm9?7>BA_hRrA1t*x7B5@zMqi5Q*NFTK7eX?(D z9|8)Y!DHT45@9G&XYfp)9%}@YGbsuQ9kW;BD4x)nF+-xL$T?h+j`*Dn9QEPj-fbap znx_LA6dE@h{fXlS0%u%tqu+|J-=m3lA!wlLlab?BjoingP7LQT1yJ?-_LDy#IK31HqqR8>iaK#Ld25_+kOZVKBF*hMB6vJ7D$O;@ z6OFH6T!7^*lB(jkuw&ro)@4U$^H%y->Y8=Gpviq6sLDXV{+)coG#X}klTEqb+WIbT*?E*}yMX;;te}|TJ2v<|X zuvwabX;}}}^y#rygxad{TY$<^i=xJ9f`qbqlSb^rqzj{=v{M9A*CBx8t##|xHBa7_ z78n!24^7_m?d3blcb1Q0LCEQ_gPtRMkQo$O88~kD`bVIC zR(930!CiFV{a|+QBIr?!HqsC%%Z9K3lSC0iSZS0V!lHrrgM)_7T-$EbBEqvj@BA~m zv?awxA-UWRKl<)Y-}+u^axT}BTfau3<=Q(sJ0`WH^~=<{HkLTjLH8 zOJfh4OzBmO1|!>HR4G3OB$(X(=7j3)0$$Tn+%!)0(rO+pt#_C2DSs?$4?DN}MN2txr%Vx|_Xxg@d3W(7$#R4iI znx~JH^jNjgMmepKL>>G}+M__4=Z}>1fNZ=mf@n*0)D6JENhXkthQ7oQi?opv^}uYh zNqeLdjG3gO4u2=DQ8(h2QzJHcW0H0K0-+;7hpz94Y4JqIbAB|A0-M@O;l zlI^pgdA2H1k3Cy%*&gWxd)76eib-X~$lLWHN5Tpyt7{NZbBc$Pqjp}mHWP{JR=WTe zS*a;-%{lz2soq2-^7i^0#2?8;PaC_h;KZTWZQhsqC^A1Oateysd> z`HAxH%TJb{DnDKRL;0EVv*qW?&zD~)|FQgH`K9v9<-c3e0BspyNC@6}FBV@ZzFvH* z_-^ro;>X2x#obGLmG&(iP&&ADSn0^pF{RT=7nFWd`bFvX(r-$Sm!2=ZQTnK~SNV|g zapg107nOfjzPWr``L6Q4df2^L$rOwK1kA~_W_}oI9(gv-ViuLy|i}dqQN$Bri=GNcRg8ES#=wBM^ACBh$ zIG-o<5955Na&dRk;&Ae8Az5GV`&GO;(l^`@LGXOVrdkpMTAqJw_f%sIeH4$KImP9&n zBd%bdW=_*nv;%mduWWSq-&8J>)cNO1=b)I{cIwA}{Gr!O&n^z@~Wh4#%N|A_Xj!^}f_LN!hyWyPEs0L;y{raRM_-PW&d zUDH?pF9q4Cj{qb&35wlKGfWT$%r-A(x*fFRk6d|Gu^|Xhz+VcJxe(3x%4*s?nrdu< z4WinK_*6D&Y3qCC_sg5E*cjD9Rzgl@-zvXdey99y`GfL4vaZhz3@w2`m}^@$Uldap zNCDK$k-^d7{?$7+mJBskH+F$+8Xeprl}(KqQ#(>E_VdPM==P>1-Y?y{P%WavN+{Y)k77$kCxgygJ`e&>)#G0GoaNSFwd?+NMwa+z%P#ABXTkIRgd8+U$H=Pw)kFO|%!e#rYmQZvI%tG_)SMLlrWc!C&aLq}Dv5v}@pM9DGC8df zFuI8mxSd;a2`>eb5U`QkiO}9Id;;nK;9_0YfDxmEIHZ%q^ThUvBnF6jP$o@kM>~X0 z!1*h=_>vu1z8I5Iabj~{p_~U{>Qto-)Sn)!$Cgm)d8tWl0QJ6xm^Ka7%X~Yrz6#=N zW@e~=IcT3JH&^filWGSs&$~~bE_K1H7nSbCE1|p6x_MDab%U5k_ly}Cp$l}c)4B&^ z-HGWKrhCw*dy`Evu(}{3=kvuypMNtR5{9d-hAfFtkedt-lx>#)OxHwF;XY# zi*g?Ivu0(bHc-{_WVtwG#+TiW~CRUI8 z#AT-THIH|A5O#<=32lolP(5e^^K-=kSd#rp)T=s0uqSm0VDI_bm!|9ruV|lQm~qS7hl)RvG1H9QD|=M- ztn5|UyRuJZ-^zZK{VNAl4y+thIk<92<p^6*zRS`YxzC`<2GXaNJsKq(*h4m`8a!t(1ZGg-ZKypBM*9);6V=%gH!!MD>cBb6>)*tN&502o8HAgoFAX6jJs6WFMH&I*Y6^mFpho&; z7sNn(%`kbg1d$DKg`%tBzDCUDi6ucAqbTRGV#*X~3DgEQTo9{A3)HxUR}KmFzW49! zMD_CR&x+N@T%K43OsMz85sbP(y^Nz%V)ZeXCpMiX)Kf0Eg(-}>K)vL0wP7am)jQHN{iK6HMIgk1oGf=(s{g-3)#P{aVov8Quexr?0z4ZMy zv3lZrK6y`l4-fi$zwySXUiw}yhVR%|JUSL|V0)Fp;#b%P zGJ`E+83y8Oh0QmYAhI34L_x466iD+p60hTHi_d*dg2>ibNI|eY6iD-E5+J@7*YpwB6R#=5y0`sKCN%O0k3EufBfgC z)24|(lJUnTM^=ui99=o4a%|s+?RorE+TJw94s~Gb(3R&Z?YUIj6FJ z{cqvfnH^)p%Lhm2uSN&RLe=b2qPbBeN{o2vG__Ih`Y6SgMlP7?>oGXk6Nm z;OvWfeHodPDAHnLlUe03BoOu3)Y>YMgi^5SA&wN=WcD-(B%e*`v__IP-OrIQ-=z1< zfmZ^FCY;TCnT$q~DR&n~!laW(<{&JAM6=F@l+9`+nRmBvBs^v&kxU9nAi){4sJO5p zwY6y^PzvpI14qKE?In`QBMBt9*xreh%V{J~3P{&bq=h8*%nphnfv5)wc9e@K7fJ!? z6^<0gp4nF=kbJQR2Z9umjJ@a8E(-Naj6J!F!ZMkafbs?3q)8e|2H#bx%p6>fO9^U1 zsCnRln8$0=re%aKaM+gAjIBh|C^J0q2C^O$*z7HwBeVk4*&GVnMnQQ3ZmZS4#+flg zL&?TDl|zxn@kHEKt9^~L(MB3dHqP;lSD~-KeljvBURR1YBV#|Q!vJNI{bXM%*;g3- zq*a9WlNJH&CsY6NLGvx_>-WuJH_5iJPdl%2e&vG7g_Vmc7gsK+Tw1xTa(U&7%9WL$ zRDN3dS*4-M#l-`p)HQp?XtOeikw}4?QKp!^Vpb}HD0w5+jt*7PZuEvkI}Hw-c36%C z?J_W4((?<;alu^9FPI^rmG>_fySUUGy-jy}dj^CA$(2-=ij_e9-e%{jb%U74D^sSZ zRmC-Hu4p`@f-DN3So`tRghXECLv0pS;F4^(Pk4W{4PL zL6*6?a!uvh%5{~4eZV(Pz)S5SudQ7^ry1ZEdeFfK|noI$5R@! zI=~_GNBZF~Mr*4&xrw9M#F-XI(+EjF0A3Wweko)U5&YPao-VCa3()ExVt9(@COXlJ z9vxm0baix&01jmEZ4bH5j`sL9YT1rSaAIOIoS2xhW>g%G%SoHS%}tN4n;y_nwR{N@DW6MQO>a*Q=KsOOj{qf4X5(gtQ z@N&6H7+3H+*ff#)6-NJ$)r`f_9j>APD(G-a3~wG&^NVn^Fk*Gp9Zc^9O#@zpN2QPVYiU zp2Ucr;efQt9G_Fuohny)z^N^{Xt_NH2aeKhyKUt4VT)HndU^e+%**NMtsbWfI`YT_dNn@uWW;V~wgcQYsWUej+%_e1W96pGFDo}! za>{)}^%bkez&JS*$?d{DD^XvDa+>sEuN&-;PUWVU2cFuLLWtTEZY2A z4J0Ur6!d}s1!$Fk@}jzNq%pQK-hh{wlcXRh=Y@b-NvRJ2HgEh9awDf~j%eEq1CD|o zQnZ~DjI0zSeHQJ-^9W%ixJ6`weX@on7~heXUMthw+>w{QrE+WKw#v8a-vNo4?XZ$R zGSH8M0XeZ{1V*o(p;MCDrT9;HF1v{t8nIIF>eUP=o^a%o`QXw75RPMo8=3;aZXNkf zpcH_vU_dyYRa14zFiZg9kk$xe zL;~>{7ZV7lLEIL>xj1Q&oCi6L0pT==1mYZP0^ux(8wgIuNgz25asmUwSr7@t>t7QH zCqdjmZEXrj&Vn4pfbjcX5{Os7CJ=nw%LA0lDIib^QFjOf!q59iAYSO0K=5rJ4^Vr% z0s^G~w4b^UNv2)IPUb9e600AE@Uk?a9!#cfRGfH(fSu&P8k-gJ-_Rqf;B}gsEIa(x z!w3g|=w7dmJ1Tcp?yB5fxubP%79UM${ zE`tqQ;KSXQ&z* zDb%gOC!i|q=mHFbK07lVomsfhLm$(S7kU7F=B7e%IBiY3@dxlh7F!pbtQMSYJu7#B z%0Tza%b6Odhr;Z8gWJaooN3CdW`UD^yz)fl_mw9rPgQoWzlKfSHZrh$0Q-1tXtJ(f zv@o8d60%?@&QPVr%nclkgn>?KfM*~u4V}k;87k2=x}Wgsl&lk-kg#=($+;8OF|K(~ z?N``or-9MNK$JnrERF4zf{;Pv&C^L^vyi4*BhXEcTJnKC;4t74Fmm{mOw<@gi~4}l z=?*O_hP`{$Cy5!c;gzFf*u|?RgsGWiUl?NvS!hB$$K-9ojAGQDG|Y#QiK$FhOon-$ z_aev!z0cK+m<`&J)^AnofXT29m<&r#hjGu0HPh7QppjJr=nc7IlPqdtPoS931SvuNJK$6oR1Vjk>K%j5lNoj<3 z`&xYpW(m$+4J<~cQ&X7Ga>>#<29m-?p7f@Y7740r3(XVj^DIwn5;9M=b2Y0iPxM+Am|5$mk@>1m= z>o}gCl^u``FL)T%D{Wm|bg&jg!BF1A^`%-9fh?MRTJ#D=4`+RXnQfDh4ILdPw)Jo^ zrd%E1J=_oF?Xa1FoiNZv$@hcV*8U)}cPBKL_Xf6CgAQHuuD3U^J|AfOXVx3+(0E2i zIS$BOQLcS~Q4VABM3h^tNzk=bCeY#=T~WSW6k?XU3iS0d9n{BjHAPI)M|_qY+tHWtban5;AK( zcDYf9uC>=|dA+hWT1Ok4k7cNRAt*k}3Rf7;hmKv&QjQGZKU3*U!anHiVA)J41V^4r zAdq&|uJ^=OwD z#)E_~hqe>~V!;EEP74T72#z{BhUksk!W_{Oh+cnNWHJbW3IXCc0ui@Ga#Dx2MX$dt zV96XIWLq3TAmX+#2OQK2e_OP*2?#kMa1eor+rk|1QV4%rz!xmg3fUI>h;L@+boh~> zlQ|I7Fj83OKaH(qf*=7*#q{dB5^O<($}?eR0^CW-d}h3Qp?dVFwMLwNn5pgs?k>K*V8Zj&>;o4?7!# zq<}sdb|kX<;;=I*fI{%Fvq4A-K!sohiR`{O>`V%v5IpQ`5Rw8=AwZDGUJ$p1NdW|6 zfxj&z1)xHJI5cjH1@JzK$V>{L5dOB16o3i=Vt)b=w}nXo6vE#Yk^&aUw%C(E#BE_x z0EO_kg`|K5vMv6HPyjkAuAZ9bhM)lOmK*}a*$ro(5(#3V0ILwE0Gr4LP{2o(k1L;4 zKCP^)tgo!C?p|%Ey&ABT0oe_<+GnE|&eylwNI}-ULA$giY!pSWQVC)4)d;1JqL?%g zqoAM{1*_fxsS;4e6bh`WQ52I2G>R1TqQGRARtYE_^?!uX;mk>JAtKz{CV|9Ad$yUZ z8Yq(WVr4Q^F~H4_;TG4IQ#dnm37nMm!ez4vrxgR-SJX-qZq1Wm_J#5|Ae5vR3Kq&E zr2zC$;|*}5>}HWETsfxg5;+ERk<78aR5Jdeadw=DRw15aHW8U)OPhDIE$ORV1xwqW z)xD~FSNEyzTivg!KjXe?+5EvB8jft+I_hyzkoguK%UQBbs|446N#((+WxW)|%(fT> z1-&ScZCWLuER0b4D2kbFF$xNLQ6Sq^Et4t%r6)pJKvB%DH%380FAA&yty(5k0!mS# z0J%{VGodw#6!fCN9WPoXp!7#5%wuLA$0$J_%Vv=U#ft;VUn&%!ENY9{2Wu25=(Ppz zo7O4;<*mkBQTk#ayV6$!iS&i0Nv3Zjl?-T0`dWo}`r1Tf`mS}Q?;2P7<_@SHSUsqE zaP^Stq1D5xdnxCRj6uG|n|{q5Wm$1g0pxLtYd} zU_?QcfUM_-0tH)K}iicBT^oIUz zHhSAub;5e|#v2j}gN|exlhK=um_iIE23awj88ie=%CZ)o+ZwS_G^rpe& zkj!scGv7iwBnMI22b&X3@D=g^U!022}IB{mVyF=}F0OfzK;wjlg05(@@jSLfAR&tYP55 z%<@s4j|3`-6gku_gZ^|%NO!JrxpS?{oh_$SE8?i$tQ_pXScUr~oy0Sw+$n{1KIliM zCH%SOG?i_GJMYxrKfFR*$|;lE=%9P`0!SpQwZl%d{!w7WjS||Sq@5HAi%#bsb=QVt zJY0U4wX>1g5f-QhK`#(=2U1d?)MJ!Bf?{+B6a@smD9{}Mickr`H>46;8SiQp3Iv|g z;U_CC`FzrMQT%y?;)HIdM@HZ&t_b{=D+1G}SI?-PS-mpeP}w^yE-Sb16zl!(2eLMiz5pBNC1lqHZcmP-J|6%2a91_Z|)FiM6;K`8)zS;ap74vyfh zM3$1VZw%-dl#umW)!I6VCNhk+D7RX_=V9yAo+SA53Uy51T<|SZW0z;9e*jU z***b}0@@6A4A~4Hx|+eZ9|p`9Kgs-VA2p$*4q#;48~xO8{&WBhJfF) zhS;j7$4q4oIi7}qURwP8i5ue7@iv5huVh2q7j1tRG3}%Q;uR21(ttf~5+^j82!+Pq zhSNaiqUy!fORASvzg&M88fcd2yXrgP*A3KuYsg4*l%^MPFe5=4Y!_L zK;&aig~43d#mUd8G%F$EcQ_D=;xP1KCJ)I?QrN0W<4}<$cm}#zgja zG0CHdR!OkheOBbhj=GdG65cKh*P%Ez-W@Q9OxxJ0pVl&Q0P`6>E7xs}8yBm0)9x<|+X-FD*52s@80t}p28hfb`L2>C3mUMiK)>n#=| zi;h@aU&dhD?ifL7aqU$OnM91n7hW+8D4&o_tu?NYS{o&_CAC_9QvK43evrt3pI|in zg(E8GR<5f2ymCY3SC!i`Ca9)%F~q>Dlb=FtGrS9u(C&W|LWn@q@)ey?? za}xeX|KK$x*(e{?w>fYtNVeVai2Lt&xH4iSc_j%sHJ58iM|f%Yq-#cgjHPV~+)C03 zr`UFcSDTp`5fd8nIvz4Bo3Ih2AP%E9#qNw*mrbXoCJ4Y&)wg#>h8l~p43SYzD9+Fg za&GOgk3nez{SPYr1N|$P$NI@ABB5W%x%I;)2Bi)3KQE4&&dlySJc8?z9b$j5bIN!zb^_d8P!4 zkcAi)x9vpDoNQ%r)s8+yB)|0%jXELx@Wv24^)kVTUJvJ8Fl*HJvv@>Dcq*bhCeve0 zQ#$8m+onQ%Pg~Qdh;xMRBx!>SbegN z2bN}K8;zx_pp~tsAC!r@nnF=%WYKv~l07keU^10Sba0~ko)$H%{Ir(nzTFR@%t>UvkSkko<)iSYgZ6!`Pm1<+7)Q6pn2D8;hk#W0`cQWY`2OK+oQt|Hrs7v zuiuIV_QJ;R;8nBz*mBXJEpZn{!V@S9o@n*GWVS_y_ry(&PCZCdd5A|jOz&3vW%cIj z#`WjHv{~83t3+q6LYm*JrcBf8v?!`WxWs|1D@s18HDQ3&}(4Sjs ztXPVtVw(+7wMQYtmJWC@V2mon1i)|%P>%u3F)9J5`v72&3IM1M26c=hOm7g?#O3smz`tA!ILY(^Cj0siYG^ghIT|AlhrW& za!JC=LeTBzsZ(LHK&S&h>yHDC42jPgHO=1G#p1(8k?m&uLGnsvpnbc>gW%aT-WsHj zp4vwpT77hFjl;Wo#1Xy22DQ(ZXS4RVgH9#F^c55qBH zm}3Fk)To2cAj+1B?(9WTJ?fByCGjv6A}oK!uw#7`k8&VA1>?>AkWWGs5qb*I9C&nQ z+Qp5SZIfVjVDg&piiXqXsaZa2(u=j4!p>IGe87L$R%P z35%_?7f58>_hr)wRi37c3^ba~{vw(%W%D+Z*#L6_n(pE1`SNSia69ARXn%ba?l_M& zU9M6e)|O1!7iFB3gkDSz&KmIP@$B40tHGj9q!I`GyEpEG2+5#qtL9@xSWRF+R0n>H zlY{{}rsG6ZZxKP?IdotoM9Vj}>UJ%>I{wgcV#}k|zpQtNLD1mNiwCd^RaFL>ML$F- z+_z2i=|Le4mXS#e_!Ugqw3|Im`g0Q4H8Ur}rkRR3Z0r(fJ9ImukhacHZl~U0E*T5y zw_=6Ht};Uej59-+E23J!Z3ZPbyCIa^>=G7Jd4_L zccXb{V|GMngVgz}`d-iY4G`Nxg#~h$OqS~s0JvYm4}oVWgrJyFxG4tdBOqkm&IAELpB-?7 z0ziaDu;e=Bs8s``rOC8N0s_T+0Ps0YsSVWcpjx`2^vjk`Zs3bsTFChT;P|o92MB{Y zRH*@E^)6w+NPq!&UUD=8>@(aNI{rTk7B;pZ*R{^ZJ>UJYUAZ2I}VaI=3i){ zsU`(|5FH&ktr0-JrgkikE{5;4V?L`bugw!$O8QXXtDssXpnN?-8SJMh$(^-vV?zfG zl0FppET|L|NwHR;^e-D?wlvReDd|I*G6n9kmny-QJ=G>x+=L-v`nwS%K0Fm@RsU8 z|J=swz=&;<{o~ma;}Z?kWkOhuh;pR!NcJ6gGe3SY#v|jEP@fk`={nr=iH7MdVzvs;^dGt9GxL3^r$=*Mrb(dA&MA?SmK{Yz#L0 zl*2;Ys-n*^p&U559S$_X4iz}#kh+n7W(DTf+LSi%@wdfiFyL$Fcs@)m7xIDx8j%8! z(*O}h5+d3;I@uZ&v?Zt*XEwFx(Za<~R5@ zA7z~$wWBCRkJx~yUJkyFnebqf-G?rDVysQyg!diZrlv9Bf_9wBk<*xb=zxu=%|x*{ zNZ{l_(nQ$mla;z4MpjFHY=;wTLsRV5m44ja_kVlliR-}JM!^^0Ry6L9QgWUtP_CtRf*degKzGF%OpGU zK?Fq+a&8FN0jRWr{<)0@kSN5t5ohA+HYcYFT#+hoE^U-7qs~=R?X~J7II{1~yZ+uvRe$(>@qbL{qtq%@fC(>0Ap40|@E9eRTRpOwP%oIMJ z;OfOOE9DQHcG&SZDs+MJl1@X2e@7bXcgOH|zdEL&&;`o>U3msLYS_9ZPH~ymF67+m zVYN|d1O5M^^aCK#Z{~&8FXY_%VN|WOf&Rl{=fqp?%!DB72i@9XObyyW7byR}I9Lhk z08Qjf2dy3?)i6Q#LhyOVMC2saLn7mkwI6HysQPjBlj^6{ zb=CFNe^5>D@n!VVZ9O|Ua@6SJ_Qt+as`|3+}mc0g{P^f=?tStVlMLRf05>?eDUo{>9Z$hlyrt z(on6t*Y>ErriL7i!G0LP=^=-4Gb=DmwB&%IY{&t>NKH2lY)Max;PrtAK}${KBXjM4 zm*z&hlFX~+D4u0M_L^Pg;${}qlDMHe7a6WkIJlk; zGW;_;+wdhB&*)@lJk$1O@oaA%b*5*+cCK~B^P0%7mIiL!tG0LTP!-S1hgbOGS&uVN zl*KdrBDKjl;<<@@)U5WuPdJ_zsCWkTzIZ04@_4qt8r^2+isvRz2O0jE#q*~!p7CAW z@l2e+;<qX(@xin-gJyH;|I-)zU zV#VL2HVX@B=L2Z6OJKr5y-M!!682(LD|`9&QQ4<6d!w*+y`2%)(MH3x=4t2SVb({R zM{QkHjHnqb?mLpF&|Yf%9@;)D8ZYXvY;zsV6FRn?mdN0Cii8<^ql>QNMJ8=5{XEtI zwF7JasJ2G08XQ~(t?iic=+(n36lK9Jp8dQnxZ`eEk3WRP%^rv>ZXzIqJ388AYu*^q zV)2@*J67FasA2q7|?=qU7a&d8tXJe+_<*YhtcQ<1+h{DhK$t%}f?@gM~{^q!MN#?2j z?-RAG<%rq^Y6!K<;9}nps!tE0gsi3|!K(P1RMFOwCNDW3K!aTZ6K1BrS3@X#V={z- ze#V%0VfIGcisTqkM{@Ha)M<@h;}A-`jkCvPp3sr)bcCFD zc8Y`nxEKVP{JPL33I~oBV59xG(dlZEF;WMj%2jy)QsxhN=XWPIs z;S(L`9*ZQ4dxS#GUfVp}Thi_co?~mr)qYt22)pDCuvXW^wXZGt?hh@WlY*LffgWaR zaUK3sRQQYHYJOP!`<_7$cw{D=0Y9zJ!p(`=d`tmlzHR84G(XA#&ubb<5SOhw349uY zo$;9sMVB^Sg~-4qT2(PCZm{J+(lI&_d{)U!@JR*RK7rxs3AGbz=hZ*JTtJgmO&Qan zF+^RUhi*zbnF&I}LR%)pNvVgb+5yd;p$=#wBQs&c$zaWw#JA>6+pW!Q+Ad0JpB=op zn^+=-upUhlwYKHt+O_HvBXFQ)WE)6(xs+x$vmU|q2PjskPH;U3J{`Fe{7pL!+q)E~~A2xPqdlrS;Tb zB-#!wm0xX&oNpE4mfA$5rQ;cgt~sgkFxZt7?Se<-nq9SzeXur63jhCZTFV)=EmoAk zxD2=z0(Saa)eoy{YkSuAsqJ4osCG#0@Y<2JV`|6OPO6n+CUTt?chzy`;XZG5poRROXYm?Ll4igWu}TtyeYAT=-VE z{B(7|W6N3{rI*RClNWkL58rCU6jYfow(h&975I=5zhp*N`N<(hj_xk*XQTgm<@v!ow4 z%gC#{_%|r)+D6 zoLXzA-~5)79@#1JYu2*x{p~D#e>*oFl5z%I@BA%LGZVhHJB)iD<&H5v_d`8|Vu5Xu z$tb1J7$XV=Hdrr-Q25?Qih^Q+C~$T{Dg~5$15cz+iUTCw`e(A-vuA^jujm0yGC@r* zX(mW?d~JIZZ`)jMhaY`+r*C~PH96PblKZj>x4F3_zh*9|U0A!Qc5&^k`g*9he%t6amwm{Su;COVlo&gJoEyfn@ClwU-~c6|9t zP;5gqcXsBcLNrfXbHCh$m+2?G!Z!+2n?VYqjM|z@8jH6A3S|&pOO*0qqTI|B?NE^N zD$isxLK!HpDdhu;v5Sz5XeNkO4pLs_*=$BA1LYgZuc>EbIK=zX`1VKY8W{_M2dRIO z?hy>AKUwZzK#z{l$k>i&hM)EHt0h_QgnB1-4w>PBox$5`pxp~Q+4w;v>JbptJ%h)Z z_&Pu7k?o?CC4GWNN2o{OQnlv&Km?qQ`+@j^7~T(@BnqtzCVcD=<1h+!NPM)}m-vz? zKO>7X++xm-A1jkhc5J(}c3JK6+7-1cYd@*&FOqE*o)j6GpK6H+QrWA{Jj-!-w6#qL zL)LXFZj=w_rYGo8?ZKAHdwt6FM?6p&j+>}*7&vW|R6d)$d7n?Yp2$GuupgKy?@Q%2 zNh;r*C|}@Ht_P~99QLp>oEl?-zuSet5ojuN#*Ym{ zfQN7X_)3Fl%^hVywJr_Bqq*5h&81kguQce>F%GI|X@LJs<+_rZyX5)NOg~)z(V{v+ zoVa3187-lM6!F6doFEy4iwF`rVd6@t!wIGRBJ~52daOK}sfStcD72fYhpMB07QexBUjpINeM5Z+#$OljV*AQqs1(j=h|Uw;#=A3lZ? z>2Kb$OT>p0dQM^f!+m5DU=1 z@x~d{hwp!FeRmi~!F^7P#}Gi(G<`5;>uVlGD6B?pS#C>`BgBn4=9-uG$zdtM5KQ22 z4LDHNKcL9q;s)Mw(jGOPo|81z8eqU5At`A!Ns>+?CYwK6TnP|_awkBaTzc4C7lF1t zwa*G+u;0}ZH>iC zcEIUG+qxtARS&_195{Bms;OYsdxsI>+Op|dtrdKGl^m6genPP@3^-FObppuk z4V)Y3h@Gmpe^_Hso1?{b6dG-lY?>$zLnJX01LR~ZZukMd%R`5P21sAwlPZ;Aq?SKp_sNyz$9%DGk1D2NX}DXu;9;JwRR!qbp2{@s>&-R zXLi@avavugS1oY&Vs=tIbymwxoa!8kJTQpJyE;5{vlXBD>E>*GL8V_z%7QDo*Dp2uvc91q5Ivjl{<<7 zT2CU3A#dq1SiN5-;4w^Mzt}``c+Gz{-T~{|_4`MSZly2n041&2%m13{I81=x|Bl%$ zPr@#AS!KX|KTtfYA)v`x`s2bV2EBuh+s4os{3ezDvqXEtG)Puz1Zuf4hQK~f)#Fgd zaONTq*vWYzTHwA2C9eSB^UGm$c%@`cZ1}OT^wYIJ)SjumpvOPhcCyzo!Xw(Y*iVNiD^`vUuNZ^y z$jvvyBi%1sZWpB<8?sq37^xo%R1ajM0;5|Eua@i(ul^fx5$OjhGW2o0KMb#gMu_eo zX@pfc3YAl3#!_93u!@cl9SE>qw*)l;!e$y_G)6Fr%@|=c5CInLmY_yJn5%|}{ll2d zDt(MvGlD>|Fh60jDRctJLS;t(DBi3j9mTisLFW=TXUsdr5D=YV7;q~f%$hJAgCfBH=R$)d1u_&0T2 zlC^eYJ}Sl#18eOI2L#U4tFiT-+Kj;^$U;qerx*gn!pwmFsbA=XxVc1|A?_TKfoW8E zF~)EpL>e|FphiIWCuIhV`(iUps?)83Vqs?B_8r|CUr}ZZkk&BCF2V?H4cwuiTH}Y> z4B8qd*+me+tpQ{=pj+cqWyWG+hEYmItpQSDo`N+Lp%Gf+hYkFmRYw$o9-h$VX!#^h z=-;Q3xnl5yOOo=0Lr(IT)!weXQ+v1eUhNfm zr+6094UdU7V+p-Pjbh;Kjnq7lCQf)Zx6sBDLMsxpf>E3NB#cQE8V1EeVPGgLwF1ly z^1DuLFuoAxsCob7a5*|QA>=}VT3fYVK$@YE;7&JmoJ2AcT3ZC;k#LjXIxHbCnBylJ zX_O+FX&oV;C{zGc$*y4q=qMc*{(04J8FbvD(@q%>edmWfqJ- zhy%?rO@xJVp-}jlVyPF9ZjH=ZLCrE5C4z#UFC44A9n6xN0ql{+G)TV5Br(#h^BtQT zqfm^W(ClJKvSf}${1PUM3=<@&#v(3`dA~Wwd{Fza_EGKQ+9$P7YwK$3YX|BEfPRX^ zm01bty(&1oU=5(@5T4F$W%5i;J|Kel6CGFmlmbkuiLg+P#FY~Yu3`rUL>r)~x721q zzeUV4E2IcY2!>*{w&rkrqQL%2n>8%4B;S~0ln4vuLZQ;>HW;TUq?|GfM-{{@liD??e+AQ8$Cb>mW<7zD+HypnxAO5*A z3&tD7ER%6GmXHheV0(L;(u-zEz9CWT;TsJZKau2{_%Eqst{HsemZf~-l$_X@X7`>w zdiLzut7q??eR}ro*{|m-I#>GTGPVpVlWz3xwSJT%-d9w-12kQ38KVw zj3Jq1qmhJMC=!s3(hEqpsPKgmi!@61%_iAsC@C0<1!SW&1K6e-Y}F_QGbtbf6M~^& zKmjnk(LTIZgN-sUlLI0!As7ml&E{Z)qrq;i{}T>z+HvF}O_TRKn>3)&lw>GeTU)Ff zJo!6i9E?V&C(U6_1SbST(eMza(hOjCN5;X-q2L{9oXI;88rJyXvESYf#wp!^_aqzZ zV7hp?N5jSmmgJuJFR5ha8QkNRrQG9`oY+|BfSv<;4(d6$=a8O5dk*V4yl1X%1L!?z z8<^~)*Ku*|!rMSmrQn}0nf%kPo)CkOk9C0cGhQ$$D1sA$B*2_#a83~hJi-uY@GolP zpr@n8nJg5cNy$*S*4B0$^Ju(bZQL+3&K&hba6&K?4ZcbP!yXORri{bU2{q1SJ&mR$ zL*d}6`A9c7^A%+r3{fPUWOS4FBDit29Ppmj3}Dl=aoW3bnR>R#dlB0BS`K&*$3NPc zUsA@wK!qA-GLeRpf}yU2noDa&18WEvKFP+5(AkEkfU{in&{qdF!Jyi-Z8ySGS zV%HB+VFtjAFKR>seyj|D31HmH%Jpk#5UZ|zDhtFl$twkldz|8G<-# zRVzf$b?Wa9$~~2f^aVg51rYkc($L`IRBptKS)mNA`B<(#Wrr}vT9wP7r);KOhOJvY z%svWrsQ+#K@-T0$Umjw%nR*elZtbvCI;3XaXX%&6_|h*A5!+0=3|Y7ObUHhv!*#KK zd5ACl@({1h)Qf<1Yll_XAr-9a5)|8r!5h-pcYX3E3}iJ-OtV9MwWLUpKrL1Y4L1sD}J1qf*c_~Ob? zw3_z~Z32wgA`@UB*bD*0ye7b&f+18VOlZ6U36mKbMD6;Busk8!3}O%v#671ZVFy#m ze6S?GRfs3PO=Mz2y9;_Q?767t;+{)-F73Ij=klIyR@A}ZoLqtf7tB7Vc5dyw+WECh zYCo<0taerH>e@B6YirlleqOu2_KVsLwR>t0)P7rgwD$YjQ?+MnuhrhKt?k*r=ZKyY zd(P-Nzvqgc*0RGEvP`jQLVwc_YtyY)aBsKqCtl4>@6*cQRk6m^nG~;DANzFS; zE_7UWgF1E1L@&GPTOD0Z0+-z+^wP_24hp>Nh63SW8fK^IWj7Qr35V$xe%Xyj69%Ka zImIm~bMP~}>}GfWWjEAA?6MpBqGnsr%WnS7f7uO1VVB*wQRrniOUH594TXy$N|Q`T zJ1Ck75*=ULZs=t<*YsT5b6wBRdu|WC>;`?H_lU#!dE>I1zSU40q^2g4Oms4i%Wj%J zg&dw-88i(KC$Dy?53%XP>+0Om)%?ublDAc2ylbuOB&_L3`z{` zCv5SCUUu_~o*Q~@?76AumpwQ4Y$uW};IbRAx5;HUeXH@tk^jrvn+Hf%RO#ZiWo1=& zR~I0(h>HCjX2h*B^X3BR?+x9ZRc*Iqb(dYeD2{_VIx~(k<2=S?oRJ1(6WL@J5m^Oy zPy|E}6i^lcW#2?(-(?2@>EDUvM4Z@e#H~uJ{&>%!BhMG-#P;3q#67p#Q{K$l9yhKe z#&e6^Fyr{V%8cn^H^Mk8c4HeC1-C@cbBo+qftdCc=_i?1mXfs>+P(VmG4a ztk{ih{7t0ixy5dnapbJbxGr`hjI&}lw(+fr@!VoJ%s4r$NwFJYoE5vVjc=|?(&QGq z0o(p!H}KfO>g1Fc+m?6HmSc|w{$e-WGAnjtTOJo$KCe!LFD|f*u9m-9Z*gkVVmH}t zShK{k32%9Eb4ny1BX!sbb_8~Hv;Ua=c$pBB3b+b6|tT0;Bc#c41{Q)9V#|HPri zZo>9Sv72SmJ}XY6?6aJ%-##=;7+g~9ri%8V9)+@RCYfk_poUF?eNybE2knQ8-5B;s zk(O|LNU@uprTv^@H`G2Yb`!Qwirw6qTI`0RxW#S|YddR?NGx`?Vjaa^2W($9^|<{n!m-H;&yjcJtURW4DgoHg@~i9b==h zVmAy9k7ZIOCWDV-VzC=5q@c!Nv71xl#crs5qu5Oz0xfoPN4(e##W0H9 z`x1-Ym^f~+8wK}P3rz(WC1TkvPdgUhXe$xkSrogucWh%qu^Z+uQgE}_4Hvnw*p1~Z zgq9S$xlLa9V8v;?Z(~ysQtT!d0k$hy?B=ub%1yY~4Yf~;-Q)t0VmJRPuax8zyP*(9 zv71~BNSdl*H;*J2yP;VAVmAczZPw7Jc_?lj<+o%rF`?aT3uO%4KlZ@bgJTbkT`Fk_ z746ImqRe-EY7?Rzt`t@5#&VcFPoQr1KK}fcQ|yMC=Xzt*y1qH}j-+BY6u~Zb19FR~ z*z*p{2cEk~E_Rb=hDlYHPcE2Hc4txS=E~G!H#8c)VmEoNh!@SH&hW%xw3Tpqrp0a^ z8GCf>v9S}Airp}mQ5t~j44}%9VmFXJ!D2V|6v!)fllwDzT!*dCb`5VlEVbAT4S=`U zO|CcMD^s z2s+3;8iG|c@x3K%LFi&P*=|7yxOM~(qGZZ#8X{Ee#)246@q!k+xgoLG4aM;lyHOt5 zF;i!o6>A`hx*CmhsHu`0q}WZin|wcm6}xe#N53p~ z^FPvju-Fa6Q<*2lZgR~7y^<4SLeeXE4GN~7C;?%<*Ffz#*3(yAUB*?8ZPK#cpyDNUQw9bpc9ZJ{DR$Gr%hT{SlM=Sr%L#^Vre+g+=_$<(TI}W%g5~8DyPcf>$5# zV(cN(4RMWCy5ZbPP!RH3Y=RrK*v%f&4Stn1bU8s|@W-442vY3k7<7YG&MMt7Uz4JfN?eXjaDx=PIVQc>4TZw~+xrCm_a1w#IQv9iOS(_w zv=jTpOpD#TI<{$Sugcz)eJWq7>|5Ed^1tz7H!K1wk4LM}=uH{kb1g%@cZu30;D7La z0*l?eHeT$8!WhMFA}~N@Rk52t%9qc9i||)()eU-58f@~U(M%Pe;Dv~)`rrP1%d z1cr*YOC2hs*v&)At(;;vrdvj_n}}Oxv748T7r;evonWyW3W^+rUufjw=Ltx7I3!(ulFR1U0sxpGkDE0u#Qhg1%&ybcEdm}Dyt1&17Q%jG5tiZ>*4IM*$+ z*v+TVt(;;vY&t0{qu5QvEu+}YTcul!f)KY{u7XgaVX9kZv71rp7BCi$B{pp5LZxzx zw@ZaGirr-BmN{B3cTsK?8ZEQf&4;90z)gr-E{8!Z-Y(TGqu5Pmyy%^<-yo!(d&p*R z57Gb9W3M%5zsYY)_nX|7v*R>}SH4;~qH<*AsLIimV=Bj19>ld`l%R398%&d%#ctGw zD~jE?yA3IJ^G1o3SL}wZN<=b?-9(U#VmA-U=?jd7Ru6DD8-x-K$()i0jNdD>*v(D| zmRIbC`Xy@Dq=K2nZtg^|yka*7m|5&55=FDv%|lqOBe&QMMYD_DMBuDqH!n)(up~{N zIQm@a28T^FOpT;j?B)sOTwbvo(>b%)O~g5?*iEm&bs|M3D6F1}_THoarDsQL>*v%Vpf|*rCT)v~=%#taJ8Tir6VmC|BIXD`rbM7vr&_v5r=d5BkpG4>K ziruh@rQpnBHxcK|VmI4M=NO%#&bh<~(PYb1=d5Bk3#D^FX#||F*bQ|~G)zS^i`~@F zIcwxx`lFmHHgZ<6n}3kb0kNUZxeN&5M8j0)%wjh+g99b(LkOxDn!OL{f9bJTptBF< zx25|~Zp+zmpi?TRR!*y&Uint#jLMmnZ&&t~si9!88#c4>It3|q1FwSWVmI#IgT-#% zFC{uyE08RZW$T?}0osRFFtRAo<0UZ(gBc^{l#u5fT1YoI541!-Fy&r@o=#l3LvY8B#Z$qc5`}q zu^S484kX2F@Vk}oRlZ;OLFI>)vns2^HJzMdH-O_Uc9ZQUiru(#Ru#LE-}%fdc4Jr< z(-vQv@|y?sQ5Cz{3Of(U5UdvibC#4`Fw7foHTtcSVmCXA)S0MG<1cn&SQk?^zw@-% z%|Bu1d0`N-qT%QZb)M7(2}K^VuvqM7vAAL&Ytvv^5VP2g(R(>v^Sf^pyZN`IVmAhe zUF=3UGG)ymwcpducp9;dKEH|B;b&Ux=0}wuSI(*Yq;hWMyvhqIo@@igcml_?h70pB zX0aRQCoAM)ISSO06uVi9^9_=AszwRW${>O@oqYgou`qLNd;FMkfo+)Rg1cO_3-*lm zAsEGO4pS}!i`}sKpb@M|?E|32ZaU}!BZA5WchM*S)(-YWJxhEDMzNa=T>$c@M!_t0 zW4Hj#q5!nm%{t`*9R*;8p<$L8y?hspVmEuC3qbLd3qS-z2+%C*0xfp4E~(g!5hc6W zjaU%&dhjfKsAOX;8fauLd|#8*9}ne2;%xJkGue zH8ef7vbG!isMK>wuOZ2A{FZn(q6{r2$JrMkeTqLbhYbk?(x7?_^YwzH^gTfS;env*AJ-tp?_vvTUx@Z^yV6vGs z2pDga-Jc+rKgcjBL%+l4$pN!wA5F1!xZt{zf`5wR9~5kPeu2MkoMl7qLGwQWDm{{KLvToc_vu zcmYo><)?q%%wM<=%rk3X{yFiA^1#$mW?f$V4X<2i7U}!wsIUdL@1K4YRxEtzj=dBv z3&i<%e4LulRB9w8?SQ>Q!^@d_E`Z}Oze%LQaDVUcfco_8K&jL>FkF7mXFjq1BcJM- zKV0q|ei=VKJ3KV}x23^(i%Na-M=z^fUinq!*OemTVK*mGh0N3j+x4!Xn+j{_;BQts_nnEgY;BLnkBO7kHa3m_UJ8y^(n0GtJD#@Y8q z<>GQTWpq|Fgb73(E!m!yAjydqVG><07x46Sb&3U5tS@)xR2ZyX3<8py(jFlEP9f9? zg1die1ZWpS7#;=$ZVwQymi%{mI^zg(6AI4?-Y^C+ZyrE!g8*@Yf~ZpncOTVWK*Jcs z{P_UE4Fbe59rlgKML;g5;iHfEDcLL=8_U9;u*NXG*%!BC)4P95SUv1-45oK)sVx4F zp6yBlrIG$Y{$57JL=1#Y_D!1(lizRiOm>ASC;RaHUe&92mKKb_)L#fwe{|!~onaP> zL2wV=pjRJW&RP%*cW=g+^VX@+*joDkSB}P}7a0xHEM)sm(TVbp-fNJ)9P-EkuG{$BImFaqf}b z)80Jcn21?ni{Qd14?B>!YMy-U(NBMl|06m1hHtFgRJplwOXb$eZI#_)c;Z){PsZ;Os%lyl9vY0MB=54JU+mRJmzN_+w%H5SeR_>|XTe+|D7Wr7vo?5X~4T^IN ztI}Dl8N^NP99d6kYj^FHgf)oV0%d+RJKp4Tf&EBH%&%sJO>)fxe{D}OYheC{PCq+7 z2PT)1p=rQz5k!EN&S8=D*gi0ptZT3)&eMIezhjvyYExPmgg}{IiV1 z^fVhpDT?hdHs-D_ytxA{Q{w=eDgR3$5FRhBlf=`4#oY)WAgZi&4zf+33(lsePP z*p?^{z3|dt?P7~>!2)Rx7T<~TQGpRK7Hs)6;wTm>(7a&`VPs@b8U%>z#lc$UgqLB6 zbG7CkOE|AZ%NWSQg~}wLd>b8sXAI&X|`+*juqVrfbRvdM}$( z(E>IH%BIEUyi>|zbKW*7dr?oGjv>BQZJs5=4^$qkJXCqO@<`>;%43zsD^FB@wu(J{ zm6!klj+ZX2+)(*_<^IZ_Dwih8_V9%mTei=HY=4<0+kZo8(z&vI!!O%I#Re|hTUIUE zK1-7AH3XIILkNa!|6Gb}uk91rK4czPos#WuP$9~d?X`VFwhtkgvVE2)+uI;0+lNpr z+5X4`*`7k6z8Er3Wcx?bWP5GhknKYNrfk1uf^4q=v}_-;PGtMPNs;ZfZ6e!;j8obE ze#zkSWqWO&$o3)gRJOlZnwMvYJfv*7NtrMDji z^2k$n*hE@1x*^+t4rc}&&U$8eWqT3~Xq*}g6v+SDvFL(q{|)t^7m@9CBy8C}Jf!+T zFWe?&*o({d`&7SF-M6}5b^q!C)dQ7P!UIP%>K46~8_A8|ET-jb5C$fFOIF;=u(qwyW-jwY*f;~kQ`((0ws0CYt z;eThGtGH}`aP^Stq1D5xhgZK^J)*jcd@RV7?HgK4(y~3@Ihbtku01W=_bc-`vOP7g zWc#3bD%)R`DBEiUOSYFNwhu*Q`>+XP2L&cm?3jPB zWqSie$@W1EL$?3CVsjDMUW3@Oy##W05xjgz9QL$HnRdlx`=hEySC6S4TRpD&wd(QJ zuUAi~?yY2daCBqosmk8fuT+n$exrJ8l5C&BWqU`quM63}r*8>l1k~Tg&nQhgN494M z@iHgO2)HvZMZda~?R)x`D3kC%EZKfuf^1JAsB9lXFl75{;<7!pPh|U$c`Dm~SA{4? zwx{+D**=6|%J%b;WP29`W&03{CEI^8D%+b7s4s@h6WRWkDY8AaZpii_08_SqEGpYm z04>{xtP|P(<+yB5Z4=o(WSq+O7fA+}C)-o=M79r^r?UOA(!4xFys|wt&)P*+FqQ2e zO_A-XeJb0B`ftegPfG{#WP1ugWc!ePD%+p0%!g%r)4Y=HL*}V$e_33%H?7BlPh|UZ zl4N^o-jeNw0|PyMOJHMGf9k=Bsq(=l?7Yiqz$j;N+5V*J$< zW&3K1Y)_pvWP918(t@78CE%d?vt;{|m8c$;?F|ef+Xo>G+5RMj5SHyt1TEVK5e(V> zc%`Z5+_pC%v}_-QFl75rDu^7}-h|MyeGtNs?LUsZw14Y?Zd7l%l2UtY0>D0Y<~mJ3^<%~WqTtS(3r~hVMluV6J`6biNsiR zLAL+1deF<2?P(-z**@%smhHoBQd})A+n-fEyZWQ*kE`cYe^NcSdS3PXYLD1)@@0E) z(=XfCg>2u`w?u9H@ITnY7rAY}nGi5?WqXQ1W%~etA=|G>lIl3P5E0fO#t0FOJLh)Hspt1IDRr|Hc&A zo|-phdycSWPu~)lnd(omPbSNUTCg=3{&&W?ip%yFRDV{zuzFGT=hcg=msCG49}9A1 zd*&EkW+k`n`Od*)`<}if$}9LEu=ccUe}^(3l!Z~qHO=eB-x(E!IJI6P9)3rVG}8F=#Fgv!Bp9vhQg8U z!=5C|_F)q#!RU@`zaT-jr*R;%z3jfbwyA8tyL?p0y=_kcsB9lZFl76alVp1XgUa?n z5L34QJUWsm+gl(?whv+$vi+1|bGfoT1+is&3FPb|RJISdNtt%VW&2-NFRflyy}bIX z>aVL;RIjXFRoz+1_H`!Pf3y0->QAe`s9s(DbfRqUxozJNvi(5c618{2|Je8`rAgxka;TG-;*ZWYx`8T4*?jm zy{=*tE|QZ~H2{(AL-wg`|3eucQPu`unKN%wndX&jA2Ls6`=6!A_O$b{WkqEB?)jwA6soqSNW%t4~xnQ@VPvNDfy`N&*`AtLvVG7zmF>TlDBEiUOSYFN zwhu*Q`>+XP2L;*Q3RD+m`x6pndmRT$whudzEZc`oq{N{+vi*v5*xJ22WU{KjU2x7|i{~@1w zWKA3YZF{;4@`m)u&9@C2vi*A$n~TWy+7ny04^JtJ&3Sej{l-hk3Oh@R%l1!JpQ=7x zeWvYuA$?yxGFi{?+SSvpzEc3ZPyEnLj0 zh$2={AJweO)~xQRF5T-Nz~vlX1DM-r@3vuWdkuVqtz?M#Z09C*QArWt$gkMC%x%IV z^kR`xUZf20o}DdO@h)_J19cwip_(e3$9ebx-b~8vBYPicK;|}bvds}2NufBbNGMp5 zSnQWk$m=zo*Ra6MV}o2bCq)fvqnee??7;9JB*(>kPpT}VWRy4SMqD<*9AUPT%f({9 zjJW(kOc)s#F<nT7W@T+V zF#H$EGiI|n3Jgq{LNf;YWd!C^MqrE?<0)j}2Byf2Nw^o=m8H~`I@H&Yz^pN6jHed0 z9T@(L4w_&UL!EZjPVq>a063h#w6UA?NVU6AibS3eLt+n66Y5=6%A=b zSX-DSygqfr5y93XjgpSw1L2Qs9A=5?&%q!6M^Yen=;i7w)xT6RI;gVG?BhrG43fSvGV_Fs0{pf6)X z30Jce8Ve`I*=2*X>;TOM<4@`U!2bm0*(m=n|IzNZVZ__lgt5QgJj$a`N$pbXm$6Zw zGJP9#5M~#^L}nKahcml;y~Ha#bbLG!OY#;fX3}HHoL&51zzte{xo_XveziBt88!8R z)l1p;E5g&%`j3$DCVKCCpI4;ZkiOR%81HFddLwpV=WnkR<(k_df!Uk+x- z1{q9$6E<~WEMH-v^s-WgN~SLM%b2>aPTv7GN*pFKbuk>Qtu=N1y|kuos8N!)uWovk zdTUPI-kx6WFrB*n2h3)OatProjsV3BT}fD`hdXX+vQ@jCO2%91||qWym=J0ug@|MxHon_&2Sem+!ewO z1os_mmtJgE>b7BJ>nLh}ziAvmw7*$UF1A#dzN z?tiUfdKniBho(1-uVqQ%fujbNfF1S6w#t$!{mniXRvy@M(_VcWKPPWkt{c~%+pu&6 ziUrMJOchMY#wl&K*#I{M1NoFRy@q@yq-K7~gPMkB`KCADe1Mw*)6Y&{3$8^z68g-Cgiee8qie_1j;$TqxeoqmQNRA|%pQwz-1T=G znNP?z*k@tru)}sclrrq|wG;lIPva$@lD;K9is_LByw2h{iH^5aIJR z155grK)BRj${_lGW;*O^Q(zGPpBhB|i5*$>*FT8VN6#Sodg2bEztxOM^dLr8qIy7@oN`to{3m!^T++9MjG-vvqPBL)fsE}m^fS|8pXmaF_%Stz zU??(()JM-C`g-CHqQBLQd`cL^Q)&Z@eipQv9m+R_AZr= z&Z(OjGeRbe7$gUXErL<=smS~e+Nd1S?TGf~&6K}ZyjwOn{ee~dOK3t^H524C9K2mT z@azo+VG-hfVCUn|ovnu8zqC8Mu)qsx)q014%v9Mjjx#*0tpd`0olh{N;iVdi6UD`~ z@T$PJaj<#wh+#ncQ|H4BZEyvwD?MwiBsvWqZy3jc_qU`;0Qrsv;m57F_^1WK&f3^A zhYL{v!b}3l7Z9Y~nIN8oSH%j}Fb=YC;UI6xLGDJ7m2K*YS$)*-gf)zVz>TOC!X$Wd zxp*IkZDH(OlV$cy4WDALc5#T!Hj@ScVUNx~u~8TM7sHTwf*tZV#RQbiH&;dh=NXB^ zH!y+|UYnw2+?y@75W6B61)S46o9kVX;b20d4hf0yvf=w8qXUWiqM6(ug%GkoBbnBn zeR0#KQ7Q|>_eJcPk&`%DPFA*yv7m@$XMJIsP9)wi9{a7g<{P63eY5k=5Chy884Q=9 z7H8o#AvU&z$@IF{$(>O^ebw9<8J5@?v+&xGJ7WUaHrwFND9|p)r4BnIgObq;PhGa( zCE&c_4SZ)5AbV+$DFPBcRoH%)0P@B+@|{tDOd$wtcp9W0UKeb?O90t+TfQ?2kc$xn zwlM-?3hQ*TvHdOqz zJcTBgv+)d`LIi;fX9$6vLfjxA96o&)fDekMkp zg~Tb{lFiYC#3>IWRciZwR=cpa`Ks447rAZ+C)MCLYTvA#TsyUPLG7a23HbOLRReXs z4o3}yLgPXW9PeAgyCDCchz61KGZl_tn*xuo|D}W^&`ENK*!0nSd=2)*7~-5(GxEtC zVkHHT1>1XZ?I1mfY?b6lx<(2HR*Deg`BuYw4iDY~GZ;kw&rFAXZ3+zHZfX$0P-GBs zoifGKGl;&PxP$0#H6x!A2JsiQJ#Y{~!-@?eRm$u^6cSkBK@9zjI_z&#U=Vj#LQ;Gs zQXic`^!LOb#89gl`IIn-m)17wL5!|Ms+75d2-9!D3rW*KSx*DjVJZd1~ZDxh8kQ$g{giIKz2HHSu5p+il97s|FbvW2V z?^2}3=tIel1YEo%YT(91HPAp|x?vp0QUmWWpLx~sEK!U+GMfJ27MlsdEM-tUQjbo~TVH{HpJfVmh zsKGpHAR^kk0pAxHPC>8oiSlD zS!&>c=FX@%-(p7%)L6C}81~9m124p-p05UKC_@bl;}~k-=QIe>&@x*MG(fb576viY z!1o|Xz8XkCs2UgsG1S0w5hPy?Bp_4`41*YI;MbGYK#k+7fe7YV<3vBoX_dB!i>raZ zu3b^PvUXMN>e_E=*VL}9U03^U?RT~7Yd6$xtld<*xpqtK*4k~g+iQ2!?yNn4yg5$| z)J0f8f+NR}P`yf9TAa*K1MkICC|3nsqDS*@xfO z_TB2N?NF^|Z(aPckMHqMi$!Z-6eA!pHfp=cUzhtn-MgfR{B3+aHQ$MuZ&CB`@p8j_ zr>8t!ZD2O3bfcVVZ|um*?5$d#U+o?4htZ`gZ_R7AUya-`Ovw#y^;@t$d;IQ4@?AT7Z1|Fz@W4UPMkq7m=^-W zeAuut65J@2IEL`!I2EYndL+#3stK_?!HdB`2o$piPHfZwdL(u*t{qqa2`)fEG5`=B ze0usB*!RFCHm{XL=H87rQJ}FrM#{##wb#Y`a_^p_a708~CA8@uDGl_N^vhGFLC6x4 z%ke|KWu9>YceX1J&l_PyQ_2fQ$|H-)eG7*ksy$qLr1og-vD)LcCu)DH-PU;-8ZH`Y zuUNKj`NS%49S;z@f(-Kq_m=zRp|V|B)Q{QBa5V64;b4S4gw-J>uzvUPfF2ISlrn}gU~S2Q-*IXgB7Vr=Yr12-z&jZej<=)4)6!`SRx zG&a~dJ2pddv+hi`^=V*UfT5cSYevsBwi}e~U4*^CF6_Z!@M#U8PXqID*8(t313v&% z)&~G_8hk`Pwsa;ZnFsO`gL(7CM3_u)0gCGjgW$s7XawehL~z*=&K&q*f)7w%pEcx1 z=9cnVda^yihe6(+3~y?@VSFH1iG5)b+}N9dFh9IkG-;&RPZJzrHS1VQ?#cg~W_MoT zY-R%&Ih!$Fys>jO2M!wRY!0+a-hg{95n2E3fFrqQ^Uh*PyJz#fr)p2vo~b=sd#?6; z?SHP5_MI^8-+p{uu?3 z%hEM~&C-1yP?r874WK=6Svmno@PM-PRfIw7?Z7<&HG;#^eLfg0{aAv*ya=&$ijm-k z!O{;@fy!m+8p3AjJ})Rs{|^nIN5W<41R%i$%F;iqS^E0ePM}d>jygL5o45A5@Ue7n zD`O|{Tbdn9f2H=9+N-rqwY{>vvwgBJWv?s5(ox6=v-I^n+gf`<5=-~~%m~H=gw-`Y zYnHx!A(pQE53(&^C*cK_Vl3TjBsm&gW9c79CYr?3F*aeA?sbd2+>^x8y+)E_(>0d< z8H`O5OINWeI&Y8&r#->UE;e0b>Cef{I>OR1C@xEf)4*Qp221}J4WLg0m!%T`<1}Df zi3>nk`ujD9*2l8-x)bA`8o_4iJ_O3rx6ugtP_DTwoggImKw0{HLZF!wL6(jX9+vL& z!eHs2Cm_s^AWNqp362;n{S%s{N6%)&VJzJ}oBfA~t)K;3C2uk_W$F86`)3Da2WDT+ z4$8ig9h@DK9h&X0h)*6%&#*Xy%hEUWlowkkvcb~7ssZ#`a^@igFoth>jSqmb^nDaS z9!ngajWbOW&Fh=scFLAUrJH=Y_%2 z_ah+8j}S{YKoT4=So&u*OOKw-ctSCj?w-y5L&Rn2vs*|rW$9nbj?ccHosfMaJ2Cra zc2ah7c1m_}=VPF~Zv}UymXDK^h?CaI@NG2F5cKqgcqwIa%?h|>Ro>1zmw~G*tB@7> zfCie{h0GT_pG<+EVG0oB(xF$}DgbSxfz}a^oE#4Yf`%zT@Wu!LajO8dSOe|4MtkJ) zcM>{im;%(_&w#j90QzI+bu1r0xOz$qk$f}KmvPokv9_3RwuZ_cDaN35p_;Ik6*t4q z$!IIVsk(Mj-m0P_=9P?&FXv36!>5+GsSxcjL?_{#jGHMCovxjgJF4i2#UP`zll|2j z(1b{I_4t`uFN9*fqbT+}|7M3xT$;8;*7X3XnJ1hU+o!85iB~~!r^QpmS19G;& zDZY%;<1Zw&?amivZHMj|66*e*_5Nlp!_rb65 z%vpqB`zaJ5?4TW?6Lo~d6v7C>?p$+)7IhR%ttvQ&SOrw}H)j!oEr{VIuQBYP9iaiP zd)vr8M2ySm#7z9P<<72~eN+0MF7PigxQvjVF? z4|di-Q@dy&R|zFR&@crEnUw(Q(Ln2nM=rA>K+rG+2$_`t8q`3$uF)R3%!&X(!xSK7 zRs!hP;=^#9SuvbEW~H!zSpgK^{Y%zR*(2q7=~rF7q#xgin}KN?1!HehXj(N;f_paP zXe`rfpF_hV1M^0LAI#gN;v!~L9;ecA;gc#oE{an@MbO^TUpX$CP$k9%duNmZ+fBtq zEPy;VrQ^caKzdvho0^NbXeyN$7wnx8myQIrJu*mB#A~8|x#t&duPPvDIFU@Z7??M-Ig$ug-{mUj~9t) zGgtFw=VGzJ-WjoZpN@@KR2UoBkF8Rt*1RdWrtq_GbF`+q@lm=XbZm^XDueCVs*+&E zrr=q%&D_qLP3#rF^bhu7?~Hl#NwOP@MJ0FR40huze>X0;s?0CE{?&J!P1hBQ4))H7 z&M=9Nm^v~#tk$YkIo6swpb-_~fZNXT+}XKMbg*|uboQQp35;-ch-n>)AG?KUX>6F7 z1kI&76n!v;Vr=tL9-vE19g12LMdn1P<(DpXLAFx)Z%czi@DZlrEq<7tm7SgaDEo1C zPWF@R-0ZyU{OqUM1=-KC3$u%|pJx|mmt=Qpr6WK6rf=@EJe{d@tY9ztzau0PL1qd> zqNN&0D7i9|>ZIQY5Z7?28s!HB(Wv|5z-y0BJ@%-4k%s_4YiZ#p`G^qb!;o!v@I4fxFzh>q5b5~HIvBQrXy z3#H$5d;+Nxzhk}qD9p@Re3WvO7$5AQojSQ$Czr(HLV?6D9_avu(r=*%p*%BZ5mNe5 zVuY}Rc7*;*M@Sq37$LueL?Tph4xvahXAx2=QeuR#gLZ^&C+RmBenqhS={FT1mVRUP zgm|rg<4%Wv4!P+!f4c(POnUn5m)WJ+W!dG~ud-ifS7cXaS7ldcyJ&hKL=Zs_ob+2= zzkmSD3MeI|2OX$!RH}xU70^{+R{vK6iHDy6v!X!!sV5GE%t`>gs)5Agd4O3_ApT$; z2SR2gfCe;>cwh-ID+f+?ZzL`O zamw!yVN+@8H@}(GxM(Vs7#B^Y7L34?=0bSV9Nlrvyy-U;oSgJqXy#yoYi^>`mGql@s^!T^u@hr-yy-V1 zIt6!QOmNLnbh?p#dt9dq#MHqwiZ}g6gTwi!dmSP)b1=a*N3rQf`tA2RHiFtUb1`}L!6q|0O-~O+TjaXC|8*loJ#-`w!DwuxrPrqb_v#A^Dw>@=ijI+w0extD| zcvfM8YmVkkH_~q#$XO*8Rc`u?2B#>?!35V_MW+ktx93Q7#MH@6zZuafICn6?HCNH; zLi%lYl754AuK2Mx{ib5W({Jm&={Nso;iljG?NT=tndij3wKx5CO?GW|UH04TciHvX z4cU#^P1()aE!nNvZQ1SF9oe1P@3XtI?`WkXH~m)E*U~-dw+)bfYlK81kwaRpfrOG9 z5{U>9&yi3`WrY_AMIr%I)}kULn0CJh-@}29Z>uh+-%eK15%VffD$>#6Q;QSLc!#M}l=g0* z*Kg;=3vVkC9jz86ir-o-G80U_Dmu~hn_du8f%KcV!w?;mWD-*YelrE;j@FD4qk|o^ zQv=J2q~Az<0;vlFX3l1i z(vK1&gdMbJ(7)&ii9-M*qzG;y}o(1kgDuog#)Pk69_KQ2GrbXphuP(rYAeS7(rZ^P5SHizZZwqPQkhB$=|kii=nPGA_Pa0(ubuoATaa z^*cn^R9ceBZzeS^no1?cMN=sfmroQ*zv&qhkQe+e5gs)sk?BhM?MW%yC8pnWXhOnN zC^kq?5~UZvndDic=u_gX!QL4urbBgX#5SMLok(m7&KsmAa}ygyoDyS$y)$C-ED`O* z*@OuufBFrBlaqe)4|#8Y!StKoO!Ca>O8V_l5*@JC!ew%G-1M8jUFuyOy#}0@&y!whtbv6$SzEZIJzrFx9wn;lzpd? zhO*C^MeRckd0~#f2p~d)AI%gYa*D_+0NyT&P%aNjg8*@E=OZjc<&|sRH^o0pDx^W@ z6>Ehd8b(2ehLlM_Ib4o4`|)x$)=vFn17vv=V|aK_8U%ezlTyx&u zq#)2TiUJ=o1r%-*VBRIaO~C#W^F(UH;c3eoMnM)XWUerafU%v#m}u`phNKprxV&K$ zV{~*-S_F(Er=Ny!mD+3-MfORx>p)w~A4Ikf@u|N^qtrd7=MBalV||48UT_2cJRkbo ztG;)ApZb^T`_}iX?_WQleqjB}^@lo7LgPgPyRMuBxA_#=W3hLy#ZMeUOM9nXKeeXk zy@hw$z^`Z&{7q)P(;n7Yz-nm?Oi`yn_HZXHIt?wsY5vt+97KQLAX$yyZWW0%wda?~ zM|UGOQbRCW?6A>Yvr}m2cm7w-f_6`D-&yM{d}WZh57&ujL5Dl z+sP3@N!K5dO?&lid`stxyaQ7!SqBJ9;U!T0J%F~!JwSOd+=IdC2cQR~HXGK+`o|Ek zw$OvV_;AVcxa}2tzXgEz=AzEwLJdS@g0#A^2V^G$`6i<-AeZ;RV>q=U}csfrKL zvomHSITDa!lCOAq9@P}IibVMIe7>_eqZ1`~m3bP%B9Bkt6V8*53JYtR9u-U#=UmO{ zT2yu}8WrrE%_-(hKMa$2aEed#{Lg2ru<*usq{dt_KA$aMJnJcWIt-bPo2;5GdiLkC z>i)0QkFS5d{#b#10k`@Y4Ff43!17Q(VJLZzJFU-#I zneGeUsGnH>X8p4CePJn<$q4NW8+uNf$-dzInKkadHnZLrj!)kgl<%Q^!PmjU`-0a< zawNL8FWj2EFQ~8t_64s)MfU}-k>sd!ZC`jy?+dX90u>gvF92zG_64s?&c5JnmF)OT z_l1+|r_@ia|40hJYu2tDUk9X7DA`ViV<|rR@OJQ6B_)J4TiD4L@L zg6*^d!ue)}0l}UM^C5bBIRqF4h+zW322DUX_jL^j_K=ki(bvZzz#u^MYl!9RKpPSe z?195jg($>w_Pn1D0a+0U6c}U>Wew5RW8tXF6rvr6fUoNU1T)CJ5Q&#HYbO{&;On{s zVImFyi4kEA?B5|1FKgCLYx_=KgxH^s+lO!K3Ugrp2RcN{*Q-%*)IkEUa(R3%4Gr;8 z5Oe884bj%q)k%p^h;|$TQX*^=1jMuQqmvLejo^NTia<=n5#W=M!XAX_R0S|i0P>dH zbQ}P_2npjLJov24gs{oG0meaQTiA*VFNgSwgAYOqi)^l5qA}WRQA-RbZ$!ehvK_~O z??JMW5Uct^6{rclZ@3?GA`laCgoO*)NC<$V6u>kA$XnCXae&cLHWC8hU#4Gy=fM)+ zi1YPg?Sz{z;y<^yaZrJbd{L+oJF4h5=h_hzZtKkrp~HN#eeenXVC#9Z9X-ANt@;`D zGwa{3f2aQ4`uFPJum7O_!}?kEv+F;q|G55@&aUvwMdj%>C|T^a8~h>(=t0gowhZM# z(Hi#W5plaf{<{1l>nPheNzJo+8@c9D#pCAS+J<4i(^EdzHop@w&ujMOnn%HxnP(;Y zsCoEx`2yQ~otlsK9(7r6-s(NP#a;fnZT?NfJiLXJADlLgJ$vJc_8xv+{-tfcMa{>0 z-=?u=S7r?J(EDH6=HJ|51*sQd(p{x{JoBcF8mi3X3k_Ax9mrp-=()nO&qY+F-@&8t zNdLf|o3X_b{as2Uv8Lejh(*Lh_>vi<%@@L#%tkk6okjdhJ`?NLu4a0n%yu=Pkh@(f zTDi~LqF@+xqqo0LENb~FJ0VoPB(-BKt4yVWKrYu9|4}v{f7++AMvUUb4X0vrHba^D|=0a24+1 zpVcp{UsV5j{o?v1^aCc>gpbeK31@Zz8i7M^LnOW^W+QlEHRy%&O)gW6s{|)PxzH zH&U7p$L)fV@(3Ka3;Qpx|Em7$`icUa16AiB=jinO#y4xDoWuJ&W7fiU;%hW(&M{hm zbD;Zh+N@SdN;Qyy9)cE&hq}m8s$)OIIedQd3MMfq5sa>Jj@Kn|4h)LRIe_8Xvw?Ds zTIa(sH{+ZG0eqap2VroIehre#IS7cuIeZ`n=XiY@=RgdXbNCPl=jco09BAL=96tMm zb4ZO$a0DsAxspR0?Yo@AXPQ~o)Q@^HuZT-6XZ|lFSKbXup@Nqi8IXXSp`gZRq=kWf{*uCK_ z^fj6_=Xf77f_%<_etS3vOfB1KgLBjnA)j+71ebI85Gd#95Y7>uy@(~o3$~{;s2d6YvB%~&-ko4$F}L5 zL%AQ~9Nr!l<{W-2>A~n4=h!}lbEu#=oCEwQ+p~dkj%At-kgb#Nix15QB3pPU9Si z;c^Zi0^uCxG|qwcUC!aNPdLZjX`BP?yPU&kpKy+ArG1_Y33Cp#?{W^GeZn~|B%CAm zq&SW!oO8HOih+H`-nB!`(wFH>Imi9=2kH;jAF4lGf296s{jvJv^*fU}2PWPFoTJlo zvv2o~at`nBj7Y#)=xa1<&M}URAfI!f-yY5ZQ_FVR;2bSP$mbji!Q~u21j;$yM>t1x z_971F9PaE5#Mz#`p=Rl0HdCGBPxUA3Pt}htz&S7%8sZ!qR`lHJo3$~{;s2cx0eFeg zXMEP2ahu1#g9BH`~W#8c( zUi*Y|klYG1jXWvhbYh%CR}d#U2bi#@txxChH%nipGvyr5)SsBnRDQ606*sdk8bzv-Z9SM|D6$uNw#~t#%Ikr6eGyz9O$>pIiOo*yI%(9cv~9h zPzVm^@FGyoF`+pJw2jPO#9^GnGkXJZb~%T4IBcE6+enPrOgYD2>aW%})jwWPaclu^+lyi80XUtmIAbgEx%{gu@z&X(UAm{M)usG-NT1gK^*Eq*LNt^?N;&Kik z`1Wj|oMT%pLFDQj2;k!!J_v(zJgGr)bq)gJa1I}c!8wM~bPmLDIfoB{aE?Ev=^SX^ zN| z+M#CY%XFrkWADa3jW0F!ZS2?Bzi~k0z{ZywZ%^hNcpD(VIXXRe`F8Ip=kWf{hyLB03WK%9L@Ncdan$2Sq!9~ceiJeIH|AZ&-3z>6f9_TC z-oqNZt@<4N(;$EQ3tnYt-BY`_c3c`fPtDjImseW4hocd4d=hn}wpI`rJ{et>s z^(*Sv*Ke-hUB9pXME&XdEA_n^2Q?0D9NxH?Q-ek2)zMehvc`^8ObCkBc*Q!~P5!#v zx1w(exT5|xzMGoQT@%baYJc1utO@Y~h%^tYZ_qaX7Ggd>oyp82&1dHID{I0${JK2P zHvfO9`DpKPMRW63@7XJB3vKfw#C-lk3iQ54W3OLX6TOFDm$$IZZ%56?dS9cl*RQNe z^U(W6w)xHE>!hpO6YK#?EPeAWN7ijr23Ru~QC_KpS%pi}J>{(}qwuzVN!Ww6e~t!V zy_avS81I8w04(ScfZkpP0QLajbOkV_JuqK5GXbU&Jm~8K0A>#W4$%PG1M`(33n0OR z{(c4^JlIpdm%O^Yk`IEe1h7F>s5B9vT|7uo3P4%}Cw@&Zm=^-Wyij9fB)9>!02qew z<9rpU<$5H{H%Lr~-5-|#fAU6vFTdDqh~QT_PlXwBpR_PI&ZKNVXRDI&f-g+H#--dH`qCQ-u#!` ztU-vU~l=X z*_oVV9*85;s;XilOeVMhWmSYhaG|Xcm zy3Y&B(ht)BdL&$yP5=^Ipe%ha&C*#hs<+Fk{!V!wb2MO%Iy(WIxAwa5v2<@M<4E;e znjK63UgP_XA2fd0IID4X<427jH=ZiQ(ox6=v-I^n+gf`<5=-~~%m~H=gw-`YYnFag zA(pQE53(&^C!O?QjEQ=UBuArbEd6)LM3Y!L#wN_ty>97B;b~0NYa}@~U1RBg#MmUU zbQPPT^9G6VT*RhpEd3*LvyQNI42sLr;WV(9y1~*9&;a^0a9KJ5Fir!umAC+urGH*? zXnibuSh_~AS-KB_vh;Up1bryiT$WA{5`3U6{q2N6Gbe&99U(j{-RFhD(vKq`%#R>T zryvQA7%ctEnx#k2X2fAE-94NAhltD4XSd1Bl%@Zqac<+h#`%q(HZExVtZ`xEqQ=h~ zuPWk`$I>%Qqq!^{zRR)LI*|>QezpeCYss016u=lhNRoR1C`&&@0pziC0${Ur9{^?P z2WbH9fy2@%K!OL9rT-6M(0V&?SUN#)Sh~*#gQZ_aF!YAtXz2zttb;?lqDejjplu8mWYb;&m8B$of zj!n^dQ;en0E;e0b=^vAubv{d1L2+3+oCfw%H&{AWm4;vH)4*Zr6u>wQ*jC~KP?o-* z=Fs|Bc3C<>uvxkffwJ`XXas#IyDXg|B=|sC`i_J^=dpAJ;bG}MFASD`IssvRgjl)( zlHiEJ(vQ(BJ$g3d3B_2tdp7$I5tpUUZXwN-rC-^&s&RGWH;ro=*EX(e{I>DC#`TRI zIv;~P!d7rsYWX-xi8yy&vWEPKqi6^zk%jDT7t66tu351T?&@r3oy)-0l~u@!{I>?0 z+J(#)JD*H}pkWFSv$#U)l*`KWF=`|##uYX+G4)h8Y+9F7=yAtXY1AZ;%3-68Eqvv zRo70+aTOgguVi$5IcE|bKDES6g=mK%Itk}w+)RP!bnUD>O+`m61{s~5#5aG9q$i0E zUk~Zg8IqSHbF{v$MrRY0WoMAv!9!xHZ=k>Yp3i(@{YO64GrxbRw_if7Jbv(tFae92_&2@Z$q8Ew}cF>N`r#f$B@hPvKS|t|OJ7snW zZUR|#$RWK%CJ<|0WcM*Y+^mL>7M1Pp41(>aP=v69c7*2X2#G0#5rW;>syb>#sNfu0 zIM;IswxB{0!VcOI`ZQNQhL9)p_mK$Y(F{&2Q2mGx{+=UA+be%_F=|a}AaJ3Ogn-^z z7%2@y@#%RZ<@r#2dcnLK8#gs>ZrswiwQ*bH_QoBJI~%`myk66TasC(~xU1{3zD*1i zjB!`ey$)0wEo~oSR=|jX9_*%prgkAD*-v9@w=D_KKjkJS7UWmcuW{@#+> z+e+e|Bl}`Wf|-<7!~MO(npO>z%%ibPkH(?lk%4(5!}B%oduM6E$lsO*7cMHnw@W^$ z;v!~L9;ecA;ggD=iU|%8PBj;C(S#~7F39+dxLmE`A{Ia%o6>RNYal%?NLI$?A}*Rr zCB_ANXT)VeXDh{{*gDGRQ93ew(WXZRY0BJ0MvUT`NNftu8>A+46B|XG5@UnCGh%bBcy1e- z0O~EyrZGvq;lZ}%roJ#ZvVD>BX)|P&bF$ySh9fvtVsx-~MsyA((Gfc_Mh6~jYtFUm zj7F#6ZoI|ZM(3Gg(ZSvs(b-+DE0_yn>d1AK!DDR}=AWW@k(smQ+{Wg*VzI&A8L|10 zj*Xx;7#sF(OPI+*Yzpqji{>^qI~R)$_RfgSMLITOQDJOgKhE4s17uMZTvJ=mZEQBN zPk4e@l(^$y?~K^Is$*lERT*r@S?+dR@T}Tqj$^~W2bLTg?41#tTgYxK7M0wMGuVx@ z{N1?Vs(Qm5N9VdiGY5NTMCUUkI%4X`=+t35uIFyYs|wDYZRa>TI~R%$_RfgTcQPkBxg8_crcp+~0Vh@nGYj#>0(A8jm&}Ydqd~qVcE3la0%?(vhEjBku?B#10jS zRgMIr(8uvox@Dd{(b6-vLsP}w6jlk}V449s35{pM}e<@DP& zDmr3b`rsESxo%kK=?MGo|&f=q#qr~`N2krPQ z)5#^VxKJSRi$^*@q4ZlQLMYG7S%j2+lo%oGpdF#Rb%ewrfD!UbNF+i9=MaiCa~2_` zA|*x$J7`B}IZ404@GFAl7Mx=FNfjV=t4Dtxg`_zc+3=iTZu-sNuD~|albn8gy75fo z*~W8?=Nm6HUTpli@lxaE#-*Ab2oWTZeyi&j5IpHOsBu)PhL{!5RbW;h(m>+jC%~*I z5P#~SJf!0VLS`j^w$(u5@jSq+C=h=zj{_mI53%%~hrMdA{8l=gL%r6rNFB#PpG zGpTXWgep;l!QL4Ui|47hhy{?7ej{-Sh*N%t2%Aci!~JGblPD6IjZ(Jb7noqv$xpwL(1g-&q1YfnnUmGDNztdo*kJFB z)$~Rk8?nvjawi&_g7XHc$=t+75vRo1VDF6Be2Iv53F$W#oSgJqXy#yoYi^>`mGql@ zs^!T^u@mQ}-;C%K+>J58HAm6uM*8goI#rO6ext#G=Dze>Xy#yoYmQ>mjr7|}9UDPy zFva9eztPwfWH*@LnxoisBmMSm9UHNzFgD)w8;woDHH8VTIf_j;(r=IG*cfM(KmA5y zQ}C?91lL@}rVHt}OUYR!7FBNgjRvPE%fSTKTt%k~>9>!N=!mJ4n|?E*Q*iEJf@`j# z(}ncgZ6y5$$Bg2~-t?P_4Nt$V_omq21vg(LL!mKA^o!k z5=w4JBqBgOM?xhPKM;yU0_ZIoC^!8^J#y1;UXM^D5ZJ;?-%Nq%XtgL&{MKrbnSR?{MJJkm(+grMkbd*KMFgWcijLNd5~HIv zBQrWbD3X37@d>0(Lh(UiCNXv5H&bBtY*NZmVtlZJcIu?5lS^W8p+MqIzmWii(rO~26y6`VsT(#%d{VjZGWohXgY=uulj0wmKewPZT-~48hBcn)E zVq`RlB9ZwADcdEc-*jj~!j#`B!l344)+qXv7#mHWNNirxu@T#RK6fIqDL8MCnk33n z{tze68%3NFV}rdj(r+IoqMbOKFu~+~`%UdOIq5gQTfO}S({Fw=$DG0v($`i;b<;8|5L{Wj~^bRqqA64{N#qRLOdk>C_%IR(>ivyM&|(rUGm^vvWQr{r2_d z3C(XbPi%g(c~bM_<|)lno2NBTZ+@$JM)S<(x0~N-ez*C(=FXk9U}{mRJp~_4R@HaB z(pUovZ?d+a67jDWXS?xVmX}!)(Z(~-@T#>@!}yWdHnb&%*)Pk>ZNsN@o@G5AZ0|C@ zl2!DVkHBzzI?7f9hl{s`!Q!8V#D25SM6a-{^GepEGPv78HesZHU{6*bNPMdqybb&+ z-b7@bp4?;7nw#kRy+R)9ouTK-I-X*LMpz+rC?iZMJqC=CL{@tu#NBfD}(wrAB%7T27& zHz^3TjH1AV1r%-*V0M+?CSd=Gc_Ovp@U-O(qaX_xGFO;Iz!;Yp6YX8dkkrBxmp6=J zjE)XUi-7Ut>8BxFCBFXErsLly)vg08PM#34?PJf;_y)r3=H+i*vS{8Lj6H@H&Fd|1 zx)r(3knkr`i*`gd?bWyOJ)JMYzq1ix9gs&pTYbC)s=o)&Hn|5V4~Bd2che6*4@zw| ztdaGPAz*Ex2aF-A^&glO=K2pbirbOv-yC*p{j)&BpS%7Ce%8FOc~SG{%};eUK!Zht zQ_JID9p4d2A#V&@s{CB3_-%O~Yt?UDhqlL;M!%Z6V?!1^pJI)PZT{QxzP9Z{l0Kz9Y3GP5>4J_>L5f349dmAlvr4(Kh%MwT-WbvY1fY z{I}(UZQFY&+sop%@%vXSCWdYH+w!5dZ8}e4Rr`0M^JIe=6Zizd5w`8WSN&cJpK{3m zTF*{&o>1Em6R>@hZTqvz_OiHbI!_GS?6>7(Y}^0Qd4aDTcs6P8qBn}n^K`Nk@&w)% zHVXRD`l;1zn1{z%=K14EnJr)VGagTH*@b?__Krv!v3a~`ZXV_Xih}k&plm0TlT#Ze zC&#t#uuD4!r}CY*#cev$LFepLg`88ea`2}m)?ie8BqQ1FZK_63xWb~a~pq6BXk zPeWMb@d5zK8Y&Uk3~C3tl71k?7jKup)h5z_0}N1+PQo{qpd&Sh764Mv|k_wSD0q^u7=y zLpxzu*uDUSMNsXSOU}M9JI80bFI>~Sws~Fi`1E~YDVE6y?F$=vPMXQS;Qg63?!Gp& z-WLYb_XXv9XkYMku<*X%HIf{OuI&rs$@_u|OJHB{I#hID@ES>uO4s&<_v?Kj_CTP* z!uACq?asd7b;;QmyseTQpXt8vyXN)H8=4170eH>YmE-GxGzul#$#5*iM<3n}9;>8s zw1$iQr&-$pd=G3;8U#hNLLk^qDia?;iAcJ^|hG^@taMWcA(T+pF zhm!z;8RTAk5ZL2Zr8R3O7((Fdx&&b&4giS}VGiuSEE6wl)=q2tPF{rApN`vyZ|e$k zVE_K9`1u_$Y|Ew6%t4>*?yGL?}c%4go0y$D9bnL>yt^LN*ct;2Z@o zO#t%N^mH6xbd-&R061X!68G3Q35j(2rHs{(A6mILy z4WYw)vVHIg_FU_GvK_std2{oY=B>@!nzuLaXx`cUeenPi}J2lVlZRDCq6_1-^ueeb2 zou2Z!w)qbb^SowXu6Y!EnR!;SkD7;HmoKo*PgC>J-lHzd&0D>Px46qcx6SWN%)?tq z`N3(^*t0jDXz$_IT*zOn=()nO&qY)%9g;g9(ciHZ6>B8c6nq}Bhlt#x;n;V<^ZtXu*2b1pELd10c*KfUFXHZ(y9?hY)nq{aU2LfMy8@3l<1_ zV81Etiz_hFzQX{NeQ1_oe`I8U+XMRxrTulZ|4tS`*@tEc_7^T3;P$}&E7HEW`6Bxt zo=M``i@74)nKU{&fVW;A;kOFm?BjzK*?(~l6Rq)a)kL$Wt>OUDX6eiHk_E<|W%7WX zpJDrjj|U7t+I+0}c=L(opPElLpK3nce5U!X&hyZ8(ZEu^PIGRJwDIJGmf$$gfGLkA z+3tOnZ}%SMU9nPN(cc-72pAW;_bhJd-6p^KKDldKU!ijnJ<4y^j80wNt+MTO37+MI zL72NALWC)T;5^G|1Zb9k08ew1+#n!)ewvX!n7zC=k=ctQC|WzSHxOsZV7oYGRr8QB zXYX}t!VJ$FDb0uDcELz_1g=#s?0>HLeDj6owgor`s?I^q(dqe(Z`MXRhxd2JtcC5w z*J#$9<9`Zp4s;(*o7E~wsRlC8!{VI7=O@1c7lRVP=o;tPFNt$tP+ZOd4A-6wlykhV z^I@2qan6ANKF;BTFgVBGXpmgaK|mbN;R7)^$Gg)w2V%IK!-qgP$D7kQ2ikWzhtEFY z98x0_96?HOuH?{0`!473*(aRi;WW;H_Fc~5vrjn3ErfGKAIcDga}Iou!Faauu0NqW z#8zN|Wja&N@#p4C&6k_6H2>0kwYjOeS8MOqVac2WAEyJHqtkP(Z}*OJ4)5=b-5btA zU!z%bj*E~H_r^TIo#PBh_i=t z_=dxry#ZTd%x20tzSP>cwO?y8opX$1?l;6aKxO)^Z`Q^*hyQoRtc5#_KI60I90#Ry z4&{D`b9j4Lm~;58qz9vGoa3kz&Y^z=S<*eL9D~S^6@aDd#w#bztku zt%F)$X&u};q;+WPu+}$IImb9^?0(Jx9$oL-y0JMziJ||6YJ|p!-42;p<^>&f&F^ z9*nMWj?X7?4h)LRIe_5Xvw?Ds^_mXkat;LWaSk7Z!8x|qAi11_fH<7P2V!uJC25=k zF0>rio#UIWlUgUY9x1>%Fc%u)92-{j-0GXPG0x%toe_cQ zHQq+E<{bZ0fODYxA^aH*FNDKX}J|;-{Bly`-F3(_r^LIXtsB5NDTjc!$H*IlPU;n9Y=Pe82UB)(>0f z7vLP23k`CPPS2gbSsUdX-rpIs7B&c9qgiu~@dBI!-4AjOUk{6O4zHE;V04XhtV-e> z7!;Rt0KvCs1LYiluO*0FodW@UoWloUaE{G1NUqL7Kpf8D12H(q_Gvl?Vz`{chd?;T zXqwJ}_Fc~5vrjn3Luon(+IKmJ&pzQCH>c?wXy4@=KKq1oT&8snUYIiP4TNz-;he*L zQVi@f_O2ajmcC49$~n$%{iyZh);X=8w9ajv*E+xT)7DMNoC9wI1UN^h=Puvw9pxO} z-x-mBv(VRQ)|_L1WCZz~1O4`J4wzcD(+21Gdql|R916kZ96kifIX*x*M^xuP9L_o1 z*&B$nJ$pmV(#LG3oa1M$3tJbp{!MHMr4_3?to)6*RqkBOU5-~dSTneoE8ozXfQN;i z@{`s~EkQ_yIk=YFKYce`6)f?V>a`GW2||Uz+G3)W0@*m~@gvfRg)+a1nEV^_F5~V6 zUa&v6SW553t*@>69Q@NDfBOqwWoRAIII?k6TWa zKGb};`AGBG=8MgJTKl&SZynV-v2{x8d#$rt7qoufx}>!&rv{74s}o*XYgaKLC|ctc z>-ui;*X6!W-x6>|{cU_ZH6K|M?J8=2+#IY4@dAi6536s`Hvd{;K96o@blioSKjJ9#=FsZ}pzNvbNAR{}*CD_K?!9(b(%()a(meEjk!`+5zD~NjJ;5HZ#L~Cla%|U78DPy|M0uqWW)&_?_msD`jKbUcC1DTN z{%IP3^w0c+l4e0L&f$d{F~v5A0Wl z41fd=`uiDx@ZjI&d&#TYEBPSkN&p*3g-VJ5?cza#QUKB-IB_1qU|t9e`$CP0k>Cc@ z0$>=zk26)Emg|wQ-yoq7%M-kS7f9gqZek=3(*SxT>~qQhNN@oTDgY23?8U#h2QIOB zom<+AqCjIjs*HJSuM2fn#agk$D$+)rRy}#A6@QHrHgWf~8oHu&W$UWe)ve#Ou4!G{ zx~|pVc^Mim8fvfLQUbV+oZWqOwOzvS*xQe{Tt2<}E zx_Xt2&7?gyJmnGf+>ou)V}msa=OQ*;D|mD}#>SpEo*IcHHbv(RRwA5>*z8<%-eBkK zd9$nBtU-v z;6LTFW@mDec_5BVr>Y7?m`rd1%Bl#1;6hy^Fc&0(T~@_FNbmvbssMuUVLK_fO|~ca zFp#<`Cb_^(jW>)B1Qb@0Cc%xb5)kG`psB>Eu=l!mAed~tSjjfwnH@9wS-P*dX zb$ja?MSOBuI%;X)wlNXm7En+54c3Wlu=Jxe02{y%OD6!v@c98KOW#ic2_8_E{*Qz~>+QgPwZC1{2o6j4`Czd0GYAIrBE-@uMuHm#OFvEp zDwm~e2%Dw*yr3+7qXy6;;j(lBkl+Gk>7UjtofV^cyR7Q(DbGVk1Lml+6R>$}uL~bb z_qH;20>7o%vGhAzzi-{u`a|pP)*oB37+y~F*!(lKq4AlW9jE16HQ|27@IIl z_jMU!Q;em1jU>cR#HMR3U4DUZXflbVtJoBsH%NrjSo-W@(>0d<9=TaZSULv9W$ADl z*h}4D>7Ua8`ZRD^Isq_F1Gbg80F%rDTt%qBWv>t6e)_T14MC(aKeDYX&hG{gHrNehQ7F#E>!O~CG0D3Js z^N<11H&wRL(iM7Jt2vudw*sGV*-NVnw~XF|6&oAuKf?PEng=KvvjYKLjCVk~`jvFRF1f3MuE^I5tIip$dBG_aSt z!P58D0Qxj=SULqTP6M`;xB!%;e@1g?eJr~yogmmO-G@L~`VJaFAIdIErw9o?P?nA_ z=}O@n3AB?SR1hAP?(@Q6=|?BBbOR*85rd`guUUHZY{nCcv2^!r_8%fHOP}3Bnkh^F zbL*wn%dJ;he`&qi+SJ->hrM^$XNPZfJ_g$RR&ZBp`8Y|5ICoyMhWv=5Xb35hh3sw@ z%gs)%S+Nf8>TGA7%fQu@Rmh5bLIX|hLZ0gEd@==shABXhONU-@s{r&i4YZDUg!`b+$sQ7HPEhWv_~#~CqU3J1*pHD0dcDU^i=0{ypr_lDKSK{lC&@5tfR-; zV!qiLDtn|DgG$k|;%3-68Ew^NJ?m{MI$~bQ==gHZBszR*iJJ=14nuSj&dIo$0@3N( zS$U9(j#vybIy;GP{u)V75*@xC(xWpZ(s!~9xmP3ZYIHV1S#}1w9XuqK`UcF8TPk=` zh#Wg;XXUT%yk4#>v4ZiQ4}22Ya~i94JjIuBdVJ>1b$o!L7m5#d(2mcV&Kp^L%B!bV ziN*C!nO%aLKu#Upf%lbAk zP%y?_N%uNXX|%L`h*^PEpa-ip(9|v($W=lK5Hw5yLS`j^Hq$`sh(|87B0$hE1qhjy z09vGhc3q=Aa+wtYf`%zT$gBj=E%MWaj9D?9JZ7b^SX;Tbm8_w%M{0hFGOJQwe{V@0 zPbHB--3+E}f|-<7!~MO(T7VcRnMY%}w_joR4-JnD%o`b=uX*1)OAAK+wluhKQK@fq z5)O2GB=S?Bq}j7*gGRK|1C65!Jt@Z@bvRD zC>}69l5SDc&yFB{8Kb9GIO?^+t^%JEH>CX zBQ|Xv8$oR_HtgM&Fq4JY6x@#&&24OUE*2Z?oe`T;b!^0ws@i-VN9Wc;Ge=(?iOy$Gbkx+zqB9TZcwUr_mld2l?_0;w z=@g2NzB&?}JLK0<oEPX2u?UQVlxTMv)!SDyUpF!Pq~2}5W7RUqlw$>EYO-% zCYQJVudi>KwqT}Uf#}#h zqr~Xw3v`bLPAPQ!X5$k$I^iAb>(?7I>nuKI=O{5g`U2hfe8?Uysl}x?Nchbo8=%nf zTPQ+$duE+Q$m|~_Mo3?v8=-4#gj5mG5#qOyP=pH3A-zen&LU)XkrE@MFVKz9mgx8m z(r+3p?t@c9b4`H6Q$1E5C7(Y0<2Qb;6`+|?^6}fLmD4JxSAJMIqjF~DN0qZGKd$_w z@)O%0s7(;n9(Xa3t$h0bcJ1yVOZfzAp8$-5rhhm5d5y0cP1 z8(JWBdmiYlFp#`4&j-?-l>$Odsk&habXFKh-l^mR>CQ?4-DQqbREi?UZx$lo7LUECk%0EouE>#>$>Xs#OQ=A_rH7>THO5B9e zS4VCZPcU&&3m|g*hT;;~oZ=lq-Bj9kI6q8kTx=_q7#G`0q2t;IiyXh9$ON_*c$ZKg zwN4^qnyAFc*d_`^=1bYOoqT`^NGE>$hC&lMehbA$Hz@05HLWr2Q(|oN)sfZIZ)2lq zKH59s*c6;Mx;0rhu`!KPVr=x)k=T3{ZQ3OqznS1fj^9EvM;~ylo9Oi9_$|Aum4}mx ziKEAFBsvAzSRZh$qv-VF_^o4)3KEXraB#q!JAMnz9DTsGj$+e`&RdjlA z{B}7yeuFY&`eXL^&BR6?zir1Jzwx!oKYruwQg545j^ECy{Iqgz&dplSl#my#-P`uc1vMkN3&;***Qv#kKH+LenSBY9lwPlq_=0**$guKM~M;A7wFEQi*1Bd5zrB0kKb^F3eF+DNwdx( zWOk7fBcw0TjnMni@f)PyG+6BMn+=dSezU55`Q+*!zwvXe0L`Qyzgx^$p~IB#n7F6~ki~`jmVjLZ&`q(Mn!H1(n@T%m;)h9%i*2P6<6>JW6qid1 z9lzNb6WCthT|#}-I*E*Fq7oxxn3ByPR%!z9ld(>^7} zMqeE{VtUxdM$vq{cS5l#IB#@ovTkBy8mGkA=&K{KS%Nn0RBh4+OzhilhHWCpZ+y!8 z`U@Vv@xvs~oSq!NwNP{v6YJ=(Z@-b~6lCLq$8T#Jon9QjZElYW)YQ?(DD2yBI5=R= z9l!BT_4OA#e&dHppEBaHeE;cr5 zQR&$5$8RV$1=m!;IyyZ#e%k^?M@^mh@f(g#!MRiL_-(DD(}Ux;~dG7;47A&?tx|o3HP%TVsRz!<)huc8R2V@w}bnFUyOZEuvLN>4BH6$Q@XV z#14Ti8d&_Yyu=;&(2EBf6$18lyV2QM;Bom$=yUSyiK zYR1Ut;KHU)92!}?P=r)zF?lbATc?E`3a7a8vg_~wd`LbU5FVs|I@8@=x_o#sAgGVL zd*6{a2*NBEU|?WC4F}_&pN&7hV)>{U-+Oi2j4#Y`$A@potKsB}04hXUG*gAh`-r>& zkaoEU1tu(@$T0!t=G? z+Zzr~TWOdJvf+lp6)_@U3}zUMhdzN)GABH7rC~0{v}qHw5dq`0@fRUn19JTv(&2g1 zunw%atU~0`$8OW|2}B;>#>q=@Olfn%G5Di-edRTefgA9T5&C<$@<`>;%43y3R{m6Z zyz)fl$;wlev61J&c*cYswp|LzlT+jyGg+?H5{F>vGVOMwW2KK5X4=57aG-dTwPxB! zMy7~wX-yc#PQ$i`KWVkoU|2{Az(wejWbqItlT!H8i&H4|_3cCISM)~7p z>z}6GS^v^cZv9Vqrt)m%&y~Ma_8ZwAjAl$6U6QXlUe!&ZGzLn|ROZxg%ey_QCT}VT{I>zb)_Sj{QGo>_z!w>z;FT7>x1Q;cx8(!f zv3JyCgPVC@?XTf^vOSFnNDv(Ajy+3{4Swa0jpqp-TmH6uxI6Zj&De|b$Hw!7j4gg! zKGGd~r;)$OwFCDiL!YojF_*bJsp&pJ+5%Bv(fZNlLog4Ic7~U?CuOsO(d~&|cA=jM z?#QuG>Qh*mU z#fNxdyVCL9@B;fY$9>Lbt$E@30=%Go5AgzbfrWX29V9stJ>!L0>AaxB65s{aA@qKE z__0s4JlH{!qtY{8SY&x2uNkW8un1m&hDEj7c`kXpuy&4j%L{K+-ma{vJe|%93-xC* zLcFkj>Ev#Bf&H12cg|+5dEwb~UNF9gc!9gX!o0u^k{pSi@xn)vdBKDwzzeKHMR|c8 zBsnTQ(6oEJz`Eq|0&A7*c(=Upz3T4OJ*q3S4dAgA+YYaUrcv!= zdnX(V^{tPzgWIZX=V(lB_Mh(10qB8E%m#!V&G#b+!L$m()2tv6;;t|b(bp#-U_gL) z4}uU$QxM+sx&%VpWW^!YTTep3fB>HW%LRGKLt+hXCOufDi*pFFpg^n_@G`by z+>Y;^i=gqx^T!8mT{Rqxf0+%@lI=_uyxl3jn)jsRjyZag0V6d@rG%7eYKlMpd^ zw}(7rr!8W|g_lGAiUUDNHKLfSw^@uKv8Xc)@7xH5Y1^TE4A6rVnNX|xCKIT|mN$Gc zCj_xLA7R4{MJ5!$=>}jN0mRnycs{_iX(AH}VAt_CVMPx}B98ADTPOVUBKdQd#$gwT z>=%cOM5)3w=Z~XWxOZ<%Hah5??Gt|y_qE)e?X>S#_p0t)-KV;5b-(Hls{2a!|vIG2VMtOV)cCy54H(HSd_Jh1Swn%ReDr?~9sY=^2`*ry|rofiB6s+0(eUz{ebM3dhOZc2e6kM@55F$|${l_P51)JW zdS6x!?_52+#a+J49sXlzcz6pb9-JW@d-28-zIym|`AT>AC3yI}s~^I#7mv)4;o<79 zafhEf^17Hg`q14R_b~HjNbjL$C;4g*)g%|rFSaRN=Zr5mQSH_t+CAbiN({ZzDZU)t&o!@Mhm`=a&4l7@e3$Ixu+ z;xowHQPP9)SS%O@-0Uga%X9Y(50n#c`UKFEhQMqgA6W1>+XMxy@NAQlq3q5EcsxZ7 z2bFEb$j%Ux=@TKEOGV^WFX=tnVF09E0tECi*^mJ8j}~Ouf_Qxl1{sFEV7qDpen2M! zAYw=WX{&y3!mxZELba2=TBN}Mvjl`GQ`C4c{s*)1)gv(3_+AHK#s{;6@uyCmAjgC8 z-_FKgiLc)~MKI%oS;F`mZa6`X2jf4Rjjx`3$*w;H z_0;NV)w@Ri3Z^qAER^ds^3=$XuAE>Aj>{7;Yy2j*-$$+^o&*IoRKk2mqaMMr+-3e7-=>q1}gSv)mj~ znnVV!uz1hG`6(ZP%Y#zE=vmM4Z%I9e4vOD%K!@wj2HbNj9N8J>W`5710l1!ngCIS} zrWPdHb083}=iop{&+$)bJ%`5ddkzi(^&Fd|^&EP9zvtk_M?FWjN2Yp&Yzxlcav0L% z`#lFYKI%E{P3t-I_=IrQyxpywDV-NLbVZqLE~j<7e>Le6Nddydm|M-cBh zwBJn60aMF$n)DnCHA1}SFbICn!6D$DV@K3;N#MS={9cG=Jg!>@5ro$XBfG`*ShEUT6)i6+z<5}>=hR7 zIrvf1gVD2|<2xxmhY5<;bATUZcQ)XjW6ZV#v3(8$!1Np}1nD`pupqIX1B19d2Ma=a zj%HHNVKBU&gGE3+#|M&n4l};jbFky1p5x7I{P;eH8Q<$U*zr-%k-gBR_9b*r5TOyhTo21WE7VwYSU%cEujhH$4Xx6i?wr7zQNdyZdJe_6e_`m5?C z)k~|tu3lEXyn0n?&oQj`*!i9VJi47@@4TLa{~d|MQo-K-;A`D;oTod2XwPB%_InPv ztg?Guq~{pZ2+^LyB6vLqi-3EMf44mc*yhY$ok7uaFtaxhXTRrQ)8Y0UtkK%_9KWev zS-q;dPl298KU)&)IYvr%a#H|ZZ>-)_y}A0ol6ww)@E+(n zMoPcu*gLo9V1Gv<0kx1bTI-(UNZk>{dk*b4({sSoa-AkU#}bVY?>P*D-*a#Xxaash z>N#>}uf~x*hd+A*adu~K$Sgf)-R^VTTD`6MyK22a&!NvkLp{g#+m!C%W^G>2!T*j# z0A6C`24Cx*V`+h&L%Sd9IoK;K+;i}wqz9vCJ;(M*J%d$Wp_5#t}USGkXJZ_InOC9qv8{Yov14ZO`#Q z^}*^x)ky_<4t*9H>^VkC_j9v0x94DgM`kS$1ZT9?J;z51^c>p#V9&u_Vey`W9VI;& zJ?l9JlX?yv6u;+y2H%|xxaXKC&LyzzG9NhS*=eQ(&bsY6o~b@t{d4tKiVz02Sw12@f1{o%_a4k$q95fD zX7FHc_J-DCxLGKbpLb^J0EAQx2an~xH2yF=DmWl5&1)g-CkPFOu+;~x7|6vjw;wr1 zB9w6xHThS?9>!e_UWkAG$5Q&9t1ex(EBvR4^6f8pm0|vs^RJqJ_59z?zh?fm^KYB~ zhxvb;|J?jn=kHNDuyRV}?8@bp8!8V}9;`f6dAjmk<@w4Bl@}{7RbH;VQu%A;ZFuB|}*+h8qq{-mn`rzRPeJ@s5 z7fG)!sNwX^Eluevz3lH?w;3bGZS-}na$mo3yMNN;sT0(5?pb>8x9OdmmtNyJq<1ct zUgp~11J_=9S+nl^Oi1s`)h`rC?;K6S;q=ZcZPZnI+26TtGe&EZ-iK^@=jEi=dJgHG z$EBCKHZHxaS$BRWr1!7Y&oA2q7^*A^!w`Ieb5;LK)mN&2tNw1}0r>Nb3GnT3@LYeI z)O*KxPIdNdopUhNbS=IWG=I)c@R!A7rPAuY1u&NRC)rxP5(ULduyuLDZW{;}^M00Z zBeHGf{UleTH&)712POe=O$Opxf7Qpv?}tm8sIDYvwTD5fF5ua#gO)N1l zzgGR$h^Rd?21XZ;ErcARue;Ls#D#-{`jenw>m*V9e5^E~XcB`zLrDzS6iDK6Dv4^K zoFrl&-6RICL@&@Ri9xHbd`d{-8`b}?NnDhdMBO^UWiIlQxM-|2sf#4?KcfzFHU*Nn zmq{WFl#@j4Ba=k#O8g}9R$cj&ki@sD+uJ0H7p$WzQMU<@ME&ZfW*YIQvC@<-lF0vz zI?UM=NaDYmB#JVkTYSIM6>NijWRl2TiJwH?sw(@sr3~b>&k+62D)2(k2mo)Y{*6 zgL*MX*9*uPZ0*U<8R(iQ{xnwFyo)6AKcfzFHU*Nnr%56Vl#@j4Ba=k#O8g}9R$cj& zki@-fH`pYKuQJ3Mo4NWn5i$lJPH>Y5_lYyRNFx6;>M&y$kO@SnS%_I>9%1I*jkx3$V zC4LfltFC-XNa7D_=VeKRqn^C(bgr%!!q!Qm_|sVFLq(Gq{26jMU{fH8EtNzyP)-uD zk8TnJSK=fwXw{WZ2}wMl_CGd>dEMz;T`%A=-R@NUX{@wm7fIxQMjhsC3MBD=nIytM zIZ4DmGD+mF#7`n`)s;^PNj#{wlTBh?cREkkM97%ior*t=m1cL5ME+;gVa}#N692&@ z5eAAUk@(0Yk-HKL67#y#dAeRe#@y~y{AsK-*hLcgpHYW7n*vFk zYLW;8s1ofK=C9JAKfGduEa@V(5fq+5|VgK?JbkU;oKzZdNI6W*iRzp$CZYQ zCo%9d;xKDdAc-65B#MD@l8AlulgM6)m&AZoS3V^q@wnOolf;#Iw-`pC80MOLiy{65 zGT+6M82A}+n6)X8#M5;W#Xvbp)HP8$1au>H=dNo22AJvV2j18c+hl#s-e zY8z#G592Eqj)`Y%)K{^+M>Dq4^-$WugRR-sY(2Dm*;r{{)XAREqRB>tM_Z?jY#=2P zGvWE{F&@yFrrH>=$8KPh_`K9ywtMUX%0&{7@$|#!^4~0YjHhqFd~hYA^d@g$uk51(Q>MZ*KO4d`Khsv-Ixf)avS2{|`Je z*Ynl2X3a~PtOB#T3@%z-`pU>$nl=6;T;fEv(&LnE=tdelbvH;AgtCKH`Rh~=%IdeD z$1YRKUe%{wW7z^dQCB{tc53ak+Ud0)*3PJ%Sv!5?3*hYZ^0x4d<1*0?E4?0{zjd3a z4DDpwRuT9LpTNzSFxPg$FrwIJvOwOXCNNOxb)5*o^z|ti7!zQ=jA6vKrGlZ#7-H=Z z7}&GSgIRAq1p{LO%+44_Y^*65s&L@Jh}Su?su%L6zhA+?m;kc_h7nso3Wf?DcrdW< zlLs?lf`WlD0cHh;5t|bVhJFXogMpoiJeYw21p{LO%(9WMh?zE7PN3!62_QvnK8cd- zfN4I|#EEEJ02{?%D~BzZPoo43O!L9YWd$b31+cGUu;CRVQ_3@+LkSp|=7UX|q`>63 z0QSw1ui7w!x-i1Z?DuK&+~)VXDg1vuZ!C{iJqw?VQ?AYv9#$FJxjL#U%%_+NqsN47{>a{k42e3X?nC?=1dRfB z7efp4K|rulTFM#oX@fC}F#PIbF~BY#0~9OASI7~;j}K>L0;urEap8(06TiAx7-gD| z)ZahZjtgL0>Kh3V_duIr@P33}WHj24uyvY0l_EDo^43bX>-o)Ja1by&GO5Xj)=5PkBFAMf5#)ziQQUp?XbQw5|N)|>v#D|(joec ztiz!U^C#n^No74IOvU$QcO&YRD-n8qH!>IQM#AejvriBI20+8&-#Z@uHBV^4q{IoS zuZ)EM|BQSQE_QlZQl03WrCt(O?RET>Wq$lO+QQ;vLk+rL<~59sGZLSs1Ue9>{|;KE^)jW$;eV{lbXRB1d)B;1{ztT{v(YbVzpPzc`&I3d+NHH$ z*DkAFUb~|9o7$DNt7=!*ep|byc59|+yh!cxsIO1>{G^W{gqfXri&O``qu+rKsPSOl zeNh99FBZi+6HWB?cMJfS_?uJm% z3KgV)jkvjf{>__if~(avm=>gI{qyF@|A-3GhS$}uuia3)v367K=GrZ_TWhz~epkD_ zc1P{b+Fi9xvwf7|6+=?NH*jV=U!NIEJ3DKJRXN((FGmxz5n&O0KD%ulUI8;!>?8&@ z&k=|)%twLEb3G=&jAIzFg&5d8r!Z*$Fystuo=X_Dd$>o&>_Eh}x_Z;!fC#gEPoQ+D z@xYJwjXw%0oT#oQJ{t{+G|q1AE%gtR2;|Tw1Y~L+HeOeGShMD}V*3L6%19per+E`4+*Pbv(0oK z)N0t0=0Tukd6)~FG&hfw1Y~L+rmwp^oK!3i`pQTi9v^=iE_kAv&^ZNAmj-DJ5yATd z!NpC^=Ym#g6tK^leXz^40Pb26-$66As zVcTt6dn@Pn6uS4!EbZFg4t@!b?(O21!AXehyG)mQssH^l*reC}Q|ZuMHav-AqZem0sw6J!F#_j z9sn#b07DkQ+wwyILkR$|>oZ!KP2>>9*gAmO!081=@*VZC{B?$oV#d>(pOaXi-1Axb{EP!_wZUBT?{w$g} zaX^g+9z31_z|&L~z}x6E0KzOE06vVY#sh$I1^`b`Eh+V7>p*bd@|ho6Fmv{|2WQWQ zM|=!`Fv|ykduKVG$iZg%374ht*p%==?E!cN&Oi)F!+em*lgr9fruu(p+il`ca=K=l zuimXI!AY61>#r|yvN=1;;(+D_xRc?;RyI6GcVY|skT zwt$T&=cPv?`#5Xfr}_w7+onBTd#3hm?a#Hp)Sjz7UwfhUV(q2c%e7Z(f35wk_G;}* z*}md7a6&&DybtUvR`m0A($2`_##Z?l0|OERMg)v)5XO9i z;TI2#F+U$;;zWr7BLc=Egi$dVe*M50m3)kHSz^G5fYC%4RfFNR&m`y7d<+n65jlqu z0b@SGs2L2uhG0Kx`52(tA~0Y?z?hveuAFINfdnfEMwv4^9|kIj9u#o)!Z>1)1S<%^ zNmwROK_re^C#y3$1qa2w4WiTSNom(8!Y$pcSIifQ_KjDbKH2B{(yCP=eknyfm$}TK-3LNVCD~wKr;S*50bUU0YLIUH@Kv z_xc|7J?rnXQ*ks#qk0WD8``kgT+uZI;y6}<_IH3 zqZotID2t(JbX3vk`UoRNqZotID2t(JbX3vk1cVWzQH()pl*LdqI;v>&ZG;h{QH()p zl*LdqI;v>&RfG|vQH()pl*LdqI;v>&MT8NfQH()pl*LdqI;v>&SxaxDbD}hgQ5+g& zVHAzZL1B$7!Z=YHB{&JoMA7Kz9JNlGhDJxDG^$a=laho+SzjcLiUGls4;UH+)10nU zqX<@UUw)8(E4j?V&?vw#R+L6Lo9<|IulnBged_zx_pAS)zJL9I`hoR>>Ic{7>Zv$1 zvN%SgdW&frVTa;6G$OWFzsu368W93}D8h)*D8|6^BY+`j6fo5E*dJlUXcS{$8Vz6w z8U+kRqu)UoF&f1fm_`E_f<^&D(dai3MvO)=2By&fhM-ZvP&E1<2qQ+L7z5L207K9y zU?>{>3c`rdD8|4v8o&@V3K)t;zko1eG>S1WjRr6TjRJW9~ls2^EBs(y6+nEJ8xt(qdbPB(b0v9Mvp)k z5gH{JghqJ`Nu#3+6^$N*Fd{TcFbIwE7?MUu7b+Uv7hyzblwc4Vi-8}L}-*?5E|t%B#n+{H}$(3dV`r3>qZF*rBNP6(x@5~*2v8m zCq|t&#WW*Srq9Mt7eB`Xmk;!IQTZuz@9wCi4h@vr`V~u zC`NG@gXWIKP!uOd1dQVlMvUSx2BkO_Ls8r!MRAB47R4wIV^E4?F%-p#5y1~c4U1wF zhcPI{u^5Wt#E5`_s9{lz;xGoKI2J=uoEQ->c18J!Q5?pg6vtvHid&>Q#jhib7{y@> zN^vZPqPRt>Q~WneJ&WQLhfy4gV__7<$w47rzri?BiX%7)%S2J!qKx7$F%$?cz+LwY#qm~@;y9b`DDJHKkLy3FpItwv{?q!o^`F&$UO%t?5i?Cz#`YAe=I(z8 z>~I&iQfxBp!&00a5z@C5VZvW_yZTBaFFb&)GY&B!0}z_X9owunl+& zBZ40b5ym`&;XRf>Fy`fB^!G~)7!fcU2qQ+-I97zJ`B+J+UYYHUZiO&nRE;qRRr45< zs#j)vqaQ;UF{;KGgsOQAN!2T}z0nUNj2Km83_{gBhNSA1+1}^}5JrruF$SS(9z#;~ z%4~1+?-53fsxbzkY92#U^~!8-^j(HRVZ}tdQH(;Vnun28tpVYy4H z1{~GW{0qhr6D&K*@(wY{YMhfW#o&!MvE=8dc3@kKBPLmf;~ivDoP=oxZ@fty)e;P; zw~oYLa!U`6oL_px04^WAx|@(3h7&{{LC-|Mb7yr6zz{i6CW>c6aC zT>n-5lKQ3fU)L|IUtYhW{+s$|%=8~#9_zC0&I#CIS{+^vC1`)P1j!L$TJD7~VkHP; zkU7a?$PzTXTusT<2qRX4Fa{|>JccYm!^>3(viq^a%VQ-7V~`TWW5^ODM}%0}{n+8< zu@ZzaND1OGWC@ZZ0*2j>9bO(QK^TLSARa@OAUPsn*!|ey<*^ckF$h2K7_tP(5dp*Q z#||%#l^~2kxPixzB}k447(1eQ6)Qm)gOng1LzbZ7JA@G{K^TLSARa@OpyB1} zZei3=DXf@i3Bo9}1o1Gk1gSwGUT0vOXbB=X3CmrUAiz=U{bY<2EkOh)VT#ET1URY$ z?T&GxC5Yf8Ofy-607sRe@9GjHf}C^rgOU6aBnEK#*e^i=D^h}3o9;@`RrRauzpYxa}&sQ;*b ze*Mb&@9H*vba=!U^s>nHU(UAv&yu(`ysMP65{Uq~lSJ`z5IHZJ#Nf}6!vUKDN&JOM zq8cckMB<~H#K4s}Neo(bMS1iTWf!Is`M-zI7aNlGMatD7x|~A&C#v53xziqtmd+x%3Y>Y50t@aR_>uhw9(4Nfe*Bi8VH1k#m_u&`#XE zizM7fR&DTv5VW6BO>Y4~)9%ks2yAq#Hd8@8`N=V`(^&M>z#mn)rBoYB| zzb1l2 z&CF;LQN4hd2+1vm_&JE2cacQ?XVhWNra%%uYmx{9hDFZj?j(K=BIiYu82lM>IABvCi62o(R0HKCQP)Ii>@+rkD{+z-wCc*I zgd{#upJtPo*PVt%&Sesz^V_nEB=SF_4s$jIl9z8$6kmzNM<$8fmG~=>x9ZBL zgd{#wf8HiBuR9HkoXeF6E!kifN#uV<9p-EbB=L2VL>MS1iMl4jtn|85`8Uo$s`d5%1I)siQXv& zgr2(+edL2tB)(KX$RsgO}%Ph39#E9@X*~CA%cpEoKq+yavp|qM9#C%zbA^EQ#@DXT!Xq%l&fo#?1{NNiMGffX>+MJ zBIkdXEOKsRBA2{#8xx=bhq8lKX)YHRIe(-6X8o=D+x0c|)s62pHpxEFnIm#ONM*qn zS^`&6xdSU4wgUoJ3fFL>1PuN~3?nv$)ptPM?`AqM<~!GOcM8E!k@L@D7_n`sVBB}m z92g^V9)_VJ=i6f#t8C)FhUUNw=LfByh@5{C!-%aP<&FEXLk9*v*sZ>(81{yWoPPqt z*l)DD-#c_*%*QvwFjVAxF_r>{Puzk(N?*i%U&sLh(|nIyk@KxFm=q(=z$%WmhyweoWbZ?e0J&daGz#2Z452a>0)f}dq@}E4qXt81 zf~$KSzq(iqsRypCgbRA{c1t-Z2kJRO;1NQG>4Lq0iDp8JI!L9AH9ZkIKVB>AB#4~bmvUQv%a&F^6Mb7p7@K+cWIlq$dsF?g((t#5>w`iQmxyEE_a$moe5`X7; zbWJZr&a25H=QbvCF*&>#bMQ!C3j|R8WM-alyRuH9rJFuhQfm@MtBoS@_{Px=b zAd&OAJB0wS$T^Y-7qgldIVT<9uql707&FK>;Whq8Ikjj&B3Vg!0)3> zh>*y67yyf$PuBoalspTOU-S$BnB^xKi<}!->l~4D6eS{Z9(IF@oEtIqOpjbQJ$^TW zd_j8PVH_%Q{<_t)2Kj7zujL6$B8RBRc^JtNIls|D#YN5u6c#xTLpdVnZ)Bwg7BLYY z_csnr^oYoL7>J6Tzpim|M9z^%MC3e-Lq*P?w4sA6iNzlfIY&TLbL^HUqAHBN8*uyID?%*Kxz zXElD@_(|jJ#yO3jHqLEmwS&0G`Jh$P7Gmf&z)JplU}wi=*bqV@=by@MTeTp0X!9I_ zV3BiptU&Fdcqmll{NotL9tC)t=M)C*ABJG4$oY3NW>=!*NT>~~x!8aSv;25rk@M-v zBIg!GUb@pBDRuWbEQOfJIfe8@&NVI*!oL2E*VSU^ zjmY_b(>#dzDPLWj>Gz<{YOo^bIv#!=T#@q+&^!pVn8>-8hXU(i`nt=*NyYYO^p%nQ znLCn2&TUX68#o0p$Pi?IAZV3F0mVhmFKYav@yo`=jbAk`Xl1|JucRx+E?~& zM~xV`BXT}>C#Bvzu!~cX;K3;(a=t!65;IOAdH1Cb66&Z!NRG()1ikH;AaXuv(0q|| z?V9VEthE~@PiuA6%pfSo0UJ?kdn0mwCyI%XUde>tS&?%ZlW}J&HgKt;^w9^r%2|Yb zk@HAkQ)AK#k@M@5Mb2$Rr1#EJ4@QJ6^`KRv%Y{YGFK=AY_)X)=#v|E11H20@9<~W= z`5CEOVP@|clr-(Y*WAU8Mb29WAR=-;hybj}IlRe~si?aESmeB703ssi7{H30hXJt2 z`5XfvRhD^?a}0nV4+?nzTYg65{GSYf5GBuY;I+9ZL{?xs>;V=z|DXXt65-z6Cjzh% z;b8zQa{m4dK#7uP9(a#z8319HKZ~%)`2!h%5+%<7yp28sAk6Xsu*mt_8GsZe4~d-H zBnz{A04#F8fqudzE^=-msK|LZ4^-s*eflIgN93I1q|8|Oc&k=UhuhWKTx&&&KgC4ODNc$%ROEc~LL%oDO%OMTqB~_U)9iL=OST5OuT;0;Wv2`Z zk@I_!M9%FcV3G51Sh2|YS;->j7Dc+`)V83Tq_zdEP;Cp?h!&@~$obWc-!`skT-&&= zaed>4#*K}e8aFp?Y24blt?|3Y?G5uuYdHE3f5v=}h*6u*n9tow=?4#d)5)#aR}}vV zMugSzS^b%2_)GXR<`lzx*EozJK4Y#%1dQzwM)>pJ6l2hGR>%+W`ES605dmW{!U%u< zn_`&He~0}LpZ^97B^J~{7~#)pJ6vKR%IgBAb{|y-G zv&{1lM)>pJ6vKS}JB%Sd{|y-G^WPsu7~#)FsVxRw} zDE9N;VHolG?`%+*TmOS`BA@?ua1xe@`24rPQJ??b)u{8vM9wV={1WbJ^y8RfAW$vv zmOB48V@$6+o>24BpR&fho|6@tRRt`BSMhq+dPeCBIoZx7%>{f7<7KH7>Y(SL846& zMvO)=2BlFJL(ym^RVl;{|D2=ihibgXbpEnRjj7BjArBN0`(P$>*^9sU<(J02C zG|FNq8qI`!oW~Mldwz_jcOsEd4@(~BIni{@uVc7QPvkMa{gXJqhK0;3!1PBL!&T& z%Pb6y@>Y~aIh*ci^x?)MjYk`gHU8N6Q{(Z*6OAVuPc@!y%-2&9M2chGsD21T=q2NB zRO$y0e3zq9H6m16EBPoT$+Newy~nO97z59b0EQIR(IV$o@=;2XXBhq_2FAcN8o-cZ zG+N}`N+n83@(jb@$G{kvMgtg9j7E!`{~O9jj7BjArqKX~6r<51=U+k?F&f1fm_`E_ zQjA86obQA%Vl;{|FpUNybf*2q~HCrYCPCt;aLF&e;8-RNmaBIkoNuyfi{6vHi=|%|#p-~<~(x?_W-ydN_x>15bXq3m0G^$0; zt&W?NB+sbY+Yu%hghqJ`Nuyfi-0HYVN%9QC+Y}}kghqJ`Nuyfi-0HYVN%9QCJO3mY zghqJ`Nuyfi-0HYVN%9QCJNYCSghqJ`Nuyfi{67r6#YN8P3ZXR0!$=x6BIj3QoEVJ~ zZ%8*Pb<6#wC~4G)oL^=XfOBuT36j?O1)Yz=$At#=#jzNQ z;xdu*FIeh{ik#DEITXjjD2me}=fA`_QHsOfI26a?D2me}=jR!U1LOGZFv$%=aWH_p z?iq^XttiEDHr-L&9?d}=bASKDOY2rO~OC)?r7blc( z2linpPK%rmBa9funcWhhF^o1cr0}ngAt??l<*`W{Vazqt-TMRp@ndd21`#>0B8;%Y z>>$CImybb2&gUYG7**p~5vu0%A*ou6oNtLRV%;dlAXLp`NUGK%=l_T>A~*FUR)nf~ z3`x~m0xa| z=_xL9eqi&U=E2QFnuj(IYaZS_qIqQVsOHhlW17b{k83V4(?2G1K3KK8KuF|VmL7);WOVF+eBUXYi1}Q;21`#>8`>`>Ra~dmBf_Mxf za&GryV;gLf>@jGO3(?-6PqVBPi~&lJhgdR^YrEqn`bo7 zZ2qWuR`bWrpIec0VD42PxU>HI`aSjg>i5?ltUp|TwEoBXW2kl*Z2*7d9?yT-CUv@lfNL#@`ydHxFnY-~37Q##E8>YEa~So)$UZ zr*A>_+@kzH5Y3p#dE{p%yg?fo-ZYW($>XUa=fp)v9wc}raRM1BEe})_m*c3?Of2ky@ zfuif4`bgJ(#7XolRm7?*pAwRIZu4N9MDrRSFLGX;t$S;ThIpsWik!(aaLk)eM(5;&zt{klbEA>Rt<}s%Orx>*OV@j z$p4Hck+Ug~#9@;}7$_%+x&lKg997C#2rBmV~lSJ-H{3P;LUHO!d#9uT|wMopQ)3C_7 zOd@c|yZvm$Ya&b?{%6!-&Za;TzhjaJ1LdqlT@&S%k#}w)P7*rptxpL_ytw%Tn?&=K z>_B4^7CD#xfp+5NT_lnJ8BHQ*Qy__-Gf9Mja+0WPBBa8Rk&HO$CXu^dQWNFqez+K) z5|VgH^WSX}b7Ul|L;&2ciJ+Z0vx_A1Kch+HY#4__HE}1CL>MTZMB*bur`(nJbjn+G zEK(M&1QL}*aUw@9p;8Eki<+z zQi0_pQP)Ii>?e`C5n-|Q}u$p4Hw%-Ix3;+tkA z=60vVN0&|^vD}sTN#w1%@+l#Szisx}B<6LeVUcr5r_hoOc9BH>XVhWNra%&(FiC`g z;wzE($Rv@w595D-Dz0lTqY4(vT7GezL zlSEV#moO`lyAnT%yj52|B_#32=7m`jg)}!f7`w$F0^m+f%#^*0CNcOko^BEW3phoUQ=5|a44=B_4*c_Qc4u*kVwiE!m3 z{*~t?Q3`_lKO+vaHU*M+sZOF8C?|=!CJG^UpHA5;@sb#@>dL2tB;L_HKYMIVd@*JP zc*u*KS9y_hu_vrV&Yd)f4@+eu!sBFbrHY(e7*FI}LybB};xV3Nk@LtPD8iX;u?r+- zO>acb&(hk2xgzH_Ail_X#F=!F^T;4+5$TP{`45E*E za|_{!oQGi?k@K?=R8-`gLLrg!Fq9*5o_+p3QRJNBxgzHp)QzHCU7KW&&E0_RFT*fa*~FEh zbzp||duU-8DssLJh6#(DJ1|B#I}Afb&KF@Au{oh~<9=brfiWL~4Z~28^Cp%8kBOW+ zKuF{~4CRWPw=q~uFhPcfgRyc^J$UIsXEY=8lP+J7`GcJdEaw zoKqq2n8>+@mN4C2k@Jrd-(n)?E}9iN5BuhdoWD%b%m%qHhU%du_~we7Z;>o=j?g?! zEA8D1hi>Vk{ShlvRWgxtcO-dpQ&{Buf#!qFhnf#JA89_?e60D$=AW96H=k%e*?g*b zLq;!JkUXOo_pQfjK;#@AfK;~#pK>l#R2V%b+#?)m??WOY=N1L-F09CT7zAD~la})J zvaJn9OynG6Ad&Mh1`#=bS4Jj)Dn2GB_8EDRa|}a8&cjHq$oYHqjYO`BX?i*tlFeVL$hp2~H_b3eK9HERy%9OzAX((xMnpXSTOcA@N<6oH;dP9fsFV%o<<&Mg`za;`C5NI4->Mb0CGq=mmX zBIhf!SI_c9&TT}f$hmgIk3SVTuN(dGsK~j65wwUJ^bkuEk@IH^NL1t;gCLRfuq#C5 z{F1D$XAEi{LE-AU-Z#~@wnY#5-aM-t(pcq_di z_iMWd0EwK30kFt9k_Z>Gnin}o0E?HQ>ZC=^T@SFxxlvJ%iJT(@oFf1vavlc2BIicdI!ELjVGxn?FbWkp*JKHyQ`+N! zPre`=X=%walyE9?{({xCj*FZlAS!Ym_Q(-AztTd*Ma~Hn7C8??IU?sTW-Vi$$T>nH zBIjWsDsujU#>o*mM>s^}Jd8s{&L6U&i;J8iAS!YmMsh^X&$Li+k#hotMb5)ej>!4l z$s*?ni`fv$q{$s-b2o&7R;VBaY{boVagp;kn{PGWZmwyrZhfz{duxx@o~`e<_G<0j z+NZT|>yd09B`$JaMZ(}n}MvkjVM+?6x&WpYTeL-C zk#h>@iJWUx7gTO(q>7wJ20?+(1b7|qHV}dDjmY^XGzp@cQ(K(gy^xy()X}M{^poI< zoF77yAi%;R=Ux)r`_Vvb#4{w2e)%tdTQ4|BS`vCAa=t^hOOh{gPJ@C)&h>oqv*3!H z&!pnoVkyK#&MBlPa;|aN#jx?Z%0q8N&c96aAm(R4GK@u}gA-SLWuR2I*b}OCefn8iAN96ns zz3rGFa&FOlk#p^uizjRCM#b#a~A-M zoX;`<5s`BYU`5Wu09fSwLk1usa*hG4#Bvw_w)~99`9Bzdh{!nxumam*04#F8xdDiX zoMQkh5grD>BIh$QfT+m11;8TbVE`<0erE;{6*;#6SmZnmfJM$<$pE4v=N15qoQDCh z$oYEu375FYxrLx2=V1^kaz0(31m}pHQ=F6;3m&LC1w9ams&ws;lepptrO5})*lEyqEa_%?{HBSmf!-!DyR%CmZLTotv8FPwZ zzH1!D5T7wuBLc=Ugb`Mtpcv-!-(d{#`ES605dou#Fv1EH6vKS}JB%Sd{|y*0B48Mq zPxwn%fr4U~Z!?E6#OJ@&h=4I0`4Lv2pcv-6%wY`i`ES605dq^P2qXOYZ;D|){~g8< zpZ^977!feGKp5fAe^U(e`R_1>`206uz=(kHzKn6jUt*vCrYQFF-(eW>`R{B{!1*S| ziG2Rs!AV#q;`84EM}7YLKa4tWOyu06z%SvhMsMSafk3t3o9=SQBIhfOI&bcaw1idM z*Y^~b3+2*j&zAzq?Np42oL7k) zF{M!tj7BjArBN0`(P$=e z{wne#Mxz*m(kP3eXfzW!e-UBCXcS{m8f7sQjbqs5J|8hO8WTCU-e8gQFa{Pm-`LP7xE+5Bny?B(qcDKWEDVkER+L6Lo9<}z zSFKB0m$rW0x~z41>x$NIT35ENYF*trS5HMHNgjGL+K3(#k#mS^rh3fLs1Z50l8;i7 zJj3uFyCN94%my%|sE!;Fs=1YXjES6A2?nOo0EQH!(IV$oDlsNM)hm>A|IGW0~k__MvI*9h%jO_iZL*a1~8-;jTSlI4q?P-6k}i-4PZzy8ZB}@ ziZEg{iZL*a1~8-;jTSloxTZIVbG#eHD1=4>Fj9<04GQ!3WQ-G~QG%1OOr#hM;HYl& z*d&p2JBPt-+>Hi&!6N71OBOk|D3V5;n|nnq-*uS9qfvQ9j1{I)-ljVmy{2_->$=wU zts7c5wr*bS*3&Z!@SMtKZLqgv$L>bS*3&M5|=Q659ms1`Z@ zlA*V_$T>x!G|IzB8Z{#4mtdS2jgqX8ZZxnIC5;-9^9zjvaPBQPLGpS-Vj@Tlci?ZQa-UL+kT)*+xXpt3>daQXG6-Xkbsr z)r{gYk@JHPMvUV0=fH@_x#&ifkh+VZC@vE@-xp!TC=O##ievpy6qkvdBWj3j^7TGHP28S4B)PNhT?cDN^zV`cNF(P>%rDTt%qBWv>t6e*7{@XPp!vW4;pHS ziJVu7R4}19p@ciIk4rydPZ30fRTtMl7%_@7yCqoUTu>a3At_FaoNt9N=0fh&=gwS_ zbLz)jwC5baAR^}hqVyCOIe)VCRO{*1Gp%P^e{TJy^<3-u)(fo{ zTQ9Xy6f%t+!flx7M^)x4+lky}d_!&-VMR$T>9jt3L44=Fghv zH7{sh)cj@hSItYCmo=|wUfI05c}?@W<_*o8nzuA>Yu?_xvw45>>E;{F{aOdLj&7aM zI;VAU>$k1nweD{{(fVua`|V5hS9QdbF%VJy6U_6L=$qDYVFyKL>WZaf^M}TE68}F` zwwL$lTadlnApeipKa!@h>NF9Etvc>WBLxvvCl3Tln*f0!VM)zLAokA3y}P0yqU_{> zh%c-Gh=@5nF*g1f_$U96Gyf=%nST_`4V#&Oxn^Pp<`{`7`05&^jK0Odgn@zeCeW{P zo2N{XXnOzN?S0z&wy&|l6c5A%r-g3wAVTsH8+1wHp8HjPT4c}Iyox|#(*lDy(}D$2 z(_&Ojix&|{Y+7ItXIiizYFdn{Y4NO?7GN8trFly*5H~Gg1UGElwBXI0X~7wFH!Xh9 z-oJf7dnX-CaqJqI7Mgm;g&kgF>Y(yXZd#}zVU2wSfyAZ-1|icT03xOZfT(Hl1q2eC z78ry~ivWn27678A#g5sukhVF~0s)Qr(?X8mhRvTAAu}>9c%$y7#X;?Z+lRD&ylfL- z#j+|1z?1#^wGV6`+J155cKGv*3GhlC%oX{XHY;zt)$G}`KRolFzx0hS&IHr!ytzCD zhFdsiC-FYsSgABh>&ph^zTKvRSGiURHvLlvCct}jCC!ur6M-p_6zZg@1Cu{EP+os( zd4n0{^`@-4VEk@T1Js3?tj^hL)-0z>q<$H_soZP+|I4$!!`sy?W$^k!UdnVw0H#jL z;4jbby=Q$#wr7vrrB>O}(VUbS%_aDPpiY@6 z*kY9}g=5M&r3Im!<(i44|iu5X-C(bRQN>cn|xEOpqog=4Vg?5B>qBqnvN**oA~ z-^uMyrl$_o1J1Ykr4=cuW6fOOIHRJe+Y+TtY_UdDhkRQ&2HUKD>bOf{QpcLT1Mc;m z+ODUk4%GwBw@T?#DXC-4T;DjOqN#fiN}brXj;0Rzwr~t~uKm<;m&BxwHG2o#>pQ*u zf%Md&dcgTsE$x_+I@ZkfjWa5mx-}?u;>0PMI^^5JF*tYfQ^#ErlRDPy9dNJjjP^iw z+$A>H#r_GqGr!er^Bk+RgT1zF-(=Cy_=>Sod9{-?xiPOsgsrx>80kA_TOJ`;={vY% z42|E{Hv#PAX8ESs$1{YUA~?W)br}t>WEbJWW;*|-gnBc+89#)Vye zh~T7IT1qD_QQrWZC^Znli%ht=GHaIe#X*FF^%C`NkBXO@4%o*+dWq%r`uob$;BH?0 z+oB9R{QVPm+eAz+l2m4p1RJ%$rkMi)xy{vI-ul13y4~k@DQ(a{sjuHa_fKAb>VyrZ z4otBZ_tAl=8^SKww5jEdU>9uTRbS7(cDwD0#mlfF*Bs}>1%)Lu%}>CTDU-~wa+ZD> z;xS$R4eN2u31?dT-0E>frt8$Hc36OVU-lkO_Qe{t=H`SmjXqfu0oicF0W}~XT$>?e zpRCCcoNvCOprLQpL=dJ;8&CrR!jt2#K)5EV2^Zh&GUOqRH818(w%w*BOgDMooikF# z`7kHtgoh_1oSoOc@|x$xe-f(!rsTi|FaxJdEl-6RxZ&g1EDJ>-*nAc?BxAq9cCrykYjzF?d zgfPTYI%-77pm|LO{vviy)Fkm27RG>mlROOZl#Ut^FwC>?aB^p3<wq<_~FlWjFAv4@dS+;5irbCA@CO)E9VhASWg%uAy(oE8Z{zdwDr7#lN}o? z=W~Y`L)hi#Lq6RiM+A&B5r&PG^PxirBOzAu=@xld2Nee+xJi{vZUib4r4Z7#KSxK@H#%q&SSjB_U{q%0|dWm4tmJMM}c1f0Gq~DG5{0 zYoFh~pnYNcqV_M^zieOJ{#E;u_NDD#w=Zk&W|mjv9RgTh`X*1l8Gz@Dc+j-G4_6xC z>0TfOi1IfOhF!vbX}}m{3G*1DG>9jNCC0xa3`=+Z;=&kY1@jo9Gyn#S2!8wv!VoK1 zl^=g?VGOc>c?@W)1%_I{_O&(n#D9k2FD;Bg)-R7i-XZu5@+0^Tfs=Exe0dD=4#7%< zA(pR-m0y0aA7u6N7~~y-7~~y-mU$3SJ?)SW9Z*1SxKG@98$RqwRZ}eW0c&48;dEz6S{f87-YKe7_vePFIThWWP}l`5Ez402p&UL z2>H?gRH0)LhG_AWAAW_v7^Fh*7~~QE!x2WTLSPJ1A$Sb(h`;$F8qAkig}@l3Lhu;m z5&wOVAF&F7F-V2rF~}qS_FEeAf&45V{!I|ZAQghgAdmQe7x@vZ5Ez402p)qx;{Pqf zsL@CKos~{21P?-R;)=Avb9@9w##A7+$x_8vlMrk4+9DnvFSu-><_6(Ig1lBrnF>naEaN@WNGDnvFS zV0;Z>SoZch3W9;yJA?rhLSU%={$CM>WpD2uf?y!_4q-rr5E$zI{GSnqWpA%S5DdiL zAq=Px0z=)Ne-2?-_V(`12?k>C5C&8TfuZisKZP(Xdwcf~1Ou^m2m>mFzC5C&8TfdL}|#>n_fVwXYL#u>umAXPej%Ap2u*NMvzK`X=%A)AaL z=vfGUm0b?Lu2w?y(WFrE`w~-$)UceZL7eW}o3j#y&!ha%+7%yN9#0wz| z;01x9cwrZW5#t4nfp{T=0lXkE6fb-kVZ?X=V<27#VE``(48;pOBa9d?U<||yAq?OJ zfuVR|2ZRyh1&o1sA%p?EATSg!tWdn5Y;$lnM!!>8Q_{ zJ!_VCq(cygJ|PfOb1^xK{;YM7i#3o80k;Kk6dcpiCkMD(=!X{A5g-qLTpwLoz-;@^?5HNVRUx;H+8xBLoBzvH_5(*_gU6vjIwug|eY9&dtV& z(Sv7$m&6)2eH$z7?9@}LB<16MN}iaF2=h*VKTZ54*05m=)Ubsxpkd2K1PuNC zH1U^M!-g?X!xqAThAkTrFg}f96>Hcq25Q(s7|^f@4AroWBaB$XhA~jX7Q%prO<<^o zZ7ITtHEb9IHEbaaAVYzn8n&$wMyz4O7^qz<^hR3 zcAE|12F%P3dR2^>m>zjXYJS+SATUpunXe#tPnh+;-ComP-C2?}D|Bu2XT{u7`MSug zIM?P(JX;i+6=r;YR&W4#R+KG5Y*ruycUEu+cvkeGSs{vD>|yL7gCk}Ilstb{%q_VA zV`l|x=FSSvXzgaj?wvh4dv-QWnH9rfu9#OU-xiq_=h&P@W`!N!pA{Sco)rTYAu=m4 zf;%fX1UxI&pjjc>lh~}VIAT^nlj6^cc_lYs?5tqT+*!dHt=+8HtFw1!pUw+Ov%;(Z zuYwGg%J)QO#ql<0u~}ip_h$tMfM>}+8klI62h zE`73Zfx5p@|69Dvkqrrz`A+>H;kHAO2YM~YHo`6eL>!o_ApztK1R~~#^29w3p&)32 z1U-Q^T7bZi0P+d~vA0g{c?bm&w@z6z5CjoN<^Tdi0?2a+#NIo(+d&jW+&krgi1Ta! zQM=ubBM^J@^Z$HHXseQ(w(F82J zp#mdA;C?#tKD?nK;69dpn1S0+p_s6t0+?z;g*xd@Zdk>A{d&_PvcHu(3R>jZ%s@SDB0bJ7M7@l{KG+WW@`|!T3oW@KnU6CPlt&g z$H)$YxMatH5VCs~c@iT#4C0a<2SUgW^H7ZJFo;Wb90(!12aqQ*vcn)Q*>NC*?Cvf= zb{Z%^b{v*Vc0Vjib{I26c5_SarwKWd+(?I$OT93 zA!D-R93!84kvEsjSjziu$?mAm(Vb&D$99hE9N#&ib7JS7M6%O;EJt>58#O6Pc2}Z> z6(c(h!jT;ZLdfnZ1QH`V4C0a<2SUj1F$5ALI}GBI9S1_l4)aiq>@bK+b{q&HJKSx@ z$PRPAd*&Sb$>@a4C?B`p;sC+1e< z=5@|&9UjSR?v{r7BNrT>>^R3fvg3@_j_gkEoYFb9b6V&0&JR0hbk6MjpG30LM*mb{NDZI}U`9-5m%dMs^s)B|8p;kloD)Bt~`^ z#3efpgpl3U2qZ>!7{nzz4up{1Wd+Di0|m&A!*a=P|Dt4vF+*fGSaK(KH)O|-;*uR_ z)MK*S8ScqFeu^2tt}`Xd({pX@ltJhJ1A){gAX>ioF#lg`lmoZIpa9u% zST5NeT$JoEW{B+Om)yzS4cW1yxXYb0>M_~vipWkp3>PIk9Ue(`@JO6bcH9*+WXGDN zd*3bDUDCO<^XtxKoy$8{bbiyhvh$5ZvNN~u%xP?;RDO4q?9M?8D@Jx2gd;l+gpeKH zgo=?J264%b10iI03-TmJb{NDZI}U`99p<4J*^KlYcDUP)ksStc$&LddWOs1^ zveQ5Tvg5E^vfH~T*%op>rYN_ILtlI-BwT%YW? zD`v=!HB0xtTe7>l^V`lfoohSSb*}H+(7CZQBa!UP?K?wu)lzx$DA}EWC?ZC78iXS| z4up^$-h_&g9R_j9jsqcNcNy{|Ms^s)B|8p;klim4NQ~?-h)Z@H2qC+35lD>eFo;Wb z90(!1vkH)%1`3cJhvkypu0_cXV}{7CT5>0MH)O|-;x2d2sK;dYaYT0F^?)eZ>F`Lh zgO>z+vg59pAv@MA-TQ9I?&i)dom)G%b$-{my>mzB&dzxwufk(0GX~%zmqXyYR-E#M zndTU|7-0&I51@-3Rgc>(a41jAin4jn4PLmL+CO2pjgo$sVx;E5oAj0RyqE0YbEs3N zmN$gYp-x*hePlE7ToyP#ikzP}YnJ zDi(@9b9wF?Zp|z(@O}#l49Io4Uy87S5vBzKGhv+u=GLNt(U<22X0I$TAd7_p17EiG z95a=*x2hQ_2FfWH}B@ZPqOB@lX>OVOk(Clh$cq)&Q*tz~onV z_2s#NX^eaxhM7Kb`AT@X9~d_9ZCAUHq@jJdFXM%>%dG?Oao222c*6AR@s|OmoEgV! zm`Q-Lh7@4&s4x$abEmLbI$f2XB{8P&rLNgjgrED0^~B$I?(W>vxwms)=MSBarq?gM zDHEz+pmNn!{bGOTMu9V0>-x1`di}D_^EAy}A3RN5uzs^J@s3p+bXdSH51zrK-PzjRuU{94brYDL)vrIN*DoEIQ2h!7Mi+>66PTXW zuMefxFC7-He!+9YF1OP9bqT6pViO^D4>qWgWDSC?1iyZzP=lS}@U0?C~#g395ik{W4 z8R_*)2PRa%SeFXdFLspl!1Szs?VMh}bYMdDi*>1R{bEN+4@}SM*L~^rO9v)YzgU<0 z`U}=Cc9itM^sIhOPpw}%EL{D9N5NfgrS;m)fsiZ1DX0#hRtZ zxZC>m$IhQRk9VHvJlT1wb8dS5(p#sY`URq>UDYr4cWx9oqqVMIccs@a>pWk-xa%uk zzt~aIL(#MP^=5kg(t!!pFV>~P^@|-PJup41UrW;Kmkvy*ez7hUu3zjZ>4E84{kkH( ze(Au3>KE%$;rhjnk{+0z)vq^F>z57-SHIxtewSNm{W=xZFLCr4tzQ~R)-N~!_3IZK zJimUiX6Z5RwthX+dA9TC&R;sub)N5hHMxEn3F%P%0%ho~>KFSvHwv85TGy|8lIs_8 zp08ir^%bvQ>?rA>=vn<*lU%<{U_$kab*XUuVn<02Owa1qw#oI&1SV9!SeFXdFLspl z!1SzsU6owFOkhIwi*>1R{bEN+4@}SM*V~Ep%Y=oiU+}_)%dND2or~&M-m3@(N!Bm- zRRr}%j>`S|wU#mNwtl_Xd8zYq=atT1JAdmeNUvXd+cZ?a=9gA4t z+w}Tno#*QpcYVd{7duLND0)`Eo=vY`IxwO7#ky3uezBvZ2c~EBYkqqD(t!!pFV>~P z^@|-PJup41Uq4H)Upg?M`o+3bxPGytqz9&F_3N3``lZ9d)h~Dl$K_U9zs^AQEAQ=+ ztu&G>Rqop*>W>_i`}J!rW87{1dad(%=Z(&rowqt~cly%nm)Q8WNe@NO>es#L^-BjPRKHl43fC`ol=Q&#tbTnUy?*Jy zgz6XTQsMf=j*=djp4G1t((9KFOsIabE)}j{>?rAh=~?}{C$)a*uyFMYUaNAsmDaBl zQ2ok#VQ4FjBukb1!jSqSN9BI~TFV%BTfbH>_}+ru7woZM&jsIKaA|t|(%Yt?`c*CM z*j4>vf9K9L&SaQ$LONe@iV z>euA-`lSOCs$Z;2h3gkPN_t>=R=@U0uU|Saq58$TRJeYzqofC>XZ7o{)cU2v!qqQ$ zQ_kg9TE7lJ^(*fku&p$bELHA1VCs(?mHYK;Eo0nm{n~rMJ`46;u-}3oEZBd+x0Y=W z57|##v2<)9ydk>kACG7s)jpFIfN$peGr?r3BKC}Jv_T}xH+ka^PvHj=v%k8(? z-|Kw8vv22s&XJvyIzQ_Cyz{HhRh^qUcXjUXJl1)-^Frs<&YI3%3l3PY|H$ny_KXQb z%T~aVqJFgu-Xd~8<34CV!Fh|Xw`eq`VLtzbL1|y%9f7i zq|Chd1HFcxi}D>tSY=B`7mm#-EePc-*G#yUXH+z6Umd?6JS%6{7JVpT5c>w6{6FAc z-(d?5Oi!Jjm4Vd3lk6#}W6j*uaYjW`w;f7d&hz|(=6QaZX!<;VHZ!?P%GMm7bgbDs z;9lPm3wBLUoxa@-qz)e9Oi3MU=K97N6;0g`N?p#Qtb>Edw}p-bQIeRv2i)sB zX2GK5)R{y6K$!tVmK}s z6ZGI*lFg!11E?KMDsp7 zb8P#WA6hVT_P1dJX3ka?VO-edL-hAgl$KJv?Yxmq#W#W`4t-*H+wJ~8>fSrdj^fPs zKSvXe!i>ak*Z6U|*V>@66XULgSP&8|c|c(9cHtYQ-z*;!HE zC0T-+e`&dQSEJSPxpDaOp=C zjos$?a)HU?(&V<-SIkP4eF({nTZHWXJ7T2YR5V2sGuSs3<8;{=<#I1$us!&tOMi|S zZ1+Tzq5e^_A*CO%Z<58BG>J2yMPU4E%5a>0sxbI*fEoQ@-=BofsX_LE5gRZihX_(7$R4HhZt$D^v`jr{qV>Y`}!m>M6TvYMmWrmp%>$!f7uE#SX}mau#ZoQ z79m&1BSxAl{oGTP;gKu$?MYyWT&j^Xo+4?Smu$_(=Vj4nHTJTSYvLXHb90E-OWJd&H_vA6ebOQ{5 z+wrWPOrOpn&?G>{5ro}6#t_FOfu6vPV-{q_3=V-N0kUxH1JF?T0~5FmOGrBd!I~wA z26TaB594Maxwl4n#E4bOvdIoh*!>;u2(UncRZ7n^cr@47U+ITObJP3JtDaw7UA>@s zVfCWw#nnrymsT&UUS7STdS&&nWO^+|a%Wb)yn$_n5Qnq8coA5`GRhiQB+v3cB1Sre zO>4jmWeU>_W(~j)Q}_pn!KSdy8Zbkd!8C(e12Du4{tjZW87vs)+`{*EFBo4t_sBn;EyFk?YBgInCacl*Wp9wJ0k>cWZO_tSji0qT#MRYns@GPpt6pEdp?YI=P4%Yg&DFKlTdKEK zPfe;b8gbn`$bGU_2ywVNqY-e314)PAEkf0tf*3A`zzn5iXa;wPXhc-ZD#Ty~BWAK$ zFPNc}3(epT5sipyISMgc4uKhpL(q&a<`B_{aEL<@!{rc|p*RH1;0_Uu2!}WTF!%W+>z&TsYA5I_R?~~ zA>tOHYW@W=*kB6vHdYl10}Z8(0S>_!VkCcz7^!+24xuoRdfOP_5R4(z`+JCys<&|u zp)ino+Zf;wj3Lzf+lY~>w{Z`lFpzrN7~l|$A=G;@Vx;PA+(Re~q~10LI0Rz|^&UZt zRK1OR2!(;v+r|KgU<{$&ZNx~`+qj2N7)ZTs3~&g>5b7O{y~%bNM66pOQVyFG+Af1= zK%XbNLRh1aLfB$rg;1Y`XdBOB2}$fSOn#)guKH;8vFh)tk5`|l{=WKQoZC8N!lesx zXNAY5x=ldTU9d4g7Z^k6!uJuwr3;vWbiu{|U0@8M3p*o*OBXN$>4J>`y1*Dh7q&wTmo8ui z(ghm>bb&F1E_@3yT)Kc6NEd7j&;`a2y0Ep-1reK}3kiqN1<`;$Pjp?dMj>6W#Y{{W zo~r(#`gHY~>L07mR-darU%hJhCu}cbia5S$ya{$Lo{^eM26;;@LsNBV2z6L#ssm~l z1mgR{pJdOe`5(irIqa)!>tnZ>vj+yu^#ca7aP4Wepz2Uab-4>D{6EKc%;TMWYa?hR zY%yXa-c=P^eOjFyEQFp`%Zt;WR_~__MHnPQVeD`%z?rEp41?^Um^?Wi3f3+R#q!}# zp`qZg0WlPVvjzr?{Vs(FM{WU8d2_&)A{dJ)Vklh43l%mN8(}aQ&ih0Zd2#w!{PXax z(2SfGVGYKDzf?iII-sNm2BVfe80i6M&@c?f_QRjXgTZKDiw9!}CWg5p#p4g70Z8A` z=>I53KEZ7)BEZ7zyhHJrw8EC;~W59xqF~oxHn~33B zuwe#Tu-O=}U}FriV2cpLwP3>xv|zI_V8O;1V!`$e#BeRxFas^vYz$biF@{*M%|{H^ zf(0<~U=y(!njkqmSkna2fId(31)DVrX@V_gVhgs{s;^hysJ>bK zbM>w2+tqiftA}@F&eUDwCv}O}A&s?KD7SYY3N#`9{ZWlA(*{eG8%$9U&4DCb9>4lk z8{==0i1#6lrCHiOgn0nU5N4zVrfZfrE-`^^H)eGKUbzGUGzf$#W3NJrDsgw+ zzsXBEJUOyBRGgl$q&hOgSb1axiTc=}E+aM15SBsQ=y$za{Y&+|>a|`~A-&P8irJ;g zZH}rqJsmT)8*QtKq|J6tAYaH zs(3#oII02@^s1l;xGLU8Rl$}guBu2mtSVrUVpheLB|TweRghtNRZu|_tBO5?y@I`i z=e?>TnE{4_z=zt`IjZ9Dbj(~;k+g4C1qHxW@lr}~RRtpGRY4JORXmHTf-NYWRgrL5 zRlu^+tcszMo-nd1$S}PssGx~e#lFF>gZ+Zb;&=Q)c2YcaSv=IyR~B>9uVCO4<>3b^ z+&)W{(&BP8HY@&r*l#)FCc&BSlrIvtL-dB5{xl?oC@0E0Anbv;Xc8cAAPB1u(G&e~ zhzdakV(kfgVh#{!5+E-lNP6p}KMzqM?A9q>3|JxTkvTxbz0-3DlHNP%+d(RX-8*GL zloREjK#=t2N#6ldA?)TU3!4wT8K02r6J5gR`8YjvpV7<6u z7MHu^riEj#QB4)m3Yz3`Wtc%?l5Z?(PvsJHqCA@=4v9YSRQ;muK6snlRN!9POEuXZ+1JyZVj4P%n5}KnPMj)l-N-a zMeJTg5SQ3th%R;%L=n4Z5X2>R7@~_E1yRHf>yS(AFhmzS3ZjVJgQzDivBMBu>?nvL zcK75EI|;Ig9mUec?zp^ShnY69n_be2yA!b^ThXUG6;!a;orJ_L4Z^y#!%?5K{F{d?c3*c}!e9;^tC2#ySn3RVV32XbO%iJe@>Qep?UQInlwcO{xw zF0qpkO6(|zB6d$9h)e7+L>D^>qKMsN2;veu4AI4of+%8#b;u=l7@~_E1yRHfueM!c zhatMyQ4mG!*5(j939^VC#nQ#@@VsJ&nKrT8vZNPxCt^poqEB}!s9>=>7>QlRmd2b} zGCf?^^eqkXM=Cj{*ijub#EuFQz3)`)jt!0rRt3igCj=)3Cj}=5d&ILhOYGz$0ZQy( zcc9NHc4r}paEYCSP+~_x6tTM(L0n>oA-dR65Jl|nKoFPMVTdkv6hslbn-Rn%b{L|I z9R*Ru?rH>ai5-UMVn;y~vAZ;f*h!E@>?oElc6;X)JIu6+-B3v{?oPyxY(*D4DyU$w z`#BOjHtf#ZSeYKKYcTlAPM!E8l^j#-sE!$8M+Hqx>`o0%3r-Kt2+j=73eFDB2|g3o ze1_N!${l`6?BLk4&75K7VL2qktDL=ii=MrHrlA$AHx7dr}~h}|PdA{=6; zKy?nvLc5D2_E&*A@j$-Lzw>+oVDNLK# z%_-@{-HF(dt>|J$1r;oIyCbn<@1VHEE=dp9HFy)n6g%pQi9I_q%)j@YuI$bW&JR`x z7X%ju7X=pwmjn-aid}O1PCTH1Gp;`76ua}##B!|c1|@_NI|`zR9lrTD^>qKMt~s3$J5!w_BUD2O6A+cj`B-Koa2+I|-r0j)Ev+hc}^I zVuvBR*ijHg>@Gz;afuy<=we4f6tP>4ATF`P5MAsjh$42UBZy1vFhmzS3ZjVJi8;hh zf-GW3v2?Nf*SunfnKrSTU($=a6R{&((Wg5VRIu31Lt@8%9^e!^nI0~7@FM|J?5Hay z#EuN}?|r9YcUy3Ka7S=wa9415a8K~t;Bw!?80RF%#lSZ=L+E%9x>$aK7o3HoNgk_; zO7fe-%A~ITuI?q9dHp+|AW;YJt8c1j{ooP4eb?V#nGWB+o3V6~?_rF%^V(sIvv+ZH zzH3ta@?rMdSoT)@Q&HGqj9>CSj4@3N{1k>&1^<3?{DPUiOX)X~Kbpi8b{OMszK1cU ziGic7@+7ABBdwUN@=c!ftVsPgk+1k3#+W9?IE>Lfl_r0ri7D(b#x48~V@%Vc9LAWW zq@ru9dKlx?=rBgM(sOxOBIIIzY93~vw90cQdzimmb$S@%eZl>~1HpsAL&3wrSN#1; zZpzsF3y#9-$iK*cr)Pl*ny`PZ_xG=~^R!G;*O%ik;kZu8R{T>@n16lT-@jyHZ2m=d zDYt)-t@tOVF#r0lzkkWZ*!+v^Qfd&M#!j~4pP0h@>oI@-l8LeT7uhBM!-R{ON`?8? z=Dz+V(?a_CtLk4DA^&2V2u}Z!Bn!A7Y=7G6Uy{VF3U;YY|00uT`WG4IpW{yb>&f7$ z;19vm!85@hgY*6UOKzRo{0k06?a05#f2U`G3YxHgt?~D-wDYuoQP-E>zsOenQ&E_I zz3A^>GBGy)BD<8^zsOen6H}OfZRzh{GBGy)BD<8^zsOen6H}Ofo#*dgGBGy)BD<8^ zzsOen6H}Ofz2NI#GA)#U!Q1`1wyOShH1aR@=+o(6lEnQB9)OzuMJCVmFEY$O$DR7u zbHVe$3&D%QpMsZypLqLMa)h+azu;u(j{J-KcX}46pb7ieT5tbCou~bay1xAWMYiIf zio*QsWpDpV5@Yi(vP-%Bi)_U|F@^cpTyOtM5@Yi(vP-%Bi)_U|F@^cp1>XLZB*x}n zWS4UL7ukw`VhZ!GmpuI|Neks)@PiFqTUGx$9r;(*PZ1Il_b>gY2;z^Fl$-uF!5nw$ zU#|qO2J3^@g4csLg01}hOKzLm{A+G$yd(c2|D9fGRM3R|>mq;uN;^;c7j=F4{flhH zKNW@f*Q5UaB@<)wFS1Ly{flhHKQV>**XR8GOD4wVUu2hZ`xn`Ye_{&ruT}p3B@<)w zFS1Ly{flhHKQV>**E(PSl4+s*3x0#6Ypd#CtB`+X{kmk1Byp?Ke_bN}NJ+WrUlYu6 zr~dWl;H}{8;GJMY@NQ7@_b<6^YV)sorR_WNFY@2%l|}_k*uPHj_ph|`w0}|8m*2n0 zR{T>@n19{k?_V-8Hvb~Kl-s|^R{RrFn15~N?_V-8Hvb~Kl-s|^R{RrFn1Ai>?_V-8 zHvb~Kl-s|^R{RrFn18MH^)Hzg%D>=eRl2sS{5Zd)M}tLPoyW;B5JE|-2`dG)aBit3TomDOXa$5oH7 zo>)D(dT#Zq>TT7Bt4~&6sIISWsJ>s_BiJWc791KJ6Pyy98(bP(7u*`$8$1&HK6o~G zIe0VpOR#5cS#8Pi{m}NuyTgU!@JNxLAHh+y(w| zeY8~CUj2?c{IYCGKdZ*9D32IngQb%7kgWcmDe$YYsr{8{@T;-Dr3a5a!crzK%z4z0 z(y#jHfA*f0_pf~-9x@Q!tRYKwA&ic}KMqDq-5En>jY30ai^)4=dx#+u&1DQ3>Q|r- zneBSiVzfpT-?Q?8watbf60>ZZMHxeu{O||X8nPDoPxWAyZL=tVvzV&3G0O~NUCRo} zJ8IjGJq|sq#MkD0DPcbD8}#JAK=;ZAgFt!@ovcdB(7~JRK0`-_=|e{ag!&d}M-atBM_m#zbY$2j=wA7-+9Lm3ySu@($g{(a>eQ z#WjBj^)1lO35th~x+G%g$goY&z4D6MZ115<9`aj;4j$e63>_J!_l*k5J9M8!LznRa z!+hMgU{rm9As#yFl8B)r!!|+p%171){f7?u0p;WH)XHb*$S}QcR8Zcb>qSGC@$7DX z^6U=EG8k2#-Ni#kT@o>LWY{L?UU_BhQ~pDT{D2xd*s%2(Ix_J^3A$H4uJ&wvYB4-67-jn>^a*(L=gY5Y^EfyZD&7&Pg=6ER zrOF=Kps@q+;uhi9xR-`^fIFZj|b1c=IRzg!lrLF?t=omlHV+l)kY zXr4Y=H*KDUWw#IKB8v6^@CBKo9TtwIDbmlUPYGizE*sI+)ypIK*==VH|8*HQv3kR; zqxQDYi!Xn>w(HM#n>lY_KtDPw zwhhP(-{6}$ID6-rqub5gqB?WdFNbE$8l01+B@WFVfWE%8Sze_nYH@^6_K{{N2+cEE*mm^dXH!j2$#kLAR>Z(9Aug_7MD$!F{4K`2!w~n z-hz?o6$0Si>`KIg2TR${DmJl^ofYL>k|n4~R`Z{S&kFWT>Q;}M-uN2(pWuJ2KuPvY zgMHY({z^aW!%m-aeC>qViM5kzC)ZA?omxAsc6#lxSPxpDaOp=Cjos$?a)HU?(&V<- zp`oS9K7?e(Ekbtx4KdPhDw?8+8SI;iak^}ba=Di=phaN(6JoI46H$id#KH{t4nh`V z(j?A+7J>1@l;Jr0bUx12B6hZVMnBm1C&$KFi@=zV7-_D|T1Wj@c$r2@H{|uSiBX%#WcL|J6G)ElcGh))e(r1=1M>JRAqSN zihX+$7$R4P$PZk?Us$fb$h>Ukpksot!0e7poys91S>Htvwto~u9MuaD_N~s0%IfRm z5NHyzwH<=6osJk{8bVT902#`L^!IZJGzpMzAqcxCk0GWTUSG^(hQc41z-3rM+8GGeEI~A&3nY6OHv`GNHOeDK ztWuUuc38sh?{G&TETR9*+F7-;YvFvRTr2gG2z6oN6&SZ8Af>`$Z$K{F~9 z&VUv{A?6_lyPXyc)8a4#Zltpq+~O85f);@>h!_hJhG}t_u^^klEpG85Xb~8HJN$i6 zhs`T2dxLBZxP{H*FlEqVs!yGoGzy$OF^5g|n3FNvJ*NA#X@Vo>`>!yEP578&+NshX zk15~RCpcox|3W$htCb9gz$DWlSOdCFnhs%!QXGPgi8qR#ayZ1s&srVgvfAafD{5EP zuBu&KyQX$+?Yi3awHs>vakx685pakDNr&JqLe(6D7%qpv z45egf26u>PL{!WQ#9##@X0ll?n4y#l&EO6ZjfiSF7%^N9ff&9D-(WhloamL+phZE{DJj#UW@0cZg_2IK+P-hRY!^LvaY2!5tzR5f1Uc5yRyW zn4vfX&EO6ZjR=SMDPp)B0y7kcpc&jDq7mT`|A-hahrkTQA!r77h-gGO#19fhg&E^? z2ux8Og2r%%5RJlIzY24l4xw;7raN~C;E4Ht3Ffc~Z*>TT<1yvALjXt2`SYbiu+C>V z1SXjd!5YwY(sT$*l;RL{%)}hx=GxlYEwx)~x7BX1-BG)Z1W_Ye!@jy#V`9ilC^mzEO_5w{3c^8>_SgDKS8SXC$tG?X?5I0R#ek^Bx~r0Q)r zgu+1TZDW8#Fosa??GYnYZ{r?9VIcLkF~A`hL#X#CVx;PA+(Re~q~10LI0Rz|^&Uoy zRK1OR2!(;v+r|KgU<{$&4a7**+qj2N7)ZTs3~&g>5b9k;j8wgidkBSr)Z4}YhhPk$ z-d`VklkGByShqr?95yMmT?WyBK2LOoutp(;u*Jj*p*{=IHlD>2lGtUKe1GkM+Jm)+ zY7f^QsjaI$3J+O#VfP%pb;yKE7v#t3?)1OxVTp5ZmNQT1L;aY$* zQ(qVc*+VgTay%5QT^Ne}hChXdg2M*HPz=r*7%=v`6e1kC1w`e|0b7b-ET)K|h~FGY z5<4aS1MR6)Etpri%{qn14w=>cfa zFbu}X@Tc)$FxuDR!5D&xVXjE=_`_%b(swlaKg!WKA?Ikwi_=Hrmt*VUvU^2+WQem& z4G-29ZPo%)9t~NeyvuOIGNt3{qOG#K7y|Qcf!;sXo~=Dsd%pHU?Zw)SvFX9XimY)!;)E!Z#vE!b=fSgMu+2dX*Mbc*(1OjzfCU?4hy~l%5W}@#!wj@wvoT=7#u#G3_9d}k6R{bZAUQl( z(*)6gK2P)on>7k)f-PoZ3$~YPFV|kFy;@sed#(0*?Ty+c!#gr(>aNunf=!6mA&s?K zD7SYY3N#`9{ZWlA(*{eG8%$9U&4DDGAHVul8{==0i1#6lrCHiOgn0nU5PDMr z(>2Q*mzcn|8?(9quUrBF8U#XV>{UonCGM{KH+dyO7I;!H>bj%!8k+yGE1qHxW@n%YJR0SsJRY4JORlI_#f-O&6RgrR7 zRlp*}tcop5dcw%6Aj9;kpn@h=74O$RsC`)bu2)qgGr({V_)z;gM^)^fj+v_}lJ?E2 zpa8fko=yp_sz3z2DkuW3ipNn^umz>FDiRK>3RqT}RWVf36Gm1A8KzeS6*RG`*dyFC z+$%gce#b9lC&fdT#X}u^Ww9Xr3I;w=9)6(0?Xy%V?NF}9X2t&x`z=S@BslXL`66LE zL~pq1PeW3Oa-zHg!XB85CIRvyg0T7!J<%VBs1Q^j)}F8@<^X{v0rCujq_AjP_9i&3oy;BxMIZ^&W1W9k6^c^4-!fu|jAj*mI_jsQu zpMvxg(YX17!9u0#`yIib)YQ|u&!5<3c_h}}~N;u1Ry(Z!B}C}Q^*g1E#ELv*pD zAd1*w9dd~shUj8PK@_pO6ZOO;b{L|I9R*RuZfy>+lOT)OQ7m2T4$mugm}wKc*(JTW zI}tmw6@9u>K?RH5!AR^f?)?_blIh{Prr-OCKT^p-pH7R#j_O$1zxSPr-9h2O;UVGj z@X+wE@bGX&_;g(JSz;&Gv6R@sZPa9^*j<1omP_m;gc3UnqKMri2;veu4AI4of+%8l zAA-2V4nuUYqacddVI6Xb9fs&)M?n;^!>etV*kOn+b`(SryK8cYodj9Lj$-Lzw|`!- z!%UmlZCTQbyA!b^ThXUG6;!a;{R)X)#+Jr{Su#Cb*Yqt7@kc5-rr1#(GsKPx620$K z?2ZhN3Ri|lhsT7+hR21g!hJo(PCgQ##13```kZ2SB9aJ~*hvT_b`(SryIT>&C3YC1 ziyZ|~#O_7}afuy<=we4f6tTM+L0n>oA-dR65Jl`RLJ*hOVTdkv6hslbb90ED1X;w6 zV(DV{?|H=zGi_owRMLyP6R{&((Z!AmDp>5khs2HzyYn_yribeq48F2cC;mt!#}qrN zV}{sKK@$_Z6T%b2lfsk3Q^Hfj)56okzlm!;V`Voeclar>gJa7!bBf)0Xkt0UE`d;D zM?n;^!#95pu~Q(r*ijHg?CwE5afqD)(Z!B}C}MXTf;hxZf#_mKK@_pO9zh&pr$BVE zqacddUFk1&3CJRL6iXMo{c?((!nBFqoRVJLoroRTiY|6kP{CsN10;6r9Tbf5?IpMkCdExot>QHV%Wr<`lbA z(Zq6zorF+gM?n;^!#95}vBMBu>?nvLc56{jTw;eIy4X<=MeMK+xx@}bbg`o#ir8I- zdg2m04AI4of+%8lK@PE#AdA>hEM4rDEU7ruf&;RM_n-?c4U};?>iN{3&V@Ti^EI8OT){;%flZlirukjV!6alLMXALAd1-GO(>VxVTdkv6hslbYfw*IVuvBR*ijHg?63~G#12Dr zv7;c0*x}W-OYAU27dr}~h}{`E#7=@NVn?xbvHL|{vBON8*v%{H#odY6k*(;{oeC;g z?7o4-j=h!Z6g!z7E_U#4t|@lZ6%%4dhWYotQ?a`$ygIxlyf(Zpygs}kyfK{VDR#;2 zJ0W&(dd_E@Vs`+N2$$GN2qktDL=ii@3FQ(y4AI4of+%7q-_&7O=n^{&(Z!B}C}MXy zN|#IQFhmzS3ZjVJDg<$f9fs&)M?n;^J1U3RNsvYCD3&gEKg=t3m}wKc`6a!$I}tmw z6@9u>K?RH5=aJa4p9eU_PNs*89sEeZ6g%pQ39%!?{CnT2*xeM~9Ig#-32zN=3vUna z2(R%yjB!D7Tnv13GlY)!po`@vc)?jXn&h#nsH8u!o7C0c)xBghuYczgBYLk0vpN9me=w-@_Qw#K6&3c@oq6kygxB`6f?#R;2!$$j5vS zV@wlc9LDILN|Qg*#1wWIA5^C5pppuJG>gp76Kfz2SY~-}?KP+?28T7aWDvk$;i@PR{}rG-3aG+~2>_ z&eJkYU0;sFgyT9TTk%gtVgA+S?_V-8Hvb~Kl-s|^R{RrFn15~K?_V-8Hvb~Klp2Jm zv6HR%C#Ep}y4BymWMXXoMRv*mFyUgRQeplz$=APRS}6a5_l9+CRsHKMzP!RcR; z#61YM5|n!|@kdI^P5&ZC%D?zJ^{)rQ2g8TLhr>t0b>YkY{w4R>Z2kr30e0kHz^;r13@bU18@b}@9;d%c4CAUs({so7kcI02= zztgio1x?t$R{Q%`+IiZ)sO!t`Ut}x(sVL099`^SynHZaYkzLB|Ut}x(i7Cv#X8QY= zOpMLH$S&pfFR~T?#1!UV$N2k~OpMLH$S&pfFR~T?#1!UV5Bd6+Obg{-@OHnht*U=5 zNB+egeLDS1lDL1t15ney$mE&+MTYt3xKsc7L-=&~O!&v}+3>mW$KL*x93gGmLjINYQ-p-X{Y(ETg7_mP<)(j4Fvp$x*9+l`;h(~n!k5EW!f*Kdm)thB`Pbai zct`$4{yV+WsGte^*9rdqm3E%?FY5a8`xn`Ye<}*|uUq{6OD4wVUu2hZ`xn`Ye_{&r zug(1ZOD4wVUu2hZ`xn`Ye_{&rul@b~OD4wVUu2hZ`xn`Ye_{&rueHAZCDTIr7yJfC z*H+cPRv`b%`gO@1N#a(e|GGr{k&<%Lzb2UDPW@|r_*(dS_(u3<_~&q=zkkVXQ=5Oy zD{bGAf06%AuQV!X!v1xjzkj8jr~Qk%zWn}0w&I_P!u;!EfB%w+vH2I-rQH5Sw&I_d z!u;z4fB%w+vH2I-rQH5Sw&I_d!u)G@fB%w+vH2I-rQH5Sw&I_d!u;zZU;mP6q5KPe zR;6pJ>R$&S|H}Ho&>TtPR;B-7Nc@qKa?`&inBz|U>+SHJa6|ZR_?Pg#@CJYXlG~;> z|C(RgsU!a)|D9fGRM3R|>u3J{m3E%?FY5a8`xn`Ye<}*|ucQ6_OD4wVUu2hZ`xn`Y ze_{&ruV?)IOD4wVUu2hZ`xn`Ye_{&rubuto;I?B#B#<{u?myM@q^~|C(TqJN2&*!VklZ;U3YR(O%Iz3%7&c zRrHQ;GaA5qD@(s{K<%K~A+0eg*oF*{(+|Mr%~@JuB}Qy*vDnm}T26${4cb zhd;2^khREvst2=dn?(Vf#ZXL||Bf~a9_sR!F z3;c&puJkNJ2k$TW3>_J!_l*k5J9O`(q04xSD;z?73$$~B;-RB1i5NOEY!h^^d`R?Z z@1aW`@>_-u9^Ly49T}$gjS9*;bQ{soWxT);;=To=>I)3<&{3B}3>_J^3A$H4H2ReP z&>=sdd>o!y`3xNyruU5s$~$x~qoK=qb{8hk?w~A#QT5qfJap705kp6YZG!HV50AS1 zhYtAxHFU6H>oas@nBF%kDDTiciiR#@+d53Pt@+TY+t%^WQI|vv9T~O>x>r6Tdf9*I zkRMP(2YVGhLq~?`eWQZ%4&C)==rVR}!eqyW51qPW6AvAANyN~RVVj_P<)fl|;!}&^ zalt6tKcP>+3+KzPY4bQZ6e`{ksfA2E&_MiC4{0#B`z~Q>xJ^fw1Oa6+LS5_k)F=B$v*r;rCsb5P<&|Ooe z_IFR~@99e)H0U3E865r*T%@gc&n>M1w%MW$Y~&nO-3P?#-@5Jb18_{j6dW8`)V=-X&Rr znq)QqdHAeg&!leksOgQbvHuDF#|o5W&otPF?dz}f!#?cvDMv@gM8`(QMXRFYqZ6VN zqm!cF#d^>Jg-buGXzVu6mkUfDmnOHx4h=0;_8}xQZV|HkJ;X@Asc4EOX0UH6#_6&# z%H>|hfEI!AZNy-^C!!3^iG>;P9fT~#q)D6sEdpb4%5a>08sc0nVrQ#o^n-nWa%`Nn z2#hTdBh8gr>!=@#JaWZ8KM4$xtN$M{(p>2$pQ`=v$QAqgBrrs-J|h|7Fh7P~jE8>k zDPpj=>|C*rPl^^HSNkGHnk)U>QVm11jyeZ2)lcXA&yA`J%Jm?EXa%*90E-OWX{+JprP;w zCU6;+kah-wHA@f;=mN^$mCptGeFFHS39bKGEuf<62%*vNHu&of{aF!P@0&7@CSp$pYS^gGcq*K_m2Fy^V zFwJ1r01PpOw?+&$g>BY=8OjW%8O$1hA!cwLG1v?i40CQ_hBAR^MpqYShzYzEVz3D; z80OT%3}yb(3}!#j4>5liAO@Sif?>`q%uuE;&0zKe3^9GTL<}~41;ex-%ur@8&0zKe z3^9AZiWqE{LNMkT>uk(`{fSf|Xhx;N8PFmq#1|2R-A)UJX>phVH_}-QZgGnjL5sln z8^lYZgGnjL5sln^zipV9X7A9>nEun8Y?OgmNj<1yv?`UFSJ`5#J$V6~Fr5SU~-1ZzOoNz)-L zQHn#*G4V#xQx1pN_*tt%To_#xT^wB!T^d~$T^?N#T^U^!T^(H$T^p@UsxumK-8{&B zvQ`LjxH_W|aEJp*hu|$j)$ETLE{DJjrDSLZcZg_2RLnkz!3svqWV2o{Ln#-U!5tzR z5!JE;FR5ibK#0?hw(4aEKovhRY!^LvaY2!5tzR5f1TP#BezTW+)CpGq^)UBf=qe zL=2ZhV20ulG=n=tG$I^gJW*7bF;0iT6xAVU40j08D9rV5b9k+ zj8wgidkBSr)Z4}YhhPk$-hYo6sd^jt5DEjSw~YY~!5Bil=ORX`-o`zI!a(Y6V}L_2 zhEVTWh>@zdaSx#|kb2t~;1G-<)ceb0Z?atm5$jfnl*1;4w#y(I(C3M+5Y{N95Vn|D zA=GCf+Qze3LK3?Slkbl1iGCa18{HS(A3YE~2rtdyQbTF36n~9+&DuUFgCJ zLKor|K^JyH43{oo2GRu^19X8ggf4807%pAF45SM-2IvA~2whl&7%pAF45SM-2IvA~ z2wnIlVz_hxGmtLW7@!M`A#@=^43{oo2GRu^19X8ggf4soFafyO2h=VI#5adO$(~d5KZaX# z*jL4)>e&MW=K28xS-AGJT2OT;q`KS%6#k#%1Ml%pzO@lF61EsI67Q-Ctv;se!?$We-Mr02(w5gR#}{r}1Dg+SlU27=npmu1N9t!)O4~cQpDx%F#F> z=V-`_(?{bwW9#9vdqsU@h_g%$57riK)&f%=4OyeS%W%UorQ_2FB<4j5Jja!7e3lYP$V8aZwV6!n` z!NwS3!S)Y`;aad^23oM$7_eYt46$IFhZwE}8)l#dn~ebrHpUPOwn4;jE!Z#vE!b=f zSgKEZ7)BEZ9Da7_J2yW}pR| zjR6Zb#t;j(Pl^Sbh|SOh$>G78CWr>~d7>}atWii4Y%vpCuss(&AH5L082u@FDSA12 zCAw&MN9Ii3wfaJ^3Gq6lu~rM^_6|gWCd9u#sS0P1}xV!G(Mzbnrmnye8s^Xw@ z%-C+UttyiC&8naPxGJ7a39hO@1idOK0{??)d*|2=-kFJvdhLzl%v9ergHrC-6oC(6SQRJeVXDy5yv z)!3}~|6#x7h?@jw#)rML;t&x1X-EoDPLy{**aLGo+8vq%$fNRYMfeM=4*}61ho}%# zAl9C+C+4C_fINU8>8+FgJVb@CTc>z2V1=+p=HifgfZUBB>AjP_9i&3oy;BxMIZ^&* z1W9k6^c^4-!fu|jAj*mI*Lj~PpMvxg5a*3UUP+~_x6tTM(L0n>o zA-dR65Jl|nKoFPMVTdkv6hsj_tV1rb!w_BUD2O6?Ft{ zb`(n&yS?*@9cJ3ZZgxp8?oPyxY(<~$R8YZU_j4q68TWqCESVmzYx=#P_#>4Z^y#!% z?5K{F{d?c3*e$F7roMmufck;;gX#y@52-&D*L;@P$#pCxc5oXt*(r7>qKV}aI|-r0 zj)Ev+cPoOp#12Drv7;c0*xiUAF0sQ9UF;}`B6e7ZTw;eIy4X<=MeOiu+a-1wqKh2` zQN-@t9AYOy7O|sPy4d}DUa`YWo7inx(u=zju_Ig2r#lr?u-JVMiCxB)Ml?&NhwGZY zr6K-ECC3yys$+)OQ9+{jor>L|^~36i*H_e!s2^EBs=l(mx2M?2M*@`C!R|nxQ|y)_ ziExRXgivBfK@_pO96?-ShatMyQ4mG!E<_NQ*kOn+b`(SryK@l4C3YC1iyZ|~#O`DS zafuy<=we4f6tO!lhuBGwMeHb+E_VNzSL`s;CU!$5y|_COJF*pB?5LoE#jc6Ojt#r> zHddyG>lzHcvQsDiNF~PVz&xSEQi=75K8PQh$43Q=FcH^3Pcw>3ZjUeyz6II=ny*vqKh2`QN->F zlrD$ZDG*)kD2O6|J$1r;oI-$Y`^-a&DRU6LNIYw#wDDR$Hq6MJ@Kn1Am(UD=&dKec{Z{q*`7^)u^d z)z7Z4^Ax+}_MLb@0cTu&%qey&(8O|yorF+gM?n;^!#95}vBMBu>?nvLc9)`_xWo=a zbg`o#ir8Tta)}*==we4f6tO!U^~5E17@~_E1yRKA#2jKLK^C#2Si0E#YhJO#Oq61A+cjG!#TxHriY6iyb@=M9d*To*pXrWz3)`)&aIzUKfk`Z zenI`h`bG7N>%a08yX5wr5IZ;!=@U+|I{-~Am)J=NC3X}<5j(sIWNG2FhmzS3ZjS|)*+YJVTdkv6hsj_yxMk&9fs&)M?n;^J1U3RNsvYCD3&gEKg=t3 zm}wKcc_qELI}tmw6@9u>K?RH5=aJa4w{o3gC)2~l4&Kc*#g4jSLhQ&e|K4{hc9+&K zt6yHfqJCxls`}OSYwDh_o(v|p?}XUF={cWqik(zcE@F^j%c~~|gc3UnqKF;dgmQ_U z>@Y+ZI|`zR-H{055<3jh#g2j~Vs{XNxWo=abg`o#irDR!L+m8T zB6bu@7rVuI#SSxVVmH5}7k4LON4BC*cPgl0v73s-j{Q8qDRweFTNnQc)NiWaTwhzi%J(qFC^;?$zPTAf$9vGl@)Nw^EF4YpSXETg zpV&?6>hJ1avYFSv^9d4l@V@${de)EZ;B%<`{gvtPIn)_TAM!nn5qDlYjB#ieN9VgH z#V;Rbzl~*Y#Xl8=9me>+?_rE-V&JDRtSb2To8uSE>|IK~k^Iplrm({p8@`7zrip>0 zt@0$M_am*Ct@2Ht^sGqzH<35^9>$m^#yE`8J(VVZq=_l)Fvj=%4r5Hyq8!GUq@<#2 zt9lsY$>=afw$gKXSR&+Nerg_OpR~$zCwrK`Ty=UFbKYLsNY$?tNuBE|B{rd97s{f(Bi?@FzM@ZZJ3r>da$iK*cr)Pl*ny`PZ^!6{*dD_3I>&x$7WGnuu zD9pdE_x7(OF*g4qyOi6%$X5IlQ<#5E@%FDIF*g4qyOi6%$X5IlQ<#74?d@MlVr>3J zb}6@ik*)YArZE4y&eOk=v{3#9KiJT zzsOenQ&E_I9qsR5GBGy)BD<8^zsOen6H}OfJ>&0RGBGy)BD<8^zsOen6H}Of?dTlPt@b@pdZEEwc`K6sY@-On=>6JzWP1wJ-_xG=~^R$0a z*O%YF$X5JQQJ8-%_4hBC7@L2QUCQlWWGnuODa^la_xCTE7@L2QUCQlWWGnuODa^k@ zfB%w+vH2I-rQH5Sw&I_d!u)HAuYbw3Q2qtKl+(3U^{;%txEq5nD`?l z<)(j4Fvp$x*M|DL^}p2LtG{3Wp#HOk+rjTDddIgJ4dA)o(l7ivS{Cge9T*)PEsqY1 zRzyceE2ER63!>|yyP}7p-$&0zuSRb~Z%2QLK8*IOFRve6Ke>KR{gV2%^;_z9*B`9^ zuKslW#rkXYcj_P3pB=s*+WvTVxNsaEDe`mtcAGgkXJA14jQiYK>1W&*j?3qX{6xGt zyTCuLkCsZ`Rlnm7zbsqQ&#Eyi$|FYDV5ww1B&)w?3jAtpYJX)K{A#Rk>F#5Xu#|}l za~<`g_NzYnpS@@0JsOpG$UtHV!`|X4y82GKMVq;Sa1eWG(Wa>cK4AW>ElVF;#72mKnyn zmKBtD)V3OX9C}uXug&#R!rWQ7Z_tzf0^KX`)A$$vp_5f<89I2A-Dl{?Fn#E#pu9u( z6*P42_xWMyP~QUWbfdU3sY{CI94D(2gLAhmN`=V(7@QP0+pavc^{aLnl{ymZ5|9mwbkf4Ac8Y1?3&O zjcDlHZ*jrUp}qy$IYIHzQI|vv9T~O>x>w%6@i*Q>mptUR3>`eW_Zd1eOz#^Nly~SR zp`mlXz%X|f?prXbzQ7O<9d${>(2-%ApnK&58#Dcf4*3D)C=d-l1EM zhR*%$4u%f(Ef`gw-Ni#kT@o>LWY{L?Uisk06#t<^en1T!Y}on?9T}$gjS9*;bdRH< zb8lP2(4oEsqw2PGJap705kp6YZG!HVmp9(3Rh0oBDVS3-Fpu9u31`VBi z#|DND^(`1xcWmOJqb`XUIx=h%bgz6^TC-jJM#GD(nk2H(RhD@K{BN_z4MKJ-0h@c$@iIT?RvI#S0^oRz5 z@W9wxFfzSD0Nk5hiFoi}Df?N)CN{FOqP$D81U1QO{`2rz!JbLo>QU1hUt|9h{ErnV z$)0Jj58KyY>4$yT=~GrTj%Xa&II6L-adhLD#<7j#8t=w>&;o@^zaVSuHqV!fFdmmC zx5W+(Emig*Br|Riviq-yk$zLr6iv)v-&Bm#Wn+}fy^H}Z0^=u$!FEqX8JZIdGvGT2 zS&T`OI0IS)#{Wzi?4VNm1C&sQh_Q&Bt)9^j_WjAR@%ZS|If#+w%B*$F@W>VW{3I|$ zuD*sCX|A-BPqlt{)wg#zQ;!6f;;{cCOgRCq;`e9)}@Dnk((x zQ;p$~EB5V4V2E5DC_iuse_^@$BJ;ADgN_Np0<$|Zbt;F5WbKR~Z2u^RII0&Q>|31~ zmDShBA--0YGn5HTGrGDsLrmad#9$LxFwCii8Or>n8O(m5A7cJC5QEKM z!7yhQW+>B_W-$8!hM2xp#9-4`FiiWw3}yDx3}!#T5VQB|h{1L#1Y@4D&c+PbpGXyg zW>hMi0WE?;3?T-)ofZt!;xGelq_Y^@;ubH07J)H<7z+}HX>pjbAe+H0Zt)^$5g1zx ze;?Fg^9sw}AY0dLVe>dl8T6RyQ>P}40%r;4u*n{CGG@ESbe}d&aKwE7CFZaRA9GAQ zRr=#G<@@>sN6h)3NrzyylHm}TWI6*$ zh~aVw%uq^(W^jjyMnuINiWsb5#7s8p1v8X#p&8sEq7hLo2Ox&aAuvO62%6Ew93mPK z4zVv{xEumA6o;T0+##Y7;Sfs^!{rc|p*RH1;0_Uu2#5GTh~aVw%upPHW^jjyMubD` zh8Qk~zzoG9Xa;wPXhb-~zaWOoAuvO62%5niA{r46@nghrIRs`X4nZ@xLqsFOA-|UV^yIr&`{bK;1G-}NWEfJ_+RK1OR2!(;v+r|KgU<{$&A!4NJZQMgB45Z#R1~>#`2=)F4#7NcKxQ9>}NWEOF7lO}5J*V%-Xna@eHMb{Rwi`aIDU!WxAX!WI)Ng!(K*+jtgBNMe^^@@h3w5CjD+pbPTLfL$6){}8fEh>^Yz)u^ z#t^#jeZ+9-0%jmxurWXv7(?j7&WPdC1gN$UBC>a3pNJm0%HhWs3V3;7cc|qf{g*Xz!*Xowi3D^ zVl#9h;SjnY8qnv7t_#*Eqzkr~iRr?9jr$u9G#+d`)Ofh@NMl`N-SAJ?Uc?k}eA9Rn z>|8t}HJ1$XmRg3U>d+ACu+mfq)Gi3bcEg`!&#Czz!>u{&tKw1h?12Gu{eXciTzgtA zs5%rVT3O7>ru>V5A42 zLBlW@!^5A(gTZKDiw9!}CWg5p#p4g70Z8A`=>I53gcz;`8)l#dn~ebrHpUPOwr?VaYr%#YXu)P< zz=Dl2#DXnC4A+7UGth#~#()JIV~7RYHxR?MV8aZwV6!n`!NwS3!8RW;TnjeLKnpe- z0~TzIAr@@25yQ1$!wj@wvoT=7#u#G3_7%i%E!Z#vE!b=fSgruCTorGm z1Xoocf?gFA0awM#s4AG***_mWcUG8iSXF@Kq0dLp*@YL@?2?`^vMR_hy(*}niB-j` zjrEP!8voa)Dk8g9z>yO7I;vu2I%bZlNZU87f&$>Gcr7J3ssa=As-OtCD*lA3f-O&6 zRgrR7Rlp*}tcop5dcw%6Aj9;kpn@h=6>l`&Z2Y=`8Jed+)Re=b4RZs+66_28-U<*oTRU{l%6|k%{t7536CycBLGEA=uDrjO= z@pj{##)ih1<9GZ*c2YcaSv=IyR~CcmS1|C2^6&!{Zl9$}>3ijBY*zgLu-|gTO@cFD zFJB~tL)=+$2#EePB!ws^$~z$Jfw^cBAkQHPs}BLuABU(AR3O%#uqWp1@Oi$*cnU$% zTPOW_hzeo1PVr*E3Sp1T0V3|59z&4y-bvpMQX%Z#DGQ>UD1RS&uIcxF;*V5v(5KU4v7JUpMz_E^Gd#xqtJ$xaPCOPOf7qv4h*F$xg954^1qW*hvT_b`(Sry9W`(C3YC1 ziyZ|~#O@vhafuy<=we4f6tTlP3Pj@P)V6poF61$8ojlo$mJzUrHEe-KUDmkXuQ5`eH zjtUaJ?^Ns#Y#!7+xOqr(dGpZbVa>yv$9syMd?Y}L9qbPDImK=jk_eaBNeCr&6hslb zn-Rn%b{L|I9R*Ru?m7fD^>qKMsD zImAwaEMiBobg|n#uh?OxP3(qBdU1Cmc4RBM*ik_Ri`_So*s)=E-p0!Ga9xAJS9a>e zAF1S+Vn=n%5IZVpVq$kh^T_5=&6Ulgo5wVdZ64SBdR+4vE4x9t!%vAF99y=TQ|!)0 z6U!lX34{_m3ZjS|zWH;AodVItj)Ev+cPHwJL+liYE_M_|5xcbr;t)FpqKh2`QN->V z1aXL+0@1~ef+%8lnZMX2AdA>hEM4sO$tiXU(- zDR#;2J0W&(AkrtCVz&}aESK0x2qktDL=ii@3FQ(y4AI4of+%8lCF+Sw>@Y+ZI|`zR z9o8Y2*kOn+b`(SrJG|O?oElc0bE2c9>}syLlzOxH}O$ zvK4*0Q$Yob-4~JAvA1%aVkgtX#SY%hHN}p)VnXc5F#q0nDs~q%FKk}aytsKu^U~&J z&C8n$JjE`#eJ8{YPS5#_Q|y)@iExRXgivBfK@_pWn@}#X!w_BUD2O6D^>qKMs!9AYOy7O|sPy4d~Cykdu$HnE#u z(u=zju_Ig2r#lr?u-Nq@v130EaEhHw4;MT5k$@?7)D;tAM~3gF}g zYn#_KuW#Pae8}@K#<_#ZaWU}C%@8`?gD#ez;00&lXp+aOqLTi^Zc3%eq;xqL+$UcOoz{*&RDw6^DsuG^V(sIb9QlbzH3ta@?rMdSoT)@Q&HGq zj2k@F8pTe-J;NNeKUof+GDg8$BN0XSs4r6S49>$0g14mosNlfoYS}|MYn>^`R zk@{~UZ}L2h5hcbrjL|)nCV!-fDeN%D54{d!L}^hDV@y&~(X~}QjBzzOjFGMMTppGP zxtO1thuJ5s^4!TD<}X*B9>%z)c~kS|=Gx{h&0CxE{ryXB%Gmr1j>785zsP^5XMqZu zuz#)f_ph|`v`kaim*X(uxK7Dd{8Lewf4%JQUotT^|027T+rP+G{1a1{f6evxFPRvd zf012E4Z_pd$yWRmQ<#5U;O}2DF*g4qyX1eEa4}P>0gq>JqWfElzTAoM@q^~{~|}qzxX=!uiKkV3*qTFEV+if01GSIquZI?rq-JyubNC^TFmr&8z(VOKzRo z{0k06?a05#f2U`G3YxHgt@QV=wDYuoQP-E>zsOenQ&E_IUGMK-GBGy)BD<8^zsOen z6H}OfP4V|HnHZaYkzLB|Ut}x(i7Cv#_V)KLnHZaYkzLB|Ut}x(i7Cv#uJiRTnHI{w z;O%~0TUGx$2>BO#^y&03N#gzm4?s=-B9mwO7a8WC<4*nSk>zsOenQ&E_It?~A+Br!JsBD<8^ zzsOen6H}Of^?CbOk{FwRkzLB|Ut}x(i7Cv#e(mjFNn&jNMRqB-f03>DC#Ep}y3y0W zlC)6%1wYu(wN>@6V~~Gk{S+Y~asSePiXi?-NxA7?6U=d^{`LFjlg+1^e`r44e5Sdz zzkkVXQ=5OyEsb~NU*x~jD~$@8uzxM{_ph|`w0}|8m*2n0R{T>@n18MI_b-_kn}3mA z%I#ldEB=Wo%)j3C_b-_kn}3mA%I#ldEB=Wo%)fT?_b-_kn}3mA%I#ldEB=Wo%)id} z^)Hzg%D><@IJ&l~{>wudH8}%#kE+Rr;?>#2+asH~njZIquZIo^3wYe7^ZY^Tp<$ zntlHMCAUp&{xz?(eMkO9{yV+WsGte^*Dw72EA2e(U)1&G_b;*)|5Oy_U&s0TmrRV! zzsN4-_Ajy(|HKsLU(fmbmrRV!zsN4-_Ajy(|HKsLU*GljFPRvdf013v?O$Xo{)s8f zzmE0wFPRp~zu;$8y0)tRwG8=J)(?i}ND{Xy{RczhkCc>~{x!iIcj{j+H(zPK+Faj! zt@(QMZh!xh+om@EnqS(fBmW}*onC2F(1iW#+y4HQcAoYx>iY8g7ukw`Dhl(jz5M-4 zCdTGpWS4UL7ukw`VhZ!GyZrr2CdTGpWS4UL7ukw`VhZ!GhQEKw#Mu0c>{4$3B3toK zOkw`Dr>}p>v{3#9zm(IpRrRl5BLB+z4cHt>;#Q^q22A{sl5*3(CYa++{p-!UMgw-}&lmP=?A_S6v0vjijRP77H4bSU+Bm$is&P)^%EqmY zdmE27o@%_iNHBWD@ZeG#6v3Xnbx6Ox}Pc;A7e5v_H^WEmQ z!}mkmAMXwqj>98GevaR6GY97k4CtS6A4)&tzHnSVPvj@!&D{n5aecH@`hof#clc%5 zl73c=Sy3J_!Ujtv>mgbFJyYOUV^jMp)8JQQeM^5Z_6SRvxG?8YKT5yqqyO1^R(`Mf z%Xr8@bhCym*@ZAV2LCu1Ep=xMnKcRxnJp&okZmi5Of;7*v9IxL)VLjF5^|!p&`__Ks$mc z9y;ohh@m6HHbM8wd$+#kKXh`XXBj$pf5~U)$S}QcR8Zcbdl?N~##>xNL#S_oc1}<{ zbkrpgLq~>fg6@^~ZT)}VLzg_{w+tOTy7w76GEDCq6_j`A)}x`zc!6OE_bnJzUtoxb zj=Cgb=*X~5(7p10tC=d-l2OO4PC~wyP@RS9h7A-sy@4m zhmN`=V(7@QP0+paZ(8sA4;}IYYUp6Y)@SI*FuiY7P~M@t9SvQ^w)If5ZOw;H-L{U0 zj=Cgb=*X~5(7o~jt*8Bm4*3B!bg)<9GjwE_-Zv^J@6fGALzl5*GnDMu@S#(8Y~rD# zE{PaAGHercuY6GJ=J?cNcw8{b_D|>&@P_8guW9o*I20=05vhe^1MuP& z;cU7mhj)NGtj)WlHoM&yr}yfo>!t*V%5J}07Og?+Zw>FnTJPCrB&tL6^wGL$^DHd8 zeK;3UvzL|rw zcb+-A-OMejGiUu0_P++_rfG>ovj?EBFKw1rX^L7LA(VZj845zPQT_cK#hV3GDL%^+ zdc-(l&JEf}n#E;9rcdt?4Fch;m;gjX(2s*mlg8q*2{UH&hz5ah$JkpiGQC0o+?!pA zc<^8;`&q>%HnOv#yi2kKHOXrJ^YB^0o=M&6QPUe=WB(KUj}<7%o@uZT+t**|hke-T zQx0h@Zynk?taW&6MeB&xk*%XzUL#W-CyM!DR}7|}E)NEwc^ zPls@>7O}I{Gy1{4KRGteS_H;d5F^c%S?j1Di#&40K0gTzk*hBtMw%=ASu>NY*%lu>GSL;;3GLuy1u{R90Ufhd`5%t*sG+?R3Nt z(-4x<0?1G{q`#j-phI zM<6Vr|LE2+tz%oqwN|x`Z=KLOv2{}G<1WP_6{Nj+oceUdB!>$GhlxrRS23sN6h(M zr9-e<$#4ivG97|7pzEaR5SA##A?TQRqv$DzLu~x4)gjJko!L68b$08V*14_oTIaV` zw=QU1*t)27ajPq-&S=DS^C0)hS|P;Y>WoIfAr2%Rg0~1&b1-7K90D_xlA#&gA)*mc zG0PBx6^xk4X1!pBQZ6)uJ47@hs%0<4a5)5KC=Nk0x|l;mBf=s612J3PL^#BE5X0pVn4vfX&EO6ZjR=R>K2cPdF;0iT6xAVU40j08 zD9rWqF~{i;3ddu*bB6$qnD1v|4x8{+hfp{kQ=U5naKxNHSvmyke1=0{lIakv0bM6e zhpW;mTi3L%ZC%&8zI8+E#@6z91F5%-0S>_! zLcNC(BUNwX9ztOt^|mpTTRZC=8_DHU>BZV+i#g7<-fLGKg5W zLZlovDYRV%(SSZrbcL`+A%(ET#0sH43(+>7#S)U(Wte*m(l)-A1DTer1tZ{5-Q zn>e?1$b?H5bb&F1F6@XHE?vM3qzg6% z=mKL1T^L6Umo8ui(ghm>bb&F1E-XY0mo8ui(ghm>bb&F1F0>HCr3;vWbiu{|U0@8M z3pK=W=>ldTU9d4g7Z^k6!rvo?OBXN$>4J>`y1*Dh7v>6G5V0A$kZ=fH5Dn<_MArpt z6w(D-%*1rzuGZbHds@G3-P^jab${!D))T`&VS5o%#PLnzO|WzEjMQ8*$XjX|nyN!X zsKZKA9Ze&MW=K28xS-AGJT2OT;q`KS%6#k#%1Ml%p zzO@lF61EsI67Q-Ctv;O|edo1L|>0|M=;a#B_IW58(j0JzGf_Qa6Nev7}EqgH11JIyh7>scE(|9l#?Q8L1 z48g=OSEP9SVKe~gI~x5T7%i5Y&~3duc(g2FB z<4j5Jja!7eYa)hg!G;-V!DeH?f{ii6f-OJ{*Mbc*(1OjzfCU?4hy~lKEZ7)BEZDw=7_J2yW}pR|jR6Zb#t;j(FCm6&!G;-V z!DeH?f{ii6g6(sN;aad^23oM$7_eYt46$JQZ(_kFVly;Ba(J+&38Ddgp6ClUYZTH1 zTg=23Y>&5|X#KwRWb3KcA6ieho@w1byd!g_?pl2z*o1f;(pam7a(f4&KojEMAJy10 zZLn0i!4w7297w{+@vC38G5!{bcpuVOnx*YSm6+z@OH5$fjaglQ zS1y474FciMW3NJrDsgw+zsXBEJUOyBRGgl$q&hOgSb1axiTc=}E+aM15SBsQ=yyHa zdam_+>r}6*kltuk#q3h$Hb+$)nvNOUjkZ-q(!N<06aZJniz&fX6^Ni$1x3JB@eHa8 zW_FIxM-PPwhgAhw9{POr++BEK%`WK)BddZ8)2o6Cnpjo5*!olJrPgjfRT0^>0*;ip z*HIORq+{l&inM*RDkuQ1isw^;qbe{#uL_EQtKtu+D%kSGRTU|RRRt_k%&OS3q$iB5 z3NlQu3Myz~Rq;ye)zGcsM1vssa)8 zs-OtCD(*#9!4{Oxsz^AjDqvY@R>e?BPZ(JhWSCwRRM5n#;`P=Wtv6dU<9GZ*c2Yca zSv=IyR~B>9uVCO4<>3b^+&)W{(htkk*sS>fVZY^wn*?XROuk6i4$&KK`qPjUqMRu2 zfUpPVqDg=}fgr3tL{Id`Au0qFh_xr|i8(-^Nq{_pAnC1>{yap5uv@2iF<^zTN9F(# z_fGdANP6$2ZwILmcJGu0QBIV<4MEbICw&JqCA@=4v9@Y+ZI|`zR9o8Y2*kOn+ zb`(SryX#R;Tw;eIy4X<=MeMH3A$AgE5j%>di`{;C#SSxVVmG^_7k4LON4BC*cPgl0 zvHJlMyNr9kIkRMXxUT8hEM4rD^Kb9n~>I?5H5o`%cAfzxJ~BZ`%8} z4`?6QKB#?g`xH;HlaB-_v4h=#KBw5NKoa2+I|-r0j)Ev+cQt~z#12Drv7;c0*j4ZQ|zdY8Dd8TO-$^T zw-0R});_$wqJ2dB$o5ff`McbVmEEA+;itq7jxF2FDRw8JiRBQx1VV`&1yRHf-~2hm zPJ!rRM?n;^TZ4My5IY5;iyZ|~#O@jdafqD)(Z!B}C}MXpf;hxZf#_mKK@_n&&tL2k zkVWh$mM(U`$|-gV(7@uDz;#eEWp&1Z>Sa{Ep^pnx;3KIRm=m1ttQ#7;se zv7;c0*x{Q$m)K#5E_M_|5xXlb4z-0cOrIVEBbV&f(jP9FCwvHFT**-PNs*8 z9lR1}iXC;ugxHZ`{=M&1>`rc<(mu6)TKn|&8SOLMXSI*@6uad1oe(=X5a|<6u{#7! zESK0x2qktDL=ii@3FQ(y4AI4of+%8l0qTiM>@Y+ZI|`zR9o8Y2*kOn+b`(SrJG|O< zi5-UMVn;y~u{$=0*h!E@>?oElcDv>kJIu6+-Mo@s+?|LW*@`~hsi1D^>qKMrAImAwaEMiBobg|nZuh?OxP3-2E^y2PB?8sL1=}rX|EOviE zV#j_S;1oNV9xit9BLP$Fs4FJKjtukfeWzk~N&C|FW$nw`SG2EeU)8?4{h04zjB}FX zV&I#bA#}V4T`WJr3(msPB#%`^CH;xrq^|z1?j@Uf{X3r^Q3vmneg$PPY-+TUN9 z4xdAvv2?BPVT`!*+F^`ycX4#SYf}93VfNct_E!8;QP^ROFZ&+Gm?j2(3d5>`f4@0? z!OY&J^c%?^O=1c=jB&2-VT@^F;ApEniRt}FD`u;FlP5hZQvXfl1-^$drin2QV{}iY z$scKA3OkJPCBMTM)3hjuF(xUg=-R3t#&|k9jFGMMTppGPxtO1thuJ5s^4!TD<}X*B z9>#cW`?~h^?Hk%Rw%4@h`TLjLl(G329EH`9f06%A&jJ-RVgI_w-@nq%(=tt6Uyj3s z<2of<@lQoz{`IK8f62ty{EO^TZvP@%@lQ-){`EP3|B{KZ`4`!x)F3>KoovNFF@^cp zDu4fyiLv%)4wE%dk}0TDEDCE zkCc>~{zZ#euBnJoD{0q(l z?8v{!f2U`G3YxHgo#5|Za+47b7$8^E)b-`}FR~T?R21f4xA^;)OpMLH$S&pfFR~T? z#1!UVoB8{fOpMLH$S&pfFR~T?#1!UV`}_NsOpMLH$S&pfFR~T?#1!UVYkmDoriJn^ zcokgNR@J{&Apc_f(@y`AByLr(OKtiWnLN|K$T0sLcj{kvw(n}+-M**&+xETfEB*aT zZk^iv3l2r?$iK*cr)Pl*ny`QE>+fG_=V||qD*WbTnVr>3Jb}6@i zk*)YArZE3{+uy%rVr>3Jb}6@ik*)YArZE5dslR{8#Mu0c>{4$3B3toKOkw_Yj<0{o zv{3#9Z};oks`}SH$iLX5Pp5xL68A570BZUdnLN|K$T0sLcj{mFw;yOf*nX(}aQl(= zZr=Wt93gGqj?d@MlVr>3J zb}6@ik*)YArZE3{*W166#Mu0c>{4$3B3toKOkw`Do40@cKib{{Os?We8}6Czo}N)a z!XO!AK-%B-E>5y0NC>a@Gtwx`bl=WH@Oo`aiX`<}XWF)*(6i)>Qn^^5cp9+sQ=(di|oFFZ=pMdI=9j*VeCN z!q+bq7}xqmHYxM^MS2MjOxM=0r^44S6&Tn0MK&q(`bByP4@}qAukFIuFBKTq`b9P= z^ZG@42@g!y)~};O*DnzD8Cl0^!MFID#2CE_2cRGwVFK4gqL zUBA|hKRW){_~YYGj6XR(J$(IAvZ-tR+AOzCN9z~)JA0&2Mjv|p`eyk06*rzw5n$*@W-wQ*F6cS&m>=%Z_ zKT@eYxqf}f7>z9&EUF+A9+`o0Sev!YkM;c}Hq1Ugm z@bxQhJiUHV&zF7uBE5u%qHF8dkHXh46&Tn0MK&q(`bByP4@}qAuS>(%FBKTq`b9P= z^ZG@42@g!y*0164^-BfDwSJLJ%DjG&Ucv*@we{X8ACI<#f1XolZ5e-Z#{49V?iZ}! zrsNdIJw3t`c)p;0D|pTWzWgNgPv#E~+D9>U=c6rI{VXDY{ovD!Jv+{Td6R09{@(}k zJp=JuZiQm8w=hsz_0#RQ`o{Nj(+5gD1Ne&FK>xs}iha}O7JH}nzBT^#_zuxFEL6p) zzLZ^}FFur#>;okzFf$BR6?&nN>;>ryqP0o%J~*FS7_Cjj@q!P;nO{X_;Zpv=65_>P z5tGpX3>yOC)f2xqSM1IA6iWcZ{yteO6ldo9_#1?&4$=WwI3J%@{@dbTC((Z96@=_7Ql}B7=prRd{Foz45ioV zV;np&$Hzo00naJaTg%*Ov!R%<=XzCKKDlF=5}`c6i>#`_!dUf%#&- zTPh|K^_3VC_6-Z#c?-;Z58mHjWMo8XG zFjRYbHx*yxOioUHgtsBzqz1izYJ7Ehr}EC_UCO(bcPsB+-ZpvyAm$b(mTO6EiM<9g z43*Qs5|TQ58@#CI68yGcO(mAri&OAfQTF#qNb568g&k-5f8?`Z$vpRgk<7Jkm6du* zh*^SUUYrKGdphLq8Suqf{^7b}wJ{zqjn-#Iv{o`REtb&2qTR&ez<~4yU3Em%%f6vn zXz@7mkG1|}{t)|os`XJ84Fhb|^5}_Vezpi?ZUJ8)v5jnjEcNk?rl&JP;tEmyKy(*h zBvax#Fs%n4>GQ?uGa$+{AzNb@rs`N1VyzsHJ z)@Y--PEO@TWc772zh`-`^4{gu(OPKO+?mVAx7v1PYw763c%AJ=2gR&hOidUid+9$> zGiSP7g_gBixqfQuOv(=DQwMHQScf&v^DD0j3&3h~qhRiY5LNDkiqoNIXF$)+ocxby zfDP~&tTp4ci506>u!JGoKe%YY0_(d#FwXS=$e*b3?rDj}Ud4dNXowwQ*P=0%Gg65j zjhTi1nF9mylYG87Esn;W?Z3ez6!y3}S=A=7Fm0yh5 zsy3$&emKqm#D{52MrQ$x`w`%)ztSN#Jm% zd$96)FBS{j894v4eE5k`?p-{5a^+KFhM9TY_w^NpJMjNqIc8v2r;Qo5M>Lle1YmYv z1o)z_bO;a)*|Uu{j+x~4K>2U9z0L;)^2`-@ekJ+}8}Nn3Xxy=bCM(y+Bba%ePn#yZ zf%kb)n|bf8;$siG$9mQ4dBzOp3H;t5zoJ~4kASgI zMrIUPSFarMY{Rs*xj9!+2Q#mK*gi9FtOe^T??AoKJB%5ZcTVHd^VquU7DgqJ`&{&I zJWY-=CfBR77z`Pgd%@+>{jaxPk^5thKTCba8uHpoKoA`;1Ovx~zzn?sT7Uh%QSOmp z%#OBVjmTHopcgq|$enYl{!zcd2HY38K1;cdV%Nz%g6i68JY z>mQhTz0aFh;NHOdHEkx-71%oL*_x=>gQ>kWVZXK)aa1<-Axs$QTNBa`--mDi#5(Yp zT;ogVn^T8<{8j!RwXMmV{mTcG4=f*4KDc~H`OxxV<-^NIl#eVQRX)0WO!?UIapmL7 zCzMYt|E7FWIggy2^&a_+^5qLrd#YMVWeC)#8D0*3RDXE-ASm?noa z5d=jlyAjL}ZZv{v?zDTB@cuM*+WAw;r8ma zszNb}pYcX+5C24k!X$+bqoB4v^1jhlbEwYmUBe@;lfwKNG42e?8-91}?cl-m!uSzLD^OsU$$66`H z;W#d(92`(ei9PG36o+fAl=A;n*&wZy5<53aDGu*?DdjuLKCDKSQ(ltMR|oizw9rMO&##1(dfAGVb8 z*|1Vd90R+Q;(C6ul~B`?9&jOT%w;a6Tw1=Y{D<=WSxYG+MkPU2U)0t@Y~P2r<)svA z>R?er-&=To#oC{0!X{6rrIf9+mQu_BkfjuN`}25_uCJ8h^br(|PD?3Q1eQ|bAS6mD z&Ii|b%}%4B)~(K5O1ZpzMR}p5U$7L$^vl+fM(9$?5S)u+r4(yO8>N)Npi+tfpvmGc z1f!Hv^_NmK|1o=XIgd*z^Zlii*t1qjae0nQDIZm=I<1rv`!-4`F7J9NWs87PO6*=Q zrMSFnrIf|;;ZsW~v3H}C;&QK-QobHkO3?s}Qi=<~D5b3Omr`Q?S}DclJT9d?Ev3`c zQi|qVE2X%cYo(OA{!&WpJ1(WTJYy;4@~~1$?At7*xcnQXlz&pijiCE zO26`+R!Y&lYl67TyH-m1L{KS3bFY_DT>kY^N?%whMME%3DJ}@3lu}alj+9bL44{=# zT;AhS%1O#~N-0Hi9hXvEuH#b5SwW?g*ttlUhoN{p+O^mwT<0@~rfp zT1tt%>!lQzcde9iX<#WO21t}r1d6?g1En*!CcI8!t@L1|Z%s%O&fzkbQm!grUB0G# zZTY(L_2nDNHPVO$H!0BMA3hAX3 z)^MinTaAM43zkx%@KQ>Qku0SMBpZma=DaFdcuOfxA7&3g6~SuHbk+miDW!ZgsFV^% z!YHM5sMlpicF3oNCK z#PtQclrpp}tBTkizz$ub`mf6!O6{S4#5y+3g0;2NQc6!)DMf3lRZ4NSRCHt7V~bu) zvmhE4P)d2YyhyT~hvI`O5NN%lDNZDnC*_*;h&#(q4qqN-4vllrp<_3#_BS z|D%;s8opAB?pQ0OI2^~Nl>hXWQgqLHDaGMhE2Y#_*}z>&(VZKm6o+@cl=3gWQi|?e zE2TJG$EB1d-cpL;Su3SDTx+G2e^4=Tmr``+Mk&SNT`#445w~s5Qi|?gFQquVYo(O+ zLP{yRd##j0d+&d={8;(%@)PAJ%TJY`E6|? z6emd9g5{Bp-b%U7UrNziX_QjXDX$*T!h563#F7j zLP{xm4D3>h>-qIH$Ym4K#_Xk(=gQBQUnrlHt(3x=s19ei-%1%4r4(yi@u`ziN^$;* zwO^D{942h?bXrO|KU*oq4ggt7aXcm)@WG`Nr;ng$bXrQ;FsPKG2O&{PaXz@dYjzq1 zwJv)p<)!k=<IW(k{qWd;WDK7s;DP>9(JKUud9YHUpxcqCSlr_q`yOd&h*Gefa z?^-G4y?|1R;a)GLxcuv-l!rq~DF%X3N^wCLrIbfhy~9~b(E+qlipzUkO8KR7?JT7j zuH#aQ%XM5z*)^b)qB}QADK7VVDMh_El2S_1{p+O^mwT<0a<#vdqI=g%DK76?DdoVR zQi=|cD5VIL8P*~W`%-gj!s{eSBYkT^ns5%6xs>v1`L*)v9|xCGoIcDR0QKK$PZvumKM5$M=#el=DXwtqrIg<&eLA(2qC+G~Db6_A!WDK7td zDP_IDQi=|eD5VG>yB&Nk1ea2rKFqlQ%l2+rMP|+CrH|Y<&lm`Dd&ciQsPz`r4;@s#e&sD{Kr`!-7{F8@X;BrMMuBQp!E5-jPyDi2<}yipzUkO8LLabxJ8k za~+pbT(09%$}fXTDY0{-l;U!)mr~SwBdMj7*uP#%ak!p-w!KIWKBvDEcKz2L$TnH|uIDMFN0m=(jxVl(M*-s5sPbno1MWU4AY=%8liH6ui zl`vsLHG3)LkCn?SS5zJgETw3#YS?e3jPO#5-2t9bit9(LW0fAn-dnNVvbJ_wN-2kx zQnaR8r4-jgi*8JNY`v61dm$PYP)fO~@;j}RGQvtJM^%oioLITI@`uWmm8&a1i2f7a zCYdv^)v_(yu$5;Q_I;Y)>1*E8JPIF7Q7?2VQ#eUEYs>bsmF;a;v40v}xr)7&GGhzy zhkwPsKFu}U4Y(%y9{k5S{p=T8EoGZTereo%^VVh?4lIMvN~PE_fIZfJ5x@rU@$$V3 z#Lb+^d)stGWv?!bv|DL661PYJhHU(L%~)T@AC)7%^>mdCuzn+7@3ocdDr=+f^6;(# z<*nMTV0g{zMOb51FLSwm^b67bar9Ak&13)Avi3y8N6zO& zblC?kj7zw6JZY^id$d4pOuifd3jY%?DbAAr%lHtK-wg}A&x*zU(X>w?Ahvb`s(L!( z*2f9?!Mf$ur93j?3RLr&Y&|O6E~F2N#Xjj1df-sm+Y{TYToG-RHknj!OUn=>m`msv zutuZ*fWXfgXy8A}L}6avtT#%ThM@KLYn}nF+Y|j zgyo6?D`QN9wy?i|gynV<8uF=Yp@Ij0yVAxQJ)m84sSw1|JT zxPO(5UV5&>?w00uu5)#Py;E}Ag?4Da*`a2xds}W5^qo@wUn+N1?ymf`a!=)Nm3u4q zRn~~=U~!Z!CFk9|!6_C?(yN$Pf`$MQU0PYOl3h6+>lHMV zG7SL(xk8zPR>D3iBjM^6ocSeEy^B^!(-62)X+W8CxD({|XhnO=Hv4jhh+=YQisOMB zh9FIw)+e1ptM-y24D4(qkcgr6u@b#i(li8W`t*Ku3}E}nObGu5Spym+R$1$NR2CLk zhCt1j0XNqRw}7;(Y}N``$d>65jOSBi;U#vIY05JF>=4c&Gl)?bnl8yTjuB%$#KrxUL zzY2MVIW!zR&HU(x>}jSgUpldLrJU%T@XjAf?xoexLE{kYxpQ^r09ll?Vyw}c5Ti)U z3jX~tx^Jav2;2r6^ee}#caN6Ya%@yUNzUqCbhu#%(8oU3C!8{v%O#Atv<@Q72pf=j59~}eOKS;3U<82;11WOQp z1e2yAU>k4TkB$NCF0IC}73(TB3zNJb(Rh6TY(wBS*@V{^gloY2h0HHoSGE*rV#Tq( zrl!w4VHtu2dvE0ykhW_xs>M}twwdg)RZ4n%FcBTh?Y+17*POi}#p;40Q*Jwb@9nZ; zWa`cQ{#+Q6WXjxoPh0!rS0HT|AEx@)1C<9W4^=Ef%F%M)$u_!-gvvE5k#?1I%k9h_Utc*#8K%t>+2wq>`G_>bi+v^pg z+#bh>iP9gwm8bT`L48&#O+$N*c#cd1eBT>~lh{qG77ELd=1rScQf?udC&>gSx4m)G zhz+&EQnn#z)29z8bKbI3WcC(&Uj`@lp2=lhgM&SFP#|Z_VEcDw&B2b7jgy;St#Qe1 zwL(+2A&r|kb3mDMybUFu-2ZBL?kT5iL-5vFXF!>AyayELf;}?>lbp*v>)7TxD3EaI zmD_TdTO|zJ2Wv3N#a+da8-_IKBOmFLPGKl27`6%4V3Nzag5icCFzcyG!4PpWD{|!hK&IL+g)Zdwhv}dB4HA{YX!v(LxASZ>yu6a=KJmS)!tg1WJx;# zfFqslt-+kwTQev2W|G=lJM65zHEG56*2VlT{6au-Z~gAtU$Gj$vA5pf&B|Mqw=3^d z{$6>v@?K?a<^9SBm8r_=Xs2lBXqRZ$Xt!whXpd;mXs>ARXrE}`Xm+$3T+E#@ItDt| zwksN}$kWriP@azvrv*&np$eSZFCakt8=Q(%w6+08(#maQ?Y8-u0W2cR%cG}O_fGal zJF$l-!m&=K70I&-gK+dGDJ?5_W(&9_J(MZ9`2rxYKT%+sQZ)hgo!3&|j_fI>M?1rR zpIcns7-uB_Rn1=v)%>IipdN!6XL$_OeDN6ZP1^7ndGQzzMZ2@dC^ag)rhqhX2r6!a zNu^jlh%nFcDC@Ftz#o0EfJNksZFZ0XszIVZ@ln)?H+o=5b8U{w-xuuxQP?lqKRO^f zFuEh_C>&Df2YsWkk((bn3O5KJg$VB)g*0x!DExSaQHYP>9EFa@@Q=b5GmS!gkd#sA zcohFAEbF7N;n79#NyI2*UjjF>QX^Ni2SnlE=#c2p=r92r&{GbVr8eo9Vr?l`^Zi!Fx$GjnKsZ^+XnioX2URFFcv5p6Yv zCv2;Bz@_Ji=r_@;tc!(w(OwF@EH?s!i>O{!n+~paw3n)mo(+^1PAZRye}=B!lw4$rIl`#Sn;Pc4k=9!~u3cAPa#w$$@7%j1Ua;#}D-R;y^s&cWplb!(dw6f%)Dq zq#Oywh~N*@sP{i3jQeTbZ#6tU|4VEPizVpwe(3dq-lL+Uqd!Hz0=u~basY1y*;Afc zR|DQy!-v#vLfNYkFHf2C_A_z%b0GtsZ6PM2ebfUqw`nhB4K^(N@E^bv z@I7A06WCwg6*0n7MC^G^i=Stk=0u$>C#vTm&nGKO`t$G~WO|+r^}Prekr!@RQ66HljV*F2a^r*L<+`nEeWwuctu)@<3#^_XvcaMmy- zcPuKG@eZDw-2IQWZkbBmd{ET>6 zW=u6J^<|kjG|C>v2H#Y8A6M-v0t|zqB!+^~d~07ZOYAK4!(_d`i9ocE*yp(C4vg1U zK%@CwP??sT3u*(Y?5*jr98_4C5QDiw*6EP;ODzU&vyP`jZ}f3C9b^dj9$Mvk*j*7b z!i+&;Qn(+Hor|B%hA8~WNg=5;TM!wc*C$1qpWukVq*%+~E(-kKEZpQ#Zd&XUVXk!Bd&{M;)>^AnST2f&yVr$nblzsfi%)Xp<~QViw#JDe2c zFOxAK%sQSFFK3+;W(-`Df_TJ^CI#syI3it`6n{4+1$#q3<+aK|eA7@4>LGekkgcL7 z1!)-E{OptB^yrM}8yP2s+Kr`8is9Uh4krcq%VZ1)vyLalU$agMGX}0nK|EqdlY;aU z9FZ62n4H@m}0 zLH;rs1H!E1NpWw+NnypnH7STk>}XPueu5*?g-Ib_z?Xx3#4{-{I?A4&6lANYNkJM0 zH$VHNI6L}%^u>&mLhTsSC&i-N`W;RR@|VdN5M~`uitDpZ3Nr?-NkKefN0Wl|6C9B) zOp4o$m12=^QmE+2NwJ8Y6lANYNkJM0H$VHNI5#>knistWG;D7F%68OljIuYW)GLWe z$tk|pT3SPUd8HcexaA5yd$m1RAOxqlGONAX?)epKc&Z7T1)bg}^HX_!C2I(4v^+jz zolZ3y%-$c<9|#`MY-*9c!zvuYA&CONdO3d&D}{?=%#Wu7RU%-vb_bG=p_I1&h31$Y2uYFu>0(09#Zf8x ziR?acM8)bpy^Imxn7pzD#;W^f$T`nnWbO~?KUOe+gEInmqP2n@jgiTQO^ZbJLIY;j z0L(RBFR-m;sR(F?Q`WXY8PD~N@rTF5DQa@kt>?y&0u213-SXZ`qsyYBqF=IB@@rF| zO2ghUR_djk9|i<&uDHGn_A17*lFf8nRwkMq8s$5pJsEyK{H`ggL=v8?62%wwNqZIP z0C+pr0L%WkZYWRST&X>bC=qGwD^Vgc9|r8RJd9Z&lKpNx%xP_Qmj=A5BqEx61}AInx!fW z41}N43u&2Ao=W*8Oa5Mf&iBsk=b`xnqCNcnE^Qp!M_TOm$HyMM52%)g0K-ljY%LLL zAnAuYu7R_SUx)V2>4RM%e}77Bkyt~G;X8t5NM@&Pk>EAMTyYDle~U0Wg+q2+^<;!t zzJk4aM!$$OqCtS27XscwYK(G+0P&K%Z?mzY#?GgRw~*|2F*F1)^8)nt7KJ^b` zt}{69nJqj4uS9#oEXc9PNZ;zS$4GP+%k+aUi4Ab#WY0jUXW%y3PJM4Y?Yijt=!WRV z=q5Prb8~b{bZhkIXjb$lw03S^wZV>5#8;CMXBijau?%jk);+av7#$s3+FA&aGnu2{ zJL)WeT+sQl=l>y#gU^aDdYv3*Tu+|K5J%bLC7<0RX^Cd=1V07fftpe zQ-Eo<--6)xkIA%a9M!eA>@k)!hcTs}#a2%2`HEtk^=O1$NFL*At-fjv+z!X>?~MKu-4)#({WZELf-kK^Ujq+wituLTDDq|6ICXIvTsT zU(t-+gH?cg_{bA?r-f)@n-#5iubEsMR3C7=00{9JCgu`AhGjo2Tc(59+xEB>+%5p5 zzrRnq1d!7u2xPZ<+>&H^Q!U|k0U!edpipy{0P?T$-izfEq9t-Ibx#Uz7=QvdcuAjt z@-OXIVceGBC0aIxaLc4N$NJgeIB3FJWgK%B+LI6yj@OLk8;=o7H_OePp_y*}pmwF2 zIxuiwbbs_f^kDQ*^lNi=M+}wBNeW6BhC%iBmy}a{mL|fvigh2@`S~JO~Gq$0F18)33o`K1rnB)`L zw?;nI(;4LRJMHJd2aqW7JUC#;9Sx2bX|D2wzo)xDGjgl7#+$nuh|DDakJ_##|6=q~ z^fE|)tTqf~u2HyP+P8s=t7zOBQZeqg_^*rWTM1$E?hINYzJBf25(jhhEd-Hr)UM5` zC6Yfh1{RYl2`ip;%pIfk`i8=`-tRg)itsL#F>FwBEpbbA_Ze;iO*)y5)sR-C6XP~llN0-tIv)E=U{shyj0nwHoM(Gn3LsU=eWH7#)mDKB}nLTH;nAS|Yj!S{~qD(-KvPIL(I9P1pYyApo}vfH1Vg*|Hxv!A6h-Z$}Vr z7XV^tiMvST0aHu-M4*<4P(mCGgEFnx(E@KmWZh;F@Nppi`go~k|iv^U1vFK_v#+i zJ*#_F_pa_!-M9Md>VDP3vS^9J>da({mN=MOXeF-@Es^|{u~lRu4q?@qmbhakEfJfY zq9qcK#z?&q>_W9f(oJX_x}YU)pFvB+usF3uvNb(DCg5a$8skfm$N@LnF3~#u8Q?Yl-7ov_x#WTT3LKtrIPgbQ2ng z?r4d>57ZL1pb%Q(5FFjN#)7FOJ{PDZA`Gb|QZR;=ctaK~5wYA_BH2M9TH;W+mWYqx z(h?mHkyT41-2@M|u4suzhH8lz6Ix58#(}9NJ|CzhA`q!1QaFZ|sD`yqOVnTpEs=sT zw8ZJUmN*0(X6*{mMCBQ=gqAo&YKi1vuu5uQU9BtH)H2t?nD7C5|XDgU}Kox?^^3(zV0|AzC5=B(+4!zosQNrM%?P5)pvX z5-A8nOI#A7B_c#pOQZlaEpa$ROGNicEs=7sX^ARC9xV|8C@qnKFto%MWj}bdLv62B=yJX#`xP+B4dVrYr#`{0~{Lo#rkOGFe(OQcW?E%9wlOJpf0O-n>1&e1XB z==$GK&YpzG&b?-Ak@6UI#>PZ(Mv*(i%dImWz2q8wIY zW@Ob8&#zuky|8*R-?K|C(YJwHWN3-dT0={OJUn3~gvq@#Xo-te&T(sr!@2D&gg`Bk z{Gly;Ycx*d4m-s{$EfJgU))I+l>qJW=-Gm0BJ6d8nP)pQ;LTHJ@xuQK5OfB)o zKrInrNG*|qF|@>!vS^8j<<=6(4hqo{XN7Bt_!urN(eV&jwM5cQ@L=nTmN*isC1Oly zEs+`rrj~e9pq7Y0q?SnG7+Rtl);=v!gCVp;3dYb9pV76%VUL!GSVBu2CbdLzFj&i= zBMDo}puJ8N!t2b5uRK2~b0LbOEkR|daeiV0yQwu)J`#0xTM ziP-EEEs=P%PP9bQO=ujtpd}ukK}*E2IJHEwHQBX9(oJ|!x}ha5*0n?*iNe4LEfMpC zp(T=yvPhI;%v&VNVI^ipRxRffsOR`1reMBfH(Geb*+)*4zOqJW=-Gm0BJ6htCfm)&# z6hccJ$rbIfU}}jc2Wp83Lu!c>jG-m2&Y~qEmRn0CJ19g;d?8#*#K&-HiH?WJswI+c zf(Khyw8Yy(wM2{wttC?9z|;~?3Dgo1h}04(979V~!`i1MYA}SBNWmCd;`O?g$i4}c zb}kXIgqAo$YKi1vu$Dnb61J8>hm}|cvucSCR3EH9RDHPmNOev1(duK>$E#yOTH=xv zEfJ!-r?pNQTH-SyS|S1@wM5FlrX^07@{&hOL;y-lq#z6}@wE^w5h0RVA_bsni7$p| ziReD5B~tD+Em4KYqa`8$r6p1jhL(7m><5pQh#-`fNP!qy;zkn0qa`8;r6p1zhL(6+ zpq7Xzl$J=L7+T`FnwH2?PMVg8NSvc%#?ke^k(@mVk)31NX;u4RR2+`d)nR7HP@jWSvrE7@@Lu-i?imoMY5~w92j7v+T zfJ`m1DBF{+B_a^5B~mcDmY9NpC0=K0i7Zd0X^Duav_wo*mhv}}v!^d+ zs}M_;u>5wN<*b*huT)>HzE*v``bPE5>RZ*ftLJ3V5;s@8K1E9$$sJ%NuMjPf{FT8k zm|{X$iLGK*EwP?SOT=cUXoqJW= z-Gm0BJ6dAsw^y{F5L)7*T+tp2rk41NKrInrNG*|qF|@?3vS^8j<<=6(4hqo{uL;)@ z@iAOlqT?a5YKf$q;K9}vEiw4pD;N`6OQgnusU`k0P)kH0QcI+83@uR&YoC^=!4O&^ z1!HK5N9$T5`;>N?mWWtFOT;f}<1*+-u8FHYoOYpuCi{JfA5^ERt7|*ecCPJG+qJe^ zZTH#+L0aO{6fF^=d%Cqw8Cv2MAzC5=B(+4!zosQVD&-}QmWTk9mPkPuTH;M1S|UOu zwL}U)(-N-@(Gt;pQcI-VYg(cTkw;5J07^@wAPg<>e`G&+v_u4suXo*?Ay@FwJYKdfPvTKQ? zoA97?LrXNiz2YNL7#N`?VxB+}a`s3js0sU=c4hL)&? zwNFdbU^8^o;V5>KrCrgl>8 zy)7-9vz}3B0y40r2K1I;uTU}@@R<&Kxv5- zgrOy#5~3v{L{dwn05mP}gb*ze-6yp~%Dtu~st|d!LDeUpuFEZtc9<`L%qQmN@Fs5+S;`CUcIaC7vy1v2-mF zVQ4LpLeaIvI|H>ugmGz!6p*PUULxC*t|cN6ttC=0x|Vpp1WDHt5rozfDG*&tR6+A; zi3sD;5-A{4OZ-8gmWWU;Es=sUwZz8)wM2w+X^9k+sU;o~swEmE}OWZ8C#zF|x63HJL1B($m zJByZxSZ*zm?4S@W@mJwmB0h#oOLRO$RxOcq6Fk_uq9q1@dj(@cYl+l2Ftx-*fm$L0 zky;{!V`zzLSo^d@4TjJXDHuab+)~#PH}hzTh$Xbd%}6bg91PYn=t#oWGU%`p%V1V5 z@w(dewHs=(0GgKgKOtHox=(6}lzUA}R3Y+ci3mVxi4=sPC2l7B z!J{Q22&E-bAcmHBmIU!=i3mbzi4=&TC4N0nOGFe(OQcW?Epe%)C9;&0rX?a0=jfPm zbp3C$oIMGVoqNsLBIPk+=_dO-&bQTWuia6*v-X$TUA4Pwf34k9`$m|SxWc0)LUdn9 z<{V8++(*h{=~^Pf&{`seqHBp~2Wp83Qg67i_5yqt@Qb4AbSPs+@5z3_{Qc$Lrcx9lLh)^yqk%BU{#QzG_5)sR# zB~nqJW= z-Gs)W3tD29Z?9ljoLVB;n(SI4=_WiV-Ov(^Z?E`B6b43UiI^u0Es<=LMWP&I-Xc*B zD={;&YKf249B>x(Gp2Fp@Ha*miRR(x~yn`L7cJ!(c5jehinE=y-^^a@H*<_U3zvlk$IkvIx8@-?!uJkYQwHw3Jyl)fFvq zRp5PzaZG3}ks1f4miSL$T4D@DYKat%p(Uze?a>l-7(z>=U<@sBm98Z&N!Jo%ETJVX zA+pBln(Xg5KV5sK_H6CB+Viy+YA@Das=Ztr4bc)8FHF%AA-et6I%Q~y z{}G@i#sEnzk@Bx;iNBWeQo5EH15jEb1z~83I|OKnF+@^JqyRK6@kaq#V(dPtB~tD+ zEm4IiT}zAsC@qnKFto%^%YI1L5@QfbOQb*yE%7)BlCCAjAe5F!ff!n1BTP$-Q7A2u zLNT<&VNFY9DJMlsjFC7;$Bd)ve@k-qBt&-ZHDgPe$EY)2{%Y;D+UvD9YH!xws=Zx% zr}lR!U3?1`(m6`?>;1>CF57;G`3n=fA&-^_(VdaZIm+wgGhJ z7$Yhz5mS|={4L4Z(-*TpRtVuJ2MmErXW0cu?{B z6fJQ{Znl-YLbOEkR|X4ViV0yQ6qBr4;*DAEON^VHq9qcK)`^x#x(SU#7qrCl!tYCr z!{XEu$<}1o5=l4VLFtB;IIiE9=p#`$O@x++dBV^V$wpZu$}#3G66LTGGb5{(xLbYq z`X2S0buH1ifg3cmL};y{B|;uv-%1FRmu1irhg8mSYl)lZ=35AXS|a&FV_-2FOIY#P zcA_O7ltoL#rn|L7;@LXU5=l3qf#{Bw_)egfs0D@45;xBk?Xh5LiTOY+5n)Izk%BR_ z#7DAdiHPOa63Gq<(Gn}+S|UD%OG|V-L{=@4bQ3(-x}qgM7OEv;OlU2U8V9D9SP0Y- z5s1_hDI7yfRKwb*C2BB)mPo-ETH+^lEpc;?mWWtFOWd5)63M|}ErX6EY%PNhE3ph_ zJ(sw5eV_Wi^)DjVe(h?~YLra{kX^AZ5q-lwW#5p=< z99{q0JZDcrWanNpwn%x5Sh~r6F7c51q4mS+hu4p&A6Y-Desuj9;N?MD;*b*gfRT?@ zVe4%v2N2!QC3B9ZCCWGMJz65d&{`seqHBr&6R0I3j7v+TfJ`m%+fwFB*Afwk))FZg zT}#|nf~0GS2tsR#6o{@Rs-XF_M1*l^i4>5jC4MYWOGGG_mPkRFTH=0zS|UQZv_uNZ z)DpJ{)e;fQr6p2Wrk3~#Q%hudDosm7M5QHSs!GgXd-`Iw3bAAf%Wv0N&N{AseEo#_ ziS^&qPpY3>Kc#+ZeRUQsaai&C6fJS{+(IjPg=mT7uMB>{6cfTqY!$O=iQmkmC1SHv zv_#_3I?)nIH=%Lpf|gj#pe15hoLVB;n(SI4=_WiV-Ov)B(6vM#iNe4LEfMpCp(T=y zvPhI;%v&VNVI^ipRxR=L`Wf{z>+kAXqHhB?Y-owlT0={OJUn70gvmprccADxw~xz% zkaj=IimpGIKe%wgf<)zYMCBYqOPsZ3d)dnNwt}S&F3fFVLAb@lfM2qqLLA&mZtvBRE@52S^i2;6sW6>Q&aRa%9_MJ}D;vy79yD3F` zM3|D|#S(`rh0qD|6y#>k_$x`#k7HZ{koLb#GIVG070tkiB-p_~`H?(BIf}tU2qcu^{Znqs? zHsSICs$zhjphmOl*PSzpy>fRe)Ix~Oru+!V(B{stpsr{)COPO#Vet|<>bPErqi)!p z^OUgY2QrjJHM)JuA`Uoi2#MQ|V@Qklw%>!1Hh@_;-@8DJtKq@4Os?#exM-siV@oWI z0fxbYC;M5&-__5q|Gs`s{oML__4Df&)Gw@`5q%xnKc~ouJap%$_`pf_rll|9HekFq z0ZUhL%v!q)f$_cQs|=z5Bpwhx$q|yPghCJkqZdF^7&no6kVj!0Q3y(5^kNtiV^OvO zs5`b|Br(4fhL9M&2%5&2lm3CVqyNN-c5H*t7`^^Akx@m-BQhd_5*fW1hRS%E>| zh$u>B^r9Ft;};}~M`lD6B{O}uo1^-JoP)-S97q5jAE<@GD-SJszA-)5OX z>4L74izBw$xUSkdL&&P_3d=xIG6N~MaCC7UFq(S!#Su}Y;uwOWOO7gTKFJYrP;v}GGBw9P z%RUlPBK8s6$QthsAr@+mAy}s9xJ+UREfKMjyD~K%P;?BzGF8VnqVKV(R1#VuV2Lf@ zU@}`NFjO5wz)ackZ|x%Rzv)Uvg!z~6U6{6QQkd~CRN_j4+cOz+SCA=7Ujc@lWw5L3 z*VM1AUsu1renb7n`c3se)z^*QfUwUk2{jSIAj?F9z)BLKU!-&ZQ+vcMAyYvhmJKVF z2_ayr1VHSw5xse9C+Yr~v6FO}aTOq!Resz#`Y4kCNVnmhCv!iGBS*eu0VPplrhzf z*;B$F&6oMRbOC;X!YAU=4H2@?ei2wQ&qwH1I2x!><#w5wAMBY-rwf^V& z*ZAvTbNk0emsgkaT$%E@&&7)jDU$8*{s*^X;`hY~D?v=YnL&(PtddZQ7&(~R&Vmp* zNTeX1gJzZrJI*u)4?74mNd7X&jHjVa#K>wEF%ny!B1V#J=*ds#vrWynS@M4=eaf6~ zU5G_@#K`jl#YinKlo&afE7~K%6eAA_6eAIb79%MfLyY`!7BLdRj029CJKUWVB1S$K zE=J;WIK@cEkjpGal751xUw6dFV?)JA42wgIqy~d2Mjjd{Mj{d|Mp8hA7^z0LPmI)X z#4$&EtR-iWAx2(kh>?S^cSsW>5lxDbgNfDAJ;JTk(QOz!c(RL;chv8!|D}Fc{qFi- z>-W_ER=>Ai3KAn1E0K+9miqF@1Qh7Y?^$b?Ax7RCB1R$tAx2UFni%<>l%_mlBqESv zB!yv!k&lIlk%&QvkraX^Mm`iGMxuX0jHLW)Vx)?aM~p-SQjDZ93^DR>*%ux$5>ZGo zl0q@W$QcsFBSs<$DMnH#h8TH8pcsiTq!>xT7-Hm!x){k4P})`%v4j|j`3Lu_VnW*U z5edEDj%6R8727yw7bEYlKTv`v7BNgg=LD7^8&?4#Bz#}6qYGQ z-We)JBA8Q*q`*uu@&ZeYWLYasj6_TnBQbF$r?NehF?R)-vh)>T*jWa9qW)z4sru9P zXX?+^pQ}G#f1&=PEMnwlN(V?2BL{Oowo+M;7)k!j*hzBvhcM$RKxQ#=<4j^CwmeOY zB%Y0lZkfeM(ob+Gx^Nt_KZ6*Fk#UQWWP3UgBS}9Q;?fN<@_0jx^wBL0juay?Yaq#U z4Qllf=>Wsv2!Q;wnn_SnrXE0V z2P;8L-Vwb3&jsptyTR1&Pm8(`ahhfc-q*-XfxH%3>!*v_?()%;+8mwNJung`{-Fl}aWI>`MqK<=M8DK8HhsQqiyu8+0Z z@eSVS`Sz)_xWUR4;;FZ{Xg9dn+pD>SLiWd_5-TmpBXBCVP+72#qQqF5=%i!WP%N?M z3#|R{mvTR!$45}4XPG*$8EL!~P)2%Sdi-3UFV2_=abE}GK5Oy|(F_)gzQ)S&ts)4z zD!mO6r%>Z?aBCQB{9vM|F}CQ7gFwHq(BmU0AX86g7#1AgV`$C$kPxZ8F`F?THC+IXswyM-k!%tVD6Ix{R7a|)1a%T7hbQwQGc`kR{h@u z1t_()-m*Qu3i@1}$+0V~OBSlUB@FdxHWB5D1uL(BLWC}1l07cek79fIcpETif)-;i zGcN*AGvN;Wza?9-YP{BFH;cEHXD=C?07g^KOGta;~^}pBOt-n`aTYta)L4B&ex^a`xiTc}Hwi{yliVkE+ z$Q<%Yrnj03o|hPc zEu;N@!4kYQl^X{)vR|}Oogw+M_@C+w32Wp?n;lYyO)F2x^4$WpcGBI-Y<&$a?A+L; zv1?bL~&a8l}`R6m!GuV}zY$6RrCa?mKB5Xz6r0t&o);+7U;5M~A~ z@M6H?B|HMerm{3JQD+F^G`D@iF-8EZ5P*EX!2N;$o1-5 z%v@u4*tbVx&&FPjy&L;9_HE1yoM&novgcV{&a?GX=h;BmJX0XnJab~`^K3)ekoLru z4K_~1t**(LrZBjjHX@xMypYI!!Wg+wEM}$pgiIM?L!F#z3Pu=);1mkz6@WHsGgY8} zxqK|oU{q+*+#Zb5iQPwu!RWTr2cyf14aO(Z2II$x!C2U@v47)$#(|B4qSxU+&n-dX zhB6p*pj_4#B@c!!8B}YhFox!GDP)F}LY6WI8(0I9E#5`BkcksnN(=G*jI}-8hPC`E zv*jj7N8F?uvV*w!s{~OM?N$dvVL2a6ra9GeVXhYR^v7dL#cUaSv2DTU(TTawNmv}F zrmmV|SW;+9j{~FT>d6dh{;BrE;G=Ij?@AmCYJXv7eiagKtcJd?F@l}@tiqanmDyx7 z1AjRug01h8dk=0L(%3or0Gc?rUyNavvZNqGj(Al?mDXy=ONo>>ovr;F1&{iGU$WMF z%|6W7e<9k4DN_AnFtZTI^E+%WOALM$1Zl5EzxNpfCqRIo;E;4@8XVhx5yr>>b}t5q zo(U>G%3e)|fQA_doYe2B;S?N!?6cyq#^H@~qJB0crm-y}-_XW`f|?h25dqq(nIY?l zYL9S zA^hp-vFFIfx1)FAALHvHB*7%ABAa7XggT(j0s+FwLYPFMr4cn*Qhuq=0jC-3_)beC zv*npk*w8Fp(EyGwH7`c7baEXxURc6D(|-J--EugHT#|l;n(*%s={Y43<^-3QQ0!g= z8cJ9OL9M&4^2?x3&u|zyZW(nLIkj5@ZbtZsJP4~!9g1E2kbS5qeh78!&>!77bNZxL zXz{VphAf+vAd`V81*uGJ?jV;XE@6n#gt@)EIY$~>-pr%VX{YVeVi!EH;pp>PK5fNY zKjtnE(Y1<{dOl;9cTKb%8+*l3CLb%xHe_#lH0$*G|oYe2)yoTyOHZHMjHs zsFlm69o;ylactwb#_^348Yeb>(>SSda^rK+wqWPE=wWlzSD7wih8fr#yl35Stvkly z>O1BA#=L)7@m~y^WN#{pBMgIZdU{IAEsW2F(Z8|QfNIEYt)NxNxG`WAgu!J1NDT){@{uBYv5#B+{LNab;cpW zAE+4;(m26@LoCC?u-XiRIY}mS8}PxYPmHO_AQJKwR)<#_>KVP&@kq`cR(IeyrK zHJjO+*^YZCu5V3_$@iii0bLU9mF=ZlL6Vbqp$ZEXKz&6P28_5%nmpNMMhhO`C@ zVqtCr3yRM}QAd{Z5Z;AlHN;KY-+)ILSgwB9V>gq20A;T=Q+X)b*gfYq?hb$1cXPZ8 zKZQ#U=H`2s9lI0?nA*)g+Rt zR5xhX>f)9=h$Ng`w3}@a$;+ev3%xmK`ieSGoo)HM{IUW+pG$d0XJVjZYppv~xRQ{w zXY2mi8oEZd5O(e9{1qXEWe}XnUw6yGUlA^azmfwYxl>*WE>v#ET zFlSbK`9ipaW83zMt!nT-3oJbR&5-#+_I*EbzA%3gG^;k+D1ieLc{JLd<&XY0-pVLX z1>3iyXxR3f&^X4DnPcOPW6ywg1`=s;XwgO3F|3?S1vSqg?0X?jI$_svD8f$lpF!Bq zZ0BJ!sR+C0YyQSGJ$cgPwN~_NhJAh-FVB z>@&}AT+q0%aZ%&q#wCqQ8<#cy(D-BH^2Qa7D;p;U(RTa*1xec>*qd5Qyg}Q~4y5gf z;-Kvmj!D~RhR}9|p=djWq0#n(!f1O80jWJn+bIx(wjUBm+Y!e>+bJNEw!aWW+Yu+Y zIXZ1W+@S5=xn|M!L1L}}%^u9zV~(0@E<LhXpXZ#+FU=_}KS9^28@%Gi zr_yz@5jI`NOSITw4RwWAccamT_vZFAxjLH_DWBGe#58g1^XAcJl~oSllNrg>ccAKur!*&)dzD+ zEGQ>ef6w6RgCG`Il7vC;@Bt)O*PAK0IyBS9?zy#bNCvKsH(94}^`YDrWCImjW}={V zF_+w`kiWFDENpxTvyQp?yil%=Eq8GBp#$NC#J^ z;7qRm%`99U;ZnFd(bG&>{Rm4L@aKLV;MPE{jt@a|b*jk*SKm4lS4XrouI^~Fs^y9{ z&k_OP2mWT}`*zfCcI(Py>JC?bCyc9OTu81?b%M^-|2vGUBM8aWDG;5jFVD)=V>pA| zn@bN*X34xkbM^VbTs_8iaCNG+7FXXLIdnQ#M=YAFQ%D9^|98Ym=js{`#nmYsgRAdh zaP=XNypL#VGO3M{$<@iZYM$y7q@FYkU)eHq_1hY^H|}WM+4xK2uEyPszc%h^{H<|s zZHau8uGiSEn#EuKuGit{y{> z&?_h9s?_5(GXExV>L=O>jjs0`Z9&-+^ zP8wQsjrP|WSAVeaP~+joBaJnUN1=+Cfve-q!Kqw*DA%y&S{PR+e@8Gg!mcx}zC`YY z!nis%K9#Ez50@;hhj4Y$QFt`Ez|}uta&ex^8nxa`nd>Pr#9`?cg_9SNA0Yyjhwx8<;t?T0dRO{v}tOuqMRhxf!|oB9(GH zTzx3FjRoc8>h~I4eaOSr@c|@P*PAK0IyBS9?s>W~k%6n@)vGC7eK@xr*+4&6Cx2;W zS=inZW*u|&%R;$2w%ozhhvBAZtJxM;|L-hZ9pO^AIt7{J>PLlgb%bR-;n z)e$a*s}nsP#?@6-P@dqHrwfzk!to(!u1+=C;OZlpxH_Vxadk(VGjny)Pw-^w4p%=o zjH_c@NUlzGg3i?^!nitukX)St(Yg9RWaa8HTsl{$fN8G&elS;$u^n8U0=2mMw~#}p zb9Ka`xjKbpaP?8dN$2Vs4#m|e9D}QW+u-WM9M;aKZYdChtJea#I^sCEIt65M^;3hmI^qO3 zN9XEIgR6Vzn%X!^u1?K0;MT)Ad(1hwI%#Mve6+vLxcb|TcN%|hyxVxMv9|HGEL?pv z`X*Y7iw);~Y|XVWu1@}rU}l6}XI%ZROk5ospUTyVhwF^1la9ip(FLx4g~`>~tVrYP z7$3#eaax3o50a~Y$QS_SUIYJ^fvbPem}=~Aa&=!az>8NUSBF+xTpd!}4%UR2+&3dv z-%O<(4_6<~{mg=La`g)hu0HJH>i7VXtLx1aTpgNeWB2UbJU9baU!u}W3RfS=ttK1j z=j!Aytt<;WB*Ls?uD)d`SI3q+xcW%0XgAy9>JwSGI>M!JbqX@c)&Dz`t0Sa?t5a|$ zSKlZLS4X%Mu1@rH7*|(SK_6GghoHGS)ntRKubYXhBU&0)ceFV(S10`hPp0m0^#x&E z9pgfBb*d9|u09yX)e(f`>J*61)j!C})nmAHu1*2dT>buFt{!7MxH<)DarG^bL#K0f z#G<)6g=BE``G}Lw)ioT7t5Y}zS6^yy^$`zOM>NURM`*52&M~U4P8tSJ#_U{u*XC}` z-J5$f_iXOf+`G9?bKmB#oBK8QZywORCWxyqQJWc(t3$B&w3c|IuD&9Wt0Rhot5Y~8 zS3fy~t0N4>)hP^(tA9F-tH%%|xurl1uKw9Tu8ueku1*1&Tz!`yu8ugt&C$8~0)wl2 z=b9R8lB-j54Y>74&K`3Pu1*?SbB*@b8CO53d2sWP=Aq5Qnuj-QS-ASUF1S7);#jjLmP6j#S- z;qO1C7l&Ae#~?dbKeBmL^A(e;`;x)tcw4Ect3#_Tt_~^g5NkqAiZ>L)-&fyUr5q1e zAITkIK{>hlK?YYJ@o;r~0Lj($W(uwj&9t$5j%~IxaP_4sy`*sUMY$8m2Ku==`AaLy z0#_%@I_B!nhH`amxr3`O$`$QqTU`A!S-3jFrEql$GRf7epg0n=RloM5gVV>`Gy1!{5ixyYf@xjJIeT%AHP zxcXa&lg`yO9Ez(`I0je$sKM12dAK^FNv^(#=IZ1eqqsV07(5xXbM@n!Cp1rN{-$|S z^W^3!%~PAFHBWDz(LA&H+vb}=Tz#q9%#d6if_=KR#2Z}wAhSpr8{dLCGf7d*_`TOQM&2yXQHUCc*uD(odrc=54qTD&wTnpps z$7$j3KL=O; zkTJ;4)h}pX*o;iB?n?&CEUpf%wzxW^xC^WaG5OCK>*~u?%JFdZMY&5XC?{9{p25`@ zdAK@0faL0WGX+%(o@%qLvV_0=%BKtq{W8o}2Q17HlfU|-o7#&e;g#ht~8 z`^RG#ix0aSqx0djFk(80egAk2V)0=&h|Y(9jyp(J#@nu^zdlJNu`H6j!6&Q zI0ilZqr87ynWx@>8l$oAU$H!D(?jKkn1?1kOfd|eXltjg9cJ@}d^s(j`_iraKWf*R zO}ni5hvpxfmp89yUfH~=d3E!e=C#c$Lx|xr*Zt$r4%kz(`^T*X#UO@Pg%QITB|!|` zI3_WiCtJh5x&|{X{wAjWDW@2RnVHks(Hi(Jrf>;a zz}?tmBSGL49${$B2HIao1g>~}^M>Y)&6}EkYMv2(OZYO+E#c4<_U0Jb8;g)TZqDJ`pAbjkJpk9V zA1^w&P%QQq%zN6YJIU1(8XKU^+HZi9X>4wZ0hP)d<6glZsM#3OIP*LJOWyk9X#cno;=*>fxTviMeVX>TSz?xDE8H5n%#4ljN# z!z)wC;wPZOP5^ERwjlU?pGqr!ru@>%dNcr+YdX2C`&*%O3R~`=Q*gPO-E50aT_iW9 z@|te3^G#gS9fz3NnH|X6o`jh_yU2aAZTvBzoDJLK;A~WTOwP7L7S4unDV&WSIN3QH z=_hy?b%(PpMFx_}*)S|5XQTQ+=WI&?Ia`cEayAOa;B4E=#&|dz!jPPeLeV+fUKp`d z&W0c)XQM!L&bF1D9^wXVT-g(MZO5}vSO(3*jW#MNzc3RYL#RQR$T3u6Nsn8!oLL4z zZM-o+3BLgKATq>sCW=Tj6QzP@FwvhOPC66Sa4059;TTNxNLi>nj}7Fbh~nU*6pqP9*9P%X#92_8;+Y&iHR+>~t% zA~3Y(1nsXgKKgL;k>;A_qs_;f*JmgvF7sS}4KsrA2e`C2*_fUp6u8(noD))#1dzXD zL9l2AVaNBUnXkY8RhDvM+;~MsNoGhqT*h)@S`@>h(S>s2cV#&dA1Iv`;^0uU5GRGd z|Lk%iLJ}h>JO(h>)`$_u*|A9rfjZCQ|4~~jdY@=M+59HoD8ZFl@DM=he5oM5{#x3b zNtJsjj#v|7^3n{X5O2#&A%$=QrUem73dvtusRvel!mMLb_(3Qs#FjfqA>86+H`^kG z>e?L-DMTQW6jCrcDg1dTDMT0tDWrf*QrOHw3K1@a6cYW~Q6Z1?6FiK%Lkb^6ijztT zF)So0r20T7g>wQ)VT?kOLJGzpg)75IA;OTPkV4T(q4+G{9Qn~-RV_>u@(_e1g%pTR z3Wt%Yu@5oDOf6A(j$!zLRx^?E9F&~yCMmoUp**BegCa>G)h3e^UW#NbofIMxO$sR> zgA{IwIO(KN!=Xqag=3Jy|7Vaw&qb2U5KWRoxM6X}-k|BOmU@#tez^3JofJOPe75;q z^ZDir%@><5HD7MN(tNe~TJ!bh8_jwUDa0FmNm2;G9NpP*R9sE>cK=S)}k;gA{t_gjJ-Z<^+&9xIoz& z8xB%P8d`IV_SYFHe5?6(^PT43o9{NC%0de9DqZ@FsocuL?YPNS2arPYcPt1NsUYk+ zBZVK$L<+I-sics2xXwr+=_ouJT_A_>SwfEHI4VIH*#ovFkB}xvA%c*kkOI+3;cR4T9#R;?(4>$8GD)GT*{h14 zoQcW9KN=KC3MnX)6ds0TEu9o15={yzAcGVRAx=6e)Nm+LNZ}Zyux*e+&y9s~CX=KP z?`br-9+?%WN+D?&oIbLX!qu&vT06IPY3_G#_g`a}>Z#H(US zQV7BRp0yksq;Ts%Qiv!HQb^&Lr0}93QiwPtDWp(zQkV}Vg$Uy!g%pxS3il2rg$U*% zg%p@Y3U4q-p?6MLq>!2uK;q!0UTbVPNFixx%?a9HXQXhy*8Z&nS_ifcYVDkb6ylw& zsiY9DVNJF=fE1FyV?nT}0%6w~DLgL|Da6L7l0xF)IwOUoqwr{SffOEVl0wggzRNH^ ziWK6c@b{mC6n@AUWG97(v<__znWWH{3gQcW1u2A9Tci-O&kojvnEX+ON+I6=mqH5R zPCpAGloXP`v{Da{Lc*+LQaBPy3bEx5QV91F+0C{{VKs~tA`nRmDHxp;s#1uT6e5g+ z6jDGYDV&~#6e3&-DJ1%}BT`8E2_8n>A%!17ijztTF)So0r20T7g|`Qi!We}lg%pfI z3UjhCp5vnkLy|%YMJI*xF=DBt5J5;%NP+02@WoJ47{kz{kODGEp{m(?NudTsl0pi~ zB!xdgvX)K?5s4;+6p%p*XCY2HDb#Q%Qb^$#q;R1@3O!fjEkiU(3h_cflN6F!fg**Z zVQ~7$P704`9oagnb#&{P*0HVQTF19eXr0*lP3xrA$*o<3NFm-yN|Hhd_MX;qY>>i{ zKvIY(4pKTr;8Lvs%Av9nCjNczo2C3gVk%1u4|8RF(e%H^*8NVzQip6yim5DWniCkFy{`Ng?@5 zEA;>=B+NP{g*SzgLTtH%6v72KcC#%~sOl}AN+AM~q>zHqN#THOkCzl8jDr+XKqe`C zGz%$2xD--I^lL|?kn|HgjJiV#1Mh*su#lvX>I0n=o)Sn3V-%7UQZNQ7yeEtlA`D3i zDHNR)z7<9a5ria#6o^g=uMH)IF$_%#DIk*+))C5cd{l!XNg)MglEQH$Yw4sAk!Vs# z0U4z5NyJGfg&Gb;3Mm|e6!saU&~pddGDMT45O1C{NgT7PK$vGs5eDa6Y!Nm2;GKHXZ54N^EQkQ5?{gA`IYCMn!L zh!i3YNeU?xofKXaN(vFiMG7e-ixmD#C@DlR7b&E`EK>M$gA{t_ghdLeIRPXN?jE(q zhJzH6hSr>*{dGnPuV`J_x~g?`>zdZ(Sx6z?LYYbm;bO^Ts{=?O`8yT_i&PMHosq&v zGm%1Ud@3m<9e+Wli>=yw^Lez_ZdKuR<^fY zH40oUSIn(rUfBt&PwW*gM7UXG(ScPohau>F;?eTGpJhNlnLj+ZV1c_~+*rMmVzkX}8YWMl6`LmMHY{OS*N&R6oZ^K{ z`YWe5wf@xFvNi&jRQ2&bfZHMu>AAjgOXbeW{gpQ=zm5)y4v&tEj)_i)PK-{DPK(Zr zeixk+ogZBkT@w8vx-z;tx;DBkx;J_(dLeoxdNq14+O4{O_2B9u)#IwCSI?_nRK2)* zb@i6&U#s_3@2@^leX06Rb#3+i>K?TNYe(0Pubogkvvxu4irO``Yiob5{jK(B?aA6x zwO4BI)^@G$S>LOEaQ)c&Y4zXM&#GTkzp8$7{kHn;_513N*I%r^T7Rwnc73PD?u}nJ z4r(0QIHGY>^c;HFs$q z*gT?nbn}?zam}-u=Ql5EUfjI2d0q47=55W}n-4V~Z$8z0y7^}Fz2*nasphX+2e%Gu z9o{;n_1o6jt>3pUZ(ZBEp><>H=GGO_8W5dLI-VrYzPz7WSeGlh{+ zWc^v%dilh*qpe)-fWj8w2mfGD^c1nTioN-n`NEFtcz%)kpNX-Nepy#>`lpJ0Gv*e1 zXHG5=H}V!nD{VEWe=>iw1q;ke0QEM4B{Y#=T$a|vd_lH&0W`6vI7|L7cD2ULeBX}z zzOt0xdmB6p-mzvr6VU$8i1|MV zoov29s0V=A21TG>w)uZ40#mPKjDUI`BLdT+uft=`DYc_UedS6u2Ilj-t>SE}w_jL7 zu2tPvw1;?c_H6VAN%r7qO9oLGpI~E5-eqZKbKO6fr8=KCPj~{)8?CEgXQvo=2j`4eKA2>kPhKSR`mCPS{6A`$x_E2r&#l{9x3}(SofZ8D z{MWe!cA;PoW}QW1MT!sivsS6g#=+FcI_*}jKxG{#}p zPEO%ZS^kFmo5}ZXDK&eydAT!?TTV`{Y~W?t~lo+}uC zetV|$)13BOj^fXYGo?T6y-Q1(YHyrV?En7nnbKXo4?8p3tv#6pZta!jpB{4`GWoXu zP>~<|4^{cK+0uXM{Ux7cXI*>7olx@TarYsUKRr=;Ak^R4+|l~=&zDQ3+d@5^oeixA ze^%rhCHJ8$Kky$i`MLj4k+0rb`cf!ov*pUsKYw^@=|6{doa=4xYCGKDpPnlHS>Rji zgDvIm@8^G^^qJ7j+gVGy8Gp+1lV5NjGI{Pj?n6bs@{6Va7!2Ib25KPwl;w|p(S69| z4gaAczrN&1Rld1YdNdfg-8!cY)jzK+mHsdof_o#bqut;CaJuyK-e1&in>pXPd*Ek6 z{P>g8r4NL%c6x3o_0NC1v-Igecd@LZ2L1ED?kx4ggwRV-t>UQvaQ#E27ee~pz8iY| z^Nlm5e-SLYIOuI_*SNnwI#c?Skh<@ukN$b{OzD?%>dc?)~sv|D;?x(feC&`VDvbGJEnU{;ZVc*|PtX$&dY~YFWNib*!4n zAJqM)iv0J+$!X-M!jax?I9M;s_wMqa;C5&Ir;2>;<1S$x34i_LrK#Sg);Wc&>vGhk z!NERXX!=i?{QV98sUkPp{!>-{Pse|%$fQ1`!+QMt{LE|_ng{$({QrM6y zDO{6J5ze~l(bmav)u3hhv_UhuX3&cKszIxAuR&|_8H3j4K2kqX*7w^Og2##d&;aWw zJYn*({9fcCFlaGb82G0s#PWf^7IBC{y>siR_9n5f7Fc7`bL2j}fNx(Iz@QfoQOfe& zsJMBU`Pex*GB+~Z5<gP9C<@45GtlOr^m9HG(V2#qF3Xf!!O zBe@?~?RA94h+SyZfeoS277!Y30in?r5E`Qprlbpv3DnRSp$m=Zv=AD}H8f@iE;ObP zp)rLBjVVNEOd&#J3K1Gph|riqgvJyiG^P-tkx)aUwn#&xK@l1aiqL3KghqoRG#V74 z(Vz&8q<*4=&`9j(a~>K^j?fr+h!`<6Qi$biXpGo}#_S-3Mq*!W9vaDgcwuNfL_uhb z%G5Nz4!ir}*Ci~PQ!|QmUd<=0EDH(CWHDhCIW@-4qr9brm1Q|$nVe2oMb40w)^`U7 z_^LM893m#;dDShs<@2iGYq5*f9sGR4fZ9vVkEsvm3(2f8FT z4%NzXmfEe_dHR*m=aVKS*RQ?Kr3*U1gMK-a_Mu{>Dq9qDW7czHx`%3I=~0_gWAL3_ zTPQ>FcPU3$Dj#gCDfm9LBA5R>xh(gja#qNF<#mk|+EfNm&QPHVYIi0plxPC%&ZJ6(nbhuzG$=6>?5@aJ zOM%@LX_|_b);5&^lr1VWLG7+cml92Y-4*FkVJ5Y^Dnm-l1iNt&U@5S>D)*R*mUhKd z22ie2p$TetRjyH@39uUrwxwLy#3j;wRF2^$-9dk2Z&SYr=8J)YLxsHvkDSnyt<7`z zGO#|B$0_*Kt(~^~HsP$M9=7!I@T+6A@96K4dK-q@9eE;!oASGa$FzmFvh7YDh$ zM_gsy?VatR{If`>W;F3&V<=BXcElI3-fgY-aJ4X6K)<6;s=hu(hmQU}>6{k3-r97n zc$(Z90p7VF--y&30V>Z#=8YI`47$5Rd6w9B*$`bU-;Q+3Rfp$A2Rnmvax?O2#}VIj zNaXo(K14L$J}2KHcf&Uv9_%~e1q!ozPyWEQ2BR9L0E$<7sXIjAmWgq`yEoj~y&#k0 zymblR2sY%X!F&C-%#drX_@bcmW1duN&GK4rALpUgg>fEgy~E&I>ms?-P^HA&ZI1jbH-{4y7=~3S5AGFtXnShfN`#A7SCdiM&9>?LTGsJ2paQ_k(Rhc6% zwRZLn+|BXxI#~0~sl0*{s^Atsb~-?~JqlCkhrNRVW=>z0B0b^?!cEoId8aH>ap_UY zeqY`{Mtj{Z%)FBn*6$tcdHj(vd>PyHkvb!GC2#fh-c@~!?l{^Yb3b(3}!`}8@XzO34Mgc(?8C5S6N z?m3wwJEp9?j$bgn9^kc$n~Q?gX)2e>awAQj$wMiu$ipeb`)(<$$s;MO%cCh=mB&)p zkjGQFCQlH$9zeVB1^r2bmgOmfX7V+IR^(}eR^=Ik*5q3Tt;IZgI45+2Cd4g2Cd0!2Cd8M23?gm4BC)44Z0?8rL?jlZyU5M?~tC* zr_KlKd&8~m_KL{T?uvrPTw0MiVqefsYtLPS%~P0j=^^OO z)P-@rx#M=ME|SmZ>G9WYV?V{;<9GaSS zaI?FPCl;i~9fdpK*Cb~wj4w?V&SakWL@c`1?W57L&N(OOZ4Rt@i{xscUUR^}<(OCv z%n*gtKvFdj_tU(A7KVWqhJnOtpfB1PNI?z67u#SUxf-aKCou5zh=G-0AgLNy$qlqH z474x|Bvu1`(at~$YG5TANUjD}y@6*&46FtNN!7q=ZlHx>poL)|u^Q-$b_P;V1FO+M z@)_Nyaezy3S&8hR#gpmWic(_@bL5eeA}n$Omb*@olUatYZAnm4W6?cv4} zbL73`47i8f_Y%Igxc<0e2(C-6Qt)OWN9dJnlwx77WA3GJyKAP_5?gbhq2>)*k^8B} z;VR4ZaSGdT-9uU!uChEt9*3(e50i4ZM)2rxmF0`fF*aNy+URhV<&p7hdFwVtv^ZR4 zd6YQ{!&R2Y$YT#5l9j=O;rW6aqaN%(ig=Dz!Xv9$S234d=Raf%Nt>o1>Sh|w? z>n6XFAEIC-HL`f}n*PCjM zatgkDw{kVdDMkt_IjJu^U&+aR8E(PqlIrBm4nTD!C)VM{qw~0k^(g7&rKBr4HJ>dX zP^{LJe70QDm7JP4&9CI7c`x~uoZR|wu>8-nYSCn$^#7glmgu`mo5R&ol-aA74k)Vx7h$*IQS!b(0) zVH;L*(!y|IB`1%=g(aJm!!?3OhYPDUbBqnwh&DQ0Sgpsi<*n0|oLU?%tmLGH;lfHz z9(&lYbY{N=US{N>@ zpg7vmdW_6`Iw`)#f0sGW3Z1s z@-yRbA8?Lv#%J$ik6_I0D;l_41*E>B?O{h2$KhbVC#MLHyE1z_!@)jo-o;`g?(Aa| zV8pJry^DIQuV>IQc8sNIGwcqF^j58JXJ_-E-`R1!Gi6G;&vNoG3D-K5j_La*{`Sm+ zv8dw?_V#zW*vL!l(++k!GDA4)(z>gXInoo6YS+$F@I~X!3NCvVh_z^cBXEgO)0Pjs z8Oy{zt(tL~P|eT{`*_ZLhE&b)RLxkS;EVQVREf1{f4i?4;E9VLb8iGpX%6fTbA8et z&!NU_5vnn`+)-n?q-u<(YD|xUFWMV3Bvxbmt-ULRnzjbA*USM1Dhl}rs?oF91kD~T|(^mlsPh&5Vw~x zFUFvITC^|@w>y1VB%IcI@GR{Vk*h^pvlQ9%aee>k0KbchcPgZjhx{C4TgAFernm!q zG{t!LMrKmn2cAta?sUssf?)}^Cnp$|Y{){2JHU6OcmTYZ;y&=n6c2$r@ zBh3WEl8&@f+yUN9@c?)$#eLvUq<9G2O)xCkl3s#g$(9UL+yTCn;sNmG6!(EYnc^Yv zJqaG@Yn5;PmFPRO-lf!Y-zJ?4j&@-ke)===kb1w@mv=~mTekXmj3Z}b(V>t{I2zs% zAZKzs1S2jaFUwJKCdZ>O;zIIFX33cx*KWjxUh-mwvV4X@Awwqjkry*$ z^0z4zGF0S#@?wUH{2dB~3{`o6yqKXXf0sfbLroqeFJ`F8-=h#awY4JGi9)C$?Ni)Ba zc|%?$E+lWre4f0}!viy`nAp>r8 zk{2^%@;@jPGF0R(@?wUH{7(vn3{`oXyqE!}QBWvksL4Cz#SAt1IfdA%9bE5!%(&hM zpCD&)T<;TyYT+s!TwV%v za$N6|GdZsJi3`bby-&{MxZWo&B**nWIg{ghpSX}5*Zbs5j_ZBmLULU1C%lE>!1X>k zr-2H0QV0cU23+rx7c<~`pF$x6uJ_4{8F0N%p^yRB`{cz8xZbBw$bjp8@?r*D?^7sb z!1X?PF$1pmDa20Q!u39JCy-U4|F%@ zS+G?5Btq9G*!--0l0fZ~2wk6`P1+}f-csKuBXp3z2lr}xdIp<7VbkO|!wu3IGL)&g z^^KZ2(<}FYBw6^W(Vh@B*=~3%6Jo$+TR3h}FlQ@YhDHa5SOJX z#KkA!aXc(+9bDMihO@|gesMoFm*dU_I01P~jyJ_-h-2~=_#F8OS4?NSe^DQ2WYC)2XVALbZ_rhFz@QCz(4cE_oz(Xc+J-MdH!O@@dlt^*VGCE} zix#fRBNnd7qZY2qV-{YO$1U8DCoH@sPZ~H|k*6$-?Q|B-Vt;q8hF3SrR#s+B%SL7uNSLJ03*W?uo*X4&6UX@oZ+>qBSye6*``%5HuRj?v& zm>h>fn;d(YO7IvHECEJ7er@GUY4fGapaoGaSzkvRq2|%COwna zWoYtMxlHcAb>KK2T(@Spqj`w3CRc0)7f4qRQE;N#Aqvh^J4C^)&O?-{+<%BtlLrn_ z>hjfnkl!`n`C0upw>wehB#&PG;5cqN8 zWA6KvrhS5NE}XHCgM9FfeU70Za-^TMIBsXnkRQV_{0IGWdSr#fLUM>36e+|FiWK4o zMGA3)B89j?kwV;{NFi=eq!7=*QivyAgtMVV`aH{^cxYu%Jedmgy%(SL+r(ozcnD?W zz>_9};&DH^)&7{8A3m_@Vw+I z>2cr7xQmRfQWnOBC<|lTlZCOl$->yeWMOPnBA!-D-~`vl5a#&}A~&Twy0iQtLYEb< zfjms)(rx!}Z}C(!?}F(WJ>e2BA_~r^3%9O3(=)v$5{9o*W2^)Fjz%`+%Il(z8M1e~ zL%a^$&l=#=V${~}oD&)5MofhS?nfz@V3G-r;kPgjHr>6(>$#azIfN^x5U!j;xH94K zyv$w;$J*wlPR}adKR?vi^L(T(F<$D~0iKJ!H{~#X`=W=9VG9vY=XkfbBa0CqakzJ> zt#=|{O>rB;`s0YFee-(QlK%5n-cv`Mb-jJvh$iinmgN?M;t)22R^$k&H?6&Y9y=W- zEnJo<3ukiF!ULH$@Fot$v2a4{sN1-CH{L%|G|ClS%Qk)-_m+Gt1gG!ePeF2@z>#%AjPdYt|pNcu?4~7_y zn{m1wnZZxRpi!7tH}hGaGdNhn;9m)YdyTO{2fj7NcDC_S71=SZcWZYKPdvupey4L@ zP7yi_+v|7B(ip?L%(6`8O1!&+MxQ1;uGOq}ceM61#B%{V16ES*Y^ajEVsKDr3-2N{ zEZmi|5l`Rhe`e=kqkDd^{mG6@zH_wcC(Lw-lAg|al*(LC*86z0GGp?x%#z<0(&L4m z3xl2Ac1PwY9uK0BP4w;#^g|ggk3z;m~LPhSdg{mytLQPKELS0VT0yYp) z$omS+U0YHN2eY+*W`rj(DAMqMZ$q%t3R5yN|~r`nxS zi{p#m$5rJ_RAN;_9Kfm4M=0f04K|1HPx)w6rt_*U?CKe@&{k5-pC1b?qjq~RG0%tR zA=OmPb3(1BYRG#IY9m!cURCd+n%lcRY#{+`I!i5|lbfA&=~=iVePTZ{8GT6d(``c^ zJIVPF6+bWVyBf}iOb#C+_dcZOr$-;6=D*6zmysF%Xq7r;4JIH+j-;3f@%FW0E>O-ko^r2KO z`ViIJCi)Pyd`>zavM_uo;;9+^DL4FngUHRe)!~?9x>aV9aMr_3oGw2{>a*jDWq~ZF z#3O7{O{qWEflKF+igZg7Dk9YEfUY7^pIs{=iz!hNsiwqE8NCLZXyPBY_rNh%kxVp! z+=ZEkt|FOef+_XcwIZ2lf{dg@MKaL@%TwaGKU6e1(Nv_H98e~9RA`F`)lRp~0$oR{ z6}e3s3uG}RDk44ZemW1wSnGx5OnzxU6*0b2O(qzp{Nmcuz(_r3V6=Fict(Ge&+Q<2 zB){ZC&nUxYqZzU}{YeIF0=h87HI+0cn&<`X2l5RV*PLjA7WqyO>1Ub~P0&$}^mEOL zCTM|gU^Rq&&50&xf#XUQ-)$F~6HU;_F?+l{?TM!1+#bi(o|JogEUxw>JlK=)U{B=J zC(u9D^1&{)W9@Cp#C`eH9}&88)D$jl$*e7OrDO{GTXMTCbma~TIy%m(L4Qvc4c-Ai zY4Ab+lAJPl2mCz-AM|moguy%D?;|he_U!bx&`rxxnJOsVy{?>&%5*{5LPwp6%1E9| z_^GC-jO0OARiiSJXTK|rs7xRCwzYb2kc|}Uc>$X#ZXxwniZ8+WK0zGDp@*&1d-B`N8zC2>^4e;Mc`7UO?JZkbw z@|el@<#F=R_kHcnCy0Yn4ZKr*-4?p?4O75e`KB#&c~iKVN27 zV`fx*%nY@m!>Umk$)hndDn4dnwRJHw#V%&1*u~5gyO>EFMkB<`l>3-za2GRE?qg=k zeatktiX>!C&lOtx5JJ-TjPZu+Zg9qg?(-sgjO#yS|o3?b=a4enwlxr>QvPl%aO@lnhxE?P##N4}6pqh(Y^@@TY-%19oKmQfkWqtP-d zK3d|{0v9b)?4o6gU9?QGi!EmQ8JrNLda zOu3JiCP%b1Iie-GbE-;+mc+rS@@Q!bh?b_H(b5(WElokAr7a*@8iJ3OhTx;6A^2!% z2tHaGf{&Jl;G?A>_-JVeK3W=rkCukuqopDEXlV#OT2crD>!W4FQ*L1Ki&7ojd&W6} ze2iQaGMTdl9Cb-SU90YHePGXtT+hGRyIUXNc(AR{)+~-&3NseR4V$@ypKI-)oOz3* zoCS-coJEV{R@Ets!~P|Usk7&l!uWA6Z=e z$l~fp7FRz?c<>{GJ3lhG^CN>hKT3G;ql5=PN_g<2gaZ%4&W{Z4{Ai5hG7?AA!jB#r^&=d)>ix*#>PHq=KT3G;Ba5pa zSzP_d;_62hS3k12`ccAzA6Z=e$l~fp7FR#AxcZUB)sGS${K(+Wj|}eo$l%V85+3|0 z;lYm*9{ecb!H*Ii{3zkUj}jjIDB;165+3}>;_62!_kLt>=SLP-KQg%UBZE6XBG)Uy zIxZ3Mv#wb1-ukuZNCg3wzHJE3)OVsVt(S=SZLZ*wy}YEH2bUz*8Z^B=jlx!YTfkm> zTfk;}TflC6TflaETflyMTfl~UTflyM3ZdN__}NliG9-M@#=*HrS#H__PAjtoyuM=#Re2>5T52m^PP`Z=M?MKu$YjzM z@PeW(;1xw%z)Om@fY%gl0WT`r0$x>21Q%v7XKev<))p{lZ2@!E7BFXR0dv+CFlTK6 zbC!aev+*)?7>6V9;H%_rn2qJa}xvgU6DG(a1g47T~eA0FSi=cx)o% z9=jK(NIn&U$Jzos))wHgwg8W{1$eA2z+-Iz9-9cc$JzpBt}S5Z+5%>-Enw!_0%oo) zVCLEaW-bLcbK?c?5$R|PY zRa=0s+5&vl7T~M40AIBQ_^K_yR}&%kRa?NEwFS&sTfm&P1HL#S8V~lY76kyM96*hSK{QzCqeL4TY#_H0({jL;H$O( zU$q7Jsx81*6Cw9iTfm&P1WRCOr76!JV%f-1%z4gRdq$_-ev~ zuO>YBDtQ=(+*fS@zG@5bRa=0sCPMD3e?3l)d=dm-wFUU9Ex=c80lsPr@KsxYui659 zH4$=OwFS&sTfm&P1~Li}hm;p`rM0dwfiYL%Dr;hoAU9%oFF9uH|Z^aYL->nkgB7S3ee!ua`4;=D%O z7GE5v?#xzsdCWTZCeS3Qw+`=msdXuK)>#CLd_e6YJ z_xjKzskg4;txK`9&cd+H!my4wuTlGMoVwS8WMQJI#zpJgJ4chG-ny!{F2&9|3&T1K z!#ZMboj>1|^j3df!?{Zvdjq_v1>5GDY9UN41!;Y2LzS6SK>}6gQUx!A>TwhEsp4L2 z9pII$q#h_cgY$STD^dEF2SaQxKXr)G!;vaRo=v=sjrZiEGVj~7b)h%B?6lL=LN_=K zb>WDWm<|25u{k(sZR5B4Nb?MNS#nFv5Ty2YM@76oc9@jO%wZBILd=U z%%T>QWr<46f{Jh?BZV;wa4HYASe#l=mK7?oI9O1YDutLuEx?(%RALrbfU|Wdj9Gx6 z6QCB0QwuWbQHjOr55(hime|)Zi&{{TD^y|@Sbzg=DU4ZAk$b7d;?x2hphYDX2Mcg) z4uzOSEvU-%puBkTPi9>}iWy-?RUTr-F*~aAFtu2y+JPUFe)Z}q0 zF$*lH$&(buEU3v-)M9aJ0S+>x5{rWcHF=ss%%T?5n zYQdVUP>IFC0-U~0A&;dlGUA}BCZ$*!On|aQ<+ei5L;!}^r5H<8BOvuC#S&o!lp&Rv zNjn0+nsbFx%%o=EY&|ODX5c(6im^mzMp^Eo6iZYy%5p!Iuza-LiZ&CcL&Uh?m`t%Q zTQkI=cwL=!b(&9=U9T)q2}@nuEp?0Jp%sp6VW%jC)@wERd2|)46!Ux#ag~G>?^tY1 zK|+sW&7&0NmbR>+2K!`hZgdeJi+tjJ<2c{{M~nUapIoTfBp2i7-gqjq40 zOC@hdSsJP2?ZE11O0Wa#AEhxnu*y*zwFB#1DtSBbllH0P?Z6snO0WZ~Af+)ou+~u< zwF9eNDtS99@<1wiJFpU(670Y#NNLOttaa2z?Z9f6O5TpDJeo@04y=Tx1Us-6QW~=Z zD;~8`JFw=ZlDDHK&!iGO)BDTu#9tu64)_bD+zv<@W#BK=ayy`Te=#Lg2B$D3R0gM@ zG*%g$g4$?ha0*jGWtjPlVri98cy(x`VhUrahv@%R@ zQ$l5!!={AFFo!9PRfaiCZL~7XVN*h7n5d?N$}mwWja7z;N^P_ + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Peripheral Interrupts + DCD IRQ000_Handler + DCD IRQ001_Handler + DCD IRQ002_Handler + DCD IRQ003_Handler + DCD IRQ004_Handler + DCD IRQ005_Handler + DCD IRQ006_Handler + DCD IRQ007_Handler + DCD IRQ008_Handler + DCD IRQ009_Handler + DCD IRQ010_Handler + DCD IRQ011_Handler + DCD IRQ012_Handler + DCD IRQ013_Handler + DCD IRQ014_Handler + DCD IRQ015_Handler + DCD IRQ016_Handler + DCD IRQ017_Handler + DCD IRQ018_Handler + DCD IRQ019_Handler + DCD IRQ020_Handler + DCD IRQ021_Handler + DCD IRQ022_Handler + DCD IRQ023_Handler + DCD IRQ024_Handler + DCD IRQ025_Handler + DCD IRQ026_Handler + DCD IRQ027_Handler + DCD IRQ028_Handler + DCD IRQ029_Handler + DCD IRQ030_Handler + DCD IRQ031_Handler + DCD IRQ032_Handler + DCD IRQ033_Handler + DCD IRQ034_Handler + DCD IRQ035_Handler + DCD IRQ036_Handler + DCD IRQ037_Handler + DCD IRQ038_Handler + DCD IRQ039_Handler + DCD IRQ040_Handler + DCD IRQ041_Handler + DCD IRQ042_Handler + DCD IRQ043_Handler + DCD IRQ044_Handler + DCD IRQ045_Handler + DCD IRQ046_Handler + DCD IRQ047_Handler + DCD IRQ048_Handler + DCD IRQ049_Handler + DCD IRQ050_Handler + DCD IRQ051_Handler + DCD IRQ052_Handler + DCD IRQ053_Handler + DCD IRQ054_Handler + DCD IRQ055_Handler + DCD IRQ056_Handler + DCD IRQ057_Handler + DCD IRQ058_Handler + DCD IRQ059_Handler + DCD IRQ060_Handler + DCD IRQ061_Handler + DCD IRQ062_Handler + DCD IRQ063_Handler + DCD IRQ064_Handler + DCD IRQ065_Handler + DCD IRQ066_Handler + DCD IRQ067_Handler + DCD IRQ068_Handler + DCD IRQ069_Handler + DCD IRQ070_Handler + DCD IRQ071_Handler + DCD IRQ072_Handler + DCD IRQ073_Handler + DCD IRQ074_Handler + DCD IRQ075_Handler + DCD IRQ076_Handler + DCD IRQ077_Handler + DCD IRQ078_Handler + DCD IRQ079_Handler + DCD IRQ080_Handler + DCD IRQ081_Handler + DCD IRQ082_Handler + DCD IRQ083_Handler + DCD IRQ084_Handler + DCD IRQ085_Handler + DCD IRQ086_Handler + DCD IRQ087_Handler + DCD IRQ088_Handler + DCD IRQ089_Handler + DCD IRQ090_Handler + DCD IRQ091_Handler + DCD IRQ092_Handler + DCD IRQ093_Handler + DCD IRQ094_Handler + DCD IRQ095_Handler + DCD IRQ096_Handler + DCD IRQ097_Handler + DCD IRQ098_Handler + DCD IRQ099_Handler + DCD IRQ100_Handler + DCD IRQ101_Handler + DCD IRQ102_Handler + DCD IRQ103_Handler + DCD IRQ104_Handler + DCD IRQ105_Handler + DCD IRQ106_Handler + DCD IRQ107_Handler + DCD IRQ108_Handler + DCD IRQ109_Handler + DCD IRQ110_Handler + DCD IRQ111_Handler + DCD IRQ112_Handler + DCD IRQ113_Handler + DCD IRQ114_Handler + DCD IRQ115_Handler + DCD IRQ116_Handler + DCD IRQ117_Handler + DCD IRQ118_Handler + DCD IRQ119_Handler + DCD IRQ120_Handler + DCD IRQ121_Handler + DCD IRQ122_Handler + DCD IRQ123_Handler + DCD IRQ124_Handler + DCD IRQ125_Handler + DCD IRQ126_Handler + DCD IRQ127_Handler + DCD IRQ128_Handler + DCD IRQ129_Handler + DCD IRQ130_Handler + DCD IRQ131_Handler + DCD IRQ132_Handler + DCD IRQ133_Handler + DCD IRQ134_Handler + DCD IRQ135_Handler + DCD IRQ136_Handler + DCD IRQ137_Handler + DCD IRQ138_Handler + DCD IRQ139_Handler + DCD IRQ140_Handler + DCD IRQ141_Handler + DCD IRQ142_Handler + DCD IRQ143_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main +SET_SRAM3_WAIT + LDR R0, =0x40050804 + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x40050800 + MOV R1, #0x1100 + STR R1, [R0] + + LDR R0, =0x40050804 + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT IRQ000_Handler [WEAK] + EXPORT IRQ001_Handler [WEAK] + EXPORT IRQ002_Handler [WEAK] + EXPORT IRQ003_Handler [WEAK] + EXPORT IRQ004_Handler [WEAK] + EXPORT IRQ005_Handler [WEAK] + EXPORT IRQ006_Handler [WEAK] + EXPORT IRQ007_Handler [WEAK] + EXPORT IRQ008_Handler [WEAK] + EXPORT IRQ009_Handler [WEAK] + EXPORT IRQ010_Handler [WEAK] + EXPORT IRQ011_Handler [WEAK] + EXPORT IRQ012_Handler [WEAK] + EXPORT IRQ013_Handler [WEAK] + EXPORT IRQ014_Handler [WEAK] + EXPORT IRQ015_Handler [WEAK] + EXPORT IRQ016_Handler [WEAK] + EXPORT IRQ017_Handler [WEAK] + EXPORT IRQ018_Handler [WEAK] + EXPORT IRQ019_Handler [WEAK] + EXPORT IRQ020_Handler [WEAK] + EXPORT IRQ021_Handler [WEAK] + EXPORT IRQ022_Handler [WEAK] + EXPORT IRQ023_Handler [WEAK] + EXPORT IRQ024_Handler [WEAK] + EXPORT IRQ025_Handler [WEAK] + EXPORT IRQ026_Handler [WEAK] + EXPORT IRQ027_Handler [WEAK] + EXPORT IRQ028_Handler [WEAK] + EXPORT IRQ029_Handler [WEAK] + EXPORT IRQ030_Handler [WEAK] + EXPORT IRQ031_Handler [WEAK] + EXPORT IRQ032_Handler [WEAK] + EXPORT IRQ033_Handler [WEAK] + EXPORT IRQ034_Handler [WEAK] + EXPORT IRQ035_Handler [WEAK] + EXPORT IRQ036_Handler [WEAK] + EXPORT IRQ037_Handler [WEAK] + EXPORT IRQ038_Handler [WEAK] + EXPORT IRQ039_Handler [WEAK] + EXPORT IRQ040_Handler [WEAK] + EXPORT IRQ041_Handler [WEAK] + EXPORT IRQ042_Handler [WEAK] + EXPORT IRQ043_Handler [WEAK] + EXPORT IRQ044_Handler [WEAK] + EXPORT IRQ045_Handler [WEAK] + EXPORT IRQ046_Handler [WEAK] + EXPORT IRQ047_Handler [WEAK] + EXPORT IRQ048_Handler [WEAK] + EXPORT IRQ049_Handler [WEAK] + EXPORT IRQ050_Handler [WEAK] + EXPORT IRQ051_Handler [WEAK] + EXPORT IRQ052_Handler [WEAK] + EXPORT IRQ053_Handler [WEAK] + EXPORT IRQ054_Handler [WEAK] + EXPORT IRQ055_Handler [WEAK] + EXPORT IRQ056_Handler [WEAK] + EXPORT IRQ057_Handler [WEAK] + EXPORT IRQ058_Handler [WEAK] + EXPORT IRQ059_Handler [WEAK] + EXPORT IRQ060_Handler [WEAK] + EXPORT IRQ061_Handler [WEAK] + EXPORT IRQ062_Handler [WEAK] + EXPORT IRQ063_Handler [WEAK] + EXPORT IRQ064_Handler [WEAK] + EXPORT IRQ065_Handler [WEAK] + EXPORT IRQ066_Handler [WEAK] + EXPORT IRQ067_Handler [WEAK] + EXPORT IRQ068_Handler [WEAK] + EXPORT IRQ069_Handler [WEAK] + EXPORT IRQ070_Handler [WEAK] + EXPORT IRQ071_Handler [WEAK] + EXPORT IRQ072_Handler [WEAK] + EXPORT IRQ073_Handler [WEAK] + EXPORT IRQ074_Handler [WEAK] + EXPORT IRQ075_Handler [WEAK] + EXPORT IRQ076_Handler [WEAK] + EXPORT IRQ077_Handler [WEAK] + EXPORT IRQ078_Handler [WEAK] + EXPORT IRQ079_Handler [WEAK] + EXPORT IRQ080_Handler [WEAK] + EXPORT IRQ081_Handler [WEAK] + EXPORT IRQ082_Handler [WEAK] + EXPORT IRQ083_Handler [WEAK] + EXPORT IRQ084_Handler [WEAK] + EXPORT IRQ085_Handler [WEAK] + EXPORT IRQ086_Handler [WEAK] + EXPORT IRQ087_Handler [WEAK] + EXPORT IRQ088_Handler [WEAK] + EXPORT IRQ089_Handler [WEAK] + EXPORT IRQ090_Handler [WEAK] + EXPORT IRQ091_Handler [WEAK] + EXPORT IRQ092_Handler [WEAK] + EXPORT IRQ093_Handler [WEAK] + EXPORT IRQ094_Handler [WEAK] + EXPORT IRQ095_Handler [WEAK] + EXPORT IRQ096_Handler [WEAK] + EXPORT IRQ097_Handler [WEAK] + EXPORT IRQ098_Handler [WEAK] + EXPORT IRQ099_Handler [WEAK] + EXPORT IRQ100_Handler [WEAK] + EXPORT IRQ101_Handler [WEAK] + EXPORT IRQ102_Handler [WEAK] + EXPORT IRQ103_Handler [WEAK] + EXPORT IRQ104_Handler [WEAK] + EXPORT IRQ105_Handler [WEAK] + EXPORT IRQ106_Handler [WEAK] + EXPORT IRQ107_Handler [WEAK] + EXPORT IRQ108_Handler [WEAK] + EXPORT IRQ109_Handler [WEAK] + EXPORT IRQ110_Handler [WEAK] + EXPORT IRQ111_Handler [WEAK] + EXPORT IRQ112_Handler [WEAK] + EXPORT IRQ113_Handler [WEAK] + EXPORT IRQ114_Handler [WEAK] + EXPORT IRQ115_Handler [WEAK] + EXPORT IRQ116_Handler [WEAK] + EXPORT IRQ117_Handler [WEAK] + EXPORT IRQ118_Handler [WEAK] + EXPORT IRQ119_Handler [WEAK] + EXPORT IRQ120_Handler [WEAK] + EXPORT IRQ121_Handler [WEAK] + EXPORT IRQ122_Handler [WEAK] + EXPORT IRQ123_Handler [WEAK] + EXPORT IRQ124_Handler [WEAK] + EXPORT IRQ125_Handler [WEAK] + EXPORT IRQ126_Handler [WEAK] + EXPORT IRQ127_Handler [WEAK] + EXPORT IRQ128_Handler [WEAK] + EXPORT IRQ129_Handler [WEAK] + EXPORT IRQ130_Handler [WEAK] + EXPORT IRQ131_Handler [WEAK] + EXPORT IRQ132_Handler [WEAK] + EXPORT IRQ133_Handler [WEAK] + EXPORT IRQ134_Handler [WEAK] + EXPORT IRQ135_Handler [WEAK] + EXPORT IRQ136_Handler [WEAK] + EXPORT IRQ137_Handler [WEAK] + EXPORT IRQ138_Handler [WEAK] + EXPORT IRQ139_Handler [WEAK] + EXPORT IRQ140_Handler [WEAK] + EXPORT IRQ141_Handler [WEAK] + EXPORT IRQ142_Handler [WEAK] + EXPORT IRQ143_Handler [WEAK] + +IRQ000_Handler +IRQ001_Handler +IRQ002_Handler +IRQ003_Handler +IRQ004_Handler +IRQ005_Handler +IRQ006_Handler +IRQ007_Handler +IRQ008_Handler +IRQ009_Handler +IRQ010_Handler +IRQ011_Handler +IRQ012_Handler +IRQ013_Handler +IRQ014_Handler +IRQ015_Handler +IRQ016_Handler +IRQ017_Handler +IRQ018_Handler +IRQ019_Handler +IRQ020_Handler +IRQ021_Handler +IRQ022_Handler +IRQ023_Handler +IRQ024_Handler +IRQ025_Handler +IRQ026_Handler +IRQ027_Handler +IRQ028_Handler +IRQ029_Handler +IRQ030_Handler +IRQ031_Handler +IRQ032_Handler +IRQ033_Handler +IRQ034_Handler +IRQ035_Handler +IRQ036_Handler +IRQ037_Handler +IRQ038_Handler +IRQ039_Handler +IRQ040_Handler +IRQ041_Handler +IRQ042_Handler +IRQ043_Handler +IRQ044_Handler +IRQ045_Handler +IRQ046_Handler +IRQ047_Handler +IRQ048_Handler +IRQ049_Handler +IRQ050_Handler +IRQ051_Handler +IRQ052_Handler +IRQ053_Handler +IRQ054_Handler +IRQ055_Handler +IRQ056_Handler +IRQ057_Handler +IRQ058_Handler +IRQ059_Handler +IRQ060_Handler +IRQ061_Handler +IRQ062_Handler +IRQ063_Handler +IRQ064_Handler +IRQ065_Handler +IRQ066_Handler +IRQ067_Handler +IRQ068_Handler +IRQ069_Handler +IRQ070_Handler +IRQ071_Handler +IRQ072_Handler +IRQ073_Handler +IRQ074_Handler +IRQ075_Handler +IRQ076_Handler +IRQ077_Handler +IRQ078_Handler +IRQ079_Handler +IRQ080_Handler +IRQ081_Handler +IRQ082_Handler +IRQ083_Handler +IRQ084_Handler +IRQ085_Handler +IRQ086_Handler +IRQ087_Handler +IRQ088_Handler +IRQ089_Handler +IRQ090_Handler +IRQ091_Handler +IRQ092_Handler +IRQ093_Handler +IRQ094_Handler +IRQ095_Handler +IRQ096_Handler +IRQ097_Handler +IRQ098_Handler +IRQ099_Handler +IRQ100_Handler +IRQ101_Handler +IRQ102_Handler +IRQ103_Handler +IRQ104_Handler +IRQ105_Handler +IRQ106_Handler +IRQ107_Handler +IRQ108_Handler +IRQ109_Handler +IRQ110_Handler +IRQ111_Handler +IRQ112_Handler +IRQ113_Handler +IRQ114_Handler +IRQ115_Handler +IRQ116_Handler +IRQ117_Handler +IRQ118_Handler +IRQ119_Handler +IRQ120_Handler +IRQ121_Handler +IRQ122_Handler +IRQ123_Handler +IRQ124_Handler +IRQ125_Handler +IRQ126_Handler +IRQ127_Handler +IRQ128_Handler +IRQ129_Handler +IRQ130_Handler +IRQ131_Handler +IRQ132_Handler +IRQ133_Handler +IRQ134_Handler +IRQ135_Handler +IRQ136_Handler +IRQ137_Handler +IRQ138_Handler +IRQ139_Handler +IRQ140_Handler +IRQ141_Handler +IRQ142_Handler +IRQ143_Handler + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F460xC.ld b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F460xC.ld new file mode 100644 index 0000000000..e1d87f9002 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F460xC.ld @@ -0,0 +1,208 @@ +/****************************************************************************** + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F460xC.ld */ +/* Abstract Linker script for HC32F460 Device with */ +/* 256KByte FLASH, 192KByte RAM */ +/* Version V1.0 */ +/* Date 2022-03-31 */ +/*****************************************************************************/ + +/* Custom defines, according to section 7.7 of the user manual. + Take OTP sector 0 for example. */ +__OTP_DATA_START = 0x03000C00; +__OTP_DATA_SIZE = 64; +__OTP_LOCK_START = 0x03000FC0; +__OTP_LOCK_SIZE = 4; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 256K + OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE + OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE + RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 188K + RET_RAM (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data_sec : + { + KEEP(*(.otp_data_sec)) + } >OTP_DATA + + .otp_lock_sec : + { + KEEP(*(.otp_lock_sec)) + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4); + .ret_ram_data : AT (__etext_ret_ram) + { + . = ALIGN(4); + __data_start_ret_ram__ = .; + *(.ret_ram_data) + *(.ret_ram_data*) + . = ALIGN(4); + __data_end_ret_ram__ = .; + } >RET_RAM + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + + .ret_ram_bss : + { + . = ALIGN(4); + __bss_start_ret_ram__ = .; + *(.ret_ram_bss) + *(.ret_ram_bss*) + . = ALIGN(4); + __bss_end_ret_ram__ = .; + } >RET_RAM + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F460xE.ld b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F460xE.ld new file mode 100644 index 0000000000..e782491c53 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F460xE.ld @@ -0,0 +1,208 @@ +/****************************************************************************** + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F460xE.ld */ +/* Abstract Linker script for HC32F460 Device with */ +/* 512KByte FLASH, 192KByte RAM */ +/* Version V1.0 */ +/* Date 2022-03-31 */ +/*****************************************************************************/ + +/* Custom defines, according to section 7.7 of the user manual. + Take OTP sector 0 for example. */ +__OTP_DATA_START = 0x03000C00; +__OTP_DATA_SIZE = 64; +__OTP_LOCK_START = 0x03000FC0; +__OTP_LOCK_SIZE = 4; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 512K + OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE + OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE + RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 188K + RET_RAM (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data_sec : + { + KEEP(*(.otp_data_sec)) + } >OTP_DATA + + .otp_lock_sec : + { + KEEP(*(.otp_lock_sec)) + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4); + .ret_ram_data : AT (__etext_ret_ram) + { + . = ALIGN(4); + __data_start_ret_ram__ = .; + *(.ret_ram_data) + *(.ret_ram_data*) + . = ALIGN(4); + __data_end_ret_ram__ = .; + } >RET_RAM + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + + .ret_ram_bss : + { + . = ALIGN(4); + __bss_start_ret_ram__ = .; + *(.ret_ram_bss) + *(.ret_ram_bss*) + . = ALIGN(4); + __bss_end_ret_ram__ = .; + } >RET_RAM + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f460.S b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f460.S new file mode 100644 index 0000000000..c9f1c9ca1d --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f460.S @@ -0,0 +1,534 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +/*****************************************************************************/ +/* Startup for GCC */ +/* Version V1.0 */ +/* Date 2022-03-31 */ +/* Target-mcu HC32F460 */ +/*****************************************************************************/ + +/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + .syntax unified + .arch armv7e-m + .cpu cortex-m4 + .fpu softvfp + .thumb + +/* +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +*/ + .equ Stack_Size, 0x00002000 + + .section .stack + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +*/ + .equ Heap_Size, 0x00002000 + + .if Heap_Size != 0 /* Heap is provided */ + .section .heap + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + .endif + +/* +; Interrupt vector table start. +*/ + .section .vectors, "a", %progbits + .align 2 + .type __Vectors, %object + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* -14 NMI Handler */ + .long HardFault_Handler /* -13 Hard Fault Handler */ + .long MemManage_Handler /* -12 MPU Fault Handler */ + .long BusFault_Handler /* -11 Bus Fault Handler */ + .long UsageFault_Handler /* -10 Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* -5 SVCall Handler */ + .long DebugMon_Handler /* -4 Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* -2 PendSV Handler */ + .long SysTick_Handler /* -1 SysTick Handler */ + + /* Interrupts */ + .long IRQ000_Handler + .long IRQ001_Handler + .long IRQ002_Handler + .long IRQ003_Handler + .long IRQ004_Handler + .long IRQ005_Handler + .long IRQ006_Handler + .long IRQ007_Handler + .long IRQ008_Handler + .long IRQ009_Handler + .long IRQ010_Handler + .long IRQ011_Handler + .long IRQ012_Handler + .long IRQ013_Handler + .long IRQ014_Handler + .long IRQ015_Handler + .long IRQ016_Handler + .long IRQ017_Handler + .long IRQ018_Handler + .long IRQ019_Handler + .long IRQ020_Handler + .long IRQ021_Handler + .long IRQ022_Handler + .long IRQ023_Handler + .long IRQ024_Handler + .long IRQ025_Handler + .long IRQ026_Handler + .long IRQ027_Handler + .long IRQ028_Handler + .long IRQ029_Handler + .long IRQ030_Handler + .long IRQ031_Handler + .long IRQ032_Handler + .long IRQ033_Handler + .long IRQ034_Handler + .long IRQ035_Handler + .long IRQ036_Handler + .long IRQ037_Handler + .long IRQ038_Handler + .long IRQ039_Handler + .long IRQ040_Handler + .long IRQ041_Handler + .long IRQ042_Handler + .long IRQ043_Handler + .long IRQ044_Handler + .long IRQ045_Handler + .long IRQ046_Handler + .long IRQ047_Handler + .long IRQ048_Handler + .long IRQ049_Handler + .long IRQ050_Handler + .long IRQ051_Handler + .long IRQ052_Handler + .long IRQ053_Handler + .long IRQ054_Handler + .long IRQ055_Handler + .long IRQ056_Handler + .long IRQ057_Handler + .long IRQ058_Handler + .long IRQ059_Handler + .long IRQ060_Handler + .long IRQ061_Handler + .long IRQ062_Handler + .long IRQ063_Handler + .long IRQ064_Handler + .long IRQ065_Handler + .long IRQ066_Handler + .long IRQ067_Handler + .long IRQ068_Handler + .long IRQ069_Handler + .long IRQ070_Handler + .long IRQ071_Handler + .long IRQ072_Handler + .long IRQ073_Handler + .long IRQ074_Handler + .long IRQ075_Handler + .long IRQ076_Handler + .long IRQ077_Handler + .long IRQ078_Handler + .long IRQ079_Handler + .long IRQ080_Handler + .long IRQ081_Handler + .long IRQ082_Handler + .long IRQ083_Handler + .long IRQ084_Handler + .long IRQ085_Handler + .long IRQ086_Handler + .long IRQ087_Handler + .long IRQ088_Handler + .long IRQ089_Handler + .long IRQ090_Handler + .long IRQ091_Handler + .long IRQ092_Handler + .long IRQ093_Handler + .long IRQ094_Handler + .long IRQ095_Handler + .long IRQ096_Handler + .long IRQ097_Handler + .long IRQ098_Handler + .long IRQ099_Handler + .long IRQ100_Handler + .long IRQ101_Handler + .long IRQ102_Handler + .long IRQ103_Handler + .long IRQ104_Handler + .long IRQ105_Handler + .long IRQ106_Handler + .long IRQ107_Handler + .long IRQ108_Handler + .long IRQ109_Handler + .long IRQ110_Handler + .long IRQ111_Handler + .long IRQ112_Handler + .long IRQ113_Handler + .long IRQ114_Handler + .long IRQ115_Handler + .long IRQ116_Handler + .long IRQ117_Handler + .long IRQ118_Handler + .long IRQ119_Handler + .long IRQ120_Handler + .long IRQ121_Handler + .long IRQ122_Handler + .long IRQ123_Handler + .long IRQ124_Handler + .long IRQ125_Handler + .long IRQ126_Handler + .long IRQ127_Handler + .long IRQ128_Handler + .long IRQ129_Handler + .long IRQ130_Handler + .long IRQ131_Handler + .long IRQ132_Handler + .long IRQ133_Handler + .long IRQ134_Handler + .long IRQ135_Handler + .long IRQ136_Handler + .long IRQ137_Handler + .long IRQ138_Handler + .long IRQ139_Handler + .long IRQ140_Handler + .long IRQ141_Handler + .long IRQ142_Handler + .long IRQ143_Handler +__Vectors_End: + .equ __Vectors_Size, __Vectors_End - __Vectors + .size __Vectors, . - __Vectors +/* +; Interrupt vector table end. +*/ + +/* +; Reset handler start. +*/ + .section .text.Reset_Handler + .align 2 + .weak Reset_Handler + .type Reset_Handler, %function + .globl Reset_Handler +Reset_Handler: +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + /* Copy data from read only memory to RAM. */ +CopyData: + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ +CopyLoop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt CopyLoop + +CopyData1: + ldr r1, =__etext_ret_ram + ldr r2, =__data_start_ret_ram__ + ldr r3, =__data_end_ret_ram__ +CopyLoop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt CopyLoop1 + +/* This part of work usually is done in C library startup code. + * Otherwise, define this macro to enable it in this startup. + * + * There are two schemes too. + * One can clear multiple BSS sections. Another can only clear one section. + * The former is more size expensive than the latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + /* Clear BSS section. */ +ClearBss: + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +ClearLoop: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt ClearLoop + +ClearBss1: + ldr r1, =__bss_start_ret_ram__ + ldr r2, =__bss_end_ret_ram__ + + movs r0, 0 +ClearLoop1: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt ClearLoop1 + +SetSRAM3Wait: + ldr r0, =0x40050804 + mov r1, #0x77 + str r1, [r0] + + ldr r0, =0x4005080C + mov r1, #0x77 + str r1, [r0] + + ldr r0, =0x40050800 + mov r1, #0x1100 + str r1, [r0] + + ldr r0, =0x40050804 + mov r1, #0x76 + str r1, [r0] + + ldr r0, =0x4005080C + mov r1, #0x76 + str r1, [r0] + + /* Call the clock system initialization function. */ + bl SystemInit + /* Call the application's entry point. */ + bl entry + bx lr + .size Reset_Handler, . - Reset_Handler +/* +; Reset handler end. +*/ + +/* +; Default handler start. +*/ + .section .text.Default_Handler, "ax", %progbits + .align 2 +Default_Handler: + b . + .size Default_Handler, . - Default_Handler +/* +; Default handler end. +*/ + +/* Macro to define default exception/interrupt handlers. + * Default handler are weak symbols with an endless loop. + * They can be overwritten by real handlers. + */ + .macro Set_Default_Handler Handler_Name + .weak \Handler_Name + .set \Handler_Name, Default_Handler + .endm + +/* Default exception/interrupt handler */ + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler IRQ000_Handler + Set_Default_Handler IRQ001_Handler + Set_Default_Handler IRQ002_Handler + Set_Default_Handler IRQ003_Handler + Set_Default_Handler IRQ004_Handler + Set_Default_Handler IRQ005_Handler + Set_Default_Handler IRQ006_Handler + Set_Default_Handler IRQ007_Handler + Set_Default_Handler IRQ008_Handler + Set_Default_Handler IRQ009_Handler + Set_Default_Handler IRQ010_Handler + Set_Default_Handler IRQ011_Handler + Set_Default_Handler IRQ012_Handler + Set_Default_Handler IRQ013_Handler + Set_Default_Handler IRQ014_Handler + Set_Default_Handler IRQ015_Handler + Set_Default_Handler IRQ016_Handler + Set_Default_Handler IRQ017_Handler + Set_Default_Handler IRQ018_Handler + Set_Default_Handler IRQ019_Handler + Set_Default_Handler IRQ020_Handler + Set_Default_Handler IRQ021_Handler + Set_Default_Handler IRQ022_Handler + Set_Default_Handler IRQ023_Handler + Set_Default_Handler IRQ024_Handler + Set_Default_Handler IRQ025_Handler + Set_Default_Handler IRQ026_Handler + Set_Default_Handler IRQ027_Handler + Set_Default_Handler IRQ028_Handler + Set_Default_Handler IRQ029_Handler + Set_Default_Handler IRQ030_Handler + Set_Default_Handler IRQ031_Handler + Set_Default_Handler IRQ032_Handler + Set_Default_Handler IRQ033_Handler + Set_Default_Handler IRQ034_Handler + Set_Default_Handler IRQ035_Handler + Set_Default_Handler IRQ036_Handler + Set_Default_Handler IRQ037_Handler + Set_Default_Handler IRQ038_Handler + Set_Default_Handler IRQ039_Handler + Set_Default_Handler IRQ040_Handler + Set_Default_Handler IRQ041_Handler + Set_Default_Handler IRQ042_Handler + Set_Default_Handler IRQ043_Handler + Set_Default_Handler IRQ044_Handler + Set_Default_Handler IRQ045_Handler + Set_Default_Handler IRQ046_Handler + Set_Default_Handler IRQ047_Handler + Set_Default_Handler IRQ048_Handler + Set_Default_Handler IRQ049_Handler + Set_Default_Handler IRQ050_Handler + Set_Default_Handler IRQ051_Handler + Set_Default_Handler IRQ052_Handler + Set_Default_Handler IRQ053_Handler + Set_Default_Handler IRQ054_Handler + Set_Default_Handler IRQ055_Handler + Set_Default_Handler IRQ056_Handler + Set_Default_Handler IRQ057_Handler + Set_Default_Handler IRQ058_Handler + Set_Default_Handler IRQ059_Handler + Set_Default_Handler IRQ060_Handler + Set_Default_Handler IRQ061_Handler + Set_Default_Handler IRQ062_Handler + Set_Default_Handler IRQ063_Handler + Set_Default_Handler IRQ064_Handler + Set_Default_Handler IRQ065_Handler + Set_Default_Handler IRQ066_Handler + Set_Default_Handler IRQ067_Handler + Set_Default_Handler IRQ068_Handler + Set_Default_Handler IRQ069_Handler + Set_Default_Handler IRQ070_Handler + Set_Default_Handler IRQ071_Handler + Set_Default_Handler IRQ072_Handler + Set_Default_Handler IRQ073_Handler + Set_Default_Handler IRQ074_Handler + Set_Default_Handler IRQ075_Handler + Set_Default_Handler IRQ076_Handler + Set_Default_Handler IRQ077_Handler + Set_Default_Handler IRQ078_Handler + Set_Default_Handler IRQ079_Handler + Set_Default_Handler IRQ080_Handler + Set_Default_Handler IRQ081_Handler + Set_Default_Handler IRQ082_Handler + Set_Default_Handler IRQ083_Handler + Set_Default_Handler IRQ084_Handler + Set_Default_Handler IRQ085_Handler + Set_Default_Handler IRQ086_Handler + Set_Default_Handler IRQ087_Handler + Set_Default_Handler IRQ088_Handler + Set_Default_Handler IRQ089_Handler + Set_Default_Handler IRQ090_Handler + Set_Default_Handler IRQ091_Handler + Set_Default_Handler IRQ092_Handler + Set_Default_Handler IRQ093_Handler + Set_Default_Handler IRQ094_Handler + Set_Default_Handler IRQ095_Handler + Set_Default_Handler IRQ096_Handler + Set_Default_Handler IRQ097_Handler + Set_Default_Handler IRQ098_Handler + Set_Default_Handler IRQ099_Handler + Set_Default_Handler IRQ100_Handler + Set_Default_Handler IRQ101_Handler + Set_Default_Handler IRQ102_Handler + Set_Default_Handler IRQ103_Handler + Set_Default_Handler IRQ104_Handler + Set_Default_Handler IRQ105_Handler + Set_Default_Handler IRQ106_Handler + Set_Default_Handler IRQ107_Handler + Set_Default_Handler IRQ108_Handler + Set_Default_Handler IRQ109_Handler + Set_Default_Handler IRQ110_Handler + Set_Default_Handler IRQ111_Handler + Set_Default_Handler IRQ112_Handler + Set_Default_Handler IRQ113_Handler + Set_Default_Handler IRQ114_Handler + Set_Default_Handler IRQ115_Handler + Set_Default_Handler IRQ116_Handler + Set_Default_Handler IRQ117_Handler + Set_Default_Handler IRQ118_Handler + Set_Default_Handler IRQ119_Handler + Set_Default_Handler IRQ120_Handler + Set_Default_Handler IRQ121_Handler + Set_Default_Handler IRQ122_Handler + Set_Default_Handler IRQ123_Handler + Set_Default_Handler IRQ124_Handler + Set_Default_Handler IRQ125_Handler + Set_Default_Handler IRQ126_Handler + Set_Default_Handler IRQ127_Handler + Set_Default_Handler IRQ128_Handler + Set_Default_Handler IRQ129_Handler + Set_Default_Handler IRQ130_Handler + Set_Default_Handler IRQ131_Handler + Set_Default_Handler IRQ132_Handler + Set_Default_Handler IRQ133_Handler + Set_Default_Handler IRQ134_Handler + Set_Default_Handler IRQ135_Handler + Set_Default_Handler IRQ136_Handler + Set_Default_Handler IRQ137_Handler + Set_Default_Handler IRQ138_Handler + Set_Default_Handler IRQ139_Handler + Set_Default_Handler IRQ140_Handler + Set_Default_Handler IRQ141_Handler + Set_Default_Handler IRQ142_Handler + Set_Default_Handler IRQ143_Handler + + .end diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HDSC_HC32F460.svd b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HDSC_HC32F460.svd new file mode 100644 index 0000000000..03dbb3b098 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HDSC_HC32F460.svd @@ -0,0 +1,53428 @@ + + + HDSC + HDSC + HDSC_HC32F460 + ARMCM4 + 1.0 + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 32 + read-write + 0x0 + 0x0 + + + ADC1 + desc ADC + 0x40040000 + + 0x0 + 0xD0 + + + + STR + desc STR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + STRT + desc STRT + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x2 + 16 + read-write + 0x0 + 0x7F3 + + + MS + desc MS + 1 + 0 + read-write + + + ACCSEL + desc ACCSEL + 5 + 4 + read-write + + + CLREN + desc CLREN + 6 + 6 + read-write + + + DFMT + desc DFMT + 7 + 7 + read-write + + + AVCNT + desc AVCNT + 10 + 8 + read-write + + + + + CR1 + desc CR1 + 0x4 + 16 + read-write + 0x0 + 0x4 + + + RSCHSEL + desc RSCHSEL + 2 + 2 + read-write + + + + + TRGSR + desc TRGSR + 0xA + 16 + read-write + 0x0 + 0x8383 + + + TRGSELA + desc TRGSELA + 1 + 0 + read-write + + + TRGENA + desc TRGENA + 7 + 7 + read-write + + + TRGSELB + desc TRGSELB + 9 + 8 + read-write + + + TRGENB + desc TRGENB + 15 + 15 + read-write + + + + + CHSELRA + desc CHSELRA + 0xC + 32 + read-write + 0x0 + 0x1FFFF + + + CHSELA + desc CHSELA + 16 + 0 + read-write + + + + + CHSELRB + desc CHSELRB + 0x10 + 32 + read-write + 0x0 + 0x1FFFF + + + CHSELB + desc CHSELB + 16 + 0 + read-write + + + + + AVCHSELR + desc AVCHSELR + 0x14 + 32 + read-write + 0x0 + 0x1FFFF + + + AVCHSEL + desc AVCHSEL + 16 + 0 + read-write + + + + + SSTR0 + desc SSTR0 + 0x20 + 8 + read-write + 0xB + 0xFF + + + SSTR1 + desc SSTR1 + 0x21 + 8 + read-write + 0xB + 0xFF + + + SSTR2 + desc SSTR2 + 0x22 + 8 + read-write + 0xB + 0xFF + + + SSTR3 + desc SSTR3 + 0x23 + 8 + read-write + 0xB + 0xFF + + + SSTR4 + desc SSTR4 + 0x24 + 8 + read-write + 0xB + 0xFF + + + SSTR5 + desc SSTR5 + 0x25 + 8 + read-write + 0xB + 0xFF + + + SSTR6 + desc SSTR6 + 0x26 + 8 + read-write + 0xB + 0xFF + + + SSTR7 + desc SSTR7 + 0x27 + 8 + read-write + 0xB + 0xFF + + + SSTR8 + desc SSTR8 + 0x28 + 8 + read-write + 0xB + 0xFF + + + SSTR9 + desc SSTR9 + 0x29 + 8 + read-write + 0xB + 0xFF + + + SSTR10 + desc SSTR10 + 0x2A + 8 + read-write + 0xB + 0xFF + + + SSTR11 + desc SSTR11 + 0x2B + 8 + read-write + 0xB + 0xFF + + + SSTR12 + desc SSTR12 + 0x2C + 8 + read-write + 0xB + 0xFF + + + SSTR13 + desc SSTR13 + 0x2D + 8 + read-write + 0xB + 0xFF + + + SSTR14 + desc SSTR14 + 0x2E + 8 + read-write + 0xB + 0xFF + + + SSTR15 + desc SSTR15 + 0x2F + 8 + read-write + 0xB + 0xFF + + + SSTRL + desc SSTRL + 0x30 + 8 + read-write + 0xB + 0xFF + + + CHMUXR0 + desc CHMUXR0 + 0x38 + 16 + read-write + 0x3210 + 0xFFFF + + + CH00MUX + desc CH00MUX + 3 + 0 + read-write + + + CH01MUX + desc CH01MUX + 7 + 4 + read-write + + + CH02MUX + desc CH02MUX + 11 + 8 + read-write + + + CH03MUX + desc CH03MUX + 15 + 12 + read-write + + + + + CHMUXR1 + desc CHMUXR1 + 0x3A + 16 + read-write + 0x7654 + 0xFFFF + + + CH04MUX + desc CH04MUX + 3 + 0 + read-write + + + CH05MUX + desc CH05MUX + 7 + 4 + read-write + + + CH06MUX + desc CH06MUX + 11 + 8 + read-write + + + CH07MUX + desc CH07MUX + 15 + 12 + read-write + + + + + CHMUXR2 + desc CHMUXR2 + 0x3C + 16 + read-write + 0xBA98 + 0xFFFF + + + CH08MUX + desc CH08MUX + 3 + 0 + read-write + + + CH09MUX + desc CH09MUX + 7 + 4 + read-write + + + CH10MUX + desc CH10MUX + 11 + 8 + read-write + + + CH11MUX + desc CH11MUX + 15 + 12 + read-write + + + + + CHMUXR3 + desc CHMUXR3 + 0x3E + 16 + read-write + 0xFEDC + 0xFFFF + + + CH12MUX + desc CH12MUX + 3 + 0 + read-write + + + CH13MUX + desc CH13MUX + 7 + 4 + read-write + + + CH14MUX + desc CH14MUX + 11 + 8 + read-write + + + CH15MUX + desc CH15MUX + 15 + 12 + read-write + + + + + ISR + desc ISR + 0x46 + 8 + read-write + 0x0 + 0x3 + + + EOCAF + desc EOCAF + 0 + 0 + read-write + + + EOCBF + desc EOCBF + 1 + 1 + read-write + + + + + ICR + desc ICR + 0x47 + 8 + read-write + 0x0 + 0x3 + + + EOCAIEN + desc EOCAIEN + 0 + 0 + read-write + + + EOCBIEN + desc EOCBIEN + 1 + 1 + read-write + + + + + SYNCCR + desc SYNCCR + 0x4C + 16 + read-write + 0xC00 + 0xFF71 + + + SYNCEN + desc SYNCEN + 0 + 0 + read-write + + + SYNCMD + desc SYNCMD + 6 + 4 + read-write + + + SYNCDLY + desc SYNCDLY + 15 + 8 + read-write + + + + + DR0 + desc DR0 + 0x50 + 16 + read-only + 0x0 + 0xFFFF + + + DR1 + desc DR1 + 0x52 + 16 + read-only + 0x0 + 0xFFFF + + + DR2 + desc DR2 + 0x54 + 16 + read-only + 0x0 + 0xFFFF + + + DR3 + desc DR3 + 0x56 + 16 + read-only + 0x0 + 0xFFFF + + + DR4 + desc DR4 + 0x58 + 16 + read-only + 0x0 + 0xFFFF + + + DR5 + desc DR5 + 0x5A + 16 + read-only + 0x0 + 0xFFFF + + + DR6 + desc DR6 + 0x5C + 16 + read-only + 0x0 + 0xFFFF + + + DR7 + desc DR7 + 0x5E + 16 + read-only + 0x0 + 0xFFFF + + + DR8 + desc DR8 + 0x60 + 16 + read-only + 0x0 + 0xFFFF + + + DR9 + desc DR9 + 0x62 + 16 + read-only + 0x0 + 0xFFFF + + + DR10 + desc DR10 + 0x64 + 16 + read-only + 0x0 + 0xFFFF + + + DR11 + desc DR11 + 0x66 + 16 + read-only + 0x0 + 0xFFFF + + + DR12 + desc DR12 + 0x68 + 16 + read-only + 0x0 + 0xFFFF + + + DR13 + desc DR13 + 0x6A + 16 + read-only + 0x0 + 0xFFFF + + + DR14 + desc DR14 + 0x6C + 16 + read-only + 0x0 + 0xFFFF + + + DR15 + desc DR15 + 0x6E + 16 + read-only + 0x0 + 0xFFFF + + + DR16 + desc DR16 + 0x70 + 16 + read-only + 0x0 + 0xFFFF + + + AWDCR + desc AWDCR + 0xA0 + 16 + read-write + 0x0 + 0x1D1 + + + AWDEN + desc AWDEN + 0 + 0 + read-write + + + AWDMD + desc AWDMD + 4 + 4 + read-write + + + AWDSS + desc AWDSS + 7 + 6 + read-write + + + AWDIEN + desc AWDIEN + 8 + 8 + read-write + + + + + AWDDR0 + desc AWDDR0 + 0xA4 + 16 + read-write + 0x0 + 0xFFFF + + + AWDDR1 + desc AWDDR1 + 0xA6 + 16 + read-write + 0x0 + 0xFFFF + + + AWDCHSR + desc AWDCHSR + 0xAC + 32 + read-write + 0x0 + 0x1FFFF + + + AWDCH + desc AWDCH + 16 + 0 + read-write + + + + + AWDSR + desc AWDSR + 0xB0 + 32 + read-write + 0x0 + 0x1FFFF + + + AWDF + desc AWDF + 16 + 0 + read-write + + + + + PGACR + desc PGACR + 0xC0 + 16 + read-write + 0x0 + 0xF + + + PGACTL + desc PGACTL + 3 + 0 + read-write + + + + + PGAGSR + desc PGAGSR + 0xC2 + 16 + read-write + 0x0 + 0xF + + + GAIN + desc GAIN + 3 + 0 + read-write + + + + + PGAINSR0 + desc PGAINSR0 + 0xCC + 16 + read-write + 0x0 + 0x1FF + + + PGAINSEL + desc PGAINSEL + 8 + 0 + read-write + + + + + PGAINSR1 + desc PGAINSR1 + 0xCE + 16 + read-write + 0x0 + 0x1 + + + PGAVSSEN + desc PGAVSSEN + 0 + 0 + read-write + + + + + + + ADC2 + desc ADC + 0x40040400 + + 0x0 + 0xD0 + + + + AES + desc AES + 0x40008000 + + 0x0 + 0x30 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x3 + + + START + desc START + 0 + 0 + read-write + + + MODE + desc MODE + 1 + 1 + read-write + + + + + DR0 + desc DR0 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR1 + desc DR1 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR2 + desc DR2 + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR3 + desc DR3 + 0x1C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR0 + desc KR0 + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR1 + desc KR1 + 0x24 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR2 + desc KR2 + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR3 + desc KR3 + 0x2C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + AOS + desc AOS + 0x40010800 + + 0x0 + 0x174 + + + + INTSFTTRG + desc INTSFTTRG + 0x0 + 32 + write-only + 0x0 + 0x1 + + + STRG + desc STRG + 0 + 0 + write-only + + + + + DCU_TRGSEL1 + desc DCU_TRGSEL1 + 0x4 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DCU_TRGSEL2 + desc DCU_TRGSEL2 + 0x8 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DCU_TRGSEL3 + desc DCU_TRGSEL3 + 0xC + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DCU_TRGSEL4 + desc DCU_TRGSEL4 + 0x10 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL0 + desc DMA1_TRGSEL0 + 0x14 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL1 + desc DMA1_TRGSEL1 + 0x18 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL2 + desc DMA1_TRGSEL2 + 0x1C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL3 + desc DMA1_TRGSEL3 + 0x20 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL0 + desc DMA2_TRGSEL0 + 0x24 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL1 + desc DMA2_TRGSEL1 + 0x28 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL2 + desc DMA2_TRGSEL2 + 0x2C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL3 + desc DMA2_TRGSEL3 + 0x30 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA_TRGSELRC + desc DMA_TRGSELRC + 0x34 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR6_HTSSR0 + desc TMR6_HTSSR0 + 0x38 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR6_HTSSR1 + desc TMR6_HTSSR1 + 0x3C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR0_HTSSR + desc TMR0_HTSSR + 0x40 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + PEVNTTRGSR12 + desc PEVNTTRGSR12 + 0x44 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + PEVNTTRGSR34 + desc PEVNTTRGSR34 + 0x48 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMRA_HTSSR0 + desc TMRA_HTSSR0 + 0x4C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMRA_HTSSR1 + desc TMRA_HTSSR1 + 0x50 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + OTS_TRG + desc OTS_TRG + 0x54 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC1_ITRGSELR0 + desc ADC1_ITRGSELR0 + 0x58 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC1_ITRGSELR1 + desc ADC1_ITRGSELR1 + 0x5C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC2_ITRGSELR0 + desc ADC2_ITRGSELR0 + 0x60 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC2_ITRGSELR1 + desc ADC2_ITRGSELR1 + 0x64 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + COMTRG1 + desc COMTRG1 + 0x68 + 32 + read-write + 0x1FF + 0x1FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + + + COMTRG2 + desc COMTRG2 + 0x6C + 32 + read-write + 0x1FF + 0x1FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + + + PEVNTDIRR1 + desc PEVNTDIRR1 + 0x100 + 32 + read-write + 0x0 + 0xFFFF + + + PDIR00 + desc PDIR00 + 0 + 0 + read-write + + + PDIR01 + desc PDIR01 + 1 + 1 + read-write + + + PDIR02 + desc PDIR02 + 2 + 2 + read-write + + + PDIR03 + desc PDIR03 + 3 + 3 + read-write + + + PDIR04 + desc PDIR04 + 4 + 4 + read-write + + + PDIR05 + desc PDIR05 + 5 + 5 + read-write + + + PDIR06 + desc PDIR06 + 6 + 6 + read-write + + + PDIR07 + desc PDIR07 + 7 + 7 + read-write + + + PDIR08 + desc PDIR08 + 8 + 8 + read-write + + + PDIR09 + desc PDIR09 + 9 + 9 + read-write + + + PDIR10 + desc PDIR10 + 10 + 10 + read-write + + + PDIR11 + desc PDIR11 + 11 + 11 + read-write + + + PDIR12 + desc PDIR12 + 12 + 12 + read-write + + + PDIR13 + desc PDIR13 + 13 + 13 + read-write + + + PDIR14 + desc PDIR14 + 14 + 14 + read-write + + + PDIR15 + desc PDIR15 + 15 + 15 + read-write + + + + + PEVNTIDR1 + desc PEVNTIDR1 + 0x104 + 32 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PEVNTODR1 + desc PEVNTODR1 + 0x108 + 32 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + PEVNTORR1 + desc PEVNTORR1 + 0x10C + 32 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + PEVNTOSR1 + desc PEVNTOSR1 + 0x110 + 32 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PEVNTRISR1 + desc PEVNTRISR1 + 0x114 + 32 + read-write + 0x0 + 0xFFFF + + + RIS00 + desc RIS00 + 0 + 0 + read-write + + + RIS01 + desc RIS01 + 1 + 1 + read-write + + + RIS02 + desc RIS02 + 2 + 2 + read-write + + + RIS03 + desc RIS03 + 3 + 3 + read-write + + + RIS04 + desc RIS04 + 4 + 4 + read-write + + + RIS05 + desc RIS05 + 5 + 5 + read-write + + + RIS06 + desc RIS06 + 6 + 6 + read-write + + + RIS07 + desc RIS07 + 7 + 7 + read-write + + + RIS08 + desc RIS08 + 8 + 8 + read-write + + + RIS09 + desc RIS09 + 9 + 9 + read-write + + + RIS10 + desc RIS10 + 10 + 10 + read-write + + + RIS11 + desc RIS11 + 11 + 11 + read-write + + + RIS12 + desc RIS12 + 12 + 12 + read-write + + + RIS13 + desc RIS13 + 13 + 13 + read-write + + + RIS14 + desc RIS14 + 14 + 14 + read-write + + + RIS15 + desc RIS15 + 15 + 15 + read-write + + + + + PEVNTFAL1 + desc PEVNTFAL1 + 0x118 + 32 + read-write + 0x0 + 0xFFFF + + + FAL00 + desc FAL00 + 0 + 0 + read-write + + + FAL01 + desc FAL01 + 1 + 1 + read-write + + + FAL02 + desc FAL02 + 2 + 2 + read-write + + + FAL03 + desc FAL03 + 3 + 3 + read-write + + + FAL04 + desc FAL04 + 4 + 4 + read-write + + + FAL05 + desc FAL05 + 5 + 5 + read-write + + + FAL06 + desc FAL06 + 6 + 6 + read-write + + + FAL07 + desc FAL07 + 7 + 7 + read-write + + + FAL08 + desc FAL08 + 8 + 8 + read-write + + + FAL09 + desc FAL09 + 9 + 9 + read-write + + + FAL10 + desc FAL10 + 10 + 10 + read-write + + + FAL11 + desc FAL11 + 11 + 11 + read-write + + + FAL12 + desc FAL12 + 12 + 12 + read-write + + + FAL13 + desc FAL13 + 13 + 13 + read-write + + + FAL14 + desc FAL14 + 14 + 14 + read-write + + + FAL15 + desc FAL15 + 15 + 15 + read-write + + + + + PEVNTDIRR2 + desc PEVNTDIRR2 + 0x11C + 32 + read-write + 0x0 + 0xFFFF + + + PDIR00 + desc PDIR00 + 0 + 0 + read-write + + + PDIR01 + desc PDIR01 + 1 + 1 + read-write + + + PDIR02 + desc PDIR02 + 2 + 2 + read-write + + + PDIR03 + desc PDIR03 + 3 + 3 + read-write + + + PDIR04 + desc PDIR04 + 4 + 4 + read-write + + + PDIR05 + desc PDIR05 + 5 + 5 + read-write + + + PDIR06 + desc PDIR06 + 6 + 6 + read-write + + + PDIR07 + desc PDIR07 + 7 + 7 + read-write + + + PDIR08 + desc PDIR08 + 8 + 8 + read-write + + + PDIR09 + desc PDIR09 + 9 + 9 + read-write + + + PDIR10 + desc PDIR10 + 10 + 10 + read-write + + + PDIR11 + desc PDIR11 + 11 + 11 + read-write + + + PDIR12 + desc PDIR12 + 12 + 12 + read-write + + + PDIR13 + desc PDIR13 + 13 + 13 + read-write + + + PDIR14 + desc PDIR14 + 14 + 14 + read-write + + + PDIR15 + desc PDIR15 + 15 + 15 + read-write + + + + + PEVNTIDR2 + desc PEVNTIDR2 + 0x120 + 32 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PEVNTODR2 + desc PEVNTODR2 + 0x124 + 32 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + PEVNTORR2 + desc PEVNTORR2 + 0x128 + 32 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + PEVNTOSR2 + desc PEVNTOSR2 + 0x12C + 32 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PEVNTRISR2 + desc PEVNTRISR2 + 0x130 + 32 + read-write + 0x0 + 0xFFFF + + + RIS00 + desc RIS00 + 0 + 0 + read-write + + + RIS01 + desc RIS01 + 1 + 1 + read-write + + + RIS02 + desc RIS02 + 2 + 2 + read-write + + + RIS03 + desc RIS03 + 3 + 3 + read-write + + + RIS04 + desc RIS04 + 4 + 4 + read-write + + + RIS05 + desc RIS05 + 5 + 5 + read-write + + + RIS06 + desc RIS06 + 6 + 6 + read-write + + + RIS07 + desc RIS07 + 7 + 7 + read-write + + + RIS08 + desc RIS08 + 8 + 8 + read-write + + + RIS09 + desc RIS09 + 9 + 9 + read-write + + + RIS10 + desc RIS10 + 10 + 10 + read-write + + + RIS11 + desc RIS11 + 11 + 11 + read-write + + + RIS12 + desc RIS12 + 12 + 12 + read-write + + + RIS13 + desc RIS13 + 13 + 13 + read-write + + + RIS14 + desc RIS14 + 14 + 14 + read-write + + + RIS15 + desc RIS15 + 15 + 15 + read-write + + + + + PEVNTFAL2 + desc PEVNTFAL2 + 0x134 + 32 + read-write + 0x0 + 0xFFFF + + + FAL00 + desc FAL00 + 0 + 0 + read-write + + + FAL01 + desc FAL01 + 1 + 1 + read-write + + + FAL02 + desc FAL02 + 2 + 2 + read-write + + + FAL03 + desc FAL03 + 3 + 3 + read-write + + + FAL04 + desc FAL04 + 4 + 4 + read-write + + + FAL05 + desc FAL05 + 5 + 5 + read-write + + + FAL06 + desc FAL06 + 6 + 6 + read-write + + + FAL07 + desc FAL07 + 7 + 7 + read-write + + + FAL08 + desc FAL08 + 8 + 8 + read-write + + + FAL09 + desc FAL09 + 9 + 9 + read-write + + + FAL10 + desc FAL10 + 10 + 10 + read-write + + + FAL11 + desc FAL11 + 11 + 11 + read-write + + + FAL12 + desc FAL12 + 12 + 12 + read-write + + + FAL13 + desc FAL13 + 13 + 13 + read-write + + + FAL14 + desc FAL14 + 14 + 14 + read-write + + + FAL15 + desc FAL15 + 15 + 15 + read-write + + + + + PEVNTDIRR3 + desc PEVNTDIRR3 + 0x138 + 32 + read-write + 0x0 + 0xFFFF + + + PDIR00 + desc PDIR00 + 0 + 0 + read-write + + + PDIR01 + desc PDIR01 + 1 + 1 + read-write + + + PDIR02 + desc PDIR02 + 2 + 2 + read-write + + + PDIR03 + desc PDIR03 + 3 + 3 + read-write + + + PDIR04 + desc PDIR04 + 4 + 4 + read-write + + + PDIR05 + desc PDIR05 + 5 + 5 + read-write + + + PDIR06 + desc PDIR06 + 6 + 6 + read-write + + + PDIR07 + desc PDIR07 + 7 + 7 + read-write + + + PDIR08 + desc PDIR08 + 8 + 8 + read-write + + + PDIR09 + desc PDIR09 + 9 + 9 + read-write + + + PDIR10 + desc PDIR10 + 10 + 10 + read-write + + + PDIR11 + desc PDIR11 + 11 + 11 + read-write + + + PDIR12 + desc PDIR12 + 12 + 12 + read-write + + + PDIR13 + desc PDIR13 + 13 + 13 + read-write + + + PDIR14 + desc PDIR14 + 14 + 14 + read-write + + + PDIR15 + desc PDIR15 + 15 + 15 + read-write + + + + + PEVNTIDR3 + desc PEVNTIDR3 + 0x13C + 32 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PEVNTODR3 + desc PEVNTODR3 + 0x140 + 32 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + PEVNTORR3 + desc PEVNTORR3 + 0x144 + 32 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + PEVNTOSR3 + desc PEVNTOSR3 + 0x148 + 32 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PEVNTRISR3 + desc PEVNTRISR3 + 0x14C + 32 + read-write + 0x0 + 0xFFFF + + + RIS00 + desc RIS00 + 0 + 0 + read-write + + + RIS01 + desc RIS01 + 1 + 1 + read-write + + + RIS02 + desc RIS02 + 2 + 2 + read-write + + + RIS03 + desc RIS03 + 3 + 3 + read-write + + + RIS04 + desc RIS04 + 4 + 4 + read-write + + + RIS05 + desc RIS05 + 5 + 5 + read-write + + + RIS06 + desc RIS06 + 6 + 6 + read-write + + + RIS07 + desc RIS07 + 7 + 7 + read-write + + + RIS08 + desc RIS08 + 8 + 8 + read-write + + + RIS09 + desc RIS09 + 9 + 9 + read-write + + + RIS10 + desc RIS10 + 10 + 10 + read-write + + + RIS11 + desc RIS11 + 11 + 11 + read-write + + + RIS12 + desc RIS12 + 12 + 12 + read-write + + + RIS13 + desc RIS13 + 13 + 13 + read-write + + + RIS14 + desc RIS14 + 14 + 14 + read-write + + + RIS15 + desc RIS15 + 15 + 15 + read-write + + + + + PEVNTFAL3 + desc PEVNTFAL3 + 0x150 + 32 + read-write + 0x0 + 0xFFFF + + + FAL00 + desc FAL00 + 0 + 0 + read-write + + + FAL01 + desc FAL01 + 1 + 1 + read-write + + + FAL02 + desc FAL02 + 2 + 2 + read-write + + + FAL03 + desc FAL03 + 3 + 3 + read-write + + + FAL04 + desc FAL04 + 4 + 4 + read-write + + + FAL05 + desc FAL05 + 5 + 5 + read-write + + + FAL06 + desc FAL06 + 6 + 6 + read-write + + + FAL07 + desc FAL07 + 7 + 7 + read-write + + + FAL08 + desc FAL08 + 8 + 8 + read-write + + + FAL09 + desc FAL09 + 9 + 9 + read-write + + + FAL10 + desc FAL10 + 10 + 10 + read-write + + + FAL11 + desc FAL11 + 11 + 11 + read-write + + + FAL12 + desc FAL12 + 12 + 12 + read-write + + + FAL13 + desc FAL13 + 13 + 13 + read-write + + + FAL14 + desc FAL14 + 14 + 14 + read-write + + + FAL15 + desc FAL15 + 15 + 15 + read-write + + + + + PEVNTDIRR4 + desc PEVNTDIRR4 + 0x154 + 32 + read-write + 0x0 + 0xFFFF + + + PDIR00 + desc PDIR00 + 0 + 0 + read-write + + + PDIR01 + desc PDIR01 + 1 + 1 + read-write + + + PDIR02 + desc PDIR02 + 2 + 2 + read-write + + + PDIR03 + desc PDIR03 + 3 + 3 + read-write + + + PDIR04 + desc PDIR04 + 4 + 4 + read-write + + + PDIR05 + desc PDIR05 + 5 + 5 + read-write + + + PDIR06 + desc PDIR06 + 6 + 6 + read-write + + + PDIR07 + desc PDIR07 + 7 + 7 + read-write + + + PDIR08 + desc PDIR08 + 8 + 8 + read-write + + + PDIR09 + desc PDIR09 + 9 + 9 + read-write + + + PDIR10 + desc PDIR10 + 10 + 10 + read-write + + + PDIR11 + desc PDIR11 + 11 + 11 + read-write + + + PDIR12 + desc PDIR12 + 12 + 12 + read-write + + + PDIR13 + desc PDIR13 + 13 + 13 + read-write + + + PDIR14 + desc PDIR14 + 14 + 14 + read-write + + + PDIR15 + desc PDIR15 + 15 + 15 + read-write + + + + + PEVNTIDR4 + desc PEVNTIDR4 + 0x158 + 32 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PEVNTODR4 + desc PEVNTODR4 + 0x15C + 32 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + PEVNTORR4 + desc PEVNTORR4 + 0x160 + 32 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + PEVNTOSR4 + desc PEVNTOSR4 + 0x164 + 32 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PEVNTRISR4 + desc PEVNTRISR4 + 0x168 + 32 + read-write + 0x0 + 0xFFFF + + + RIS00 + desc RIS00 + 0 + 0 + read-write + + + RIS01 + desc RIS01 + 1 + 1 + read-write + + + RIS02 + desc RIS02 + 2 + 2 + read-write + + + RIS03 + desc RIS03 + 3 + 3 + read-write + + + RIS04 + desc RIS04 + 4 + 4 + read-write + + + RIS05 + desc RIS05 + 5 + 5 + read-write + + + RIS06 + desc RIS06 + 6 + 6 + read-write + + + RIS07 + desc RIS07 + 7 + 7 + read-write + + + RIS08 + desc RIS08 + 8 + 8 + read-write + + + RIS09 + desc RIS09 + 9 + 9 + read-write + + + RIS10 + desc RIS10 + 10 + 10 + read-write + + + RIS11 + desc RIS11 + 11 + 11 + read-write + + + RIS12 + desc RIS12 + 12 + 12 + read-write + + + RIS13 + desc RIS13 + 13 + 13 + read-write + + + RIS14 + desc RIS14 + 14 + 14 + read-write + + + RIS15 + desc RIS15 + 15 + 15 + read-write + + + + + PEVNTFAL4 + desc PEVNTFAL4 + 0x16C + 32 + read-write + 0x0 + 0xFFFF + + + FAL00 + desc FAL00 + 0 + 0 + read-write + + + FAL01 + desc FAL01 + 1 + 1 + read-write + + + FAL02 + desc FAL02 + 2 + 2 + read-write + + + FAL03 + desc FAL03 + 3 + 3 + read-write + + + FAL04 + desc FAL04 + 4 + 4 + read-write + + + FAL05 + desc FAL05 + 5 + 5 + read-write + + + FAL06 + desc FAL06 + 6 + 6 + read-write + + + FAL07 + desc FAL07 + 7 + 7 + read-write + + + FAL08 + desc FAL08 + 8 + 8 + read-write + + + FAL09 + desc FAL09 + 9 + 9 + read-write + + + FAL10 + desc FAL10 + 10 + 10 + read-write + + + FAL11 + desc FAL11 + 11 + 11 + read-write + + + FAL12 + desc FAL12 + 12 + 12 + read-write + + + FAL13 + desc FAL13 + 13 + 13 + read-write + + + FAL14 + desc FAL14 + 14 + 14 + read-write + + + FAL15 + desc FAL15 + 15 + 15 + read-write + + + + + PEVNTNFCR + desc PEVNTNFCR + 0x170 + 32 + read-write + 0x0 + 0x7070707 + + + NFEN1 + desc NFEN1 + 0 + 0 + read-write + + + DIVS1 + desc DIVS1 + 2 + 1 + read-write + + + NFEN2 + desc NFEN2 + 8 + 8 + read-write + + + DIVS2 + desc DIVS2 + 10 + 9 + read-write + + + NFEN3 + desc NFEN3 + 16 + 16 + read-write + + + DIVS3 + desc DIVS3 + 18 + 17 + read-write + + + NFEN4 + desc NFEN4 + 24 + 24 + read-write + + + DIVS4 + desc DIVS4 + 26 + 25 + read-write + + + + + + + CAN + desc CAN + 0x40070400 + + 0x0 + 0xCA + + + + RBUF + desc RBUF + 0x0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TBUF + desc TBUF + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CFG_STAT + desc CFG_STAT + 0xA0 + 8 + read-write + 0x80 + 0xFF + + + BUSOFF + desc BUSOFF + 0 + 0 + read-write + + + TACTIVE + desc TACTIVE + 1 + 1 + read-only + + + RACTIVE + desc RACTIVE + 2 + 2 + read-only + + + TSSS + desc TSSS + 3 + 3 + read-write + + + TPSS + desc TPSS + 4 + 4 + read-write + + + LBMI + desc LBMI + 5 + 5 + read-write + + + LBME + desc LBME + 6 + 6 + read-write + + + RESET + desc RESET + 7 + 7 + read-write + + + + + TCMD + desc TCMD + 0xA1 + 8 + read-write + 0x0 + 0xDF + + + TSA + desc TSA + 0 + 0 + read-write + + + TSALL + desc TSALL + 1 + 1 + read-write + + + TSONE + desc TSONE + 2 + 2 + read-write + + + TPA + desc TPA + 3 + 3 + read-write + + + TPE + desc TPE + 4 + 4 + read-write + + + LOM + desc LOM + 6 + 6 + read-write + + + TBSEL + desc TBSEL + 7 + 7 + read-write + + + + + TCTRL + desc TCTRL + 0xA2 + 8 + read-write + 0x90 + 0x73 + + + TSSTAT + desc TSSTAT + 1 + 0 + read-only + + + TTTBM + desc TTTBM + 4 + 4 + read-write + + + TSMODE + desc TSMODE + 5 + 5 + read-write + + + TSNEXT + desc TSNEXT + 6 + 6 + read-write + + + + + RCTRL + desc RCTRL + 0xA3 + 8 + read-write + 0x0 + 0xFB + + + RSTAT + desc RSTAT + 1 + 0 + read-only + + + RBALL + desc RBALL + 3 + 3 + read-write + + + RREL + desc RREL + 4 + 4 + read-write + + + ROV + desc ROV + 5 + 5 + read-only + + + ROM + desc ROM + 6 + 6 + read-write + + + SACK + desc SACK + 7 + 7 + read-write + + + + + RTIE + desc RTIE + 0xA4 + 8 + read-write + 0xFE + 0xFF + + + TSFF + desc TSFF + 0 + 0 + read-only + + + EIE + desc EIE + 1 + 1 + read-write + + + TSIE + desc TSIE + 2 + 2 + read-write + + + TPIE + desc TPIE + 3 + 3 + read-write + + + RAFIE + desc RAFIE + 4 + 4 + read-write + + + RFIE + desc RFIE + 5 + 5 + read-write + + + ROIE + desc ROIE + 6 + 6 + read-write + + + RIE + desc RIE + 7 + 7 + read-write + + + + + RTIF + desc RTIF + 0xA5 + 8 + read-write + 0x0 + 0xFF + + + AIF + desc AIF + 0 + 0 + read-write + + + EIF + desc EIF + 1 + 1 + read-write + + + TSIF + desc TSIF + 2 + 2 + read-write + + + TPIF + desc TPIF + 3 + 3 + read-write + + + RAFIF + desc RAFIF + 4 + 4 + read-write + + + RFIF + desc RFIF + 5 + 5 + read-write + + + ROIF + desc ROIF + 6 + 6 + read-write + + + RIF + desc RIF + 7 + 7 + read-write + + + + + ERRINT + desc ERRINT + 0xA6 + 8 + read-write + 0x0 + 0xFF + + + BEIF + desc BEIF + 0 + 0 + read-write + + + BEIE + desc BEIE + 1 + 1 + read-write + + + ALIF + desc ALIF + 2 + 2 + read-write + + + ALIE + desc ALIE + 3 + 3 + read-write + + + EPIF + desc EPIF + 4 + 4 + read-write + + + EPIE + desc EPIE + 5 + 5 + read-write + + + EPASS + desc EPASS + 6 + 6 + read-only + + + EWARN + desc EWARN + 7 + 7 + read-only + + + + + LIMIT + desc LIMIT + 0xA7 + 8 + read-write + 0x1B + 0xFF + + + EWL + desc EWL + 3 + 0 + read-write + + + AFWL + desc AFWL + 7 + 4 + read-write + + + + + SBT + desc SBT + 0xA8 + 32 + read-write + 0x1020203 + 0xFF7F7FFF + + + S_SEG_1 + desc S_SEG_1 + 7 + 0 + read-write + + + S_SEG_2 + desc S_SEG_2 + 14 + 8 + read-write + + + S_SJW + desc S_SJW + 22 + 16 + read-write + + + S_PRESC + desc S_PRESC + 31 + 24 + read-write + + + + + EALCAP + desc EALCAP + 0xB0 + 8 + read-only + 0x0 + 0xFF + + + ALC + desc ALC + 4 + 0 + read-only + + + KOER + desc KOER + 7 + 5 + read-only + + + + + RECNT + desc RECNT + 0xB2 + 8 + read-write + 0x0 + 0xFF + + + TECNT + desc TECNT + 0xB3 + 8 + read-write + 0x0 + 0xFF + + + ACFCTRL + desc ACFCTRL + 0xB4 + 8 + read-write + 0x0 + 0x2F + + + ACFADR + desc ACFADR + 3 + 0 + read-write + + + SELMASK + desc SELMASK + 5 + 5 + read-write + + + + + ACFEN + desc ACFEN + 0xB6 + 8 + read-write + 0x1 + 0xFF + + + AE_1 + desc AE_1 + 0 + 0 + read-write + + + AE_2 + desc AE_2 + 1 + 1 + read-write + + + AE_3 + desc AE_3 + 2 + 2 + read-write + + + AE_4 + desc AE_4 + 3 + 3 + read-write + + + AE_5 + desc AE_5 + 4 + 4 + read-write + + + AE_6 + desc AE_6 + 5 + 5 + read-write + + + AE_7 + desc AE_7 + 6 + 6 + read-write + + + AE_8 + desc AE_8 + 7 + 7 + read-write + + + + + ACF + desc ACF + 0xB8 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + ACODEORAMASK + desc ACODEORAMASK + 28 + 0 + read-write + + + AIDE + desc AIDE + 29 + 29 + read-write + + + AIDEE + desc AIDEE + 30 + 30 + read-write + + + + + TBSLOT + desc TBSLOT + 0xBE + 8 + read-write + 0x0 + 0xFF + + + TBPTR + desc TBPTR + 5 + 0 + read-write + + + TBF + desc TBF + 6 + 6 + read-write + + + TBE + desc TBE + 7 + 7 + read-write + + + + + TTCFG + desc TTCFG + 0xBF + 8 + read-write + 0x90 + 0xFF + + + TTEN + desc TTEN + 0 + 0 + read-write + + + T_PRESC + desc T_PRESC + 2 + 1 + read-write + + + TTIF + desc TTIF + 3 + 3 + read-write + + + TTIE + desc TTIE + 4 + 4 + read-write + + + TEIF + desc TEIF + 5 + 5 + read-write + + + WTIF + desc WTIF + 6 + 6 + read-write + + + WTIE + desc WTIE + 7 + 7 + read-write + + + + + REF_MSG + desc REF_MSG + 0xC0 + 32 + read-write + 0x0 + 0x9FFFFFFF + + + REF_ID + desc REF_ID + 28 + 0 + read-write + + + REF_IDE + desc REF_IDE + 31 + 31 + read-write + + + + + TRG_CFG + desc TRG_CFG + 0xC4 + 16 + read-write + 0x0 + 0xF73F + + + TTPTR + desc TTPTR + 5 + 0 + read-write + + + TTYPE + desc TTYPE + 10 + 8 + read-write + + + TEW + desc TEW + 15 + 12 + read-write + + + + + TT_TRIG + desc TT_TRIG + 0xC6 + 16 + read-write + 0x0 + 0xFFFF + + + TT_WTRIG + desc TT_WTRIG + 0xC8 + 16 + read-write + 0xFFFF + 0xFFFF + + + + + CMP1 + desc CMP + 0x4004A000 + + 0x0 + 0xA + + + + CTRL + desc CTRL + 0x0 + 16 + read-write + 0x0 + 0xF1E7 + + + FLTSL + desc FLTSL + 2 + 0 + read-write + + + EDGSL + desc EDGSL + 6 + 5 + read-write + + + IEN + desc IEN + 7 + 7 + read-write + + + CVSEN + desc CVSEN + 8 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + INV + desc INV + 13 + 13 + read-write + + + CMPOE + desc CMPOE + 14 + 14 + read-write + + + CMPON + desc CMPON + 15 + 15 + read-write + + + + + VLTSEL + desc VLTSEL + 0x2 + 16 + read-write + 0x0 + 0x7F0F + + + RVSL + desc RVSL + 3 + 0 + read-write + + + CVSL + desc CVSL + 11 + 8 + read-write + + + C4SL + desc C4SL + 14 + 12 + read-write + + + + + OUTMON + desc OUTMON + 0x4 + 16 + read-only + 0x0 + 0xF01 + + + OMON + desc OMON + 0 + 0 + read-only + + + CVST + desc CVST + 11 + 8 + read-only + + + + + CVSSTB + desc CVSSTB + 0x6 + 16 + read-write + 0x5 + 0xF + + + STB + desc STB + 3 + 0 + read-write + + + + + CVSPRD + desc CVSPRD + 0x8 + 16 + read-write + 0xF + 0xFF + + + PRD + desc PRD + 7 + 0 + read-write + + + + + + + CMP2 + desc CMP + 0x4004A010 + + 0x0 + 0xA + + + + CMP3 + desc CMP + 0x4004A020 + + 0x0 + 0xA + + + + CMPCR + desc CMPCR + 0x4004A000 + CMP1 + + 0x0 + 0x10E + + + + DADR1 + desc DADR1 + 0x100 + 16 + read-write + 0x0 + 0xFF + + + DATA + desc DATA + 7 + 0 + read-write + + + + + DADR2 + desc DADR2 + 0x102 + 16 + read-write + 0x0 + 0xFF + + + DATA + desc DATA + 7 + 0 + read-write + + + + + DACR + desc DACR + 0x108 + 16 + read-write + 0x0 + 0x3 + + + DA1EN + desc DA1EN + 0 + 0 + read-write + + + DA2EN + desc DA2EN + 1 + 1 + read-write + + + + + RVADC + desc RVADC + 0x10C + 16 + read-write + 0x0 + 0x13 + + + DA1SW + desc DA1SW + 0 + 0 + read-write + + + DA2SW + desc DA2SW + 1 + 1 + read-write + + + VREFSW + desc VREFSW + 4 + 4 + read-write + + + WPRT + desc WPRT + 15 + 8 + read-write + + + + + + + CMU + desc CMU + 0x40054000 + + 0x0 + 0x42A + + + + PERICKSEL + desc PERICKSEL + 0x10 + 16 + read-write + 0x0 + 0xF + + + PERICKSEL + desc PERICKSEL + 3 + 0 + read-write + + + + + I2SCKSEL + desc I2SCKSEL + 0x12 + 16 + read-write + 0xBBBB + 0xFFFF + + + I2S1CKSEL + desc I2S1CKSEL + 3 + 0 + read-write + + + I2S2CKSEL + desc I2S2CKSEL + 7 + 4 + read-write + + + I2S3CKSEL + desc I2S3CKSEL + 11 + 8 + read-write + + + I2S4CKSEL + desc I2S4CKSEL + 15 + 12 + read-write + + + + + SCFGR + desc SCFGR + 0x20 + 32 + read-write + 0x0 + 0x7777777 + + + PCLK0S + desc PCLK0S + 2 + 0 + read-write + + + PCLK1S + desc PCLK1S + 6 + 4 + read-write + + + PCLK2S + desc PCLK2S + 10 + 8 + read-write + + + PCLK3S + desc PCLK3S + 14 + 12 + read-write + + + PCLK4S + desc PCLK4S + 18 + 16 + read-write + + + EXCKS + desc EXCKS + 22 + 20 + read-write + + + HCLKS + desc HCLKS + 26 + 24 + read-write + + + + + USBCKCFGR + desc USBCKCFGR + 0x24 + 8 + read-write + 0x40 + 0xF0 + + + USBCKS + desc USBCKS + 7 + 4 + read-write + + + + + CKSWR + desc CKSWR + 0x26 + 8 + read-write + 0x1 + 0x7 + + + CKSW + desc CKSW + 2 + 0 + read-write + + + + + PLLCR + desc PLLCR + 0x2A + 8 + read-write + 0x1 + 0x1 + + + MPLLOFF + desc MPLLOFF + 0 + 0 + read-write + + + + + UPLLCR + desc UPLLCR + 0x2E + 8 + read-write + 0x1 + 0x1 + + + UPLLOFF + desc UPLLOFF + 0 + 0 + read-write + + + + + XTALCR + desc XTALCR + 0x32 + 8 + read-write + 0x1 + 0x1 + + + XTALSTP + desc XTALSTP + 0 + 0 + read-write + + + + + HRCCR + desc HRCCR + 0x36 + 8 + read-write + 0x1 + 0x1 + + + HRCSTP + desc HRCSTP + 0 + 0 + read-write + + + + + MRCCR + desc MRCCR + 0x38 + 8 + read-write + 0x80 + 0x1 + + + MRCSTP + desc MRCSTP + 0 + 0 + read-write + + + + + OSCSTBSR + desc OSCSTBSR + 0x3C + 8 + read-write + 0x0 + 0x69 + + + HRCSTBF + desc HRCSTBF + 0 + 0 + read-write + + + XTALSTBF + desc XTALSTBF + 3 + 3 + read-write + + + MPLLSTBF + desc MPLLSTBF + 5 + 5 + read-write + + + UPLLSTBF + desc UPLLSTBF + 6 + 6 + read-write + + + + + MCOCFGR1 + desc MCOCFGR1 + 0x3D + 8 + read-write + 0x0 + 0xFF + + + MCOSEL + desc MCOSEL + 3 + 0 + read-write + + + MCODIV + desc MCODIV + 6 + 4 + read-write + + + MCOEN + desc MCOEN + 7 + 7 + read-write + + + + + MCOCFGR2 + desc MCOCFGR2 + 0x3E + 8 + read-write + 0x0 + 0xFF + + + MCOSEL + desc MCOSEL + 3 + 0 + read-write + + + MCODIV + desc MCODIV + 6 + 4 + read-write + + + MCOEN + desc MCOEN + 7 + 7 + read-write + + + + + TPIUCKCFGR + desc TPIUCKCFGR + 0x3F + 8 + read-write + 0x0 + 0x83 + + + TPIUCKS + desc TPIUCKS + 1 + 0 + read-write + + + TPIUCKOE + desc TPIUCKOE + 7 + 7 + read-write + + + + + XTALSTDCR + desc XTALSTDCR + 0x40 + 8 + read-write + 0x0 + 0x87 + + + XTALSTDIE + desc XTALSTDIE + 0 + 0 + read-write + + + XTALSTDRE + desc XTALSTDRE + 1 + 1 + read-write + + + XTALSTDRIS + desc XTALSTDRIS + 2 + 2 + read-write + + + XTALSTDE + desc XTALSTDE + 7 + 7 + read-write + + + + + XTALSTDSR + desc XTALSTDSR + 0x41 + 8 + read-write + 0x0 + 0x1 + + + XTALSTDF + desc XTALSTDF + 0 + 0 + read-write + + + + + MRCTRM + desc MRCTRM + 0x61 + 8 + read-write + 0x0 + 0xFF + + + HRCTRM + desc HRCTRM + 0x62 + 8 + read-write + 0x0 + 0xFF + + + XTALSTBCR + desc XTALSTBCR + 0xA2 + 8 + read-write + 0x5 + 0xF + + + XTALSTB + desc XTALSTB + 3 + 0 + read-write + + + + + PLLCFGR + desc PLLCFGR + 0x100 + 32 + read-write + 0x11101300 + 0xFFF1FF9F + + + MPLLM + desc MPLLM + 4 + 0 + read-write + + + PLLSRC + desc PLLSRC + 7 + 7 + read-write + + + MPLLN + desc MPLLN + 16 + 8 + read-write + + + MPLLR + desc MPLLR + 23 + 20 + read-write + + + MPLLQ + desc MPLLQ + 27 + 24 + read-write + + + MPLLP + desc MPLLP + 31 + 28 + read-write + + + + + UPLLCFGR + desc UPLLCFGR + 0x104 + 32 + read-write + 0x11101300 + 0xFFF1FF1F + + + UPLLM + desc UPLLM + 4 + 0 + read-write + + + UPLLN + desc UPLLN + 16 + 8 + read-write + + + UPLLR + desc UPLLR + 23 + 20 + read-write + + + UPLLQ + desc UPLLQ + 27 + 24 + read-write + + + UPLLP + desc UPLLP + 31 + 28 + read-write + + + + + XTALCFGR + desc XTALCFGR + 0x410 + 8 + read-write + 0x80 + 0xF0 + + + XTALDRV + desc XTALDRV + 5 + 4 + read-write + + + XTALMS + desc XTALMS + 6 + 6 + read-write + + + SUPDRV + desc SUPDRV + 7 + 7 + read-write + + + + + XTAL32CR + desc XTAL32CR + 0x420 + 8 + read-write + 0x0 + 0x1 + + + XTAL32STP + desc XTAL32STP + 0 + 0 + read-write + + + + + XTAL32CFGR + desc XTAL32CFGR + 0x421 + 8 + read-write + 0x0 + 0x7 + + + XTAL32DRV + desc XTAL32DRV + 2 + 0 + read-write + + + + + XTAL32NFR + desc XTAL32NFR + 0x425 + 8 + read-write + 0x0 + 0x3 + + + XTAL32NF + desc XTAL32NF + 1 + 0 + read-write + + + + + LRCCR + desc LRCCR + 0x427 + 8 + read-write + 0x0 + 0x1 + + + LRCSTP + desc LRCSTP + 0 + 0 + read-write + + + + + LRCTRM + desc LRCTRM + 0x429 + 8 + read-write + 0x0 + 0xFF + + + + + CRC + desc CRC + 0x40008C00 + + 0x0 + 0x100 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x1C + 0x1E + + + CR + desc CR + 1 + 1 + read-write + + + REFIN + desc REFIN + 2 + 2 + read-write + + + REFOUT + desc REFOUT + 3 + 3 + read-write + + + XOROUT + desc XOROUT + 4 + 4 + read-write + + + + + RESLT + desc RESLT + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CRC_REG + desc CRC_REG + 15 + 0 + read-write + + + CRCFLAG_16 + desc CRCFLAG_16 + 16 + 16 + read-only + + + + + FLG + desc FLG + 0xC + 32 + read-only + 0x1 + 0x1 + + + CRCFLAG_32 + desc CRCFLAG_32 + 0 + 0 + read-only + + + + + DAT0 + desc DAT0 + 0x80 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT1 + desc DAT1 + 0x84 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT2 + desc DAT2 + 0x88 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT3 + desc DAT3 + 0x8C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT4 + desc DAT4 + 0x90 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT5 + desc DAT5 + 0x94 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT6 + desc DAT6 + 0x98 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT7 + desc DAT7 + 0x9C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT8 + desc DAT8 + 0xA0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT9 + desc DAT9 + 0xA4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT10 + desc DAT10 + 0xA8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT11 + desc DAT11 + 0xAC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT12 + desc DAT12 + 0xB0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT13 + desc DAT13 + 0xB4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT14 + desc DAT14 + 0xB8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT15 + desc DAT15 + 0xBC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT16 + desc DAT16 + 0xC0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT17 + desc DAT17 + 0xC4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT18 + desc DAT18 + 0xC8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT19 + desc DAT19 + 0xCC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT20 + desc DAT20 + 0xD0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT21 + desc DAT21 + 0xD4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT22 + desc DAT22 + 0xD8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT23 + desc DAT23 + 0xDC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT24 + desc DAT24 + 0xE0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT25 + desc DAT25 + 0xE4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT26 + desc DAT26 + 0xE8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT27 + desc DAT27 + 0xEC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT28 + desc DAT28 + 0xF0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT29 + desc DAT29 + 0xF4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT30 + desc DAT30 + 0xF8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT31 + desc DAT31 + 0xFC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + + + DBGC + desc DBGC + 0xE0042000 + + 0x0 + 0x28 + + + + AUTHID0 + desc AUTHID0 + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + AUTHID1 + desc AUTHID1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + AUTHID2 + desc AUTHID2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RESV0 + desc RESV0 + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MCUSTAT + desc MCUSTAT + 0x10 + 32 + read-write + 0x0 + 0x30F + + + AUTH + desc AUTH + 0 + 0 + read-write + + + REMVLOCK + desc REMVLOCK + 1 + 1 + read-write + + + SAFTYLOCK1 + desc SAFTYLOCK1 + 2 + 2 + read-write + + + SAFTYLOCK2 + desc SAFTYLOCK2 + 3 + 3 + read-write + + + CPUSTOP + desc CPUSTOP + 8 + 8 + read-write + + + CPUSLEEP + desc CPUSLEEP + 9 + 9 + read-write + + + + + MCUCTL + desc MCUCTL + 0x14 + 32 + read-write + 0x0 + 0x103 + + + EDBGRQ + desc EDBGRQ + 0 + 0 + read-write + + + RESTART + desc RESTART + 1 + 1 + read-write + + + DIRQ + desc DIRQ + 8 + 8 + read-write + + + + + FMCCTL + desc FMCCTL + 0x18 + 32 + read-write + 0x0 + 0x7 + + + ERASEREQ + desc ERASEREQ + 0 + 0 + read-write + + + ERASEACK + desc ERASEACK + 1 + 1 + read-write + + + ERASEERR + desc ERASEERR + 2 + 2 + read-write + + + + + MCUDBGSTAT + desc MCUDBGSTAT + 0x1C + 32 + read-write + 0x0 + 0x3 + + + CDBGPWRUPREQ + desc CDBGPWRUPREQ + 0 + 0 + read-write + + + CDBGPWRUPACK + desc CDBGPWRUPACK + 1 + 1 + read-write + + + + + MCUSTPCTL + desc MCUSTPCTL + 0x20 + 32 + read-write + 0x3 + 0xFFF0C03F + + + SWDTSTP + desc SWDTSTP + 0 + 0 + read-write + + + WDTSTP + desc WDTSTP + 1 + 1 + read-write + + + RTCSTP + desc RTCSTP + 2 + 2 + read-write + + + PVD0STP + desc PVD0STP + 3 + 3 + read-write + + + PVD1STP + desc PVD1STP + 4 + 4 + read-write + + + PVD2STP + desc PVD2STP + 5 + 5 + read-write + + + TMR01STP + desc TMR01STP + 14 + 14 + read-write + + + TMR02STP + desc TMR02STP + 15 + 15 + read-write + + + TMR41STP + desc TMR41STP + 20 + 20 + read-write + + + TMR42STP + desc TMR42STP + 21 + 21 + read-write + + + TMR43STP + desc TMR43STP + 22 + 22 + read-write + + + TM61STP + desc TM61STP + 23 + 23 + read-write + + + TM62STP + desc TM62STP + 24 + 24 + read-write + + + TMR63STP + desc TMR63STP + 25 + 25 + read-write + + + TMRA1STP + desc TMRA1STP + 26 + 26 + read-write + + + TMRA2STP + desc TMRA2STP + 27 + 27 + read-write + + + TMRA3STP + desc TMRA3STP + 28 + 28 + read-write + + + TMRA4STP + desc TMRA4STP + 29 + 29 + read-write + + + TMRA5STP + desc TMRA5STP + 30 + 30 + read-write + + + TMRA6STP + desc TMRA6STP + 31 + 31 + read-write + + + + + MCUTRACECTL + desc MCUTRACECTL + 0x24 + 32 + read-write + 0x0 + 0x7 + + + TRACEMODE + desc TRACEMODE + 1 + 0 + read-write + + + TRACEIOEN + desc TRACEIOEN + 2 + 2 + read-write + + + + + + + DCU1 + desc DCU + 0x40052000 + + 0x0 + 0x1C + + + + CTL + desc CTL + 0x0 + 32 + read-write + 0x80000000 + 0x8000011F + + + MODE + desc MODE + 2 + 0 + read-write + + + DATASIZE + desc DATASIZE + 4 + 3 + read-write + + + COMP_TRG + desc COMP_TRG + 8 + 8 + read-write + + + INTEN + desc INTEN + 31 + 31 + read-write + + + + + FLAG + desc FLAG + 0x4 + 32 + read-only + 0x0 + 0x7F + + + FLAG_OP + desc FLAG_OP + 0 + 0 + read-only + + + FLAG_LS2 + desc FLAG_LS2 + 1 + 1 + read-only + + + FLAG_EQ2 + desc FLAG_EQ2 + 2 + 2 + read-only + + + FLAG_GT2 + desc FLAG_GT2 + 3 + 3 + read-only + + + FLAG_LS1 + desc FLAG_LS1 + 4 + 4 + read-only + + + FLAG_EQ1 + desc FLAG_EQ1 + 5 + 5 + read-only + + + FLAG_GT1 + desc FLAG_GT1 + 6 + 6 + read-only + + + + + DATA0 + desc DATA0 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA1 + desc DATA1 + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA2 + desc DATA2 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + FLAGCLR + desc FLAGCLR + 0x14 + 32 + write-only + 0x0 + 0x7F + + + CLR_OP + desc CLR_OP + 0 + 0 + write-only + + + CLR_LS2 + desc CLR_LS2 + 1 + 1 + write-only + + + CLR_EQ2 + desc CLR_EQ2 + 2 + 2 + write-only + + + CLR_GT2 + desc CLR_GT2 + 3 + 3 + write-only + + + CLR_LS1 + desc CLR_LS1 + 4 + 4 + write-only + + + CLR_EQ1 + desc CLR_EQ1 + 5 + 5 + write-only + + + CLR_GT1 + desc CLR_GT1 + 6 + 6 + write-only + + + + + INTSEL + desc INTSEL + 0x18 + 32 + read-write + 0x0 + 0x1FF + + + INT_OP + desc INT_OP + 0 + 0 + read-write + + + INT_LS2 + desc INT_LS2 + 1 + 1 + read-write + + + INT_EQ2 + desc INT_EQ2 + 2 + 2 + read-write + + + INT_GT2 + desc INT_GT2 + 3 + 3 + read-write + + + INT_LS1 + desc INT_LS1 + 4 + 4 + read-write + + + INT_EQ1 + desc INT_EQ1 + 5 + 5 + read-write + + + INT_GT1 + desc INT_GT1 + 6 + 6 + read-write + + + INT_WIN + desc INT_WIN + 8 + 7 + read-write + + + + + + + DCU2 + desc DCU + 0x40052400 + + 0x0 + 0x1C + + + + DCU3 + desc DCU + 0x40052800 + + 0x0 + 0x1C + + + + DCU4 + desc DCU + 0x40052C00 + + 0x0 + 0x1C + + + + DMA1 + desc DMA + 0x40053000 + + 0x0 + 0x120 + + + + EN + desc EN + 0x0 + 32 + read-write + 0x0 + 0x1 + + + EN + desc EN + 0 + 0 + read-write + + + + + INTSTAT0 + desc INTSTAT0 + 0x4 + 32 + read-only + 0x0 + 0xF000F + + + TRNERR + desc TRNERR + 3 + 0 + read-only + + + REQERR + desc REQERR + 19 + 16 + read-only + + + + + INTSTAT1 + desc INTSTAT1 + 0x8 + 32 + read-only + 0x0 + 0xF000F + + + TC + desc TC + 3 + 0 + read-only + + + BTC + desc BTC + 19 + 16 + read-only + + + + + INTMASK0 + desc INTMASK0 + 0xC + 32 + read-write + 0x0 + 0xF000F + + + MSKTRNERR + desc MSKTRNERR + 3 + 0 + read-write + + + MSKREQERR + desc MSKREQERR + 19 + 16 + read-write + + + + + INTMASK1 + desc INTMASK1 + 0x10 + 32 + read-write + 0x0 + 0xF000F + + + MSKTC + desc MSKTC + 3 + 0 + read-write + + + MSKBTC + desc MSKBTC + 19 + 16 + read-write + + + + + INTCLR0 + desc INTCLR0 + 0x14 + 32 + write-only + 0x0 + 0xF000F + + + CLRTRNERR + desc CLRTRNERR + 3 + 0 + write-only + + + CLRREQERR + desc CLRREQERR + 19 + 16 + write-only + + + + + INTCLR1 + desc INTCLR1 + 0x18 + 32 + write-only + 0x0 + 0xF000F + + + CLRTC + desc CLRTC + 3 + 0 + write-only + + + CLRBTC + desc CLRBTC + 19 + 16 + write-only + + + + + CHEN + desc CHEN + 0x1C + 32 + read-write + 0x0 + 0xF + + + CHEN + desc CHEN + 3 + 0 + read-write + + + + + REQSTAT + desc REQSTAT + 0x20 + 32 + read-only + 0x0 + 0x800F + + + CHREQ + desc CHREQ + 3 + 0 + read-only + + + RCFGREQ + desc RCFGREQ + 15 + 15 + read-only + + + + + CHSTAT + desc CHSTAT + 0x24 + 32 + read-only + 0x0 + 0xF0003 + + + DMAACT + desc DMAACT + 0 + 0 + read-only + + + RCFGACT + desc RCFGACT + 1 + 1 + read-only + + + CHACT + desc CHACT + 19 + 16 + read-only + + + + + RCFGCTL + desc RCFGCTL + 0x2C + 32 + read-write + 0x0 + 0x3F0F03 + + + RCFGEN + desc RCFGEN + 0 + 0 + read-write + + + RCFGLLP + desc RCFGLLP + 1 + 1 + read-write + + + RCFGCHS + desc RCFGCHS + 11 + 8 + read-write + + + SARMD + desc SARMD + 17 + 16 + read-write + + + DARMD + desc DARMD + 19 + 18 + read-write + + + CNTMD + desc CNTMD + 21 + 20 + read-write + + + + + SAR0 + desc SAR0 + 0x40 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR0 + desc DAR0 + 0x44 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL0 + desc DTCTL0 + 0x48 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT0 + desc RPT0 + 0x4C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB0 + desc RPTB0 + 0x4C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL0 + desc SNSEQCTL0 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB0 + desc SNSEQCTLB0 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL0 + desc DNSEQCTL0 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB0 + desc DNSEQCTLB0 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP0 + desc LLP0 + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL0 + desc CHCTL0 + 0x5C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR0 + desc MONSAR0 + 0x60 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR0 + desc MONDAR0 + 0x64 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL0 + desc MONDTCTL0 + 0x68 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT0 + desc MONRPT0 + 0x6C + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL0 + desc MONSNSEQCTL0 + 0x70 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL0 + desc MONDNSEQCTL0 + 0x74 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR1 + desc SAR1 + 0x80 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR1 + desc DAR1 + 0x84 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL1 + desc DTCTL1 + 0x88 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT1 + desc RPT1 + 0x8C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB1 + desc RPTB1 + 0x8C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL1 + desc SNSEQCTL1 + 0x90 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB1 + desc SNSEQCTLB1 + 0x90 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL1 + desc DNSEQCTL1 + 0x94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB1 + desc DNSEQCTLB1 + 0x94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP1 + desc LLP1 + 0x98 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL1 + desc CHCTL1 + 0x9C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR1 + desc MONSAR1 + 0xA0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR1 + desc MONDAR1 + 0xA4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL1 + desc MONDTCTL1 + 0xA8 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT1 + desc MONRPT1 + 0xAC + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL1 + desc MONSNSEQCTL1 + 0xB0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL1 + desc MONDNSEQCTL1 + 0xB4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR2 + desc SAR2 + 0xC0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR2 + desc DAR2 + 0xC4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL2 + desc DTCTL2 + 0xC8 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT2 + desc RPT2 + 0xCC + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB2 + desc RPTB2 + 0xCC + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL2 + desc SNSEQCTL2 + 0xD0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB2 + desc SNSEQCTLB2 + 0xD0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL2 + desc DNSEQCTL2 + 0xD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB2 + desc DNSEQCTLB2 + 0xD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP2 + desc LLP2 + 0xD8 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL2 + desc CHCTL2 + 0xDC + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR2 + desc MONSAR2 + 0xE0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR2 + desc MONDAR2 + 0xE4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL2 + desc MONDTCTL2 + 0xE8 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT2 + desc MONRPT2 + 0xEC + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL2 + desc MONSNSEQCTL2 + 0xF0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL2 + desc MONDNSEQCTL2 + 0xF4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR3 + desc SAR3 + 0x100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR3 + desc DAR3 + 0x104 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL3 + desc DTCTL3 + 0x108 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT3 + desc RPT3 + 0x10C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB3 + desc RPTB3 + 0x10C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL3 + desc SNSEQCTL3 + 0x110 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB3 + desc SNSEQCTLB3 + 0x110 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL3 + desc DNSEQCTL3 + 0x114 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB3 + desc DNSEQCTLB3 + 0x114 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP3 + desc LLP3 + 0x118 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL3 + desc CHCTL3 + 0x11C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR3 + desc MONSAR3 + 0x120 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR3 + desc MONDAR3 + 0x124 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL3 + desc MONDTCTL3 + 0x128 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT3 + desc MONRPT3 + 0x12C + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL3 + desc MONSNSEQCTL3 + 0x130 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL3 + desc MONDNSEQCTL3 + 0x134 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + + + DMA2 + desc DMA + 0x40053400 + + 0x0 + 0x120 + + + + EFM + desc EFM + 0x40010400 + + 0x0 + 0x208 + + + + FAPRT + desc FAPRT + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + FAPRT + desc FAPRT + 15 + 0 + read-write + + + + + FSTP + desc FSTP + 0x4 + 32 + read-write + 0x0 + 0x1 + + + FSTP + desc FSTP + 0 + 0 + read-write + + + + + FRMC + desc FRMC + 0x8 + 32 + read-write + 0x0 + 0x10101F1 + + + SLPMD + desc SLPMD + 0 + 0 + read-write + + + FLWT + desc FLWT + 7 + 4 + read-write + + + LVM + desc LVM + 8 + 8 + read-write + + + CACHE + desc CACHE + 16 + 16 + read-write + + + CRST + desc CRST + 24 + 24 + read-write + + + + + FWMC + desc FWMC + 0xC + 32 + read-write + 0x0 + 0x171 + + + PEMODE + desc PEMODE + 0 + 0 + read-write + + + PEMOD + desc PEMOD + 6 + 4 + read-write + + + BUSHLDCTL + desc BUSHLDCTL + 8 + 8 + read-write + + + + + FSR + desc FSR + 0x10 + 32 + read-only + 0x100 + 0x13F + + + PEWERR + desc PEWERR + 0 + 0 + read-only + + + PEPRTERR + desc PEPRTERR + 1 + 1 + read-only + + + PGSZERR + desc PGSZERR + 2 + 2 + read-only + + + PGMISMTCH + desc PGMISMTCH + 3 + 3 + read-only + + + OPTEND + desc OPTEND + 4 + 4 + read-only + + + COLERR + desc COLERR + 5 + 5 + read-only + + + RDY + desc RDY + 8 + 8 + read-only + + + + + FSCLR + desc FSCLR + 0x14 + 32 + read-write + 0x0 + 0x3F + + + PEWERRCLR + desc PEWERRCLR + 0 + 0 + read-write + + + PEPRTERRCLR + desc PEPRTERRCLR + 1 + 1 + read-write + + + PGSZERRCLR + desc PGSZERRCLR + 2 + 2 + read-write + + + PGMISMTCHCLR + desc PGMISMTCHCLR + 3 + 3 + read-write + + + OPTENDCLR + desc OPTENDCLR + 4 + 4 + read-write + + + COLERRCLR + desc COLERRCLR + 5 + 5 + read-write + + + + + FITE + desc FITE + 0x18 + 32 + read-write + 0x0 + 0x7 + + + PEERRITE + desc PEERRITE + 0 + 0 + read-write + + + OPTENDITE + desc OPTENDITE + 1 + 1 + read-write + + + COLERRITE + desc COLERRITE + 2 + 2 + read-write + + + + + FSWP + desc FSWP + 0x1C + 32 + read-only + 0x1 + 0x1 + + + FSWP + desc FSWP + 0 + 0 + read-only + + + + + FPMTSW + desc FPMTSW + 0x20 + 32 + read-write + 0x0 + 0x7FFFF + + + FPMTSW + desc FPMTSW + 18 + 0 + read-write + + + + + FPMTEW + desc FPMTEW + 0x24 + 32 + read-write + 0x0 + 0x7FFFF + + + FPMTEW + desc FPMTEW + 18 + 0 + read-write + + + + + UQID0 + desc UQID0 + 0x50 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + UQID1 + desc UQID1 + 0x54 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + UQID2 + desc UQID2 + 0x58 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MMF_REMPRT + desc MMF_REMPRT + 0x100 + 32 + read-write + 0x0 + 0xFFFF + + + REMPRT + desc REMPRT + 15 + 0 + read-write + + + + + MMF_REMCR0 + desc MMF_REMCR0 + 0x104 + 32 + read-write + 0x0 + 0x9FFFF01F + + + RMSIZE + desc RMSIZE + 4 + 0 + read-write + + + RMTADDR + desc RMTADDR + 28 + 12 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + MMF_REMCR1 + desc MMF_REMCR1 + 0x108 + 32 + read-write + 0x0 + 0x9FFFF01F + + + RMSIZE + desc RMSIZE + 4 + 0 + read-write + + + RMTADDR + desc RMTADDR + 28 + 12 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + + + EMB0 + desc EMB + 0x40017C00 + + 0x0 + 0x18 + + + + CTL + desc CTL + 0x0 + 32 + read-write + 0x0 + 0xF00001EF + + + PORTINEN + desc PORTINEN + 0 + 0 + read-write + + + CMPEN0 + desc CMPEN0 + 1 + 1 + read-write + + + CMPEN1 + desc CMPEN1 + 2 + 2 + read-write + + + CMPEN2 + desc CMPEN2 + 3 + 3 + read-write + + + OSCSTPEN + desc OSCSTPEN + 5 + 5 + read-write + + + PWMSEN0 + desc PWMSEN0 + 6 + 6 + read-write + + + PWMSEN1 + desc PWMSEN1 + 7 + 7 + read-write + + + PWMSEN2 + desc PWMSEN2 + 8 + 8 + read-write + + + NFSEL + desc NFSEL + 29 + 28 + read-write + + + NFEN + desc NFEN + 30 + 30 + read-write + + + INVSEL + desc INVSEL + 31 + 31 + read-write + + + + + PWMLV + desc PWMLV + 0x4 + 32 + read-write + 0x0 + 0x7 + + + PWMLV0 + desc PWMLV0 + 0 + 0 + read-write + + + PWMLV1 + desc PWMLV1 + 1 + 1 + read-write + + + PWMLV2 + desc PWMLV2 + 2 + 2 + read-write + + + + + SOE + desc SOE + 0x8 + 32 + read-write + 0x0 + 0x1 + + + SOE + desc SOE + 0 + 0 + read-write + + + + + STAT + desc STAT + 0xC + 32 + read-only + 0x0 + 0x3F + + + PORTINF + desc PORTINF + 0 + 0 + read-only + + + PWMSF + desc PWMSF + 1 + 1 + read-only + + + CMPF + desc CMPF + 2 + 2 + read-only + + + OSF + desc OSF + 3 + 3 + read-only + + + PORTINST + desc PORTINST + 4 + 4 + read-only + + + PWMST + desc PWMST + 5 + 5 + read-only + + + + + STATCLR + desc STATCLR + 0x10 + 32 + write-only + 0x0 + 0xF + + + PORTINFCLR + desc PORTINFCLR + 0 + 0 + write-only + + + PWMSFCLR + desc PWMSFCLR + 1 + 1 + write-only + + + CMPFCLR + desc CMPFCLR + 2 + 2 + write-only + + + OSFCLR + desc OSFCLR + 3 + 3 + write-only + + + + + INTEN + desc INTEN + 0x14 + 32 + read-write + 0x0 + 0xF + + + PORTINTEN + desc PORTINTEN + 0 + 0 + read-write + + + PWMINTEN + desc PWMINTEN + 1 + 1 + read-write + + + CMPINTEN + desc CMPINTEN + 2 + 2 + read-write + + + OSINTEN + desc OSINTEN + 3 + 3 + read-write + + + + + + + EMB1 + desc EMB + 0x40017C20 + + 0x0 + 0x18 + + + + EMB2 + desc EMB + 0x40017C40 + + 0x0 + 0x18 + + + + EMB3 + desc EMB + 0x40017C60 + + 0x0 + 0x18 + + + + FCM + desc FCM + 0x40048400 + + 0x0 + 0x24 + + + + LVR + desc LVR + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + LVR + desc LVR + 15 + 0 + read-write + + + + + UVR + desc UVR + 0x4 + 32 + read-write + 0x0 + 0xFFFF + + + UVR + desc UVR + 15 + 0 + read-write + + + + + CNTR + desc CNTR + 0x8 + 32 + read-only + 0x0 + 0xFFFF + + + CNTR + desc CNTR + 15 + 0 + read-only + + + + + STR + desc STR + 0xC + 32 + read-write + 0x0 + 0x1 + + + START + desc START + 0 + 0 + read-write + + + + + MCCR + desc MCCR + 0x10 + 32 + read-write + 0x0 + 0xF3 + + + MDIVS + desc MDIVS + 1 + 0 + read-write + + + MCKS + desc MCKS + 7 + 4 + read-write + + + + + RCCR + desc RCCR + 0x14 + 32 + read-write + 0x0 + 0xB3FB + + + RDIVS + desc RDIVS + 1 + 0 + read-write + + + RCKS + desc RCKS + 6 + 3 + read-write + + + INEXS + desc INEXS + 7 + 7 + read-write + + + DNFS + desc DNFS + 9 + 8 + read-write + + + EDGES + desc EDGES + 13 + 12 + read-write + + + EXREFE + desc EXREFE + 15 + 15 + read-write + + + + + RIER + desc RIER + 0x18 + 32 + read-write + 0x0 + 0x97 + + + ERRIE + desc ERRIE + 0 + 0 + read-write + + + MENDIE + desc MENDIE + 1 + 1 + read-write + + + OVFIE + desc OVFIE + 2 + 2 + read-write + + + ERRINTRS + desc ERRINTRS + 4 + 4 + read-write + + + ERRE + desc ERRE + 7 + 7 + read-write + + + + + SR + desc SR + 0x1C + 32 + read-only + 0x0 + 0x7 + + + ERRF + desc ERRF + 0 + 0 + read-only + + + MENDF + desc MENDF + 1 + 1 + read-only + + + OVF + desc OVF + 2 + 2 + read-only + + + + + CLR + desc CLR + 0x20 + 32 + write-only + 0x0 + 0x7 + + + ERRFCLR + desc ERRFCLR + 0 + 0 + write-only + + + MENDFCLR + desc MENDFCLR + 1 + 1 + write-only + + + OVFCLR + desc OVFCLR + 2 + 2 + write-only + + + + + + + GPIO + desc GPIO + 0x40053800 + + 0x0 + 0x54C + + + + PIDRA + desc PIDRA + 0x0 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRA + desc PODRA + 0x4 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERA + desc POERA + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRA + desc POSRA + 0x8 + 16 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PORRA + desc PORRA + 0xA + 16 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + POTRA + desc POTRA + 0xC + 16 + read-write + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + read-write + + + POT01 + desc POT01 + 1 + 1 + read-write + + + POT02 + desc POT02 + 2 + 2 + read-write + + + POT03 + desc POT03 + 3 + 3 + read-write + + + POT04 + desc POT04 + 4 + 4 + read-write + + + POT05 + desc POT05 + 5 + 5 + read-write + + + POT06 + desc POT06 + 6 + 6 + read-write + + + POT07 + desc POT07 + 7 + 7 + read-write + + + POT08 + desc POT08 + 8 + 8 + read-write + + + POT09 + desc POT09 + 9 + 9 + read-write + + + POT10 + desc POT10 + 10 + 10 + read-write + + + POT11 + desc POT11 + 11 + 11 + read-write + + + POT12 + desc POT12 + 12 + 12 + read-write + + + POT13 + desc POT13 + 13 + 13 + read-write + + + POT14 + desc POT14 + 14 + 14 + read-write + + + POT15 + desc POT15 + 15 + 15 + read-write + + + + + PIDRB + desc PIDRB + 0x10 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRB + desc PODRB + 0x14 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERB + desc POERB + 0x16 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRB + desc POSRB + 0x18 + 16 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PORRB + desc PORRB + 0x1A + 16 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + POTRB + desc POTRB + 0x1C + 16 + read-write + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + read-write + + + POT01 + desc POT01 + 1 + 1 + read-write + + + POT02 + desc POT02 + 2 + 2 + read-write + + + POT03 + desc POT03 + 3 + 3 + read-write + + + POT04 + desc POT04 + 4 + 4 + read-write + + + POT05 + desc POT05 + 5 + 5 + read-write + + + POT06 + desc POT06 + 6 + 6 + read-write + + + POT07 + desc POT07 + 7 + 7 + read-write + + + POT08 + desc POT08 + 8 + 8 + read-write + + + POT09 + desc POT09 + 9 + 9 + read-write + + + POT10 + desc POT10 + 10 + 10 + read-write + + + POT11 + desc POT11 + 11 + 11 + read-write + + + POT12 + desc POT12 + 12 + 12 + read-write + + + POT13 + desc POT13 + 13 + 13 + read-write + + + POT14 + desc POT14 + 14 + 14 + read-write + + + POT15 + desc POT15 + 15 + 15 + read-write + + + + + PIDRC + desc PIDRC + 0x20 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRC + desc PODRC + 0x24 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERC + desc POERC + 0x26 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRC + desc POSRC + 0x28 + 16 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PORRC + desc PORRC + 0x2A + 16 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + POTRC + desc POTRC + 0x2C + 16 + read-write + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + read-write + + + POT01 + desc POT01 + 1 + 1 + read-write + + + POT02 + desc POT02 + 2 + 2 + read-write + + + POT03 + desc POT03 + 3 + 3 + read-write + + + POT04 + desc POT04 + 4 + 4 + read-write + + + POT05 + desc POT05 + 5 + 5 + read-write + + + POT06 + desc POT06 + 6 + 6 + read-write + + + POT07 + desc POT07 + 7 + 7 + read-write + + + POT08 + desc POT08 + 8 + 8 + read-write + + + POT09 + desc POT09 + 9 + 9 + read-write + + + POT10 + desc POT10 + 10 + 10 + read-write + + + POT11 + desc POT11 + 11 + 11 + read-write + + + POT12 + desc POT12 + 12 + 12 + read-write + + + POT13 + desc POT13 + 13 + 13 + read-write + + + POT14 + desc POT14 + 14 + 14 + read-write + + + POT15 + desc POT15 + 15 + 15 + read-write + + + + + PIDRD + desc PIDRD + 0x30 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRD + desc PODRD + 0x34 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERD + desc POERD + 0x36 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRD + desc POSRD + 0x38 + 16 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PORRD + desc PORRD + 0x3A + 16 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + POTRD + desc POTRD + 0x3C + 16 + read-write + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + read-write + + + POT01 + desc POT01 + 1 + 1 + read-write + + + POT02 + desc POT02 + 2 + 2 + read-write + + + POT03 + desc POT03 + 3 + 3 + read-write + + + POT04 + desc POT04 + 4 + 4 + read-write + + + POT05 + desc POT05 + 5 + 5 + read-write + + + POT06 + desc POT06 + 6 + 6 + read-write + + + POT07 + desc POT07 + 7 + 7 + read-write + + + POT08 + desc POT08 + 8 + 8 + read-write + + + POT09 + desc POT09 + 9 + 9 + read-write + + + POT10 + desc POT10 + 10 + 10 + read-write + + + POT11 + desc POT11 + 11 + 11 + read-write + + + POT12 + desc POT12 + 12 + 12 + read-write + + + POT13 + desc POT13 + 13 + 13 + read-write + + + POT14 + desc POT14 + 14 + 14 + read-write + + + POT15 + desc POT15 + 15 + 15 + read-write + + + + + PIDRE + desc PIDRE + 0x40 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRE + desc PODRE + 0x44 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERE + desc POERE + 0x46 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRE + desc POSRE + 0x48 + 16 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PORRE + desc PORRE + 0x4A + 16 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + POTRE + desc POTRE + 0x4C + 16 + read-write + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + read-write + + + POT01 + desc POT01 + 1 + 1 + read-write + + + POT02 + desc POT02 + 2 + 2 + read-write + + + POT03 + desc POT03 + 3 + 3 + read-write + + + POT04 + desc POT04 + 4 + 4 + read-write + + + POT05 + desc POT05 + 5 + 5 + read-write + + + POT06 + desc POT06 + 6 + 6 + read-write + + + POT07 + desc POT07 + 7 + 7 + read-write + + + POT08 + desc POT08 + 8 + 8 + read-write + + + POT09 + desc POT09 + 9 + 9 + read-write + + + POT10 + desc POT10 + 10 + 10 + read-write + + + POT11 + desc POT11 + 11 + 11 + read-write + + + POT12 + desc POT12 + 12 + 12 + read-write + + + POT13 + desc POT13 + 13 + 13 + read-write + + + POT14 + desc POT14 + 14 + 14 + read-write + + + POT15 + desc POT15 + 15 + 15 + read-write + + + + + PIDRH + desc PIDRH + 0x50 + 16 + read-only + 0x0 + 0x7 + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + + + PODRH + desc PODRH + 0x54 + 16 + read-write + 0x0 + 0x7 + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + + + POERH + desc POERH + 0x56 + 16 + read-write + 0x0 + 0x7 + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + + + POSRH + desc POSRH + 0x58 + 16 + read-write + 0x0 + 0x7 + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + + + PORRH + desc PORRH + 0x5A + 16 + read-write + 0x0 + 0x7 + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + + + POTRH + desc POTRH + 0x5C + 16 + read-write + 0x0 + 0x7 + + + POT00 + desc POT00 + 0 + 0 + read-write + + + POT01 + desc POT01 + 1 + 1 + read-write + + + POT02 + desc POT02 + 2 + 2 + read-write + + + + + PSPCR + desc PSPCR + 0x3F4 + 16 + read-write + 0x0 + 0x1F + + + SPFE + desc SPFE + 4 + 0 + read-write + + + + + PCCR + desc PCCR + 0x3F8 + 16 + read-write + 0x0 + 0xC00F + + + BFSEL + desc BFSEL + 3 + 0 + read-write + + + RDWT + desc RDWT + 15 + 14 + read-write + + + + + PINAER + desc PINAER + 0x3FA + 16 + read-write + 0x0 + 0x3F + + + PINAE + desc PINAE + 5 + 0 + read-write + + + + + PWPR + desc PWPR + 0x3FC + 16 + read-write + 0x0 + 0xFF01 + + + WE + desc WE + 0 + 0 + read-write + + + WP + desc WP + 15 + 8 + write-only + + + + + PCRA0 + desc PCRA0 + 0x400 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA0 + desc PFSRA0 + 0x402 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA1 + desc PCRA1 + 0x404 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA1 + desc PFSRA1 + 0x406 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA2 + desc PCRA2 + 0x408 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA2 + desc PFSRA2 + 0x40A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA3 + desc PCRA3 + 0x40C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA3 + desc PFSRA3 + 0x40E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA4 + desc PCRA4 + 0x410 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA4 + desc PFSRA4 + 0x412 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA5 + desc PCRA5 + 0x414 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA5 + desc PFSRA5 + 0x416 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA6 + desc PCRA6 + 0x418 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA6 + desc PFSRA6 + 0x41A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA7 + desc PCRA7 + 0x41C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA7 + desc PFSRA7 + 0x41E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA8 + desc PCRA8 + 0x420 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA8 + desc PFSRA8 + 0x422 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA9 + desc PCRA9 + 0x424 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA9 + desc PFSRA9 + 0x426 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA10 + desc PCRA10 + 0x428 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA10 + desc PFSRA10 + 0x42A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA11 + desc PCRA11 + 0x42C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA11 + desc PFSRA11 + 0x42E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA12 + desc PCRA12 + 0x430 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA12 + desc PFSRA12 + 0x432 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA13 + desc PCRA13 + 0x434 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA13 + desc PFSRA13 + 0x436 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA14 + desc PCRA14 + 0x438 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA14 + desc PFSRA14 + 0x43A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA15 + desc PCRA15 + 0x43C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA15 + desc PFSRA15 + 0x43E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB0 + desc PCRB0 + 0x440 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB0 + desc PFSRB0 + 0x442 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB1 + desc PCRB1 + 0x444 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB1 + desc PFSRB1 + 0x446 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB2 + desc PCRB2 + 0x448 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB2 + desc PFSRB2 + 0x44A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB3 + desc PCRB3 + 0x44C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB3 + desc PFSRB3 + 0x44E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB4 + desc PCRB4 + 0x450 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB4 + desc PFSRB4 + 0x452 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB5 + desc PCRB5 + 0x454 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB5 + desc PFSRB5 + 0x456 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB6 + desc PCRB6 + 0x458 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB6 + desc PFSRB6 + 0x45A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB7 + desc PCRB7 + 0x45C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB7 + desc PFSRB7 + 0x45E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB8 + desc PCRB8 + 0x460 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB8 + desc PFSRB8 + 0x462 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB9 + desc PCRB9 + 0x464 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB9 + desc PFSRB9 + 0x466 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB10 + desc PCRB10 + 0x468 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB10 + desc PFSRB10 + 0x46A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB11 + desc PCRB11 + 0x46C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB11 + desc PFSRB11 + 0x46E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB12 + desc PCRB12 + 0x470 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB12 + desc PFSRB12 + 0x472 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB13 + desc PCRB13 + 0x474 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB13 + desc PFSRB13 + 0x476 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB14 + desc PCRB14 + 0x478 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB14 + desc PFSRB14 + 0x47A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB15 + desc PCRB15 + 0x47C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB15 + desc PFSRB15 + 0x47E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC0 + desc PCRC0 + 0x480 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC0 + desc PFSRC0 + 0x482 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC1 + desc PCRC1 + 0x484 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC1 + desc PFSRC1 + 0x486 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC2 + desc PCRC2 + 0x488 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC2 + desc PFSRC2 + 0x48A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC3 + desc PCRC3 + 0x48C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC3 + desc PFSRC3 + 0x48E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC4 + desc PCRC4 + 0x490 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC4 + desc PFSRC4 + 0x492 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC5 + desc PCRC5 + 0x494 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC5 + desc PFSRC5 + 0x496 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC6 + desc PCRC6 + 0x498 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC6 + desc PFSRC6 + 0x49A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC7 + desc PCRC7 + 0x49C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC7 + desc PFSRC7 + 0x49E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC8 + desc PCRC8 + 0x4A0 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC8 + desc PFSRC8 + 0x4A2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC9 + desc PCRC9 + 0x4A4 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC9 + desc PFSRC9 + 0x4A6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC10 + desc PCRC10 + 0x4A8 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC10 + desc PFSRC10 + 0x4AA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC11 + desc PCRC11 + 0x4AC + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC11 + desc PFSRC11 + 0x4AE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC12 + desc PCRC12 + 0x4B0 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC12 + desc PFSRC12 + 0x4B2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC13 + desc PCRC13 + 0x4B4 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC13 + desc PFSRC13 + 0x4B6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC14 + desc PCRC14 + 0x4B8 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC14 + desc PFSRC14 + 0x4BA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC15 + desc PCRC15 + 0x4BC + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC15 + desc PFSRC15 + 0x4BE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD0 + desc PCRD0 + 0x4C0 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD0 + desc PFSRD0 + 0x4C2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD1 + desc PCRD1 + 0x4C4 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD1 + desc PFSRD1 + 0x4C6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD2 + desc PCRD2 + 0x4C8 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD2 + desc PFSRD2 + 0x4CA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD3 + desc PCRD3 + 0x4CC + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD3 + desc PFSRD3 + 0x4CE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD4 + desc PCRD4 + 0x4D0 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD4 + desc PFSRD4 + 0x4D2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD5 + desc PCRD5 + 0x4D4 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD5 + desc PFSRD5 + 0x4D6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD6 + desc PCRD6 + 0x4D8 + 16 + read-write + 0x8100 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD6 + desc PFSRD6 + 0x4DA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD7 + desc PCRD7 + 0x4DC + 16 + read-write + 0x8100 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD7 + desc PFSRD7 + 0x4DE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD8 + desc PCRD8 + 0x4E0 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD8 + desc PFSRD8 + 0x4E2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD9 + desc PCRD9 + 0x4E4 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD9 + desc PFSRD9 + 0x4E6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD10 + desc PCRD10 + 0x4E8 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD10 + desc PFSRD10 + 0x4EA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD11 + desc PCRD11 + 0x4EC + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD11 + desc PFSRD11 + 0x4EE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD12 + desc PCRD12 + 0x4F0 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD12 + desc PFSRD12 + 0x4F2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD13 + desc PCRD13 + 0x4F4 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD13 + desc PFSRD13 + 0x4F6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD14 + desc PCRD14 + 0x4F8 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD14 + desc PFSRD14 + 0x4FA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD15 + desc PCRD15 + 0x4FC + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD15 + desc PFSRD15 + 0x4FE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE0 + desc PCRE0 + 0x500 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE0 + desc PFSRE0 + 0x502 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE1 + desc PCRE1 + 0x504 + 16 + read-write + 0x40 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE1 + desc PFSRE1 + 0x506 + 16 + read-write + 0xD + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE2 + desc PCRE2 + 0x508 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE2 + desc PFSRE2 + 0x50A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE3 + desc PCRE3 + 0x50C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE3 + desc PFSRE3 + 0x50E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE4 + desc PCRE4 + 0x510 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE4 + desc PFSRE4 + 0x512 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE5 + desc PCRE5 + 0x514 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE5 + desc PFSRE5 + 0x516 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE6 + desc PCRE6 + 0x518 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE6 + desc PFSRE6 + 0x51A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE7 + desc PCRE7 + 0x51C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE7 + desc PFSRE7 + 0x51E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE8 + desc PCRE8 + 0x520 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE8 + desc PFSRE8 + 0x522 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE9 + desc PCRE9 + 0x524 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE9 + desc PFSRE9 + 0x526 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE10 + desc PCRE10 + 0x528 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE10 + desc PFSRE10 + 0x52A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE11 + desc PCRE11 + 0x52C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE11 + desc PFSRE11 + 0x52E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE12 + desc PCRE12 + 0x530 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE12 + desc PFSRE12 + 0x532 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE13 + desc PCRE13 + 0x534 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE13 + desc PFSRE13 + 0x536 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE14 + desc PCRE14 + 0x538 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE14 + desc PFSRE14 + 0x53A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE15 + desc PCRE15 + 0x53C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE15 + desc PFSRE15 + 0x53E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH0 + desc PCRH0 + 0x540 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH0 + desc PFSRH0 + 0x542 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH1 + desc PCRH1 + 0x544 + 16 + read-write + 0x40 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH1 + desc PFSRH1 + 0x546 + 16 + read-write + 0xD + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH2 + desc PCRH2 + 0x548 + 16 + read-write + 0x50 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH2 + desc PFSRH2 + 0x54A + 16 + read-write + 0xD + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + + + HASH + desc HASH + 0x40008400 + + 0x0 + 0x80 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x3 + + + START + desc START + 0 + 0 + read-write + + + FST_GRP + desc FST_GRP + 1 + 1 + read-write + + + + + HR7 + desc HR7 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR6 + desc HR6 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR5 + desc HR5 + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR4 + desc HR4 + 0x1C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR3 + desc HR3 + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR2 + desc HR2 + 0x24 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR1 + desc HR1 + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR0 + desc HR0 + 0x2C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR15 + desc DR15 + 0x40 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR14 + desc DR14 + 0x44 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR13 + desc DR13 + 0x48 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR12 + desc DR12 + 0x4C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR11 + desc DR11 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR10 + desc DR10 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR9 + desc DR9 + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR8 + desc DR8 + 0x5C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR7 + desc DR7 + 0x60 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR6 + desc DR6 + 0x64 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR5 + desc DR5 + 0x68 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR4 + desc DR4 + 0x6C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR3 + desc DR3 + 0x70 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR2 + desc DR2 + 0x74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR1 + desc DR1 + 0x78 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR0 + desc DR0 + 0x7C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + I2C1 + desc I2C + 0x4004E000 + + 0x0 + 0x34 + + + + CR1 + desc CR1 + 0x0 + 32 + read-write + 0x40 + 0x87DF + + + PE + desc PE + 0 + 0 + read-write + + + SMBUS + desc SMBUS + 1 + 1 + read-write + + + SMBALRTEN + desc SMBALRTEN + 2 + 2 + read-write + + + SMBDEFAULTEN + desc SMBDEFAULTEN + 3 + 3 + read-write + + + SMBHOSTEN + desc SMBHOSTEN + 4 + 4 + read-write + + + GCEN + desc GCEN + 6 + 6 + read-write + + + RESTART + desc RESTART + 7 + 7 + read-write + + + START + desc START + 8 + 8 + read-write + + + STOP + desc STOP + 9 + 9 + read-write + + + ACK + desc ACK + 10 + 10 + read-write + + + SWRST + desc SWRST + 15 + 15 + read-write + + + + + CR2 + desc CR2 + 0x4 + 32 + read-write + 0x0 + 0xF052DF + + + STARTIE + desc STARTIE + 0 + 0 + read-write + + + SLADDR0IE + desc SLADDR0IE + 1 + 1 + read-write + + + SLADDR1IE + desc SLADDR1IE + 2 + 2 + read-write + + + TENDIE + desc TENDIE + 3 + 3 + read-write + + + STOPIE + desc STOPIE + 4 + 4 + read-write + + + RFULLIE + desc RFULLIE + 6 + 6 + read-write + + + TEMPTYIE + desc TEMPTYIE + 7 + 7 + read-write + + + ARLOIE + desc ARLOIE + 9 + 9 + read-write + + + NACKIE + desc NACKIE + 12 + 12 + read-write + + + TMOUTIE + desc TMOUTIE + 14 + 14 + read-write + + + GENCALLIE + desc GENCALLIE + 20 + 20 + read-write + + + SMBDEFAULTIE + desc SMBDEFAULTIE + 21 + 21 + read-write + + + SMBHOSTIE + desc SMBHOSTIE + 22 + 22 + read-write + + + SMBALRTIE + desc SMBALRTIE + 23 + 23 + read-write + + + + + CR3 + desc CR3 + 0x8 + 32 + read-write + 0x6 + 0x87 + + + TMOUTEN + desc TMOUTEN + 0 + 0 + read-write + + + LTMOUT + desc LTMOUT + 1 + 1 + read-write + + + HTMOUT + desc HTMOUT + 2 + 2 + read-write + + + FACKEN + desc FACKEN + 7 + 7 + read-write + + + + + CR4 + desc CR4 + 0xC + 32 + read-write + 0x300307 + 0x400 + + + BUSWAIT + desc BUSWAIT + 10 + 10 + read-write + + + + + SLR0 + desc SLR0 + 0x10 + 32 + read-write + 0x1000 + 0x93FF + + + SLADDR0 + desc SLADDR0 + 9 + 0 + read-write + + + SLADDR0EN + desc SLADDR0EN + 12 + 12 + read-write + + + ADDRMOD0 + desc ADDRMOD0 + 15 + 15 + read-write + + + + + SLR1 + desc SLR1 + 0x14 + 32 + read-write + 0x0 + 0x93FF + + + SLADDR1 + desc SLADDR1 + 9 + 0 + read-write + + + SLADDR1EN + desc SLADDR1EN + 12 + 12 + read-write + + + ADDRMOD1 + desc ADDRMOD1 + 15 + 15 + read-write + + + + + SLTR + desc SLTR + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + TOUTLOW + desc TOUTLOW + 15 + 0 + read-write + + + TOUTHIGH + desc TOUTHIGH + 31 + 16 + read-write + + + + + SR + desc SR + 0x1C + 32 + read-write + 0x0 + 0xF756DF + + + STARTF + desc STARTF + 0 + 0 + read-write + + + SLADDR0F + desc SLADDR0F + 1 + 1 + read-write + + + SLADDR1F + desc SLADDR1F + 2 + 2 + read-write + + + TENDF + desc TENDF + 3 + 3 + read-write + + + STOPF + desc STOPF + 4 + 4 + read-write + + + RFULLF + desc RFULLF + 6 + 6 + read-write + + + TEMPTYF + desc TEMPTYF + 7 + 7 + read-write + + + ARLOF + desc ARLOF + 9 + 9 + read-write + + + ACKRF + desc ACKRF + 10 + 10 + read-write + + + NACKF + desc NACKF + 12 + 12 + read-write + + + TMOUTF + desc TMOUTF + 14 + 14 + read-write + + + MSL + desc MSL + 16 + 16 + read-write + + + BUSY + desc BUSY + 17 + 17 + read-write + + + TRA + desc TRA + 18 + 18 + read-write + + + GENCALLF + desc GENCALLF + 20 + 20 + read-write + + + SMBDEFAULTF + desc SMBDEFAULTF + 21 + 21 + read-write + + + SMBHOSTF + desc SMBHOSTF + 22 + 22 + read-write + + + SMBALRTF + desc SMBALRTF + 23 + 23 + read-write + + + + + CLR + desc CLR + 0x20 + 32 + write-only + 0x0 + 0xF052DF + + + STARTFCLR + desc STARTFCLR + 0 + 0 + write-only + + + SLADDR0FCLR + desc SLADDR0FCLR + 1 + 1 + write-only + + + SLADDR1FCLR + desc SLADDR1FCLR + 2 + 2 + write-only + + + TENDFCLR + desc TENDFCLR + 3 + 3 + write-only + + + STOPFCLR + desc STOPFCLR + 4 + 4 + write-only + + + RFULLFCLR + desc RFULLFCLR + 6 + 6 + write-only + + + TEMPTYFCLR + desc TEMPTYFCLR + 7 + 7 + write-only + + + ARLOFCLR + desc ARLOFCLR + 9 + 9 + write-only + + + NACKFCLR + desc NACKFCLR + 12 + 12 + write-only + + + TMOUTFCLR + desc TMOUTFCLR + 14 + 14 + write-only + + + GENCALLFCLR + desc GENCALLFCLR + 20 + 20 + write-only + + + SMBDEFAULTFCLR + desc SMBDEFAULTFCLR + 21 + 21 + write-only + + + SMBHOSTFCLR + desc SMBHOSTFCLR + 22 + 22 + write-only + + + SMBALRTFCLR + desc SMBALRTFCLR + 23 + 23 + write-only + + + + + DTR + desc DTR + 0x24 + 8 + write-only + 0xFF + 0xFF + + + DT + desc DT + 7 + 0 + write-only + + + + + DRR + desc DRR + 0x28 + 8 + read-only + 0x0 + 0xFF + + + DR + desc DR + 7 + 0 + read-only + + + + + CCR + desc CCR + 0x2C + 32 + read-write + 0x1F1F + 0x71F1F + + + SLOWW + desc SLOWW + 4 + 0 + read-write + + + SHIGHW + desc SHIGHW + 12 + 8 + read-write + + + FREQ + desc FREQ + 18 + 16 + read-write + + + + + FLTR + desc FLTR + 0x30 + 32 + read-write + 0x10 + 0x33 + + + DNF + desc DNF + 1 + 0 + read-write + + + DNFEN + desc DNFEN + 4 + 4 + read-write + + + ANFEN + desc ANFEN + 5 + 5 + read-write + + + + + + + I2C2 + desc I2C + 0x4004E400 + + 0x0 + 0x34 + + + + I2C3 + desc I2C + 0x4004E800 + + 0x0 + 0x34 + + + + I2S1 + desc I2S + 0x4001E000 + + 0x0 + 0x1C + + + + CTRL + desc CTRL + 0x0 + 32 + read-write + 0x2200 + 0xFF77FF + + + TXE + desc TXE + 0 + 0 + read-write + + + TXIE + desc TXIE + 1 + 1 + read-write + + + RXE + desc RXE + 2 + 2 + read-write + + + RXIE + desc RXIE + 3 + 3 + read-write + + + EIE + desc EIE + 4 + 4 + read-write + + + WMS + desc WMS + 5 + 5 + read-write + + + ODD + desc ODD + 6 + 6 + read-write + + + MCKOE + desc MCKOE + 7 + 7 + read-write + + + TXBIRQWL + desc TXBIRQWL + 10 + 8 + read-write + + + RXBIRQWL + desc RXBIRQWL + 14 + 12 + read-write + + + FIFOR + desc FIFOR + 16 + 16 + read-write + + + CODECRC + desc CODECRC + 17 + 17 + read-write + + + I2SPLLSEL + desc I2SPLLSEL + 18 + 18 + read-write + + + SDOE + desc SDOE + 19 + 19 + read-write + + + LRCKOE + desc LRCKOE + 20 + 20 + read-write + + + CKOE + desc CKOE + 21 + 21 + read-write + + + DUPLEX + desc DUPLEX + 22 + 22 + read-write + + + CLKSEL + desc CLKSEL + 23 + 23 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-only + 0x14 + 0x3F + + + TXBA + desc TXBA + 0 + 0 + read-only + + + RXBA + desc RXBA + 1 + 1 + read-only + + + TXBE + desc TXBE + 2 + 2 + read-only + + + TXBF + desc TXBF + 3 + 3 + read-only + + + RXBE + desc RXBE + 4 + 4 + read-only + + + RXBF + desc RXBF + 5 + 5 + read-only + + + + + ER + desc ER + 0x8 + 32 + read-write + 0x0 + 0x3 + + + TXERR + desc TXERR + 0 + 0 + read-write + + + RXERR + desc RXERR + 1 + 1 + read-write + + + + + CFGR + desc CFGR + 0xC + 32 + read-write + 0x0 + 0x3F + + + I2SSTD + desc I2SSTD + 1 + 0 + read-write + + + DATLEN + desc DATLEN + 3 + 2 + read-write + + + CHLEN + desc CHLEN + 4 + 4 + read-write + + + PCMSYNC + desc PCMSYNC + 5 + 5 + read-write + + + + + TXBUF + desc TXBUF + 0x10 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + RXBUF + desc RXBUF + 0x14 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PR + desc PR + 0x18 + 32 + read-write + 0x2 + 0xFF + + + I2SDIV + desc I2SDIV + 7 + 0 + read-write + + + + + + + I2S2 + desc I2S + 0x4001E400 + + 0x0 + 0x1C + + + + I2S3 + desc I2S + 0x40022000 + + 0x0 + 0x1C + + + + I2S4 + desc I2S + 0x40022400 + + 0x0 + 0x1C + + + + ICG + desc ICG + 0x00000400 + + 0x0 + 0x20 + + + + ICG0 + desc ICG0 + 0x0 + 32 + read-only + 0xFFFFFFFF + 0x1FFF1FFF + + + SWDTAUTS + desc SWDTAUTS + 0 + 0 + read-only + + + SWDTITS + desc SWDTITS + 1 + 1 + read-only + + + SWDTPERI + desc SWDTPERI + 3 + 2 + read-only + + + SWDTCKS + desc SWDTCKS + 7 + 4 + read-only + + + SWDTWDPT + desc SWDTWDPT + 11 + 8 + read-only + + + SWDTSLPOFF + desc SWDTSLPOFF + 12 + 12 + read-only + + + WDTAUTS + desc WDTAUTS + 16 + 16 + read-only + + + WDTITS + desc WDTITS + 17 + 17 + read-only + + + WDTPERI + desc WDTPERI + 19 + 18 + read-only + + + WDTCKS + desc WDTCKS + 23 + 20 + read-only + + + WDTWDPT + desc WDTWDPT + 27 + 24 + read-only + + + WDTSLPOFF + desc WDTSLPOFF + 28 + 28 + read-only + + + + + ICG1 + desc ICG1 + 0x4 + 32 + read-only + 0xFFFFFFFF + 0xFC070101 + + + HRCFREQSEL + desc HRCFREQSEL + 0 + 0 + read-only + + + HRCSTOP + desc HRCSTOP + 8 + 8 + read-only + + + BOR_LEV + desc BOR_LEV + 17 + 16 + read-only + + + BORDIS + desc BORDIS + 18 + 18 + read-only + + + SMPCLK + desc SMPCLK + 27 + 26 + read-only + + + NMITRG + desc NMITRG + 28 + 28 + read-only + + + NMIEN + desc NMIEN + 29 + 29 + read-only + + + NFEN + desc NFEN + 30 + 30 + read-only + + + NMIICGEN + desc NMIICGEN + 31 + 31 + read-only + + + + + ICG2 + desc ICG2 + 0x8 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + ICG3 + desc ICG3 + 0xC + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + ICG4 + desc ICG4 + 0x10 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + ICG5 + desc ICG5 + 0x14 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + ICG6 + desc ICG6 + 0x18 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + ICG7 + desc ICG7 + 0x1C + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + + + INTC + desc INTC + 0x40051000 + + 0x0 + 0x2A8 + + + + NMICR + desc NMICR + 0x0 + 32 + read-write + 0x0 + 0xB1 + + + NMITRG + desc NMITRG + 0 + 0 + read-write + + + NSMPCLK + desc NSMPCLK + 5 + 4 + read-write + + + NFEN + desc NFEN + 7 + 7 + read-write + + + + + NMIENR + desc NMIENR + 0x4 + 32 + read-write + 0x0 + 0xF2F + + + NMIENR + desc NMIENR + 0 + 0 + read-write + + + SWDTENR + desc SWDTENR + 1 + 1 + read-write + + + PVD1ENR + desc PVD1ENR + 2 + 2 + read-write + + + PVD2ENR + desc PVD2ENR + 3 + 3 + read-write + + + XTALSTPENR + desc XTALSTPENR + 5 + 5 + read-write + + + REPENR + desc REPENR + 8 + 8 + read-write + + + RECCENR + desc RECCENR + 9 + 9 + read-write + + + BUSMENR + desc BUSMENR + 10 + 10 + read-write + + + WDTENR + desc WDTENR + 11 + 11 + read-write + + + + + NMIFR + desc NMIFR + 0x8 + 32 + read-write + 0x0 + 0xF2F + + + NMIFR + desc NMIFR + 0 + 0 + read-write + + + SWDTFR + desc SWDTFR + 1 + 1 + read-write + + + PVD1FR + desc PVD1FR + 2 + 2 + read-write + + + PVD2FR + desc PVD2FR + 3 + 3 + read-write + + + XTALSTPFR + desc XTALSTPFR + 5 + 5 + read-write + + + REPFR + desc REPFR + 8 + 8 + read-write + + + RECCFR + desc RECCFR + 9 + 9 + read-write + + + BUSMFR + desc BUSMFR + 10 + 10 + read-write + + + WDTFR + desc WDTFR + 11 + 11 + read-write + + + + + NMICFR + desc NMICFR + 0xC + 32 + read-write + 0x0 + 0xF2F + + + NMICFR + desc NMICFR + 0 + 0 + read-write + + + SWDTCFR + desc SWDTCFR + 1 + 1 + read-write + + + PVD1CFR + desc PVD1CFR + 2 + 2 + read-write + + + PVD2CFR + desc PVD2CFR + 3 + 3 + read-write + + + XTALSTPCFR + desc XTALSTPCFR + 5 + 5 + read-write + + + REPCFR + desc REPCFR + 8 + 8 + read-write + + + RECCCFR + desc RECCCFR + 9 + 9 + read-write + + + BUSMCFR + desc BUSMCFR + 10 + 10 + read-write + + + WDTCFR + desc WDTCFR + 11 + 11 + read-write + + + + + EIRQCR0 + desc EIRQCR0 + 0x10 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR1 + desc EIRQCR1 + 0x14 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR2 + desc EIRQCR2 + 0x18 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR3 + desc EIRQCR3 + 0x1C + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR4 + desc EIRQCR4 + 0x20 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR5 + desc EIRQCR5 + 0x24 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR6 + desc EIRQCR6 + 0x28 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR7 + desc EIRQCR7 + 0x2C + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR8 + desc EIRQCR8 + 0x30 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR9 + desc EIRQCR9 + 0x34 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR10 + desc EIRQCR10 + 0x38 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR11 + desc EIRQCR11 + 0x3C + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR12 + desc EIRQCR12 + 0x40 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR13 + desc EIRQCR13 + 0x44 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR14 + desc EIRQCR14 + 0x48 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR15 + desc EIRQCR15 + 0x4C + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + WUPEN + desc WUPEN + 0x50 + 32 + read-write + 0x0 + 0x2FFFFFF + + + EIRQWUEN + desc EIRQWUEN + 15 + 0 + read-write + + + SWDTWUEN + desc SWDTWUEN + 16 + 16 + read-write + + + PVD1WUEN + desc PVD1WUEN + 17 + 17 + read-write + + + PVD2WUEN + desc PVD2WUEN + 18 + 18 + read-write + + + CMPI0WUEN + desc CMPI0WUEN + 19 + 19 + read-write + + + WKTMWUEN + desc WKTMWUEN + 20 + 20 + read-write + + + RTCALMWUEN + desc RTCALMWUEN + 21 + 21 + read-write + + + RTCPRDWUEN + desc RTCPRDWUEN + 22 + 22 + read-write + + + TMR0WUEN + desc TMR0WUEN + 23 + 23 + read-write + + + RXWUEN + desc RXWUEN + 25 + 25 + read-write + + + + + EIRQFR + desc EIRQFR + 0x54 + 32 + read-write + 0x0 + 0xFFFF + + + EIRQFR0 + desc EIRQFR0 + 0 + 0 + read-write + + + EIRQFR1 + desc EIRQFR1 + 1 + 1 + read-write + + + EIRQFR2 + desc EIRQFR2 + 2 + 2 + read-write + + + EIRQFR3 + desc EIRQFR3 + 3 + 3 + read-write + + + EIRQFR4 + desc EIRQFR4 + 4 + 4 + read-write + + + EIRQFR5 + desc EIRQFR5 + 5 + 5 + read-write + + + EIRQFR6 + desc EIRQFR6 + 6 + 6 + read-write + + + EIRQFR7 + desc EIRQFR7 + 7 + 7 + read-write + + + EIRQFR8 + desc EIRQFR8 + 8 + 8 + read-write + + + EIRQFR9 + desc EIRQFR9 + 9 + 9 + read-write + + + EIRQFR10 + desc EIRQFR10 + 10 + 10 + read-write + + + EIRQFR11 + desc EIRQFR11 + 11 + 11 + read-write + + + EIRQFR12 + desc EIRQFR12 + 12 + 12 + read-write + + + EIRQFR13 + desc EIRQFR13 + 13 + 13 + read-write + + + EIRQFR14 + desc EIRQFR14 + 14 + 14 + read-write + + + EIRQFR15 + desc EIRQFR15 + 15 + 15 + read-write + + + + + EIRQCFR + desc EIRQCFR + 0x58 + 32 + read-write + 0x0 + 0xFFFF + + + EIRQCFR0 + desc EIRQCFR0 + 0 + 0 + read-write + + + EIRQCFR1 + desc EIRQCFR1 + 1 + 1 + read-write + + + EIRQCFR2 + desc EIRQCFR2 + 2 + 2 + read-write + + + EIRQCFR3 + desc EIRQCFR3 + 3 + 3 + read-write + + + EIRQCFR4 + desc EIRQCFR4 + 4 + 4 + read-write + + + EIRQCFR5 + desc EIRQCFR5 + 5 + 5 + read-write + + + EIRQCFR6 + desc EIRQCFR6 + 6 + 6 + read-write + + + EIRQCFR7 + desc EIRQCFR7 + 7 + 7 + read-write + + + EIRQCFR8 + desc EIRQCFR8 + 8 + 8 + read-write + + + EIRQCFR9 + desc EIRQCFR9 + 9 + 9 + read-write + + + EIRQCFR10 + desc EIRQCFR10 + 10 + 10 + read-write + + + EIRQCFR11 + desc EIRQCFR11 + 11 + 11 + read-write + + + EIRQCFR12 + desc EIRQCFR12 + 12 + 12 + read-write + + + EIRQCFR13 + desc EIRQCFR13 + 13 + 13 + read-write + + + EIRQCFR14 + desc EIRQCFR14 + 14 + 14 + read-write + + + EIRQCFR15 + desc EIRQCFR15 + 15 + 15 + read-write + + + + + SEL0 + desc SEL0 + 0x5C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL1 + desc SEL1 + 0x60 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL2 + desc SEL2 + 0x64 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL3 + desc SEL3 + 0x68 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL4 + desc SEL4 + 0x6C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL5 + desc SEL5 + 0x70 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL6 + desc SEL6 + 0x74 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL7 + desc SEL7 + 0x78 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL8 + desc SEL8 + 0x7C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL9 + desc SEL9 + 0x80 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL10 + desc SEL10 + 0x84 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL11 + desc SEL11 + 0x88 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL12 + desc SEL12 + 0x8C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL13 + desc SEL13 + 0x90 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL14 + desc SEL14 + 0x94 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL15 + desc SEL15 + 0x98 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL16 + desc SEL16 + 0x9C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL17 + desc SEL17 + 0xA0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL18 + desc SEL18 + 0xA4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL19 + desc SEL19 + 0xA8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL20 + desc SEL20 + 0xAC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL21 + desc SEL21 + 0xB0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL22 + desc SEL22 + 0xB4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL23 + desc SEL23 + 0xB8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL24 + desc SEL24 + 0xBC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL25 + desc SEL25 + 0xC0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL26 + desc SEL26 + 0xC4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL27 + desc SEL27 + 0xC8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL28 + desc SEL28 + 0xCC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL29 + desc SEL29 + 0xD0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL30 + desc SEL30 + 0xD4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL31 + desc SEL31 + 0xD8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL32 + desc SEL32 + 0xDC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL33 + desc SEL33 + 0xE0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL34 + desc SEL34 + 0xE4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL35 + desc SEL35 + 0xE8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL36 + desc SEL36 + 0xEC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL37 + desc SEL37 + 0xF0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL38 + desc SEL38 + 0xF4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL39 + desc SEL39 + 0xF8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL40 + desc SEL40 + 0xFC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL41 + desc SEL41 + 0x100 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL42 + desc SEL42 + 0x104 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL43 + desc SEL43 + 0x108 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL44 + desc SEL44 + 0x10C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL45 + desc SEL45 + 0x110 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL46 + desc SEL46 + 0x114 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL47 + desc SEL47 + 0x118 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL48 + desc SEL48 + 0x11C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL49 + desc SEL49 + 0x120 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL50 + desc SEL50 + 0x124 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL51 + desc SEL51 + 0x128 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL52 + desc SEL52 + 0x12C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL53 + desc SEL53 + 0x130 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL54 + desc SEL54 + 0x134 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL55 + desc SEL55 + 0x138 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL56 + desc SEL56 + 0x13C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL57 + desc SEL57 + 0x140 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL58 + desc SEL58 + 0x144 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL59 + desc SEL59 + 0x148 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL60 + desc SEL60 + 0x14C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL61 + desc SEL61 + 0x150 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL62 + desc SEL62 + 0x154 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL63 + desc SEL63 + 0x158 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL64 + desc SEL64 + 0x15C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL65 + desc SEL65 + 0x160 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL66 + desc SEL66 + 0x164 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL67 + desc SEL67 + 0x168 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL68 + desc SEL68 + 0x16C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL69 + desc SEL69 + 0x170 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL70 + desc SEL70 + 0x174 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL71 + desc SEL71 + 0x178 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL72 + desc SEL72 + 0x17C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL73 + desc SEL73 + 0x180 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL74 + desc SEL74 + 0x184 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL75 + desc SEL75 + 0x188 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL76 + desc SEL76 + 0x18C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL77 + desc SEL77 + 0x190 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL78 + desc SEL78 + 0x194 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL79 + desc SEL79 + 0x198 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL80 + desc SEL80 + 0x19C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL81 + desc SEL81 + 0x1A0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL82 + desc SEL82 + 0x1A4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL83 + desc SEL83 + 0x1A8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL84 + desc SEL84 + 0x1AC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL85 + desc SEL85 + 0x1B0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL86 + desc SEL86 + 0x1B4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL87 + desc SEL87 + 0x1B8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL88 + desc SEL88 + 0x1BC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL89 + desc SEL89 + 0x1C0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL90 + desc SEL90 + 0x1C4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL91 + desc SEL91 + 0x1C8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL92 + desc SEL92 + 0x1CC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL93 + desc SEL93 + 0x1D0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL94 + desc SEL94 + 0x1D4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL95 + desc SEL95 + 0x1D8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL96 + desc SEL96 + 0x1DC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL97 + desc SEL97 + 0x1E0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL98 + desc SEL98 + 0x1E4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL99 + desc SEL99 + 0x1E8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL100 + desc SEL100 + 0x1EC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL101 + desc SEL101 + 0x1F0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL102 + desc SEL102 + 0x1F4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL103 + desc SEL103 + 0x1F8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL104 + desc SEL104 + 0x1FC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL105 + desc SEL105 + 0x200 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL106 + desc SEL106 + 0x204 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL107 + desc SEL107 + 0x208 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL108 + desc SEL108 + 0x20C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL109 + desc SEL109 + 0x210 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL110 + desc SEL110 + 0x214 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL111 + desc SEL111 + 0x218 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL112 + desc SEL112 + 0x21C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL113 + desc SEL113 + 0x220 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL114 + desc SEL114 + 0x224 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL115 + desc SEL115 + 0x228 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL116 + desc SEL116 + 0x22C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL117 + desc SEL117 + 0x230 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL118 + desc SEL118 + 0x234 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL119 + desc SEL119 + 0x238 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL120 + desc SEL120 + 0x23C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL121 + desc SEL121 + 0x240 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL122 + desc SEL122 + 0x244 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL123 + desc SEL123 + 0x248 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL124 + desc SEL124 + 0x24C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL125 + desc SEL125 + 0x250 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL126 + desc SEL126 + 0x254 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL127 + desc SEL127 + 0x258 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + VSSEL128 + desc VSSEL128 + 0x25C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL129 + desc VSSEL129 + 0x260 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL130 + desc VSSEL130 + 0x264 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL131 + desc VSSEL131 + 0x268 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL132 + desc VSSEL132 + 0x26C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL133 + desc VSSEL133 + 0x270 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL134 + desc VSSEL134 + 0x274 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL135 + desc VSSEL135 + 0x278 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL136 + desc VSSEL136 + 0x27C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL137 + desc VSSEL137 + 0x280 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL138 + desc VSSEL138 + 0x284 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL139 + desc VSSEL139 + 0x288 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL140 + desc VSSEL140 + 0x28C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL141 + desc VSSEL141 + 0x290 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL142 + desc VSSEL142 + 0x294 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL143 + desc VSSEL143 + 0x298 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + SWIER + desc SWIER + 0x29C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SWIE0 + desc SWIE0 + 0 + 0 + read-write + + + SWIE1 + desc SWIE1 + 1 + 1 + read-write + + + SWIE2 + desc SWIE2 + 2 + 2 + read-write + + + SWIE3 + desc SWIE3 + 3 + 3 + read-write + + + SWIE4 + desc SWIE4 + 4 + 4 + read-write + + + SWIE5 + desc SWIE5 + 5 + 5 + read-write + + + SWIE6 + desc SWIE6 + 6 + 6 + read-write + + + SWIE7 + desc SWIE7 + 7 + 7 + read-write + + + SWIE8 + desc SWIE8 + 8 + 8 + read-write + + + SWIE9 + desc SWIE9 + 9 + 9 + read-write + + + SWIE10 + desc SWIE10 + 10 + 10 + read-write + + + SWIE11 + desc SWIE11 + 11 + 11 + read-write + + + SWIE12 + desc SWIE12 + 12 + 12 + read-write + + + SWIE13 + desc SWIE13 + 13 + 13 + read-write + + + SWIE14 + desc SWIE14 + 14 + 14 + read-write + + + SWIE15 + desc SWIE15 + 15 + 15 + read-write + + + SWIE16 + desc SWIE16 + 16 + 16 + read-write + + + SWIE17 + desc SWIE17 + 17 + 17 + read-write + + + SWIE18 + desc SWIE18 + 18 + 18 + read-write + + + SWIE19 + desc SWIE19 + 19 + 19 + read-write + + + SWIE20 + desc SWIE20 + 20 + 20 + read-write + + + SWIE21 + desc SWIE21 + 21 + 21 + read-write + + + SWIE22 + desc SWIE22 + 22 + 22 + read-write + + + SWIE23 + desc SWIE23 + 23 + 23 + read-write + + + SWIE24 + desc SWIE24 + 24 + 24 + read-write + + + SWIE25 + desc SWIE25 + 25 + 25 + read-write + + + SWIE26 + desc SWIE26 + 26 + 26 + read-write + + + SWIE27 + desc SWIE27 + 27 + 27 + read-write + + + SWIE28 + desc SWIE28 + 28 + 28 + read-write + + + SWIE29 + desc SWIE29 + 29 + 29 + read-write + + + SWIE30 + desc SWIE30 + 30 + 30 + read-write + + + SWIE31 + desc SWIE31 + 31 + 31 + read-write + + + + + EVTER + desc EVTER + 0x2A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + EVTE0 + desc EVTE0 + 0 + 0 + read-write + + + EVTE1 + desc EVTE1 + 1 + 1 + read-write + + + EVTE2 + desc EVTE2 + 2 + 2 + read-write + + + EVTE3 + desc EVTE3 + 3 + 3 + read-write + + + EVTE4 + desc EVTE4 + 4 + 4 + read-write + + + EVTE5 + desc EVTE5 + 5 + 5 + read-write + + + EVTE6 + desc EVTE6 + 6 + 6 + read-write + + + EVTE7 + desc EVTE7 + 7 + 7 + read-write + + + EVTE8 + desc EVTE8 + 8 + 8 + read-write + + + EVTE9 + desc EVTE9 + 9 + 9 + read-write + + + EVTE10 + desc EVTE10 + 10 + 10 + read-write + + + EVTE11 + desc EVTE11 + 11 + 11 + read-write + + + EVTE12 + desc EVTE12 + 12 + 12 + read-write + + + EVTE13 + desc EVTE13 + 13 + 13 + read-write + + + EVTE14 + desc EVTE14 + 14 + 14 + read-write + + + EVTE15 + desc EVTE15 + 15 + 15 + read-write + + + EVTE16 + desc EVTE16 + 16 + 16 + read-write + + + EVTE17 + desc EVTE17 + 17 + 17 + read-write + + + EVTE18 + desc EVTE18 + 18 + 18 + read-write + + + EVTE19 + desc EVTE19 + 19 + 19 + read-write + + + EVTE20 + desc EVTE20 + 20 + 20 + read-write + + + EVTE21 + desc EVTE21 + 21 + 21 + read-write + + + EVTE22 + desc EVTE22 + 22 + 22 + read-write + + + EVTE23 + desc EVTE23 + 23 + 23 + read-write + + + EVTE24 + desc EVTE24 + 24 + 24 + read-write + + + EVTE25 + desc EVTE25 + 25 + 25 + read-write + + + EVTE26 + desc EVTE26 + 26 + 26 + read-write + + + EVTE27 + desc EVTE27 + 27 + 27 + read-write + + + EVTE28 + desc EVTE28 + 28 + 28 + read-write + + + EVTE29 + desc EVTE29 + 29 + 29 + read-write + + + EVTE30 + desc EVTE30 + 30 + 30 + read-write + + + EVTE31 + desc EVTE31 + 31 + 31 + read-write + + + + + IER + desc IER + 0x2A4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + IER0 + desc IER0 + 0 + 0 + read-write + + + IER1 + desc IER1 + 1 + 1 + read-write + + + IER2 + desc IER2 + 2 + 2 + read-write + + + IER3 + desc IER3 + 3 + 3 + read-write + + + IER4 + desc IER4 + 4 + 4 + read-write + + + IER5 + desc IER5 + 5 + 5 + read-write + + + IER6 + desc IER6 + 6 + 6 + read-write + + + IER7 + desc IER7 + 7 + 7 + read-write + + + IER8 + desc IER8 + 8 + 8 + read-write + + + IER9 + desc IER9 + 9 + 9 + read-write + + + IER10 + desc IER10 + 10 + 10 + read-write + + + IER11 + desc IER11 + 11 + 11 + read-write + + + IER12 + desc IER12 + 12 + 12 + read-write + + + IER13 + desc IER13 + 13 + 13 + read-write + + + IER14 + desc IER14 + 14 + 14 + read-write + + + IER15 + desc IER15 + 15 + 15 + read-write + + + IER16 + desc IER16 + 16 + 16 + read-write + + + IER17 + desc IER17 + 17 + 17 + read-write + + + IER18 + desc IER18 + 18 + 18 + read-write + + + IER19 + desc IER19 + 19 + 19 + read-write + + + IER20 + desc IER20 + 20 + 20 + read-write + + + IER21 + desc IER21 + 21 + 21 + read-write + + + IER22 + desc IER22 + 22 + 22 + read-write + + + IER23 + desc IER23 + 23 + 23 + read-write + + + IER24 + desc IER24 + 24 + 24 + read-write + + + IER25 + desc IER25 + 25 + 25 + read-write + + + IER26 + desc IER26 + 26 + 26 + read-write + + + IER27 + desc IER27 + 27 + 27 + read-write + + + IER28 + desc IER28 + 28 + 28 + read-write + + + IER29 + desc IER29 + 29 + 29 + read-write + + + IER30 + desc IER30 + 30 + 30 + read-write + + + IER31 + desc IER31 + 31 + 31 + read-write + + + + + + + KEYSCAN + desc KEYSCAN + 0x40050C00 + + 0x0 + 0xC + + + + SCR + desc SCR + 0x0 + 32 + read-write + 0x0 + 0xFF37FFFF + + + KEYINSEL + desc KEYINSEL + 15 + 0 + read-write + + + KEYOUTSEL + desc KEYOUTSEL + 18 + 16 + read-write + + + CKSEL + desc CKSEL + 21 + 20 + read-write + + + T_LLEVEL + desc T_LLEVEL + 28 + 24 + read-write + + + T_HIZ + desc T_HIZ + 31 + 29 + read-write + + + + + SER + desc SER + 0x4 + 32 + read-write + 0x0 + 0x1 + + + SEN + desc SEN + 0 + 0 + read-write + + + + + SSR + desc SSR + 0x8 + 32 + read-write + 0x0 + 0x7 + + + INDEX + desc INDEX + 2 + 0 + read-write + + + + + + + MPU + desc MPU + 0x40050000 + + 0x0 + 0x4020 + + + + RGD0 + desc RGD0 + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD1 + desc RGD1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD2 + desc RGD2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD3 + desc RGD3 + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD4 + desc RGD4 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD5 + desc RGD5 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD6 + desc RGD6 + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD7 + desc RGD7 + 0x1C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD8 + desc RGD8 + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD9 + desc RGD9 + 0x24 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD10 + desc RGD10 + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD11 + desc RGD11 + 0x2C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD12 + desc RGD12 + 0x30 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD13 + desc RGD13 + 0x34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD14 + desc RGD14 + 0x38 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD15 + desc RGD15 + 0x3C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGCR0 + desc RGCR0 + 0x40 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR1 + desc RGCR1 + 0x44 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR2 + desc RGCR2 + 0x48 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR3 + desc RGCR3 + 0x4C + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR4 + desc RGCR4 + 0x50 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR5 + desc RGCR5 + 0x54 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR6 + desc RGCR6 + 0x58 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR7 + desc RGCR7 + 0x5C + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR8 + desc RGCR8 + 0x60 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR9 + desc RGCR9 + 0x64 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR10 + desc RGCR10 + 0x68 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR11 + desc RGCR11 + 0x6C + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR12 + desc RGCR12 + 0x70 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR13 + desc RGCR13 + 0x74 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR14 + desc RGCR14 + 0x78 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR15 + desc RGCR15 + 0x7C + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + CR + desc CR + 0x80 + 32 + read-write + 0x0 + 0x8F8F8F + + + SMPU2BRP + desc SMPU2BRP + 0 + 0 + read-write + + + SMPU2BWP + desc SMPU2BWP + 1 + 1 + read-write + + + SMPU2ACT + desc SMPU2ACT + 3 + 2 + read-write + + + SMPU2E + desc SMPU2E + 7 + 7 + read-write + + + SMPU1BRP + desc SMPU1BRP + 8 + 8 + read-write + + + SMPU1BWP + desc SMPU1BWP + 9 + 9 + read-write + + + SMPU1ACT + desc SMPU1ACT + 11 + 10 + read-write + + + SMPU1E + desc SMPU1E + 15 + 15 + read-write + + + FMPUBRP + desc FMPUBRP + 16 + 16 + read-write + + + FMPUBWP + desc FMPUBWP + 17 + 17 + read-write + + + FMPUACT + desc FMPUACT + 19 + 18 + read-write + + + FMPUE + desc FMPUE + 23 + 23 + read-write + + + + + SR + desc SR + 0x84 + 32 + read-only + 0x0 + 0x10101 + + + SMPU2EAF + desc SMPU2EAF + 0 + 0 + read-only + + + SMPU1EAF + desc SMPU1EAF + 8 + 8 + read-only + + + FMPUEAF + desc FMPUEAF + 16 + 16 + read-only + + + + + ECLR + desc ECLR + 0x88 + 32 + write-only + 0x0 + 0x10101 + + + SMPU2ECLR + desc SMPU2ECLR + 0 + 0 + write-only + + + SMPU1ECLR + desc SMPU1ECLR + 8 + 8 + write-only + + + FMPUECLR + desc FMPUECLR + 16 + 16 + write-only + + + + + WP + desc WP + 0x8C + 32 + read-write + 0x0 + 0xFFFF + + + MPUWE + desc MPUWE + 0 + 0 + read-write + + + WKEY + desc WKEY + 15 + 1 + write-only + + + + + IPPR + desc IPPR + 0x401C + 32 + read-write + 0x0 + 0xBFFFF3FF + + + AESRDP + desc AESRDP + 0 + 0 + read-write + + + AESWRP + desc AESWRP + 1 + 1 + read-write + + + HASHRDP + desc HASHRDP + 2 + 2 + read-write + + + HASHWRP + desc HASHWRP + 3 + 3 + read-write + + + TRNGRDP + desc TRNGRDP + 4 + 4 + read-write + + + TRNGWRP + desc TRNGWRP + 5 + 5 + read-write + + + CRCRDP + desc CRCRDP + 6 + 6 + read-write + + + CRCWRP + desc CRCWRP + 7 + 7 + read-write + + + EFMRDP + desc EFMRDP + 8 + 8 + read-write + + + EFMWRP + desc EFMWRP + 9 + 9 + read-write + + + WDTRDP + desc WDTRDP + 12 + 12 + read-write + + + WDTWRP + desc WDTWRP + 13 + 13 + read-write + + + SWDTRDP + desc SWDTRDP + 14 + 14 + read-write + + + SWDTWRP + desc SWDTWRP + 15 + 15 + read-write + + + BKSRAMRDP + desc BKSRAMRDP + 16 + 16 + read-write + + + BKSRAMWRP + desc BKSRAMWRP + 17 + 17 + read-write + + + RTCRDP + desc RTCRDP + 18 + 18 + read-write + + + RTCWRP + desc RTCWRP + 19 + 19 + read-write + + + DMPURDP + desc DMPURDP + 20 + 20 + read-write + + + DMPUWRP + desc DMPUWRP + 21 + 21 + read-write + + + SRAMCRDP + desc SRAMCRDP + 22 + 22 + read-write + + + SRAMCWRP + desc SRAMCWRP + 23 + 23 + read-write + + + INTCRDP + desc INTCRDP + 24 + 24 + read-write + + + INTCWRP + desc INTCWRP + 25 + 25 + read-write + + + SYSCRDP + desc SYSCRDP + 26 + 26 + read-write + + + SYSCWRP + desc SYSCWRP + 27 + 27 + read-write + + + MSTPRDP + desc MSTPRDP + 28 + 28 + read-write + + + MSTPWRP + desc MSTPWRP + 29 + 29 + read-write + + + BUSERRE + desc BUSERRE + 31 + 31 + read-write + + + + + + + OTS + desc OTS + 0x4004A400 + + 0x0 + 0xC + + + + CTL + desc CTL + 0x0 + 16 + read-write + 0x0 + 0xF + + + OTSST + desc OTSST + 0 + 0 + read-write + + + OTSCK + desc OTSCK + 1 + 1 + read-write + + + OTSIE + desc OTSIE + 2 + 2 + read-write + + + TSSTP + desc TSSTP + 3 + 3 + read-write + + + + + DR1 + desc DR1 + 0x2 + 16 + read-write + 0x0 + 0xFFFF + + + DR2 + desc DR2 + 0x4 + 16 + read-write + 0x0 + 0xFFFF + + + ECR + desc ECR + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + LPR + desc LPR + 0x8 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + TSOFS + desc TSOFS + 7 + 0 + read-only + + + TSSLP + desc TSSLP + 31 + 8 + read-only + + + + + + + PERIC + desc PERIC + 0x40055400 + + 0x0 + 0x8 + + + + USBFS_SYCTLREG + desc USBFS_SYCTLREG + 0x0 + 32 + read-write + 0x0 + 0x3 + + + DFB + desc DFB + 0 + 0 + read-write + + + SOFEN + desc SOFEN + 1 + 1 + read-write + + + + + SDIOC_SYCTLREG + desc SDIOC_SYCTLREG + 0x4 + 32 + read-write + 0x0 + 0xA + + + SELMMC1 + desc SELMMC1 + 1 + 1 + read-write + + + SELMMC2 + desc SELMMC2 + 3 + 3 + read-write + + + + + + + PWC + desc PWC + 0x40048000 + + 0x0 + 0xC42C + + + + FCG0 + desc FCG0 + 0x0 + 32 + read-write + 0xFFFFFAEE + 0x8FF3C511 + + + SRAMH + desc SRAMH + 0 + 0 + read-write + + + SRAM12 + desc SRAM12 + 4 + 4 + read-write + + + SRAM3 + desc SRAM3 + 8 + 8 + read-write + + + SRAMRET + desc SRAMRET + 10 + 10 + read-write + + + DMA1 + desc DMA1 + 14 + 14 + read-write + + + DMA2 + desc DMA2 + 15 + 15 + read-write + + + FCM + desc FCM + 16 + 16 + read-write + + + AOS + desc AOS + 17 + 17 + read-write + + + AES + desc AES + 20 + 20 + read-write + + + HASH + desc HASH + 21 + 21 + read-write + + + TRNG + desc TRNG + 22 + 22 + read-write + + + CRC + desc CRC + 23 + 23 + read-write + + + DCU1 + desc DCU1 + 24 + 24 + read-write + + + DCU2 + desc DCU2 + 25 + 25 + read-write + + + DCU3 + desc DCU3 + 26 + 26 + read-write + + + DCU4 + desc DCU4 + 27 + 27 + read-write + + + KEY + desc KEY + 31 + 31 + read-write + + + + + FCG1 + desc FCG1 + 0x4 + 32 + read-write + 0xFFFFFFFF + 0xF0FFD79 + + + CAN + desc CAN + 0 + 0 + read-write + + + QSPI + desc QSPI + 3 + 3 + read-write + + + I2C1 + desc I2C1 + 4 + 4 + read-write + + + I2C2 + desc I2C2 + 5 + 5 + read-write + + + I2C3 + desc I2C3 + 6 + 6 + read-write + + + USBFS + desc USBFS + 8 + 8 + read-write + + + SDIOC1 + desc SDIOC1 + 10 + 10 + read-write + + + SDIOC2 + desc SDIOC2 + 11 + 11 + read-write + + + I2S1 + desc I2S1 + 12 + 12 + read-write + + + I2S2 + desc I2S2 + 13 + 13 + read-write + + + I2S3 + desc I2S3 + 14 + 14 + read-write + + + I2S4 + desc I2S4 + 15 + 15 + read-write + + + SPI1 + desc SPI1 + 16 + 16 + read-write + + + SPI2 + desc SPI2 + 17 + 17 + read-write + + + SPI3 + desc SPI3 + 18 + 18 + read-write + + + SPI4 + desc SPI4 + 19 + 19 + read-write + + + USART1 + desc USART1 + 24 + 24 + read-write + + + USART2 + desc USART2 + 25 + 25 + read-write + + + USART3 + desc USART3 + 26 + 26 + read-write + + + USART4 + desc USART4 + 27 + 27 + read-write + + + + + FCG2 + desc FCG2 + 0x8 + 32 + read-write + 0xFFFFFFFF + 0x787FF + + + TIMER0_1 + desc TIMER0_1 + 0 + 0 + read-write + + + TIMER0_2 + desc TIMER0_2 + 1 + 1 + read-write + + + TIMERA_1 + desc TIMERA_1 + 2 + 2 + read-write + + + TIMERA_2 + desc TIMERA_2 + 3 + 3 + read-write + + + TIMERA_3 + desc TIMERA_3 + 4 + 4 + read-write + + + TIMERA_4 + desc TIMERA_4 + 5 + 5 + read-write + + + TIMERA_5 + desc TIMERA_5 + 6 + 6 + read-write + + + TIMERA_6 + desc TIMERA_6 + 7 + 7 + read-write + + + TIMER4_1 + desc TIMER4_1 + 8 + 8 + read-write + + + TIMER4_2 + desc TIMER4_2 + 9 + 9 + read-write + + + TIMER4_3 + desc TIMER4_3 + 10 + 10 + read-write + + + EMB + desc EMB + 15 + 15 + read-write + + + TIMER6_1 + desc TIMER6_1 + 16 + 16 + read-write + + + TIMER6_2 + desc TIMER6_2 + 17 + 17 + read-write + + + TIMER6_3 + desc TIMER6_3 + 18 + 18 + read-write + + + + + FCG3 + desc FCG3 + 0xC + 32 + read-write + 0xFFFFFFFF + 0x1103 + + + ADC1 + desc ADC1 + 0 + 0 + read-write + + + ADC2 + desc ADC2 + 1 + 1 + read-write + + + CMP + desc CMP + 8 + 8 + read-write + + + OTS + desc OTS + 12 + 12 + read-write + + + + + FCG0PC + desc FCG0PC + 0x10 + 32 + read-write + 0x0 + 0xFFFF0001 + + + PRT0 + desc PRT0 + 0 + 0 + read-write + + + FCG0PCWE + desc FCG0PCWE + 31 + 16 + write-only + + + + + WKTCR + desc WKTCR + 0x4400 + 16 + read-write + 0x0 + 0xFFFF + + + WKTMCMP + desc WKTMCMP + 11 + 0 + read-write + + + WKOVF + desc WKOVF + 12 + 12 + read-write + + + WKCKS + desc WKCKS + 14 + 13 + read-write + + + WKTCE + desc WKTCE + 15 + 15 + read-write + + + + + STPMCR + desc STPMCR + 0xC00C + 16 + read-write + 0x4000 + 0x8003 + + + FLNWT + desc FLNWT + 0 + 0 + read-write + + + CKSMRC + desc CKSMRC + 1 + 1 + read-write + + + STOP + desc STOP + 15 + 15 + read-write + + + + + RAMPC0 + desc RAMPC0 + 0xC014 + 32 + read-write + 0x0 + 0x1FF + + + RAMPDC0 + desc RAMPDC0 + 0 + 0 + read-write + + + RAMPDC1 + desc RAMPDC1 + 1 + 1 + read-write + + + RAMPDC2 + desc RAMPDC2 + 2 + 2 + read-write + + + RAMPDC3 + desc RAMPDC3 + 3 + 3 + read-write + + + RAMPDC4 + desc RAMPDC4 + 4 + 4 + read-write + + + RAMPDC5 + desc RAMPDC5 + 5 + 5 + read-write + + + RAMPDC6 + desc RAMPDC6 + 6 + 6 + read-write + + + RAMPDC7 + desc RAMPDC7 + 7 + 7 + read-write + + + RAMPDC8 + desc RAMPDC8 + 8 + 8 + read-write + + + + + RAMOPM + desc RAMOPM + 0xC018 + 16 + read-write + 0x8043 + 0xFFFF + + + PVDICR + desc PVDICR + 0xC0E0 + 8 + read-write + 0x0 + 0x11 + + + PVD1NMIS + desc PVD1NMIS + 0 + 0 + read-write + + + PVD2NMIS + desc PVD2NMIS + 4 + 4 + read-write + + + + + PVDDSR + desc PVDDSR + 0xC0E1 + 8 + read-write + 0x11 + 0x33 + + + PVD1MON + desc PVD1MON + 0 + 0 + read-write + + + PVD1DETFLG + desc PVD1DETFLG + 1 + 1 + read-write + + + PVD2MON + desc PVD2MON + 4 + 4 + read-write + + + PVD2DETFLG + desc PVD2DETFLG + 5 + 5 + read-write + + + + + FPRC + desc FPRC + 0xC3FE + 16 + read-write + 0x0 + 0xFF0F + + + FPRCB0 + desc FPRCB0 + 0 + 0 + read-write + + + FPRCB1 + desc FPRCB1 + 1 + 1 + read-write + + + FPRCB2 + desc FPRCB2 + 2 + 2 + read-write + + + FPRCB3 + desc FPRCB3 + 3 + 3 + read-write + + + FPRCWE + desc FPRCWE + 15 + 8 + read-write + + + + + PWRC0 + desc PWRC0 + 0xC400 + 8 + read-write + 0x0 + 0xBF + + + PDMDS + desc PDMDS + 1 + 0 + read-write + + + VVDRSD + desc VVDRSD + 2 + 2 + read-write + + + RETRAMSD + desc RETRAMSD + 3 + 3 + read-write + + + IORTN + desc IORTN + 5 + 4 + read-write + + + PWDN + desc PWDN + 7 + 7 + read-write + + + + + PWRC1 + desc PWRC1 + 0xC401 + 8 + read-write + 0x0 + 0xC3 + + + VPLLSD + desc VPLLSD + 0 + 0 + read-write + + + VHRCSD + desc VHRCSD + 1 + 1 + read-write + + + STPDAS + desc STPDAS + 7 + 6 + read-write + + + + + PWRC2 + desc PWRC2 + 0xC402 + 8 + read-write + 0xFF + 0x3F + + + DDAS + desc DDAS + 3 + 0 + read-write + + + DVS + desc DVS + 5 + 4 + read-write + + + + + PWRC3 + desc PWRC3 + 0xC403 + 8 + read-write + 0x7 + 0x4 + + + PDTS + desc PDTS + 2 + 2 + read-write + + + + + PDWKE0 + desc PDWKE0 + 0xC404 + 8 + read-write + 0x0 + 0xFF + + + WKE00 + desc WKE00 + 0 + 0 + read-write + + + WKE01 + desc WKE01 + 1 + 1 + read-write + + + WKE02 + desc WKE02 + 2 + 2 + read-write + + + WKE03 + desc WKE03 + 3 + 3 + read-write + + + WKE10 + desc WKE10 + 4 + 4 + read-write + + + WKE11 + desc WKE11 + 5 + 5 + read-write + + + WKE12 + desc WKE12 + 6 + 6 + read-write + + + WKE13 + desc WKE13 + 7 + 7 + read-write + + + + + PDWKE1 + desc PDWKE1 + 0xC405 + 8 + read-write + 0x0 + 0xFF + + + WKE20 + desc WKE20 + 0 + 0 + read-write + + + WKE21 + desc WKE21 + 1 + 1 + read-write + + + WKE22 + desc WKE22 + 2 + 2 + read-write + + + WKE23 + desc WKE23 + 3 + 3 + read-write + + + WKE30 + desc WKE30 + 4 + 4 + read-write + + + WKE31 + desc WKE31 + 5 + 5 + read-write + + + WKE32 + desc WKE32 + 6 + 6 + read-write + + + WKE33 + desc WKE33 + 7 + 7 + read-write + + + + + PDWKE2 + desc PDWKE2 + 0xC406 + 8 + read-write + 0x0 + 0xB7 + + + VD1WKE + desc VD1WKE + 0 + 0 + read-write + + + VD2WKE + desc VD2WKE + 1 + 1 + read-write + + + NMIWKE + desc NMIWKE + 2 + 2 + read-write + + + RTCPRDWKE + desc RTCPRDWKE + 4 + 4 + read-write + + + RTCALMWKE + desc RTCALMWKE + 5 + 5 + read-write + + + WKTMWKE + desc WKTMWKE + 7 + 7 + read-write + + + + + PDWKES + desc PDWKES + 0xC407 + 8 + read-write + 0x0 + 0x7F + + + WK0EGS + desc WK0EGS + 0 + 0 + read-write + + + WK1EGS + desc WK1EGS + 1 + 1 + read-write + + + WK2EGS + desc WK2EGS + 2 + 2 + read-write + + + WK3EGS + desc WK3EGS + 3 + 3 + read-write + + + VD1EGS + desc VD1EGS + 4 + 4 + read-write + + + VD2EGS + desc VD2EGS + 5 + 5 + read-write + + + NMIEGS + desc NMIEGS + 6 + 6 + read-write + + + + + PDWKF0 + desc PDWKF0 + 0xC408 + 8 + read-write + 0x0 + 0x7F + + + PTWK0F + desc PTWK0F + 0 + 0 + read-write + + + PTWK1F + desc PTWK1F + 1 + 1 + read-write + + + PTWK2F + desc PTWK2F + 2 + 2 + read-write + + + PTWK3F + desc PTWK3F + 3 + 3 + read-write + + + VD1WKF + desc VD1WKF + 4 + 4 + read-write + + + VD2WKF + desc VD2WKF + 5 + 5 + read-write + + + NMIWKF + desc NMIWKF + 6 + 6 + read-write + + + + + PDWKF1 + desc PDWKF1 + 0xC409 + 8 + read-write + 0x0 + 0xB8 + + + RTCPRDWKF + desc RTCPRDWKF + 4 + 4 + read-write + + + RTCALMWKF + desc RTCALMWKF + 5 + 5 + read-write + + + WKTMWKF + desc WKTMWKF + 7 + 7 + read-write + + + + + PWCMR + desc PWCMR + 0xC40A + 8 + read-write + 0x0 + 0x80 + + + ADBUFE + desc ADBUFE + 7 + 7 + read-write + + + + + MDSWCR + desc MDSWCR + 0xC40F + 8 + read-write + 0x0 + 0xFF + + + PVDCR0 + desc PVDCR0 + 0xC412 + 8 + read-write + 0x0 + 0x61 + + + EXVCCINEN + desc EXVCCINEN + 0 + 0 + read-write + + + PVD1EN + desc PVD1EN + 5 + 5 + read-write + + + PVD2EN + desc PVD2EN + 6 + 6 + read-write + + + + + PVDCR1 + desc PVDCR1 + 0xC413 + 8 + read-write + 0x0 + 0x77 + + + PVD1IRE + desc PVD1IRE + 0 + 0 + read-write + + + PVD1IRS + desc PVD1IRS + 1 + 1 + read-write + + + PVD1CMPOE + desc PVD1CMPOE + 2 + 2 + read-write + + + PVD2IRE + desc PVD2IRE + 4 + 4 + read-write + + + PVD2IRS + desc PVD2IRS + 5 + 5 + read-write + + + PVD2CMPOE + desc PVD2CMPOE + 6 + 6 + read-write + + + + + PVDFCR + desc PVDFCR + 0xC414 + 8 + read-write + 0x11 + 0x77 + + + PVD1NFDIS + desc PVD1NFDIS + 0 + 0 + read-write + + + PVD1NFCKS + desc PVD1NFCKS + 2 + 1 + read-write + + + PVD2NFDIS + desc PVD2NFDIS + 4 + 4 + read-write + + + PVD2NFCKS + desc PVD2NFCKS + 6 + 5 + read-write + + + + + PVDLCR + desc PVDLCR + 0xC415 + 8 + read-write + 0x0 + 0x77 + + + PVD1LVL + desc PVD1LVL + 2 + 0 + read-write + + + PVD2LVL + desc PVD2LVL + 6 + 4 + read-write + + + + + XTAL32CS + desc XTAL32CS + 0xC42B + 8 + read-write + 0x2 + 0x80 + + + CSDIS + desc CSDIS + 7 + 7 + read-write + + + + + + + QSPI + desc QSPI + 0x9C000000 + + 0x0 + 0x808 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x3F0000 + 0x3F3FFF + + + MDSEL + desc MDSEL + 2 + 0 + read-write + + + PFE + desc PFE + 3 + 3 + read-write + + + PFSAE + desc PFSAE + 4 + 4 + read-write + + + DCOME + desc DCOME + 5 + 5 + read-write + + + XIPE + desc XIPE + 6 + 6 + read-write + + + SPIMD3 + desc SPIMD3 + 7 + 7 + read-write + + + IPRSL + desc IPRSL + 9 + 8 + read-write + + + APRSL + desc APRSL + 11 + 10 + read-write + + + DPRSL + desc DPRSL + 13 + 12 + read-write + + + DIV + desc DIV + 21 + 16 + read-write + + + + + CSCR + desc CSCR + 0x4 + 32 + read-write + 0xF + 0x3F + + + SSHW + desc SSHW + 3 + 0 + read-write + + + SSNW + desc SSNW + 5 + 4 + read-write + + + + + FCR + desc FCR + 0x8 + 32 + read-write + 0x80B3 + 0x8F77 + + + AWSL + desc AWSL + 1 + 0 + read-write + + + FOUR_BIC + desc FOUR_BIC + 2 + 2 + read-write + + + SSNHD + desc SSNHD + 4 + 4 + read-write + + + SSNLD + desc SSNLD + 5 + 5 + read-write + + + WPOL + desc WPOL + 6 + 6 + read-write + + + DMCYCN + desc DMCYCN + 11 + 8 + read-write + + + DUTY + desc DUTY + 15 + 15 + read-write + + + + + SR + desc SR + 0xC + 32 + read-write + 0x8000 + 0xDFC1 + + + BUSY + desc BUSY + 0 + 0 + read-write + + + XIPF + desc XIPF + 6 + 6 + read-write + + + RAER + desc RAER + 7 + 7 + read-write + + + PFNUM + desc PFNUM + 12 + 8 + read-write + + + PFFUL + desc PFFUL + 14 + 14 + read-write + + + PFAN + desc PFAN + 15 + 15 + read-write + + + + + DCOM + desc DCOM + 0x10 + 32 + read-write + 0x0 + 0xFF + + + DCOM + desc DCOM + 7 + 0 + read-write + + + + + CCMD + desc CCMD + 0x14 + 32 + read-write + 0x0 + 0xFF + + + RIC + desc RIC + 7 + 0 + read-write + + + + + XCMD + desc XCMD + 0x18 + 32 + read-write + 0xFF + 0xFF + + + XIPMC + desc XIPMC + 7 + 0 + read-write + + + + + SR2 + desc SR2 + 0x24 + 32 + write-only + 0x0 + 0x80 + + + RAERCLR + desc RAERCLR + 7 + 7 + write-only + + + + + EXAR + desc EXAR + 0x804 + 32 + read-write + 0x0 + 0xFC000000 + + + EXADR + desc EXADR + 31 + 26 + read-write + + + + + + + RMU + desc RMU + 0x400540C0 + + 0x0 + 0x2 + + + + RSTF0 + desc RSTF0 + 0x0 + 16 + read-write + 0x2 + 0xFFFF + + + PORF + desc PORF + 0 + 0 + read-write + + + PINRF + desc PINRF + 1 + 1 + read-write + + + BORF + desc BORF + 2 + 2 + read-write + + + PVD1RF + desc PVD1RF + 3 + 3 + read-write + + + PVD2RF + desc PVD2RF + 4 + 4 + read-write + + + WDRF + desc WDRF + 5 + 5 + read-write + + + SWDRF + desc SWDRF + 6 + 6 + read-write + + + PDRF + desc PDRF + 7 + 7 + read-write + + + SWRF + desc SWRF + 8 + 8 + read-write + + + MPUERF + desc MPUERF + 9 + 9 + read-write + + + RAPERF + desc RAPERF + 10 + 10 + read-write + + + RAECRF + desc RAECRF + 11 + 11 + read-write + + + CKFERF + desc CKFERF + 12 + 12 + read-write + + + XTALERF + desc XTALERF + 13 + 13 + read-write + + + MULTIRF + desc MULTIRF + 14 + 14 + read-write + + + CLRF + desc CLRF + 15 + 15 + read-write + + + + + + + RTC + desc RTC + 0x4004C000 + + 0x0 + 0x40 + + + + CR0 + desc CR0 + 0x0 + 8 + read-write + 0x0 + 0x1 + + + RESET + desc RESET + 0 + 0 + read-write + + + + + CR1 + desc CR1 + 0x4 + 8 + read-write + 0x0 + 0xFF + + + PRDS + desc PRDS + 2 + 0 + read-write + + + AMPM + desc AMPM + 3 + 3 + read-write + + + ALMFCLR + desc ALMFCLR + 4 + 4 + read-write + + + ONEHZOE + desc ONEHZOE + 5 + 5 + read-write + + + ONEHZSEL + desc ONEHZSEL + 6 + 6 + read-write + + + START + desc START + 7 + 7 + read-write + + + + + CR2 + desc CR2 + 0x8 + 8 + read-write + 0x0 + 0xEB + + + RWREQ + desc RWREQ + 0 + 0 + read-write + + + RWEN + desc RWEN + 1 + 1 + read-write + + + ALMF + desc ALMF + 3 + 3 + read-write + + + PRDIE + desc PRDIE + 5 + 5 + read-write + + + ALMIE + desc ALMIE + 6 + 6 + read-write + + + ALME + desc ALME + 7 + 7 + read-write + + + + + CR3 + desc CR3 + 0xC + 8 + read-write + 0x0 + 0x90 + + + LRCEN + desc LRCEN + 4 + 4 + read-write + + + RCKSEL + desc RCKSEL + 7 + 7 + read-write + + + + + SEC + desc SEC + 0x10 + 8 + read-write + 0x0 + 0x7F + + + SECU + desc SECU + 3 + 0 + read-write + + + SECD + desc SECD + 6 + 4 + read-write + + + + + MIN + desc MIN + 0x14 + 8 + read-write + 0x0 + 0x7F + + + MINU + desc MINU + 3 + 0 + read-write + + + MIND + desc MIND + 6 + 4 + read-write + + + + + HOUR + desc HOUR + 0x18 + 8 + read-write + 0x12 + 0x3F + + + HOURU + desc HOURU + 3 + 0 + read-write + + + HOURD + desc HOURD + 5 + 4 + read-write + + + + + WEEK + desc WEEK + 0x1C + 8 + read-write + 0x0 + 0x7 + + + WEEK + desc WEEK + 2 + 0 + read-write + + + + + DAY + desc DAY + 0x20 + 8 + read-write + 0x0 + 0x3F + + + DAYU + desc DAYU + 3 + 0 + read-write + + + DAYD + desc DAYD + 5 + 4 + read-write + + + + + MON + desc MON + 0x24 + 8 + read-write + 0x0 + 0x1F + + + MON + desc MON + 4 + 0 + read-write + + + + + YEAR + desc YEAR + 0x28 + 8 + read-write + 0x0 + 0xFF + + + YEARU + desc YEARU + 3 + 0 + read-write + + + YEARD + desc YEARD + 7 + 4 + read-write + + + + + ALMMIN + desc ALMMIN + 0x2C + 8 + read-write + 0x12 + 0x7F + + + ALMMINU + desc ALMMINU + 3 + 0 + read-write + + + ALMMIND + desc ALMMIND + 6 + 4 + read-write + + + + + ALMHOUR + desc ALMHOUR + 0x30 + 8 + read-write + 0x0 + 0x3F + + + ALMHOURU + desc ALMHOURU + 3 + 0 + read-write + + + ALMHOURD + desc ALMHOURD + 5 + 4 + read-write + + + + + ALMWEEK + desc ALMWEEK + 0x34 + 8 + read-write + 0x0 + 0x7F + + + ALMWEEK + desc ALMWEEK + 6 + 0 + read-write + + + + + ERRCRH + desc ERRCRH + 0x38 + 8 + read-write + 0x0 + 0x81 + + + COMP8 + desc COMP8 + 0 + 0 + read-write + + + COMPEN + desc COMPEN + 7 + 7 + read-write + + + + + ERRCRL + desc ERRCRL + 0x3C + 8 + read-write + 0x20 + 0xFF + + + COMP + desc COMP + 7 + 0 + read-write + + + + + + + SDIOC1 + desc SDIOC + 0x4006FC00 + + 0x0 + 0x54 + + + + BLKSIZE + desc BLKSIZE + 0x4 + 16 + read-write + 0x0 + 0xFFF + + + TBS + desc TBS + 11 + 0 + read-write + + + + + BLKCNT + desc BLKCNT + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + ARG0 + desc ARG0 + 0x8 + 16 + read-write + 0x0 + 0xFFFF + + + ARG1 + desc ARG1 + 0xA + 16 + read-write + 0x0 + 0xFFFF + + + TRANSMODE + desc TRANSMODE + 0xC + 16 + read-write + 0x0 + 0x3E + + + BCE + desc BCE + 1 + 1 + read-write + + + ATCEN + desc ATCEN + 3 + 2 + read-write + + + DDIR + desc DDIR + 4 + 4 + read-write + + + MULB + desc MULB + 5 + 5 + read-write + + + + + CMD + desc CMD + 0xE + 16 + read-write + 0x0 + 0x3FFB + + + RESTYP + desc RESTYP + 1 + 0 + read-write + + + CCE + desc CCE + 3 + 3 + read-write + + + ICE + desc ICE + 4 + 4 + read-write + + + DAT + desc DAT + 5 + 5 + read-write + + + TYP + desc TYP + 7 + 6 + read-write + + + IDX + desc IDX + 13 + 8 + read-write + + + + + RESP0 + desc RESP0 + 0x10 + 16 + read-only + 0x0 + 0xFFFF + + + RESP1 + desc RESP1 + 0x12 + 16 + read-only + 0x0 + 0xFFFF + + + RESP2 + desc RESP2 + 0x14 + 16 + read-only + 0x0 + 0xFFFF + + + RESP3 + desc RESP3 + 0x16 + 16 + read-only + 0x0 + 0xFFFF + + + RESP4 + desc RESP4 + 0x18 + 16 + read-only + 0x0 + 0xFFFF + + + RESP5 + desc RESP5 + 0x1A + 16 + read-only + 0x0 + 0xFFFF + + + RESP6 + desc RESP6 + 0x1C + 16 + read-only + 0x0 + 0xFFFF + + + RESP7 + desc RESP7 + 0x1E + 16 + read-only + 0x0 + 0xFFFF + + + BUF0 + desc BUF0 + 0x20 + 16 + read-write + 0x0 + 0xFFFF + + + BUF1 + desc BUF1 + 0x22 + 16 + read-write + 0x0 + 0xFFFF + + + PSTAT + desc PSTAT + 0x24 + 32 + read-only + 0x0 + 0x1FF0F07 + + + CIC + desc CIC + 0 + 0 + read-only + + + CID + desc CID + 1 + 1 + read-only + + + DA + desc DA + 2 + 2 + read-only + + + WTA + desc WTA + 8 + 8 + read-only + + + RTA + desc RTA + 9 + 9 + read-only + + + BWE + desc BWE + 10 + 10 + read-only + + + BRE + desc BRE + 11 + 11 + read-only + + + CIN + desc CIN + 16 + 16 + read-only + + + CSS + desc CSS + 17 + 17 + read-only + + + CDL + desc CDL + 18 + 18 + read-only + + + WPL + desc WPL + 19 + 19 + read-only + + + DATL + desc DATL + 23 + 20 + read-only + + + CMDL + desc CMDL + 24 + 24 + read-only + + + + + HOSTCON + desc HOSTCON + 0x28 + 8 + read-write + 0x0 + 0xE6 + + + DW + desc DW + 1 + 1 + read-write + + + HSEN + desc HSEN + 2 + 2 + read-write + + + EXDW + desc EXDW + 5 + 5 + read-write + + + CDTL + desc CDTL + 6 + 6 + read-write + + + CDSS + desc CDSS + 7 + 7 + read-write + + + + + PWRCON + desc PWRCON + 0x29 + 8 + read-write + 0x0 + 0x1 + + + PWON + desc PWON + 0 + 0 + read-write + + + + + BLKGPCON + desc BLKGPCON + 0x2A + 8 + read-write + 0x0 + 0xF + + + SABGR + desc SABGR + 0 + 0 + read-write + + + CR + desc CR + 1 + 1 + read-write + + + RWC + desc RWC + 2 + 2 + read-write + + + IABG + desc IABG + 3 + 3 + read-write + + + + + CLKCON + desc CLKCON + 0x2C + 16 + read-write + 0x2 + 0xFF05 + + + ICE + desc ICE + 0 + 0 + read-write + + + CE + desc CE + 2 + 2 + read-write + + + FS + desc FS + 15 + 8 + read-write + + + + + TOUTCON + desc TOUTCON + 0x2E + 8 + read-write + 0x0 + 0xF + + + DTO + desc DTO + 3 + 0 + read-write + + + + + SFTRST + desc SFTRST + 0x2F + 8 + read-write + 0x0 + 0x7 + + + RSTA + desc RSTA + 0 + 0 + read-write + + + RSTC + desc RSTC + 1 + 1 + read-write + + + RSTD + desc RSTD + 2 + 2 + read-write + + + + + NORINTST + desc NORINTST + 0x30 + 16 + read-write + 0x0 + 0x81F7 + + + CC + desc CC + 0 + 0 + read-write + + + TC + desc TC + 1 + 1 + read-write + + + BGE + desc BGE + 2 + 2 + read-write + + + BWR + desc BWR + 4 + 4 + read-write + + + BRR + desc BRR + 5 + 5 + read-write + + + CIST + desc CIST + 6 + 6 + read-write + + + CRM + desc CRM + 7 + 7 + read-write + + + CINT + desc CINT + 8 + 8 + read-only + + + EI + desc EI + 15 + 15 + read-only + + + + + ERRINTST + desc ERRINTST + 0x32 + 16 + read-write + 0x0 + 0x17F + + + CTOE + desc CTOE + 0 + 0 + read-write + + + CCE + desc CCE + 1 + 1 + read-write + + + CEBE + desc CEBE + 2 + 2 + read-write + + + CIE + desc CIE + 3 + 3 + read-write + + + DTOE + desc DTOE + 4 + 4 + read-write + + + DCE + desc DCE + 5 + 5 + read-write + + + DEBE + desc DEBE + 6 + 6 + read-write + + + ACE + desc ACE + 8 + 8 + read-write + + + + + NORINTSTEN + desc NORINTSTEN + 0x34 + 16 + read-write + 0x0 + 0x1F7 + + + CCEN + desc CCEN + 0 + 0 + read-write + + + TCEN + desc TCEN + 1 + 1 + read-write + + + BGEEN + desc BGEEN + 2 + 2 + read-write + + + BWREN + desc BWREN + 4 + 4 + read-write + + + BRREN + desc BRREN + 5 + 5 + read-write + + + CISTEN + desc CISTEN + 6 + 6 + read-write + + + CRMEN + desc CRMEN + 7 + 7 + read-write + + + CINTEN + desc CINTEN + 8 + 8 + read-write + + + + + ERRINTSTEN + desc ERRINTSTEN + 0x36 + 16 + read-write + 0x0 + 0x17F + + + CTOEEN + desc CTOEEN + 0 + 0 + read-write + + + CCEEN + desc CCEEN + 1 + 1 + read-write + + + CEBEEN + desc CEBEEN + 2 + 2 + read-write + + + CIEEN + desc CIEEN + 3 + 3 + read-write + + + DTOEEN + desc DTOEEN + 4 + 4 + read-write + + + DCEEN + desc DCEEN + 5 + 5 + read-write + + + DEBEEN + desc DEBEEN + 6 + 6 + read-write + + + ACEEN + desc ACEEN + 8 + 8 + read-write + + + + + NORINTSGEN + desc NORINTSGEN + 0x38 + 16 + read-write + 0x0 + 0x1F7 + + + CCSEN + desc CCSEN + 0 + 0 + read-write + + + TCSEN + desc TCSEN + 1 + 1 + read-write + + + BGESEN + desc BGESEN + 2 + 2 + read-write + + + BWRSEN + desc BWRSEN + 4 + 4 + read-write + + + BRRSEN + desc BRRSEN + 5 + 5 + read-write + + + CISTSEN + desc CISTSEN + 6 + 6 + read-write + + + CRMSEN + desc CRMSEN + 7 + 7 + read-write + + + CINTSEN + desc CINTSEN + 8 + 8 + read-write + + + + + ERRINTSGEN + desc ERRINTSGEN + 0x3A + 16 + read-write + 0x0 + 0x17F + + + CTOESEN + desc CTOESEN + 0 + 0 + read-write + + + CCESEN + desc CCESEN + 1 + 1 + read-write + + + CEBESEN + desc CEBESEN + 2 + 2 + read-write + + + CIESEN + desc CIESEN + 3 + 3 + read-write + + + DTOESEN + desc DTOESEN + 4 + 4 + read-write + + + DCESEN + desc DCESEN + 5 + 5 + read-write + + + DEBESEN + desc DEBESEN + 6 + 6 + read-write + + + ACESEN + desc ACESEN + 8 + 8 + read-write + + + + + ATCERRST + desc ATCERRST + 0x3C + 16 + read-only + 0x0 + 0x9F + + + NE + desc NE + 0 + 0 + read-only + + + TOE + desc TOE + 1 + 1 + read-only + + + CE + desc CE + 2 + 2 + read-only + + + EBE + desc EBE + 3 + 3 + read-only + + + IE + desc IE + 4 + 4 + read-only + + + CMDE + desc CMDE + 7 + 7 + read-only + + + + + FEA + desc FEA + 0x50 + 16 + write-only + 0x0 + 0x9F + + + FNE + desc FNE + 0 + 0 + write-only + + + FTOE + desc FTOE + 1 + 1 + write-only + + + FCE + desc FCE + 2 + 2 + write-only + + + FEBE + desc FEBE + 3 + 3 + write-only + + + FIE + desc FIE + 4 + 4 + write-only + + + FCMDE + desc FCMDE + 7 + 7 + write-only + + + + + FEE + desc FEE + 0x52 + 16 + write-only + 0x0 + 0x17F + + + FCTOE + desc FCTOE + 0 + 0 + write-only + + + FCCE + desc FCCE + 1 + 1 + write-only + + + FCEBE + desc FCEBE + 2 + 2 + write-only + + + FCIE + desc FCIE + 3 + 3 + write-only + + + FDTOE + desc FDTOE + 4 + 4 + write-only + + + FDCE + desc FDCE + 5 + 5 + write-only + + + FDEBE + desc FDEBE + 6 + 6 + write-only + + + FACE + desc FACE + 8 + 8 + write-only + + + + + + + SDIOC2 + desc SDIOC + 0x40070000 + + 0x0 + 0x54 + + + + SPI1 + desc SPI + 0x4001C000 + + 0x0 + 0x1C + + + + DR + desc DR + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CR1 + desc CR1 + 0x4 + 32 + read-write + 0x0 + 0xFFFB + + + SPIMDS + desc SPIMDS + 0 + 0 + read-write + + + TXMDS + desc TXMDS + 1 + 1 + read-write + + + MSTR + desc MSTR + 3 + 3 + read-write + + + SPLPBK + desc SPLPBK + 4 + 4 + read-write + + + SPLPBK2 + desc SPLPBK2 + 5 + 5 + read-write + + + SPE + desc SPE + 6 + 6 + read-write + + + CSUSPE + desc CSUSPE + 7 + 7 + read-write + + + EIE + desc EIE + 8 + 8 + read-write + + + TXIE + desc TXIE + 9 + 9 + read-write + + + RXIE + desc RXIE + 10 + 10 + read-write + + + IDIE + desc IDIE + 11 + 11 + read-write + + + MODFE + desc MODFE + 12 + 12 + read-write + + + PATE + desc PATE + 13 + 13 + read-write + + + PAOE + desc PAOE + 14 + 14 + read-write + + + PAE + desc PAE + 15 + 15 + read-write + + + + + CFG1 + desc CFG1 + 0xC + 32 + read-write + 0x10 + 0x77700F43 + + + FTHLV + desc FTHLV + 1 + 0 + read-write + + + SPRDTD + desc SPRDTD + 6 + 6 + read-write + + + SS0PV + desc SS0PV + 8 + 8 + read-write + + + SS1PV + desc SS1PV + 9 + 9 + read-write + + + SS2PV + desc SS2PV + 10 + 10 + read-write + + + SS3PV + desc SS3PV + 11 + 11 + read-write + + + MSSI + desc MSSI + 22 + 20 + read-write + + + MSSDL + desc MSSDL + 26 + 24 + read-write + + + MIDI + desc MIDI + 30 + 28 + read-write + + + + + SR + desc SR + 0x14 + 32 + read-write + 0x20 + 0xBF + + + OVRERF + desc OVRERF + 0 + 0 + read-write + + + IDLNF + desc IDLNF + 1 + 1 + read-only + + + MODFERF + desc MODFERF + 2 + 2 + read-write + + + PERF + desc PERF + 3 + 3 + read-write + + + UDRERF + desc UDRERF + 4 + 4 + read-write + + + TDEF + desc TDEF + 5 + 5 + read-write + + + RDFF + desc RDFF + 7 + 7 + read-write + + + + + CFG2 + desc CFG2 + 0x18 + 32 + read-write + 0xF1D + 0xFFFF + + + CPHA + desc CPHA + 0 + 0 + read-write + + + CPOL + desc CPOL + 1 + 1 + read-write + + + MBR + desc MBR + 4 + 2 + read-write + + + SSA + desc SSA + 7 + 5 + read-write + + + DSIZE + desc DSIZE + 11 + 8 + read-write + + + LSBF + desc LSBF + 12 + 12 + read-write + + + MIDIE + desc MIDIE + 13 + 13 + read-write + + + MSSDLE + desc MSSDLE + 14 + 14 + read-write + + + MSSIE + desc MSSIE + 15 + 15 + read-write + + + + + + + SPI2 + desc SPI + 0x4001C400 + + 0x0 + 0x1C + + + + SPI3 + desc SPI + 0x40020000 + + 0x0 + 0x1C + + + + SPI4 + desc SPI + 0x40020400 + + 0x0 + 0x1C + + + + SRAMC + desc SRAMC + 0x40050800 + + 0x0 + 0x14 + + + + WTCR + desc WTCR + 0x0 + 32 + read-write + 0x0 + 0x77777777 + + + SRAM12_RWT + desc SRAM12_RWT + 2 + 0 + read-write + + + SRAM12_WWT + desc SRAM12_WWT + 6 + 4 + read-write + + + SRAM3_RWT + desc SRAM3_RWT + 10 + 8 + read-write + + + SRAM3_WWT + desc SRAM3_WWT + 14 + 12 + read-write + + + SRAMH_RWT + desc SRAMH_RWT + 18 + 16 + read-write + + + SRAMH_WWT + desc SRAMH_WWT + 22 + 20 + read-write + + + SRAMR_RWT + desc SRAMR_RWT + 26 + 24 + read-write + + + SRAMR_WWT + desc SRAMR_WWT + 30 + 28 + read-write + + + + + WTPR + desc WTPR + 0x4 + 32 + read-write + 0x0 + 0xFF + + + WTPRC + desc WTPRC + 0 + 0 + read-write + + + WTPRKW + desc WTPRKW + 7 + 1 + read-write + + + + + CKCR + desc CKCR + 0x8 + 32 + read-write + 0x0 + 0x3010001 + + + PYOAD + desc PYOAD + 0 + 0 + read-write + + + ECCOAD + desc ECCOAD + 16 + 16 + read-write + + + ECCMOD + desc ECCMOD + 25 + 24 + read-write + + + + + CKPR + desc CKPR + 0xC + 32 + read-write + 0x0 + 0xFF + + + CKPRC + desc CKPRC + 0 + 0 + read-write + + + CKPRKW + desc CKPRKW + 7 + 1 + read-write + + + + + CKSR + desc CKSR + 0x10 + 32 + read-write + 0x0 + 0x1F + + + SRAM3_1ERR + desc SRAM3_1ERR + 0 + 0 + read-write + + + SRAM3_2ERR + desc SRAM3_2ERR + 1 + 1 + read-write + + + SRAM12_PYERR + desc SRAM12_PYERR + 2 + 2 + read-write + + + SRAMH_PYERR + desc SRAMH_PYERR + 3 + 3 + read-write + + + SRAMR_PYERR + desc SRAMR_PYERR + 4 + 4 + read-write + + + + + + + SWDT + desc SWDT + 0x40049400 + + 0x0 + 0xC + + + + SR + desc SR + 0x4 + 32 + read-write + 0x0 + 0x3FFFF + + + CNT + desc CNT + 15 + 0 + read-only + + + UDF + desc UDF + 16 + 16 + read-write + + + REF + desc REF + 17 + 17 + read-write + + + + + RR + desc RR + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + RF + desc RF + 15 + 0 + read-write + + + + + + + TMR01 + desc TMR0 + 0x40024000 + + 0x0 + 0x18 + + + + CNTAR + desc CNTAR + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + CNTA + desc CNTA + 15 + 0 + read-write + + + + + CNTBR + desc CNTBR + 0x4 + 32 + read-write + 0x0 + 0xFFFF + + + CNTB + desc CNTB + 15 + 0 + read-write + + + + + CMPAR + desc CMPAR + 0x8 + 32 + read-write + 0xFFFF + 0xFFFF + + + CMPA + desc CMPA + 15 + 0 + read-write + + + + + CMPBR + desc CMPBR + 0xC + 32 + read-write + 0xFFFF + 0xFFFF + + + CMPB + desc CMPB + 15 + 0 + read-write + + + + + BCONR + desc BCONR + 0x10 + 32 + read-write + 0x0 + 0xF7F7F7F7 + + + CSTA + desc CSTA + 0 + 0 + read-write + + + CAPMDA + desc CAPMDA + 1 + 1 + read-write + + + INTENA + desc INTENA + 2 + 2 + read-write + + + CKDIVA + desc CKDIVA + 7 + 4 + read-write + + + SYNSA + desc SYNSA + 8 + 8 + read-write + + + SYNCLKA + desc SYNCLKA + 9 + 9 + read-write + + + ASYNCLKA + desc ASYNCLKA + 10 + 10 + read-write + + + HSTAA + desc HSTAA + 12 + 12 + read-write + + + HSTPA + desc HSTPA + 13 + 13 + read-write + + + HCLEA + desc HCLEA + 14 + 14 + read-write + + + HICPA + desc HICPA + 15 + 15 + read-write + + + CSTB + desc CSTB + 16 + 16 + read-write + + + CAPMDB + desc CAPMDB + 17 + 17 + read-write + + + INTENB + desc INTENB + 18 + 18 + read-write + + + CKDIVB + desc CKDIVB + 23 + 20 + read-write + + + SYNSB + desc SYNSB + 24 + 24 + read-write + + + SYNCLKB + desc SYNCLKB + 25 + 25 + read-write + + + ASYNCLKB + desc ASYNCLKB + 26 + 26 + read-write + + + HSTAB + desc HSTAB + 28 + 28 + read-write + + + HSTPB + desc HSTPB + 29 + 29 + read-write + + + HCLEB + desc HCLEB + 30 + 30 + read-write + + + HICPB + desc HICPB + 31 + 31 + read-write + + + + + STFLR + desc STFLR + 0x14 + 32 + read-write + 0x0 + 0x10001 + + + CMFA + desc CMFA + 0 + 0 + read-write + + + CMFB + desc CMFB + 16 + 16 + read-write + + + + + + + TMR02 + desc TMR0 + 0x40024400 + + 0x0 + 0x18 + + + + TMR41 + desc TMR4 + 0x40017000 + + 0x0 + 0xF2 + + + + OCCRUH + desc OCCRUH + 0x2 + 16 + read-write + 0x0 + 0xFFFF + + + OCCRUL + desc OCCRUL + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + OCCRVH + desc OCCRVH + 0xA + 16 + read-write + 0x0 + 0xFFFF + + + OCCRVL + desc OCCRVL + 0xE + 16 + read-write + 0x0 + 0xFFFF + + + OCCRWH + desc OCCRWH + 0x12 + 16 + read-write + 0x0 + 0xFFFF + + + OCCRWL + desc OCCRWL + 0x16 + 16 + read-write + 0x0 + 0xFFFF + + + OCSRU + desc OCSRU + 0x18 + 16 + read-write + 0xFF00 + 0xFF + + + OCEH + desc OCEH + 0 + 0 + read-write + + + OCEL + desc OCEL + 1 + 1 + read-write + + + OCPH + desc OCPH + 2 + 2 + read-write + + + OCPL + desc OCPL + 3 + 3 + read-write + + + OCIEH + desc OCIEH + 4 + 4 + read-write + + + OCIEL + desc OCIEL + 5 + 5 + read-write + + + OCFH + desc OCFH + 6 + 6 + read-write + + + OCFL + desc OCFL + 7 + 7 + read-write + + + + + OCERU + desc OCERU + 0x1A + 16 + read-write + 0x0 + 0x3FFF + + + CHBUFEN + desc CHBUFEN + 1 + 0 + read-write + + + CLBUFEN + desc CLBUFEN + 3 + 2 + read-write + + + MHBUFEN + desc MHBUFEN + 5 + 4 + read-write + + + MLBUFEN + desc MLBUFEN + 7 + 6 + read-write + + + LMCH + desc LMCH + 8 + 8 + read-write + + + LMCL + desc LMCL + 9 + 9 + read-write + + + LMMH + desc LMMH + 10 + 10 + read-write + + + LMML + desc LMML + 11 + 11 + read-write + + + MCECH + desc MCECH + 12 + 12 + read-write + + + MCECL + desc MCECL + 13 + 13 + read-write + + + + + OCSRV + desc OCSRV + 0x1C + 16 + read-write + 0xFF00 + 0xFF + + + OCEH + desc OCEH + 0 + 0 + read-write + + + OCEL + desc OCEL + 1 + 1 + read-write + + + OCPH + desc OCPH + 2 + 2 + read-write + + + OCPL + desc OCPL + 3 + 3 + read-write + + + OCIEH + desc OCIEH + 4 + 4 + read-write + + + OCIEL + desc OCIEL + 5 + 5 + read-write + + + OCFH + desc OCFH + 6 + 6 + read-write + + + OCFL + desc OCFL + 7 + 7 + read-write + + + + + OCERV + desc OCERV + 0x1E + 16 + read-write + 0x0 + 0x3FFF + + + CHBUFEN + desc CHBUFEN + 1 + 0 + read-write + + + CLBUFEN + desc CLBUFEN + 3 + 2 + read-write + + + MHBUFEN + desc MHBUFEN + 5 + 4 + read-write + + + MLBUFEN + desc MLBUFEN + 7 + 6 + read-write + + + LMCH + desc LMCH + 8 + 8 + read-write + + + LMCL + desc LMCL + 9 + 9 + read-write + + + LMMH + desc LMMH + 10 + 10 + read-write + + + LMML + desc LMML + 11 + 11 + read-write + + + MCECH + desc MCECH + 12 + 12 + read-write + + + MCECL + desc MCECL + 13 + 13 + read-write + + + + + OCSRW + desc OCSRW + 0x20 + 16 + read-write + 0xFF00 + 0xFF + + + OCEH + desc OCEH + 0 + 0 + read-write + + + OCEL + desc OCEL + 1 + 1 + read-write + + + OCPH + desc OCPH + 2 + 2 + read-write + + + OCPL + desc OCPL + 3 + 3 + read-write + + + OCIEH + desc OCIEH + 4 + 4 + read-write + + + OCIEL + desc OCIEL + 5 + 5 + read-write + + + OCFH + desc OCFH + 6 + 6 + read-write + + + OCFL + desc OCFL + 7 + 7 + read-write + + + + + OCERW + desc OCERW + 0x22 + 16 + read-write + 0x0 + 0x3FFF + + + CHBUFEN + desc CHBUFEN + 1 + 0 + read-write + + + CLBUFEN + desc CLBUFEN + 3 + 2 + read-write + + + MHBUFEN + desc MHBUFEN + 5 + 4 + read-write + + + MLBUFEN + desc MLBUFEN + 7 + 6 + read-write + + + LMCH + desc LMCH + 8 + 8 + read-write + + + LMCL + desc LMCL + 9 + 9 + read-write + + + LMMH + desc LMMH + 10 + 10 + read-write + + + LMML + desc LMML + 11 + 11 + read-write + + + MCECH + desc MCECH + 12 + 12 + read-write + + + MCECL + desc MCECL + 13 + 13 + read-write + + + + + OCMRHUH + desc OCMRHUH + 0x24 + 16 + read-write + 0x0 + 0xFFFF + + + OCFDCH + desc OCFDCH + 0 + 0 + read-write + + + OCFPKH + desc OCFPKH + 1 + 1 + read-write + + + OCFUCH + desc OCFUCH + 2 + 2 + read-write + + + OCFZRH + desc OCFZRH + 3 + 3 + read-write + + + OPDCH + desc OPDCH + 5 + 4 + read-write + + + OPPKH + desc OPPKH + 7 + 6 + read-write + + + OPUCH + desc OPUCH + 9 + 8 + read-write + + + OPZRH + desc OPZRH + 11 + 10 + read-write + + + OPNPKH + desc OPNPKH + 13 + 12 + read-write + + + OPNZRH + desc OPNZRH + 15 + 14 + read-write + + + + + OCMRLUL + desc OCMRLUL + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OCFDCL + desc OCFDCL + 0 + 0 + read-write + + + OCFPKL + desc OCFPKL + 1 + 1 + read-write + + + OCFUCL + desc OCFUCL + 2 + 2 + read-write + + + OCFZRL + desc OCFZRL + 3 + 3 + read-write + + + OPDCL + desc OPDCL + 5 + 4 + read-write + + + OPPKL + desc OPPKL + 7 + 6 + read-write + + + OPUCL + desc OPUCL + 9 + 8 + read-write + + + OPZRL + desc OPZRL + 11 + 10 + read-write + + + OPNPKL + desc OPNPKL + 13 + 12 + read-write + + + OPNZRL + desc OPNZRL + 15 + 14 + read-write + + + EOPNDCL + desc EOPNDCL + 17 + 16 + read-write + + + EOPNUCL + desc EOPNUCL + 19 + 18 + read-write + + + EOPDCL + desc EOPDCL + 21 + 20 + read-write + + + EOPPKL + desc EOPPKL + 23 + 22 + read-write + + + EOPUCL + desc EOPUCL + 25 + 24 + read-write + + + EOPZRL + desc EOPZRL + 27 + 26 + read-write + + + EOPNPKL + desc EOPNPKL + 29 + 28 + read-write + + + EOPNZRL + desc EOPNZRL + 31 + 30 + read-write + + + + + OCMRHVH + desc OCMRHVH + 0x2C + 16 + read-write + 0x0 + 0xFFFF + + + OCFDCH + desc OCFDCH + 0 + 0 + read-write + + + OCFPKH + desc OCFPKH + 1 + 1 + read-write + + + OCFUCH + desc OCFUCH + 2 + 2 + read-write + + + OCFZRH + desc OCFZRH + 3 + 3 + read-write + + + OPDCH + desc OPDCH + 5 + 4 + read-write + + + OPPKH + desc OPPKH + 7 + 6 + read-write + + + OPUCH + desc OPUCH + 9 + 8 + read-write + + + OPZRH + desc OPZRH + 11 + 10 + read-write + + + OPNPKH + desc OPNPKH + 13 + 12 + read-write + + + OPNZRH + desc OPNZRH + 15 + 14 + read-write + + + + + OCMRLVL + desc OCMRLVL + 0x30 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OCFDCL + desc OCFDCL + 0 + 0 + read-write + + + OCFPKL + desc OCFPKL + 1 + 1 + read-write + + + OCFUCL + desc OCFUCL + 2 + 2 + read-write + + + OCFZRL + desc OCFZRL + 3 + 3 + read-write + + + OPDCL + desc OPDCL + 5 + 4 + read-write + + + OPPKL + desc OPPKL + 7 + 6 + read-write + + + OPUCL + desc OPUCL + 9 + 8 + read-write + + + OPZRL + desc OPZRL + 11 + 10 + read-write + + + OPNPKL + desc OPNPKL + 13 + 12 + read-write + + + OPNZRL + desc OPNZRL + 15 + 14 + read-write + + + EOPNDCL + desc EOPNDCL + 17 + 16 + read-write + + + EOPNUCL + desc EOPNUCL + 19 + 18 + read-write + + + EOPDCL + desc EOPDCL + 21 + 20 + read-write + + + EOPPKL + desc EOPPKL + 23 + 22 + read-write + + + EOPUCL + desc EOPUCL + 25 + 24 + read-write + + + EOPZRL + desc EOPZRL + 27 + 26 + read-write + + + EOPNPKL + desc EOPNPKL + 29 + 28 + read-write + + + EOPNZRL + desc EOPNZRL + 31 + 30 + read-write + + + + + OCMRHWH + desc OCMRHWH + 0x34 + 16 + read-write + 0x0 + 0xFFFF + + + OCFDCH + desc OCFDCH + 0 + 0 + read-write + + + OCFPKH + desc OCFPKH + 1 + 1 + read-write + + + OCFUCH + desc OCFUCH + 2 + 2 + read-write + + + OCFZRH + desc OCFZRH + 3 + 3 + read-write + + + OPDCH + desc OPDCH + 5 + 4 + read-write + + + OPPKH + desc OPPKH + 7 + 6 + read-write + + + OPUCH + desc OPUCH + 9 + 8 + read-write + + + OPZRH + desc OPZRH + 11 + 10 + read-write + + + OPNPKH + desc OPNPKH + 13 + 12 + read-write + + + OPNZRH + desc OPNZRH + 15 + 14 + read-write + + + + + OCMRLWL + desc OCMRLWL + 0x38 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OCFDCL + desc OCFDCL + 0 + 0 + read-write + + + OCFPKL + desc OCFPKL + 1 + 1 + read-write + + + OCFUCL + desc OCFUCL + 2 + 2 + read-write + + + OCFZRL + desc OCFZRL + 3 + 3 + read-write + + + OPDCL + desc OPDCL + 5 + 4 + read-write + + + OPPKL + desc OPPKL + 7 + 6 + read-write + + + OPUCL + desc OPUCL + 9 + 8 + read-write + + + OPZRL + desc OPZRL + 11 + 10 + read-write + + + OPNPKL + desc OPNPKL + 13 + 12 + read-write + + + OPNZRL + desc OPNZRL + 15 + 14 + read-write + + + EOPNDCL + desc EOPNDCL + 17 + 16 + read-write + + + EOPNUCL + desc EOPNUCL + 19 + 18 + read-write + + + EOPDCL + desc EOPDCL + 21 + 20 + read-write + + + EOPPKL + desc EOPPKL + 23 + 22 + read-write + + + EOPUCL + desc EOPUCL + 25 + 24 + read-write + + + EOPZRL + desc EOPZRL + 27 + 26 + read-write + + + EOPNPKL + desc EOPNPKL + 29 + 28 + read-write + + + EOPNZRL + desc EOPNZRL + 31 + 30 + read-write + + + + + CPSR + desc CPSR + 0x42 + 16 + read-write + 0xFFFF + 0xFFFF + + + CNTR + desc CNTR + 0x46 + 16 + read-write + 0x0 + 0xFFFF + + + CCSR + desc CCSR + 0x48 + 16 + read-write + 0x40 + 0xE3FF + + + CKDIV + desc CKDIV + 3 + 0 + read-write + + + CLEAR + desc CLEAR + 4 + 4 + read-write + + + MODE + desc MODE + 5 + 5 + read-write + + + STOP + desc STOP + 6 + 6 + read-write + + + BUFEN + desc BUFEN + 7 + 7 + read-write + + + IRQPEN + desc IRQPEN + 8 + 8 + read-write + + + IRQPF + desc IRQPF + 9 + 9 + read-write + + + IRQZEN + desc IRQZEN + 13 + 13 + read-write + + + IRQZF + desc IRQZF + 14 + 14 + read-write + + + ECKEN + desc ECKEN + 15 + 15 + read-write + + + + + CVPR + desc CVPR + 0x4A + 16 + read-write + 0x0 + 0xFFFF + + + ZIM + desc ZIM + 3 + 0 + read-write + + + PIM + desc PIM + 7 + 4 + read-write + + + ZIC + desc ZIC + 11 + 8 + read-only + + + PIC + desc PIC + 15 + 12 + read-only + + + + + PFSRU + desc PFSRU + 0x82 + 16 + read-write + 0x0 + 0xFFFF + + + PDARU + desc PDARU + 0x84 + 16 + read-write + 0x0 + 0xFFFF + + + PDBRU + desc PDBRU + 0x86 + 16 + read-write + 0x0 + 0xFFFF + + + PFSRV + desc PFSRV + 0x8A + 16 + read-write + 0x0 + 0xFFFF + + + PDARV + desc PDARV + 0x8C + 16 + read-write + 0x0 + 0xFFFF + + + PDBRV + desc PDBRV + 0x8E + 16 + read-write + 0x0 + 0xFFFF + + + PFSRW + desc PFSRW + 0x92 + 16 + read-write + 0x0 + 0xFFFF + + + PDARW + desc PDARW + 0x94 + 16 + read-write + 0x0 + 0xFFFF + + + PDBRW + desc PDBRW + 0x96 + 16 + read-write + 0x0 + 0xFFFF + + + POCRU + desc POCRU + 0x98 + 16 + read-write + 0xFF00 + 0xF7 + + + DIVCK + desc DIVCK + 2 + 0 + read-write + + + PWMMD + desc PWMMD + 5 + 4 + read-write + + + LVLS + desc LVLS + 7 + 6 + read-write + + + + + POCRV + desc POCRV + 0x9C + 16 + read-write + 0xFF00 + 0xF7 + + + DIVCK + desc DIVCK + 2 + 0 + read-write + + + PWMMD + desc PWMMD + 5 + 4 + read-write + + + LVLS + desc LVLS + 7 + 6 + read-write + + + + + POCRW + desc POCRW + 0xA0 + 16 + read-write + 0xFF00 + 0xF7 + + + DIVCK + desc DIVCK + 2 + 0 + read-write + + + PWMMD + desc PWMMD + 5 + 4 + read-write + + + LVLS + desc LVLS + 7 + 6 + read-write + + + + + RCSR + desc RCSR + 0xA4 + 16 + read-write + 0x0 + 0xFFF7 + + + RTIDU + desc RTIDU + 0 + 0 + read-write + + + RTIDV + desc RTIDV + 1 + 1 + read-write + + + RTIDW + desc RTIDW + 2 + 2 + read-write + + + RTIFU + desc RTIFU + 4 + 4 + read-only + + + RTICU + desc RTICU + 5 + 5 + read-write + + + RTEU + desc RTEU + 6 + 6 + read-write + + + RTSU + desc RTSU + 7 + 7 + read-write + + + RTIFV + desc RTIFV + 8 + 8 + read-only + + + RTICV + desc RTICV + 9 + 9 + read-write + + + RTEV + desc RTEV + 10 + 10 + read-write + + + RTSV + desc RTSV + 11 + 11 + read-write + + + RTIFW + desc RTIFW + 12 + 12 + read-only + + + RTICW + desc RTICW + 13 + 13 + read-write + + + RTEW + desc RTEW + 14 + 14 + read-write + + + RTSW + desc RTSW + 15 + 15 + read-write + + + + + SCCRUH + desc SCCRUH + 0xB2 + 16 + read-write + 0x0 + 0xFFFF + + + SCCRUL + desc SCCRUL + 0xB6 + 16 + read-write + 0x0 + 0xFFFF + + + SCCRVH + desc SCCRVH + 0xBA + 16 + read-write + 0x0 + 0xFFFF + + + SCCRVL + desc SCCRVL + 0xBE + 16 + read-write + 0x0 + 0xFFFF + + + SCCRWH + desc SCCRWH + 0xC2 + 16 + read-write + 0x0 + 0xFFFF + + + SCCRWL + desc SCCRWL + 0xC6 + 16 + read-write + 0x0 + 0xFFFF + + + SCSRUH + desc SCSRUH + 0xC8 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRUH + desc SCMRUH + 0xCA + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRUL + desc SCSRUL + 0xCC + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRUL + desc SCMRUL + 0xCE + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRVH + desc SCSRVH + 0xD0 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRVH + desc SCMRVH + 0xD2 + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRVL + desc SCSRVL + 0xD4 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRVL + desc SCMRVL + 0xD6 + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRWH + desc SCSRWH + 0xD8 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRWH + desc SCMRWH + 0xDA + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRWL + desc SCSRWL + 0xDC + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRWL + desc SCMRWL + 0xDE + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + ECSR + desc ECSR + 0xF0 + 16 + read-write + 0x0 + 0x80 + + + HOLD + desc HOLD + 7 + 7 + read-write + + + + + + + TMR42 + desc TMR4 + 0x40024800 + + 0x0 + 0xF2 + + + + TMR43 + desc TMR4 + 0x40024C00 + + 0x0 + 0xF2 + + + + TMR4CR + desc TMR4CR + 0x40055408 + + 0x0 + 0xC + + + + ECER1 + desc ECER1 + 0x0 + 32 + read-write + 0x0 + 0x3 + + + EMBVAL + desc EMBVAL + 1 + 0 + read-write + + + + + ECER2 + desc ECER2 + 0x4 + 32 + read-write + 0x0 + 0x3 + + + EMBVAL + desc EMBVAL + 1 + 0 + read-write + + + + + ECER3 + desc ECER3 + 0x8 + 32 + read-write + 0x0 + 0x3 + + + EMBVAL + desc EMBVAL + 1 + 0 + read-write + + + + + + + TMR61 + desc TMR6 + 0x40018000 + + 0x0 + 0x90 + + + + CNTER + desc CNTER + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + CNT + desc CNT + 15 + 0 + read-write + + + + + PERAR + desc PERAR + 0x4 + 32 + read-write + 0xFFFF + 0xFFFF + + + PERA + desc PERA + 15 + 0 + read-write + + + + + PERBR + desc PERBR + 0x8 + 32 + read-write + 0xFFFF + 0xFFFF + + + PERB + desc PERB + 15 + 0 + read-write + + + + + PERCR + desc PERCR + 0xC + 32 + read-write + 0xFFFF + 0xFFFF + + + PERC + desc PERC + 15 + 0 + read-write + + + + + GCMAR + desc GCMAR + 0x10 + 32 + read-write + 0xFFFF + 0xFFFF + + + GCMA + desc GCMA + 15 + 0 + read-write + + + + + GCMBR + desc GCMBR + 0x14 + 32 + read-write + 0xFFFF + 0xFFFF + + + GCMB + desc GCMB + 15 + 0 + read-write + + + + + GCMCR + desc GCMCR + 0x18 + 32 + read-write + 0xFFFF + 0xFFFF + + + GCMC + desc GCMC + 15 + 0 + read-write + + + + + GCMDR + desc GCMDR + 0x1C + 32 + read-write + 0xFFFF + 0xFFFF + + + GCMD + desc GCMD + 15 + 0 + read-write + + + + + GCMER + desc GCMER + 0x20 + 32 + read-write + 0xFFFF + 0xFFFF + + + GCME + desc GCME + 15 + 0 + read-write + + + + + GCMFR + desc GCMFR + 0x24 + 32 + read-write + 0xFFFF + 0xFFFF + + + GCMF + desc GCMF + 15 + 0 + read-write + + + + + SCMAR + desc SCMAR + 0x28 + 32 + read-write + 0xFFFF + 0xFFFF + + + SCMA + desc SCMA + 15 + 0 + read-write + + + + + SCMBR + desc SCMBR + 0x2C + 32 + read-write + 0xFFFF + 0xFFFF + + + SCMB + desc SCMB + 15 + 0 + read-write + + + + + SCMCR + desc SCMCR + 0x30 + 32 + read-write + 0xFFFF + 0xFFFF + + + SCMC + desc SCMC + 15 + 0 + read-write + + + + + SCMDR + desc SCMDR + 0x34 + 32 + read-write + 0xFFFF + 0xFFFF + + + SCMD + desc SCMD + 15 + 0 + read-write + + + + + SCMER + desc SCMER + 0x38 + 32 + read-write + 0xFFFF + 0xFFFF + + + SCME + desc SCME + 15 + 0 + read-write + + + + + SCMFR + desc SCMFR + 0x3C + 32 + read-write + 0xFFFF + 0xFFFF + + + SCMF + desc SCMF + 15 + 0 + read-write + + + + + DTUAR + desc DTUAR + 0x40 + 32 + read-write + 0xFFFF + 0xFFFF + + + DTUA + desc DTUA + 15 + 0 + read-write + + + + + DTDAR + desc DTDAR + 0x44 + 32 + read-write + 0xFFFF + 0xFFFF + + + DTDA + desc DTDA + 15 + 0 + read-write + + + + + DTUBR + desc DTUBR + 0x48 + 32 + read-write + 0xFFFF + 0xFFFF + + + DTUB + desc DTUB + 15 + 0 + read-write + + + + + DTDBR + desc DTDBR + 0x4C + 32 + read-write + 0xFFFF + 0xFFFF + + + DTDB + desc DTDB + 15 + 0 + read-write + + + + + GCONR + desc GCONR + 0x50 + 32 + read-write + 0x100 + 0xF017F + + + START + desc START + 0 + 0 + read-write + + + MODE + desc MODE + 3 + 1 + read-write + + + CKDIV + desc CKDIV + 6 + 4 + read-write + + + DIR + desc DIR + 8 + 8 + read-write + + + ZMSKREV + desc ZMSKREV + 16 + 16 + read-write + + + ZMSKPOS + desc ZMSKPOS + 17 + 17 + read-write + + + ZMSKVAL + desc ZMSKVAL + 19 + 18 + read-write + + + + + ICONR + desc ICONR + 0x54 + 32 + read-write + 0x0 + 0xF01FF + + + INTENA + desc INTENA + 0 + 0 + read-write + + + INTENB + desc INTENB + 1 + 1 + read-write + + + INTENC + desc INTENC + 2 + 2 + read-write + + + INTEND + desc INTEND + 3 + 3 + read-write + + + INTENE + desc INTENE + 4 + 4 + read-write + + + INTENF + desc INTENF + 5 + 5 + read-write + + + INTENOVF + desc INTENOVF + 6 + 6 + read-write + + + INTENUDF + desc INTENUDF + 7 + 7 + read-write + + + INTENDTE + desc INTENDTE + 8 + 8 + read-write + + + INTENSAU + desc INTENSAU + 16 + 16 + read-write + + + INTENSAD + desc INTENSAD + 17 + 17 + read-write + + + INTENSBU + desc INTENSBU + 18 + 18 + read-write + + + INTENSBD + desc INTENSBD + 19 + 19 + read-write + + + + + PCONR + desc PCONR + 0x58 + 32 + read-write + 0x0 + 0x19FF19FF + + + CAPMDA + desc CAPMDA + 0 + 0 + read-write + + + STACA + desc STACA + 1 + 1 + read-write + + + STPCA + desc STPCA + 2 + 2 + read-write + + + STASTPSA + desc STASTPSA + 3 + 3 + read-write + + + CMPCA + desc CMPCA + 5 + 4 + read-write + + + PERCA + desc PERCA + 7 + 6 + read-write + + + OUTENA + desc OUTENA + 8 + 8 + read-write + + + EMBVALA + desc EMBVALA + 12 + 11 + read-write + + + CAPMDB + desc CAPMDB + 16 + 16 + read-write + + + STACB + desc STACB + 17 + 17 + read-write + + + STPCB + desc STPCB + 18 + 18 + read-write + + + STASTPSB + desc STASTPSB + 19 + 19 + read-write + + + CMPCB + desc CMPCB + 21 + 20 + read-write + + + PERCB + desc PERCB + 23 + 22 + read-write + + + OUTENB + desc OUTENB + 24 + 24 + read-write + + + EMBVALB + desc EMBVALB + 28 + 27 + read-write + + + + + BCONR + desc BCONR + 0x5C + 32 + read-write + 0x0 + 0x3333030F + + + BENA + desc BENA + 0 + 0 + read-write + + + BSEA + desc BSEA + 1 + 1 + read-write + + + BENB + desc BENB + 2 + 2 + read-write + + + BSEB + desc BSEB + 3 + 3 + read-write + + + BENP + desc BENP + 8 + 8 + read-write + + + BSEP + desc BSEP + 9 + 9 + read-write + + + BENSPA + desc BENSPA + 16 + 16 + read-write + + + BSESPA + desc BSESPA + 17 + 17 + read-write + + + BTRUSPA + desc BTRUSPA + 20 + 20 + read-write + + + BTRDSPA + desc BTRDSPA + 21 + 21 + read-write + + + BENSPB + desc BENSPB + 24 + 24 + read-write + + + BSESPB + desc BSESPB + 25 + 25 + read-write + + + BTRUSPB + desc BTRUSPB + 28 + 28 + read-write + + + BTRDSPB + desc BTRDSPB + 29 + 29 + read-write + + + + + DCONR + desc DCONR + 0x60 + 32 + read-write + 0x0 + 0x131 + + + DTCEN + desc DTCEN + 0 + 0 + read-write + + + DTBENU + desc DTBENU + 4 + 4 + read-write + + + DTBEND + desc DTBEND + 5 + 5 + read-write + + + SEPA + desc SEPA + 8 + 8 + read-write + + + + + FCONR + desc FCONR + 0x68 + 32 + read-write + 0x0 + 0x770077 + + + NOFIENGA + desc NOFIENGA + 0 + 0 + read-write + + + NOFICKGA + desc NOFICKGA + 2 + 1 + read-write + + + NOFIENGB + desc NOFIENGB + 4 + 4 + read-write + + + NOFICKGB + desc NOFICKGB + 6 + 5 + read-write + + + NOFIENTA + desc NOFIENTA + 16 + 16 + read-write + + + NOFICKTA + desc NOFICKTA + 18 + 17 + read-write + + + NOFIENTB + desc NOFIENTB + 20 + 20 + read-write + + + NOFICKTB + desc NOFICKTB + 22 + 21 + read-write + + + + + VPERR + desc VPERR + 0x6C + 32 + read-write + 0x0 + 0x1F0300 + + + SPPERIA + desc SPPERIA + 8 + 8 + read-write + + + SPPERIB + desc SPPERIB + 9 + 9 + read-write + + + PCNTE + desc PCNTE + 17 + 16 + read-write + + + PCNTS + desc PCNTS + 20 + 18 + read-write + + + + + STFLR + desc STFLR + 0x70 + 32 + read-write + 0x80000000 + 0x80E01FFF + + + CMAF + desc CMAF + 0 + 0 + read-write + + + CMBF + desc CMBF + 1 + 1 + read-write + + + CMCF + desc CMCF + 2 + 2 + read-write + + + CMDF + desc CMDF + 3 + 3 + read-write + + + CMEF + desc CMEF + 4 + 4 + read-write + + + CMFF + desc CMFF + 5 + 5 + read-write + + + OVFF + desc OVFF + 6 + 6 + read-write + + + UDFF + desc UDFF + 7 + 7 + read-write + + + DTEF + desc DTEF + 8 + 8 + read-only + + + CMSAUF + desc CMSAUF + 9 + 9 + read-write + + + CMSADF + desc CMSADF + 10 + 10 + read-write + + + CMSBUF + desc CMSBUF + 11 + 11 + read-write + + + CMSBDF + desc CMSBDF + 12 + 12 + read-write + + + VPERNUM + desc VPERNUM + 23 + 21 + read-only + + + DIRF + desc DIRF + 31 + 31 + read-only + + + + + HSTAR + desc HSTAR + 0x74 + 32 + read-write + 0x0 + 0x80000FF3 + + + HSTA0 + desc HSTA0 + 0 + 0 + read-write + + + HSTA1 + desc HSTA1 + 1 + 1 + read-write + + + HSTA4 + desc HSTA4 + 4 + 4 + read-write + + + HSTA5 + desc HSTA5 + 5 + 5 + read-write + + + HSTA6 + desc HSTA6 + 6 + 6 + read-write + + + HSTA7 + desc HSTA7 + 7 + 7 + read-write + + + HSTA8 + desc HSTA8 + 8 + 8 + read-write + + + HSTA9 + desc HSTA9 + 9 + 9 + read-write + + + HSTA10 + desc HSTA10 + 10 + 10 + read-write + + + HSTA11 + desc HSTA11 + 11 + 11 + read-write + + + STAS + desc STAS + 31 + 31 + read-write + + + + + HSTPR + desc HSTPR + 0x78 + 32 + read-write + 0x0 + 0x80000FF3 + + + HSTP0 + desc HSTP0 + 0 + 0 + read-write + + + HSTP1 + desc HSTP1 + 1 + 1 + read-write + + + HSTP4 + desc HSTP4 + 4 + 4 + read-write + + + HSTP5 + desc HSTP5 + 5 + 5 + read-write + + + HSTP6 + desc HSTP6 + 6 + 6 + read-write + + + HSTP7 + desc HSTP7 + 7 + 7 + read-write + + + HSTP8 + desc HSTP8 + 8 + 8 + read-write + + + HSTP9 + desc HSTP9 + 9 + 9 + read-write + + + HSTP10 + desc HSTP10 + 10 + 10 + read-write + + + HSTP11 + desc HSTP11 + 11 + 11 + read-write + + + STPS + desc STPS + 31 + 31 + read-write + + + + + HCLRR + desc HCLRR + 0x7C + 32 + read-write + 0x0 + 0x80000FF3 + + + HCLE0 + desc HCLE0 + 0 + 0 + read-write + + + HCLE1 + desc HCLE1 + 1 + 1 + read-write + + + HCLE4 + desc HCLE4 + 4 + 4 + read-write + + + HCLE5 + desc HCLE5 + 5 + 5 + read-write + + + HCLE6 + desc HCLE6 + 6 + 6 + read-write + + + HCLE7 + desc HCLE7 + 7 + 7 + read-write + + + HCLE8 + desc HCLE8 + 8 + 8 + read-write + + + HCLE9 + desc HCLE9 + 9 + 9 + read-write + + + HCLE10 + desc HCLE10 + 10 + 10 + read-write + + + HCLE11 + desc HCLE11 + 11 + 11 + read-write + + + CLES + desc CLES + 31 + 31 + read-write + + + + + HCPAR + desc HCPAR + 0x80 + 32 + read-write + 0x0 + 0xFF3 + + + HCPA0 + desc HCPA0 + 0 + 0 + read-write + + + HCPA1 + desc HCPA1 + 1 + 1 + read-write + + + HCPA4 + desc HCPA4 + 4 + 4 + read-write + + + HCPA5 + desc HCPA5 + 5 + 5 + read-write + + + HCPA6 + desc HCPA6 + 6 + 6 + read-write + + + HCPA7 + desc HCPA7 + 7 + 7 + read-write + + + HCPA8 + desc HCPA8 + 8 + 8 + read-write + + + HCPA9 + desc HCPA9 + 9 + 9 + read-write + + + HCPA10 + desc HCPA10 + 10 + 10 + read-write + + + HCPA11 + desc HCPA11 + 11 + 11 + read-write + + + + + HCPBR + desc HCPBR + 0x84 + 32 + read-write + 0x0 + 0xFF3 + + + HCPB0 + desc HCPB0 + 0 + 0 + read-write + + + HCPB1 + desc HCPB1 + 1 + 1 + read-write + + + HCPB4 + desc HCPB4 + 4 + 4 + read-write + + + HCPB5 + desc HCPB5 + 5 + 5 + read-write + + + HCPB6 + desc HCPB6 + 6 + 6 + read-write + + + HCPB7 + desc HCPB7 + 7 + 7 + read-write + + + HCPB8 + desc HCPB8 + 8 + 8 + read-write + + + HCPB9 + desc HCPB9 + 9 + 9 + read-write + + + HCPB10 + desc HCPB10 + 10 + 10 + read-write + + + HCPB11 + desc HCPB11 + 11 + 11 + read-write + + + + + HCUPR + desc HCUPR + 0x88 + 32 + read-write + 0x0 + 0x30FFF + + + HCUP0 + desc HCUP0 + 0 + 0 + read-write + + + HCUP1 + desc HCUP1 + 1 + 1 + read-write + + + HCUP2 + desc HCUP2 + 2 + 2 + read-write + + + HCUP3 + desc HCUP3 + 3 + 3 + read-write + + + HCUP4 + desc HCUP4 + 4 + 4 + read-write + + + HCUP5 + desc HCUP5 + 5 + 5 + read-write + + + HCUP6 + desc HCUP6 + 6 + 6 + read-write + + + HCUP7 + desc HCUP7 + 7 + 7 + read-write + + + HCUP8 + desc HCUP8 + 8 + 8 + read-write + + + HCUP9 + desc HCUP9 + 9 + 9 + read-write + + + HCUP10 + desc HCUP10 + 10 + 10 + read-write + + + HCUP11 + desc HCUP11 + 11 + 11 + read-write + + + HCUP16 + desc HCUP16 + 16 + 16 + read-write + + + HCUP17 + desc HCUP17 + 17 + 17 + read-write + + + + + HCDOR + desc HCDOR + 0x8C + 32 + read-write + 0x0 + 0x30FFF + + + HCDO0 + desc HCDO0 + 0 + 0 + read-write + + + HCDO1 + desc HCDO1 + 1 + 1 + read-write + + + HCDO2 + desc HCDO2 + 2 + 2 + read-write + + + HCDO3 + desc HCDO3 + 3 + 3 + read-write + + + HCDO4 + desc HCDO4 + 4 + 4 + read-write + + + HCDO5 + desc HCDO5 + 5 + 5 + read-write + + + HCDO6 + desc HCDO6 + 6 + 6 + read-write + + + HCDO7 + desc HCDO7 + 7 + 7 + read-write + + + HCDO8 + desc HCDO8 + 8 + 8 + read-write + + + HCDO9 + desc HCDO9 + 9 + 9 + read-write + + + HCDO10 + desc HCDO10 + 10 + 10 + read-write + + + HCDO11 + desc HCDO11 + 11 + 11 + read-write + + + HCDO16 + desc HCDO16 + 16 + 16 + read-write + + + HCDO17 + desc HCDO17 + 17 + 17 + read-write + + + + + + + TMR62 + desc TMR6 + 0x40018400 + + 0x0 + 0x90 + + + + TMR63 + desc TMR6 + 0x40018800 + + 0x0 + 0x90 + + + + TMR6CR + desc TMR6CR + 0x40018000 + TMR61 + + 0x0 + 0x400 + + + + SSTAR + desc SSTAR + 0x3F4 + 32 + read-write + 0x0 + 0x7 + + + SSTA1 + desc SSTA1 + 0 + 0 + read-write + + + SSTA2 + desc SSTA2 + 1 + 1 + read-write + + + SSTA3 + desc SSTA3 + 2 + 2 + read-write + + + + + SSTPR + desc SSTPR + 0x3F8 + 32 + read-write + 0x0 + 0x7 + + + SSTP1 + desc SSTP1 + 0 + 0 + read-write + + + SSTP2 + desc SSTP2 + 1 + 1 + read-write + + + SSTP3 + desc SSTP3 + 2 + 2 + read-write + + + + + SCLRR + desc SCLRR + 0x3FC + 32 + read-write + 0x0 + 0x7 + + + SCLE1 + desc SCLE1 + 0 + 0 + read-write + + + SCLE2 + desc SCLE2 + 1 + 1 + read-write + + + SCLE3 + desc SCLE3 + 2 + 2 + read-write + + + + + + + TMRA1 + desc TMRA + 0x40015000 + + 0x0 + 0x160 + + + + CNTER + desc CNTER + 0x0 + 16 + read-write + 0x0 + 0xFFFF + + + CNT + desc CNT + 15 + 0 + read-write + + + + + PERAR + desc PERAR + 0x4 + 16 + read-write + 0xFFFF + 0xFFFF + + + PER + desc PER + 15 + 0 + read-write + + + + + CMPAR1 + desc CMPAR1 + 0x40 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR2 + desc CMPAR2 + 0x44 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR3 + desc CMPAR3 + 0x48 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR4 + desc CMPAR4 + 0x4C + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR5 + desc CMPAR5 + 0x50 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR6 + desc CMPAR6 + 0x54 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR7 + desc CMPAR7 + 0x58 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR8 + desc CMPAR8 + 0x5C + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + BCSTR + desc BCSTR + 0x80 + 16 + read-write + 0x2 + 0xF0FF + + + START + desc START + 0 + 0 + read-write + + + DIR + desc DIR + 1 + 1 + read-write + + + MODE + desc MODE + 2 + 2 + read-write + + + SYNST + desc SYNST + 3 + 3 + read-write + + + CKDIV + desc CKDIV + 7 + 4 + read-write + + + ITENOVF + desc ITENOVF + 12 + 12 + read-write + + + ITENUDF + desc ITENUDF + 13 + 13 + read-write + + + OVFF + desc OVFF + 14 + 14 + read-write + + + UDFF + desc UDFF + 15 + 15 + read-write + + + + + HCONR + desc HCONR + 0x84 + 16 + read-write + 0x0 + 0xF777 + + + HSTA0 + desc HSTA0 + 0 + 0 + read-write + + + HSTA1 + desc HSTA1 + 1 + 1 + read-write + + + HSTA2 + desc HSTA2 + 2 + 2 + read-write + + + HSTP0 + desc HSTP0 + 4 + 4 + read-write + + + HSTP1 + desc HSTP1 + 5 + 5 + read-write + + + HSTP2 + desc HSTP2 + 6 + 6 + read-write + + + HCLE0 + desc HCLE0 + 8 + 8 + read-write + + + HCLE1 + desc HCLE1 + 9 + 9 + read-write + + + HCLE2 + desc HCLE2 + 10 + 10 + read-write + + + HCLE3 + desc HCLE3 + 12 + 12 + read-write + + + HCLE4 + desc HCLE4 + 13 + 13 + read-write + + + HCLE5 + desc HCLE5 + 14 + 14 + read-write + + + HCLE6 + desc HCLE6 + 15 + 15 + read-write + + + + + HCUPR + desc HCUPR + 0x88 + 16 + read-write + 0x0 + 0x1FFF + + + HCUP0 + desc HCUP0 + 0 + 0 + read-write + + + HCUP1 + desc HCUP1 + 1 + 1 + read-write + + + HCUP2 + desc HCUP2 + 2 + 2 + read-write + + + HCUP3 + desc HCUP3 + 3 + 3 + read-write + + + HCUP4 + desc HCUP4 + 4 + 4 + read-write + + + HCUP5 + desc HCUP5 + 5 + 5 + read-write + + + HCUP6 + desc HCUP6 + 6 + 6 + read-write + + + HCUP7 + desc HCUP7 + 7 + 7 + read-write + + + HCUP8 + desc HCUP8 + 8 + 8 + read-write + + + HCUP9 + desc HCUP9 + 9 + 9 + read-write + + + HCUP10 + desc HCUP10 + 10 + 10 + read-write + + + HCUP11 + desc HCUP11 + 11 + 11 + read-write + + + HCUP12 + desc HCUP12 + 12 + 12 + read-write + + + + + HCDOR + desc HCDOR + 0x8C + 16 + read-write + 0x0 + 0x1FFF + + + HCDO0 + desc HCDO0 + 0 + 0 + read-write + + + HCDO1 + desc HCDO1 + 1 + 1 + read-write + + + HCDO2 + desc HCDO2 + 2 + 2 + read-write + + + HCDO3 + desc HCDO3 + 3 + 3 + read-write + + + HCDO4 + desc HCDO4 + 4 + 4 + read-write + + + HCDO5 + desc HCDO5 + 5 + 5 + read-write + + + HCDO6 + desc HCDO6 + 6 + 6 + read-write + + + HCDO7 + desc HCDO7 + 7 + 7 + read-write + + + HCDO8 + desc HCDO8 + 8 + 8 + read-write + + + HCDO9 + desc HCDO9 + 9 + 9 + read-write + + + HCDO10 + desc HCDO10 + 10 + 10 + read-write + + + HCDO11 + desc HCDO11 + 11 + 11 + read-write + + + HCDO12 + desc HCDO12 + 12 + 12 + read-write + + + + + ICONR + desc ICONR + 0x90 + 16 + read-write + 0x0 + 0xFF + + + ITEN1 + desc ITEN1 + 0 + 0 + read-write + + + ITEN2 + desc ITEN2 + 1 + 1 + read-write + + + ITEN3 + desc ITEN3 + 2 + 2 + read-write + + + ITEN4 + desc ITEN4 + 3 + 3 + read-write + + + ITEN5 + desc ITEN5 + 4 + 4 + read-write + + + ITEN6 + desc ITEN6 + 5 + 5 + read-write + + + ITEN7 + desc ITEN7 + 6 + 6 + read-write + + + ITEN8 + desc ITEN8 + 7 + 7 + read-write + + + + + ECONR + desc ECONR + 0x94 + 16 + read-write + 0x0 + 0xFF + + + ETEN1 + desc ETEN1 + 0 + 0 + read-write + + + ETEN2 + desc ETEN2 + 1 + 1 + read-write + + + ETEN3 + desc ETEN3 + 2 + 2 + read-write + + + ETEN4 + desc ETEN4 + 3 + 3 + read-write + + + ETEN5 + desc ETEN5 + 4 + 4 + read-write + + + ETEN6 + desc ETEN6 + 5 + 5 + read-write + + + ETEN7 + desc ETEN7 + 6 + 6 + read-write + + + ETEN8 + desc ETEN8 + 7 + 7 + read-write + + + + + FCONR + desc FCONR + 0x98 + 16 + read-write + 0x0 + 0x7707 + + + NOFIENTG + desc NOFIENTG + 0 + 0 + read-write + + + NOFICKTG + desc NOFICKTG + 2 + 1 + read-write + + + NOFIENCA + desc NOFIENCA + 8 + 8 + read-write + + + NOFICKCA + desc NOFICKCA + 10 + 9 + read-write + + + NOFIENCB + desc NOFIENCB + 12 + 12 + read-write + + + NOFICKCB + desc NOFICKCB + 14 + 13 + read-write + + + + + STFLR + desc STFLR + 0x9C + 16 + read-write + 0x0 + 0xFF + + + CMPF1 + desc CMPF1 + 0 + 0 + read-write + + + CMPF2 + desc CMPF2 + 1 + 1 + read-write + + + CMPF3 + desc CMPF3 + 2 + 2 + read-write + + + CMPF4 + desc CMPF4 + 3 + 3 + read-write + + + CMPF5 + desc CMPF5 + 4 + 4 + read-write + + + CMPF6 + desc CMPF6 + 5 + 5 + read-write + + + CMPF7 + desc CMPF7 + 6 + 6 + read-write + + + CMPF8 + desc CMPF8 + 7 + 7 + read-write + + + + + BCONR1 + desc BCONR1 + 0xC0 + 16 + read-write + 0x0 + 0x7 + + + BEN + desc BEN + 0 + 0 + read-write + + + BSE0 + desc BSE0 + 1 + 1 + read-write + + + BSE1 + desc BSE1 + 2 + 2 + read-write + + + + + BCONR2 + desc BCONR2 + 0xC8 + 16 + read-write + 0x0 + 0x7 + + + BEN + desc BEN + 0 + 0 + read-write + + + BSE0 + desc BSE0 + 1 + 1 + read-write + + + BSE1 + desc BSE1 + 2 + 2 + read-write + + + + + BCONR3 + desc BCONR3 + 0xD0 + 16 + read-write + 0x0 + 0x7 + + + BEN + desc BEN + 0 + 0 + read-write + + + BSE0 + desc BSE0 + 1 + 1 + read-write + + + BSE1 + desc BSE1 + 2 + 2 + read-write + + + + + BCONR4 + desc BCONR4 + 0xD8 + 16 + read-write + 0x0 + 0x7 + + + BEN + desc BEN + 0 + 0 + read-write + + + BSE0 + desc BSE0 + 1 + 1 + read-write + + + BSE1 + desc BSE1 + 2 + 2 + read-write + + + + + CCONR1 + desc CCONR1 + 0x100 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR2 + desc CCONR2 + 0x104 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR3 + desc CCONR3 + 0x108 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR4 + desc CCONR4 + 0x10C + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR5 + desc CCONR5 + 0x110 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR6 + desc CCONR6 + 0x114 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR7 + desc CCONR7 + 0x118 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR8 + desc CCONR8 + 0x11C + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + PCONR1 + desc PCONR1 + 0x140 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR2 + desc PCONR2 + 0x144 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR3 + desc PCONR3 + 0x148 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR4 + desc PCONR4 + 0x14C + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR5 + desc PCONR5 + 0x150 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR6 + desc PCONR6 + 0x154 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR7 + desc PCONR7 + 0x158 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR8 + desc PCONR8 + 0x15C + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + + + TMRA2 + desc TMRA + 0x40015400 + + 0x0 + 0x160 + + + + TMRA3 + desc TMRA + 0x40015800 + + 0x0 + 0x160 + + + + TMRA4 + desc TMRA + 0x40015C00 + + 0x0 + 0x160 + + + + TMRA5 + desc TMRA + 0x40016000 + + 0x0 + 0x160 + + + + TMRA6 + desc TMRA + 0x40016400 + + 0x0 + 0x160 + + + + TRNG + desc TRNG + 0x40041000 + + 0x0 + 0x14 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x3 + + + EN + desc EN + 0 + 0 + read-write + + + RUN + desc RUN + 1 + 1 + read-write + + + + + MR + desc MR + 0x4 + 32 + read-write + 0x12 + 0x1D + + + LOAD + desc LOAD + 0 + 0 + read-write + + + CNT + desc CNT + 4 + 2 + read-write + + + + + DR0 + desc DR0 + 0xC + 32 + read-only + 0x8000000 + 0xFFFFFFFF + + + DR1 + desc DR1 + 0x10 + 32 + read-only + 0x8000200 + 0xFFFFFFFF + + + + + USART1 + desc USART + 0x4001D000 + + 0x0 + 0x1C + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x101EB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + RTOF + desc RTOF + 8 + 8 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + DR + desc DR + 0x4 + 32 + read-write + 0x1FF + 0x1FF03FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + RDR + desc RDR + 24 + 16 + read-write + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFFFF + 0xFF7F + + + DIV_FRACTION + desc DIV_FRACTION + 6 + 0 + read-write + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xF11B96FF + + + RTOE + desc RTOE + 0 + 0 + read-write + + + RTOIE + desc RTOIE + 1 + 1 + read-write + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + write-only + + + CFE + desc CFE + 17 + 17 + write-only + + + CORE + desc CORE + 19 + 19 + write-only + + + CRTOF + desc CRTOF + 20 + 20 + write-only + + + MS + desc MS + 24 + 24 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + FBME + desc FBME + 29 + 29 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x0 + 0x3801 + + + MPE + desc MPE + 0 + 0 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0xE00220 + + + SCEN + desc SCEN + 5 + 5 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + BCN + desc BCN + 23 + 21 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0x3 + + + PSC + desc PSC + 1 + 0 + read-write + + + + + + + USART2 + desc USART + 0x4001D400 + + 0x0 + 0x1C + + + + USART3 + desc USART + 0x40021000 + + 0x0 + 0x1C + + + + USART4 + desc USART + 0x40021400 + + 0x0 + 0x1C + + + + USBFS + desc USBFS + 0x400C0000 + + 0x0 + 0xE04 + + + + GVBUSCFG + desc GVBUSCFG + 0x0 + 32 + read-write + 0x0 + 0xC0 + + + VBUSOVEN + desc VBUSOVEN + 6 + 6 + read-write + + + VBUSVAL + desc VBUSVAL + 7 + 7 + read-write + + + + + GAHBCFG + desc GAHBCFG + 0x8 + 32 + read-write + 0x0 + 0x1BF + + + GINTMSK + desc GINTMSK + 0 + 0 + read-write + + + HBSTLEN + desc HBSTLEN + 4 + 1 + read-write + + + DMAEN + desc DMAEN + 5 + 5 + read-write + + + TXFELVL + desc TXFELVL + 7 + 7 + read-write + + + PTXFELVL + desc PTXFELVL + 8 + 8 + read-write + + + + + GUSBCFG + desc GUSBCFG + 0xC + 32 + read-write + 0xA00 + 0x60003C47 + + + TOCAL + desc TOCAL + 2 + 0 + read-write + + + PHYSEL + desc PHYSEL + 6 + 6 + read-write + + + TRDT + desc TRDT + 13 + 10 + read-write + + + FHMOD + desc FHMOD + 29 + 29 + read-write + + + FDMOD + desc FDMOD + 30 + 30 + read-write + + + + + GRSTCTL + desc GRSTCTL + 0x10 + 32 + read-write + 0x80000000 + 0xC00007F7 + + + CSRST + desc CSRST + 0 + 0 + read-write + + + HSRST + desc HSRST + 1 + 1 + read-write + + + FCRST + desc FCRST + 2 + 2 + read-write + + + RXFFLSH + desc RXFFLSH + 4 + 4 + read-write + + + TXFFLSH + desc TXFFLSH + 5 + 5 + read-write + + + TXFNUM + desc TXFNUM + 10 + 6 + read-write + + + DMAREQ + desc DMAREQ + 30 + 30 + read-only + + + AHBIDL + desc AHBIDL + 31 + 31 + read-only + + + + + GINTSTS + desc GINTSTS + 0x14 + 32 + read-only + 0x14000020 + 0xF77CFCFB + + + CMOD + desc CMOD + 0 + 0 + read-only + + + MMIS + desc MMIS + 1 + 1 + read-write + + + SOF + desc SOF + 3 + 3 + read-write + + + RXFNE + desc RXFNE + 4 + 4 + read-only + + + NPTXFE + desc NPTXFE + 5 + 5 + read-only + + + GINAKEFF + desc GINAKEFF + 6 + 6 + read-only + + + GONAKEFF + desc GONAKEFF + 7 + 7 + read-only + + + ESUSP + desc ESUSP + 10 + 10 + read-write + + + USBSUSP + desc USBSUSP + 11 + 11 + read-write + + + USBRST + desc USBRST + 12 + 12 + read-write + + + ENUMDNE + desc ENUMDNE + 13 + 13 + read-write + + + ISOODRP + desc ISOODRP + 14 + 14 + read-write + + + EOPF + desc EOPF + 15 + 15 + read-write + + + IEPINT + desc IEPINT + 18 + 18 + read-only + + + OEPINT + desc OEPINT + 19 + 19 + read-only + + + IISOIXFR + desc IISOIXFR + 20 + 20 + read-write + + + IPXFR_INCOMPISOOUT + desc IPXFR_INCOMPISOOUT + 21 + 21 + read-write + + + DATAFSUSP + desc DATAFSUSP + 22 + 22 + read-write + + + HPRTINT + desc HPRTINT + 24 + 24 + read-only + + + HCINT + desc HCINT + 25 + 25 + read-only + + + PTXFE + desc PTXFE + 26 + 26 + read-only + + + CIDSCHG + desc CIDSCHG + 28 + 28 + read-write + + + DISCINT + desc DISCINT + 29 + 29 + read-write + + + VBUSVINT + desc VBUSVINT + 30 + 30 + read-write + + + WKUINT + desc WKUINT + 31 + 31 + read-write + + + + + GINTMSK + desc GINTMSK + 0x18 + 32 + read-write + 0x0 + 0xF77CFCFA + + + MMISM + desc MMISM + 1 + 1 + read-write + + + SOFM + desc SOFM + 3 + 3 + read-write + + + RXFNEM + desc RXFNEM + 4 + 4 + read-write + + + NPTXFEM + desc NPTXFEM + 5 + 5 + read-write + + + GINAKEFFM + desc GINAKEFFM + 6 + 6 + read-write + + + GONAKEFFM + desc GONAKEFFM + 7 + 7 + read-write + + + ESUSPM + desc ESUSPM + 10 + 10 + read-write + + + USBSUSPM + desc USBSUSPM + 11 + 11 + read-write + + + USBRSTM + desc USBRSTM + 12 + 12 + read-write + + + ENUMDNEM + desc ENUMDNEM + 13 + 13 + read-write + + + ISOODRPM + desc ISOODRPM + 14 + 14 + read-write + + + EOPFM + desc EOPFM + 15 + 15 + read-write + + + IEPIM + desc IEPIM + 18 + 18 + read-write + + + OEPIM + desc OEPIM + 19 + 19 + read-write + + + IISOIXFRM + desc IISOIXFRM + 20 + 20 + read-write + + + IPXFRM_INCOMPISOOUTM + desc IPXFRM_INCOMPISOOUTM + 21 + 21 + read-write + + + DATAFSUSPM + desc DATAFSUSPM + 22 + 22 + read-write + + + HPRTIM + desc HPRTIM + 24 + 24 + read-write + + + HCIM + desc HCIM + 25 + 25 + read-write + + + PTXFEM + desc PTXFEM + 26 + 26 + read-write + + + CIDSCHGM + desc CIDSCHGM + 28 + 28 + read-write + + + DISCIM + desc DISCIM + 29 + 29 + read-write + + + VBUSVIM + desc VBUSVIM + 30 + 30 + read-write + + + WKUIM + desc WKUIM + 31 + 31 + read-write + + + + + GRXSTSR + desc GRXSTSR + 0x1C + 32 + read-only + 0x0 + 0x1FFFFF + + + CHNUM_EPNUM + desc CHNUM_EPNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + + + GRXSTSP + desc GRXSTSP + 0x20 + 32 + read-only + 0x0 + 0x1FFFFF + + + CHNUM_EPNUM + desc CHNUM_EPNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + + + GRXFSIZ + desc GRXFSIZ + 0x24 + 32 + read-write + 0x140 + 0x7FF + + + RXFD + desc RXFD + 10 + 0 + read-write + + + + + HNPTXFSIZ + desc HNPTXFSIZ + 0x28 + 32 + read-write + 0x2000140 + 0xFFFFFFFF + + + NPTXFSA + desc NPTXFSA + 15 + 0 + read-write + + + NPTXFD + desc NPTXFD + 31 + 16 + read-write + + + + + HNPTXSTS + desc HNPTXSTS + 0x2C + 32 + read-only + 0x80100 + 0x7FFFFFFF + + + NPTXFSAV + desc NPTXFSAV + 15 + 0 + read-only + + + NPTQXSAV + desc NPTQXSAV + 23 + 16 + read-only + + + NPTXQTOP + desc NPTXQTOP + 30 + 24 + read-only + + + + + CID + desc CID + 0x3C + 32 + read-write + 0x12345678 + 0xFFFFFFFF + + + HPTXFSIZ + desc HPTXFSIZ + 0x100 + 32 + read-write + 0x1400280 + 0x7FF0FFF + + + PTXSA + desc PTXSA + 11 + 0 + read-write + + + PTXFD + desc PTXFD + 26 + 16 + read-write + + + + + DIEPTXF1 + desc DIEPTXF1 + 0x104 + 32 + read-write + 0x1000240 + 0x3FF0FFF + + + INEPTXSA + desc INEPTXSA + 11 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 25 + 16 + read-write + + + + + DIEPTXF2 + desc DIEPTXF2 + 0x108 + 32 + read-write + 0x1000340 + 0x3FF0FFF + + + INEPTXSA + desc INEPTXSA + 11 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 25 + 16 + read-write + + + + + DIEPTXF3 + desc DIEPTXF3 + 0x10C + 32 + read-write + 0x1000440 + 0x3FF0FFF + + + INEPTXSA + desc INEPTXSA + 11 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 25 + 16 + read-write + + + + + DIEPTXF4 + desc DIEPTXF4 + 0x110 + 32 + read-write + 0x1000540 + 0x3FF0FFF + + + INEPTXSA + desc INEPTXSA + 11 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 25 + 16 + read-write + + + + + DIEPTXF5 + desc DIEPTXF5 + 0x114 + 32 + read-write + 0x1000640 + 0x3FF0FFF + + + INEPTXSA + desc INEPTXSA + 11 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 25 + 16 + read-write + + + + + HCFG + desc HCFG + 0x400 + 32 + read-write + 0x200000 + 0x7 + + + FSLSPCS + desc FSLSPCS + 1 + 0 + read-write + + + FSLSS + desc FSLSS + 2 + 2 + read-write + + + + + HFIR + desc HFIR + 0x404 + 32 + read-write + 0xEA60 + 0xFFFF + + + FRIVL + desc FRIVL + 15 + 0 + read-write + + + + + HFNUM + desc HFNUM + 0x408 + 32 + read-only + 0x3FFF + 0xFFFFFFFF + + + FRNUM + desc FRNUM + 15 + 0 + read-only + + + FTREM + desc FTREM + 31 + 16 + read-only + + + + + HPTXSTS + desc HPTXSTS + 0x410 + 32 + read-only + 0x80100 + 0xFFFFFFFF + + + PTXFSAVL + desc PTXFSAVL + 15 + 0 + read-only + + + PTXQSAV + desc PTXQSAV + 23 + 16 + read-only + + + PTXQTOP + desc PTXQTOP + 31 + 24 + read-only + + + + + HAINT + desc HAINT + 0x414 + 32 + read-only + 0x0 + 0xFFF + + + HAINT + desc HAINT + 11 + 0 + read-only + + + + + HAINTMSK + desc HAINTMSK + 0x418 + 32 + read-write + 0x0 + 0xFFF + + + HAINTM + desc HAINTM + 11 + 0 + read-write + + + + + HPRT + desc HPRT + 0x440 + 32 + read-only + 0x0 + 0x61DCF + + + PCSTS + desc PCSTS + 0 + 0 + read-only + + + PCDET + desc PCDET + 1 + 1 + read-write + + + PENA + desc PENA + 2 + 2 + read-write + + + PENCHNG + desc PENCHNG + 3 + 3 + read-write + + + PRES + desc PRES + 6 + 6 + read-write + + + PSUSP + desc PSUSP + 7 + 7 + read-write + + + PRST + desc PRST + 8 + 8 + read-write + + + PLSTS + desc PLSTS + 11 + 10 + read-only + + + PWPR + desc PWPR + 12 + 12 + read-write + + + PSPD + desc PSPD + 18 + 17 + read-only + + + + + HCCHAR0 + desc HCCHAR0 + 0x500 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT0 + desc HCINT0 + 0x508 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK0 + desc HCINTMSK0 + 0x50C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ0 + desc HCTSIZ0 + 0x510 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA0 + desc HCDMA0 + 0x514 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR1 + desc HCCHAR1 + 0x520 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT1 + desc HCINT1 + 0x528 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK1 + desc HCINTMSK1 + 0x52C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ1 + desc HCTSIZ1 + 0x530 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA1 + desc HCDMA1 + 0x534 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR2 + desc HCCHAR2 + 0x540 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT2 + desc HCINT2 + 0x548 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK2 + desc HCINTMSK2 + 0x54C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ2 + desc HCTSIZ2 + 0x550 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA2 + desc HCDMA2 + 0x554 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR3 + desc HCCHAR3 + 0x560 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT3 + desc HCINT3 + 0x568 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK3 + desc HCINTMSK3 + 0x56C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ3 + desc HCTSIZ3 + 0x570 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA3 + desc HCDMA3 + 0x574 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR4 + desc HCCHAR4 + 0x580 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT4 + desc HCINT4 + 0x588 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK4 + desc HCINTMSK4 + 0x58C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ4 + desc HCTSIZ4 + 0x590 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA4 + desc HCDMA4 + 0x594 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR5 + desc HCCHAR5 + 0x5A0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT5 + desc HCINT5 + 0x5A8 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK5 + desc HCINTMSK5 + 0x5AC + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ5 + desc HCTSIZ5 + 0x5B0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA5 + desc HCDMA5 + 0x5B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR6 + desc HCCHAR6 + 0x5C0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT6 + desc HCINT6 + 0x5C8 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK6 + desc HCINTMSK6 + 0x5CC + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ6 + desc HCTSIZ6 + 0x5D0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA6 + desc HCDMA6 + 0x5D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR7 + desc HCCHAR7 + 0x5E0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT7 + desc HCINT7 + 0x5E8 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK7 + desc HCINTMSK7 + 0x5EC + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ7 + desc HCTSIZ7 + 0x5F0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA7 + desc HCDMA7 + 0x5F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR8 + desc HCCHAR8 + 0x600 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT8 + desc HCINT8 + 0x608 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK8 + desc HCINTMSK8 + 0x60C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ8 + desc HCTSIZ8 + 0x610 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA8 + desc HCDMA8 + 0x614 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR9 + desc HCCHAR9 + 0x620 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT9 + desc HCINT9 + 0x628 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK9 + desc HCINTMSK9 + 0x62C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ9 + desc HCTSIZ9 + 0x630 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA9 + desc HCDMA9 + 0x634 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR10 + desc HCCHAR10 + 0x640 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT10 + desc HCINT10 + 0x648 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK10 + desc HCINTMSK10 + 0x64C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ10 + desc HCTSIZ10 + 0x650 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA10 + desc HCDMA10 + 0x654 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR11 + desc HCCHAR11 + 0x660 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT11 + desc HCINT11 + 0x668 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK11 + desc HCINTMSK11 + 0x66C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ11 + desc HCTSIZ11 + 0x670 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA11 + desc HCDMA11 + 0x674 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DCFG + desc DCFG + 0x800 + 32 + read-write + 0x8200000 + 0x1FF7 + + + DSPD + desc DSPD + 1 + 0 + read-write + + + NZLSOHSK + desc NZLSOHSK + 2 + 2 + read-write + + + DAD + desc DAD + 10 + 4 + read-write + + + PFIVL + desc PFIVL + 12 + 11 + read-write + + + + + DCTL + desc DCTL + 0x804 + 32 + read-write + 0x2 + 0xF8F + + + RWUSIG + desc RWUSIG + 0 + 0 + read-write + + + SDIS + desc SDIS + 1 + 1 + read-write + + + GINSTS + desc GINSTS + 2 + 2 + read-only + + + GONSTS + desc GONSTS + 3 + 3 + read-only + + + SGINAK + desc SGINAK + 7 + 7 + write-only + + + CGINAK + desc CGINAK + 8 + 8 + write-only + + + SGONAK + desc SGONAK + 9 + 9 + write-only + + + CGONAK + desc CGONAK + 10 + 10 + write-only + + + POPRGDNE + desc POPRGDNE + 11 + 11 + read-write + + + + + DSTS + desc DSTS + 0x808 + 32 + read-only + 0x2 + 0x3FFF0F + + + SUSPSTS + desc SUSPSTS + 0 + 0 + read-only + + + ENUMSPD + desc ENUMSPD + 2 + 1 + read-only + + + EERR + desc EERR + 3 + 3 + read-only + + + FNSOF + desc FNSOF + 21 + 8 + read-only + + + + + DIEPMSK + desc DIEPMSK + 0x810 + 32 + read-write + 0x0 + 0x7B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + TOM + desc TOM + 3 + 3 + read-write + + + ITTXFEMSK + desc ITTXFEMSK + 4 + 4 + read-write + + + INEPNMM + desc INEPNMM + 5 + 5 + read-write + + + INEPNEM + desc INEPNEM + 6 + 6 + read-write + + + + + DOEPMSK + desc DOEPMSK + 0x814 + 32 + read-write + 0x0 + 0x1B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + STUPM + desc STUPM + 3 + 3 + read-write + + + OTEPDM + desc OTEPDM + 4 + 4 + read-write + + + + + DAINT + desc DAINT + 0x818 + 32 + read-write + 0x0 + 0x3F003F + + + IEPINT + desc IEPINT + 5 + 0 + read-write + + + OEPINT + desc OEPINT + 21 + 16 + read-write + + + + + DAINTMSK + desc DAINTMSK + 0x81C + 32 + read-write + 0x0 + 0x3F003F + + + IEPINTM + desc IEPINTM + 5 + 0 + read-write + + + OEPINTM + desc OEPINTM + 21 + 16 + read-write + + + + + DIEPEMPMSK + desc DIEPEMPMSK + 0x834 + 32 + read-write + 0x0 + 0x3F + + + INEPTXFEM + desc INEPTXFEM + 5 + 0 + read-write + + + + + DIEPCTL0 + desc DIEPCTL0 + 0x900 + 32 + read-write + 0x8000 + 0xCFEE8003 + + + MPSIZ + desc MPSIZ + 1 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT0 + desc DIEPINT0 + 0x908 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ0 + desc DIEPTSIZ0 + 0x910 + 32 + read-write + 0x0 + 0x18007F + + + XFRSIZ + desc XFRSIZ + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 20 + 19 + read-write + + + + + DIEPDMA0 + desc DIEPDMA0 + 0x914 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS0 + desc DTXFSTS0 + 0x918 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL1 + desc DIEPCTL1 + 0x920 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT1 + desc DIEPINT1 + 0x928 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ1 + desc DIEPTSIZ1 + 0x930 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DIEPDMA1 + desc DIEPDMA1 + 0x934 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS1 + desc DTXFSTS1 + 0x938 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL2 + desc DIEPCTL2 + 0x940 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT2 + desc DIEPINT2 + 0x948 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ2 + desc DIEPTSIZ2 + 0x950 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DIEPDMA2 + desc DIEPDMA2 + 0x954 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS2 + desc DTXFSTS2 + 0x958 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL3 + desc DIEPCTL3 + 0x960 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT3 + desc DIEPINT3 + 0x968 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ3 + desc DIEPTSIZ3 + 0x970 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DIEPDMA3 + desc DIEPDMA3 + 0x974 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS3 + desc DTXFSTS3 + 0x978 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL4 + desc DIEPCTL4 + 0x980 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT4 + desc DIEPINT4 + 0x988 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ4 + desc DIEPTSIZ4 + 0x990 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DIEPDMA4 + desc DIEPDMA4 + 0x994 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS4 + desc DTXFSTS4 + 0x998 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL5 + desc DIEPCTL5 + 0x9A0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT5 + desc DIEPINT5 + 0x9A8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ5 + desc DIEPTSIZ5 + 0x9B0 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DIEPDMA5 + desc DIEPDMA5 + 0x9B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS5 + desc DTXFSTS5 + 0x9B8 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DOEPCTL0 + desc DOEPCTL0 + 0xB00 + 32 + read-write + 0x8000 + 0xCC3E8003 + + + MPSIZ + desc MPSIZ + 1 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT0 + desc DOEPINT0 + 0xB08 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ0 + desc DOEPTSIZ0 + 0xB10 + 32 + read-write + 0x0 + 0x6008007F + + + XFRSIZ + desc XFRSIZ + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 19 + 19 + read-write + + + STUPCNT + desc STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA0 + desc DOEPDMA0 + 0xB14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL1 + desc DOEPCTL1 + 0xB20 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT1 + desc DOEPINT1 + 0xB28 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ1 + desc DOEPTSIZ1 + 0xB30 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA1 + desc DOEPDMA1 + 0xB34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL2 + desc DOEPCTL2 + 0xB40 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT2 + desc DOEPINT2 + 0xB48 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ2 + desc DOEPTSIZ2 + 0xB50 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA2 + desc DOEPDMA2 + 0xB54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL3 + desc DOEPCTL3 + 0xB60 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT3 + desc DOEPINT3 + 0xB68 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ3 + desc DOEPTSIZ3 + 0xB70 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA3 + desc DOEPDMA3 + 0xB74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL4 + desc DOEPCTL4 + 0xB80 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT4 + desc DOEPINT4 + 0xB88 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ4 + desc DOEPTSIZ4 + 0xB90 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA4 + desc DOEPDMA4 + 0xB94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL5 + desc DOEPCTL5 + 0xBA0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT5 + desc DOEPINT5 + 0xBA8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ5 + desc DOEPTSIZ5 + 0xBB0 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA5 + desc DOEPDMA5 + 0xBB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + GCCTL + desc GCCTL + 0xE00 + 32 + read-write + 0x0 + 0x3 + + + STPPCLK + desc STPPCLK + 0 + 0 + read-write + + + GATEHCLK + desc GATEHCLK + 1 + 1 + read-write + + + + + + + WDT + desc WDT + 0x40049000 + + 0x0 + 0xC + + + + CR + desc CR + 0x0 + 32 + read-write + 0x80010FF3 + 0x80010FF3 + + + PERI + desc PERI + 1 + 0 + read-write + + + CKS + desc CKS + 7 + 4 + read-write + + + WDPT + desc WDPT + 11 + 8 + read-write + + + SLPOFF + desc SLPOFF + 16 + 16 + read-write + + + ITS + desc ITS + 31 + 31 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-write + 0x0 + 0x3FFFF + + + CNT + desc CNT + 15 + 0 + read-only + + + UDF + desc UDF + 16 + 16 + read-write + + + REF + desc REF + 17 + 17 + read-write + + + + + RR + desc RR + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + RF + desc RF + 15 + 0 + read-write + + + + + + + diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460.mac b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460.mac new file mode 100644 index 0000000000..e30bd40aa2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460.mac @@ -0,0 +1,16 @@ +setup() +{ + ; +} + +execUserPreload() +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); +} +execUserFlashInit() // Called by debugger before loading flash loader in RAM. +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); +} + diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460.out b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460.out new file mode 100644 index 0000000000000000000000000000000000000000..bc22e45614324a3c7226aca23132dab4593052cd GIT binary patch literal 26660 zcmeHw349#InQv8Jn&}yhW_0Hi_AnJT_=UHXJVr=Ct#B1ik-P)jcyh zjPVgiy!Yy-n(FVUs_*;itLo~i>eiM;OBQp^nG+N?oe}iD!mLNy8G9MAkTJcMS-?+c z1w{2Ti|9_Cp{f7DiA%!KuSZK_R+Jri{ZFl}{zv@}j$QIiB^bn6N=(9=)+UjoKBl+M5C7+)M}?Rj+TgY3vt z$9Pj?D}R)+Xb!VJdhIE;v+0s|_zKt7n;N%mfhS* zxl1JvFWKCvL__ZyxpnVo^-8Nddi^C&XQ_v;ZyMLCl_>q!A=OLrz>$@g*UFGvFWI)% zD4{&Q8l|=8;)*wpHRLb;%Hr&?J+gKN=Rs}pz|n03E0#`A)xYu>u0{QGk2NhL3F;Bk^!gNi+A(HXtv%795~O)&rg#I# z29ADqAWbPwQ8bj&^C;rQ)s2;x@MvB%H~Pf8+tdT^s->QXcLlQg`ApaTUAgK(Wu|w( zJ8xHBVgK~T$!X38aJJ<=?ACT=yTPj*!j(_!S7z?|0r)+;JT(vV$;*#0Z_AsiY8))+ zXOnYgd~j&_5$=8ewV!A4!>ruw|1wfuZuB=JRmzqA+${aDTCN^4o9bIB_FT-EZ=qgi z)#-IEjn{eW^}21-{Qhl|{C+Rstp=}~%m)ViH3I|MZCagnt5!E~^tO)%jvhqZgZLcc zUc{#mA4UA>M??F-|IM)f!Q7_YC9c-x?`>TXXmW)t+usI`jvK%={B7Xqz(?LjZxe5& zn5Mf^^tV1@mj6+)r|qLgq;h5QU-!2=Rz(=@MAi&x zFY?qGQcUkKN|WEA`DzDi$e1|W0y*Y@#WAB>kQcG>|P!O;SPX zFdm&!V?N~DnW8xLJr9T0*zKUfZmA&i&B!Gh3}&H0QbE!*j2#*)18qi%;*>cPO{%eF zpj8f|EyFmVu}z>Y&Y(@l^#Fp(luf?eY?j5cc$Si-x-^&WGF(|Mm&@%kU7jqj%ZG|Z zuwWzdo%+1ZH!5G`CtE}VvN|qy3Pp@T_8o|gkYa(5V$+SJ@I7o?m%A0Q%^SU0pwL|Pd=Hv)cPMGFPunt`YANsMC7hl zgxN%gSdh2j#;one4*e!=r@HGT8<70qizv+LLG^j3Wy~BL+z17O9#q{tOr|- zLQdsGiO>2@va_Jm$25%t(;p`SzTFOT{~;;xtGtXu{z=jtA5o| zMg|jsE3xh*({v>q4J8Wu_@ zk_o0vW)c&Q_d!NwvL?ZJM@MfY8H5P&U|VNAd@V?>{P#F->+9%uIw3Z55CvJbf)m{2Of>N$Xa#`VI9Wdfd61NddG z7Xe;OEwmzpw&`t*ccPuxgNmn2&69*h323u0lnk*ws;6A_vln3XPm_D7DX&`-N%Y3z z-R$3?fxC9hRIaOEMQ`O|@cvY(l#E6)T8+I0w{XvyQUitPVS}^Zq}wQK6n9|@)~DO| zBJ?~8Vy5r@FI+9|tPu(}b;pv6x|4~Gj5ipCP!rsCCdOU`WH;Mr){-=AM0^uku7$`_ z%irP3(em;{EE%!Yyv!KGEzq1?xXnTBPl1}GBF%ul09k(x1*Dn_A-toe7)mmA{j4#8 z*MZf^Y9_mS7#^&BG>o=V84b8thC(q*vpfp`tiVM#q6x-uLBUZlJwl9Rq*V?r#&~<4 z7$#}35`oP9DKH`#@OH#in5^Fim822hfbfnHn{ije{loT_ZQK~gskb{Bv8?&&(3GCy zX!Ly#ng-A_q^7S3O>sY3kcfn?W&9gFyO3jwDW=B6F5CevSqq%T#pJ@CMFc~=U2-1L z+Z*X>`}o-dJtxxh;Fs|vN)C4VB~oeh6j^1QsS>F)diMOcGgcy%mXFwp=Vwon& z+KcXY0MU=BcL+W99juOU_u~+;q4V0{sz`5NSA_9qBZtcyH3*Da&o=pAUjY&xV~O<@ zDDZqrfuGw7G)I!n@xDYDI)sc|ejz%B1(Mk}t7bLbmfC%J521Y+`x@e?(TVh-MWGp3 zI$DMsoM;r*4BcTlkMZ5y%;jX?4&a>}UhyOq?~ua` zF^!+P2RyW9ksa#_T^*6nMj+IjPnokjW8K#VL+$N}NN+FWH}i?p1sYxKY5~{IBiMHt z3b+Y-e;UMEjObec#06LesIn2vx7x-K%Tz>2#l8>Rs4*+GIxSdy&d1mrxQU9E_xu1N z3bTrN7UOqwGf&v{9uS-?Uh&Wwl#h^LDVjo7eF7Zb;g6>L>%6#pOB2H{HJMop7Z zbJ60^9XX8MjJvvQvKELanoP`(89(4OnX@ECSq3-R0lUfWhkdf`#-v38{sb?cCOrHq z6#5bjhh+(C0`mKh0?74_gDJ~EB2yYb6N&j?EP?qwm=%F(v@wqZ^AaNS!Nh_GX1D&C zFbFRpjvC{Vm1y$$E@U zhPIG4f{Ey%+KPHnRGT#&%vm4MC z2*cPUphk_E$V8hEe+x6!V{RfGz+DOvGpuy4V)!`6aM?;$l1BQD;`Wl>wW5us2*dGU$mbFHqm0yQg z=?TMSG#M+tT@4gVJ7=eE<3N^Ik?pg^9US2Nx+ejO`Ei^T->Ld?Wz+m>bSnBEj-ui= z+Z+ie;|W&$s2Z?rRV7NyS%98dOWHWv?N4dFK-q9)R zeGtnL^<{2&NK^#c&QsX=_~o4GCVr73oZbR<)3Sz^@M)G2>kglG8OPrXW2g6I&)C8x zv9@4Cyt^ZIb#Pfc(G}{fj55CU={J6&XA9cGNJprzGuaEYBGB(-3B0|$lS0P?c6Ag} zg!VM^Yf5jj9cwEowjIg_Z1cr|yE@nz>xyL*eBQ=zG!nix#oDuRU8pl%)U$dAZ8oL% z{nQ)3_Qn6M-^&M~qfDY(GqJ(QhGZgyf+ej&(!xS(V6`1DZvUwsV0Xh|6tRi3Zr>m--hbuk@QgM!j%+VtxZ8Si%Lkv>-bz8y%qe;R> zDdDdmq1Ugg1$se1&-3f!bM&mDvhjMYy2;daRUd2VSpisDsn)rF^x1j0)Z)*!ohK<8 zJmDWllbvZv9-gq5!xKEhfL{^feICDOa!CH9y@^)zE3s_z%w2!zr*(Q=p=EpZGd^j% zJ)=yx4@tOZ*(jBcb`#Y97_HLL&V;&++qOg3!1(wf9z)Nh+chk0Zfb66>JE4IwMR~K zM)3c@tRfswM1tY2THIXuQy={61NxV8Y}Deu?l55w{_E`z=$G5brtaQkVi>kL*43Uu zwvISaku#EE6BTvjiHbzaiHbda!8&FFQxQ}niK~aqVkGu8CEV2;>kVSpia2k)^_hqD z-AXvQu_uzsd5E@>P*!g&Omh~Q@isLz{gH?rVm=g4F?^fg&RAOt@eXnflIT@+Jsl@X zG3-@Gm_W(G&)a|_KcUXFOdD)OkW4Ol*4n7P-Za~f_=c|Jh7`-x4M{QWk{O=mscD%+ z^lYRvMKq(6a2d{Wwa3ybEpw)AcK*TBHq5rfBxmILnWR-Lrios9Pf*|1f9I?ETk4Q$ zn=Yqq5}SxnBkCW#vHv&vA%$%h<9i4F4w}lH?sR#GWZagF?k{`g9qd0)8(pkKj`G;39-6phtIKsOyEgy9m?4F=K&^(!{V}Vj(WCk_?v3psM$7 z&Ij>*6u{N6spP<}v`%xDRiZ5!2tac#-y}WY*WF_PzQM=pJ`coGNV-b~i>|Acq}xi; ztzv9JfvV7>#iLt>a-BC;RVn*pL{T4SrBue?hfdt=!x(ow?(6v7&QLj?2AU*0ub#Ucz9a0BHdl6 zoA{kVqM`9H(LCE;PK)vAZd;XV^#bare=pq-s|1kAqnqj!L2#=J@`=H#E)uB&nMeCq(MEj5_Za~C|W&z)TO{a7q{3oR^ki6KE zlYx#hVef%)wvv(w0!zPBC6ba#fu!FmiKOI0fu!F$L}aIgN>2wY*V@Hg<{;^ixGZ^% zgQ7H317d+TBWjqLr&RKZH(X#Wi)eOUx=e*ST#sRYK`bd2JyPfl47$ATuRIPKPvc<;cX%;N@&JCBt*#qydOmQZkrGWyzeE4bMsJ zl6d8CB6$H;pit};lq3)bhfF)|1_^4XyouCbhzNlxA@blr3}mOwFvG@C15pCma8fe3Viz#fTRCf{1iStAZ!uCJDX|dcudJ|{5|Vass08S^@W)w*_)g72GUs2{ zLfE)Ppx+D&rJF>G*esajkILL?p{eG3H7r4@W|pRUT&f32qoPjZnp&f3n)--h2%Ogi z;LpGysAD`hMWnJ~)$dcyvB+1XdXO|4>NFksvP8aIf%6uLd~W=D#}P(Tv&Z8nkR!<1 z<8Ynp7o~W|X=)Btljjj|ex6|QjZw`)fymCG%C9NV)b4zN@CBTVLacmCE#&Gs*@V>8 z7rCm|n`)s~^#KIp=Uma$UvRn{lZ~Ik32Oc%=uX#TCPE{G$%qP@g#JRu==LEFd)opy zR)VOocffWCSHw2t4F+IDcaZOt{tnP1h|Zbk^jiSLHw95)^nU4UxXR?qI9pDPvZvF_ zri=Js#-S(CiF+EN!szwWH*u9&?4Tpp#7ZxpDU9Am?Z=g5O`TZ=#%7>bME?cQ*AX+0 zND_mEs4#j@^cT2t7}7@&ffS<+?158rmqUEw5l^n-yd2S`6!c!`4>RfV;8&V~UJm`+ zOa^((h!`dzDvaI`r9InJ4bD*+Vv&{5i=xx)GBVDb5W@sSh0)uhbY_OiNT0SKx(uaA zXgtikBRVun>kvPVPEF~Ir??z4_Q^TJ@#sGAD~1K5)7ZKNej_opz{G)xz(FLY5tttU zvjk2cF}s2J6EI&wTT9Gcz?=t7ug8EZF?)eo2TTQ8Q(_KKIl%leg`vm1E(N}V){;E* zjPny<;yA4$F&1t{9BZD>p*`s^c?fjM4rQ4s>an9Cl<`m@F@zT zth^{2LxG-i#Xc7XzbeCRUaxXJZv1W0-7yr*#mg$9Lb4_Df1(PjMTPwJiQJGC{#I0I zOf4TbtU6S7Rngr~iOQ&zU;?I4Gx0l6*(a@WH*_yi6y@!Se7vmk52#XCjl%M|rm1f+ zHk6;Qo5qClxkgvfBc{(V%B%Fg3lC*0=f2?bRvAX3=-cPr>o%`5UFs%%iZQO}PS{D; zudMhxjKjRN2Ik>ahN&6rioT<%h8vowntG{QnoU*o%@f{to7Wl}iXI6IUC6(L;mE;w z30fEE6SdS#1!wmZ?Y3gf=tWE2T3j&0$Ro4qIr(2BNzp3qIl{}6h2{H3t&t|;a?2$F|w}R zugJP~mgSF6n5wbXH^b21U*k5_b3C=iIiAbcSGi{Cwg3SVpik7MKrhioq^#mdaRN;z zP#ZD-uAq)KGS%&`FeA6<7Pq) zHWljp3XKUAP9O&?UIUMRD9F79u(+!JkgT9`BT!ysjqy)6uXh<`-Pv0HdUDF~!Fi8m>+;%duJc{7l2=hy&+)P@zUsJH>GUrb2bwVmFonid zh0YKwqLEJ8Oe++&P*K!>3-ZE3D6Of_NHgiWQL)NzY%V%nTSJD@UFZH1L*E9YQJuSeHcnV_KUoDux{CH-EZ7oQ zgCb#@@7Gqj=J4vPRK-|Z^fVdvzFSmvT*;+(EPh*>x#xTRR3O<38{8wB8Md-bE6j{S zq%6YBb51>L%c*94QM3@<<}kD|h3<0-ok-4TA?iyf<;|rETZEDCtsvKC!J>-#zeJxd zo^!x$-XI)#54mHvf`hH9_GXAzO2hxoHoQj~KIfmDwkmi|Ho+r@=6`eMkIC4E=Ygu~ zeX3^MQ1tYrcc|*(ckKq@1=l$i&VSyF$$V}zN=@S;BYAaI8?kAck7e7(mx1tGaK!us_#&{nVWTP zXhnCKH{|MWb5q`RTTqfBK7k+#cZN6u=sENRl`K?Pfugu?YvmKFMR&WkAC+LJ(~5RZ z?YQtBQ(5(z+cYNsysFLA=I<@-xpaR1L3H7uJ>+|7$p4%Wfu>nP1R827d_oZ}R@fLt zF@FIO&J`jYv_)_g?JSFu2+bFe2%Ami!qsk5JNN$i16OPxBt>E=Dk`7-nA_CNtQo5XVB#)m>Y!+#n5H_@b?!ttG_A#OxM|@Al7%YNSoV>O z3V)9Zi%{V@Ss?~HyF!ns@U2s>@cEV8cNj04U<%~@d@ENb33CsSTe%IhXoo}AdG;=l ziv@W*wT9bp6ZwL}7)+oI<<{g)OXQ}^RatOHV_o@jhfS7Zvx!ou5XrW_d^r>Eo#JzY z))Ksb6#2N%R-E4EWsAL`+OoXun!%sYh+BW5lEopMGg|tf{nxlvQIUwW#}YV?YXw(e z+dSDZ-%guxlCg6Ty*V7}23aIF^^A$OXhUT1i>&d!Br5L;^_(fwE{XNxRocvbaVor` zLLOo~L$w6)9goUbxC7-z=)(zCYSBQvG7j{*jtCsKy9erp<6T|g>OBujB&YWZ@bMiJ zWuN@lT}n^y(C_h2m<{eV;Zm#Oj5!ecB&^#V58{9kK8-^sKmfN#+WIJsbhpPs-SazR z$z*2)aJZ*$egnQt6WLI)wAQL1R0mMY;@xyf=ShOLU!0~b#8IV|k&fO#`6lZ$OaB;4 zi{ekyt*naWQJ4cKU4r46Gx5b7yx9v1j-E~z_yiv&I4gcH4_3mq zr`b9go!+YGooQ7pz2HKtVm&Sr(!=o~r<8}2dt2n*XVln(hSRuX=#%=A)M*-FkOblX zKc4)>JowWzo&Q5igOC5)0DDyyMi=A7HrQj zSS1k>$*y>Nq?1+R18$X}Bo0Zo^(9d#LRl9pYiDK2(>#~^F}I_R!Ec^a;?pMhs@Z2) zWp_M=x8BeUmADxvt7~N%1cl(BLkL#aIG9<^#hgKJf6%ZhDRXTGCx??^He0g%@H%7ojbZr@6m}&a<@%f%6&C)>Fl6o z?3JZ=#RNxsOEX=Jn4rr|zTr}1e{lqn#rFc6#isyM#ioq4gx<{>y3;Dy7KnU{y4#6& zK|Gm^ciFaWfKxVHIs}jfWw1&_kPcG^6Y;Jf&Ce2RVwYVJUN>uY?E>o1g9ELfU?bBG zZx7J227)DivCd6PgaB+<7YAGJ%z%kbn;1wCB>k%yFwysBz*PQEv512NK^NuI%Oe7` zVOm~yVB%jg1Qy@z77T`vhd#+8`3-TvMqbk@{o4Zx0FFE=%D*14lV4?qILmC=@)4bm z6x04A5(J&mxwys*7-fl1dJ&cA_u@Cx9<+s?X^)4A%?>2bGq`s2rTS>w{lg6Xe+ii0 z2tk6Nv;V{|y@Npz!EaDv+k^7I4KP!m4~d@AM`H$;2>PY^>FX(EFS0BCzXAI!;Jqn+ zS)YP+M351576JW0hW=fEGwZ(|FzuldH}QWSFfA<$5b(`_u}PDH$zHU3>d?OoIxQhO z@Lhmukx!wt-j)U|P=11$+_U*%|OE zz)gS`*z{`v-wc?x+=zb*;Qs~~iGcBe1L5xk2SEQvT-*(MsZIYD;3ojr+3=45)3)$V z8{Q9?c5bo%Dav~WFztSlzfgVu4tNUS88-YIz{>$w+AwS({*MPh!T-Mj|Jk+&<@aEN zShxL|VA?Rw&VXwGJN`xTHvp!6@^-ttrGVRQ|0nxh1(^Jw>=%GPUt_}n1x$PLPXF+O zPM_4>YL6EL-wv4mw+QhQ{EZ>-gMil&PSD?`=C%)gi98l$A$cGP0uhIVNB(9og6v3v zSnXm3OniS7SMtZoZ6BF@GLv$gMNMz?b!GrNI6^KTB6?W3xUUp#&@_R{kkE1E9&5nnHg>Rt|5Hw^^BE{pzl|P@a=4X9|M;esCXJ* zGplhel*guq^8I)S-+SO&N6wZJsGO$|Gt28-0Y5S`m~1-T$1?dg!Ji8TvkCgIfkQL( PIHcRaH{Aj3l*;)(--e>I literal 0 HcmV?d00001 diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460_otp.mac b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460_otp.mac new file mode 100644 index 0000000000..e30bd40aa2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460_otp.mac @@ -0,0 +1,16 @@ +setup() +{ + ; +} + +execUserPreload() +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); +} +execUserFlashInit() // Called by debugger before loading flash loader in RAM. +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); +} + diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460_otp.out b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F460_otp.out new file mode 100644 index 0000000000000000000000000000000000000000..c1e69334072c5c894b055041295e0ce80d4a6960 GIT binary patch literal 23452 zcmeHP3v^V~x!(J{GIM4onaL9fgad>}z=R|OL=*)AG||W_QE@fb$z(DiBS|LAOdzNQ ztw_aQtydA|NS`o?7h!yUDmXmbIzQguo;Y?mpHTP)-u+DtC%spj#uKKs;$I7lu{WDP_b^``Y3qCV@?Grpro+6k zp^ZPxSXUmi{&whbR{6@|`oiV6EDwxnSkbWZxx?)8`CX5_#TI#X6F1U1YaeB=*B<6p zbz2D6&%n{wmE~EG;js=^cUiCZvFf(!u0@_jh_hVNGhBhgl@rP*YNvSL(7eCc$E=6{ z_~w<&>iY~`vl?cc&ASS^^1FWe))nfWx75kL-8(`#2ly<{qdW4|rx6uU+nP20JE;sn1Dg4Nh zVC|73+D+Ob?Rss|k$1-*Ir8pWT$6FN;F^JJ6|QBtnvM*u^M52bxGTRgzsb|K^6kr4 zg&I8(%Whpq-kop+X|%2*@2W@q4gN;nMpu>|$k5;V8?%BBvqvvOnF+5n}RY!@0waiM-R7nTh3oPPp5 zQxlZVaQQDsI<9D#dn{O1FbwOsEPn*bc~H1`7``z`l7?4I*8QO&&PJ0Pf+1IEM{|F$ zPWVinD;ffg2V-z4?58R+(Zj+jB%~cA?b{mB>PDnpuM@2Sv?Wd^#4_K0QiNRtntvGW z(Hx@P4w^EIc87;(2l4DeA`_&{Hw5jq5oz^k6B>JaMA}yb?Y$9cUxv$JqROm}Olgh{ zuRwK;?S!7&hS6@xC0aRTB6lW8J#R$E)7Xp=X?2mt|Ot~yKKfrQW4$o0?RFCG-J%%U8M?l?|okS)K3FsC&hk1dq9 z7~Rlmt;d^p4e~mz`FQhQhrCW}Ki<4gAaAxelmfyahM@8K1+A-+iFL_HkF`AB9ZOj= z2IkMJXl-1)#%kW2O2>Lqt;>4aV;vo_4(ozMa(#QOH`-;LS~a&dlI&?sC8MpK-H}vR zcOudeOSX1GPHYp{Y9%@>@l{bq0vE4nZnWxW*Uy?|)hBxTP+ZbF|J15etE+0NYHI4{ zoI3l0Iki@2B55sNb1oxai@=q5Z<=Yk677m48TV*EF-U&*Y!fJR97OIW=f9n z6lyh#7MXICjfptMDqVk#dpxi^OSh#Nk0F>tLm#zgX}4I z{nOMu)J&^8KbB0z6TR#|VS%@ovfgxZGvoC}G0X(For$p*0om0y znyn-Y8*u#@R&IdG(#n^Sa;&@{8BfP-GtVqW+Rz6h*NRx{nx$M6!FOT%az$*4zS1%zUjWBHZ0Q63`;}k8Pd|<3rq1lT9S-K)-!%L4-|6+j&RsTb3jej0jF^> zxv*yu;Yg}S&LdK(SWo*0&mIn9?oaPNU&C7$HLw$xNYdzysm?fA5=k1pXYD&_5=ok- zV4V){jOTb@CbVEn^+a#-t(ZQXb1GzX8a;EpZ^4=i08JQ!4#9@ zM5k;y;2AgV8(^7-oW6KZWL-?ocKJoMr&Cs6cf5CfIMUIPjHObHhbPPsSh#8(fpzl< z^tX_E3ek{J$Z}l%#Xvj+M751z{$?9PEYonI8L)dP+i3FYPK<};=%asuSFgm=N_zD^ zs42WE9-WN$n+3wHWRjD^6t59s`BK39OQ(`kQ(!QMziaS~WmV+1>xnGiO!%g<$%OhI zq3o9sJ}_z8y}&&IT%ZXraEnn3j9-#lM4X2R+b7-&_@$wu`+&m8!u;O{egl?7(a$Wb z(^|RL1IW7zw@DxeA4I~x13Xka@7X-ef18c@4KT0aVt&$ucu3CUgh6-**Qly5sw;Ze zXSrBD#*;+W*I}qB>PyUb7{7_z6?P^(;AHU)s<4~5tT6{mFMRwfylgtT8tW0G&2TcB z7AkhY@L0z17aYUwISS)n=Vp;;tF*G=WC|r?7#!~4re9h&9aTN5s+BCGrIcbUJ??R= z%by7~Q=2-{;fwn_)}eY1awCs-!Y&Gd)TSuj@cGN!8~6e0j8+8W=dMv{DA?^(k z{&5>0OJa_Ch!>6}_kyWpy2 zn5T#ykUtG-x;%BaV&w9xVI-LlkdFGM;`Nj5_X8cs`sp6U8zl6r5-r?xk5W)VxF}|d z{sM^3#kyzKO;c@*%T0HooKfW_auLQ+YYi5xpLE>Bc4gHZWizniA3-%ShOJ7*`p|?~ z*_%peJd+)kJuqq&FZuyg6TOt$U#h>Il^s;D7Y8i8MA?mEw0RqkJl7NcJeoX}U8#o3 zq`!TchcA#7)l>&Q@!$oxaM6R?)qq*4U!^pc>UsGS z{OyCWrA_hnaDAe;GrlgoB9ZKgbXRpTe)%t7`LP}lw574mNPl-a1+*g2Z{`TR{W_XK z#|5^f3y;{2Eb}2HmF~cMV1{kGGJtJ~1aRxZ-SM8dOYnlt(XLo@eTKDf^TtSbR@9R^ z-ZWBO*?kIi+a1^aM8Ag*LU%EVZgXS9v4M0l0>P42DQQt*HL%+DeOLXv9%6T*(J1V4 zx}U^`^Z^yf+)Cm_o!b^+mqW4eh}OA!R<5q9dI3^=9<<^d>olWB$vUazUYuG`gSxHZ zp3$TsEoZ`czlDbWpsp6_MIpT)sE^Cjb4ts{>2>O5rmm~{7)#Fy!P82O&V!@R&(}yR z-naccQPI#6ZW~R0rZqwMc_&9p@CgUrBGkJQ_mep+f7sqcE09%KmU!a!KOMkp13J_} z%=y&Qa;5KX9c9YBM#??OMyYnR`l-G!TD7B1C97ud+g-c&j{ z4BH&<>Bu14Mx3n3S;?@;iaPRSMWW?o#h$`or7nr-2#S%!mLW44i9Mu5ds6XK7%T0> zx$XKVcI($D(e&oNSSIIQTKa~pR6I)a7MbxTH8Ta0i0xudl*llAi{S2fdj|0)atzYw zMRgM$fyglIR7aRZN#P3ya7-c6oz-c;Muf@bl4paB>Q80ae!vHM(gPWmX#;67^^zH$ z)uk#J95SVJ0NBt6N-^sFBvSGK~?|uxk9jA2LW77 znMxi8wE$jj6!x*3wNpOe--cPa6ZKF~_m)7X&nsi}T%WF!nHLRKURTGFbuqGT?3m(W zmD4PC)ljDCV^m??8sa-;GP!Q)ARhH=TMAKvdYfQtGIg)|)h&6t8Pau2QQ?rQKAC!^ z)nh1o17nVA896)r*qaHh*Fu>CYq#(qm@at?)Q0(dIoj)8@Gy% zfLA~0<BV0ofSuF4K5rdPW!39%=QK#XonW8bcEuv53du}QcT_9oc&B1LRNPO<_c`hxt9=4C(+ z;d0KtWlw_=-&9-*qi<>sA?4aPZkivL|h7^k7R!5W^i`kiA5Gd-^$Rrb&}!Q#wLdGxD-Yo%+OXmF=RJyiEamS z}lL13B;2XhTDWc>~Bv*fuQ zm<3SvQjByGLoYxZfjJGXl$f31*$vE>0uF{I&jy;_S#Xx*p;_z_VCKU&5<^qTEx;7R z84^RYw;uzun1*xKg9`}A28t8a`(=$}36(=wf=_+WS2iRH_ZHd8x|vgz-&Hkq^=sp6{nh}zSS70I9)f5@fD{UJ*5wsxrR|ut@od~H=xXZ%Hyv#jAZGz z7Tn`CFEKspW%^WOZ0XJLldfM_`6Y~Rd~z+^!>bKbGd7lfTT=}$EKxP}9Itens_0wB zzvDI68v~^eMTITYc7)@o@o=1|uz)_6<7O$$P!#Q^GR%TSOcaWy2 zA-Jr!;`Am_3^hoOltL|%!ZE65EMDCdCFh4_T!E>u@n2Db*JLI8%OD0ndY^|Fh1#=1 zN81!S45d&bRH$uII7S(j3adqX`{ywC7oiMQz54g8Xr{`IP(`U#5}aXP>M{IE;U>5{ z=k>VfE?qV2cKHFDQD~x3-6xQZf^D%lxg7Jd6Z|K!a_Jx zcVmS6q_3`{JgA}E((N~U16tuGa@V-<{6_-1Onc3ZxocPRYRc+6TGr*CJ!;l33J>js z$AyQee=Bt2?D##jRAEaLh2ItCg~hN}Q}2)-(siS9P0-j;|&=X`DX8`7tJ_Z}c|(lLBQpMHR2R`YouJ!|Vn&AJjTk&9z( zs28Tt;7Z{bjdQ%hFit3Y!d#mJk16USI5Xg_S6ZxeqGL7ApLQt%9fY>hdm9q4^9_VT-Ap+2S>|+23Dy zWbIXhvNRsr?<|k0sC@1tUQ;)7X0`~x^g@CTiUx{lsh8(*@?H3RJR5M}y9i@v6)RSJq zpmpZ`nX>@P`wL{xlTm ziS(UJH#fyo_=Ll~w?PF|R?5RDC$Xe3z9FrOM>`=qMj!22nYSJBxf0MDJ7Z|by?rn< zn&{~PS84%X%TE0BlcP6S$UpwCizlDhL9U~p7#Q4}qLZ!4liHxrU*YB6L>QaK_&l3- z^Z<9n+WRSv^>)M~y$ieJ>2!AtaI~*~VLiT%jtx|vTW3`gsuQRciC#+5{$SW{BPZw& zvHjdS(pD-Q&}f~Y^bhd15PuSymsPp43ogO#WjH!(7QWoZcPa4E39CM6kH2;D-?b~q z(bee=AL1jqkEIXDLo@L2NvI{)AYfIdW?7Zzo^hsCxe1A+Z0-1CflOhacC!8=M4Z4ALU{|KrSwch>(y<4ia#|Gon!agz~zT~9+ZP4^d1$1M_zwBz#> zS~sk(t*WVJMj+>0uM*&6_*gz(oy@UHR+Z|)fsu5i9VsW?jIUkV+2U#|xrwc+v62b4 z823%AN<4qUk@ogvY-0vWMtax9QVuAViya`|+nI3EG|*w6Fk)_)OWD!!ZJquw~L`bH45*@K_R)s$psfwg=Af~-P4WS6-J*>Qgm8Vbe9M%Uk zq0Yf4jjQnKE&g@mG*;D{h~tX@R6`XW)ajZ!8HYh3IP4I@HMI_Aj+2--=(H~lwUTnG z&EVv4GR$R7D=%2KV(EO=(D<2#=9a~4T2Kt;$Qxr(lylNYC8?hH=Cw-NPo~?*M z)2X&_GSL&JN!8lU&UmbTS+b>O4)wM{ffh-y$Y+N)j?i)if+gD^f5Qb6eWwd1`Mxrh*S_6OYQJS;&3ze17i56b@rK({^b z5j|s%#tbeIbf@yy0w#Y^J>Y*(Sv%2P@)Ce|X7bDO%U$Jf0-Y8Qkqbd*TLII)jsO9Z z{o7pd)u7X2oI}3>u)F^0pPim|(eDEMtP8#u@PE1BU4Wl=!H)nw;DUbv7{Q`j2p0ba zFaQAuq2G&uCjrKSKhCM>>>a>!T`>JmRU_afHk~#&z6cmw1%e+NP3-G{5eaw^64bs3 z4nf{(B<=*f&8D{krd=NLHyp9d`Ybe+~nt_C)>(p?&0Fv&v~-1Q)yD zAYgp%&n~z7AHj0~(|`Knj>r(7-@4&7pgZ672GJfl_|V@dSad-b(g&I#5OGLope1ov zAU{$dRw~*F#P??hK&scI*&{@88@C z+w{|i@U=pL$4G!H5O_8&H+nn@GTi#v^b3aYmBXP^?B#5bL?Ag)TyA*{lNtN0y|*U0 zBt0>N?`}Mzb~=?{Gm@N3hVWq)g}<}48C-ljhVZRDjjxFM z?(75L`?bOUe*p#YDe?dS literal 0 HcmV?d00001 diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf new file mode 100644 index 0000000000..dcc0be6376 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460_RAM.icf @@ -0,0 +1,56 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x1FFF8000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x1FFF8000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x1FFFFFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x20000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x20020000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_IRAM3_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM4_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM4_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM5_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM5_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x100; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x100; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf new file mode 100644 index 0000000000..e938594387 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xC.icf @@ -0,0 +1,50 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00; +define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf new file mode 100644 index 0000000000..35a29c5fa1 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/linker/HC32F460xE.icf @@ -0,0 +1,50 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00; +define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x20026FFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f460.s b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f460.s new file mode 100644 index 0000000000..c90e2f4408 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f460.s @@ -0,0 +1,991 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Startup for IAR */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/* Target-mcu HC32F460 */ +;/****************************************************************************/ + + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Peripheral Interrupts + DCD IRQ000_Handler + DCD IRQ001_Handler + DCD IRQ002_Handler + DCD IRQ003_Handler + DCD IRQ004_Handler + DCD IRQ005_Handler + DCD IRQ006_Handler + DCD IRQ007_Handler + DCD IRQ008_Handler + DCD IRQ009_Handler + DCD IRQ010_Handler + DCD IRQ011_Handler + DCD IRQ012_Handler + DCD IRQ013_Handler + DCD IRQ014_Handler + DCD IRQ015_Handler + DCD IRQ016_Handler + DCD IRQ017_Handler + DCD IRQ018_Handler + DCD IRQ019_Handler + DCD IRQ020_Handler + DCD IRQ021_Handler + DCD IRQ022_Handler + DCD IRQ023_Handler + DCD IRQ024_Handler + DCD IRQ025_Handler + DCD IRQ026_Handler + DCD IRQ027_Handler + DCD IRQ028_Handler + DCD IRQ029_Handler + DCD IRQ030_Handler + DCD IRQ031_Handler + DCD IRQ032_Handler + DCD IRQ033_Handler + DCD IRQ034_Handler + DCD IRQ035_Handler + DCD IRQ036_Handler + DCD IRQ037_Handler + DCD IRQ038_Handler + DCD IRQ039_Handler + DCD IRQ040_Handler + DCD IRQ041_Handler + DCD IRQ042_Handler + DCD IRQ043_Handler + DCD IRQ044_Handler + DCD IRQ045_Handler + DCD IRQ046_Handler + DCD IRQ047_Handler + DCD IRQ048_Handler + DCD IRQ049_Handler + DCD IRQ050_Handler + DCD IRQ051_Handler + DCD IRQ052_Handler + DCD IRQ053_Handler + DCD IRQ054_Handler + DCD IRQ055_Handler + DCD IRQ056_Handler + DCD IRQ057_Handler + DCD IRQ058_Handler + DCD IRQ059_Handler + DCD IRQ060_Handler + DCD IRQ061_Handler + DCD IRQ062_Handler + DCD IRQ063_Handler + DCD IRQ064_Handler + DCD IRQ065_Handler + DCD IRQ066_Handler + DCD IRQ067_Handler + DCD IRQ068_Handler + DCD IRQ069_Handler + DCD IRQ070_Handler + DCD IRQ071_Handler + DCD IRQ072_Handler + DCD IRQ073_Handler + DCD IRQ074_Handler + DCD IRQ075_Handler + DCD IRQ076_Handler + DCD IRQ077_Handler + DCD IRQ078_Handler + DCD IRQ079_Handler + DCD IRQ080_Handler + DCD IRQ081_Handler + DCD IRQ082_Handler + DCD IRQ083_Handler + DCD IRQ084_Handler + DCD IRQ085_Handler + DCD IRQ086_Handler + DCD IRQ087_Handler + DCD IRQ088_Handler + DCD IRQ089_Handler + DCD IRQ090_Handler + DCD IRQ091_Handler + DCD IRQ092_Handler + DCD IRQ093_Handler + DCD IRQ094_Handler + DCD IRQ095_Handler + DCD IRQ096_Handler + DCD IRQ097_Handler + DCD IRQ098_Handler + DCD IRQ099_Handler + DCD IRQ100_Handler + DCD IRQ101_Handler + DCD IRQ102_Handler + DCD IRQ103_Handler + DCD IRQ104_Handler + DCD IRQ105_Handler + DCD IRQ106_Handler + DCD IRQ107_Handler + DCD IRQ108_Handler + DCD IRQ109_Handler + DCD IRQ110_Handler + DCD IRQ111_Handler + DCD IRQ112_Handler + DCD IRQ113_Handler + DCD IRQ114_Handler + DCD IRQ115_Handler + DCD IRQ116_Handler + DCD IRQ117_Handler + DCD IRQ118_Handler + DCD IRQ119_Handler + DCD IRQ120_Handler + DCD IRQ121_Handler + DCD IRQ122_Handler + DCD IRQ123_Handler + DCD IRQ124_Handler + DCD IRQ125_Handler + DCD IRQ126_Handler + DCD IRQ127_Handler + DCD IRQ128_Handler + DCD IRQ129_Handler + DCD IRQ130_Handler + DCD IRQ131_Handler + DCD IRQ132_Handler + DCD IRQ133_Handler + DCD IRQ134_Handler + DCD IRQ135_Handler + DCD IRQ136_Handler + DCD IRQ137_Handler + DCD IRQ138_Handler + DCD IRQ139_Handler + DCD IRQ140_Handler + DCD IRQ141_Handler + DCD IRQ142_Handler + DCD IRQ143_Handler + + THUMB +; Dummy Exception Handlers (infinite loops which can be modified) + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler +;SetSRAM3Wait + LDR R0, =0x40050804 + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x77 + STR R1, [R0] + + LDR R0, =0x40050800 + MOV R1, #0x1100 + STR R1, [R0] + + LDR R0, =0x40050804 + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =0x4005080C + MOV R1, #0x76 + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK IRQ000_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ000_Handler + B IRQ000_Handler + + PUBWEAK IRQ001_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ001_Handler + B IRQ001_Handler + + PUBWEAK IRQ002_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ002_Handler + B IRQ002_Handler + + PUBWEAK IRQ003_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ003_Handler + B IRQ003_Handler + + PUBWEAK IRQ004_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ004_Handler + B IRQ004_Handler + + PUBWEAK IRQ005_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ005_Handler + B IRQ005_Handler + + PUBWEAK IRQ006_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ006_Handler + B IRQ006_Handler + + PUBWEAK IRQ007_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ007_Handler + B IRQ007_Handler + + PUBWEAK IRQ008_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ008_Handler + B IRQ008_Handler + + PUBWEAK IRQ009_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ009_Handler + B IRQ009_Handler + + PUBWEAK IRQ010_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ010_Handler + B IRQ010_Handler + + PUBWEAK IRQ011_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ011_Handler + B IRQ011_Handler + + PUBWEAK IRQ012_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ012_Handler + B IRQ012_Handler + + PUBWEAK IRQ013_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ013_Handler + B IRQ013_Handler + + PUBWEAK IRQ014_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ014_Handler + B IRQ014_Handler + + PUBWEAK IRQ015_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ015_Handler + B IRQ015_Handler + + PUBWEAK IRQ016_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ016_Handler + B IRQ016_Handler + + PUBWEAK IRQ017_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ017_Handler + B IRQ017_Handler + + PUBWEAK IRQ018_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ018_Handler + B IRQ018_Handler + + PUBWEAK IRQ019_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ019_Handler + B IRQ019_Handler + + PUBWEAK IRQ020_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ020_Handler + B IRQ020_Handler + + PUBWEAK IRQ021_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ021_Handler + B IRQ021_Handler + + PUBWEAK IRQ022_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ022_Handler + B IRQ022_Handler + + PUBWEAK IRQ023_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ023_Handler + B IRQ023_Handler + + PUBWEAK IRQ024_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ024_Handler + B IRQ024_Handler + + PUBWEAK IRQ025_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ025_Handler + B IRQ025_Handler + + PUBWEAK IRQ026_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ026_Handler + B IRQ026_Handler + + PUBWEAK IRQ027_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ027_Handler + B IRQ027_Handler + + PUBWEAK IRQ028_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ028_Handler + B IRQ028_Handler + + PUBWEAK IRQ029_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ029_Handler + B IRQ029_Handler + + PUBWEAK IRQ030_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ030_Handler + B IRQ030_Handler + + PUBWEAK IRQ031_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ031_Handler + B IRQ031_Handler + + PUBWEAK IRQ032_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ032_Handler + B IRQ032_Handler + + PUBWEAK IRQ033_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ033_Handler + B IRQ033_Handler + + PUBWEAK IRQ034_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ034_Handler + B IRQ034_Handler + + PUBWEAK IRQ035_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ035_Handler + B IRQ035_Handler + + PUBWEAK IRQ036_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ036_Handler + B IRQ036_Handler + + PUBWEAK IRQ037_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ037_Handler + B IRQ037_Handler + + PUBWEAK IRQ038_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ038_Handler + B IRQ038_Handler + + PUBWEAK IRQ039_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ039_Handler + B IRQ039_Handler + + PUBWEAK IRQ040_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ040_Handler + B IRQ040_Handler + + PUBWEAK IRQ041_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ041_Handler + B IRQ041_Handler + + PUBWEAK IRQ042_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ042_Handler + B IRQ042_Handler + + PUBWEAK IRQ043_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ043_Handler + B IRQ043_Handler + + PUBWEAK IRQ044_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ044_Handler + B IRQ044_Handler + + PUBWEAK IRQ045_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ045_Handler + B IRQ045_Handler + + PUBWEAK IRQ046_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ046_Handler + B IRQ046_Handler + + PUBWEAK IRQ047_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ047_Handler + B IRQ047_Handler + + PUBWEAK IRQ048_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ048_Handler + B IRQ048_Handler + + PUBWEAK IRQ049_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ049_Handler + B IRQ049_Handler + + PUBWEAK IRQ050_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ050_Handler + B IRQ050_Handler + + PUBWEAK IRQ051_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ051_Handler + B IRQ051_Handler + + PUBWEAK IRQ052_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ052_Handler + B IRQ052_Handler + + PUBWEAK IRQ053_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ053_Handler + B IRQ053_Handler + + PUBWEAK IRQ054_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ054_Handler + B IRQ054_Handler + + PUBWEAK IRQ055_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ055_Handler + B IRQ055_Handler + + PUBWEAK IRQ056_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ056_Handler + B IRQ056_Handler + + PUBWEAK IRQ057_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ057_Handler + B IRQ057_Handler + + PUBWEAK IRQ058_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ058_Handler + B IRQ058_Handler + + PUBWEAK IRQ059_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ059_Handler + B IRQ059_Handler + + PUBWEAK IRQ060_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ060_Handler + B IRQ060_Handler + + PUBWEAK IRQ061_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ061_Handler + B IRQ061_Handler + + PUBWEAK IRQ062_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ062_Handler + B IRQ062_Handler + + PUBWEAK IRQ063_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ063_Handler + B IRQ063_Handler + + PUBWEAK IRQ064_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ064_Handler + B IRQ064_Handler + + PUBWEAK IRQ065_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ065_Handler + B IRQ065_Handler + + PUBWEAK IRQ066_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ066_Handler + B IRQ066_Handler + + PUBWEAK IRQ067_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ067_Handler + B IRQ067_Handler + + PUBWEAK IRQ068_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ068_Handler + B IRQ068_Handler + + PUBWEAK IRQ069_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ069_Handler + B IRQ069_Handler + + PUBWEAK IRQ070_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ070_Handler + B IRQ070_Handler + + PUBWEAK IRQ071_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ071_Handler + B IRQ071_Handler + + PUBWEAK IRQ072_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ072_Handler + B IRQ072_Handler + + PUBWEAK IRQ073_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ073_Handler + B IRQ073_Handler + + PUBWEAK IRQ074_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ074_Handler + B IRQ074_Handler + + PUBWEAK IRQ075_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ075_Handler + B IRQ075_Handler + + PUBWEAK IRQ076_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ076_Handler + B IRQ076_Handler + + PUBWEAK IRQ077_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ077_Handler + B IRQ077_Handler + + PUBWEAK IRQ078_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ078_Handler + B IRQ078_Handler + + PUBWEAK IRQ079_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ079_Handler + B IRQ079_Handler + + PUBWEAK IRQ080_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ080_Handler + B IRQ080_Handler + + PUBWEAK IRQ081_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ081_Handler + B IRQ081_Handler + + PUBWEAK IRQ082_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ082_Handler + B IRQ082_Handler + + PUBWEAK IRQ083_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ083_Handler + B IRQ083_Handler + + PUBWEAK IRQ084_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ084_Handler + B IRQ084_Handler + + PUBWEAK IRQ085_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ085_Handler + B IRQ085_Handler + + PUBWEAK IRQ086_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ086_Handler + B IRQ086_Handler + + PUBWEAK IRQ087_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ087_Handler + B IRQ087_Handler + + PUBWEAK IRQ088_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ088_Handler + B IRQ088_Handler + + PUBWEAK IRQ089_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ089_Handler + B IRQ089_Handler + + PUBWEAK IRQ090_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ090_Handler + B IRQ090_Handler + + PUBWEAK IRQ091_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ091_Handler + B IRQ091_Handler + + PUBWEAK IRQ092_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ092_Handler + B IRQ092_Handler + + PUBWEAK IRQ093_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ093_Handler + B IRQ093_Handler + + PUBWEAK IRQ094_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ094_Handler + B IRQ094_Handler + + PUBWEAK IRQ095_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ095_Handler + B IRQ095_Handler + + PUBWEAK IRQ096_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ096_Handler + B IRQ096_Handler + + PUBWEAK IRQ097_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ097_Handler + B IRQ097_Handler + + PUBWEAK IRQ098_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ098_Handler + B IRQ098_Handler + + PUBWEAK IRQ099_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ099_Handler + B IRQ099_Handler + + PUBWEAK IRQ100_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ100_Handler + B IRQ100_Handler + + PUBWEAK IRQ101_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ101_Handler + B IRQ101_Handler + + PUBWEAK IRQ102_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ102_Handler + B IRQ102_Handler + + PUBWEAK IRQ103_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ103_Handler + B IRQ103_Handler + + PUBWEAK IRQ104_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ104_Handler + B IRQ104_Handler + + PUBWEAK IRQ105_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ105_Handler + B IRQ105_Handler + + PUBWEAK IRQ106_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ106_Handler + B IRQ106_Handler + + PUBWEAK IRQ107_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ107_Handler + B IRQ107_Handler + + PUBWEAK IRQ108_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ108_Handler + B IRQ108_Handler + + PUBWEAK IRQ109_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ109_Handler + B IRQ109_Handler + + PUBWEAK IRQ110_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ110_Handler + B IRQ110_Handler + + PUBWEAK IRQ111_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ111_Handler + B IRQ111_Handler + + PUBWEAK IRQ112_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ112_Handler + B IRQ112_Handler + + PUBWEAK IRQ113_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ113_Handler + B IRQ113_Handler + + PUBWEAK IRQ114_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ114_Handler + B IRQ114_Handler + + PUBWEAK IRQ115_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ115_Handler + B IRQ115_Handler + + PUBWEAK IRQ116_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ116_Handler + B IRQ116_Handler + + PUBWEAK IRQ117_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ117_Handler + B IRQ117_Handler + + PUBWEAK IRQ118_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ118_Handler + B IRQ118_Handler + + PUBWEAK IRQ119_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ119_Handler + B IRQ119_Handler + + PUBWEAK IRQ120_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ120_Handler + B IRQ120_Handler + + PUBWEAK IRQ121_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ121_Handler + B IRQ121_Handler + + PUBWEAK IRQ122_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ122_Handler + B IRQ122_Handler + + PUBWEAK IRQ123_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ123_Handler + B IRQ123_Handler + + PUBWEAK IRQ124_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ124_Handler + B IRQ124_Handler + + PUBWEAK IRQ125_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ125_Handler + B IRQ125_Handler + + PUBWEAK IRQ126_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ126_Handler + B IRQ126_Handler + + PUBWEAK IRQ127_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ127_Handler + B IRQ127_Handler + + PUBWEAK IRQ128_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ128_Handler + B IRQ128_Handler + + PUBWEAK IRQ129_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ129_Handler + B IRQ129_Handler + + PUBWEAK IRQ130_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ130_Handler + B IRQ130_Handler + + PUBWEAK IRQ131_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ131_Handler + B IRQ131_Handler + + PUBWEAK IRQ132_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ132_Handler + B IRQ132_Handler + + PUBWEAK IRQ133_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ133_Handler + B IRQ133_Handler + + PUBWEAK IRQ134_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ134_Handler + B IRQ134_Handler + + PUBWEAK IRQ135_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ135_Handler + B IRQ135_Handler + + PUBWEAK IRQ136_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ136_Handler + B IRQ136_Handler + + PUBWEAK IRQ137_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ137_Handler + B IRQ137_Handler + + PUBWEAK IRQ138_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ138_Handler + B IRQ138_Handler + + PUBWEAK IRQ139_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ139_Handler + B IRQ139_Handler + + PUBWEAK IRQ140_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ140_Handler + B IRQ140_Handler + + PUBWEAK IRQ141_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ141_Handler + B IRQ141_Handler + + PUBWEAK IRQ142_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ142_Handler + B IRQ142_Handler + + PUBWEAK IRQ143_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ143_Handler + B IRQ143_Handler + + END diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HDSC_HC32F460.svd b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HDSC_HC32F460.svd new file mode 100644 index 0000000000..03dbb3b098 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HDSC_HC32F460.svd @@ -0,0 +1,53428 @@ + + + HDSC + HDSC + HDSC_HC32F460 + ARMCM4 + 1.0 + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 32 + read-write + 0x0 + 0x0 + + + ADC1 + desc ADC + 0x40040000 + + 0x0 + 0xD0 + + + + STR + desc STR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + STRT + desc STRT + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x2 + 16 + read-write + 0x0 + 0x7F3 + + + MS + desc MS + 1 + 0 + read-write + + + ACCSEL + desc ACCSEL + 5 + 4 + read-write + + + CLREN + desc CLREN + 6 + 6 + read-write + + + DFMT + desc DFMT + 7 + 7 + read-write + + + AVCNT + desc AVCNT + 10 + 8 + read-write + + + + + CR1 + desc CR1 + 0x4 + 16 + read-write + 0x0 + 0x4 + + + RSCHSEL + desc RSCHSEL + 2 + 2 + read-write + + + + + TRGSR + desc TRGSR + 0xA + 16 + read-write + 0x0 + 0x8383 + + + TRGSELA + desc TRGSELA + 1 + 0 + read-write + + + TRGENA + desc TRGENA + 7 + 7 + read-write + + + TRGSELB + desc TRGSELB + 9 + 8 + read-write + + + TRGENB + desc TRGENB + 15 + 15 + read-write + + + + + CHSELRA + desc CHSELRA + 0xC + 32 + read-write + 0x0 + 0x1FFFF + + + CHSELA + desc CHSELA + 16 + 0 + read-write + + + + + CHSELRB + desc CHSELRB + 0x10 + 32 + read-write + 0x0 + 0x1FFFF + + + CHSELB + desc CHSELB + 16 + 0 + read-write + + + + + AVCHSELR + desc AVCHSELR + 0x14 + 32 + read-write + 0x0 + 0x1FFFF + + + AVCHSEL + desc AVCHSEL + 16 + 0 + read-write + + + + + SSTR0 + desc SSTR0 + 0x20 + 8 + read-write + 0xB + 0xFF + + + SSTR1 + desc SSTR1 + 0x21 + 8 + read-write + 0xB + 0xFF + + + SSTR2 + desc SSTR2 + 0x22 + 8 + read-write + 0xB + 0xFF + + + SSTR3 + desc SSTR3 + 0x23 + 8 + read-write + 0xB + 0xFF + + + SSTR4 + desc SSTR4 + 0x24 + 8 + read-write + 0xB + 0xFF + + + SSTR5 + desc SSTR5 + 0x25 + 8 + read-write + 0xB + 0xFF + + + SSTR6 + desc SSTR6 + 0x26 + 8 + read-write + 0xB + 0xFF + + + SSTR7 + desc SSTR7 + 0x27 + 8 + read-write + 0xB + 0xFF + + + SSTR8 + desc SSTR8 + 0x28 + 8 + read-write + 0xB + 0xFF + + + SSTR9 + desc SSTR9 + 0x29 + 8 + read-write + 0xB + 0xFF + + + SSTR10 + desc SSTR10 + 0x2A + 8 + read-write + 0xB + 0xFF + + + SSTR11 + desc SSTR11 + 0x2B + 8 + read-write + 0xB + 0xFF + + + SSTR12 + desc SSTR12 + 0x2C + 8 + read-write + 0xB + 0xFF + + + SSTR13 + desc SSTR13 + 0x2D + 8 + read-write + 0xB + 0xFF + + + SSTR14 + desc SSTR14 + 0x2E + 8 + read-write + 0xB + 0xFF + + + SSTR15 + desc SSTR15 + 0x2F + 8 + read-write + 0xB + 0xFF + + + SSTRL + desc SSTRL + 0x30 + 8 + read-write + 0xB + 0xFF + + + CHMUXR0 + desc CHMUXR0 + 0x38 + 16 + read-write + 0x3210 + 0xFFFF + + + CH00MUX + desc CH00MUX + 3 + 0 + read-write + + + CH01MUX + desc CH01MUX + 7 + 4 + read-write + + + CH02MUX + desc CH02MUX + 11 + 8 + read-write + + + CH03MUX + desc CH03MUX + 15 + 12 + read-write + + + + + CHMUXR1 + desc CHMUXR1 + 0x3A + 16 + read-write + 0x7654 + 0xFFFF + + + CH04MUX + desc CH04MUX + 3 + 0 + read-write + + + CH05MUX + desc CH05MUX + 7 + 4 + read-write + + + CH06MUX + desc CH06MUX + 11 + 8 + read-write + + + CH07MUX + desc CH07MUX + 15 + 12 + read-write + + + + + CHMUXR2 + desc CHMUXR2 + 0x3C + 16 + read-write + 0xBA98 + 0xFFFF + + + CH08MUX + desc CH08MUX + 3 + 0 + read-write + + + CH09MUX + desc CH09MUX + 7 + 4 + read-write + + + CH10MUX + desc CH10MUX + 11 + 8 + read-write + + + CH11MUX + desc CH11MUX + 15 + 12 + read-write + + + + + CHMUXR3 + desc CHMUXR3 + 0x3E + 16 + read-write + 0xFEDC + 0xFFFF + + + CH12MUX + desc CH12MUX + 3 + 0 + read-write + + + CH13MUX + desc CH13MUX + 7 + 4 + read-write + + + CH14MUX + desc CH14MUX + 11 + 8 + read-write + + + CH15MUX + desc CH15MUX + 15 + 12 + read-write + + + + + ISR + desc ISR + 0x46 + 8 + read-write + 0x0 + 0x3 + + + EOCAF + desc EOCAF + 0 + 0 + read-write + + + EOCBF + desc EOCBF + 1 + 1 + read-write + + + + + ICR + desc ICR + 0x47 + 8 + read-write + 0x0 + 0x3 + + + EOCAIEN + desc EOCAIEN + 0 + 0 + read-write + + + EOCBIEN + desc EOCBIEN + 1 + 1 + read-write + + + + + SYNCCR + desc SYNCCR + 0x4C + 16 + read-write + 0xC00 + 0xFF71 + + + SYNCEN + desc SYNCEN + 0 + 0 + read-write + + + SYNCMD + desc SYNCMD + 6 + 4 + read-write + + + SYNCDLY + desc SYNCDLY + 15 + 8 + read-write + + + + + DR0 + desc DR0 + 0x50 + 16 + read-only + 0x0 + 0xFFFF + + + DR1 + desc DR1 + 0x52 + 16 + read-only + 0x0 + 0xFFFF + + + DR2 + desc DR2 + 0x54 + 16 + read-only + 0x0 + 0xFFFF + + + DR3 + desc DR3 + 0x56 + 16 + read-only + 0x0 + 0xFFFF + + + DR4 + desc DR4 + 0x58 + 16 + read-only + 0x0 + 0xFFFF + + + DR5 + desc DR5 + 0x5A + 16 + read-only + 0x0 + 0xFFFF + + + DR6 + desc DR6 + 0x5C + 16 + read-only + 0x0 + 0xFFFF + + + DR7 + desc DR7 + 0x5E + 16 + read-only + 0x0 + 0xFFFF + + + DR8 + desc DR8 + 0x60 + 16 + read-only + 0x0 + 0xFFFF + + + DR9 + desc DR9 + 0x62 + 16 + read-only + 0x0 + 0xFFFF + + + DR10 + desc DR10 + 0x64 + 16 + read-only + 0x0 + 0xFFFF + + + DR11 + desc DR11 + 0x66 + 16 + read-only + 0x0 + 0xFFFF + + + DR12 + desc DR12 + 0x68 + 16 + read-only + 0x0 + 0xFFFF + + + DR13 + desc DR13 + 0x6A + 16 + read-only + 0x0 + 0xFFFF + + + DR14 + desc DR14 + 0x6C + 16 + read-only + 0x0 + 0xFFFF + + + DR15 + desc DR15 + 0x6E + 16 + read-only + 0x0 + 0xFFFF + + + DR16 + desc DR16 + 0x70 + 16 + read-only + 0x0 + 0xFFFF + + + AWDCR + desc AWDCR + 0xA0 + 16 + read-write + 0x0 + 0x1D1 + + + AWDEN + desc AWDEN + 0 + 0 + read-write + + + AWDMD + desc AWDMD + 4 + 4 + read-write + + + AWDSS + desc AWDSS + 7 + 6 + read-write + + + AWDIEN + desc AWDIEN + 8 + 8 + read-write + + + + + AWDDR0 + desc AWDDR0 + 0xA4 + 16 + read-write + 0x0 + 0xFFFF + + + AWDDR1 + desc AWDDR1 + 0xA6 + 16 + read-write + 0x0 + 0xFFFF + + + AWDCHSR + desc AWDCHSR + 0xAC + 32 + read-write + 0x0 + 0x1FFFF + + + AWDCH + desc AWDCH + 16 + 0 + read-write + + + + + AWDSR + desc AWDSR + 0xB0 + 32 + read-write + 0x0 + 0x1FFFF + + + AWDF + desc AWDF + 16 + 0 + read-write + + + + + PGACR + desc PGACR + 0xC0 + 16 + read-write + 0x0 + 0xF + + + PGACTL + desc PGACTL + 3 + 0 + read-write + + + + + PGAGSR + desc PGAGSR + 0xC2 + 16 + read-write + 0x0 + 0xF + + + GAIN + desc GAIN + 3 + 0 + read-write + + + + + PGAINSR0 + desc PGAINSR0 + 0xCC + 16 + read-write + 0x0 + 0x1FF + + + PGAINSEL + desc PGAINSEL + 8 + 0 + read-write + + + + + PGAINSR1 + desc PGAINSR1 + 0xCE + 16 + read-write + 0x0 + 0x1 + + + PGAVSSEN + desc PGAVSSEN + 0 + 0 + read-write + + + + + + + ADC2 + desc ADC + 0x40040400 + + 0x0 + 0xD0 + + + + AES + desc AES + 0x40008000 + + 0x0 + 0x30 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x3 + + + START + desc START + 0 + 0 + read-write + + + MODE + desc MODE + 1 + 1 + read-write + + + + + DR0 + desc DR0 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR1 + desc DR1 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR2 + desc DR2 + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR3 + desc DR3 + 0x1C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR0 + desc KR0 + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR1 + desc KR1 + 0x24 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR2 + desc KR2 + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + KR3 + desc KR3 + 0x2C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + AOS + desc AOS + 0x40010800 + + 0x0 + 0x174 + + + + INTSFTTRG + desc INTSFTTRG + 0x0 + 32 + write-only + 0x0 + 0x1 + + + STRG + desc STRG + 0 + 0 + write-only + + + + + DCU_TRGSEL1 + desc DCU_TRGSEL1 + 0x4 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DCU_TRGSEL2 + desc DCU_TRGSEL2 + 0x8 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DCU_TRGSEL3 + desc DCU_TRGSEL3 + 0xC + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DCU_TRGSEL4 + desc DCU_TRGSEL4 + 0x10 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL0 + desc DMA1_TRGSEL0 + 0x14 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL1 + desc DMA1_TRGSEL1 + 0x18 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL2 + desc DMA1_TRGSEL2 + 0x1C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA1_TRGSEL3 + desc DMA1_TRGSEL3 + 0x20 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL0 + desc DMA2_TRGSEL0 + 0x24 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL1 + desc DMA2_TRGSEL1 + 0x28 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL2 + desc DMA2_TRGSEL2 + 0x2C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA2_TRGSEL3 + desc DMA2_TRGSEL3 + 0x30 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + DMA_TRGSELRC + desc DMA_TRGSELRC + 0x34 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR6_HTSSR0 + desc TMR6_HTSSR0 + 0x38 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR6_HTSSR1 + desc TMR6_HTSSR1 + 0x3C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMR0_HTSSR + desc TMR0_HTSSR + 0x40 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + PEVNTTRGSR12 + desc PEVNTTRGSR12 + 0x44 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + PEVNTTRGSR34 + desc PEVNTTRGSR34 + 0x48 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMRA_HTSSR0 + desc TMRA_HTSSR0 + 0x4C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + TMRA_HTSSR1 + desc TMRA_HTSSR1 + 0x50 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + OTS_TRG + desc OTS_TRG + 0x54 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC1_ITRGSELR0 + desc ADC1_ITRGSELR0 + 0x58 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC1_ITRGSELR1 + desc ADC1_ITRGSELR1 + 0x5C + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC2_ITRGSELR0 + desc ADC2_ITRGSELR0 + 0x60 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + ADC2_ITRGSELR1 + desc ADC2_ITRGSELR1 + 0x64 + 32 + read-write + 0x1FF + 0xC00001FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + COMTRG_EN + desc COMTRG_EN + 31 + 30 + read-write + + + + + COMTRG1 + desc COMTRG1 + 0x68 + 32 + read-write + 0x1FF + 0x1FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + + + COMTRG2 + desc COMTRG2 + 0x6C + 32 + read-write + 0x1FF + 0x1FF + + + TRGSEL + desc TRGSEL + 8 + 0 + read-write + + + + + PEVNTDIRR1 + desc PEVNTDIRR1 + 0x100 + 32 + read-write + 0x0 + 0xFFFF + + + PDIR00 + desc PDIR00 + 0 + 0 + read-write + + + PDIR01 + desc PDIR01 + 1 + 1 + read-write + + + PDIR02 + desc PDIR02 + 2 + 2 + read-write + + + PDIR03 + desc PDIR03 + 3 + 3 + read-write + + + PDIR04 + desc PDIR04 + 4 + 4 + read-write + + + PDIR05 + desc PDIR05 + 5 + 5 + read-write + + + PDIR06 + desc PDIR06 + 6 + 6 + read-write + + + PDIR07 + desc PDIR07 + 7 + 7 + read-write + + + PDIR08 + desc PDIR08 + 8 + 8 + read-write + + + PDIR09 + desc PDIR09 + 9 + 9 + read-write + + + PDIR10 + desc PDIR10 + 10 + 10 + read-write + + + PDIR11 + desc PDIR11 + 11 + 11 + read-write + + + PDIR12 + desc PDIR12 + 12 + 12 + read-write + + + PDIR13 + desc PDIR13 + 13 + 13 + read-write + + + PDIR14 + desc PDIR14 + 14 + 14 + read-write + + + PDIR15 + desc PDIR15 + 15 + 15 + read-write + + + + + PEVNTIDR1 + desc PEVNTIDR1 + 0x104 + 32 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PEVNTODR1 + desc PEVNTODR1 + 0x108 + 32 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + PEVNTORR1 + desc PEVNTORR1 + 0x10C + 32 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + PEVNTOSR1 + desc PEVNTOSR1 + 0x110 + 32 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PEVNTRISR1 + desc PEVNTRISR1 + 0x114 + 32 + read-write + 0x0 + 0xFFFF + + + RIS00 + desc RIS00 + 0 + 0 + read-write + + + RIS01 + desc RIS01 + 1 + 1 + read-write + + + RIS02 + desc RIS02 + 2 + 2 + read-write + + + RIS03 + desc RIS03 + 3 + 3 + read-write + + + RIS04 + desc RIS04 + 4 + 4 + read-write + + + RIS05 + desc RIS05 + 5 + 5 + read-write + + + RIS06 + desc RIS06 + 6 + 6 + read-write + + + RIS07 + desc RIS07 + 7 + 7 + read-write + + + RIS08 + desc RIS08 + 8 + 8 + read-write + + + RIS09 + desc RIS09 + 9 + 9 + read-write + + + RIS10 + desc RIS10 + 10 + 10 + read-write + + + RIS11 + desc RIS11 + 11 + 11 + read-write + + + RIS12 + desc RIS12 + 12 + 12 + read-write + + + RIS13 + desc RIS13 + 13 + 13 + read-write + + + RIS14 + desc RIS14 + 14 + 14 + read-write + + + RIS15 + desc RIS15 + 15 + 15 + read-write + + + + + PEVNTFAL1 + desc PEVNTFAL1 + 0x118 + 32 + read-write + 0x0 + 0xFFFF + + + FAL00 + desc FAL00 + 0 + 0 + read-write + + + FAL01 + desc FAL01 + 1 + 1 + read-write + + + FAL02 + desc FAL02 + 2 + 2 + read-write + + + FAL03 + desc FAL03 + 3 + 3 + read-write + + + FAL04 + desc FAL04 + 4 + 4 + read-write + + + FAL05 + desc FAL05 + 5 + 5 + read-write + + + FAL06 + desc FAL06 + 6 + 6 + read-write + + + FAL07 + desc FAL07 + 7 + 7 + read-write + + + FAL08 + desc FAL08 + 8 + 8 + read-write + + + FAL09 + desc FAL09 + 9 + 9 + read-write + + + FAL10 + desc FAL10 + 10 + 10 + read-write + + + FAL11 + desc FAL11 + 11 + 11 + read-write + + + FAL12 + desc FAL12 + 12 + 12 + read-write + + + FAL13 + desc FAL13 + 13 + 13 + read-write + + + FAL14 + desc FAL14 + 14 + 14 + read-write + + + FAL15 + desc FAL15 + 15 + 15 + read-write + + + + + PEVNTDIRR2 + desc PEVNTDIRR2 + 0x11C + 32 + read-write + 0x0 + 0xFFFF + + + PDIR00 + desc PDIR00 + 0 + 0 + read-write + + + PDIR01 + desc PDIR01 + 1 + 1 + read-write + + + PDIR02 + desc PDIR02 + 2 + 2 + read-write + + + PDIR03 + desc PDIR03 + 3 + 3 + read-write + + + PDIR04 + desc PDIR04 + 4 + 4 + read-write + + + PDIR05 + desc PDIR05 + 5 + 5 + read-write + + + PDIR06 + desc PDIR06 + 6 + 6 + read-write + + + PDIR07 + desc PDIR07 + 7 + 7 + read-write + + + PDIR08 + desc PDIR08 + 8 + 8 + read-write + + + PDIR09 + desc PDIR09 + 9 + 9 + read-write + + + PDIR10 + desc PDIR10 + 10 + 10 + read-write + + + PDIR11 + desc PDIR11 + 11 + 11 + read-write + + + PDIR12 + desc PDIR12 + 12 + 12 + read-write + + + PDIR13 + desc PDIR13 + 13 + 13 + read-write + + + PDIR14 + desc PDIR14 + 14 + 14 + read-write + + + PDIR15 + desc PDIR15 + 15 + 15 + read-write + + + + + PEVNTIDR2 + desc PEVNTIDR2 + 0x120 + 32 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PEVNTODR2 + desc PEVNTODR2 + 0x124 + 32 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + PEVNTORR2 + desc PEVNTORR2 + 0x128 + 32 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + PEVNTOSR2 + desc PEVNTOSR2 + 0x12C + 32 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PEVNTRISR2 + desc PEVNTRISR2 + 0x130 + 32 + read-write + 0x0 + 0xFFFF + + + RIS00 + desc RIS00 + 0 + 0 + read-write + + + RIS01 + desc RIS01 + 1 + 1 + read-write + + + RIS02 + desc RIS02 + 2 + 2 + read-write + + + RIS03 + desc RIS03 + 3 + 3 + read-write + + + RIS04 + desc RIS04 + 4 + 4 + read-write + + + RIS05 + desc RIS05 + 5 + 5 + read-write + + + RIS06 + desc RIS06 + 6 + 6 + read-write + + + RIS07 + desc RIS07 + 7 + 7 + read-write + + + RIS08 + desc RIS08 + 8 + 8 + read-write + + + RIS09 + desc RIS09 + 9 + 9 + read-write + + + RIS10 + desc RIS10 + 10 + 10 + read-write + + + RIS11 + desc RIS11 + 11 + 11 + read-write + + + RIS12 + desc RIS12 + 12 + 12 + read-write + + + RIS13 + desc RIS13 + 13 + 13 + read-write + + + RIS14 + desc RIS14 + 14 + 14 + read-write + + + RIS15 + desc RIS15 + 15 + 15 + read-write + + + + + PEVNTFAL2 + desc PEVNTFAL2 + 0x134 + 32 + read-write + 0x0 + 0xFFFF + + + FAL00 + desc FAL00 + 0 + 0 + read-write + + + FAL01 + desc FAL01 + 1 + 1 + read-write + + + FAL02 + desc FAL02 + 2 + 2 + read-write + + + FAL03 + desc FAL03 + 3 + 3 + read-write + + + FAL04 + desc FAL04 + 4 + 4 + read-write + + + FAL05 + desc FAL05 + 5 + 5 + read-write + + + FAL06 + desc FAL06 + 6 + 6 + read-write + + + FAL07 + desc FAL07 + 7 + 7 + read-write + + + FAL08 + desc FAL08 + 8 + 8 + read-write + + + FAL09 + desc FAL09 + 9 + 9 + read-write + + + FAL10 + desc FAL10 + 10 + 10 + read-write + + + FAL11 + desc FAL11 + 11 + 11 + read-write + + + FAL12 + desc FAL12 + 12 + 12 + read-write + + + FAL13 + desc FAL13 + 13 + 13 + read-write + + + FAL14 + desc FAL14 + 14 + 14 + read-write + + + FAL15 + desc FAL15 + 15 + 15 + read-write + + + + + PEVNTDIRR3 + desc PEVNTDIRR3 + 0x138 + 32 + read-write + 0x0 + 0xFFFF + + + PDIR00 + desc PDIR00 + 0 + 0 + read-write + + + PDIR01 + desc PDIR01 + 1 + 1 + read-write + + + PDIR02 + desc PDIR02 + 2 + 2 + read-write + + + PDIR03 + desc PDIR03 + 3 + 3 + read-write + + + PDIR04 + desc PDIR04 + 4 + 4 + read-write + + + PDIR05 + desc PDIR05 + 5 + 5 + read-write + + + PDIR06 + desc PDIR06 + 6 + 6 + read-write + + + PDIR07 + desc PDIR07 + 7 + 7 + read-write + + + PDIR08 + desc PDIR08 + 8 + 8 + read-write + + + PDIR09 + desc PDIR09 + 9 + 9 + read-write + + + PDIR10 + desc PDIR10 + 10 + 10 + read-write + + + PDIR11 + desc PDIR11 + 11 + 11 + read-write + + + PDIR12 + desc PDIR12 + 12 + 12 + read-write + + + PDIR13 + desc PDIR13 + 13 + 13 + read-write + + + PDIR14 + desc PDIR14 + 14 + 14 + read-write + + + PDIR15 + desc PDIR15 + 15 + 15 + read-write + + + + + PEVNTIDR3 + desc PEVNTIDR3 + 0x13C + 32 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PEVNTODR3 + desc PEVNTODR3 + 0x140 + 32 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + PEVNTORR3 + desc PEVNTORR3 + 0x144 + 32 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + PEVNTOSR3 + desc PEVNTOSR3 + 0x148 + 32 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PEVNTRISR3 + desc PEVNTRISR3 + 0x14C + 32 + read-write + 0x0 + 0xFFFF + + + RIS00 + desc RIS00 + 0 + 0 + read-write + + + RIS01 + desc RIS01 + 1 + 1 + read-write + + + RIS02 + desc RIS02 + 2 + 2 + read-write + + + RIS03 + desc RIS03 + 3 + 3 + read-write + + + RIS04 + desc RIS04 + 4 + 4 + read-write + + + RIS05 + desc RIS05 + 5 + 5 + read-write + + + RIS06 + desc RIS06 + 6 + 6 + read-write + + + RIS07 + desc RIS07 + 7 + 7 + read-write + + + RIS08 + desc RIS08 + 8 + 8 + read-write + + + RIS09 + desc RIS09 + 9 + 9 + read-write + + + RIS10 + desc RIS10 + 10 + 10 + read-write + + + RIS11 + desc RIS11 + 11 + 11 + read-write + + + RIS12 + desc RIS12 + 12 + 12 + read-write + + + RIS13 + desc RIS13 + 13 + 13 + read-write + + + RIS14 + desc RIS14 + 14 + 14 + read-write + + + RIS15 + desc RIS15 + 15 + 15 + read-write + + + + + PEVNTFAL3 + desc PEVNTFAL3 + 0x150 + 32 + read-write + 0x0 + 0xFFFF + + + FAL00 + desc FAL00 + 0 + 0 + read-write + + + FAL01 + desc FAL01 + 1 + 1 + read-write + + + FAL02 + desc FAL02 + 2 + 2 + read-write + + + FAL03 + desc FAL03 + 3 + 3 + read-write + + + FAL04 + desc FAL04 + 4 + 4 + read-write + + + FAL05 + desc FAL05 + 5 + 5 + read-write + + + FAL06 + desc FAL06 + 6 + 6 + read-write + + + FAL07 + desc FAL07 + 7 + 7 + read-write + + + FAL08 + desc FAL08 + 8 + 8 + read-write + + + FAL09 + desc FAL09 + 9 + 9 + read-write + + + FAL10 + desc FAL10 + 10 + 10 + read-write + + + FAL11 + desc FAL11 + 11 + 11 + read-write + + + FAL12 + desc FAL12 + 12 + 12 + read-write + + + FAL13 + desc FAL13 + 13 + 13 + read-write + + + FAL14 + desc FAL14 + 14 + 14 + read-write + + + FAL15 + desc FAL15 + 15 + 15 + read-write + + + + + PEVNTDIRR4 + desc PEVNTDIRR4 + 0x154 + 32 + read-write + 0x0 + 0xFFFF + + + PDIR00 + desc PDIR00 + 0 + 0 + read-write + + + PDIR01 + desc PDIR01 + 1 + 1 + read-write + + + PDIR02 + desc PDIR02 + 2 + 2 + read-write + + + PDIR03 + desc PDIR03 + 3 + 3 + read-write + + + PDIR04 + desc PDIR04 + 4 + 4 + read-write + + + PDIR05 + desc PDIR05 + 5 + 5 + read-write + + + PDIR06 + desc PDIR06 + 6 + 6 + read-write + + + PDIR07 + desc PDIR07 + 7 + 7 + read-write + + + PDIR08 + desc PDIR08 + 8 + 8 + read-write + + + PDIR09 + desc PDIR09 + 9 + 9 + read-write + + + PDIR10 + desc PDIR10 + 10 + 10 + read-write + + + PDIR11 + desc PDIR11 + 11 + 11 + read-write + + + PDIR12 + desc PDIR12 + 12 + 12 + read-write + + + PDIR13 + desc PDIR13 + 13 + 13 + read-write + + + PDIR14 + desc PDIR14 + 14 + 14 + read-write + + + PDIR15 + desc PDIR15 + 15 + 15 + read-write + + + + + PEVNTIDR4 + desc PEVNTIDR4 + 0x158 + 32 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PEVNTODR4 + desc PEVNTODR4 + 0x15C + 32 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + PEVNTORR4 + desc PEVNTORR4 + 0x160 + 32 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + PEVNTOSR4 + desc PEVNTOSR4 + 0x164 + 32 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PEVNTRISR4 + desc PEVNTRISR4 + 0x168 + 32 + read-write + 0x0 + 0xFFFF + + + RIS00 + desc RIS00 + 0 + 0 + read-write + + + RIS01 + desc RIS01 + 1 + 1 + read-write + + + RIS02 + desc RIS02 + 2 + 2 + read-write + + + RIS03 + desc RIS03 + 3 + 3 + read-write + + + RIS04 + desc RIS04 + 4 + 4 + read-write + + + RIS05 + desc RIS05 + 5 + 5 + read-write + + + RIS06 + desc RIS06 + 6 + 6 + read-write + + + RIS07 + desc RIS07 + 7 + 7 + read-write + + + RIS08 + desc RIS08 + 8 + 8 + read-write + + + RIS09 + desc RIS09 + 9 + 9 + read-write + + + RIS10 + desc RIS10 + 10 + 10 + read-write + + + RIS11 + desc RIS11 + 11 + 11 + read-write + + + RIS12 + desc RIS12 + 12 + 12 + read-write + + + RIS13 + desc RIS13 + 13 + 13 + read-write + + + RIS14 + desc RIS14 + 14 + 14 + read-write + + + RIS15 + desc RIS15 + 15 + 15 + read-write + + + + + PEVNTFAL4 + desc PEVNTFAL4 + 0x16C + 32 + read-write + 0x0 + 0xFFFF + + + FAL00 + desc FAL00 + 0 + 0 + read-write + + + FAL01 + desc FAL01 + 1 + 1 + read-write + + + FAL02 + desc FAL02 + 2 + 2 + read-write + + + FAL03 + desc FAL03 + 3 + 3 + read-write + + + FAL04 + desc FAL04 + 4 + 4 + read-write + + + FAL05 + desc FAL05 + 5 + 5 + read-write + + + FAL06 + desc FAL06 + 6 + 6 + read-write + + + FAL07 + desc FAL07 + 7 + 7 + read-write + + + FAL08 + desc FAL08 + 8 + 8 + read-write + + + FAL09 + desc FAL09 + 9 + 9 + read-write + + + FAL10 + desc FAL10 + 10 + 10 + read-write + + + FAL11 + desc FAL11 + 11 + 11 + read-write + + + FAL12 + desc FAL12 + 12 + 12 + read-write + + + FAL13 + desc FAL13 + 13 + 13 + read-write + + + FAL14 + desc FAL14 + 14 + 14 + read-write + + + FAL15 + desc FAL15 + 15 + 15 + read-write + + + + + PEVNTNFCR + desc PEVNTNFCR + 0x170 + 32 + read-write + 0x0 + 0x7070707 + + + NFEN1 + desc NFEN1 + 0 + 0 + read-write + + + DIVS1 + desc DIVS1 + 2 + 1 + read-write + + + NFEN2 + desc NFEN2 + 8 + 8 + read-write + + + DIVS2 + desc DIVS2 + 10 + 9 + read-write + + + NFEN3 + desc NFEN3 + 16 + 16 + read-write + + + DIVS3 + desc DIVS3 + 18 + 17 + read-write + + + NFEN4 + desc NFEN4 + 24 + 24 + read-write + + + DIVS4 + desc DIVS4 + 26 + 25 + read-write + + + + + + + CAN + desc CAN + 0x40070400 + + 0x0 + 0xCA + + + + RBUF + desc RBUF + 0x0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + TBUF + desc TBUF + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CFG_STAT + desc CFG_STAT + 0xA0 + 8 + read-write + 0x80 + 0xFF + + + BUSOFF + desc BUSOFF + 0 + 0 + read-write + + + TACTIVE + desc TACTIVE + 1 + 1 + read-only + + + RACTIVE + desc RACTIVE + 2 + 2 + read-only + + + TSSS + desc TSSS + 3 + 3 + read-write + + + TPSS + desc TPSS + 4 + 4 + read-write + + + LBMI + desc LBMI + 5 + 5 + read-write + + + LBME + desc LBME + 6 + 6 + read-write + + + RESET + desc RESET + 7 + 7 + read-write + + + + + TCMD + desc TCMD + 0xA1 + 8 + read-write + 0x0 + 0xDF + + + TSA + desc TSA + 0 + 0 + read-write + + + TSALL + desc TSALL + 1 + 1 + read-write + + + TSONE + desc TSONE + 2 + 2 + read-write + + + TPA + desc TPA + 3 + 3 + read-write + + + TPE + desc TPE + 4 + 4 + read-write + + + LOM + desc LOM + 6 + 6 + read-write + + + TBSEL + desc TBSEL + 7 + 7 + read-write + + + + + TCTRL + desc TCTRL + 0xA2 + 8 + read-write + 0x90 + 0x73 + + + TSSTAT + desc TSSTAT + 1 + 0 + read-only + + + TTTBM + desc TTTBM + 4 + 4 + read-write + + + TSMODE + desc TSMODE + 5 + 5 + read-write + + + TSNEXT + desc TSNEXT + 6 + 6 + read-write + + + + + RCTRL + desc RCTRL + 0xA3 + 8 + read-write + 0x0 + 0xFB + + + RSTAT + desc RSTAT + 1 + 0 + read-only + + + RBALL + desc RBALL + 3 + 3 + read-write + + + RREL + desc RREL + 4 + 4 + read-write + + + ROV + desc ROV + 5 + 5 + read-only + + + ROM + desc ROM + 6 + 6 + read-write + + + SACK + desc SACK + 7 + 7 + read-write + + + + + RTIE + desc RTIE + 0xA4 + 8 + read-write + 0xFE + 0xFF + + + TSFF + desc TSFF + 0 + 0 + read-only + + + EIE + desc EIE + 1 + 1 + read-write + + + TSIE + desc TSIE + 2 + 2 + read-write + + + TPIE + desc TPIE + 3 + 3 + read-write + + + RAFIE + desc RAFIE + 4 + 4 + read-write + + + RFIE + desc RFIE + 5 + 5 + read-write + + + ROIE + desc ROIE + 6 + 6 + read-write + + + RIE + desc RIE + 7 + 7 + read-write + + + + + RTIF + desc RTIF + 0xA5 + 8 + read-write + 0x0 + 0xFF + + + AIF + desc AIF + 0 + 0 + read-write + + + EIF + desc EIF + 1 + 1 + read-write + + + TSIF + desc TSIF + 2 + 2 + read-write + + + TPIF + desc TPIF + 3 + 3 + read-write + + + RAFIF + desc RAFIF + 4 + 4 + read-write + + + RFIF + desc RFIF + 5 + 5 + read-write + + + ROIF + desc ROIF + 6 + 6 + read-write + + + RIF + desc RIF + 7 + 7 + read-write + + + + + ERRINT + desc ERRINT + 0xA6 + 8 + read-write + 0x0 + 0xFF + + + BEIF + desc BEIF + 0 + 0 + read-write + + + BEIE + desc BEIE + 1 + 1 + read-write + + + ALIF + desc ALIF + 2 + 2 + read-write + + + ALIE + desc ALIE + 3 + 3 + read-write + + + EPIF + desc EPIF + 4 + 4 + read-write + + + EPIE + desc EPIE + 5 + 5 + read-write + + + EPASS + desc EPASS + 6 + 6 + read-only + + + EWARN + desc EWARN + 7 + 7 + read-only + + + + + LIMIT + desc LIMIT + 0xA7 + 8 + read-write + 0x1B + 0xFF + + + EWL + desc EWL + 3 + 0 + read-write + + + AFWL + desc AFWL + 7 + 4 + read-write + + + + + SBT + desc SBT + 0xA8 + 32 + read-write + 0x1020203 + 0xFF7F7FFF + + + S_SEG_1 + desc S_SEG_1 + 7 + 0 + read-write + + + S_SEG_2 + desc S_SEG_2 + 14 + 8 + read-write + + + S_SJW + desc S_SJW + 22 + 16 + read-write + + + S_PRESC + desc S_PRESC + 31 + 24 + read-write + + + + + EALCAP + desc EALCAP + 0xB0 + 8 + read-only + 0x0 + 0xFF + + + ALC + desc ALC + 4 + 0 + read-only + + + KOER + desc KOER + 7 + 5 + read-only + + + + + RECNT + desc RECNT + 0xB2 + 8 + read-write + 0x0 + 0xFF + + + TECNT + desc TECNT + 0xB3 + 8 + read-write + 0x0 + 0xFF + + + ACFCTRL + desc ACFCTRL + 0xB4 + 8 + read-write + 0x0 + 0x2F + + + ACFADR + desc ACFADR + 3 + 0 + read-write + + + SELMASK + desc SELMASK + 5 + 5 + read-write + + + + + ACFEN + desc ACFEN + 0xB6 + 8 + read-write + 0x1 + 0xFF + + + AE_1 + desc AE_1 + 0 + 0 + read-write + + + AE_2 + desc AE_2 + 1 + 1 + read-write + + + AE_3 + desc AE_3 + 2 + 2 + read-write + + + AE_4 + desc AE_4 + 3 + 3 + read-write + + + AE_5 + desc AE_5 + 4 + 4 + read-write + + + AE_6 + desc AE_6 + 5 + 5 + read-write + + + AE_7 + desc AE_7 + 6 + 6 + read-write + + + AE_8 + desc AE_8 + 7 + 7 + read-write + + + + + ACF + desc ACF + 0xB8 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + ACODEORAMASK + desc ACODEORAMASK + 28 + 0 + read-write + + + AIDE + desc AIDE + 29 + 29 + read-write + + + AIDEE + desc AIDEE + 30 + 30 + read-write + + + + + TBSLOT + desc TBSLOT + 0xBE + 8 + read-write + 0x0 + 0xFF + + + TBPTR + desc TBPTR + 5 + 0 + read-write + + + TBF + desc TBF + 6 + 6 + read-write + + + TBE + desc TBE + 7 + 7 + read-write + + + + + TTCFG + desc TTCFG + 0xBF + 8 + read-write + 0x90 + 0xFF + + + TTEN + desc TTEN + 0 + 0 + read-write + + + T_PRESC + desc T_PRESC + 2 + 1 + read-write + + + TTIF + desc TTIF + 3 + 3 + read-write + + + TTIE + desc TTIE + 4 + 4 + read-write + + + TEIF + desc TEIF + 5 + 5 + read-write + + + WTIF + desc WTIF + 6 + 6 + read-write + + + WTIE + desc WTIE + 7 + 7 + read-write + + + + + REF_MSG + desc REF_MSG + 0xC0 + 32 + read-write + 0x0 + 0x9FFFFFFF + + + REF_ID + desc REF_ID + 28 + 0 + read-write + + + REF_IDE + desc REF_IDE + 31 + 31 + read-write + + + + + TRG_CFG + desc TRG_CFG + 0xC4 + 16 + read-write + 0x0 + 0xF73F + + + TTPTR + desc TTPTR + 5 + 0 + read-write + + + TTYPE + desc TTYPE + 10 + 8 + read-write + + + TEW + desc TEW + 15 + 12 + read-write + + + + + TT_TRIG + desc TT_TRIG + 0xC6 + 16 + read-write + 0x0 + 0xFFFF + + + TT_WTRIG + desc TT_WTRIG + 0xC8 + 16 + read-write + 0xFFFF + 0xFFFF + + + + + CMP1 + desc CMP + 0x4004A000 + + 0x0 + 0xA + + + + CTRL + desc CTRL + 0x0 + 16 + read-write + 0x0 + 0xF1E7 + + + FLTSL + desc FLTSL + 2 + 0 + read-write + + + EDGSL + desc EDGSL + 6 + 5 + read-write + + + IEN + desc IEN + 7 + 7 + read-write + + + CVSEN + desc CVSEN + 8 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + INV + desc INV + 13 + 13 + read-write + + + CMPOE + desc CMPOE + 14 + 14 + read-write + + + CMPON + desc CMPON + 15 + 15 + read-write + + + + + VLTSEL + desc VLTSEL + 0x2 + 16 + read-write + 0x0 + 0x7F0F + + + RVSL + desc RVSL + 3 + 0 + read-write + + + CVSL + desc CVSL + 11 + 8 + read-write + + + C4SL + desc C4SL + 14 + 12 + read-write + + + + + OUTMON + desc OUTMON + 0x4 + 16 + read-only + 0x0 + 0xF01 + + + OMON + desc OMON + 0 + 0 + read-only + + + CVST + desc CVST + 11 + 8 + read-only + + + + + CVSSTB + desc CVSSTB + 0x6 + 16 + read-write + 0x5 + 0xF + + + STB + desc STB + 3 + 0 + read-write + + + + + CVSPRD + desc CVSPRD + 0x8 + 16 + read-write + 0xF + 0xFF + + + PRD + desc PRD + 7 + 0 + read-write + + + + + + + CMP2 + desc CMP + 0x4004A010 + + 0x0 + 0xA + + + + CMP3 + desc CMP + 0x4004A020 + + 0x0 + 0xA + + + + CMPCR + desc CMPCR + 0x4004A000 + CMP1 + + 0x0 + 0x10E + + + + DADR1 + desc DADR1 + 0x100 + 16 + read-write + 0x0 + 0xFF + + + DATA + desc DATA + 7 + 0 + read-write + + + + + DADR2 + desc DADR2 + 0x102 + 16 + read-write + 0x0 + 0xFF + + + DATA + desc DATA + 7 + 0 + read-write + + + + + DACR + desc DACR + 0x108 + 16 + read-write + 0x0 + 0x3 + + + DA1EN + desc DA1EN + 0 + 0 + read-write + + + DA2EN + desc DA2EN + 1 + 1 + read-write + + + + + RVADC + desc RVADC + 0x10C + 16 + read-write + 0x0 + 0x13 + + + DA1SW + desc DA1SW + 0 + 0 + read-write + + + DA2SW + desc DA2SW + 1 + 1 + read-write + + + VREFSW + desc VREFSW + 4 + 4 + read-write + + + WPRT + desc WPRT + 15 + 8 + read-write + + + + + + + CMU + desc CMU + 0x40054000 + + 0x0 + 0x42A + + + + PERICKSEL + desc PERICKSEL + 0x10 + 16 + read-write + 0x0 + 0xF + + + PERICKSEL + desc PERICKSEL + 3 + 0 + read-write + + + + + I2SCKSEL + desc I2SCKSEL + 0x12 + 16 + read-write + 0xBBBB + 0xFFFF + + + I2S1CKSEL + desc I2S1CKSEL + 3 + 0 + read-write + + + I2S2CKSEL + desc I2S2CKSEL + 7 + 4 + read-write + + + I2S3CKSEL + desc I2S3CKSEL + 11 + 8 + read-write + + + I2S4CKSEL + desc I2S4CKSEL + 15 + 12 + read-write + + + + + SCFGR + desc SCFGR + 0x20 + 32 + read-write + 0x0 + 0x7777777 + + + PCLK0S + desc PCLK0S + 2 + 0 + read-write + + + PCLK1S + desc PCLK1S + 6 + 4 + read-write + + + PCLK2S + desc PCLK2S + 10 + 8 + read-write + + + PCLK3S + desc PCLK3S + 14 + 12 + read-write + + + PCLK4S + desc PCLK4S + 18 + 16 + read-write + + + EXCKS + desc EXCKS + 22 + 20 + read-write + + + HCLKS + desc HCLKS + 26 + 24 + read-write + + + + + USBCKCFGR + desc USBCKCFGR + 0x24 + 8 + read-write + 0x40 + 0xF0 + + + USBCKS + desc USBCKS + 7 + 4 + read-write + + + + + CKSWR + desc CKSWR + 0x26 + 8 + read-write + 0x1 + 0x7 + + + CKSW + desc CKSW + 2 + 0 + read-write + + + + + PLLCR + desc PLLCR + 0x2A + 8 + read-write + 0x1 + 0x1 + + + MPLLOFF + desc MPLLOFF + 0 + 0 + read-write + + + + + UPLLCR + desc UPLLCR + 0x2E + 8 + read-write + 0x1 + 0x1 + + + UPLLOFF + desc UPLLOFF + 0 + 0 + read-write + + + + + XTALCR + desc XTALCR + 0x32 + 8 + read-write + 0x1 + 0x1 + + + XTALSTP + desc XTALSTP + 0 + 0 + read-write + + + + + HRCCR + desc HRCCR + 0x36 + 8 + read-write + 0x1 + 0x1 + + + HRCSTP + desc HRCSTP + 0 + 0 + read-write + + + + + MRCCR + desc MRCCR + 0x38 + 8 + read-write + 0x80 + 0x1 + + + MRCSTP + desc MRCSTP + 0 + 0 + read-write + + + + + OSCSTBSR + desc OSCSTBSR + 0x3C + 8 + read-write + 0x0 + 0x69 + + + HRCSTBF + desc HRCSTBF + 0 + 0 + read-write + + + XTALSTBF + desc XTALSTBF + 3 + 3 + read-write + + + MPLLSTBF + desc MPLLSTBF + 5 + 5 + read-write + + + UPLLSTBF + desc UPLLSTBF + 6 + 6 + read-write + + + + + MCOCFGR1 + desc MCOCFGR1 + 0x3D + 8 + read-write + 0x0 + 0xFF + + + MCOSEL + desc MCOSEL + 3 + 0 + read-write + + + MCODIV + desc MCODIV + 6 + 4 + read-write + + + MCOEN + desc MCOEN + 7 + 7 + read-write + + + + + MCOCFGR2 + desc MCOCFGR2 + 0x3E + 8 + read-write + 0x0 + 0xFF + + + MCOSEL + desc MCOSEL + 3 + 0 + read-write + + + MCODIV + desc MCODIV + 6 + 4 + read-write + + + MCOEN + desc MCOEN + 7 + 7 + read-write + + + + + TPIUCKCFGR + desc TPIUCKCFGR + 0x3F + 8 + read-write + 0x0 + 0x83 + + + TPIUCKS + desc TPIUCKS + 1 + 0 + read-write + + + TPIUCKOE + desc TPIUCKOE + 7 + 7 + read-write + + + + + XTALSTDCR + desc XTALSTDCR + 0x40 + 8 + read-write + 0x0 + 0x87 + + + XTALSTDIE + desc XTALSTDIE + 0 + 0 + read-write + + + XTALSTDRE + desc XTALSTDRE + 1 + 1 + read-write + + + XTALSTDRIS + desc XTALSTDRIS + 2 + 2 + read-write + + + XTALSTDE + desc XTALSTDE + 7 + 7 + read-write + + + + + XTALSTDSR + desc XTALSTDSR + 0x41 + 8 + read-write + 0x0 + 0x1 + + + XTALSTDF + desc XTALSTDF + 0 + 0 + read-write + + + + + MRCTRM + desc MRCTRM + 0x61 + 8 + read-write + 0x0 + 0xFF + + + HRCTRM + desc HRCTRM + 0x62 + 8 + read-write + 0x0 + 0xFF + + + XTALSTBCR + desc XTALSTBCR + 0xA2 + 8 + read-write + 0x5 + 0xF + + + XTALSTB + desc XTALSTB + 3 + 0 + read-write + + + + + PLLCFGR + desc PLLCFGR + 0x100 + 32 + read-write + 0x11101300 + 0xFFF1FF9F + + + MPLLM + desc MPLLM + 4 + 0 + read-write + + + PLLSRC + desc PLLSRC + 7 + 7 + read-write + + + MPLLN + desc MPLLN + 16 + 8 + read-write + + + MPLLR + desc MPLLR + 23 + 20 + read-write + + + MPLLQ + desc MPLLQ + 27 + 24 + read-write + + + MPLLP + desc MPLLP + 31 + 28 + read-write + + + + + UPLLCFGR + desc UPLLCFGR + 0x104 + 32 + read-write + 0x11101300 + 0xFFF1FF1F + + + UPLLM + desc UPLLM + 4 + 0 + read-write + + + UPLLN + desc UPLLN + 16 + 8 + read-write + + + UPLLR + desc UPLLR + 23 + 20 + read-write + + + UPLLQ + desc UPLLQ + 27 + 24 + read-write + + + UPLLP + desc UPLLP + 31 + 28 + read-write + + + + + XTALCFGR + desc XTALCFGR + 0x410 + 8 + read-write + 0x80 + 0xF0 + + + XTALDRV + desc XTALDRV + 5 + 4 + read-write + + + XTALMS + desc XTALMS + 6 + 6 + read-write + + + SUPDRV + desc SUPDRV + 7 + 7 + read-write + + + + + XTAL32CR + desc XTAL32CR + 0x420 + 8 + read-write + 0x0 + 0x1 + + + XTAL32STP + desc XTAL32STP + 0 + 0 + read-write + + + + + XTAL32CFGR + desc XTAL32CFGR + 0x421 + 8 + read-write + 0x0 + 0x7 + + + XTAL32DRV + desc XTAL32DRV + 2 + 0 + read-write + + + + + XTAL32NFR + desc XTAL32NFR + 0x425 + 8 + read-write + 0x0 + 0x3 + + + XTAL32NF + desc XTAL32NF + 1 + 0 + read-write + + + + + LRCCR + desc LRCCR + 0x427 + 8 + read-write + 0x0 + 0x1 + + + LRCSTP + desc LRCSTP + 0 + 0 + read-write + + + + + LRCTRM + desc LRCTRM + 0x429 + 8 + read-write + 0x0 + 0xFF + + + + + CRC + desc CRC + 0x40008C00 + + 0x0 + 0x100 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x1C + 0x1E + + + CR + desc CR + 1 + 1 + read-write + + + REFIN + desc REFIN + 2 + 2 + read-write + + + REFOUT + desc REFOUT + 3 + 3 + read-write + + + XOROUT + desc XOROUT + 4 + 4 + read-write + + + + + RESLT + desc RESLT + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CRC_REG + desc CRC_REG + 15 + 0 + read-write + + + CRCFLAG_16 + desc CRCFLAG_16 + 16 + 16 + read-only + + + + + FLG + desc FLG + 0xC + 32 + read-only + 0x1 + 0x1 + + + CRCFLAG_32 + desc CRCFLAG_32 + 0 + 0 + read-only + + + + + DAT0 + desc DAT0 + 0x80 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT1 + desc DAT1 + 0x84 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT2 + desc DAT2 + 0x88 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT3 + desc DAT3 + 0x8C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT4 + desc DAT4 + 0x90 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT5 + desc DAT5 + 0x94 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT6 + desc DAT6 + 0x98 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT7 + desc DAT7 + 0x9C + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT8 + desc DAT8 + 0xA0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT9 + desc DAT9 + 0xA4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT10 + desc DAT10 + 0xA8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT11 + desc DAT11 + 0xAC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT12 + desc DAT12 + 0xB0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT13 + desc DAT13 + 0xB4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT14 + desc DAT14 + 0xB8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT15 + desc DAT15 + 0xBC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT16 + desc DAT16 + 0xC0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT17 + desc DAT17 + 0xC4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT18 + desc DAT18 + 0xC8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT19 + desc DAT19 + 0xCC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT20 + desc DAT20 + 0xD0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT21 + desc DAT21 + 0xD4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT22 + desc DAT22 + 0xD8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT23 + desc DAT23 + 0xDC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT24 + desc DAT24 + 0xE0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT25 + desc DAT25 + 0xE4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT26 + desc DAT26 + 0xE8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT27 + desc DAT27 + 0xEC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT28 + desc DAT28 + 0xF0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT29 + desc DAT29 + 0xF4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT30 + desc DAT30 + 0xF8 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DAT31 + desc DAT31 + 0xFC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + + + DBGC + desc DBGC + 0xE0042000 + + 0x0 + 0x28 + + + + AUTHID0 + desc AUTHID0 + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + AUTHID1 + desc AUTHID1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + AUTHID2 + desc AUTHID2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + RESV0 + desc RESV0 + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MCUSTAT + desc MCUSTAT + 0x10 + 32 + read-write + 0x0 + 0x30F + + + AUTH + desc AUTH + 0 + 0 + read-write + + + REMVLOCK + desc REMVLOCK + 1 + 1 + read-write + + + SAFTYLOCK1 + desc SAFTYLOCK1 + 2 + 2 + read-write + + + SAFTYLOCK2 + desc SAFTYLOCK2 + 3 + 3 + read-write + + + CPUSTOP + desc CPUSTOP + 8 + 8 + read-write + + + CPUSLEEP + desc CPUSLEEP + 9 + 9 + read-write + + + + + MCUCTL + desc MCUCTL + 0x14 + 32 + read-write + 0x0 + 0x103 + + + EDBGRQ + desc EDBGRQ + 0 + 0 + read-write + + + RESTART + desc RESTART + 1 + 1 + read-write + + + DIRQ + desc DIRQ + 8 + 8 + read-write + + + + + FMCCTL + desc FMCCTL + 0x18 + 32 + read-write + 0x0 + 0x7 + + + ERASEREQ + desc ERASEREQ + 0 + 0 + read-write + + + ERASEACK + desc ERASEACK + 1 + 1 + read-write + + + ERASEERR + desc ERASEERR + 2 + 2 + read-write + + + + + MCUDBGSTAT + desc MCUDBGSTAT + 0x1C + 32 + read-write + 0x0 + 0x3 + + + CDBGPWRUPREQ + desc CDBGPWRUPREQ + 0 + 0 + read-write + + + CDBGPWRUPACK + desc CDBGPWRUPACK + 1 + 1 + read-write + + + + + MCUSTPCTL + desc MCUSTPCTL + 0x20 + 32 + read-write + 0x3 + 0xFFF0C03F + + + SWDTSTP + desc SWDTSTP + 0 + 0 + read-write + + + WDTSTP + desc WDTSTP + 1 + 1 + read-write + + + RTCSTP + desc RTCSTP + 2 + 2 + read-write + + + PVD0STP + desc PVD0STP + 3 + 3 + read-write + + + PVD1STP + desc PVD1STP + 4 + 4 + read-write + + + PVD2STP + desc PVD2STP + 5 + 5 + read-write + + + TMR01STP + desc TMR01STP + 14 + 14 + read-write + + + TMR02STP + desc TMR02STP + 15 + 15 + read-write + + + TMR41STP + desc TMR41STP + 20 + 20 + read-write + + + TMR42STP + desc TMR42STP + 21 + 21 + read-write + + + TMR43STP + desc TMR43STP + 22 + 22 + read-write + + + TM61STP + desc TM61STP + 23 + 23 + read-write + + + TM62STP + desc TM62STP + 24 + 24 + read-write + + + TMR63STP + desc TMR63STP + 25 + 25 + read-write + + + TMRA1STP + desc TMRA1STP + 26 + 26 + read-write + + + TMRA2STP + desc TMRA2STP + 27 + 27 + read-write + + + TMRA3STP + desc TMRA3STP + 28 + 28 + read-write + + + TMRA4STP + desc TMRA4STP + 29 + 29 + read-write + + + TMRA5STP + desc TMRA5STP + 30 + 30 + read-write + + + TMRA6STP + desc TMRA6STP + 31 + 31 + read-write + + + + + MCUTRACECTL + desc MCUTRACECTL + 0x24 + 32 + read-write + 0x0 + 0x7 + + + TRACEMODE + desc TRACEMODE + 1 + 0 + read-write + + + TRACEIOEN + desc TRACEIOEN + 2 + 2 + read-write + + + + + + + DCU1 + desc DCU + 0x40052000 + + 0x0 + 0x1C + + + + CTL + desc CTL + 0x0 + 32 + read-write + 0x80000000 + 0x8000011F + + + MODE + desc MODE + 2 + 0 + read-write + + + DATASIZE + desc DATASIZE + 4 + 3 + read-write + + + COMP_TRG + desc COMP_TRG + 8 + 8 + read-write + + + INTEN + desc INTEN + 31 + 31 + read-write + + + + + FLAG + desc FLAG + 0x4 + 32 + read-only + 0x0 + 0x7F + + + FLAG_OP + desc FLAG_OP + 0 + 0 + read-only + + + FLAG_LS2 + desc FLAG_LS2 + 1 + 1 + read-only + + + FLAG_EQ2 + desc FLAG_EQ2 + 2 + 2 + read-only + + + FLAG_GT2 + desc FLAG_GT2 + 3 + 3 + read-only + + + FLAG_LS1 + desc FLAG_LS1 + 4 + 4 + read-only + + + FLAG_EQ1 + desc FLAG_EQ1 + 5 + 5 + read-only + + + FLAG_GT1 + desc FLAG_GT1 + 6 + 6 + read-only + + + + + DATA0 + desc DATA0 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA1 + desc DATA1 + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DATA2 + desc DATA2 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + FLAGCLR + desc FLAGCLR + 0x14 + 32 + write-only + 0x0 + 0x7F + + + CLR_OP + desc CLR_OP + 0 + 0 + write-only + + + CLR_LS2 + desc CLR_LS2 + 1 + 1 + write-only + + + CLR_EQ2 + desc CLR_EQ2 + 2 + 2 + write-only + + + CLR_GT2 + desc CLR_GT2 + 3 + 3 + write-only + + + CLR_LS1 + desc CLR_LS1 + 4 + 4 + write-only + + + CLR_EQ1 + desc CLR_EQ1 + 5 + 5 + write-only + + + CLR_GT1 + desc CLR_GT1 + 6 + 6 + write-only + + + + + INTSEL + desc INTSEL + 0x18 + 32 + read-write + 0x0 + 0x1FF + + + INT_OP + desc INT_OP + 0 + 0 + read-write + + + INT_LS2 + desc INT_LS2 + 1 + 1 + read-write + + + INT_EQ2 + desc INT_EQ2 + 2 + 2 + read-write + + + INT_GT2 + desc INT_GT2 + 3 + 3 + read-write + + + INT_LS1 + desc INT_LS1 + 4 + 4 + read-write + + + INT_EQ1 + desc INT_EQ1 + 5 + 5 + read-write + + + INT_GT1 + desc INT_GT1 + 6 + 6 + read-write + + + INT_WIN + desc INT_WIN + 8 + 7 + read-write + + + + + + + DCU2 + desc DCU + 0x40052400 + + 0x0 + 0x1C + + + + DCU3 + desc DCU + 0x40052800 + + 0x0 + 0x1C + + + + DCU4 + desc DCU + 0x40052C00 + + 0x0 + 0x1C + + + + DMA1 + desc DMA + 0x40053000 + + 0x0 + 0x120 + + + + EN + desc EN + 0x0 + 32 + read-write + 0x0 + 0x1 + + + EN + desc EN + 0 + 0 + read-write + + + + + INTSTAT0 + desc INTSTAT0 + 0x4 + 32 + read-only + 0x0 + 0xF000F + + + TRNERR + desc TRNERR + 3 + 0 + read-only + + + REQERR + desc REQERR + 19 + 16 + read-only + + + + + INTSTAT1 + desc INTSTAT1 + 0x8 + 32 + read-only + 0x0 + 0xF000F + + + TC + desc TC + 3 + 0 + read-only + + + BTC + desc BTC + 19 + 16 + read-only + + + + + INTMASK0 + desc INTMASK0 + 0xC + 32 + read-write + 0x0 + 0xF000F + + + MSKTRNERR + desc MSKTRNERR + 3 + 0 + read-write + + + MSKREQERR + desc MSKREQERR + 19 + 16 + read-write + + + + + INTMASK1 + desc INTMASK1 + 0x10 + 32 + read-write + 0x0 + 0xF000F + + + MSKTC + desc MSKTC + 3 + 0 + read-write + + + MSKBTC + desc MSKBTC + 19 + 16 + read-write + + + + + INTCLR0 + desc INTCLR0 + 0x14 + 32 + write-only + 0x0 + 0xF000F + + + CLRTRNERR + desc CLRTRNERR + 3 + 0 + write-only + + + CLRREQERR + desc CLRREQERR + 19 + 16 + write-only + + + + + INTCLR1 + desc INTCLR1 + 0x18 + 32 + write-only + 0x0 + 0xF000F + + + CLRTC + desc CLRTC + 3 + 0 + write-only + + + CLRBTC + desc CLRBTC + 19 + 16 + write-only + + + + + CHEN + desc CHEN + 0x1C + 32 + read-write + 0x0 + 0xF + + + CHEN + desc CHEN + 3 + 0 + read-write + + + + + REQSTAT + desc REQSTAT + 0x20 + 32 + read-only + 0x0 + 0x800F + + + CHREQ + desc CHREQ + 3 + 0 + read-only + + + RCFGREQ + desc RCFGREQ + 15 + 15 + read-only + + + + + CHSTAT + desc CHSTAT + 0x24 + 32 + read-only + 0x0 + 0xF0003 + + + DMAACT + desc DMAACT + 0 + 0 + read-only + + + RCFGACT + desc RCFGACT + 1 + 1 + read-only + + + CHACT + desc CHACT + 19 + 16 + read-only + + + + + RCFGCTL + desc RCFGCTL + 0x2C + 32 + read-write + 0x0 + 0x3F0F03 + + + RCFGEN + desc RCFGEN + 0 + 0 + read-write + + + RCFGLLP + desc RCFGLLP + 1 + 1 + read-write + + + RCFGCHS + desc RCFGCHS + 11 + 8 + read-write + + + SARMD + desc SARMD + 17 + 16 + read-write + + + DARMD + desc DARMD + 19 + 18 + read-write + + + CNTMD + desc CNTMD + 21 + 20 + read-write + + + + + SAR0 + desc SAR0 + 0x40 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR0 + desc DAR0 + 0x44 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL0 + desc DTCTL0 + 0x48 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT0 + desc RPT0 + 0x4C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB0 + desc RPTB0 + 0x4C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL0 + desc SNSEQCTL0 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB0 + desc SNSEQCTLB0 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL0 + desc DNSEQCTL0 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB0 + desc DNSEQCTLB0 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP0 + desc LLP0 + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL0 + desc CHCTL0 + 0x5C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR0 + desc MONSAR0 + 0x60 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR0 + desc MONDAR0 + 0x64 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL0 + desc MONDTCTL0 + 0x68 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT0 + desc MONRPT0 + 0x6C + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL0 + desc MONSNSEQCTL0 + 0x70 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL0 + desc MONDNSEQCTL0 + 0x74 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR1 + desc SAR1 + 0x80 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR1 + desc DAR1 + 0x84 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL1 + desc DTCTL1 + 0x88 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT1 + desc RPT1 + 0x8C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB1 + desc RPTB1 + 0x8C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL1 + desc SNSEQCTL1 + 0x90 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB1 + desc SNSEQCTLB1 + 0x90 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL1 + desc DNSEQCTL1 + 0x94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB1 + desc DNSEQCTLB1 + 0x94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP1 + desc LLP1 + 0x98 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL1 + desc CHCTL1 + 0x9C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR1 + desc MONSAR1 + 0xA0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR1 + desc MONDAR1 + 0xA4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL1 + desc MONDTCTL1 + 0xA8 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT1 + desc MONRPT1 + 0xAC + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL1 + desc MONSNSEQCTL1 + 0xB0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL1 + desc MONDNSEQCTL1 + 0xB4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR2 + desc SAR2 + 0xC0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR2 + desc DAR2 + 0xC4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL2 + desc DTCTL2 + 0xC8 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT2 + desc RPT2 + 0xCC + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB2 + desc RPTB2 + 0xCC + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL2 + desc SNSEQCTL2 + 0xD0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB2 + desc SNSEQCTLB2 + 0xD0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL2 + desc DNSEQCTL2 + 0xD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB2 + desc DNSEQCTLB2 + 0xD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP2 + desc LLP2 + 0xD8 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL2 + desc CHCTL2 + 0xDC + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR2 + desc MONSAR2 + 0xE0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR2 + desc MONDAR2 + 0xE4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL2 + desc MONDTCTL2 + 0xE8 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT2 + desc MONRPT2 + 0xEC + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL2 + desc MONSNSEQCTL2 + 0xF0 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL2 + desc MONDNSEQCTL2 + 0xF4 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + SAR3 + desc SAR3 + 0x100 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DAR3 + desc DAR3 + 0x104 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTCTL3 + desc DTCTL3 + 0x108 + 32 + read-write + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-write + + + CNT + desc CNT + 31 + 16 + read-write + + + + + RPT3 + desc RPT3 + 0x10C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-write + + + DRPT + desc DRPT + 25 + 16 + read-write + + + + + RPTB3 + desc RPTB3 + 0x10C + 32 + read-write + 0x0 + 0x3FF03FF + + + SRPTB + desc SRPTB + 9 + 0 + read-write + + + DRPTB + desc DRPTB + 25 + 16 + read-write + + + + + SNSEQCTL3 + desc SNSEQCTL3 + 0x110 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-write + + + SNSCNT + desc SNSCNT + 31 + 20 + read-write + + + + + SNSEQCTLB3 + desc SNSEQCTLB3 + 0x110 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SNSDIST + desc SNSDIST + 19 + 0 + read-write + + + SNSCNTB + desc SNSCNTB + 31 + 20 + read-write + + + + + DNSEQCTL3 + desc DNSEQCTL3 + 0x114 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-write + + + DNSCNT + desc DNSCNT + 31 + 20 + read-write + + + + + DNSEQCTLB3 + desc DNSEQCTLB3 + 0x114 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DNSDIST + desc DNSDIST + 19 + 0 + read-write + + + DNSCNTB + desc DNSCNTB + 31 + 20 + read-write + + + + + LLP3 + desc LLP3 + 0x118 + 32 + read-write + 0x0 + 0xFFFFFFFC + + + LLP + desc LLP + 31 + 2 + read-write + + + + + CHCTL3 + desc CHCTL3 + 0x11C + 32 + read-write + 0x1000 + 0x1FFF + + + SINC + desc SINC + 1 + 0 + read-write + + + DINC + desc DINC + 3 + 2 + read-write + + + SRPTEN + desc SRPTEN + 4 + 4 + read-write + + + DRPTEN + desc DRPTEN + 5 + 5 + read-write + + + SNSEQEN + desc SNSEQEN + 6 + 6 + read-write + + + DNSEQEN + desc DNSEQEN + 7 + 7 + read-write + + + HSIZE + desc HSIZE + 9 + 8 + read-write + + + LLPEN + desc LLPEN + 10 + 10 + read-write + + + LLPRUN + desc LLPRUN + 11 + 11 + read-write + + + IE + desc IE + 12 + 12 + read-write + + + + + MONSAR3 + desc MONSAR3 + 0x120 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDAR3 + desc MONDAR3 + 0x124 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MONDTCTL3 + desc MONDTCTL3 + 0x128 + 32 + read-only + 0x1 + 0xFFFF03FF + + + BLKSIZE + desc BLKSIZE + 9 + 0 + read-only + + + CNT + desc CNT + 31 + 16 + read-only + + + + + MONRPT3 + desc MONRPT3 + 0x12C + 32 + read-only + 0x0 + 0x3FF03FF + + + SRPT + desc SRPT + 9 + 0 + read-only + + + DRPT + desc DRPT + 25 + 16 + read-only + + + + + MONSNSEQCTL3 + desc MONSNSEQCTL3 + 0x130 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + SOFFSET + desc SOFFSET + 19 + 0 + read-only + + + SNSCNT + desc SNSCNT + 31 + 20 + read-only + + + + + MONDNSEQCTL3 + desc MONDNSEQCTL3 + 0x134 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DOFFSET + desc DOFFSET + 19 + 0 + read-only + + + DNSCNT + desc DNSCNT + 31 + 20 + read-only + + + + + + + DMA2 + desc DMA + 0x40053400 + + 0x0 + 0x120 + + + + EFM + desc EFM + 0x40010400 + + 0x0 + 0x208 + + + + FAPRT + desc FAPRT + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + FAPRT + desc FAPRT + 15 + 0 + read-write + + + + + FSTP + desc FSTP + 0x4 + 32 + read-write + 0x0 + 0x1 + + + FSTP + desc FSTP + 0 + 0 + read-write + + + + + FRMC + desc FRMC + 0x8 + 32 + read-write + 0x0 + 0x10101F1 + + + SLPMD + desc SLPMD + 0 + 0 + read-write + + + FLWT + desc FLWT + 7 + 4 + read-write + + + LVM + desc LVM + 8 + 8 + read-write + + + CACHE + desc CACHE + 16 + 16 + read-write + + + CRST + desc CRST + 24 + 24 + read-write + + + + + FWMC + desc FWMC + 0xC + 32 + read-write + 0x0 + 0x171 + + + PEMODE + desc PEMODE + 0 + 0 + read-write + + + PEMOD + desc PEMOD + 6 + 4 + read-write + + + BUSHLDCTL + desc BUSHLDCTL + 8 + 8 + read-write + + + + + FSR + desc FSR + 0x10 + 32 + read-only + 0x100 + 0x13F + + + PEWERR + desc PEWERR + 0 + 0 + read-only + + + PEPRTERR + desc PEPRTERR + 1 + 1 + read-only + + + PGSZERR + desc PGSZERR + 2 + 2 + read-only + + + PGMISMTCH + desc PGMISMTCH + 3 + 3 + read-only + + + OPTEND + desc OPTEND + 4 + 4 + read-only + + + COLERR + desc COLERR + 5 + 5 + read-only + + + RDY + desc RDY + 8 + 8 + read-only + + + + + FSCLR + desc FSCLR + 0x14 + 32 + read-write + 0x0 + 0x3F + + + PEWERRCLR + desc PEWERRCLR + 0 + 0 + read-write + + + PEPRTERRCLR + desc PEPRTERRCLR + 1 + 1 + read-write + + + PGSZERRCLR + desc PGSZERRCLR + 2 + 2 + read-write + + + PGMISMTCHCLR + desc PGMISMTCHCLR + 3 + 3 + read-write + + + OPTENDCLR + desc OPTENDCLR + 4 + 4 + read-write + + + COLERRCLR + desc COLERRCLR + 5 + 5 + read-write + + + + + FITE + desc FITE + 0x18 + 32 + read-write + 0x0 + 0x7 + + + PEERRITE + desc PEERRITE + 0 + 0 + read-write + + + OPTENDITE + desc OPTENDITE + 1 + 1 + read-write + + + COLERRITE + desc COLERRITE + 2 + 2 + read-write + + + + + FSWP + desc FSWP + 0x1C + 32 + read-only + 0x1 + 0x1 + + + FSWP + desc FSWP + 0 + 0 + read-only + + + + + FPMTSW + desc FPMTSW + 0x20 + 32 + read-write + 0x0 + 0x7FFFF + + + FPMTSW + desc FPMTSW + 18 + 0 + read-write + + + + + FPMTEW + desc FPMTEW + 0x24 + 32 + read-write + 0x0 + 0x7FFFF + + + FPMTEW + desc FPMTEW + 18 + 0 + read-write + + + + + UQID0 + desc UQID0 + 0x50 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + UQID1 + desc UQID1 + 0x54 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + UQID2 + desc UQID2 + 0x58 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + MMF_REMPRT + desc MMF_REMPRT + 0x100 + 32 + read-write + 0x0 + 0xFFFF + + + REMPRT + desc REMPRT + 15 + 0 + read-write + + + + + MMF_REMCR0 + desc MMF_REMCR0 + 0x104 + 32 + read-write + 0x0 + 0x9FFFF01F + + + RMSIZE + desc RMSIZE + 4 + 0 + read-write + + + RMTADDR + desc RMTADDR + 28 + 12 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + MMF_REMCR1 + desc MMF_REMCR1 + 0x108 + 32 + read-write + 0x0 + 0x9FFFF01F + + + RMSIZE + desc RMSIZE + 4 + 0 + read-write + + + RMTADDR + desc RMTADDR + 28 + 12 + read-write + + + EN + desc EN + 31 + 31 + read-write + + + + + + + EMB0 + desc EMB + 0x40017C00 + + 0x0 + 0x18 + + + + CTL + desc CTL + 0x0 + 32 + read-write + 0x0 + 0xF00001EF + + + PORTINEN + desc PORTINEN + 0 + 0 + read-write + + + CMPEN0 + desc CMPEN0 + 1 + 1 + read-write + + + CMPEN1 + desc CMPEN1 + 2 + 2 + read-write + + + CMPEN2 + desc CMPEN2 + 3 + 3 + read-write + + + OSCSTPEN + desc OSCSTPEN + 5 + 5 + read-write + + + PWMSEN0 + desc PWMSEN0 + 6 + 6 + read-write + + + PWMSEN1 + desc PWMSEN1 + 7 + 7 + read-write + + + PWMSEN2 + desc PWMSEN2 + 8 + 8 + read-write + + + NFSEL + desc NFSEL + 29 + 28 + read-write + + + NFEN + desc NFEN + 30 + 30 + read-write + + + INVSEL + desc INVSEL + 31 + 31 + read-write + + + + + PWMLV + desc PWMLV + 0x4 + 32 + read-write + 0x0 + 0x7 + + + PWMLV0 + desc PWMLV0 + 0 + 0 + read-write + + + PWMLV1 + desc PWMLV1 + 1 + 1 + read-write + + + PWMLV2 + desc PWMLV2 + 2 + 2 + read-write + + + + + SOE + desc SOE + 0x8 + 32 + read-write + 0x0 + 0x1 + + + SOE + desc SOE + 0 + 0 + read-write + + + + + STAT + desc STAT + 0xC + 32 + read-only + 0x0 + 0x3F + + + PORTINF + desc PORTINF + 0 + 0 + read-only + + + PWMSF + desc PWMSF + 1 + 1 + read-only + + + CMPF + desc CMPF + 2 + 2 + read-only + + + OSF + desc OSF + 3 + 3 + read-only + + + PORTINST + desc PORTINST + 4 + 4 + read-only + + + PWMST + desc PWMST + 5 + 5 + read-only + + + + + STATCLR + desc STATCLR + 0x10 + 32 + write-only + 0x0 + 0xF + + + PORTINFCLR + desc PORTINFCLR + 0 + 0 + write-only + + + PWMSFCLR + desc PWMSFCLR + 1 + 1 + write-only + + + CMPFCLR + desc CMPFCLR + 2 + 2 + write-only + + + OSFCLR + desc OSFCLR + 3 + 3 + write-only + + + + + INTEN + desc INTEN + 0x14 + 32 + read-write + 0x0 + 0xF + + + PORTINTEN + desc PORTINTEN + 0 + 0 + read-write + + + PWMINTEN + desc PWMINTEN + 1 + 1 + read-write + + + CMPINTEN + desc CMPINTEN + 2 + 2 + read-write + + + OSINTEN + desc OSINTEN + 3 + 3 + read-write + + + + + + + EMB1 + desc EMB + 0x40017C20 + + 0x0 + 0x18 + + + + EMB2 + desc EMB + 0x40017C40 + + 0x0 + 0x18 + + + + EMB3 + desc EMB + 0x40017C60 + + 0x0 + 0x18 + + + + FCM + desc FCM + 0x40048400 + + 0x0 + 0x24 + + + + LVR + desc LVR + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + LVR + desc LVR + 15 + 0 + read-write + + + + + UVR + desc UVR + 0x4 + 32 + read-write + 0x0 + 0xFFFF + + + UVR + desc UVR + 15 + 0 + read-write + + + + + CNTR + desc CNTR + 0x8 + 32 + read-only + 0x0 + 0xFFFF + + + CNTR + desc CNTR + 15 + 0 + read-only + + + + + STR + desc STR + 0xC + 32 + read-write + 0x0 + 0x1 + + + START + desc START + 0 + 0 + read-write + + + + + MCCR + desc MCCR + 0x10 + 32 + read-write + 0x0 + 0xF3 + + + MDIVS + desc MDIVS + 1 + 0 + read-write + + + MCKS + desc MCKS + 7 + 4 + read-write + + + + + RCCR + desc RCCR + 0x14 + 32 + read-write + 0x0 + 0xB3FB + + + RDIVS + desc RDIVS + 1 + 0 + read-write + + + RCKS + desc RCKS + 6 + 3 + read-write + + + INEXS + desc INEXS + 7 + 7 + read-write + + + DNFS + desc DNFS + 9 + 8 + read-write + + + EDGES + desc EDGES + 13 + 12 + read-write + + + EXREFE + desc EXREFE + 15 + 15 + read-write + + + + + RIER + desc RIER + 0x18 + 32 + read-write + 0x0 + 0x97 + + + ERRIE + desc ERRIE + 0 + 0 + read-write + + + MENDIE + desc MENDIE + 1 + 1 + read-write + + + OVFIE + desc OVFIE + 2 + 2 + read-write + + + ERRINTRS + desc ERRINTRS + 4 + 4 + read-write + + + ERRE + desc ERRE + 7 + 7 + read-write + + + + + SR + desc SR + 0x1C + 32 + read-only + 0x0 + 0x7 + + + ERRF + desc ERRF + 0 + 0 + read-only + + + MENDF + desc MENDF + 1 + 1 + read-only + + + OVF + desc OVF + 2 + 2 + read-only + + + + + CLR + desc CLR + 0x20 + 32 + write-only + 0x0 + 0x7 + + + ERRFCLR + desc ERRFCLR + 0 + 0 + write-only + + + MENDFCLR + desc MENDFCLR + 1 + 1 + write-only + + + OVFCLR + desc OVFCLR + 2 + 2 + write-only + + + + + + + GPIO + desc GPIO + 0x40053800 + + 0x0 + 0x54C + + + + PIDRA + desc PIDRA + 0x0 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRA + desc PODRA + 0x4 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERA + desc POERA + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRA + desc POSRA + 0x8 + 16 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PORRA + desc PORRA + 0xA + 16 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + POTRA + desc POTRA + 0xC + 16 + read-write + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + read-write + + + POT01 + desc POT01 + 1 + 1 + read-write + + + POT02 + desc POT02 + 2 + 2 + read-write + + + POT03 + desc POT03 + 3 + 3 + read-write + + + POT04 + desc POT04 + 4 + 4 + read-write + + + POT05 + desc POT05 + 5 + 5 + read-write + + + POT06 + desc POT06 + 6 + 6 + read-write + + + POT07 + desc POT07 + 7 + 7 + read-write + + + POT08 + desc POT08 + 8 + 8 + read-write + + + POT09 + desc POT09 + 9 + 9 + read-write + + + POT10 + desc POT10 + 10 + 10 + read-write + + + POT11 + desc POT11 + 11 + 11 + read-write + + + POT12 + desc POT12 + 12 + 12 + read-write + + + POT13 + desc POT13 + 13 + 13 + read-write + + + POT14 + desc POT14 + 14 + 14 + read-write + + + POT15 + desc POT15 + 15 + 15 + read-write + + + + + PIDRB + desc PIDRB + 0x10 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRB + desc PODRB + 0x14 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERB + desc POERB + 0x16 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRB + desc POSRB + 0x18 + 16 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PORRB + desc PORRB + 0x1A + 16 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + POTRB + desc POTRB + 0x1C + 16 + read-write + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + read-write + + + POT01 + desc POT01 + 1 + 1 + read-write + + + POT02 + desc POT02 + 2 + 2 + read-write + + + POT03 + desc POT03 + 3 + 3 + read-write + + + POT04 + desc POT04 + 4 + 4 + read-write + + + POT05 + desc POT05 + 5 + 5 + read-write + + + POT06 + desc POT06 + 6 + 6 + read-write + + + POT07 + desc POT07 + 7 + 7 + read-write + + + POT08 + desc POT08 + 8 + 8 + read-write + + + POT09 + desc POT09 + 9 + 9 + read-write + + + POT10 + desc POT10 + 10 + 10 + read-write + + + POT11 + desc POT11 + 11 + 11 + read-write + + + POT12 + desc POT12 + 12 + 12 + read-write + + + POT13 + desc POT13 + 13 + 13 + read-write + + + POT14 + desc POT14 + 14 + 14 + read-write + + + POT15 + desc POT15 + 15 + 15 + read-write + + + + + PIDRC + desc PIDRC + 0x20 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRC + desc PODRC + 0x24 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERC + desc POERC + 0x26 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRC + desc POSRC + 0x28 + 16 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PORRC + desc PORRC + 0x2A + 16 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + POTRC + desc POTRC + 0x2C + 16 + read-write + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + read-write + + + POT01 + desc POT01 + 1 + 1 + read-write + + + POT02 + desc POT02 + 2 + 2 + read-write + + + POT03 + desc POT03 + 3 + 3 + read-write + + + POT04 + desc POT04 + 4 + 4 + read-write + + + POT05 + desc POT05 + 5 + 5 + read-write + + + POT06 + desc POT06 + 6 + 6 + read-write + + + POT07 + desc POT07 + 7 + 7 + read-write + + + POT08 + desc POT08 + 8 + 8 + read-write + + + POT09 + desc POT09 + 9 + 9 + read-write + + + POT10 + desc POT10 + 10 + 10 + read-write + + + POT11 + desc POT11 + 11 + 11 + read-write + + + POT12 + desc POT12 + 12 + 12 + read-write + + + POT13 + desc POT13 + 13 + 13 + read-write + + + POT14 + desc POT14 + 14 + 14 + read-write + + + POT15 + desc POT15 + 15 + 15 + read-write + + + + + PIDRD + desc PIDRD + 0x30 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRD + desc PODRD + 0x34 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERD + desc POERD + 0x36 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRD + desc POSRD + 0x38 + 16 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PORRD + desc PORRD + 0x3A + 16 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + POTRD + desc POTRD + 0x3C + 16 + read-write + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + read-write + + + POT01 + desc POT01 + 1 + 1 + read-write + + + POT02 + desc POT02 + 2 + 2 + read-write + + + POT03 + desc POT03 + 3 + 3 + read-write + + + POT04 + desc POT04 + 4 + 4 + read-write + + + POT05 + desc POT05 + 5 + 5 + read-write + + + POT06 + desc POT06 + 6 + 6 + read-write + + + POT07 + desc POT07 + 7 + 7 + read-write + + + POT08 + desc POT08 + 8 + 8 + read-write + + + POT09 + desc POT09 + 9 + 9 + read-write + + + POT10 + desc POT10 + 10 + 10 + read-write + + + POT11 + desc POT11 + 11 + 11 + read-write + + + POT12 + desc POT12 + 12 + 12 + read-write + + + POT13 + desc POT13 + 13 + 13 + read-write + + + POT14 + desc POT14 + 14 + 14 + read-write + + + POT15 + desc POT15 + 15 + 15 + read-write + + + + + PIDRE + desc PIDRE + 0x40 + 16 + read-only + 0x0 + 0xFFFF + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + PIN03 + desc PIN03 + 3 + 3 + read-only + + + PIN04 + desc PIN04 + 4 + 4 + read-only + + + PIN05 + desc PIN05 + 5 + 5 + read-only + + + PIN06 + desc PIN06 + 6 + 6 + read-only + + + PIN07 + desc PIN07 + 7 + 7 + read-only + + + PIN08 + desc PIN08 + 8 + 8 + read-only + + + PIN09 + desc PIN09 + 9 + 9 + read-only + + + PIN10 + desc PIN10 + 10 + 10 + read-only + + + PIN11 + desc PIN11 + 11 + 11 + read-only + + + PIN12 + desc PIN12 + 12 + 12 + read-only + + + PIN13 + desc PIN13 + 13 + 13 + read-only + + + PIN14 + desc PIN14 + 14 + 14 + read-only + + + PIN15 + desc PIN15 + 15 + 15 + read-only + + + + + PODRE + desc PODRE + 0x44 + 16 + read-write + 0x0 + 0xFFFF + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + POUT03 + desc POUT03 + 3 + 3 + read-write + + + POUT04 + desc POUT04 + 4 + 4 + read-write + + + POUT05 + desc POUT05 + 5 + 5 + read-write + + + POUT06 + desc POUT06 + 6 + 6 + read-write + + + POUT07 + desc POUT07 + 7 + 7 + read-write + + + POUT08 + desc POUT08 + 8 + 8 + read-write + + + POUT09 + desc POUT09 + 9 + 9 + read-write + + + POUT10 + desc POUT10 + 10 + 10 + read-write + + + POUT11 + desc POUT11 + 11 + 11 + read-write + + + POUT12 + desc POUT12 + 12 + 12 + read-write + + + POUT13 + desc POUT13 + 13 + 13 + read-write + + + POUT14 + desc POUT14 + 14 + 14 + read-write + + + POUT15 + desc POUT15 + 15 + 15 + read-write + + + + + POERE + desc POERE + 0x46 + 16 + read-write + 0x0 + 0xFFFF + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + POUTE03 + desc POUTE03 + 3 + 3 + read-write + + + POUTE04 + desc POUTE04 + 4 + 4 + read-write + + + POUTE05 + desc POUTE05 + 5 + 5 + read-write + + + POUTE06 + desc POUTE06 + 6 + 6 + read-write + + + POUTE07 + desc POUTE07 + 7 + 7 + read-write + + + POUTE08 + desc POUTE08 + 8 + 8 + read-write + + + POUTE09 + desc POUTE09 + 9 + 9 + read-write + + + POUTE10 + desc POUTE10 + 10 + 10 + read-write + + + POUTE11 + desc POUTE11 + 11 + 11 + read-write + + + POUTE12 + desc POUTE12 + 12 + 12 + read-write + + + POUTE13 + desc POUTE13 + 13 + 13 + read-write + + + POUTE14 + desc POUTE14 + 14 + 14 + read-write + + + POUTE15 + desc POUTE15 + 15 + 15 + read-write + + + + + POSRE + desc POSRE + 0x48 + 16 + read-write + 0x0 + 0xFFFF + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + POS03 + desc POS03 + 3 + 3 + read-write + + + POS04 + desc POS04 + 4 + 4 + read-write + + + POS05 + desc POS05 + 5 + 5 + read-write + + + POS06 + desc POS06 + 6 + 6 + read-write + + + POS07 + desc POS07 + 7 + 7 + read-write + + + POS08 + desc POS08 + 8 + 8 + read-write + + + POS09 + desc POS09 + 9 + 9 + read-write + + + POS10 + desc POS10 + 10 + 10 + read-write + + + POS11 + desc POS11 + 11 + 11 + read-write + + + POS12 + desc POS12 + 12 + 12 + read-write + + + POS13 + desc POS13 + 13 + 13 + read-write + + + POS14 + desc POS14 + 14 + 14 + read-write + + + POS15 + desc POS15 + 15 + 15 + read-write + + + + + PORRE + desc PORRE + 0x4A + 16 + read-write + 0x0 + 0xFFFF + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + POR03 + desc POR03 + 3 + 3 + read-write + + + POR04 + desc POR04 + 4 + 4 + read-write + + + POR05 + desc POR05 + 5 + 5 + read-write + + + POR06 + desc POR06 + 6 + 6 + read-write + + + POR07 + desc POR07 + 7 + 7 + read-write + + + POR08 + desc POR08 + 8 + 8 + read-write + + + POR09 + desc POR09 + 9 + 9 + read-write + + + POR10 + desc POR10 + 10 + 10 + read-write + + + POR11 + desc POR11 + 11 + 11 + read-write + + + POR12 + desc POR12 + 12 + 12 + read-write + + + POR13 + desc POR13 + 13 + 13 + read-write + + + POR14 + desc POR14 + 14 + 14 + read-write + + + POR15 + desc POR15 + 15 + 15 + read-write + + + + + POTRE + desc POTRE + 0x4C + 16 + read-write + 0x0 + 0xFFFF + + + POT00 + desc POT00 + 0 + 0 + read-write + + + POT01 + desc POT01 + 1 + 1 + read-write + + + POT02 + desc POT02 + 2 + 2 + read-write + + + POT03 + desc POT03 + 3 + 3 + read-write + + + POT04 + desc POT04 + 4 + 4 + read-write + + + POT05 + desc POT05 + 5 + 5 + read-write + + + POT06 + desc POT06 + 6 + 6 + read-write + + + POT07 + desc POT07 + 7 + 7 + read-write + + + POT08 + desc POT08 + 8 + 8 + read-write + + + POT09 + desc POT09 + 9 + 9 + read-write + + + POT10 + desc POT10 + 10 + 10 + read-write + + + POT11 + desc POT11 + 11 + 11 + read-write + + + POT12 + desc POT12 + 12 + 12 + read-write + + + POT13 + desc POT13 + 13 + 13 + read-write + + + POT14 + desc POT14 + 14 + 14 + read-write + + + POT15 + desc POT15 + 15 + 15 + read-write + + + + + PIDRH + desc PIDRH + 0x50 + 16 + read-only + 0x0 + 0x7 + + + PIN00 + desc PIN00 + 0 + 0 + read-only + + + PIN01 + desc PIN01 + 1 + 1 + read-only + + + PIN02 + desc PIN02 + 2 + 2 + read-only + + + + + PODRH + desc PODRH + 0x54 + 16 + read-write + 0x0 + 0x7 + + + POUT00 + desc POUT00 + 0 + 0 + read-write + + + POUT01 + desc POUT01 + 1 + 1 + read-write + + + POUT02 + desc POUT02 + 2 + 2 + read-write + + + + + POERH + desc POERH + 0x56 + 16 + read-write + 0x0 + 0x7 + + + POUTE00 + desc POUTE00 + 0 + 0 + read-write + + + POUTE01 + desc POUTE01 + 1 + 1 + read-write + + + POUTE02 + desc POUTE02 + 2 + 2 + read-write + + + + + POSRH + desc POSRH + 0x58 + 16 + read-write + 0x0 + 0x7 + + + POS00 + desc POS00 + 0 + 0 + read-write + + + POS01 + desc POS01 + 1 + 1 + read-write + + + POS02 + desc POS02 + 2 + 2 + read-write + + + + + PORRH + desc PORRH + 0x5A + 16 + read-write + 0x0 + 0x7 + + + POR00 + desc POR00 + 0 + 0 + read-write + + + POR01 + desc POR01 + 1 + 1 + read-write + + + POR02 + desc POR02 + 2 + 2 + read-write + + + + + POTRH + desc POTRH + 0x5C + 16 + read-write + 0x0 + 0x7 + + + POT00 + desc POT00 + 0 + 0 + read-write + + + POT01 + desc POT01 + 1 + 1 + read-write + + + POT02 + desc POT02 + 2 + 2 + read-write + + + + + PSPCR + desc PSPCR + 0x3F4 + 16 + read-write + 0x0 + 0x1F + + + SPFE + desc SPFE + 4 + 0 + read-write + + + + + PCCR + desc PCCR + 0x3F8 + 16 + read-write + 0x0 + 0xC00F + + + BFSEL + desc BFSEL + 3 + 0 + read-write + + + RDWT + desc RDWT + 15 + 14 + read-write + + + + + PINAER + desc PINAER + 0x3FA + 16 + read-write + 0x0 + 0x3F + + + PINAE + desc PINAE + 5 + 0 + read-write + + + + + PWPR + desc PWPR + 0x3FC + 16 + read-write + 0x0 + 0xFF01 + + + WE + desc WE + 0 + 0 + read-write + + + WP + desc WP + 15 + 8 + write-only + + + + + PCRA0 + desc PCRA0 + 0x400 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA0 + desc PFSRA0 + 0x402 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA1 + desc PCRA1 + 0x404 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA1 + desc PFSRA1 + 0x406 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA2 + desc PCRA2 + 0x408 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA2 + desc PFSRA2 + 0x40A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA3 + desc PCRA3 + 0x40C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA3 + desc PFSRA3 + 0x40E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA4 + desc PCRA4 + 0x410 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA4 + desc PFSRA4 + 0x412 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA5 + desc PCRA5 + 0x414 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA5 + desc PFSRA5 + 0x416 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA6 + desc PCRA6 + 0x418 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA6 + desc PFSRA6 + 0x41A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA7 + desc PCRA7 + 0x41C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA7 + desc PFSRA7 + 0x41E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA8 + desc PCRA8 + 0x420 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA8 + desc PFSRA8 + 0x422 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA9 + desc PCRA9 + 0x424 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA9 + desc PFSRA9 + 0x426 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA10 + desc PCRA10 + 0x428 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA10 + desc PFSRA10 + 0x42A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA11 + desc PCRA11 + 0x42C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA11 + desc PFSRA11 + 0x42E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA12 + desc PCRA12 + 0x430 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA12 + desc PFSRA12 + 0x432 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA13 + desc PCRA13 + 0x434 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA13 + desc PFSRA13 + 0x436 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA14 + desc PCRA14 + 0x438 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA14 + desc PFSRA14 + 0x43A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRA15 + desc PCRA15 + 0x43C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRA15 + desc PFSRA15 + 0x43E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB0 + desc PCRB0 + 0x440 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB0 + desc PFSRB0 + 0x442 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB1 + desc PCRB1 + 0x444 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB1 + desc PFSRB1 + 0x446 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB2 + desc PCRB2 + 0x448 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB2 + desc PFSRB2 + 0x44A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB3 + desc PCRB3 + 0x44C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB3 + desc PFSRB3 + 0x44E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB4 + desc PCRB4 + 0x450 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB4 + desc PFSRB4 + 0x452 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB5 + desc PCRB5 + 0x454 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB5 + desc PFSRB5 + 0x456 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB6 + desc PCRB6 + 0x458 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB6 + desc PFSRB6 + 0x45A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB7 + desc PCRB7 + 0x45C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB7 + desc PFSRB7 + 0x45E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB8 + desc PCRB8 + 0x460 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB8 + desc PFSRB8 + 0x462 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB9 + desc PCRB9 + 0x464 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB9 + desc PFSRB9 + 0x466 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB10 + desc PCRB10 + 0x468 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB10 + desc PFSRB10 + 0x46A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB11 + desc PCRB11 + 0x46C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB11 + desc PFSRB11 + 0x46E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB12 + desc PCRB12 + 0x470 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB12 + desc PFSRB12 + 0x472 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB13 + desc PCRB13 + 0x474 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB13 + desc PFSRB13 + 0x476 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB14 + desc PCRB14 + 0x478 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB14 + desc PFSRB14 + 0x47A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRB15 + desc PCRB15 + 0x47C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRB15 + desc PFSRB15 + 0x47E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC0 + desc PCRC0 + 0x480 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC0 + desc PFSRC0 + 0x482 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC1 + desc PCRC1 + 0x484 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC1 + desc PFSRC1 + 0x486 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC2 + desc PCRC2 + 0x488 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC2 + desc PFSRC2 + 0x48A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC3 + desc PCRC3 + 0x48C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC3 + desc PFSRC3 + 0x48E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC4 + desc PCRC4 + 0x490 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC4 + desc PFSRC4 + 0x492 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC5 + desc PCRC5 + 0x494 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC5 + desc PFSRC5 + 0x496 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC6 + desc PCRC6 + 0x498 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC6 + desc PFSRC6 + 0x49A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC7 + desc PCRC7 + 0x49C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC7 + desc PFSRC7 + 0x49E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC8 + desc PCRC8 + 0x4A0 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC8 + desc PFSRC8 + 0x4A2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC9 + desc PCRC9 + 0x4A4 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC9 + desc PFSRC9 + 0x4A6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC10 + desc PCRC10 + 0x4A8 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC10 + desc PFSRC10 + 0x4AA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC11 + desc PCRC11 + 0x4AC + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC11 + desc PFSRC11 + 0x4AE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC12 + desc PCRC12 + 0x4B0 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC12 + desc PFSRC12 + 0x4B2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC13 + desc PCRC13 + 0x4B4 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC13 + desc PFSRC13 + 0x4B6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC14 + desc PCRC14 + 0x4B8 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC14 + desc PFSRC14 + 0x4BA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRC15 + desc PCRC15 + 0x4BC + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRC15 + desc PFSRC15 + 0x4BE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD0 + desc PCRD0 + 0x4C0 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD0 + desc PFSRD0 + 0x4C2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD1 + desc PCRD1 + 0x4C4 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD1 + desc PFSRD1 + 0x4C6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD2 + desc PCRD2 + 0x4C8 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD2 + desc PFSRD2 + 0x4CA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD3 + desc PCRD3 + 0x4CC + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD3 + desc PFSRD3 + 0x4CE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD4 + desc PCRD4 + 0x4D0 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD4 + desc PFSRD4 + 0x4D2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD5 + desc PCRD5 + 0x4D4 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD5 + desc PFSRD5 + 0x4D6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD6 + desc PCRD6 + 0x4D8 + 16 + read-write + 0x8100 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD6 + desc PFSRD6 + 0x4DA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD7 + desc PCRD7 + 0x4DC + 16 + read-write + 0x8100 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD7 + desc PFSRD7 + 0x4DE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD8 + desc PCRD8 + 0x4E0 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD8 + desc PFSRD8 + 0x4E2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD9 + desc PCRD9 + 0x4E4 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD9 + desc PFSRD9 + 0x4E6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD10 + desc PCRD10 + 0x4E8 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD10 + desc PFSRD10 + 0x4EA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD11 + desc PCRD11 + 0x4EC + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD11 + desc PFSRD11 + 0x4EE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD12 + desc PCRD12 + 0x4F0 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD12 + desc PFSRD12 + 0x4F2 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD13 + desc PCRD13 + 0x4F4 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD13 + desc PFSRD13 + 0x4F6 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD14 + desc PCRD14 + 0x4F8 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD14 + desc PFSRD14 + 0x4FA + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRD15 + desc PCRD15 + 0x4FC + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRD15 + desc PFSRD15 + 0x4FE + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE0 + desc PCRE0 + 0x500 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE0 + desc PFSRE0 + 0x502 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE1 + desc PCRE1 + 0x504 + 16 + read-write + 0x40 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE1 + desc PFSRE1 + 0x506 + 16 + read-write + 0xD + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE2 + desc PCRE2 + 0x508 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE2 + desc PFSRE2 + 0x50A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE3 + desc PCRE3 + 0x50C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE3 + desc PFSRE3 + 0x50E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE4 + desc PCRE4 + 0x510 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE4 + desc PFSRE4 + 0x512 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE5 + desc PCRE5 + 0x514 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE5 + desc PFSRE5 + 0x516 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE6 + desc PCRE6 + 0x518 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE6 + desc PFSRE6 + 0x51A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE7 + desc PCRE7 + 0x51C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE7 + desc PFSRE7 + 0x51E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE8 + desc PCRE8 + 0x520 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE8 + desc PFSRE8 + 0x522 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE9 + desc PCRE9 + 0x524 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE9 + desc PFSRE9 + 0x526 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE10 + desc PCRE10 + 0x528 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE10 + desc PFSRE10 + 0x52A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE11 + desc PCRE11 + 0x52C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE11 + desc PFSRE11 + 0x52E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE12 + desc PCRE12 + 0x530 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE12 + desc PFSRE12 + 0x532 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE13 + desc PCRE13 + 0x534 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE13 + desc PFSRE13 + 0x536 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE14 + desc PCRE14 + 0x538 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE14 + desc PFSRE14 + 0x53A + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRE15 + desc PCRE15 + 0x53C + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRE15 + desc PFSRE15 + 0x53E + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH0 + desc PCRH0 + 0x540 + 16 + read-write + 0x0 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH0 + desc PFSRH0 + 0x542 + 16 + read-write + 0x0 + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH1 + desc PCRH1 + 0x544 + 16 + read-write + 0x40 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH1 + desc PFSRH1 + 0x546 + 16 + read-write + 0xD + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + PCRH2 + desc PCRH2 + 0x548 + 16 + read-write + 0x50 + 0xD377 + + + POUT + desc POUT + 0 + 0 + read-write + + + POUTE + desc POUTE + 1 + 1 + read-write + + + NOD + desc NOD + 2 + 2 + read-write + + + DRV + desc DRV + 5 + 4 + read-write + + + PUU + desc PUU + 6 + 6 + read-write + + + PIN + desc PIN + 8 + 8 + read-only + + + INVE + desc INVE + 9 + 9 + read-write + + + INTE + desc INTE + 12 + 12 + read-write + + + LTE + desc LTE + 14 + 14 + read-write + + + DDIS + desc DDIS + 15 + 15 + read-write + + + + + PFSRH2 + desc PFSRH2 + 0x54A + 16 + read-write + 0xD + 0x13F + + + FSEL + desc FSEL + 5 + 0 + read-write + + + BFE + desc BFE + 8 + 8 + read-write + + + + + + + HASH + desc HASH + 0x40008400 + + 0x0 + 0x80 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x3 + + + START + desc START + 0 + 0 + read-write + + + FST_GRP + desc FST_GRP + 1 + 1 + read-write + + + + + HR7 + desc HR7 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR6 + desc HR6 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR5 + desc HR5 + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR4 + desc HR4 + 0x1C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR3 + desc HR3 + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR2 + desc HR2 + 0x24 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR1 + desc HR1 + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HR0 + desc HR0 + 0x2C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR15 + desc DR15 + 0x40 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR14 + desc DR14 + 0x44 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR13 + desc DR13 + 0x48 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR12 + desc DR12 + 0x4C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR11 + desc DR11 + 0x50 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR10 + desc DR10 + 0x54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR9 + desc DR9 + 0x58 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR8 + desc DR8 + 0x5C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR7 + desc DR7 + 0x60 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR6 + desc DR6 + 0x64 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR5 + desc DR5 + 0x68 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR4 + desc DR4 + 0x6C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR3 + desc DR3 + 0x70 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR2 + desc DR2 + 0x74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR1 + desc DR1 + 0x78 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DR0 + desc DR0 + 0x7C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + I2C1 + desc I2C + 0x4004E000 + + 0x0 + 0x34 + + + + CR1 + desc CR1 + 0x0 + 32 + read-write + 0x40 + 0x87DF + + + PE + desc PE + 0 + 0 + read-write + + + SMBUS + desc SMBUS + 1 + 1 + read-write + + + SMBALRTEN + desc SMBALRTEN + 2 + 2 + read-write + + + SMBDEFAULTEN + desc SMBDEFAULTEN + 3 + 3 + read-write + + + SMBHOSTEN + desc SMBHOSTEN + 4 + 4 + read-write + + + GCEN + desc GCEN + 6 + 6 + read-write + + + RESTART + desc RESTART + 7 + 7 + read-write + + + START + desc START + 8 + 8 + read-write + + + STOP + desc STOP + 9 + 9 + read-write + + + ACK + desc ACK + 10 + 10 + read-write + + + SWRST + desc SWRST + 15 + 15 + read-write + + + + + CR2 + desc CR2 + 0x4 + 32 + read-write + 0x0 + 0xF052DF + + + STARTIE + desc STARTIE + 0 + 0 + read-write + + + SLADDR0IE + desc SLADDR0IE + 1 + 1 + read-write + + + SLADDR1IE + desc SLADDR1IE + 2 + 2 + read-write + + + TENDIE + desc TENDIE + 3 + 3 + read-write + + + STOPIE + desc STOPIE + 4 + 4 + read-write + + + RFULLIE + desc RFULLIE + 6 + 6 + read-write + + + TEMPTYIE + desc TEMPTYIE + 7 + 7 + read-write + + + ARLOIE + desc ARLOIE + 9 + 9 + read-write + + + NACKIE + desc NACKIE + 12 + 12 + read-write + + + TMOUTIE + desc TMOUTIE + 14 + 14 + read-write + + + GENCALLIE + desc GENCALLIE + 20 + 20 + read-write + + + SMBDEFAULTIE + desc SMBDEFAULTIE + 21 + 21 + read-write + + + SMBHOSTIE + desc SMBHOSTIE + 22 + 22 + read-write + + + SMBALRTIE + desc SMBALRTIE + 23 + 23 + read-write + + + + + CR3 + desc CR3 + 0x8 + 32 + read-write + 0x6 + 0x87 + + + TMOUTEN + desc TMOUTEN + 0 + 0 + read-write + + + LTMOUT + desc LTMOUT + 1 + 1 + read-write + + + HTMOUT + desc HTMOUT + 2 + 2 + read-write + + + FACKEN + desc FACKEN + 7 + 7 + read-write + + + + + CR4 + desc CR4 + 0xC + 32 + read-write + 0x300307 + 0x400 + + + BUSWAIT + desc BUSWAIT + 10 + 10 + read-write + + + + + SLR0 + desc SLR0 + 0x10 + 32 + read-write + 0x1000 + 0x93FF + + + SLADDR0 + desc SLADDR0 + 9 + 0 + read-write + + + SLADDR0EN + desc SLADDR0EN + 12 + 12 + read-write + + + ADDRMOD0 + desc ADDRMOD0 + 15 + 15 + read-write + + + + + SLR1 + desc SLR1 + 0x14 + 32 + read-write + 0x0 + 0x93FF + + + SLADDR1 + desc SLADDR1 + 9 + 0 + read-write + + + SLADDR1EN + desc SLADDR1EN + 12 + 12 + read-write + + + ADDRMOD1 + desc ADDRMOD1 + 15 + 15 + read-write + + + + + SLTR + desc SLTR + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + TOUTLOW + desc TOUTLOW + 15 + 0 + read-write + + + TOUTHIGH + desc TOUTHIGH + 31 + 16 + read-write + + + + + SR + desc SR + 0x1C + 32 + read-write + 0x0 + 0xF756DF + + + STARTF + desc STARTF + 0 + 0 + read-write + + + SLADDR0F + desc SLADDR0F + 1 + 1 + read-write + + + SLADDR1F + desc SLADDR1F + 2 + 2 + read-write + + + TENDF + desc TENDF + 3 + 3 + read-write + + + STOPF + desc STOPF + 4 + 4 + read-write + + + RFULLF + desc RFULLF + 6 + 6 + read-write + + + TEMPTYF + desc TEMPTYF + 7 + 7 + read-write + + + ARLOF + desc ARLOF + 9 + 9 + read-write + + + ACKRF + desc ACKRF + 10 + 10 + read-write + + + NACKF + desc NACKF + 12 + 12 + read-write + + + TMOUTF + desc TMOUTF + 14 + 14 + read-write + + + MSL + desc MSL + 16 + 16 + read-write + + + BUSY + desc BUSY + 17 + 17 + read-write + + + TRA + desc TRA + 18 + 18 + read-write + + + GENCALLF + desc GENCALLF + 20 + 20 + read-write + + + SMBDEFAULTF + desc SMBDEFAULTF + 21 + 21 + read-write + + + SMBHOSTF + desc SMBHOSTF + 22 + 22 + read-write + + + SMBALRTF + desc SMBALRTF + 23 + 23 + read-write + + + + + CLR + desc CLR + 0x20 + 32 + write-only + 0x0 + 0xF052DF + + + STARTFCLR + desc STARTFCLR + 0 + 0 + write-only + + + SLADDR0FCLR + desc SLADDR0FCLR + 1 + 1 + write-only + + + SLADDR1FCLR + desc SLADDR1FCLR + 2 + 2 + write-only + + + TENDFCLR + desc TENDFCLR + 3 + 3 + write-only + + + STOPFCLR + desc STOPFCLR + 4 + 4 + write-only + + + RFULLFCLR + desc RFULLFCLR + 6 + 6 + write-only + + + TEMPTYFCLR + desc TEMPTYFCLR + 7 + 7 + write-only + + + ARLOFCLR + desc ARLOFCLR + 9 + 9 + write-only + + + NACKFCLR + desc NACKFCLR + 12 + 12 + write-only + + + TMOUTFCLR + desc TMOUTFCLR + 14 + 14 + write-only + + + GENCALLFCLR + desc GENCALLFCLR + 20 + 20 + write-only + + + SMBDEFAULTFCLR + desc SMBDEFAULTFCLR + 21 + 21 + write-only + + + SMBHOSTFCLR + desc SMBHOSTFCLR + 22 + 22 + write-only + + + SMBALRTFCLR + desc SMBALRTFCLR + 23 + 23 + write-only + + + + + DTR + desc DTR + 0x24 + 8 + write-only + 0xFF + 0xFF + + + DT + desc DT + 7 + 0 + write-only + + + + + DRR + desc DRR + 0x28 + 8 + read-only + 0x0 + 0xFF + + + DR + desc DR + 7 + 0 + read-only + + + + + CCR + desc CCR + 0x2C + 32 + read-write + 0x1F1F + 0x71F1F + + + SLOWW + desc SLOWW + 4 + 0 + read-write + + + SHIGHW + desc SHIGHW + 12 + 8 + read-write + + + FREQ + desc FREQ + 18 + 16 + read-write + + + + + FLTR + desc FLTR + 0x30 + 32 + read-write + 0x10 + 0x33 + + + DNF + desc DNF + 1 + 0 + read-write + + + DNFEN + desc DNFEN + 4 + 4 + read-write + + + ANFEN + desc ANFEN + 5 + 5 + read-write + + + + + + + I2C2 + desc I2C + 0x4004E400 + + 0x0 + 0x34 + + + + I2C3 + desc I2C + 0x4004E800 + + 0x0 + 0x34 + + + + I2S1 + desc I2S + 0x4001E000 + + 0x0 + 0x1C + + + + CTRL + desc CTRL + 0x0 + 32 + read-write + 0x2200 + 0xFF77FF + + + TXE + desc TXE + 0 + 0 + read-write + + + TXIE + desc TXIE + 1 + 1 + read-write + + + RXE + desc RXE + 2 + 2 + read-write + + + RXIE + desc RXIE + 3 + 3 + read-write + + + EIE + desc EIE + 4 + 4 + read-write + + + WMS + desc WMS + 5 + 5 + read-write + + + ODD + desc ODD + 6 + 6 + read-write + + + MCKOE + desc MCKOE + 7 + 7 + read-write + + + TXBIRQWL + desc TXBIRQWL + 10 + 8 + read-write + + + RXBIRQWL + desc RXBIRQWL + 14 + 12 + read-write + + + FIFOR + desc FIFOR + 16 + 16 + read-write + + + CODECRC + desc CODECRC + 17 + 17 + read-write + + + I2SPLLSEL + desc I2SPLLSEL + 18 + 18 + read-write + + + SDOE + desc SDOE + 19 + 19 + read-write + + + LRCKOE + desc LRCKOE + 20 + 20 + read-write + + + CKOE + desc CKOE + 21 + 21 + read-write + + + DUPLEX + desc DUPLEX + 22 + 22 + read-write + + + CLKSEL + desc CLKSEL + 23 + 23 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-only + 0x14 + 0x3F + + + TXBA + desc TXBA + 0 + 0 + read-only + + + RXBA + desc RXBA + 1 + 1 + read-only + + + TXBE + desc TXBE + 2 + 2 + read-only + + + TXBF + desc TXBF + 3 + 3 + read-only + + + RXBE + desc RXBE + 4 + 4 + read-only + + + RXBF + desc RXBF + 5 + 5 + read-only + + + + + ER + desc ER + 0x8 + 32 + read-write + 0x0 + 0x3 + + + TXERR + desc TXERR + 0 + 0 + read-write + + + RXERR + desc RXERR + 1 + 1 + read-write + + + + + CFGR + desc CFGR + 0xC + 32 + read-write + 0x0 + 0x3F + + + I2SSTD + desc I2SSTD + 1 + 0 + read-write + + + DATLEN + desc DATLEN + 3 + 2 + read-write + + + CHLEN + desc CHLEN + 4 + 4 + read-write + + + PCMSYNC + desc PCMSYNC + 5 + 5 + read-write + + + + + TXBUF + desc TXBUF + 0x10 + 32 + write-only + 0x0 + 0xFFFFFFFF + + + RXBUF + desc RXBUF + 0x14 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PR + desc PR + 0x18 + 32 + read-write + 0x2 + 0xFF + + + I2SDIV + desc I2SDIV + 7 + 0 + read-write + + + + + + + I2S2 + desc I2S + 0x4001E400 + + 0x0 + 0x1C + + + + I2S3 + desc I2S + 0x40022000 + + 0x0 + 0x1C + + + + I2S4 + desc I2S + 0x40022400 + + 0x0 + 0x1C + + + + ICG + desc ICG + 0x00000400 + + 0x0 + 0x20 + + + + ICG0 + desc ICG0 + 0x0 + 32 + read-only + 0xFFFFFFFF + 0x1FFF1FFF + + + SWDTAUTS + desc SWDTAUTS + 0 + 0 + read-only + + + SWDTITS + desc SWDTITS + 1 + 1 + read-only + + + SWDTPERI + desc SWDTPERI + 3 + 2 + read-only + + + SWDTCKS + desc SWDTCKS + 7 + 4 + read-only + + + SWDTWDPT + desc SWDTWDPT + 11 + 8 + read-only + + + SWDTSLPOFF + desc SWDTSLPOFF + 12 + 12 + read-only + + + WDTAUTS + desc WDTAUTS + 16 + 16 + read-only + + + WDTITS + desc WDTITS + 17 + 17 + read-only + + + WDTPERI + desc WDTPERI + 19 + 18 + read-only + + + WDTCKS + desc WDTCKS + 23 + 20 + read-only + + + WDTWDPT + desc WDTWDPT + 27 + 24 + read-only + + + WDTSLPOFF + desc WDTSLPOFF + 28 + 28 + read-only + + + + + ICG1 + desc ICG1 + 0x4 + 32 + read-only + 0xFFFFFFFF + 0xFC070101 + + + HRCFREQSEL + desc HRCFREQSEL + 0 + 0 + read-only + + + HRCSTOP + desc HRCSTOP + 8 + 8 + read-only + + + BOR_LEV + desc BOR_LEV + 17 + 16 + read-only + + + BORDIS + desc BORDIS + 18 + 18 + read-only + + + SMPCLK + desc SMPCLK + 27 + 26 + read-only + + + NMITRG + desc NMITRG + 28 + 28 + read-only + + + NMIEN + desc NMIEN + 29 + 29 + read-only + + + NFEN + desc NFEN + 30 + 30 + read-only + + + NMIICGEN + desc NMIICGEN + 31 + 31 + read-only + + + + + ICG2 + desc ICG2 + 0x8 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + ICG3 + desc ICG3 + 0xC + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + ICG4 + desc ICG4 + 0x10 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + ICG5 + desc ICG5 + 0x14 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + ICG6 + desc ICG6 + 0x18 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + ICG7 + desc ICG7 + 0x1C + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + + + INTC + desc INTC + 0x40051000 + + 0x0 + 0x2A8 + + + + NMICR + desc NMICR + 0x0 + 32 + read-write + 0x0 + 0xB1 + + + NMITRG + desc NMITRG + 0 + 0 + read-write + + + NSMPCLK + desc NSMPCLK + 5 + 4 + read-write + + + NFEN + desc NFEN + 7 + 7 + read-write + + + + + NMIENR + desc NMIENR + 0x4 + 32 + read-write + 0x0 + 0xF2F + + + NMIENR + desc NMIENR + 0 + 0 + read-write + + + SWDTENR + desc SWDTENR + 1 + 1 + read-write + + + PVD1ENR + desc PVD1ENR + 2 + 2 + read-write + + + PVD2ENR + desc PVD2ENR + 3 + 3 + read-write + + + XTALSTPENR + desc XTALSTPENR + 5 + 5 + read-write + + + REPENR + desc REPENR + 8 + 8 + read-write + + + RECCENR + desc RECCENR + 9 + 9 + read-write + + + BUSMENR + desc BUSMENR + 10 + 10 + read-write + + + WDTENR + desc WDTENR + 11 + 11 + read-write + + + + + NMIFR + desc NMIFR + 0x8 + 32 + read-write + 0x0 + 0xF2F + + + NMIFR + desc NMIFR + 0 + 0 + read-write + + + SWDTFR + desc SWDTFR + 1 + 1 + read-write + + + PVD1FR + desc PVD1FR + 2 + 2 + read-write + + + PVD2FR + desc PVD2FR + 3 + 3 + read-write + + + XTALSTPFR + desc XTALSTPFR + 5 + 5 + read-write + + + REPFR + desc REPFR + 8 + 8 + read-write + + + RECCFR + desc RECCFR + 9 + 9 + read-write + + + BUSMFR + desc BUSMFR + 10 + 10 + read-write + + + WDTFR + desc WDTFR + 11 + 11 + read-write + + + + + NMICFR + desc NMICFR + 0xC + 32 + read-write + 0x0 + 0xF2F + + + NMICFR + desc NMICFR + 0 + 0 + read-write + + + SWDTCFR + desc SWDTCFR + 1 + 1 + read-write + + + PVD1CFR + desc PVD1CFR + 2 + 2 + read-write + + + PVD2CFR + desc PVD2CFR + 3 + 3 + read-write + + + XTALSTPCFR + desc XTALSTPCFR + 5 + 5 + read-write + + + REPCFR + desc REPCFR + 8 + 8 + read-write + + + RECCCFR + desc RECCCFR + 9 + 9 + read-write + + + BUSMCFR + desc BUSMCFR + 10 + 10 + read-write + + + WDTCFR + desc WDTCFR + 11 + 11 + read-write + + + + + EIRQCR0 + desc EIRQCR0 + 0x10 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR1 + desc EIRQCR1 + 0x14 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR2 + desc EIRQCR2 + 0x18 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR3 + desc EIRQCR3 + 0x1C + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR4 + desc EIRQCR4 + 0x20 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR5 + desc EIRQCR5 + 0x24 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR6 + desc EIRQCR6 + 0x28 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR7 + desc EIRQCR7 + 0x2C + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR8 + desc EIRQCR8 + 0x30 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR9 + desc EIRQCR9 + 0x34 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR10 + desc EIRQCR10 + 0x38 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR11 + desc EIRQCR11 + 0x3C + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR12 + desc EIRQCR12 + 0x40 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR13 + desc EIRQCR13 + 0x44 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR14 + desc EIRQCR14 + 0x48 + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + EIRQCR15 + desc EIRQCR15 + 0x4C + 32 + read-write + 0x0 + 0xB3 + + + EIRQTRG + desc EIRQTRG + 1 + 0 + read-write + + + EISMPCLK + desc EISMPCLK + 5 + 4 + read-write + + + EFEN + desc EFEN + 7 + 7 + read-write + + + + + WUPEN + desc WUPEN + 0x50 + 32 + read-write + 0x0 + 0x2FFFFFF + + + EIRQWUEN + desc EIRQWUEN + 15 + 0 + read-write + + + SWDTWUEN + desc SWDTWUEN + 16 + 16 + read-write + + + PVD1WUEN + desc PVD1WUEN + 17 + 17 + read-write + + + PVD2WUEN + desc PVD2WUEN + 18 + 18 + read-write + + + CMPI0WUEN + desc CMPI0WUEN + 19 + 19 + read-write + + + WKTMWUEN + desc WKTMWUEN + 20 + 20 + read-write + + + RTCALMWUEN + desc RTCALMWUEN + 21 + 21 + read-write + + + RTCPRDWUEN + desc RTCPRDWUEN + 22 + 22 + read-write + + + TMR0WUEN + desc TMR0WUEN + 23 + 23 + read-write + + + RXWUEN + desc RXWUEN + 25 + 25 + read-write + + + + + EIRQFR + desc EIRQFR + 0x54 + 32 + read-write + 0x0 + 0xFFFF + + + EIRQFR0 + desc EIRQFR0 + 0 + 0 + read-write + + + EIRQFR1 + desc EIRQFR1 + 1 + 1 + read-write + + + EIRQFR2 + desc EIRQFR2 + 2 + 2 + read-write + + + EIRQFR3 + desc EIRQFR3 + 3 + 3 + read-write + + + EIRQFR4 + desc EIRQFR4 + 4 + 4 + read-write + + + EIRQFR5 + desc EIRQFR5 + 5 + 5 + read-write + + + EIRQFR6 + desc EIRQFR6 + 6 + 6 + read-write + + + EIRQFR7 + desc EIRQFR7 + 7 + 7 + read-write + + + EIRQFR8 + desc EIRQFR8 + 8 + 8 + read-write + + + EIRQFR9 + desc EIRQFR9 + 9 + 9 + read-write + + + EIRQFR10 + desc EIRQFR10 + 10 + 10 + read-write + + + EIRQFR11 + desc EIRQFR11 + 11 + 11 + read-write + + + EIRQFR12 + desc EIRQFR12 + 12 + 12 + read-write + + + EIRQFR13 + desc EIRQFR13 + 13 + 13 + read-write + + + EIRQFR14 + desc EIRQFR14 + 14 + 14 + read-write + + + EIRQFR15 + desc EIRQFR15 + 15 + 15 + read-write + + + + + EIRQCFR + desc EIRQCFR + 0x58 + 32 + read-write + 0x0 + 0xFFFF + + + EIRQCFR0 + desc EIRQCFR0 + 0 + 0 + read-write + + + EIRQCFR1 + desc EIRQCFR1 + 1 + 1 + read-write + + + EIRQCFR2 + desc EIRQCFR2 + 2 + 2 + read-write + + + EIRQCFR3 + desc EIRQCFR3 + 3 + 3 + read-write + + + EIRQCFR4 + desc EIRQCFR4 + 4 + 4 + read-write + + + EIRQCFR5 + desc EIRQCFR5 + 5 + 5 + read-write + + + EIRQCFR6 + desc EIRQCFR6 + 6 + 6 + read-write + + + EIRQCFR7 + desc EIRQCFR7 + 7 + 7 + read-write + + + EIRQCFR8 + desc EIRQCFR8 + 8 + 8 + read-write + + + EIRQCFR9 + desc EIRQCFR9 + 9 + 9 + read-write + + + EIRQCFR10 + desc EIRQCFR10 + 10 + 10 + read-write + + + EIRQCFR11 + desc EIRQCFR11 + 11 + 11 + read-write + + + EIRQCFR12 + desc EIRQCFR12 + 12 + 12 + read-write + + + EIRQCFR13 + desc EIRQCFR13 + 13 + 13 + read-write + + + EIRQCFR14 + desc EIRQCFR14 + 14 + 14 + read-write + + + EIRQCFR15 + desc EIRQCFR15 + 15 + 15 + read-write + + + + + SEL0 + desc SEL0 + 0x5C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL1 + desc SEL1 + 0x60 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL2 + desc SEL2 + 0x64 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL3 + desc SEL3 + 0x68 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL4 + desc SEL4 + 0x6C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL5 + desc SEL5 + 0x70 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL6 + desc SEL6 + 0x74 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL7 + desc SEL7 + 0x78 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL8 + desc SEL8 + 0x7C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL9 + desc SEL9 + 0x80 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL10 + desc SEL10 + 0x84 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL11 + desc SEL11 + 0x88 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL12 + desc SEL12 + 0x8C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL13 + desc SEL13 + 0x90 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL14 + desc SEL14 + 0x94 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL15 + desc SEL15 + 0x98 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL16 + desc SEL16 + 0x9C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL17 + desc SEL17 + 0xA0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL18 + desc SEL18 + 0xA4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL19 + desc SEL19 + 0xA8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL20 + desc SEL20 + 0xAC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL21 + desc SEL21 + 0xB0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL22 + desc SEL22 + 0xB4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL23 + desc SEL23 + 0xB8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL24 + desc SEL24 + 0xBC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL25 + desc SEL25 + 0xC0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL26 + desc SEL26 + 0xC4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL27 + desc SEL27 + 0xC8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL28 + desc SEL28 + 0xCC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL29 + desc SEL29 + 0xD0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL30 + desc SEL30 + 0xD4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL31 + desc SEL31 + 0xD8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL32 + desc SEL32 + 0xDC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL33 + desc SEL33 + 0xE0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL34 + desc SEL34 + 0xE4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL35 + desc SEL35 + 0xE8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL36 + desc SEL36 + 0xEC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL37 + desc SEL37 + 0xF0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL38 + desc SEL38 + 0xF4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL39 + desc SEL39 + 0xF8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL40 + desc SEL40 + 0xFC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL41 + desc SEL41 + 0x100 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL42 + desc SEL42 + 0x104 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL43 + desc SEL43 + 0x108 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL44 + desc SEL44 + 0x10C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL45 + desc SEL45 + 0x110 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL46 + desc SEL46 + 0x114 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL47 + desc SEL47 + 0x118 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL48 + desc SEL48 + 0x11C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL49 + desc SEL49 + 0x120 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL50 + desc SEL50 + 0x124 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL51 + desc SEL51 + 0x128 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL52 + desc SEL52 + 0x12C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL53 + desc SEL53 + 0x130 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL54 + desc SEL54 + 0x134 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL55 + desc SEL55 + 0x138 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL56 + desc SEL56 + 0x13C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL57 + desc SEL57 + 0x140 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL58 + desc SEL58 + 0x144 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL59 + desc SEL59 + 0x148 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL60 + desc SEL60 + 0x14C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL61 + desc SEL61 + 0x150 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL62 + desc SEL62 + 0x154 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL63 + desc SEL63 + 0x158 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL64 + desc SEL64 + 0x15C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL65 + desc SEL65 + 0x160 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL66 + desc SEL66 + 0x164 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL67 + desc SEL67 + 0x168 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL68 + desc SEL68 + 0x16C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL69 + desc SEL69 + 0x170 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL70 + desc SEL70 + 0x174 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL71 + desc SEL71 + 0x178 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL72 + desc SEL72 + 0x17C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL73 + desc SEL73 + 0x180 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL74 + desc SEL74 + 0x184 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL75 + desc SEL75 + 0x188 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL76 + desc SEL76 + 0x18C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL77 + desc SEL77 + 0x190 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL78 + desc SEL78 + 0x194 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL79 + desc SEL79 + 0x198 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL80 + desc SEL80 + 0x19C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL81 + desc SEL81 + 0x1A0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL82 + desc SEL82 + 0x1A4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL83 + desc SEL83 + 0x1A8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL84 + desc SEL84 + 0x1AC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL85 + desc SEL85 + 0x1B0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL86 + desc SEL86 + 0x1B4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL87 + desc SEL87 + 0x1B8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL88 + desc SEL88 + 0x1BC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL89 + desc SEL89 + 0x1C0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL90 + desc SEL90 + 0x1C4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL91 + desc SEL91 + 0x1C8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL92 + desc SEL92 + 0x1CC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL93 + desc SEL93 + 0x1D0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL94 + desc SEL94 + 0x1D4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL95 + desc SEL95 + 0x1D8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL96 + desc SEL96 + 0x1DC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL97 + desc SEL97 + 0x1E0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL98 + desc SEL98 + 0x1E4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL99 + desc SEL99 + 0x1E8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL100 + desc SEL100 + 0x1EC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL101 + desc SEL101 + 0x1F0 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL102 + desc SEL102 + 0x1F4 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL103 + desc SEL103 + 0x1F8 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL104 + desc SEL104 + 0x1FC + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL105 + desc SEL105 + 0x200 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL106 + desc SEL106 + 0x204 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL107 + desc SEL107 + 0x208 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL108 + desc SEL108 + 0x20C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL109 + desc SEL109 + 0x210 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL110 + desc SEL110 + 0x214 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL111 + desc SEL111 + 0x218 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL112 + desc SEL112 + 0x21C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL113 + desc SEL113 + 0x220 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL114 + desc SEL114 + 0x224 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL115 + desc SEL115 + 0x228 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL116 + desc SEL116 + 0x22C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL117 + desc SEL117 + 0x230 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL118 + desc SEL118 + 0x234 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL119 + desc SEL119 + 0x238 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL120 + desc SEL120 + 0x23C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL121 + desc SEL121 + 0x240 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL122 + desc SEL122 + 0x244 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL123 + desc SEL123 + 0x248 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL124 + desc SEL124 + 0x24C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL125 + desc SEL125 + 0x250 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL126 + desc SEL126 + 0x254 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL127 + desc SEL127 + 0x258 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + VSSEL128 + desc VSSEL128 + 0x25C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL129 + desc VSSEL129 + 0x260 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL130 + desc VSSEL130 + 0x264 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL131 + desc VSSEL131 + 0x268 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL132 + desc VSSEL132 + 0x26C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL133 + desc VSSEL133 + 0x270 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL134 + desc VSSEL134 + 0x274 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL135 + desc VSSEL135 + 0x278 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL136 + desc VSSEL136 + 0x27C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL137 + desc VSSEL137 + 0x280 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL138 + desc VSSEL138 + 0x284 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL139 + desc VSSEL139 + 0x288 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL140 + desc VSSEL140 + 0x28C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL141 + desc VSSEL141 + 0x290 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL142 + desc VSSEL142 + 0x294 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL143 + desc VSSEL143 + 0x298 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 11 + 11 + read-write + + + VSEL12 + desc VSEL12 + 12 + 12 + read-write + + + VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + SWIER + desc SWIER + 0x29C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + SWIE0 + desc SWIE0 + 0 + 0 + read-write + + + SWIE1 + desc SWIE1 + 1 + 1 + read-write + + + SWIE2 + desc SWIE2 + 2 + 2 + read-write + + + SWIE3 + desc SWIE3 + 3 + 3 + read-write + + + SWIE4 + desc SWIE4 + 4 + 4 + read-write + + + SWIE5 + desc SWIE5 + 5 + 5 + read-write + + + SWIE6 + desc SWIE6 + 6 + 6 + read-write + + + SWIE7 + desc SWIE7 + 7 + 7 + read-write + + + SWIE8 + desc SWIE8 + 8 + 8 + read-write + + + SWIE9 + desc SWIE9 + 9 + 9 + read-write + + + SWIE10 + desc SWIE10 + 10 + 10 + read-write + + + SWIE11 + desc SWIE11 + 11 + 11 + read-write + + + SWIE12 + desc SWIE12 + 12 + 12 + read-write + + + SWIE13 + desc SWIE13 + 13 + 13 + read-write + + + SWIE14 + desc SWIE14 + 14 + 14 + read-write + + + SWIE15 + desc SWIE15 + 15 + 15 + read-write + + + SWIE16 + desc SWIE16 + 16 + 16 + read-write + + + SWIE17 + desc SWIE17 + 17 + 17 + read-write + + + SWIE18 + desc SWIE18 + 18 + 18 + read-write + + + SWIE19 + desc SWIE19 + 19 + 19 + read-write + + + SWIE20 + desc SWIE20 + 20 + 20 + read-write + + + SWIE21 + desc SWIE21 + 21 + 21 + read-write + + + SWIE22 + desc SWIE22 + 22 + 22 + read-write + + + SWIE23 + desc SWIE23 + 23 + 23 + read-write + + + SWIE24 + desc SWIE24 + 24 + 24 + read-write + + + SWIE25 + desc SWIE25 + 25 + 25 + read-write + + + SWIE26 + desc SWIE26 + 26 + 26 + read-write + + + SWIE27 + desc SWIE27 + 27 + 27 + read-write + + + SWIE28 + desc SWIE28 + 28 + 28 + read-write + + + SWIE29 + desc SWIE29 + 29 + 29 + read-write + + + SWIE30 + desc SWIE30 + 30 + 30 + read-write + + + SWIE31 + desc SWIE31 + 31 + 31 + read-write + + + + + EVTER + desc EVTER + 0x2A0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + EVTE0 + desc EVTE0 + 0 + 0 + read-write + + + EVTE1 + desc EVTE1 + 1 + 1 + read-write + + + EVTE2 + desc EVTE2 + 2 + 2 + read-write + + + EVTE3 + desc EVTE3 + 3 + 3 + read-write + + + EVTE4 + desc EVTE4 + 4 + 4 + read-write + + + EVTE5 + desc EVTE5 + 5 + 5 + read-write + + + EVTE6 + desc EVTE6 + 6 + 6 + read-write + + + EVTE7 + desc EVTE7 + 7 + 7 + read-write + + + EVTE8 + desc EVTE8 + 8 + 8 + read-write + + + EVTE9 + desc EVTE9 + 9 + 9 + read-write + + + EVTE10 + desc EVTE10 + 10 + 10 + read-write + + + EVTE11 + desc EVTE11 + 11 + 11 + read-write + + + EVTE12 + desc EVTE12 + 12 + 12 + read-write + + + EVTE13 + desc EVTE13 + 13 + 13 + read-write + + + EVTE14 + desc EVTE14 + 14 + 14 + read-write + + + EVTE15 + desc EVTE15 + 15 + 15 + read-write + + + EVTE16 + desc EVTE16 + 16 + 16 + read-write + + + EVTE17 + desc EVTE17 + 17 + 17 + read-write + + + EVTE18 + desc EVTE18 + 18 + 18 + read-write + + + EVTE19 + desc EVTE19 + 19 + 19 + read-write + + + EVTE20 + desc EVTE20 + 20 + 20 + read-write + + + EVTE21 + desc EVTE21 + 21 + 21 + read-write + + + EVTE22 + desc EVTE22 + 22 + 22 + read-write + + + EVTE23 + desc EVTE23 + 23 + 23 + read-write + + + EVTE24 + desc EVTE24 + 24 + 24 + read-write + + + EVTE25 + desc EVTE25 + 25 + 25 + read-write + + + EVTE26 + desc EVTE26 + 26 + 26 + read-write + + + EVTE27 + desc EVTE27 + 27 + 27 + read-write + + + EVTE28 + desc EVTE28 + 28 + 28 + read-write + + + EVTE29 + desc EVTE29 + 29 + 29 + read-write + + + EVTE30 + desc EVTE30 + 30 + 30 + read-write + + + EVTE31 + desc EVTE31 + 31 + 31 + read-write + + + + + IER + desc IER + 0x2A4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + IER0 + desc IER0 + 0 + 0 + read-write + + + IER1 + desc IER1 + 1 + 1 + read-write + + + IER2 + desc IER2 + 2 + 2 + read-write + + + IER3 + desc IER3 + 3 + 3 + read-write + + + IER4 + desc IER4 + 4 + 4 + read-write + + + IER5 + desc IER5 + 5 + 5 + read-write + + + IER6 + desc IER6 + 6 + 6 + read-write + + + IER7 + desc IER7 + 7 + 7 + read-write + + + IER8 + desc IER8 + 8 + 8 + read-write + + + IER9 + desc IER9 + 9 + 9 + read-write + + + IER10 + desc IER10 + 10 + 10 + read-write + + + IER11 + desc IER11 + 11 + 11 + read-write + + + IER12 + desc IER12 + 12 + 12 + read-write + + + IER13 + desc IER13 + 13 + 13 + read-write + + + IER14 + desc IER14 + 14 + 14 + read-write + + + IER15 + desc IER15 + 15 + 15 + read-write + + + IER16 + desc IER16 + 16 + 16 + read-write + + + IER17 + desc IER17 + 17 + 17 + read-write + + + IER18 + desc IER18 + 18 + 18 + read-write + + + IER19 + desc IER19 + 19 + 19 + read-write + + + IER20 + desc IER20 + 20 + 20 + read-write + + + IER21 + desc IER21 + 21 + 21 + read-write + + + IER22 + desc IER22 + 22 + 22 + read-write + + + IER23 + desc IER23 + 23 + 23 + read-write + + + IER24 + desc IER24 + 24 + 24 + read-write + + + IER25 + desc IER25 + 25 + 25 + read-write + + + IER26 + desc IER26 + 26 + 26 + read-write + + + IER27 + desc IER27 + 27 + 27 + read-write + + + IER28 + desc IER28 + 28 + 28 + read-write + + + IER29 + desc IER29 + 29 + 29 + read-write + + + IER30 + desc IER30 + 30 + 30 + read-write + + + IER31 + desc IER31 + 31 + 31 + read-write + + + + + + + KEYSCAN + desc KEYSCAN + 0x40050C00 + + 0x0 + 0xC + + + + SCR + desc SCR + 0x0 + 32 + read-write + 0x0 + 0xFF37FFFF + + + KEYINSEL + desc KEYINSEL + 15 + 0 + read-write + + + KEYOUTSEL + desc KEYOUTSEL + 18 + 16 + read-write + + + CKSEL + desc CKSEL + 21 + 20 + read-write + + + T_LLEVEL + desc T_LLEVEL + 28 + 24 + read-write + + + T_HIZ + desc T_HIZ + 31 + 29 + read-write + + + + + SER + desc SER + 0x4 + 32 + read-write + 0x0 + 0x1 + + + SEN + desc SEN + 0 + 0 + read-write + + + + + SSR + desc SSR + 0x8 + 32 + read-write + 0x0 + 0x7 + + + INDEX + desc INDEX + 2 + 0 + read-write + + + + + + + MPU + desc MPU + 0x40050000 + + 0x0 + 0x4020 + + + + RGD0 + desc RGD0 + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD1 + desc RGD1 + 0x4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD2 + desc RGD2 + 0x8 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD3 + desc RGD3 + 0xC + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD4 + desc RGD4 + 0x10 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD5 + desc RGD5 + 0x14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD6 + desc RGD6 + 0x18 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD7 + desc RGD7 + 0x1C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD8 + desc RGD8 + 0x20 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD9 + desc RGD9 + 0x24 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD10 + desc RGD10 + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD11 + desc RGD11 + 0x2C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD12 + desc RGD12 + 0x30 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD13 + desc RGD13 + 0x34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD14 + desc RGD14 + 0x38 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGD15 + desc RGD15 + 0x3C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + MPURGSIZE + desc MPURGSIZE + 4 + 0 + read-write + + + MPURGADDR + desc MPURGADDR + 31 + 5 + read-write + + + + + RGCR0 + desc RGCR0 + 0x40 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR1 + desc RGCR1 + 0x44 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR2 + desc RGCR2 + 0x48 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR3 + desc RGCR3 + 0x4C + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR4 + desc RGCR4 + 0x50 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR5 + desc RGCR5 + 0x54 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR6 + desc RGCR6 + 0x58 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR7 + desc RGCR7 + 0x5C + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR8 + desc RGCR8 + 0x60 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR9 + desc RGCR9 + 0x64 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR10 + desc RGCR10 + 0x68 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR11 + desc RGCR11 + 0x6C + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR12 + desc RGCR12 + 0x70 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR13 + desc RGCR13 + 0x74 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR14 + desc RGCR14 + 0x78 + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + RGCR15 + desc RGCR15 + 0x7C + 32 + read-write + 0x0 + 0x838383 + + + S2RGRP + desc S2RGRP + 0 + 0 + read-write + + + S2RGWP + desc S2RGWP + 1 + 1 + read-write + + + S2RGE + desc S2RGE + 7 + 7 + read-write + + + S1RGRP + desc S1RGRP + 8 + 8 + read-write + + + S1RGWP + desc S1RGWP + 9 + 9 + read-write + + + S1RGE + desc S1RGE + 15 + 15 + read-write + + + FRGRP + desc FRGRP + 16 + 16 + read-write + + + FRGWP + desc FRGWP + 17 + 17 + read-write + + + FRGE + desc FRGE + 23 + 23 + read-write + + + + + CR + desc CR + 0x80 + 32 + read-write + 0x0 + 0x8F8F8F + + + SMPU2BRP + desc SMPU2BRP + 0 + 0 + read-write + + + SMPU2BWP + desc SMPU2BWP + 1 + 1 + read-write + + + SMPU2ACT + desc SMPU2ACT + 3 + 2 + read-write + + + SMPU2E + desc SMPU2E + 7 + 7 + read-write + + + SMPU1BRP + desc SMPU1BRP + 8 + 8 + read-write + + + SMPU1BWP + desc SMPU1BWP + 9 + 9 + read-write + + + SMPU1ACT + desc SMPU1ACT + 11 + 10 + read-write + + + SMPU1E + desc SMPU1E + 15 + 15 + read-write + + + FMPUBRP + desc FMPUBRP + 16 + 16 + read-write + + + FMPUBWP + desc FMPUBWP + 17 + 17 + read-write + + + FMPUACT + desc FMPUACT + 19 + 18 + read-write + + + FMPUE + desc FMPUE + 23 + 23 + read-write + + + + + SR + desc SR + 0x84 + 32 + read-only + 0x0 + 0x10101 + + + SMPU2EAF + desc SMPU2EAF + 0 + 0 + read-only + + + SMPU1EAF + desc SMPU1EAF + 8 + 8 + read-only + + + FMPUEAF + desc FMPUEAF + 16 + 16 + read-only + + + + + ECLR + desc ECLR + 0x88 + 32 + write-only + 0x0 + 0x10101 + + + SMPU2ECLR + desc SMPU2ECLR + 0 + 0 + write-only + + + SMPU1ECLR + desc SMPU1ECLR + 8 + 8 + write-only + + + FMPUECLR + desc FMPUECLR + 16 + 16 + write-only + + + + + WP + desc WP + 0x8C + 32 + read-write + 0x0 + 0xFFFF + + + MPUWE + desc MPUWE + 0 + 0 + read-write + + + WKEY + desc WKEY + 15 + 1 + write-only + + + + + IPPR + desc IPPR + 0x401C + 32 + read-write + 0x0 + 0xBFFFF3FF + + + AESRDP + desc AESRDP + 0 + 0 + read-write + + + AESWRP + desc AESWRP + 1 + 1 + read-write + + + HASHRDP + desc HASHRDP + 2 + 2 + read-write + + + HASHWRP + desc HASHWRP + 3 + 3 + read-write + + + TRNGRDP + desc TRNGRDP + 4 + 4 + read-write + + + TRNGWRP + desc TRNGWRP + 5 + 5 + read-write + + + CRCRDP + desc CRCRDP + 6 + 6 + read-write + + + CRCWRP + desc CRCWRP + 7 + 7 + read-write + + + EFMRDP + desc EFMRDP + 8 + 8 + read-write + + + EFMWRP + desc EFMWRP + 9 + 9 + read-write + + + WDTRDP + desc WDTRDP + 12 + 12 + read-write + + + WDTWRP + desc WDTWRP + 13 + 13 + read-write + + + SWDTRDP + desc SWDTRDP + 14 + 14 + read-write + + + SWDTWRP + desc SWDTWRP + 15 + 15 + read-write + + + BKSRAMRDP + desc BKSRAMRDP + 16 + 16 + read-write + + + BKSRAMWRP + desc BKSRAMWRP + 17 + 17 + read-write + + + RTCRDP + desc RTCRDP + 18 + 18 + read-write + + + RTCWRP + desc RTCWRP + 19 + 19 + read-write + + + DMPURDP + desc DMPURDP + 20 + 20 + read-write + + + DMPUWRP + desc DMPUWRP + 21 + 21 + read-write + + + SRAMCRDP + desc SRAMCRDP + 22 + 22 + read-write + + + SRAMCWRP + desc SRAMCWRP + 23 + 23 + read-write + + + INTCRDP + desc INTCRDP + 24 + 24 + read-write + + + INTCWRP + desc INTCWRP + 25 + 25 + read-write + + + SYSCRDP + desc SYSCRDP + 26 + 26 + read-write + + + SYSCWRP + desc SYSCWRP + 27 + 27 + read-write + + + MSTPRDP + desc MSTPRDP + 28 + 28 + read-write + + + MSTPWRP + desc MSTPWRP + 29 + 29 + read-write + + + BUSERRE + desc BUSERRE + 31 + 31 + read-write + + + + + + + OTS + desc OTS + 0x4004A400 + + 0x0 + 0xC + + + + CTL + desc CTL + 0x0 + 16 + read-write + 0x0 + 0xF + + + OTSST + desc OTSST + 0 + 0 + read-write + + + OTSCK + desc OTSCK + 1 + 1 + read-write + + + OTSIE + desc OTSIE + 2 + 2 + read-write + + + TSSTP + desc TSSTP + 3 + 3 + read-write + + + + + DR1 + desc DR1 + 0x2 + 16 + read-write + 0x0 + 0xFFFF + + + DR2 + desc DR2 + 0x4 + 16 + read-write + 0x0 + 0xFFFF + + + ECR + desc ECR + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + LPR + desc LPR + 0x8 + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + TSOFS + desc TSOFS + 7 + 0 + read-only + + + TSSLP + desc TSSLP + 31 + 8 + read-only + + + + + + + PERIC + desc PERIC + 0x40055400 + + 0x0 + 0x8 + + + + USBFS_SYCTLREG + desc USBFS_SYCTLREG + 0x0 + 32 + read-write + 0x0 + 0x3 + + + DFB + desc DFB + 0 + 0 + read-write + + + SOFEN + desc SOFEN + 1 + 1 + read-write + + + + + SDIOC_SYCTLREG + desc SDIOC_SYCTLREG + 0x4 + 32 + read-write + 0x0 + 0xA + + + SELMMC1 + desc SELMMC1 + 1 + 1 + read-write + + + SELMMC2 + desc SELMMC2 + 3 + 3 + read-write + + + + + + + PWC + desc PWC + 0x40048000 + + 0x0 + 0xC42C + + + + FCG0 + desc FCG0 + 0x0 + 32 + read-write + 0xFFFFFAEE + 0x8FF3C511 + + + SRAMH + desc SRAMH + 0 + 0 + read-write + + + SRAM12 + desc SRAM12 + 4 + 4 + read-write + + + SRAM3 + desc SRAM3 + 8 + 8 + read-write + + + SRAMRET + desc SRAMRET + 10 + 10 + read-write + + + DMA1 + desc DMA1 + 14 + 14 + read-write + + + DMA2 + desc DMA2 + 15 + 15 + read-write + + + FCM + desc FCM + 16 + 16 + read-write + + + AOS + desc AOS + 17 + 17 + read-write + + + AES + desc AES + 20 + 20 + read-write + + + HASH + desc HASH + 21 + 21 + read-write + + + TRNG + desc TRNG + 22 + 22 + read-write + + + CRC + desc CRC + 23 + 23 + read-write + + + DCU1 + desc DCU1 + 24 + 24 + read-write + + + DCU2 + desc DCU2 + 25 + 25 + read-write + + + DCU3 + desc DCU3 + 26 + 26 + read-write + + + DCU4 + desc DCU4 + 27 + 27 + read-write + + + KEY + desc KEY + 31 + 31 + read-write + + + + + FCG1 + desc FCG1 + 0x4 + 32 + read-write + 0xFFFFFFFF + 0xF0FFD79 + + + CAN + desc CAN + 0 + 0 + read-write + + + QSPI + desc QSPI + 3 + 3 + read-write + + + I2C1 + desc I2C1 + 4 + 4 + read-write + + + I2C2 + desc I2C2 + 5 + 5 + read-write + + + I2C3 + desc I2C3 + 6 + 6 + read-write + + + USBFS + desc USBFS + 8 + 8 + read-write + + + SDIOC1 + desc SDIOC1 + 10 + 10 + read-write + + + SDIOC2 + desc SDIOC2 + 11 + 11 + read-write + + + I2S1 + desc I2S1 + 12 + 12 + read-write + + + I2S2 + desc I2S2 + 13 + 13 + read-write + + + I2S3 + desc I2S3 + 14 + 14 + read-write + + + I2S4 + desc I2S4 + 15 + 15 + read-write + + + SPI1 + desc SPI1 + 16 + 16 + read-write + + + SPI2 + desc SPI2 + 17 + 17 + read-write + + + SPI3 + desc SPI3 + 18 + 18 + read-write + + + SPI4 + desc SPI4 + 19 + 19 + read-write + + + USART1 + desc USART1 + 24 + 24 + read-write + + + USART2 + desc USART2 + 25 + 25 + read-write + + + USART3 + desc USART3 + 26 + 26 + read-write + + + USART4 + desc USART4 + 27 + 27 + read-write + + + + + FCG2 + desc FCG2 + 0x8 + 32 + read-write + 0xFFFFFFFF + 0x787FF + + + TIMER0_1 + desc TIMER0_1 + 0 + 0 + read-write + + + TIMER0_2 + desc TIMER0_2 + 1 + 1 + read-write + + + TIMERA_1 + desc TIMERA_1 + 2 + 2 + read-write + + + TIMERA_2 + desc TIMERA_2 + 3 + 3 + read-write + + + TIMERA_3 + desc TIMERA_3 + 4 + 4 + read-write + + + TIMERA_4 + desc TIMERA_4 + 5 + 5 + read-write + + + TIMERA_5 + desc TIMERA_5 + 6 + 6 + read-write + + + TIMERA_6 + desc TIMERA_6 + 7 + 7 + read-write + + + TIMER4_1 + desc TIMER4_1 + 8 + 8 + read-write + + + TIMER4_2 + desc TIMER4_2 + 9 + 9 + read-write + + + TIMER4_3 + desc TIMER4_3 + 10 + 10 + read-write + + + EMB + desc EMB + 15 + 15 + read-write + + + TIMER6_1 + desc TIMER6_1 + 16 + 16 + read-write + + + TIMER6_2 + desc TIMER6_2 + 17 + 17 + read-write + + + TIMER6_3 + desc TIMER6_3 + 18 + 18 + read-write + + + + + FCG3 + desc FCG3 + 0xC + 32 + read-write + 0xFFFFFFFF + 0x1103 + + + ADC1 + desc ADC1 + 0 + 0 + read-write + + + ADC2 + desc ADC2 + 1 + 1 + read-write + + + CMP + desc CMP + 8 + 8 + read-write + + + OTS + desc OTS + 12 + 12 + read-write + + + + + FCG0PC + desc FCG0PC + 0x10 + 32 + read-write + 0x0 + 0xFFFF0001 + + + PRT0 + desc PRT0 + 0 + 0 + read-write + + + FCG0PCWE + desc FCG0PCWE + 31 + 16 + write-only + + + + + WKTCR + desc WKTCR + 0x4400 + 16 + read-write + 0x0 + 0xFFFF + + + WKTMCMP + desc WKTMCMP + 11 + 0 + read-write + + + WKOVF + desc WKOVF + 12 + 12 + read-write + + + WKCKS + desc WKCKS + 14 + 13 + read-write + + + WKTCE + desc WKTCE + 15 + 15 + read-write + + + + + STPMCR + desc STPMCR + 0xC00C + 16 + read-write + 0x4000 + 0x8003 + + + FLNWT + desc FLNWT + 0 + 0 + read-write + + + CKSMRC + desc CKSMRC + 1 + 1 + read-write + + + STOP + desc STOP + 15 + 15 + read-write + + + + + RAMPC0 + desc RAMPC0 + 0xC014 + 32 + read-write + 0x0 + 0x1FF + + + RAMPDC0 + desc RAMPDC0 + 0 + 0 + read-write + + + RAMPDC1 + desc RAMPDC1 + 1 + 1 + read-write + + + RAMPDC2 + desc RAMPDC2 + 2 + 2 + read-write + + + RAMPDC3 + desc RAMPDC3 + 3 + 3 + read-write + + + RAMPDC4 + desc RAMPDC4 + 4 + 4 + read-write + + + RAMPDC5 + desc RAMPDC5 + 5 + 5 + read-write + + + RAMPDC6 + desc RAMPDC6 + 6 + 6 + read-write + + + RAMPDC7 + desc RAMPDC7 + 7 + 7 + read-write + + + RAMPDC8 + desc RAMPDC8 + 8 + 8 + read-write + + + + + RAMOPM + desc RAMOPM + 0xC018 + 16 + read-write + 0x8043 + 0xFFFF + + + PVDICR + desc PVDICR + 0xC0E0 + 8 + read-write + 0x0 + 0x11 + + + PVD1NMIS + desc PVD1NMIS + 0 + 0 + read-write + + + PVD2NMIS + desc PVD2NMIS + 4 + 4 + read-write + + + + + PVDDSR + desc PVDDSR + 0xC0E1 + 8 + read-write + 0x11 + 0x33 + + + PVD1MON + desc PVD1MON + 0 + 0 + read-write + + + PVD1DETFLG + desc PVD1DETFLG + 1 + 1 + read-write + + + PVD2MON + desc PVD2MON + 4 + 4 + read-write + + + PVD2DETFLG + desc PVD2DETFLG + 5 + 5 + read-write + + + + + FPRC + desc FPRC + 0xC3FE + 16 + read-write + 0x0 + 0xFF0F + + + FPRCB0 + desc FPRCB0 + 0 + 0 + read-write + + + FPRCB1 + desc FPRCB1 + 1 + 1 + read-write + + + FPRCB2 + desc FPRCB2 + 2 + 2 + read-write + + + FPRCB3 + desc FPRCB3 + 3 + 3 + read-write + + + FPRCWE + desc FPRCWE + 15 + 8 + read-write + + + + + PWRC0 + desc PWRC0 + 0xC400 + 8 + read-write + 0x0 + 0xBF + + + PDMDS + desc PDMDS + 1 + 0 + read-write + + + VVDRSD + desc VVDRSD + 2 + 2 + read-write + + + RETRAMSD + desc RETRAMSD + 3 + 3 + read-write + + + IORTN + desc IORTN + 5 + 4 + read-write + + + PWDN + desc PWDN + 7 + 7 + read-write + + + + + PWRC1 + desc PWRC1 + 0xC401 + 8 + read-write + 0x0 + 0xC3 + + + VPLLSD + desc VPLLSD + 0 + 0 + read-write + + + VHRCSD + desc VHRCSD + 1 + 1 + read-write + + + STPDAS + desc STPDAS + 7 + 6 + read-write + + + + + PWRC2 + desc PWRC2 + 0xC402 + 8 + read-write + 0xFF + 0x3F + + + DDAS + desc DDAS + 3 + 0 + read-write + + + DVS + desc DVS + 5 + 4 + read-write + + + + + PWRC3 + desc PWRC3 + 0xC403 + 8 + read-write + 0x7 + 0x4 + + + PDTS + desc PDTS + 2 + 2 + read-write + + + + + PDWKE0 + desc PDWKE0 + 0xC404 + 8 + read-write + 0x0 + 0xFF + + + WKE00 + desc WKE00 + 0 + 0 + read-write + + + WKE01 + desc WKE01 + 1 + 1 + read-write + + + WKE02 + desc WKE02 + 2 + 2 + read-write + + + WKE03 + desc WKE03 + 3 + 3 + read-write + + + WKE10 + desc WKE10 + 4 + 4 + read-write + + + WKE11 + desc WKE11 + 5 + 5 + read-write + + + WKE12 + desc WKE12 + 6 + 6 + read-write + + + WKE13 + desc WKE13 + 7 + 7 + read-write + + + + + PDWKE1 + desc PDWKE1 + 0xC405 + 8 + read-write + 0x0 + 0xFF + + + WKE20 + desc WKE20 + 0 + 0 + read-write + + + WKE21 + desc WKE21 + 1 + 1 + read-write + + + WKE22 + desc WKE22 + 2 + 2 + read-write + + + WKE23 + desc WKE23 + 3 + 3 + read-write + + + WKE30 + desc WKE30 + 4 + 4 + read-write + + + WKE31 + desc WKE31 + 5 + 5 + read-write + + + WKE32 + desc WKE32 + 6 + 6 + read-write + + + WKE33 + desc WKE33 + 7 + 7 + read-write + + + + + PDWKE2 + desc PDWKE2 + 0xC406 + 8 + read-write + 0x0 + 0xB7 + + + VD1WKE + desc VD1WKE + 0 + 0 + read-write + + + VD2WKE + desc VD2WKE + 1 + 1 + read-write + + + NMIWKE + desc NMIWKE + 2 + 2 + read-write + + + RTCPRDWKE + desc RTCPRDWKE + 4 + 4 + read-write + + + RTCALMWKE + desc RTCALMWKE + 5 + 5 + read-write + + + WKTMWKE + desc WKTMWKE + 7 + 7 + read-write + + + + + PDWKES + desc PDWKES + 0xC407 + 8 + read-write + 0x0 + 0x7F + + + WK0EGS + desc WK0EGS + 0 + 0 + read-write + + + WK1EGS + desc WK1EGS + 1 + 1 + read-write + + + WK2EGS + desc WK2EGS + 2 + 2 + read-write + + + WK3EGS + desc WK3EGS + 3 + 3 + read-write + + + VD1EGS + desc VD1EGS + 4 + 4 + read-write + + + VD2EGS + desc VD2EGS + 5 + 5 + read-write + + + NMIEGS + desc NMIEGS + 6 + 6 + read-write + + + + + PDWKF0 + desc PDWKF0 + 0xC408 + 8 + read-write + 0x0 + 0x7F + + + PTWK0F + desc PTWK0F + 0 + 0 + read-write + + + PTWK1F + desc PTWK1F + 1 + 1 + read-write + + + PTWK2F + desc PTWK2F + 2 + 2 + read-write + + + PTWK3F + desc PTWK3F + 3 + 3 + read-write + + + VD1WKF + desc VD1WKF + 4 + 4 + read-write + + + VD2WKF + desc VD2WKF + 5 + 5 + read-write + + + NMIWKF + desc NMIWKF + 6 + 6 + read-write + + + + + PDWKF1 + desc PDWKF1 + 0xC409 + 8 + read-write + 0x0 + 0xB8 + + + RTCPRDWKF + desc RTCPRDWKF + 4 + 4 + read-write + + + RTCALMWKF + desc RTCALMWKF + 5 + 5 + read-write + + + WKTMWKF + desc WKTMWKF + 7 + 7 + read-write + + + + + PWCMR + desc PWCMR + 0xC40A + 8 + read-write + 0x0 + 0x80 + + + ADBUFE + desc ADBUFE + 7 + 7 + read-write + + + + + MDSWCR + desc MDSWCR + 0xC40F + 8 + read-write + 0x0 + 0xFF + + + PVDCR0 + desc PVDCR0 + 0xC412 + 8 + read-write + 0x0 + 0x61 + + + EXVCCINEN + desc EXVCCINEN + 0 + 0 + read-write + + + PVD1EN + desc PVD1EN + 5 + 5 + read-write + + + PVD2EN + desc PVD2EN + 6 + 6 + read-write + + + + + PVDCR1 + desc PVDCR1 + 0xC413 + 8 + read-write + 0x0 + 0x77 + + + PVD1IRE + desc PVD1IRE + 0 + 0 + read-write + + + PVD1IRS + desc PVD1IRS + 1 + 1 + read-write + + + PVD1CMPOE + desc PVD1CMPOE + 2 + 2 + read-write + + + PVD2IRE + desc PVD2IRE + 4 + 4 + read-write + + + PVD2IRS + desc PVD2IRS + 5 + 5 + read-write + + + PVD2CMPOE + desc PVD2CMPOE + 6 + 6 + read-write + + + + + PVDFCR + desc PVDFCR + 0xC414 + 8 + read-write + 0x11 + 0x77 + + + PVD1NFDIS + desc PVD1NFDIS + 0 + 0 + read-write + + + PVD1NFCKS + desc PVD1NFCKS + 2 + 1 + read-write + + + PVD2NFDIS + desc PVD2NFDIS + 4 + 4 + read-write + + + PVD2NFCKS + desc PVD2NFCKS + 6 + 5 + read-write + + + + + PVDLCR + desc PVDLCR + 0xC415 + 8 + read-write + 0x0 + 0x77 + + + PVD1LVL + desc PVD1LVL + 2 + 0 + read-write + + + PVD2LVL + desc PVD2LVL + 6 + 4 + read-write + + + + + XTAL32CS + desc XTAL32CS + 0xC42B + 8 + read-write + 0x2 + 0x80 + + + CSDIS + desc CSDIS + 7 + 7 + read-write + + + + + + + QSPI + desc QSPI + 0x9C000000 + + 0x0 + 0x808 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x3F0000 + 0x3F3FFF + + + MDSEL + desc MDSEL + 2 + 0 + read-write + + + PFE + desc PFE + 3 + 3 + read-write + + + PFSAE + desc PFSAE + 4 + 4 + read-write + + + DCOME + desc DCOME + 5 + 5 + read-write + + + XIPE + desc XIPE + 6 + 6 + read-write + + + SPIMD3 + desc SPIMD3 + 7 + 7 + read-write + + + IPRSL + desc IPRSL + 9 + 8 + read-write + + + APRSL + desc APRSL + 11 + 10 + read-write + + + DPRSL + desc DPRSL + 13 + 12 + read-write + + + DIV + desc DIV + 21 + 16 + read-write + + + + + CSCR + desc CSCR + 0x4 + 32 + read-write + 0xF + 0x3F + + + SSHW + desc SSHW + 3 + 0 + read-write + + + SSNW + desc SSNW + 5 + 4 + read-write + + + + + FCR + desc FCR + 0x8 + 32 + read-write + 0x80B3 + 0x8F77 + + + AWSL + desc AWSL + 1 + 0 + read-write + + + FOUR_BIC + desc FOUR_BIC + 2 + 2 + read-write + + + SSNHD + desc SSNHD + 4 + 4 + read-write + + + SSNLD + desc SSNLD + 5 + 5 + read-write + + + WPOL + desc WPOL + 6 + 6 + read-write + + + DMCYCN + desc DMCYCN + 11 + 8 + read-write + + + DUTY + desc DUTY + 15 + 15 + read-write + + + + + SR + desc SR + 0xC + 32 + read-write + 0x8000 + 0xDFC1 + + + BUSY + desc BUSY + 0 + 0 + read-write + + + XIPF + desc XIPF + 6 + 6 + read-write + + + RAER + desc RAER + 7 + 7 + read-write + + + PFNUM + desc PFNUM + 12 + 8 + read-write + + + PFFUL + desc PFFUL + 14 + 14 + read-write + + + PFAN + desc PFAN + 15 + 15 + read-write + + + + + DCOM + desc DCOM + 0x10 + 32 + read-write + 0x0 + 0xFF + + + DCOM + desc DCOM + 7 + 0 + read-write + + + + + CCMD + desc CCMD + 0x14 + 32 + read-write + 0x0 + 0xFF + + + RIC + desc RIC + 7 + 0 + read-write + + + + + XCMD + desc XCMD + 0x18 + 32 + read-write + 0xFF + 0xFF + + + XIPMC + desc XIPMC + 7 + 0 + read-write + + + + + SR2 + desc SR2 + 0x24 + 32 + write-only + 0x0 + 0x80 + + + RAERCLR + desc RAERCLR + 7 + 7 + write-only + + + + + EXAR + desc EXAR + 0x804 + 32 + read-write + 0x0 + 0xFC000000 + + + EXADR + desc EXADR + 31 + 26 + read-write + + + + + + + RMU + desc RMU + 0x400540C0 + + 0x0 + 0x2 + + + + RSTF0 + desc RSTF0 + 0x0 + 16 + read-write + 0x2 + 0xFFFF + + + PORF + desc PORF + 0 + 0 + read-write + + + PINRF + desc PINRF + 1 + 1 + read-write + + + BORF + desc BORF + 2 + 2 + read-write + + + PVD1RF + desc PVD1RF + 3 + 3 + read-write + + + PVD2RF + desc PVD2RF + 4 + 4 + read-write + + + WDRF + desc WDRF + 5 + 5 + read-write + + + SWDRF + desc SWDRF + 6 + 6 + read-write + + + PDRF + desc PDRF + 7 + 7 + read-write + + + SWRF + desc SWRF + 8 + 8 + read-write + + + MPUERF + desc MPUERF + 9 + 9 + read-write + + + RAPERF + desc RAPERF + 10 + 10 + read-write + + + RAECRF + desc RAECRF + 11 + 11 + read-write + + + CKFERF + desc CKFERF + 12 + 12 + read-write + + + XTALERF + desc XTALERF + 13 + 13 + read-write + + + MULTIRF + desc MULTIRF + 14 + 14 + read-write + + + CLRF + desc CLRF + 15 + 15 + read-write + + + + + + + RTC + desc RTC + 0x4004C000 + + 0x0 + 0x40 + + + + CR0 + desc CR0 + 0x0 + 8 + read-write + 0x0 + 0x1 + + + RESET + desc RESET + 0 + 0 + read-write + + + + + CR1 + desc CR1 + 0x4 + 8 + read-write + 0x0 + 0xFF + + + PRDS + desc PRDS + 2 + 0 + read-write + + + AMPM + desc AMPM + 3 + 3 + read-write + + + ALMFCLR + desc ALMFCLR + 4 + 4 + read-write + + + ONEHZOE + desc ONEHZOE + 5 + 5 + read-write + + + ONEHZSEL + desc ONEHZSEL + 6 + 6 + read-write + + + START + desc START + 7 + 7 + read-write + + + + + CR2 + desc CR2 + 0x8 + 8 + read-write + 0x0 + 0xEB + + + RWREQ + desc RWREQ + 0 + 0 + read-write + + + RWEN + desc RWEN + 1 + 1 + read-write + + + ALMF + desc ALMF + 3 + 3 + read-write + + + PRDIE + desc PRDIE + 5 + 5 + read-write + + + ALMIE + desc ALMIE + 6 + 6 + read-write + + + ALME + desc ALME + 7 + 7 + read-write + + + + + CR3 + desc CR3 + 0xC + 8 + read-write + 0x0 + 0x90 + + + LRCEN + desc LRCEN + 4 + 4 + read-write + + + RCKSEL + desc RCKSEL + 7 + 7 + read-write + + + + + SEC + desc SEC + 0x10 + 8 + read-write + 0x0 + 0x7F + + + SECU + desc SECU + 3 + 0 + read-write + + + SECD + desc SECD + 6 + 4 + read-write + + + + + MIN + desc MIN + 0x14 + 8 + read-write + 0x0 + 0x7F + + + MINU + desc MINU + 3 + 0 + read-write + + + MIND + desc MIND + 6 + 4 + read-write + + + + + HOUR + desc HOUR + 0x18 + 8 + read-write + 0x12 + 0x3F + + + HOURU + desc HOURU + 3 + 0 + read-write + + + HOURD + desc HOURD + 5 + 4 + read-write + + + + + WEEK + desc WEEK + 0x1C + 8 + read-write + 0x0 + 0x7 + + + WEEK + desc WEEK + 2 + 0 + read-write + + + + + DAY + desc DAY + 0x20 + 8 + read-write + 0x0 + 0x3F + + + DAYU + desc DAYU + 3 + 0 + read-write + + + DAYD + desc DAYD + 5 + 4 + read-write + + + + + MON + desc MON + 0x24 + 8 + read-write + 0x0 + 0x1F + + + MON + desc MON + 4 + 0 + read-write + + + + + YEAR + desc YEAR + 0x28 + 8 + read-write + 0x0 + 0xFF + + + YEARU + desc YEARU + 3 + 0 + read-write + + + YEARD + desc YEARD + 7 + 4 + read-write + + + + + ALMMIN + desc ALMMIN + 0x2C + 8 + read-write + 0x12 + 0x7F + + + ALMMINU + desc ALMMINU + 3 + 0 + read-write + + + ALMMIND + desc ALMMIND + 6 + 4 + read-write + + + + + ALMHOUR + desc ALMHOUR + 0x30 + 8 + read-write + 0x0 + 0x3F + + + ALMHOURU + desc ALMHOURU + 3 + 0 + read-write + + + ALMHOURD + desc ALMHOURD + 5 + 4 + read-write + + + + + ALMWEEK + desc ALMWEEK + 0x34 + 8 + read-write + 0x0 + 0x7F + + + ALMWEEK + desc ALMWEEK + 6 + 0 + read-write + + + + + ERRCRH + desc ERRCRH + 0x38 + 8 + read-write + 0x0 + 0x81 + + + COMP8 + desc COMP8 + 0 + 0 + read-write + + + COMPEN + desc COMPEN + 7 + 7 + read-write + + + + + ERRCRL + desc ERRCRL + 0x3C + 8 + read-write + 0x20 + 0xFF + + + COMP + desc COMP + 7 + 0 + read-write + + + + + + + SDIOC1 + desc SDIOC + 0x4006FC00 + + 0x0 + 0x54 + + + + BLKSIZE + desc BLKSIZE + 0x4 + 16 + read-write + 0x0 + 0xFFF + + + TBS + desc TBS + 11 + 0 + read-write + + + + + BLKCNT + desc BLKCNT + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + ARG0 + desc ARG0 + 0x8 + 16 + read-write + 0x0 + 0xFFFF + + + ARG1 + desc ARG1 + 0xA + 16 + read-write + 0x0 + 0xFFFF + + + TRANSMODE + desc TRANSMODE + 0xC + 16 + read-write + 0x0 + 0x3E + + + BCE + desc BCE + 1 + 1 + read-write + + + ATCEN + desc ATCEN + 3 + 2 + read-write + + + DDIR + desc DDIR + 4 + 4 + read-write + + + MULB + desc MULB + 5 + 5 + read-write + + + + + CMD + desc CMD + 0xE + 16 + read-write + 0x0 + 0x3FFB + + + RESTYP + desc RESTYP + 1 + 0 + read-write + + + CCE + desc CCE + 3 + 3 + read-write + + + ICE + desc ICE + 4 + 4 + read-write + + + DAT + desc DAT + 5 + 5 + read-write + + + TYP + desc TYP + 7 + 6 + read-write + + + IDX + desc IDX + 13 + 8 + read-write + + + + + RESP0 + desc RESP0 + 0x10 + 16 + read-only + 0x0 + 0xFFFF + + + RESP1 + desc RESP1 + 0x12 + 16 + read-only + 0x0 + 0xFFFF + + + RESP2 + desc RESP2 + 0x14 + 16 + read-only + 0x0 + 0xFFFF + + + RESP3 + desc RESP3 + 0x16 + 16 + read-only + 0x0 + 0xFFFF + + + RESP4 + desc RESP4 + 0x18 + 16 + read-only + 0x0 + 0xFFFF + + + RESP5 + desc RESP5 + 0x1A + 16 + read-only + 0x0 + 0xFFFF + + + RESP6 + desc RESP6 + 0x1C + 16 + read-only + 0x0 + 0xFFFF + + + RESP7 + desc RESP7 + 0x1E + 16 + read-only + 0x0 + 0xFFFF + + + BUF0 + desc BUF0 + 0x20 + 16 + read-write + 0x0 + 0xFFFF + + + BUF1 + desc BUF1 + 0x22 + 16 + read-write + 0x0 + 0xFFFF + + + PSTAT + desc PSTAT + 0x24 + 32 + read-only + 0x0 + 0x1FF0F07 + + + CIC + desc CIC + 0 + 0 + read-only + + + CID + desc CID + 1 + 1 + read-only + + + DA + desc DA + 2 + 2 + read-only + + + WTA + desc WTA + 8 + 8 + read-only + + + RTA + desc RTA + 9 + 9 + read-only + + + BWE + desc BWE + 10 + 10 + read-only + + + BRE + desc BRE + 11 + 11 + read-only + + + CIN + desc CIN + 16 + 16 + read-only + + + CSS + desc CSS + 17 + 17 + read-only + + + CDL + desc CDL + 18 + 18 + read-only + + + WPL + desc WPL + 19 + 19 + read-only + + + DATL + desc DATL + 23 + 20 + read-only + + + CMDL + desc CMDL + 24 + 24 + read-only + + + + + HOSTCON + desc HOSTCON + 0x28 + 8 + read-write + 0x0 + 0xE6 + + + DW + desc DW + 1 + 1 + read-write + + + HSEN + desc HSEN + 2 + 2 + read-write + + + EXDW + desc EXDW + 5 + 5 + read-write + + + CDTL + desc CDTL + 6 + 6 + read-write + + + CDSS + desc CDSS + 7 + 7 + read-write + + + + + PWRCON + desc PWRCON + 0x29 + 8 + read-write + 0x0 + 0x1 + + + PWON + desc PWON + 0 + 0 + read-write + + + + + BLKGPCON + desc BLKGPCON + 0x2A + 8 + read-write + 0x0 + 0xF + + + SABGR + desc SABGR + 0 + 0 + read-write + + + CR + desc CR + 1 + 1 + read-write + + + RWC + desc RWC + 2 + 2 + read-write + + + IABG + desc IABG + 3 + 3 + read-write + + + + + CLKCON + desc CLKCON + 0x2C + 16 + read-write + 0x2 + 0xFF05 + + + ICE + desc ICE + 0 + 0 + read-write + + + CE + desc CE + 2 + 2 + read-write + + + FS + desc FS + 15 + 8 + read-write + + + + + TOUTCON + desc TOUTCON + 0x2E + 8 + read-write + 0x0 + 0xF + + + DTO + desc DTO + 3 + 0 + read-write + + + + + SFTRST + desc SFTRST + 0x2F + 8 + read-write + 0x0 + 0x7 + + + RSTA + desc RSTA + 0 + 0 + read-write + + + RSTC + desc RSTC + 1 + 1 + read-write + + + RSTD + desc RSTD + 2 + 2 + read-write + + + + + NORINTST + desc NORINTST + 0x30 + 16 + read-write + 0x0 + 0x81F7 + + + CC + desc CC + 0 + 0 + read-write + + + TC + desc TC + 1 + 1 + read-write + + + BGE + desc BGE + 2 + 2 + read-write + + + BWR + desc BWR + 4 + 4 + read-write + + + BRR + desc BRR + 5 + 5 + read-write + + + CIST + desc CIST + 6 + 6 + read-write + + + CRM + desc CRM + 7 + 7 + read-write + + + CINT + desc CINT + 8 + 8 + read-only + + + EI + desc EI + 15 + 15 + read-only + + + + + ERRINTST + desc ERRINTST + 0x32 + 16 + read-write + 0x0 + 0x17F + + + CTOE + desc CTOE + 0 + 0 + read-write + + + CCE + desc CCE + 1 + 1 + read-write + + + CEBE + desc CEBE + 2 + 2 + read-write + + + CIE + desc CIE + 3 + 3 + read-write + + + DTOE + desc DTOE + 4 + 4 + read-write + + + DCE + desc DCE + 5 + 5 + read-write + + + DEBE + desc DEBE + 6 + 6 + read-write + + + ACE + desc ACE + 8 + 8 + read-write + + + + + NORINTSTEN + desc NORINTSTEN + 0x34 + 16 + read-write + 0x0 + 0x1F7 + + + CCEN + desc CCEN + 0 + 0 + read-write + + + TCEN + desc TCEN + 1 + 1 + read-write + + + BGEEN + desc BGEEN + 2 + 2 + read-write + + + BWREN + desc BWREN + 4 + 4 + read-write + + + BRREN + desc BRREN + 5 + 5 + read-write + + + CISTEN + desc CISTEN + 6 + 6 + read-write + + + CRMEN + desc CRMEN + 7 + 7 + read-write + + + CINTEN + desc CINTEN + 8 + 8 + read-write + + + + + ERRINTSTEN + desc ERRINTSTEN + 0x36 + 16 + read-write + 0x0 + 0x17F + + + CTOEEN + desc CTOEEN + 0 + 0 + read-write + + + CCEEN + desc CCEEN + 1 + 1 + read-write + + + CEBEEN + desc CEBEEN + 2 + 2 + read-write + + + CIEEN + desc CIEEN + 3 + 3 + read-write + + + DTOEEN + desc DTOEEN + 4 + 4 + read-write + + + DCEEN + desc DCEEN + 5 + 5 + read-write + + + DEBEEN + desc DEBEEN + 6 + 6 + read-write + + + ACEEN + desc ACEEN + 8 + 8 + read-write + + + + + NORINTSGEN + desc NORINTSGEN + 0x38 + 16 + read-write + 0x0 + 0x1F7 + + + CCSEN + desc CCSEN + 0 + 0 + read-write + + + TCSEN + desc TCSEN + 1 + 1 + read-write + + + BGESEN + desc BGESEN + 2 + 2 + read-write + + + BWRSEN + desc BWRSEN + 4 + 4 + read-write + + + BRRSEN + desc BRRSEN + 5 + 5 + read-write + + + CISTSEN + desc CISTSEN + 6 + 6 + read-write + + + CRMSEN + desc CRMSEN + 7 + 7 + read-write + + + CINTSEN + desc CINTSEN + 8 + 8 + read-write + + + + + ERRINTSGEN + desc ERRINTSGEN + 0x3A + 16 + read-write + 0x0 + 0x17F + + + CTOESEN + desc CTOESEN + 0 + 0 + read-write + + + CCESEN + desc CCESEN + 1 + 1 + read-write + + + CEBESEN + desc CEBESEN + 2 + 2 + read-write + + + CIESEN + desc CIESEN + 3 + 3 + read-write + + + DTOESEN + desc DTOESEN + 4 + 4 + read-write + + + DCESEN + desc DCESEN + 5 + 5 + read-write + + + DEBESEN + desc DEBESEN + 6 + 6 + read-write + + + ACESEN + desc ACESEN + 8 + 8 + read-write + + + + + ATCERRST + desc ATCERRST + 0x3C + 16 + read-only + 0x0 + 0x9F + + + NE + desc NE + 0 + 0 + read-only + + + TOE + desc TOE + 1 + 1 + read-only + + + CE + desc CE + 2 + 2 + read-only + + + EBE + desc EBE + 3 + 3 + read-only + + + IE + desc IE + 4 + 4 + read-only + + + CMDE + desc CMDE + 7 + 7 + read-only + + + + + FEA + desc FEA + 0x50 + 16 + write-only + 0x0 + 0x9F + + + FNE + desc FNE + 0 + 0 + write-only + + + FTOE + desc FTOE + 1 + 1 + write-only + + + FCE + desc FCE + 2 + 2 + write-only + + + FEBE + desc FEBE + 3 + 3 + write-only + + + FIE + desc FIE + 4 + 4 + write-only + + + FCMDE + desc FCMDE + 7 + 7 + write-only + + + + + FEE + desc FEE + 0x52 + 16 + write-only + 0x0 + 0x17F + + + FCTOE + desc FCTOE + 0 + 0 + write-only + + + FCCE + desc FCCE + 1 + 1 + write-only + + + FCEBE + desc FCEBE + 2 + 2 + write-only + + + FCIE + desc FCIE + 3 + 3 + write-only + + + FDTOE + desc FDTOE + 4 + 4 + write-only + + + FDCE + desc FDCE + 5 + 5 + write-only + + + FDEBE + desc FDEBE + 6 + 6 + write-only + + + FACE + desc FACE + 8 + 8 + write-only + + + + + + + SDIOC2 + desc SDIOC + 0x40070000 + + 0x0 + 0x54 + + + + SPI1 + desc SPI + 0x4001C000 + + 0x0 + 0x1C + + + + DR + desc DR + 0x0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + CR1 + desc CR1 + 0x4 + 32 + read-write + 0x0 + 0xFFFB + + + SPIMDS + desc SPIMDS + 0 + 0 + read-write + + + TXMDS + desc TXMDS + 1 + 1 + read-write + + + MSTR + desc MSTR + 3 + 3 + read-write + + + SPLPBK + desc SPLPBK + 4 + 4 + read-write + + + SPLPBK2 + desc SPLPBK2 + 5 + 5 + read-write + + + SPE + desc SPE + 6 + 6 + read-write + + + CSUSPE + desc CSUSPE + 7 + 7 + read-write + + + EIE + desc EIE + 8 + 8 + read-write + + + TXIE + desc TXIE + 9 + 9 + read-write + + + RXIE + desc RXIE + 10 + 10 + read-write + + + IDIE + desc IDIE + 11 + 11 + read-write + + + MODFE + desc MODFE + 12 + 12 + read-write + + + PATE + desc PATE + 13 + 13 + read-write + + + PAOE + desc PAOE + 14 + 14 + read-write + + + PAE + desc PAE + 15 + 15 + read-write + + + + + CFG1 + desc CFG1 + 0xC + 32 + read-write + 0x10 + 0x77700F43 + + + FTHLV + desc FTHLV + 1 + 0 + read-write + + + SPRDTD + desc SPRDTD + 6 + 6 + read-write + + + SS0PV + desc SS0PV + 8 + 8 + read-write + + + SS1PV + desc SS1PV + 9 + 9 + read-write + + + SS2PV + desc SS2PV + 10 + 10 + read-write + + + SS3PV + desc SS3PV + 11 + 11 + read-write + + + MSSI + desc MSSI + 22 + 20 + read-write + + + MSSDL + desc MSSDL + 26 + 24 + read-write + + + MIDI + desc MIDI + 30 + 28 + read-write + + + + + SR + desc SR + 0x14 + 32 + read-write + 0x20 + 0xBF + + + OVRERF + desc OVRERF + 0 + 0 + read-write + + + IDLNF + desc IDLNF + 1 + 1 + read-only + + + MODFERF + desc MODFERF + 2 + 2 + read-write + + + PERF + desc PERF + 3 + 3 + read-write + + + UDRERF + desc UDRERF + 4 + 4 + read-write + + + TDEF + desc TDEF + 5 + 5 + read-write + + + RDFF + desc RDFF + 7 + 7 + read-write + + + + + CFG2 + desc CFG2 + 0x18 + 32 + read-write + 0xF1D + 0xFFFF + + + CPHA + desc CPHA + 0 + 0 + read-write + + + CPOL + desc CPOL + 1 + 1 + read-write + + + MBR + desc MBR + 4 + 2 + read-write + + + SSA + desc SSA + 7 + 5 + read-write + + + DSIZE + desc DSIZE + 11 + 8 + read-write + + + LSBF + desc LSBF + 12 + 12 + read-write + + + MIDIE + desc MIDIE + 13 + 13 + read-write + + + MSSDLE + desc MSSDLE + 14 + 14 + read-write + + + MSSIE + desc MSSIE + 15 + 15 + read-write + + + + + + + SPI2 + desc SPI + 0x4001C400 + + 0x0 + 0x1C + + + + SPI3 + desc SPI + 0x40020000 + + 0x0 + 0x1C + + + + SPI4 + desc SPI + 0x40020400 + + 0x0 + 0x1C + + + + SRAMC + desc SRAMC + 0x40050800 + + 0x0 + 0x14 + + + + WTCR + desc WTCR + 0x0 + 32 + read-write + 0x0 + 0x77777777 + + + SRAM12_RWT + desc SRAM12_RWT + 2 + 0 + read-write + + + SRAM12_WWT + desc SRAM12_WWT + 6 + 4 + read-write + + + SRAM3_RWT + desc SRAM3_RWT + 10 + 8 + read-write + + + SRAM3_WWT + desc SRAM3_WWT + 14 + 12 + read-write + + + SRAMH_RWT + desc SRAMH_RWT + 18 + 16 + read-write + + + SRAMH_WWT + desc SRAMH_WWT + 22 + 20 + read-write + + + SRAMR_RWT + desc SRAMR_RWT + 26 + 24 + read-write + + + SRAMR_WWT + desc SRAMR_WWT + 30 + 28 + read-write + + + + + WTPR + desc WTPR + 0x4 + 32 + read-write + 0x0 + 0xFF + + + WTPRC + desc WTPRC + 0 + 0 + read-write + + + WTPRKW + desc WTPRKW + 7 + 1 + read-write + + + + + CKCR + desc CKCR + 0x8 + 32 + read-write + 0x0 + 0x3010001 + + + PYOAD + desc PYOAD + 0 + 0 + read-write + + + ECCOAD + desc ECCOAD + 16 + 16 + read-write + + + ECCMOD + desc ECCMOD + 25 + 24 + read-write + + + + + CKPR + desc CKPR + 0xC + 32 + read-write + 0x0 + 0xFF + + + CKPRC + desc CKPRC + 0 + 0 + read-write + + + CKPRKW + desc CKPRKW + 7 + 1 + read-write + + + + + CKSR + desc CKSR + 0x10 + 32 + read-write + 0x0 + 0x1F + + + SRAM3_1ERR + desc SRAM3_1ERR + 0 + 0 + read-write + + + SRAM3_2ERR + desc SRAM3_2ERR + 1 + 1 + read-write + + + SRAM12_PYERR + desc SRAM12_PYERR + 2 + 2 + read-write + + + SRAMH_PYERR + desc SRAMH_PYERR + 3 + 3 + read-write + + + SRAMR_PYERR + desc SRAMR_PYERR + 4 + 4 + read-write + + + + + + + SWDT + desc SWDT + 0x40049400 + + 0x0 + 0xC + + + + SR + desc SR + 0x4 + 32 + read-write + 0x0 + 0x3FFFF + + + CNT + desc CNT + 15 + 0 + read-only + + + UDF + desc UDF + 16 + 16 + read-write + + + REF + desc REF + 17 + 17 + read-write + + + + + RR + desc RR + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + RF + desc RF + 15 + 0 + read-write + + + + + + + TMR01 + desc TMR0 + 0x40024000 + + 0x0 + 0x18 + + + + CNTAR + desc CNTAR + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + CNTA + desc CNTA + 15 + 0 + read-write + + + + + CNTBR + desc CNTBR + 0x4 + 32 + read-write + 0x0 + 0xFFFF + + + CNTB + desc CNTB + 15 + 0 + read-write + + + + + CMPAR + desc CMPAR + 0x8 + 32 + read-write + 0xFFFF + 0xFFFF + + + CMPA + desc CMPA + 15 + 0 + read-write + + + + + CMPBR + desc CMPBR + 0xC + 32 + read-write + 0xFFFF + 0xFFFF + + + CMPB + desc CMPB + 15 + 0 + read-write + + + + + BCONR + desc BCONR + 0x10 + 32 + read-write + 0x0 + 0xF7F7F7F7 + + + CSTA + desc CSTA + 0 + 0 + read-write + + + CAPMDA + desc CAPMDA + 1 + 1 + read-write + + + INTENA + desc INTENA + 2 + 2 + read-write + + + CKDIVA + desc CKDIVA + 7 + 4 + read-write + + + SYNSA + desc SYNSA + 8 + 8 + read-write + + + SYNCLKA + desc SYNCLKA + 9 + 9 + read-write + + + ASYNCLKA + desc ASYNCLKA + 10 + 10 + read-write + + + HSTAA + desc HSTAA + 12 + 12 + read-write + + + HSTPA + desc HSTPA + 13 + 13 + read-write + + + HCLEA + desc HCLEA + 14 + 14 + read-write + + + HICPA + desc HICPA + 15 + 15 + read-write + + + CSTB + desc CSTB + 16 + 16 + read-write + + + CAPMDB + desc CAPMDB + 17 + 17 + read-write + + + INTENB + desc INTENB + 18 + 18 + read-write + + + CKDIVB + desc CKDIVB + 23 + 20 + read-write + + + SYNSB + desc SYNSB + 24 + 24 + read-write + + + SYNCLKB + desc SYNCLKB + 25 + 25 + read-write + + + ASYNCLKB + desc ASYNCLKB + 26 + 26 + read-write + + + HSTAB + desc HSTAB + 28 + 28 + read-write + + + HSTPB + desc HSTPB + 29 + 29 + read-write + + + HCLEB + desc HCLEB + 30 + 30 + read-write + + + HICPB + desc HICPB + 31 + 31 + read-write + + + + + STFLR + desc STFLR + 0x14 + 32 + read-write + 0x0 + 0x10001 + + + CMFA + desc CMFA + 0 + 0 + read-write + + + CMFB + desc CMFB + 16 + 16 + read-write + + + + + + + TMR02 + desc TMR0 + 0x40024400 + + 0x0 + 0x18 + + + + TMR41 + desc TMR4 + 0x40017000 + + 0x0 + 0xF2 + + + + OCCRUH + desc OCCRUH + 0x2 + 16 + read-write + 0x0 + 0xFFFF + + + OCCRUL + desc OCCRUL + 0x6 + 16 + read-write + 0x0 + 0xFFFF + + + OCCRVH + desc OCCRVH + 0xA + 16 + read-write + 0x0 + 0xFFFF + + + OCCRVL + desc OCCRVL + 0xE + 16 + read-write + 0x0 + 0xFFFF + + + OCCRWH + desc OCCRWH + 0x12 + 16 + read-write + 0x0 + 0xFFFF + + + OCCRWL + desc OCCRWL + 0x16 + 16 + read-write + 0x0 + 0xFFFF + + + OCSRU + desc OCSRU + 0x18 + 16 + read-write + 0xFF00 + 0xFF + + + OCEH + desc OCEH + 0 + 0 + read-write + + + OCEL + desc OCEL + 1 + 1 + read-write + + + OCPH + desc OCPH + 2 + 2 + read-write + + + OCPL + desc OCPL + 3 + 3 + read-write + + + OCIEH + desc OCIEH + 4 + 4 + read-write + + + OCIEL + desc OCIEL + 5 + 5 + read-write + + + OCFH + desc OCFH + 6 + 6 + read-write + + + OCFL + desc OCFL + 7 + 7 + read-write + + + + + OCERU + desc OCERU + 0x1A + 16 + read-write + 0x0 + 0x3FFF + + + CHBUFEN + desc CHBUFEN + 1 + 0 + read-write + + + CLBUFEN + desc CLBUFEN + 3 + 2 + read-write + + + MHBUFEN + desc MHBUFEN + 5 + 4 + read-write + + + MLBUFEN + desc MLBUFEN + 7 + 6 + read-write + + + LMCH + desc LMCH + 8 + 8 + read-write + + + LMCL + desc LMCL + 9 + 9 + read-write + + + LMMH + desc LMMH + 10 + 10 + read-write + + + LMML + desc LMML + 11 + 11 + read-write + + + MCECH + desc MCECH + 12 + 12 + read-write + + + MCECL + desc MCECL + 13 + 13 + read-write + + + + + OCSRV + desc OCSRV + 0x1C + 16 + read-write + 0xFF00 + 0xFF + + + OCEH + desc OCEH + 0 + 0 + read-write + + + OCEL + desc OCEL + 1 + 1 + read-write + + + OCPH + desc OCPH + 2 + 2 + read-write + + + OCPL + desc OCPL + 3 + 3 + read-write + + + OCIEH + desc OCIEH + 4 + 4 + read-write + + + OCIEL + desc OCIEL + 5 + 5 + read-write + + + OCFH + desc OCFH + 6 + 6 + read-write + + + OCFL + desc OCFL + 7 + 7 + read-write + + + + + OCERV + desc OCERV + 0x1E + 16 + read-write + 0x0 + 0x3FFF + + + CHBUFEN + desc CHBUFEN + 1 + 0 + read-write + + + CLBUFEN + desc CLBUFEN + 3 + 2 + read-write + + + MHBUFEN + desc MHBUFEN + 5 + 4 + read-write + + + MLBUFEN + desc MLBUFEN + 7 + 6 + read-write + + + LMCH + desc LMCH + 8 + 8 + read-write + + + LMCL + desc LMCL + 9 + 9 + read-write + + + LMMH + desc LMMH + 10 + 10 + read-write + + + LMML + desc LMML + 11 + 11 + read-write + + + MCECH + desc MCECH + 12 + 12 + read-write + + + MCECL + desc MCECL + 13 + 13 + read-write + + + + + OCSRW + desc OCSRW + 0x20 + 16 + read-write + 0xFF00 + 0xFF + + + OCEH + desc OCEH + 0 + 0 + read-write + + + OCEL + desc OCEL + 1 + 1 + read-write + + + OCPH + desc OCPH + 2 + 2 + read-write + + + OCPL + desc OCPL + 3 + 3 + read-write + + + OCIEH + desc OCIEH + 4 + 4 + read-write + + + OCIEL + desc OCIEL + 5 + 5 + read-write + + + OCFH + desc OCFH + 6 + 6 + read-write + + + OCFL + desc OCFL + 7 + 7 + read-write + + + + + OCERW + desc OCERW + 0x22 + 16 + read-write + 0x0 + 0x3FFF + + + CHBUFEN + desc CHBUFEN + 1 + 0 + read-write + + + CLBUFEN + desc CLBUFEN + 3 + 2 + read-write + + + MHBUFEN + desc MHBUFEN + 5 + 4 + read-write + + + MLBUFEN + desc MLBUFEN + 7 + 6 + read-write + + + LMCH + desc LMCH + 8 + 8 + read-write + + + LMCL + desc LMCL + 9 + 9 + read-write + + + LMMH + desc LMMH + 10 + 10 + read-write + + + LMML + desc LMML + 11 + 11 + read-write + + + MCECH + desc MCECH + 12 + 12 + read-write + + + MCECL + desc MCECL + 13 + 13 + read-write + + + + + OCMRHUH + desc OCMRHUH + 0x24 + 16 + read-write + 0x0 + 0xFFFF + + + OCFDCH + desc OCFDCH + 0 + 0 + read-write + + + OCFPKH + desc OCFPKH + 1 + 1 + read-write + + + OCFUCH + desc OCFUCH + 2 + 2 + read-write + + + OCFZRH + desc OCFZRH + 3 + 3 + read-write + + + OPDCH + desc OPDCH + 5 + 4 + read-write + + + OPPKH + desc OPPKH + 7 + 6 + read-write + + + OPUCH + desc OPUCH + 9 + 8 + read-write + + + OPZRH + desc OPZRH + 11 + 10 + read-write + + + OPNPKH + desc OPNPKH + 13 + 12 + read-write + + + OPNZRH + desc OPNZRH + 15 + 14 + read-write + + + + + OCMRLUL + desc OCMRLUL + 0x28 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OCFDCL + desc OCFDCL + 0 + 0 + read-write + + + OCFPKL + desc OCFPKL + 1 + 1 + read-write + + + OCFUCL + desc OCFUCL + 2 + 2 + read-write + + + OCFZRL + desc OCFZRL + 3 + 3 + read-write + + + OPDCL + desc OPDCL + 5 + 4 + read-write + + + OPPKL + desc OPPKL + 7 + 6 + read-write + + + OPUCL + desc OPUCL + 9 + 8 + read-write + + + OPZRL + desc OPZRL + 11 + 10 + read-write + + + OPNPKL + desc OPNPKL + 13 + 12 + read-write + + + OPNZRL + desc OPNZRL + 15 + 14 + read-write + + + EOPNDCL + desc EOPNDCL + 17 + 16 + read-write + + + EOPNUCL + desc EOPNUCL + 19 + 18 + read-write + + + EOPDCL + desc EOPDCL + 21 + 20 + read-write + + + EOPPKL + desc EOPPKL + 23 + 22 + read-write + + + EOPUCL + desc EOPUCL + 25 + 24 + read-write + + + EOPZRL + desc EOPZRL + 27 + 26 + read-write + + + EOPNPKL + desc EOPNPKL + 29 + 28 + read-write + + + EOPNZRL + desc EOPNZRL + 31 + 30 + read-write + + + + + OCMRHVH + desc OCMRHVH + 0x2C + 16 + read-write + 0x0 + 0xFFFF + + + OCFDCH + desc OCFDCH + 0 + 0 + read-write + + + OCFPKH + desc OCFPKH + 1 + 1 + read-write + + + OCFUCH + desc OCFUCH + 2 + 2 + read-write + + + OCFZRH + desc OCFZRH + 3 + 3 + read-write + + + OPDCH + desc OPDCH + 5 + 4 + read-write + + + OPPKH + desc OPPKH + 7 + 6 + read-write + + + OPUCH + desc OPUCH + 9 + 8 + read-write + + + OPZRH + desc OPZRH + 11 + 10 + read-write + + + OPNPKH + desc OPNPKH + 13 + 12 + read-write + + + OPNZRH + desc OPNZRH + 15 + 14 + read-write + + + + + OCMRLVL + desc OCMRLVL + 0x30 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OCFDCL + desc OCFDCL + 0 + 0 + read-write + + + OCFPKL + desc OCFPKL + 1 + 1 + read-write + + + OCFUCL + desc OCFUCL + 2 + 2 + read-write + + + OCFZRL + desc OCFZRL + 3 + 3 + read-write + + + OPDCL + desc OPDCL + 5 + 4 + read-write + + + OPPKL + desc OPPKL + 7 + 6 + read-write + + + OPUCL + desc OPUCL + 9 + 8 + read-write + + + OPZRL + desc OPZRL + 11 + 10 + read-write + + + OPNPKL + desc OPNPKL + 13 + 12 + read-write + + + OPNZRL + desc OPNZRL + 15 + 14 + read-write + + + EOPNDCL + desc EOPNDCL + 17 + 16 + read-write + + + EOPNUCL + desc EOPNUCL + 19 + 18 + read-write + + + EOPDCL + desc EOPDCL + 21 + 20 + read-write + + + EOPPKL + desc EOPPKL + 23 + 22 + read-write + + + EOPUCL + desc EOPUCL + 25 + 24 + read-write + + + EOPZRL + desc EOPZRL + 27 + 26 + read-write + + + EOPNPKL + desc EOPNPKL + 29 + 28 + read-write + + + EOPNZRL + desc EOPNZRL + 31 + 30 + read-write + + + + + OCMRHWH + desc OCMRHWH + 0x34 + 16 + read-write + 0x0 + 0xFFFF + + + OCFDCH + desc OCFDCH + 0 + 0 + read-write + + + OCFPKH + desc OCFPKH + 1 + 1 + read-write + + + OCFUCH + desc OCFUCH + 2 + 2 + read-write + + + OCFZRH + desc OCFZRH + 3 + 3 + read-write + + + OPDCH + desc OPDCH + 5 + 4 + read-write + + + OPPKH + desc OPPKH + 7 + 6 + read-write + + + OPUCH + desc OPUCH + 9 + 8 + read-write + + + OPZRH + desc OPZRH + 11 + 10 + read-write + + + OPNPKH + desc OPNPKH + 13 + 12 + read-write + + + OPNZRH + desc OPNZRH + 15 + 14 + read-write + + + + + OCMRLWL + desc OCMRLWL + 0x38 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + OCFDCL + desc OCFDCL + 0 + 0 + read-write + + + OCFPKL + desc OCFPKL + 1 + 1 + read-write + + + OCFUCL + desc OCFUCL + 2 + 2 + read-write + + + OCFZRL + desc OCFZRL + 3 + 3 + read-write + + + OPDCL + desc OPDCL + 5 + 4 + read-write + + + OPPKL + desc OPPKL + 7 + 6 + read-write + + + OPUCL + desc OPUCL + 9 + 8 + read-write + + + OPZRL + desc OPZRL + 11 + 10 + read-write + + + OPNPKL + desc OPNPKL + 13 + 12 + read-write + + + OPNZRL + desc OPNZRL + 15 + 14 + read-write + + + EOPNDCL + desc EOPNDCL + 17 + 16 + read-write + + + EOPNUCL + desc EOPNUCL + 19 + 18 + read-write + + + EOPDCL + desc EOPDCL + 21 + 20 + read-write + + + EOPPKL + desc EOPPKL + 23 + 22 + read-write + + + EOPUCL + desc EOPUCL + 25 + 24 + read-write + + + EOPZRL + desc EOPZRL + 27 + 26 + read-write + + + EOPNPKL + desc EOPNPKL + 29 + 28 + read-write + + + EOPNZRL + desc EOPNZRL + 31 + 30 + read-write + + + + + CPSR + desc CPSR + 0x42 + 16 + read-write + 0xFFFF + 0xFFFF + + + CNTR + desc CNTR + 0x46 + 16 + read-write + 0x0 + 0xFFFF + + + CCSR + desc CCSR + 0x48 + 16 + read-write + 0x40 + 0xE3FF + + + CKDIV + desc CKDIV + 3 + 0 + read-write + + + CLEAR + desc CLEAR + 4 + 4 + read-write + + + MODE + desc MODE + 5 + 5 + read-write + + + STOP + desc STOP + 6 + 6 + read-write + + + BUFEN + desc BUFEN + 7 + 7 + read-write + + + IRQPEN + desc IRQPEN + 8 + 8 + read-write + + + IRQPF + desc IRQPF + 9 + 9 + read-write + + + IRQZEN + desc IRQZEN + 13 + 13 + read-write + + + IRQZF + desc IRQZF + 14 + 14 + read-write + + + ECKEN + desc ECKEN + 15 + 15 + read-write + + + + + CVPR + desc CVPR + 0x4A + 16 + read-write + 0x0 + 0xFFFF + + + ZIM + desc ZIM + 3 + 0 + read-write + + + PIM + desc PIM + 7 + 4 + read-write + + + ZIC + desc ZIC + 11 + 8 + read-only + + + PIC + desc PIC + 15 + 12 + read-only + + + + + PFSRU + desc PFSRU + 0x82 + 16 + read-write + 0x0 + 0xFFFF + + + PDARU + desc PDARU + 0x84 + 16 + read-write + 0x0 + 0xFFFF + + + PDBRU + desc PDBRU + 0x86 + 16 + read-write + 0x0 + 0xFFFF + + + PFSRV + desc PFSRV + 0x8A + 16 + read-write + 0x0 + 0xFFFF + + + PDARV + desc PDARV + 0x8C + 16 + read-write + 0x0 + 0xFFFF + + + PDBRV + desc PDBRV + 0x8E + 16 + read-write + 0x0 + 0xFFFF + + + PFSRW + desc PFSRW + 0x92 + 16 + read-write + 0x0 + 0xFFFF + + + PDARW + desc PDARW + 0x94 + 16 + read-write + 0x0 + 0xFFFF + + + PDBRW + desc PDBRW + 0x96 + 16 + read-write + 0x0 + 0xFFFF + + + POCRU + desc POCRU + 0x98 + 16 + read-write + 0xFF00 + 0xF7 + + + DIVCK + desc DIVCK + 2 + 0 + read-write + + + PWMMD + desc PWMMD + 5 + 4 + read-write + + + LVLS + desc LVLS + 7 + 6 + read-write + + + + + POCRV + desc POCRV + 0x9C + 16 + read-write + 0xFF00 + 0xF7 + + + DIVCK + desc DIVCK + 2 + 0 + read-write + + + PWMMD + desc PWMMD + 5 + 4 + read-write + + + LVLS + desc LVLS + 7 + 6 + read-write + + + + + POCRW + desc POCRW + 0xA0 + 16 + read-write + 0xFF00 + 0xF7 + + + DIVCK + desc DIVCK + 2 + 0 + read-write + + + PWMMD + desc PWMMD + 5 + 4 + read-write + + + LVLS + desc LVLS + 7 + 6 + read-write + + + + + RCSR + desc RCSR + 0xA4 + 16 + read-write + 0x0 + 0xFFF7 + + + RTIDU + desc RTIDU + 0 + 0 + read-write + + + RTIDV + desc RTIDV + 1 + 1 + read-write + + + RTIDW + desc RTIDW + 2 + 2 + read-write + + + RTIFU + desc RTIFU + 4 + 4 + read-only + + + RTICU + desc RTICU + 5 + 5 + read-write + + + RTEU + desc RTEU + 6 + 6 + read-write + + + RTSU + desc RTSU + 7 + 7 + read-write + + + RTIFV + desc RTIFV + 8 + 8 + read-only + + + RTICV + desc RTICV + 9 + 9 + read-write + + + RTEV + desc RTEV + 10 + 10 + read-write + + + RTSV + desc RTSV + 11 + 11 + read-write + + + RTIFW + desc RTIFW + 12 + 12 + read-only + + + RTICW + desc RTICW + 13 + 13 + read-write + + + RTEW + desc RTEW + 14 + 14 + read-write + + + RTSW + desc RTSW + 15 + 15 + read-write + + + + + SCCRUH + desc SCCRUH + 0xB2 + 16 + read-write + 0x0 + 0xFFFF + + + SCCRUL + desc SCCRUL + 0xB6 + 16 + read-write + 0x0 + 0xFFFF + + + SCCRVH + desc SCCRVH + 0xBA + 16 + read-write + 0x0 + 0xFFFF + + + SCCRVL + desc SCCRVL + 0xBE + 16 + read-write + 0x0 + 0xFFFF + + + SCCRWH + desc SCCRWH + 0xC2 + 16 + read-write + 0x0 + 0xFFFF + + + SCCRWL + desc SCCRWL + 0xC6 + 16 + read-write + 0x0 + 0xFFFF + + + SCSRUH + desc SCSRUH + 0xC8 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRUH + desc SCMRUH + 0xCA + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRUL + desc SCSRUL + 0xCC + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRUL + desc SCMRUL + 0xCE + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRVH + desc SCSRVH + 0xD0 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRVH + desc SCMRVH + 0xD2 + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRVL + desc SCSRVL + 0xD4 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRVL + desc SCMRVL + 0xD6 + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRWH + desc SCSRWH + 0xD8 + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRWH + desc SCMRWH + 0xDA + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + SCSRWL + desc SCSRWL + 0xDC + 16 + read-write + 0x0 + 0xF33F + + + BUFEN + desc BUFEN + 1 + 0 + read-write + + + EVTOS + desc EVTOS + 4 + 2 + read-write + + + LMC + desc LMC + 5 + 5 + read-write + + + EVTMS + desc EVTMS + 8 + 8 + read-write + + + EVTDS + desc EVTDS + 9 + 9 + read-write + + + DEN + desc DEN + 12 + 12 + read-write + + + PEN + desc PEN + 13 + 13 + read-write + + + UEN + desc UEN + 14 + 14 + read-write + + + ZEN + desc ZEN + 15 + 15 + read-write + + + + + SCMRWL + desc SCMRWL + 0xDE + 16 + read-write + 0xFF00 + 0xCF + + + AMC + desc AMC + 3 + 0 + read-write + + + MZCE + desc MZCE + 6 + 6 + read-write + + + MPCE + desc MPCE + 7 + 7 + read-write + + + + + ECSR + desc ECSR + 0xF0 + 16 + read-write + 0x0 + 0x80 + + + HOLD + desc HOLD + 7 + 7 + read-write + + + + + + + TMR42 + desc TMR4 + 0x40024800 + + 0x0 + 0xF2 + + + + TMR43 + desc TMR4 + 0x40024C00 + + 0x0 + 0xF2 + + + + TMR4CR + desc TMR4CR + 0x40055408 + + 0x0 + 0xC + + + + ECER1 + desc ECER1 + 0x0 + 32 + read-write + 0x0 + 0x3 + + + EMBVAL + desc EMBVAL + 1 + 0 + read-write + + + + + ECER2 + desc ECER2 + 0x4 + 32 + read-write + 0x0 + 0x3 + + + EMBVAL + desc EMBVAL + 1 + 0 + read-write + + + + + ECER3 + desc ECER3 + 0x8 + 32 + read-write + 0x0 + 0x3 + + + EMBVAL + desc EMBVAL + 1 + 0 + read-write + + + + + + + TMR61 + desc TMR6 + 0x40018000 + + 0x0 + 0x90 + + + + CNTER + desc CNTER + 0x0 + 32 + read-write + 0x0 + 0xFFFF + + + CNT + desc CNT + 15 + 0 + read-write + + + + + PERAR + desc PERAR + 0x4 + 32 + read-write + 0xFFFF + 0xFFFF + + + PERA + desc PERA + 15 + 0 + read-write + + + + + PERBR + desc PERBR + 0x8 + 32 + read-write + 0xFFFF + 0xFFFF + + + PERB + desc PERB + 15 + 0 + read-write + + + + + PERCR + desc PERCR + 0xC + 32 + read-write + 0xFFFF + 0xFFFF + + + PERC + desc PERC + 15 + 0 + read-write + + + + + GCMAR + desc GCMAR + 0x10 + 32 + read-write + 0xFFFF + 0xFFFF + + + GCMA + desc GCMA + 15 + 0 + read-write + + + + + GCMBR + desc GCMBR + 0x14 + 32 + read-write + 0xFFFF + 0xFFFF + + + GCMB + desc GCMB + 15 + 0 + read-write + + + + + GCMCR + desc GCMCR + 0x18 + 32 + read-write + 0xFFFF + 0xFFFF + + + GCMC + desc GCMC + 15 + 0 + read-write + + + + + GCMDR + desc GCMDR + 0x1C + 32 + read-write + 0xFFFF + 0xFFFF + + + GCMD + desc GCMD + 15 + 0 + read-write + + + + + GCMER + desc GCMER + 0x20 + 32 + read-write + 0xFFFF + 0xFFFF + + + GCME + desc GCME + 15 + 0 + read-write + + + + + GCMFR + desc GCMFR + 0x24 + 32 + read-write + 0xFFFF + 0xFFFF + + + GCMF + desc GCMF + 15 + 0 + read-write + + + + + SCMAR + desc SCMAR + 0x28 + 32 + read-write + 0xFFFF + 0xFFFF + + + SCMA + desc SCMA + 15 + 0 + read-write + + + + + SCMBR + desc SCMBR + 0x2C + 32 + read-write + 0xFFFF + 0xFFFF + + + SCMB + desc SCMB + 15 + 0 + read-write + + + + + SCMCR + desc SCMCR + 0x30 + 32 + read-write + 0xFFFF + 0xFFFF + + + SCMC + desc SCMC + 15 + 0 + read-write + + + + + SCMDR + desc SCMDR + 0x34 + 32 + read-write + 0xFFFF + 0xFFFF + + + SCMD + desc SCMD + 15 + 0 + read-write + + + + + SCMER + desc SCMER + 0x38 + 32 + read-write + 0xFFFF + 0xFFFF + + + SCME + desc SCME + 15 + 0 + read-write + + + + + SCMFR + desc SCMFR + 0x3C + 32 + read-write + 0xFFFF + 0xFFFF + + + SCMF + desc SCMF + 15 + 0 + read-write + + + + + DTUAR + desc DTUAR + 0x40 + 32 + read-write + 0xFFFF + 0xFFFF + + + DTUA + desc DTUA + 15 + 0 + read-write + + + + + DTDAR + desc DTDAR + 0x44 + 32 + read-write + 0xFFFF + 0xFFFF + + + DTDA + desc DTDA + 15 + 0 + read-write + + + + + DTUBR + desc DTUBR + 0x48 + 32 + read-write + 0xFFFF + 0xFFFF + + + DTUB + desc DTUB + 15 + 0 + read-write + + + + + DTDBR + desc DTDBR + 0x4C + 32 + read-write + 0xFFFF + 0xFFFF + + + DTDB + desc DTDB + 15 + 0 + read-write + + + + + GCONR + desc GCONR + 0x50 + 32 + read-write + 0x100 + 0xF017F + + + START + desc START + 0 + 0 + read-write + + + MODE + desc MODE + 3 + 1 + read-write + + + CKDIV + desc CKDIV + 6 + 4 + read-write + + + DIR + desc DIR + 8 + 8 + read-write + + + ZMSKREV + desc ZMSKREV + 16 + 16 + read-write + + + ZMSKPOS + desc ZMSKPOS + 17 + 17 + read-write + + + ZMSKVAL + desc ZMSKVAL + 19 + 18 + read-write + + + + + ICONR + desc ICONR + 0x54 + 32 + read-write + 0x0 + 0xF01FF + + + INTENA + desc INTENA + 0 + 0 + read-write + + + INTENB + desc INTENB + 1 + 1 + read-write + + + INTENC + desc INTENC + 2 + 2 + read-write + + + INTEND + desc INTEND + 3 + 3 + read-write + + + INTENE + desc INTENE + 4 + 4 + read-write + + + INTENF + desc INTENF + 5 + 5 + read-write + + + INTENOVF + desc INTENOVF + 6 + 6 + read-write + + + INTENUDF + desc INTENUDF + 7 + 7 + read-write + + + INTENDTE + desc INTENDTE + 8 + 8 + read-write + + + INTENSAU + desc INTENSAU + 16 + 16 + read-write + + + INTENSAD + desc INTENSAD + 17 + 17 + read-write + + + INTENSBU + desc INTENSBU + 18 + 18 + read-write + + + INTENSBD + desc INTENSBD + 19 + 19 + read-write + + + + + PCONR + desc PCONR + 0x58 + 32 + read-write + 0x0 + 0x19FF19FF + + + CAPMDA + desc CAPMDA + 0 + 0 + read-write + + + STACA + desc STACA + 1 + 1 + read-write + + + STPCA + desc STPCA + 2 + 2 + read-write + + + STASTPSA + desc STASTPSA + 3 + 3 + read-write + + + CMPCA + desc CMPCA + 5 + 4 + read-write + + + PERCA + desc PERCA + 7 + 6 + read-write + + + OUTENA + desc OUTENA + 8 + 8 + read-write + + + EMBVALA + desc EMBVALA + 12 + 11 + read-write + + + CAPMDB + desc CAPMDB + 16 + 16 + read-write + + + STACB + desc STACB + 17 + 17 + read-write + + + STPCB + desc STPCB + 18 + 18 + read-write + + + STASTPSB + desc STASTPSB + 19 + 19 + read-write + + + CMPCB + desc CMPCB + 21 + 20 + read-write + + + PERCB + desc PERCB + 23 + 22 + read-write + + + OUTENB + desc OUTENB + 24 + 24 + read-write + + + EMBVALB + desc EMBVALB + 28 + 27 + read-write + + + + + BCONR + desc BCONR + 0x5C + 32 + read-write + 0x0 + 0x3333030F + + + BENA + desc BENA + 0 + 0 + read-write + + + BSEA + desc BSEA + 1 + 1 + read-write + + + BENB + desc BENB + 2 + 2 + read-write + + + BSEB + desc BSEB + 3 + 3 + read-write + + + BENP + desc BENP + 8 + 8 + read-write + + + BSEP + desc BSEP + 9 + 9 + read-write + + + BENSPA + desc BENSPA + 16 + 16 + read-write + + + BSESPA + desc BSESPA + 17 + 17 + read-write + + + BTRUSPA + desc BTRUSPA + 20 + 20 + read-write + + + BTRDSPA + desc BTRDSPA + 21 + 21 + read-write + + + BENSPB + desc BENSPB + 24 + 24 + read-write + + + BSESPB + desc BSESPB + 25 + 25 + read-write + + + BTRUSPB + desc BTRUSPB + 28 + 28 + read-write + + + BTRDSPB + desc BTRDSPB + 29 + 29 + read-write + + + + + DCONR + desc DCONR + 0x60 + 32 + read-write + 0x0 + 0x131 + + + DTCEN + desc DTCEN + 0 + 0 + read-write + + + DTBENU + desc DTBENU + 4 + 4 + read-write + + + DTBEND + desc DTBEND + 5 + 5 + read-write + + + SEPA + desc SEPA + 8 + 8 + read-write + + + + + FCONR + desc FCONR + 0x68 + 32 + read-write + 0x0 + 0x770077 + + + NOFIENGA + desc NOFIENGA + 0 + 0 + read-write + + + NOFICKGA + desc NOFICKGA + 2 + 1 + read-write + + + NOFIENGB + desc NOFIENGB + 4 + 4 + read-write + + + NOFICKGB + desc NOFICKGB + 6 + 5 + read-write + + + NOFIENTA + desc NOFIENTA + 16 + 16 + read-write + + + NOFICKTA + desc NOFICKTA + 18 + 17 + read-write + + + NOFIENTB + desc NOFIENTB + 20 + 20 + read-write + + + NOFICKTB + desc NOFICKTB + 22 + 21 + read-write + + + + + VPERR + desc VPERR + 0x6C + 32 + read-write + 0x0 + 0x1F0300 + + + SPPERIA + desc SPPERIA + 8 + 8 + read-write + + + SPPERIB + desc SPPERIB + 9 + 9 + read-write + + + PCNTE + desc PCNTE + 17 + 16 + read-write + + + PCNTS + desc PCNTS + 20 + 18 + read-write + + + + + STFLR + desc STFLR + 0x70 + 32 + read-write + 0x80000000 + 0x80E01FFF + + + CMAF + desc CMAF + 0 + 0 + read-write + + + CMBF + desc CMBF + 1 + 1 + read-write + + + CMCF + desc CMCF + 2 + 2 + read-write + + + CMDF + desc CMDF + 3 + 3 + read-write + + + CMEF + desc CMEF + 4 + 4 + read-write + + + CMFF + desc CMFF + 5 + 5 + read-write + + + OVFF + desc OVFF + 6 + 6 + read-write + + + UDFF + desc UDFF + 7 + 7 + read-write + + + DTEF + desc DTEF + 8 + 8 + read-only + + + CMSAUF + desc CMSAUF + 9 + 9 + read-write + + + CMSADF + desc CMSADF + 10 + 10 + read-write + + + CMSBUF + desc CMSBUF + 11 + 11 + read-write + + + CMSBDF + desc CMSBDF + 12 + 12 + read-write + + + VPERNUM + desc VPERNUM + 23 + 21 + read-only + + + DIRF + desc DIRF + 31 + 31 + read-only + + + + + HSTAR + desc HSTAR + 0x74 + 32 + read-write + 0x0 + 0x80000FF3 + + + HSTA0 + desc HSTA0 + 0 + 0 + read-write + + + HSTA1 + desc HSTA1 + 1 + 1 + read-write + + + HSTA4 + desc HSTA4 + 4 + 4 + read-write + + + HSTA5 + desc HSTA5 + 5 + 5 + read-write + + + HSTA6 + desc HSTA6 + 6 + 6 + read-write + + + HSTA7 + desc HSTA7 + 7 + 7 + read-write + + + HSTA8 + desc HSTA8 + 8 + 8 + read-write + + + HSTA9 + desc HSTA9 + 9 + 9 + read-write + + + HSTA10 + desc HSTA10 + 10 + 10 + read-write + + + HSTA11 + desc HSTA11 + 11 + 11 + read-write + + + STAS + desc STAS + 31 + 31 + read-write + + + + + HSTPR + desc HSTPR + 0x78 + 32 + read-write + 0x0 + 0x80000FF3 + + + HSTP0 + desc HSTP0 + 0 + 0 + read-write + + + HSTP1 + desc HSTP1 + 1 + 1 + read-write + + + HSTP4 + desc HSTP4 + 4 + 4 + read-write + + + HSTP5 + desc HSTP5 + 5 + 5 + read-write + + + HSTP6 + desc HSTP6 + 6 + 6 + read-write + + + HSTP7 + desc HSTP7 + 7 + 7 + read-write + + + HSTP8 + desc HSTP8 + 8 + 8 + read-write + + + HSTP9 + desc HSTP9 + 9 + 9 + read-write + + + HSTP10 + desc HSTP10 + 10 + 10 + read-write + + + HSTP11 + desc HSTP11 + 11 + 11 + read-write + + + STPS + desc STPS + 31 + 31 + read-write + + + + + HCLRR + desc HCLRR + 0x7C + 32 + read-write + 0x0 + 0x80000FF3 + + + HCLE0 + desc HCLE0 + 0 + 0 + read-write + + + HCLE1 + desc HCLE1 + 1 + 1 + read-write + + + HCLE4 + desc HCLE4 + 4 + 4 + read-write + + + HCLE5 + desc HCLE5 + 5 + 5 + read-write + + + HCLE6 + desc HCLE6 + 6 + 6 + read-write + + + HCLE7 + desc HCLE7 + 7 + 7 + read-write + + + HCLE8 + desc HCLE8 + 8 + 8 + read-write + + + HCLE9 + desc HCLE9 + 9 + 9 + read-write + + + HCLE10 + desc HCLE10 + 10 + 10 + read-write + + + HCLE11 + desc HCLE11 + 11 + 11 + read-write + + + CLES + desc CLES + 31 + 31 + read-write + + + + + HCPAR + desc HCPAR + 0x80 + 32 + read-write + 0x0 + 0xFF3 + + + HCPA0 + desc HCPA0 + 0 + 0 + read-write + + + HCPA1 + desc HCPA1 + 1 + 1 + read-write + + + HCPA4 + desc HCPA4 + 4 + 4 + read-write + + + HCPA5 + desc HCPA5 + 5 + 5 + read-write + + + HCPA6 + desc HCPA6 + 6 + 6 + read-write + + + HCPA7 + desc HCPA7 + 7 + 7 + read-write + + + HCPA8 + desc HCPA8 + 8 + 8 + read-write + + + HCPA9 + desc HCPA9 + 9 + 9 + read-write + + + HCPA10 + desc HCPA10 + 10 + 10 + read-write + + + HCPA11 + desc HCPA11 + 11 + 11 + read-write + + + + + HCPBR + desc HCPBR + 0x84 + 32 + read-write + 0x0 + 0xFF3 + + + HCPB0 + desc HCPB0 + 0 + 0 + read-write + + + HCPB1 + desc HCPB1 + 1 + 1 + read-write + + + HCPB4 + desc HCPB4 + 4 + 4 + read-write + + + HCPB5 + desc HCPB5 + 5 + 5 + read-write + + + HCPB6 + desc HCPB6 + 6 + 6 + read-write + + + HCPB7 + desc HCPB7 + 7 + 7 + read-write + + + HCPB8 + desc HCPB8 + 8 + 8 + read-write + + + HCPB9 + desc HCPB9 + 9 + 9 + read-write + + + HCPB10 + desc HCPB10 + 10 + 10 + read-write + + + HCPB11 + desc HCPB11 + 11 + 11 + read-write + + + + + HCUPR + desc HCUPR + 0x88 + 32 + read-write + 0x0 + 0x30FFF + + + HCUP0 + desc HCUP0 + 0 + 0 + read-write + + + HCUP1 + desc HCUP1 + 1 + 1 + read-write + + + HCUP2 + desc HCUP2 + 2 + 2 + read-write + + + HCUP3 + desc HCUP3 + 3 + 3 + read-write + + + HCUP4 + desc HCUP4 + 4 + 4 + read-write + + + HCUP5 + desc HCUP5 + 5 + 5 + read-write + + + HCUP6 + desc HCUP6 + 6 + 6 + read-write + + + HCUP7 + desc HCUP7 + 7 + 7 + read-write + + + HCUP8 + desc HCUP8 + 8 + 8 + read-write + + + HCUP9 + desc HCUP9 + 9 + 9 + read-write + + + HCUP10 + desc HCUP10 + 10 + 10 + read-write + + + HCUP11 + desc HCUP11 + 11 + 11 + read-write + + + HCUP16 + desc HCUP16 + 16 + 16 + read-write + + + HCUP17 + desc HCUP17 + 17 + 17 + read-write + + + + + HCDOR + desc HCDOR + 0x8C + 32 + read-write + 0x0 + 0x30FFF + + + HCDO0 + desc HCDO0 + 0 + 0 + read-write + + + HCDO1 + desc HCDO1 + 1 + 1 + read-write + + + HCDO2 + desc HCDO2 + 2 + 2 + read-write + + + HCDO3 + desc HCDO3 + 3 + 3 + read-write + + + HCDO4 + desc HCDO4 + 4 + 4 + read-write + + + HCDO5 + desc HCDO5 + 5 + 5 + read-write + + + HCDO6 + desc HCDO6 + 6 + 6 + read-write + + + HCDO7 + desc HCDO7 + 7 + 7 + read-write + + + HCDO8 + desc HCDO8 + 8 + 8 + read-write + + + HCDO9 + desc HCDO9 + 9 + 9 + read-write + + + HCDO10 + desc HCDO10 + 10 + 10 + read-write + + + HCDO11 + desc HCDO11 + 11 + 11 + read-write + + + HCDO16 + desc HCDO16 + 16 + 16 + read-write + + + HCDO17 + desc HCDO17 + 17 + 17 + read-write + + + + + + + TMR62 + desc TMR6 + 0x40018400 + + 0x0 + 0x90 + + + + TMR63 + desc TMR6 + 0x40018800 + + 0x0 + 0x90 + + + + TMR6CR + desc TMR6CR + 0x40018000 + TMR61 + + 0x0 + 0x400 + + + + SSTAR + desc SSTAR + 0x3F4 + 32 + read-write + 0x0 + 0x7 + + + SSTA1 + desc SSTA1 + 0 + 0 + read-write + + + SSTA2 + desc SSTA2 + 1 + 1 + read-write + + + SSTA3 + desc SSTA3 + 2 + 2 + read-write + + + + + SSTPR + desc SSTPR + 0x3F8 + 32 + read-write + 0x0 + 0x7 + + + SSTP1 + desc SSTP1 + 0 + 0 + read-write + + + SSTP2 + desc SSTP2 + 1 + 1 + read-write + + + SSTP3 + desc SSTP3 + 2 + 2 + read-write + + + + + SCLRR + desc SCLRR + 0x3FC + 32 + read-write + 0x0 + 0x7 + + + SCLE1 + desc SCLE1 + 0 + 0 + read-write + + + SCLE2 + desc SCLE2 + 1 + 1 + read-write + + + SCLE3 + desc SCLE3 + 2 + 2 + read-write + + + + + + + TMRA1 + desc TMRA + 0x40015000 + + 0x0 + 0x160 + + + + CNTER + desc CNTER + 0x0 + 16 + read-write + 0x0 + 0xFFFF + + + CNT + desc CNT + 15 + 0 + read-write + + + + + PERAR + desc PERAR + 0x4 + 16 + read-write + 0xFFFF + 0xFFFF + + + PER + desc PER + 15 + 0 + read-write + + + + + CMPAR1 + desc CMPAR1 + 0x40 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR2 + desc CMPAR2 + 0x44 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR3 + desc CMPAR3 + 0x48 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR4 + desc CMPAR4 + 0x4C + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR5 + desc CMPAR5 + 0x50 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR6 + desc CMPAR6 + 0x54 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR7 + desc CMPAR7 + 0x58 + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + CMPAR8 + desc CMPAR8 + 0x5C + 16 + read-write + 0xFFFF + 0xFFFF + + + CMP + desc CMP + 15 + 0 + read-write + + + + + BCSTR + desc BCSTR + 0x80 + 16 + read-write + 0x2 + 0xF0FF + + + START + desc START + 0 + 0 + read-write + + + DIR + desc DIR + 1 + 1 + read-write + + + MODE + desc MODE + 2 + 2 + read-write + + + SYNST + desc SYNST + 3 + 3 + read-write + + + CKDIV + desc CKDIV + 7 + 4 + read-write + + + ITENOVF + desc ITENOVF + 12 + 12 + read-write + + + ITENUDF + desc ITENUDF + 13 + 13 + read-write + + + OVFF + desc OVFF + 14 + 14 + read-write + + + UDFF + desc UDFF + 15 + 15 + read-write + + + + + HCONR + desc HCONR + 0x84 + 16 + read-write + 0x0 + 0xF777 + + + HSTA0 + desc HSTA0 + 0 + 0 + read-write + + + HSTA1 + desc HSTA1 + 1 + 1 + read-write + + + HSTA2 + desc HSTA2 + 2 + 2 + read-write + + + HSTP0 + desc HSTP0 + 4 + 4 + read-write + + + HSTP1 + desc HSTP1 + 5 + 5 + read-write + + + HSTP2 + desc HSTP2 + 6 + 6 + read-write + + + HCLE0 + desc HCLE0 + 8 + 8 + read-write + + + HCLE1 + desc HCLE1 + 9 + 9 + read-write + + + HCLE2 + desc HCLE2 + 10 + 10 + read-write + + + HCLE3 + desc HCLE3 + 12 + 12 + read-write + + + HCLE4 + desc HCLE4 + 13 + 13 + read-write + + + HCLE5 + desc HCLE5 + 14 + 14 + read-write + + + HCLE6 + desc HCLE6 + 15 + 15 + read-write + + + + + HCUPR + desc HCUPR + 0x88 + 16 + read-write + 0x0 + 0x1FFF + + + HCUP0 + desc HCUP0 + 0 + 0 + read-write + + + HCUP1 + desc HCUP1 + 1 + 1 + read-write + + + HCUP2 + desc HCUP2 + 2 + 2 + read-write + + + HCUP3 + desc HCUP3 + 3 + 3 + read-write + + + HCUP4 + desc HCUP4 + 4 + 4 + read-write + + + HCUP5 + desc HCUP5 + 5 + 5 + read-write + + + HCUP6 + desc HCUP6 + 6 + 6 + read-write + + + HCUP7 + desc HCUP7 + 7 + 7 + read-write + + + HCUP8 + desc HCUP8 + 8 + 8 + read-write + + + HCUP9 + desc HCUP9 + 9 + 9 + read-write + + + HCUP10 + desc HCUP10 + 10 + 10 + read-write + + + HCUP11 + desc HCUP11 + 11 + 11 + read-write + + + HCUP12 + desc HCUP12 + 12 + 12 + read-write + + + + + HCDOR + desc HCDOR + 0x8C + 16 + read-write + 0x0 + 0x1FFF + + + HCDO0 + desc HCDO0 + 0 + 0 + read-write + + + HCDO1 + desc HCDO1 + 1 + 1 + read-write + + + HCDO2 + desc HCDO2 + 2 + 2 + read-write + + + HCDO3 + desc HCDO3 + 3 + 3 + read-write + + + HCDO4 + desc HCDO4 + 4 + 4 + read-write + + + HCDO5 + desc HCDO5 + 5 + 5 + read-write + + + HCDO6 + desc HCDO6 + 6 + 6 + read-write + + + HCDO7 + desc HCDO7 + 7 + 7 + read-write + + + HCDO8 + desc HCDO8 + 8 + 8 + read-write + + + HCDO9 + desc HCDO9 + 9 + 9 + read-write + + + HCDO10 + desc HCDO10 + 10 + 10 + read-write + + + HCDO11 + desc HCDO11 + 11 + 11 + read-write + + + HCDO12 + desc HCDO12 + 12 + 12 + read-write + + + + + ICONR + desc ICONR + 0x90 + 16 + read-write + 0x0 + 0xFF + + + ITEN1 + desc ITEN1 + 0 + 0 + read-write + + + ITEN2 + desc ITEN2 + 1 + 1 + read-write + + + ITEN3 + desc ITEN3 + 2 + 2 + read-write + + + ITEN4 + desc ITEN4 + 3 + 3 + read-write + + + ITEN5 + desc ITEN5 + 4 + 4 + read-write + + + ITEN6 + desc ITEN6 + 5 + 5 + read-write + + + ITEN7 + desc ITEN7 + 6 + 6 + read-write + + + ITEN8 + desc ITEN8 + 7 + 7 + read-write + + + + + ECONR + desc ECONR + 0x94 + 16 + read-write + 0x0 + 0xFF + + + ETEN1 + desc ETEN1 + 0 + 0 + read-write + + + ETEN2 + desc ETEN2 + 1 + 1 + read-write + + + ETEN3 + desc ETEN3 + 2 + 2 + read-write + + + ETEN4 + desc ETEN4 + 3 + 3 + read-write + + + ETEN5 + desc ETEN5 + 4 + 4 + read-write + + + ETEN6 + desc ETEN6 + 5 + 5 + read-write + + + ETEN7 + desc ETEN7 + 6 + 6 + read-write + + + ETEN8 + desc ETEN8 + 7 + 7 + read-write + + + + + FCONR + desc FCONR + 0x98 + 16 + read-write + 0x0 + 0x7707 + + + NOFIENTG + desc NOFIENTG + 0 + 0 + read-write + + + NOFICKTG + desc NOFICKTG + 2 + 1 + read-write + + + NOFIENCA + desc NOFIENCA + 8 + 8 + read-write + + + NOFICKCA + desc NOFICKCA + 10 + 9 + read-write + + + NOFIENCB + desc NOFIENCB + 12 + 12 + read-write + + + NOFICKCB + desc NOFICKCB + 14 + 13 + read-write + + + + + STFLR + desc STFLR + 0x9C + 16 + read-write + 0x0 + 0xFF + + + CMPF1 + desc CMPF1 + 0 + 0 + read-write + + + CMPF2 + desc CMPF2 + 1 + 1 + read-write + + + CMPF3 + desc CMPF3 + 2 + 2 + read-write + + + CMPF4 + desc CMPF4 + 3 + 3 + read-write + + + CMPF5 + desc CMPF5 + 4 + 4 + read-write + + + CMPF6 + desc CMPF6 + 5 + 5 + read-write + + + CMPF7 + desc CMPF7 + 6 + 6 + read-write + + + CMPF8 + desc CMPF8 + 7 + 7 + read-write + + + + + BCONR1 + desc BCONR1 + 0xC0 + 16 + read-write + 0x0 + 0x7 + + + BEN + desc BEN + 0 + 0 + read-write + + + BSE0 + desc BSE0 + 1 + 1 + read-write + + + BSE1 + desc BSE1 + 2 + 2 + read-write + + + + + BCONR2 + desc BCONR2 + 0xC8 + 16 + read-write + 0x0 + 0x7 + + + BEN + desc BEN + 0 + 0 + read-write + + + BSE0 + desc BSE0 + 1 + 1 + read-write + + + BSE1 + desc BSE1 + 2 + 2 + read-write + + + + + BCONR3 + desc BCONR3 + 0xD0 + 16 + read-write + 0x0 + 0x7 + + + BEN + desc BEN + 0 + 0 + read-write + + + BSE0 + desc BSE0 + 1 + 1 + read-write + + + BSE1 + desc BSE1 + 2 + 2 + read-write + + + + + BCONR4 + desc BCONR4 + 0xD8 + 16 + read-write + 0x0 + 0x7 + + + BEN + desc BEN + 0 + 0 + read-write + + + BSE0 + desc BSE0 + 1 + 1 + read-write + + + BSE1 + desc BSE1 + 2 + 2 + read-write + + + + + CCONR1 + desc CCONR1 + 0x100 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR2 + desc CCONR2 + 0x104 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR3 + desc CCONR3 + 0x108 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR4 + desc CCONR4 + 0x10C + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR5 + desc CCONR5 + 0x110 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR6 + desc CCONR6 + 0x114 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR7 + desc CCONR7 + 0x118 + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + CCONR8 + desc CCONR8 + 0x11C + 16 + read-write + 0x0 + 0x7371 + + + CAPMD + desc CAPMD + 0 + 0 + read-write + + + HICP0 + desc HICP0 + 4 + 4 + read-write + + + HICP1 + desc HICP1 + 5 + 5 + read-write + + + HICP2 + desc HICP2 + 6 + 6 + read-write + + + HICP3 + desc HICP3 + 8 + 8 + read-write + + + HICP4 + desc HICP4 + 9 + 9 + read-write + + + NOFIENCP + desc NOFIENCP + 12 + 12 + read-write + + + NOFICKCP + desc NOFICKCP + 14 + 13 + read-write + + + + + PCONR1 + desc PCONR1 + 0x140 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR2 + desc PCONR2 + 0x144 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR3 + desc PCONR3 + 0x148 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR4 + desc PCONR4 + 0x14C + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR5 + desc PCONR5 + 0x150 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR6 + desc PCONR6 + 0x154 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR7 + desc PCONR7 + 0x158 + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + PCONR8 + desc PCONR8 + 0x15C + 16 + read-write + 0x0 + 0x13FF + + + STAC + desc STAC + 1 + 0 + read-write + + + STPC + desc STPC + 3 + 2 + read-write + + + CMPC + desc CMPC + 5 + 4 + read-write + + + PERC + desc PERC + 7 + 6 + read-write + + + FORC + desc FORC + 9 + 8 + read-write + + + OUTEN + desc OUTEN + 12 + 12 + read-write + + + + + + + TMRA2 + desc TMRA + 0x40015400 + + 0x0 + 0x160 + + + + TMRA3 + desc TMRA + 0x40015800 + + 0x0 + 0x160 + + + + TMRA4 + desc TMRA + 0x40015C00 + + 0x0 + 0x160 + + + + TMRA5 + desc TMRA + 0x40016000 + + 0x0 + 0x160 + + + + TMRA6 + desc TMRA + 0x40016400 + + 0x0 + 0x160 + + + + TRNG + desc TRNG + 0x40041000 + + 0x0 + 0x14 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x3 + + + EN + desc EN + 0 + 0 + read-write + + + RUN + desc RUN + 1 + 1 + read-write + + + + + MR + desc MR + 0x4 + 32 + read-write + 0x12 + 0x1D + + + LOAD + desc LOAD + 0 + 0 + read-write + + + CNT + desc CNT + 4 + 2 + read-write + + + + + DR0 + desc DR0 + 0xC + 32 + read-only + 0x8000000 + 0xFFFFFFFF + + + DR1 + desc DR1 + 0x10 + 32 + read-only + 0x8000200 + 0xFFFFFFFF + + + + + USART1 + desc USART + 0x4001D000 + + 0x0 + 0x1C + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x101EB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + RTOF + desc RTOF + 8 + 8 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + DR + desc DR + 0x4 + 32 + read-write + 0x1FF + 0x1FF03FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + RDR + desc RDR + 24 + 16 + read-write + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFFFF + 0xFF7F + + + DIV_FRACTION + desc DIV_FRACTION + 6 + 0 + read-write + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xF11B96FF + + + RTOE + desc RTOE + 0 + 0 + read-write + + + RTOIE + desc RTOIE + 1 + 1 + read-write + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + write-only + + + CFE + desc CFE + 17 + 17 + write-only + + + CORE + desc CORE + 19 + 19 + write-only + + + CRTOF + desc CRTOF + 20 + 20 + write-only + + + MS + desc MS + 24 + 24 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + FBME + desc FBME + 29 + 29 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x0 + 0x3801 + + + MPE + desc MPE + 0 + 0 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0xE00220 + + + SCEN + desc SCEN + 5 + 5 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + BCN + desc BCN + 23 + 21 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0x3 + + + PSC + desc PSC + 1 + 0 + read-write + + + + + + + USART2 + desc USART + 0x4001D400 + + 0x0 + 0x1C + + + + USART3 + desc USART + 0x40021000 + + 0x0 + 0x1C + + + + USART4 + desc USART + 0x40021400 + + 0x0 + 0x1C + + + + USBFS + desc USBFS + 0x400C0000 + + 0x0 + 0xE04 + + + + GVBUSCFG + desc GVBUSCFG + 0x0 + 32 + read-write + 0x0 + 0xC0 + + + VBUSOVEN + desc VBUSOVEN + 6 + 6 + read-write + + + VBUSVAL + desc VBUSVAL + 7 + 7 + read-write + + + + + GAHBCFG + desc GAHBCFG + 0x8 + 32 + read-write + 0x0 + 0x1BF + + + GINTMSK + desc GINTMSK + 0 + 0 + read-write + + + HBSTLEN + desc HBSTLEN + 4 + 1 + read-write + + + DMAEN + desc DMAEN + 5 + 5 + read-write + + + TXFELVL + desc TXFELVL + 7 + 7 + read-write + + + PTXFELVL + desc PTXFELVL + 8 + 8 + read-write + + + + + GUSBCFG + desc GUSBCFG + 0xC + 32 + read-write + 0xA00 + 0x60003C47 + + + TOCAL + desc TOCAL + 2 + 0 + read-write + + + PHYSEL + desc PHYSEL + 6 + 6 + read-write + + + TRDT + desc TRDT + 13 + 10 + read-write + + + FHMOD + desc FHMOD + 29 + 29 + read-write + + + FDMOD + desc FDMOD + 30 + 30 + read-write + + + + + GRSTCTL + desc GRSTCTL + 0x10 + 32 + read-write + 0x80000000 + 0xC00007F7 + + + CSRST + desc CSRST + 0 + 0 + read-write + + + HSRST + desc HSRST + 1 + 1 + read-write + + + FCRST + desc FCRST + 2 + 2 + read-write + + + RXFFLSH + desc RXFFLSH + 4 + 4 + read-write + + + TXFFLSH + desc TXFFLSH + 5 + 5 + read-write + + + TXFNUM + desc TXFNUM + 10 + 6 + read-write + + + DMAREQ + desc DMAREQ + 30 + 30 + read-only + + + AHBIDL + desc AHBIDL + 31 + 31 + read-only + + + + + GINTSTS + desc GINTSTS + 0x14 + 32 + read-only + 0x14000020 + 0xF77CFCFB + + + CMOD + desc CMOD + 0 + 0 + read-only + + + MMIS + desc MMIS + 1 + 1 + read-write + + + SOF + desc SOF + 3 + 3 + read-write + + + RXFNE + desc RXFNE + 4 + 4 + read-only + + + NPTXFE + desc NPTXFE + 5 + 5 + read-only + + + GINAKEFF + desc GINAKEFF + 6 + 6 + read-only + + + GONAKEFF + desc GONAKEFF + 7 + 7 + read-only + + + ESUSP + desc ESUSP + 10 + 10 + read-write + + + USBSUSP + desc USBSUSP + 11 + 11 + read-write + + + USBRST + desc USBRST + 12 + 12 + read-write + + + ENUMDNE + desc ENUMDNE + 13 + 13 + read-write + + + ISOODRP + desc ISOODRP + 14 + 14 + read-write + + + EOPF + desc EOPF + 15 + 15 + read-write + + + IEPINT + desc IEPINT + 18 + 18 + read-only + + + OEPINT + desc OEPINT + 19 + 19 + read-only + + + IISOIXFR + desc IISOIXFR + 20 + 20 + read-write + + + IPXFR_INCOMPISOOUT + desc IPXFR_INCOMPISOOUT + 21 + 21 + read-write + + + DATAFSUSP + desc DATAFSUSP + 22 + 22 + read-write + + + HPRTINT + desc HPRTINT + 24 + 24 + read-only + + + HCINT + desc HCINT + 25 + 25 + read-only + + + PTXFE + desc PTXFE + 26 + 26 + read-only + + + CIDSCHG + desc CIDSCHG + 28 + 28 + read-write + + + DISCINT + desc DISCINT + 29 + 29 + read-write + + + VBUSVINT + desc VBUSVINT + 30 + 30 + read-write + + + WKUINT + desc WKUINT + 31 + 31 + read-write + + + + + GINTMSK + desc GINTMSK + 0x18 + 32 + read-write + 0x0 + 0xF77CFCFA + + + MMISM + desc MMISM + 1 + 1 + read-write + + + SOFM + desc SOFM + 3 + 3 + read-write + + + RXFNEM + desc RXFNEM + 4 + 4 + read-write + + + NPTXFEM + desc NPTXFEM + 5 + 5 + read-write + + + GINAKEFFM + desc GINAKEFFM + 6 + 6 + read-write + + + GONAKEFFM + desc GONAKEFFM + 7 + 7 + read-write + + + ESUSPM + desc ESUSPM + 10 + 10 + read-write + + + USBSUSPM + desc USBSUSPM + 11 + 11 + read-write + + + USBRSTM + desc USBRSTM + 12 + 12 + read-write + + + ENUMDNEM + desc ENUMDNEM + 13 + 13 + read-write + + + ISOODRPM + desc ISOODRPM + 14 + 14 + read-write + + + EOPFM + desc EOPFM + 15 + 15 + read-write + + + IEPIM + desc IEPIM + 18 + 18 + read-write + + + OEPIM + desc OEPIM + 19 + 19 + read-write + + + IISOIXFRM + desc IISOIXFRM + 20 + 20 + read-write + + + IPXFRM_INCOMPISOOUTM + desc IPXFRM_INCOMPISOOUTM + 21 + 21 + read-write + + + DATAFSUSPM + desc DATAFSUSPM + 22 + 22 + read-write + + + HPRTIM + desc HPRTIM + 24 + 24 + read-write + + + HCIM + desc HCIM + 25 + 25 + read-write + + + PTXFEM + desc PTXFEM + 26 + 26 + read-write + + + CIDSCHGM + desc CIDSCHGM + 28 + 28 + read-write + + + DISCIM + desc DISCIM + 29 + 29 + read-write + + + VBUSVIM + desc VBUSVIM + 30 + 30 + read-write + + + WKUIM + desc WKUIM + 31 + 31 + read-write + + + + + GRXSTSR + desc GRXSTSR + 0x1C + 32 + read-only + 0x0 + 0x1FFFFF + + + CHNUM_EPNUM + desc CHNUM_EPNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + + + GRXSTSP + desc GRXSTSP + 0x20 + 32 + read-only + 0x0 + 0x1FFFFF + + + CHNUM_EPNUM + desc CHNUM_EPNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + + + GRXFSIZ + desc GRXFSIZ + 0x24 + 32 + read-write + 0x140 + 0x7FF + + + RXFD + desc RXFD + 10 + 0 + read-write + + + + + HNPTXFSIZ + desc HNPTXFSIZ + 0x28 + 32 + read-write + 0x2000140 + 0xFFFFFFFF + + + NPTXFSA + desc NPTXFSA + 15 + 0 + read-write + + + NPTXFD + desc NPTXFD + 31 + 16 + read-write + + + + + HNPTXSTS + desc HNPTXSTS + 0x2C + 32 + read-only + 0x80100 + 0x7FFFFFFF + + + NPTXFSAV + desc NPTXFSAV + 15 + 0 + read-only + + + NPTQXSAV + desc NPTQXSAV + 23 + 16 + read-only + + + NPTXQTOP + desc NPTXQTOP + 30 + 24 + read-only + + + + + CID + desc CID + 0x3C + 32 + read-write + 0x12345678 + 0xFFFFFFFF + + + HPTXFSIZ + desc HPTXFSIZ + 0x100 + 32 + read-write + 0x1400280 + 0x7FF0FFF + + + PTXSA + desc PTXSA + 11 + 0 + read-write + + + PTXFD + desc PTXFD + 26 + 16 + read-write + + + + + DIEPTXF1 + desc DIEPTXF1 + 0x104 + 32 + read-write + 0x1000240 + 0x3FF0FFF + + + INEPTXSA + desc INEPTXSA + 11 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 25 + 16 + read-write + + + + + DIEPTXF2 + desc DIEPTXF2 + 0x108 + 32 + read-write + 0x1000340 + 0x3FF0FFF + + + INEPTXSA + desc INEPTXSA + 11 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 25 + 16 + read-write + + + + + DIEPTXF3 + desc DIEPTXF3 + 0x10C + 32 + read-write + 0x1000440 + 0x3FF0FFF + + + INEPTXSA + desc INEPTXSA + 11 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 25 + 16 + read-write + + + + + DIEPTXF4 + desc DIEPTXF4 + 0x110 + 32 + read-write + 0x1000540 + 0x3FF0FFF + + + INEPTXSA + desc INEPTXSA + 11 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 25 + 16 + read-write + + + + + DIEPTXF5 + desc DIEPTXF5 + 0x114 + 32 + read-write + 0x1000640 + 0x3FF0FFF + + + INEPTXSA + desc INEPTXSA + 11 + 0 + read-write + + + INEPTXFD + desc INEPTXFD + 25 + 16 + read-write + + + + + HCFG + desc HCFG + 0x400 + 32 + read-write + 0x200000 + 0x7 + + + FSLSPCS + desc FSLSPCS + 1 + 0 + read-write + + + FSLSS + desc FSLSS + 2 + 2 + read-write + + + + + HFIR + desc HFIR + 0x404 + 32 + read-write + 0xEA60 + 0xFFFF + + + FRIVL + desc FRIVL + 15 + 0 + read-write + + + + + HFNUM + desc HFNUM + 0x408 + 32 + read-only + 0x3FFF + 0xFFFFFFFF + + + FRNUM + desc FRNUM + 15 + 0 + read-only + + + FTREM + desc FTREM + 31 + 16 + read-only + + + + + HPTXSTS + desc HPTXSTS + 0x410 + 32 + read-only + 0x80100 + 0xFFFFFFFF + + + PTXFSAVL + desc PTXFSAVL + 15 + 0 + read-only + + + PTXQSAV + desc PTXQSAV + 23 + 16 + read-only + + + PTXQTOP + desc PTXQTOP + 31 + 24 + read-only + + + + + HAINT + desc HAINT + 0x414 + 32 + read-only + 0x0 + 0xFFF + + + HAINT + desc HAINT + 11 + 0 + read-only + + + + + HAINTMSK + desc HAINTMSK + 0x418 + 32 + read-write + 0x0 + 0xFFF + + + HAINTM + desc HAINTM + 11 + 0 + read-write + + + + + HPRT + desc HPRT + 0x440 + 32 + read-only + 0x0 + 0x61DCF + + + PCSTS + desc PCSTS + 0 + 0 + read-only + + + PCDET + desc PCDET + 1 + 1 + read-write + + + PENA + desc PENA + 2 + 2 + read-write + + + PENCHNG + desc PENCHNG + 3 + 3 + read-write + + + PRES + desc PRES + 6 + 6 + read-write + + + PSUSP + desc PSUSP + 7 + 7 + read-write + + + PRST + desc PRST + 8 + 8 + read-write + + + PLSTS + desc PLSTS + 11 + 10 + read-only + + + PWPR + desc PWPR + 12 + 12 + read-write + + + PSPD + desc PSPD + 18 + 17 + read-only + + + + + HCCHAR0 + desc HCCHAR0 + 0x500 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT0 + desc HCINT0 + 0x508 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK0 + desc HCINTMSK0 + 0x50C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ0 + desc HCTSIZ0 + 0x510 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA0 + desc HCDMA0 + 0x514 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR1 + desc HCCHAR1 + 0x520 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT1 + desc HCINT1 + 0x528 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK1 + desc HCINTMSK1 + 0x52C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ1 + desc HCTSIZ1 + 0x530 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA1 + desc HCDMA1 + 0x534 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR2 + desc HCCHAR2 + 0x540 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT2 + desc HCINT2 + 0x548 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK2 + desc HCINTMSK2 + 0x54C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ2 + desc HCTSIZ2 + 0x550 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA2 + desc HCDMA2 + 0x554 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR3 + desc HCCHAR3 + 0x560 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT3 + desc HCINT3 + 0x568 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK3 + desc HCINTMSK3 + 0x56C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ3 + desc HCTSIZ3 + 0x570 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA3 + desc HCDMA3 + 0x574 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR4 + desc HCCHAR4 + 0x580 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT4 + desc HCINT4 + 0x588 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK4 + desc HCINTMSK4 + 0x58C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ4 + desc HCTSIZ4 + 0x590 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA4 + desc HCDMA4 + 0x594 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR5 + desc HCCHAR5 + 0x5A0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT5 + desc HCINT5 + 0x5A8 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK5 + desc HCINTMSK5 + 0x5AC + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ5 + desc HCTSIZ5 + 0x5B0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA5 + desc HCDMA5 + 0x5B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR6 + desc HCCHAR6 + 0x5C0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT6 + desc HCINT6 + 0x5C8 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK6 + desc HCINTMSK6 + 0x5CC + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ6 + desc HCTSIZ6 + 0x5D0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA6 + desc HCDMA6 + 0x5D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR7 + desc HCCHAR7 + 0x5E0 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT7 + desc HCINT7 + 0x5E8 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK7 + desc HCINTMSK7 + 0x5EC + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ7 + desc HCTSIZ7 + 0x5F0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA7 + desc HCDMA7 + 0x5F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR8 + desc HCCHAR8 + 0x600 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT8 + desc HCINT8 + 0x608 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK8 + desc HCINTMSK8 + 0x60C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ8 + desc HCTSIZ8 + 0x610 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA8 + desc HCDMA8 + 0x614 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR9 + desc HCCHAR9 + 0x620 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT9 + desc HCINT9 + 0x628 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK9 + desc HCINTMSK9 + 0x62C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ9 + desc HCTSIZ9 + 0x630 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA9 + desc HCDMA9 + 0x634 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR10 + desc HCCHAR10 + 0x640 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT10 + desc HCINT10 + 0x648 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK10 + desc HCINTMSK10 + 0x64C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ10 + desc HCTSIZ10 + 0x650 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA10 + desc HCDMA10 + 0x654 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + HCCHAR11 + desc HCCHAR11 + 0x660 + 32 + read-write + 0x0 + 0xFFCEFFFF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSDEV + desc LSDEV + 17 + 17 + read-write + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + DAD + desc DAD + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCINT11 + desc HCINT11 + 0x668 + 32 + read-write + 0x0 + 0x7BB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + CHH + desc CHH + 1 + 1 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + TXERR + desc TXERR + 7 + 7 + read-write + + + BBERR + desc BBERR + 8 + 8 + read-write + + + FRMOR + desc FRMOR + 9 + 9 + read-write + + + DTERR + desc DTERR + 10 + 10 + read-write + + + + + HCINTMSK11 + desc HCINTMSK11 + 0x66C + 32 + read-write + 0x0 + 0x7BB + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + CHHM + desc CHHM + 1 + 1 + read-write + + + STALLM + desc STALLM + 3 + 3 + read-write + + + NAKM + desc NAKM + 4 + 4 + read-write + + + ACKM + desc ACKM + 5 + 5 + read-write + + + TXERRM + desc TXERRM + 7 + 7 + read-write + + + BBERRM + desc BBERRM + 8 + 8 + read-write + + + FRMORM + desc FRMORM + 9 + 9 + read-write + + + DTERRM + desc DTERRM + 10 + 10 + read-write + + + + + HCTSIZ11 + desc HCTSIZ11 + 0x670 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + DPID + desc DPID + 30 + 29 + read-write + + + + + HCDMA11 + desc HCDMA11 + 0x674 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DCFG + desc DCFG + 0x800 + 32 + read-write + 0x8200000 + 0x1FF7 + + + DSPD + desc DSPD + 1 + 0 + read-write + + + NZLSOHSK + desc NZLSOHSK + 2 + 2 + read-write + + + DAD + desc DAD + 10 + 4 + read-write + + + PFIVL + desc PFIVL + 12 + 11 + read-write + + + + + DCTL + desc DCTL + 0x804 + 32 + read-write + 0x2 + 0xF8F + + + RWUSIG + desc RWUSIG + 0 + 0 + read-write + + + SDIS + desc SDIS + 1 + 1 + read-write + + + GINSTS + desc GINSTS + 2 + 2 + read-only + + + GONSTS + desc GONSTS + 3 + 3 + read-only + + + SGINAK + desc SGINAK + 7 + 7 + write-only + + + CGINAK + desc CGINAK + 8 + 8 + write-only + + + SGONAK + desc SGONAK + 9 + 9 + write-only + + + CGONAK + desc CGONAK + 10 + 10 + write-only + + + POPRGDNE + desc POPRGDNE + 11 + 11 + read-write + + + + + DSTS + desc DSTS + 0x808 + 32 + read-only + 0x2 + 0x3FFF0F + + + SUSPSTS + desc SUSPSTS + 0 + 0 + read-only + + + ENUMSPD + desc ENUMSPD + 2 + 1 + read-only + + + EERR + desc EERR + 3 + 3 + read-only + + + FNSOF + desc FNSOF + 21 + 8 + read-only + + + + + DIEPMSK + desc DIEPMSK + 0x810 + 32 + read-write + 0x0 + 0x7B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + TOM + desc TOM + 3 + 3 + read-write + + + ITTXFEMSK + desc ITTXFEMSK + 4 + 4 + read-write + + + INEPNMM + desc INEPNMM + 5 + 5 + read-write + + + INEPNEM + desc INEPNEM + 6 + 6 + read-write + + + + + DOEPMSK + desc DOEPMSK + 0x814 + 32 + read-write + 0x0 + 0x1B + + + XFRCM + desc XFRCM + 0 + 0 + read-write + + + EPDM + desc EPDM + 1 + 1 + read-write + + + STUPM + desc STUPM + 3 + 3 + read-write + + + OTEPDM + desc OTEPDM + 4 + 4 + read-write + + + + + DAINT + desc DAINT + 0x818 + 32 + read-write + 0x0 + 0x3F003F + + + IEPINT + desc IEPINT + 5 + 0 + read-write + + + OEPINT + desc OEPINT + 21 + 16 + read-write + + + + + DAINTMSK + desc DAINTMSK + 0x81C + 32 + read-write + 0x0 + 0x3F003F + + + IEPINTM + desc IEPINTM + 5 + 0 + read-write + + + OEPINTM + desc OEPINTM + 21 + 16 + read-write + + + + + DIEPEMPMSK + desc DIEPEMPMSK + 0x834 + 32 + read-write + 0x0 + 0x3F + + + INEPTXFEM + desc INEPTXFEM + 5 + 0 + read-write + + + + + DIEPCTL0 + desc DIEPCTL0 + 0x900 + 32 + read-write + 0x8000 + 0xCFEE8003 + + + MPSIZ + desc MPSIZ + 1 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT0 + desc DIEPINT0 + 0x908 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ0 + desc DIEPTSIZ0 + 0x910 + 32 + read-write + 0x0 + 0x18007F + + + XFRSIZ + desc XFRSIZ + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 20 + 19 + read-write + + + + + DIEPDMA0 + desc DIEPDMA0 + 0x914 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS0 + desc DTXFSTS0 + 0x918 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL1 + desc DIEPCTL1 + 0x920 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT1 + desc DIEPINT1 + 0x928 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ1 + desc DIEPTSIZ1 + 0x930 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DIEPDMA1 + desc DIEPDMA1 + 0x934 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS1 + desc DTXFSTS1 + 0x938 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL2 + desc DIEPCTL2 + 0x940 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT2 + desc DIEPINT2 + 0x948 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ2 + desc DIEPTSIZ2 + 0x950 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DIEPDMA2 + desc DIEPDMA2 + 0x954 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS2 + desc DTXFSTS2 + 0x958 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL3 + desc DIEPCTL3 + 0x960 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT3 + desc DIEPINT3 + 0x968 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ3 + desc DIEPTSIZ3 + 0x970 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DIEPDMA3 + desc DIEPDMA3 + 0x974 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS3 + desc DTXFSTS3 + 0x978 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL4 + desc DIEPCTL4 + 0x980 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT4 + desc DIEPINT4 + 0x988 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ4 + desc DIEPTSIZ4 + 0x990 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DIEPDMA4 + desc DIEPDMA4 + 0x994 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS4 + desc DTXFSTS4 + 0x998 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DIEPCTL5 + desc DIEPCTL5 + 0x9A0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-write + + + EONUM_DPID + desc EONUM_DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-only + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID_SEVNFRM + desc SD0PID_SEVNFRM + 28 + 28 + read-write + + + SODDFRM + desc SODDFRM + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT5 + desc DIEPINT5 + 0x9A8 + 32 + read-write + 0x80 + 0xDB + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + TOC + desc TOC + 3 + 3 + read-write + + + TTXFE + desc TTXFE + 4 + 4 + read-write + + + INEPNE + desc INEPNE + 6 + 6 + read-write + + + TXFE + desc TXFE + 7 + 7 + read-only + + + + + DIEPTSIZ5 + desc DIEPTSIZ5 + 0x9B0 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DIEPDMA5 + desc DIEPDMA5 + 0x9B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS5 + desc DTXFSTS5 + 0x9B8 + 32 + read-only + 0x100 + 0xFFFF + + + INEPTFSAV + desc INEPTFSAV + 15 + 0 + read-only + + + + + DOEPCTL0 + desc DOEPCTL0 + 0xB00 + 32 + read-write + 0x8000 + 0xCC3E8003 + + + MPSIZ + desc MPSIZ + 1 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT0 + desc DOEPINT0 + 0xB08 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ0 + desc DOEPTSIZ0 + 0xB10 + 32 + read-write + 0x0 + 0x6008007F + + + XFRSIZ + desc XFRSIZ + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 19 + 19 + read-write + + + STUPCNT + desc STUPCNT + 30 + 29 + read-write + + + + + DOEPDMA0 + desc DOEPDMA0 + 0xB14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL1 + desc DOEPCTL1 + 0xB20 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT1 + desc DOEPINT1 + 0xB28 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ1 + desc DOEPTSIZ1 + 0xB30 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA1 + desc DOEPDMA1 + 0xB34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL2 + desc DOEPCTL2 + 0xB40 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT2 + desc DOEPINT2 + 0xB48 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ2 + desc DOEPTSIZ2 + 0xB50 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA2 + desc DOEPDMA2 + 0xB54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL3 + desc DOEPCTL3 + 0xB60 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT3 + desc DOEPINT3 + 0xB68 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ3 + desc DOEPTSIZ3 + 0xB70 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA3 + desc DOEPDMA3 + 0xB74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL4 + desc DOEPCTL4 + 0xB80 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT4 + desc DOEPINT4 + 0xB88 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ4 + desc DOEPTSIZ4 + 0xB90 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA4 + desc DOEPDMA4 + 0xB94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL5 + desc DOEPCTL5 + 0xBA0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPSIZ + desc MPSIZ + 10 + 0 + read-write + + + USBAEP + desc USBAEP + 15 + 15 + read-only + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYP + desc EPTYP + 19 + 18 + read-write + + + SNPM + desc SNPM + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + read-write + + + SNAK + desc SNAK + 27 + 27 + read-write + + + SD0PID + desc SD0PID + 28 + 28 + read-write + + + SD1PID + desc SD1PID + 29 + 29 + read-write + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT5 + desc DOEPINT5 + 0xBA8 + 32 + read-write + 0x0 + 0x5B + + + XFRC + desc XFRC + 0 + 0 + read-write + + + EPDISD + desc EPDISD + 1 + 1 + read-write + + + STUP + desc STUP + 3 + 3 + read-write + + + OTEPDIS + desc OTEPDIS + 4 + 4 + read-write + + + B2BSTUP + desc B2BSTUP + 6 + 6 + read-write + + + + + DOEPTSIZ5 + desc DOEPTSIZ5 + 0xBB0 + 32 + read-write + 0x0 + 0x1FFFFFFF + + + XFRSIZ + desc XFRSIZ + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + + + DOEPDMA5 + desc DOEPDMA5 + 0xBB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + GCCTL + desc GCCTL + 0xE00 + 32 + read-write + 0x0 + 0x3 + + + STPPCLK + desc STPPCLK + 0 + 0 + read-write + + + GATEHCLK + desc GATEHCLK + 1 + 1 + read-write + + + + + + + WDT + desc WDT + 0x40049000 + + 0x0 + 0xC + + + + CR + desc CR + 0x0 + 32 + read-write + 0x80010FF3 + 0x80010FF3 + + + PERI + desc PERI + 1 + 0 + read-write + + + CKS + desc CKS + 7 + 4 + read-write + + + WDPT + desc WDPT + 11 + 8 + read-write + + + SLPOFF + desc SLPOFF + 16 + 16 + read-write + + + ITS + desc ITS + 31 + 31 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-write + 0x0 + 0x3FFFF + + + CNT + desc CNT + 15 + 0 + read-only + + + UDF + desc UDF + 16 + 16 + read-write + + + REF + desc REF + 17 + 17 + read-write + + + + + RR + desc RR + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + RF + desc RF + 15 + 0 + read-write + + + + + + + diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f460.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f460.c new file mode 100644 index 0000000000..758fe17675 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f460.c @@ -0,0 +1,241 @@ +/** + ******************************************************************************* + * @file system_hc32f460.c + * @brief This file provides two functions and two global variables to be called + * from user application. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +#include "hc32_ll_def.h" + +/** + * @addtogroup CMSIS + * @{ + */ + +/** + * @addtogroup HC32F460_System + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ +/** + * @defgroup HC32F460_System_Local_Macros HC32F460 System Local Macros + * @{ + */ +#define HRC_16MHz_VALUE (16000000UL) /*!< Internal high speed RC freq. */ +#define HRC_20MHz_VALUE (20000000UL) /*!< Internal high speed RC freq. */ +/* HRC select */ +#define HRC_FREQ_MON() (*((volatile uint32_t *)(0x40010684UL))) + +/* Vector Table base offset field */ +#ifndef VECT_TAB_OFFSET +#define VECT_TAB_OFFSET (0x0UL) /*!< This value must be a multiple of 0x400. */ +#endif + +/* Re-define main function */ +#ifndef RE_DEFINE_MAIN +#define RE_DEFINE_MAIN (1) /*!< Non-zero value to re-define main function. */ +#endif +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Global_Variable + * @{ + */ + +/*!< System clock frequency (Core clock) */ +uint32_t SystemCoreClock; +/*!< High speed RC frequency (HCR clock) */ +uint32_t HRC_VALUE; + +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @addtogroup HC32F460_System_Global_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. Initialize the System and update + * the SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings */ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */ +#endif + SystemCoreClockUpdate(); +#if defined (ROM_EXT_QSPI) + SystemInit_QspiMem(); +#endif /* ROM_EXT_QSPI */ + /* Configure the Vector Table relocation */ + SCB->VTOR = VECT_TAB_OFFSET; /* Vector Table Relocation */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint8_t u8SysClkSrc; + uint32_t plln; + uint32_t pllp; + uint32_t pllm; + uint32_t u32PllSrcFreq; + + /* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */ + if (1UL == (HRC_FREQ_MON() & 1UL)) { + HRC_VALUE = HRC_16MHz_VALUE; + } else { + HRC_VALUE = HRC_20MHz_VALUE; + } + u8SysClkSrc = CM_CMU->CKSWR & CMU_CKSWR_CKSW; + switch (u8SysClkSrc) { + case 0x00U: /* use internal high speed RC */ + SystemCoreClock = HRC_VALUE; + break; + case 0x01U: /* use internal middle speed RC */ + SystemCoreClock = MRC_VALUE; + break; + case 0x02U: /* use internal low speed RC */ + SystemCoreClock = LRC_VALUE; + break; + case 0x03U: /* use external high speed OSC */ + SystemCoreClock = XTAL_VALUE; + break; + case 0x04U: /* use external low speed OSC */ + SystemCoreClock = XTAL32_VALUE; + break; + case 0x05U: /* use MPLL */ + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + plln = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLN) >> CMU_PLLCFGR_MPLLN_POS; + pllp = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLP) >> CMU_PLLCFGR_MPLLP_POS; + pllm = (CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLM) >> CMU_PLLCFGR_MPLLM_POS; + if (0UL == (CM_CMU->PLLCFGR & CMU_PLLCFGR_PLLSRC)) { /* use external highspeed OSC as PLL source */ + u32PllSrcFreq = XTAL_VALUE; + } else { /* use internal high RC as PLL source */ + u32PllSrcFreq = HRC_VALUE; + } + SystemCoreClock = u32PllSrcFreq / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL); + break; + default: + break; + } +} + +#if (RE_DEFINE_MAIN) +#if (defined (__CC_ARM) || defined (__CLANG_ARM)) || \ + (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +extern int32_t $Super$$main(void); +/* re-define main function */ +int $Sub$$main(void) +{ + SystemCoreClockUpdate(); + $Super$$main(); + return 0; +} +#elif defined (__ICCARM__) +extern int32_t main(void); +/* __low_level_init will auto called by IAR cstartup */ +extern void __iar_data_init3(void); +int __low_level_init(void) +{ + /* call IAR table copy function. */ + __iar_data_init3(); + SystemCoreClockUpdate(); + main(); + return 0; +} +#endif +#endif /* RE_DEFINE_MAIN */ + +#if defined (ROM_EXT_QSPI) +/** + * @brief Initialize the QSPI memory. + * @param None + * @retval None + */ +__WEAKDEF void SystemInit_QspiMem(void) +{ + /* QSPI configure */ + CM_GPIO->PWPR = 0xA501U; + /* High driver */ + CM_GPIO->PCRC7 = 0x0120U; + CM_GPIO->PCRC6 = 0x0120U; + CM_GPIO->PCRD8 = 0x0120U; + CM_GPIO->PCRD9 = 0x0120U; + CM_GPIO->PCRD10 = 0x0120U; + CM_GPIO->PCRD11 = 0x0120U; + /* Set function */ + CM_GPIO->PFSRC7 = 0x07U; + CM_GPIO->PFSRC6 = 0x07U; + CM_GPIO->PFSRD8 = 0x07U; + CM_GPIO->PFSRD9 = 0x07U; + CM_GPIO->PFSRD10 = 0x07U; + CM_GPIO->PFSRD11 = 0x07U; + /* qspi configure */ + CM_PWC->FCG1 &= ~0x00000008UL; + CM_QSPI->CR = 0x0002000D; + CM_QSPI->CSCR = 0x00000001; + CM_QSPI->FCR = 0x00008332; + /* XIP */ + CM_QSPI->XCMD = 0x20; + CM_QSPI->CR |= QSPI_CR_XIPE; +} +#endif /* ROM_EXT_QSPI */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_common_tables.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_common_tables.h new file mode 100644 index 0000000000..721b18dd2d --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_common_tables.h @@ -0,0 +1,517 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + /* Double Precision Float CFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + extern const uint16_t armBitRevTable[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16) + extern const uint64_t twiddleCoefF64_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32) + extern const uint64_t twiddleCoefF64_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64) + extern const uint64_t twiddleCoefF64_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128) + extern const uint64_t twiddleCoefF64_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256) + extern const uint64_t twiddleCoefF64_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512) + extern const uint64_t twiddleCoefF64_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024) + extern const uint64_t twiddleCoefF64_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048) + extern const uint64_t twiddleCoefF64_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096) + extern const uint64_t twiddleCoefF64_4096[8192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) + extern const float32_t twiddleCoef_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + extern const float32_t twiddleCoef_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) + extern const float32_t twiddleCoef_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + extern const float32_t twiddleCoef_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) + extern const float32_t twiddleCoef_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + extern const float32_t twiddleCoef_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) + extern const float32_t twiddleCoef_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + extern const float32_t twiddleCoef_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + extern const float32_t twiddleCoef_4096[8192]; + #define twiddleCoef twiddleCoef_4096 + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) + extern const q31_t twiddleCoef_16_q31[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + extern const q31_t twiddleCoef_32_q31[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) + extern const q31_t twiddleCoef_64_q31[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + extern const q31_t twiddleCoef_128_q31[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) + extern const q31_t twiddleCoef_256_q31[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + extern const q31_t twiddleCoef_512_q31[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) + extern const q31_t twiddleCoef_1024_q31[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + extern const q31_t twiddleCoef_2048_q31[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + extern const q31_t twiddleCoef_4096_q31[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + extern const q15_t twiddleCoef_16_q15[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + extern const q15_t twiddleCoef_32_q15[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) + extern const q15_t twiddleCoef_64_q15[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + extern const q15_t twiddleCoef_128_q15[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) + extern const q15_t twiddleCoef_256_q15[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + extern const q15_t twiddleCoef_512_q15[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) + extern const q15_t twiddleCoef_1024_q15[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + extern const q15_t twiddleCoef_2048_q15[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + extern const q15_t twiddleCoef_4096_q15[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + /* Double Precision Float RFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32) + extern const uint64_t twiddleCoefF64_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64) + extern const uint64_t twiddleCoefF64_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128) + extern const uint64_t twiddleCoefF64_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256) + extern const uint64_t twiddleCoefF64_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512) + extern const uint64_t twiddleCoefF64_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024) + extern const uint64_t twiddleCoefF64_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048) + extern const uint64_t twiddleCoefF64_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096) + extern const uint64_t twiddleCoefF64_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) + extern const float32_t twiddleCoef_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) + extern const float32_t twiddleCoef_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) + extern const float32_t twiddleCoef_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) + extern const float32_t twiddleCoef_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) + extern const float32_t twiddleCoef_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) + extern const float32_t twiddleCoef_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) + extern const float32_t twiddleCoef_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096) + extern const float32_t twiddleCoef_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* Double precision floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16) + #define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32) + #define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64) + #define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128) + #define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256) + #define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512) + #define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024) + #define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048) + #define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096) + #define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + /* floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) + extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) + extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) + extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) + extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) + extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) + extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) + extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) + #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* fixed-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) + #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) + #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) + #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) + #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) + #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) + #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) + #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) + #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) + extern const float32_t realCoefA[8192]; + extern const float32_t realCoefB[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) + extern const q31_t realCoefAQ31[8192]; + extern const q31_t realCoefBQ31[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) + extern const q15_t realCoefAQ15[8192]; + extern const q15_t realCoefBQ15[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + extern const float32_t Weights_128[256]; + extern const float32_t cos_factors_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + extern const float32_t Weights_512[1024]; + extern const float32_t cos_factors_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + extern const float32_t Weights_2048[4096]; + extern const float32_t cos_factors_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + extern const float32_t Weights_8192[16384]; + extern const float32_t cos_factors_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + extern const q15_t WeightsQ15_128[256]; + extern const q15_t cos_factorsQ15_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + extern const q15_t WeightsQ15_512[1024]; + extern const q15_t cos_factorsQ15_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + extern const q15_t WeightsQ15_2048[4096]; + extern const q15_t cos_factorsQ15_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + extern const q15_t WeightsQ15_8192[16384]; + extern const q15_t cos_factorsQ15_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + extern const q31_t WeightsQ31_128[256]; + extern const q31_t cos_factorsQ31_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + extern const q31_t WeightsQ31_512[1024]; + extern const q31_t cos_factorsQ31_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + extern const q31_t WeightsQ31_2048[4096]; + extern const q31_t cos_factorsQ31_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + extern const q31_t WeightsQ31_8192[16384]; + extern const q31_t cos_factorsQ31_8192[8192]; + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) + extern const q15_t armRecipTableQ15[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + extern const q31_t armRecipTableQ31[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + /* Tables for Fast Math Sine and Cosine */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) + extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) + extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) + extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if defined(ARM_MATH_MVEI) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) + extern const q31_t sqrtTable_Q31[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + + #if defined(ARM_MATH_MVEI) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) + extern const q15_t sqrtTable_Q15[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + extern const float32_t exp_tab[8]; + extern const float32_t __logf_lut_f32[8]; +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) +extern const unsigned char hwLUT[256]; +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#endif /* ARM_COMMON_TABLES_H */ + diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_const_structs.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_const_structs.h new file mode 100644 index 0000000000..83984c40cd --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_const_structs.h @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096; + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_helium_utils.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_helium_utils.h new file mode 100644 index 0000000000..7609d329f0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_helium_utils.h @@ -0,0 +1,348 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_helium_utils.h + * Description: Utility functions for Helium development + * + * $Date: 09. September 2019 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_UTILS_HELIUM_H_ +#define _ARM_UTILS_HELIUM_H_ + +/*************************************** + +Definitions available for MVEF and MVEI + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) + +#define INACTIVELANE 0 /* inactive lane content */ + + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */ + +/*************************************** + +Definitions available for MVEF only + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) + +__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in) +{ + float32_t acc; + + acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) + + vgetq_lane(in, 2) + vgetq_lane(in, 3); + + return acc; +} + +/* newton initial guess */ +#define INVSQRT_MAGIC_F32 0x5f3759df + +#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\ +{ \ + float32x4_t tmp; \ + \ + /* tmp = xhalf * x * x */ \ + tmp = vmulq(xStart, xStart); \ + tmp = vmulq(tmp, xHalf); \ + /* (1.5f - xhalf * x * x) */ \ + tmp = vsubq(vdupq_n_f32(1.5f), tmp); \ + /* x = x*(1.5f-xhalf*x*x); */ \ + invSqrt = vmulq(tmp, xStart); \ +} +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */ + +/*************************************** + +Definitions available for MVEI only + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) + + +#include "arm_common_tables.h" + +/* Following functions are used to transpose matrix in f32 and q31 cases */ +__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + static const uint32x4_t vecOffs = { 0, 2, 1, 3 }; + /* + * + * | 0 1 | => | 0 2 | + * | 2 3 | | 1 3 | + * + */ + uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn); + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; + const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; + /* + * + * | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 | + * | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 | + * | 6 7 8 | | 2 5 8 | (row major) | 8 . . . | + * + */ + uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc); + uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]); + + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2); + + pDataDest[8] = pDataSrc[8]; + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest) +{ + /* + * 4x4 Matrix transposition + * is 4 x de-interleave operation + * + * 0 1 2 3 0 4 8 12 + * 4 5 6 7 1 5 9 13 + * 8 9 10 11 2 6 10 14 + * 12 13 14 15 3 7 11 15 + */ + + uint32x4x4_t vecIn; + + vecIn = vld4q((uint32_t const *) pDataSrc); + vstrwq(pDataDest, vecIn.val[0]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[1]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[2]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[3]); + + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve( + uint16_t srcRows, + uint16_t srcCols, + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + uint32x4_t vecOffs; + uint32_t i; + uint32_t blkCnt; + uint32_t const *pDataC; + uint32_t *pDataDestR; + uint32x4_t vecIn; + + vecOffs = vidupq_u32((uint32_t)0, 1); + vecOffs = vecOffs * srcCols; + + i = srcCols; + do + { + pDataC = (uint32_t const *) pDataSrc; + pDataDestR = pDataDest; + + blkCnt = srcRows >> 2; + while (blkCnt > 0U) + { + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq(pDataDestR, vecIn); + pDataDestR += 4; + pDataC = pDataC + srcCols * 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = srcRows & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq_p(pDataDestR, vecIn, p0); + } + + pDataSrc += 1; + pDataDest += srcRows; + } + while (--i); + + return (ARM_MATH_SUCCESS); +} + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) +__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn) +{ + q63x2_t vecTmpLL; + q31x4_t vecTmp0, vecTmp1; + q31_t scale; + q63_t tmp64; + q31x4_t vecNrm, vecDst, vecIdx, vecSignBits; + + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + /* + * index = in >> 24; + */ + vecIdx = vecNrm >> 24; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + vecTmpLL = vmullbq_int(vecNrm, vecTmp0); + + /* + * scale elements 0, 2 + */ + scale = 26 + (vecSignBits[0] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[0] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[2] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[2] = (q31_t) tmp64; + + vecTmpLL = vmulltq_int(vecNrm, vecTmp0); + + /* + * scale elements 1, 3 + */ + scale = 26 + (vecSignBits[1] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[1] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[3] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[3] = (q31_t) tmp64; + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0)); + + return vecDst; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) +__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn) +{ + q31x4_t vecTmpLev, vecTmpLodd, vecSignL; + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecNrm, vecDst, vecIdx, vecSignBits; + + vecDst = vuninitializedq_s16(); + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + + vecIdx = vecNrm >> 8; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + + vecSignBits = vecSignBits >> 1; + + vecTmpLev = vmullbq_int(vecNrm, vecTmp0); + vecTmpLodd = vmulltq_int(vecNrm, vecTmp0); + + vecTmp0 = vecSignBits + 10; + /* + * negate sign to apply register based vshl + */ + vecTmp0 = -vecTmp0; + + /* + * shift even elements + */ + vecSignL = vmovlbq(vecTmp0); + vecTmpLev = vshlq(vecTmpLev, vecSignL); + /* + * shift odd elements + */ + vecSignL = vmovltq(vecTmp0); + vecTmpLodd = vshlq(vecTmpLodd, vecSignL); + /* + * merge and narrow odd and even parts + */ + vecDst = vmovnbq_s32(vecDst, vecTmpLev); + vecDst = vmovntq_s32(vecDst, vecTmpLodd); + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0)); + + return vecDst; +} +#endif + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */ + +#endif diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_math.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_math.h new file mode 100644 index 0000000000..48bee62cd9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_math.h @@ -0,0 +1,8970 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.7.0 + * @date 18. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M and Cortex-A processor + * based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filtering functions + * - Matrix functions + * - Transform functions + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * - Support Vector Machine functions (SVM) + * - Bayes classifier functions + * - Distance functions + * + * The library has generally separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * + * Here is the list of pre-built libraries : + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library is now tested on Fast Models building with cmake. + * Core M0, M7, A5 are tested. + * + * + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP\\Projects\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * There is also a work in progress cmake build. The README file is giving more details. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_LOOPUNROLL: + * + * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions + * + * - ARM_MATH_NEON: + * + * Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions. + * It is not enabled by default when Neon is available because performances are + * dependent on the compiler and target architecture. + * + * - ARM_MATH_NEON_EXPERIMENTAL: + * + * Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of + * of some DSP functions. Experimental Neon versions currently do not have better + * performances than the scalar versions. + * + * - ARM_MATH_HELIUM: + * + * It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_FLOAT16. + * + * - ARM_MATH_MVEF: + * + * Select Helium versions of the f32 algorithms. + * It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI. + * + * - ARM_MATH_MVEI: + * + * Select Helium versions of the int and fixed point algorithms. + * + * - ARM_MATH_FLOAT16: + * + * Float16 implementations of some algorithms (Requires MVE extension). + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |---------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP\\DSP_Lib_TestSuite | DSP_Lib test suite | + * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP\\Include | DSP_Lib include files | + * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries | + * |\b CMSIS\\DSP\\Projects | Projects to rebuild DSP_Lib binaries | + * |\b CMSIS\\DSP\\Source | DSP_Lib source files | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15() + * for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ + +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ + +/** + * @defgroup groupSVM SVM Functions + * This set of functions is implementing SVM classification on 2 classes. + * The training must be done from scikit-learn. The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/SVM.py + * + * If more than 2 classes are needed, the functions in this folder + * will have to be used, as building blocks, to do multi-class classification. + * + * No multi-class classification is provided in this SVM folder. + * + */ + + +/** + * @defgroup groupBayes Bayesian estimators + * + * Implement the naive gaussian Bayes estimator. + * The training must be done from scikit-learn. + * + * The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/Bayes.py + */ + +/** + * @defgroup groupDistance Distance functions + * + * Distance functions for use with clustering algorithms. + * There are distance functions for float vectors and boolean vectors. + * + */ + + +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + + +/* Included for instrinsics definitions */ +#if defined (_MSC_VER ) +#include +#define __STATIC_FORCEINLINE static __forceinline +#define __STATIC_INLINE static __inline +#define __ALIGNED(x) __declspec(align(x)) + +#elif defined (__GNUC_PYTHON__) +#include +#define __ALIGNED(x) __attribute__((aligned(x))) +#define __STATIC_FORCEINLINE static __attribute__((inline)) +#define __STATIC_INLINE static __attribute__((inline)) +#pragma GCC diagnostic ignored "-Wunused-function" +#pragma GCC diagnostic ignored "-Wattributes" + +#else +#include "cmsis_compiler.h" +#endif + + + +#include +#include +#include +#include + + +#define F64_MAX ((float64_t)DBL_MAX) +#define F32_MAX ((float32_t)FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_MAX ((float16_t)FLT_MAX) +#endif + +#define F64_MIN (-DBL_MAX) +#define F32_MIN (-FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_MIN (-(float16_t)FLT_MAX) +#endif + +#define F64_ABSMAX ((float64_t)DBL_MAX) +#define F32_ABSMAX ((float32_t)FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_ABSMAX ((float16_t)FLT_MAX) +#endif + +#define F64_ABSMIN ((float64_t)0.0) +#define F32_ABSMIN ((float32_t)0.0) + +#if defined(ARM_MATH_FLOAT16) +#define F16_ABSMIN ((float16_t)0.0) +#endif + +#define Q31_MAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_MAX ((q15_t)(0x7FFF)) +#define Q7_MAX ((q7_t)(0x7F)) +#define Q31_MIN ((q31_t)(0x80000000L)) +#define Q15_MIN ((q15_t)(0x8000)) +#define Q7_MIN ((q7_t)(0x80)) + +#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_ABSMAX ((q15_t)(0x7FFF)) +#define Q7_ABSMAX ((q7_t)(0x7F)) +#define Q31_ABSMIN ((q31_t)0) +#define Q15_ABSMIN ((q15_t)0) +#define Q7_ABSMIN ((q7_t)0) + +/* evaluate ARM DSP feature */ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define ARM_MATH_DSP 1 +#endif + +#if defined(ARM_MATH_NEON) +#include +#endif + +#if defined (ARM_MATH_HELIUM) + #define ARM_MATH_MVEF + #define ARM_MATH_FLOAT16 +#endif + +#if defined (ARM_MATH_MVEF) + #define ARM_MATH_MVEI + #define ARM_MATH_FLOAT16 +#endif + +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) +#include +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 ((q31_t)(0x100)) +#define DELTA_Q15 ((q15_t)0x5) +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macros for complex numbers + */ + + /* Dimension C vector space */ + #define CMPLX_DIM 2 + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief vector types + */ +#if defined(ARM_MATH_NEON) || defined (ARM_MATH_MVEI) + /** + * @brief 64-bit fractional 128-bit vector data type in 1.63 format + */ + typedef int64x2_t q63x2_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 1.31 format. + */ + typedef int32x4_t q31x4_t; + + /** + * @brief 16-bit fractional 128-bit vector data type with 16-bit alignement in 1.15 format. + */ + typedef __ALIGNED(2) int16x8_t q15x8_t; + + /** + * @brief 8-bit fractional 128-bit vector data type with 8-bit alignement in 1.7 format. + */ + typedef __ALIGNED(1) int8x16_t q7x16_t; + + /** + * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format. + */ + typedef int32x4x2_t q31x4x2_t; + + /** + * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format. + */ + typedef int32x4x4_t q31x4x4_t; + + /** + * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format. + */ + typedef int16x8x2_t q15x8x2_t; + + /** + * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format. + */ + typedef int16x8x4_t q15x8x4_t; + + /** + * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format. + */ + typedef int8x16x2_t q7x16x2_t; + + /** + * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format. + */ + typedef int8x16x4_t q7x16x4_t; + + /** + * @brief 32-bit fractional data type in 9.23 format. + */ + typedef int32_t q23_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 9.23 format. + */ + typedef int32x4_t q23x4_t; + + /** + * @brief 64-bit status 128-bit vector data type. + */ + typedef int64x2_t status64x2_t; + + /** + * @brief 32-bit status 128-bit vector data type. + */ + typedef int32x4_t status32x4_t; + + /** + * @brief 16-bit status 128-bit vector data type. + */ + typedef int16x8_t status16x8_t; + + /** + * @brief 8-bit status 128-bit vector data type. + */ + typedef int8x16_t status8x16_t; + + +#endif + +#if defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF) /* floating point vector*/ + /** + * @brief 32-bit floating-point 128-bit vector type + */ + typedef float32x4_t f32x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector data type + */ + typedef __ALIGNED(2) float16x8_t f16x8_t; +#endif + + /** + * @brief 32-bit floating-point 128-bit vector pair data type + */ + typedef float32x4x2_t f32x4x2_t; + + /** + * @brief 32-bit floating-point 128-bit vector quadruplet data type + */ + typedef float32x4x4_t f32x4x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector pair data type + */ + typedef float16x8x2_t f16x8x2_t; + + /** + * @brief 16-bit floating-point 128-bit vector quadruplet data type + */ + typedef float16x8x4_t f16x8x4_t; +#endif + + /** + * @brief 32-bit ubiquitous 128-bit vector data type + */ + typedef union _any32x4_t + { + float32x4_t f; + int32x4_t i; + } any32x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit ubiquitous 128-bit vector data type + */ + typedef union _any16x8_t + { + float16x8_t f; + int16x8_t i; + } any16x8_t; +#endif + +#endif + +#if defined(ARM_MATH_NEON) + /** + * @brief 32-bit fractional 64-bit vector data type in 1.31 format. + */ + typedef int32x2_t q31x2_t; + + /** + * @brief 16-bit fractional 64-bit vector data type in 1.15 format. + */ + typedef __ALIGNED(2) int16x4_t q15x4_t; + + /** + * @brief 8-bit fractional 64-bit vector data type in 1.7 format. + */ + typedef __ALIGNED(1) int8x8_t q7x8_t; + + /** + * @brief 32-bit float 64-bit vector data type. + */ + typedef float32x2_t f32x2_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit float 64-bit vector data type. + */ + typedef __ALIGNED(2) float16x4_t f16x4_t; +#endif + + /** + * @brief 32-bit floating-point 128-bit vector triplet data type + */ + typedef float32x4x3_t f32x4x3_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector triplet data type + */ + typedef float16x8x3_t f16x8x3_t; +#endif + + /** + * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format + */ + typedef int32x4x3_t q31x4x3_t; + + /** + * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format + */ + typedef int16x8x3_t q15x8x3_t; + + /** + * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format + */ + typedef int8x16x3_t q7x16x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector pair data type + */ + typedef float32x2x2_t f32x2x2_t; + + /** + * @brief 32-bit floating-point 64-bit vector triplet data type + */ + typedef float32x2x3_t f32x2x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector quadruplet data type + */ + typedef float32x2x4_t f32x2x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 64-bit vector pair data type + */ + typedef float16x4x2_t f16x4x2_t; + + /** + * @brief 16-bit floating-point 64-bit vector triplet data type + */ + typedef float16x4x3_t f16x4x3_t; + + /** + * @brief 16-bit floating-point 64-bit vector quadruplet data type + */ + typedef float16x4x4_t f16x4x4_t; +#endif + + /** + * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format + */ + typedef int32x2x2_t q31x2x2_t; + + /** + * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format + */ + typedef int32x2x3_t q31x2x3_t; + + /** + * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format + */ + typedef int32x4x3_t q31x2x4_t; + + /** + * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format + */ + typedef int16x4x2_t q15x4x2_t; + + /** + * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format + */ + typedef int16x4x2_t q15x4x3_t; + + /** + * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format + */ + typedef int16x4x3_t q15x4x4_t; + + /** + * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format + */ + typedef int8x8x2_t q7x8x2_t; + + /** + * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format + */ + typedef int8x8x3_t q7x8x3_t; + + /** + * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format + */ + typedef int8x8x4_t q7x8x4_t; + + /** + * @brief 32-bit ubiquitous 64-bit vector data type + */ + typedef union _any32x2_t + { + float32x2_t f; + int32x2_t i; + } any32x2_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit ubiquitous 64-bit vector data type + */ + typedef union _any16x4_t + { + float16x4_t f; + int16x4_t i; + } any16x4_t; +#endif + + /** + * @brief 32-bit status 64-bit vector data type. + */ + typedef int32x4_t status32x2_t; + + /** + * @brief 16-bit status 64-bit vector data type. + */ + typedef int16x8_t status16x4_t; + + /** + * @brief 8-bit status 64-bit vector data type. + */ + typedef int8x16_t status8x8_t; + +#endif + + + +/** + @brief definition to read/write two 16 bit values. + @deprecated + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __un(aligned) int32_t +#elif defined(_MSC_VER ) + #define __SIMD32_TYPE int32_t +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) +#define __SIMD64(addr) (*( int64_t **) & (addr)) + +#define STEP(x) (x) <= 0 ? 0 : 1 +#define SQ(x) ((x) * (x)) + +/* SIMD replacement */ + + +/** + @brief Read 2 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2 ( + q15_t * pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, pQ15, 4); +#else + val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ; +#endif + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_ia ( + q15_t ** pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ15, 4); +#else + val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF); +#endif + + *pQ15 += 2; + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_da ( + q15_t ** pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ15, 4); +#else + val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF); +#endif + + *pQ15 -= 2; + return (val); +} + +/** + @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2_ia ( + q15_t ** pQ15, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ15, &val, 4); +#else + (*pQ15)[0] = (val & 0x0FFFF); + (*pQ15)[1] = (val >> 16) & 0x0FFFF; +#endif + + *pQ15 += 2; +} + +/** + @brief Write 2 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2 ( + q15_t * pQ15, + q31_t value) +{ + q31_t val = value; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (pQ15, &val, 4); +#else + pQ15[0] = val & 0x0FFFF; + pQ15[1] = val >> 16; +#endif +} + + +/** + @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_ia ( + q7_t ** pQ7) +{ + q31_t val; + + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ7, 4); +#else + val =(((*pQ7)[3] & 0x0FF) << 24) | (((*pQ7)[2] & 0x0FF) << 16) | (((*pQ7)[1] & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF); +#endif + + *pQ7 += 4; + + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_da ( + q7_t ** pQ7) +{ + q31_t val; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ7, 4); +#else + val = ((((*pQ7)[3]) & 0x0FF) << 24) | ((((*pQ7)[2]) & 0x0FF) << 16) | ((((*pQ7)[1]) & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF); +#endif + *pQ7 -= 4; + + return (val); +} + +/** + @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4_ia ( + q7_t ** pQ7, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ7, &val, 4); +#else + (*pQ7)[0] = val & 0x0FF; + (*pQ7)[1] = (val >> 8) & 0x0FF; + (*pQ7)[2] = (val >> 16) & 0x0FF; + (*pQ7)[3] = (val >> 24) & 0x0FF; + +#endif + *pQ7 += 4; +} + +/* + +Normally those kind of definitions are in a compiler file +in Core or Core_A. + +But for MSVC compiler it is a bit special. The goal is very specific +to CMSIS-DSP and only to allow the use of this library from other +systems like Python or Matlab. + +MSVC is not going to be used to cross-compile to ARM. So, having a MSVC +compiler file in Core or Core_A would not make sense. + +*/ +#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#ifndef ARM_MATH_DSP + /** + * @brief definition to pack two 16 bit values. + */ + #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#endif + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_FORCEINLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_FORCEINLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + __STATIC_FORCEINLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y) ) ); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + const q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + const q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + +/** + * @brief Integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb) +{ + float32_t r = x; + nb --; + while(nb > 0) + { + r = r * x; + nb--; + } + return(r); +} + +/** + * @brief 64-bit to 32-bit unsigned normalization + * @param[in] in is input unsigned long long value + * @param[out] normalized is the 32-bit normalized value + * @param[out] norm is norm scale + */ +__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm) +{ + int32_t n1; + int32_t hi = (int32_t) (in >> 32); + int32_t lo = (int32_t) ((in << 32) >> 32); + + n1 = __CLZ(hi) - 32; + if (!n1) + { + /* + * input fits in 32-bit + */ + n1 = __CLZ(lo); + if (!n1) + { + /* + * MSB set, need to scale down by 1 + */ + *norm = -1; + *normalized = (((uint32_t) lo) >> 1); + } else + { + if (n1 == 32) + { + /* + * input is zero + */ + *norm = 0; + *normalized = 0; + } else + { + /* + * 32-bit normalization + */ + *norm = n1 - 1; + *normalized = lo << *norm; + } + } + } else + { + /* + * input fits in 64-bit + */ + n1 = 1 - n1; + *norm = -n1; + /* + * 64 bit normalization + */ + *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1)); + } +} + +__STATIC_INLINE q31_t arm_div_q63_to_q31(q63_t num, q31_t den) +{ + q31_t result; + uint64_t absNum; + int32_t normalized; + int32_t norm; + + /* + * if sum fits in 32bits + * avoid costly 64-bit division + */ + absNum = num > 0 ? num : -num; + arm_norm_64_to_32u(absNum, &normalized, &norm); + if (norm > 0) + /* + * 32-bit division + */ + result = (q31_t) num / den; + else + /* + * 64-bit division + */ + result = (q31_t) (num / den); + + return result; +} + + +/* + * @brief C custom defined intrinsic functions + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 + */ + __STATIC_FORCEINLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 + */ + __STATIC_FORCEINLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 + */ + __STATIC_FORCEINLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 + */ + __STATIC_FORCEINLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 + */ + __STATIC_FORCEINLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 + */ + __STATIC_FORCEINLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX + */ + __STATIC_FORCEINLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX + */ + __STATIC_FORCEINLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX + */ + __STATIC_FORCEINLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX + */ + __STATIC_FORCEINLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX + */ + __STATIC_FORCEINLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX + */ + __STATIC_FORCEINLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD + */ + __STATIC_FORCEINLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB + */ + __STATIC_FORCEINLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD + */ + __STATIC_FORCEINLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX + */ + __STATIC_FORCEINLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX + */ + __STATIC_FORCEINLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD + */ + __STATIC_FORCEINLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX + */ + __STATIC_FORCEINLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD + */ + __STATIC_FORCEINLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD + */ + __STATIC_FORCEINLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 + */ + __STATIC_FORCEINLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA + */ + __STATIC_FORCEINLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter (fast version). + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns either + * ARM_MATH_SUCCESS if initialization was successful or + * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter (fast version). + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + /** + * @brief Instance structure for the modified Biquad coefs required by vectorized code. + */ + typedef struct + { + float32_t coeffs[8][4]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ + } arm_biquad_mod_coef_f32; +#endif + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pCoeffsMod points to the modified filter coefficients (only MVE version). + * @param[in] pState points to the state buffer. + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + void arm_biquad_cascade_df1_mve_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + arm_biquad_mod_coef_f32 * pCoeffsMod, + float32_t * pState); +#endif + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u16( + const uint16_t * pSrc, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u32( + const uint32_t * pSrc, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u8( + const uint8_t * pSrc, + uint8_t * pDst, + uint32_t blockSize); + +/** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_BITONIC = 0, + /**< Bitonic sort */ + ARM_SORT_BUBBLE = 1, + /**< Bubble sort */ + ARM_SORT_HEAP = 2, + /**< Heap sort */ + ARM_SORT_INSERTION = 3, + /**< Insertion sort */ + ARM_SORT_QUICK = 4, + /**< Quick sort */ + ARM_SORT_SELECTION = 5 + /**< Selection sort */ + } arm_sort_alg; + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_DESCENDING = 0, + /**< Descending order (9 to 0) */ + ARM_SORT_ASCENDING = 1 + /**< Ascending order (0 to 9) */ + } arm_sort_dir; + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_alg alg; /**< Sorting algorithm selected */ + arm_sort_dir dir; /**< Sorting order (direction) */ + } arm_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] alg Selected algorithm. + * @param[in] dir Sorting order. + */ + void arm_sort_init_f32( + arm_sort_instance_f32 * S, + arm_sort_alg alg, + arm_sort_dir dir); + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_dir dir; /**< Sorting order (direction) */ + float32_t * buffer; /**< Working buffer */ + } arm_merge_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in,out] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_merge_sort_f32( + const arm_merge_sort_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] dir Sorting order. + * @param[in] buffer Working buffer. + */ + void arm_merge_sort_init_f32( + arm_merge_sort_instance_f32 * S, + arm_sort_dir dir, + float32_t * buffer); + + /** + * @brief Struct for specifying cubic spline type + */ + typedef enum + { + ARM_SPLINE_NATURAL = 0, /**< Natural spline */ + ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */ + } arm_spline_type; + + /** + * @brief Instance structure for the floating-point cubic spline interpolation. + */ + typedef struct + { + arm_spline_type type; /**< Type (boundary conditions) */ + const float32_t * x; /**< x values */ + const float32_t * y; /**< y values */ + uint32_t n_x; /**< Number of known data points */ + float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */ + } arm_spline_instance_f32; + + /** + * @brief Processing function for the floating-point cubic spline interpolation. + * @param[in] S points to an instance of the floating-point spline structure. + * @param[in] xq points to the x values ot the interpolated data points. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples of output data. + */ + void arm_spline_f32( + arm_spline_instance_f32 * S, + const float32_t * xq, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point cubic spline interpolation. + * @param[in,out] S points to an instance of the floating-point spline structure. + * @param[in] type type of cubic spline interpolation (boundary conditions) + * @param[in] x points to the x values of the known data points. + * @param[in] y points to the y values of the known data points. + * @param[in] n number of known data points. + * @param[in] coeffs coefficients array for b, c, and d + * @param[in] tempBuffer buffer array for internal computations + */ + void arm_spline_init_f32( + arm_spline_instance_f32 * S, + arm_spline_type type, + const float32_t * x, + const float32_t * y, + uint32_t n, + float32_t * coeffs, + float32_t * tempBuffer); + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q15_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q15; + +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen); + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q31_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q31; + +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen); + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const float32_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_f32; + + + arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen); + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + /** + * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float64_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f64; + + void arm_cfft_f64( + const arm_cfft_instance_f64 * S, + float64_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) + arm_cfft_instance_q15 cfftInst; +#else + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) + arm_cfft_instance_q31 cfftInst; +#else + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f64 ; + +arm_status arm_rfft_fast_init_f64 ( + arm_rfft_fast_instance_f64 * S, + uint16_t fftLen); + + +void arm_rfft_fast_f64( + arm_rfft_fast_instance_f64 * S, + float64_t * p, float64_t * pOut, + uint8_t ifftFlag); + + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + + + void arm_rfft_fast_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + +/** + @brief Instance structure for floating-point FIR decimator. + */ +typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + */ +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + +#if defined(ARM_MATH_NEON) +void arm_biquad_cascade_df2T_compute_coefs_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs); +#endif + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + const float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + +/** + @brief Correlation of Q15 sequences + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+   *
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return processed output sample. + */ + __STATIC_FORCEINLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + +/** + @brief Process function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +__STATIC_FORCEINLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + +/** + @brief Process function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +__STATIC_FORCEINLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @return none + */ + __STATIC_FORCEINLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + +/** + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + +/** + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] pIa points to output three-phase coordinate a + @param[out] pIb points to output three-phase coordinate b + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + * + * The function implements the forward Park transform. + * + */ + __STATIC_FORCEINLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + +/** + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] pId points to output rotor reference frame d + @param[out] pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + +/** + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + __STATIC_FORCEINLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= (S->nValues - 1)) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + __STATIC_FORCEINLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); + #else + *pOut = sqrtf(in); + #endif + +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @brief Vector Floating-point square root function. + * @param[in] pIn input vector. + * @param[out] pOut vector of square roots of input elements. + * @param[in] len length of input vector. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + void arm_vsqrt_f32( + float32_t * pIn, + float32_t * pOut, + uint16_t len); + + void arm_vsqrt_q31( + q31_t * pIn, + q31_t * pOut, + uint16_t len); + + void arm_vsqrt_q15( + q15_t * pIn, + q15_t * pOut, + uint16_t len); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset; + int32_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q15_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q7_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +/** + * @brief Struct for specifying SVM Kernel + */ +typedef enum +{ + ARM_ML_KERNEL_LINEAR = 0, + /**< Linear kernel */ + ARM_ML_KERNEL_POLYNOMIAL = 1, + /**< Polynomial kernel */ + ARM_ML_KERNEL_RBF = 2, + /**< Radial Basis Function kernel */ + ARM_ML_KERNEL_SIGMOID = 3 + /**< Sigmoid kernel */ +} arm_ml_kernel_type; + + +/** + * @brief Instance structure for linear SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ +} arm_svm_linear_instance_f32; + + +/** + * @brief Instance structure for polynomial SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float32_t coef0; /**< Polynomial constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_polynomial_instance_f32; + +/** + * @brief Instance structure for rbf SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_rbf_instance_f32; + +/** + * @brief Instance structure for sigmoid SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t coef0; /**< Independant constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_sigmoid_instance_f32; + +/** + * @brief SVM linear instance init function + * @param[in] S Parameters for SVM functions + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes); + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM polynomial instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + int32_t degree, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM radial basis function instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t gamma + ); + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ +void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + +/** + * @brief SVM sigmoid instance init function + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + + +/** + * @brief Instance structure for Naive Gaussian Bayesian estimator. + */ +typedef struct +{ + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float32_t *theta; /**< Mean values for the Gaussians */ + const float32_t *sigma; /**< Variances for the Gaussians */ + const float32_t *classPriors; /**< Class prior probabilities */ + float32_t epsilon; /**< Additive value to variances */ +} arm_gaussian_naive_bayes_instance_f32; + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] S points to a naive bayes instance structure + * @param[in] in points to the elements of the input vector. + * @param[in] pBuffer points to a buffer of length numberOfClasses + * @return The predicted class + * + */ + + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pBuffer); + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + + +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize); + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product . + * + */ + + +float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t *pTmpBuffer); + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize); + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA + ,const float32_t * pSrcB + ,uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize); + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ +float32_t arm_weighted_sum_f32(const float32_t *in + , const float32_t *weigths + , uint32_t blockSize); + + +/** + * @brief Barycenter + * + * + * @param[in] in List of vectors + * @param[in] weights Weights of the vectors + * @param[out] out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ +void arm_barycenter_f32(const float32_t *in + , const float32_t *weights + , float32_t *out + , uint32_t nbVectors + , uint32_t vecDim); + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x 0 and y 0, + * it will compute the right value (0) but a division per zero will occur + * and shoudl be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize); + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] n Norm order (>= 2) + * @param[in] blockSize vector length + * @return distance + * + */ + + + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize); + +/** + * @brief Dice distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + + +float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Hamming distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Jaccard distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Kulsinski distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Roger Stanimoto distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Russell-Rao distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Michener distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Sneath distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Yule distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex ) + (yIndex ) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex ) + (yIndex+1) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0x0FFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0x0FFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0x0FFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0x0FFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#endif + + + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_mve_tables.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_mve_tables.h new file mode 100644 index 0000000000..4d2c135ac6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_mve_tables.h @@ -0,0 +1,235 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables.h + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * $Date: 08. January 2020 + * $Revision: V1.7.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #ifndef _ARM_MVE_TABLES_H + #define _ARM_MVE_TABLES_H + + #include "arm_math.h" + + + + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2]; +extern float32_t rearranged_twiddle_stride1_16_f32[8]; +extern float32_t rearranged_twiddle_stride2_16_f32[8]; +extern float32_t rearranged_twiddle_stride3_16_f32[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3]; +extern float32_t rearranged_twiddle_stride1_64_f32[40]; +extern float32_t rearranged_twiddle_stride2_64_f32[40]; +extern float32_t rearranged_twiddle_stride3_64_f32[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4]; +extern float32_t rearranged_twiddle_stride1_256_f32[168]; +extern float32_t rearranged_twiddle_stride2_256_f32[168]; +extern float32_t rearranged_twiddle_stride3_256_f32[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5]; +extern float32_t rearranged_twiddle_stride1_1024_f32[680]; +extern float32_t rearranged_twiddle_stride2_1024_f32[680]; +extern float32_t rearranged_twiddle_stride3_1024_f32[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6]; +extern float32_t rearranged_twiddle_stride1_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride2_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride3_4096_f32[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2]; +extern q31_t rearranged_twiddle_stride1_16_q31[8]; +extern q31_t rearranged_twiddle_stride2_16_q31[8]; +extern q31_t rearranged_twiddle_stride3_16_q31[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3]; +extern q31_t rearranged_twiddle_stride1_64_q31[40]; +extern q31_t rearranged_twiddle_stride2_64_q31[40]; +extern q31_t rearranged_twiddle_stride3_64_q31[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4]; +extern q31_t rearranged_twiddle_stride1_256_q31[168]; +extern q31_t rearranged_twiddle_stride2_256_q31[168]; +extern q31_t rearranged_twiddle_stride3_256_q31[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5]; +extern q31_t rearranged_twiddle_stride1_1024_q31[680]; +extern q31_t rearranged_twiddle_stride2_1024_q31[680]; +extern q31_t rearranged_twiddle_stride3_1024_q31[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6]; +extern q31_t rearranged_twiddle_stride1_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride2_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride3_4096_q31[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2]; +extern q15_t rearranged_twiddle_stride1_16_q15[8]; +extern q15_t rearranged_twiddle_stride2_16_q15[8]; +extern q15_t rearranged_twiddle_stride3_16_q15[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3]; +extern q15_t rearranged_twiddle_stride1_64_q15[40]; +extern q15_t rearranged_twiddle_stride2_64_q15[40]; +extern q15_t rearranged_twiddle_stride3_64_q15[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4]; +extern q15_t rearranged_twiddle_stride1_256_q15[168]; +extern q15_t rearranged_twiddle_stride2_256_q15[168]; +extern q15_t rearranged_twiddle_stride3_256_q15[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5]; +extern q15_t rearranged_twiddle_stride1_1024_q15[680]; +extern q15_t rearranged_twiddle_stride2_1024_q15[680]; +extern q15_t rearranged_twiddle_stride3_1024_q15[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6]; +extern q15_t rearranged_twiddle_stride1_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride2_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride3_4096_q15[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#endif /*_ARM_MVE_TABLES_H*/ + diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_vec_math.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_vec_math.h new file mode 100644 index 0000000000..0ce9464bcb --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/arm_vec_math.h @@ -0,0 +1,372 @@ +/****************************************************************************** + * @file arm_vec_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.7.0 + * @date 15. October 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_MATH_H +#define _ARM_VEC_MATH_H + +#include "arm_math.h" +#include "arm_common_tables.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define INV_NEWTON_INIT_F32 0x7EF127EA + +static const float32_t __logf_rng_f32=0.693147180f; + + +/* fast inverse approximation (3x newton) */ +__STATIC_INLINE f32x4_t vrecip_medprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +/* fast inverse approximation (4x newton) */ +__STATIC_INLINE f32x4_t vrecip_hiprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +__STATIC_INLINE f32x4_t vdiv_f32( + f32x4_t num, f32x4_t den) +{ + return vmulq(num, vrecip_hiprec_f32(den)); +} + +/** + @brief Single-precision taylor dev. + @param[in] x f32 quad vector input + @param[in] coeffs f32 quad vector coeffs + @return destination f32 quad vector + */ + +__STATIC_INLINE f32x4_t vtaylor_polyq_f32( + f32x4_t x, + const float32_t * coeffs) +{ + f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]); + f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]); + f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]); + f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]); + f32x4_t x2 = vmulq(x, x); + f32x4_t x4 = vmulq(x2, x2); + f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4); + + return res; +} + +__STATIC_INLINE f32x4_t vmant_exp_f32( + f32x4_t x, + int32x4_t * e) +{ + any32x4_t r; + int32x4_t n; + + r.f = x; + n = r.i >> 23; + n = n - 127; + r.i = r.i - (n << 23); + + *e = n; + return r.f; +} + + +__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn) +{ + q31x4_t vecExpUnBiased; + f32x4_t vecTmpFlt0, vecTmpFlt1; + f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; + f32x4_t vecExpUnBiasedFlt; + + /* + * extract exponent + */ + vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased); + + vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1; + /* + * a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]); + */ + vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]); + vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]); + /* + * b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]); + */ + vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]); + vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]); + /* + * c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]); + */ + vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]); + vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]); + /* + * d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]); + */ + vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]); + vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]); + /* + * a = a + b * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0); + /* + * c = c + d * xx; + */ + vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0); + /* + * xx = xx * xx; + */ + vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0; + vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased); + /* + * r.f = a + c * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0); + /* + * add exponent + * r.f = r.f + ((float32_t) m) * __logf_rng_f32; + */ + vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32); + // set log0 down to -inf + vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f)); + return vecAcc0; +} + +__STATIC_INLINE f32x4_t vexpq_f32( + f32x4_t x) +{ + // Perform range reduction [-log(2),log(2)] + int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f)); + f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f)); + + // Polynomial Approximation + f32x4_t poly = vtaylor_polyq_f32(val, exp_tab); + + // Reconstruct + poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23))); + + poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126)); + return poly; +} + +__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb) +{ + f32x4_t r = x; + nb--; + while (nb > 0) { + r = vmulq(r, x); + nb--; + } + return (r); +} + +__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn) +{ + f32x4_t vecSx, vecW, vecTmp; + any32x4_t v; + + vecSx = vabsq(vecIn); + + v.f = vecIn; + v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i); + + vecW = vmulq(vecSx, v.f); + + // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w))))))); + vecTmp = vsubq(vdupq_n_f32(8.0f), vecW); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -70.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 8.0f); + v.f = vmulq(v.f, vecTmp); + + v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f)); + /* + * restore sign + */ + v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f)); + return v.f; +} + +__STATIC_INLINE f32x4_t vtanhq_f32( + f32x4_t val) +{ + f32x4_t x = + vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f)); + f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f)); + f32x4_t num = vsubq_n_f32(exp2x, 1.f); + f32x4_t den = vaddq_n_f32(exp2x, 1.f); + f32x4_t tanh = vmulq_f32(num, vrecip_f32(den)); + return tanh; +} + +__STATIC_INLINE f32x4_t vpowq_f32( + f32x4_t val, + f32x4_t n) +{ + return vexpq_f32(vmulq_f32(n, vlogq_f32(val))); +} + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" +/** + * @brief Vectorized integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb) +{ + float32x4_t r = x; + nb --; + while(nb > 0) + { + r = vmulq_f32(r , x); + nb--; + } + return(r); +} + + +__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) +{ + float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN)); + float32x4_t e = vrsqrteq_f32(x1); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + return vmulq_f32(x, e); +} + +__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec) +{ + float32x4_t tempF; + int32x4_t tempHI,tempLO; + + tempLO = vmovl_s16(vget_low_s16(vec)); + tempF = vcvtq_n_f32_s32(tempLO,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempLO = vcvtq_n_s32_f32(tempF,15); + + tempHI = vmovl_s16(vget_high_s16(vec)); + tempF = vcvtq_n_f32_s32(tempHI,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempHI = vcvtq_n_s32_f32(tempF,15); + + return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI))); +} + +__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec) +{ + float32x4_t temp; + + temp = vcvtq_n_f32_s32(vec,31); + temp = __arm_vec_sqrt_f32_neon(temp); + return(vcvtq_n_s32_f32(temp,31)); +} + +#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_VEC_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cachel1_armv7.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cachel1_armv7.h new file mode 100644 index 0000000000..d2c3e2291f --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.0 + * @date 03. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_armcc.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_armcc.h new file mode 100644 index 0000000000..237ff6ec3e --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_armcc.h @@ -0,0 +1,885 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.2.1 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_armclang.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_armclang.h new file mode 100644 index 0000000000..90de9dbf8f --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_armclang.h @@ -0,0 +1,1467 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.3.1 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_armclang_ltm.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..0e5c7349d3 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1893 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_compiler.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_gcc.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_gcc.h new file mode 100644 index 0000000000..a2778f58e8 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_gcc.h @@ -0,0 +1,2177 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_iccarm.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..7eeffca5c7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_iccarm.h @@ -0,0 +1,968 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.2.0 + * @date 28. January 2020 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_version.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_version.h new file mode 100644 index 0000000000..2f048e4552 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.4 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_armv81mml.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_armv81mml.h new file mode 100644 index 0000000000..1ad19e215a --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_armv81mml.h @@ -0,0 +1,4191 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.3.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[4]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */ + uint32_t RESERVED14[3]; + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_armv8mbl.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_armv8mbl.h new file mode 100644 index 0000000000..932d3d188b --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_armv8mml.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_armv8mml.h new file mode 100644 index 0000000000..71f000bcad --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_armv8mml.h @@ -0,0 +1,3196 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm0.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm0.h new file mode 100644 index 0000000000..6441ff3419 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm0plus.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm0plus.h new file mode 100644 index 0000000000..4e7179a614 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm1.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm1.h new file mode 100644 index 0000000000..76b4569743 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm23.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm23.h new file mode 100644 index 0000000000..55fff99509 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm3.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm3.h new file mode 100644 index 0000000000..24453a8863 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm33.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm33.h new file mode 100644 index 0000000000..13359be3ed --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm33.h @@ -0,0 +1,3264 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm35p.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm35p.h new file mode 100644 index 0000000000..6a5f6ad147 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm35p.h @@ -0,0 +1,3264 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm4.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm4.h new file mode 100644 index 0000000000..4e0e886697 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm55.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm55.h new file mode 100644 index 0000000000..6efaa3f842 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm55.h @@ -0,0 +1,4215 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_CM55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[4]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */ + uint32_t RESERVED14[3]; + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm7.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm7.h new file mode 100644 index 0000000000..e1c31c275d --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_cm7.h @@ -0,0 +1,2362 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_sc000.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_sc000.h new file mode 100644 index 0000000000..dbc755fff3 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_sc300.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_sc300.h new file mode 100644 index 0000000000..e8914ba601 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/mpu_armv7.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/mpu_armv7.h new file mode 100644 index 0000000000..791a8dae65 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.1 + * @date 10. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/mpu_armv8.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/mpu_armv8.h new file mode 100644 index 0000000000..ef44ad01df --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.2 + * @date 10. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/pmu_armv8.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/pmu_armv8.h new file mode 100644 index 0000000000..dbd39d20c7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.0 + * @date 24. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/tz_context.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/tz_context.h new file mode 100644 index 0000000000..0d09749f3a --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/cmsis/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll.h new file mode 100644 index 0000000000..1ececb91a7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll.h @@ -0,0 +1,325 @@ +/** + ******************************************************************************* + * @file hc32_ll.h + * @brief This file contains HC32 Series Device Driver Library file call + * management. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_H__ +#define __HC32_LL_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_Global + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup LL_Global_Macros LL Global Macros + * @{ + */ + +/** + * @defgroup Peripheral_Register_WP_Local_Macros Peripheral Register Write Protection Local Macros + * @{ + */ +#define LL_PERIPH_EFM (1UL << 0U) +#define LL_PERIPH_FCG (1UL << 1U) +#define LL_PERIPH_GPIO (1UL << 2U) +#define LL_PERIPH_INTC (1UL << 3U) +#define LL_PERIPH_LVD (1UL << 4U) +#define LL_PERIPH_MPU (1UL << 5U) +#define LL_PERIPH_PWC_CLK_RMU (1UL << 6U) +#define LL_PERIPH_SRAM (1UL << 7U) +#define LL_PERIPH_ALL (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_GPIO | LL_PERIPH_INTC | \ + LL_PERIPH_LVD | LL_PERIPH_MPU | LL_PERIPH_SRAM | LL_PERIPH_PWC_CLK_RMU) +/** + * @} + */ + +/* Defined use Device Driver Library */ +#if !defined (USE_DDL_DRIVER) +/** + * @brief Comment the line below if you will not use the Device Driver Library. + * In this case, the application code will be based on direct access to + * peripherals registers. + */ +/* #define USE_DDL_DRIVER */ +#endif /* USE_DDL_DRIVER */ + +/** +* @defgroup HC32_Series_DDL_Version HC32 Series Device Driver Library Version +* @{ +*/ +#define HC32_DDL_VER_MAIN 0x01U /*!< [31:24] main version */ +#define HC32_DDL_VER_SUB1 0x00U /*!< [23:16] sub1 version */ +#define HC32_DDL_VER_SUB2 0x00U /*!< [15:8] sub2 version */ +#define HC32_DDL_VER_PATCH 0x00U /*!< [7:0] patch version */ +#define HC32_DDL_VER ((HC32_DDL_VER_MAIN << 24) | (HC32_DDL_VER_SUB1 << 16) | \ + (HC32_DDL_VER_SUB2 << 8 ) | (HC32_DDL_VER_PATCH)) +/** + * @} + */ + +/** +* @defgroup HC32_Series_DDL_Release_Version HC32 Series DDL Release Version +* @{ +*/ +#define HC32_DDL_REV_MAIN 0x03U /*!< [31:24] main version */ +#define HC32_DDL_REV_SUB1 0x00U /*!< [23:16] sub1 version */ +#define HC32_DDL_REV_SUB2 0x00U /*!< [15:8] sub2 version */ +#define HC32_DDL_REV_PATCH 0x00U /*!< [7:0] patch version */ +#define HC32_DDL_REV ((HC32_DDL_REV_MAIN << 24) | (HC32_DDL_REV_SUB1 << 16) | \ + (HC32_DDL_REV_SUB2 << 8 ) | (HC32_DDL_REV_PATCH)) +/** + * @} + */ + +/** + * @} + */ + +/* Use Device Driver Library */ +#if defined (USE_DDL_DRIVER) + +/** + * @brief Include peripheral module's header file + */ +#if (LL_ADC_ENABLE == DDL_ON) +#include "hc32_ll_adc.h" +#endif /* LL_ADC_ENABLE */ + +#if (LL_AES_ENABLE == DDL_ON) +#include "hc32_ll_aes.h" +#endif /* LL_AES_ENABLE */ + +#if (LL_AOS_ENABLE == DDL_ON) +#include "hc32_ll_aos.h" +#endif /* LL_AOS_ENABLE */ + +#if (LL_CAN_ENABLE == DDL_ON) +#include "hc32_ll_can.h" +#endif /* LL_CAN_ENABLE */ + +#if (LL_CLK_ENABLE == DDL_ON) +#include "hc32_ll_clk.h" +#endif /* LL_CLK_ENABLE */ + +#if (LL_CMP_ENABLE == DDL_ON) +#include "hc32_ll_cmp.h" +#endif /* LL_CMP_ENABLE */ + +#if (LL_CRC_ENABLE == DDL_ON) +#include "hc32_ll_crc.h" +#endif /* LL_CRC_ENABLE */ + +#if (LL_DCU_ENABLE == DDL_ON) +#include "hc32_ll_dcu.h" +#endif /* LL_DCU_ENABLE */ + +#if (LL_DMA_ENABLE == DDL_ON) +#include "hc32_ll_dma.h" +#endif /* LL_DMA_ENABLE */ + +#if (LL_EFM_ENABLE == DDL_ON) +#include "hc32_ll_efm.h" +#endif /* LL_EFM_ENABLE */ + +#if (LL_EMB_ENABLE == DDL_ON) +#include "hc32_ll_emb.h" +#endif /* LL_EMB_ENABLE */ + +#if (LL_EVENT_PORT_ENABLE == DDL_ON) +#include "hc32_ll_event_port.h" +#endif /* LL_EVENT_PORT_ENABLE */ + +#if (LL_FCG_ENABLE == DDL_ON) +#include "hc32_ll_fcg.h" +#endif /* LL_FCG_ENABLE */ + +#if (LL_FCM_ENABLE == DDL_ON) +#include "hc32_ll_fcm.h" +#endif /* LL_FCM_ENABLE */ + +#if (LL_GPIO_ENABLE == DDL_ON) +#include "hc32_ll_gpio.h" +#endif /* LL_GPIO_ENABLE */ + +#if (LL_HASH_ENABLE == DDL_ON) +#include "hc32_ll_hash.h" +#endif /* LL_HASH_ENABLE */ + +#if (LL_I2C_ENABLE == DDL_ON) +#include "hc32_ll_i2c.h" +#endif /* LL_I2C_ENABLE */ + +#if (LL_I2S_ENABLE == DDL_ON) +#include "hc32_ll_i2s.h" +#endif /* LL_I2S_ENABLE */ + +#if (LL_ICG_ENABLE == DDL_ON) +#include "hc32_ll_icg.h" +#endif /* LL_ICG_ENABLE */ + +#if (LL_INTERRUPTS_ENABLE == DDL_ON) +#include "hc32_ll_interrupts.h" +#endif /* LL_INTERRUPTS_ENABLE */ + +#if (LL_INTERRUPTS_SHARE_ENABLE == DDL_ON) +#include "hc32f460_ll_interrupts_share.h" +#endif /* LL_INTERRUPTS_ENABLE */ + +#if (LL_KEYSCAN_ENABLE == DDL_ON) +#include "hc32_ll_keyscan.h" +#endif /* LL_KEYSCAN_ENABLE */ + +#if (LL_MPU_ENABLE == DDL_ON) +#include "hc32_ll_mpu.h" +#endif /* LL_MPU_ENABLE */ + +#if (LL_OTS_ENABLE == DDL_ON) +#include "hc32_ll_ots.h" +#endif /* LL_OTS_ENABLE */ + +#if (LL_PWC_ENABLE == DDL_ON) +#include "hc32_ll_pwc.h" +#endif /* LL_PWC_ENABLE */ + +#if (LL_QSPI_ENABLE == DDL_ON) +#include "hc32_ll_qspi.h" +#endif /* LL_QSPI_ENABLE */ + +#if (LL_RMU_ENABLE == DDL_ON) +#include "hc32_ll_rmu.h" +#endif /* LL_RMU_ENABLE */ + +#if (LL_RTC_ENABLE == DDL_ON) +#include "hc32_ll_rtc.h" +#endif /* LL_RTC_ENABLE */ + +#if (LL_SDIOC_ENABLE == DDL_ON) +#include "hc32_ll_sdioc.h" +#endif /* LL_SDIOC_ENABLE */ + +#if (LL_SPI_ENABLE == DDL_ON) +#include "hc32_ll_spi.h" +#endif /* LL_SPI_ENABLE */ + +#if (LL_SRAM_ENABLE == DDL_ON) +#include "hc32_ll_sram.h" +#endif /* LL_SRAM_ENABLE */ + +#if (LL_SWDT_ENABLE == DDL_ON) +#include "hc32_ll_swdt.h" +#endif /* LL_SWDT_ENABLE */ + +#if (LL_TMR0_ENABLE == DDL_ON) +#include "hc32_ll_tmr0.h" +#endif /* LL_TMR0_ENABLE */ + +#if (LL_TMR4_ENABLE == DDL_ON) +#include "hc32_ll_tmr4.h" +#endif /* LL_TMR4_ENABLE */ + +#if (LL_TMR6_ENABLE == DDL_ON) +#include "hc32_ll_tmr6.h" +#endif /* LL_TMR6_ENABLE */ + +#if (LL_TMRA_ENABLE == DDL_ON) +#include "hc32_ll_tmra.h" +#endif /* LL_TMRA_ENABLE */ + +#if (LL_TRNG_ENABLE == DDL_ON) +#include "hc32_ll_trng.h" +#endif /* LL_TRNG_ENABLE */ + +#if (LL_USART_ENABLE == DDL_ON) +#include "hc32_ll_usart.h" +#endif /* LL_USART_ENABLE */ + +#if (LL_UTILITY_ENABLE == DDL_ON) +#include "hc32_ll_utility.h" +#endif /* LL_UTILITY_ENABLE */ + +#if (LL_USB_ENABLE == DDL_ON) +#include "hc32_ll_usb.h" +#endif /* LL_USB_ENABLE */ + +#if (LL_WDT_ENABLE == DDL_ON) +#include "hc32_ll_wdt.h" +#endif /* LL_WDT_ENABLE */ + +#endif /* USE_DDL_DRIVER */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup LL_Global_Functions + * @{ + */ +void LL_PERIPH_WE(uint32_t u32Peripheral); +void LL_PERIPH_WP(uint32_t u32Peripheral); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_DDL_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_adc.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_adc.h new file mode 100644 index 0000000000..1517c7509d --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_adc.h @@ -0,0 +1,508 @@ +/** + ******************************************************************************* + * @file hc32_ll_adc.h + * @brief This file contains all the functions prototypes of the ADC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_ADC_H__ +#define __HC32_LL_ADC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_ADC + * @{ + */ + +#if (LL_ADC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Types ADC Global Types + * @{ + */ +/** + * @brief Structure definition of analog watchdog(AWD) configuration. + */ +typedef struct { + uint16_t u16WatchdogMode; /*!< Specifies the ADC analog watchdog mode. + This parameter can be a value of @ref ADC_AWD_Mode */ + uint16_t u16LowThreshold; /*!< Specifies the ADC analog watchdog Low threshold value. */ + uint16_t u16HighThreshold; /*!< Specifies the ADC analog watchdog High threshold value. */ +} stc_adc_awd_config_t; + +/** + * @brief Structure definition of ADC initialization. + */ +typedef struct { + uint16_t u16ScanMode; /*!< Specifies the ADC scan convert mode. + This parameter can be a value of @ref ADC_Scan_Mode */ + uint16_t u16Resolution; /*!< Specifies the ADC resolution. + This parameter can be a value of @ref ADC_Resolution */ + uint16_t u16DataAlign; /*!< Specifies ADC data alignment. + This parameter can be a value of @ref ADC_Data_Align */ +} stc_adc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Macros ADC Global Macros + * @{ + */ + +/** + * @defgroup ADC_Sequence ADC Sequence + * @{ + */ +#define ADC_SEQ_A (0U) /*!< ADC sequence A. */ +#define ADC_SEQ_B (1U) /*!< ADC sequence B. */ +/** + * @} + */ + +/** + * @defgroup ADC_Channel ADC Channel + * @{ + */ +#define ADC_CH0 (0U) /*!< Default input pin: PA0 for ADC1, PA4 for ADC2. */ +#define ADC_CH1 (1U) /*!< Default input pin: PA1 for ADC1, PA5 for ADC2. */ +#define ADC_CH2 (2U) /*!< Default input pin: PA2 for ADC1, PA6 for ADC2. */ +#define ADC_CH3 (3U) /*!< Default input pin: PA3 for ADC1, PA7 for ADC2. */ +#define ADC_CH4 (4U) /*!< Default input pin: PA4 for ADC1, PB0 for ADC2. */ +#define ADC_CH5 (5U) /*!< Default input pin: PA5 for ADC1, PB1 for ADC2. */ +#define ADC_CH6 (6U) /*!< Default input pin: PA6 for ADC1, PC0 for ADC2. */ +#define ADC_CH7 (7U) /*!< Default input pin: PA7 for ADC1, PC1 for ADC2. */ +#define ADC_CH8 (8U) /*!< Default input pin: PB0 for ADC1, internal analog signal for ADC2. */ +#define ADC_CH9 (9U) /*!< Default input pin: PB1 for ADC1, NOT supprot ADC2. */ +#define ADC_CH10 (10U) /*!< Default input pin: PC0 for ADC1, NOT supprot ADC2. */ +#define ADC_CH11 (11U) /*!< Default input pin: PC1 for ADC1, NOT supprot ADC2. */ +#define ADC_CH12 (12U) /*!< Default input pin: PC2 for ADC1, NOT supprot ADC2. */ +#define ADC_CH13 (13U) /*!< Default input pin: PC3 for ADC1, NOT supprot ADC2. */ +#define ADC_CH14 (14U) /*!< Default input pin: PC4 for ADC1, NOT supprot ADC2. */ +#define ADC_CH15 (15U) /*!< Default input pin: PC5 for ADC1, NOT supprot ADC2. */ +#define ADC_CH16 (16U) /*!< ADC1 extended channel, input source is internal analog signal */ + +#define ADC1_EXT_CH (ADC_CH16) /*!< ADC1 extended channel, input source is internal analog signal: + internal reference voltage or 8bit-DAC. */ +#define ADC2_EXT_CH (ADC_CH8) /*!< ADC2 extended channel, input source is internal analog signal: + internal reference voltage or 8bit-DAC. */ +/** + * @} + */ + +/** + * @defgroup ADC_Scan_Mode ADC Scan Convert Mode + * @{ + */ +#define ADC_MD_SEQA_SINGLESHOT (0x0U) /*!< Sequence A single shot. Sequence B is disabled. */ +#define ADC_MD_SEQA_CONT (ADC_CR0_MS_0) /*!< Sequence A continuous. Sequence B is disabled. */ +#define ADC_MD_SEQA_SEQB_SINGLESHOT (ADC_CR0_MS_1) /*!< Sequence A and B both single shot. */ +#define ADC_MD_SEQA_CONT_SEQB_SINGLESHOT (ADC_CR0_MS) /*!< Sequence A continuous and sequence B single shot. */ +/** + * @} + */ + +/** + * @defgroup ADC_Resolution ADC Resolution + * @{ + */ +#define ADC_RESOLUTION_12BIT (0x0U) /*!< Resolution is 12 bit. */ +#define ADC_RESOLUTION_10BIT (ADC_CR0_ACCSEL_0) /*!< Resolution is 10 bit. */ +#define ADC_RESOLUTION_8BIT (ADC_CR0_ACCSEL_1) /*!< Resolution is 8 bit. */ +/** + * @} + */ + +/** + * @defgroup ADC_Data_Align ADC Data Align + * @{ + */ +#define ADC_DATAALIGN_RIGHT (0x0U) /*!< Right alignment of converted data. */ +#define ADC_DATAALIGN_LEFT (ADC_CR0_DFMT) /*!< Left alignment of converted data. */ +/** + * @} + */ + +/** + * @defgroup ADC_Average_Count ADC Average Count + * @{ + */ +#define ADC_AVG_CNT2 (0x0U) /*!< 2 consecutive average conversions. */ +#define ADC_AVG_CNT4 (0x1U << ADC_CR0_AVCNT_POS) /*!< 4 consecutive average conversions. */ +#define ADC_AVG_CNT8 (0x2U << ADC_CR0_AVCNT_POS) /*!< 8 consecutive average conversions. */ +#define ADC_AVG_CNT16 (0x3U << ADC_CR0_AVCNT_POS) /*!< 16 consecutive average conversions. */ +#define ADC_AVG_CNT32 (0x4U << ADC_CR0_AVCNT_POS) /*!< 32 consecutive average conversions. */ +#define ADC_AVG_CNT64 (0x5U << ADC_CR0_AVCNT_POS) /*!< 64 consecutive average conversions. */ +#define ADC_AVG_CNT128 (0x6U << ADC_CR0_AVCNT_POS) /*!< 128 consecutive average conversions. */ +#define ADC_AVG_CNT256 (0x7U << ADC_CR0_AVCNT_POS) /*!< 256 consecutive average conversions. */ +/** + * @} + */ + +/** + * @defgroup ADC_SeqA_Resume_Mode ADC Sequence A Resume Mode + * @brief After interrupted by sequence B, sequence A continues to scan from the interrupt channel or the first channel. + * @{ + */ +#define ADC_SEQA_RESUME_SCAN_CONT (0U) /*!< Scanning will continue from the interrupted channel. */ +#define ADC_SEQA_RESUME_SCAN_RESTART (ADC_CR1_RSCHSEL) /*!< Scanning will start from the first channel. */ +/** + * @} + */ + +/** + * @defgroup ADC_Hard_Trigger_Sel ADC Hard Trigger Selection + * @{ + */ +#define ADC_HARDTRIG_ADTRG_PIN (0x0U) /*!< Selects the following edge of pin ADTRG as the trigger of ADC sequence. */ +#define ADC_HARDTRIG_EVT0 (ADC_TRGSR_TRGSELA_0) /*!< Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_ITRGSELR0(x=(null), 1, 2, 3). */ +#define ADC_HARDTRIG_EVT1 (ADC_TRGSR_TRGSELA_1) /*!< Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_ITRGSELR1(x=(null), 1, 2, 3). */ +#define ADC_HARDTRIG_EVT0_EVT1 (ADC_TRGSR_TRGSELA) /*!< Selects two internal events as the trigger of ADC sequence. + The two events are specified by register ADCx_ITRGSELR0 and register ADCx_ITRGSELR1. */ +/** + * @} + */ + +/** + * @defgroup ADC_Int_Type ADC Interrupt Type + * @{ + */ +#define ADC_INT_EOCA (ADC_ICR_EOCAIEN) /*!< Interrupt of the end of conversion of sequence A. */ +#define ADC_INT_EOCB (ADC_ICR_EOCBIEN) /*!< Interrupt of the end of conversion of sequence B. */ +#define ADC_INT_ALL (ADC_INT_EOCA | ADC_INT_EOCB) +/** + * @} + */ + +/** + * @defgroup ADC_Status_Flag ADC Status Flag + * @{ + */ +#define ADC_FLAG_EOCA (ADC_ISR_EOCAF) /*!< Status flag of the end of conversion of sequence A. */ +#define ADC_FLAG_EOCB (ADC_ISR_EOCBF) /*!< Status flag of the end of conversion of sequence B. */ +#define ADC_FLAG_ALL (ADC_FLAG_EOCA | ADC_FLAG_EOCB) +/** + * @} + */ + +/** + * @defgroup ADC_Sync_Unit ADC Synchronous Unit + * @{ + */ +#define ADC_SYNC_ADC1_ADC2 (0U) /*!< ADC1 and ADC2 work synchronously. */ +/** + * @} + */ + +/** + * @defgroup ADC_Sync_Mode ADC Synchronous Mode + * @{ + */ +#define ADC_SYNC_SINGLE_DELAY_TRIG (0U) /*!< Single shot delayed trigger mode. + When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + All ADCs scan once. */ +#define ADC_SYNC_SINGLE_PARALLEL_TRIG (ADC_SYNCCR_SYNCMD_1) /*!< Single shot parallel trigger mode. + When the trigger condition occurs, all ADCs start at the same time. + All ADCs scan once. */ +#define ADC_SYNC_CYCLIC_DELAY_TRIG (ADC_SYNCCR_SYNCMD_2) /*!< Cyclic delayed trigger mode. + When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + All ADCs scan cyclicly(keep scaning till you stop them). */ +#define ADC_SYNC_CYCLIC_PARALLEL_TRIG (ADC_SYNCCR_SYNCMD_2 | \ + ADC_SYNCCR_SYNCMD_1) /*!< Single shot parallel trigger mode. + When the trigger condition occurs, all ADCs start at the same time. + All ADCs scan cyclicly(keep scaning till you stop them). */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Unit ADC Analog Watchdog Unit + * @{ + */ +#define ADC_AWD0 (0U) /*!< ADC analog watchdog 0. */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Int_Type ADC AWD Interrupt Type + * @{ + */ +#define ADC_AWD_INT_SEQA (ADC_AWDCR_AWDSS_0) /*!< Interrupt of AWD sequence A. */ +#define ADC_AWD_INT_SEQB (ADC_AWDCR_AWDSS_1) /*!< Interrupt of AWD sequence B. */ +#define ADC_AWD_INT_ALL (ADC_AWDCR_AWDSS) +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Mode ADC Analog Watchdog Mode + * @{ + */ +#define ADC_AWD_MD_CMP_OUT (0x0U) /*!< ADCValue > HighThreshold or ADCValue < LowThreshold */ +#define ADC_AWD_MD_CMP_IN (0x1U) /*!< LowThreshold < ADCValue < HighThreshold */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Status_Flag ADC AWD Status Flag + * @{ + */ +#define ADC_AWD_FLAG_CH0 (1UL << ADC_CH0) +#define ADC_AWD_FLAG_CH1 (1UL << ADC_CH1) +#define ADC_AWD_FLAG_CH2 (1UL << ADC_CH2) +#define ADC_AWD_FLAG_CH3 (1UL << ADC_CH3) +#define ADC_AWD_FLAG_CH4 (1UL << ADC_CH4) +#define ADC_AWD_FLAG_CH5 (1UL << ADC_CH5) +#define ADC_AWD_FLAG_CH6 (1UL << ADC_CH6) +#define ADC_AWD_FLAG_CH7 (1UL << ADC_CH7) +#define ADC_AWD_FLAG_CH8 (1UL << ADC_CH8) +#define ADC_AWD_FLAG_CH9 (1UL << ADC_CH9) +#define ADC_AWD_FLAG_CH10 (1UL << ADC_CH10) +#define ADC_AWD_FLAG_CH11 (1UL << ADC_CH11) +#define ADC_AWD_FLAG_CH12 (1UL << ADC_CH12) +#define ADC_AWD_FLAG_CH13 (1UL << ADC_CH13) +#define ADC_AWD_FLAG_CH14 (1UL << ADC_CH14) +#define ADC_AWD_FLAG_CH15 (1UL << ADC_CH15) +#define ADC_AWD_FLAG_CH16 (1UL << ADC_CH16) +#define ADC1_AWD_FLAG_ALL (0x1FFFFUL) +#define ADC2_AWD_FLAG_ALL (0x1FFUL) + +/** + * @} + */ + +/** + * @defgroup ADC_PGA_Unit ADC PGA Unit + * @{ + */ +#define ADC_PGA1 (0U) /*!< PGA1, belongs to ADC1. Input source can one of @ref ADC_PGA_Input_Src */ +/** + * @} + */ + +/** + * @defgroup ADC_PGA_Gain ADC PGA Gain Factor + * @{ + */ +#define ADC_PGA_GAIN_2 (0x0U) /*!< PGA gain factor is 2. */ +#define ADC_PGA_GAIN_2P133 (0x1U) /*!< PGA gain factor is 2.133. */ +#define ADC_PGA_GAIN_2P286 (0x2U) /*!< PGA gain factor is 2.286. */ +#define ADC_PGA_GAIN_2P667 (0x3U) /*!< PGA gain factor is 2.667. */ +#define ADC_PGA_GAIN_2P909 (0x4U) /*!< PGA gain factor is 2.909. */ +#define ADC_PGA_GAIN_3P2 (0x5U) /*!< PGA gain factor is 3.2. */ +#define ADC_PGA_GAIN_3P556 (0x6U) /*!< PGA gain factor is 2.556. */ +#define ADC_PGA_GAIN_4 (0x7U) /*!< PGA gain factor is 4. */ +#define ADC_PGA_GAIN_4P571 (0x8U) /*!< PGA gain factor is 4.571. */ +#define ADC_PGA_GAIN_5P333 (0x9U) /*!< PGA gain factor is 5.333. */ +#define ADC_PGA_GAIN_6P4 (0xAU) /*!< PGA gain factor is 6.4. */ +#define ADC_PGA_GAIN_8 (0xBU) /*!< PGA gain factor is 8. */ +#define ADC_PGA_GAIN_10P667 (0xCU) /*!< PGA gain factor is 10.667. */ +#define ADC_PGA_GAIN_16 (0xDU) /*!< PGA gain factor is 16. */ +#define ADC_PGA_GAIN_32 (0xEU) /*!< PGA gain factor is 32. */ +/** + * @} + */ + +/** + * @defgroup ADC_PGA_VSS ADC PGA VSS + * @{ + */ +#define ADC_PGA_VSS_PGAVSS (0U) /*!< Use pin PGAx_VSS as the reference GND of PGAx. */ +#define ADC_PGA_VSS_AVSS (1U) /*!< Use AVSS as the reference GND of PGAx. */ +/** + * @} + */ + +/** + * @defgroup ADC_PGA_Input_Src ADC PGA Input Source + * @{ + */ +#define ADC_PGA_PIN_ADC1_PA0 (ADC_PGAINSR0_PGAINSEL_0) /*!< ADC1 pin ADC1_IN0(PA0). */ +#define ADC_PGA_PIN_ADC1_PA1 (ADC_PGAINSR0_PGAINSEL_1) /*!< ADC1 pin ADC1_IN1(PA1). */ +#define ADC_PGA_PIN_ADC1_PA2 (ADC_PGAINSR0_PGAINSEL_2) /*!< ADC1 pin ADC1_IN2(PA2). */ +#define ADC_PGA_PIN_ADC1_PA3 (ADC_PGAINSR0_PGAINSEL_3) /*!< ADC1 pin ADC1_IN3(PA3). */ +#define ADC_PGA_PIN_ADC1_PA4 (ADC_PGAINSR0_PGAINSEL_4) /*!< ADC1 pin ADC12_IN4(PA4). */ +#define ADC_PGA_PIN_ADC1_PA5 (ADC_PGAINSR0_PGAINSEL_5) /*!< ADC1 pin ADC12_IN5(PA5). */ +#define ADC_PGA_PIN_ADC1_PA6 (ADC_PGAINSR0_PGAINSEL_6) /*!< ADC1 pin ADC12_IN6(PA6). */ +#define ADC_PGA_PIN_ADC1_PA7 (ADC_PGAINSR0_PGAINSEL_7) /*!< ADC1 pin ADC12_IN7(PA7). */ +#define ADC_PGA_8BIT_DAC (ADC_PGAINSR0_PGAINSEL_8) /*!< Internal 8bit-DAC to ADC1. */ +/** + * @} + */ + +/** + * @defgroup ADC_Remap_Pin ADC Remap Pin + * @{ + */ +#define ADC1_PIN_PA0 (0U) /*!< ADC1_IN0(PA0): default channel is ADC_CH0 of ADC1. */ +#define ADC1_PIN_PA1 (1U) /*!< ADC1_IN1(PA1): default channel is ADC_CH1 of ADC1. */ +#define ADC1_PIN_PA2 (2U) /*!< ADC1_IN2(PA2): default channel is ADC_CH2 of ADC1. */ +#define ADC1_PIN_PA3 (3U) /*!< ADC1_IN3(PA3): default channel is ADC_CH3 of ADC1. */ +#define ADC1_PIN_PA4 (4U) /*!< ADC12_IN4(PA4): default channel is ADC_CH4 of ADC1. */ +#define ADC1_PIN_PA5 (5U) /*!< ADC12_IN5(PA5): default channel is ADC_CH5 of ADC1. */ +#define ADC1_PIN_PA6 (6U) /*!< ADC12_IN6(PA6): default channel is ADC_CH6 of ADC1. */ +#define ADC1_PIN_PA7 (7U) /*!< ADC12_IN7(PA7): default channel is ADC_CH7 of ADC1. */ +#define ADC1_PIN_PB0 (8U) /*!< ADC12_IN8(PB0): default channel is ADC_CH8 of ADC1. */ +#define ADC1_PIN_PB1 (9U) /*!< ADC12_IN9(PB1): default channel is ADC_CH9 of ADC1. */ +#define ADC1_PIN_PC0 (10U) /*!< ADC12_IN10(PC0): default channel is ADC_CH10 of ADC1. */ +#define ADC1_PIN_PC1 (11U) /*!< ADC12_IN11(PC1): default channel is ADC_CH11 of ADC1. */ +#define ADC1_PIN_PC2 (12U) /*!< ADC1_IN12(PC2): default channel is ADC_CH12 of ADC1. */ +#define ADC1_PIN_PC3 (13U) /*!< ADC1_IN13(PC3): default channel is ADC_CH13 of ADC1. */ +#define ADC1_PIN_PC4 (14U) /*!< ADC1_IN14(PC4): default channel is ADC_CH14 of ADC1. */ +#define ADC1_PIN_PC5 (15U) /*!< ADC1_IN15(PC5): default channel is ADC_CH15 of ADC1. */ + +#define ADC2_PIN_PA4 (0U) /*!< ADC12_IN4(PA4): default channel is ADC_CH0 of ADC2 */ +#define ADC2_PIN_PA5 (1U) /*!< ADC12_IN5(PA5): default channel is ADC_CH1 of ADC2 */ +#define ADC2_PIN_PA6 (2U) /*!< ADC12_IN6(PA6): default channel is ADC_CH2 of ADC2 */ +#define ADC2_PIN_PA7 (3U) /*!< ADC12_IN7(PA7): default channel is ADC_CH3 of ADC2 */ +#define ADC2_PIN_PB0 (4U) /*!< ADC12_IN8(PB0): default channel is ADC_CH4 of ADC2 */ +#define ADC2_PIN_PB1 (5U) /*!< ADC12_IN9(PB1): default channel is ADC_CH5 of ADC2 */ +#define ADC2_PIN_PC0 (6U) /*!< ADC12_IN10(PC0): default channel is ADC_CH6 of ADC2 */ +#define ADC2_PIN_PC1 (7U) /*!< ADC12_IN11(PC1): default channel is ADC_CH7 of ADC2 */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup ADC_Global_Functions + * @{ + */ +/******************************************************************************* + Basic features + ******************************************************************************/ +int32_t ADC_Init(CM_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcAdcInit); +void ADC_DeInit(CM_ADC_TypeDef *ADCx); +int32_t ADC_StructInit(stc_adc_init_t *pstcAdcInit); +void ADC_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint8_t u8Ch, en_functional_state_t enNewState); + +void ADC_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8SampleTime); + +/* Conversion data average calculation function. */ +void ADC_ConvDataAverageConfig(CM_ADC_TypeDef *ADCx, uint16_t u16AverageCount); +void ADC_ConvDataAverageChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState); + +void ADC_TriggerConfig(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint16_t u16TriggerSel); +void ADC_TriggerCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState); +void ADC_IntCmd(CM_ADC_TypeDef *ADCx, uint8_t u8IntType, en_functional_state_t enNewState); + +void ADC_Start(CM_ADC_TypeDef *ADCx); +void ADC_Stop(CM_ADC_TypeDef *ADCx); + +uint16_t ADC_GetValue(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch); + +en_flag_status_t ADC_GetStatus(const CM_ADC_TypeDef *ADCx, uint8_t u8Flag); +void ADC_ClearStatus(CM_ADC_TypeDef *ADCx, uint8_t u8Flag); + +/******************************************************************************* + Advanced features + ******************************************************************************/ +/* Channel remap. */ +void ADC_ChRemap(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8AdcPin); +uint8_t ADC_GetChPin(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch); +void ADC_ResetChMapping(CM_ADC_TypeDef *ADCx); + +/* Sync mode. */ +void ADC_SyncModeConfig(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TriggerDelay); +void ADC_SyncModeCmd(en_functional_state_t enNewState); + +/* Analog watchdog */ +int32_t ADC_AWD_Config(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch, const stc_adc_awd_config_t *pstcAwd); + +void ADC_AWD_SetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16WatchdogMode); +uint16_t ADC_AWD_GetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit); +void ADC_AWD_SetThreshold(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16LowThreshold, uint16_t u16HighThreshold); +void ADC_AWD_SelectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch); + +void ADC_AWD_DeselectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch); + +void ADC_AWD_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, en_functional_state_t enNewState); +void ADC_AWD_IntCmd(CM_ADC_TypeDef *ADCx, uint16_t u16IntType, en_functional_state_t enNewState); +en_flag_status_t ADC_AWD_GetStatus(const CM_ADC_TypeDef *ADCx, uint32_t u32Flag); +void ADC_AWD_ClearStatus(CM_ADC_TypeDef *ADCx, uint32_t u32Flag); + +/* PGA */ +void ADC_PGA_Config(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, uint8_t u8Gain, uint8_t u8PgaVss); +void ADC_PGA_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, en_functional_state_t enNewState); +void ADC_PGA_SelectInputSrc(CM_ADC_TypeDef *ADCx, uint16_t u16PgaInputSrc); +void ADC_PGA_DeselectInputSrc(CM_ADC_TypeDef *ADCx); + +void ADC_DataRegAutoClearCmd(CM_ADC_TypeDef *ADCx, en_functional_state_t enNewState); +void ADC_SetSeqAResumeMode(CM_ADC_TypeDef *ADCx, uint16_t u16SeqAResumeMode); + +/** + * @} + */ + +#endif /* LL_ADC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_ADC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aes.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aes.h new file mode 100644 index 0000000000..e59f01da20 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aes.h @@ -0,0 +1,113 @@ +/** + ******************************************************************************* + * @file hc32_ll_aes.h + * @brief This file contains all the functions prototypes of the AES driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_AES_H__ +#define __HC32_LL_AES_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_AES + * @{ + */ + +#if (LL_AES_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AES_Global_Macros AES Global Macros + * @{ + */ + +/** + * @defgroup AES_Key_Size AES Key Size + * @{ + */ +#define AES_KEY_SIZE_16BYTE (16U) +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup AES_Global_Functions + * @{ + */ +int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Ciphertext); + +int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Plaintext); +/** + * @} + */ + +#endif /* LL_AES_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_AES_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aos.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aos.h new file mode 100644 index 0000000000..847439ae77 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aos.h @@ -0,0 +1,170 @@ +/** + ******************************************************************************* + * @file hc32_ll_aos.h + * @brief This file contains all the functions prototypes of the AOS driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_AOS_H__ +#define __HC32_LL_AOS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_AOS + * @{ + */ + +#if (LL_AOS_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AOS_Global_Macros AOS Global Macros + * @{ + */ + +/** + * @defgroup AOS_Trigger_Select AOS Trigger Select + * @{ + */ +#define AOS_DCU1 (uint32_t)(&CM_AOS->DCU_TRGSEL1) +#define AOS_DCU2 (uint32_t)(&CM_AOS->DCU_TRGSEL2) +#define AOS_DCU3 (uint32_t)(&CM_AOS->DCU_TRGSEL3) +#define AOS_DCU4 (uint32_t)(&CM_AOS->DCU_TRGSEL4) +#define AOS_DMA1_0 (uint32_t)(&CM_AOS->DMA1_TRGSEL0) +#define AOS_DMA1_1 (uint32_t)(&CM_AOS->DMA1_TRGSEL1) +#define AOS_DMA1_2 (uint32_t)(&CM_AOS->DMA1_TRGSEL2) +#define AOS_DMA1_3 (uint32_t)(&CM_AOS->DMA1_TRGSEL3) +#define AOS_DMA2_0 (uint32_t)(&CM_AOS->DMA2_TRGSEL0) +#define AOS_DMA2_1 (uint32_t)(&CM_AOS->DMA2_TRGSEL1) +#define AOS_DMA2_2 (uint32_t)(&CM_AOS->DMA2_TRGSEL2) +#define AOS_DMA2_3 (uint32_t)(&CM_AOS->DMA2_TRGSEL3) +#define AOS_DMA_RC (uint32_t)(&CM_AOS->DMA_TRGSELRC) +#define AOS_TMR6_0 (uint32_t)(&CM_AOS->TMR6_HTSSR0) +#define AOS_TMR6_1 (uint32_t)(&CM_AOS->TMR6_HTSSR1) +#define AOS_TMR0 (uint32_t)(&CM_AOS->TMR0_HTSSR) +#define AOS_EVTPORT12 (uint32_t)(&CM_AOS->PEVNTTRGSR12) +#define AOS_EVTPORT34 (uint32_t)(&CM_AOS->PEVNTTRGSR34) +#define AOS_TMRA_0 (uint32_t)(&CM_AOS->TMRA_HTSSR0) +#define AOS_TMRA_1 (uint32_t)(&CM_AOS->TMRA_HTSSR1) +#define AOS_OTS (uint32_t)(&CM_AOS->OTS_TRG) +#define AOS_ADC1_0 (uint32_t)(&CM_AOS->ADC1_ITRGSELR0) +#define AOS_ADC1_1 (uint32_t)(&CM_AOS->ADC1_ITRGSELR1) +#define AOS_ADC2_0 (uint32_t)(&CM_AOS->ADC2_ITRGSELR0) +#define AOS_ADC2_1 (uint32_t)(&CM_AOS->ADC2_ITRGSELR1) +#define AOS_COMM_1 (uint32_t)(&CM_AOS->COMTRG1) +#define AOS_COMM_2 (uint32_t)(&CM_AOS->COMTRG2) + +/** + * @} + */ + +/** + * @defgroup AOS_Common_Trigger_ID AOS Common Trigger ID + * @{ + */ +#define AOS_COMM_TRIG1 (1UL << 30U) +#define AOS_COMM_TRIG2 (1UL << 31U) +#define AOS_COMM_TRIG_MASK (AOS_COMM_TRIG1 | AOS_COMM_TRIG2) + +/** + * @} + */ + +/** + * @defgroup AOS_Trigger_Select_Mask AOS Trigger Select Mask + * @{ + */ +#define AOS_TRIG_SEL_MASK (0x1FFUL) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup AOS_Global_Functions + * @{ + */ + +/** + * @brief AOS software trigger. + * @param None + * @retval None + */ +__STATIC_INLINE void AOS_SW_Trigger(void) +{ + WRITE_REG32(bCM_AOS->INTSFTTRG_b.STRG, SET); +} + +void AOS_CommonTriggerCmd(uint32_t u32TriggerSel, uint32_t u32CommonTrigger, en_functional_state_t enNewState); +void AOS_SetTriggerEventSrc(uint32_t u32TriggerSel, en_event_src_t enEvent); + +/** + * @} + */ + +#endif /* LL_AOS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_AOS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_can.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_can.h new file mode 100644 index 0000000000..2884ecaf97 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_can.h @@ -0,0 +1,664 @@ +/** + ******************************************************************************* + * @file hc32_ll_can.h + * @brief This file contains all the functions prototypes of the CAN driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CAN_H__ +#define __HC32_LL_CAN_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CAN + * @{ + */ +#if (LL_CAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CAN_Global_Types CAN Global Types + * @{ + */ +/** + * @brief CAN bit time configuration structure. + * @note 1. TQ = u32Prescaler / CANClock. + * @note 2. Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ. + * @note 3. Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2)) + * @note 4. See user manual of the target MCU and ISO11898-1 for more details. + */ +typedef struct { + uint32_t u32Prescaler; /*!< Specifies the prescaler of CAN clock, [1, 256]. */ + uint32_t u32TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + u32TimeSeg1 Contains synchronization segment, + propagation time segment and phase buffer segment 1. */ + uint32_t u32TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + Phase buffer segment 2. */ + uint32_t u32SJW; /*!< Synchronization Jump Width. + Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. */ +} stc_can_bit_time_config_t; + +/** + * @brief CAN acceptance filter configuration structure. + */ +typedef struct { + uint32_t u32ID; /*!< Specifies the identifier(ID). 11 bits standard ID or 29 bits extended ID, depending on IDE. */ + uint32_t u32IDMask; /*!< Specifies the identifier(ID) mask. The mask bits of ID will be ignored by the acceptance filter. */ + uint32_t u32IDType; /*!< Specifies the identifier(ID) type. This parameter can be a value of @ref CAN_ID_Type */ +} stc_can_filter_config_t; + +/* CAN-FD structure */ + +/** + * @brief TTCAN configuration structure. + */ +typedef struct { + uint32_t u32RefMsgID; /*!< Reference message identifier. */ + uint32_t u32RefMsgIDE; /*!< Reference message identifier extension bit. + '1' to set the ID which is specified by parameter 'u32RefMsgID' as an extended ID while + '0' to set it as a standard ID. */ + uint8_t u8NTUPrescaler; /*!< Prescaler of NTU(network time unit). The source is the bit time which is defined by SBT. + This parameter can be a value of @ref TTCAN_NTU_Prescaler */ + uint8_t u8TxBufMode; /*!< TTCAN Transmit Buffer Mode. + This parameter can be a value of @ref TTCAN_Tx_Buf_Mode */ + uint16_t u16TriggerType; /*!< Trigger type of TTCAN. + This parameter can be a value of @ref TTCAN_Trigger_Type */ + uint16_t u16TxEnableWindow; /*!< Tx_Enable window. Time period within which the transmission of a message may be started. Range is [1, 16] */ + uint16_t u16TxTriggerTime; /*!< Specifies for the referred message the time window of the matrix cycle at which it is to be transmitted. Range is [0, 65535] */ + uint16_t u16WatchTriggerTime; /*!< Time mark used to check whether the time since the last valid reference message has been too long. Range is [0, 65535] */ +} stc_can_ttc_config_t; + +/** + * @brief CAN initialization structure. + */ +typedef struct { + stc_can_bit_time_config_t stcBitCfg; /*!< Bit time configuration of classical CAN bit. @ref stc_can_bit_time_config_t */ + stc_can_filter_config_t *pstcFilter; /*!< Pointer to a @ref stc_can_filter_config_t structure that + contains the configuration informations for the acceptance filters. */ + uint16_t u16FilterSelect; /*!< Selects acceptance filters. + This parameter can be values of @ref CAN_Acceptance_Filter */ + uint8_t u8WorkMode; /*!< Specifies the work mode of CAN. + This parameter can be a value of @ref CAN_Work_Mode */ + uint8_t u8PTBSingleShotTx; /*!< Enable or disable single shot transmission of PTB. + This parameter can be a value of @ref PTB_SingleShot_Tx_En */ + uint8_t u8STBSingleShotTx; /*!< Enable or disable single shot transmission of STB. + This parameter can be a value of @ref STB_SingleShot_Tx_En */ + uint8_t u8STBPrioMode; /*!< Enable or disable the priority decision mode of STB. + This parameter can be a value of @ref CAN_STB_Prio_Mode_En + NOTE: A frame in the PTB has always the highest priority regardless of the ID. */ + uint8_t u8RxWarnLimit; /*!< Specifies receive buffer almost full warning limit. Rang is [1, 8]. + Each CAN unit has 8 receive buffers. When the number of received frames reaches + the value specified by u8RxWarnLimit, register bit RTIF.RAFIF is set and the interrupt occurred + if it was enabled. */ + uint8_t u8ErrorWarnLimit; /*!< Specifies programmable error warning limit. Range is [0, 15]. + Error warning limit = (u8ErrorWarnLimit + 1) * 8. */ + uint8_t u8RxAllFrame; /*!< Enable or disable receive all frames(includes frames with error). + This parameter can be a value of @ref CAN_Rx_All_En */ + uint8_t u8RxOvfMode; /*!< Receive buffer overflow mode. In case of a full receive buffer when a new frame is received. + This parameter can be a value of @ref CAN_Rx_Ovf_Mode */ + uint8_t u8SelfAck; /*!< Enable or disable self-acknowledge. + This parameter can be a value of @ref CAN_Self_ACK_En */ + + stc_can_ttc_config_t *pstcCanTtc; /*!< Pointer to a TTCAN configuration structure. @ref stc_can_ttc_config_t + Set it to NULL if not needed TTCAN. */ +} stc_can_init_t; + +/** + * @brief CAN error information structure. + */ +typedef struct { + uint8_t u8ArbitrLostPos; /*!< Bit position in the frame where the arbitration has been lost. */ + uint8_t u8ErrorType; /*!< CAN error type. This parameter can be a value of @ref CAN_Err_Type */ + uint8_t u8RxErrorCount; /*!< Receive error count. */ + uint8_t u8TxErrorCount; /*!< Transmit error count. */ +} stc_can_error_info_t; + +/** + * @brief CAN TX frame data structure. + */ +typedef struct { + uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */ + union { + uint32_t u32Ctrl; + struct { + uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame. + It should be zero while the frame is remote frame. + This parameter can be a value of @ref CAN_Data_Length_Code */ + uint32_t BRS: 1; /*!< Bit rate switch. */ + uint32_t FDF: 1; /*!< CAN FD frame. */ + uint32_t RTR: 1; /*!< Remote transmission request bit. + It is used to distinguish between data frames and remote frames. */ + uint32_t IDE: 1; /*!< Identifier extension flag. + It is used to distinguish between standard format and extended format. + This parameter can be a 1 or 0. */ + uint32_t RSVD: 24; /*!< Reserved bits. */ + }; + }; + uint8_t au8Data[8U]; /*!< TX data payload. */ +} stc_can_tx_frame_t; + +/** + * @brief CAN RX frame data structure. + */ +typedef struct { + uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */ + union { + uint32_t u32Ctrl; + struct { + uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame. + It should be zero while the frame is remote frame. + This parameter can be a value of @ref CAN_Data_Length_Code */ + uint32_t BRS: 1; /*!< Bit rate switch. */ + uint32_t FDF: 1; /*!< CAN FD frame. */ + uint32_t RTR: 1; /*!< Remote transmission request bit. + It is used to distinguish between data frames and remote frames. */ + uint32_t IDE: 1; /*!< Identifier extension flag. + It is used to distinguish between standard format and extended format. + This parameter can be 1 or 0. */ + uint32_t RSVD: 4; /*!< Reserved bits. */ + uint32_t TX: 1; /*!< This bit is set to 1 when receiving self-transmitted data in loopback mode. */ + uint32_t ERRT: 3; /*!< Error type. */ + uint32_t CYCLE_TIME: 16; /*!< Cycle time of time-triggered communication(TTC). */ + }; + }; + uint8_t au8Data[8U]; /*!< RX data payload. */ +} stc_can_rx_frame_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CAN_Global_Macros CAN Global Macros + * @{ + */ + +/** + * @defgroup CAN_Work_Mode CAN Work Mode + * @{ + */ +#define CAN_WORK_MD_NORMAL (0U) /*!< Normal work mode. */ +#define CAN_WORK_MD_SILENT (1U) /*!< Silent work mode. Prohibit data transmission. */ +#define CAN_WORK_MD_ILB (2U) /*!< Internal loop back mode, just for self-test while developing. */ +#define CAN_WORK_MD_ELB (3U) /*!< External loop back mode, just for self-test while developing. */ +#define CAN_WORK_MD_ELB_SILENT (4U) /*!< External loop back silent mode, just for self-test while developing. + It is forbidden to respond to received frames and error frames, + but data can be transmitted. */ +/** + * @} + */ + +/** + * @defgroup CAN_Tx_Buf_Type CAN Transmit Buffer Type + * @{ + */ +#define CAN_TX_BUF_PTB (0U) /*!< Primary transmit buffer. */ +#define CAN_TX_BUF_STB (1U) /*!< Secondary transmit buffer. */ +/** + * @} + */ + +/** + * @defgroup CAN_Data_Length_Code CAN Data Length Code + * @{ + */ +#define CAN_DLC0 (0x0U) /*!< CAN2.0 and CAN FD: the size of data field is 0 bytes. */ +#define CAN_DLC1 (0x1U) /*!< CAN2.0 and CAN FD: the size of data field is 1 bytes. */ +#define CAN_DLC2 (0x2U) /*!< CAN2.0 and CAN FD: the size of data field is 2 bytes. */ +#define CAN_DLC3 (0x3U) /*!< CAN2.0 and CAN FD: the size of data field is 3 bytes. */ +#define CAN_DLC4 (0x4U) /*!< CAN2.0 and CAN FD: the size of data field is 4 bytes. */ +#define CAN_DLC5 (0x5U) /*!< CAN2.0 and CAN FD: the size of data field is 5 bytes. */ +#define CAN_DLC6 (0x6U) /*!< CAN2.0 and CAN FD: the size of data field is 6 bytes. */ +#define CAN_DLC7 (0x7U) /*!< CAN2.0 and CAN FD: the size of data field is 7 bytes. */ +#define CAN_DLC8 (0x8U) /*!< CAN2.0 and CAN FD: the size of data field is 8 bytes. */ +/** + * @} + */ + +/** + * @defgroup PTB_SingleShot_Tx_En PTB Single Shot Transmission Function Control + * @{ + */ +#define CAN_PTB_SINGLESHOT_TX_DISABLE (0x0U) /*!< Primary transmit buffer auto retransmit. */ +#define CAN_PTB_SINGLESHOT_TX_ENABLE (CAN_CFG_STAT_TPSS) /*!< Primary transmit buffer single short transmit. */ +/** + * @} + */ + +/** + * @defgroup STB_SingleShot_Tx_En STB Single Shot Transmission Function Control + * @{ + */ +#define CAN_STB_SINGLESHOT_TX_DISABLE (0x0U) /*!< Secondary transmit buffer auto retransmit. */ +#define CAN_STB_SINGLESHOT_TX_ENABLE (CAN_CFG_STAT_TSSS) /*!< Secondary transmit buffer single short transmit. */ +/** + * @} + */ + +/** + * @defgroup CAN_Tx_Request CAN Transmission Request + * @{ + */ +#define CAN_TX_REQ_STB_ONE (CAN_TCMD_TSONE) /*!< Transmit one STB frame. */ +#define CAN_TX_REQ_STB_ALL (CAN_TCMD_TSALL) /*!< Transmit all STB frames. */ +#define CAN_TX_REQ_PTB (CAN_TCMD_TPE) /*!< Transmit PTB frame. */ +/** + * @} + */ + +/** + * @defgroup CAN_STB_Prio_Mode_En CAN STB Priority Mode Function Control + * @note A frame in the PTB has always the highest priority regardless of the ID. + * @{ + */ +#define CAN_STB_PRIO_MD_DISABLE (0x0U) /*!< The frame first in will first be transmitted. */ +#define CAN_STB_PRIO_MD_ENABLE (CAN_TCTRL_TSMODE) /*!< The frame with lower ID will first be transmitted. */ +/** + * @} + */ + +/** + * @defgroup CAN_Tx_Buf_Status CAN Transmit Buffer Status + * @{ + */ +#define CAN_TX_BUF_EMPTY (0x0U) /*!< TTCAN is disabled(TTEN == 0): STB is empty. + TTCAN is disabled(TTEN == 1) and transmit buffer is specified by TBPTR and TTPTR(TTTBM == 1): + PTB and STB are both empty. */ +#define CAN_TX_BUF_NOT_MORE_THAN_HALF (0x1U) /*!< TTEN == 0: STB is less than or equal to half full; + TTEN == 1 && TTTBM == 1: PTB and STB are neither empty. */ +#define CAN_TX_BUF_MORE_THAN_HALF (0x2U) /*!< TTEN == 0: STB is more than half full; + TTEN == 1 && TTTBM == 1: reserved value. */ +#define CAN_TX_BUF_FULL (0x3U) /*!< TTEN == 0: STB is full; + TTEN == 1 && TTTBM == 1: PTB and STB are both full. */ +/** + * @} + */ + +/** + * @defgroup CAN_Rx_Buf_Status CAN Receive Buffer Status + * @{ + */ +#define CAN_RX_BUF_EMPTY (0x0U) /*!< Receive buffer is empty. */ +#define CAN_RX_BUF_NOT_WARN (0x1U) /*!< Receive buffer is not empty, but is less than almost full warning limit. */ +#define CAN_RX_BUF_WARN (0x2U) /*!< Receive buffer is not full and not overflow, but is more than or equal to almost full warning limit. */ +#define CAN_RX_BUF_FULL (0x3U) /*!< Receive buffer is full. */ +/** + * @} + */ + +/** + * @defgroup CAN_Rx_All_En CAN Receive All Frames + * @{ + */ +#define CAN_RX_ALL_FRAME_DISABLE (0x0U) /*!< Only receives correct frames. */ +#define CAN_RX_ALL_FRAME_ENABLE (CAN_RCTRL_RBALL) /*!< Receives all frames, including frames with error. */ +/** + * @} + */ + +/** + * @defgroup CAN_Rx_Ovf_Mode CAN Receive Buffer Overflow Mode + * @{ + */ +#define CAN_RX_OVF_SAVE_NEW (0x0U) /*!< Saves the newly received data and the oldest frame will be overwritten. */ +#define CAN_RX_OVF_DISCARD_NEW (CAN_RCTRL_ROM) /*!< Discard the newly received data. */ +/** + * @} + */ + +/** + * @defgroup CAN_Self_ACK_En CAN Self-ACK Function Control + * @{ + */ +#define CAN_SELF_ACK_DISABLE (0x0U) /*!< Disable self-acknowledge. */ +#define CAN_SELF_ACK_ENABLE (CAN_RCTRL_SACK) /*!< Enable self-acknowledge. */ +/** + * @} + */ + +/** + * @defgroup CAN_Interrupt_Type CAN Interrupt Type + * @{ + */ +#define CAN_INT_ERR_INT (1UL << 1U) /*!< Register bit RTIE.EIE. The interrupt RTIF.EIF will be set if enabled by RTIE.EIE under the following conditions: + The border of the error warning limit has been crossed in either direction by RECNT or TECNT or + the BUSOFF bit has been changed in either direction. */ +#define CAN_INT_STB_TX (1UL << 2U) /*!< Register bit RTIE.TSIE. STB was transmitted. */ +#define CAN_INT_PTB_TX (1UL << 3U) /*!< Register bit RTIE.TPIE. PTB was transmitted. */ +#define CAN_INT_RX_BUF_WARN (1UL << 4U) /*!< Register bit RTIE.RAFIE. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */ +#define CAN_INT_RX_BUF_FULL (1UL << 5U) /*!< Register bit RTIE.RFIE. The FIFO of receive buffer is full. */ +#define CAN_INT_RX_OVERRUN (1UL << 6U) /*!< Register bit RTIE.ROIE. Receive buffers are full and there is a further message to be stored. */ +#define CAN_INT_RX (1UL << 7U) /*!< Register bit RTIE.RIE. Received a valid data frame or remote frame. */ +#define CAN_INT_BUS_ERR (1UL << 9U) /*!< Register bit ERRINT.BEIE. Each of the error defined by EALCAP.KOER can cause bus-error inetrrupt. */ +#define CAN_INT_ARBITR_LOST (1UL << 11U) /*!< Register bit ERRINT.ALIE. Arbitration lost. */ +#define CAN_INT_ERR_PASSIVE (1UL << 13U) /*!< Register bit ERRINT.EPIE. A change from error-passive to error-active or error-active to error-passive has occurred. */ + +#define CAN_INT_ALL (CAN_INT_ERR_INT | \ + CAN_INT_STB_TX | \ + CAN_INT_PTB_TX | \ + CAN_INT_RX_BUF_WARN | \ + CAN_INT_RX_BUF_FULL | \ + CAN_INT_RX_OVERRUN | \ + CAN_INT_RX | \ + CAN_INT_BUS_ERR | \ + CAN_INT_ARBITR_LOST | \ + CAN_INT_ERR_PASSIVE) +/** + * @} + */ + +/** + * @defgroup CAN_Status_Flag CAN Status Flag + * @{ + */ +#define CAN_FLAG_BUS_OFF (1UL << 0U) /*!< Register bit CFG_STAT.BUSOFF. CAN bus off. */ +#define CAN_FLAG_TX_GOING (1UL << 1U) /*!< Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. */ +#define CAN_FLAG_RX_GOING (1UL << 2U) /*!< Register bit CFG_STAT.RACTIVE. CAN bus is receiving. */ +#define CAN_FLAG_RX_BUF_OVF (1UL << 5U) /*!< Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one frame will be lost. */ +#define CAN_FLAG_TX_BUF_FULL (1UL << 8U) /*!< Register bit RTIE.TSFF. Transmit buffers are all full. + TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled. + TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled.*/ +#define CAN_FLAG_TX_ABORTED (1UL << 16U) /*!< Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. */ +#define CAN_FLAG_ERR_INT (1UL << 17U) /*!< Register bit RTIF.EIF. The interrupt RTIF.EIF will be set if enabled by RTIE.EIE under the following conditions: + The border of the error warning limit has been crossed in either direction by RECNT or TECNT or + the BUSOFF bit has been changed in either direction. */ +#define CAN_FLAG_STB_TX (1UL << 18U) /*!< Register bit RTIF.TSIF. STB was transmitted. */ +#define CAN_FLAG_PTB_TX (1UL << 19U) /*!< Register bit RTIF.TPIF. PTB was transmitted. */ +#define CAN_FLAG_RX_BUF_WARN (1UL << 20U) /*!< Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */ +#define CAN_FLAG_RX_BUF_FULL (1UL << 21U) /*!< Register bit RTIF.RFIF. The FIFO of receive buffer is full. */ +#define CAN_FLAG_RX_OVERRUN (1UL << 22U) /*!< Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. */ +#define CAN_FLAG_RX (1UL << 23U) /*!< Register bit RTIF.RIF. Received a valid data frame or remote frame. */ +#define CAN_FLAG_BUS_ERR (1UL << 24U) /*!< Register bit ERRINT.BEIF. Each of the error defined by EALCAP.KOER can make this flag set. */ +#define CAN_FLAG_ARBITR_LOST (1UL << 26U) /*!< Register bit ERRINT.ALIF. Arbitration lost. */ +#define CAN_FLAG_ERR_PASSIVE (1UL << 28U) /*!< Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. */ +#define CAN_FLAG_ERR_PASSIVE_NODE (1UL << 30U) /*!< Register bit ERRINT.EPASS. The node is an error-passive node. */ +#define CAN_FLAG_TEC_REC_WARN (1UL << 31U) /*!< Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. */ + +#define CAN_FLAG_ALL (CAN_FLAG_BUS_OFF | \ + CAN_FLAG_TX_GOING | \ + CAN_FLAG_RX_GOING | \ + CAN_FLAG_RX_BUF_OVF | \ + CAN_FLAG_TX_BUF_FULL | \ + CAN_FLAG_TX_ABORTED | \ + CAN_FLAG_ERR_INT | \ + CAN_FLAG_STB_TX | \ + CAN_FLAG_PTB_TX | \ + CAN_FLAG_RX_BUF_WARN | \ + CAN_FLAG_RX_BUF_FULL | \ + CAN_FLAG_RX_OVERRUN | \ + CAN_FLAG_RX | \ + CAN_FLAG_BUS_ERR | \ + CAN_FLAG_ARBITR_LOST | \ + CAN_FLAG_ERR_PASSIVE | \ + CAN_FLAG_ERR_PASSIVE_NODE | \ + CAN_FLAG_TEC_REC_WARN) + +#define CAN_FLAG_CLR_ALL (CAN_FLAG_RX_BUF_OVF | \ + CAN_FLAG_TX_ABORTED | \ + CAN_FLAG_ERR_INT | \ + CAN_FLAG_STB_TX | \ + CAN_FLAG_PTB_TX | \ + CAN_FLAG_RX_BUF_WARN | \ + CAN_FLAG_RX_BUF_FULL | \ + CAN_FLAG_RX_OVERRUN | \ + CAN_FLAG_RX | \ + CAN_FLAG_BUS_ERR | \ + CAN_FLAG_ARBITR_LOST | \ + CAN_FLAG_ERR_PASSIVE) +/** + * @} + */ + +/** + * @defgroup CAN_ID_Type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD_EXT (0x0U) /*!< Acceptance filter accept frames with both standard ID and extended ID. */ +#define CAN_ID_STD (CAN_ACF_AIDEE) /*!< Acceptance filter accept frames with only standard ID. */ +#define CAN_ID_EXT (CAN_ACF_AIDEE | \ + CAN_ACF_AIDE) /*!< Acceptance filter accept frames with only extended ID. */ +/** + * @} + */ + +/** + * @defgroup CAN_Err_Type CAN Error Type + * @{ + */ +#define CAN_ERR_NONE (0U) /*!< No error. */ +#define CAN_ERR_BIT (0x1U) /*!< Error is bit error. */ +#define CAN_ERR_FORM (0x2U) /*!< Error is form error. */ +#define CAN_ERR_STUFF (0x3U) /*!< Error is stuff error. */ +#define CAN_ERR_ACK (0x4U) /*!< Error is ACK error. */ +#define CAN_ERR_CRC (0x5U) /*!< Error is CRC error. */ +#define CAN_ERR_OTHER (0x6U) /*!< Error is other error. + Dominant bits after own error flag, received active Error Flag too long, + dominant bit during Passive-Error-Flag after ACK error. */ +/** + * @} + */ + +/** + * @defgroup CAN_Acceptance_Filter CAN Acceptance Filter + * @{ + */ +#define CAN_FILTER1 (CAN_ACFEN_AE_1) /*!< Acceptance filter 1 select bit. */ +#define CAN_FILTER2 (CAN_ACFEN_AE_2) /*!< Acceptance filter 2 select bit. */ +#define CAN_FILTER3 (CAN_ACFEN_AE_3) /*!< Acceptance filter 3 select bit. */ +#define CAN_FILTER4 (CAN_ACFEN_AE_4) /*!< Acceptance filter 4 select bit. */ +#define CAN_FILTER5 (CAN_ACFEN_AE_5) /*!< Acceptance filter 5 select bit. */ +#define CAN_FILTER6 (CAN_ACFEN_AE_6) /*!< Acceptance filter 6 select bit. */ +#define CAN_FILTER7 (CAN_ACFEN_AE_7) /*!< Acceptance filter 7 select bit. */ +#define CAN_FILTER8 (CAN_ACFEN_AE_8) /*!< Acceptance filter 8 select bit. */ +#define CAN_FILTER_ALL (0xFFU) +/** + * @} + */ + +/** + * @defgroup TTCAN_Tx_Buf_Mode TTCAN Transmit Buffer Mode + * @{ + */ +#define CAN_TTC_TX_BUF_MD_CAN (0x0U) /*!< Normal CAN mode. TTCAN transmit buffer depends on the priority mode of STB which is defined by @ref CAN_STB_Prio_Mode_En */ +#define CAN_TTC_TX_BUF_MD_TTCAN (CAN_TCTRL_TTTBM) /*!< Full TTCAN mode. TTCAN transmit buffer is pointed by TBSLOT.TBPTR(for data filling) and + TRG_CFG.TTPTR(for data transmission). */ +/** + * @} + */ + +/** + * @defgroup TTCAN_Tx_Buf_Sel TTCAN Transmit Buffer Selection + * @{ + */ +#define CAN_TTC_TX_BUF_PTB (0x0U) /*!< Point to PTB. */ +#define CAN_TTC_TX_BUF_STB1 (0x1U) /*!< Point to STB slot 1. */ +#define CAN_TTC_TX_BUF_STB2 (0x2U) /*!< Point to STB slot 2. */ +#define CAN_TTC_TX_BUF_STB3 (0x3U) /*!< Point to STB slot 3. */ +#define CAN_TTC_TX_BUF_STB4 (0x4U) /*!< Point to STB slot 4. */ +/** + * @} + */ + +/** + * @defgroup TTCAN_Tx_Buf_Mark_State TTCAN Transmit Buffer Mark State + * @{ + */ +#define CAN_TTC_TX_BUF_MARK_EMPTY (CAN_TBSLOT_TBE) /*!< Marks the transmit buffer selected by TBSLOT.TBPTR as "empty". + TBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. + If a transmission from this slot is active, then TBE stays set as long as either the + transmission completes or after a transmission error or arbitration loss the transmission + is not active any more. If both TBF and TBE are set, then TBE wins. */ +#define CAN_TTC_TX_BUF_MARK_FILLED (CAN_TBSLOT_TBF) /*!< Marks the transmit buffer selected by TBSLOT.TBPTR as "filled". + TBF is automatically reset to 0 as soon as the slot is marked as filled and RTIE.TSFF=1. + If both TBF and TBE are set, then TBE wins. */ +/** + * @} + */ + +/** + * @defgroup TTCAN_Interrupt_Type TTCAN Interrupt Type + * @{ + */ +#define CAN_TTC_INT_TIME_TRIG (CAN_TTCFG_TTIE) /*!< Time trigger interrupt. */ +#define CAN_TTC_INT_WATCH_TRIG (CAN_TTCFG_WTIE) /*!< Watch trigger interrupt. */ +#define CAN_TTC_INT_ALL (CAN_TTC_INT_TIME_TRIG | \ + CAN_TTC_INT_WATCH_TRIG) +/** + * @} + */ + +/** + * @defgroup TTCAN_Status_Flag TTCAN Status Flag + * @{ + */ +#define CAN_TTC_FLAG_TIME_TRIG (CAN_TTCFG_TTIF) /*!< Time trigger interrupt flag. */ +#define CAN_TTC_FLAG_TRIG_ERR (CAN_TTCFG_TEIF) /*!< Trigger error interrupt flag. */ +#define CAN_TTC_FLAG_WATCH_TRIG (CAN_TTCFG_WTIF) /*!< Watch trigger interrupt flag. */ + +#define CAN_TTC_FLAG_ALL (CAN_TTC_FLAG_TIME_TRIG | \ + CAN_TTC_FLAG_TRIG_ERR | \ + CAN_TTC_FLAG_WATCH_TRIG) +/** + * @} + */ + +/** + * @defgroup TTCAN_NTU_Prescaler TTCAN Network Time Unit Prescaler + * @{ + */ +#define CAN_TTC_NTU_PRESCALER1 (0x0U) /*!< NTU is SBT bit time * 1. */ +#define CAN_TTC_NTU_PRESCALER2 (CAN_TTCFG_T_PRESC_0) /*!< NTU is SBT bit time * 2. */ +#define CAN_TTC_NTU_PRESCALER4 (CAN_TTCFG_T_PRESC_1) /*!< NTU is SBT bit time * 4. */ +#define CAN_TTC_NTU_PRESCALER8 (CAN_TTCFG_T_PRESC) /*!< NTU is SBT bit time * 8. */ +/** + * @} + */ + +/** + * @defgroup TTCAN_Trigger_Type TTCAN Trigger Type + * @note Except for the immediate trigger, all triggers set TTIF if TTIE is enabled. + * @{ + */ +#define CAN_TTC_TRIG_IMMED_TRIG (0x0U) /*!< Immediate trigger for immediate transmission. */ +#define CAN_TTC_TRIG_TIME_TRIG (CAN_TRG_CFG_TTYPE_0) /*!< Time trigger for receive triggers. */ +#define CAN_TTC_TRIG_SINGLESHOT_TX_TRIG (CAN_TRG_CFG_TTYPE_1) /*!< Single shot transmit trigger for exclusive time windows. */ +#define CAN_TTC_TRIG_TX_START_TRIG (CAN_TRG_CFG_TTYPE_1 | \ + CAN_TRG_CFG_TTYPE_0) /*!< Transmit start trigger for merged arbitrating time windows. */ +#define CAN_TTC_TRIG_TX_STOP_TRIG (CAN_TRG_CFG_TTYPE_2) /*!< Transmit stop trigger for merged arbitrating time windows. */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CAN_Global_Functions + * @{ + */ +/* Classical CAN */ +int32_t CAN_Init(CM_CAN_TypeDef *CANx, const stc_can_init_t *pstcCanInit); +int32_t CAN_StructInit(stc_can_init_t *pstcCanInit); +void CAN_DeInit(CM_CAN_TypeDef *CANx); +void CAN_IntCmd(CM_CAN_TypeDef *CANx, uint32_t u32IntType, en_functional_state_t enNewState); +int32_t CAN_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType, const stc_can_tx_frame_t *pstcTx); +void CAN_StartTx(CM_CAN_TypeDef *CANx, uint8_t u8TxRequest); +void CAN_AbortTx(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType); +int32_t CAN_GetRxFrame(CM_CAN_TypeDef *CANx, stc_can_rx_frame_t *pstcRx); + +en_flag_status_t CAN_GetStatus(const CM_CAN_TypeDef *CANx, uint32_t u32Flag); +void CAN_ClearStatus(CM_CAN_TypeDef *CANx, uint32_t u32Flag); +uint32_t CAN_GetStatusValue(const CM_CAN_TypeDef *CANx); +int32_t CAN_GetErrorInfo(const CM_CAN_TypeDef *CANx, stc_can_error_info_t *pstcErr); +uint8_t CAN_GetTxBufStatus(const CM_CAN_TypeDef *CANx); +uint8_t CAN_GetRxBufStatus(const CM_CAN_TypeDef *CANx); +void CAN_FilterCmd(CM_CAN_TypeDef *CANx, uint16_t u16FilterSelect, en_functional_state_t enNewState); +void CAN_SetRxWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8RxWarnLimit); +void CAN_SetErrorWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8ErrorWarnLimit); + +/* TTCAN */ +int32_t CAN_TTC_StructInit(stc_can_ttc_config_t *pstcCanTtc); +int32_t CAN_TTC_Config(CM_CAN_TypeDef *CANx, const stc_can_ttc_config_t *pstcCanTtc); +void CAN_TTC_IntCmd(CM_CAN_TypeDef *CANx, uint8_t u8IntType, en_functional_state_t enNewState); +void CAN_TTC_Cmd(CM_CAN_TypeDef *CANx, en_functional_state_t enNewState); + +en_flag_status_t CAN_TTC_GetStatus(const CM_CAN_TypeDef *CANx, uint8_t u8Flag); +void CAN_TTC_ClearStatus(CM_CAN_TypeDef *CANx, uint8_t u8Flag); +uint8_t CAN_TTC_GetStatusValue(const CM_CAN_TypeDef *CANx); + +void CAN_TTC_SetTriggerType(CM_CAN_TypeDef *CANx, uint16_t u16TriggerType); +void CAN_TTC_SetTxEnableWindow(CM_CAN_TypeDef *CANx, uint16_t u16TxEnableWindow); +void CAN_TTC_SetTxTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16TxTriggerTime); +void CAN_TTC_SetWatchTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16WatchTriggerTime); + +int32_t CAN_TTC_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8CANTTCTxBuf, const stc_can_tx_frame_t *pstcTx); + +int32_t CAN_TTC_GetConfig(const CM_CAN_TypeDef *CANx, stc_can_ttc_config_t *pstcCanTtc); + +/** + * @} + */ + +#endif /* LL_CAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_clk.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_clk.h new file mode 100644 index 0000000000..d49864c3e2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_clk.h @@ -0,0 +1,748 @@ +/** + ******************************************************************************* + * @file hc32_ll_clk.h + * @brief This file contains all the functions prototypes of the CLK driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CLK_H__ +#define __HC32_LL_CLK_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CLK + * @{ + */ + +#if (LL_CLK_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CLK_Global_Types CLK Global Types + * @{ + */ +/** + * @brief CLK XTAL configuration structure definition + */ +typedef struct { + uint8_t u8State; /*!< The new state of the XTAL. + This parameter can be a value of @ref CLK_XTAL_Config */ + + uint8_t u8Drv; /*!< The XTAL drive ability. + This parameter can be a value of @ref CLK_XTAL_Config */ + + uint8_t u8Mode; /*!< The XTAL mode selection osc or exclk. + This parameter can be a value of @ref CLK_XTAL_Config */ + + uint8_t u8SuperDrv; /*!< The XTAL super drive on or off. + This parameter can be a value of @ref CLK_XTAL_Config */ + + uint8_t u8StableTime; /*!< The XTAL stable time selection. + This parameter can be a value of @ref CLK_XTAL_Config */ +} stc_clock_xtal_init_t; + +/** + * @brief CLK XTAL fault detect configuration structure definition + */ +typedef struct { + uint8_t u8State; /*!< Specifies the new state of XTALSTD. + This parameter can be a value of @ref CLK_XTALSTD_Config */ + + uint8_t u8Mode; /*!< Specifies the XTALSTD mode. + This parameter can be a value of @ref CLK_XTALSTD_Config */ + + uint8_t u8Int; /*!< Specifies the XTALSTD interrupt on or off. + This parameter can be a value of @ref CLK_XTALSTD_Config */ + + uint8_t u8Reset; /*!< Specifies the XTALSTD reset on or off. + This parameter can be a value of @ref CLK_XTALSTD_Config */ +} stc_clock_xtalstd_init_t; + +/** + * @brief CLK XTAL32 configuration structure definition + */ +typedef struct { + uint8_t u8State; /*!< Xtal32 new state, + @ref CLK_XTAL32_Config for details */ + + uint8_t u8Drv; /*!< Xtal32 drive capacity setting, + @ref CLK_XTAL32_Config for details */ + + uint8_t u8Filter; /*!< Xtal32 noise filter setting, + @ref CLK_XTAL32_Config for details */ +} stc_clock_xtal32_init_t; + +/** + * @brief CLK clock frequency configuration structure definition + */ +typedef struct { + union { + uint32_t SCFGR; /*!< clock frequency config register */ + struct { + uint32_t PCLK0S : 3; /*!< PCLK0 */ + uint32_t resvd0 : 1; /*!< reserved */ + uint32_t PCLK1S : 3; /*!< PCLK1 */ + uint32_t resvd1 : 1; /*!< reserved */ + uint32_t PCLK2S : 3; /*!< PCLK2 */ + uint32_t resvd2 : 1; /*!< reserved */ + uint32_t PCLK3S : 3; /*!< PCLK3 */ + uint32_t resvd3 : 1; /*!< reserved */ + uint32_t PCLK4S : 3; /*!< PCLK4 */ + uint32_t resvd4 : 1; /*!< reserved */ + uint32_t EXCKS : 3; /*!< EXCLK */ + uint32_t resvd5 : 1; /*!< reserved */ + uint32_t HCLKS : 3; /*!< HCLK */ + uint32_t resvd6 : 5; /*!< reserved */ + } SCFGR_f; + }; +} stc_clock_scale_t; + +/** + * @brief CLK PLL configuration structure definition + * @note PLL for MPLL while HC32F460,HC32F451,HC32F452 + * PLL for PLLH while HC32F4A0 + */ +typedef struct { + uint8_t u8PLLState; /*!< PLL new state, @ref CLK_PLL_Config for details */ + union { + uint32_t PLLCFGR; /*!< PLL config register */ + struct { + uint32_t PLLM : 5; /*!< PLL M divide */ + uint32_t resvd0 : 2; /*!< reserved */ + uint32_t PLLSRC : 1; /*!< PLL/PLLA source clock select */ + uint32_t PLLN : 9; /*!< PLL N multi */ + uint32_t resvd1 : 3; /*!< reserved */ + uint32_t PLLR : 4; /*!< PLL R divide */ + uint32_t PLLQ : 4; /*!< PLL Q divide */ + uint32_t PLLP : 4; /*!< PLL P divide */ + } PLLCFGR_f; + }; +} stc_clock_pll_init_t; + +/** + * @brief CLK PLLx configuration structure definition + * @note PLLx for UPLL while HC32F460,HC32F451,HC32F452 + * PLLx for PLLA while HC32F4A0 + */ +typedef struct { + uint8_t u8PLLState; /*!< PLLx new state, @ref CLK_PLLx_State for details */ + union { + uint32_t PLLCFGR; /*!< PLLx config register */ + struct { + uint32_t PLLM : 5; /*!< PLLx M divide */ + uint32_t resvd0 : 3; /*!< reserved */ + uint32_t PLLN : 9; /*!< PLLx N multi- */ + uint32_t resvd1 : 3; /*!< reserved */ + uint32_t PLLR : 4; /*!< PLLx R divide */ + uint32_t PLLQ : 4; /*!< PLLx Q divide */ + uint32_t PLLP : 4; /*!< PLLx P divide */ + } PLLCFGR_f; + }; +} stc_clock_pllx_init_t; + +/** + * @brief CLK bus frequency structure definition + */ +typedef struct { + uint32_t u32SysclkFreq; /*!< System clock frequency. */ + uint32_t u32HclkFreq; /*!< Hclk frequency. */ + + uint32_t u32Pclk1Freq; /*!< Pclk1 frequency. */ + uint32_t u32Pclk4Freq; /*!< Pclk4 frequency. */ + uint32_t u32Pclk3Freq; /*!< Pclk3 frequency. */ + uint32_t u32ExclkFreq; /*!< Exclk frequency. */ + uint32_t u32Pclk0Freq; /*!< Pclk0 frequency. */ + uint32_t u32Pclk2Freq; /*!< Pclk2 frequency. */ +} stc_clock_freq_t; + +/** + * @brief CLK PLL clock frequency structure definition + */ +typedef struct { + uint32_t u32PllVcin; /*!< PLL vcin clock frequency. */ + uint32_t u32PllVco; /*!< PLL vco clock frequency. */ + uint32_t u32PllP; /*!< PLLp clock frequency. */ + uint32_t u32PllQ; /*!< PLLq clock frequency. */ + uint32_t u32PllR; /*!< PLLr clock frequency. */ + uint32_t u32PllxVcin; /*!< pllx vcin clock frequency. */ + uint32_t u32PllxVco; /*!< pllx vco clock frequency. */ + uint32_t u32PllxP; /*!< pllxp clock frequency. */ + uint32_t u32PllxQ; /*!< pllxq clock frequency. */ + uint32_t u32PllxR; /*!< pllxr clock frequency. */ +} stc_pll_clock_freq_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CLK_Global_Macros CLK Global Macros + * @{ + */ +/** + * @defgroup CLK_PLLx_State CLK PLLx State + * @note PLLx for UPLL while HC32F460,HC32F451,HC32F452 + * PLLx for PLLA while HC32F4A0 + * @{ + */ +#define CLK_PLLX_OFF (0x01U) +#define CLK_PLLX_ON (0x00U) +/** + * @} + */ + +/** + * @defgroup CLK_PLL_Config PLL Config + * @{ + */ +/** + * @brief PLL function config. + */ +#define CLK_PLL_OFF (0x01U) +#define CLK_PLL_ON (0x00U) + +/** + * @brief PLL/A source clock selection. + */ +#define CLK_PLL_SRC_XTAL (0x00UL) +#define CLK_PLL_SRC_HRC (0x01UL) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL_Config XTAL Config + * @{ + */ +/** + * @brief XTAL function config. + */ +#define CLK_XTAL_OFF (CMU_XTALCR_XTALSTP) +#define CLK_XTAL_ON (0x00U) + +/** + * @brief XTAL driver ability + * @note HC32F451/HC32F452 | | | + * @note HC32F4A0/HC32F460 | | | + * @note HC32F472 | HC32M423/HC32M424 | HC32M120/HC32F120/HC32F160 | + * High: [20~25] | [20~24] | [20] | + * Mid: [16~20) | [16~20) | [10~20) | + * Low: (8~16) | (8~16) | (4~10) | + * ULow: [4~8] | [4~8] | [4] | + */ +#define CLK_XTAL_DRV_HIGH (0x00U << CMU_XTALCFGR_XTALDRV_POS) +#define CLK_XTAL_DRV_MID (0x01U << CMU_XTALCFGR_XTALDRV_POS) +#define CLK_XTAL_DRV_LOW (0x02U << CMU_XTALCFGR_XTALDRV_POS) +#define CLK_XTAL_DRV_ULOW (0x03U << CMU_XTALCFGR_XTALDRV_POS) + +/** + * @brief XTAL super drive on or off + */ +#define CLK_XTAL_SUPDRV_ON (CMU_XTALCFGR_SUPDRV) +#define CLK_XTAL_SUPDRV_OFF (0x00U) + +/** + * @brief XTAL mode selection osc or exclk + */ +#define CLK_XTAL_MD_OSC (0x00U) +#define CLK_XTAL_MD_EXCLK (CMU_XTALCFGR_XTALMS) + +/** + * @brief XTAL stable time selection. + * @note a cycle of stable counter = a cycle of LRC divide by 8 + */ +#define CLK_XTAL_STB_133US (0x01U) /*!< 35 stable count cycle, approx. 133us */ +#define CLK_XTAL_STB_255US (0x02U) /*!< 67 stable count cycle, approx. 255us */ +#define CLK_XTAL_STB_499US (0x03U) /*!< 131 stable count cycle, approx. 499us */ +#define CLK_XTAL_STB_988US (0x04U) /*!< 259 stable count cycle, approx. 988us */ +#define CLK_XTAL_STB_2MS (0x05U) /*!< 547 stable count cycle, approx. 2ms */ +#define CLK_XTAL_STB_4MS (0x06U) /*!< 1059 stable count cycle, approx. 4ms */ +#define CLK_XTAL_STB_8MS (0x07U) /*!< 2147 stable count cycle, approx. 8ms */ +#define CLK_XTAL_STB_16MS (0x08U) /*!< 4291 stable count cycle, approx. 16ms */ +#define CLK_XTAL_STB_31MS (0x09U) /*!< 8163 stable count cycle, approx. 32ms */ + +/** + * @} + */ + +/** + * @defgroup CLK_XTALSTD_Config XTALSTD Config + * @{ + */ + +/** + * @brief XTAL error detection on or off + */ +#define CLK_XTALSTD_OFF (0x00U) +#define CLK_XTALSTD_ON (CMU_XTALSTDCR_XTALSTDE) + +/** + * @brief XTALSTD mode selection + */ +#define CLK_XTALSTD_MD_RST (CMU_XTALSTDCR_XTALSTDRIS) +#define CLK_XTALSTD_MD_INT (0x00U) + +/** + * @brief XTALSTD reset on or off + */ +#define CLK_XTALSTD_RST_OFF (0x00U) +#define CLK_XTALSTD_RST_ON (CMU_XTALSTDCR_XTALSTDRE) + +/** + * @brief XTALSTD interrupt on or off + */ +#define CLK_XTALSTD_INT_OFF (0x00U) +#define CLK_XTALSTD_INT_ON (CMU_XTALSTDCR_XTALSTDIE) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL32_Config XTAL32 Config + * @{ + */ +/** + * @brief XTAL32 function config. + */ +#define CLK_XTAL32_OFF (CMU_XTAL32CR_XTAL32STP) +#define CLK_XTAL32_ON (0x00U) + +/** + * @brief XTAL32 driver ability. + */ +#define CLK_XTAL32_DRV_MID (0x00U) +#define CLK_XTAL32_DRV_HIGH (0x01U) + +/** + * @brief XTAL32 filtering selection. + */ +#define CLK_XTAL32_FILTER_ALL_MD (0x00U) /*!< Valid in run,stop,power down mode. */ +#define CLK_XTAL32_FILTER_RUN_MD (0x01U) /*!< Valid in run mode. */ +#define CLK_XTAL32_FILTER_OFF (0x03U) /*!< Invalid in run,stop,power down mode. */ +/** + * @} + */ + +/** + * @defgroup CLK_HRC_Config HRC Config + * @{ + */ +#define CLK_HRC_OFF (CMU_HRCCR_HRCSTP) +#define CLK_HRC_ON (0x00U) +/** + * @} + */ + +/** + * @defgroup CLK_HrcFreq_Sel Hrc Freqency Selection + * @{ + */ + +/** + * @} + */ + +/** + * @defgroup CLK_STB_Flag CLK Stable Flags + * @{ + */ +#define CLK_STB_FLAG_HRC (CMU_OSCSTBSR_HRCSTBF) +#define CLK_STB_FLAG_XTAL (CMU_OSCSTBSR_XTALSTBF) +#define CLK_STB_FLAG_PLL (CMU_OSCSTBSR_MPLLSTBF) +#define CLK_STB_FLAG_PLLX (CMU_OSCSTBSR_UPLLSTBF) +#define CLK_STB_FLAG_MASK (CMU_OSCSTBSR_HRCSTBF | CMU_OSCSTBSR_XTALSTBF | \ + CMU_OSCSTBSR_MPLLSTBF | CMU_OSCSTBSR_UPLLSTBF) + +/** + * @} + */ + +/** + * @defgroup CLK_System_Clock_Source System Clock Source + * @{ + */ +#define CLK_SYSCLK_SRC_HRC (0x00U) +#define CLK_SYSCLK_SRC_MRC (0x01U) +#define CLK_SYSCLK_SRC_LRC (0x02U) +#define CLK_SYSCLK_SRC_XTAL (0x03U) +#define CLK_SYSCLK_SRC_XTAL32 (0x04U) +#define CLK_SYSCLK_SRC_PLL (0x05U) + +/** + * @} + */ + +/** + * @defgroup CLK_Bus_Clock_Sel Clock Bus Clock Category Selection + * @{ + */ +#define CLK_BUS_PCLK0 (CMU_SCFGR_PCLK0S) +#define CLK_BUS_PCLK1 (CMU_SCFGR_PCLK1S) +#define CLK_BUS_PCLK2 (CMU_SCFGR_PCLK2S) +#define CLK_BUS_PCLK3 (CMU_SCFGR_PCLK3S) +#define CLK_BUS_PCLK4 (CMU_SCFGR_PCLK4S) +#define CLK_BUS_EXCLK (CMU_SCFGR_EXCKS) +#define CLK_BUS_HCLK (CMU_SCFGR_HCLKS) +#define CLK_BUS_CLK_ALL (CLK_BUS_PCLK0 | CLK_BUS_PCLK1 | CLK_BUS_PCLK2 | CLK_BUS_PCLK3 | \ + CLK_BUS_PCLK4 | CLK_BUS_EXCLK | CLK_BUS_HCLK) + +/** + * @} + */ + +/** + * @defgroup CLK_Clock_Divider Clock Divider + * @{ + */ + +/** + * @defgroup CLK_System_Clock_Divider System Clock Divider + * @{ + */ +#define CLK_SYSCLK_DIV1 (0x00U) +#define CLK_SYSCLK_DIV2 (0x01U) +#define CLK_SYSCLK_DIV4 (0x02U) +#define CLK_SYSCLK_DIV8 (0x03U) +#define CLK_SYSCLK_DIV16 (0x04U) +#define CLK_SYSCLK_DIV32 (0x05U) +#define CLK_SYSCLK_DIV64 (0x06U) +/** + * @} + */ + +/** + * @defgroup CLK_HCLK_Divider CLK HCLK Divider + * @{ + */ +#define CLK_HCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_HCLKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK1_Divider CLK PCLK1 Divider + * @{ + */ +#define CLK_PCLK1_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK1S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK4_Divider CLK PCLK4 Divider + * @{ + */ +#define CLK_PCLK4_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK4S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK3_Divider CLK PCLK3 Divider + * @{ + */ +#define CLK_PCLK3_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK3S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_EXCLK_Divider CLK EXCLK Divider + * @{ + */ +#define CLK_EXCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_EXCKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK2_Divider CLK PCLK2 Divider + * @{ + */ +#define CLK_PCLK2_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK2S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK0_Divider CLK PCLK0 Divider + * @{ + */ +#define CLK_PCLK0_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK0S_POS) +/** + * @} + */ +/** + * @} + */ + +/** + * @defgroup CLK_USBCLK_Sel CLK USB Clock Selection + * @{ + */ +#define CLK_USBCLK_SYSCLK_DIV2 (0x02U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_SYSCLK_DIV3 (0x03U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_SYSCLK_DIV4 (0x04U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLP (0x08U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLQ (0x09U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLR (0x0AU << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLXP (0x0BU << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLXQ (0x0CU << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USBCLK_PLLXR (0x0DU << CMU_USBCKCFGR_USBCKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PERIPH_Sel CLK Peripheral Clock Selection + * @note ADC,I2S,DAC,TRANG + * @{ + */ +#define CLK_PERIPHCLK_PCLK (0x0000U) /* PCLK2 is used for ADC clock, \ + PCLK3 is used for I2S clock, \ + PCLK4 is used for DAC/TRANG clock */ +#define CLK_PERIPHCLK_PLLP (0x0008U) +#define CLK_PERIPHCLK_PLLQ (0x0009U) +#define CLK_PERIPHCLK_PLLR (0x000AU) +#define CLK_PERIPHCLK_PLLXP (0x000BU) +#define CLK_PERIPHCLK_PLLXQ (0x000CU) +#define CLK_PERIPHCLK_PLLXR (0x000DU) +/** + * @} + */ + +/** + * @defgroup CLK_I2S_Sel CLK I2S Channel Selection + * @{ + */ +#define CLK_I2S1 (0x00U) +#define CLK_I2S2 (0x01U) +#define CLK_I2S3 (0x02U) +#define CLK_I2S4 (0x03U) +/** + * @} + */ + +/** + * @defgroup CLK_TPIU_Divider TPIU clock divider + * @{ + */ +#define CLK_TPIUCLK_DIV1 (0x00U) +#define CLK_TPIUCLK_DIV2 (0x01U) +#define CLK_TPIUCLK_DIV4 (0x02U) +/** + * @} + */ + +/** + * @defgroup CLK_MCO_Channel_Sel CLK MCO Channel Select + * @{ + */ +#define CLK_MCO1 (0x00U) +#define CLK_MCO2 (0x01U) +/** + * @} + */ + +/** + * @defgroup CLK_MCO_Clock_Source CLK MCO Clock Source + * @{ + */ +#define CLK_MCO_SRC_HRC (0x00U) +#define CLK_MCO_SRC_MRC (0x01U) +#define CLK_MCO_SRC_LRC (0x02U) +#define CLK_MCO_SRC_XTAL (0x03U) +#define CLK_MCO_SRC_XTAL32 (0x04U) +#define CLK_MCO_SRC_PLLP (0x06U) +#define CLK_MCO_SRC_PLLXP (0x07U) +#define CLK_MCO_SRC_PLLQ (0x08U) +#define CLK_MCO_SRC_PLLXQ (0x09U) +#define CLK_MCO_SRC_HCLK (0x0BU) + +/** + * @} + */ + +/** + * @defgroup CLK_MCO_Clock_Prescaler CLK MCO Clock Prescaler + * @{ + */ +#define CLK_MCO_DIV1 (0x00U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV2 (0x01U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV4 (0x02U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV8 (0x03U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV16 (0x04U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV32 (0x05U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV64 (0x06U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV128 (0x07U << CMU_MCOCFGR_MCODIV_POS) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CLK_Global_Functions + * @{ + */ + +int32_t CLK_HrcCmd(en_functional_state_t enNewState); + +int32_t CLK_MrcCmd(en_functional_state_t enNewState); + +int32_t CLK_LrcCmd(en_functional_state_t enNewState); + +void CLK_HrcTrim(int8_t i8TrimVal); +void CLK_MrcTrim(int8_t i8TrimVal); +void CLK_LrcTrim(int8_t i8TrimVal); + +int32_t CLK_XtalStructInit(stc_clock_xtal_init_t *pstcXtalInit); +int32_t CLK_XtalInit(const stc_clock_xtal_init_t *pstcXtalInit); +int32_t CLK_XtalCmd(en_functional_state_t enNewState); + +int32_t CLK_XtalStdStructInit(stc_clock_xtalstd_init_t *pstcXtalStdInit); +int32_t CLK_XtalStdInit(const stc_clock_xtalstd_init_t *pstcXtalStdInit); +void CLK_ClearXtalStdStatus(void); +en_flag_status_t CLK_GetXtalStdStatus(void); + +int32_t CLK_Xtal32StructInit(stc_clock_xtal32_init_t *pstcXtal32Init); +int32_t CLK_Xtal32Init(const stc_clock_xtal32_init_t *pstcXtal32Init); +int32_t CLK_Xtal32Cmd(en_functional_state_t enNewState); + +void CLK_SetPLLSrc(uint32_t u32PllSrc); +int32_t CLK_PLLStructInit(stc_clock_pll_init_t *pstcPLLInit); +int32_t CLK_PLLInit(const stc_clock_pll_init_t *pstcPLLInit); +int32_t CLK_PLLCmd(en_functional_state_t enNewState); +int32_t CLK_GetPLLClockFreq(stc_pll_clock_freq_t *pstcPllClkFreq); + +int32_t CLK_PLLxStructInit(stc_clock_pllx_init_t *pstcPLLxInit); +int32_t CLK_PLLxInit(const stc_clock_pllx_init_t *pstcPLLxInit); +int32_t CLK_PLLxCmd(en_functional_state_t enNewState); + +void CLK_MCOConfig(uint8_t u8Ch, uint8_t u8Src, uint8_t u8Div); +void CLK_MCOCmd(uint8_t u8Ch, en_functional_state_t enNewState); + +en_flag_status_t CLK_GetStableStatus(uint8_t u8Flag); + +void CLK_SetSysClockSrc(uint8_t u8Src); +void CLK_SetClockDiv(uint32_t u32Clock, uint32_t u32Div); +int32_t CLK_GetClockFreq(stc_clock_freq_t *pstcClockFreq); +uint32_t CLK_GetBusClockFreq(uint32_t u32Clock); + +void CLK_SetPeriClockSrc(uint16_t u16Src); + +void CLK_SetUSBClockSrc(uint8_t u8Src); +void CLK_SetI2SClockSrc(uint8_t u8Unit, uint8_t u8Src); + +void CLK_TpiuClockCmd(en_functional_state_t enNewState); +void CLK_SetTpiuClockDiv(uint8_t u8Div); + +/** + * @} + */ + +#endif /* LL_CLK_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CLK_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_cmp.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_cmp.h new file mode 100644 index 0000000000..0c5819469a --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_cmp.h @@ -0,0 +1,280 @@ +/** + ******************************************************************************* + * @file hc32_ll_cmp.h + * @brief Head file for CMP module. + * + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CMP_H__ +#define __HC32_LL_CMP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CMP + * @{ + */ + +#if (LL_CMP_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CMP_Global_Types CMP Global Types + * @{ + */ + +/** + * @brief CMP normal mode configuration structure + */ +typedef struct { + uint16_t u16PositiveInput; /*!< Positive(compare voltage) input @ref CMP_Positive_Input_Select */ + uint16_t u16NegativeInput; /*!< Negative(Reference voltage) input @ref CMP_Negative_Input_Select */ + uint16_t u16OutPolarity; /*!< Output polarity select, @ref CMP_Out_Polarity_Select */ + uint16_t u16OutDetectEdge; /*!< Output detect edge, @ref CMP_Out_Detect_Edge_Select */ + uint16_t u16OutFilter; /*!< Output Filter, @ref CMP_Out_Filter */ +} stc_cmp_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup CMP_Global_Macros CMP Global Macros + * @{ + */ + +#define VISR_OFFSET (8U) + +/** + * @defgroup CMP_Positive_Input_Select CMP Positive(Compare) Voltage Input + * @{ + */ +#define CMP_POSITIVE_NONE (0x0U) + +/* Note: + Normal mode: + 1) Select one positive input from the following values. + Scan mode: + 2) Select any combination of the following values, but the XXX_PGAO/ XXX_PGAO_BP/ XXX_CMP1_INP4/ XXX_CMP3_INP4 + should not be valid at the same time. +*/ +/* CMP1 */ +#define CMP1_POSITIVE_CMP1_INP1 (CMP_VLTSEL_CVSL_0) /*!< Pin CMP1_INP1 */ +#define CMP1_POSITIVE_CMP1_INP2 (CMP_VLTSEL_CVSL_1) /*!< Pin CMP1_INP2 */ +#define CMP1_POSITIVE_CMP1_INP3 (CMP_VLTSEL_CVSL_2) /*!< Pin CMP1_INP3 */ +#define CMP1_POSITIVE_PGAO (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_0) /*!< Internal voltage PGAO */ +#define CMP1_POSITIVE_PGAO_BP (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_1) /*!< Internal voltage PGAO_BP */ +#define CMP1_POSITIVE_CMP1_INP4 (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_2) /*!< Pin CMP1_INP4 */ +/* CMP2 */ +#define CMP2_POSITIVE_CMP2_INP1 (CMP_VLTSEL_CVSL_0) /*!< Pin CMP2_INP1 */ +#define CMP2_POSITIVE_CMP2_INP2 (CMP_VLTSEL_CVSL_1) /*!< Pin CMP2_INP2 */ +#define CMP2_POSITIVE_CMP2_INP3 (CMP_VLTSEL_CVSL_2) /*!< Pin CMP2_INP3 */ +#define CMP2_POSITIVE_PGAO (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_0) /*!< Internal voltage PGAO */ +#define CMP2_POSITIVE_PGAO_BP (CMP_VLTSEL_CVSL_3 | CMP_VLTSEL_C4SL_1) /*!< Internal voltage PGAO_BP */ +/* CMP3 */ +#define CMP3_POSITIVE_CMP3_INP1 (CMP_VLTSEL_CVSL_0) /*!< Pin CMP3_INP1 */ +#define CMP3_POSITIVE_CMP3_INP2 (CMP_VLTSEL_CVSL_1) /*!< Pin CMP3_INP2 */ +#define CMP3_POSITIVE_CMP3_INP3 (CMP_VLTSEL_CVSL_2) /*!< Pin CMP3_INP3 */ +#define CMP3_POSITIVE_CMP3_INP4 (CMP_VLTSEL_CVSL_3) /*!< Pin CMP3_INP4 */ +/** + * @} + */ + +/** + * @defgroup CMP_Scan_Inp_Status CMP Scan Function Positive In INP Source + * @{ + */ +#define CMP_SCAN_STAT_NONE (0U) +#define CMP_SCAN_STAT_INP1 (1U << CMP_OUTMON_CVST_POS) +#define CMP_SCAN_STAT_INP2 (2U << CMP_OUTMON_CVST_POS) +#define CMP_SCAN_STAT_INP3 (4U << CMP_OUTMON_CVST_POS) +#define CMP_SCAN_STAT_INP4 (8U << CMP_OUTMON_CVST_POS) +/** + * @} + */ + +/** + * @defgroup CMP_Negative_Input_Select CMP Negative(Reference) Voltage Input + * @{ + */ +#define CMP_NEGATIVE_NONE (0x0U) + +/* Select negative input for CMP1 */ +#define CMP1_NEGATIVE_CMP1_INM1 (1U << CMP_VLTSEL_RVSL_POS) /*!< Pin CMP1_INM1 */ +#define CMP1_NEGATIVE_CMP1_INM2 (2U << CMP_VLTSEL_RVSL_POS) /*!< Pin CMP1_INM2 */ +#define CMP1_NEGATIVE_DAC1 (4U << CMP_VLTSEL_RVSL_POS) /*!< DAC1 voltage */ +#define CMP1_NEGATIVE_VREF (8U << CMP_VLTSEL_RVSL_POS) /*!< Internal VREF voltage */ +/* Select negative input for CMP2 */ +#define CMP2_NEGATIVE_CMP2_INM1 (1U << CMP_VLTSEL_RVSL_POS) /*!< Pin CMP2_INM1 */ +#define CMP2_NEGATIVE_CMP2_INM2 (2U << CMP_VLTSEL_RVSL_POS) /*!< Pin CMP2_INM2 */ +#define CMP2_NEGATIVE_DAC2 (4U << CMP_VLTSEL_RVSL_POS) /*!< DAC2 voltage */ +#define CMP2_NEGATIVE_VREF (8U << CMP_VLTSEL_RVSL_POS) /*!< Internal VREF voltage */ +/* Select negative input for CMP3 */ +#define CMP3_NEGATIVE_CMP3_INM1 (1U << CMP_VLTSEL_RVSL_POS) /*!< Pin CMP3_INM1 */ +#define CMP3_NEGATIVE_CMP3_INM2 (2U << CMP_VLTSEL_RVSL_POS) /*!< Pin CMP3_INM2 */ +#define CMP3_NEGATIVE_DAC1 (4U << CMP_VLTSEL_RVSL_POS) /*!< DAC1 voltage */ +#define CMP3_NEGATIVE_DAC2 (8U << CMP_VLTSEL_RVSL_POS) /*!< DAC2 voltage */ +/** + * @} + */ + +/** + * @defgroup CMP_Out_Polarity_Select CMP Output Polarity + * @{ + */ +#define CMP_OUT_INVT_OFF (0x0U) /*!< CMP output don't reverse */ +#define CMP_OUT_INVT_ON (CMP_CTRL_INV) /*!< CMP output level reverse */ +/** + * @} + */ + +/** + * @defgroup CMP_Out_Detect_Edge_Select CMP Output Detect Edge + * @{ + */ +#define CMP_DETECT_EDGS_NONE (0U) /*!< Do not detect edge */ + +#define CMP_DETECT_EDGS_RISING (1U << CMP_CTRL_EDGSL_POS) /*!< Detect rising edge */ +#define CMP_DETECT_EDGS_FALLING (2U << CMP_CTRL_EDGSL_POS) /*!< Detect falling edge */ +#define CMP_DETECT_EDGS_BOTH (3U << CMP_CTRL_EDGSL_POS) /*!< Detect rising and falling edges */ +/** + * @} + */ + +/** + * @defgroup CMP_Out_Filter CMP Output Filter Configuration + * @{ + */ +#define CMP_OUT_FILTER_NONE (0U) /*!< Do not filter */ + +#define CMP_OUT_FILTER_CLK (1U << CMP_CTRL_FLTSL_POS) +#define CMP_OUT_FILTER_CLK_DIV2 (2U << CMP_CTRL_FLTSL_POS) +#define CMP_OUT_FILTER_CLK_DIV4 (3U << CMP_CTRL_FLTSL_POS) +#define CMP_OUT_FILTER_CLK_DIV8 (4U << CMP_CTRL_FLTSL_POS) +#define CMP_OUT_FILTER_CLK_DIV16 (5U << CMP_CTRL_FLTSL_POS) +#define CMP_OUT_FILTER_CLK_DIV32 (6U << CMP_CTRL_FLTSL_POS) +#define CMP_OUT_FILTER_CLK_DIV64 (7U << CMP_CTRL_FLTSL_POS) +/** + * @} + */ + +/** + * @defgroup CMP_8BitDAC_Adc_Ref_Switch CMP 8 bit DAC ADC Reference Voltage Switch + * @{ + */ +#define CMP_ADC_REF_VREF (CMPCR_RVADC_VREFSW) +#define CMP_ADC_REF_DA2 (CMPCR_RVADC_DA2SW) +#define CMP_ADC_REF_DA1 (CMPCR_RVADC_DA1SW) +/** + * @} + */ + +/** + * @defgroup CMP_8Bit_Dac_Ch CMP 8 bit DAC Channel + * @{ + */ +#define CMP_8BITDAC_CH1 (CMPCR_DACR_DA1EN) +#define CMP_8BITDAC_CH2 (CMPCR_DACR_DA2EN) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CMP_Global_Functions + * @{ + */ + +int32_t CMP_StructInit(stc_cmp_init_t *pstcCmpInit); +int32_t CMP_NormalModeInit(CM_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcCmpInit); +void CMP_DeInit(CM_CMP_TypeDef *CMPx); + +void CMP_FuncCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +void CMP_IntCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +void CMP_CompareOutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +void CMP_PinVcoutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +en_flag_status_t CMP_GetStatus(const CM_CMP_TypeDef *CMPx); +void CMP_SetOutDetectEdge(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges); +void CMP_SetOutFilter(CM_CMP_TypeDef *CMPx, uint8_t u8CmpFilter); +void CMP_SetOutPolarity(CM_CMP_TypeDef *CMPx, uint16_t u16CmpPolarity); +void CMP_SetPositiveInput(CM_CMP_TypeDef *CMPx, uint16_t u16PositiveInput); +void CMP_SetNegativeInput(CM_CMP_TypeDef *CMPx, uint16_t u16NegativeInput); + +uint16_t CMP_GetScanInpSrc(CM_CMP_TypeDef *CMPx); +int32_t CMP_ScanTimeConfig(CM_CMP_TypeDef *CMPx, uint8_t u8ScanStable, uint8_t u8ScanPeriod); +void CMP_ScanCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); + +void CMP_8BitDAC_Cmd(uint8_t u8Ch, en_functional_state_t enNewState); +void CMP_8BitDAC_AdcRefCmd(uint16_t u16AdcRefSw, en_functional_state_t enNewState); + +void CMP_8BitDAC_WriteData(uint8_t u8Ch, uint16_t u16DACData); + +/** + * @} + */ + +#endif /* LL_CMP_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CMP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_crc.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_crc.h new file mode 100644 index 0000000000..51a0bf42c2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_crc.h @@ -0,0 +1,197 @@ +/** + ******************************************************************************* + * @file hc32_ll_crc.h + * @brief This file contains all the functions prototypes of the CRC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CRC_H__ +#define __HC32_LL_CRC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CRC + * @{ + */ + +#if (LL_CRC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CRC_Global_Types CRC Global Types + * @{ + */ + +/** + * @brief CRC initialization structure definition + */ +typedef struct { + uint32_t u32Protocol; /*!< Specifies CRC Protocol. + This parameter can be a value of @ref CRC_Protocol_Control_Bit */ + uint32_t u32InitValue; /*!< Specifies initial CRC value and value upper 16 bit is ignored when using CRC16. + This parameter can be a value of @ref CRC_Initial_Value */ + uint32_t u32RefIn; /*!< Specifies CRC Retroflexion Input. + This parameter can be a value of @ref CRC_Retroflexion_Input */ + uint32_t u32RefOut; /*!< Specifies CRC Retroflexion Output. + This parameter can be a value of @ref CRC_Retroflexion_Output */ + uint32_t u32XorOut; /*!< Specifies CRC XOR Output. + This parameter can be a value of @ref CRC_XOR_Output */ +} stc_crc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CRC_Global_Macros CRC Global Macros + * @{ + */ + +/** + * @defgroup CRC_Protocol_Control_Bit CRC Protocol Control Bit + * @note: - CRC16 polynomial is X^16 + X^12 + X^5 + 1 + * - CRC32 polynomial is X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + \ + * X^10 + X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 + * @{ + */ +#define CRC_CRC16 (0x0UL) +#define CRC_CRC32 (CRC_CR_CR) +/** + * @} + */ + +/** + * @defgroup CRC_Initial_Value CRC Initial Value + * @{ + */ +#define CRC16_INIT_VALUE (0xFFFFUL) +#define CRC32_INIT_VALUE (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup CRC_Retroflexion_Input CRC Retroflexion Input + * @{ + */ +#define CRC_REFIN_DISABLE (0x0UL) +#define CRC_REFIN_ENABLE (CRC_CR_REFIN) +/** + * @} + */ + +/** + * @defgroup CRC_Retroflexion_Output CRC Retroflexion Output + * @{ + */ +#define CRC_REFOUT_DISABLE (0x0UL) +#define CRC_REFOUT_ENABLE (CRC_CR_REFOUT) +/** + * @} + */ + +/** + * @defgroup CRC_XOR_Output CRC XOR Output + * @{ + */ +#define CRC_XOROUT_DISABLE (0x0UL) +#define CRC_XOROUT_ENABLE (CRC_CR_XOROUT) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CRC_Global_Functions + * @{ + */ +int32_t CRC_StructInit(stc_crc_init_t *pstcCrcInit); +int32_t CRC_Init(const stc_crc_init_t *pstcCrcInit); +void CRC_DeInit(void); + +en_flag_status_t CRC_GetResultStatus(void); + +uint32_t CRC_AccumulateData8(const uint8_t au8Data[], uint32_t u32Len); +uint32_t CRC_AccumulateData16(const uint16_t au16Data[], uint32_t u32Len); +uint32_t CRC_AccumulateData32(const uint32_t au32Data[], uint32_t u32Len); + +uint32_t CRC_CalculateData8(uint32_t u32InitValue, const uint8_t au8Data[], uint32_t u32Len); +uint32_t CRC_CalculateData16(uint32_t u32InitValue, const uint16_t au16Data[], uint32_t u32Len); +uint32_t CRC_CalculateData32(uint32_t u32InitValue, const uint32_t au32Data[], uint32_t u32Len); + +en_flag_status_t CRC_CheckData8(uint32_t u32InitValue, const uint8_t au8Data[], + uint32_t u32Len, uint32_t u32ExpectValue); +en_flag_status_t CRC_CheckData16(uint32_t u32InitValue, const uint16_t au16Data[], + uint32_t u32Len, uint32_t u32ExpectValue); +en_flag_status_t CRC_CheckData32(uint32_t u32InitValue, const uint32_t au32Data[], + uint32_t u32Len, uint32_t u32ExpectValue); + +/** + * @} + */ + +#endif /* LL_CRC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CRC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dcu.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dcu.h new file mode 100644 index 0000000000..9fc635b369 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dcu.h @@ -0,0 +1,264 @@ +/** + ******************************************************************************* + * @file hc32_ll_dcu.h + * @brief This file contains all the functions prototypes of the DCU(Data + * Computing Unit) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DCU_H__ +#define __HC32_LL_DCU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_DCU + * @{ + */ + +#if (LL_DCU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Types DCU Global Types + * @{ + */ + +/** + * @brief DCU initialization structure definition + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies DCU operation. + This parameter can be a value of @ref DCU_Mode */ + uint32_t u32DataWidth; /*!< Specifies DCU data width. + This parameter can be a value of @ref DCU_Data_Width */ +} stc_dcu_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Macros DCU Global Macros + * @{ + */ + +/** + * @defgroup DCU_Data_Width DCU Data Width + * @{ + */ +#define DCU_DATA_WIDTH_8BIT (0UL) /*!< DCU data width: 8 bit */ +#define DCU_DATA_WIDTH_16BIT (DCU_CTL_DATASIZE_0) /*!< DCU data width: 16 bit */ +#define DCU_DATA_WIDTH_32BIT (DCU_CTL_DATASIZE_1) /*!< DCU data width: 32 bit */ +/** + * @} + */ + +/** + * @defgroup DCU_Compare_Trigger_Condition DCU Compare Trigger Condition + * @{ + */ +#define DCU_CMP_TRIG_DATA0 (0UL) /*!< DCU compare triggered by DATA0 */ +#define DCU_CMP_TRIG_DATA0_DATA1_DATA2 (DCU_CTL_COMP_TRG) /*!< DCU compare triggered by DATA0 or DATA1 or DATA2 */ +/** + * @} + */ + +/** + * @defgroup DCU_Mode DCU Mode + * @{ + */ +#define DCU_MD_INVD (0UL) /*!< DCU invalid */ +#define DCU_MD_ADD (1UL) /*!< DCU add operation */ +#define DCU_MD_SUB (2UL) /*!< DCU sub operation */ +#define DCU_MD_HW_ADD (3UL) /*!< DCU hardware trigger add */ +#define DCU_MD_HW_SUB (4UL) /*!< DCU hardware trigger sub */ +#define DCU_MD_CMP (5UL) /*!< DCU compare */ +/** + * @} + */ + +/** + * @defgroup DCU_Flag DCU Flag + * @{ + */ +#define DCU_FLAG_CARRY (DCU_FLAG_FLAG_OP) /*!< DCU addition overflow or subtraction underflow flag */ +#define DCU_FLAG_DATA0_LT_DATA2 (DCU_FLAG_FLAG_LS2) /*!< DCU DATA0 < DATA2 flag */ +#define DCU_FLAG_DATA0_EQ_DATA2 (DCU_FLAG_FLAG_EQ2) /*!< DCU DATA0 = DATA2 flag */ +#define DCU_FLAG_DATA0_GT_DATA2 (DCU_FLAG_FLAG_GT2) /*!< DCU DATA0 > DATA2 flag */ +#define DCU_FLAG_DATA0_LT_DATA1 (DCU_FLAG_FLAG_LS1) /*!< DCU DATA0 < DATA1 flag */ +#define DCU_FLAG_DATA0_EQ_DATA1 (DCU_FLAG_FLAG_EQ1) /*!< DCU DATA0 = DATA1 flag */ +#define DCU_FLAG_DATA0_GT_DATA1 (DCU_FLAG_FLAG_GT1) /*!< DCU DATA0 > DATA1 flag */ + +#define DCU_FLAG_ALL (0x0000007FUL) +/** + * @} + */ + +/** + * @defgroup DCU_Category DCU Category + * @{ + */ +#define DCU_CATEGORY_OP (0UL) /*!< DCU operation result(overflow/underflow) */ +#define DCU_CATEGORY_CMP_WIN (1UL) /*!< DCU comparison(window) */ +#define DCU_CATEGORY_CMP_NON_WIN (2UL) /*!< DCU comparison(non-window) */ +/** + * @} + */ + +/** + * @defgroup DCU_Interrupt_Type DCU Interrupt Type + * @{ + */ +/** + * @defgroup DCU_Compare_Interrupt DCU Compare(Non-window) Interrupt + * @{ + * @note Compare interrupt selection is valid only when select DCU comparison(non-window) interrupt(DCU_INTSEL.INT_WIN=0) under DCU compare mode + */ +#define DCU_INT_CMP_DATA0_LT_DATA2 (DCU_INTSEL_INT_LS2) /*!< DCU DATA0 < DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_EQ_DATA2 (DCU_INTSEL_INT_EQ2) /*!< DCU DATA0 = DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_GT_DATA2 (DCU_INTSEL_INT_GT2) /*!< DCU DATA0 > DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_LT_DATA1 (DCU_INTSEL_INT_LS1) /*!< DCU DATA0 < DATA1 interrupt */ +#define DCU_INT_CMP_DATA0_EQ_DATA1 (DCU_INTSEL_INT_EQ1) /*!< DCU DATA0 = DATA1 interrupt */ +#define DCU_INT_CMP_DATA0_GT_DATA1 (DCU_INTSEL_INT_GT1) /*!< DCU DATA0 > DATA1 interrupt */ +#define DCU_INT_CMP_NON_WIN_ALL (DCU_INT_CMP_DATA0_LT_DATA2 | \ + DCU_INT_CMP_DATA0_EQ_DATA2 | \ + DCU_INT_CMP_DATA0_GT_DATA2 | \ + DCU_INT_CMP_DATA0_LT_DATA1 | \ + DCU_INT_CMP_DATA0_EQ_DATA1 | \ + DCU_INT_CMP_DATA0_GT_DATA1) +/** + * @} + */ + +/** + * @defgroup DCU_Window_Compare_Interrupt DCU Window Compare Interrupt + * @{ + */ +#define DCU_INT_CMP_WIN_INSIDE (DCU_INTSEL_INT_WIN_0) /*!< DCU comparison(DATA2 <= DATA0 <= DATA1) interrupt */ +#define DCU_INT_CMP_WIN_OUTSIDE (DCU_INTSEL_INT_WIN_1) /*!< DCU comparison(DATA0 < DATA2 & DATA0 > DATA1 ) interrupt */ +#define DCU_INT_CMP_WIN_ALL (DCU_INT_CMP_WIN_INSIDE | DCU_INT_CMP_WIN_OUTSIDE) +/** + * @} + */ + +/** + * @defgroup DCU_Operation_Interrupt DCU Operation Interrupt + * @{ + */ +#define DCU_INT_OP_CARRY (DCU_INTSEL_INT_OP) /*!< DCU addition overflow or subtraction underflow interrupt */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup DCU_Data_Register_Index DCU Data Register Index + * @{ + */ +#define DCU_DATA0_IDX (0UL) /*!< DCU DATA0 */ +#define DCU_DATA1_IDX (1UL) /*!< DCU DATA1 */ +#define DCU_DATA2_IDX (2UL) /*!< DCU DATA2 */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DCU_Global_Functions + * @{ + */ + +/* Initialization and configuration functions */ +int32_t DCU_Init(CM_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcDcuInit); +int32_t DCU_StructInit(stc_dcu_init_t *pstcDcuInit); +int32_t DCU_DeInit(CM_DCU_TypeDef *DCUx); + +void DCU_SetMode(CM_DCU_TypeDef *DCUx, uint32_t u32Mode); +void DCU_SetDataWidth(CM_DCU_TypeDef *DCUx, uint32_t u32DataWidth); +void DCU_SetCompareCond(CM_DCU_TypeDef *DCUx, uint32_t u32Cond); + +/* Interrupt and flag management functions */ +en_flag_status_t DCU_GetStatus(const CM_DCU_TypeDef *DCUx, uint32_t u32Flag); +void DCU_ClearStatus(CM_DCU_TypeDef *DCUx, uint32_t u32Flag); +void DCU_GlobalIntCmd(CM_DCU_TypeDef *DCUx, en_functional_state_t enNewState); +void DCU_IntCmd(CM_DCU_TypeDef *DCUx, uint32_t u32IntCategory, uint32_t u32IntType, en_functional_state_t enNewState); + +/* Read and write functions */ +uint8_t DCU_ReadData8(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData8(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint8_t u8Data); +uint16_t DCU_ReadData16(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData16(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint16_t u16Data); +uint32_t DCU_ReadData32(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData32(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint32_t u32Data); + +/** + * @} + */ + +#endif /* LL_DCU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DCU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_def.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_def.h new file mode 100644 index 0000000000..96c1289ed2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_def.h @@ -0,0 +1,376 @@ +/** + ******************************************************************************* + * @file hc32_ll_def.h + * @brief This file contains LL common definitions: enumeration, macros and + * structures definitions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DEF_H__ +#define __HC32_LL_DEF_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include + +/** + * @addtogroup LL_Common + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup LL_Common_Global_Types LL Common Global Types + * @{ + */ + +/** + * @brief Single precision floating point number (4 byte) + */ +typedef float float32_t; + +/** + * @brief Double precision floating point number (8 byte) + */ +typedef double float64_t; + +/** + * @brief Function pointer type to void/void function + */ +typedef void (*func_ptr_t)(void); + +/** + * @brief Functional state + */ +typedef enum { + DISABLE = 0U, + ENABLE = 1U, +} en_functional_state_t; + +/** + * @brief Flag status + */ +typedef enum { + RESET = 0U, + SET = 1U, +} en_flag_status_t, en_int_status_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup LL_Common_Global_Macros LL Common Global Macros + * @{ + */ + +/** + * @defgroup Compiler_Macros Compiler Macros + * @{ + */ +#ifndef __UNUSED +#define __UNUSED __attribute__((unused)) +#endif /* __UNUSED */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#ifndef __WEAKDEF +#define __WEAKDEF __attribute__((weak)) +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN __attribute__((aligned(4))) +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE __attribute__((noinline)) +#endif /* __NOINLINE */ +/* RAM functions are defined using the toolchain options. +Functions that are executed in RAM should reside in a separate source module. +Using the 'Options for File' dialog you can simply change the 'Code / Const' +area of a module to a memory space in physical RAM. */ +#ifndef __RAM_FUNC +#define __RAM_FUNC +#endif /* __RAM_FUNC */ +#ifndef __NO_INIT +#define __NO_INIT +#endif /* __NO_INIT */ +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */ +#ifndef __WEAKDEF +#define __WEAKDEF __attribute__((weak)) +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN __attribute__((aligned (4))) +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE __attribute__((noinline)) +#endif /* __NOINLINE */ +#ifndef __RAM_FUNC +#define __RAM_FUNC __attribute__((long_call, section(".ramfunc"))) +/* Usage: __RAM_FUNC void foo(void) */ +#endif /* __RAM_FUNC */ +#ifndef __NO_INIT +#define __NO_INIT __attribute__((section(".noinit"))) +#endif /* __NO_INIT */ +#elif defined (__ICCARM__) /*!< IAR Compiler */ +#ifndef __WEAKDEF +#define __WEAKDEF __weak +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN _Pragma("data_alignment=4") +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE _Pragma("optimize = no_inline") +#endif /* __NOINLINE */ +#ifndef __RAM_FUNC +#define __RAM_FUNC __ramfunc +#endif /* __RAM_FUNC */ +#ifndef __NO_INIT +#define __NO_INIT __no_init +#endif /* __NO_INIT */ +#elif defined (__CC_ARM) /*!< ARM Compiler */ +#ifndef __WEAKDEF +#define __WEAKDEF __attribute__((weak)) +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN __align(4) +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE __attribute__((noinline)) +#endif /* __NOINLINE */ +#ifndef __NO_INIT +#define __NO_INIT +#endif /* __NO_INIT */ +/* RAM functions are defined using the toolchain options. +Functions that are executed in RAM should reside in a separate source module. +Using the 'Options for File' dialog you can simply change the 'Code / Const' +area of a module to a memory space in physical RAM. */ +#ifndef __RAM_FUNC +#define __RAM_FUNC __attribute__((section("RAMCODE"))) +#endif /* __RAM_FUNC */ +#else +#error "unsupported compiler!!" +#endif +/** + * @} + */ + +/** + * @defgroup Extend_Macros Extend Macros + * @{ + */ +/* Decimal to BCD */ +#define DEC2BCD(x) ((((x) / 10U) << 4U) + ((x) % 10U)) + +/* BCD to decimal */ +#define BCD2DEC(x) ((((x) >> 4U) * 10U) + ((x) & 0x0FU)) + +/* Returns the dimension of an array */ +#define ARRAY_SZ(x) ((sizeof(x)) / (sizeof((x)[0]))) + +/* Returns the minimum value out of two values */ +#define LL_MIN(x, y) ((x) < (y) ? (x) : (y)) + +/* Returns the maximum value out of two values */ +#define LL_MAX(x, y) ((x) > (y) ? (x) : (y)) +/** + * @} + */ + +/** + * @defgroup Check_Parameters_Validity Check Parameters Validity + * @{ + */ + +/* Check Functional State */ +#define IS_FUNCTIONAL_STATE(state) (((state) == DISABLE) || ((state) == ENABLE)) + +/** + * @defgroup Check_Address_Align_Validity Check Address Align Validity + * @{ + */ +#define IS_ADDR_ALIGN(addr, align) (0UL == (((uint32_t)(addr)) & (((uint32_t)(align)) - 1UL))) +#define IS_ADDR_ALIGN_HALFWORD(addr) (0UL == (((uint32_t)(addr)) & 0x1UL)) +#define IS_ADDR_ALIGN_WORD(addr) (0UL == (((uint32_t)(addr)) & 0x3UL)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup Peripheral_Bit_Band Peripheral Bit Band + * @{ + */ +#define __PERIPH_BIT_BAND_BASE (0x42000000UL) +#define __PERIPH_BASE (0x40000000UL) +#define __REG_OFS(regAddr) ((regAddr) - __PERIPH_BASE) +#define __BIT_BAND_ADDR(regAddr, pos) ((__REG_OFS(regAddr) << 5U) + ((uint32_t)(pos) << 2U) + __PERIPH_BIT_BAND_BASE) +#define PERIPH_BIT_BAND(regAddr, pos) (*(__IO uint32_t *)__BIT_BAND_ADDR((regAddr), (pos))) +/** + * @} + */ + +/** + * @defgroup Generic_Error_Codes Generic Error Codes + * @{ + */ +#define LL_OK (0) /*!< No error */ +#define LL_ERR (-1) /*!< Non-specific error code */ +#define LL_ERR_UNINIT (-2) /*!< Module (or part of it) was not initialized properly */ +#define LL_ERR_INVD_PARAM (-3) /*!< Provided parameter is not valid */ +#define LL_ERR_INVD_MD (-4) /*!< Operation not allowed in current mode */ +#define LL_ERR_NOT_RDY (-5) /*!< A requested final state is not reached */ +#define LL_ERR_BUSY (-6) /*!< A conflicting or requested operation is still in progress */ +#define LL_ERR_ADDR_ALIGN (-7) /*!< Address alignment does not match */ +#define LL_ERR_TIMEOUT (-8) /*!< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) */ +#define LL_ERR_BUF_EMPTY (-9) /*!< Circular buffer can not be read because the buffer is empty */ +#define LL_ERR_BUF_FULL (-10) /*!< Circular buffer can not be written because the buffer is full */ +/** + * @} + */ + +/** + * @defgroup Chip_Module_Switch Chip Module Switch + * @{ + */ +#define DDL_ON (1U) +#define DDL_OFF (0U) +/** + * @} + */ + +/** + * @defgroup Bit_Mask_Macros Bit Mask Macros + * @{ + */ +#define BIT_MASK_00 (1UL << 0U) +#define BIT_MASK_01 (1UL << 1U) +#define BIT_MASK_02 (1UL << 2U) +#define BIT_MASK_03 (1UL << 3U) +#define BIT_MASK_04 (1UL << 4U) +#define BIT_MASK_05 (1UL << 5U) +#define BIT_MASK_06 (1UL << 6U) +#define BIT_MASK_07 (1UL << 7U) +#define BIT_MASK_08 (1UL << 8U) +#define BIT_MASK_09 (1UL << 9U) +#define BIT_MASK_10 (1UL << 10U) +#define BIT_MASK_11 (1UL << 11U) +#define BIT_MASK_12 (1UL << 12U) +#define BIT_MASK_13 (1UL << 13U) +#define BIT_MASK_14 (1UL << 14U) +#define BIT_MASK_15 (1UL << 15U) +#define BIT_MASK_16 (1UL << 16U) +#define BIT_MASK_17 (1UL << 17U) +#define BIT_MASK_18 (1UL << 18U) +#define BIT_MASK_19 (1UL << 19U) +#define BIT_MASK_20 (1UL << 20U) +#define BIT_MASK_21 (1UL << 21U) +#define BIT_MASK_22 (1UL << 22U) +#define BIT_MASK_23 (1UL << 23U) +#define BIT_MASK_24 (1UL << 24U) +#define BIT_MASK_25 (1UL << 25U) +#define BIT_MASK_26 (1UL << 26U) +#define BIT_MASK_27 (1UL << 27U) +#define BIT_MASK_28 (1UL << 28U) +#define BIT_MASK_29 (1UL << 29U) +#define BIT_MASK_30 (1UL << 30U) +#define BIT_MASK_31 (1UL << 31U) +/** + * @} + */ + +/** + * @defgroup Register_Macros Register Macros + * @{ + */ +#define RW_MEM8(addr) (*(volatile uint8_t *)(addr)) +#define RW_MEM16(addr) (*(volatile uint16_t *)(addr)) +#define RW_MEM32(addr) (*(volatile uint32_t *)(addr)) + +#define SET_REG_BIT(REG, BIT) ((REG) |= (BIT)) +#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT))) +#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT))) +#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT))) + +#define CLR_REG_BIT(REG, BIT) ((REG) &= (~(BIT))) +#define CLR_REG8_BIT(REG, BIT) ((REG) &= ((uint8_t)(~((uint8_t)(BIT))))) +#define CLR_REG16_BIT(REG, BIT) ((REG) &= ((uint16_t)(~((uint16_t)(BIT))))) +#define CLR_REG32_BIT(REG, BIT) ((REG) &= ((uint32_t)(~((uint32_t)(BIT))))) + +#define READ_REG_BIT(REG, BIT) ((REG) & (BIT)) +#define READ_REG8_BIT(REG, BIT) ((REG) & ((uint8_t)(BIT))) +#define READ_REG16_BIT(REG, BIT) ((REG) & ((uint16_t)(BIT))) +#define READ_REG32_BIT(REG, BIT) ((REG) & ((uint32_t)(BIT))) + +#define CLR_REG(REG) ((REG) = (0U)) +#define CLR_REG8(REG) ((REG) = ((uint8_t)(0U))) +#define CLR_REG16(REG) ((REG) = ((uint16_t)(0U))) +#define CLR_REG32(REG) ((REG) = ((uint32_t)(0UL))) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) +#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL))) +#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL))) +#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL))) + +#define READ_REG(REG) (REG) +#define READ_REG8(REG) (REG) +#define READ_REG16(REG) (REG) +#define READ_REG32(REG) (REG) + +#define MODIFY_REG(REGS, CLRMASK, SETMASK) (WRITE_REG((REGS), (((READ_REG(REGS)) & (~(CLRMASK))) | ((SETMASK) & (CLRMASK))))) +#define MODIFY_REG8(REGS, CLRMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLRMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLRMASK))))) +#define MODIFY_REG16(REGS, CLRMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLRMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLRMASK))))) +#define MODIFY_REG32(REGS, CLRMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLRMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLRMASK))))) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DEF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dma.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dma.h new file mode 100644 index 0000000000..aafa7fc294 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dma.h @@ -0,0 +1,567 @@ +/** + ******************************************************************************* + * @file hc32_ll_dma.h + * @brief This file contains all the functions prototypes of the DMA driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DMA_H__ +#define __HC32_LL_DMA_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_DMA + * @{ + */ + +#if (LL_DMA_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Types DMA Global Types + * @{ + */ + +/** + * @brief DMA basic configuration + */ +typedef struct { + uint32_t u32IntEn; /*!< Specifies the DMA interrupt function. + This parameter can be a value of @ref DMA_Int_Config */ + uint32_t u32SrcAddr; /*!< Specifies the DMA source address. */ + uint32_t u32DestAddr; /*!< Specifies the DMA destination address. */ + uint32_t u32DataWidth; /*!< Specifies the DMA transfer data width. + This parameter can be a value of @ref DMA_DataWidth_Sel */ + uint32_t u32BlockSize; /*!< Specifies the DMA block size. */ + uint32_t u32TransCount; /*!< Specifies the DMA transfer count. */ + uint32_t u32SrcAddrInc; /*!< Specifies the source address increment mode. + This parameter can be a value of @ref DMA_SrcAddr_Incremented_Mode */ + uint32_t u32DestAddrInc; /*!< Specifies the destination address increment mode. + This parameter can be a value of @ref DMA_DesAddr_Incremented_Mode */ +} stc_dma_init_t; + +/** + * @brief DMA repeat mode configuration + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies the DMA source repeat function. + This parameter can be a value of @ref DMA_Repeat_Config */ + uint32_t u32SrcCount; /*!< Specifies the DMA source repeat size. */ + uint32_t u32DestCount; /*!< Specifies the DMA destination repeat size. */ +} stc_dma_repeat_init_t; + +/** + * @brief DMA non-sequence mode configuration + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies the DMA source non-sequence function. + This parameter can be a value of @ref DMA_NonSeq_Config */ + uint32_t u32SrcCount; /*!< Specifies the DMA source non-sequence function count. */ + uint32_t u32SrcOffset; /*!< Specifies the DMA source non-sequence function offset. */ + uint32_t u32DestCount; /*!< Specifies the DMA destination non-sequence function count. */ + uint32_t u32DestOffset; /*!< Specifies the DMA destination non-sequence function offset. */ +} stc_dma_nonseq_init_t; + +/** + * @brief DMA Link List Pointer (LLP) mode configuration + */ +typedef struct { + uint32_t u32State; /*!< Specifies the DMA LLP function. + This parameter can be a value of @ref DMA_Llp_En */ + uint32_t u32Mode; /*!< Specifies the DMA LLP auto or wait REQ. + This parameter can be a value of @ref DMA_Llp_Mode */ + uint32_t u32Addr; /*!< Specifies the DMA list pointer address for LLP function. */ +} stc_dma_llp_init_t; + +/** + * @brief DMA re-config function configuration + */ +typedef struct { + uint32_t u32CountMode; /*!< Specifies the DMA reconfig function count mode. + This parameter can be a value of @ref DMA_Reconfig_Count_Sel */ + uint32_t u32DestAddrMode; /*!< Specifies the DMA reconfig function destination address mode. + This parameter can be a value of @ref DMA_Reconfig_DestAddr_Sel */ + uint32_t u32SrcAddrMode; /*!< Specifies the DMA reconfig function source address mode. + This parameter can be a value of @ref DMA_Reconfig_SrcAddr_Sel */ +} stc_dma_reconfig_init_t; + +/** + * @brief Dma LLP(linked list pointer) descriptor structure definition + */ +typedef struct { + uint32_t SARx; /*!< LLP source address */ + uint32_t DARx; /*!< LLP destination address */ + uint32_t DTCTLx; /*!< LLP transfer count and block size */ + uint32_t RPTx; /*!< LLP source & destination repeat size */ + uint32_t SNSEQCTLx; /*!< LLP source non-seq count and offset */ + uint32_t DNSEQCTLx; /*!< LLP destination non-seq count and offset */ + uint32_t LLPx; /*!< LLP next list pointer */ + uint32_t CHCTLx; /*!< LLP channel control */ +} stc_dma_llp_descriptor_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Macros DMA Global Macros + * @{ + */ + +/** + * @defgroup DMA_Channel_selection DMA Channel Position selection + * @{ + */ +#define DMA_CH0 (0x00U) /*!< DMA Channel 0 */ +#define DMA_CH1 (0x01U) /*!< DMA Channel 1 */ + +#define DMA_CH2 (0x02U) /*!< DMA Channel 2 */ +#define DMA_CH3 (0x03U) /*!< DMA Channel 3 */ + +/** + * @} + */ + +/** + * @defgroup DMA_Mx_Channel_selection DMA Multiplex Channel selection + * @{ + */ +#define DMA_MX_CH0 (0x01UL) /*!< DMA Channel 0 position */ +#define DMA_MX_CH1 (0x02UL) /*!< DMA Channel 1 position */ +#define DMA_MX_CH_ALL (DMA_CHEN_CHEN) /*!< DMA Channel mask position */ + +#define DMA_MX_CH2 (0x04UL) /*!< DMA Channel 2 position */ +#define DMA_MX_CH3 (0x08UL) /*!< DMA Channel 3 position */ + +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Request_Err_Sel DMA request error flag selection + * @{ + */ +#define DMA_FLAG_REQ_ERR_CH0 (DMA_INTSTAT0_REQERR_0) /*!< DMA request error flag CH.0 */ +#define DMA_FLAG_REQ_ERR_CH1 (DMA_INTSTAT0_REQERR_1) /*!< DMA request error flag CH.1 */ + +#define DMA_FLAG_REQ_ERR_CH2 (DMA_INTSTAT0_REQERR_2) /*!< DMA request error flag CH.2 */ +#define DMA_FLAG_REQ_ERR_CH3 (DMA_INTSTAT0_REQERR_3) /*!< DMA request error flag CH.3 */ + +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Trans_Err_Sel DMA transfer error flag selection + * @{ + */ +#define DMA_FLAG_TRANS_ERR_CH0 (DMA_INTSTAT0_TRNERR_0) /*!< DMA transfer error flag CH.0 */ +#define DMA_FLAG_TRANS_ERR_CH1 (DMA_INTSTAT0_TRNERR_1) /*!< DMA transfer error flag CH.1 */ + +#define DMA_FLAG_TRANS_ERR_CH2 (DMA_INTSTAT0_TRNERR_2) /*!< DMA transfer error flag CH.2 */ +#define DMA_FLAG_TRANS_ERR_CH3 (DMA_INTSTAT0_TRNERR_3) /*!< DMA transfer error flag CH.3 */ + +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Btc_Sel DMA block transfer completed flag selection + * @{ + */ +#define DMA_FLAG_BTC_CH0 (DMA_INTSTAT1_BTC_0) /*!< DMA block transfer completed flag CH.0 */ +#define DMA_FLAG_BTC_CH1 (DMA_INTSTAT1_BTC_1) /*!< DMA block transfer completed flag CH.1 */ + +#define DMA_FLAG_BTC_CH2 (DMA_INTSTAT1_BTC_2) /*!< DMA block transfer completed flag CH.2 */ +#define DMA_FLAG_BTC_CH3 (DMA_INTSTAT1_BTC_3) /*!< DMA block transfer completed flag CH.3 */ + +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Tc_Sel DMA transfer completed flag selection + * @{ + */ +#define DMA_FLAG_TC_CH0 (DMA_INTSTAT1_TC_0) /*!< DMA transfer completed flag CH.0 */ +#define DMA_FLAG_TC_CH1 (DMA_INTSTAT1_TC_1) /*!< DMA transfer completed flag CH.1 */ + +#define DMA_FLAG_TC_CH2 (DMA_INTSTAT1_TC_2) /*!< DMA transfer completed flag CH.2 */ +#define DMA_FLAG_TC_CH3 (DMA_INTSTAT1_TC_3) /*!< DMA transfer completed flag CH.3 */ + +/** + * @} + */ + +/** + * @defgroup DMA_Int_Request_Err_Sel DMA request error interrupt selection + * @{ + */ +#define DMA_INT_REQ_ERR_CH0 (DMA_INTMASK0_MSKREQERR_0) /*!< DMA request error interrupt CH.0 */ +#define DMA_INT_REQ_ERR_CH1 (DMA_INTMASK0_MSKREQERR_1) /*!< DMA request error interrupt CH.1 */ + +#define DMA_INT_REQ_ERR_CH2 (DMA_INTMASK0_MSKREQERR_2) /*!< DMA request error interrupt CH.2 */ +#define DMA_INT_REQ_ERR_CH3 (DMA_INTMASK0_MSKREQERR_3) /*!< DMA request error interrupt CH.3 */ + +/** + * @} + */ + +/** + * @defgroup DMA_Int_Trans_Err_Sel DMA transfer error interrupt selection + * @{ + */ +#define DMA_INT_TRANS_ERR_CH0 (DMA_INTMASK0_MSKTRNERR_0) /*!< DMA transfer error interrupt CH.0 */ +#define DMA_INT_TRANS_ERR_CH1 (DMA_INTMASK0_MSKTRNERR_1) /*!< DMA transfer error interrupt CH.1 */ + +#define DMA_INT_TRANS_ERR_CH2 (DMA_INTMASK0_MSKTRNERR_2) /*!< DMA transfer error interrupt CH.2 */ +#define DMA_INT_TRANS_ERR_CH3 (DMA_INTMASK0_MSKTRNERR_3) /*!< DMA transfer error interrupt CH.3 */ + +/** + * @} + */ + +/** + * @defgroup DMA_Int_Btc_Sel DMA block transfer completed interrupt selection + * @{ + */ +#define DMA_INT_BTC_CH0 (DMA_INTMASK1_MSKBTC_0) /*!< DMA block transfer completed interrupt CH.0 */ +#define DMA_INT_BTC_CH1 (DMA_INTMASK1_MSKBTC_1) /*!< DMA block transfer completed interrupt CH.1 */ + +#define DMA_INT_BTC_CH2 (DMA_INTMASK1_MSKBTC_2) /*!< DMA block transfer completed interrupt CH.2 */ +#define DMA_INT_BTC_CH3 (DMA_INTMASK1_MSKBTC_3) /*!< DMA block transfer completed interrupt CH.3 */ + +/** + * @} + */ + +/** + * @defgroup DMA_Int_Tc_Sel DMA transfer completed interrupt selection + * @{ + */ +#define DMA_INT_TC_CH0 (DMA_INTMASK1_MSKTC_0) /*!< DMA transfer completed interrupt CH.0 */ +#define DMA_INT_TC_CH1 (DMA_INTMASK1_MSKTC_1) /*!< DMA transfer completed interrupt CH.1 */ + +#define DMA_INT_TC_CH2 (DMA_INTMASK1_MSKTC_2) /*!< DMA transfer completed interrupt CH.2 */ +#define DMA_INT_TC_CH3 (DMA_INTMASK1_MSKTC_3) /*!< DMA transfer completed interrupt CH.3 */ + +/** + * @} + */ + +/** + * @defgroup DMA_FlagMsk_Sel DMA flag mask selection + * @{ + */ +#define DMA_FLAG_ERR_MASK (DMA_INTSTAT0_TRNERR | DMA_INTSTAT0_REQERR) /*!< DMA error flag mask */ +#define DMA_FLAG_TRANS_MASK (DMA_INTSTAT1_TC | DMA_INTSTAT1_BTC) /*!< DMA transfer flag mask */ +/** + * @} + */ + +/** + * @defgroup DMA_IntMsk_Sel DMA interrupt mask selection + * @{ + */ +#define DMA_INT_ERR_MASK (DMA_INTMASK0_MSKREQERR | DMA_INTMASK0_MSKTRNERR) /*!< DMA error interrupt mask */ +#define DMA_INT_TRANS_MASK (DMA_INTMASK1_MSKTC | DMA_INTMASK1_MSKBTC) /*!< DMA transfer interrupt mask */ +/** + * @} + */ + +/** + * @defgroup DMA_Req_Status_Sel DMA request status + * @{ + */ +#define DMA_STAT_REQ_RECONFIG (DMA_REQSTAT_RCFGREQ) /*!< DMA request from reconfig */ +#define DMA_STAT_REQ_CH0 (DMA_REQSTAT_CHREQ_0) /*!< DMA request from CH.0 */ +#define DMA_STAT_REQ_CH1 (DMA_REQSTAT_CHREQ_1) /*!< DMA request from CH.1 */ +#define DMA_STAT_REQ_CH2 (DMA_REQSTAT_CHREQ_2) /*!< DMA request from CH.2 */ +#define DMA_STAT_REQ_CH3 (DMA_REQSTAT_CHREQ_3) /*!< DMA request from CH.3 */ + +#define DMA_STAT_REQ_MASK (DMA_REQSTAT_CHREQ | DMA_REQSTAT_RCFGREQ) /*!< DMA request mask */ +/** + * @} + */ + +/** + * @defgroup DMA_Trans_Status_Sel DMA transfer status + * @{ + */ +#define DMA_STAT_TRANS_CH0 (DMA_CHSTAT_CHACT_0) /*!< DMA transfer status of CH.0 */ +#define DMA_STAT_TRANS_CH1 (DMA_CHSTAT_CHACT_1) /*!< DMA transfer status of CH.1 */ +#define DMA_STAT_TRANS_DMA (DMA_CHSTAT_DMAACT) /*!< DMA transfer status of the DMA */ + +#define DMA_STAT_TRANS_CH2 (DMA_CHSTAT_CHACT_2) /*!< DMA transfer status of CH.2 */ +#define DMA_STAT_TRANS_CH3 (DMA_CHSTAT_CHACT_3) /*!< DMA transfer status of CH.3 */ + +#define DMA_STAT_TRANS_RECONFIG (DMA_CHSTAT_RCFGACT) /*!< DMA reconfig status */ + +#define DMA_STAT_TRANS_MASK (DMA_CHSTAT_DMAACT | DMA_CHSTAT_CHACT | DMA_CHSTAT_RCFGACT) +/** + * @} + */ + +/** + * @defgroup DMA_DataWidth_Sel DMA transfer data width + * @{ + */ +#define DMA_DATAWIDTH_8BIT (0x00000000UL) /*!< DMA transfer data width 8bit */ +#define DMA_DATAWIDTH_16BIT (DMA_CHCTL_HSIZE_0) /*!< DMA transfer data width 16bit */ +#define DMA_DATAWIDTH_32BIT (DMA_CHCTL_HSIZE_1) /*!< DMA transfer data width 32bit */ + +/** + * @} + */ + +/** + * @defgroup DMA_Llp_En DMA LLP(linked list pinter) enable or disable + * @{ + */ +#define DMA_LLP_DISABLE (0x00000000UL) /*!< DMA linked list pinter disable */ + +#define DMA_LLP_ENABLE (DMA_CHCTL_LLPEN) /*!< DMA linked list pinter enable */ + +/** + * @} + */ + +/** + * @defgroup DMA_Llp_Mode DMA linked list pinter mode while transferring complete + * @{ + */ +#define DMA_LLP_WAIT (0x00000000UL) /*!< DMA Llp wait next request while transfering complete */ + +#define DMA_LLP_RUN (DMA_CHCTL_LLPRUN) /*!< DMA Llp run right now while transfering complete */ + +/** + * @} + */ + +/** + * @defgroup DMA_SrcAddr_Incremented_Mode DMA source address increment mode + * @{ + */ +#define DMA_SRC_ADDR_FIX (0x00000000UL) /*!< DMA source address fix */ + +#define DMA_SRC_ADDR_INC (DMA_CHCTL_SINC_0) /*!< DMA source address increment */ +#define DMA_SRC_ADDR_DEC (DMA_CHCTL_SINC_1) /*!< DMA source address decrement */ + +/** + * @} + */ + +/** + * @defgroup DMA_DesAddr_Incremented_Mode DMA destination address increment mode + * @{ + */ +#define DMA_DEST_ADDR_FIX (0x00000000UL) /*!< DMA destination address fix */ +#define DMA_DEST_ADDR_INC (DMA_CHCTL_DINC_0) /*!< DMA destination address increment */ +#define DMA_DEST_ADDR_DEC (DMA_CHCTL_DINC_1) /*!< DMA destination address decrement */ + +/** + * @} + */ + +/** + * @defgroup DMA_Int_Config DMA interrupt function config + * @{ + */ +#define DMA_INT_ENABLE (DMA_CHCTL_IE) /*!< DMA interrupt enable */ +#define DMA_INT_DISABLE (0x00000000UL) /*!< DMA interrupt disable */ +/** + * @} + */ + +/** + * @defgroup DMA_Repeat_Config DMA repeat mode function config + * @{ + */ +#define DMA_RPT_NONE (0x00000000UL) /*!< DMA repeat disable */ +#define DMA_RPT_SRC (DMA_CHCTL_SRPTEN) /*!< DMA source repeat enable */ +#define DMA_RPT_DEST (DMA_CHCTL_DRPTEN) /*!< DMA destination repeat enable */ +#define DMA_RPT_BOTH (DMA_CHCTL_SRPTEN | DMA_CHCTL_DRPTEN) /*!< DMA source & destination repeat enable */ + +/** + * @} + */ + +/** + * @defgroup DMA_NonSeq_Config DMA non-sequence mode function config + * @{ + */ +#define DMA_NON_SEQ_NONE (0x00000000UL) /*!< DMA non-sequence disable */ +#define DMA_NON_SEQ_SRC (DMA_CHCTL_SNSEQEN) /*!< DMA source non-sequence enable */ +#define DMA_NON_SEQ_DEST (DMA_CHCTL_DNSEQEN) /*!< DMA destination non-sequence enable */ +#define DMA_NON_SEQ_BOTH (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN) /*!< DMA source & destination non-sequence enable */ + +/** + * @} + */ + +/** + * @defgroup DMA_Reconfig_Count_Sel DMA reconfig count mode selection + * @{ + */ +#define DMA_RC_CNT_KEEP (0x00000000UL) /*!< Keep the original counting method */ +#define DMA_RC_CNT_SRC (DMA_RCFGCTL_CNTMD_0) /*!< Use source address counting method */ +#define DMA_RC_CNT_DEST (DMA_RCFGCTL_CNTMD_1) /*!< Use destination address counting method */ +/** + * @} + */ + +/** + * @defgroup DMA_Reconfig_DestAddr_Sel DMA reconfig destination address mode selection + * @{ + */ +#define DMA_RC_DEST_ADDR_KEEP (0x00000000UL) /*!< Destination address Keep the original mode */ +#define DMA_RC_DEST_ADDR_NS (DMA_RCFGCTL_DARMD_0) /*!< Destination address non-sequence */ +#define DMA_RC_DEST_ADDR_RPT (DMA_RCFGCTL_DARMD_1) /*!< Destination address repeat */ +/** + * @} + */ + +/** + * @defgroup DMA_Reconfig_SrcAddr_Sel DMA reconfig source address mode selection + * @{ + */ +#define DMA_RC_SRC_ADDR_KEEP (0x00000000UL) /*!< Source address Keep the original mode */ +#define DMA_RC_SRC_ADDR_NS (DMA_RCFGCTL_SARMD_0) /*!< Source address non-sequence */ +#define DMA_RC_SRC_ADDR_RPT (DMA_RCFGCTL_SARMD_1) /*!< Source address repeat */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DMA_Global_Functions + * @{ + */ +void DMA_Cmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState); + +void DMA_ErrIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState); +en_flag_status_t DMA_GetErrStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag); +void DMA_ClearErrStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag); + +void DMA_TransCompleteIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32TransCompleteInt, en_functional_state_t enNewState); +en_flag_status_t DMA_GetTransCompleteStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag); +void DMA_ClearTransCompleteStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag); + +int32_t DMA_ChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); + +en_flag_status_t DMA_GetRequestStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status); +en_flag_status_t DMA_GetTransStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status); + +int32_t DMA_SetSrcAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr); +int32_t DMA_SetDestAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr); +int32_t DMA_SetTransCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Count); +int32_t DMA_SetBlockSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size); + +int32_t DMA_SetSrcRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size); +int32_t DMA_SetDestRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size); +int32_t DMA_SetNonSeqSrcCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count); +int32_t DMA_SetNonSeqDestCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count); +int32_t DMA_SetNonSeqSrcOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset); +int32_t DMA_SetNonSeqDestOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset); + +void DMA_SetLlpAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr); + +int32_t DMA_StructInit(stc_dma_init_t *pstcDmaInit); +int32_t DMA_Init(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit); +void DMA_DeInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch); + +int32_t DMA_RepeatStructInit(stc_dma_repeat_init_t *pstcDmaRepeatInit); +int32_t DMA_RepeatInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_repeat_init_t *pstcDmaRepeatInit); + +int32_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit); +int32_t DMA_NonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit); + +int32_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit); +int32_t DMA_LlpInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit); + +void DMA_LlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); + +int32_t DMA_ReconfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit); +int32_t DMA_ReconfigInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit); +void DMA_ReconfigCmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState); +void DMA_ReconfigLlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); + +uint32_t DMA_GetSrcAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetDestAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetTransCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetBlockSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetSrcRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetDestRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqSrcCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqDestCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqSrcOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqDestOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); + +/** + * @} + */ + +#endif /* LL_DMA_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DMA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_efm.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_efm.h new file mode 100644 index 0000000000..53bbc06af7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_efm.h @@ -0,0 +1,458 @@ +/** + ******************************************************************************* + * @file hc32_ll_efm.h + * @brief This file contains all the functions prototypes of the EFM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_EFM_H__ +#define __HC32_LL_EFM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EFM + * @{ + */ + +#if (LL_EFM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EFM_Global_Types EFM Global Types + * @{ + */ +/** + * @brief EFM unique ID definition + */ +typedef struct { + uint32_t u32UniqueID0; /*!< unique ID 0. */ + uint32_t u32UniqueID1; /*!< unique ID 1. */ + uint32_t u32UniqueID2; /*!< unique ID 2. */ +} stc_efm_unique_id_t; + +typedef struct { + uint32_t u32State; + uint32_t u32Addr; + uint32_t u32Size; +} stc_efm_remap_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EFM_Global_Macros EFM Global Macros + * @{ + */ +/** + * @defgroup EFM_Address EFM Address Area + * @{ + */ +#define EFM_START_ADDR (0x00000000UL) /*!< Flash start address */ + +#define EFM_END_ADDR (0x0007FFFFUL) /*!< Flash end address */ +#define EFM_OTP_START_ADDR (0x03000C00UL) /*!< OTP start address */ +#define EFM_OTP_END_ADDR (0x03000FFBUL) /*!< OTP end address */ +#define EFM_OTP_LOCK_ADDR_START (0x03000FC0UL) /*!< OTP lock start address */ +#define EFM_OTP_LOCK_ADDR_END (0x03000FFCUL) /*!< OTP lock end address */ + +/** + * @} + */ + +/** + * @defgroup EFM_Chip_Sel EFM Chip Selection + * @{ + */ +#define EFM_CHIP_ALL (EFM_FSTP_FSTP) +/** + * @} + */ + +/** + * @defgroup EFM_Bus_Status EFM Bus Status + * @{ + */ +#define EFM_BUS_HOLD (0x0UL) /*!< Bus busy while flash program or erase */ +#define EFM_BUS_RELEASE (0x1UL) /*!< Bus release while flash program or erase */ +/** + * @} + */ + +/** + * @defgroup EFM_Wait_Cycle EFM Wait Cycle + * @{ + */ + +#define EFM_WAIT_CYCLE0 (0U << EFM_FRMC_FLWT_POS) /*!< Don't insert read wait cycle */ +#define EFM_WAIT_CYCLE1 (1U << EFM_FRMC_FLWT_POS) /*!< Insert 1 read wait cycle */ + +#define EFM_WAIT_CYCLE2 (2U << EFM_FRMC_FLWT_POS) /*!< Insert 2 read wait cycles */ +#define EFM_WAIT_CYCLE3 (3U << EFM_FRMC_FLWT_POS) /*!< Insert 3 read wait cycles */ +#define EFM_WAIT_CYCLE4 (4U << EFM_FRMC_FLWT_POS) /*!< Insert 4 read wait cycles */ +#define EFM_WAIT_CYCLE5 (5U << EFM_FRMC_FLWT_POS) /*!< Insert 5 read wait cycles */ +#define EFM_WAIT_CYCLE6 (6U << EFM_FRMC_FLWT_POS) /*!< Insert 6 read wait cycles */ +#define EFM_WAIT_CYCLE7 (7U << EFM_FRMC_FLWT_POS) /*!< Insert 7 read wait cycles */ +#define EFM_WAIT_CYCLE8 (8U << EFM_FRMC_FLWT_POS) /*!< Insert 8 read wait cycles */ +#define EFM_WAIT_CYCLE9 (9U << EFM_FRMC_FLWT_POS) /*!< Insert 9 read wait cycles */ +#define EFM_WAIT_CYCLE10 (10U << EFM_FRMC_FLWT_POS) /*!< Insert 10 read wait cycles */ +#define EFM_WAIT_CYCLE11 (11U << EFM_FRMC_FLWT_POS) /*!< Insert 11 read wait cycles */ +#define EFM_WAIT_CYCLE12 (12U << EFM_FRMC_FLWT_POS) /*!< Insert 12 read wait cycles */ +#define EFM_WAIT_CYCLE13 (13U << EFM_FRMC_FLWT_POS) /*!< Insert 13 read wait cycles */ +#define EFM_WAIT_CYCLE14 (14U << EFM_FRMC_FLWT_POS) /*!< Insert 14 read wait cycles */ +#define EFM_WAIT_CYCLE15 (15U << EFM_FRMC_FLWT_POS) /*!< Insert 15 read wait cycles */ +/** + * @} + */ + +/** + * @defgroup EFM_Swap_Address EFM Swap Address + * @{ + */ +#define EFM_SWAP_ADDR (0x0007FFDCUL) +#define EFM_SWAP_DATA (0xFFFF4321UL) +/** + * @} + */ + +/** + * @defgroup EFM_OperateMode_Sel EFM Operate Mode Selection + * @{ + */ +#define EFM_MD_READONLY (0x0UL << EFM_FWMC_PEMOD_POS) /*!< Read only mode */ +#define EFM_MD_PGM_SINGLE (0x1UL << EFM_FWMC_PEMOD_POS) /*!< Program single mode */ +#define EFM_MD_PGM_READBACK (0x2UL << EFM_FWMC_PEMOD_POS) /*!< Program and read back mode */ +#define EFM_MD_PGM_SEQ (0x3UL << EFM_FWMC_PEMOD_POS) /*!< Program sequence mode */ +#define EFM_MD_ERASE_SECTOR (0x4UL << EFM_FWMC_PEMOD_POS) /*!< Sector erase mode */ + +#define EFM_MD_ERASE_ALL_CHIP (0x5UL << EFM_FWMC_PEMOD_POS) /*!< Chip erase mode */ +/** + * @} + */ + +/** + * @defgroup EFM_Flag_Sel EFM Flag Selection + * @{ + */ +#define EFM_FLAG_PEWERR (EFM_FSR_PEWERR) /*!< EFM Programming/erase error flag. */ +#define EFM_FLAG_PGMISMTCH (EFM_FSR_PGMISMTCH) /*!< EFM Programming missing match error flag */ +#define EFM_FLAG_OPTEND (EFM_FSR_OPTEND) /*!< EFM End of operation flag. */ +#define EFM_FLAG_COLERR (EFM_FSR_COLERR) /*!< EFM Read collide error flag. */ +#define EFM_FLAG_PEPRTERR (EFM_FSR_PEPRTERR) /*!< EFM write protect address error flag */ +#define EFM_FLAG_RDY (EFM_FSR_RDY) /*!< EFM ready flag. */ +#define EFM_FLAG_PGSZERR (EFM_FSR_PGSZERR) /*!< EFM Programming/erase protect area error flag. */ + +#define EFM_FLAG_ALL (EFM_FLAG_PEWERR | EFM_FLAG_PGMISMTCH | EFM_FLAG_OPTEND | EFM_FLAG_PEPRTERR | \ + EFM_FLAG_COLERR | EFM_FLAG_PGSZERR | EFM_FLAG_RDY) + +/** + * @} + */ + +/** + * @defgroup EFM_Interrupt_Sel EFM Interrupt Selection + * @{ + */ +#define EFM_INT_PEERR (EFM_FITE_PEERRITE) /*!< Program/erase error Interrupt source */ +#define EFM_INT_OPTEND (EFM_FITE_OPTENDITE) /*!< End of EFM operation Interrupt source */ +#define EFM_INT_COLERR (EFM_FITE_COLERRITE) /*!< Read collide error Interrupt source */ + +#define EFM_INT_ALL (EFM_FITE_PEERRITE | EFM_FITE_OPTENDITE | EFM_FITE_COLERRITE) +/** + * @} + */ + +/** + * @defgroup EFM_Keys EFM Keys + * @{ + */ +#define EFM_REG_UNLOCK_KEY1 (0x0123UL) +#define EFM_REG_UNLOCK_KEY2 (0x3210UL) +#define EFM_REG_LOCK_KEY (0x0000UL) +/** + * @} + */ + +/** + * @defgroup EFM_Sector_Size EFM Sector Size + * @{ + */ +#define SECTOR_SIZE (0x2000UL) + +/** + * @} + */ + +/** + * @defgroup EFM_Sector_Address EFM Sector Address + * @{ + */ +#define EFM_SECTOR_ADDR(x) (uint32_t)(SECTOR_SIZE * (x)) +/** + * @} + */ + +/** + * @defgroup EFM_OTP_Base_Address EFM Otp Base Address + * @{ + */ +#define EFM_OTP_BASE1_ADDR (0x03000C00UL) +#define EFM_OTP_BASE1_SIZE (0x40UL) +#define EFM_OTP_BASE1_OFFSET (0UL) +#define EFM_OTP_LOCK_ADDR (0x03000FC0UL) + +/** + * @} + */ + +/** + * @defgroup EFM_OTP_Address EFM Otp Address + * @{ + */ +#define EFM_OTP_BLOCK0 (EFM_OTP_BASE1_ADDR + ((0UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK1 (EFM_OTP_BASE1_ADDR + ((1UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK2 (EFM_OTP_BASE1_ADDR + ((2UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK3 (EFM_OTP_BASE1_ADDR + ((3UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK4 (EFM_OTP_BASE1_ADDR + ((4UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK5 (EFM_OTP_BASE1_ADDR + ((5UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK6 (EFM_OTP_BASE1_ADDR + ((6UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK7 (EFM_OTP_BASE1_ADDR + ((7UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK8 (EFM_OTP_BASE1_ADDR + ((8UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK9 (EFM_OTP_BASE1_ADDR + ((9UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK10 (EFM_OTP_BASE1_ADDR + ((10UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK11 (EFM_OTP_BASE1_ADDR + ((11UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK12 (EFM_OTP_BASE1_ADDR + ((12UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK13 (EFM_OTP_BASE1_ADDR + ((13UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) +#define EFM_OTP_BLOCK14 (EFM_OTP_BASE1_ADDR + ((14UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE)) + +/** + * @} + */ + +/** + * @defgroup EFM_OTP_Lock_Address EFM Otp Lock_address + * @note x at range of 0~14 while HC32F460, HC32F451, HC32F452 + * x at range of 0~181 while HC32F4A0, HC32F472 + * @{ + */ +#define EFM_OTP_BLOCK_LOCKADDR(x) (EFM_OTP_LOCK_ADDR + 0x04UL * (x)) /*!< OTP block x lock address */ +/** + * @} + */ + +#define EFM_REMAP_REG_LOCK_KEY (0x0000UL) +#define EFM_REMAP_REG_UNLOCK_KEY1 (0x0123UL) +#define EFM_REMAP_REG_UNLOCK_KEY2 (0x3210UL) + +/** + * @defgroup EFM_Remap_State EFM remap function state + * @{ + */ +#define EFM_REMAP_OFF (0UL) +#define EFM_REMAP_ON EFM_MMF_REMCR_EN +/** + * @} + */ + +/** + * @defgroup EFM_Remap_Size EFM remap size definition + * @note refer to chip user manual for details size spec. + * @{ + */ +#define EFM_REMAP_4K (12UL) +#define EFM_REMAP_8K (13UL) +#define EFM_REMAP_16K (14UL) +#define EFM_REMAP_32K (15UL) +#define EFM_REMAP_64K (16UL) +#define EFM_REMAP_128K (17UL) +#define EFM_REMAP_256K (18UL) +#define EFM_REMAP_512K (19UL) +/** + * @} + */ + +/** + * @defgroup EFM_Remap_Index EFM remap index + * @{ + */ +#define EFM_REMAP_IDX0 (0U) +#define EFM_REMAP_IDX1 (1U) +/** + * @} + */ + +/** + * @defgroup EFM_Remap_BaseAddr EFM remap base address + * @{ + */ +#define EFM_REMAP_BASE_ADDR0 (0x2000000UL) +#define EFM_REMAP_BASE_ADDR1 (0x2080000UL) +/** + * @} + */ + +/** + * @defgroup EFM_Remap_Region EFM remap ROM/RAM region + * @{ + */ +#define EFM_REMAP_ROM_END_ADDR EFM_END_ADDR + +#define EFM_REMAP_RAM_START_ADDR (0x1FFF8000UL) +#define EFM_REMAP_RAM_END_ADDR (0x1FFFFFFFUL) +/** + * @} + */ + +/** + * @} + */ +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EFM_Global_Functions + * @{ + */ + +/** + * @brief EFM Protect Unlock. + * @param None + * @retval None + */ + +__STATIC_INLINE void EFM_REG_Unlock(void) +{ + WRITE_REG32(CM_EFM->FAPRT, EFM_REG_UNLOCK_KEY1); + WRITE_REG32(CM_EFM->FAPRT, EFM_REG_UNLOCK_KEY2); +} + +/** + * @brief EFM Protect Lock. + * @param None + * @retval None + */ +__STATIC_INLINE void EFM_REG_Lock(void) +{ + WRITE_REG32(CM_EFM->FAPRT, EFM_REG_LOCK_KEY); +} + +/** + * @brief EFM remap Unlock. + * @param None + * @retval None + */ +__STATIC_INLINE void EFM_REMAP_Unlock(void) +{ + WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_UNLOCK_KEY1); + WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_UNLOCK_KEY2); +} + +/** + * @brief EFM remap Lock. + * @param None + * @retval None + */ +__STATIC_INLINE void EFM_REMAP_Lock(void) +{ + WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_LOCK_KEY); +} + +void EFM_Cmd(uint32_t u32Flash, en_functional_state_t enNewState); +void EFM_FWMC_Cmd(en_functional_state_t enNewState); +void EFM_SetBusStatus(uint32_t u32Status); +void EFM_IntCmd(uint32_t u32EfmInt, en_functional_state_t enNewState); +void EFM_ClearStatus(uint32_t u32Flag); +int32_t EFM_SetWaitCycle(uint32_t u32WaitCycle); +int32_t EFM_SetOperateMode(uint32_t u32Mode); +int32_t EFM_ReadByte(uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32ByteLen); +int32_t EFM_Program(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len); +int32_t EFM_ProgramWord(uint32_t u32Addr, uint32_t u32Data); +int32_t EFM_ProgramWordReadBack(uint32_t u32Addr, uint32_t u32Data); +int32_t EFM_SequenceProgram(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len); +int32_t EFM_SectorErase(uint32_t u32Addr); +int32_t EFM_ChipErase(uint8_t u8Chip); + +en_flag_status_t EFM_GetAnyStatus(uint32_t u32Flag); +en_flag_status_t EFM_GetStatus(uint32_t u32Flag); +void EFM_GetUID(stc_efm_unique_id_t *pstcUID); + +void EFM_CacheCmd(en_functional_state_t enNewState); + +void EFM_LowVoltageReadCmd(en_functional_state_t enNewState); +int32_t EFM_SwapCmd(en_functional_state_t enNewState); +en_flag_status_t EFM_GetSwapStatus(void); +int32_t EFM_OTP_Lock(uint32_t u32Addr); + +int32_t EFM_REMAP_StructInit(stc_efm_remap_init_t *pstcEfmRemapInit); +int32_t EFM_REMAP_Init(uint8_t u8RemapIdx, stc_efm_remap_init_t *pstcEfmRemapInit); +void EFM_REMAP_DeInit(void); +void EFM_REMAP_Cmd(uint8_t u8RemapIdx, en_functional_state_t enNewState); +void EFM_REMAP_SetAddr(uint8_t u8RemapIdx, uint32_t u32Addr); +void EFM_REMAP_SetSize(uint8_t u8RemapIdx, uint32_t u32Size); + +void EFM_LowVoltageCmd(en_functional_state_t enNewState); + +void EFM_SetWindowProtectAddr(uint32_t u32StartAddr, uint32_t u32EndAddr); + +/** + * @} + */ + +#endif /* LL_EFM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_EFM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_emb.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_emb.h new file mode 100644 index 0000000000..42a0029df0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_emb.h @@ -0,0 +1,413 @@ +/** + ******************************************************************************* + * @file hc32_ll_emb.h + * @brief This file contains all the functions prototypes of the EMB + * (Emergency Brake) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_EMB_H__ +#define __HC32_LL_EMB_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EMB + * @{ + */ + +#if (LL_EMB_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EMB_Global_Types EMB Global Types + * @{ + */ + +/** + * @brief EMB monitor OSC failure configuration + */ +typedef struct { + uint32_t u32OscState; /*!< Enable or disable EMB detect OSC failure function + This parameter can be a value of @ref EMB_OSC_Selection */ +} stc_emb_monitor_osc_t; + +/** + * @brief EMB monitor EMB port configuration + */ +typedef struct { + uint32_t u32PortState; /*!< Enable or disable EMB detect port in control function + This parameter can be a value of EMB_Port_Selection */ + uint32_t u32PortLevel; /*!< EMB detect port level + This parameter can be a value of EMB_Detect_Port_Level */ + uint32_t u32PortFilterDiv; /*!< EMB port filter division + This parameter can be a value of EMB_Port_Filter_Clock_Division */ + uint32_t u32PortFilterState; /*!< EMB port filter division + This parameter can be a value of EMB_Port_Filter_Selection */ +} stc_emb_monitor_port_config_t; + +/** + * @brief EMB monitor TMR4 or TMR6 PWM configuration + */ +typedef struct { + uint32_t u32PwmState; /*!< Enable or disable EMB detect TMR4/6 PWM channel same phase function + This parameter can be a value of EMB_TMR4_PWM_Selection or EMB_TMR6_PWM_Selection */ + uint32_t u32PwmLevel; /*!< Detect TMR4/6 PWM channel polarity level + This parameter can be a value of EMB_Detect_TMR4_PWM_Level or EMB_Detect_TMR6_PWM_Level */ +} stc_emb_monitor_tmr_pwm_t; + +/** + * @brief EMB monitor port in configuration + */ +typedef struct { + stc_emb_monitor_port_config_t stcPort1; /*!< EMB detect EMB port in function + This parameter details refer @ref stc_emb_monitor_port_config_t structure */ +} stc_emb_monitor_port_t; + +/** + * @brief EMB monitor CMP configuration + */ +typedef struct { + uint32_t u32Cmp1State; /*!< Enable or disable EMB detect CMP1 result function + This parameter can be a value of @ref EMB_CMP_Selection */ + uint32_t u32Cmp2State; /*!< Enable or disable EMB detect CMP2 result function + This parameter can be a value of @ref EMB_CMP_Selection */ + uint32_t u32Cmp3State; /*!< Enable or disable EMB detect CMP3 result function + This parameter can be a value of @ref EMB_CMP_Selection */ +} stc_emb_monitor_cmp_t; + +/** + * @brief EMB monitor TMR4 configuration + */ +typedef struct { + stc_emb_monitor_tmr_pwm_t stcTmr4PwmU; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr4PwmV; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr4PwmW; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ +} stc_emb_monitor_tmr4_t; + +/** + * @brief EMB monitor TMR6 configuration + */ +typedef struct { + stc_emb_monitor_tmr_pwm_t stcTmr6_1; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr6_2; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr6_3; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ +} stc_emb_monitor_tmr6_t; + +/** + * @brief EMB control TMR4 initialization configuration + */ +typedef struct { + stc_emb_monitor_cmp_t stcCmp; /*!< EMB detect CMP function + This parameter details refer @ref stc_emb_monitor_cmp_t structure */ + stc_emb_monitor_osc_t stcOsc; /*!< EMB detect OSC function + This parameter details refer @ref stc_emb_monitor_osc_t structure */ + stc_emb_monitor_port_t stcPort; /*!< EMB detect EMB port function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + stc_emb_monitor_tmr4_t stcTmr4; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr4_t structure */ +} stc_emb_tmr4_init_t; + +/** + * @brief EMB control TMR6 initialization configuration + */ +typedef struct { + stc_emb_monitor_cmp_t stcCmp; /*!< EMB detect CMP function + This parameter details refer @ref stc_emb_monitor_cmp_t structure */ + stc_emb_monitor_osc_t stcOsc; /*!< EMB detect OSC function + This parameter details refer @ref stc_emb_monitor_osc_t structure */ + stc_emb_monitor_port_t stcPort; /*!< EMB detect EMB port function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + stc_emb_monitor_tmr6_t stcTmr6; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr6_t structure */ +} stc_emb_tmr6_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EMB_Global_Macros EMB Global Macros + * @{ + */ + +/** + * @defgroup EMB_CMP_Selection EMB CMP Selection + * @{ + */ +#define EMB_CMP1_DISABLE (0UL) +#define EMB_CMP2_DISABLE (0UL) +#define EMB_CMP3_DISABLE (0UL) +#define EMB_CMP4_DISABLE (0UL) + +#define EMB_CMP1_ENABLE (EMB_CTL_CMPEN0) +#define EMB_CMP2_ENABLE (EMB_CTL_CMPEN1) +#define EMB_CMP3_ENABLE (EMB_CTL_CMPEN2) +/** + * @} + */ + +/** + * @defgroup EMB_OSC_Selection EMB OSC Selection + * @{ + */ +#define EMB_OSC_DISABLE (0UL) + +#define EMB_OSC_ENABLE (EMB_CTL_OSCSTPEN) +/** + * @} + */ + +/** + * @defgroup EMB_TMR4_PWM_Selection EMB TMR4 PWM Selection + * @{ + */ +#define EMB_TMR4_PWM_W_DISABLE (0UL) +#define EMB_TMR4_PWM_V_DISABLE (0UL) +#define EMB_TMR4_PWM_U_DISABLE (0UL) + +#define EMB_TMR4_PWM_W_ENABLE (EMB_CTL_PWMSEN0) +#define EMB_TMR4_PWM_V_ENABLE (EMB_CTL_PWMSEN1) +#define EMB_TMR4_PWM_U_ENABLE (EMB_CTL_PWMSEN2) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR4_PWM_Level EMB Detect TMR4 PWM Level + * @{ + */ +#define EMB_DETECT_TMR4_PWM_W_BOTH_LOW (0UL) +#define EMB_DETECT_TMR4_PWM_V_BOTH_LOW (0UL) +#define EMB_DETECT_TMR4_PWM_U_BOTH_LOW (0UL) + +#define EMB_DETECT_TMR4_PWM_W_BOTH_HIGH (EMB_PWMLV_PWMLV0) +#define EMB_DETECT_TMR4_PWM_V_BOTH_HIGH (EMB_PWMLV_PWMLV1) +#define EMB_DETECT_TMR4_PWM_U_BOTH_HIGH (EMB_PWMLV_PWMLV2) +/** + * @} + */ + +/** + * @defgroup EMB_TMR6_PWM_Selection EMB TMR6 PWM Selection + * @{ + */ +#define EMB_TMR6_1_PWM_DISABLE (0UL) +#define EMB_TMR6_2_PWM_DISABLE (0UL) +#define EMB_TMR6_3_PWM_DISABLE (0UL) +#define EMB_TMR6_4_PWM_DISABLE (0UL) +#define EMB_TMR6_5_PWM_DISABLE (0UL) +#define EMB_TMR6_6_PWM_DISABLE (0UL) +#define EMB_TMR6_7_PWM_DISABLE (0UL) +#define EMB_TMR6_8_PWM_DISABLE (0UL) +#define EMB_TMR6_9_PWM_DISABLE (0UL) +#define EMB_TMR6_10_PWM_DISABLE (0UL) + +#define EMB_TMR6_1_PWM_ENABLE (EMB_CTL_PWMSEN0) +#define EMB_TMR6_2_PWM_ENABLE (EMB_CTL_PWMSEN1) +#define EMB_TMR6_3_PWM_ENABLE (EMB_CTL_PWMSEN2) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR6_PWM_Level EMB TMR6 PWM Level + * @{ + */ +#define EMB_DETECT_TMR6_1_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_2_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_3_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_4_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_5_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_6_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_7_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_8_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_9_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_10_PWM_BOTH_LOW (0UL) + +#define EMB_DETECT_TMR6_1_PWM_BOTH_HIGH (EMB_PWMLV_PWMLV0) +#define EMB_DETECT_TMR6_2_PWM_BOTH_HIGH (EMB_PWMLV_PWMLV1) +#define EMB_DETECT_TMR6_3_PWM_BOTH_HIGH (EMB_PWMLV_PWMLV2) +/** + * @} + */ + +/** + * @defgroup EMB_Port_Selection EMB Port Selection + * @{ + */ +#define EMB_PORT1_DISABLE (0UL) +#define EMB_PORT2_DISABLE (0UL) +#define EMB_PORT3_DISABLE (0UL) +#define EMB_PORT4_DISABLE (0UL) +#define EMB_PORT5_DISABLE (0UL) +#define EMB_PORT6_DISABLE (0UL) + +#define EMB_PORT1_ENABLE (EMB_CTL_PORTINEN) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_Port_Level EMB Detect Port Level + * @{ + */ +#define EMB_PORT1_DETECT_LVL_HIGH (0UL) +#define EMB_PORT2_DETECT_LVL_HIGH (0UL) +#define EMB_PORT3_DETECT_LVL_HIGH (0UL) +#define EMB_PORT4_DETECT_LVL_HIGH (0UL) +#define EMB_PORT5_DETECT_LVL_HIGH (0UL) +#define EMB_PORT6_DETECT_LVL_HIGH (0UL) + +#define EMB_PORT1_DETECT_LVL_LOW (EMB_CTL_INVSEL) +/** + * @} + */ + +/** + * @defgroup EMB_Port_Filter_Selection EMB Port Filter Selection + * @{ + */ +#define EMB_PORT1_FILTER_DISABLE (0UL) +#define EMB_PORT2_FILTER_DISABLE (0UL) +#define EMB_PORT3_FILTER_DISABLE (0UL) +#define EMB_PORT4_FILTER_DISABLE (0UL) +#define EMB_PORT5_FILTER_DISABLE (0UL) +#define EMB_PORT6_FILTER_DISABLE (0UL) + +#define EMB_PORT1_FILTER_ENABLE (EMB_CTL_NFEN) +/** + * @} + */ + +/** + * @defgroup EMB_Port_Filter_Clock_Division EMB Port Filter Clock Division + * @{ + */ +#define EMB_PORT1_FILTER_CLK_DIV1 (0UL << EMB_CTL_NFSEL_POS) +#define EMB_PORT1_FILTER_CLK_DIV8 (1UL << EMB_CTL_NFSEL_POS) +#define EMB_PORT1_FILTER_CLK_DIV32 (2UL << EMB_CTL_NFSEL_POS) +#define EMB_PORT1_FILTER_CLK_DIV128 (3UL << EMB_CTL_NFSEL_POS) +/** + * @} + */ + +/** + * @defgroup EMB_Flag_State EMB Flag State + * @{ + */ +#define EMB_FLAG_PWMS (EMB_STAT_PWMSF) +#define EMB_FLAG_CMP (EMB_STAT_CMPF) +#define EMB_FLAG_OSC (EMB_STAT_OSF) +#define EMB_FLAG_PORT1 (EMB_STAT_PORTINF) +#define EMB_STAT_PWMS (EMB_STAT_PWMST) +#define EMB_STAT_PORT1 (EMB_STAT_PORTINST) +#define EMB_FLAG_ALL (EMB_FLAG_PWMS | EMB_FLAG_CMP | EMB_FLAG_OSC | EMB_FLAG_PORT1 | \ + EMB_STAT_PWMS | EMB_STAT_PORT1) +/** + * @} + */ + +/** + * @defgroup EMB_Interrupt EMB Interrupt + * @{ + */ +#define EMB_INT_PWMS (EMB_INTEN_PWMINTEN) +#define EMB_INT_CMP (EMB_INTEN_CMPINTEN) +#define EMB_INT_OSC (EMB_INTEN_OSINTEN) +#define EMB_INT_PORT1 (EMB_INTEN_PORTINTEN) +#define EMB_INT_ALL (EMB_INT_PWMS | EMB_INT_CMP | EMB_INT_OSC | EMB_INT_PORT1) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EMB_Global_Functions + * @{ + */ +int32_t EMB_TMR4_StructInit(stc_emb_tmr4_init_t *pstcEmbInit); +int32_t EMB_TMR4_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr4_init_t *pstcEmbInit); + +int32_t EMB_TMR6_StructInit(stc_emb_tmr6_init_t *pstcEmbInit); +int32_t EMB_TMR6_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr6_init_t *pstcEmbInit); + +void EMB_DeInit(CM_EMB_TypeDef *EMBx); +void EMB_IntCmd(CM_EMB_TypeDef *EMBx, uint32_t u32IntType, en_functional_state_t enNewState); +void EMB_ClearStatus(CM_EMB_TypeDef *EMBx, uint32_t u32Flag); +en_flag_status_t EMB_GetStatus(const CM_EMB_TypeDef *EMBx, uint32_t u32Flag); +void EMB_SWBrake(CM_EMB_TypeDef *EMBx, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_EMB_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_EMB_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_event_port.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_event_port.h new file mode 100644 index 0000000000..55b6b1ae10 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_event_port.h @@ -0,0 +1,233 @@ +/** + ******************************************************************************* + * @file hc32_ll_event_port.h + * @brief This file contains all the functions prototypes of the Event Port + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_EVENT_PORT_H__ +#define __HC32_LL_EVENT_PORT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EVENT_PORT + * @{ + */ + +#if (LL_EVENT_PORT_ENABLE == DDL_ON) +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EP_Global_Types Event Port Global Types + * @{ + */ + +/** + * @brief Event Pin Set and Reset enumeration + */ +typedef enum { + EVT_PIN_RESET = 0U, /*!< Pin reset */ + EVT_PIN_SET = 1U /*!< Pin set */ +} en_ep_state_t; + +typedef struct { + uint32_t u32PinDir; /*!< Input/Output setting, @ref EP_PinDirection_Sel for details */ + en_ep_state_t enPinState; /*!< Corresponding pin initial state, @ref en_ep_state_t for details */ + uint32_t u32PinTriggerOps; /*!< Corresponding pin state after triggered, @ref EP_TriggerOps_Sel for details */ + uint32_t u32Edge; /*!< Event port trigger edge, @ref EP_Trigger_Sel for details */ + uint32_t u32Filter; /*!< Filter clock function setting, @ref EP_FilterClock_Sel for details */ + uint32_t u32FilterClock; /*!< Filter clock, ref@ EP_FilterClock_Div for details */ +} stc_ep_init_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EP_Global_Macros Event Port Global Macros + * @{ + */ + +/** + * @defgroup EP_Port_source EP Port Source + * @{ + */ +#define EVT_PORT_1 (0U) /*!< Event port 1 */ +#define EVT_PORT_2 (1U) /*!< Event port 2 */ +#define EVT_PORT_3 (2U) /*!< Event port 3 */ +#define EVT_PORT_4 (3U) /*!< Event port 4 */ +/** + * @} + */ + +/** + * @defgroup EP_pins_define EP Pin Source + * @{ + */ +#define EVT_PIN_00 (0x0001U) /*!< Event port Pin 00 */ +#define EVT_PIN_01 (0x0002U) /*!< Event port Pin 01 */ +#define EVT_PIN_02 (0x0004U) /*!< Event port Pin 02 */ +#define EVT_PIN_03 (0x0008U) /*!< Event port Pin 03 */ +#define EVT_PIN_04 (0x0010U) /*!< Event port Pin 04 */ +#define EVT_PIN_05 (0x0020U) /*!< Event port Pin 05 */ +#define EVT_PIN_06 (0x0040U) /*!< Event port Pin 06 */ +#define EVT_PIN_07 (0x0080U) /*!< Event port Pin 07 */ +#define EVT_PIN_08 (0x0100U) /*!< Event port Pin 08 */ +#define EVT_PIN_09 (0x0200U) /*!< Event port Pin 09 */ +#define EVT_PIN_10 (0x0400U) /*!< Event port Pin 10 */ +#define EVT_PIN_11 (0x0800U) /*!< Event port Pin 11 */ +#define EVT_PIN_12 (0x1000U) /*!< Event port Pin 12 */ +#define EVT_PIN_13 (0x2000U) /*!< Event port Pin 13 */ +#define EVT_PIN_14 (0x4000U) /*!< Event port Pin 14 */ +#define EVT_PIN_15 (0x8000U) /*!< Event port Pin 15 */ +#define EVT_PIN_All (0xFFFFU) /*!< All event pins are selected */ +#define EVT_PIN_MASK (0xFFFFU) /*!< Event pin mask for assert test */ +/** + * @} + */ + +/** + * @defgroup EP_PinDirection_Sel EP Pin Input/Output Direction Selection + * @{ + */ +#define EP_DIR_IN (0UL) /*!< EP input */ +#define EP_DIR_OUT (1UL) /*!< EP output */ +/** + * @} + */ + +/** + * @defgroup EP_FilterClock_Sel Event Port Filter Function Selection + * @{ + */ +#define EP_FILTER_OFF (0UL) /*!< EP filter function OFF */ + +#define EP_FILTER_ON (1UL) /*!< EP filter function ON */ + +/** + * @} + */ + +/** + * @defgroup EP_FilterClock_Div Event Port Filter Sampling Clock Division Selection + * @{ + */ +#define EP_FCLK_DIV1 (0UL) /*!< PCLK as EP filter clock source */ +#define EP_FCLK_DIV8 (1UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div8 as EP filter clock source */ +#define EP_FCLK_DIV32 (2UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div32 as EP filter clock source */ +#define EP_FCLK_DIV64 (3UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div64 as EP filter clock source */ + +/** + * @} + */ + +/** + * @defgroup EP_Trigger_Sel Event Port Trigger Edge Selection + * @{ + */ +#define EP_TRIG_NONE (0UL) /*!< No Trigger by edge */ +#define EP_TRIG_FALLING (1UL) /*!< Trigger by falling edge */ +#define EP_TRIG_RISING (2UL) /*!< Trigger by rising edge */ +#define EP_TRIG_BOTH (3UL) /*!< Trigger by falling and rising edge */ + +/** + * @} + */ + +/** + * @defgroup EP_TriggerOps_Sel Event Port Operation + * @{ + */ +#define EP_OPS_NONE (0UL) /*!< Pin no action after triggered */ +#define EP_OPS_LOW (1UL) /*!< Pin ouput low after triggered */ +#define EP_OPS_HIGH (2UL) /*!< Pin ouput high after triggered */ +#define EP_OPS_TOGGLE (3UL) /*!< Pin toggle after triggered */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EP_Global_Functions + * @{ + */ +void EP_DeInit(void); +int32_t EP_StructInit(stc_ep_init_t *pstcEventPortInit); + +int32_t EP_Init(uint8_t u8EventPort, uint16_t u16EventPin, const stc_ep_init_t *pstcEventPortInit); +int32_t EP_SetTriggerEdge(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Edge); +int32_t EP_SetTriggerOps(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Ops); +en_ep_state_t EP_ReadInputPins(uint8_t u8EventPort, uint16_t u16EventPin); +uint16_t EP_ReadInputPort(uint8_t u8EventPort); +en_ep_state_t EP_ReadOutputPins(uint8_t u8EventPort, uint16_t u16EventPin); +uint16_t EP_ReadOutputPort(uint8_t u8EventPort); +void EP_SetPins(uint8_t u8EventPort, uint16_t u16EventPin); +void EP_ResetPins(uint8_t u8EventPort, uint16_t u16EventPin); +void EP_SetDir(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Dir); + +/** + * @} + */ + +#endif /* LL_EVENT_PORT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_EVENT_PORT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcg.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcg.h new file mode 100644 index 0000000000..01f8512286 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcg.h @@ -0,0 +1,203 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcg.h + * @brief This file contains all the functions prototypes of the FCG driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_FCG_H__ +#define __HC32_LL_FCG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_FCG + * @{ + */ + +#if (LL_FCG_ENABLE == DDL_ON) +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCG_Global_Macros FCG Global Macros + * @{ + */ +/** + * @defgroup FCG_FCG0_Peripheral FCG FCG0 peripheral + * @{ + */ +#define FCG0_PERIPH_SRAMH (PWC_FCG0_SRAMH) +#define FCG0_PERIPH_SRAM12 (PWC_FCG0_SRAM12) +#define FCG0_PERIPH_SRAM3 (PWC_FCG0_SRAM3) +#define FCG0_PERIPH_SRAMRET (PWC_FCG0_SRAMRET) +#define FCG0_PERIPH_DMA1 (PWC_FCG0_DMA1) +#define FCG0_PERIPH_DMA2 (PWC_FCG0_DMA2) +#define FCG0_PERIPH_FCM (PWC_FCG0_FCM) +#define FCG0_PERIPH_AOS (PWC_FCG0_AOS) +#define FCG0_PERIPH_AES (PWC_FCG0_AES) +#define FCG0_PERIPH_HASH (PWC_FCG0_HASH) +#define FCG0_PERIPH_TRNG (PWC_FCG0_TRNG) +#define FCG0_PERIPH_CRC (PWC_FCG0_CRC) +#define FCG0_PERIPH_DCU1 (PWC_FCG0_DCU1) +#define FCG0_PERIPH_DCU2 (PWC_FCG0_DCU2) +#define FCG0_PERIPH_DCU3 (PWC_FCG0_DCU3) +#define FCG0_PERIPH_DCU4 (PWC_FCG0_DCU4) +#define FCG0_PERIPH_KEY (PWC_FCG0_KEY) +/** + * @} + */ + +/** + * @defgroup FCG_FCG1_Peripheral FCG FCG1 peripheral + * @{ + */ +#define FCG1_PERIPH_CAN (PWC_FCG1_CAN) +#define FCG1_PERIPH_QSPI (PWC_FCG1_QSPI) +#define FCG1_PERIPH_I2C1 (PWC_FCG1_I2C1) +#define FCG1_PERIPH_I2C2 (PWC_FCG1_I2C2) +#define FCG1_PERIPH_I2C3 (PWC_FCG1_I2C3) +#define FCG1_PERIPH_USBFS (PWC_FCG1_USBFS) +#define FCG1_PERIPH_SDIOC1 (PWC_FCG1_SDIOC1) +#define FCG1_PERIPH_SDIOC2 (PWC_FCG1_SDIOC2) +#define FCG1_PERIPH_I2S1 (PWC_FCG1_I2S1) +#define FCG1_PERIPH_I2S2 (PWC_FCG1_I2S2) +#define FCG1_PERIPH_I2S3 (PWC_FCG1_I2S3) +#define FCG1_PERIPH_I2S4 (PWC_FCG1_I2S4) +#define FCG1_PERIPH_SPI1 (PWC_FCG1_SPI1) +#define FCG1_PERIPH_SPI2 (PWC_FCG1_SPI2) +#define FCG1_PERIPH_SPI3 (PWC_FCG1_SPI3) +#define FCG1_PERIPH_SPI4 (PWC_FCG1_SPI4) +#define FCG1_PERIPH_USART1 (PWC_FCG1_USART1) +#define FCG1_PERIPH_USART2 (PWC_FCG1_USART2) +#define FCG1_PERIPH_USART3 (PWC_FCG1_USART3) +#define FCG1_PERIPH_USART4 (PWC_FCG1_USART4) +/** + * @} + */ + +/** + * @defgroup FCG_FCG2_Peripheral FCG FCG2 peripheral + * @{ + */ +#define FCG2_PERIPH_TMR0_1 (PWC_FCG2_TIMER0_1) +#define FCG2_PERIPH_TMR0_2 (PWC_FCG2_TIMER0_2) +#define FCG2_PERIPH_TMRA_1 (PWC_FCG2_TIMERA_1) +#define FCG2_PERIPH_TMRA_2 (PWC_FCG2_TIMERA_2) +#define FCG2_PERIPH_TMRA_3 (PWC_FCG2_TIMERA_3) +#define FCG2_PERIPH_TMRA_4 (PWC_FCG2_TIMERA_4) +#define FCG2_PERIPH_TMRA_5 (PWC_FCG2_TIMERA_5) +#define FCG2_PERIPH_TMRA_6 (PWC_FCG2_TIMERA_6) +#define FCG2_PERIPH_TMR4_1 (PWC_FCG2_TIMER4_1) +#define FCG2_PERIPH_TMR4_2 (PWC_FCG2_TIMER4_2) +#define FCG2_PERIPH_TMR4_3 (PWC_FCG2_TIMER4_3) +#define FCG2_PERIPH_EMB (PWC_FCG2_EMB) +#define FCG2_PERIPH_TMR6_1 (PWC_FCG2_TIMER6_1) +#define FCG2_PERIPH_TMR6_2 (PWC_FCG2_TIMER6_2) +#define FCG2_PERIPH_TMR6_3 (PWC_FCG2_TIMER6_3) +/** + * @} + */ + +/** + * @defgroup FCG_FCG3_Peripheral FCG FCG3 peripheral + * @{ + */ +#define FCG3_PERIPH_ADC1 (PWC_FCG3_ADC1) +#define FCG3_PERIPH_ADC2 (PWC_FCG3_ADC2) +#define FCG3_PERIPH_CMP (PWC_FCG3_CMP) +#define FCG3_PERIPH_OTS (PWC_FCG3_OTS) +/** + * @} + */ + +/** + * @defgroup FCG_FCGx_Peripheral_Mask FCG FCGx Peripheral Mask + * @{ + */ +#define FCG_FCG0_PERIPH_MASK (0x8FF3C511UL) +#define FCG_FCG1_PERIPH_MASK (0x0F0FFD79UL) +#define FCG_FCG2_PERIPH_MASK (0x000787FFUL) +#define FCG_FCG3_PERIPH_MASK (0x00001103UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup FCG_Global_Functions + * @{ + */ + +void FCG_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState); + +void FCG_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState); +void FCG_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState); +void FCG_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_FCG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_FCG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcm.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcm.h new file mode 100644 index 0000000000..a4612cd7d6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcm.h @@ -0,0 +1,292 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcm.h + * @brief This file contains all the functions prototypes of the FCM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_FCM_H__ +#define __HC32_LL_FCM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_FCM + * @{ + */ + +#if (LL_FCM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Types FCM Global Types + * @{ + */ +/** + * @brief FCM Init structure definition + */ +typedef struct { + uint16_t u16LowerLimit; /*!< FCM lower limit value */ + uint16_t u16UpperLimit; /*!< FCM upper limit value */ + uint32_t u32TargetClock; /*!< FCM target clock source selection, @ref FCM_Target_Clock_Src */ + uint32_t u32TargetClockDiv; /*!< FCM target clock source division selection, @ref FCM_Target_Clock_Div */ + uint32_t u32ExtRefClockEnable; /*!< FCM external reference clock function config, @ref FCM_Ext_Ref_Clock_Config */ + uint32_t u32RefClockEdge; /*!< FCM reference clock trigger edge selection, @ref FCM_Ref_Clock_Edge */ + uint32_t u32DigitalFilter; /*!< FCM digital filter function config, @ref FCM_Digital_Filter_Config */ + uint32_t u32RefClock; /*!< FCM reference clock source selection, @ref FCM_Ref_Clock_Src */ + uint32_t u32RefClockDiv; /*!< FCM reference clock source division selection, @ref FCM_Ref_Clock_Div */ + uint32_t u32ExceptionType; /*!< FCM exception type select, @ref FCM_Exception_Type */ +} stc_fcm_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Macros FCM Global Macros + * @{ + */ + +/** + * @defgroup FCM_Target_Clock_Src FCM Target Clock Source + * @{ + */ +#define FCM_TARGET_CLK_XTAL (0x00UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_XTAL32 (0x01UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_HRC (0x02UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_LRC (0x03UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_SWDTLRC (0x04UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_PCLK1 (0x05UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_UPLLP (0x06UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_MRC (0x07UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_MPLLP (0x08UL << FCM_MCCR_MCKS_POS) + +/** + * @} + */ + +/** + * @defgroup FCM_Target_Clock_Div FCM Target Clock Division + * @{ + */ +#define FCM_TARGET_CLK_DIV1 (0x00UL << FCM_MCCR_MDIVS_POS) +#define FCM_TARGET_CLK_DIV4 (0x01UL << FCM_MCCR_MDIVS_POS) +#define FCM_TARGET_CLK_DIV8 (0x02UL << FCM_MCCR_MDIVS_POS) +#define FCM_TARGET_CLK_DIV32 (0x03UL << FCM_MCCR_MDIVS_POS) +/** + * @} + */ + +/** + * @defgroup FCM_Ext_Ref_Clock_Config FCM External Reference Clock Config + * @{ + */ +#define FCM_EXT_REF_OFF (0x00UL) +#define FCM_EXT_REF_ON (FCM_RCCR_EXREFE) +/** + * @} + */ + +/** + * @defgroup FCM_Ref_Clock_Edge FCM Reference Clock Edge + * @{ + */ +#define FCM_REF_CLK_RISING (0x00UL) +#define FCM_REF_CLK_FALLING (FCM_RCCR_EDGES_0) +#define FCM_REF_CLK_BOTH (FCM_RCCR_EDGES_1) +/** + * @} + */ + +/** + * @defgroup FCM_Digital_Filter_Config FCM Digital Filter Config + * @{ + */ +#define FCM_DIG_FILTER_OFF (0x00UL) +#define FCM_DIG_FILTER_DIV1 (FCM_RCCR_DNFS_0) +#define FCM_DIG_FILTER_DIV4 (FCM_RCCR_DNFS_1) +#define FCM_DIG_FILTER_DIV16 (FCM_RCCR_DNFS) +/** + * @} + */ + +/** + * @defgroup FCM_Ref_Clock_Src FCM Feference Clock Source + * @{ + */ +#define FCM_REF_CLK_EXTCLK (0x00UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_XTAL (0x10UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_XTAL32 (0x11UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_HRC (0x12UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_LRC (0x13UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_SWDTLRC (0x14UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_PCLK1 (0x15UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_UPLLP (0x16UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_MRC (0x17UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_MPLLP (0x18UL << FCM_RCCR_RCKS_POS) + +/** + * @} + */ + +/** + * @defgroup FCM_Ref_Clock_Div FCM Reference Clock Division + * @{ + */ +#define FCM_REF_CLK_DIV32 (0x00UL << FCM_RCCR_RDIVS_POS) +#define FCM_REF_CLK_DIV128 (0x01UL << FCM_RCCR_RDIVS_POS) +#define FCM_REF_CLK_DIV1024 (0x02UL << FCM_RCCR_RDIVS_POS) +#define FCM_REF_CLK_DIV8192 (0x03UL << FCM_RCCR_RDIVS_POS) +/** + * @} + */ + +/** + * @defgroup FCM_Abnormal_Reset_Func FCM Abnormal Reset Function Config + * @{ + */ +#define FCM_ERR_RST_OFF (0x00UL) +#define FCM_ERR_RST_ON (FCM_RIER_ERRE) +/** + * @} + */ + +/** + * @defgroup FCM_Exception_Type FCM Exception Type + * @{ + */ +#define FCM_EXP_TYPE_INT (0x00UL) +#define FCM_EXP_TYPE_RST (FCM_RIER_ERRINTRS) +/** + * @} + */ + +/** + * @defgroup FCM_Int_Type FCM Interrupt Type + * @{ + */ +#define FCM_INT_OVF (FCM_RIER_OVFIE) +#define FCM_INT_END (FCM_RIER_MENDIE) +#define FCM_INT_ERR (FCM_RIER_ERRIE) +/** + * @} + */ + +/** + * @defgroup FCM_Flag_Sel FCM Status Flag Selection + * @{ + */ +#define FCM_FLAG_ERR (FCM_SR_ERRF) +#define FCM_FLAG_END (FCM_SR_MENDF) +#define FCM_FLAG_OVF (FCM_SR_OVF) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup FCM_Global_Functions + * @{ + */ + +/** + * @brief Set FCM upper limit value. + * @param u16Limit + * @retval None. + */ +__STATIC_INLINE void FCM_SetUpperLimit(uint16_t u16Limit) +{ + WRITE_REG32(CM_FCM->UVR, u16Limit); +} + +/** + * @brief Set FCM lower limit value. + * @param u16Limit + * @retval None + */ +__STATIC_INLINE void FCM_SetLowerLimit(uint16_t u16Limit) +{ + WRITE_REG32(CM_FCM->LVR, u16Limit); +} + +int32_t FCM_Init(const stc_fcm_init_t *pstcFcmInit); +int32_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit); +void FCM_DeInit(void); +uint16_t FCM_GetCountValue(void); +void FCM_SetUpperLimit(uint16_t u16Limit); +void FCM_SetLowerLimit(uint16_t u16Limit); +void FCM_SetTargetClock(uint32_t u32ClockSrc, uint32_t u32Div); +void FCM_SetRefClock(uint32_t u32ClockSrc, uint32_t u32Div); +en_flag_status_t FCM_GetStatus(uint32_t u32Flag); +void FCM_ClearStatus(uint32_t u32Flag); +void FCM_ResetCmd(en_functional_state_t enNewState); +void FCM_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState); +void FCM_Cmd(en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_FCM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_FCM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_gpio.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_gpio.h new file mode 100644 index 0000000000..2ab386572f --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_gpio.h @@ -0,0 +1,454 @@ +/** + ******************************************************************************* + * @file hc32_ll_gpio.h + * @brief This file contains all the functions prototypes of the GPIO driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_GPIO_H__ +#define __HC32_LL_GPIO_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_GPIO + * @{ + */ + +#if (LL_GPIO_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Types GPIO Global Types + * @{ + */ + +/** + * @brief GPIO Pin Set and Reset enumeration + */ +typedef enum { + PIN_RESET = 0U, /*!< Pin reset */ + PIN_SET = 1U /*!< Pin set */ +} en_pin_state_t; + +/** + * @brief GPIO Init structure definition + */ +typedef struct { + uint16_t u16PinState; /*!< Set pin state to High or Low, @ref GPIO_PinState_Sel for details */ + uint16_t u16PinDir; /*!< Pin mode setting, @ref GPIO_PinDirection_Sel for details */ + uint16_t u16PinOutputType; /*!< Output type setting, @ref GPIO_PinOutType_Sel for details */ + uint16_t u16PinDrv; /*!< Pin drive capacity setting, @ref GPIO_PinDrv_Sel for details */ + uint16_t u16Latch; /*!< Pin latch setting, @ref GPIO_PinLatch_Sel for details */ + uint16_t u16PullUp; /*!< Internal pull-up resistor setting, @ref GPIO_PinPU_Sel for details */ + uint16_t u16Invert; /*!< Pin input/output invert setting, @ref GPIO_PinInvert_Sel */ + uint16_t u16ExtInt; /*!< External interrupt pin setting, @ref GPIO_PinExtInt_Sel for details */ + uint16_t u16PinAttr; /*!< Digital or analog attribute setting, @ref GPIO_PinMode_Sel for details */ +} stc_gpio_init_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Macros GPIO Global Macros + * @{ + */ + +/** + * @defgroup GPIO_Pins_Define GPIO Pin Source + * @{ + */ +#define GPIO_PIN_00 (0x0001U) /*!< Pin 00 selected */ +#define GPIO_PIN_01 (0x0002U) /*!< Pin 01 selected */ +#define GPIO_PIN_02 (0x0004U) /*!< Pin 02 selected */ +#define GPIO_PIN_03 (0x0008U) /*!< Pin 03 selected */ +#define GPIO_PIN_04 (0x0010U) /*!< Pin 04 selected */ +#define GPIO_PIN_05 (0x0020U) /*!< Pin 05 selected */ +#define GPIO_PIN_06 (0x0040U) /*!< Pin 06 selected */ +#define GPIO_PIN_07 (0x0080U) /*!< Pin 07 selected */ + +#define GPIO_PIN_08 (0x0100U) /*!< Pin 08 selected */ +#define GPIO_PIN_09 (0x0200U) /*!< Pin 09 selected */ +#define GPIO_PIN_10 (0x0400U) /*!< Pin 10 selected */ +#define GPIO_PIN_11 (0x0800U) /*!< Pin 11 selected */ +#define GPIO_PIN_12 (0x1000U) /*!< Pin 12 selected */ +#define GPIO_PIN_13 (0x2000U) /*!< Pin 13 selected */ +#define GPIO_PIN_14 (0x4000U) /*!< Pin 14 selected */ +#define GPIO_PIN_15 (0x8000U) /*!< Pin 15 selected */ +#define GPIO_PIN_ALL (0xFFFFU) /*!< All pins selected */ + +/** + * @} + */ + +/** + * @defgroup GPIO_All_Pins_Define GPIO All Pin Definition for Each Product + * @{ + */ +#define GPIO_PIN_A_ALL (0xFFFFU) /*!< Pin A all*/ +#define GPIO_PIN_B_ALL (0xFFFFU) /*!< Pin B all*/ +#define GPIO_PIN_C_ALL (0xFFFFU) /*!< Pin C all*/ +#define GPIO_PIN_D_ALL (0xFFFFU) /*!< Pin D all*/ +#define GPIO_PIN_E_ALL (0xFFFFU) /*!< Pin E all*/ +#define GPIO_PIN_H_ALL (0x0007U) /*!< Pin H all*/ + +/** + * @} + */ + +/** + * @defgroup GPIO_Port_Source GPIO Port Source + * @{ + */ +#define GPIO_PORT_A (0x00U) /*!< Port A selected */ +#define GPIO_PORT_B (0x01U) /*!< Port B selected */ +#define GPIO_PORT_C (0x02U) /*!< Port C selected */ +#define GPIO_PORT_D (0x03U) /*!< Port D selected */ +#define GPIO_PORT_E (0x04U) /*!< Port E selected */ +#define GPIO_PORT_H (0x05U) /*!< Port H selected */ + +/** + * @} + */ + +/** + * @defgroup GPIO_Function_Sel GPIO Function Selection + * @{ + */ +#define GPIO_FUNC_0 (0U) +#define GPIO_FUNC_1 (1U) +#define GPIO_FUNC_2 (2U) +#define GPIO_FUNC_3 (3U) +#define GPIO_FUNC_4 (4U) +#define GPIO_FUNC_5 (5U) +#define GPIO_FUNC_6 (6U) +#define GPIO_FUNC_7 (7U) + +#define GPIO_FUNC_8 (8U) +#define GPIO_FUNC_9 (9U) +#define GPIO_FUNC_10 (10U) +#define GPIO_FUNC_11 (11U) +#define GPIO_FUNC_12 (12U) +#define GPIO_FUNC_13 (13U) +#define GPIO_FUNC_14 (14U) +#define GPIO_FUNC_15 (15U) + +#define GPIO_FUNC_32 (32U) +#define GPIO_FUNC_33 (33U) +#define GPIO_FUNC_34 (34U) +#define GPIO_FUNC_35 (35U) +#define GPIO_FUNC_36 (36U) +#define GPIO_FUNC_37 (37U) +#define GPIO_FUNC_38 (38U) +#define GPIO_FUNC_39 (39U) +#define GPIO_FUNC_40 (40U) +#define GPIO_FUNC_41 (41U) +#define GPIO_FUNC_42 (42U) +#define GPIO_FUNC_43 (43U) +#define GPIO_FUNC_44 (44U) +#define GPIO_FUNC_45 (45U) +#define GPIO_FUNC_46 (46U) +#define GPIO_FUNC_47 (47U) +#define GPIO_FUNC_48 (48U) +#define GPIO_FUNC_49 (49U) +#define GPIO_FUNC_50 (50U) +#define GPIO_FUNC_51 (51U) +#define GPIO_FUNC_52 (52U) +#define GPIO_FUNC_53 (53U) +#define GPIO_FUNC_54 (54U) +#define GPIO_FUNC_55 (55U) +#define GPIO_FUNC_56 (56U) +#define GPIO_FUNC_57 (57U) +#define GPIO_FUNC_58 (58U) +#define GPIO_FUNC_59 (59U) + +/** + * @} + */ + +/** + * @defgroup GPIO_DebugPin_Sel GPIO Debug Pin Selection + * @{ + */ +#define GPIO_PIN_TCK (0x01U) +#define GPIO_PIN_TMS (0x02U) +#define GPIO_PIN_TDO (0x04U) +#define GPIO_PIN_TDI (0x08U) +#define GPIO_PIN_TRST (0x10U) +#define GPIO_PIN_DEBUG_JTAG (0x1FU) + +#define GPIO_PIN_SWCLK (0x01U) +#define GPIO_PIN_SWDIO (0x02U) +#define GPIO_PIN_SWO (0x04U) +#define GPIO_PIN_DEBUG_SWD (0x07U) +#define GPIO_PIN_DEBUG (0x1FU) + +/** + * @} + */ + +/** + * @defgroup GPIO_Hprwm_Pin_Sel GPIO Hrpwm Pin Selection + * @{ + */ +/** + * @} + */ + +/** + * @defgroup GPIO_ReadCycle_Sel GPIO Pin Read Wait Cycle Selection + * @{ + */ +#define GPIO_RD_WAIT0 (0x00U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT1 (0x01U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT2 (0x02U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT3 (0x03U << GPIO_PCCR_RDWT_POS) + +/** + * @} + */ + +/** + * @defgroup GPIO_PinState_Sel GPIO Pin Output State Selection + * @{ + */ +#define PIN_STAT_RST (0U) +#define PIN_STAT_SET (GPIO_PCR_POUT) +/** + * @} + */ + +/** + * @defgroup GPIO_PinDirection_Sel GPIO Pin Input/Output Direction Selection + * @{ + */ +#define PIN_DIR_IN (0U) +#define PIN_DIR_OUT (GPIO_PCR_POUTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinOutType_Sel GPIO Pin Output Type Selection + * @{ + */ +#define PIN_OUT_TYPE_CMOS (0U) +#define PIN_OUT_TYPE_NMOS (GPIO_PCR_NOD) +/** + * @} + */ + +/** + * @defgroup GPIO_PinDrv_Sel GPIO Pin Drive Capacity Selection + * @{ + */ +#define PIN_LOW_DRV (0U) +#define PIN_MID_DRV (GPIO_PCR_DRV_0) +#define PIN_HIGH_DRV (GPIO_PCR_DRV_1) + +/** + * @} + */ + +/** + * @defgroup GPIO_PinLatch_Sel GPIO Pin Output Latch Selection + * @{ + */ +#define PIN_LATCH_OFF (0U) +#define PIN_LATCH_ON (GPIO_PCR_LTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinPU_Sel GPIO Pin Internal Pull-Up Resistor Selection + * @{ + */ +#define PIN_PU_OFF (0U) +#define PIN_PU_ON (GPIO_PCR_PUU) +/** + * @} + */ + +/** + * @defgroup GPIO_PinPD_Sel GPIO Pin Internal Pull-Down Resistor Selection + * @{ + */ +#define PIN_PD_OFF (0U) +#define PIN_PD_ON (GPIO_PCR_PUD) +/** + * @} + */ + +/** + * @defgroup GPIO_PinInputSw_Sel GPIO Pin Input Switch Resistor Selection + * @{ + */ +#define PIN_IN_SW_OFF (0U) +#define PIN_IN_SW_ON (GPIO_PCR_PINAE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinInvert_Sel GPIO Pin I/O Invert Selection + * @{ + */ +#define PIN_INVT_OFF (0U) +#define PIN_INVT_ON (GPIO_PCR_INVE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinExtInt_Sel GPIO Pin External Interrupt Selection + * @{ + */ +#define PIN_EXTINT_OFF (0U) +#define PIN_EXTINT_ON (GPIO_PCR_INTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinMode_Sel GPIO Pin Mode Selection + * @{ + */ +#define PIN_ATTR_DIGITAL (0U) +#define PIN_ATTR_ANALOG (GPIO_PCR_DDIS) +/** + * @} + */ + +/** + * @defgroup GPIO_PinSubFuncSet_Sel GPIO Pin Sub-function Enable or Disable + * @{ + */ +#define PIN_SUBFUNC_DISABLE (0U) +#define PIN_SUBFUNC_ENABLE (GPIO_PFSR_BFE) +/** + * @} + */ + +/** + * @defgroup GPIO_Register_Protect_Key GPIO Registers Protect Key + * @{ + */ +#define GPIO_REG_LOCK_KEY (0xA500U) +#define GPIO_REG_UNLOCK_KEY (0xA501U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup GPIO_Global_Functions + * @{ + */ +/** + * @brief GPIO lock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write disable + * @param None + * @retval None + */ +__STATIC_INLINE void GPIO_REG_Lock(void) +{ + WRITE_REG16(CM_GPIO->PWPR, GPIO_REG_LOCK_KEY); +} + +/** + * @brief GPIO unlock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write enable + * @param None + * @retval None + */ +__STATIC_INLINE void GPIO_REG_Unlock(void) +{ + WRITE_REG16(CM_GPIO->PWPR, GPIO_REG_UNLOCK_KEY); +} + +int32_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit); +void GPIO_DeInit(void); +int32_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit); +void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState); +void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint16_t u16Func); +void GPIO_SubFuncCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState); +void GPIO_SetSubFunc(uint8_t u8Func); +void GPIO_SetReadWaitCycle(uint16_t u16ReadWait); +void GPIO_InputMOSCmd(uint8_t u8Port, en_functional_state_t enNewState); +void GPIO_OutputCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState); +en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin); +uint16_t GPIO_ReadInputPort(uint8_t u8Port); +en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin); +uint16_t GPIO_ReadOutputPort(uint8_t u8Port); +void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin); +void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin); +void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal); +void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin); + +/** + * @} + */ + +#endif /* LL_GPIO_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_GPIO_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_hash.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_hash.h new file mode 100644 index 0000000000..57763de8dc --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_hash.h @@ -0,0 +1,93 @@ +/** + ******************************************************************************* + * @file hc32_ll_hash.h + * @brief This file contains all the functions prototypes of the HASH driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_HASH_H__ +#define __HC32_LL_HASH_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_HASH + * @{ + */ + +#if (LL_HASH_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup HASH_Global_Functions + * @{ + */ + +int32_t HASH_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize, uint8_t *pu8MsgDigest); + +/** + * @} + */ + +#endif /* LL_HASH_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_HASH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2c.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2c.h new file mode 100644 index 0000000000..961719119e --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2c.h @@ -0,0 +1,319 @@ +/** + ******************************************************************************* + * @file hc32_ll_i2c.h + * @brief This file contains all the functions prototypes of the Inter-Integrated + * Circuit(I2C). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_I2C_H__ +#define __HC32_LL_I2C_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_I2C + * @{ + */ + +#if (LL_I2C_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup I2C_Global_Types I2C Global Types + * @{ + */ + +/** + * @brief I2c configuration structure + */ +typedef struct { + uint32_t u32ClockDiv; /*!< I2C clock division for i2c source clock */ + uint32_t u32Baudrate; /*!< I2C baudrate config */ + uint32_t u32SclTime; /*!< The SCL rising and falling time, count of T(i2c source clock after frequency divider) */ +} stc_i2c_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup I2C_Global_Macros I2C Global Macros + * @{ + */ + +/** + * @defgroup I2C_Trans_Dir I2C Transfer Direction + * @{ + */ +#define I2C_DIR_TX (0x0U) +#define I2C_DIR_RX (0x1U) +/** + * @} + */ + +/** + * @defgroup I2C_Addr_Config I2C Address Configurate + * @{ + */ +#define I2C_ADDR_DISABLE (0U) +#define I2C_ADDR_7BIT (I2C_SLR0_SLADDR0EN) +#define I2C_ADDR_10BIT (I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0EN) +/** + * @} + */ + +/** + * @defgroup I2C_Clock_Division I2C Clock Division + * @{ + */ +#define I2C_CLK_DIV1 (0UL) /*!< I2c source clock/1 */ +#define I2C_CLK_DIV2 (1UL) /*!< I2c source clock/2 */ +#define I2C_CLK_DIV4 (2UL) /*!< I2c source clock/4 */ +#define I2C_CLK_DIV8 (3UL) /*!< I2c source clock/8 */ +#define I2C_CLK_DIV16 (4UL) /*!< I2c source clock/16 */ +#define I2C_CLK_DIV32 (5UL) /*!< I2c source clock/32 */ +#define I2C_CLK_DIV64 (6UL) /*!< I2c source clock/64 */ +#define I2C_CLK_DIV128 (7UL) /*!< I2c source clock/128 */ +/** + * @} + */ + +/** + * @defgroup I2C_Address_Num I2C Address Number + * @{ + */ +#define I2C_ADDR0 (0UL) +#define I2C_ADDR1 (1UL) +/** + * @} + */ + +/** + * @defgroup I2C_Ack_Config I2C ACK Configurate + * @{ + */ +#define I2C_ACK (0UL) /*!< Send ACK after date receive */ +#define I2C_NACK (I2C_CR1_ACK) /*!< Send NACK after date received */ +/** + * @} + */ + +/** + * @defgroup I2C_Smbus_Match_Config I2C SMBUS Address Match Configurate + * @{ + */ +#define I2C_SMBUS_MATCH_ALARM (I2C_CR1_SMBALRTEN) +#define I2C_SMBUS_MATCH_DEFAULT (I2C_CR1_SMBDEFAULTEN) +#define I2C_SMBUS_MATCH_HOST (I2C_CR1_SMBHOSTEN) +#define I2C_SMBUS_MATCH_ALL (I2C_CR1_SMBALRTEN | I2C_CR1_SMBDEFAULTEN | I2C_CR1_SMBHOSTEN) +/** + * @} + */ + +/** + * @defgroup I2C_Digital_Filter_Clock I2C Digital Filter Clock + * @{ + */ +#define I2C_DIG_FILTER_CLK_DIV1 (0UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/1 */ +#define I2C_DIG_FILTER_CLK_DIV2 (1UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/2 */ +#define I2C_DIG_FILTER_CLK_DIV3 (2UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/3 */ +#define I2C_DIG_FILTER_CLK_DIV4 (3UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/4 */ +/** + * @} + */ + +/** + * @defgroup I2C_Flag I2C Flag + * @{ + */ +#define I2C_FLAG_START (I2C_SR_STARTF) /*!< Start condition detected */ +#define I2C_FLAG_MATCH_ADDR0 (I2C_SR_SLADDR0F) /*!< Address 0 detected */ +#define I2C_FLAG_MATCH_ADDR1 (I2C_SR_SLADDR1F) /*!< Address 1 detected */ +#define I2C_FLAG_TX_CPLT (I2C_SR_TENDF) /*!< Transfer end */ +#define I2C_FLAG_STOP (I2C_SR_STOPF) /*!< Stop condition detected */ +#define I2C_FLAG_RX_FULL (I2C_SR_RFULLF) /*!< Receive buffer full */ +#define I2C_FLAG_TX_EMPTY (I2C_SR_TEMPTYF) /*!< Transfer buffer empty */ +#define I2C_FLAG_ARBITRATE_FAIL (I2C_SR_ARLOF) /*!< Arbitration fails */ +#define I2C_FLAG_ACKR (I2C_SR_ACKRF) /*!< ACK status */ +#define I2C_FLAG_NACKF (I2C_SR_NACKF) /*!< NACK detected */ +#define I2C_FLAG_TMOUTF (I2C_SR_TMOUTF) /*!< Time out detected */ +#define I2C_FLAG_MASTER (I2C_SR_MSL) /*!< Master mode flag */ +#define I2C_FLAG_BUSY (I2C_SR_BUSY) /*!< Bus busy status */ +#define I2C_FLAG_TRA (I2C_SR_TRA) /*!< Transfer mode flag */ +#define I2C_FLAG_GENERAL_CALL (I2C_SR_GENCALLF) /*!< General call detected */ +#define I2C_FLAG_SMBUS_DEFAULT_MATCH (I2C_SR_SMBDEFAULTF) /*!< SMBUS default address detected */ +#define I2C_FLAG_SMBUS_HOST_MATCH (I2C_SR_SMBHOSTF) /*!< SMBUS host address detected */ +#define I2C_FLAG_SMBUS_ALARM_MATCH (I2C_SR_SMBALRTF) /*!< SMBUS alarm address detected */ + +#define I2C_FLAG_CLR_ALL (I2C_FLAG_START | I2C_FLAG_MATCH_ADDR0 | I2C_FLAG_MATCH_ADDR1 \ + | I2C_FLAG_TX_CPLT | I2C_FLAG_STOP | I2C_FLAG_RX_FULL | I2C_FLAG_TX_EMPTY \ + | I2C_FLAG_ARBITRATE_FAIL | I2C_FLAG_NACKF | I2C_FLAG_TMOUTF \ + | I2C_FLAG_GENERAL_CALL | I2C_FLAG_SMBUS_DEFAULT_MATCH \ + | I2C_FLAG_SMBUS_HOST_MATCH | I2C_FLAG_SMBUS_ALARM_MATCH) +#define I2C_FLAG_ALL (I2C_FLAG_START | I2C_FLAG_MATCH_ADDR0 | I2C_FLAG_MATCH_ADDR1 | I2C_FLAG_TX_CPLT \ + | I2C_FLAG_STOP | I2C_FLAG_RX_FULL | I2C_FLAG_TX_EMPTY | I2C_FLAG_ARBITRATE_FAIL\ + | I2C_FLAG_ACKR | I2C_FLAG_NACKF | I2C_FLAG_TMOUTF | I2C_FLAG_MASTER \ + | I2C_FLAG_BUSY | I2C_FLAG_TRA | I2C_FLAG_GENERAL_CALL \ + | I2C_FLAG_SMBUS_DEFAULT_MATCH | I2C_FLAG_SMBUS_HOST_MATCH \ + | I2C_FLAG_SMBUS_ALARM_MATCH) +/** + * @} + */ + +/** + * @defgroup I2C_Int_Flag I2C Interrupt Flag Bits + * @{ + */ +#define I2C_INT_START (I2C_CR2_STARTIE) +#define I2C_INT_MATCH_ADDR0 (I2C_CR2_SLADDR0IE) +#define I2C_INT_MATCH_ADDR1 (I2C_CR2_SLADDR1IE) +#define I2C_INT_TX_CPLT (I2C_CR2_TENDIE) +#define I2C_INT_STOP (I2C_CR2_STOPIE) +#define I2C_INT_RX_FULL (I2C_CR2_RFULLIE) +#define I2C_INT_TX_EMPTY (I2C_CR2_TEMPTYIE) +#define I2C_INT_ARBITRATE_FAIL (I2C_CR2_ARLOIE) +#define I2C_INT_NACK (I2C_CR2_NACKIE) +#define I2C_INT_TMOUTIE (I2C_CR2_TMOUTIE) +#define I2C_INT_GENERAL_CALL (I2C_CR2_GENCALLIE) +#define I2C_INT_SMBUS_DEFAULT_MATCH (I2C_CR2_SMBDEFAULTIE) +#define I2C_INT_SMBUS_HOST_MATCH (I2C_CR2_SMBHOSTIE) +#define I2C_INT_SMBUS_ALARM_MATCH (I2C_CR2_SMBALRTIE) + +#define I2C_INT_ALL (I2C_INT_START | I2C_INT_MATCH_ADDR0 | I2C_INT_MATCH_ADDR1 | I2C_INT_TX_CPLT \ + | I2C_INT_STOP | I2C_INT_RX_FULL | I2C_INT_TX_EMPTY | I2C_INT_ARBITRATE_FAIL \ + | I2C_INT_NACK | I2C_INT_TMOUTIE | I2C_INT_GENERAL_CALL \ + | I2C_INT_SMBUS_DEFAULT_MATCH | I2C_INT_SMBUS_HOST_MATCH \ + | I2C_INT_SMBUS_ALARM_MATCH) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup I2C_Global_Functions + * @{ + */ + +/* Initialization and Configuration **********************************/ +int32_t I2C_StructInit(stc_i2c_init_t *pstcI2cInit); +int32_t I2C_BaudrateConfig(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error); +void I2C_DeInit(CM_I2C_TypeDef *I2Cx); +int32_t I2C_Init(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error); +void I2C_SlaveAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr); +void I2C_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_FastAckCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_BusWaitCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_SmbusConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState); +void I2C_SmbusCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_DigitalFilterConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32FilterClock); +void I2C_DigitalFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_AnalogFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_GeneralCallCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_SWResetCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_IntCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32IntType, en_functional_state_t enNewState); + +/* Start/Restart/Stop ************************************************/ +void I2C_GenerateStart(CM_I2C_TypeDef *I2Cx); +void I2C_GenerateRestart(CM_I2C_TypeDef *I2Cx); +void I2C_GenerateStop(CM_I2C_TypeDef *I2Cx); + +/* Status management *************************************************/ +en_flag_status_t I2C_GetStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag); +void I2C_ClearStatus(CM_I2C_TypeDef *I2Cx, uint32_t u32Flag); + +/* Data transfer ************************************ ***************/ +void I2C_WriteData(CM_I2C_TypeDef *I2Cx, uint8_t u8Data); +uint8_t I2C_ReadData(const CM_I2C_TypeDef *I2Cx); +void I2C_AckConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AckConfig); + +/* Time out function *************************************************/ +void I2C_SCLHighTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutH); +void I2C_SCLLowTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutL); +void I2C_SCLHighTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_SCLLowTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_SCLTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +/* High level functions for reference ********************************/ +int32_t I2C_Start(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout); +int32_t I2C_Restart(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout); +int32_t I2C_TransAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout); +int32_t I2C_Trans10BitAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout); +int32_t I2C_TransData(CM_I2C_TypeDef *I2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout); +int32_t I2C_ReceiveData(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); +int32_t I2C_MasterReceiveDataAndStop(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); +int32_t I2C_Stop(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout); +int32_t I2C_WaitStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout); + +/** + * @} + */ + +#endif /* LL_I2C_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_I2C_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2s.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2s.h new file mode 100644 index 0000000000..2ff44d175f --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2s.h @@ -0,0 +1,342 @@ +/** + ******************************************************************************* + * @file hc32_ll_i2s.h + * @brief This file contains all the functions prototypes of the I2S driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_I2S_H__ +#define __HC32_LL_I2S_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_I2S + * @{ + */ + +#if (LL_I2S_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup I2S_Global_Types I2S Global Types + * @{ + */ + +/** + * @brief I2S Init structure definition + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Specifies the clock source of I2S. + This parameter can be a value of @ref I2S_Clock_Source */ + uint32_t u32Mode; /*!< Specifies the master/slave mode of I2S. + This parameter can be a value of @ref I2S_Mode */ + uint32_t u32Protocol; /*!< Specifies the communication protocol of I2S. + This parameter can be a value of @ref I2S_Protocol */ + uint32_t u32TransMode; /*!< Specifies the transmission mode for the I2S communication. + This parameter can be a value of @ref I2S_Trans_Mode */ + uint32_t u32AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + uint32_t u32ChWidth; /*!< Specifies the channel length for the I2S communication. + This parameter can be a value of @ref I2S_Channel_Length */ + uint32_t u32DataWidth; /*!< Specifies the data length for the I2S communication. + This parameter can be a value of @ref I2S_Data_Length */ + uint32_t u32MCKOutput; /*!< Specifies the validity of the MCK output for I2S. + This parameter can be a value of @ref I2S_MCK_Output */ + uint32_t u32TransFIFOLevel; /*!< Specifies the level of transfer FIFO. + This parameter can be a value of @ref I2S_Trans_Level */ + uint32_t u32ReceiveFIFOLevel; /*!< Specifies the level of receive FIFO. + This parameter can be a value of @ref I2S_Receive_Level */ +} stc_i2s_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup I2S_Global_Macros I2S Global Macros + * @{ + */ + +/** + * @defgroup I2S_External_Clock_Frequency I2S External Clock Frequency + * @{ + */ +#ifndef I2S_EXT_CLK_FREQ +#define I2S_EXT_CLK_FREQ (12288000UL) /*!< Value of the external oscillator */ +#endif /* I2S_EXT_CLK_FREQ */ +/** + * @} + */ + +/** + * @defgroup I2S_Clock_Source I2S Clock Source + * @{ + */ +#define I2S_CLK_SRC_PLL (I2S_CTRL_I2SPLLSEL) /*!< Internal PLL Clock */ +#define I2S_CLK_SRC_EXT (I2S_CTRL_CLKSEL) /*!< External Clock */ +/** + * @} + */ + +/** + * @defgroup I2S_Mode I2S Mode + * @{ + */ +#define I2S_MD_MASTER (0UL) /*!< Master mode */ +#define I2S_MD_SLAVE (I2S_CTRL_WMS) /*!< Slave mode */ +/** + * @} + */ + +/** + * @defgroup I2S_Protocol I2S Communication Protocol + * @{ + */ +#define I2S_PROTOCOL_PHILLIPS (0UL) /*!< Phillips protocol */ +#define I2S_PROTOCOL_MSB (I2S_CFGR_I2SSTD_0) /*!< MSB justified protocol */ +#define I2S_PROTOCOL_LSB (I2S_CFGR_I2SSTD_1) /*!< LSB justified protocol */ +#define I2S_PROTOCOL_PCM_SHORT (I2S_CFGR_I2SSTD) /*!< PCM short-frame protocol */ +#define I2S_PROTOCOL_PCM_LONG (I2S_CFGR_I2SSTD | I2S_CFGR_PCMSYNC) /*!< PCM long-frame protocol */ +/** + * @} + */ + +/** + * @defgroup I2S_Trans_Mode I2S Transfer Mode + * @{ + */ +#define I2S_TRANS_MD_HALF_DUPLEX_RX (0UL) /*!< Receive only and half duplex mode */ +#define I2S_TRANS_MD_HALF_DUPLEX_TX (I2S_CTRL_SDOE) /*!< Send only and half duplex mode */ +#define I2S_TRANS_MD_FULL_DUPLEX (I2S_CTRL_DUPLEX | I2S_CTRL_SDOE) /*!< Full duplex mode */ +/** + * @} + */ + +/** + * @defgroup I2S_Audio_Frequency I2S Audio Frequency + * @{ + */ +#define I2S_AUDIO_FREQ_192K (192000UL) /*!< FS = 192000Hz */ +#define I2S_AUDIO_FREQ_96K (96000UL) /*!< FS = 96000Hz */ +#define I2S_AUDIO_FREQ_48K (48000UL) /*!< FS = 48000Hz */ +#define I2S_AUDIO_FREQ_44K (44100UL) /*!< FS = 44100Hz */ +#define I2S_AUDIO_FREQ_32K (32000UL) /*!< FS = 32000Hz */ +#define I2S_AUDIO_FREQ_22K (22050UL) /*!< FS = 22050Hz */ +#define I2S_AUDIO_FREQ_16K (16000UL) /*!< FS = 16000Hz */ +#define I2S_AUDIO_FREQ_8K (8000UL) /*!< FS = 8000Hz */ +#define I2S_AUDIO_FREQ_DEFAULT (2UL) +/** + * @} + */ + +/** + * @defgroup I2S_Channel_Length I2S Channel Length + * @{ + */ +#define I2S_CH_LEN_16BIT (0UL) /*!< Channel length is 16bits */ +#define I2S_CH_LEN_32BIT (I2S_CFGR_CHLEN) /*!< Channel length is 32bits */ +/** + * @} + */ + +/** + * @defgroup I2S_Data_Length I2S Data Length + * @{ + */ +#define I2S_DATA_LEN_16BIT (0UL) /*!< Transfer data length is 16bits */ +#define I2S_DATA_LEN_24BIT (I2S_CFGR_DATLEN_0) /*!< Transfer data length is 24bits */ +#define I2S_DATA_LEN_32BIT (I2S_CFGR_DATLEN_1) /*!< Transfer data length is 32bits */ +/** + * @} + */ + +/** + * @defgroup I2S_MCK_Output I2S MCK Output + * @{ + */ +#define I2S_MCK_OUTPUT_DISABLE (0UL) /*!< Disable the drive clock(MCK) output */ +#define I2S_MCK_OUTPUT_ENABLE (I2S_CTRL_MCKOE) /*!< Enable the drive clock(MCK) output */ +/** + * @} + */ + +/** + * @defgroup I2S_Trans_Level I2S Transfer Level + * @{ + */ +#define I2S_TRANS_LVL0 (0x00UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 0 */ +#define I2S_TRANS_LVL1 (0x01UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 1 */ +#define I2S_TRANS_LVL2 (0x02UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 2 */ + +/** + * @} + */ + +/** + * @defgroup I2S_Receive_Level I2S Receive Level + * @{ + */ +#define I2S_RECEIVE_LVL0 (0x00UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 0 */ +#define I2S_RECEIVE_LVL1 (0x01UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 1 */ +#define I2S_RECEIVE_LVL2 (0x02UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 2 */ + +/** + * @} + */ + +/** + * @defgroup I2S_Com_Func I2S Communication Function + * @{ + */ +#define I2S_FUNC_TX (I2S_CTRL_TXE) /*!< Transfer function */ +#define I2S_FUNC_RX (I2S_CTRL_RXE) /*!< Receive function */ +#define I2S_FUNC_ALL (I2S_FUNC_TX | I2S_FUNC_RX) +/** + * @} + */ + +/** + * @defgroup I2S_Reset_Type I2S Reset Type + * @{ + */ +#define I2S_RST_TYPE_CODEC (I2S_CTRL_CODECRC) /*!< Reset codec of I2S */ +#define I2S_RST_TYPE_FIFO (I2S_CTRL_FIFOR) /*!< Reset FIFO of I2S */ + +#define I2S_RST_TYPE_ALL (I2S_RST_TYPE_CODEC | I2S_RST_TYPE_FIFO) +/** + * @} + */ + +/** + * @defgroup I2S_Interrupt I2S Interrupt + * @{ + */ +#define I2S_INT_TX (I2S_CTRL_TXIE) /*!< Transfer interrupt */ +#define I2S_INT_RX (I2S_CTRL_RXIE) /*!< Receive interrupt */ +#define I2S_INT_ERR (I2S_CTRL_EIE) /*!< Communication error interrupt */ +#define I2S_INT_ALL (I2S_INT_TX | I2S_INT_RX | I2S_INT_ERR) +/** + * @} + */ + +/** + * @defgroup I2S_Flag I2S Flag + * @{ + */ +#define I2S_FLAG_TX_ALARM (I2S_SR_TXBA) /*!< Transfer buffer alarm flag */ +#define I2S_FLAG_RX_ALARM (I2S_SR_RXBA) /*!< Receive buffer alarm flag */ +#define I2S_FLAG_TX_EMPTY (I2S_SR_TXBE) /*!< Transfer buffer empty flag */ +#define I2S_FLAG_TX_FULL (I2S_SR_TXBF) /*!< Transfer buffer full flag */ +#define I2S_FLAG_RX_EMPTY (I2S_SR_RXBE) /*!< Receive buffer empty flag */ +#define I2S_FLAG_RX_FULL (I2S_SR_RXBF) /*!< Receive buffer full flag */ +#define I2S_FLAG_TX_ERR (I2S_ER_TXERR << 16U) /*!< Transfer overflow or underflow flag */ +#define I2S_FLAG_RX_ERR (I2S_ER_RXERR << 16U) /*!< Receive overflow flag */ +#define I2S_FLAG_ALL (I2S_FLAG_TX_ALARM | I2S_FLAG_RX_ALARM | I2S_FLAG_TX_EMPTY | \ + I2S_FLAG_TX_FULL | I2S_FLAG_RX_EMPTY | I2S_FLAG_RX_FULL | \ + I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR) +#define I2S_FLAG_CLR_ALL (I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup I2S_Global_Functions + * @{ + */ + +/* Initialization and configuration functions */ +void I2S_DeInit(CM_I2S_TypeDef *I2Sx); +int32_t I2S_Init(CM_I2S_TypeDef *I2Sx, const stc_i2s_init_t *pstcI2sInit); +int32_t I2S_StructInit(stc_i2s_init_t *pstcI2sInit); +void I2S_SWReset(CM_I2S_TypeDef *I2Sx, uint32_t u32Type); +void I2S_SetTransMode(CM_I2S_TypeDef *I2Sx, uint32_t u32Mode); +void I2S_SetTransFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level); +void I2S_SetReceiveFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level); +void I2S_SetProtocol(CM_I2S_TypeDef *I2Sx, uint32_t u32Protocol); +int32_t I2S_SetAudioFreq(CM_I2S_TypeDef *I2Sx, uint32_t u32Freq); +void I2S_MCKOutputCmd(CM_I2S_TypeDef *I2Sx, en_functional_state_t enNewState); +void I2S_FuncCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32Func, en_functional_state_t enNewState); + +/* Transfer and receive data functions */ +void I2S_WriteData(CM_I2S_TypeDef *I2Sx, uint32_t u32Data); +uint32_t I2S_ReadData(const CM_I2S_TypeDef *I2Sx); +int32_t I2S_Trans(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout); +int32_t I2S_Receive(const CM_I2S_TypeDef *I2Sx, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout); +int32_t I2S_TransReceive(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf, + void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout); + +/* Interrupt and flag management functions */ +void I2S_IntCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t I2S_GetStatus(const CM_I2S_TypeDef *I2Sx, uint32_t u32Flag); +void I2S_ClearStatus(CM_I2S_TypeDef *I2Sx, uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_I2S_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_I2S_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_icg.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_icg.h new file mode 100644 index 0000000000..43026f50bb --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_icg.h @@ -0,0 +1,488 @@ +/** + ******************************************************************************* + * @file hc32_ll_icg.h + * @brief This file contains all the Macro Definitions of the ICG driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_ICG_H__ +#define __HC32_LL_ICG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_ICG + * @{ + */ + +#if (LL_ICG_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ICG_Global_Macros ICG Global Macros + * @{ + */ + +/** + * @defgroup ICG_SWDT_Reset_State ICG SWDT Reset State + * @{ + */ +#define ICG_SWDT_RST_START (0UL) /*!< SWDT auto start after reset */ +#define ICG_SWDT_RST_STOP (ICG_ICG0_SWDTAUTS) /*!< SWDT stop after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Exception_Type ICG SWDT Exception Type + * @{ + */ +#define ICG_SWDT_EXP_TYPE_INT (0UL) /*!< SWDT trigger interrupt */ +#define ICG_SWDT_EXP_TYPE_RST (ICG_ICG0_SWDTITS) /*!< SWDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Count_Period ICG SWDT Count Period + * @{ + */ +#define ICG_SWDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */ +#define ICG_SWDT_CNT_PERIOD4096 (ICG_ICG0_SWDTPERI_0) /*!< 4096 clock cycle */ +#define ICG_SWDT_CNT_PERIOD16384 (ICG_ICG0_SWDTPERI_1) /*!< 16384 clock cycle */ +#define ICG_SWDT_CNT_PERIOD65536 (ICG_ICG0_SWDTPERI) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Clock_Division ICG SWDT Clock Division + * @{ + */ +#define ICG_SWDT_CLK_DIV1 (0UL) /*!< CLK */ +#define ICG_SWDT_CLK_DIV16 (0x04UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/16 */ +#define ICG_SWDT_CLK_DIV32 (0x05UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/32 */ +#define ICG_SWDT_CLK_DIV64 (0x06UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/64 */ +#define ICG_SWDT_CLK_DIV128 (0x07UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/128 */ +#define ICG_SWDT_CLK_DIV256 (0x08UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/256 */ +#define ICG_SWDT_CLK_DIV2048 (0x0BUL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/2048 */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Refresh_Range ICG SWDT Refresh Range + * @{ + */ +#define ICG_SWDT_RANGE_0TO25PCT (0x01UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% */ +#define ICG_SWDT_RANGE_25TO50PCT (0x02UL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~50% */ +#define ICG_SWDT_RANGE_0TO50PCT (0x03UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~50% */ +#define ICG_SWDT_RANGE_50TO75PCT (0x04UL << ICG_ICG0_SWDTWDPT_POS) /*!< 50%~75% */ +#define ICG_SWDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 50%~75% */ +#define ICG_SWDT_RANGE_25TO75PCT (0x06UL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~75% */ +#define ICG_SWDT_RANGE_0TO75PCT (0x07UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~75% */ +#define ICG_SWDT_RANGE_75TO100PCT (0x08UL << ICG_ICG0_SWDTWDPT_POS) /*!< 75%~100% */ +#define ICG_SWDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 75%~100% */ +#define ICG_SWDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~50% & 75%~100% */ +#define ICG_SWDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~50% & 75%~100% */ +#define ICG_SWDT_RANGE_50TO100PCT (0x0CUL << ICG_ICG0_SWDTWDPT_POS) /*!< 50%~100% */ +#define ICG_SWDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 50%~100% */ +#define ICG_SWDT_RANGE_25TO100PCT (0x0EUL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~100% */ +#define ICG_SWDT_RANGE_0TO100PCT (0x0FUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~100% */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_LPM_Count ICG SWDT Low Power Mode Count + * @brief Counting control of SWDT in sleep/stop mode + * @{ + */ +#define ICG_SWDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep/stop mode */ +#define ICG_SWDT_LPM_CNT_STOP (ICG_ICG0_SWDTSLPOFF) /*!< Stop counting in sleep/stop mode */ +/** + * @} + */ + +/* WDT function */ +/** + * @defgroup ICG_WDT_Reset_State ICG WDT Reset State + * @{ + */ +#define ICG_WDT_RST_START (0UL) /*!< WDT auto start after reset */ +#define ICG_WDT_RST_STOP (ICG_ICG0_WDTAUTS) /*!< WDT stop after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Exception_Type ICG WDT Exception Type + * @{ + */ +#define ICG_WDT_EXP_TYPE_INT (0UL) /*!< WDT trigger interrupt */ +#define ICG_WDT_EXP_TYPE_RST (ICG_ICG0_WDTITS) /*!< WDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Count_Period ICG WDT Count Period + * @{ + */ +#define REDEF_ICG_WDTPERI_POS ICG_ICG0_WDTPERI_POS + +#define ICG_WDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */ +#define ICG_WDT_CNT_PERIOD4096 (0x01UL << REDEF_ICG_WDTPERI_POS) /*!< 4096 clock cycle */ +#define ICG_WDT_CNT_PERIOD16384 (0x02UL << REDEF_ICG_WDTPERI_POS) /*!< 16384 clock cycle */ +#define ICG_WDT_CNT_PERIOD65536 (0x03UL << REDEF_ICG_WDTPERI_POS) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Clock_Division ICG WDT Clock Division + * @{ + */ +#define REDEF_ICG_WDTCKS_POS ICG_ICG0_WDTCKS_POS + +#define ICG_WDT_CLK_DIV4 (0x02UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/4 */ +#define ICG_WDT_CLK_DIV64 (0x06UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/64 */ +#define ICG_WDT_CLK_DIV128 (0x07UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/128 */ +#define ICG_WDT_CLK_DIV256 (0x08UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/256 */ +#define ICG_WDT_CLK_DIV512 (0x09UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/512 */ +#define ICG_WDT_CLK_DIV1024 (0x0AUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/1024 */ +#define ICG_WDT_CLK_DIV2048 (0x0BUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/2048 */ +#define ICG_WDT_CLK_DIV8192 (0x0DUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/8192 */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Refresh_Range ICG WDT Refresh Range + * @{ + */ +#define REDEF_ICG_WDTWDPT_POS ICG_ICG0_WDTWDPT_POS + +#define ICG_WDT_RANGE_0TO25PCT (0x01UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% */ +#define ICG_WDT_RANGE_25TO50PCT (0x02UL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~50% */ +#define ICG_WDT_RANGE_0TO50PCT (0x03UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~50% */ +#define ICG_WDT_RANGE_50TO75PCT (0x04UL << REDEF_ICG_WDTWDPT_POS) /*!< 50%~75% */ +#define ICG_WDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 50%~75% */ +#define ICG_WDT_RANGE_25TO75PCT (0x06UL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~75% */ +#define ICG_WDT_RANGE_0TO75PCT (0x07UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~75% */ +#define ICG_WDT_RANGE_75TO100PCT (0x08UL << REDEF_ICG_WDTWDPT_POS) /*!< 75%~100% */ +#define ICG_WDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 75%~100% */ +#define ICG_WDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~50% & 75%~100% */ +#define ICG_WDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~50% & 75%~100% */ +#define ICG_WDT_RANGE_50TO100PCT (0x0CUL << REDEF_ICG_WDTWDPT_POS) /*!< 50%~100% */ +#define ICG_WDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 50%~100% */ +#define ICG_WDT_RANGE_25TO100PCT (0x0EUL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~100% */ +#define ICG_WDT_RANGE_0TO100PCT (0x0FUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~100% */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_LPM_Count ICG WDT Low Power Mode Count + * @brief Counting control of WDT in sleep mode + * @{ + */ +#define ICG_WDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep mode */ +#define ICG_WDT_LPM_CNT_STOP (ICG_ICG0_WDTSLPOFF) /*!< Stop counting in sleep mode */ +/** + * @} + */ + +/* NMI Pin function */ +/** + * @defgroup ICG_NMI_Pin_Filter_Clock_Division ICG NMI Pin Filter Clock Division + * @{ + */ +#define REDEF_ICG_NMIFCLK_POS ICG_ICG1_SMPCLK_POS + +#define ICG_NMI_PIN_FILTER_CLK_DIV1 (0UL) /*!< CLK */ +#define ICG_NMI_PIN_FILTER_CLK_DIV8 (0x01UL << REDEF_ICG_NMIFCLK_POS) /*!< CLK/8 */ +#define ICG_NMI_PIN_FILTER_CLK_DIV32 (0x02UL << REDEF_ICG_NMIFCLK_POS) /*!< CLK/32 */ +#define ICG_NMI_PIN_FILTER_CLK_DIV64 (0x03UL << REDEF_ICG_NMIFCLK_POS) /*!< CLK/64 */ +/** + * @} + */ + +/** + * @defgroup ICG_NMI_Pin_Filter ICG NMI Pin Filter + * @{ + */ +#define ICG_NMI_PIN_FILTER_DISABLE (0UL) /*!< Disable NMI Pin filter */ +#define ICG_NMI_PIN_FILTER_ENABLE (ICG_ICG1_NFEN) /*!< Enable NMI Pin filter */ +/** + * @} + */ + +/** + * @defgroup ICG_NMI_Pin_Trigger_Edge ICG NMI Pin Trigger Edge + * @{ + */ +#define ICG_NMI_PIN_TRIG_EDGE_FALLING (0UL) /*!< Falling edge trigger */ +#define ICG_NMI_PIN_TRIG_EDGE_RISING (ICG_ICG1_NMITRG) /*!< Rising edge trigger */ +/** + * @} + */ + +/** + * @defgroup ICG_NMI_Pin_Interrupt ICG NMI Pin Interrupt + * @{ + */ +#define ICG_NMI_PIN_INT_DISABLE (0UL) /*!< Disable NMI pin interrupt */ +#define ICG_NMI_PIN_INT_ENABLE (ICG_ICG1_NMIEN) /*!< Enable NMI pin interrupt */ +/** + * @} + */ + +/** + * @defgroup ICG_NMI_Pin_Reset_State ICG NMI Pin Reset State + * @{ + */ +#define ICG_NMI_PIN_RST_ENABLE (0UL) /*!< Enable NMI pin after reset */ +#define ICG_NMI_PIN_RST_DISABLE (ICG_ICG1_NMIICGEN) /*!< Disable NMI pin after reset */ +/** + * @} + */ + +/* BOR function */ +/** + * @defgroup ICG_BOR_Voltage_Threshold ICG BOR Voltage Threshold + * @{ + */ +#define ICG_BOR_VOL_THRESHOLD_LVL0 (0UL) /*!< BOR voltage threshold 1.9V */ +#define ICG_BOR_VOL_THRESHOLD_LVL1 (ICG_ICG1_BOR_LEV_0) /*!< BOR voltage threshold 2.0V */ +#define ICG_BOR_VOL_THRESHOLD_LVL2 (ICG_ICG1_BOR_LEV_1) /*!< BOR voltage threshold 2.1V */ +#define ICG_BOR_VOL_THRESHOLD_LVL3 (ICG_ICG1_BOR_LEV) /*!< BOR voltage threshold 2.3V */ +/** + * @} + */ + +/** + * @defgroup ICG_BOR_Reset_State ICG BOR Reset State + * @{ + */ +#define ICG_BOR_RST_ENABLE (0UL) /*!< Enable BOR voltage detection after reset */ +#define ICG_BOR_RST_DISABLE (ICG_ICG1_BORDIS) /*!< Disable BOR voltage detection after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_HRC_Frequency_Select ICG HRC Frequency Select + * @{ + */ + +#define ICG_HRC_20M (0UL) /*!< HRC = 20MHZ */ +#define ICG_HRC_16M (ICG_ICG1_HRCFREQSEL) /*!< HRC = 16MHZ */ +/** + * @} + */ + +/** + * @defgroup ICG_HRC_Reset_State ICG HRC Reset State + * @{ + */ +#define ICG_HRC_RST_OSCILLATION (0UL) /*!< HRC Oscillation after reset */ +#define ICG_HRC_RST_STOP (ICG_ICG1_HRCSTOP) /*!< HRC stop after reset */ +/** + * @} + */ + +/* LVD function */ + +/* Core lockup function */ + +/* Flash function */ + +/** + * @} + */ + +/** + * @defgroup ICG_Register_Configuration ICG Register Configuration + * @{ + */ + +/** + ******************************************************************************* + * @defgroup ICG_SWDT_Preload_Configuration ICG SWDT Preload Configuration + * @{ + ******************************************************************************* + */ +/* SWDT register config */ +#define ICG_RB_SWDT_AUTS (ICG_SWDT_RST_STOP) +#define ICG_RB_SWDT_ITS (ICG_SWDT_EXP_TYPE_RST) +#define ICG_RB_SWDT_PERI (ICG_SWDT_CNT_PERIOD65536) +#define ICG_RB_SWDT_CKS (ICG_SWDT_CLK_DIV2048) +#define ICG_RB_SWDT_WDPT (ICG_SWDT_RANGE_0TO100PCT) +#define ICG_RB_SWDT_SLTPOFF (ICG_SWDT_LPM_CNT_STOP) + +/* SWDT register value */ +#define ICG_REG_SWDT_CONFIG (ICG_RB_SWDT_AUTS | ICG_RB_SWDT_ITS | ICG_RB_SWDT_PERI | \ + ICG_RB_SWDT_CKS | ICG_RB_SWDT_WDPT | ICG_RB_SWDT_SLTPOFF) +/** + * @} + */ + +/** + ******************************************************************************* + * @defgroup ICG_WDT_Preload_Configuration ICG WDT Preload Configuration + * @{ + ******************************************************************************* + */ +/* WDT register config */ +#define ICG_RB_WDT_AUTS (ICG_WDT_RST_STOP) +#define ICG_RB_WDT_ITS (ICG_WDT_EXP_TYPE_RST) +#define ICG_RB_WDT_PERI (ICG_WDT_CNT_PERIOD65536) +#define ICG_RB_WDT_CKS (ICG_WDT_CLK_DIV8192) +#define ICG_RB_WDT_WDPT (ICG_WDT_RANGE_0TO100PCT) +#define ICG_RB_WDT_SLTPOFF (ICG_WDT_LPM_CNT_STOP) + +/* WDT register value */ +#define ICG_REG_WDT_CONFIG (ICG_RB_WDT_AUTS | ICG_RB_WDT_ITS | ICG_RB_WDT_PERI | \ + ICG_RB_WDT_CKS | ICG_RB_WDT_WDPT | ICG_RB_WDT_SLTPOFF) +/** + * @} + */ + +/** + ******************************************************************************* + * @defgroup ICG_NMI_Pin_Preload_Configuration ICG NMI Pin Preload Configuration + * @{ + ******************************************************************************* + */ +/* NMI register config */ +#define ICG_RB_NMI_FCLK (ICG_NMI_PIN_FILTER_CLK_DIV64) +#define ICG_RB_NMI_FEN (ICG_NMI_PIN_FILTER_ENABLE) +#define ICG_RB_NMI_TRG (ICG_NMI_PIN_TRIG_EDGE_RISING) +#define ICG_RB_NMI_EN (ICG_NMI_PIN_INT_ENABLE) +#define ICG_RB_NMI_ICGEN (ICG_NMI_PIN_RST_DISABLE) + +/* NMI register value */ +#define ICG_REG_NMI_CONFIG (ICG_RB_NMI_FCLK | ICG_RB_NMI_FEN | ICG_RB_NMI_TRG | \ + ICG_RB_NMI_EN | ICG_RB_NMI_ICGEN) +/** + * @} + */ + +/** + ******************************************************************************* + * @defgroup ICG_BOR_Preload_Configuration ICG BOR Preload Configuration + * @{ + ******************************************************************************* + */ +/* BOR register config */ +#define ICG_RB_BOR_LEV (ICG_BOR_VOL_THRESHOLD_LVL3) +#define ICG_RB_BOR_DIS (ICG_BOR_RST_DISABLE) + +/* BOR register value */ +#define ICG_REG_BOR_CONFIG (ICG_RB_BOR_LEV | ICG_RB_BOR_DIS) +/** + * @} + */ + +/** + ******************************************************************************* + * @defgroup ICG_HRC_Preload_Configuration ICG HRC Preload Configuration + * @{ + ******************************************************************************* + */ +/* HRC register config */ +#define ICG_RB_HRC_FREQSEL (ICG_HRC_16M) +#define ICG_RB_HRC_STOP (ICG_HRC_RST_OSCILLATION) + +/* HRC register value */ +#define ICG_REG_HRC_CONFIG (ICG_RB_HRC_FREQSEL | ICG_RB_HRC_STOP) +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup ICG_Register_Value ICG Register Value + * @{ + */ +/* ICG register value */ +#ifndef ICG_REG_CFG0_CONST +#define ICG_REG_CFG0_CONST (ICG_REG_WDT_CONFIG | ICG_REG_SWDT_CONFIG | 0xE000E000UL) +#endif +#ifndef ICG_REG_CFG1_CONST +#define ICG_REG_CFG1_CONST (ICG_REG_NMI_CONFIG | ICG_REG_BOR_CONFIG | ICG_REG_HRC_CONFIG | 0x03F8FEFEUL) +#endif +/* ICG reserved value */ +#define ICG_REG_RESV_CONST (0xFFFFFFFFUL) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +#endif /* LL_ICG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_ICG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_interrupts.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_interrupts.h new file mode 100644 index 0000000000..9c099df5b8 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_interrupts.h @@ -0,0 +1,602 @@ +/** + ******************************************************************************* + * @file hc32_ll_interrupts.h + * @brief This file contains all the functions prototypes of the interrupt driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_INTERRUPTS_H__ +#define __HC32_LL_INTERRUPTS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_INTERRUPTS + * @{ + */ + +#if (LL_INTERRUPTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Types INTC Global Types + * @{ + */ + +/** + * @brief Interrupt registration structure definition + */ +typedef struct { + en_int_src_t enIntSrc; /*!< Peripheral interrupt number, can be any value @ref en_int_src_t */ + IRQn_Type enIRQn; /*!< Peripheral IRQ type, can be INT000_IRQn~INT127_IRQn @ref IRQn_Type */ + func_ptr_t pfnCallback; /*!< Callback function for corresponding peripheral IRQ */ +} stc_irq_signin_config_t; + +/** + * @brief NMI initialize configuration structure definition + */ +typedef struct { + uint32_t u32Src; /*!< NMI trigger source, @ref NMI_TriggerSrc_Sel for details */ + uint32_t u32Edge; /*!< NMI pin trigger edge, @ref NMI_Trigger_level_Sel for details */ + uint32_t u32Filter; /*!< NMI filter function setting, @ref NMI_FilterClock_Sel for details */ + uint32_t u32FilterClock; /*!< NMI filter clock division, @ref NMI_FilterClock_Div for details */ +} stc_nmi_init_t; + +/** + * @brief EXTINT initialize configuration structure definition + */ +typedef struct { + uint32_t u32Filter; /*!< ExtInt filter (A) function setting, @ref EXTINT_FilterClock_Sel for details */ + uint32_t u32FilterClock; /*!< ExtInt filter (A) clock division, @ref EXTINT_FilterClock_Div for details */ + uint32_t u32Edge; /*!< ExtInt trigger edge, @ref EXTINT_Trigger_Sel for details */ +} stc_extint_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Macros INTC Global Macros + * @{ + */ +/** + * @defgroup INTC_Priority_Sel Interrupt Priority Level 00 ~ 15 + * @{ + */ +#define DDL_IRQ_PRIO_00 (0U) +#define DDL_IRQ_PRIO_01 (1U) +#define DDL_IRQ_PRIO_02 (2U) +#define DDL_IRQ_PRIO_03 (3U) +#define DDL_IRQ_PRIO_04 (4U) +#define DDL_IRQ_PRIO_05 (5U) +#define DDL_IRQ_PRIO_06 (6U) +#define DDL_IRQ_PRIO_07 (7U) +#define DDL_IRQ_PRIO_08 (8U) +#define DDL_IRQ_PRIO_09 (9U) +#define DDL_IRQ_PRIO_10 (10U) +#define DDL_IRQ_PRIO_11 (11U) +#define DDL_IRQ_PRIO_12 (12U) +#define DDL_IRQ_PRIO_13 (13U) +#define DDL_IRQ_PRIO_14 (14U) +#define DDL_IRQ_PRIO_15 (15U) + +#define DDL_IRQ_PRIO_DEFAULT (DDL_IRQ_PRIO_15) + +/** + * @} + */ + +/** + * @defgroup NMI_TriggerSrc_Sel NMI Trigger Source Selection + * @{ + */ +#define NMI_SRC_PIN (INTC_NMIFR_NMIFR) +#define NMI_SRC_SWDT (INTC_NMIFR_SWDTFR) +#define NMI_SRC_LVD1 (INTC_NMIFR_PVD1FR) +#define NMI_SRC_LVD2 (INTC_NMIFR_PVD2FR) +#define NMI_SRC_XTAL (INTC_NMIFR_XTALSTPFR) +#define NMI_SRC_SRAM_PARITY (INTC_NMIFR_REPFR) +#define NMI_SRC_SRAM_ECC (INTC_NMIFR_RECCFR) +#define NMI_SRC_BUS_ERR (INTC_NMIFR_BUSMFR) +#define NMI_SRC_WDT (INTC_NMIFR_WDTFR) +#define NMI_SRC_ALL (NMI_SRC_PIN | NMI_SRC_SWDT | NMI_SRC_LVD1 | \ + NMI_SRC_LVD2 | NMI_SRC_XTAL | NMI_SRC_BUS_ERR | \ + NMI_SRC_SRAM_PARITY | NMI_SRC_WDT | NMI_SRC_SRAM_ECC) + +/** + * @} + */ + +/** + * @defgroup NMI_Trigger_level_Sel NMI Pin Trigger Edge Selection + * @{ + */ +#define NMI_TRIG_FALLING (0UL) +#define NMI_TRIG_RISING (INTC_NMICR_NMITRG) +/** + * @} + */ + +/** + * @defgroup NMI_FilterClock_Sel NMI Pin Filter Selection + * @{ + */ +#define NMI_FILTER_OFF (0UL) +#define NMI_FILTER_ON (INTC_NMICR_NFEN) +/** + * @} + */ + +/** + * @defgroup NMI_FilterClock_Div NMI Pin Filter Sampling Clock Division Selection + * @{ + */ +#define NMI_FCLK_DIV1 (0UL << INTC_NMICR_NSMPCLK_POS) +#define NMI_FCLK_DIV8 (1UL << INTC_NMICR_NSMPCLK_POS) +#define NMI_FCLK_DIV32 (2UL << INTC_NMICR_NSMPCLK_POS) +#define NMI_FCLK_DIV64 (3UL << INTC_NMICR_NSMPCLK_POS) +/** + * @} + */ + +/** + * @defgroup EXTINT_Channel_Sel External Interrupt Channel Selection + * @{ + */ +#define EXTINT_CH00 (1UL << 0U) +#define EXTINT_CH01 (1UL << 1U) +#define EXTINT_CH02 (1UL << 2U) +#define EXTINT_CH03 (1UL << 3U) +#define EXTINT_CH04 (1UL << 4U) +#define EXTINT_CH05 (1UL << 5U) +#define EXTINT_CH06 (1UL << 6U) +#define EXTINT_CH07 (1UL << 7U) +#define EXTINT_CH08 (1UL << 8U) +#define EXTINT_CH09 (1UL << 9U) +#define EXTINT_CH10 (1UL <<10U) +#define EXTINT_CH11 (1UL <<11U) +#define EXTINT_CH12 (1UL <<12U) +#define EXTINT_CH13 (1UL <<13U) +#define EXTINT_CH14 (1UL <<14U) +#define EXTINT_CH15 (1UL <<15U) +#define EXTINT_CH_ALL (EXTINT_CH00 | EXTINT_CH01 | EXTINT_CH02 | EXTINT_CH03 | \ + EXTINT_CH04 | EXTINT_CH05 | EXTINT_CH06 | EXTINT_CH07 | \ + EXTINT_CH08 | EXTINT_CH09 | EXTINT_CH10 | EXTINT_CH11 | \ + EXTINT_CH12 | EXTINT_CH13 | EXTINT_CH14 | EXTINT_CH15) +/** + * @} + */ + +/** + * @defgroup INT_Channel_Sel Interrupt Channel Selection + * @{ + */ +#define INTC_INT0 INTC_IER_IER0 +#define INTC_INT1 INTC_IER_IER1 +#define INTC_INT2 INTC_IER_IER2 +#define INTC_INT3 INTC_IER_IER3 +#define INTC_INT4 INTC_IER_IER4 +#define INTC_INT5 INTC_IER_IER5 +#define INTC_INT6 INTC_IER_IER6 +#define INTC_INT7 INTC_IER_IER7 +#define INTC_INT8 INTC_IER_IER8 +#define INTC_INT9 INTC_IER_IER9 +#define INTC_INT10 INTC_IER_IER10 +#define INTC_INT11 INTC_IER_IER11 +#define INTC_INT12 INTC_IER_IER12 +#define INTC_INT13 INTC_IER_IER13 +#define INTC_INT14 INTC_IER_IER14 +#define INTC_INT15 INTC_IER_IER15 +#define INTC_INT16 INTC_IER_IER16 +#define INTC_INT17 INTC_IER_IER17 +#define INTC_INT18 INTC_IER_IER18 +#define INTC_INT19 INTC_IER_IER19 +#define INTC_INT20 INTC_IER_IER20 +#define INTC_INT21 INTC_IER_IER21 +#define INTC_INT22 INTC_IER_IER22 +#define INTC_INT23 INTC_IER_IER23 +#define INTC_INT24 INTC_IER_IER24 +#define INTC_INT25 INTC_IER_IER25 +#define INTC_INT26 INTC_IER_IER26 +#define INTC_INT27 INTC_IER_IER27 +#define INTC_INT28 INTC_IER_IER28 +#define INTC_INT29 INTC_IER_IER29 +#define INTC_INT30 INTC_IER_IER30 +#define INTC_INT31 INTC_IER_IER31 +#define INTC_INT_ALL (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup INTC_Event_Channel_Sel Event Channel Selection + * @{ + */ +#define INTC_EVT0 INTC_EVTER_EVTE0 +#define INTC_EVT1 INTC_EVTER_EVTE1 +#define INTC_EVT2 INTC_EVTER_EVTE2 +#define INTC_EVT3 INTC_EVTER_EVTE3 +#define INTC_EVT4 INTC_EVTER_EVTE4 +#define INTC_EVT5 INTC_EVTER_EVTE5 +#define INTC_EVT6 INTC_EVTER_EVTE6 +#define INTC_EVT7 INTC_EVTER_EVTE7 +#define INTC_EVT8 INTC_EVTER_EVTE8 +#define INTC_EVT9 INTC_EVTER_EVTE9 +#define INTC_EVT10 INTC_EVTER_EVTE10 +#define INTC_EVT11 INTC_EVTER_EVTE11 +#define INTC_EVT12 INTC_EVTER_EVTE12 +#define INTC_EVT13 INTC_EVTER_EVTE13 +#define INTC_EVT14 INTC_EVTER_EVTE14 +#define INTC_EVT15 INTC_EVTER_EVTE15 +#define INTC_EVT16 INTC_EVTER_EVTE16 +#define INTC_EVT17 INTC_EVTER_EVTE17 +#define INTC_EVT18 INTC_EVTER_EVTE18 +#define INTC_EVT19 INTC_EVTER_EVTE19 +#define INTC_EVT20 INTC_EVTER_EVTE20 +#define INTC_EVT21 INTC_EVTER_EVTE21 +#define INTC_EVT22 INTC_EVTER_EVTE22 +#define INTC_EVT23 INTC_EVTER_EVTE23 +#define INTC_EVT24 INTC_EVTER_EVTE24 +#define INTC_EVT25 INTC_EVTER_EVTE25 +#define INTC_EVT26 INTC_EVTER_EVTE26 +#define INTC_EVT27 INTC_EVTER_EVTE27 +#define INTC_EVT28 INTC_EVTER_EVTE28 +#define INTC_EVT29 INTC_EVTER_EVTE29 +#define INTC_EVT30 INTC_EVTER_EVTE30 +#define INTC_EVT31 INTC_EVTER_EVTE31 +#define INTC_EVT_ALL (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup SWINT_Channel_Sel Software Interrupt Channel Selection + * @{ + */ +#define SWINT_CH00 INTC_SWIER_SWIE0 +#define SWINT_CH01 INTC_SWIER_SWIE1 +#define SWINT_CH02 INTC_SWIER_SWIE2 +#define SWINT_CH03 INTC_SWIER_SWIE3 +#define SWINT_CH04 INTC_SWIER_SWIE4 +#define SWINT_CH05 INTC_SWIER_SWIE5 +#define SWINT_CH06 INTC_SWIER_SWIE6 +#define SWINT_CH07 INTC_SWIER_SWIE7 +#define SWINT_CH08 INTC_SWIER_SWIE8 +#define SWINT_CH09 INTC_SWIER_SWIE9 +#define SWINT_CH10 INTC_SWIER_SWIE10 +#define SWINT_CH11 INTC_SWIER_SWIE11 +#define SWINT_CH12 INTC_SWIER_SWIE12 +#define SWINT_CH13 INTC_SWIER_SWIE13 +#define SWINT_CH14 INTC_SWIER_SWIE14 +#define SWINT_CH15 INTC_SWIER_SWIE15 +#define SWINT_CH16 INTC_SWIER_SWIE16 +#define SWINT_CH17 INTC_SWIER_SWIE17 +#define SWINT_CH18 INTC_SWIER_SWIE18 +#define SWINT_CH19 INTC_SWIER_SWIE19 +#define SWINT_CH20 INTC_SWIER_SWIE20 +#define SWINT_CH21 INTC_SWIER_SWIE21 +#define SWINT_CH22 INTC_SWIER_SWIE22 +#define SWINT_CH23 INTC_SWIER_SWIE23 +#define SWINT_CH24 INTC_SWIER_SWIE24 +#define SWINT_CH25 INTC_SWIER_SWIE25 +#define SWINT_CH26 INTC_SWIER_SWIE26 +#define SWINT_CH27 INTC_SWIER_SWIE27 +#define SWINT_CH28 INTC_SWIER_SWIE28 +#define SWINT_CH29 INTC_SWIER_SWIE29 +#define SWINT_CH30 INTC_SWIER_SWIE30 +#define SWINT_CH31 INTC_SWIER_SWIE31 +#define SWINT_ALL (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup EXTINT_FilterClock_Sel External Interrupt Filter A Function Selection + * @{ + */ +#define EXTINT_FILTER_OFF (0UL) +#define EXTINT_FILTER_ON INTC_EIRQCR_EFEN + +/** + * @} + */ + +/** + * @defgroup EXTINT_FilterClock_Div External Interrupt Filter A Sampling Clock Division Selection + * @{ + */ +#define EXTINT_FCLK_DIV1 (0UL) +#define EXTINT_FCLK_DIV8 INTC_EIRQCR_EISMPCLK_0 +#define EXTINT_FCLK_DIV32 INTC_EIRQCR_EISMPCLK_1 +#define EXTINT_FCLK_DIV64 INTC_EIRQCR_EISMPCLK + +/** + * @} + */ + +/** + * @defgroup NMI_EXTINT_FilterBTim_Sel External Interrupt Filter B Time Selection + * @{ + */ +/** + * @} + */ + +/** + * @defgroup EXTINT_Trigger_Sel External Interrupt Trigger Edge Selection + * @{ + */ +#define EXTINT_TRIG_FALLING (0UL) +#define EXTINT_TRIG_RISING INTC_EIRQCR_EIRQTRG_0 +#define EXTINT_TRIG_BOTH INTC_EIRQCR_EIRQTRG_1 +#define EXTINT_TRIG_LOW INTC_EIRQCR_EIRQTRG + +/** + * @} + */ + +/** + * @defgroup INTC_Stop_Wakeup_Source_Sel Stop Mode Wakeup Source Selection + * @{ + */ +#define INTC_STOP_WKUP_EXTINT_CH0 INTC_WUPEN_EIRQWUEN_0 +#define INTC_STOP_WKUP_EXTINT_CH1 INTC_WUPEN_EIRQWUEN_1 +#define INTC_STOP_WKUP_EXTINT_CH2 INTC_WUPEN_EIRQWUEN_2 +#define INTC_STOP_WKUP_EXTINT_CH3 INTC_WUPEN_EIRQWUEN_3 +#define INTC_STOP_WKUP_EXTINT_CH4 INTC_WUPEN_EIRQWUEN_4 +#define INTC_STOP_WKUP_EXTINT_CH5 INTC_WUPEN_EIRQWUEN_5 +#define INTC_STOP_WKUP_EXTINT_CH6 INTC_WUPEN_EIRQWUEN_6 +#define INTC_STOP_WKUP_EXTINT_CH7 INTC_WUPEN_EIRQWUEN_7 +#define INTC_STOP_WKUP_EXTINT_CH8 INTC_WUPEN_EIRQWUEN_8 +#define INTC_STOP_WKUP_EXTINT_CH9 INTC_WUPEN_EIRQWUEN_9 +#define INTC_STOP_WKUP_EXTINT_CH10 INTC_WUPEN_EIRQWUEN_10 +#define INTC_STOP_WKUP_EXTINT_CH11 INTC_WUPEN_EIRQWUEN_11 +#define INTC_STOP_WKUP_EXTINT_CH12 INTC_WUPEN_EIRQWUEN_12 +#define INTC_STOP_WKUP_EXTINT_CH13 INTC_WUPEN_EIRQWUEN_13 +#define INTC_STOP_WKUP_EXTINT_CH14 INTC_WUPEN_EIRQWUEN_14 +#define INTC_STOP_WKUP_EXTINT_CH15 INTC_WUPEN_EIRQWUEN_15 +#define INTC_STOP_WKUP_SWDT INTC_WUPEN_SWDTWUEN +#define INTC_STOP_WKUP_LVD1 INTC_WUPEN_PVD1WUEN +#define INTC_STOP_WKUP_LVD2 INTC_WUPEN_PVD2WUEN +#define INTC_STOP_WKUP_CMP INTC_WUPEN_CMPI0WUEN +#define INTC_STOP_WKUP_WKTM INTC_WUPEN_WKTMWUEN +#define INTC_STOP_WKUP_RTC_ALM INTC_WUPEN_RTCALMWUEN +#define INTC_STOP_WKUP_RTC_PRD INTC_WUPEN_RTCPRDWUEN +#define INTC_STOP_WKUP_TMR0_CMP INTC_WUPEN_TMR0WUEN +#define INTC_STOP_WKUP_USART1_RX INTC_WUPEN_RXWUEN +#define INTC_WUPEN_ALL \ + (INTC_WUPEN_EIRQWUEN | INTC_WUPEN_SWDTWUEN | \ + INTC_WUPEN_PVD1WUEN | INTC_WUPEN_PVD2WUEN | \ + INTC_WUPEN_CMPI0WUEN | INTC_WUPEN_WKTMWUEN | \ + INTC_WUPEN_RTCALMWUEN | INTC_WUPEN_RTCPRDWUEN | \ + INTC_WUPEN_TMR0WUEN | INTC_WUPEN_RXWUEN) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup INTC_Global_Functions + * @{ + */ + +int32_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig); +int32_t INTC_IrqSignOut(IRQn_Type enIRQn); +void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState); +void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState); +void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState); +void INTC_SWIntInit(uint32_t u32Ch, const func_ptr_t pfnCallback, uint32_t u32Priority); +void INTC_SWIntCmd(uint32_t u32SWInt, en_functional_state_t enNewState); + +int32_t NMI_Init(const stc_nmi_init_t *pstcNmiInit); +int32_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit); +en_flag_status_t NMI_GetNmiStatus(uint32_t u32Src); +void NMI_NmiSrcCmd(uint32_t u32Src, en_functional_state_t enNewState); +void NMI_ClearNmiStatus(uint32_t u32Src); + +int32_t EXTINT_Init(uint32_t u32Ch, const stc_extint_init_t *pstcExtIntInit); +int32_t EXTINT_StructInit(stc_extint_init_t *pstcExtIntInit); +en_flag_status_t EXTINT_GetExtIntStatus(uint32_t u32ExtIntCh); +void EXTINT_ClearExtIntStatus(uint32_t u32ExtIntCh); + +void IRQ000_Handler(void); +void IRQ001_Handler(void); +void IRQ002_Handler(void); +void IRQ003_Handler(void); +void IRQ004_Handler(void); +void IRQ005_Handler(void); +void IRQ006_Handler(void); +void IRQ007_Handler(void); + +void IRQ008_Handler(void); +void IRQ009_Handler(void); +void IRQ010_Handler(void); +void IRQ011_Handler(void); +void IRQ012_Handler(void); +void IRQ013_Handler(void); +void IRQ014_Handler(void); +void IRQ015_Handler(void); + +void IRQ016_Handler(void); +void IRQ017_Handler(void); +void IRQ018_Handler(void); +void IRQ019_Handler(void); +void IRQ020_Handler(void); +void IRQ021_Handler(void); +void IRQ022_Handler(void); +void IRQ023_Handler(void); + +void IRQ024_Handler(void); +void IRQ025_Handler(void); +void IRQ026_Handler(void); +void IRQ027_Handler(void); +void IRQ028_Handler(void); +void IRQ029_Handler(void); +void IRQ030_Handler(void); +void IRQ031_Handler(void); +void IRQ032_Handler(void); +void IRQ033_Handler(void); +void IRQ034_Handler(void); +void IRQ035_Handler(void); +void IRQ036_Handler(void); +void IRQ037_Handler(void); +void IRQ038_Handler(void); +void IRQ039_Handler(void); +void IRQ040_Handler(void); +void IRQ041_Handler(void); +void IRQ042_Handler(void); +void IRQ043_Handler(void); +void IRQ044_Handler(void); +void IRQ045_Handler(void); +void IRQ046_Handler(void); +void IRQ047_Handler(void); +void IRQ048_Handler(void); +void IRQ049_Handler(void); +void IRQ050_Handler(void); +void IRQ051_Handler(void); +void IRQ052_Handler(void); +void IRQ053_Handler(void); +void IRQ054_Handler(void); +void IRQ055_Handler(void); +void IRQ056_Handler(void); +void IRQ057_Handler(void); +void IRQ058_Handler(void); +void IRQ059_Handler(void); +void IRQ060_Handler(void); +void IRQ061_Handler(void); +void IRQ062_Handler(void); +void IRQ063_Handler(void); +void IRQ064_Handler(void); +void IRQ065_Handler(void); +void IRQ066_Handler(void); +void IRQ067_Handler(void); +void IRQ068_Handler(void); +void IRQ069_Handler(void); +void IRQ070_Handler(void); +void IRQ071_Handler(void); +void IRQ072_Handler(void); +void IRQ073_Handler(void); +void IRQ074_Handler(void); +void IRQ075_Handler(void); +void IRQ076_Handler(void); +void IRQ077_Handler(void); +void IRQ078_Handler(void); +void IRQ079_Handler(void); +void IRQ080_Handler(void); +void IRQ081_Handler(void); +void IRQ082_Handler(void); +void IRQ083_Handler(void); +void IRQ084_Handler(void); +void IRQ085_Handler(void); +void IRQ086_Handler(void); +void IRQ087_Handler(void); +void IRQ088_Handler(void); +void IRQ089_Handler(void); +void IRQ090_Handler(void); +void IRQ091_Handler(void); +void IRQ092_Handler(void); +void IRQ093_Handler(void); +void IRQ094_Handler(void); +void IRQ095_Handler(void); +void IRQ096_Handler(void); +void IRQ097_Handler(void); +void IRQ098_Handler(void); +void IRQ099_Handler(void); +void IRQ100_Handler(void); +void IRQ101_Handler(void); +void IRQ102_Handler(void); +void IRQ103_Handler(void); +void IRQ104_Handler(void); +void IRQ105_Handler(void); +void IRQ106_Handler(void); +void IRQ107_Handler(void); +void IRQ108_Handler(void); +void IRQ109_Handler(void); +void IRQ110_Handler(void); +void IRQ111_Handler(void); +void IRQ112_Handler(void); +void IRQ113_Handler(void); +void IRQ114_Handler(void); +void IRQ115_Handler(void); +void IRQ116_Handler(void); +void IRQ117_Handler(void); +void IRQ118_Handler(void); +void IRQ119_Handler(void); +void IRQ120_Handler(void); +void IRQ121_Handler(void); +void IRQ122_Handler(void); +void IRQ123_Handler(void); +void IRQ124_Handler(void); +void IRQ125_Handler(void); +void IRQ126_Handler(void); +void IRQ127_Handler(void); + +/** + * @} + */ + +#endif /* LL_INTERRUPTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_INTERRUPTS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_keyscan.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_keyscan.h new file mode 100644 index 0000000000..2cff107fbe --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_keyscan.h @@ -0,0 +1,239 @@ +/** + ******************************************************************************* + * @file hc32_ll_keyscan.h + * @brief This file contains all the functions prototypes of the KEYSCAN driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_KEYSCAN_H__ +#define __HC32_LL_KEYSCAN_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_KEYSCAN + * @{ + */ + +#if (LL_KEYSCAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Types KEYSCAN Global Types + * @{ + */ + +/** + * @brief KEYSCAN configuration + */ +typedef struct { + uint32_t u32HizCycle; /*!< Specifies the KEYSCAN Hiz cycles. + This parameter can be a value of @ref KEYSCAN_Hiz_Cycle_Sel */ + + uint32_t u32LowCycle; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Low_Cycle_Sel */ + + uint32_t u32KeyClock; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Clock_Sel */ + + uint32_t u32KeyOut; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Keyout_Sel */ + + uint32_t u32KeyIn; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Keyin_Sel */ +} stc_keyscan_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Macros KEYSCAN Global Macros + * @{ + */ + +/** + * @defgroup KEYSCAN_Hiz_Cycle_Sel KEYSCAN Hiz cycles during low ouput selection + * @{ + */ +#define KEYSCAN_HIZ_CYCLE_4 (0x00UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 4 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_8 (0x01UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 8 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_16 (0x02UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 16 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_32 (0x03UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 32 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_64 (0x04UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 64 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_256 (0x05UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 256 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_512 (0x06UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 512 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_1024 (0x07UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 1024 cycles during low ouput */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Low_Cycle_Sel KEYSCAN low level output cycles selection + * @{ + */ +#define KEYSCAN_LOW_CYCLE_4 (0x02UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^2=4 cycles */ +#define KEYSCAN_LOW_CYCLE_8 (0x03UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^3=8 cycles */ +#define KEYSCAN_LOW_CYCLE_16 (0x04UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^4=16 cycles */ +#define KEYSCAN_LOW_CYCLE_32 (0x05UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^5=32 cycles */ +#define KEYSCAN_LOW_CYCLE_64 (0x06UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^6=64 cycles */ +#define KEYSCAN_LOW_CYCLE_128 (0x07UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^7=128 cycles */ +#define KEYSCAN_LOW_CYCLE_256 (0x08UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^8=256 cycles */ +#define KEYSCAN_LOW_CYCLE_512 (0x09UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^9=512 cycles */ +#define KEYSCAN_LOW_CYCLE_1K (0x0AUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^10=1K cycles */ +#define KEYSCAN_LOW_CYCLE_2K (0x0BUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^11=2K cycles */ +#define KEYSCAN_LOW_CYCLE_4K (0x0CUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^12=4K cycles */ +#define KEYSCAN_LOW_CYCLE_8K (0x0DUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^13=8K cycles */ +#define KEYSCAN_LOW_CYCLE_16K (0x0EUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^14=16K cycles */ +#define KEYSCAN_LOW_CYCLE_32K (0x0FUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^15=32K cycles */ +#define KEYSCAN_LOW_CYCLE_64K (0x10UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^16=64K cycles */ +#define KEYSCAN_LOW_CYCLE_128K (0x11UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^17=128K cycles */ +#define KEYSCAN_LOW_CYCLE_256K (0x12UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^18=256K cycles */ +#define KEYSCAN_LOW_CYCLE_512K (0x13UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^19=512K cycles */ +#define KEYSCAN_LOW_CYCLE_1M (0x14UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^20=1M cycles */ +#define KEYSCAN_LOW_CYCLE_2M (0x15UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^21=2M cycles */ +#define KEYSCAN_LOW_CYCLE_4M (0x16UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^22=4M cycles */ +#define KEYSCAN_LOW_CYCLE_8M (0x17UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^23=8M cycles */ +#define KEYSCAN_LOW_CYCLE_16M (0x18UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^24=16M cycles */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Clock_Sel KEYSCAN scan clock selection + * @{ + */ +#define KEYSCAN_CLK_HCLK (0x00UL) /*!< Use as HCLK KEYSCAN clock */ +#define KEYSCAN_CLK_LRC (KEYSCAN_SCR_CKSEL_0) /*!< Use as LRC KEYSCAN clock */ +#define KEYSCAN_CLK_XTAL32 (KEYSCAN_SCR_CKSEL_1) /*!< Use as XTAL32 KEYSCAN clock */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Keyout_Sel KEYSCAN keyout pins selection + * @{ + */ +#define KEYSCAN_OUT_0T1 (0x01UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 1 are selected */ +#define KEYSCAN_OUT_0T2 (0x02UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 2 are selected */ +#define KEYSCAN_OUT_0T3 (0x03UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 3 are selected */ +#define KEYSCAN_OUT_0T4 (0x04UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 4 are selected */ +#define KEYSCAN_OUT_0T5 (0x05UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 5 are selected */ +#define KEYSCAN_OUT_0T6 (0x06UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 6 are selected */ +#define KEYSCAN_OUT_0T7 (0x07UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 7 are selected */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Keyin_Sel KEYSCAN keyin pins selection + * @{ + */ +#define KEYSCAN_IN_0 (KEYSCAN_SCR_KEYINSEL_0) /*!< KEYIN(EIRQ) 0 is selected */ +#define KEYSCAN_IN_1 (KEYSCAN_SCR_KEYINSEL_1) /*!< KEYIN(EIRQ) 1 is selected */ +#define KEYSCAN_IN_2 (KEYSCAN_SCR_KEYINSEL_2) /*!< KEYIN(EIRQ) 2 is selected */ +#define KEYSCAN_IN_3 (KEYSCAN_SCR_KEYINSEL_3) /*!< KEYIN(EIRQ) 3 is selected */ +#define KEYSCAN_IN_4 (KEYSCAN_SCR_KEYINSEL_4) /*!< KEYIN(EIRQ) 4 is selected */ +#define KEYSCAN_IN_5 (KEYSCAN_SCR_KEYINSEL_5) /*!< KEYIN(EIRQ) 5 is selected */ +#define KEYSCAN_IN_6 (KEYSCAN_SCR_KEYINSEL_6) /*!< KEYIN(EIRQ) 6 is selected */ +#define KEYSCAN_IN_7 (KEYSCAN_SCR_KEYINSEL_7) /*!< KEYIN(EIRQ) 7 is selected */ +#define KEYSCAN_IN_8 (KEYSCAN_SCR_KEYINSEL_8) /*!< KEYIN(EIRQ) 8 is selected */ +#define KEYSCAN_IN_9 (KEYSCAN_SCR_KEYINSEL_9) /*!< KEYIN(EIRQ) 9 is selected */ +#define KEYSCAN_IN_10 (KEYSCAN_SCR_KEYINSEL_10) /*!< KEYIN(EIRQ) 10 is selected */ +#define KEYSCAN_IN_11 (KEYSCAN_SCR_KEYINSEL_11) /*!< KEYIN(EIRQ) 11 is selected */ +#define KEYSCAN_IN_12 (KEYSCAN_SCR_KEYINSEL_12) /*!< KEYIN(EIRQ) 12 is selected */ +#define KEYSCAN_IN_13 (KEYSCAN_SCR_KEYINSEL_13) /*!< KEYIN(EIRQ) 13 is selected */ +#define KEYSCAN_IN_14 (KEYSCAN_SCR_KEYINSEL_14) /*!< KEYIN(EIRQ) 14 is selected */ +#define KEYSCAN_IN_15 (KEYSCAN_SCR_KEYINSEL_15) /*!< KEYIN(EIRQ) 15 is selected */ +#define KEYSCAN_IN_ALL (KEYSCAN_SCR_KEYINSEL) /*!< KEYIN(EIRQ) mask */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup KEYSCAN_Global_Functions + * @{ + */ +/** + * @brief Get KEYOUT index. + * @param None + * @retval uint32_t: KEYOUT index 0~7. + */ +__STATIC_INLINE uint32_t KEYSCAN_GetKeyoutIdx(void) +{ + return READ_REG32_BIT(CM_KEYSCAN->SSR, KEYSCAN_SSR_INDEX); +} + +int32_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit); +int32_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit); +void KEYSCAN_Cmd(en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_KEYSCAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_KEYSCAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mpu.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mpu.h new file mode 100644 index 0000000000..b58c8e3e04 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mpu.h @@ -0,0 +1,384 @@ +/** + ******************************************************************************* + * @file hc32_ll_mpu.h + * @brief This file contains all the functions prototypes of the MPU driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_MPU_H__ +#define __HC32_LL_MPU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_MPU + * @{ + */ + +#if (LL_MPU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Types MPU Global Types + * @{ + */ + +/** + * @brief MPU Unit configure structure definition + */ +typedef struct { + uint32_t u32ExceptionType; /*!< Specifies the type of exception that occurs when the unit accesses a protected region. + This parameter can be a value of @ref MPU_Exception_Type */ + uint32_t u32BackgroundWrite; /*!< Specifies the unit's write permission for the background space. + This parameter can be a value of @ref MPU_Background_Write_Permission */ + uint32_t u32BackgroundRead; /*!< Specifies the unit's read permission for the background space + This parameter can be a value of @ref MPU_Background_Read_Permission */ +} stc_mpu_unit_config_t; + +/** + * @brief MPU Init structure definition + */ +typedef struct { + stc_mpu_unit_config_t stcDma1; /*!< Configure storage protection unit of DMA1 */ + stc_mpu_unit_config_t stcDma2; /*!< Configure storage protection unit of DMA2 */ + stc_mpu_unit_config_t stcUsbFSDma; /*!< Configure storage protection unit of USBFS_DMA */ +} stc_mpu_init_t; + +/** + * @brief MPU Region Permission structure definition + */ +typedef struct { + uint32_t u32RegionWrite; /*!< Specifies the unit's write permission for the region. + This parameter can be a value of @ref MPU_Region_Write_Permission */ + uint32_t u32RegionRead; /*!< Specifies the unit's read permission for the region. + This parameter can be a value of @ref MPU_Region_Read_Permission */ +} stc_mpu_region_permission_t; + +/** + * @brief MPU region initialization structure definition + * @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region, + * and the low 'u32Size+1' bits are fixed at 0. + */ +typedef struct { + uint32_t u32BaseAddr; /*!< Specifies the base address of the region. + This parameter can be a number between 0UL and 0xFFFFFFE0UL */ + uint32_t u32Size; /*!< Specifies the size of the region. + This parameter can be a value of @ref MPU_Region_Size */ + stc_mpu_region_permission_t stcDma1; /*!< Specifies the DMA1 access permission for the region */ + stc_mpu_region_permission_t stcDma2; /*!< Specifies the DMA2 access permission for the region */ + stc_mpu_region_permission_t stcUsbFSDma; /*!< Specifies the USBFS_DMA access permission for the region */ +} stc_mpu_region_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Macros MPU Global Macros + * @{ + */ + +/** + * @defgroup MPU_Unit_Type MPU Unit Type + * @{ + */ +#define MPU_UNIT_DMA2 (0x01UL) /*!< System DMA_2 MPU */ +#define MPU_UNIT_DMA1 (0x02UL) /*!< System DMA_1 MPU */ +#define MPU_UNIT_USBFS_DMA (0x04UL) /*!< USBFS_DMA MPU */ +#define MPU_UNIT_ALL (MPU_UNIT_DMA2 | MPU_UNIT_DMA1 | MPU_UNIT_USBFS_DMA) +/** + * @} + */ + +/** + * @defgroup MPU_Region_Number MPU Region Number + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @{ + */ +#define MPU_REGION_NUM0 (0x00UL) /*!< MPU region number 0 */ +#define MPU_REGION_NUM1 (0x01UL) /*!< MPU region number 1 */ +#define MPU_REGION_NUM2 (0x02UL) /*!< MPU region number 2 */ +#define MPU_REGION_NUM3 (0x03UL) /*!< MPU region number 3 */ +#define MPU_REGION_NUM4 (0x04UL) /*!< MPU region number 4 */ +#define MPU_REGION_NUM5 (0x05UL) /*!< MPU region number 5 */ +#define MPU_REGION_NUM6 (0x06UL) /*!< MPU region number 6 */ +#define MPU_REGION_NUM7 (0x07UL) /*!< MPU region number 7 */ +#define MPU_REGION_NUM8 (0x08UL) /*!< MPU region number 8 */ +#define MPU_REGION_NUM9 (0x09UL) /*!< MPU region number 9 */ +#define MPU_REGION_NUM10 (0x0AUL) /*!< MPU region number 10 */ +#define MPU_REGION_NUM11 (0x0BUL) /*!< MPU region number 11 */ +#define MPU_REGION_NUM12 (0x0CUL) /*!< MPU region number 12 */ +#define MPU_REGION_NUM13 (0x0DUL) /*!< MPU region number 13 */ +#define MPU_REGION_NUM14 (0x0EUL) /*!< MPU region number 14 */ +#define MPU_REGION_NUM15 (0x0FUL) /*!< MPU region number 15 */ +/** + * @} + */ + +/** + * @defgroup MPU_Background_Write_Permission MPU Background Write Permission + * @{ + */ +#define MPU_BACKGROUND_WR_DISABLE (MPU_CR_SMPU2BWP) /*!< Disable write the background space */ +#define MPU_BACKGROUND_WR_ENABLE (0UL) /*!< Enable write the background space */ +/** + * @} + */ + +/** + * @defgroup MPU_Background_Read_Permission MPU Background Read Permission + * @{ + */ +#define MPU_BACKGROUND_RD_DISABLE (MPU_CR_SMPU2BRP) /*!< Disable read the background space */ +#define MPU_BACKGROUND_RD_ENABLE (0UL) /*!< Enable read the background space */ +/** + * @} + */ + +/** + * @defgroup MPU_Exception_Type MPU Exception Type + * @{ + */ +#define MPU_EXP_TYPE_NONE (0UL) /*!< The host unit access protection regions will be ignored */ +#define MPU_EXP_TYPE_BUS_ERR (MPU_CR_SMPU2ACT_0) /*!< The host unit access protection regions will be ignored and a bus error will be triggered */ +#define MPU_EXP_TYPE_NMI (MPU_CR_SMPU2ACT_1) /*!< The host unit access protection regions will be ignored and a NMI interrupt will be triggered */ +#define MPU_EXP_TYPE_RST (MPU_CR_SMPU2ACT) /*!< The host unit access protection regions will trigger the reset */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Write_Permission MPU Region Write Permission + * @{ + */ +#define MPU_REGION_WR_DISABLE (MPU_RGCR_S2RGWP) /*!< Disable write the region */ +#define MPU_REGION_WR_ENABLE (0UL) /*!< Enable write the region */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Read_Permission MPU Region Read Permission + * @{ + */ +#define MPU_REGION_RD_DISABLE (MPU_RGCR_S2RGRP) /*!< Disable read the region */ +#define MPU_REGION_RD_ENABLE (0UL) /*!< Enable read the region */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Size MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32BYTE (0x04UL) /*!< 32 Byte */ +#define MPU_REGION_SIZE_64BYTE (0x05UL) /*!< 64 Byte */ +#define MPU_REGION_SIZE_128BYTE (0x06UL) /*!< 126 Byte */ +#define MPU_REGION_SIZE_256BYTE (0x07UL) /*!< 256 Byte */ +#define MPU_REGION_SIZE_512BYTE (0x08UL) /*!< 512 Byte */ +#define MPU_REGION_SIZE_1KBYTE (0x09UL) /*!< 1K Byte */ +#define MPU_REGION_SIZE_2KBYTE (0x0AUL) /*!< 2K Byte */ +#define MPU_REGION_SIZE_4KBYTE (0x0BUL) /*!< 4K Byte */ +#define MPU_REGION_SIZE_8KBYTE (0x0CUL) /*!< 8K Byte */ +#define MPU_REGION_SIZE_16KBYTE (0x0DUL) /*!< 16K Byte */ +#define MPU_REGION_SIZE_32KBYTE (0x0EUL) /*!< 32K Byte */ +#define MPU_REGION_SIZE_64KBYTE (0x0FUL) /*!< 64K Byte */ +#define MPU_REGION_SIZE_128KBYTE (0x10UL) /*!< 128K Byte */ +#define MPU_REGION_SIZE_256KBYTE (0x11UL) /*!< 256K Byte */ +#define MPU_REGION_SIZE_512KBYTE (0x12UL) /*!< 512K Byte */ +#define MPU_REGION_SIZE_1MBYTE (0x13UL) /*!< 1M Byte */ +#define MPU_REGION_SIZE_2MBYTE (0x14UL) /*!< 2M Byte */ +#define MPU_REGION_SIZE_4MBYTE (0x15UL) /*!< 4M Byte */ +#define MPU_REGION_SIZE_8MBYTE (0x16UL) /*!< 8M Byte */ +#define MPU_REGION_SIZE_16MBYTE (0x17UL) /*!< 16M Byte */ +#define MPU_REGION_SIZE_32MBYTE (0x18UL) /*!< 32M Byte */ +#define MPU_REGION_SIZE_64MBYTE (0x19UL) /*!< 64M Byte */ +#define MPU_REGION_SIZE_128MBYTE (0x1AUL) /*!< 128M Byte */ +#define MPU_REGION_SIZE_256MBYTE (0x1BUL) /*!< 256M Byte */ +#define MPU_REGION_SIZE_512MBYTE (0x1CUL) /*!< 512M Byte */ +#define MPU_REGION_SIZE_1GBYTE (0x1DUL) /*!< 1G Byte */ +#define MPU_REGION_SIZE_2GBYTE (0x1EUL) /*!< 2G Byte */ +#define MPU_REGION_SIZE_4GBYTE (0x1FUL) /*!< 4G Byte */ +/** + * @} + */ + +/** + * @defgroup MPU_Flag MPU Flag + * @{ + */ +#define MPU_FLAG_SMPU1EAF (MPU_SR_SMPU1EAF) /*!< System DMA_1 error flag */ +#define MPU_FLAG_SMPU2EAF (MPU_SR_SMPU2EAF) /*!< System DMA_2 error flag */ +#define MPU_FLAG_FMPUEAF (MPU_SR_FMPUEAF) /*!< USBFS_DMA error flag */ + +#define MPU_FLAG_ALL (MPU_FLAG_SMPU1EAF | MPU_FLAG_SMPU2EAF | MPU_FLAG_FMPUEAF) +/** + * @} + */ + +/** + * @defgroup MPU_IP_Type MPU IP Type + * @note IP access protection is not available in privileged mode. + * @{ + */ +#define MPU_IP_AES (MPU_IPPR_AESRDP) /*!< AES module */ +#define MPU_IP_HASH (MPU_IPPR_HASHRDP) /*!< HASH module */ +#define MPU_IP_TRNG (MPU_IPPR_TRNGRDP) /*!< TRNG module */ +#define MPU_IP_CRC (MPU_IPPR_CRCRDP) /*!< CRC module */ +#define MPU_IP_EFM (MPU_IPPR_EFMRDP) /*!< EFM module */ +#define MPU_IP_WDT (MPU_IPPR_WDTRDP) /*!< WDT module */ +#define MPU_IP_SWDT (MPU_IPPR_SWDTRDP) /*!< SWDT module */ +#define MPU_IP_BKSRAM (MPU_IPPR_BKSRAMRDP) /*!< BKSRAM module */ +#define MPU_IP_RTC (MPU_IPPR_RTCRDP) /*!< RTC module */ +#define MPU_IP_MPU (MPU_IPPR_DMPURDP) /*!< MPU module */ +#define MPU_IP_SRAMC (MPU_IPPR_SRAMCRDP) /*!< SRAMC module */ +#define MPU_IP_INTC (MPU_IPPR_INTCRDP) /*!< INTC module */ +#define MPU_IP_RMU_CMU_PWC (MPU_IPPR_SYSCRDP) /*!< RMU, CMU and PWC modules */ +#define MPU_IP_FCG (MPU_IPPR_MSTPRDP) /*!< PWR_FCG0/1/2/3 and PWR_FCG0PC registers */ +#define MPU_IP_ALL (MPU_IP_AES | MPU_IP_HASH | MPU_IP_TRNG | MPU_IP_CRC | \ + MPU_IP_EFM | MPU_IP_WDT | MPU_IP_SWDT | MPU_IP_BKSRAM | \ + MPU_IP_RTC | MPU_IP_MPU | MPU_IP_SRAMC | MPU_IP_INTC | \ + MPU_IP_FCG | MPU_IP_RMU_CMU_PWC) +/** + * @} + */ + +/** + * @defgroup MPU_IP_Exception_Type MPU IP Exception Type + * @{ + */ +#define MPU_IP_EXP_TYPE_NONE (0UL) /*!< Access to the protected IP will be ignored */ +#define MPU_IP_EXP_TYPE_BUS_ERR (MPU_IPPR_BUSERRE) /*!< Access to the protected IP will trigger a bus error */ +/** + * @} + */ + +/** + * @defgroup MPU_Register_Protect_Key INTC Registers Protect Key + * @{ + */ +#define MPU_REG_LOCK_KEY (0x96A4UL) +#define MPU_REG_UNLOCK_KEY (0x96A5UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup MPU_Global_Functions + * @{ + */ + +/** + * @brief MPU write protect unlock. + * @param None + * @retval None + */ +__STATIC_INLINE void MPU_REG_Unlock(void) +{ + WRITE_REG32(CM_MPU->WP, MPU_REG_UNLOCK_KEY); +} + +/** + * @brief MPU write protect lock. + * @param None + * @retval None + */ +__STATIC_INLINE void MPU_REG_Lock(void) +{ + WRITE_REG32(CM_MPU->WP, MPU_REG_LOCK_KEY); +} + +void MPU_REG_Unlock(void); +void MPU_REG_Lock(void); + +void MPU_DeInit(void); +int32_t MPU_Init(const stc_mpu_init_t *pstcMpuInit); +int32_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit); +void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32Type); +void MPU_BackgroundWriteCmd(uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_BackgroundReadCmd(uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState); +en_flag_status_t MPU_GetStatus(uint32_t u32Flag); +void MPU_ClearStatus(uint32_t u32Flag); + +int32_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit); +int32_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit); +void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr); +void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size); +void MPU_RegionWriteCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_RegionReadCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); + +void MPU_IP_SetExceptionType(uint32_t u32Type); +void MPU_IP_WriteCmd(uint32_t u32Periph, en_functional_state_t enNewState); +void MPU_IP_ReadCmd(uint32_t u32Periph, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_MPU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_MPU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ots.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ots.h new file mode 100644 index 0000000000..037f26a0e9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ots.h @@ -0,0 +1,188 @@ +/** + ******************************************************************************* + * @file hc32_ll_ots.h + * @brief This file contains all the functions prototypes of the OTS driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_OTS_H__ +#define __HC32_LL_OTS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_OTS + * @{ + */ + +#if (LL_OTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup OTS_Global_Types OTS Global Types + * @{ + */ + +/** + * @brief OTS initialization structure. + */ +typedef struct { + uint16_t u16ClockSrc; /*!< Specifies clock source for OTS. + This parameter can be a value of @ref OTS_Clock_Source */ + uint16_t u16AutoOffEn; /*!< Enable or disable OTS automatic-off(after sampled temperature). + This parameter can be a value of @ref OTS_Auto_Off_En */ + float32_t f32SlopeK; /*!< K: Temperature slope (calculated by calibration experiment). + If you want to use the default parameters(slope K and offset M), + specify both 'f32SlopeK' and 'f32OffsetM' as ZERO. */ + float32_t f32OffsetM; /*!< M: Temperature offset (calculated by calibration experiment). + If you want to use the default parameters(slope K and offset M), + specify both 'f32SlopeK' and 'f32OffsetM' as ZERO. */ +} stc_ots_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup OTS_Global_Macros OTS Global Macros + * @{ + */ + +/** + * @defgroup OTS_Clock_Source OTS Clock Source + * @{ + */ +#define OTS_CLK_XTAL (0x0U) /*!< Select XTAL as OTS clock. */ +#define OTS_CLK_HRC (OTS_CTL_OTSCK) /*!< Select HRC as OTS clock */ +/** + * @} + */ + +/** + * @defgroup OTS_Auto_Off_En OTS Automatic Off Function Control + * @{ + */ +#define OTS_AUTO_OFF_DISABLE (0x0U) /*!< OTS automatically turned off when sampled done. */ +#define OTS_AUTO_OFF_ENABLE (OTS_CTL_TSSTP) /*!< OTS is still on when sampled done. */ +/** + * @} + */ + +/** + * @defgroup OTS_Param_Temp_Cond OTS Parameter Temperature Condition + * @{ + */ +#define OTS_PARAM_TEMP_COND_TN40 (0U) /*!< -40 degrees Celsius. */ +#define OTS_PARAM_TEMP_COND_T25 (1U) /*!< 25 degrees Celsius. */ +#define OTS_PARAM_TEMP_COND_T125 (2U) /*!< 125 degrees Celsius. */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup OTS_Global_Functions + * @{ + */ + +/** + * @brief Start OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Start(void) +{ + WRITE_REG32(bCM_OTS->CTL_b.OTSST, 1U); +} + +/** + * @brief Stop OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Stop(void) +{ + WRITE_REG32(bCM_OTS->CTL_b.OTSST, 0U); +} + +int32_t OTS_Init(const stc_ots_init_t *pstcOTSInit); +int32_t OTS_StructInit(stc_ots_init_t *pstcOTSInit); +void OTS_DeInit(void); + +int32_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout); + +void OTS_IntCmd(en_functional_state_t enNewState); + +int32_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, + uint16_t *pu16Ecr, float32_t *pf32A, + uint32_t u32Timeout); + +float32_t OTS_CalculateTemp(void); + +/** + * @} + */ + +#endif /* LL_OTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_OTS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_pwc.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_pwc.h new file mode 100644 index 0000000000..ad089eb6ab --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_pwc.h @@ -0,0 +1,628 @@ +/** + ******************************************************************************* + * @file hc32_ll_pwc.h + * @brief This file contains all the functions prototypes of the PWC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_PWC_H__ +#define __HC32_LL_PWC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_PWC + * @{ + */ + +#if (LL_PWC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup PWC_Global_Types PWC Global Types + * @{ + */ +/** + * @brief PWC LVD Init + */ +typedef struct { + uint32_t u32State; /*!< LVD function setting, @ref PWC_LVD_Config for details */ + uint32_t u32CompareOutputState; /*!< LVD compare output function setting, @ref PWC_LVD_CMP_Config for details */ + uint32_t u32ExceptionType; /*!< LVD interrupt or reset selection, @ref PWC_LVD_Exception_Type_Sel for details */ + uint32_t u32Filter; /*!< LVD digital filter function setting, @ref PWC_LVD_DF_Config for details */ + uint32_t u32FilterClock; /*!< LVD digital filter clock setting, @ref PWC_LVD_DFS_Clk_Sel for details */ + uint32_t u32ThresholdVoltage; /*!< LVD detect voltage setting, @ref PWC_LVD_Detection_Voltage_Sel for details */ +} stc_pwc_lvd_init_t; + +/** + * @brief PWC LVD Init + */ +typedef struct { + uint8_t u8Mode; /*!< Power down mode, @ref PWC_PDMode_Sel for details. */ + uint8_t u8IOState; /*!< IO state in power down mode, @ref PWC_PDMode_IO_Sel for details. */ + uint8_t u8VcapCtrl; /*!< Power down Wakeup time control, @ref PWC_PD_VCAP_Sel for details. */ +} stc_pwc_pd_mode_config_t; + +/** + * @brief PWC Stop mode Init + */ +typedef struct { + uint16_t u16Clock; /*!< System clock setting after wake-up from stop mode, + @ref PWC_STOP_CLK_Sel for details. */ + uint8_t u8StopDrv; /*!< Stop mode drive capacity, + @ref PWC_STOP_DRV_Sel for details. */ + uint16_t u16FlashWait; /*!< Waiting flash stable after wake-up from stop mode, + @ref STOP_FLASH_WAIT_Sel for details. */ +} stc_pwc_stop_mode_config_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup PWC_Global_Macros PWC Global Macros + * @{ + */ + +/** + * @defgroup PWC_PDMode_Sel Power down mode selection + * @{ + */ +#define PWC_PD_MD1 (0x00U) /*!< Power down mode 1 */ +#define PWC_PD_MD2 (0x01U) /*!< Power down mode 2 */ +#define PWC_PD_MD3 (0x02U) /*!< Power down mode 3 */ +#define PWC_PD_MD4 (0x03U) /*!< Power down mode 4 */ +/** + * @} + */ + +/** + * @defgroup PWC_PDMode_IO_Sel IO state config in Power down mode + * @{ + */ +#define PWC_PD_IO_KEEP1 (0x00U) /*!< IO state retain in PD mode and configurable after wakeup */ +#define PWC_PD_IO_KEEP2 (PWC_PWRC0_IORTN_0) /*!< IO state retain in PD mode and configurable after wakeup & set IORTN[1:0]=00b */ +#define PWC_PD_IO_HIZ (PWC_PWRC0_IORTN_1) /*!< IO state switch to HiZ */ +/** + * @} + */ + +/** + * @defgroup PWC_PD_VCAP_Sel Wakeup speed config in Power down mode + * @{ + */ +#define PWC_PD_VCAP_0P1UF (0x00U) /*!< VCAP1/VCAP2 = 0.1uF x2 or 0.22uF x1 */ +#define PWC_PD_VCAP_0P047UF (0x01U) /*!< VCAP1/VCAP2 = 0.047uF x2 or 0.1uF x1 */ +/** + * @} + */ + +/** + * @defgroup PWC_STOP_DRV_Sel Drive capacity while enter stop mode + * @{ + */ +#define PWC_STOP_DRV_HIGH (0x00U) /*!< Enter stop mode from high speed mode */ +#define PWC_STOP_DRV_LOW (PWC_PWRC1_STPDAS) /*!< Enter stop mode from ultra low speed mode */ +/** + * @} + */ + +/** + * @defgroup PWC_STOP_CLK_Sel System clock setting after wake-up from stop mode + * @{ + */ +#define PWC_STOP_CLK_KEEP (0x00U) /*!< Keep System clock setting after wake-up from stop mode */ +#define PWC_STOP_CLK_MRC (PWC_STPMCR_CKSMRC) /*!< System clock switch to MRC after wake-up from stop mode */ + +/** + * @} + */ + +/** + * @defgroup STOP_FLASH_WAIT_Sel Whether wait flash stable or not after wake-up from stop mode + * @{ + */ +#define PWC_STOP_FLASH_WAIT_ON (0x00U) /*!< Wait flash stable after wake-up from stop mode */ +#define PWC_STOP_FLASH_WAIT_OFF (PWC_STPMCR_FLNWT) /*!< Don't wait flash stable after wake-up from stop mode */ +/** + * @} + */ + +/** + * @defgroup PWC_RAM_Config Operating mode for RAM Config + * @{ + */ +#define PWC_RAM_HIGH_SPEED (0x8043U) /*!< MCU operating under high frequency (lower than 240MHz) */ +#define PWC_RAM_ULOW_SPEED (0x9062U) /*!< MCU operating under ultra low frequency (lower than 8MHz) */ +/** + * @} + */ + +/** + * @defgroup PWC_PD_Periph_Ram Peripheral ram to power down + * @{ + */ +#define PWC_RAM_PD_SRAM1 (PWC_RAMPC0_RAMPDC0) +#define PWC_RAM_PD_SRAM2 (PWC_RAMPC0_RAMPDC1) +#define PWC_RAM_PD_SRAM3 (PWC_RAMPC0_RAMPDC2) +#define PWC_RAM_PD_SRAMH (PWC_RAMPC0_RAMPDC3) +#define PWC_RAM_PD_USBFS (PWC_RAMPC0_RAMPDC4) +#define PWC_RAM_PD_SDIO0 (PWC_RAMPC0_RAMPDC5) +#define PWC_RAM_PD_SDIO1 (PWC_RAMPC0_RAMPDC6) +#define PWC_RAM_PD_CACHE (PWC_RAMPC0_RAMPDC8) +#define PWC_RAM_PD_CAN (PWC_RAMPC0_RAMPDC7) +#define PWC_RAM_PD_ALL (0x1FFU) + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Channel PWC LVD channel + * @{ + */ +#define PWC_LVD_CH1 (0x00U) +#define PWC_LVD_CH2 (0x01U) +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Config PWC LVD Config + * @{ + */ +#define PWC_LVD_ON (PWC_PVDCR0_PVD1EN) +#define PWC_LVD_OFF (0x00U) +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Exception_Type_Sel PWC LVD Exception Type Select + * @{ + */ +#define PWC_LVD_EXP_TYPE_NONE (0x00U) +#define PWC_LVD_EXP_TYPE_INT (0x0101U) +#define PWC_LVD_EXP_TYPE_NMI (0x0001U) +#define PWC_LVD_EXP_TYPE_RST (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS) + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_CMP_Config PWC LVD Compare Config + * @{ + */ +#define PWC_LVD_CMP_OFF (0x00U) +#define PWC_LVD_CMP_ON (PWC_PVDCR1_PVD1CMPOE) +/** + * @} + */ + +/** + * @defgroup PWC_LVD_DF_Config LVD digital filter ON or OFF + * @{ + */ +#define PWC_LVD_FILTER_ON (0x00U) +#define PWC_LVD_FILTER_OFF (0x01U) +/** + * @} + */ + +/** + * @defgroup PWC_LVD_DFS_Clk_Sel LVD digital filter sample ability + * @note modified this value must when PWC_LVD_FILTER_OFF + * @{ + */ +#define PWC_LVD_FILTER_LRC_DIV4 (0x00UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 0.25 LRC cycle */ +#define PWC_LVD_FILTER_LRC_DIV2 (0x01UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 0.5 LRC cycle */ +#define PWC_LVD_FILTER_LRC_DIV1 (0x02UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 1 LRC cycle */ +#define PWC_LVD_FILTER_LRC_MUL2 (0x03UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 2 LRC cycles */ + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Detection_Voltage_Sel PWC LVD Detection voltage + * @{ + * @note | HC32F472 || HC32F451,HC32F452 || || || +* | HC32F4A0 || HC32F460 || HC32M423/HC32M424 || HC32F120/HC32M120/HC32F160 || + * | LVD1 | LVD2 || LVD1 | LVD2 || LVD1 | LVD2 || LVD || + * LVL0 | 2.0V | 2.1V || 2.0V | 2.1V || 4.29V ~ 4.39V || 3.92V ~ 4.07V || + * LVL1 | 2.1V | 2.3V || 2.1V | 2.3V || 4.14V ~ 4.23V || 3.67V ~ 3.77V || + * LVL2 | 2.3V | 2.5V || 2.3V | 2.5V || 4.02V ~ 4.14V || 3.06V ~ 3.15V || + * LVL3 | 2.5V | 2.6V || 2.5V | 2.6V || 3.84V ~ 3.96V || 2.96V ~ 3.04V || + * LVL4 | 2.6V | 2.7V || 2.6V | 2.6V || 3.10V ~ 3.20V || 2.86V ~ 2.94V || + * LVL5 | 2.7V | 2.8V || 2.6V | 2.8V || 3.00V ~ 3.09V || 2.75V ~ 2.83V || + * LVL6 | 2.8V | 2.9V || 2.8V | 2.9V || 2.90V ~ 2.99V || 2.65V ~ 2.73V || + * LVL7 | 2.9V | --- || 2.9V | --- || 2.79V ~ 2.87V || 2.55V ~ 2.63V || + * LVL8 | --- | --- || --- | --- || 2.68V ~ 2.75V || 2.45V ~ 2.52V || + * LVL9 | --- | --- || --- | --- || 2.34V ~ 2.41V || 2.04V ~ 2.11V || + * LVL10 | --- | --- || --- | --- || 2.14V ~ 2.21V || 1.94V ~ 2.00V || + * LVL11 | --- | --- || --- | --- || 1.94V ~ 2.01V || 1.84V ~ 1.90V || + * LVL12 | --- | --- || --- | --- || 1.84V ~ 1.90V || ------------- || + * EXVCC | --- | EXVCC || --- | EXVC C || ---- | EXVCC || EXVCC || + */ +#define PWC_LVD_THRESHOLD_LVL0 (0x00U) +#define PWC_LVD_THRESHOLD_LVL1 (0x01U) +#define PWC_LVD_THRESHOLD_LVL2 (0x02U) +#define PWC_LVD_THRESHOLD_LVL3 (0x03U) +#define PWC_LVD_THRESHOLD_LVL4 (0x04U) +#define PWC_LVD_THRESHOLD_LVL5 (0x05U) +#define PWC_LVD_THRESHOLD_LVL6 (0x06U) +#define PWC_LVD_THRESHOLD_LVL7 (0x07U) +#define PWC_LVD_EXTVCC (0x07U) + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Flag LVD flag + * @{ + */ +#define PWC_LVD1_FLAG_DETECT (PWC_PVDDSR_PVD1DETFLG) /*!< VCC across VLVD1 */ +#define PWC_LVD2_FLAG_DETECT (PWC_PVDDSR_PVD2DETFLG) /*!< VCC across VLVD2 */ +#define PWC_LVD1_FLAG_MON (PWC_PVDDSR_PVD1MON) /*!< VCC > VLVD1 */ +#define PWC_LVD2_FLAG_MON (PWC_PVDDSR_PVD2MON) /*!< VCC > VLVD2 */ + +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Event_Sel Power down mode wakeup event selection + * @{ + */ +#define PWC_PD_WKUP0_POS (0U) +#define PWC_PD_WKUP1_POS (8U) +#define PWC_PD_WKUP2_POS (16U) +#define PWC_PD_WKUP_WKUP00 (PWC_PDWKE0_WKE00 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP01 (PWC_PDWKE0_WKE01 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP02 (PWC_PDWKE0_WKE02 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP03 (PWC_PDWKE0_WKE03 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP10 (PWC_PDWKE0_WKE10 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP11 (PWC_PDWKE0_WKE11 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP12 (PWC_PDWKE0_WKE12 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP13 (PWC_PDWKE0_WKE13 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP20 (PWC_PDWKE1_WKE20 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP21 (PWC_PDWKE1_WKE21 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP22 (PWC_PDWKE1_WKE22 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP23 (PWC_PDWKE1_WKE23 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP30 (PWC_PDWKE1_WKE30 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP31 (PWC_PDWKE1_WKE31 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP32 (PWC_PDWKE1_WKE32 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP33 (PWC_PDWKE1_WKE33 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_LVD1 (PWC_PDWKE2_VD1WKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_LVD2 (PWC_PDWKE2_VD2WKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_NMI (PWC_PDWKE2_NMIWKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_RTCPRD (PWC_PDWKE2_RTCPRDWKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_RTCALM (PWC_PDWKE2_RTCALMWKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_WKTM (PWC_PDWKE2_WKTMWKE << PWC_PD_WKUP2_POS) +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Trigger_Event_Sel Power down mode wakeup event selection to set trigger edge. + * @{ + */ +#define PWC_PD_WKUP_TRIG_LVD1 (PWC_PDWKES_VD1EGS) +#define PWC_PD_WKUP_TRIG_LVD2 (PWC_PDWKES_VD2EGS) +#define PWC_PD_WKUP_TRIG_WKUP0 (PWC_PDWKES_WK0EGS) +#define PWC_PD_WKUP_TRIG_WKUP1 (PWC_PDWKES_WK1EGS) +#define PWC_PD_WKUP_TRIG_WKUP2 (PWC_PDWKES_WK2EGS) +#define PWC_PD_WKUP_TRIG_WKUP3 (PWC_PDWKES_WK3EGS) + +#define PWC_PD_WKUP_TRIG_NMI (PWC_PDWKES_NMIEGS) +#define PWC_PD_WKUP_TRIG_ALL (PWC_PD_WKUP_TRIG_LVD1 | PWC_PD_WKUP_TRIG_LVD2 | PWC_PD_WKUP_TRIG_WKUP0 | \ + PWC_PD_WKUP_TRIG_WKUP1 | PWC_PD_WKUP_TRIG_WKUP2 | PWC_PD_WKUP_TRIG_WKUP3 | \ + PWC_PD_WKUP_TRIG_NMI) +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Trigger_Edge_Sel Power down mode wakeup trigger edge selection + * @{ + */ +#define PWC_PD_WKUP_TRIG_FALLING (0x00U) +#define PWC_PD_WKUP_TRIG_RISING (0x01U) +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Event_Flag_Sel Power down mode wakeup Event status selection + * @{ + */ +#define PWC_PD_WKUP_FLAG0_POS (0U) +#define PWC_PD_WKUP_FLAG1_POS (8U) +#define PWC_PD_WKUP_FLAG_WKUP0 (PWC_PDWKF0_PTWK0F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_WKUP1 (PWC_PDWKF0_PTWK1F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_WKUP2 (PWC_PDWKF0_PTWK2F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_WKUP3 (PWC_PDWKF0_PTWK3F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_LVD1 (PWC_PDWKF0_VD1WKF << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_LVD2 (PWC_PDWKF0_VD2WKF << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_NMI (PWC_PDWKF0_NMIWKF << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_RTCPRD (PWC_PDWKF1_RTCPRDWKF << PWC_PD_WKUP_FLAG1_POS) +#define PWC_PD_WKUP_FLAG_RTCALM (PWC_PDWKF1_RTCALMWKF << PWC_PD_WKUP_FLAG1_POS) +#define PWC_PD_WKUP_FLAG_WKTM (PWC_PDWKF1_WKTMWKF << PWC_PD_WKUP_FLAG1_POS) + +#define PWC_PD_WKUP_FLAG_ALL (PWC_PD_WKUP_FLAG_WKUP0 | PWC_PD_WKUP_FLAG_WKUP1 | PWC_PD_WKUP_FLAG_WKUP2 | \ + PWC_PD_WKUP_FLAG_WKUP3 | PWC_PD_WKUP_FLAG_LVD1 | PWC_PD_WKUP_FLAG_LVD2 | \ + PWC_PD_WKUP_FLAG_NMI | PWC_PD_WKUP_FLAG_RTCPRD | PWC_PD_WKUP_FLAG_RTCALM | \ + PWC_PD_WKUP_FLAG_WKTM) +/** + * @} + */ + +/** + * @defgroup PWC_Monitor_Power PWC Power Monitor voltage definition + * @{ + */ +#define PWC_PWR_MON_IREF (0x00U) /*!< Internal reference voltage */ +/** + * @} + */ + +/** + * @defgroup PWC_WKT_State PWC WKT State + * @{ + */ +#define PWC_WKT_OFF (0x00U) +#define PWC_WKT_ON (PWC_WKTCR_WKTCE) +/** + * @} + */ + +/** + * @defgroup PWC_WKT_Clock_Source PWC WKT Clock Source + * @{ + */ +#define PWC_WKT_CLK_SRC_64HZ ((0x00U << PWC_WKTCR_WKCKS_POS)) /*!< 64Hz Clock */ +#define PWC_WKT_CLK_SRC_XTAL32 ((0x01U << PWC_WKTCR_WKCKS_POS)) /*!< XTAL32 Clock */ +#define PWC_WKT_CLK_SRC_LRC ((0x02U << PWC_WKTCR_WKCKS_POS)) /*!< LRC Clock */ + +/** + * @} + */ + +/** + * @defgroup PWC_Ldo_Sel PWC LDO Selection + * @{ + */ +#define PWC_LDO_HRC (PWC_PWRC1_VHRCSD) +#define PWC_LDO_PLL (PWC_PWRC1_VPLLSD) +#define PWC_LDO_MASK (PWC_LDO_HRC | PWC_LDO_PLL) +/** + * @} + */ + +/** + * @defgroup PWC_REG_Write_Unlock_Code PWC register unlock code. + * @brief Lock/unlock Code for each module + * PWC_UNLOCK_CODE0: + * Below registers are locked in CLK module. + * XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR, + * MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR, + * SCFGR, USBCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR, + * XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM. + * PWC_UNLOCK_CODE1: + * Below registers are locked in PWC module. + * PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0, + * PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM. + * Below registers are locked in CLK module. + * PERICKSEL, I2SCKSEL, + * Below register is locked in RMU module. + * RSTF0 + * PWC_UNLOCK_CODE2: + * Below registers are locked in PWC module. + * PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR + * @{ + */ +#define PWC_WRITE_ENABLE (0xA500U) +#define PWC_UNLOCK_CODE0 (0xA501U) +#define PWC_UNLOCK_CODE1 (0xA502U) +#define PWC_UNLOCK_CODE2 (0xA508U) + +/** + * @brief PWC FCG0 Unlock/Lock code + */ +#define PWC_FCG0_REG_UNLOCK_KEY (0xA5A50001UL) +#define PWC_FCG0_REG_LOCK_KEY (0xA5A50000UL) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup PWC_Global_Functions + * @{ + */ +/** + * @brief Lock PWC, CLK, RMU register. + * @param [in] u16Module Lock code for each module. + * @arg PWC_UNLOCK_CODE0 + * @arg PWC_UNLOCK_CODE1 + * @arg PWC_UNLOCK_CODE2 + * @retval None + */ +__STATIC_INLINE void PWC_REG_Lock(uint16_t u16Module) +{ + CM_PWC->FPRC = (PWC_WRITE_ENABLE | (uint16_t)((uint16_t)(~u16Module) & (CM_PWC->FPRC))); +} + +/** + * @brief Unlock PWC, CLK, RMU register. + * @param [in] u16Module Unlock code for each module. + * @arg PWC_UNLOCK_CODE0 + * @arg PWC_UNLOCK_CODE1 + * @arg PWC_UNLOCK_CODE2 + * @retval None + */ +__STATIC_INLINE void PWC_REG_Unlock(uint16_t u16Module) +{ + SET_REG16_BIT(CM_PWC->FPRC, u16Module); +} + +/** + * @brief Lock PWC_FCG0 register . + * @param None + * @retval None + */ +__STATIC_INLINE void PWC_FCG0_REG_Lock(void) +{ + WRITE_REG32(CM_PWC->FCG0PC, PWC_FCG0_REG_LOCK_KEY); +} + +/** + * @brief Unlock PWR_FCG0 register. + * @param None + * @retval None + * @note Call this function before FCG_Fcg0PeriphClockCmd() + */ +__STATIC_INLINE void PWC_FCG0_REG_Unlock(void) +{ + WRITE_REG32(CM_PWC->FCG0PC, PWC_FCG0_REG_UNLOCK_KEY); +} + +/* PWC PD Function */ +void PWC_PD_Enter(void); +int32_t PWC_PD_StructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig); +int32_t PWC_PD_Config(const stc_pwc_pd_mode_config_t *pstcPDModeConfig); +void PWC_PD_WakeupCmd(uint32_t u32Event, en_functional_state_t enNewState); +void PWC_PD_SetWakeupTriggerEdge(uint8_t u8Event, uint8_t u8TrigEdge); +en_flag_status_t PWC_PD_GetWakeupStatus(uint16_t u16Flag); +void PWC_PD_ClearWakeupStatus(uint16_t u16Flag); +void PWC_PD_PeriphRamCmd(uint32_t u32PeriphRam, en_functional_state_t enNewState); +void PWC_PD_VdrCmd(en_functional_state_t enNewState); + +/* PWC WKTM Function */ +void PWC_WKT_Config(uint16_t u16ClkSrc, uint16_t u16CmpVal); +void PWC_WKT_SetCompareValue(uint16_t u16CmpVal); +uint16_t PWC_WKT_GetCompareValue(void); +void PWC_WKT_Cmd(en_functional_state_t enNewState); +en_flag_status_t PWC_WKT_GetStatus(void); +void PWC_WKT_ClearStatus(void); + +void PWC_RamModeConfig(uint16_t u16Mode); + +/* PWC Sleep Function */ +void PWC_SLEEP_Enter(void); + +/* PWC Stop Function */ +void PWC_STOP_Enter(void); +int32_t PWC_STOP_StructInit(stc_pwc_stop_mode_config_t *pstcStopConfig); +int32_t PWC_STOP_Config(const stc_pwc_stop_mode_config_t *pstcStopConfig); +void PWC_STOP_ClockSelect(uint8_t u8Clock); +void PWC_STOP_NvicBackup(void); +void PWC_STOP_NvicRecover(void); +void PWC_STOP_ClockBackup(void); +void PWC_STOP_ClockRecover(void); +void PWC_STOP_IrqClockBackup(void); +void PWC_STOP_IrqClockRecover(void); +void PWC_STOP_SetDrv(uint8_t u8StopDrv); +void PWC_STOP_FlashWaitCmd(en_functional_state_t enNewState); + +/* PWC Speed Switch Function */ +int32_t PWC_HighSpeedToLowSpeed(void); +int32_t PWC_LowSpeedToHighSpeed(void); +int32_t PWC_HighSpeedToHighPerformance(void); +int32_t PWC_HighPerformanceToHighSpeed(void); +int32_t PWC_LowSpeedToHighPerformance(void); +int32_t PWC_HighPerformanceToLowSpeed(void); + +/* PWC LDO Function */ +void PWC_LDO_Cmd(uint16_t u16Ldo, en_functional_state_t enNewState); + +/* PWC LVD Function, LVD for PVD while HC32F460, HC32F451, HC32F452 and HC32F4A0 */ +int32_t PWC_LVD_Init(uint8_t u8Ch, const stc_pwc_lvd_init_t *pstcLvdInit); +int32_t PWC_LVD_StructInit(stc_pwc_lvd_init_t *pstcLvdInit); +void PWC_LVD_Cmd(uint8_t u8Ch, en_functional_state_t enNewState); +void PWC_LVD_ExtInputCmd(en_functional_state_t enNewState); +void PWC_LVD_CompareOutputCmd(uint8_t u8Ch, en_functional_state_t enNewState); +void PWC_LVD_DigitalFilterCmd(uint8_t u8Ch, en_functional_state_t enNewState); +void PWC_LVD_SetFilterClock(uint8_t u8Ch, uint32_t u32Clock); +void PWC_LVD_SetThresholdVoltage(uint8_t u8Ch, uint32_t u32Voltage); +void PWC_LVD_ClearStatus(uint8_t u8Flag); +en_flag_status_t PWC_LVD_GetStatus(uint8_t u8Flag); + +/* PWC Power Monitor Function */ +void PWC_PowerMonitorCmd(en_functional_state_t enNewState); + +/* PWC RAM Function */ + +void PWC_XTAL32_PowerCmd(en_functional_state_t enNewState); +void PWC_RetSram_PowerCmd(en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_PWC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_PWC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_qspi.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_qspi.h new file mode 100644 index 0000000000..9b214659f1 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_qspi.h @@ -0,0 +1,445 @@ +/** + ******************************************************************************* + * @file hc32_ll_qspi.h + * @brief This file contains all the functions prototypes of the QSPI driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_QSPI_H__ +#define __HC32_LL_QSPI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_QSPI + * @{ + */ + +#if (LL_QSPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Types QSPI Global Types + * @{ + */ + +/** + * @brief QSPI initialization structure definition + */ +typedef struct { + uint32_t u32ClockDiv; /*!< Specifies the clock division. + This parameter can be a value of @ref QSPI_Clock_Division */ + uint32_t u32SpiMode; /*!< Specifies the SPI mode. + This parameter can be a value of @ref QSPI_SPI_Mode */ + uint32_t u32PrefetchMode; /*!< Specifies the prefetch mode. + This parameter can be a value of @ref QSPI_Prefetch_Mode */ + uint32_t u32ReadMode; /*!< Specifies the read mode. + This parameter can be a value of @ref QSPI_Read_Mode */ + uint32_t u32DummyCycle; /*!< Specifies the number of dummy cycles. + This parameter can be a value of @ref QSPI_Dummy_Cycle */ + uint32_t u32AddrWidth; /*!< Specifies the address width. + This parameter can be a value of @ref QSPI_Addr_Width */ + uint32_t u32SetupTime; /*!< Specifies the advance time of QSSN setup. + This parameter can be a value of @ref QSPI_QSSN_Setup_Time */ + uint32_t u32ReleaseTime; /*!< Specifies the delay time of QSSN release. + This parameter can be a value of @ref QSPI_QSSN_Release_Time */ + uint32_t u32IntervalTime; /*!< Specifies the minimum interval time of QSSN. + This parameter can be a value of @ref QSPI_QSSN_Interval_Time */ +} stc_qspi_init_t; + +/** + * @brief QSPI Custom read mode structure definition + */ +typedef struct { + uint32_t u32InstrProtocol; /*!< Specifies the instruction stage protocol. + This parameter can be a value of @ref QSPI_Instruction_Protocol */ + uint32_t u32AddrProtocol; /*!< Specifies the address stage protocol. + This parameter can be a value of @ref QSPI_Addr_Protocol */ + uint32_t u32DataProtocol; /*!< Specifies the data stage protocol. + This parameter can be a value of @ref QSPI_Data_Protocol */ + uint8_t u8InstrCode; /*!< Specifies the instruction code in custom read mode. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF */ +} stc_qspi_custom_mode_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Macros QSPI Global Macros + * @{ + */ + +/* QSPI memory mapping base and end address */ +#define QSPI_ROM_BASE (0x98000000UL) +#define QSPI_ROM_END (0x9BFFFFFFUL) + +/** + * @defgroup QSPI_Clock_Division QSPI Clock Division + * @{ + */ +#define QSPI_CLK_DIV2 (0x01UL << QSPI_CR_DIV_POS) /*!< Clock division by 2 */ +#define QSPI_CLK_DIV3 (0x02UL << QSPI_CR_DIV_POS) /*!< Clock division by 3 */ +#define QSPI_CLK_DIV4 (0x03UL << QSPI_CR_DIV_POS) /*!< Clock division by 4 */ +#define QSPI_CLK_DIV5 (0x04UL << QSPI_CR_DIV_POS) /*!< Clock division by 5 */ +#define QSPI_CLK_DIV6 (0x05UL << QSPI_CR_DIV_POS) /*!< Clock division by 6 */ +#define QSPI_CLK_DIV7 (0x06UL << QSPI_CR_DIV_POS) /*!< Clock division by 7 */ +#define QSPI_CLK_DIV8 (0x07UL << QSPI_CR_DIV_POS) /*!< Clock division by 8 */ +#define QSPI_CLK_DIV9 (0x08UL << QSPI_CR_DIV_POS) /*!< Clock division by 9 */ +#define QSPI_CLK_DIV10 (0x09UL << QSPI_CR_DIV_POS) /*!< Clock division by 10 */ +#define QSPI_CLK_DIV11 (0x0AUL << QSPI_CR_DIV_POS) /*!< Clock division by 11 */ +#define QSPI_CLK_DIV12 (0x0BUL << QSPI_CR_DIV_POS) /*!< Clock division by 12 */ +#define QSPI_CLK_DIV13 (0x0CUL << QSPI_CR_DIV_POS) /*!< Clock division by 13 */ +#define QSPI_CLK_DIV14 (0x0DUL << QSPI_CR_DIV_POS) /*!< Clock division by 14 */ +#define QSPI_CLK_DIV15 (0x0EUL << QSPI_CR_DIV_POS) /*!< Clock division by 15 */ +#define QSPI_CLK_DIV16 (0x0FUL << QSPI_CR_DIV_POS) /*!< Clock division by 16 */ +#define QSPI_CLK_DIV17 (0x10UL << QSPI_CR_DIV_POS) /*!< Clock division by 17 */ +#define QSPI_CLK_DIV18 (0x11UL << QSPI_CR_DIV_POS) /*!< Clock division by 18 */ +#define QSPI_CLK_DIV19 (0x12UL << QSPI_CR_DIV_POS) /*!< Clock division by 19 */ +#define QSPI_CLK_DIV20 (0x13UL << QSPI_CR_DIV_POS) /*!< Clock division by 20 */ +#define QSPI_CLK_DIV21 (0x14UL << QSPI_CR_DIV_POS) /*!< Clock division by 21 */ +#define QSPI_CLK_DIV22 (0x15UL << QSPI_CR_DIV_POS) /*!< Clock division by 22 */ +#define QSPI_CLK_DIV23 (0x16UL << QSPI_CR_DIV_POS) /*!< Clock division by 23 */ +#define QSPI_CLK_DIV24 (0x17UL << QSPI_CR_DIV_POS) /*!< Clock division by 24 */ +#define QSPI_CLK_DIV25 (0x18UL << QSPI_CR_DIV_POS) /*!< Clock division by 25 */ +#define QSPI_CLK_DIV26 (0x19UL << QSPI_CR_DIV_POS) /*!< Clock division by 26 */ +#define QSPI_CLK_DIV27 (0x1AUL << QSPI_CR_DIV_POS) /*!< Clock division by 27 */ +#define QSPI_CLK_DIV28 (0x1BUL << QSPI_CR_DIV_POS) /*!< Clock division by 28 */ +#define QSPI_CLK_DIV29 (0x1CUL << QSPI_CR_DIV_POS) /*!< Clock division by 29 */ +#define QSPI_CLK_DIV30 (0x1DUL << QSPI_CR_DIV_POS) /*!< Clock division by 30 */ +#define QSPI_CLK_DIV31 (0x1EUL << QSPI_CR_DIV_POS) /*!< Clock division by 31 */ +#define QSPI_CLK_DIV32 (0x1FUL << QSPI_CR_DIV_POS) /*!< Clock division by 32 */ +#define QSPI_CLK_DIV33 (0x20UL << QSPI_CR_DIV_POS) /*!< Clock division by 33 */ +#define QSPI_CLK_DIV34 (0x21UL << QSPI_CR_DIV_POS) /*!< Clock division by 34 */ +#define QSPI_CLK_DIV35 (0x22UL << QSPI_CR_DIV_POS) /*!< Clock division by 35 */ +#define QSPI_CLK_DIV36 (0x23UL << QSPI_CR_DIV_POS) /*!< Clock division by 36 */ +#define QSPI_CLK_DIV37 (0x24UL << QSPI_CR_DIV_POS) /*!< Clock division by 37 */ +#define QSPI_CLK_DIV38 (0x25UL << QSPI_CR_DIV_POS) /*!< Clock division by 38 */ +#define QSPI_CLK_DIV39 (0x26UL << QSPI_CR_DIV_POS) /*!< Clock division by 39 */ +#define QSPI_CLK_DIV40 (0x27UL << QSPI_CR_DIV_POS) /*!< Clock division by 40 */ +#define QSPI_CLK_DIV41 (0x28UL << QSPI_CR_DIV_POS) /*!< Clock division by 41 */ +#define QSPI_CLK_DIV42 (0x29UL << QSPI_CR_DIV_POS) /*!< Clock division by 42 */ +#define QSPI_CLK_DIV43 (0x2AUL << QSPI_CR_DIV_POS) /*!< Clock division by 43 */ +#define QSPI_CLK_DIV44 (0x2BUL << QSPI_CR_DIV_POS) /*!< Clock division by 44 */ +#define QSPI_CLK_DIV45 (0x2CUL << QSPI_CR_DIV_POS) /*!< Clock division by 45 */ +#define QSPI_CLK_DIV46 (0x2DUL << QSPI_CR_DIV_POS) /*!< Clock division by 46 */ +#define QSPI_CLK_DIV47 (0x2EUL << QSPI_CR_DIV_POS) /*!< Clock division by 47 */ +#define QSPI_CLK_DIV48 (0x2FUL << QSPI_CR_DIV_POS) /*!< Clock division by 48 */ +#define QSPI_CLK_DIV49 (0x30UL << QSPI_CR_DIV_POS) /*!< Clock division by 49 */ +#define QSPI_CLK_DIV50 (0x31UL << QSPI_CR_DIV_POS) /*!< Clock division by 50 */ +#define QSPI_CLK_DIV51 (0x32UL << QSPI_CR_DIV_POS) /*!< Clock division by 51 */ +#define QSPI_CLK_DIV52 (0x33UL << QSPI_CR_DIV_POS) /*!< Clock division by 52 */ +#define QSPI_CLK_DIV53 (0x34UL << QSPI_CR_DIV_POS) /*!< Clock division by 53 */ +#define QSPI_CLK_DIV54 (0x35UL << QSPI_CR_DIV_POS) /*!< Clock division by 54 */ +#define QSPI_CLK_DIV55 (0x36UL << QSPI_CR_DIV_POS) /*!< Clock division by 55 */ +#define QSPI_CLK_DIV56 (0x37UL << QSPI_CR_DIV_POS) /*!< Clock division by 56 */ +#define QSPI_CLK_DIV57 (0x38UL << QSPI_CR_DIV_POS) /*!< Clock division by 57 */ +#define QSPI_CLK_DIV58 (0x39UL << QSPI_CR_DIV_POS) /*!< Clock division by 58 */ +#define QSPI_CLK_DIV59 (0x3AUL << QSPI_CR_DIV_POS) /*!< Clock division by 59 */ +#define QSPI_CLK_DIV60 (0x3BUL << QSPI_CR_DIV_POS) /*!< Clock division by 60 */ +#define QSPI_CLK_DIV61 (0x3CUL << QSPI_CR_DIV_POS) /*!< Clock division by 61 */ +#define QSPI_CLK_DIV62 (0x3DUL << QSPI_CR_DIV_POS) /*!< Clock division by 62 */ +#define QSPI_CLK_DIV63 (0x3EUL << QSPI_CR_DIV_POS) /*!< Clock division by 63 */ +#define QSPI_CLK_DIV64 (0x3FUL << QSPI_CR_DIV_POS) /*!< Clock division by 64 */ +/** + * @} + */ + +/** + * @defgroup QSPI_SPI_Mode QSPI SPI Mode + * @{ + */ +#define QSPI_SPI_MD0 (0UL) /*!< Selects SPI mode 0 */ +#define QSPI_SPI_MD3 (QSPI_CR_SPIMD3) /*!< Selects SPI mode 3 */ +/** + * @} + */ + +/** + * @defgroup QSPI_Prefetch_Mode QSPI Prefetch Mode + * @{ + */ +#define QSPI_PREFETCH_MD_INVD (0UL) /*!< Disable prefetch */ +#define QSPI_PREFETCH_MD_EDGE_STOP (QSPI_CR_PFE) /*!< Stop prefetch at the edge of byte */ +#define QSPI_PREFETCH_MD_IMMED_STOP (QSPI_CR_PFE | QSPI_CR_PFSAE) /*!< Stop prefetch at current position immediately */ +/** + * @} + */ + +/** + * @defgroup QSPI_Read_Mode QSPI Read Mode + * @{ + */ +#define QSPI_RD_MD_STD_RD (0UL) /*!< Standard read mode (no dummy cycles) */ +#define QSPI_RD_MD_FAST_RD (0x01UL << QSPI_CR_MDSEL_POS) /*!< Fast read mode (dummy cycles between address and data) */ +#define QSPI_RD_MD_DUAL_OUTPUT_FAST_RD (0x02UL << QSPI_CR_MDSEL_POS) /*!< Fast read dual output mode (data on 2 lines) */ +#define QSPI_RD_MD_DUAL_IO_FAST_RD (0x03UL << QSPI_CR_MDSEL_POS) /*!< Fast read dual I/O mode (address and data on 2 lines) */ +#define QSPI_RD_MD_QUAD_OUTPUT_FAST_RD (0x04UL << QSPI_CR_MDSEL_POS) /*!< Fast read quad output mode (data on 4 lines) */ +#define QSPI_RD_MD_QUAD_IO_FAST_RD (0x05UL << QSPI_CR_MDSEL_POS) /*!< Fast read quad I/O mode (address and data on 4 lines) */ +#define QSPI_RD_MD_CUSTOM_STANDARD_RD (0x06UL << QSPI_CR_MDSEL_POS) /*!< Custom standard read mode */ +#define QSPI_RD_MD_CUSTOM_FAST_RD (0x07UL << QSPI_CR_MDSEL_POS) /*!< Custom fast read mode */ +/** + * @} + */ + +/** + * @defgroup QSPI_Dummy_Cycle QSPI Dummy Cycle + * @{ + */ +#define QSPI_DUMMY_CYCLE3 (0UL) /*!< Dummy cycle is 3 */ +#define QSPI_DUMMY_CYCLE4 (0x01UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 4 */ +#define QSPI_DUMMY_CYCLE5 (0x02UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 5 */ +#define QSPI_DUMMY_CYCLE6 (0x03UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 6 */ +#define QSPI_DUMMY_CYCLE7 (0x04UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 7 */ +#define QSPI_DUMMY_CYCLE8 (0x05UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 8 */ +#define QSPI_DUMMY_CYCLE9 (0x06UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 9 */ +#define QSPI_DUMMY_CYCLE10 (0x07UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 10 */ +#define QSPI_DUMMY_CYCLE11 (0x08UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 11 */ +#define QSPI_DUMMY_CYCLE12 (0x09UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 12 */ +#define QSPI_DUMMY_CYCLE13 (0x0AUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 13 */ +#define QSPI_DUMMY_CYCLE14 (0x0BUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 14 */ +#define QSPI_DUMMY_CYCLE15 (0x0CUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 15 */ +#define QSPI_DUMMY_CYCLE16 (0x0DUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 16 */ +#define QSPI_DUMMY_CYCLE17 (0x0EUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 15 */ +#define QSPI_DUMMY_CYCLE18 (0x0FUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 16 */ +/** + * @} + */ + +/** + * @defgroup QSPI_Addr_Width QSPI Address Width + * @{ + */ +#define QSPI_ADDR_WIDTH_8BIT (0x0U) /*!< QSPI address width is 8 bits */ +#define QSPI_ADDR_WIDTH_16BIT (QSPI_FCR_AWSL_0) /*!< QSPI address width is 16 bits */ +#define QSPI_ADDR_WIDTH_24BIT (QSPI_FCR_AWSL_1) /*!< QSPI address width is 24 bits */ +#define QSPI_ADDR_WIDTH_32BIT_INSTR_24BIT (QSPI_FCR_AWSL) /*!< QSPI address width is 32 bits and don't use 4-byte address read instruction code */ +#define QSPI_ADDR_WIDTH_32BIT_INSTR_32BIT (QSPI_FCR_AWSL | QSPI_FCR_FOUR_BIC) /*!< QSPI address width is 32 bits and use 4-byte address read instruction code */ +/** + * @} + */ + +/** + * @defgroup QSPI_QSSN_Setup_Time QSPI QSSN Setup Time + * @{ + */ +#define QSPI_QSSN_SETUP_ADVANCE_QSCK0P5 (0UL) /*!< Output QSSN signal 0.5 QSCK before the first rising edge of QSCK */ +#define QSPI_QSSN_SETUP_ADVANCE_QSCK1P5 (QSPI_FCR_SSNLD) /*!< Output QSSN signal 1.5 QSCK before the first rising edge of QSCK */ +/** + * @} + */ + +/** + * @defgroup QSPI_QSSN_Release_Time QSPI QSSN Release Time + * @{ + */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK0P5 (0UL) /*!< Release QSSN signal 0.5 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK1P5 (QSPI_FCR_SSNHD) /*!< Release QSSN signal 1.5 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK32 (QSPI_CSCR_SSNW_0 << 8U) /*!< Release QSSN signal 32 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK128 (QSPI_CSCR_SSNW_1 << 8U) /*!< Release QSSN signal 128 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_INFINITE (QSPI_CSCR_SSNW << 8U) /*!< Never release QSSN signal after the last rising edge of QSCK */ +/** + * @} + */ + +/** + * @defgroup QSPI_QSSN_Interval_Time QSPI QSSN Interval Time + * @{ + */ +#define QSPI_QSSN_INTERVAL_QSCK1 (0UL) /*!< Minimum interval time is 1 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK2 (0x01UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 2 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK3 (0x02UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 3 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK4 (0x03UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 4 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK5 (0x04UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 5 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK6 (0x05UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 6 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK7 (0x06UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 7 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK8 (0x07UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 8 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK9 (0x08UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 9 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK10 (0x09UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 10 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK11 (0x0AUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 11 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK12 (0x0BUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 12 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK13 (0x0CUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 13 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK14 (0x0DUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 14 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK15 (0x0EUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 15 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK16 (0x0FUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 16 QSCK */ +/** + * @} + */ + +/** + * @defgroup QSPI_Instruction_Protocol QSPI Instruction Protocol + * @{ + */ +#define QSPI_INSTR_PROTOCOL_1LINE (0x0U) /*!< Instruction on 1 line */ +#define QSPI_INSTR_PROTOCOL_2LINE (QSPI_CR_IPRSL_0) /*!< Instruction on 2 lines */ +#define QSPI_INSTR_PROTOCOL_4LINE (QSPI_CR_IPRSL_1) /*!< Instruction on 4 lines */ +/** + * @} + */ + +/** + * @defgroup QSPI_Addr_Protocol QSPI Address Protocol + * @{ + */ +#define QSPI_ADDR_PROTOCOL_1LINE (0x0U) /*!< Address on 1 line */ +#define QSPI_ADDR_PROTOCOL_2LINE (QSPI_CR_APRSL_0) /*!< Address on 2 lines */ +#define QSPI_ADDR_PROTOCOL_4LINE (QSPI_CR_APRSL_1) /*!< Address on 4 lines */ +/** + * @} + */ + +/** + * @defgroup QSPI_Data_Protocol QSPI Data Protocol + * @{ + */ +#define QSPI_DATA_PROTOCOL_1LINE (0x0U) /*!< Data on 1 line */ +#define QSPI_DATA_PROTOCOL_2LINE (QSPI_CR_DPRSL_0) /*!< Data on 2 lines */ +#define QSPI_DATA_PROTOCOL_4LINE (QSPI_CR_DPRSL_1) /*!< Data on 4 lines */ +/** + * @} + */ + +/** + * @defgroup QSPI_WP_Pin_Level QSPI WP Pin Level + * @{ + */ +#define QSPI_WP_PIN_LOW (0x0U) /*!< WP(QSIO2) pin output low */ +#define QSPI_WP_PIN_HIGH (QSPI_FCR_WPOL) /*!< WP(QSIO2) pin output high */ +/** + * @} + */ + +/** + * @defgroup QSPI_Status_Flag QSPI Status Flag + * @{ + */ +#define QSPI_FLAG_DIRECT_COMM_BUSY (QSPI_SR_BUSY) /*!< Serial transfer being processed */ +#define QSPI_FLAG_XIP_MD (QSPI_SR_XIPF) /*!< XIP mode */ +#define QSPI_FLAG_ROM_ACCESS_ERR (QSPI_SR_RAER) /*!< ROM access detection status in direct communication mode */ +#define QSPI_FLAG_PREFETCH_BUF_FULL (QSPI_SR_PFFUL) /*!< Prefetch buffer is full */ +#define QSPI_FLAG_PREFETCH_STOP (QSPI_SR_PFAN) /*!< Prefetch function operating */ + +#define QSPI_FLAG_ALL (QSPI_FLAG_DIRECT_COMM_BUSY | QSPI_FLAG_XIP_MD | \ + QSPI_FLAG_ROM_ACCESS_ERR | QSPI_FLAG_PREFETCH_BUF_FULL | \ + QSPI_FLAG_PREFETCH_STOP) +#define QSPI_FLAG_CLR_ALL (QSPI_FLAG_ROM_ACCESS_ERR) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup QSPI_Global_Functions + * @{ + */ + +/** + * @brief Write data in direct communication mode. + * @param [in] u8Value Byte data. + * @retval None + */ +__STATIC_INLINE void QSPI_WriteDirectCommValue(uint8_t u8Value) +{ + WRITE_REG32(CM_QSPI->DCOM, u8Value); +} + +/** + * @brief Read data in communication mode. + * @param None + * @retval uint8_t Byte data. + */ +__STATIC_INLINE uint8_t QSPI_ReadDirectCommValue(void) +{ + return (uint8_t)CM_QSPI->DCOM; +} + +/* Initialization and configuration functions */ +void QSPI_DeInit(void); +int32_t QSPI_Init(const stc_qspi_init_t *pstcQspiInit); +int32_t QSPI_StructInit(stc_qspi_init_t *pstcQspiInit); +void QSPI_SetWpPinLevel(uint32_t u32Level); +void QSPI_SetPrefetchMode(uint32_t u32Mode); +void QSPI_SelectMemoryBlock(uint8_t u8Block); +void QSPI_SetReadMode(uint32_t u32Mode); +int32_t QSPI_CustomReadConfig(const stc_qspi_custom_mode_t *pstcCustomMode); +void QSPI_XipModeCmd(uint8_t u8ModeCode, en_functional_state_t enNewState); + +/* Transfer and receive data functions */ +void QSPI_EnterDirectCommMode(void); +void QSPI_ExitDirectCommMode(void); +void QSPI_WriteDirectCommValue(uint8_t u8Value); +uint8_t QSPI_ReadDirectCommValue(void); + +/* Interrupt and flag management functions */ +uint8_t QSPI_GetPrefetchBufSize(void); +en_flag_status_t QSPI_GetStatus(uint32_t u32Flag); +void QSPI_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_QSPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_QSPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rmu.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rmu.h new file mode 100644 index 0000000000..a3320fd9ef --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rmu.h @@ -0,0 +1,127 @@ +/** + ******************************************************************************* + * @file hc32_ll_rmu.h + * @brief This file contains all the functions prototypes of the RMU driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_RMU_H__ +#define __HC32_LL_RMU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_RMU + * @{ + */ +#if (LL_RMU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RMU_Global_Macros RMU Global Macros + * @{ + */ + +/** + * @defgroup RMU_ResetCause Rmu reset cause + * @{ + */ +#define RMU_FLAG_PWR_ON (RMU_RSTF0_PORF) /*!< Power on reset */ +#define RMU_FLAG_PIN (RMU_RSTF0_PINRF) /*!< Reset pin reset */ +#define RMU_FLAG_BROWN_OUT (RMU_RSTF0_BORF) /*!< Brown-out reset */ +#define RMU_FLAG_PVD1 (RMU_RSTF0_PVD1RF) /*!< Program voltage Detection 1 reset */ +#define RMU_FLAG_PVD2 (RMU_RSTF0_PVD2RF) /*!< Program voltage Detection 2 reset */ +#define RMU_FLAG_WDT (RMU_RSTF0_WDRF) /*!< Watchdog timer reset */ +#define RMU_FLAG_SWDT (RMU_RSTF0_SWDRF) /*!< Special watchdog timer reset */ +#define RMU_FLAG_PWR_DOWN (RMU_RSTF0_PDRF) /*!< Power down reset */ +#define RMU_FLAG_SW (RMU_RSTF0_SWRF) /*!< Software reset */ +#define RMU_FLAG_MPU_ERR (RMU_RSTF0_MPUERF) /*!< Mpu error reset */ +#define RMU_FLAG_RAM_PARITY_ERR (RMU_RSTF0_RAPERF) /*!< Ram parity error reset */ +#define RMU_FLAG_RAM_ECC (RMU_RSTF0_RAECRF) /*!< Ram ECC reset */ +#define RMU_FLAG_CLK_ERR (RMU_RSTF0_CKFERF) /*!< Clk frequency error reset */ +#define RMU_FLAG_XTAL_ERR (RMU_RSTF0_XTALERF) /*!< Xtal error reset */ +#define RMU_FLAG_MX (RMU_RSTF0_MULTIRF) /*!< Multiply reset cause */ +#define RMU_FLAG_ALL (RMU_FLAG_PWR_ON | RMU_FLAG_PIN | RMU_FLAG_BROWN_OUT | RMU_FLAG_PVD1 | \ + RMU_FLAG_PVD2 | RMU_FLAG_WDT | RMU_FLAG_SWDT | RMU_FLAG_PWR_DOWN | \ + RMU_FLAG_SW | RMU_FLAG_MPU_ERR | RMU_FLAG_RAM_PARITY_ERR | RMU_FLAG_RAM_ECC | \ + RMU_FLAG_CLK_ERR | RMU_FLAG_XTAL_ERR | RMU_FLAG_MX) + +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup RMU_Global_Functions + * @{ + */ + +en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause); +void RMU_ClearStatus(void); + +/** + * @} + */ + +#endif /* LL_RMU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_RMU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rtc.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rtc.h new file mode 100644 index 0000000000..db76812ea6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rtc.h @@ -0,0 +1,366 @@ +/** + ******************************************************************************* + * @file hc32_ll_rtc.h + * @brief This file contains all the functions prototypes of the RTC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_RTC_H__ +#define __HC32_LL_RTC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_RTC + * @{ + */ + +#if (LL_RTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Types RTC Global Types + * @{ + */ + +/** + * @brief RTC Init structure definition + */ +typedef struct { + uint8_t u8ClockSrc; /*!< Specifies the RTC clock source. + This parameter can be a value of @ref RTC_Clock_Source */ + uint8_t u8HourFormat; /*!< Specifies the RTC hour format. + This parameter can be a value of @ref RTC_Hour_Format */ + uint8_t u8IntPeriod; /*!< Specifies the RTC interrupt period. + This parameter can be a value of @ref RTC_Interrupt_Period */ + uint8_t u8ClockCompen; /*!< Specifies the validity of RTC clock compensation. + This parameter can be a value of @ref RTC_Clock_Compensation */ + uint8_t u8CompenMode; /*!< Specifies the mode of RTC clock compensation. + This parameter can be a value of @ref RTC_Clock_Compensation_Mode */ + uint16_t u16CompenValue; /*!< Specifies the value of RTC clock compensation. + This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF */ +} stc_rtc_init_t; + +/** + * @brief RTC Date structure definition + */ +typedef struct { + uint8_t u8Year; /*!< Specifies the RTC Year. + This parameter can be a number between Min_Data = 0 and Max_Data = 99 */ + uint8_t u8Month; /*!< Specifies the RTC Month (in Decimal format). + This parameter can be a value of @ref RTC_Month */ + uint8_t u8Day; /*!< Specifies the RTC Day. + This parameter can be a number between Min_Data = 1 and Max_Data = 31 */ + uint8_t u8Weekday; /*!< Specifies the RTC Weekday. + This parameter can be a value of @ref RTC_Weekday */ +} stc_rtc_date_t; + +/** + * @brief RTC Time structure definition + */ +typedef struct { + uint8_t u8Hour; /*!< Specifies the RTC Hour. + This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected. + This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected */ + uint8_t u8Minute; /*!< Specifies the RTC Minute. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + uint8_t u8Second; /*!< Specifies the RTC Second. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + uint8_t u8AmPm; /*!< Specifies the RTC Am/Pm Time (in RTC_HOUR_FMT_12H mode). + This parameter can be a value of @ref RTC_Hour12_AM_PM */ +} stc_rtc_time_t; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct { + uint8_t u8AlarmHour; /*!< Specifies the RTC Alarm Hour. + This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected. + This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected */ + uint8_t u8AlarmMinute; /*!< Specifies the RTC Alarm Minute. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + uint8_t u8AlarmWeekday; /*!< Specifies the RTC Alarm Weekday. + This parameter can be a value of @ref RTC_Alarm_Weekday */ + uint8_t u8AlarmAmPm; /*!< Specifies the RTC Alarm Am/Pm Time (in RTC_HOUR_FMT_12H mode). + This parameter can be a value of @ref RTC_Hour12_AM_PM */ +} stc_rtc_alarm_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Macros RTC Global Macros + * @{ + */ + +/** + * @defgroup RTC_Data_Format RTC Data Format + * @{ + */ +#define RTC_DATA_FMT_DEC (0x00U) /*!< Decimal data format */ +#define RTC_DATA_FMT_BCD (0x01U) /*!< BCD data format */ +/** + * @} + */ + +/** + * @defgroup RTC_Decimal_BCD_Conversion RTC Decimal BCD Conversion + * @{ + */ +#define RTC_DEC2BCD(__DATA__) ((((__DATA__) / 10U) << 4U) + ((__DATA__) % 10U)) +#define RTC_BCD2DEC(__DATA__) ((((__DATA__) >> 4U) * 10U) + ((__DATA__) & 0x0FU)) +/** + * @} + */ + +/** + * @defgroup RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RTC_CLK_SRC_XTAL32 (0U) /*!< XTAL32 Clock */ +#define RTC_CLK_SRC_LRC (RTC_CR3_RCKSEL | RTC_CR3_LRCEN) /*!< RTC LRC Clock */ +/** + * @} + */ + +/** + * @defgroup RTC_Hour_Format RTC Hour Format + * @{ + */ +#define RTC_HOUR_FMT_12H (0U) /*!< 12 hour time system */ +#define RTC_HOUR_FMT_24H (RTC_CR1_AMPM) /*!< 24 hour time system */ +/** + * @} + */ + +/** + * @defgroup RTC_Interrupt_Period RTC Interrupt Period + * @{ + */ +#define RTC_INT_PERIOD_INVD (0U) /*!< Interrupt period invalid */ +#define RTC_INT_PERIOD_PER_HALF_SEC (0x01U << RTC_CR1_PRDS_POS) /*!< Interrupt period per half second */ +#define RTC_INT_PERIOD_PER_SEC (0x02U << RTC_CR1_PRDS_POS) /*!< Interrupt period per second */ +#define RTC_INT_PERIOD_PER_MINUTE (0x03U << RTC_CR1_PRDS_POS) /*!< Interrupt period per minute */ +#define RTC_INT_PERIOD_PER_HOUR (0x04U << RTC_CR1_PRDS_POS) /*!< Interrupt period per hour */ +#define RTC_INT_PERIOD_PER_DAY (0x05U << RTC_CR1_PRDS_POS) /*!< Interrupt period per day */ +#define RTC_INT_PERIOD_PER_MONTH (0x06U << RTC_CR1_PRDS_POS) /*!< Interrupt period per month */ +/** + * @} + */ + +/** + * @defgroup RTC_Clock_Compensation RTC Clock Compensation + * @{ + */ +#define RTC_CLK_COMPEN_DISABLE (0U) +#define RTC_CLK_COMPEN_ENABLE (RTC_ERRCRH_COMPEN) +/** + * @} + */ + +/** + * @defgroup RTC_Clock_Compensation_Mode RTC Clock Compensation Mode + * @{ + */ +#define RTC_CLK_COMPEN_MD_DISTRIBUTED (0U) /*!< Distributed compensation 1Hz output */ +#define RTC_CLK_COMPEN_MD_UNIFORM (RTC_CR1_ONEHZSEL) /*!< Uniform compensation 1Hz output */ +/** + * @} + */ + +/** + * @defgroup RTC_Hour12_AM_PM RTC Hour12 AM/PM + * @{ + */ +#define RTC_HOUR_24H (0U) /*!< 24-hour format */ +#define RTC_HOUR_12H_AM (0U) /*!< AM in 12-hour */ +#define RTC_HOUR_12H_PM (RTC_HOUR_HOURD_1) /*!< PM in 12-hour */ +/** + * @} + */ + +/** + * @defgroup RTC_Month RTC Month + * @{ + */ +#define RTC_MONTH_JANUARY (0x01U) +#define RTC_MONTH_FEBRUARY (0x02U) +#define RTC_MONTH_MARCH (0x03U) +#define RTC_MONTH_APRIL (0x04U) +#define RTC_MONTH_MAY (0x05U) +#define RTC_MONTH_JUNE (0x06U) +#define RTC_MONTH_JULY (0x07U) +#define RTC_MONTH_AUGUST (0x08U) +#define RTC_MONTH_SEPTEMBER (0x09U) +#define RTC_MONTH_OCTOBER (0x0AU) +#define RTC_MONTH_NOVEMBER (0x0BU) +#define RTC_MONTH_DECEMBER (0x0CU) +/** + * @} + */ + +/** + * @defgroup RTC_Weekday RTC Weekday + * @{ + */ +#define RTC_WEEKDAY_SUNDAY (0x00U) +#define RTC_WEEKDAY_MONDAY (0x01U) +#define RTC_WEEKDAY_TUESDAY (0x02U) +#define RTC_WEEKDAY_WEDNESDAY (0x03U) +#define RTC_WEEKDAY_THURSDAY (0x04U) +#define RTC_WEEKDAY_FRIDAY (0x05U) +#define RTC_WEEKDAY_SATURDAY (0x06U) +/** + * @} + */ + +/** + * @defgroup RTC_Alarm_Weekday RTC Alarm Weekday + * @{ + */ +#define RTC_ALARM_WEEKDAY_SUNDAY (0x01U) +#define RTC_ALARM_WEEKDAY_MONDAY (0x02U) +#define RTC_ALARM_WEEKDAY_TUESDAY (0x04U) +#define RTC_ALARM_WEEKDAY_WEDNESDAY (0x08U) +#define RTC_ALARM_WEEKDAY_THURSDAY (0x10U) +#define RTC_ALARM_WEEKDAY_FRIDAY (0x20U) +#define RTC_ALARM_WEEKDAY_SATURDAY (0x40U) +#define RTC_ALARM_WEEKDAY_EVERYDAY (0x7FU) +/** + * @} + */ + +/** + * @defgroup RTC_Flag RTC Flag + * @{ + */ +#define RTC_FLAG_RD_WR (RTC_CR2_RWEN) /*!< Read and write permission flag */ +#define RTC_FLAG_ALARM (RTC_CR2_ALMF) /*!< Alarm flag */ + +#define RTC_FLAG_ALL (RTC_FLAG_RD_WR | RTC_FLAG_ALARM) +#define RTC_FLAG_CLR_ALL (RTC_FLAG_ALARM) +/** + * @} + */ + +/** + * @defgroup RTC_Interrupt RTC Interrupt + * @{ + */ +#define RTC_INT_PERIOD (RTC_CR2_PRDIE) /*!< Period interrupt */ +#define RTC_INT_ALARM (RTC_CR2_ALMIE) /*!< Alarm interrupt */ + +#define RTC_INT_ALL (RTC_INT_PERIOD | RTC_INT_ALARM) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup RTC_Global_Functions + * @{ + */ + +/* Initialization and configuration functions */ +int32_t RTC_DeInit(void); +int32_t RTC_Init(const stc_rtc_init_t *pstcRtcInit); +int32_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit); +int32_t RTC_EnterRwMode(void); +int32_t RTC_ExitRwMode(void); + +/* Control configuration */ +int32_t RTC_ConfirmLPMCond(void); +void RTC_SetIntPeriod(uint8_t u8Period); +void RTC_SetClockSrc(uint8_t u8Src); +void RTC_SetClockCompenValue(uint16_t u16Value); +en_functional_state_t RTC_GetCounterState(void); +void RTC_Cmd(en_functional_state_t enNewState); +void RTC_LrcCmd(en_functional_state_t enNewState); +void RTC_OneHzOutputCmd(en_functional_state_t enNewState); +void RTC_ClockCompenCmd(en_functional_state_t enNewState); + +/* Date and time functions */ +int32_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate); +int32_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate); +int32_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime); +int32_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime); + +/* Alarm configuration functions */ +int32_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm); +int32_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm); +void RTC_AlarmCmd(en_functional_state_t enNewState); + +/* Interrupt and flag management functions */ +void RTC_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t RTC_GetStatus(uint32_t u32Flag); +void RTC_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_RTC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_RTC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sdioc.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sdioc.h new file mode 100644 index 0000000000..4e2efabdb4 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sdioc.h @@ -0,0 +1,763 @@ +/** + ******************************************************************************* + * @file hc32_ll_sdioc.h + * @brief This file contains all the functions prototypes of the SDIOC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SDIOC_H__ +#define __HC32_LL_SDIOC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SDIOC + * @{ + */ + +#if (LL_SDIOC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup SDIOC_Global_Types SDIOC Global Types + * @{ + */ + +/** + * @brief SDIOC Init structure definition + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies the SDIOC work mode. + This parameter can be a value of @ref SDIOC_Mode */ + uint8_t u8CardDetect; /*!< Specifies the SDIOC card detect way. + This parameter can be a value of @ref SDIOC_Card_Detect_Way */ + uint8_t u8SpeedMode; /*!< Specifies the SDIOC speed mode. + This parameter can be a value of @ref SDIOC_Speed_Mode */ + uint8_t u8BusWidth; /*!< Specifies the SDIOC bus width. + This parameter can be a value of @ref SDIOC_Bus_Width */ + uint16_t u16ClockDiv; /*!< Specifies the SDIOC clock division. + This parameter can be a value of @ref SDIOC_Clock_Division */ +} stc_sdioc_init_t; + +/** + * @brief SDIOC Command Configuration structure definition + */ +typedef struct { + uint32_t u32Argument; /*!< Specifies the SDIOC command argument. */ + uint16_t u16CmdIndex; /*!< Specifies the SDIOC command index. + This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ + uint16_t u16CmdType; /*!< Specifies the SDIOC command type. + This parameter can be a value of @ref SDIOC_Command_Type */ + uint16_t u16DataLine; /*!< Specifies whether SDIOC uses data lines in current command. + This parameter can be a value of @ref SDIOC_Data_Line_Valid */ + uint16_t u16ResponseType; /*!< Specifies the SDIOC response type. + This parameter can be a value of @ref SDIOC_Response_Type */ +} stc_sdioc_cmd_config_t; + +/** + * @brief SDIOC Data Configuration structure definition + */ +typedef struct { + uint16_t u16BlockSize; /*!< Specifies the SDIOC data block size. + This parameter must be a number between Min_Data = 1 and Max_Data = 512 */ + uint16_t u16BlockCount; /*!< Specifies the SDIOC data block count. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF */ + uint16_t u16TransDir; /*!< Specifies the SDIOC data transfer direction. + This parameter can be a value of @ref SDIOC_Transfer_Direction */ + uint16_t u16AutoCmd12; /*!< Specifies the validity of the SDIOC Auto Send CMD12. + This parameter can be a value of @ref SDIOC_Auto_Send_CMD12 */ + uint16_t u16TransMode; /*!< Specifies the SDIOC data transfer mode. + This parameter can be a value of @ref SDIOC_Transfer_Mode */ + uint8_t u16DataTimeout; /*!< Specifies the SDIOC data timeout time. + This parameter can be a value of @ref SDIOC_Data_Timeout_Time */ +} stc_sdioc_data_config_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SDIOC_Global_Macros SDIOC Global Macros + * @{ + */ + +/** + * @defgroup SDIOC_Mode SDIOC Mode + * @{ + */ +#define SDIOC_MD_SD (0x00UL) /*!< SDIOCx selects SD mode */ +#define SDIOC_MD_MMC (0x01UL) /*!< SDIOCx selects MMC mode */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Card_Detect_Way SDIOC Card Detect Way + * @{ + */ +#define SDIOC_CARD_DETECT_CD_PIN_LVL (0x00U) /*!< SDIOCx_CD(x=1~2) line is selected (for normal use) */ +#define SDIOC_CARD_DETECT_TEST_SIGNAL (SDIOC_HOSTCON_CDSS) /*!< The Card Detect Test Level is selected(for test purpose) */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Card_Detect_Test_Level SDIOC Card Detect Test Level + * @{ + */ +#define SDIOC_CARD_DETECT_TEST_LVL_LOW (0x00U) /*!< Card identification test signal is low level (with device insertion) */ +#define SDIOC_CARD_DETECT_TEST_LVL_HIGH (SDIOC_HOSTCON_CDTL) /*!< Card identification test signal is high level (no device insertion) */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Speed_Mode SDIOC Speed Mode + * @{ + */ +#define SDIOC_SPEED_MD_NORMAL (0x00U) /*!< Normal speed mode */ +#define SDIOC_SPEED_MD_HIGH (SDIOC_HOSTCON_HSEN) /*!< High speed mode */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Bus_Width SDIOC Bus Width + * @{ + */ +#define SDIOC_BUS_WIDTH_1BIT (0x00U) /*!< The Bus width is 1 bit */ +#define SDIOC_BUS_WIDTH_4BIT (SDIOC_HOSTCON_DW) /*!< The Bus width is 4 bit */ +#define SDIOC_BUS_WIDTH_8BIT (SDIOC_HOSTCON_EXDW) /*!< The Bus width is 8 bit */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Clock_Division SDIOC Clock Division + * @{ + */ +#define SDIOC_CLK_DIV1 (0x00U) /*!< CLK1/1 */ +#define SDIOC_CLK_DIV2 (SDIOC_CLKCON_FS_0) /*!< CLK1/2 */ +#define SDIOC_CLK_DIV4 (SDIOC_CLKCON_FS_1) /*!< CLK1/4 */ +#define SDIOC_CLK_DIV8 (SDIOC_CLKCON_FS_2) /*!< CLK1/8 */ +#define SDIOC_CLK_DIV16 (SDIOC_CLKCON_FS_3) /*!< CLK1/16 */ +#define SDIOC_CLK_DIV32 (SDIOC_CLKCON_FS_4) /*!< CLK1/32 */ +#define SDIOC_CLK_DIV64 (SDIOC_CLKCON_FS_5) /*!< CLK1/64 */ +#define SDIOC_CLK_DIV128 (SDIOC_CLKCON_FS_6) /*!< CLK1/128 */ +#define SDIOC_CLK_DIV256 (SDIOC_CLKCON_FS_7) /*!< CLK1/256 */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Command_Type SDIOC Command Type + * @{ + */ +#define SDIOC_CMD_TYPE_NORMAL (0x00U) /*!< Other commands */ +#define SDIOC_CMD_TYPE_SUSPEND (SDIOC_CMD_TYP_0) /*!< CMD52 for writing "Bus Suspend" in CCCR */ +#define SDIOC_CMD_TYPE_RESUME (SDIOC_CMD_TYP_1) /*!< CMD52 for writing "Function Select" in CCCR */ +#define SDIOC_CMD_TYPE_ABORT (SDIOC_CMD_TYP) /*!< CMD12, CMD52 for writing "I/O Abort" in CCCR */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Data_Line_Valid SDIOC Data Line Valid + * @{ + */ +#define SDIOC_DATA_LINE_DISABLE (0x00U) /*!< The current command uses only SDIOCx_CMD(x=1~2) command line */ +#define SDIOC_DATA_LINE_ENABLE (SDIOC_CMD_DAT) /*!< The current command requires the use of SDIOCx_Dy(x=1~2) data line */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Transfer_Direction SDIOC Transfer Direction + * @{ + */ +#define SDIOC_TRANS_DIR_TO_CARD (0x00U) /*!< Write (Host to Card) */ +#define SDIOC_TRANS_DIR_TO_HOST (SDIOC_TRANSMODE_DDIR) /*!< Read (Card to Host) */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Auto_Send_CMD12 SDIOC Auto Send CMD12 + * @{ + */ +#define SDIOC_AUTO_SEND_CMD12_DISABLE (0x00U) /*!< Do not send autocommands */ +#define SDIOC_AUTO_SEND_CMD12_ENABLE (SDIOC_TRANSMODE_ATCEN_0) /*!< CMD12 is automatically sent after multiple block transfers */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Transfer_Mode SDIOC Transfer Mode + * @{ + */ +#define SDIOC_TRANS_MD_SINGLE (0x00U) /*!< Single Block transfer */ +#define SDIOC_TRANS_MD_INFINITE (SDIOC_TRANSMODE_MULB) /*!< Infinite Block transfer */ +#define SDIOC_TRANS_MD_MULTI (SDIOC_TRANSMODE_MULB | SDIOC_TRANSMODE_BCE) /*!< Multiple Block transfer */ +#define SDIOC_TRANS_MD_STOP_MULTI (0x8000U | SDIOC_TRANS_MD_MULTI) /*!< Stop Multiple Block transfer */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Data_Timeout_Time SDIOC Data Timeout Time + * @{ + */ +#define SDIOC_DATA_TIMEOUT_CLK_2E13 (0x00U) /*!< Timeout time: CLK1*2^13 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E14 (0x01U) /*!< Timeout time: CLK1*2^14 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E15 (0x02U) /*!< Timeout time: CLK1*2^15 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E16 (0x03U) /*!< Timeout time: CLK1*2^16 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E17 (0x04U) /*!< Timeout time: CLK1*2^17 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E18 (0x05U) /*!< Timeout time: CLK1*2^18 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E19 (0x06U) /*!< Timeout time: CLK1*2^19 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E20 (0x07U) /*!< Timeout time: CLK1*2^20 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E21 (0x08U) /*!< Timeout time: CLK1*2^21 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E22 (0x09U) /*!< Timeout time: CLK1*2^22 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E23 (0x0AU) /*!< Timeout time: CLK1*2^23 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E24 (0x0BU) /*!< Timeout time: CLK1*2^24 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E25 (0x0CU) /*!< Timeout time: CLK1*2^25 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E26 (0x0DU) /*!< Timeout time: CLK1*2^26 */ +#define SDIOC_DATA_TIMEOUT_CLK_2E27 (0x0EU) /*!< Timeout time: CLK1*2^27 */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Response_Register SDIOC Response Register + * @{ + */ +#define SDIOC_RESP_REG_BIT0_31 (0x00U) /*!< Command Response Register 0-31bit */ +#define SDIOC_RESP_REG_BIT32_63 (0x04U) /*!< Command Response Register 32-63bit */ +#define SDIOC_RESP_REG_BIT64_95 (0x08U) /*!< Command Response Register 64-95bit */ +#define SDIOC_RESP_REG_BIT96_127 (0x0CU) /*!< Command Response Register 96-127bit */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Software_Reset_Type SDIOC Software Reset Type + * @{ + */ +#define SDIOC_SW_RST_DATA_LINE (SDIOC_SFTRST_RSTD) /*!< Only part of data circuit is reset */ +#define SDIOC_SW_RST_CMD_LINE (SDIOC_SFTRST_RSTC) /*!< Only part of command circuit is reset */ +#define SDIOC_SW_RST_ALL (SDIOC_SFTRST_RSTA) /*!< Reset the entire Host Controller except for the card detection circuit */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Output_Clock_Frequency SDIOC Output Clock Frequency + * @{ + */ +#define SDIOC_OUTPUT_CLK_FREQ_400K (400000UL) /*!< SDIOC clock: 400KHz */ +#define SDIOC_OUTPUT_CLK_FREQ_25M (25000000UL) /*!< SDIOC clock: 25MHz */ +#define SDIOC_OUTPUT_CLK_FREQ_26M (26000000UL) /*!< SDIOC clock: 26MHz */ +#define SDIOC_OUTPUT_CLK_FREQ_50M (50000000UL) /*!< SDIOC clock: 50MHz */ +#define SDIOC_OUTPUT_CLK_FREQ_52M (52000000UL) /*!< SDIOC clock: 52MHz */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Host_Flag SDIOC Host Flag + * @{ + */ +#define SDIOC_HOST_FLAG_CMDL (SDIOC_PSTAT_CMDL) /*!< CMD Line Level status */ +#define SDIOC_HOST_FLAG_DATL (SDIOC_PSTAT_DATL) /*!< DAT[3:0] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D0 (SDIOC_PSTAT_DATL_0) /*!< DAT[0] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D1 (SDIOC_PSTAT_DATL_1) /*!< DAT[1] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D2 (SDIOC_PSTAT_DATL_2) /*!< DAT[2] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D3 (SDIOC_PSTAT_DATL_3) /*!< DAT[3] Line Level status */ +#define SDIOC_HOST_FLAG_WPL (SDIOC_PSTAT_WPL) /*!< Write Protect Line Level status */ +#define SDIOC_HOST_FLAG_CDL (SDIOC_PSTAT_CDL) /*!< Card Detect Line Level status */ +#define SDIOC_HOST_FLAG_CSS (SDIOC_PSTAT_CSS) /*!< Device Stable Status */ +#define SDIOC_HOST_FLAG_CIN (SDIOC_PSTAT_CIN) /*!< Device Inserted status */ +#define SDIOC_HOST_FLAG_BRE (SDIOC_PSTAT_BRE) /*!< Data buffer full status */ +#define SDIOC_HOST_FLAG_BWE (SDIOC_PSTAT_BWE) /*!< Data buffer empty status */ +#define SDIOC_HOST_FLAG_RTA (SDIOC_PSTAT_RTA) /*!< Read operation status */ +#define SDIOC_HOST_FLAG_WTA (SDIOC_PSTAT_WTA) /*!< Write operation status */ +#define SDIOC_HOST_FLAG_DA (SDIOC_PSTAT_DA) /*!< DAT Line transfer status */ +#define SDIOC_HOST_FLAG_CID (SDIOC_PSTAT_CID) /*!< Command Inhibit with data status */ +#define SDIOC_HOST_FLAG_CIC (SDIOC_PSTAT_CIC) /*!< Command Inhibit status */ +#define SDIOC_HOST_FLAG_ALL (SDIOC_HOST_FLAG_CMDL | SDIOC_HOST_FLAG_DATL | SDIOC_HOST_FLAG_WPL | \ + SDIOC_HOST_FLAG_CDL | SDIOC_HOST_FLAG_CSS | SDIOC_HOST_FLAG_CIN | \ + SDIOC_HOST_FLAG_BRE | SDIOC_HOST_FLAG_BWE | SDIOC_HOST_FLAG_RTA | \ + SDIOC_HOST_FLAG_WTA | SDIOC_HOST_FLAG_DA | SDIOC_HOST_FLAG_CID | \ + SDIOC_HOST_FLAG_CIC) +/** + * @} + */ + +/** + * @defgroup SDIOC_Interrupt_Flag SDIOC Interrupt Flag + * @{ + */ +#define SDIOC_INT_FLAG_EI (SDIOC_NORINTST_EI) /*!< Error Interrupt Status */ +#define SDIOC_INT_FLAG_CINT (SDIOC_NORINTST_CINT) /*!< Card Interrupt status */ +#define SDIOC_INT_FLAG_CRM (SDIOC_NORINTST_CRM) /*!< Card Removal status */ +#define SDIOC_INT_FLAG_CIST (SDIOC_NORINTST_CIST) /*!< Card Insertion status */ +#define SDIOC_INT_FLAG_BRR (SDIOC_NORINTST_BRR) /*!< Buffer Read Ready status */ +#define SDIOC_INT_FLAG_BWR (SDIOC_NORINTST_BWR) /*!< Buffer Write Ready status */ +#define SDIOC_INT_FLAG_BGE (SDIOC_NORINTST_BGE) /*!< Block Gap Event status */ +#define SDIOC_INT_FLAG_TC (SDIOC_NORINTST_TC) /*!< Transfer Complete status */ +#define SDIOC_INT_FLAG_CC (SDIOC_NORINTST_CC) /*!< Command Complete status */ +#define SDIOC_INT_FLAG_ACE ((uint32_t)SDIOC_ERRINTST_ACE << 16U) /*!< Auto CMD12 Error Status */ +#define SDIOC_INT_FLAG_DEBE ((uint32_t)SDIOC_ERRINTST_DEBE << 16U) /*!< Data End Bit Error status */ +#define SDIOC_INT_FLAG_DCE ((uint32_t)SDIOC_ERRINTST_DCE << 16U) /*!< Data CRC Error status */ +#define SDIOC_INT_FLAG_DTOE ((uint32_t)SDIOC_ERRINTST_DTOE << 16U) /*!< Data Timeout Error status */ +#define SDIOC_INT_FLAG_CIE ((uint32_t)SDIOC_ERRINTST_CIE << 16U) /*!< Command Index Error status */ +#define SDIOC_INT_FLAG_CEBE ((uint32_t)SDIOC_ERRINTST_CEBE << 16U) /*!< Command End Bit Error status */ +#define SDIOC_INT_FLAG_CCE ((uint32_t)SDIOC_ERRINTST_CCE << 16U) /*!< Command CRC Error status */ +#define SDIOC_INT_FLAG_CTOE ((uint32_t)SDIOC_ERRINTST_CTOE << 16U) /*!< Command Timeout Error status */ +#define SDIOC_INT_STATIC_FLAGS (SDIOC_INT_FLAG_ACE | SDIOC_INT_FLAG_DEBE | SDIOC_INT_FLAG_DCE | \ + SDIOC_INT_FLAG_DTOE | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | \ + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE | SDIOC_INT_FLAG_TC | \ + SDIOC_INT_FLAG_CC) +#define SDIOC_NORMAL_INT_FLAG_ALL (SDIOC_INT_FLAG_EI | SDIOC_INT_FLAG_CINT | SDIOC_INT_FLAG_CRM | \ + SDIOC_INT_FLAG_CIST | SDIOC_INT_FLAG_BRR | SDIOC_INT_FLAG_BWR | \ + SDIOC_INT_FLAG_BGE | SDIOC_INT_FLAG_TC | SDIOC_INT_FLAG_CC) +#define SDIOC_ERR_INT_FLAG_ALL (SDIOC_INT_FLAG_ACE | SDIOC_INT_FLAG_DEBE | SDIOC_INT_FLAG_DCE | \ + SDIOC_INT_FLAG_DTOE | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | \ + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE) +#define SDIOC_INT_FLAG_ALL (SDIOC_NORMAL_INT_FLAG_ALL | SDIOC_ERR_INT_FLAG_ALL) +#define SDIOC_INT_FLAG_CLR_ALL (SDIOC_INT_FLAG_CRM | SDIOC_INT_FLAG_CIST | SDIOC_INT_FLAG_BRR | \ + SDIOC_INT_FLAG_BWR | SDIOC_INT_FLAG_BGE | SDIOC_INT_FLAG_TC | \ + SDIOC_INT_FLAG_CC | SDIOC_ERR_INT_FLAG_ALL) +/** + * @} + */ + +/** + * @defgroup SDIOC_Interrupt SDIOC Interrupt + * @{ + */ +#define SDIOC_INT_CINTSEN (SDIOC_NORINTSGEN_CINTSEN) /*!< Card Interrupt */ +#define SDIOC_INT_CRMSEN (SDIOC_NORINTSGEN_CRMSEN) /*!< Card Removal Interrupt */ +#define SDIOC_INT_CISTSEN (SDIOC_NORINTSGEN_CISTSEN) /*!< Card Insertion Interrupt */ +#define SDIOC_INT_BRRSEN (SDIOC_NORINTSGEN_BRRSEN) /*!< Buffer Read Ready Interrupt */ +#define SDIOC_INT_BWRSEN (SDIOC_NORINTSGEN_BWRSEN) /*!< Buffer Write Ready Interrupt */ +#define SDIOC_INT_BGESEN (SDIOC_NORINTSGEN_BGESEN) /*!< Block Gap Event Interrupt */ +#define SDIOC_INT_TCSEN (SDIOC_NORINTSGEN_TCSEN) /*!< Transfer Complete Interrupt */ +#define SDIOC_INT_CCSEN (SDIOC_NORINTSGEN_CCSEN) /*!< Command Complete Interrupt */ +#define SDIOC_INT_ACESEN ((uint32_t)SDIOC_ERRINTSGEN_ACESEN << 16U) /*!< Auto CMD12 Error Interrupt */ +#define SDIOC_INT_DEBESEN ((uint32_t)SDIOC_ERRINTSGEN_DEBESEN << 16U) /*!< Data End Bit Error Interrupt */ +#define SDIOC_INT_DCESEN ((uint32_t)SDIOC_ERRINTSGEN_DCESEN << 16U) /*!< Data CRC Error Interrupt */ +#define SDIOC_INT_DTOESEN ((uint32_t)SDIOC_ERRINTSGEN_DTOESEN << 16U) /*!< Data Timeout Error Interrupt */ +#define SDIOC_INT_CIESEN ((uint32_t)SDIOC_ERRINTSGEN_CIESEN << 16U) /*!< Command Index Error Interrupt */ +#define SDIOC_INT_CEBESEN ((uint32_t)SDIOC_ERRINTSGEN_CEBESEN << 16U) /*!< Command End Bit Error Interrupt */ +#define SDIOC_INT_CCESEN ((uint32_t)SDIOC_ERRINTSGEN_CCESEN << 16U) /*!< Command CRC Error Interrupt */ +#define SDIOC_INT_CTOESEN ((uint32_t)SDIOC_ERRINTSGEN_CTOESEN << 16U) /*!< Command Timeout Error Interrupt */ +#define SDIOC_NORMAL_INT_ALL (SDIOC_INT_CINTSEN | SDIOC_INT_CRMSEN | SDIOC_INT_CISTSEN | \ + SDIOC_INT_BRRSEN | SDIOC_INT_BWRSEN | SDIOC_INT_BGESEN | \ + SDIOC_INT_TCSEN | SDIOC_INT_CCSEN) +#define SDIOC_ERR_INT_ALL (SDIOC_INT_ACESEN | SDIOC_INT_DEBESEN | SDIOC_INT_DCESEN | \ + SDIOC_INT_DTOESEN | SDIOC_INT_CIESEN | SDIOC_INT_CEBESEN | \ + SDIOC_INT_CCESEN | SDIOC_INT_CTOESEN) +#define SDIOC_INT_ALL (SDIOC_NORMAL_INT_ALL | SDIOC_ERR_INT_ALL) +/** + * @} + */ + +/** + * @defgroup SDIOC_Auto_CMD_Error_Flag SDIOC Auto CMD Error Flag + * @{ + */ +#define SDIOC_AUTO_CMD_ERR_FLAG_CMDE (SDIOC_ATCERRST_CMDE) /*!< Command Not Issued By Auto CMD12 Error Status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_IE (SDIOC_ATCERRST_IE) /*!< Auto CMD12 Index Error status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_EBE (SDIOC_ATCERRST_EBE) /*!< Auto CMD12 End Bit Error status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_CE (SDIOC_ATCERRST_CE) /*!< Auto CMD12 CRC Error status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_TOE (SDIOC_ATCERRST_TOE) /*!< Auto CMD12 Timeout Error status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_NE (SDIOC_ATCERRST_NE) /*!< Auto CMD12 Not Executed status */ +#define SDIOC_AUTO_CMD_ERR_FLAG_ALL (SDIOC_AUTO_CMD_ERR_FLAG_CMDE | SDIOC_AUTO_CMD_ERR_FLAG_IE | \ + SDIOC_AUTO_CMD_ERR_FLAG_EBE | SDIOC_AUTO_CMD_ERR_FLAG_CE | \ + SDIOC_AUTO_CMD_ERR_FLAG_TOE | SDIOC_AUTO_CMD_ERR_FLAG_NE) +/** + * @} + */ + +/** + * @defgroup SDIOC_Force_Auto_CMD_Error SDIOC Force Auto CMD Error + * @{ + */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FCMDE (SDIOC_FEA_FCMDE) /*!< Force Event for Command Not Issued By Auto CMD12 Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FIE (SDIOC_FEA_FIE) /*!< Force Event for Auto CMD12 Index Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FEBE (SDIOC_FEA_FEBE) /*!< Force Event for Auto CMD12 End Bit Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FCE (SDIOC_FEA_FCE) /*!< Force Event for Auto CMD12 CRC Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FTOE (SDIOC_FEA_FTOE) /*!< Force Event for Auto CMD12 Timeout Error */ +#define SDIOC_FORCE_AUTO_CMD_ERR_FNE (SDIOC_FEA_FNE) /*!< Force Event for Auto CMD12 Not Executed */ +#define SDIOC_FORCE_AUTO_CMD_ERR_ALL (SDIOC_FORCE_AUTO_CMD_ERR_FCMDE | SDIOC_FORCE_AUTO_CMD_ERR_FIE | \ + SDIOC_FORCE_AUTO_CMD_ERR_FEBE | SDIOC_FORCE_AUTO_CMD_ERR_FCE | \ + SDIOC_FORCE_AUTO_CMD_ERR_FTOE | SDIOC_FORCE_AUTO_CMD_ERR_FNE) +/** + * @} + */ + +/** + * @defgroup SDIOC_Force_Error_Interrupt SDIOC Force Error Interrupt + * @{ + */ +#define SDIOC_FORCE_ERR_INT_FACE (SDIOC_FEE_FACE) /*!< Force Event for Auto CMD12 Error */ +#define SDIOC_FORCE_ERR_INT_FDEBE (SDIOC_FEE_FDEBE) /*!< Force Event for Data End Bit Error */ +#define SDIOC_FORCE_ERR_INT_FDCE (SDIOC_FEE_FDCE) /*!< Force Event for Data CRC Error */ +#define SDIOC_FORCE_ERR_INT_FDTOE (SDIOC_FEE_FDTOE) /*!< Force Event for Data Timeout Error */ +#define SDIOC_FORCE_ERR_INT_FCIE (SDIOC_FEE_FCIE) /*!< Force Event for Command Index Error */ +#define SDIOC_FORCE_ERR_INT_FCEBE (SDIOC_FEE_FCEBE) /*!< Force Event for Command End Bit Error */ +#define SDIOC_FORCE_ERR_INT_FCCE (SDIOC_FEE_FCCE) /*!< Force Event for Command CRC Error */ +#define SDIOC_FORCE_ERR_INT_FCTOE (SDIOC_FEE_FCTOE) /*!< Force Event for Command Timeout Error */ +#define SDIOC_FORCE_ERR_INT_ALL (SDIOC_FORCE_ERR_INT_FACE | SDIOC_FORCE_ERR_INT_FDEBE | \ + SDIOC_FORCE_ERR_INT_FDCE | SDIOC_FORCE_ERR_INT_FDTOE | \ + SDIOC_FORCE_ERR_INT_FCIE | SDIOC_FORCE_ERR_INT_FCEBE | \ + SDIOC_FORCE_ERR_INT_FCCE | SDIOC_FORCE_ERR_INT_FCTOE) +/** + * @} + */ + +/** + * @defgroup SDIOC_Response_Type SDIOC Response Type + * @{ + */ +#define SDIOC_RESP_TYPE_NO (0x00U) /*!< No Response */ +#define SDIOC_RESP_TYPE_R2 (SDIOC_CMD_RESTYP_0) /*!< Command Response 2 */ +#define SDIOC_RESP_TYPE_R3_R4 (SDIOC_CMD_RESTYP_1) /*!< Command Response 3, 4 */ +#define SDIOC_RESP_TYPE_R1_R5_R6_R7 (SDIOC_CMD_RESTYP_1 | SDIOC_CMD_ICE | SDIOC_CMD_CCE) /*!< Command Response 1, 5, 6, 7 */ +#define SDIOC_RESP_TYPE_R1B_R5B (SDIOC_CMD_RESTYP | SDIOC_CMD_ICE | SDIOC_CMD_CCE) /*!< Command Response 1 and 5 with busy */ +/** + * @} + */ + +#define SDIOC_CMD0_GO_IDLE_STATE (0U) /*!< Resets the SD memory card. */ +#define SDIOC_CMD1_SEND_OP_COND (1U) /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDIOC_CMD2_ALL_SEND_CID (2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDIOC_CMD3_SEND_RELATIVE_ADDR (3U) /*!< Asks the card to publish a new relative address (RCA). */ +#define SDIOC_CMD4_SET_DSR (4U) /*!< Programs the DSR of all cards. */ +#define SDIOC_CMD5_IO_SEND_OP_COND (5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its \ + operating condition register (OCR) content in the response on the CMD line. */ +#define SDIOC_CMD6_SWITCH_FUNC (6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDIOC_CMD7_SELECT_DESELECT_CARD (7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDIOC_CMD8_SEND_IF_COND (8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information \ + and asks the card whether card supports voltage. */ +#define SDIOC_CMD9_SEND_CSD (9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDIOC_CMD10_SEND_CID (10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDIOC_CMD11_READ_DAT_UNTIL_STOP (11U) /*!< SD card doesn't support it. */ +#define SDIOC_CMD12_STOP_TRANSMISSION (12U) /*!< Forces the card to stop transmission. */ +#define SDIOC_CMD13_SEND_STATUS (13U) /*!< Addressed card sends its status register. */ +#define SDIOC_CMD14_HS_BUSTEST_READ (14U) /*!< Reserved */ +#define SDIOC_CMD15_GO_INACTIVE_STATE (15U) /*!< Sends an addressed card into the inactive state. */ +#define SDIOC_CMD16_SET_BLOCKLEN (16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands(read, write). \ + Default block length is fixed to 512 Bytes. Not effective for SDHS and SDXC. */ +#define SDIOC_CMD17_READ_SINGLE_BLOCK (17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed \ + 512 bytes in case of SDHC and SDXC. */ +#define SDIOC_CMD18_READ_MULTI_BLOCK (18U) /*!< Continuously transfers data blocks from card to host until interrupted by \ + STOP_TRANSMISSION command. */ +#define SDIOC_CMD19_HS_BUSTEST_WRITE (19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDIOC_CMD20_WRITE_DAT_UNTIL_STOP (20U) /*!< Speed class control command. */ +#define SDIOC_CMD23_SET_BLOCK_COUNT (23U) /*!< Specify block count for CMD18 and CMD25. */ +#define SDIOC_CMD24_WRITE_SINGLE_BLOCK (24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed\ + 512 bytes in case of SDHC and SDXC. */ +#define SDIOC_CMD25_WRITE_MULTI_BLOCK (25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDIOC_CMD26_PROGRAM_CID (26U) /*!< Reserved for manufacturers. */ +#define SDIOC_CMD27_PROGRAM_CSD (27U) /*!< Programming of the programmable bits of the CSD. */ +#define SDIOC_CMD28_SET_WRITE_PROT (28U) /*!< Sets the write protection bit of the addressed group. */ +#define SDIOC_CMD29_CLR_WRITE_PROT (29U) /*!< Clears the write protection bit of the addressed group. */ +#define SDIOC_CMD30_SEND_WRITE_PROT (30U) /*!< Asks the card to send the status of the write protection bits. */ +#define SDIOC_CMD32_ERASE_WR_BLK_START (32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDIOC_CMD33_ERASE_WR_BLK_END (33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDIOC_CMD35_ERASE_GROUP_START (35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system \ + set by switch function command (CMD6). */ +#define SDIOC_CMD36_ERASE_GROUP_END (36U) /*!< Sets the address of the last write block of the continuous range to be erased. \ + Reserved for each command system set by switch function command (CMD6). */ +#define SDIOC_CMD38_ERASE (38U) /*!< Reserved for SD security applications. */ +#define SDIOC_CMD39_FAST_IO (39U) /*!< SD card doesn't support it (Reserved). */ +#define SDIOC_CMD40_GO_IRQ_STATE (40U) /*!< SD card doesn't support it (Reserved). */ +#define SDIOC_CMD42_LOCK_UNLOCK (42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by \ + the SET_BLOCK_LEN command. */ +#define SDIOC_CMD55_APP_CMD (55U) /*!< Indicates to the card that the next command is an application specific command rather \ + than a standard command. */ +#define SDIOC_CMD56_GEN_CMD (56U) /*!< Used either to transfer a data block to the card or to get a data block from the card \ + for general purpose/application specific commands. */ +#define SDIOC_CMD64_NO_CMD (64U) /*!< No command */ + +/** + * @brief Following commands are SD Card Specific commands. + * @note SDIOC_CMD55_APP_CMD should be sent before sending these commands. + */ +#define SDIOC_ACMD6_SET_BUS_WIDTH (6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus \ + widths are given in SCR register. */ +#define SDIOC_ACMD13_SD_STATUS (13U) /*!< (ACMD13) Sends the SD status. */ +#define SDIOC_ACMD22_SEND_NUM_WR_BLOCKS (22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with \ + 32bit+CRC data block. */ +#define SDIOC_ACMD23_SET_WR_BLK_ERASE_COUNT (23U) /*!< Set the number of write blocks to be pre-erased before writing (to be used for faster \ + Multiple Block WR com-mand). */ +#define SDIOC_ACMD41_SD_APP_OP_COND (41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to \ + send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDIOC_ACMD42_SET_CLR_CARD_DETECT (42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDIOC_ACMD51_SEND_SCR (51U) /*!< Reads the SD Configuration Register (SCR). */ +#define SDIOC_ACMD52_RW_DIRECT (52U) /*!< For SD I/O card only, reserved for security specification. */ +#define SDIOC_ACMD53_RW_EXTENDED (53U) /*!< For SD I/O card only, reserved for security specification. */ + +/** + * @brief Following commands are SD Card Specific security commands. + * @note SDIOC_CMD55_APP_CMD should be sent before sending these commands. + */ +#define SDIOC_ACMD43_GET_MKB (43U) +#define SDIOC_ACMD44_GET_MID (44U) +#define SDIOC_ACMD45_SET_CER_RN1 (45U) +#define SDIOC_ACMD46_GET_CER_RN2 (46U) +#define SDIOC_ACMD47_SET_CER_RES2 (47U) +#define SDIOC_ACMD48_GET_CER_RES1 (48U) +#define SDIOC_ACMD18_SECURE_READ_MULTI_BLOCK (18U) +#define SDIOC_ACMD25_SECURE_WRITE_MULTI_BLOCK (25U) +#define SDIOC_ACMD38_SECURE_ERASE (38U) +#define SDIOC_ACMD49_CHANGE_SECURE_AREA (49U) +#define SDIOC_ACMD48_SECURE_WRITE_MKB (48U) + +/** + * @defgroup SDMMC_Error_Code SDMMC Error Code + * @{ + */ +#define SDMMC_ERR_NONE (0x00000000UL) /*!< No error */ +#define SDMMC_ERR_ADDR_OUT_OF_RANGE (0x80000000UL) /*!< Error when addressed block is out of range */ +#define SDMMC_ERR_ADDR_MISALIGNED (0x40000000UL) /*!< Misaligned address */ +#define SDMMC_ERR_BLOCK_LEN_ERR (0x20000000UL) /*!< Transferred block length is not allowed for the card or the \ + number of transferred bytes does not match the block length */ +#define SDMMC_ERR_ERASE_SEQ_ERR (0x10000000UL) /*!< An error in the sequence of erase command occurs */ +#define SDMMC_ERR_BAD_ERASE_PARAM (0x08000000UL) /*!< An invalid selection for erase groups */ +#define SDMMC_ERR_WR_PROT_VIOLATION (0x04000000UL) /*!< Attempt to program a write protect block */ +#define SDMMC_ERR_LOCK_UNLOCK_FAILED (0x01000000UL) /*!< Sequence or password error has been detected in unlock command \ + or if there was an attempt to access a locked card */ +#define SDMMC_ERR_COM_CRC_FAILED (0x00800000UL) /*!< CRC check of the previous command failed */ +#define SDMMC_ERR_ILLEGAL_CMD (0x00400000UL) /*!< Command is not legal for the card state */ +#define SDMMC_ERR_CARD_ECC_FAILED (0x00200000UL) /*!< Card internal ECC was applied but failed to correct the data */ +#define SDMMC_ERR_CC_ERR (0x00100000UL) /*!< Internal card controller error */ +#define SDMMC_ERR_GENERAL_UNKNOWN_ERR (0x00080000UL) /*!< General or unknown error */ +#define SDMMC_ERR_STREAM_RD_UNDERRUN (0x00040000UL) /*!< The card could not sustain data reading in stream rmode */ +#define SDMMC_ERR_STREAM_WR_OVERRUN (0x00020000UL) /*!< The card could not sustain data programming in stream mode */ +#define SDMMC_ERR_CID_CSD_OVERWRITE (0x00010000UL) /*!< CID/CSD overwrite error */ +#define SDMMC_ERR_WP_ERASE_SKIP (0x00008000UL) /*!< Only partial address space was erased */ +#define SDMMC_ERR_CARD_ECC_DISABLED (0x00004000UL) /*!< Command has been executed without using internal ECC */ +#define SDMMC_ERR_ERASE_RST (0x00002000UL) /*!< Erase sequence was cleared before executing because an out of \ + erase sequence command was received */ +#define SDMMC_ERR_CMD_AUTO_SEND (0x00001000UL) /*!< An error occurred in sending the command automatically */ +#define SDMMC_ERR_CMD_INDEX (0x00000800UL) /*!< The received response contains a command number error */ +#define SDMMC_ERR_CMD_STOP_BIT (0x00000400UL) /*!< Command line detects low level at stop bit */ +#define SDMMC_ERR_CMD_CRC_FAIL (0x00000200UL) /*!< Command response received (but CRC check failed) */ +#define SDMMC_ERR_CMD_TIMEOUT (0x00000100UL) /*!< Command response timeout */ +#define SDMMC_ERR_SWITCH_ERR (0x00000080UL) /*!< The card did not switch to the expected mode as requested by \ + the SWITCH command */ +#define SDMMC_ERR_DATA_STOP_BIT (0x00000040UL) /*!< Data line detects low level at stop bit */ +#define SDMMC_ERR_DATA_CRC_FAIL (0x00000020UL) /*!< Data block sent/received (CRC check failed) */ +#define SDMMC_ERR_DATA_TIMEOUT (0x00000010UL) /*!< Data timeout */ +#define SDMMC_ERR_AKE_SEQ_ERR (0x00000008UL) /*!< Error in sequence of authentication */ +#define SDMMC_ERR_INVD_VOLT (0x00000004UL) /*!< Error in case of invalid voltage range */ +#define SDMMC_ERR_REQ_NOT_APPLICABLE (0x00000002UL) /*!< Error when command request is not applicable */ +#define SDMMC_ERR_UNSUPPORT_FEATURE (0x00000001UL) /*!< Error when feature is not insupported */ + +#define SDMMC_ERR_BITS_MASK (0xFDFFE048UL) /*!< SD/MMC Error status bits mask */ +/** + * @} + */ + +/** + * @defgroup SDMMC_Card_Status_Bit SDMMC Card Status Bit + * @{ + */ +#define SDMMC_STATUS_CARD_IS_LOCKED_POS (24U) +#define SDMMC_STATUS_CARD_IS_LOCKED (0x02000000UL) /*!< When set, signals that the card is locked by the host */ +#define SDMMC_STATUS_CURR_STATE_POS (9U) +#define SDMMC_STATUS_CURR_STATE (0x00001E00UL) /*!< The state of the card when receiving the command */ +#define SDMMC_STATUS_RDY_FOR_DATA_POS (8U) +#define SDMMC_STATUS_RDY_FOR_DATA (0x00000100UL) /*!< Corresponds to buffer empty signaling on the bus */ +#define SDMMC_STATUS_APP_CMD_POS (5U) +#define SDMMC_STATUS_APP_CMD (0x00000020UL) /*!< The card will expect ACMD, or an indication that the command has been interpreted as ACMD */ +/** + * @} + */ + +/** + * @defgroup SDMMC_SCR_Register SDMMC SCR Register + * @{ + */ +#define SDMMC_SCR_PHY_SPEC_VER_1P0 (0x00000000UL) +#define SDMMC_SCR_PHY_SPEC_VER_1P1 (0x01000000UL) +#define SDMMC_SCR_PHY_SPEC_VER_2P0 (0x02000000UL) +#define SDMMC_SCR_BUS_WIDTH_4BIT (0x00040000UL) +#define SDMMC_SCR_BUS_WIDTH_1BIT (0x00010000UL) +/** + * @} + */ + +/** + * @defgroup SDMMC_OCR_Register SDMMC OCR Register + * @{ + */ +#define SDMMC_OCR_HIGH_CAPACITY (0x40000000UL) +#define SDMMC_OCR_STD_CAPACITY (0x00000000UL) +/** + * @} + */ + +/** + * @defgroup SDMMC_CSD_Register SDMMC CSD Register + * @{ + */ +/* Command Class supported */ +#define SDMMC_CSD_SUPPORT_CLASS5_ERASE (0x00000020UL) +/** + * @} + */ + +/** + * @defgroup SDMMC_Common_Parameter SDMMC Common Parameter + * @{ + */ +#define SDMMC_DATA_TIMEOUT (0x0000FFFFUL) +#define SDMMC_MAX_VOLT_TRIAL (0x0000FFFFUL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SDIOC_Global_Functions + * @{ + */ +int32_t SDIOC_DeInit(CM_SDIOC_TypeDef *SDIOCx); +int32_t SDIOC_Init(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_init_t *pstcSdiocInit); +int32_t SDIOC_StructInit(stc_sdioc_init_t *pstcSdiocInit); +int32_t SDIOC_SWReset(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Type); +void SDIOC_PowerCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); +en_functional_state_t SDIOC_GetPowerState(const CM_SDIOC_TypeDef *SDIOCx); +uint32_t SDIOC_GetMode(const CM_SDIOC_TypeDef *SDIOCx); +void SDIOC_ClockCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); +void SDIOC_SetClockDiv(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Div); +int32_t SDIOC_GetOptimumClockDiv(uint32_t u32ClockFreq, uint16_t *pu16Div); +int32_t SDIOC_VerifyClockDiv(uint32_t u32Mode, uint8_t u8SpeedMode, uint16_t u16ClockDiv); +en_flag_status_t SDIOC_GetInsertStatus(const CM_SDIOC_TypeDef *SDIOCx); +void SDIOC_SetSpeedMode(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8SpeedMode); +void SDIOC_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8BusWidth); +void SDIOC_SetCardDetectSrc(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Src); +void SDIOC_SetCardDetectTestLevel(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Level); + +int32_t SDIOC_SendCommand(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_cmd_config_t *pstcCmdConfig); +int32_t SDIOC_CommandStructInit(stc_sdioc_cmd_config_t *pstcCmdConfig); +int32_t SDIOC_GetResponse(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Reg, uint32_t *pu32Value); +int32_t SDIOC_ConfigData(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_data_config_t *pstcDataConfig); +int32_t SDIOC_DataStructInit(stc_sdioc_data_config_t *pstcDataConfig); +int32_t SDIOC_ReadBuffer(CM_SDIOC_TypeDef *SDIOCx, uint8_t au8Data[], uint32_t u32Len); +int32_t SDIOC_WriteBuffer(CM_SDIOC_TypeDef *SDIOCx, const uint8_t au8Data[], uint32_t u32Len); + +void SDIOC_BlockGapStopCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); +void SDIOC_RestartTrans(CM_SDIOC_TypeDef *SDIOCx); +void SDIOC_ReadWaitCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); +void SDIOC_BlockGapIntCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState); + +void SDIOC_IntCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState); +en_functional_state_t SDIOC_GetIntEnableState(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType); +void SDIOC_IntStatusCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t SDIOC_GetIntStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag); +void SDIOC_ClearIntStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag); +en_flag_status_t SDIOC_GetHostStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag); +en_flag_status_t SDIOC_GetAutoCmdErrorStatus(const CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Flag); +void SDIOC_ForceAutoCmdErrorEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event); +void SDIOC_ForceErrorIntEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event); + +/* SDMMC Commands management functions */ +int32_t SDMMC_CMD0_GoIdleState(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD2_AllSendCID(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD3_SendRelativeAddr(CM_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD6_SwitchFunc(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD7_SelectDeselectCard(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD8_SendInterfaceCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD9_SendCSD(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD12_StopTrans(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD16_SetBlockLength(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BlockLen, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD17_ReadSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD18_ReadMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD24_WriteSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD25_WriteMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD32_EraseBlockStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD33_EraseBlockEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD38_Erase(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD55_AppCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus); + +int32_t SDMMC_ACMD6_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BusWidth, uint32_t *pu32ErrStatus); +int32_t SDMMC_ACMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); +int32_t SDMMC_ACMD41_SendOperatCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus); +int32_t SDMMC_ACMD51_SendSCR(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus); + +int32_t SDMMC_CMD1_SendOperatCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD35_EraseGroupStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus); +int32_t SDMMC_CMD36_EraseGroupEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus); + +/** + * @} + */ + +#endif /* LL_SDIOC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SDIOC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_spi.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_spi.h new file mode 100644 index 0000000000..e5f482dcef --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_spi.h @@ -0,0 +1,432 @@ +/** + ******************************************************************************* + * @file hc32_ll_spi.h + * @brief This file contains all the functions prototypes of the SPI driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SPI_H__ +#define __HC32_LL_SPI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SPI + * @{ + */ + +#if (LL_SPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup SPI_Global_Types SPI Global Types + * @{ + */ + +/** + * @brief Structure definition of SPI initialization. + */ +typedef struct { + uint32_t u32WireMode; /*!< SPI wire mode, 3 wire mode or 4 wire mode. + This parameter can be a value of @ref SPI_Wire_Mode_Define */ + uint32_t u32TransMode; /*!< SPI transfer mode, send only or full duplex. + This parameter can be a value of @ref SPI_Trans_Mode_Define */ + uint32_t u32MasterSlave; /*!< SPI master/slave mode. + This parameter can be a value of @ref SPI_Master_Slave_Mode_Define */ + uint32_t u32ModeFaultDetect; /*!< SPI mode fault detect command. + This parameter can be a value of @ref SPI_Mode_Fault_Detect_Command_Define */ + uint32_t u32Parity; /*!< SPI parity check selection. + This parameter can be a value of @ref SPI_Parity_Check_Define */ + uint32_t u32SpiMode; /*!< SPI mode. + This parameter can be a value of @ref SPI_Mode_Define */ + uint32_t u32BaudRatePrescaler; /*!< SPI baud rate prescaler. + This parameter can be a value of @ref SPI_Baud_Rate_Prescaler_Define */ + uint32_t u32DataBits; /*!< SPI data bits, 4 bits ~ 32 bits. + This parameter can be a value of @ref SPI_Data_Size_Define */ + uint32_t u32FirstBit; /*!< MSB first or LSB first. + This parameter can be a value of @ref SPI_First_Bit_Define */ + uint32_t u32SuspendMode; /*!< SPI communication suspend function. + This parameter can be a value of @ref SPI_Com_Suspend_Func_Define */ + uint32_t u32FrameLevel; /*!< SPI frame level, SPI_1_FRAME ~ SPI_4_FRAME. + This parameter can be a value of @ref SPI_Frame_Level_Define */ +} stc_spi_init_t; + +/** + * @brief Structure definition of SPI delay time configuration. + */ +typedef struct { + uint32_t u32IntervalDelay; /*!< SPI interval time delay (Next access delay time) + This parameter can be a value of @ref SPI_Interval_Delay_Time_define */ + uint32_t u32ReleaseDelay; /*!< SPI release time delay (SCK invalid delay time) + This parameter can be a value of @ref SPI_Release_Delay_Time_define */ + uint32_t u32SetupDelay; /*!< SPI Setup time delay (SCK valid delay time) define + This parameter can be a value of @ref SPI_Setup_Delay_Time_define */ +} stc_spi_delay_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SPI_Global_Macros SPI Global Macros + * @{ + */ + +/** + * @defgroup SPI_Wire_Mode_Define SPI Wire Mode Define + * @{ + */ +#define SPI_4_WIRE (0UL) +#define SPI_3_WIRE (SPI_CR1_SPIMDS) +/** + * @} + */ + +/** + * @defgroup SPI_Trans_Mode_Define SPI Transfer Mode Define + * @{ + */ +#define SPI_FULL_DUPLEX (0UL) /*!< Full duplex. */ +#define SPI_SEND_ONLY (SPI_CR1_TXMDS) /*!< Send only. */ +/** + * @} + */ + +/** + * @defgroup SPI_Master_Slave_Mode_Define SPI Master Slave Mode Define + * @{ + */ +#define SPI_SLAVE (0UL) +#define SPI_MASTER (SPI_CR1_MSTR) +/** + * @} + */ + +/** + * @defgroup SPI_Loopback_Selection_Define SPI Loopback Selection Define + * @note Loopback mode is mainly used for parity self-diagnosis in 4-wire full-duplex mode. + * @{ + */ +#define SPI_LOOPBACK_INVD (0UL) +#define SPI_LOOPBACK_MOSI_INVT (SPI_CR1_SPLPBK) /*!< MISO data is the inverse of the data output by MOSI. */ +#define SPI_LOOPBACK_MOSI (SPI_CR1_SPLPBK2) /*!< MISO data is the data output by MOSI. */ +/** + * @} + */ + +/** + * @defgroup SPI_Int_Type_Define SPI Interrupt Type Define + * @{ + */ +#define SPI_INT_ERR (SPI_CR1_EIE) /*!< Including overload, underload and parity error. */ +#define SPI_INT_TX_BUF_EMPTY (SPI_CR1_TXIE) +#define SPI_INT_RX_BUF_FULL (SPI_CR1_RXIE) +#define SPI_INT_IDLE (SPI_CR1_IDIE) +#define SPI_IRQ_ALL (SPI_INT_ERR | SPI_INT_TX_BUF_EMPTY | SPI_INT_RX_BUF_FULL | SPI_INT_IDLE ) +/** + * @} + */ + +/** + * @defgroup SPI_Mode_Fault_Detect_Command_Define SPI Mode Fault Detect Command Define + * @{ + */ +#define SPI_MD_FAULT_DETECT_DISABLE (0UL) /*!< Disable mode fault detection. */ +#define SPI_MD_FAULT_DETECT_ENABLE (SPI_CR1_MODFE) /*!< Enable mode fault detection. */ +/** + * @} + */ + +/** + * @defgroup SPI_Parity_Check_Define SPI Parity Check Mode Define + * @{ + */ +#define SPI_PARITY_INVD (0UL) /*!< Parity check invalid. */ +#define SPI_PARITY_EVEN (SPI_CR1_PAE) /*!< Parity check selection even parity. */ +#define SPI_PARITY_ODD (SPI_CR1_PAE | SPI_CR1_PAOE) /*!< Parity check selection odd parity. */ +/** + * @} + */ + +/** + * @defgroup SPI_SS_Pin_Define SPI SSx Define + * @{ + */ +#define SPI_PIN_SS0 (SPI_CFG1_SS0PV) +#define SPI_PIN_SS1 (SPI_CFG1_SS1PV) +#define SPI_PIN_SS2 (SPI_CFG1_SS2PV) +#define SPI_PIN_SS3 (SPI_CFG1_SS3PV) +/** + * @} + */ + +/** + * @defgroup SPI_Read_Target_Buf_Define SPI Read Data Register Target Buffer Define + * @{ + */ +#define SPI_RD_TARGET_RD_BUF (0UL) /*!< Read RX buffer. */ +#define SPI_RD_TARGET_WR_BUF (SPI_CFG1_SPRDTD) /*!< Read TX buffer. */ +/** + * @} + */ + +/** + * @defgroup SPI_Frame_Level_Define SPI data frame level define, The Data in the SPI_DR register will be send to TX_BUFF + * after enough data frame write to the SPI_DR + * @{ + */ +#define SPI_1_FRAME (0UL) /*!< Data 1 frame */ +#define SPI_2_FRAME (SPI_CFG1_FTHLV_0) /*!< Data 2 frame.*/ +#define SPI_3_FRAME (SPI_CFG1_FTHLV_1) /*!< Data 3 frame.*/ +#define SPI_4_FRAME (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1) /*!< Data 4 frame.*/ +/** + * @} + */ + +/** + * @defgroup SPI_Interval_Delay_Time_define SPI Interval Time Delay (Next Access Delay Time) define + * @{ + */ +#define SPI_INTERVAL_TIME_1SCK (0UL << SPI_CFG1_MIDI_POS) /*!< 1 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_2SCK (1UL << SPI_CFG1_MIDI_POS) /*!< 2 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_3SCK (2UL << SPI_CFG1_MIDI_POS) /*!< 3 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_4SCK (3UL << SPI_CFG1_MIDI_POS) /*!< 4 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_5SCK (4UL << SPI_CFG1_MIDI_POS) /*!< 5 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_6SCK (5UL << SPI_CFG1_MIDI_POS) /*!< 6 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_7SCK (6UL << SPI_CFG1_MIDI_POS) /*!< 7 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_8SCK (7UL << SPI_CFG1_MIDI_POS) /*!< 8 SCK + 2 PCLK1 */ +/** + * @} + */ + +/** + * @defgroup SPI_Release_Delay_Time_define SPI Release Time Delay (SCK Invalid Delay Time) Define + * @{ + */ +#define SPI_RELEASE_TIME_1SCK (0UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_2SCK (1UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_3SCK (2UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_4SCK (3UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_5SCK (4UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_6SCK (5UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_7SCK (6UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_8SCK (7UL << SPI_CFG1_MSSDL_POS) +/** + * @} + */ + +/** + * @defgroup SPI_Setup_Delay_Time_define SPI Setup Time Delay (SCK Valid Delay Time) Define + * @{ + */ +#define SPI_SETUP_TIME_1SCK (0UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_2SCK (1UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_3SCK (2UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_4SCK (3UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_5SCK (4UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_6SCK (5UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_7SCK (6UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_8SCK (7UL << SPI_CFG1_MSSI_POS) +/** + * @} + */ + +/** + * @defgroup SPI_Com_Suspend_Func_Define SPI Communication Suspend Function Define + * @{ + */ +#define SPI_COM_SUSP_FUNC_OFF (0UL) +#define SPI_COM_SUSP_FUNC_ON (SPI_CR1_CSUSPE) +/** + * @} + */ + +/** + * @defgroup SPI_Mode_Define SPI Mode Define + * @{ + */ +#define SPI_MD_0 (0UL) /*!< SCK pin output low in idle state; \ + MOSI/MISO pin data valid in odd edge, \ + MOSI/MISO pin data change in even edge */ +#define SPI_MD_1 (SPI_CFG2_CPHA) /*!< SCK pin output low in idle state; \ + MOSI/MISO pin data valid in even edge, \ + MOSI/MISO pin data change in odd edge */ +#define SPI_MD_2 (SPI_CFG2_CPOL) /*!< SCK pin output high in idle state; \ + MOSI/MISO pin data valid in odd edge, \ + MOSI/MISO pin data change in even edge */ +#define SPI_MD_3 (SPI_CFG2_CPOL | SPI_CFG2_CPHA) /*!< SCK pin output high in idle state; \ + MOSI/MISO pin data valid in even edge, \ + MOSI/MISO pin data change in odd edge */ + +/** + * @} + */ + +/** + * @defgroup SPI_Baud_Rate_Prescaler_Define SPI Baudrate Prescaler Define + * @{ + */ +#define SPI_BR_CLK_DIV2 (0UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 2. */ +#define SPI_BR_CLK_DIV4 (1UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 4. */ +#define SPI_BR_CLK_DIV8 (2UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 8. */ +#define SPI_BR_CLK_DIV16 (3UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 16. */ +#define SPI_BR_CLK_DIV32 (4UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 32. */ +#define SPI_BR_CLK_DIV64 (5UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 64. */ +#define SPI_BR_CLK_DIV128 (6UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 128. */ +#define SPI_BR_CLK_DIV256 (7UL << SPI_CFG2_MBR_POS) /*!< PCLK1 / 256. */ +/** + * @} + */ + +/** + * @defgroup SPI_Data_Size_Define SPI Data Size Define + * @{ + */ +#define SPI_DATA_SIZE_4BIT (0UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_5BIT (1UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_6BIT (2UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_7BIT (3UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_8BIT (4UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_9BIT (5UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_10BIT (6UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_11BIT (7UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_12BIT (8UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_13BIT (9UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_14BIT (10UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_15BIT (11UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_16BIT (12UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_20BIT (13UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_24BIT (14UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_32BIT (15UL << SPI_CFG2_DSIZE_POS) + +/** + * @} + */ + +/** + * @defgroup SPI_First_Bit_Define SPI First Bit Define + * @{ + */ +#define SPI_FIRST_MSB (0UL) +#define SPI_FIRST_LSB (SPI_CFG2_LSBF) +/** + * @} + */ + +/** + * @defgroup SPI_State_Flag_Define SPI State Flag Define + * @{ + */ +#define SPI_FLAG_OVERLOAD (SPI_SR_OVRERF) +#define SPI_FLAG_IDLE (SPI_SR_IDLNF) +#define SPI_FLAG_MD_FAULT (SPI_SR_MODFERF) +#define SPI_FLAG_PARITY_ERR (SPI_SR_PERF) +#define SPI_FLAG_UNDERLOAD (SPI_SR_UDRERF) +#define SPI_FLAG_TX_BUF_EMPTY (SPI_SR_TDEF) /*!< This flag is set when the data in the data register \ + is copied into the shift register, but the transmission \ + of the data bit may not have been completed. */ +#define SPI_FLAG_RX_BUF_FULL (SPI_SR_RDFF) /*!< Indicates that a data was received. */ +#define SPI_FLAG_CLR_ALL (SPI_FLAG_OVERLOAD | SPI_FLAG_MD_FAULT | SPI_FLAG_PARITY_ERR | SPI_FLAG_UNDERLOAD) +#define SPI_FLAG_ALL (SPI_FLAG_OVERLOAD | SPI_FLAG_IDLE | SPI_FLAG_MD_FAULT | SPI_FLAG_PARITY_ERR | \ + SPI_FLAG_UNDERLOAD | SPI_FLAG_TX_BUF_EMPTY | SPI_FLAG_RX_BUF_FULL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SPI_Global_Functions + * @{ + */ +int32_t SPI_StructInit(stc_spi_init_t *pstcSpiInit); +int32_t SPI_Init(CM_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInit); +void SPI_DeInit(CM_SPI_TypeDef *SPIx); + +void SPI_IntCmd(CM_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState); +void SPI_Cmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState); +void SPI_WriteData(CM_SPI_TypeDef *SPIx, uint32_t u32Data); +uint32_t SPI_ReadData(const CM_SPI_TypeDef *SPIx); + +en_flag_status_t SPI_GetStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32Flag); +void SPI_ClearStatus(CM_SPI_TypeDef *SPIx, uint32_t u32Flag); +void SPI_LoopbackModeConfig(CM_SPI_TypeDef *SPIx, uint32_t u32Mode); +void SPI_ParityCheckCmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState); +void SPI_SSValidLevelConfig(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin, en_functional_state_t enNewState); + +int32_t SPI_DelayTimeConfig(CM_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayConfig); +void SPI_SSPinSelect(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin); +void SPI_ReadBufConfig(CM_SPI_TypeDef *SPIx, uint32_t u32ReadBuf); +int32_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayConfig); + +int32_t SPI_Trans(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLen, uint32_t u32Timeout); +int32_t SPI_Receive(CM_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLen, uint32_t u32Timeout); +int32_t SPI_TransReceive(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout); + +/** + * @} + */ + +#endif /* LL_SPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sram.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sram.h new file mode 100644 index 0000000000..550ebe04e4 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sram.h @@ -0,0 +1,230 @@ +/** + ******************************************************************************* + * @file hc32_ll_sram.h + * @brief This file contains all the functions prototypes of the SRAM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SRAM_H__ +#define __HC32_LL_SRAM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SRAM + * @{ + */ + +#if (LL_SRAM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SRAM_Global_Macros SRAM Global Macros + * @{ + */ + +/** + * @defgroup SRAM_Sel SRAM Selection + * @{ + */ +/* SRAM selection */ +#define SRAM_SRAMH (1UL << 2U) /*!< SRAMH: 0x1FFF8000~0x1FFFFFFF, 32KB */ +#define SRAM_SRAM12 (1UL << 0U) /*!< SRAM1: 0x20000000~0x2000FFFF, 64KB + SRAM2: 0x20010000~0x2001FFFF, 64KB */ +#define SRAM_SRAM3 (1UL << 1U) /*!< SRAM3: 0x20020000~0x20026FFF, 28KB */ +#define SRAM_SRAMR (1UL << 3U) /*!< Ret_SRAM: 0x200F0000~0x200F0FFF, 4KB */ +#define SRAM_SRAM_ALL (SRAM_SRAMH | SRAM_SRAM12 | SRAM_SRAM3 | SRAM_SRAMR) +#define SRAM_ECC_SRAM3 (SRAM_SRAM3) + +/** + * @} + */ + +/** + * @defgroup SRAM_Access_Wait_Cycle SRAM Access Wait Cycle + * @{ + */ +#define SRAM_WAIT_CYCLE0 (0U) /*!< Wait 0 CPU cycle. */ +#define SRAM_WAIT_CYCLE1 (1U) /*!< Wait 1 CPU cycle. */ +#define SRAM_WAIT_CYCLE2 (2U) /*!< Wait 2 CPU cycles. */ +#define SRAM_WAIT_CYCLE3 (3U) /*!< Wait 3 CPU cycles. */ +#define SRAM_WAIT_CYCLE4 (4U) /*!< Wait 4 CPU cycles. */ +#define SRAM_WAIT_CYCLE5 (5U) /*!< Wait 5 CPU cycles. */ +#define SRAM_WAIT_CYCLE6 (6U) /*!< Wait 6 CPU cycles. */ +#define SRAM_WAIT_CYCLE7 (7U) /*!< Wait 7 CPU cycles. */ +/** + * @} + */ + +/** + * @defgroup SRAM_Err_Mode SRAM Error Mode + * @note Even-parity check error, ECC check error. + * @{ + */ +#define SRAM_ERR_MD_NMI (0UL) /*!< Non-maskable interrupt occurres while check error occurres. */ +#define SRAM_ERR_MD_RST (1UL) /*!< System reset occurres while check error occurres. */ +/** + * @} + */ + +/** + * @defgroup SRAM_ECC_Mode SRAM ECC Mode + * @{ + */ +#define SRAM_ECC_MD_INVD (0U) /*!< The ECC mode is invalid. */ +#define SRAM_ECC_MD1 (SRAMC_CKCR_ECCMOD_0) /*!< When 1-bit error occurres: + ECC error corrects. + No 1-bit-error status flag setting, no interrupt or reset. + When 2-bit error occurres: + ECC error detects. + 2-bit-error status flag sets and interrupt or reset occurres. */ +#define SRAM_ECC_MD2 (SRAMC_CKCR_ECCMOD_1) /*!< When 1-bit error occurres: + ECC error corrects. + 1-bit-error status flag sets, no interrupt or reset. + When 2-bit error occurres: + ECC error detects. + 2-bit-error status flag sets and interrupt or reset occurres. */ +#define SRAM_ECC_MD3 (SRAMC_CKCR_ECCMOD) /*!< When 1-bit error occurres: + ECC error corrects. + 1-bit-error status flag sets and interrupt or reset occurres. + When 2-bit error occurres: + ECC error detects. + 2-bit-error status flag sets and interrupt or reset occurres. */ +/** + * @} + */ + +/** + * @defgroup SRAM_Err_Status_Flag SRAM Error Status Flag + * @{ + */ +#define SRAM_FLAG_SRAM3_1ERR (SRAMC_CKSR_SRAM3_1ERR) /*!< SRAM3 ECC 1-bit error. */ +#define SRAM_FLAG_SRAM3_2ERR (SRAMC_CKSR_SRAM3_2ERR) /*!< SRAM3 ECC 2-bit error. */ +#define SRAM_FLAG_SRAM12_PYERR (SRAMC_CKSR_SRAM12_PYERR) /*!< SRAM12 parity error. */ +#define SRAM_FLAG_SRAMH_PYERR (SRAMC_CKSR_SRAMH_PYERR) /*!< SRAMH parity error. */ +#define SRAM_FLAG_SRAMR_PYERR (SRAMC_CKSR_SRAMR_PYERR) /*!< SRAMR parity error. */ +#define SRAM_FLAG_ALL (0x1FUL) + +/** + * @} + */ + +/** + * @defgroup SRAM_Reg_Protect_Key SRAM Register Protect Key + * @{ + */ +#define SRAM_REG_LOCK_KEY (0x76U) +#define SRAM_REG_UNLOCK_KEY (0x77U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SRAM_Global_Functions + * @{ + */ + +/** + * @brief Lock SRAM registers, write protect. + * @param None + * @retval None + */ +__STATIC_INLINE void SRAM_REG_Lock(void) +{ + WRITE_REG32(CM_SRAMC->WTPR, SRAM_REG_LOCK_KEY); + WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_LOCK_KEY); +} + +/** + * @brief Unlock SRAM registers, write enable. + * @param None + * @retval None + */ +__STATIC_INLINE void SRAM_REG_Unlock(void) +{ + WRITE_REG32(CM_SRAMC->WTPR, SRAM_REG_UNLOCK_KEY); + WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_UNLOCK_KEY); +} + +void SRAM_Init(void); +void SRAM_DeInit(void); + +void SRAM_REG_Lock(void); +void SRAM_REG_Unlock(void); + +void SRAM_SetWaitCycle(uint32_t u32SramSel, uint32_t u32WriteCycle, uint32_t u32ReadCycle); +void SRAM_SetEccMode(uint32_t u32SramSel, uint32_t u32EccMode); +void SRAM_SetErrorMode(uint32_t u32SramSel, uint32_t u32ErrMode); + +en_flag_status_t SRAM_GetStatus(uint32_t u32Flag); +void SRAM_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_SRAM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SRAM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_swdt.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_swdt.h new file mode 100644 index 0000000000..eb82446e00 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_swdt.h @@ -0,0 +1,129 @@ +/** + ******************************************************************************* + * @file hc32_ll_swdt.h + * @brief This file contains all the functions prototypes of the SWDT driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SWDT_H__ +#define __HC32_LL_SWDT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SWDT + * @{ + */ + +#if (LL_SWDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SWDT_Global_Macros SWDT Global Macros + * @{ + */ + +/** + * @defgroup SWDT_Flag SWDT Flag + * @{ + */ +#define SWDT_FLAG_UDF (SWDT_SR_UDF) /*!< Count underflow flag */ +#define SWDT_FLAG_REFRESH (SWDT_SR_REF) /*!< Refresh error flag */ +#define SWDT_FLAG_ALL (SWDT_SR_UDF | SWDT_SR_REF) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SWDT_Global_Functions + * @{ + */ + +/** + * @brief Get SWDT count value. + * @param None + * @retval uint16_t Count value + */ +__STATIC_INLINE uint16_t SWDT_GetCountValue(void) +{ + return (uint16_t)(READ_REG32(CM_SWDT->SR) & SWDT_SR_CNT); +} + +/* Initialization and configuration functions */ +void SWDT_FeedDog(void); +uint16_t SWDT_GetCountValue(void); + +/* Flags management functions */ +en_flag_status_t SWDT_GetStatus(uint32_t u32Flag); +int32_t SWDT_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_SWDT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SWDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr0.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr0.h new file mode 100644 index 0000000000..b6ddbcbf16 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr0.h @@ -0,0 +1,227 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr0.h + * @brief This file contains all the functions prototypes of the TMR0 driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMR0_H__ +#define __HC32_LL_TMR0_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMR0 + * @{ + */ + +#if (LL_TMR0_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR0_Global_Types TMR0 Global Types + * @{ + */ + +/** + * @brief TMR0 initialization structure definition + * @note The 'u32ClockDiv' is invalid when the value of 'u32ClockSrc' is "TMR0_CLK_SRC_SPEC_EVT". + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Specifies the clock source of TMR0 channel. + This parameter can be a value of @ref TMR0_Clock_Source */ + uint32_t u32ClockDiv; /*!< Specifies the clock division of TMR0 channel. + This parameter can be a value of @ref TMR0_Clock_Division */ + uint32_t u32Func; /*!< Specifies the function of TMR0 channel. + This parameter can be a value of @ref TMR0_Function */ + uint16_t u16CompareValue; /*!< Specifies the compare value of TMR0 channel. + This parameter can be a value of half-word */ +} stc_tmr0_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR0_Global_Macros TMR0 Global Macros + * @{ + */ + +/** + * @defgroup TMR0_Channel TMR0 Channel + * @note TMR0 on the HC32F120,HC32F160 and HC32M120 chips is only "TMR0_CH_A". + * @{ + */ +#define TMR0_CH_A (0UL) +#define TMR0_CH_B (1UL) +/** + * @} + */ + +/** + * @defgroup TMR0_Clock_Source TMR0 Clock Source + * @note In asynchronous clock, continuous operation of the BCONR register requires waiting for 3 asynchronous clocks. + * @{ + */ +#define TMR0_CLK_SRC_INTERN_CLK (0UL) /*!< Internal clock (Synchronous clock) */ +#define TMR0_CLK_SRC_SPEC_EVT (TMR0_BCONR_SYNCLKA) /*!< Specified event (Synchronous clock) */ +#define TMR0_CLK_SRC_LRC (TMR0_BCONR_SYNSA) /*!< LRC (Asynchronous clock) */ +#define TMR0_CLK_SRC_XTAL32 (TMR0_BCONR_ASYNCLKA | TMR0_BCONR_SYNSA) /*!< XTAL32 (Asynchronous clock) */ +/** + * @} + */ + +/** + * @defgroup TMR0_Clock_Division TMR0 Clock Division + * @{ + */ +#define TMR0_CLK_DIV1 (0UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK */ +#define TMR0_CLK_DIV2 (1UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/2 */ +#define TMR0_CLK_DIV4 (2UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/4 */ +#define TMR0_CLK_DIV8 (3UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/8 */ +#define TMR0_CLK_DIV16 (4UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/16 */ +#define TMR0_CLK_DIV32 (5UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/32 */ +#define TMR0_CLK_DIV64 (6UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/64 */ +#define TMR0_CLK_DIV128 (7UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/128 */ +#define TMR0_CLK_DIV256 (8UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/256 */ +#define TMR0_CLK_DIV512 (9UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/512 */ +#define TMR0_CLK_DIV1024 (10UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/1024 */ +/** + * @} + */ + +/** + * @defgroup TMR0_Function TMR0 Function + * @{ + */ +#define TMR0_FUNC_CMP (0UL) /*!< Output comare function */ +#define TMR0_FUNC_CAPT (TMR0_BCONR_CAPMDA | TMR0_BCONR_HICPA) /*!< Input capture function */ +/** + * @} + */ + +/** + * @defgroup TMR0_Interrupt TMR0 Interrupt + * @{ + */ +#define TMR0_INT_CMP_A (TMR0_BCONR_INTENA) + +#define TMR0_INT_CMP_B (TMR0_BCONR_INTENB) +#define TMR0_INT_ALL (TMR0_INT_CMP_A | TMR0_INT_CMP_B) +/** + * @} + */ + +/** + * @defgroup TMR0_FLAG TMR0 Flag + * @{ + */ +#define TMR0_FLAG_CMP_A (TMR0_STFLR_CMFA) + +#define TMR0_FLAG_CMP_B (TMR0_STFLR_CMFB) +#define TMR0_FLAG_ALL (TMR0_FLAG_CMP_A | TMR0_FLAG_CMP_B) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR0_Global_Functions + * @{ + */ + +/* Initialization functions */ +void TMR0_DeInit(CM_TMR0_TypeDef *TMR0x); +int32_t TMR0_Init(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, const stc_tmr0_init_t *pstcTmr0Init); +int32_t TMR0_StructInit(stc_tmr0_init_t *pstcTmr0Init); +void TMR0_Start(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); +void TMR0_Stop(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); + +/* Control configuration functions */ +void TMR0_SetCountValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value); +uint16_t TMR0_GetCountValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); +void TMR0_SetCompareValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value); +uint16_t TMR0_GetCompareValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); +void TMR0_SetClockSrc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Src); +void TMR0_SetClockDiv(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Div); +void TMR0_SetFunc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Func); + +/* Hardware trigger Functions */ +void TMR0_HWCaptureCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR0_HWStartCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR0_HWStopCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR0_HWClearCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); + +/* Interrupt and flag management functions */ +void TMR0_IntCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t TMR0_GetStatus(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag); +void TMR0_ClearStatus(CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_TMR0_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMR0_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr4.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr4.h new file mode 100644 index 0000000000..66ad51b42d --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr4.h @@ -0,0 +1,773 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr4.h + * @brief This file contains all the functions prototypes of the TMR4 + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMR4_H__ +#define __HC32_LL_TMR4_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMR4 + * @{ + */ + +#if (LL_TMR4_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR4_Global_Types TMR4 Global Types + * @{ + */ + +/** + * @brief TMR4 Counter function initialization configuration + * @note The TMR4 division(u16ClockDiv) is valid when clock source is the internal clock. + */ +typedef struct { + uint16_t u16ClockSrc; /*!< TMR4 counter clock source. + This parameter can be a value of @ref TMR4_Count_Clock_Source */ + uint16_t u16ClockDiv; /*!< TMR4 counter internal clock division. + This parameter can be a value of @ref TMR4_Count_Clock_Division. */ + uint16_t u16CountMode; /*!< TMR4 counter mode. + This parameter can be a value of @ref TMR4_Count_Mode */ + uint16_t u16PeriodValue; /*!< TMR4 counter period value. + This parameter can be a value of half-word */ +} stc_tmr4_init_t; + +/** + * @brief The configuration of Output-Compare high channel(OUH/OVH/OWH) + */ +typedef union { + uint16_t OCMRx; /*!< OCMRxH(x=U/V/W) register */ + + struct { /*!< OCMRxH(x=U/V/W) register struct field bit */ + uint16_t OCFDCH : 1; /*!< OCMRxh b0 High channel's OCF status when high channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OCFPKH : 1; /*!< OCMRxh b1 High channel's OCF status when high channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OCFUCH : 1; /*!< OCMRxh b2 High channel's OCF status when high channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OCFZRH : 1; /*!< OCMRxh b3 High channel's OCF status when high channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OPDCH : 2; /*!< OCMRxh b5~b4 High channel's OP output status when high channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPPKH : 2; /*!< OCMRxh b7~b6 High channel's OP output status when high channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPUCH : 2; /*!< OCMRxh b9~b8 High channel's OP output status when high channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPZRH : 2; /*!< OCMRxh b11~b10 High channel's OP output status when high channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPNPKH : 2; /*!< OCMRxh b13~b12 High channel's OP output status when high channel match doesn't occur at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPNZRH : 2; /*!< OCMRxh b15~b14 High channel's OP output status when high channel match doesn't occur at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + } OCMRx_f; +} un_tmr4_oc_ocmrh_t; + +/** + * @brief The configuration of Output-Compare low channel(OUL/OVL/OWL) + */ +typedef union { + uint32_t OCMRx; /*!< OCMRxL(x=U/V/W) register */ + + struct { /*!< OCMRxL(x=U/V/W) register struct field bit*/ + uint32_t OCFDCL : 1; /*!< OCMRxl b0 Low channel's OCF status when low channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OCFPKL : 1; /*!< OCMRxl b1 Low channel's OCF status when low channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OCFUCL : 1; /*!< OCMRxl b2 Low channel's OCF status when low channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OCFZRL : 1; /*!< OCMRxl b3 Low channel's OCF status when low channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OPDCL : 2; /*!< OCMRxl b5~b4 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPPKL : 2; /*!< OCMRxl b7~b6 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPUCL : 2; /*!< OCMRxl b9~b8 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPZRL : 2; /*!< OCMRxl b11~b10 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPNPKL : 2; /*!< OCMRxl b13~b12 Low channel's OP output status when high channel not match and low channel not match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPNZRL : 2; /*!< OCMRxl b15~b14 Low channel's OP output status when high channel not match and low channel not match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNDCL : 2; /*!< OCMRxl b17~b16 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter is coutning down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNUCL : 2; /*!< OCMRxl b19~b18 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPDCL : 2; /*!< OCMRxl b21~b20 Low channel's OP output status when high channel and low channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPPKL : 2; /*!< OCMRxl b23~b22 Low channel's OP output status when high channel and low channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPUCL : 2; /*!< OCMRxl b25~b24 Low channel's OP output status when high channel and low channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPZRL : 2; /*!< OCMRxl b27~b26 Low channel's OP output status when high channel and low channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNPKL : 2; /*!< OCMRxl b29~b28 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNZRL : 2; /*!< OCMRxl b31~b30 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + } OCMRx_f; +} un_tmr4_oc_ocmrl_t; + +/** + * @brief TMR4 Output-Compare(OC) initialization configuration + */ +typedef struct { + uint16_t u16CompareValue; /*!< TMR4 OC compare match value. + This parameter can be a value of half-word. */ + uint16_t u16OcInvalidPolarity; /*!< Port output polarity when OC is disabled. + This parameter can be a value of @ref TMR4_OC_Invalid_Output_Polarity. */ + uint16_t u16CompareModeBufCond; /*!< Register OCMR buffer transfer condition. + This parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition. */ + uint16_t u16CompareValueBufCond; /*!< Register OCCR buffer transfer condition. + This parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition. */ + uint16_t u16BufLinkTransObject; /*!< Enable the specified object(OCMR/OCCR) register buffer linked transfer with the counter interrupt mask. + This parameter can be a value of @ref TMR4_OC_Buffer_Object. */ +} stc_tmr4_oc_init_t; + +/** + * @brief TMR4 PWM initialization configuration + * @note The clock division(u16ClockDiv) is valid when TMR4 clock source is the internal clock. + */ +typedef struct { + uint16_t u16Mode; /*!< Select PWM mode + This parameter can be a value of @ref TMR4_PWM_Mode */ + uint16_t u16ClockDiv; /*!< The internal clock division of PWM timer. + This parameter can be a value of @ref TMR4_PWM_Clock_Division. */ + uint16_t u16Polarity; /*!< TMR4 PWM polarity + This parameter can be a value of @ref TMR4_PWM_Polarity */ +} stc_tmr4_pwm_init_t; + +/** + * @brief TMR4 Special-Event(EVT) initialization configuration + */ +typedef struct { + uint16_t u16Mode; /*!< TMR4 event mode + This parameter can be a value of @ref TMR4_Event_Mode */ + uint16_t u16CompareValue; /*!< TMR4 event compare match value. + This parameter can be a value of half-word */ + uint16_t u16OutputEvent; /*!< TMR4 event output event when match count compare condition. + This parameter can be a value of @ref TMR4_Event_Output_Event */ + uint16_t u16MatchCond; /*!< Enable the specified count compare type with counter count to generate event. + This parameter can be a value of @ref TMR4_Event_Match_Condition */ +} stc_tmr4_evt_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR4_Global_Macros TMR4 Global Macros + * @{ + */ + +/** + * @defgroup TMR4_Counter_Macros TMR4 Counter Macros + * @{ + */ + +/** + * @defgroup TMR4_Count_Clock_Source TMR4 Count Clock Source + * @{ + */ +#define TMR4_CLK_SRC_INTERNCLK (0U) +#define TMR4_CLK_SRC_EXTCLK (TMR4_CCSR_ECKEN) +/** + * @} + */ + +/** + * @defgroup TMR4_Count_Clock_Division TMR4 Count Clock Division + * @{ + */ +#define TMR4_CLK_DIV1 (0U << TMR4_CCSR_CKDIV_POS) /*!< CLK */ +#define TMR4_CLK_DIV2 (1U << TMR4_CCSR_CKDIV_POS) /*!< CLK/2 */ +#define TMR4_CLK_DIV4 (2U << TMR4_CCSR_CKDIV_POS) /*!< CLK/4 */ +#define TMR4_CLK_DIV8 (3U << TMR4_CCSR_CKDIV_POS) /*!< CLK/8 */ +#define TMR4_CLK_DIV16 (4U << TMR4_CCSR_CKDIV_POS) /*!< CLK/16 */ +#define TMR4_CLK_DIV32 (5U << TMR4_CCSR_CKDIV_POS) /*!< CLK/32 */ +#define TMR4_CLK_DIV64 (6U << TMR4_CCSR_CKDIV_POS) /*!< CLK/64 */ +#define TMR4_CLK_DIV128 (7U << TMR4_CCSR_CKDIV_POS) /*!< CLK/128 */ +#define TMR4_CLK_DIV256 (8U << TMR4_CCSR_CKDIV_POS) /*!< CLK/256 */ +#define TMR4_CLK_DIV512 (9U << TMR4_CCSR_CKDIV_POS) /*!< CLK/512 */ +#define TMR4_CLK_DIV1024 (10U << TMR4_CCSR_CKDIV_POS) /*!< CLK/1024 */ +/** + * @} + */ + +/** + * @defgroup TMR4_Count_Mode TMR4 Count Mode + * @{ + */ +#define TMR4_MD_SAWTOOTH (0U) +#define TMR4_MD_TRIANGLE (TMR4_CCSR_MODE) +/** + * @} + */ + +/** + * @defgroup TMR4_Flag TMR4 Flag + * @{ + */ +#define TMR4_FLAG_CNT_PEAK ((uint32_t)TMR4_CCSR_IRQPF) /*!< Count peak flag */ +#define TMR4_FLAG_CNT_VALLEY ((uint32_t)TMR4_CCSR_IRQZF) /*!< Count valley flag */ +#define TMR4_FLAG_RELOAD_TMR_U (1UL << 0U) /*!< TMR4 PWM reload-timer flag - channel U */ +#define TMR4_FLAG_RELOAD_TMR_V (1UL << 4U) /*!< TMR4 PWM reload-timer flag - channel V */ +#define TMR4_FLAG_RELOAD_TMR_W (1UL << 8U) /*!< TMR4 PWM reload-timer flag - channel W */ +#define TMR4_FLAG_OC_CMP_UH (1UL << 16U) /*!< TMR4 output-compare compare flag - channel UH */ +#define TMR4_FLAG_OC_CMP_UL (1UL << 17U) /*!< TMR4 output-compare compare flag - channel UL */ +#define TMR4_FLAG_OC_CMP_VH (1UL << 18U) /*!< TMR4 output-compare compare flag - channel VH */ +#define TMR4_FLAG_OC_CMP_VL (1UL << 19U) /*!< TMR4 output-compare compare flag - channel VL */ +#define TMR4_FLAG_OC_CMP_WH (1UL << 20U) /*!< TMR4 output-compare compare flag - channel WH */ +#define TMR4_FLAG_OC_CMP_WL (1UL << 21U) /*!< TMR4 output-compare compare flag - channel WL */ + +#define TMR4_FLAG_ALL (TMR4_FLAG_CNT_PEAK | TMR4_FLAG_CNT_VALLEY | TMR4_FLAG_RELOAD_TMR_U | \ + TMR4_FLAG_RELOAD_TMR_V | TMR4_FLAG_RELOAD_TMR_W | TMR4_FLAG_OC_CMP_UH | \ + TMR4_FLAG_OC_CMP_UL | TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL | \ + TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL) +/** + * @} + */ + +/** + * @defgroup TMR4_Interrupt TMR4 Interrupt + * @{ + */ +#define TMR4_INT_CNT_PEAK ((uint32_t)TMR4_CCSR_IRQPEN) /*!< Count peak interrupt */ +#define TMR4_INT_CNT_VALLEY ((uint32_t)TMR4_CCSR_IRQZEN) /*!< Count valley interrupt */ +#define TMR4_INT_RELOAD_TMR_U (1UL << 0U) /*!< TMR4 PWM reload-timer interrupt - channel U */ +#define TMR4_INT_RELOAD_TMR_V (1UL << 1U) /*!< TMR4 PWM reload-timer interrupt - channel W */ +#define TMR4_INT_RELOAD_TMR_W (1UL << 2U) /*!< TMR4 PWM reload-timer interrupt - channel V */ +#define TMR4_INT_OC_CMP_UH (1UL << 16U) /*!< TMR4 output-compare compare interrupt - channel UH */ +#define TMR4_INT_OC_CMP_UL (1UL << 17U) /*!< TMR4 output-compare compare interrupt - channel UL */ +#define TMR4_INT_OC_CMP_VH (1UL << 18U) /*!< TMR4 output-compare compare interrupt - channel VH */ +#define TMR4_INT_OC_CMP_VL (1UL << 19U) /*!< TMR4 output-compare compare interrupt - channel VL */ +#define TMR4_INT_OC_CMP_WH (1UL << 20U) /*!< TMR4 output-compare compare interrupt - channel WH */ +#define TMR4_INT_OC_CMP_WL (1UL << 21U) /*!< TMR4 output-compare compare interrupt - channel WL */ + +#define TMR4_INT_ALL (TMR4_INT_CNT_PEAK | TMR4_INT_CNT_VALLEY | TMR4_INT_RELOAD_TMR_U | \ + TMR4_INT_RELOAD_TMR_V | TMR4_INT_RELOAD_TMR_W | TMR4_INT_OC_CMP_UH | \ + TMR4_INT_OC_CMP_UL | TMR4_INT_OC_CMP_VH | TMR4_INT_OC_CMP_VL | \ + TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL) +/** + * @} + */ + +/** + * @defgroup TMR4_Count_Interrupt_Mask_Time TMR4 Count Interrupt Mask Time + * @{ + */ +#define TMR4_INT_CNT_MASK0 (0U) /*!< Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak */ +#define TMR4_INT_CNT_MASK1 (1U) /*!< Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skiping 1 count) */ +#define TMR4_INT_CNT_MASK2 (2U) /*!< Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skiping 2 count) */ +#define TMR4_INT_CNT_MASK3 (3U) /*!< Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skiping 3 count) */ +#define TMR4_INT_CNT_MASK4 (4U) /*!< Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skiping 4 count) */ +#define TMR4_INT_CNT_MASK5 (5U) /*!< Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skiping 5 count) */ +#define TMR4_INT_CNT_MASK6 (6U) /*!< Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skiping 6 count) */ +#define TMR4_INT_CNT_MASK7 (7U) /*!< Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skiping 7 count) */ +#define TMR4_INT_CNT_MASK8 (8U) /*!< Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skiping 8 count) */ +#define TMR4_INT_CNT_MASK9 (9U) /*!< Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skiping 9 count) */ +#define TMR4_INT_CNT_MASK10 (10U) /*!< Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skiping 10 count) */ +#define TMR4_INT_CNT_MASK11 (11U) /*!< Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skiping 11 count) */ +#define TMR4_INT_CNT_MASK12 (12U) /*!< Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skiping 12 count) */ +#define TMR4_INT_CNT_MASK13 (13U) /*!< Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skiping 13 count) */ +#define TMR4_INT_CNT_MASK14 (14U) /*!< Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skiping 14 count) */ +#define TMR4_INT_CNT_MASK15 (15U) /*!< Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skiping 15 count) */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_Output_Compare_Macros TMR4 Output-Compare Macros + * @{ + */ + +/** + * @defgroup TMR4_OC_Channel TMR4 OC Channel + * @{ + */ +#define TMR4_OC_CH_UH (0UL) /*!< TMR4 OC channel:UH */ +#define TMR4_OC_CH_UL (1UL) /*!< TMR4 OC channel:UL */ +#define TMR4_OC_CH_VH (2UL) /*!< TMR4 OC channel:VH */ +#define TMR4_OC_CH_VL (3UL) /*!< TMR4 OC channel:VL */ +#define TMR4_OC_CH_WH (4UL) /*!< TMR4 OC channel:WH */ +#define TMR4_OC_CH_WL (5UL) /*!< TMR4 OC channel:WL */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Invalid_Output_Polarity TMR4 OC Invalid Output Polarity + * @{ + */ +#define TMR4_OC_INVD_LOW (0U) /*!< TMR4 OC Output low level when OC is invalid */ +#define TMR4_OC_INVD_HIGH (TMR4_OCSR_OCPH) /*!< TMR4 OC Output high level when OC is invalid */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Buffer_Object TMR4 OC Buffer Object + * @{ + */ +#define TMR4_OC_BUF_CMP_VALUE (0x01U) /*!< The register OCCR buffer function index */ +#define TMR4_OC_BUF_CMP_MD (0x02U) /*!< The register OCMR buffer function index */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Buffer_Transfer_Condition TMR4 OC OCCR Buffer Transfer Condition + * @{ + */ +#define TMR4_OC_BUF_COND_IMMED (0U) /*!< Buffer transfer is made when writing to the OCCR/OCMR register. */ +#define TMR4_OC_BUF_COND_VALLEY (1U) /*!< Buffer transfer is made when counter count valley */ +#define TMR4_OC_BUF_COND_PEAK (2U) /*!< Buffer transfer is made when counter count peak */ +#define TMR4_OC_BUF_COND_PEAK_VALLEY (3U) /*!< Buffer transfer is made when counter count peak or valley */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Count_Match_OCF_State TMR4 OC Count Match OCF State + * @{ + */ +#define TMR4_OC_OCF_HOLD (0U) /*!< Hold OCF when the TMR4 OC count match */ +#define TMR4_OC_OCF_SET (TMR4_OCMRH_OCFDCH) /*!< Set OCF when the TMR4 OC count match */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Count_Match_Output_Polarity TMR4 OC Count Match Output Polarity + * @{ + */ +#define TMR4_OC_HOLD (0U) /*!< Hold output when the TMR4 OC count match */ +#define TMR4_OC_HIGH (1U) /*!< Output high when the TMR4 OC count match */ +#define TMR4_OC_LOW (2U) /*!< Output low when the TMR4 OC count match */ +#define TMR4_OC_INVT (3U) /*!< Invert output when the TMR4 OC count match */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Macros TMR4 PWM Macros + * @{ + */ + +/** + * @defgroup TMR4_PWM_Channel TMR4 PWM Channel + * @{ + */ +#define TMR4_PWM_CH_U (0UL) /*!< TMR4 PWM couple channel: U */ +#define TMR4_PWM_CH_V (1UL) /*!< TMR4 PWM couple channel: V */ +#define TMR4_PWM_CH_W (2UL) /*!< TMR4 PWM couple channel: W */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Pin TMR4 PWM Pin + * @{ + */ +#define TMR4_PWM_PIN_OUH (0UL) /*!< TMR4 PWM port: TIM4__OUH */ +#define TMR4_PWM_PIN_OUL (1UL) /*!< TMR4 PWM port: TIM4__OUL */ +#define TMR4_PWM_PIN_OVH (2UL) /*!< TMR4 PWM port: TIM4__OVH */ +#define TMR4_PWM_PIN_OVL (3UL) /*!< TMR4 PWM port: TIM4__OVL */ +#define TMR4_PWM_PIN_OWH (4UL) /*!< TMR4 PWM port: TIM4__OWH */ +#define TMR4_PWM_PIN_OWL (5UL) /*!< TMR4 PWM port: TIM4__OWL */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Clock_Division TMR4 PWM Clock Division + * @{ + */ +#define TMR4_PWM_CLK_DIV1 (0U) /*!< CLK */ +#define TMR4_PWM_CLK_DIV2 (1U << TMR4_POCR_DIVCK_POS) /*!< CLK/2 */ +#define TMR4_PWM_CLK_DIV4 (2U << TMR4_POCR_DIVCK_POS) /*!< CLK/8 */ +#define TMR4_PWM_CLK_DIV8 (3U << TMR4_POCR_DIVCK_POS) /*!< CLK/8 */ +#define TMR4_PWM_CLK_DIV16 (4U << TMR4_POCR_DIVCK_POS) /*!< CLK/16 */ +#define TMR4_PWM_CLK_DIV32 (5U << TMR4_POCR_DIVCK_POS) /*!< CLK/32 */ +#define TMR4_PWM_CLK_DIV64 (6U << TMR4_POCR_DIVCK_POS) /*!< CLK/64 */ +#define TMR4_PWM_CLK_DIV128 (7U << TMR4_POCR_DIVCK_POS) /*!< CLK/128 */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Mode TMR4 PWM Mode + * @{ + */ +#define TMR4_PWM_MD_THROUGH (0U) /*!< Through mode */ +#define TMR4_PWM_MD_DEAD_TMR (TMR4_POCR_PWMMD_0) /*!< Dead timer mode */ +#define TMR4_PWM_MD_DEAD_TMR_FILTER (TMR4_POCR_PWMMD_1) /*!< Dead timer filter mode */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Polarity TMR4 PWM Polarity + * @{ + */ +#define TMR4_PWM_OXH_HOLD_OXL_HOLD (0U) /*!< Output PWML and PWMH signals without changing the level */ +#define TMR4_PWM_OXH_INVT_OXL_INVT (TMR4_POCR_LVLS_0) /*!< Output both PWML and PWMH signals reversed */ +#define TMR4_PWM_OXH_INVT_OXL_HOLD (TMR4_POCR_LVLS_1) /*!< Output the PWMH signal reversed, outputs the PWML signal without changing the level. */ +#define TMR4_PWM_OXH_HOLD_OXL_INVT (TMR4_POCR_LVLS) /*!< Output the PWMH signal without changing the level, Outputs the PWML signal reversed. */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Dead_Time_Register_Index TMR4 PWM Dead Time Register Index + * @{ + */ +#define TMR4_PWM_PDAR_IDX (0UL) /*!< TMR4_PDARn(n=U/V/W) */ +#define TMR4_PWM_PDBR_IDX (1UL) /*!< TMR4_PDBRn(n=U/V/W) */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Abnormal_Pin_Status TMR4 PWM Abnormal Pin Status + * @{ + */ +#define TMR4_PWM_ABNORMAL_PIN_NORMAL (0UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output normal */ +#define TMR4_PWM_ABNORMAL_PIN_HIZ (1UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) to Hi-z */ +#define TMR4_PWM_ABNORMAL_PIN_LOW (2UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output low level */ +#define TMR4_PWM_ABNORMAL_PIN_HIGH (3UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output high level */ +#define TMR4_PWM_ABNORMAL_PIN_HOLD (4UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output hold */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Macros TMR4 Event Macros + * @{ + */ + +/** + * @defgroup TMR4_Event_Channel TMR4 Event Channel + * @{ + */ +#define TMR4_EVT_CH_UH (0UL) /*!< TMR4 EVT channel:UH */ +#define TMR4_EVT_CH_UL (1UL) /*!< TMR4 EVT channel:UL */ +#define TMR4_EVT_CH_VH (2UL) /*!< TMR4 EVT channel:VH */ +#define TMR4_EVT_CH_VL (3UL) /*!< TMR4 EVT channel:VL */ +#define TMR4_EVT_CH_WH (4UL) /*!< TMR4 EVT channel:WH */ +#define TMR4_EVT_CH_WL (5UL) /*!< TMR4 EVT channel:WL */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Match_Condition TMR4 Event Match Condition + * @{ + */ +#define TMR4_EVT_MATCH_CNT_UP (TMR4_SCSR_UEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count up */ +#define TMR4_EVT_MATCH_CNT_DOWN (TMR4_SCSR_DEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count down */ +#define TMR4_EVT_MATCH_CNT_PEAK (TMR4_SCSR_PEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count peak */ +#define TMR4_EVT_MATCH_CNT_VALLEY (TMR4_SCSR_ZEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count vallay */ +#define TMR4_EVT_MATCH_CNT_ALL (TMR4_EVT_MATCH_CNT_DOWN | TMR4_EVT_MATCH_CNT_UP | \ + TMR4_EVT_MATCH_CNT_PEAK | TMR4_EVT_MATCH_CNT_VALLEY) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Mask TMR4 Event Mask + * @{ + */ +#define TMR4_EVT_MASK_PEAK (TMR4_SCMR_MPCE) /*!< Match with the count peak interrupt mask of the counter */ +#define TMR4_EVT_MASK_VALLEY (TMR4_SCMR_MZCE) /*!< Match with the count valley interrupt mask of the counter */ +#define TMR4_EVT_MASK_TYPE_ALL (TMR4_EVT_MASK_PEAK | TMR4_EVT_MASK_VALLEY) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Buffer_Transfer_Condition TMR4 Event Buffer Transfer Condition + * @{ + */ +#define TMR4_EVT_BUF_COND_IMMED (0U) /*!< Register SCCR&SCMR buffer transfer when writing to the SCCR&SCMR register */ +#define TMR4_EVT_BUF_COND_VALLEY (TMR4_SCSR_BUFEN_0) /*!< Register SCCR&SCMR buffer transfer when counter count valley */ +#define TMR4_EVT_BUF_COND_PEAK (TMR4_SCSR_BUFEN_1) /*!< Register SCCR&SCMR buffer transfer when counter count peak */ +#define TMR4_EVT_BUF_COND_PEAK_VALLEY (TMR4_SCSR_BUFEN) /*!< Register SCCR&SCMR buffer transfer when counter count peak or valley */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Mode TMR4 Event Mode + * @{ + */ +#define TMR4_EVT_MD_CMP (0U) /*!< TMR4 EVT compare mode */ +#define TMR4_EVT_MD_DELAY (TMR4_SCSR_EVTMS) /*!< TMR4 EVT delay mode */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Delay_Object TMR4 Event Delay Object + * @{ + */ +#define TMR4_EVT_DELAY_OCCRXH (0U) /*!< TMR4 EVT delay object: OCCRxh(x=u/v/w) */ +#define TMR4_EVT_DELAY_OCCRXL (TMR4_SCSR_EVTDS) /*!< TMR4 EVT delay object: OCCRxl(x=u/v/w) */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Mask_Times TMR4 Event Mask Times + * @{ + */ +#define TMR4_EVT_MASK0 (0U << TMR4_SCMR_AMC_POS) /*!< Mask 0 time */ +#define TMR4_EVT_MASK1 (1U << TMR4_SCMR_AMC_POS) /*!< Mask 1 times */ +#define TMR4_EVT_MASK2 (2U << TMR4_SCMR_AMC_POS) /*!< Mask 2 times */ +#define TMR4_EVT_MASK3 (3U << TMR4_SCMR_AMC_POS) /*!< Mask 3 times */ +#define TMR4_EVT_MASK4 (4U << TMR4_SCMR_AMC_POS) /*!< Mask 4 times */ +#define TMR4_EVT_MASK5 (5U << TMR4_SCMR_AMC_POS) /*!< Mask 5 times */ +#define TMR4_EVT_MASK6 (6U << TMR4_SCMR_AMC_POS) /*!< Mask 6 times */ +#define TMR4_EVT_MASK7 (7U << TMR4_SCMR_AMC_POS) /*!< Mask 7 times */ +#define TMR4_EVT_MASK8 (8U << TMR4_SCMR_AMC_POS) /*!< Mask 8 times */ +#define TMR4_EVT_MASK9 (9U << TMR4_SCMR_AMC_POS) /*!< Mask 9 times */ +#define TMR4_EVT_MASK10 (10U << TMR4_SCMR_AMC_POS) /*!< Mask 10 times */ +#define TMR4_EVT_MASK11 (11U << TMR4_SCMR_AMC_POS) /*!< Mask 11 times */ +#define TMR4_EVT_MASK12 (12U << TMR4_SCMR_AMC_POS) /*!< Mask 12 times */ +#define TMR4_EVT_MASK13 (13U << TMR4_SCMR_AMC_POS) /*!< Mask 13 times */ +#define TMR4_EVT_MASK14 (14U << TMR4_SCMR_AMC_POS) /*!< Mask 14 times */ +#define TMR4_EVT_MASK15 (15U << TMR4_SCMR_AMC_POS) /*!< Mask 15 times */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Output_Event TMR4 Event Output Event + * @{ + */ +#define TMR4_EVT_OUTPUT_EVT0 (0U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 0 */ +#define TMR4_EVT_OUTPUT_EVT1 (1U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 1 */ +#define TMR4_EVT_OUTPUT_EVT2 (2U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 2 */ +#define TMR4_EVT_OUTPUT_EVT3 (3U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 3 */ +#define TMR4_EVT_OUTPUT_EVT4 (4U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 4 */ +#define TMR4_EVT_OUTPUT_EVT5 (5U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 5 */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Output_Signal TMR4 Event Output Signal + * @{ + */ +#define TMR4_EVT_OUTPUT_NONE (0U) /*!< Disable output event signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT0_SIGNAL (1U) /*!< Output the specified event 0 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT1_SIGNAL (2U) /*!< Output the specified event 1 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT2_SIGNAL (3U) /*!< Output the specified event 2 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT3_SIGNAL (4U) /*!< Output the specified event 3 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT4_SIGNAL (5U) /*!< Output the specified event 4 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT5_SIGNAL (6U) /*!< Output the specified event 5 signal of TMR4 Special-EVT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR4_Global_Functions + * @{ + */ + +/** + * @addtogroup TMR4_Counter_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 counter functions */ +int32_t TMR4_StructInit(stc_tmr4_init_t *pstcTmr4Init); +int32_t TMR4_Init(CM_TMR4_TypeDef *TMR4x, const stc_tmr4_init_t *pstcTmr4Init); +void TMR4_DeInit(CM_TMR4_TypeDef *TMR4x); +void TMR4_SetClockSrc(CM_TMR4_TypeDef *TMR4x, uint16_t u16Src); +void TMR4_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint16_t u16Div); +void TMR4_SetCountMode(CM_TMR4_TypeDef *TMR4x, uint16_t u16Mode); +uint16_t TMR4_GetPeriodValue(const CM_TMR4_TypeDef *TMR4x); +void TMR4_SetPeriodValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value); +uint16_t TMR4_GetCountValue(const CM_TMR4_TypeDef *TMR4x); +void TMR4_SetCountValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value); +void TMR4_ClearCountValue(CM_TMR4_TypeDef *TMR4x); +void TMR4_Start(CM_TMR4_TypeDef *TMR4x); +void TMR4_Stop(CM_TMR4_TypeDef *TMR4x); +void TMR4_ClearStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag); +en_flag_status_t TMR4_GetStatus(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag); +void TMR4_IntCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, en_functional_state_t enNewState); +void TMR4_PeriodBufCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState); +uint16_t TMR4_GetCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint16_t u16IntType); +void TMR4_SetCountIntMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, uint16_t u16MaskTime); +uint16_t TMR4_GetCurrentCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint16_t u16IntType); + +/** + * @} + */ + +/** + * @addtogroup TMR4_Output_Compare_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 Output-Compare functions */ +int32_t TMR4_OC_StructInit(stc_tmr4_oc_init_t *pstcTmr4OcInit); +int32_t TMR4_OC_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_oc_init_t *pstcTmr4OcInit); +void TMR4_OC_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +uint16_t TMR4_OC_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value); +void TMR4_OC_Cmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR4_OC_ExtendControlCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR4_OC_BufIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16Object, en_functional_state_t enNewState); +uint16_t TMR4_OC_GetPolarity(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetOcInvalidPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity); +void TMR4_OC_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object, uint16_t u16BufCond); +uint16_t TMR4_OC_GetHighChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetHighChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrh_t unTmr4Ocmrh); +uint32_t TMR4_OC_GetLowChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetLowChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrl_t unTmr4Ocmrl); +/** + * @} + */ + +/** + * @addtogroup TMR4_PWM_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 PWM functions */ +int32_t TMR4_PWM_StructInit(stc_tmr4_pwm_init_t *pstcTmr4PwmInit); +int32_t TMR4_PWM_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_pwm_init_t *pstcTmr4PwmInit); +void TMR4_PWM_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Div); +void TMR4_PWM_SetPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity); +void TMR4_PWM_StartReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_StopReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_SetFilterCountValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value); +void TMR4_PWM_SetDeadTimeValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex, uint16_t u16Value); +uint16_t TMR4_PWM_GetDeadTimeValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex); + +void TMR4_PWM_SetAbnormalPinStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32PinStatus); + +/** + * @} + */ + +/** + * @addtogroup TMR4_Event_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 event functions */ +int32_t TMR4_EVT_StructInit(stc_tmr4_evt_init_t *pstcTmr4EventInit); +int32_t TMR4_EVT_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_evt_init_t *pstcTmr4EventInit); +void TMR4_EVT_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_EVT_SetDelayObject(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object); +void TMR4_EVT_SetMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16MaskTime); +uint16_t TMR4_EVT_GetMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_EVT_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value); +uint16_t TMR4_EVT_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_EVT_SetOutputEvent(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Event); +void TMR4_EVT_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16BufCond); +void TMR4_EVT_BufIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR4_EVT_EventIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16MaskType, en_functional_state_t enNewState); +void TMR4_EVT_MatchCondCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LL_TMR4_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMR4_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr6.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr6.h new file mode 100644 index 0000000000..5ae751ae72 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr6.h @@ -0,0 +1,769 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr6.h + * @brief Head file for TMR6 module. + * + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMR6_H__ +#define __HC32_LL_TMR6_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMR6 + * @{ + */ + +#if (LL_TMR6_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR6_Global_Types TMR6 Global Types + * @{ + */ + +/** + * @brief Timer6 count function structure definition + */ +typedef struct { + uint8_t u8CountSrc; /*!< Specifies the count source @ref TMR6_Count_Src_Define */ + union { + struct { + uint32_t u32ClockDiv; /*!< Count clock division select, @ref TMR6_Count_Clock_Define */ + uint32_t u32CountMode; /*!< Count mode, @ref TMR6_Count_Mode_Define */ + uint32_t u32CountDir; /*!< Count direction, @ref TMR6_Count_Dir_Define */ + } sw_count; + struct { + uint32_t u32CountUpCond; /*!< Hardware count up condition. @ref TMR6_HW_Count_Up_Cond_Define */ + uint32_t u32CountDownCond; /*!< Hardware count down condition. @ref TMR6_HW_Count_Down_Cond_Define */ + uint32_t u32Reserved; /*!< Reserved */ + } hw_count; + }; + uint32_t u32PeriodValue; /*!< The period reference value. (0x00 ~ 0xFFFF) or (0x00 ~ 0xFFFFFFFF) */ +} stc_timer6_init_t; + +/** + * @brief Timer6 pwm output function structure definition + */ +typedef struct { + uint32_t u32CompareValue; /*!< Range (0 ~ 0xFFFF) or (0 ~ 0xFFFFFFFF) */ + uint32_t u32StartPolarity; /*!< Pin polarity when count start @ref TMR6_Pin_Polarity_Define */ + uint32_t u32StopPolarity; /*!< Pin polarity when count stop @ref TMR6_Pin_Polarity_Define */ + uint32_t u32CompareMatchPolarity; /*! Pin polarity when compare register @ref TMR6_Pin_Polarity_Define */ + uint32_t u32PeriodMatchPolarity; /*! Pin polarity when period register @ref TMR6_Pin_Polarity_Define */ + uint32_t u32StartStopHold; /*! Pin polarity hold when count re-start or re-stop \ + @ref TMR6_Output_StaStp_Hold_Define */ +} stc_tmr6_pwm_init_t; + +/** + * @brief Timer6 buffer function configuration structure definition + */ +typedef struct { + uint32_t u32BufNum; /*!< The buffer number, and this parameter can be a value of \ + @ref TMR6_Buf_Num_Define */ + uint32_t u32BufTransCond; /*!< The buffer send time, and this parameter can be a value of \ + @ref TMR6_Buf_Trans_Cond_Define */ +} stc_tmr6_buf_config_t; + +/** + * @brief Timer6 Valid period function configuration structure definition + */ +typedef struct { + uint32_t u32CountCond; /*!< The count condition, and this parameter can be a value of \ + @ref TMR6_Valid_Period_Count_Cond_Define */ + uint32_t u32PeriodInterval; /*!< The interval of the valid period @ref TMR6_Valid_Period_Count_Define */ +} stc_tmr6_valid_period_config_t; + +/** + * @brief Timer6 EMB configuration structure definition + */ +typedef struct { + uint32_t u32PinStatus; /*!< Pin output status when EMB event valid @ref TMR6_Emb_Pin_Status_Define */ +} stc_tmr6_emb_config_t; + +/** + * @brief Timer6 Dead time function configuration structure definition + */ +typedef struct { + uint32_t u32EqualUpDown; /*!< Enable down count dead time register equal to up count DT register \ + @ref TMR6_Deadtime_Reg_Equal_Func_Define */ + uint32_t u32BufUp; /*!< Enable buffer transfer for up count dead time register (DTUBR-->DTUAR) \ + @ref TMR6_Deadtime_CountUp_Buf_Func_Define*/ + uint32_t u32BufDown; /*!< Enable buffer transfer for down count dead time register (DTDBR-->DTDAR) \ + @ref TMR6_Deadtime_CountDown_Buf_Func_Define*/ +} stc_tmr6_deadtime_config_t; + +/** + * @brief Timer6 Dead time function configuration structure definition + */ +typedef struct { + uint32_t u32ZMaskCycle; /*!< Z phase input mask periods selection @ref TMR6_Zmask_Cycle_Define */ + uint32_t u32PosCountMaskFunc; /*!< As position count timer, clear function enable(TRUE) or disable(FALSE) during \ + the time of Z phase input mask @ref TMR6_Zmask_Pos_Unit_Clear_Func_Define */ + uint32_t u32RevoCountMaskFunc; /*!< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) \ + during the time of Z phase input mask \ + @ref TMR6_Zmask_Revo_Unit_Count_Func_Define*/ +} stc_tmr6_zmask_config_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR6_Global_Macros TMR6 Global Macros + * @{ + */ + +/** + * @defgroup TMR6_Count_Src_Define TMR6 Count Source Define + * @{ + */ +#define TMR6_CNT_SRC_SW (0U) /*!< Timer6 normal count function */ +#define TMR6_CNT_SRC_HW (1U) /*!< Timer6 hardware count function */ +/** + * @} + */ + +/** + * @defgroup TMR6_Stat_Flag_Define TMR6 Status Flag Define + * @{ + */ +#define TMR6_FLAG_MATCH_A (TMR6_STFLR_CMAF) /*!< GCMAR match counter */ +#define TMR6_FLAG_MATCH_B (TMR6_STFLR_CMBF) /*!< GCMBR match counter */ +#define TMR6_FLAG_MATCH_C (TMR6_STFLR_CMCF) /*!< GCMCR match counter */ +#define TMR6_FLAG_MATCH_D (TMR6_STFLR_CMDF) /*!< GCMDR match counter */ +#define TMR6_FLAG_MATCH_E (TMR6_STFLR_CMEF) /*!< GCMER match counter */ +#define TMR6_FLAG_MATCH_F (TMR6_STFLR_CMFF) /*!< GCMFR match counter */ +#define TMR6_FLAG_OVF (TMR6_STFLR_OVFF) /*!< Sawtooth wave counter overflow, \ + Triangular wave peak point */ +#define TMR6_FLAG_UDF (TMR6_STFLR_UDFF) /*!< Sawtooth wave counter underflow, \ + Triangular wave valley point */ +#define TMR6_FLAG_DEAD_TIME_ERR (TMR6_STFLR_DTEF) /*!< Dead time error */ +#define TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A (TMR6_STFLR_CMSAUF) /*!< SCMAR match counter when count-up */ +#define TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A (TMR6_STFLR_CMSADF) /*!< SCMAR match counter when count-down */ +#define TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B (TMR6_STFLR_CMSBUF) /*!< SCMBR match counter when count-up */ +#define TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B (TMR6_STFLR_CMSBDF) /*!< SCMBR match counter when count-down */ +#define TMR6_FLAG_CNT_DIR (TMR6_STFLR_DIRF) /*!< Count direction flag */ +#define TMR6_FLAG_CLR_ALL (0x00001EFFUL) /*!< Clear all flag */ +#define TMR6_FLAG_ALL (TMR6_FLAG_MATCH_A | TMR6_FLAG_MATCH_B | TMR6_FLAG_MATCH_C | \ + TMR6_FLAG_MATCH_D | TMR6_FLAG_MATCH_E | TMR6_FLAG_MATCH_F | \ + TMR6_FLAG_OVF | TMR6_FLAG_UDF | TMR6_FLAG_DEAD_TIME_ERR | \ + TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A | TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A | \ + TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B | TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B | \ + TMR6_FLAG_CNT_DIR) +/** + * @} + */ + +/** + * @defgroup TMR6_Int_Flag_Define TMR6 Interrupt Flag Define + * @{ + */ +#define TMR6_INT_MATCH_A (TMR6_ICONR_INTENA) /*!< GCMAR register matched */ +#define TMR6_INT_MATCH_B (TMR6_ICONR_INTENB) /*!< GCMBR register matched */ +#define TMR6_INT_MATCH_C (TMR6_ICONR_INTENC) /*!< GCMCR register matched */ +#define TMR6_INT_MATCH_D (TMR6_ICONR_INTEND) /*!< GCMDR register matched */ +#define TMR6_INT_MATCH_E (TMR6_ICONR_INTENE) /*!< GCMER register matched */ +#define TMR6_INT_MATCH_F (TMR6_ICONR_INTENF) /*!< GCMFR register matched */ +#define TMR6_INT_OVF (TMR6_ICONR_INTENOVF) /*!< Counter register overflow */ +#define TMR6_INT_UDF (TMR6_ICONR_INTENUDF) /*!< Counter register underflow */ +#define TMR6_INT_DEAD_TIME_ERR (TMR6_ICONR_INTENDTE) /*!< Dead time error */ +#define TMR6_INT_UP_CNT_SPECIAL_MATCH_A (TMR6_ICONR_INTENSAU) /*!< SCMAR register matched when count-up */ +#define TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A (TMR6_ICONR_INTENSAD) /*!< SCMAR register matched when count-down */ +#define TMR6_INT_UP_CNT_SPECIAL_MATCH_B (TMR6_ICONR_INTENSBU) /*!< SCMBR register matched when count-up */ +#define TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B (TMR6_ICONR_INTENSBD) /*!< SCMBR register matched when count-down */ +#define TMR6_INT_ALL (TMR6_INT_MATCH_A | TMR6_INT_MATCH_B | TMR6_INT_MATCH_C | TMR6_INT_MATCH_D |\ + TMR6_INT_MATCH_E | TMR6_INT_MATCH_F | TMR6_INT_OVF | TMR6_INT_UDF | \ + TMR6_INT_DEAD_TIME_ERR | TMR6_INT_UP_CNT_SPECIAL_MATCH_A | \ + TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A | TMR6_INT_UP_CNT_SPECIAL_MATCH_B | \ + TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B) +/** + * @} + */ + +/** + * @defgroup TMR6_Period_Reg_Index_Define TMR6 Period Register Index Define + * @{ + */ +#define TMR6_PERIOD_REG_A (0x00UL) +#define TMR6_PERIOD_REG_B (0x01UL) +#define TMR6_PERIOD_REG_C (0x02UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Compare_Reg_Index_Define TMR6 Compare Register Index Define + * @{ + */ +#define TMR6_CMP_REG_A (0x00UL) +#define TMR6_CMP_REG_B (0x01UL) +#define TMR6_CMP_REG_C (0x02UL) +#define TMR6_CMP_REG_D (0x03UL) +#define TMR6_CMP_REG_E (0x04UL) +#define TMR6_CMP_REG_F (0x05UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Ch_Define TMR6 General/Special Compare Channel Define + * @{ + */ +#define TMR6_CH_A (0x00UL) +#define TMR6_CH_B (0x01UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Buf_Num_Define TMR6 Buffer Number Define + * @{ + */ +#define TMR6_BUF_SINGLE (0x00000000UL) +#define TMR6_BUF_DUAL (TMR6_BCONR_BSEA) +/** + * @} + */ + +/** + * @defgroup TMR6_Buf_Trans_Cond_Define TMR6 Buffer Transfer Time Configuration Define + * @{ + */ +#define TMR6_BUF_TRANS_INVD (0x00000000UL) +#define TMR6_BUF_TRANS_OVF (0x00000004UL) +#define TMR6_BUF_TRANS_UDF (0x00000008UL) +#define TMR6_BUF_TRANS_OVF_UDF (0x0000000CUL) + +/** + * @} + */ + +/** + * @defgroup TMR6_Valid_Period_Count_Cond_Define TMR6 Valid Period Function Count Condition Define + * @{ + */ +#define TMR6_VALID_PERIOD_INVD (0x00000000UL) /*!< Valid period function off */ +#define TMR6_VALID_PERIOD_CNT_COND_UDF (TMR6_VPERR_PCNTE_0) /*!< Count when Sawtooth waveform overflow and underflow, \ + triangular wave underflow */ +#define TMR6_VALID_PERIOD_CNT_COND_OVF (TMR6_VPERR_PCNTE_1) /*!< Count when Sawtooth waveform overflow and underflow, \ + triangular wave overflow */ +#define TMR6_VALID_PERIOD_CNT_COND_OVF_UDF (TMR6_VPERR_PCNTE) /*!< Count when Sawtooth waveform overflow and underflow, \ + triangular wave overflow and underflow */ +/** + * @} + */ + +/** + * @defgroup TMR6_Valid_Period_Count_Define TMR6 Valid Period Function Count Define + * @{ + */ +#define TMR6_VALID_PERIOD_CNT_INVD (0x00000000UL) +#define TMR6_VALID_PERIOD_CNT1 (1UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT2 (2UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT3 (3UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT4 (4UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT5 (5UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT6 (6UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT7 (7UL << TMR6_VPERR_PCNTS_POS) +/** + * @} + */ + +/** + * @defgroup TMR6_DeadTime_Reg_Define TMR6 Dead Time Register Define + * @{ + */ +#define TMR6_DEADTIME_REG_UP_A (0x00U) /*!< Register DTUAR */ +#define TMR6_DEADTIME_REG_DOWN_A (0x01U) /*!< Register DTDAR */ +#define TMR6_DEADTIME_REG_UP_B (0x02U) /*!< Register DTUBR */ +#define TMR6_DEADTIME_REG_DOWN_B (0x03U) /*!< Register DTDBR */ + +/** + * @} + */ + +/** + * @defgroup TMR6_Pin_Define TMR6 Input And Output Pin Define + * @{ + */ +#define TMR6_IO_PWMA (0x00U) /*!< Pin TIM6__PWMA */ +#define TMR6_IO_PWMB (0x01U) /*!< Pin TIM6__PWMB */ +#define TMR6_INPUT_TRIGA (0x02U) /*!< Input pin TIM6_TRIGA */ +#define TMR6_INPUT_TRIGB (0x03U) /*!< Input pin TIM6_TRIGB */ +/** + * @} + */ + +/** + * @defgroup TMR6_Input_Filter_Clock TMR6 Input Pin Filter Clock Divider Define + * @{ + */ +#define TMR6_FILTER_CLK_DIV1 (0x00U) +#define TMR6_FILTER_CLK_DIV4 (0x01U) +#define TMR6_FILTER_CLK_DIV16 (0x02U) +#define TMR6_FILTER_CLK_DIV64 (0x03U) +/** + * @} + */ + +/** + * @defgroup TMR6_Pin_Mode_Define TMR6 Pin Function Mode Selection + * @{ + */ +#define TMR6_PIN_CMP_OUTPUT (0x00U) +#define TMR6_PIN_CAPT_INPUT (TMR6_PCONR_CAPMDA) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_State_Define TMR6 Count State + * @{ + */ +#define TMR6_STAT_START (0U) /*!< Count start */ +#define TMR6_STAT_STOP (1U) /*!< Count stop */ +#define TMR6_STAT_MATCH_CMP (2U) /*!< Count match compare register */ +#define TMR6_STAT_MATCH_PERIOD (3U) /*!< Count match period register */ + +/** + * @} + */ + +/** + * @defgroup TMR6_Pin_Polarity_Define TMR6 Pin Output Polarity + * @{ + */ + +#define TMR6_PWM_LOW (0x00U) +#define TMR6_PWM_HIGH (0x01U) +#define TMR6_PWM_HOLD (0x02U) +#define TMR6_PWM_INVT (0x03U) +/** + * @} + */ + +/** + * @defgroup TMR6_Output_StaStp_Hold_Define TMR6 Output Polarity Hold When Count Start And Stop + * @{ + */ +#define TMR6_PWM_START_STOP_HOLD (TMR6_PCONR_STASTPSA) +#define TMR6_PWM_START_STOP_CHANGE (0UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Emb_Pin_Status_Define TMR6 Pin Output Status When EMB Event Valid + * @{ + */ +#define TMR6_EMB_PIN_NORMAL (0x00U) +#define TMR6_EMB_PIN_HIZ (TMR6_PCONR_EMBVALA_0) +#define TMR6_EMB_PIN_LOW (TMR6_PCONR_EMBVALA_1) +#define TMR6_EMB_PIN_HIGH (TMR6_PCONR_EMBVALA) +/** + * @} + */ + +/** + * @defgroup TMR6_Deadtime_CountUp_Buf_Func_Define TMR6 Dead Time Buffer Function For Count Up Stage + * @{ + */ +#define TMR6_DEADTIME_CNT_UP_BUF_OFF (0x00U) +#define TMR6_DEADTIME_CNT_UP_BUF_ON (TMR6_DCONR_DTBENU) +/** + * @} + */ + +/** + * @defgroup TMR6_Deadtime_CountDown_Buf_Func_Define TMR6 Dead Time Buffer Function For Count Down Stage + * @{ + */ +#define TMR6_DEADTIME_CNT_DOWN_BUF_OFF (0x00U) +#define TMR6_DEADTIME_CNT_DOWN_BUF_ON (TMR6_DCONR_DTBEND) +/** + * @} + */ + +/** + * @defgroup TMR6_Deadtime_Reg_Equal_Func_Define TMR6 Dead Time Function DTDAR Equal DTUAR + * @{ + */ +#define TMR6_DEADTIME_EQUAL_OFF (0x00U) +#define TMR6_DEADTIME_EQUAL_ON (TMR6_DCONR_SEPA) +/** + * @} + */ + +/** + * @defgroup TMR6_SW_Sync_Unit_define TMR6 Software Synchronization Start/Stop/Clear/Update Unit Number Define + * @{ + */ +#define TMR6_SW_SYNC_U1 (TMR6CR_SSTAR_SSTA1) +#define TMR6_SW_SYNC_U2 (TMR6CR_SSTAR_SSTA2) +#define TMR6_SW_SYNC_U3 (TMR6CR_SSTAR_SSTA3) +#define TMR6_SW_SYNC_ALL (0x07U) +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_start_condition_Define TMR6 Hardware Start Condition Define + * @{ + */ +#define TMR6_START_COND_EVT0 (TMR6_HSTAR_HSTA0) +#define TMR6_START_COND_EVT1 (TMR6_HSTAR_HSTA1) +#define TMR6_START_COND_PWMA_RISING (TMR6_HSTAR_HSTA4) +#define TMR6_START_COND_PWMA_FAILLING (TMR6_HSTAR_HSTA5) +#define TMR6_START_COND_PWMB_RISING (TMR6_HSTAR_HSTA6) +#define TMR6_START_COND_PWMB_FAILLING (TMR6_HSTAR_HSTA7) +#define TMR6_START_COND_TRIGEA_RISING (TMR6_HSTAR_HSTA8) +#define TMR6_START_COND_TRIGEA_FAILLING (TMR6_HSTAR_HSTA9) +#define TMR6_START_COND_TRIGEB_RISING (TMR6_HSTAR_HSTA10) +#define TMR6_START_COND_TRIGEB_FAILLING (TMR6_HSTAR_HSTA11) +#define TMR6_START_COND_ALL (0x00000FF3UL) +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_stop_condition_Define TMR6 Hardware Stop Condition Define + * @{ + */ +#define TMR6_STOP_COND_EVT0 (TMR6_HSTPR_HSTP0) +#define TMR6_STOP_COND_EVT1 (TMR6_HSTPR_HSTP1) +#define TMR6_STOP_COND_PWMA_RISING (TMR6_HSTPR_HSTP4) +#define TMR6_STOP_COND_PWMA_FAILLING (TMR6_HSTPR_HSTP5) +#define TMR6_STOP_COND_PWMB_RISING (TMR6_HSTPR_HSTP6) +#define TMR6_STOP_COND_PWMB_FAILLING (TMR6_HSTPR_HSTP7) +#define TMR6_STOP_COND_TRIGEA_RISING (TMR6_HSTPR_HSTP8) +#define TMR6_STOP_COND_TRIGEA_FAILLING (TMR6_HSTPR_HSTP9) +#define TMR6_STOP_COND_TRIGEB_RISING (TMR6_HSTPR_HSTP10) +#define TMR6_STOP_COND_TRIGEB_FAILLING (TMR6_HSTPR_HSTP11) +#define TMR6_STOP_COND_ALL (0x00000FF3UL) +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_clear_condition_Define TMR6 Hardware Clear Condition Define + * @{ + */ +#define TMR6_CLR_COND_EVT0 (TMR6_HCLRR_HCLE0) +#define TMR6_CLR_COND_EVT1 (TMR6_HCLRR_HCLE1) +#define TMR6_CLR_COND_PWMA_RISING (TMR6_HCLRR_HCLE4) +#define TMR6_CLR_COND_PWMA_FAILLING (TMR6_HCLRR_HCLE5) +#define TMR6_CLR_COND_PWMB_RISING (TMR6_HCLRR_HCLE6) +#define TMR6_CLR_COND_PWMB_FAILLING (TMR6_HCLRR_HCLE7) +#define TMR6_CLR_COND_TRIGEA_RISING (TMR6_HCLRR_HCLE8) +#define TMR6_CLR_COND_TRIGEA_FAILLING (TMR6_HCLRR_HCLE9) +#define TMR6_CLR_COND_TRIGEB_RISING (TMR6_HCLRR_HCLE10) +#define TMR6_CLR_COND_TRIGEB_FAILLING (TMR6_HCLRR_HCLE11) +#define TMR6_CLR_COND_ALL (0x00000FF3UL) +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_capture_condition_Define TMR6 Hardware Capture Condition Define + * @{ + */ +#define TMR6_CAPT_COND_EVT0 (TMR6_HCPAR_HCPA0) +#define TMR6_CAPT_COND_EVT1 (TMR6_HCPAR_HCPA1) +#define TMR6_CAPT_COND_PWMA_RISING (TMR6_HCPAR_HCPA4) +#define TMR6_CAPT_COND_PWMA_FAILLING (TMR6_HCPAR_HCPA5) +#define TMR6_CAPT_COND_PWMB_RISING (TMR6_HCPAR_HCPA6) +#define TMR6_CAPT_COND_PWMB_FAILLING (TMR6_HCPAR_HCPA7) +#define TMR6_CAPT_COND_TRIGEA_RISING (TMR6_HCPAR_HCPA8) +#define TMR6_CAPT_COND_TRIGEA_FAILLING (TMR6_HCPAR_HCPA9) +#define TMR6_CAPT_COND_TRIGEB_RISING (TMR6_HCPAR_HCPA10) +#define TMR6_CAPT_COND_TRIGEB_FAILLING (TMR6_HCPAR_HCPA11) +#define TMR6_CAPT_COND_ALL (0x00000FF3UL) +/** + * @} + */ + +/** + * @defgroup TMR6_HW_Count_Up_Cond_Define TMR6 Hardware Count Up Condition Define + * @{ + */ +#define TMR6_CNT_UP_COND_PWMA_LOW_PWMB_RISING (TMR6_HCUPR_HCUP0) +#define TMR6_CNT_UP_COND_PWMA_LOW_PWMB_FAILLING (TMR6_HCUPR_HCUP1) +#define TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING (TMR6_HCUPR_HCUP2) +#define TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_FAILLING (TMR6_HCUPR_HCUP3) +#define TMR6_CNT_UP_COND_PWMB_LOW_PWMA_RISING (TMR6_HCUPR_HCUP4) +#define TMR6_CNT_UP_COND_PWMB_LOW_PWMA_FAILLING (TMR6_HCUPR_HCUP5) +#define TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_RISING (TMR6_HCUPR_HCUP6) +#define TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_FAILLING (TMR6_HCUPR_HCUP7) +#define TMR6_CNT_UP_COND_TRIGEA_RISING (TMR6_HCUPR_HCUP8) +#define TMR6_CNT_UP_COND_TRIGEA_FAILLING (TMR6_HCUPR_HCUP9) +#define TMR6_CNT_UP_COND_TRIGEB_RISING (TMR6_HCUPR_HCUP10) +#define TMR6_CNT_UP_COND_TRIGEB_FAILLING (TMR6_HCUPR_HCUP11) +#define TMR6_CNT_UP_COND_EVT0 (TMR6_HCUPR_HCUP16) +#define TMR6_CNT_UP_COND_EVT1 (TMR6_HCUPR_HCUP17) +#define TMR6_CNT_UP_COND_ALL (0x00030FFFUL) +/** + * @} + */ + +/** + * @defgroup TMR6_HW_Count_Down_Cond_Define TMR6 Hardware Count Down Condition Define + * @{ + */ +#define TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_RISING (TMR6_HCDOR_HCDO0) +#define TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_FAILLING (TMR6_HCDOR_HCDO1) +#define TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_RISING (TMR6_HCDOR_HCDO2) +#define TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_FAILLING (TMR6_HCDOR_HCDO3) +#define TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_RISING (TMR6_HCDOR_HCDO4) +#define TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_FAILLING (TMR6_HCDOR_HCDO5) +#define TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING (TMR6_HCDOR_HCDO6) +#define TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_FAILLING (TMR6_HCDOR_HCDO7) +#define TMR6_CNT_DOWN_COND_TRIGEA_RISING (TMR6_HCDOR_HCDO8) +#define TMR6_CNT_DOWN_COND_TRIGEA_FAILLING (TMR6_HCDOR_HCDO9) +#define TMR6_CNT_DOWN_COND_TRIGEB_RISING (TMR6_HCDOR_HCDO10) +#define TMR6_CNT_DOWN_COND_TRIGEB_FAILLING (TMR6_HCDOR_HCDO11) +#define TMR6_CNT_DOWN_COND_EVT0 (TMR6_HCDOR_HCDO16) +#define TMR6_CNT_DOWN_COND_EVT1 (TMR6_HCDOR_HCDO17) +#define TMR6_CNT_DOWN_COND_ALL (0x00030FFFUL) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Dir_Define TMR6 Base Counter Function Direction Define + * @{ + */ +#define TMR6_CNT_UP (TMR6_GCONR_DIR) +#define TMR6_CNT_DOWN (0x00U) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Mode_Define TMR6 Base Counter Function Mode Define + * @{ + */ +#define TMR6_MD_SAWTOOTH (0x00U) +#define TMR6_MD_TRIANGLE_A (TMR6_GCONR_MODE_2) +#define TMR6_MD_TRIANGLE_B (TMR6_GCONR_MODE_2 | TMR6_GCONR_MODE_0) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Clock_Define TMR6 Base Counter Clock Source Define + * @{ + */ +#define TMR6_CLK_DIV1 (0x00UL) +#define TMR6_CLK_DIV2 (0x01UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV4 (0x02UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV8 (0x03UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV16 (0x04UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV64 (0x05UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV256 (0x06UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV1024 (0x07UL << TMR6_GCONR_CKDIV_POS) +/** + * @} + */ + +/** + * @defgroup TMR6_Zmask_Cycle_Define TMR6 Z Mask Input Function Mask Cycles Number Define + * @{ + */ +#define TMR6_ZMASK_FUNC_INVD (0x00U) +#define TMR6_ZMASK_CYCLE_4 (TMR6_GCONR_ZMSKVAL_0) +#define TMR6_ZMASK_CYCLE_8 (TMR6_GCONR_ZMSKVAL_1) +#define TMR6_ZMASK_CYCLE_16 (TMR6_GCONR_ZMSKVAL) +/** + * @} + */ + +/** + * @defgroup TMR6_Zmask_Pos_Unit_Clear_Func_Define TMR6 Unit As Position Timer, Z Phase Input Mask Function Define For Clear Action + * @{ + */ +#define TMR6_POS_CLR_ZMASK_FUNC_OFF (0x00U) +#define TMR6_POS_CLR_ZMASK_FUNC_ON (TMR6_GCONR_ZMSKPOS) +/** + * @} + */ + +/** + * @defgroup TMR6_Zmask_Revo_Unit_Count_Func_Define TMR6 Unit As Revolution Timer, Z Phase Input Mask Function Define For Count Action + * @{ + */ +#define TMR6_REVO_CNT_ZMASK_FUNC_OFF (0x00U) +#define TMR6_REVO_CNT_ZMASK_FUNC_ON (TMR6_GCONR_ZMSKREV) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR6_Global_Functions + * @{ + */ +/** + * @brief Get Software Sync start status + * @param None + * @retval uint32_t Data indicate the read status. + */ +__STATIC_INLINE uint32_t TMR6_GetSWSyncStartStatus(void) +{ + return READ_REG32(CM_TMR6CR->SSTAR); +} + +/* Base count */ +int32_t TMR6_StructInit(stc_timer6_init_t *pstcTmr6Init); +int32_t TMR6_Init(CM_TMR6_TypeDef *TMR6x, const stc_timer6_init_t *pstcTmr6Init); + +void TMR6_SetCountMode(CM_TMR6_TypeDef *TMR6x, uint32_t u32Mode); +void TMR6_SetCountDir(CM_TMR6_TypeDef *TMR6x, uint32_t u32Dir); +uint32_t TMR6_GetCountDir(CM_TMR6_TypeDef *TMR6x); +void TMR6_SetClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Div); + +/* Hardware count */ +void TMR6_HWCountUpCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWCountDownCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); + +/* PWM output */ +int32_t TMR6_PWM_StructInit(stc_tmr6_pwm_init_t *pstcPwmInit); +int32_t TMR6_PWM_Init(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_pwm_init_t *pstcPwmInit); +void TMR6_PWM_OutputCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_PWM_SetPolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32CountState, uint32_t u32Polarity); +void TMR6_PWM_SetStartStopHold(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32HoldStatus); + +/* Input capture */ +void TMR6_HWCaptureCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState); + +/* Pin config */ +int32_t TMR6_SetFilterClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, uint32_t u32Div); +void TMR6_FilterCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, en_functional_state_t enNewState); +void TMR6_SetFunc(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Func); + +/* Universal */ +void TMR6_IntCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t TMR6_GetStatus(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag); +void TMR6_ClearStatus(CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag); +uint32_t TMR6_GetPeriodNum(const CM_TMR6_TypeDef *TMR6x); +void TMR6_DeInit(CM_TMR6_TypeDef *TMR6x); +void TMR6_Start(CM_TMR6_TypeDef *TMR6x); +void TMR6_Stop(CM_TMR6_TypeDef *TMR6x); + +/* Register write */ +void TMR6_SetCountValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value); +void TMR6_SetPeriodValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); +void TMR6_SetCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); +void TMR6_SetSpecialCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); +void TMR6_SetDeadTimeValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); + +/* Register read */ +uint32_t TMR6_GetCountValue(const CM_TMR6_TypeDef *TMR6x); +uint32_t TMR6_GetPeriodValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); +uint32_t TMR6_GetCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); +uint32_t TMR6_GetSpecialCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); +uint32_t TMR6_GetDeadTimeValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); + +/* Buffer function */ +void TMR6_SetGeneralBufNum(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32BufNum); +void TMR6_SetPeriodBufNum(CM_TMR6_TypeDef *TMR6x, uint32_t u32BufNum); + +int32_t TMR6_SpecialBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig); +void TMR6_GeneralBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_SpecialBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_PeriodBufCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); + +/* Extend function */ +int32_t TMR6_ValidPeriodConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_valid_period_config_t *pstcValidperiodConfig); +void TMR6_ValidPeriodCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_DeadTimeFuncCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +int32_t TMR6_DeadTimeConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_config_t *pstcDeadTimeConfig); +int32_t TMR6_ZMaskConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_config_t *pstcZMaskConfig); +int32_t TMR6_EMBConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_emb_config_t *pstcEmbConfig); +int32_t TMR6_BufFuncStructInit(stc_tmr6_buf_config_t *pstcBufConfig); +int32_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_config_t *pstcValidperiodConfig); +int32_t TMR6_EMBConfigStructInit(stc_tmr6_emb_config_t *pstcEmbConfig); +int32_t TMR6_DeadTimeStructInit(stc_tmr6_deadtime_config_t *pstcDeadTimeConfig); +int32_t TMR6_ZMaskConfigStructInit(stc_tmr6_zmask_config_t *pstcZMaskConfig); + +/* Software synchronous control */ +void TMR6_SWSyncStart(uint32_t u32Unit); +void TMR6_SWSyncStop(uint32_t u32Unit); +void TMR6_SWSyncClear(uint32_t u32Unit); + +/* Hardware control */ +void TMR6_HWStartCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWStartCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +void TMR6_HWStopCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWStopCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +void TMR6_HWClearCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWClearCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +/** + * @} + */ + +#endif /* LL_TMR6_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMR6_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmra.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmra.h new file mode 100644 index 0000000000..8a7328157a --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmra.h @@ -0,0 +1,565 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmra.h + * @brief This file contains all the functions prototypes of the TMRA(TimerA) + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMRA_H__ +#define __HC32_LL_TMRA_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMRA + * @{ + */ + +#if (LL_TMRA_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Types TMRA Global Types + * @{ + */ +/** + * @brief TMRA initialization structure. + */ +typedef struct { + uint8_t u8CountSrc; /*!< Specifies the count source of TMRA. + This parameter can be a value of @ref TMRA_Count_Src */ + union { + struct { + uint16_t u16ClockDiv; /*!< Specifies the divider of software clock source. + This parameter can be a value of @ref TMRA_Clock_Divider */ + uint16_t u16CountMode; /*!< Specifies count mode. + This parameter can be a value of @ref TMRA_Count_Mode */ + uint16_t u16CountDir; /*!< Specifies count direction. + This parameter can be a value of @ref TMRA_Count_Dir */ + } sw_count; + struct { + + uint16_t u16CountUpCond; /*!< Hardware count up condition. + This parameter can be a value of @ref TMRA_Hard_Count_Up_Condition */ + uint16_t u16CountDownCond; /*!< Hardware count down condition. + This parameter can be a value of @ref TMRA_Hard_Count_Down_Condition */ + uint16_t u16Reserved; /*!< Reserved, for future use. */ + } hw_count; + }; + uint32_t u32PeriodValue; /*!< Specifies the period reference value. + This parameter can be a number between 0U and 0xFFFFU, inclusive. */ +} stc_tmra_init_t; + +/** + * @brief TMRA PWM configuration structure. + */ +typedef struct { + uint32_t u32CompareValue; /*!< Specifies compare value of the TMRA channel. + This parameter can be a number between: + 0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472. + 0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. */ + uint16_t u16StartPolarity; /*!< Specifies the polarity when the counter start counting. + This parameter can be a value of @ref TMRA_PWM_Polarity + NOTE: CAN NOT be specified as TMRA_PWM_LOW or TMRA_PWM_HIGH when + sw_count.u16ClockDiv of @ref stc_tmra_init_t is NOT specified + as @ref TMRA_CLK_DIV1 */ + uint16_t u16StopPolarity; /*!< Specifies the polarity when the counter stop counting. + This parameter can be a value of @ref TMRA_PWM_Polarity */ + uint16_t u16CompareMatchPolarity; /*!< Specifies the polarity when the counter matches the compare register. + This parameter can be a value of @ref TMRA_PWM_Polarity */ + uint16_t u16PeriodMatchPolarity; /*!< Specifies the polarity when the counter matches the period register. + This parameter can be a value of @ref TMRA_PWM_Polarity */ +} stc_tmra_pwm_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Macros TMRA Global Macros + * @{ + */ + +/** + * @defgroup TMRA_Count_Src TMRA Count Source + * @{ + */ +#define TMRA_CNT_SRC_SW (0U) +#define TMRA_CNT_SRC_HW (1U) +/** + * @} + */ + +/** + * @defgroup TMRA_Channel TMRA Channel + * @note TMRA_1 and TMRA_2 of HC32M423 contain only one channel TMRA_CH1. + * @{ + */ +#define TMRA_CH1 (0U) /*!< Channel 1 of TMRA. */ +#define TMRA_CH2 (1U) /*!< Channel 2 of TMRA. */ +#define TMRA_CH3 (2U) /*!< Channel 3 of TMRA. */ +#define TMRA_CH4 (3U) /*!< Channel 4 of TMRA. */ +#define TMRA_CH5 (4U) /*!< Channel 5 of TMRA. */ +#define TMRA_CH6 (5U) /*!< Channel 6 of TMRA. */ +#define TMRA_CH7 (6U) /*!< Channel 7 of TMRA. */ +#define TMRA_CH8 (7U) /*!< Channel 8 of TMRA. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Count_Dir TMRA Count Direction + * @{ + */ +#define TMRA_DIR_DOWN (0x0U) /*!< TMRA count down. */ +#define TMRA_DIR_UP (TMRA_BCSTR_DIR) /*!< TMRA count up. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Count_Mode TMRA Count Mode + * @{ + */ +#define TMRA_MD_SAWTOOTH (0x0U) /*!< Count mode is sawtooth wave. */ +#define TMRA_MD_TRIANGLE (TMRA_BCSTR_MODE) /*!< Count mode is triangle wave. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Function_Mode TMRA TMRA Function Mode + * @{ + */ +#define TMRA_FUNC_CMP (0x0U) /*!< Function mode of TMRA channel is ouput compare. */ +#define TMRA_FUNC_CAPT (TMRA_CCONR_CAPMD) /*!< Function mode of TMRA channel is input capture. */ +/** + * @} + */ + +/* Counter reload */ + +/** + * @defgroup TMRA_Clock_Divider TMRA Clock Divider + * @{ + */ +#define TMRA_CLK_DIV1 (0x0U) /*!< The clock source of TMRA is PCLK. */ +#define TMRA_CLK_DIV2 (0x1U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 2. */ +#define TMRA_CLK_DIV4 (0x2U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 4. */ +#define TMRA_CLK_DIV8 (0x3U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 8. */ +#define TMRA_CLK_DIV16 (0x4U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 16. */ +#define TMRA_CLK_DIV32 (0x5U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 32. */ +#define TMRA_CLK_DIV64 (0x6U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 64. */ +#define TMRA_CLK_DIV128 (0x7U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 128. */ +#define TMRA_CLK_DIV256 (0x8U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 256. */ +#define TMRA_CLK_DIV512 (0x9U << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 512. */ +#define TMRA_CLK_DIV1024 (0xAU << TMRA_BCSTR_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 1024. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Filter_Pin TMRA Pin With Filter + * @note TMRA_1 and TMRA_2 of HC32M423 do NOT contain pin TMRA_PIN_PWM2. + * @{ + */ +#define TMRA_PIN_TRIG (0U) /*!< Pin TIMA__TRIG. */ +#define TMRA_PIN_CLKA (1U) /*!< Pin TIMA__CLKA. */ +#define TMRA_PIN_CLKB (2U) /*!< Pin TIMA__CLKB. */ +#define TMRA_PIN_PWM1 (3U) /*!< Pin TIMA__PWM1. */ +#define TMRA_PIN_PWM2 (4U) /*!< Pin TIMA__PWM2. */ +#define TMRA_PIN_PWM3 (5U) /*!< Pin TIMA__PWM3. */ +#define TMRA_PIN_PWM4 (6U) /*!< Pin TIMA__PWM4. */ +#define TMRA_PIN_PWM5 (7U) /*!< Pin TIMA__PWM5. */ +#define TMRA_PIN_PWM6 (8U) /*!< Pin TIMA__PWM6. */ +#define TMRA_PIN_PWM7 (9U) /*!< Pin TIMA__PWM7. */ +#define TMRA_PIN_PWM8 (10U) /*!< Pin TIMA__PWM8. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Hard_Count_Up_Condition TMRA Hardware Count Up Condition + * @note Symmetric units: unit 1 and 2; unit 3 and 4; ...; unit 11 and 12. + * @{ + */ +#define TMRA_CNT_UP_COND_INVD (0U) /*!< TMRA hardware count up condition is INVALID. */ +#define TMRA_CNT_UP_COND_CLKA_LOW_CLKB_RISING (TMRA_HCUPR_HCUP0) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKA_LOW_CLKB_FALLING (TMRA_HCUPR_HCUP1) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING (TMRA_HCUPR_HCUP2) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_FALLING (TMRA_HCUPR_HCUP3) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_LOW_CLKA_RISING (TMRA_HCUPR_HCUP4) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_LOW_CLKA_FALLING (TMRA_HCUPR_HCUP5) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_RISING (TMRA_HCUPR_HCUP6) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_FALLING (TMRA_HCUPR_HCUP7) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_TRIG_RISING (TMRA_HCUPR_HCUP8) /*!< When a rising edge occurred on TRIG, the counter register counts up. */ +#define TMRA_CNT_UP_COND_TRIG_FALLING (TMRA_HCUPR_HCUP9) /*!< When a falling edge occurred on TRIG, the counter register counts up. */ +#define TMRA_CNT_UP_COND_EVT (TMRA_HCUPR_HCUP10) /*!< When the event specified by TMRA_HTSSR occurred, the counter register counts up. */ +/* More conditions for HC32F460, HC32F4A0, HC32M423, HC32F451, HC32F452 */ +#define TMRA_CNT_UP_COND_SYM_OVF (TMRA_HCUPR_HCUP11) /*!< When the symmetric unit overflow, the counter register counts up. */ +#define TMRA_CNT_UP_COND_SYM_UDF (TMRA_HCUPR_HCUP12) /*!< When the symmetric unit underflow, the counter register counts up. */ +#define TMRA_CNT_UP_COND_ALL (0x1FFFU) +/** + * @} + */ + +/** + * @defgroup TMRA_Hard_Count_Down_Condition TMRA Hardware Count Down Condition + * @note Symmetric units: unit 1 and 2; unit 3 and 4; ...; unit 11 and 12. + * @{ + */ +#define TMRA_CNT_DOWN_COND_INVD (0U) /*!< TMRA hardware count down condition is INVALID. */ +#define TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_RISING (TMRA_HCDOR_HCDO0) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_FALLING (TMRA_HCDOR_HCDO1) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_RISING (TMRA_HCDOR_HCDO2) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_FALLING (TMRA_HCDOR_HCDO3) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_RISING (TMRA_HCDOR_HCDO4) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_FALLING (TMRA_HCDOR_HCDO5) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING (TMRA_HCDOR_HCDO6) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_FALLING (TMRA_HCDOR_HCDO7) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_TRIG_RISING (TMRA_HCDOR_HCDO8) /*!< When a rising edge occurred on TRIG, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_TRIG_FALLING (TMRA_HCDOR_HCDO9) /*!< When a falling edge occurred on TRIG, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_EVT (TMRA_HCDOR_HCDO10) /*!< When the event specified by TMRA_HTSSR occurred, the counter register counts down. */ +/* More conditions for HC32F460, HC32F4A0, HC32M423, HC32F451, HC32F452 */ +#define TMRA_CNT_DOWN_COND_SYM_OVF (TMRA_HCDOR_HCDO11) /*!< When the symmetric unit overflow, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_SYM_UDF (TMRA_HCDOR_HCDO12) /*!< When the symmetric unit underflow, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_ALL (0x1FFFU) +/** + * @} + */ + +/** + * @defgroup TMRA_Interrupt_Type TMRA Interrupt Type + * @note TMRA_1 and TMRA_2 of HC32M423 do NOT contain interrupt TMRA_INT_CMP_CH2. + * @{ + */ +#define TMRA_INT_OVF (1UL << 12U) /*!< The interrupt of counting overflow. */ +#define TMRA_INT_UDF (1UL << 13U) /*!< The interrupt of counting underflow. */ +#define TMRA_INT_CMP_CH1 (1UL << 16U) /*!< The interrupt of compare-match of channel 1. */ +#define TMRA_INT_CMP_CH2 (1UL << 17U) /*!< The interrupt of compare-match of channel 2. */ +#define TMRA_INT_CMP_CH3 (1UL << 18U) /*!< The interrupt of compare-match of channel 3. */ +#define TMRA_INT_CMP_CH4 (1UL << 19U) /*!< The interrupt of compare-match of channel 4. */ +#define TMRA_INT_CMP_CH5 (1UL << 20U) /*!< The interrupt of compare-match of channel 5. */ +#define TMRA_INT_CMP_CH6 (1UL << 21U) /*!< The interrupt of compare-match of channel 6. */ +#define TMRA_INT_CMP_CH7 (1UL << 22U) /*!< The interrupt of compare-match of channel 7. */ +#define TMRA_INT_CMP_CH8 (1UL << 23U) /*!< The interrupt of compare-match of channel 8. */ +#define TMRA_INT_ALL (0xFF3000UL) +/** + * @} + */ + +/** + * @defgroup TMRA_Event_Type TMRA Event Type + * @note TMRA_1 and TMRA_2 of HC32M423 do NOT contain event TMRA_EVT_CMP_CH2. + * @{ + */ +#define TMRA_EVT_CMP_CH1 (TMRA_ECONR_ETEN1) /*!< The event of compare-match of channel 1. */ +#define TMRA_EVT_CMP_CH2 (TMRA_ECONR_ETEN2) /*!< The event of compare-match of channel 2. */ +#define TMRA_EVT_CMP_CH3 (TMRA_ECONR_ETEN3) /*!< The event of compare-match of channel 3. */ +#define TMRA_EVT_CMP_CH4 (TMRA_ECONR_ETEN4) /*!< The event of compare-match of channel 4. */ +#define TMRA_EVT_CMP_CH5 (TMRA_ECONR_ETEN5) /*!< The event of compare-match of channel 5. */ +#define TMRA_EVT_CMP_CH6 (TMRA_ECONR_ETEN6) /*!< The event of compare-match of channel 6. */ +#define TMRA_EVT_CMP_CH7 (TMRA_ECONR_ETEN7) /*!< The event of compare-match of channel 7. */ +#define TMRA_EVT_CMP_CH8 (TMRA_ECONR_ETEN8) /*!< The event of compare-match of channel 8. */ +#define TMRA_EVT_ALL (TMRA_EVT_CMP_CH1 | TMRA_EVT_CMP_CH2 | TMRA_EVT_CMP_CH3 | \ + TMRA_EVT_CMP_CH4 | TMRA_EVT_CMP_CH5 | TMRA_EVT_CMP_CH6 | \ + TMRA_EVT_CMP_CH7 | TMRA_EVT_CMP_CH8) +/** + * @} + */ + +/** + * @defgroup TMRA_Status_Flag TMRA Status Flag + * @note TMRA_1 and TMRA_2 of HC32M423 do NOT contain flag TMRA_FLAG_CMP_CH2. + * @{ + */ +#define TMRA_FLAG_OVF (1UL << 14U) /*!< The flag of counting overflow. */ +#define TMRA_FLAG_UDF (1UL << 15U) /*!< The flag of counting underflow. */ +#define TMRA_FLAG_CMP_CH1 (1UL << 16U) /*!< The flag of compare-match of channel 1. */ +#define TMRA_FLAG_CMP_CH2 (1UL << 17U) /*!< The flag of compare-match of channel 2. */ +#define TMRA_FLAG_CMP_CH3 (1UL << 18U) /*!< The flag of compare-match of channel 3. */ +#define TMRA_FLAG_CMP_CH4 (1UL << 19U) /*!< The flag of compare-match of channel 4. */ +#define TMRA_FLAG_CMP_CH5 (1UL << 20U) /*!< The flag of compare-match of channel 5. */ +#define TMRA_FLAG_CMP_CH6 (1UL << 21U) /*!< The flag of compare-match of channel 6. */ +#define TMRA_FLAG_CMP_CH7 (1UL << 22U) /*!< The flag of compare-match of channel 7. */ +#define TMRA_FLAG_CMP_CH8 (1UL << 23U) /*!< The flag of compare-match of channel 8. */ +#define TMRA_FLAG_ALL (0xFFC000UL) + +/** + * @} + */ + +/** + * @defgroup TMRA_Capture_Cond TMRA Capture Condition + * @note 'TMRA_CAPT_COND_TRIG_RISING' and 'TMRA_CAPT_COND_TRIG_FALLING' are only valid for channel 4. + * @{ + */ +#define TMRA_CAPT_COND_INVD (0x0U) /*!< The condition of capture is INVALID. */ +#define TMRA_CAPT_COND_PWM_RISING (TMRA_CCONR_HICP0) /*!< The condition of capture is a rising edge is sampled on pin TIMA__PWMn. */ +#define TMRA_CAPT_COND_PWM_FALLING (TMRA_CCONR_HICP1) /*!< The condition of capture is a falling edge is sampled on pin TIMA__PWMn. */ +#define TMRA_CAPT_COND_EVT (TMRA_CCONR_HICP2) /*!< The condition of capture is the specified event occurred. */ +#define TMRA_CAPT_COND_TRIG_RISING (TMRA_CCONR_HICP3) /*!< The condition of capture is a rising edge is sampled on pin TIMA__TRIG. + This condition is only valid for channel 4. */ +#define TMRA_CAPT_COND_TRIG_FALLING (TMRA_CCONR_HICP4) /*!< The condition of capture is a falling edge is sampled on pin TIMA__TRIG. + This condition is only valid for channel 4. */ +#define TMRA_CAPT_COND_ALL (TMRA_CAPT_COND_PWM_RISING | TMRA_CAPT_COND_PWM_FALLING | \ + TMRA_CAPT_COND_EVT | TMRA_CAPT_COND_TRIG_RISING | \ + TMRA_CAPT_COND_TRIG_FALLING) + +/** + * @} + */ + +/** + * @defgroup TMRA_Cmp_Value_Buf_Trans_Cond TMRA Compare Value Buffer Transmission Condition + * @{ + */ +#define TMRA_BUF_TRANS_COND_OVF_UDF_CLR (0x0U) /*!< This configuration value applies to non-triangular wave counting mode. + When counting overflow or underflow or counting register was cleared, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */ +#define TMRA_BUF_TRANS_COND_PEAK (TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */ +#define TMRA_BUF_TRANS_COND_VALLEY (TMRA_BCONR_BSE1) /*!< In triangle wave count mode, when count reached valley, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,.... */ +#define TMRA_BUF_TRANS_COND_PEAK_VALLEY (TMRA_BCONR_BSE1 | \ + TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak or valley, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */ +/** + * @} + */ + +/** + * @defgroup TMRA_Filter_Clock_Divider TMRA Filter Clock Divider + * @{ + */ +#define TMRA_FILTER_CLK_DIV1 (0x0U) /*!< The filter clock is the clock of timerA / 1 */ +#define TMRA_FILTER_CLK_DIV4 (0x1U) /*!< The filter clock is the clock of timerA / 4 */ +#define TMRA_FILTER_CLK_DIV16 (0x2U) /*!< The filter clock is the clock of timerA / 16 */ +#define TMRA_FILTER_CLK_DIV64 (0x3U) /*!< The filter clock is the clock of timerA / 64 */ +/** + * @} + */ + +/** + * @defgroup TMRA_Counter_State TMRA Counter State + * @{ + */ +#define TMRA_CNT_STAT_START (0U) /*!< Counter start counting. */ +#define TMRA_CNT_STAT_STOP (1U) /*!< Counter stop counting. */ +#define TMRA_CNT_STAT_MATCH_CMP (2U) /*!< Counter value matchs the compare value. */ +#define TMRA_CNT_STAT_MATCH_PERIOD (3U) /*!< Counter value matchs the period value. */ +/** + * @} + */ + +/** + * @defgroup TMRA_PWM_Polarity TMRA PWM Polarity + * @{ + */ +#define TMRA_PWM_LOW (0x0U) /*!< PWM output low. */ +#define TMRA_PWM_HIGH (0x1U) /*!< PWM output high. */ +#define TMRA_PWM_HOLD (0x2U) /*!< PWM output holds the current polarity. */ +#define TMRA_PWM_INVT (0x3U) /*!< PWM output reverses the current polarity. */ +/** + * @} + */ + +/** + * @defgroup TMRA_PWM_Force_Polarity TMRA PWM Force Polarity + * @{ + */ +#define TMRA_PWM_FORCE_INVD (0x0U) /*!< Force polarity is invalid. */ +#define TMRA_PWM_FORCE_LOW (TMRA_PCONR_FORC_1) /*!< Force the PWM output low at the beginning of the next cycle. + The beginning of the next cycle: overflow position or underflow position + of sawtooth wave; valley position of triangle wave. */ +#define TMRA_PWM_FORCE_HIGH (TMRA_PCONR_FORC) /*!< Force the PWM output high at the beginning of the next cycle. + The beginning of the next cycle: overflow position or underflow position + of sawtooth wave; valley position of triangle wave. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Start_Condition TMRA Hardware Start Condition + * @{ + */ +#define TMRA_START_COND_INVD (0x0U) /*!< The condition of start is INVALID. */ +#define TMRA_START_COND_TRIG_RISING (TMRA_HCONR_HSTA0) /*!< 1. Sync start is invalid: The condition is that a rising edge is sampled on TRIG of the current TMRA unit. + 2. Sync start is valid: The condition is that a rising edge is sampled on TRIG of the symmetric TMRA unit. */ +#define TMRA_START_COND_TRIG_FALLING (TMRA_HCONR_HSTA1) /*!< 1. Sync start is invalid: The condition is that a falling edge is sampled on TRIG of the current TMRA unit. + 2. Sync start is valid: The condition is that a falling edge is sampled on TRIG of the symmetric TMRA unit. */ +#define TMRA_START_COND_EVT (TMRA_HCONR_HSTA2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */ +#define TMRA_START_COND_ALL (TMRA_START_COND_TRIG_RISING | TMRA_START_COND_TRIG_FALLING | \ + TMRA_START_COND_EVT) +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Stop_Condition TMRA Hardware Stop Condition + * @{ + */ +#define TMRA_STOP_COND_INVD (0x0U) /*!< The condition of stop is INVALID. */ +#define TMRA_STOP_COND_TRIG_RISING (TMRA_HCONR_HSTP0) /*!< The condition is that a rising edge is sampled on pin TRIG of the current TMRA unit. */ +#define TMRA_STOP_COND_TRIG_FALLING (TMRA_HCONR_HSTP1) /*!< The condition is that a falling edge is sampled on pin TRIG of the current TMRA unit. */ +#define TMRA_STOP_COND_EVT (TMRA_HCONR_HSTP2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */ +#define TMRA_STOP_COND_ALL (TMRA_STOP_COND_TRIG_RISING | TMRA_STOP_COND_TRIG_FALLING | \ + TMRA_STOP_COND_EVT) +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Clear_Condition TMRA Hardware Clear Condition + * @note Symmetric units: unit 1 and 2; unit 3 and 4; ... ; unit 11 and 12. + * @{ + */ +#define TMRA_CLR_COND_INVD (0x0U) /*!< The condition of clear is INVALID. */ +#define TMRA_CLR_COND_TRIG_RISING (TMRA_HCONR_HCLE0) /*!< The condition is that a rising edge is sampled on TRIG of the current TMRA unit. */ +#define TMRA_CLR_COND_TRIG_FALLING (TMRA_HCONR_HCLE1) /*!< The condition is that a falling edge is sampled on TRIG of the current TMRA unit. */ +#define TMRA_CLR_COND_EVT (TMRA_HCONR_HCLE2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */ +#define TMRA_CLR_COND_SYM_TRIG_RISING (TMRA_HCONR_HCLE3) /*!< The condition is that a rising edge is sampled on TRIG of the symmetric unit. */ +#define TMRA_CLR_COND_SYM_TRIG_FALLING (TMRA_HCONR_HCLE4) /*!< The condition is that a falling edge is sampled on TRIG of the symmetric unit. */ +#define TMRA_CLR_COND_PWM3_RISING (TMRA_HCONR_HCLE5) /*!< The condition is that a rising edge is sampled on PWM3 of the current TMRA unit. */ +#define TMRA_CLR_COND_PWM3_FALLING (TMRA_HCONR_HCLE6) /*!< The condition is that a falling edge is sampled on PWM3 of the current TMRA unit. */ +#define TMRA_CLR_COND_ALL (TMRA_CLR_COND_TRIG_RISING | TMRA_CLR_COND_TRIG_FALLING | \ + TMRA_CLR_COND_EVT| TMRA_CLR_COND_SYM_TRIG_RISING | \ + TMRA_CLR_COND_SYM_TRIG_FALLING | TMRA_CLR_COND_PWM3_RISING| \ + TMRA_CLR_COND_PWM3_FALLING) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMRA_Global_Functions + * @{ + */ +/* Base count(use software clock PCLK/HCLK) */ +int32_t TMRA_Init(CM_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcTmraInit); +int32_t TMRA_StructInit(stc_tmra_init_t *pstcTmraInit); +void TMRA_SetCountMode(CM_TMRA_TypeDef *TMRAx, uint16_t u16Mode); +void TMRA_SetCountDir(CM_TMRA_TypeDef *TMRAx, uint16_t u16Dir); +void TMRA_SetClockDiv(CM_TMRA_TypeDef *TMRAx, uint16_t u16Div); + +/* Hardware count */ +void TMRA_HWCountUpCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +void TMRA_HWCountDownCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +/* Set function mode */ +void TMRA_SetFunc(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Func); + +/* Ouput compare */ +int32_t TMRA_PWM_Init(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, const stc_tmra_pwm_init_t *pstcPwmInit); +int32_t TMRA_PWM_StructInit(stc_tmra_pwm_init_t *pstcPwmInit); +void TMRA_PWM_OutputCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState); +void TMRA_PWM_SetPolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint8_t u8CountState, uint16_t u16Polarity); +void TMRA_PWM_SetForcePolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Polarity); + +/* Input capture */ +void TMRA_HWCaptureCondCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState); + +/* Trigger: hardware trigger to start/stop/clear the counter */ +void TMRA_HWStartCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +void TMRA_HWStopCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +void TMRA_HWClearCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); + +/* Filter */ +void TMRA_SetFilterClockDiv(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, uint16_t u16Div); +void TMRA_FilterCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, en_functional_state_t enNewState); + +/* Global */ +void TMRA_DeInit(CM_TMRA_TypeDef *TMRAx); +/* Counting direction, period value, counter value, compare value */ +uint16_t TMRA_GetCountDir(const CM_TMRA_TypeDef *TMRAx); + +void TMRA_SetPeriodValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value); +uint32_t TMRA_GetPeriodValue(const CM_TMRA_TypeDef *TMRAx); +void TMRA_SetCountValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value); +uint32_t TMRA_GetCountValue(const CM_TMRA_TypeDef *TMRAx); +void TMRA_SetCompareValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint32_t u32Value); +uint32_t TMRA_GetCompareValue(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch); + +/* Sync start. */ +void TMRA_SyncStartCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState); + +/* Reload and continue counting when overflow/underflow? */ + +void TMRA_SetCompareBufCond(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond); +void TMRA_CompareBufCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState); + +en_flag_status_t TMRA_GetStatus(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag); +void TMRA_ClearStatus(CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag); + +void TMRA_IntCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState); +void TMRA_EventCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32EventType, en_functional_state_t enNewState); + +void TMRA_Start(CM_TMRA_TypeDef *TMRAx); +void TMRA_Stop(CM_TMRA_TypeDef *TMRAx); + +/** + * @} + */ + +#endif /* LL_TMRA_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMRA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_trng.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_trng.h new file mode 100644 index 0000000000..9bff88f20e --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_trng.h @@ -0,0 +1,130 @@ +/** + ******************************************************************************* + * @file hc32_ll_trng.h + * @brief This file contains all the functions prototypes of the TRNG driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TRNG_H__ +#define __HC32_LL_TRNG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TRNG + * @{ + */ + +#if (LL_TRNG_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup TRNG_Global_Macros TRNG Global Macros + * @{ + */ + +/** + * @defgroup TRNG_Reload_Init_Value TRNG Reload Initial Value + * @{ + */ +#define TRNG_RELOAD_INIT_VAL_ENABLE (TRNG_MR_LOAD) /* Enable reload new initial value. */ +#define TRNG_RELOAD_INIT_VAL_DISABLE (0x0U) /* Disable reload new initial value. */ +/** + * @} + */ + +/** + * @defgroup TRNG_Shift_Ctrl TRNG Shift Control + * @{ + */ +#define TRNG_SHIFT_CNT32 (0x3UL << TRNG_MR_CNT_POS) /* Shift 32 times when capturing random noise. */ +#define TRNG_SHIFT_CNT64 (0x4UL << TRNG_MR_CNT_POS) /* Shift 64 times when capturing random noise. */ +#define TRNG_SHIFT_CNT128 (0x5UL << TRNG_MR_CNT_POS) /* Shift 128 times when capturing random noise. */ +#define TRNG_SHIFT_CNT256 (0x6UL << TRNG_MR_CNT_POS) /* Shift 256 times when capturing random noise. */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TRNG_Global_Functions + * @{ + */ +void TRNG_Init(uint32_t u32ShiftCount, uint32_t u32ReloadInitValueEn); + +/* For polling mode. */ +int32_t TRNG_GenerateRandom(uint32_t *pu32Random, uint8_t u8RandomLen); + +/* For interrupt mode. */ +void TRNG_Start(void); +int32_t TRNG_GetRandom(uint32_t *pu32Random, uint8_t u8RandomLen); + +/** + * @} + */ + +#endif /* LL_TRNG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TRNG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usart.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usart.h new file mode 100644 index 0000000000..4ea3b5ed33 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usart.h @@ -0,0 +1,425 @@ +/** + ******************************************************************************* + * @file hc32_ll_usart.h + * @brief This file contains all the functions prototypes of the USART(Universal + * Synchronous/Asynchronous Receiver Transmitter) driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_USART_H__ +#define __HC32_LL_USART_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_USART + * @{ + */ + +#if (LL_USART_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup USART_Global_Types USART Global Types + * @{ + */ + +/** + * @brief clock synchronization mode initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Clock Source. + This parameter can be a value of @ref USART_Clock_Source */ + uint32_t u32ClockDiv; /*!< Clock division. + This parameter can be a value of @ref USART_Clock_Division. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is valid when clock source is the internal clock. */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ + uint32_t u32HWFlowControl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_clocksync_init_t; + +/** + * @brief UART multiple-processor initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Clock Source. + This parameter can be a value of @ref USART_Clock_Source */ + uint32_t u32ClockDiv; /*!< Clock division. + This parameter can be a value of @ref USART_Clock_Division. */ + uint32_t u32CKOutput; /*!< USART_CK output selection. + This parameter can be a value of @ref USART_CK_Output_Selection. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is valid when clock source is the internal clock. */ + uint32_t u32DataWidth; /*!< Data width. + This parameter can be a value of @ref USART_Data_Width_Bit */ + uint32_t u32StopBit; /*!< Stop Bits. + This parameter can be a value of @ref USART_Stop_Bit */ + uint32_t u32OverSampleBit; /*!< Oversampling Bits. + This parameter can be a value of @ref USART_Over_Sample_Bit */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ + uint32_t u32StartBitPolarity; /*!< Start Bit Detect Polarity. + This parameter can be a value of @ref USART_Start_Bit_Polarity */ + uint32_t u32HWFlowControl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_multiprocessor_init_t; + +/** + * @brief UART mode initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Clock Source. + This parameter can be a value of @ref USART_Clock_Source */ + uint32_t u32ClockDiv; /*!< Clock division. + This parameter can be a value of @ref USART_Clock_Division. */ + uint32_t u32CKOutput; /*!< USART_CK output selection. + This parameter can be a value of @ref USART_CK_Output_Selection. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is valid when clock source is the internal clock. */ + uint32_t u32DataWidth; /*!< Data width. + This parameter can be a value of @ref USART_Data_Width_Bit */ + uint32_t u32StopBit; /*!< Stop Bits. + This parameter can be a value of @ref USART_Stop_Bit */ + uint32_t u32Parity; /*!< Parity format. + This parameter can be a value of @ref USART_Parity_Control */ + uint32_t u32OverSampleBit; /*!< Oversampling Bits. + This parameter can be a value of @ref USART_Over_Sample_Bit */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ + uint32_t u32StartBitPolarity; /*!< Start Bit Detect Polarity. + This parameter can be a value of @ref USART_Start_Bit_Polarity */ + uint32_t u32HWFlowControl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_uart_init_t; + +/** + * @brief LIN mode initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ + +/** + * @brief Smartcard mode initialization structure definition + */ +typedef struct { + uint32_t u32ClockDiv; /*!< Clock division. This parameter can be a value of @ref USART_Clock_Division. + @note This parameter is valid when clock source is the internal clock. */ + uint32_t u32CKOutput; /*!< USART_CK output selection. This parameter can be a value of @ref USART_CK_Output_Selection. + @note This parameter is valid when clock source is the internal clock. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is calculated according with smartcard default ETU and clock. */ + uint32_t u32StopBit; /*!< Stop Bits. + This parameter can be a value of @ref USART_Stop_Bit */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ +} stc_usart_smartcard_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup USART_Global_Macros USART Global Macros + * @{ + */ + +/** + * @defgroup USART_Flag USART Flag + * @{ + */ +#define USART_FLAG_RX_FULL (USART_SR_RXNE) /*!< Receive data register not empty flag */ +#define USART_FLAG_OVERRUN (USART_SR_ORE) /*!< Overrun error flag */ +#define USART_FLAG_TX_CPLT (USART_SR_TC) /*!< Transmission complete flag */ +#define USART_FLAG_TX_EMPTY (USART_SR_TXE) /*!< Transmit data register empty flag */ +#define USART_FLAG_FRAME_ERR (USART_SR_FE) /*!< Framing error flag */ +#define USART_FLAG_PARITY_ERR (USART_SR_PE) /*!< Parity error flag */ +#define USART_FLAG_MX_PROCESSOR (USART_SR_MPB) /*!< Receive processor ID flag */ +#define USART_FLAG_RX_TIMEOUT (USART_SR_RTOF) /*!< Receive timeout flag */ + +#define USART_FLAG_ALL (USART_FLAG_RX_FULL | USART_FLAG_FRAME_ERR | USART_FLAG_TX_EMPTY | \ + USART_FLAG_OVERRUN | USART_FLAG_PARITY_ERR | USART_FLAG_RX_TIMEOUT | \ + USART_FLAG_TX_CPLT | USART_FLAG_MX_PROCESSOR ) + +/** + * @} + */ + +/** + * @defgroup USART_Transmission_Type USART Transmission Type + * @{ + */ +#define USART_TRANS_DATA (0UL) +#define USART_TRANS_ID (USART_DR_MPID) +/** + * @} + */ + +/** + * @defgroup USART_Function USART Function + * @{ + */ +#define USART_TX (USART_CR1_TE) /*!< USART TX function */ +#define USART_RX (USART_CR1_RE) /*!< USART RX function */ +#define USART_INT_RX (USART_CR1_RIE) /*!< USART receive data register not empty && receive error interrupt */ +#define USART_INT_TX_CPLT (USART_CR1_TCIE) /*!< USART transmission complete interrupt */ +#define USART_INT_TX_EMPTY (USART_CR1_TXEIE) /*!< USART transmit data register empty interrupt */ + +#define USART_RX_TIMEOUT (USART_CR1_RTOE) /*!< USART RX timerout function */ +#define USART_INT_RX_TIMEOUT (USART_CR1_RTOIE) /*!< USART RX timerout interrupt */ + +#define USART_FUNC_ALL (USART_TX | USART_RX | USART_INT_RX | USART_INT_TX_CPLT | USART_RX_TIMEOUT | \ + USART_INT_RX_TIMEOUT | USART_INT_TX_EMPTY) + +/** + * @} + */ + +/** + * @defgroup USART_Parity_Control USART Parity Control + * @{ + */ +#define USART_PARITY_NONE (0UL) /*!< Parity control disabled */ +#define USART_PARITY_EVEN (USART_CR1_PCE) /*!< Parity control enabled and Even Parity is selected */ +#define USART_PARITY_ODD (USART_CR1_PCE | \ + USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** + * @defgroup USART_Data_Width_Bit USART Data Width Bit + * @{ + */ +#define USART_DATA_WIDTH_8BIT (0UL) /*!< 8 bits */ +#define USART_DATA_WIDTH_9BIT (USART_CR1_M) /*!< 9 bits */ +/** + * @} + */ + +/** + * @defgroup USART_Over_Sample_Bit USART Over Sample Bit + * @{ + */ +#define USART_OVER_SAMPLE_16BIT (0UL) /*!< Oversampling by 16 bits */ +#define USART_OVER_SAMPLE_8BIT (USART_CR1_OVER8) /*!< Oversampling by 8 bits */ +/** + * @} + */ + +/** + * @defgroup USART_First_Bit USART First Bit + * @{ + */ +#define USART_FIRST_BIT_LSB (0UL) /*!< LSB(Least Significant Bit) */ +#define USART_FIRST_BIT_MSB (USART_CR1_ML) /*!< MSB(Most Significant Bit) */ +/** + * @} + */ + +/** + * @defgroup USART_Start_Bit_Polarity USART Start Bit Polarity + * @{ + */ +#define USART_START_BIT_LOW (0UL) /*!< Detect RX pin low level */ +#define USART_START_BIT_FALLING (USART_CR1_SBS) /*!< Detect RX pin falling edge */ +/** + * @} + */ + +/** + * @defgroup USART_Clock_Source USART Clock Source + * @{ + */ +#define USART_CLK_SRC_INTERNCLK (0UL) /*!< Select internal clock source and don't output clock */ +#define USART_CLK_SRC_EXTCLK (USART_CR2_CLKC_1) /*!< Select external clock source. */ +/** + * @} + */ + +/** + * @defgroup USART_CK_Output_Selection USART_CK Output Selection + * @{ + */ +#define USART_CK_OUTPUT_DISABLE (0UL) /*!< Disable USART_CK output */ +#define USART_CK_OUTPUT_ENABLE (USART_CR2_CLKC_0) /*!< Enable USART_CK output. */ +/** + * @} + */ + +/** + * @defgroup USART_Stop_Bit USART Stop Bit + * @{ + */ +#define USART_STOPBIT_1BIT (0UL) /*!< 1 stop bit */ +#define USART_STOPBIT_2BIT (USART_CR2_STOP) /*!< 2 stop bit */ +/** + * @} + */ + +/** + * @defgroup USART_Hardware_Flow_Control USART Hardware Flow Control + * @{ + */ +#define USART_HW_FLOWCTRL_CTS (USART_CR3_CTSE) /*!< USART hardware flow control CTS mode */ +#define USART_HW_FLOWCTRL_RTS (USART_CR3_CTSE >> 1U) /*!< USART hardware flow control RTS mode */ +/** + * @} + */ + +/** + * @defgroup USART_Clock_Division USART Clock Division + * @{ + */ +#define USART_CLK_DIV1 (0UL) /*!< CLK */ +#define USART_CLK_DIV4 (1UL) /*!< CLK/4 */ +#define USART_CLK_DIV16 (2UL) /*!< CLK/16 */ +#define USART_CLK_DIV64 (3UL) /*!< CLK/64 */ +/** + * @} + */ + +/** + * @defgroup USART_Max_Timeout USART Max Timeout + * @{ + */ +#define USART_MAX_TIMEOUT (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup USART_Smartcard_ETU_Clock USART Smartcard ETU Clock + * @{ + */ +#define USART_SC_ETU_CLK32 (0UL << USART_CR3_BCN_POS) /*!< 1 etu = 32/f */ +#define USART_SC_ETU_CLK64 (1UL << USART_CR3_BCN_POS) /*!< 1 etu = 64/f */ +#define USART_SC_ETU_CLK128 (2UL << USART_CR3_BCN_POS) /*!< 1 etu = 128/f */ +#define USART_SC_ETU_CLK256 (3UL << USART_CR3_BCN_POS) /*!< 1 etu = 256/f */ +#define USART_SC_ETU_CLK372 (6UL << USART_CR3_BCN_POS) /*!< 1 etu = 372/f */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup USART_Global_Functions + * @{ + */ +int32_t USART_ClockSync_StructInit(stc_usart_clocksync_init_t *pstcClockSyncInit); +int32_t USART_ClockSync_Init(CM_USART_TypeDef *USARTx, + const stc_usart_clocksync_init_t *pstcClockSyncInit, float32_t *pf32Error); +int32_t USART_MultiProcessor_StructInit(stc_usart_multiprocessor_init_t *pstcMultiProcessorInit); +int32_t USART_MultiProcessor_Init(CM_USART_TypeDef *USARTx, + const stc_usart_multiprocessor_init_t *pstcMultiProcessorInit, float32_t *pf32Error); +int32_t USART_UART_StructInit(stc_usart_uart_init_t *pstcUartInit); +int32_t USART_UART_Init(CM_USART_TypeDef *USARTx, const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error); + +int32_t USART_SmartCard_StructInit(stc_usart_smartcard_init_t *pstcSmartCardInit); +int32_t USART_SmartCard_Init(CM_USART_TypeDef *USARTx, + const stc_usart_smartcard_init_t *pstcSmartCardInit, float32_t *pf32Error); + +void USART_DeInit(CM_USART_TypeDef *USARTx); +void USART_FuncCmd(CM_USART_TypeDef *USARTx, uint32_t u32Func, en_functional_state_t enNewState); +en_flag_status_t USART_GetStatus(const CM_USART_TypeDef *USARTx, uint32_t u32Flag); +void USART_ClearStatus(CM_USART_TypeDef *USARTx, uint32_t u32Flag); +void USART_SetParity(CM_USART_TypeDef *USARTx, uint32_t u32Parity); +void USART_SetFirstBit(CM_USART_TypeDef *USARTx, uint32_t u32FirstBit); +void USART_SetStopBit(CM_USART_TypeDef *USARTx, uint32_t u32StopBit); +void USART_SetDataWidth(CM_USART_TypeDef *USARTx, uint32_t u32DataWidth); +void USART_SetOverSampleBit(CM_USART_TypeDef *USARTx, uint32_t u32OverSampleBit); +void USART_SetStartBitPolarity(CM_USART_TypeDef *USARTx, uint32_t u32Polarity); +void USART_SetTransType(CM_USART_TypeDef *USARTx, uint32_t u32Type); +void USART_SetClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv); +uint32_t USART_GetClockDiv(const CM_USART_TypeDef *USARTx); +void USART_SetClockSrc(CM_USART_TypeDef *USARTx, uint32_t u32ClockSrc); +uint32_t USART_GetClockSrc(const CM_USART_TypeDef *USARTx); +void USART_FilterCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState); +void USART_SilenceCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState); +void USART_SetHWFlowControl(CM_USART_TypeDef *USARTx, uint32_t u32HWFlowControl); +uint16_t USART_ReadData(const CM_USART_TypeDef *USARTx); +void USART_WriteData(CM_USART_TypeDef *USARTx, uint16_t u16Data); +void USART_WriteID(CM_USART_TypeDef *USARTx, uint16_t u16ID); + +int32_t USART_SetBaudrate(CM_USART_TypeDef *USARTx, uint32_t u32Baudrate, float32_t *pf32Error); + +/* Smartcard function */ +void USART_SmartCard_SetEtuClock(CM_USART_TypeDef *USARTx, uint32_t u32EtuClock); + +int32_t USART_UART_Trans(CM_USART_TypeDef *USARTx, const void *pvBuf, uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_UART_Receive(const CM_USART_TypeDef *USARTx, void *pvBuf, uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_ClockSync_Trans(CM_USART_TypeDef *USARTx, const uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_ClockSync_Receive(CM_USART_TypeDef *USARTx, uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_ClockSync_TransReceive(CM_USART_TypeDef *USARTx, const uint8_t au8TxBuf[], uint8_t au8RxBuf[], + uint32_t u32Len, uint32_t u32Timeout); + +/** + * @} + */ + +#endif /* LL_USART_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_USART_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usb.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usb.h new file mode 100644 index 0000000000..4e878d8af2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usb.h @@ -0,0 +1,671 @@ +/** + ******************************************************************************* + * @file hc32_ll_usb.h + * @brief A detailed description is available at hardware registers + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_USB_H__ +#define __HC32_LL_USB_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +#include "usb_app_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_USB + * @{ + */ + +#if (LL_USB_ENABLE == DDL_ON) + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_MAX_TX_FIFOS (12U) +#define USB_MAX_CH_NUM (USB_MAX_TX_FIFOS) +#define USB_MAX_EP_NUM (6U) + +#define USB_MAX_EP0_SIZE (64U) +/* working mode of the USB core */ +#define DEVICE_MODE (0U) +#define HOST_MODE (1U) + +/* Macro definations for device mode*/ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << USBFS_DSTS_ENUMSPD_POS) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << USBFS_DSTS_ENUMSPD_POS) +#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << USBFS_DSTS_ENUMSPD_POS) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << USBFS_DSTS_ENUMSPD_POS) + +/* EP type */ +#define EP_TYPE_CTRL (0U) +#define EP_TYPE_ISOC (1U) +#define EP_TYPE_BULK (2U) +#define EP_TYPE_INTR (3U) +#define EP_TYPE_MSK (3U) + +/* USB port speed */ +#define PRTSPD_FULL_SPEED (1U) +#define PRTSPD_LOW_SPEED (2U) + +/* PHY clock */ +#define HCFG_30_60_MHZ (0U) +#define HCFG_48_MHZ (1U) +#define HCFG_6_MHZ (2U) + +#define USB_EP_TX_DIS (0x0000U) +#define USB_EP_TX_STALL (0x0010U) +#define USB_EP_TX_NAK (0x0020U) +#define USB_EP_TX_VALID (0x0030U) + +#define USB_EP_RX_DIS (0x0000U) +#define USB_EP_RX_STALL (0x1000U) +#define USB_EP_RX_NAK (0x2000U) +#define USB_EP_RX_VALID (0x3000U) + +#define USB_OK (0U) +#define USB_ERROR (1U) + +#define USB_FRAME_INTERVAL_80 (0UL << USBFS_DCFG_PFIVL_POS) +#define USB_FRAME_INTERVAL_85 (1UL << USBFS_DCFG_PFIVL_POS) +#define USB_FRAME_INTERVAL_90 (2UL << USBFS_DCFG_PFIVL_POS) +#define USB_FRAME_INTERVAL_95 (3UL << USBFS_DCFG_PFIVL_POS) + +#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) +#define LOBYTE(x) ((uint8_t)((uint16_t)(x) & 0x00FFU)) +#define HIBYTE(x) ((uint8_t)(((uint16_t)(x) & 0xFF00U) >>8U)) + +#ifdef USB_INTERNAL_DMA_ENABLED +#define __USB_ALIGN_END +#if defined (__GNUC__) /* GNU Compiler */ +#define __USB_ALIGN_BEGIN __attribute__ ((aligned (4))) +#elif defined (__CC_ARM) /* ARM Compiler */ +#define __USB_ALIGN_BEGIN __align(4) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __USB_ALIGN_BEGIN +#elif defined (__TASKING__) /* TASKING Compiler */ +#define __USB_ALIGN_BEGIN __align(4) +#endif +#else +#define __USB_ALIGN_BEGIN +#define __USB_ALIGN_END +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +typedef struct { + __IO uint32_t GVBUSCFG; /* VBUS Configuration Register 000h */ + uint32_t Reserved04; /* Reserved 004h */ + __IO uint32_t GAHBCFG; /* AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /* USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /* Reset Register 010h */ + __IO uint32_t GINTSTS; /* Interrupt Register 014h */ + __IO uint32_t GINTMSK; /* Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */ + __IO uint32_t HNPTXFSIZ; /* HNPTXFSIZ: Host Non-Periodic Transmit FIFO Size Register 028h */ + /* DIEPTXF0: Device IN EP0 Transmit FIFO size register 028h */ + __IO uint32_t HNPTXSTS; /* Host Non Periodic Transmit FIFO/Queue Status Register 02Ch */ + uint32_t Reserved30[3]; /* Reserved 030h-038h */ + __IO uint32_t CID; /* User ID Register 03Ch */ + uint32_t Reserved40[5]; /* Reserved 040h-050h */ + __IO uint32_t GLPMCFG; /* Low Power Mode Configuration Register 054h */ + uint32_t Reserved58[42]; /* Reserved 058h-0FCh */ + __IO uint32_t HPTXFSIZ; /* Host Periodic Transmit FIFO Size Register 100h */ + __IO uint32_t DIEPTXF[USB_MAX_TX_FIFOS]; /* Device Periodic Transmit FIFO Size Register */ +} USB_CORE_GREGS; + +typedef struct { + __IO uint32_t DCFG; /* Device Configuration Register 800h */ + __IO uint32_t DCTL; /* Device Control Register 804h */ + __IO uint32_t DSTS; /* Device Status Register (RO) 808h */ + uint32_t Reserved0C; /* Reserved 80Ch */ + __IO uint32_t DIEPMSK; /* Device IN EP Common Interrupt Mask Register 810h */ + __IO uint32_t DOEPMSK; /* Device OUT EP Common Interrupt Mask Register 814h */ + __IO uint32_t DAINT; /* Device All EP Interrupt Register 818h */ + __IO uint32_t DAINTMSK; /* Device All EP Interrupt Mask Register 81Ch */ + uint32_t Reserved20[4]; /* Reserved 820h-82Ch */ + __IO uint32_t DTHRCTL; /* Device Threshold Control Register 830h */ + __IO uint32_t DIEPEMPMSK; /* Device IN EP FIFO Empty Interrupt Mask Register 834h */ + __IO uint32_t DEACHINT; /* Deivce Each EP Interrupt Register 838h */ + __IO uint32_t DEACHINTMSK; /* Device Each EP Interrupt Mask Register 83Ch */ + uint32_t Reserved40; /* Reserved 840h */ + __IO uint32_t DIEPEACHMSK1; /* Deveice IN EP1 Interrupt Mask Register 844h */ + uint32_t Reserved48[15]; /* Reserved 848-880h */ + __IO uint32_t DOEPEACHMSK1; /* Deveice OUT EP1 Interrupt Mask Register 884h */ +} USB_CORE_DREGS; + +typedef struct { + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /* IN Endpoint Tx FIFO Status 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ +} USB_CORE_INEPREGS; + +typedef struct { + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_CORE_OUTEPREGS; + +typedef struct { + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} USB_CORE_HREGS; + +typedef struct { + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} USB_CORE_HC_REGS; + +typedef struct { /* 000h */ + USB_CORE_GREGS *GREGS; + USB_CORE_DREGS *DREGS; + USB_CORE_HREGS *HREGS; + USB_CORE_INEPREGS *INEP_REGS[USB_MAX_TX_FIFOS]; + USB_CORE_OUTEPREGS *OUTEP_REGS[USB_MAX_TX_FIFOS]; + USB_CORE_HC_REGS *HC_REGS[USB_MAX_TX_FIFOS]; + __IO uint32_t *HPRT; + __IO uint32_t *DFIFO[USB_MAX_TX_FIFOS]; + __IO uint32_t *GCCTL; +} LL_USB_TypeDef; + +typedef struct { + uint8_t host_chnum; + uint8_t dev_epnum; + uint8_t dmaen; + uint8_t low_power; + uint8_t phy_type; + uint8_t core_type; +} USB_CORE_BASIC_CFGS; + +typedef struct { + uint8_t dev_addr; + uint8_t ep_idx; + uint8_t is_epin; + uint8_t ch_speed; + uint8_t do_ping; + uint8_t ep_type; + uint16_t max_packet; + uint8_t pid_type; + uint8_t in_toggle; + uint8_t out_toggle; + /* transaction level variables*/ + uint32_t dma_addr; + uint32_t xfer_len; + uint32_t xfer_count; + uint8_t *xfer_buff; +} USB_HOST_CH; + +typedef struct { + uint8_t epidx; + uint8_t ep_dir; + uint8_t trans_type; + uint8_t ep_stall; + uint8_t data_pid_start; + uint8_t datax_pid; + uint16_t tx_fifo_num; + uint32_t maxpacket; + /* Transfer level variables */ + uint32_t rem_data_len; + uint32_t total_data_len; + uint32_t ctl_data_len; + /* transaction level variables*/ + uint32_t dma_addr; + uint32_t xfer_len; + uint32_t xfer_count; + uint8_t *xfer_buff; +} USB_DEV_EP; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @addtogroup USB_Global_Functions + * @{ + */ + +/** + * @brief get the current mode of the usb core from the corresponding register + * @param [in] USBx usb instance + * @retval current mode 1: host mode 0: device mode + */ +__STATIC_INLINE uint8_t usb_getcurmod(LL_USB_TypeDef *USBx) +{ + if (0UL != READ_REG32_BIT(USBx->GREGS->GINTSTS, USBFS_GINTSTS_CMOD)) { + return 1U; + } else { + return 0U; + } +} + +/** + * @brief Initializes the normal interrupts + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_normalinten(LL_USB_TypeDef *USBx) +{ + WRITE_REG32(USBx->GREGS->GINTSTS, 0xBFFFFFFFUL); + WRITE_REG32(USBx->GREGS->GINTMSK, USBFS_GINTMSK_WKUIM | USBFS_GINTMSK_USBSUSPM); +} + +/** + * @brief clear all the pending device interrupt bits and mask the IN and OUT + * endpoint interrupts. + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_clrandmskepint(LL_USB_TypeDef *USBx) +{ + WRITE_REG32(USBx->DREGS->DIEPMSK, 0UL); + WRITE_REG32(USBx->DREGS->DOEPMSK, 0UL); + WRITE_REG32(USBx->DREGS->DAINT, 0xFFFFFFFFUL); + WRITE_REG32(USBx->DREGS->DAINTMSK, 0UL); +} + +/** + * @brief generate a device connect signal to the USB host + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_coreconn(LL_USB_TypeDef *USBx) +{ + CLR_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_SDIS); +} + +/** + * @brief test of mode processing + * @param [in] USBx usb instance + * @param [in] reg Register write + * @retval None + */ +__STATIC_INLINE void usb_runtestmode(LL_USB_TypeDef *USBx, uint32_t reg) +{ + WRITE_REG32(USBx->DREGS->DCTL, reg); +} + +/** + * @brief Enables the controller's Global interrupts in the AHB Configuration + * registers. + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_ginten(LL_USB_TypeDef *USBx) +{ + SET_REG32_BIT(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_GINTMSK); +} + +/** + * @brief Disable the controller's Global interrupt in the AHB Configuration + * register. + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_gintdis(LL_USB_TypeDef *USBx) +{ + CLR_REG32_BIT(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_GINTMSK); +} + +/** + * @brief Get the Core Interrupt bits from the interrupt register not including + * the bits that are masked. + * @param [in] USBx usb instance + * @retval status[32bits] + */ +__STATIC_INLINE uint32_t usb_getcoreintr(LL_USB_TypeDef *USBx) +{ + uint32_t v; + v = READ_REG32(USBx->GREGS->GINTSTS); + v &= READ_REG32(USBx->GREGS->GINTMSK); + return v; +} + +/** + * @brief Get the out endpoint interrupt bits from the all endpoint interrupt + * register not including the bits masked. + * @param [in] USBx usb instance + * @retval The status that shows which OUT EP have interrupted. + */ +__STATIC_INLINE uint32_t usb_getalloepintr(LL_USB_TypeDef *USBx) +{ + uint32_t v; + v = READ_REG32(USBx->DREGS->DAINT); + v &= READ_REG32(USBx->DREGS->DAINTMSK); + return ((v & 0xFFFF0000UL) >> 16U); +} + +/** + * @brief Get the Device OUT EP Interrupt register(DOEPINT) not including the + * interrupt bits that are masked. + * @param [in] USBx usb instance + * @param [in] epnum end point index + * @retval all the interrupt bits on DOEPINTn while n = epnum + */ +__STATIC_INLINE uint32_t usb_getoepintbit(LL_USB_TypeDef *USBx, uint8_t epnum) +{ + uint32_t v; + v = READ_REG32(USBx->OUTEP_REGS[epnum]->DOEPINT); + v &= READ_REG32(USBx->DREGS->DOEPMSK); + return v; +} + +/** + * @brief Get the IN endpoint interrupt bits from the all endpoint interrupt + * register not including the bits masked. + * @param [in] USBx usb instance + * @retval The status that shows which IN EP have interrupted. + */ +__STATIC_INLINE uint32_t usb_getalliepintr(LL_USB_TypeDef *USBx) +{ + uint32_t v; + v = READ_REG32(USBx->DREGS->DAINT); + v &= READ_REG32(USBx->DREGS->DAINTMSK); + return (v & 0xFFFFUL); +} + +/** + * @brief Set the device a new address. + * @param [in] USBx usb instance + * @param [in] address device address which will be set to the corresponding register. + * @retval None + */ +__STATIC_INLINE void usb_devaddrset(LL_USB_TypeDef *USBx, uint8_t address) +{ + MODIFY_REG32(USBx->DREGS->DCFG, USBFS_DCFG_DAD, (uint32_t)address << USBFS_DCFG_DAD_POS); +} + +/** + * @brief Select the USB PHY. + * @param [in] USBx usb instance + * @param [in] PhyType USB phy, 1 select external ULPI PHY, 0 select internal FS PHY + * @retval None + */ +__STATIC_INLINE void usb_PhySelect(LL_USB_TypeDef *USBx, uint8_t PhyType) +{ + if (1U == PhyType) { + CLR_REG32_BIT(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_PHYSEL); + //SET_REG32_BIT(USBx->GREGS->GUSBCFG, 1UL<<4); //todo 手册上没有该bit + } else { + SET_REG32_BIT(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_PHYSEL); + } +} + +/** + * @brief Select the USB device PHY. + * @param [in] USBx usb instance + * @param [in] PhyType USB phy, 1 select external ULPI PHY, 0 select internal FS PHY + * @retval None + */ +__STATIC_INLINE void usb_DevPhySelect(LL_USB_TypeDef *USBx, uint8_t PhyType) +{ + if (1U == PhyType) { + CLR_REG32_BIT(USBx->DREGS->DCFG, USBFS_DCFG_DSPD); + } else { + SET_REG32_BIT(USBx->DREGS->DCFG, USBFS_DCFG_DSPD); + } + +} + +/** + * @brief USB DMA function command. + * @param [in] USBx usb instance + * @param [in] DmaCmd USB DMA command status, 0 disable, 1 enable + * @retval None + */ +__STATIC_INLINE void usb_DmaCmd(LL_USB_TypeDef *USBx, uint8_t DmaCmd) +{ + MODIFY_REG32(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_DMAEN, (uint32_t)DmaCmd << USBFS_GAHBCFG_DMAEN_POS); +} + +/** + * @brief USB burst length config. + * @param [in] USBx usb instance + * @param [in] len Burst length + * @retval None + */ +__STATIC_INLINE void usb_BurstLenConfig(LL_USB_TypeDef *USBx, uint8_t len) +{ + MODIFY_REG32(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_HBSTLEN, (uint32_t)len << USBFS_GAHBCFG_HBSTLEN_POS); +} + +/** + * @brief USB frame interval config + * @param [in] USBx usb instance + * @param [in] interval Frame interval + * @retval None + */ +__STATIC_INLINE void usb_FrameIntervalConfig(LL_USB_TypeDef *USBx, uint8_t interval) +{ + MODIFY_REG32(USBx->DREGS->DCFG, USBFS_DCFG_PFIVL, interval); +} + +#ifdef USE_HOST_MODE +/** + * @brief Read the register HPRT and reset the following bits. + * @param [in] USBx usb instance + * @retval value of HPRT + */ +//#define USBFS_HPRT_PRTOVRCURRCHNG (0x00000020UL) +__STATIC_INLINE uint32_t usb_rdhprt(LL_USB_TypeDef *USBx) +{ +//todo don't have prtovrcurrchng bit + return (READ_REG32(*USBx->HPRT) & ~(USBFS_HPRT_PENA | USBFS_HPRT_PCDET | USBFS_HPRT_PENCHNG)); +} + +/** + * @brief Issues a ping token + * @param [in] USBx usb instance + * @param [in] hc_num the host channel index + * @retval None + */ +//#define USBFS_HCTSIZ_DOPNG (0x80000000UL) +__STATIC_INLINE void usb_pingtokenissue(LL_USB_TypeDef *USBx, uint8_t hc_num) +{ + //todo don't have dopng bit + WRITE_REG32(USBx->HC_REGS[hc_num]->HCTSIZ, 1UL << USBFS_HCTSIZ_PKTCNT_POS); + MODIFY_REG32(USBx->HC_REGS[hc_num]->HCCHAR, USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS, USBFS_HCCHAR_CHENA); +} + +/** + * @brief This function returns the frame number for sof packet + * @param [in] USBx usb instance + * @retval Frame number + */ +__STATIC_INLINE uint32_t usb_ifevenframe(LL_USB_TypeDef *USBx) +{ + return ((READ_REG32(USBx->HREGS->HFNUM) + 1UL) & 0x1UL); +} + +/** + * @brief Initializes the FSLSPClkSel field of the HCFG register on the PHY type + * @param [in] USBx usb instance + * @param [in] freq clock frequency + * @retval None + */ +__STATIC_INLINE void usb_fslspclkselset(LL_USB_TypeDef *USBx, uint8_t freq) +{ + MODIFY_REG32(USBx->HREGS->HCFG, USBFS_HCFG_FSLSPCS, (uint32_t)freq << USBFS_HCFG_FSLSPCS_POS); +} + +/** + * @brief suspend the port + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_prtsusp(LL_USB_TypeDef *USBx) +{ + uint32_t u32hprt; + u32hprt = usb_rdhprt(USBx); + u32hprt |= USBFS_HPRT_PSUSP; + u32hprt &= ~USBFS_HPRT_PRES; + WRITE_REG32(*USBx->HPRT, u32hprt); +} + +/** + * @brief control the enumeration speed of the core, this function make sure that + * the maximum speed supperted by the connected device. + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_enumspeed(LL_USB_TypeDef *USBx) +{ + CLR_REG32_BIT(USBx->HREGS->HCFG, USBFS_HCFG_FSLSS); +} + +/** + * @brief set the TXFIFO and depth for non-periodic and periodic and RXFIFO size + * @param [in] USBx usb instance + * @retval None + */ +__STATIC_INLINE void usb_sethostfifo(LL_USB_TypeDef *USBx) +{ +#ifdef USB_FS_MODE + /* USBFS Core*/ + WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); /* set the RxFIFO Depth */ + /* non-periodic transmit RAM start address, set the non-periodic TxFIFO depth */ + WRITE_REG32(USBx->GREGS->HNPTXFSIZ, + (RX_FIFO_FS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS) + | (TXH_NP_FS_FIFOSIZ << USBFS_HNPTXFSIZ_NPTXFD_POS)); + /* set the host periodic TxFIFO start address, set the host periodic TxFIFO depth */ + WRITE_REG32(USBx->GREGS->HPTXFSIZ, + ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ) << USBFS_HPTXFSIZ_PTXSA_POS) + | (TXH_P_FS_FIFOSIZ << USBFS_HPTXFSIZ_PTXFD_POS)); +#else + /* USBHS Core */ + WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); + WRITE_REG32(USBx->GREGS->HNPTXFSIZ, + (RX_FIFO_HS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS) + | (TXH_NP_HS_FIFOSIZ << USBFS_HNPTXFSIZ_NPTXFD_POS)); + WRITE_REG32(USBx->GREGS->HPTXFSIZ, + ((RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ) << USBFS_HPTXFSIZ_PTXSA_POS) + | (TXH_P_HS_FIFOSIZ << USBFS_HPTXFSIZ_PTXFD_POS)); +#endif +} + +/** + * @brief reset the channel whose channel number is ch_idx + * @param [in] USBx usb instance + * @param [in] ch_idx channel number + * @retval None + */ +__STATIC_INLINE void usb_chrst(LL_USB_TypeDef *USBx, uint8_t ch_idx) +{ + MODIFY_REG32(USBx->HC_REGS[ch_idx]->HCCHAR, + USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS | USBFS_HCCHAR_EPDIR, + USBFS_HCCHAR_CHDIS); +} +#endif /* end of USE_HOST_MODE */ + +extern void usb_initusbcore(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs); +extern void usb_setregaddr(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs); +extern void usb_rdpkt(LL_USB_TypeDef *USBx, uint8_t *dest, uint16_t len); +extern void usb_wrpkt(LL_USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t u8DmaEn); +extern void usb_txfifoflush(LL_USB_TypeDef *USBx, uint32_t num); +extern void usb_rxfifoflush(LL_USB_TypeDef *USBx); +extern void usb_modeset(LL_USB_TypeDef *USBx, uint8_t mode); +extern void usb_coresoftrst(LL_USB_TypeDef *USBx); + +#ifdef USE_HOST_MODE +extern void usb_hostmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs); +extern void usb_hostinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn); +extern uint8_t usb_inithch(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn); +extern void usb_hchstop(LL_USB_TypeDef *USBx, uint8_t hc_num); +extern uint8_t usb_hchtransbegin(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn); +extern void usb_hprtrst(LL_USB_TypeDef *USBx); +extern void usb_vbusctrl(LL_USB_TypeDef *USBx, uint8_t u8State); +#endif + +#ifdef USE_DEVICE_MODE +extern void usb_devmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs); +extern void usb_devinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn); +extern void usb_ep0activate(LL_USB_TypeDef *USBx); +extern void usb_epactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_epdeactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_epntransbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn); +extern void usb_ep0transbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn); +extern void usb_setepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_clearepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_ep0revcfg(LL_USB_TypeDef *USBx, uint8_t u8DmaEn, uint8_t *u8RevBuf); +extern void usb_remotewakeupen(LL_USB_TypeDef *USBx); +extern void usb_epstatusset(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint32_t Status); +extern uint32_t usb_epstatusget(LL_USB_TypeDef *USBx, USB_DEV_EP *ep); +extern void usb_devepdis(LL_USB_TypeDef *USBx, uint8_t u8EpNum); +extern void usb_ctrldevconnect(LL_USB_TypeDef *USBx, uint8_t link); +#endif + +/** + * @} + */ + +#endif /* LL_USB_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_USB_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_utility.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_utility.h new file mode 100644 index 0000000000..236d7365fd --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_utility.h @@ -0,0 +1,131 @@ +/** + ******************************************************************************* + * @file hc32_ll_utility.h + * @brief This file contains all the functions prototypes of the DDL utility. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_UTILITY_H__ +#define __HC32_LL_UTILITY_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_UTILITY + * @{ + */ + +#if (LL_UTILITY_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup UTILITY_Global_Functions + * @{ + */ + +/* Imprecise delay */ +void DDL_DelayMS(uint32_t u32Count); +void DDL_DelayUS(uint32_t u32Count); + +/* Systick functions */ +int32_t SysTick_Init(uint32_t u32Freq); +void SysTick_Delay(uint32_t u32Delay); +void SysTick_IncTick(void); +uint32_t SysTick_GetTick(void); +void SysTick_Suspend(void); +void SysTick_Resume(void); + +#if (LL_PRINT_ENABLE == DDL_ON) +int32_t LL_PrintfInit(void *vpDevice, uint32_t u32Param, int32_t (*pfnPreinit)(void *vpDevice, uint32_t u32Param)); +#endif + +/* You can add your own assert functions by implement the function DDL_AssertHandler + definition follow the function DDL_AssertHandler declaration */ +#ifdef __DEBUG +#define DDL_ASSERT(x) \ +do { \ + ((x) ? (void)0 : DDL_AssertHandler(__FILE__, __LINE__)); \ +} while (0) +/* Exported function */ +void DDL_AssertHandler(const char *file, int line); +#else +#define DDL_ASSERT(x) ((void)0U) +#endif /* __DEBUG */ + +#if (LL_PRINT_ENABLE == DDL_ON) +#include +__WEAKDEF int32_t DDL_ConsoleOutputChar(char cData); + +#define DDL_PrintfInit (void)LL_PrintfInit +#define DDL_Printf (void)printf +#else +#define DDL_PrintfInit(vpDevice, u32Param, pfnPreinit) +#define DDL_Printf(...) +#endif + +/** + * @} + */ + +#endif /* LL_UTILITY_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_UTILITY_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_wdt.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_wdt.h new file mode 100644 index 0000000000..ac77925e6d --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32_ll_wdt.h @@ -0,0 +1,227 @@ +/** + ******************************************************************************* + * @file hc32_ll_wdt.h + * @brief This file contains all the functions prototypes of the WDT driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_WDT_H__ +#define __HC32_LL_WDT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_WDT + * @{ + */ + +#if (LL_WDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Types WDT Global Types + * @{ + */ + +/** + * @brief WDT Init structure definition + */ +typedef struct { + uint32_t u32CountPeriod; /*!< Specifies the counting period of WDT. + This parameter can be a value of @ref WDT_Count_Period */ + uint32_t u32ClockDiv; /*!< Specifies the clock division factor of WDT. + This parameter can be a value of @ref WDT_Clock_Division */ + uint32_t u32RefreshRange; /*!< Specifies the allow refresh range of WDT. + This parameter can be a value of @ref WDT_Refresh_Range */ + uint32_t u32LPMCount; /*!< Specifies the count state in Low Power Mode (Sleep Mode). + This parameter can be a value of @ref WDT_LPM_Count */ + uint32_t u32ExceptionType; /*!< Specifies the type of exception response for WDT. + This parameter can be a value of @ref WDT_Exception_Type */ +} stc_wdt_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Macros WDT Global Macros + * @{ + */ + +/** + * @defgroup WDT_Count_Period WDT Count Period + * @{ + */ +#define WDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */ +#define WDT_CNT_PERIOD4096 (WDT_CR_PERI_0) /*!< 4096 clock cycle */ +#define WDT_CNT_PERIOD16384 (WDT_CR_PERI_1) /*!< 16384 clock cycle */ +#define WDT_CNT_PERIOD65536 (WDT_CR_PERI) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup WDT_Clock_Division WDT Clock Division + * @{ + */ +#define WDT_CLK_DIV4 (0x02UL << WDT_CR_CKS_POS) /*!< PLCKx/4 */ +#define WDT_CLK_DIV64 (0x06UL << WDT_CR_CKS_POS) /*!< PLCKx/64 */ +#define WDT_CLK_DIV128 (0x07UL << WDT_CR_CKS_POS) /*!< PLCKx/128 */ +#define WDT_CLK_DIV256 (0x08UL << WDT_CR_CKS_POS) /*!< PLCKx/256 */ +#define WDT_CLK_DIV512 (0x09UL << WDT_CR_CKS_POS) /*!< PLCKx/512 */ +#define WDT_CLK_DIV1024 (0x0AUL << WDT_CR_CKS_POS) /*!< PLCKx/1024 */ +#define WDT_CLK_DIV2048 (0x0BUL << WDT_CR_CKS_POS) /*!< PLCKx/2048 */ +#define WDT_CLK_DIV8192 (0x0DUL << WDT_CR_CKS_POS) /*!< PLCKx/8192 */ +/** + * @} + */ + +/** + * @defgroup WDT_Refresh_Range WDT Refresh Range + * @{ + */ +#define WDT_RANGE_0TO25PCT (0x01UL << WDT_CR_WDPT_POS) /*!< 0%~25% */ +#define WDT_RANGE_25TO50PCT (0x02UL << WDT_CR_WDPT_POS) /*!< 25%~50% */ +#define WDT_RANGE_0TO50PCT (0x03UL << WDT_CR_WDPT_POS) /*!< 0%~50% */ +#define WDT_RANGE_50TO75PCT (0x04UL << WDT_CR_WDPT_POS) /*!< 50%~75% */ +#define WDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << WDT_CR_WDPT_POS) /*!< 0%~25% & 50%~75% */ +#define WDT_RANGE_25TO75PCT (0x06UL << WDT_CR_WDPT_POS) /*!< 25%~75% */ +#define WDT_RANGE_0TO75PCT (0x07UL << WDT_CR_WDPT_POS) /*!< 0%~75% */ +#define WDT_RANGE_75TO100PCT (0x08UL << WDT_CR_WDPT_POS) /*!< 75%~100% */ +#define WDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << WDT_CR_WDPT_POS) /*!< 0%~25% & 75%~100% */ +#define WDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << WDT_CR_WDPT_POS) /*!< 25%~50% & 75%~100% */ +#define WDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << WDT_CR_WDPT_POS) /*!< 0%~50% & 75%~100% */ +#define WDT_RANGE_50TO100PCT (0x0CUL << WDT_CR_WDPT_POS) /*!< 50%~100% */ +#define WDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << WDT_CR_WDPT_POS) /*!< 0%~25% & 50%~100% */ +#define WDT_RANGE_25TO100PCT (0x0EUL << WDT_CR_WDPT_POS) /*!< 25%~100% */ +#define WDT_RANGE_0TO100PCT (0x0FUL << WDT_CR_WDPT_POS) /*!< 0%~100% */ +/** + * @} + */ + +/** + * @defgroup WDT_LPM_Count WDT Low Power Mode Count + * @brief Counting control of WDT in sleep mode. + * @{ + */ +#define WDT_LPM_CNT_CONTINUE (0UL) /*!< Continue counting in sleep mode */ +#define WDT_LPM_CNT_STOP (WDT_CR_SLPOFF) /*!< Stop counting in sleep mode */ +/** + * @} + */ + +/** + * @defgroup WDT_Exception_Type WDT Exception Type + * @brief Specifies the exception response when a refresh error or count overflow occurs. + * @{ + */ +#define WDT_EXP_TYPE_INT (0UL) /*!< WDT trigger interrupt */ +#define WDT_EXP_TYPE_RST (WDT_CR_ITS) /*!< WDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup WDT_Flag WDT Flag + * @{ + */ +#define WDT_FLAG_UDF (WDT_SR_UDF) /*!< Count underflow flag */ +#define WDT_FLAG_REFRESH (WDT_SR_REF) /*!< Refresh error flag */ +#define WDT_FLAG_ALL (WDT_SR_UDF | WDT_SR_REF) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup WDT_Global_Functions + * @{ + */ + +/** + * @brief Get WDT count value. + * @param None + * @retval uint16_t Count value + */ +__STATIC_INLINE uint16_t WDT_GetCountValue(void) +{ + return (uint16_t)(READ_REG32(CM_WDT->SR) & WDT_SR_CNT); +} + +/* Initialization and configuration functions */ +int32_t WDT_Init(const stc_wdt_init_t *pstcWdtInit); +void WDT_FeedDog(void); +uint16_t WDT_GetCountValue(void); + +/* Flags management functions */ +en_flag_status_t WDT_GetStatus(uint32_t u32Flag); +int32_t WDT_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_WDT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_WDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32f460_ll_interrupts_share.h b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32f460_ll_interrupts_share.h new file mode 100644 index 0000000000..7d26a9718c --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/inc/hc32f460_ll_interrupts_share.h @@ -0,0 +1,350 @@ +/** + ******************************************************************************* + * @file hc32f460_ll_interrupts_share.h + * @brief This file contains all the functions prototypes of the interrupt driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F460_LL_INTERRUPTS_SHARE_H__ +#define __HC32F460_LL_INTERRUPTS_SHARE_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_HC32F460_SHARE_INTERRUPTS + * @{ + */ + +#if (LL_INTERRUPTS_SHARE_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup Share_Interrupts_Global_Functions + * @{ + */ + +int32_t INTC_ShareIrqCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState); + +void IRQ128_Handler(void); +void IRQ129_Handler(void); +void IRQ130_Handler(void); +void IRQ131_Handler(void); +void IRQ132_Handler(void); +void IRQ136_Handler(void); +void IRQ137_Handler(void); +void IRQ138_Handler(void); +void IRQ139_Handler(void); +void IRQ140_Handler(void); +void IRQ141_Handler(void); +void IRQ142_Handler(void); +void IRQ143_Handler(void); + +void EXTINT00_IrqHandler(void); +void EXTINT01_IrqHandler(void); +void EXTINT02_IrqHandler(void); +void EXTINT03_IrqHandler(void); +void EXTINT04_IrqHandler(void); +void EXTINT05_IrqHandler(void); +void EXTINT06_IrqHandler(void); +void EXTINT07_IrqHandler(void); +void EXTINT08_IrqHandler(void); +void EXTINT09_IrqHandler(void); +void EXTINT10_IrqHandler(void); +void EXTINT11_IrqHandler(void); +void EXTINT12_IrqHandler(void); +void EXTINT13_IrqHandler(void); +void EXTINT14_IrqHandler(void); +void EXTINT15_IrqHandler(void); + +void DMA1_TC0_IrqHandler(void); +void DMA1_TC1_IrqHandler(void); +void DMA1_TC2_IrqHandler(void); +void DMA1_TC3_IrqHandler(void); +void DMA2_TC0_IrqHandler(void); +void DMA2_TC1_IrqHandler(void); +void DMA2_TC2_IrqHandler(void); +void DMA2_TC3_IrqHandler(void); +void DMA1_BTC0_IrqHandler(void); +void DMA1_BTC1_IrqHandler(void); +void DMA1_BTC2_IrqHandler(void); +void DMA1_BTC3_IrqHandler(void); +void DMA2_BTC0_IrqHandler(void); +void DMA2_BTC1_IrqHandler(void); +void DMA2_BTC2_IrqHandler(void); +void DMA2_BTC3_IrqHandler(void); +void DMA1_Error0_IrqHandler(void); +void DMA1_Error1_IrqHandler(void); +void DMA1_Error2_IrqHandler(void); +void DMA1_Error3_IrqHandler(void); +void DMA2_Error0_IrqHandler(void); +void DMA2_Error1_IrqHandler(void); +void DMA2_Error2_IrqHandler(void); +void DMA2_Error3_IrqHandler(void); + +void EFM_ProgramEraseError_IrqHandler(void); +void EFM_ColError_IrqHandler(void); +void EFM_OpEnd_IrqHandler(void); +void QSPI_Error_IrqHandler(void); +void DCU1_IrqHandler(void); +void DCU2_IrqHandler(void); +void DCU3_IrqHandler(void); +void DCU4_IrqHandler(void); + +void TMR0_1_CmpA_IrqHandler(void); +void TMR0_1_CmpB_IrqHandler(void); +void TMR0_2_CmpA_IrqHandler(void); +void TMR0_2_CmpB_IrqHandler(void); + +void CLK_XtalStop_IrqHandler(void); +void PWC_WakeupTimer_IrqHandler(void); +void SWDT_IrqHandler(void); +void WDT_IrqHandler(void); + +void TMR6_1_GCmpA_IrqHandler(void); +void TMR6_1_GCmpB_IrqHandler(void); +void TMR6_1_GCmpC_IrqHandler(void); +void TMR6_1_GCmpD_IrqHandler(void); +void TMR6_1_GCmpE_IrqHandler(void); +void TMR6_1_GCmpF_IrqHandler(void); +void TMR6_1_GOvf_IrqHandler(void); +void TMR6_1_GUdf_IrqHandler(void); +void TMR6_1_GDte_IrqHandler(void); +void TMR6_1_SCmpA_IrqHandler(void); +void TMR6_1_SCmpB_IrqHandler(void); + +void TMR6_2_GCmpA_IrqHandler(void); +void TMR6_2_GCmpB_IrqHandler(void); +void TMR6_2_GCmpC_IrqHandler(void); +void TMR6_2_GCmpD_IrqHandler(void); +void TMR6_2_GCmpE_IrqHandler(void); +void TMR6_2_GCmpF_IrqHandler(void); +void TMR6_2_GOvf_IrqHandler(void); +void TMR6_2_GUdf_IrqHandler(void); +void TMR6_2_GDte_IrqHandler(void); +void TMR6_2_SCmpA_IrqHandler(void); +void TMR6_2_SCmpB_IrqHandler(void); + +void TMR6_3_GCmpA_IrqHandler(void); +void TMR6_3_GCmpB_IrqHandler(void); +void TMR6_3_GCmpC_IrqHandler(void); +void TMR6_3_GCmpD_IrqHandler(void); +void TMR6_3_GCmpE_IrqHandler(void); +void TMR6_3_GCmpF_IrqHandler(void); +void TMR6_3_GOvf_IrqHandler(void); +void TMR6_3_GUdf_IrqHandler(void); +void TMR6_3_GDte_IrqHandler(void); +void TMR6_3_SCmpA_IrqHandler(void); +void TMR6_3_SCmpB_IrqHandler(void); + +void TMRA_1_Ovf_IrqHandler(void); +void TMRA_1_Udf_IrqHandler(void); +void TMRA_1_Cmp_IrqHandler(void); +void TMRA_2_Ovf_IrqHandler(void); +void TMRA_2_Udf_IrqHandler(void); +void TMRA_2_Cmp_IrqHandler(void); +void TMRA_3_Ovf_IrqHandler(void); +void TMRA_3_Udf_IrqHandler(void); +void TMRA_3_Cmp_IrqHandler(void); +void TMRA_4_Ovf_IrqHandler(void); +void TMRA_4_Udf_IrqHandler(void); +void TMRA_4_Cmp_IrqHandler(void); +void TMRA_5_Ovf_IrqHandler(void); +void TMRA_5_Udf_IrqHandler(void); +void TMRA_5_Cmp_IrqHandler(void); +void TMRA_6_Ovf_IrqHandler(void); +void TMRA_6_Udf_IrqHandler(void); +void TMRA_6_Cmp_IrqHandler(void); + +void USBFS_Global_IrqHandler(void); + +void USART1_RxError_IrqHandler(void); +void USART1_RxFull_IrqHandler(void); +void USART1_TxEmpty_IrqHandler(void); +void USART1_TxComplete_IrqHandler(void); +void USART1_RxTO_IrqHandler(void); +void USART2_RxError_IrqHandler(void); +void USART2_RxFull_IrqHandler(void); +void USART2_TxEmpty_IrqHandler(void); +void USART2_TxComplete_IrqHandler(void); +void USART2_RxTO_IrqHandler(void); +void USART3_RxError_IrqHandler(void); +void USART3_RxFull_IrqHandler(void); +void USART3_TxEmpty_IrqHandler(void); +void USART3_TxComplete_IrqHandler(void); +void USART3_RxTO_IrqHandler(void); +void USART4_RxError_IrqHandler(void); +void USART4_RxFull_IrqHandler(void); +void USART4_TxEmpty_IrqHandler(void); +void USART4_TxComplete_IrqHandler(void); +void USART4_RxTO_IrqHandler(void); + +void SPI1_RxFull_IrqHandler(void); +void SPI1_TxEmpty_IrqHandler(void); +void SPI1_Error_IrqHandler(void); +void SPI1_Idle_IrqHandler(void); +void SPI2_RxFull_IrqHandler(void); +void SPI2_TxEmpty_IrqHandler(void); +void SPI2_Error_IrqHandler(void); +void SPI2_Idle_IrqHandler(void); +void SPI3_RxFull_IrqHandler(void); +void SPI3_TxEmpty_IrqHandler(void); +void SPI3_Error_IrqHandler(void); +void SPI3_Idle_IrqHandler(void); +void SPI4_RxFull_IrqHandler(void); +void SPI4_TxEmpty_IrqHandler(void); +void SPI4_Error_IrqHandler(void); +void SPI4_Idle_IrqHandler(void); + +void TMR4_1_GCmpUH_IrqHandler(void); +void TMR4_1_GCmpUL_IrqHandler(void); +void TMR4_1_GCmpVH_IrqHandler(void); +void TMR4_1_GCmpVL_IrqHandler(void); +void TMR4_1_GCmpWH_IrqHandler(void); +void TMR4_1_GCmpWL_IrqHandler(void); +void TMR4_1_GOvf_IrqHandler(void); +void TMR4_1_GUdf_IrqHandler(void); +void TMR4_1_ReloadU_IrqHandler(void); +void TMR4_1_ReloadV_IrqHandler(void); +void TMR4_1_ReloadW_IrqHandler(void); +void TMR4_2_GCmpUH_IrqHandler(void); +void TMR4_2_GCmpUL_IrqHandler(void); +void TMR4_2_GCmpVH_IrqHandler(void); +void TMR4_2_GCmpVL_IrqHandler(void); +void TMR4_2_GCmpWH_IrqHandler(void); +void TMR4_2_GCmpWL_IrqHandler(void); +void TMR4_2_GOvf_IrqHandler(void); +void TMR4_2_GUdf_IrqHandler(void); +void TMR4_2_ReloadU_IrqHandler(void); +void TMR4_2_ReloadV_IrqHandler(void); +void TMR4_2_ReloadW_IrqHandler(void); +void TMR4_3_GCmpUH_IrqHandler(void); +void TMR4_3_GCmpUL_IrqHandler(void); +void TMR4_3_GCmpVH_IrqHandler(void); +void TMR4_3_GCmpVL_IrqHandler(void); +void TMR4_3_GCmpWH_IrqHandler(void); +void TMR4_3_GCmpWL_IrqHandler(void); +void TMR4_3_GOvf_IrqHandler(void); +void TMR4_3_GUdf_IrqHandler(void); +void TMR4_3_ReloadU_IrqHandler(void); +void TMR4_3_ReloadV_IrqHandler(void); +void TMR4_3_ReloadW_IrqHandler(void); + +void EMB_GR0_IrqHandler(void); +void EMB_GR1_IrqHandler(void); +void EMB_GR2_IrqHandler(void); +void EMB_GR3_IrqHandler(void); + +void I2S1_Tx_IrqHandler(void); +void I2S1_Rx_IrqHandler(void); +void I2S1_Error_IrqHandler(void); +void I2S2_Tx_IrqHandler(void); +void I2S2_Rx_IrqHandler(void); +void I2S2_Error_IrqHandler(void); +void I2S3_Tx_IrqHandler(void); +void I2S3_Rx_IrqHandler(void); +void I2S3_Error_IrqHandler(void); +void I2S4_Tx_IrqHandler(void); +void I2S4_Rx_IrqHandler(void); +void I2S4_Error_IrqHandler(void); + +void I2C1_RxFull_IrqHandler(void); +void I2C1_TxComplete_IrqHandler(void); +void I2C1_TxEmpty_IrqHandler(void); +void I2C1_Error_IrqHandler(void); +void I2C2_RxFull_IrqHandler(void); +void I2C2_TxComplete_IrqHandler(void); +void I2C2_TxEmpty_IrqHandler(void); +void I2C2_Error_IrqHandler(void); +void I2C3_RxFull_IrqHandler(void); +void I2C3_TxComplete_IrqHandler(void); +void I2C3_TxEmpty_IrqHandler(void); +void I2C3_Error_IrqHandler(void); + +void PWC_LVD1_IrqHandler(void); +void PWC_LVD2_IrqHandler(void); + +void FCM_Error_IrqHandler(void); +void FCM_End_IrqHandler(void); +void FCM_Ovf_IrqHandler(void); + +void ADC1_SeqA_IrqHandler(void); +void ADC1_SeqB_IrqHandler(void); +void ADC1_ChCmp_IrqHandler(void); +void ADC1_SeqCmp_IrqHandler(void); +void ADC2_SeqA_IrqHandler(void); +void ADC2_SeqB_IrqHandler(void); +void ADC2_ChCmp_IrqHandler(void); +void ADC2_SeqCmp_IrqHandler(void); + +void SDIOC1_IrqHandler(void); +void SDIOC2_IrqHandler(void); + +void CAN_IrqHandler(void); + +/** + * @} + */ + +#endif /* LL_INTERRUPTS_SHARE_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_LL_INTERRUPTS_SHARE_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll.c new file mode 100644 index 0000000000..e8492b76c2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll.c @@ -0,0 +1,170 @@ +/** + ******************************************************************************* + * @file hc32_ll.c + * @brief This file provides firmware functions to low-level drivers (LL). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_Global Global + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup LL_Global_Functions LL Global Functions + * @{ + */ +void LL_PERIPH_WE(uint32_t u32Peripheral) +{ +#if (LL_EFM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_EFM) != 0UL) { + /* Unlock all EFM registers */ + EFM_REG_Unlock(); + } +#endif +#if (LL_FCG_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_FCG) != 0UL) { + /* Unlock FCG register */ + PWC_FCG0_REG_Unlock(); + } +#endif +#if (LL_GPIO_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_GPIO) != 0UL) { + /* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ + GPIO_REG_Unlock(); + } +#endif +#if (LL_MPU_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_MPU) != 0UL) { + /* Unlock all MPU registers */ + MPU_REG_Unlock(); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_LVD) != 0UL) { + /* Unlock LVD registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Unlock(PWC_UNLOCK_CODE2); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_PWC_CLK_RMU) != 0UL) { + /* Unlock PWC, CLK, RMU registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Unlock(PWC_UNLOCK_CODE0 | PWC_UNLOCK_CODE1); + } +#endif +#if (LL_SRAM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_SRAM) != 0UL) { + /* Unlock SRAM register: WTCR, CKCR */ + SRAM_REG_Unlock(); + } +#endif +} + +void LL_PERIPH_WP(uint32_t u32Peripheral) +{ +#if (LL_EFM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_EFM) != 0UL) { + /* Lock all EFM registers */ + EFM_REG_Lock(); + } +#endif +#if (LL_FCG_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_FCG) != 0UL) { + /* Lock FCG register */ + PWC_FCG0_REG_Lock(); + } +#endif +#if (LL_GPIO_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_GPIO) != 0UL) { + /* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ + GPIO_REG_Lock(); + } +#endif +#if (LL_MPU_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_MPU) != 0UL) { + /* Lock all MPU registers */ + MPU_REG_Lock(); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_LVD) != 0UL) { + /* Lock LVD registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Lock(PWC_UNLOCK_CODE2); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_PWC_CLK_RMU) != 0UL) { + /* Lock PWC, CLK, RMU registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Lock(PWC_UNLOCK_CODE0 | PWC_UNLOCK_CODE1); + } +#endif +#if (LL_SRAM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_SRAM) != 0UL) { + /* Lock SRAM register: WTCR, CKCR */ + SRAM_REG_Lock(); + } +#endif +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_adc.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_adc.c new file mode 100644 index 0000000000..9d9b0a84f5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_adc.c @@ -0,0 +1,1102 @@ +/** + ******************************************************************************* + * @file hc32_ll_adc.c + * @brief This file provides firmware functions to manage the Analog-to-Digital + * Converter(ADC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_adc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_ADC ADC + * @brief Analog-to-Digital Converter Driver Library + * @{ + */ + +#if (LL_ADC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ADC_Local_Macros ADC Local Macros + * @{ + */ +/** + * @defgroup ADC_PGA_En ADC PGA Function Control + * @{ + */ +#define ADC_PGA_DISABLE (0x0U) +#define ADC_PGA_ENABLE (0xEU) +/** + * @} + */ + +/** + * @defgroup ADC_Channel_Max ADC Channel Max + * @{ + */ +#define ADC1_CH_MAX (ADC_CH16) +#define ADC2_CH_MAX (ADC_CH8) +#define ADC1_REMAP_CH_MAX (ADC_CH15) +#define ADC2_REMAP_CH_MAX (ADC_CH7) +#define ADC1_REMAP_PIN_MAX (ADC1_PIN_PC5) +#define ADC2_REMAP_PIN_MAX (ADC2_PIN_PC1) +#define ADC_SSTR_NUM (16U) +#define ADC1_SSTR_NUM (ADC_SSTR_NUM) +#define ADC2_SSTR_NUM (9U) + +/** + * @} + */ + +/** + * @defgroup ADC_Check_Parameters_Validity ADC check parameters validity + * @{ + */ +#define IS_ADC_1BIT_MASK(x) (((x) != 0U) && (((x) & ((x) - 1U)) == 0U)) + +#define IS_ADC_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +/* ADC unit check */ +#define IS_ADC_UNIT(x) (((x) == CM_ADC1) || ((x) == CM_ADC2)) + +#define IS_ADC_SEQ(x) (((x) == ADC_SEQ_A) || ((x) == ADC_SEQ_B)) + +/* ADC channel check */ +#define IS_ADC_CH(adc, ch) \ +( (((adc) == CM_ADC1) && ((ch) <= ADC1_CH_MAX)) || \ + (((adc) == CM_ADC2) && ((ch) <= ADC2_CH_MAX))) + +#define IS_ADC_SCAN_MD(x) \ +( ((x) == ADC_MD_SEQA_SINGLESHOT) || \ + ((x) == ADC_MD_SEQA_CONT) || \ + ((x) == ADC_MD_SEQA_SEQB_SINGLESHOT) || \ + ((x) == ADC_MD_SEQA_CONT_SEQB_SINGLESHOT)) + +#define IS_ADC_RESOLUTION(x) \ +( ((x) == ADC_RESOLUTION_8BIT) || \ + ((x) == ADC_RESOLUTION_10BIT) || \ + ((x) == ADC_RESOLUTION_12BIT)) + +#define IS_ADC_HARDTRIG(x) \ +( ((x) == ADC_HARDTRIG_ADTRG_PIN) || \ + ((x) == ADC_HARDTRIG_EVT0) || \ + ((x) == ADC_HARDTRIG_EVT1) || \ + ((x) == ADC_HARDTRIG_EVT0_EVT1)) + +#define IS_ADC_DATAALIGN(x) \ +( ((x) == ADC_DATAALIGN_RIGHT) || \ + ((x) == ADC_DATAALIGN_LEFT)) + +#define IS_ADC_SEQA_RESUME_MD(x) \ +( ((x) == ADC_SEQA_RESUME_SCAN_CONT) || \ + ((x) == ADC_SEQA_RESUME_SCAN_RESTART)) + +#define IS_ADC_SAMPLE_TIME(x) ((x) >= 5U) + +#define IS_ADC_INT(x) IS_ADC_BIT_MASK(x, ADC_INT_ALL) + +#define IS_ADC_FLAG(x) IS_ADC_BIT_MASK(x, ADC_FLAG_ALL) + +/* Scan-average. */ +#define IS_ADC_AVG_CNT(x) (((x) | ADC_AVG_CNT256) == ADC_AVG_CNT256) + +/* Channel remap. */ +#define IS_ADC_REMAP_PIN(adc, pin) \ +( (((adc) == CM_ADC1) && ((pin) <= ADC1_REMAP_PIN_MAX)) || \ + (((adc) == CM_ADC2) && ((pin) <= ADC2_REMAP_PIN_MAX))) +#define IS_ADC_REMAP_CH(adc, ch) \ +( (((adc) == CM_ADC1) && ((ch) <= ADC1_REMAP_CH_MAX)) || \ + (((adc) == CM_ADC2) && ((ch) <= ADC2_REMAP_CH_MAX))) + +/* Sync mode. */ +#define IS_ADC_SYNC_MD(x) \ +( ((x) == ADC_SYNC_SINGLE_DELAY_TRIG) || \ + ((x) == ADC_SYNC_SINGLE_PARALLEL_TRIG) || \ + ((x) == ADC_SYNC_CYCLIC_DELAY_TRIG) || \ + ((x) == ADC_SYNC_CYCLIC_PARALLEL_TRIG)) + +#define IS_ADC_SYNC(x) ((x) == ADC_SYNC_ADC1_ADC2) + +/* Analog watchdog. */ +#define IS_ADC_AWD_MD(x) \ +( ((x) == ADC_AWD_MD_CMP_OUT) || \ + ((x) == ADC_AWD_MD_CMP_IN)) + +#define IS_ADC_AWD(x) ((x) == ADC_AWD0) + +/* AWD flag check */ +#define IS_ADC_AWD_FLAG(adc, flag) \ +( (((adc) == CM_ADC1) && IS_ADC_BIT_MASK(flag, ADC1_AWD_FLAG_ALL)) || \ + (((adc) == CM_ADC2) && IS_ADC_BIT_MASK(flag, ADC2_AWD_FLAG_ALL))) + +#define IS_ADC_AWD_INT(x) IS_ADC_BIT_MASK(x, ADC_AWD_INT_ALL) + +/* PGA */ +#define IS_ADC_PGA_GAIN(x) ((x) <= ADC_PGA_GAIN_32) + +#define IS_ADC_PGA_VSS(x) (((x) == ADC_PGA_VSS_PGAVSS) || ((x) == ADC_PGA_VSS_AVSS)) + +/* PGA unit */ +#define IS_ADC_PGA(adc, pga) (((adc) == CM_ADC1) && ((pga) == ADC_PGA1)) +#define IS_PGA_ADC(x) ((x) == CM_ADC1) +#define IS_ADC_PGA_INPUT_SRC(x) \ +( IS_ADC_BIT_MASK(x, ADC_PGAINSR0_PGAINSEL) && IS_ADC_1BIT_MASK(x)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Functions ADC Global Functions + * @{ + */ + +/** + * @brief Initializes the specified ADC peripheral according to the specified parameters + * in the structure pstcAdcInit. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] pstcAdcInit Pointer to a @ref stc_adc_init_t structure that contains the + * configuration information for the specified ADC. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcAdcInit == NULL. + */ +int32_t ADC_Init(CM_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcAdcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + if (pstcAdcInit != NULL) { + DDL_ASSERT(IS_ADC_SCAN_MD(pstcAdcInit->u16ScanMode)); + DDL_ASSERT(IS_ADC_RESOLUTION(pstcAdcInit->u16Resolution)); + DDL_ASSERT(IS_ADC_DATAALIGN(pstcAdcInit->u16DataAlign)); + + /* Configures scan mode, resolution, data align. */ + WRITE_REG16(ADCx->CR0, pstcAdcInit->u16ScanMode | \ + pstcAdcInit->u16Resolution | \ + pstcAdcInit->u16DataAlign); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Deinitializes the specified ADC peripheral registers to their default reset values. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval None + */ +void ADC_DeInit(CM_ADC_TypeDef *ADCx) +{ + /* SSTRx */ + uint8_t i; + __IO uint8_t *reg8SSTR; + uint8_t u8SSTRNum; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + /* Stop the ADC. */ + WRITE_REG8(ADCx->STR, 0U); + + /* Set the registers to reset value. */ + WRITE_REG16(ADCx->CR0, 0x0U); + WRITE_REG16(ADCx->CR1, 0x0U); + WRITE_REG16(ADCx->TRGSR, 0x0U); + WRITE_REG32(ADCx->CHSELRA, 0x0U); + WRITE_REG32(ADCx->CHSELRB, 0x0U); + WRITE_REG8(ADCx->ICR, 0x03U); + /* AVCHSELR */ + WRITE_REG32(ADCx->AVCHSELR, 0x0U); + + /* SSTRx */ + u8SSTRNum = (ADCx == CM_ADC1) ? ADC1_SSTR_NUM : ADC2_SSTR_NUM; + reg8SSTR = (__IO uint8_t *)((uint32_t)&ADCx->SSTR0); + for (i = 0U; i < u8SSTRNum; i++) { + reg8SSTR[i] = 0x0BU; + } + + /* SSTRL */ + if (ADCx == CM_ADC1) { + WRITE_REG8(ADCx->SSTRL, 0x0BU); + } + + /* CHMUXRx */ + WRITE_REG16(ADCx->CHMUXR0, 0x3210U); + WRITE_REG16(ADCx->CHMUXR1, 0x7654U); + if (ADCx == CM_ADC1) { + WRITE_REG16(ADCx->CHMUXR2, 0xBA98U); + WRITE_REG16(ADCx->CHMUXR3, 0xFEDCU); + } + + /* ISR clearing */ + WRITE_REG8(ADCx->ISR, 0x03U); + + /* Sync mode */ + WRITE_REG16(ADCx->SYNCCR, 0x0U); + + /* Analog watchdog */ + WRITE_REG16(ADCx->AWDCR, 0x0U); + WRITE_REG16(ADCx->AWDDR0, 0x0U); + WRITE_REG16(ADCx->AWDDR1, 0x0U); + WRITE_REG16(ADCx->AWDCHSR, 0x0U); + WRITE_REG16(ADCx->AWDSR, 0x0U); + + /* Sample hold */ + + /* PGA and OPA */ + if (ADCx == CM_ADC1) { + WRITE_REG16(ADCx->PGACR, 0x0U); + WRITE_REG16(ADCx->PGAGSR, 0x0U); + WRITE_REG16(ADCx->PGAINSR0, 0x0U); + WRITE_REG16(ADCx->PGAINSR1, 0x0U); + } +} + +/** + * @brief Set each @ref stc_adc_init_t field to default value. + * @param [in] pstcAdcInit Pointer to a @ref stc_adc_init_t structure + * whose fields will be set to default values. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcAdcInit == NULL. + */ +int32_t ADC_StructInit(stc_adc_init_t *pstcAdcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcAdcInit != NULL) { + pstcAdcInit->u16ScanMode = ADC_MD_SEQA_SINGLESHOT; + pstcAdcInit->u16Resolution = ADC_RESOLUTION_12BIT; + pstcAdcInit->u16DataAlign = ADC_DATAALIGN_RIGHT; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Enable or disable the specified ADC channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Seq The sequence whose channel specified by 'u8Ch' will be enabled or disabled. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: ADC sequence A. + * @arg ADC_SEQ_B: ADC sequence B. + * @param [in] u8Ch The ADC channel. + * This parameter can be values of @ref ADC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @note Sequence A and Sequence B CAN NOT include the same channel! + * @note Sequence A can always started by software(by calling @ref ADC_Start()), + * regardless of whether the hardware trigger source is valid or not. + * @note Sequence B must be specified a valid hard trigger by calling functions @ref ADC_TriggerConfig() + * and @ref ADC_TriggerCmd(). + */ +void ADC_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint8_t u8Ch, en_functional_state_t enNewState) +{ + uint32_t u32CHSELAddr; + + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32CHSELAddr = (uint32_t)&ADCx->CHSELRA + (u8Seq * 4UL); + if (enNewState == ENABLE) { + /* Enable the specified channel. */ + SET_REG32_BIT(RW_MEM32(u32CHSELAddr), 1UL << u8Ch); + } else { + /* Disable the specified channel. */ + CLR_REG32_BIT(RW_MEM32(u32CHSELAddr), 1UL << u8Ch); + } +} + +/** + * @brief Set sampling time for the specified channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch The channel to be set sampling time. + * This parameter can be values of @ref ADC_Channel + * @param [in] u8SampleTime Sampling time for the channel that specified by 'u8Ch'. + * @retval None + */ +void ADC_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8SampleTime) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_SAMPLE_TIME(u8SampleTime)); + + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + if (u8Ch < ADC_SSTR_NUM) { + u32Addr = (uint32_t)&ADCx->SSTR0 + u8Ch; + WRITE_REG8(RW_MEM8(u32Addr), u8SampleTime); + } else { + WRITE_REG8(ADCx->SSTRL, u8SampleTime); + } + +} + +/** + * @brief Set scan-average count. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16AverageCount Scan-average count. + * This parameter can be a value of @ref ADC_Average_Count + * @arg ADC_AVG_CNT2: 2 consecutive average conversions. + * @arg ADC_AVG_CNT4: 4 consecutive average conversions. + * @arg ADC_AVG_CNT8: 8 consecutive average conversions. + * @arg ADC_AVG_CNT16: 16 consecutive average conversions. + * @arg ADC_AVG_CNT32: 32 consecutive average conversions. + * @arg ADC_AVG_CNT64: 64 consecutive average conversions. + * @arg ADC_AVG_CNT128: 128 consecutive average conversions. + * @arg ADC_AVG_CNT256: 256 consecutive average conversions. + * @retval None + */ +void ADC_ConvDataAverageConfig(CM_ADC_TypeDef *ADCx, uint16_t u16AverageCount) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AVG_CNT(u16AverageCount)); + MODIFY_REG16(ADCx->CR0, ADC_CR0_AVCNT, u16AverageCount); +} + +/** + * @brief Enable or disable conversion data average calculation channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch The ADC channel. + * This parameter can be values of @ref ADC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_ConvDataAverageChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG32_BIT(ADCx->AVCHSELR, 1UL << u8Ch); + } else { + CLR_REG32_BIT(ADCx->AVCHSELR, 1UL << u8Ch); + } +} + +/** + * @brief Specifies the hard trigger for the specified ADC sequence. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADCx or CM_ADC + * @param [in] u8Seq The sequence to be configured. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: Sequence A. + * @arg ADC_SEQ_B: Sequence B. + * @param [in] u16TriggerSel Hard trigger selection. This parameter can be a value of @ref ADC_Hard_Trigger_Sel + * @arg ADC_HARDTRIG_ADTRG_PIN: Selects the following edge of pin ADTRG as the trigger of ADC sequence. + * @arg ADC_HARDTRIG_EVT0: Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_ITRGSELR0(x=(null), 1, 2, 3). + * @arg ADC_HARDTRIG_EVT1: Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_ITRGSELR1(x=(null), 1, 2, 3). + * @arg ADC_HARDTRIG_EVT0_EVT1: Selects two internal events as the trigger of ADC sequence. + The two events are specified by register ADCx_ITRGSELR0 and register ADCx_ITRGSELR1. + * @retval None + * @note ADC must be stopped while calling this function. + * @note The trigger source CANNOT be an event that generated by the sequence itself. + */ +void ADC_TriggerConfig(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint16_t u16TriggerSel) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_ADC_HARDTRIG(u16TriggerSel)); + + u8Seq *= ADC_TRGSR_TRGSELB_POS; + MODIFY_REG16(ADCx->TRGSR, \ + (uint32_t)ADC_TRGSR_TRGSELA << u8Seq, \ + (uint32_t)u16TriggerSel << u8Seq); +} + +/** + * @brief Enable or disable the hard trigger of the specified ADC sequence. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADCx or CM_ADC + * @param [in] u8Seq The sequence to be configured. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: Sequence A. + * @arg ADC_SEQ_B: Sequence B. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note ADC must be stopped while calling this function. + */ +void ADC_TriggerCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&ADCx->TRGSR; + /* Enable bit position: u8Seq * sequence_offset + enable_bit_base. */ + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, (uint32_t)u8Seq * ADC_TRGSR_TRGSELB_POS + ADC_TRGSR_TRGENA_POS), enNewState); +} + +/** + * @brief Enable or disable ADC interrupts. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8IntType ADC interrupt. + * This parameter can be values of @ref ADC_Int_Type + * @arg ADC_INT_EOCA: Interrupt of the end of conversion of sequence A. + * @arg ADC_INT_EOCB: Interrupt of the end of conversion of sequence B. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_IntCmd(CM_ADC_TypeDef *ADCx, uint8_t u8IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_INT(u8IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG8_BIT(ADCx->ICR, u8IntType); + } else { + CLR_REG8_BIT(ADCx->ICR, u8IntType); + } +} + +/** + * @brief Start sequence A conversion. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval None + */ +void ADC_Start(CM_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + WRITE_REG8(ADCx->STR, ADC_STR_STRT); +} + +/** + * @brief Stop ADC conversion, both sequence A and sequence B. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval None + */ +void ADC_Stop(CM_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + WRITE_REG8(ADCx->STR, 0U); +} + +/** + * @brief Get the ADC value of the specified channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch The ADC channel. + * This parameter can be values of @ref ADC_Channel + * @retval An uint16_t type value of ADC value. + */ +uint16_t ADC_GetValue(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + + return RW_MEM16((uint32_t)&ADCx->DR0 + u8Ch * 2UL); +} + +/** + * @brief Get the status of the specified ADC flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Flag ADC status flag. + * This parameter can be a value of @ref ADC_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ADC_GetStatus(const CM_ADC_TypeDef *ADCx, uint8_t u8Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_FLAG(u8Flag)); + + if (READ_REG8_BIT(ADCx->ISR, u8Flag) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified ADC flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Flag ADC status flag. + * This parameter can be valueS of @ref ADC_Status_Flag + * @retval None + */ +void ADC_ClearStatus(CM_ADC_TypeDef *ADCx, uint8_t u8Flag) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_FLAG(u8Flag)); + + CLR_REG8_BIT(ADCx->ISR, u8Flag); +} + +/** + * @brief Remap the correspondence between ADC channel and analog input pins. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch This parameter can be values of @ref ADC_Channel + * @param [in] u8AdcPin This parameter can be a value of @ref ADC_Remap_Pin + * @retval None + */ +void ADC_ChRemap(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8AdcPin) +{ + uint8_t u8FieldOfs; + uint8_t u8RegIdx; + __IO uint16_t *regCHMUXR; + + DDL_ASSERT(IS_ADC_REMAP_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_ADC_REMAP_PIN(ADCx, u8AdcPin)); + + regCHMUXR = (__IO uint16_t *)((uint32_t)&ADCx->CHMUXR0); + u8RegIdx = u8Ch / 4U; + u8FieldOfs = (u8Ch % 4U) * 4U; + MODIFY_REG16(regCHMUXR[u8RegIdx], \ + ((uint32_t)ADC_CHMUXR0_CH00MUX << u8FieldOfs), \ + ((uint32_t)u8AdcPin << u8FieldOfs)); +} + +/** + * @brief Get the ADC pin corresponding to the specified ADC channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch ADC channel. + * This parameter can be one of the following values of @ref ADC_Channel + * @retval An uint8_t type value of ADC pin. @ref ADC_Remap_Pin + */ +uint8_t ADC_GetChPin(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch) +{ + uint8_t u8RetPin; + uint8_t u8FieldOfs; + uint8_t u8RegIdx; + __IO uint16_t *regCHMUXR; + + DDL_ASSERT(IS_ADC_REMAP_CH(ADCx, u8Ch)); + + regCHMUXR = (__IO uint16_t *)((uint32_t)&ADCx->CHMUXR0); + u8RegIdx = u8Ch / 4U; + u8FieldOfs = (u8Ch % 4U) * 4U; + u8RetPin = ((uint8_t)(regCHMUXR[u8RegIdx] >> u8FieldOfs)) & 0xFU; + + return u8RetPin; +} + +/** + * @brief Reset channel-pin mapping. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval None + */ +void ADC_ResetChMapping(CM_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + WRITE_REG16(ADCx->CHMUXR0, 0x3210U); + WRITE_REG16(ADCx->CHMUXR1, 0x7654U); + if (ADCx == CM_ADC1) { + WRITE_REG16(ADCx->CHMUXR2, 0xBA98U); + WRITE_REG16(ADCx->CHMUXR3, 0xFEDCU); + } +} + +/** + * @brief Configures synchronous mode. + * @param [in] u16SyncUnit Specify the ADC units which work synchronously. + * This parameter can be a value of @ref ADC_Sync_Unit + * @param [in] u16SyncMode Synchronous mode. + * This parameter can be a value of @ref ADC_Sync_Mode + * @arg ADC_SYNC_SINGLE_DELAY_TRIG: Single shot delayed trigger mode. + * When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + * All ADCs scan once. + * @arg ADC_SYNC_SINGLE_PARALLEL_TRIG: Single shot parallel trigger mode. + * When the trigger condition occurs, all ADCs start at the same time. + * All ADCs scan once. + * @arg ADC_SYNC_CYCLIC_DELAY_TRIG: Cyclic delayed trigger mode. + * When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + * All ADCs scan cyclicly(keep scaning till you stop them). + * @arg ADC_SYNC_CYCLIC_PARALLEL_TRIG: Single shot parallel trigger mode. + * When the trigger condition occurs, all ADCs start at the same time. + * All ADCs scan cyclicly(keep scaning till you stop them). + * @param [in] u8TriggerDelay Trigger delay time(ADCLK cycle), range is [1, 255]. + * @retval None + */ +void ADC_SyncModeConfig(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TriggerDelay) +{ + DDL_ASSERT(IS_ADC_SYNC(u16SyncUnit)); + DDL_ASSERT(IS_ADC_SYNC_MD(u16SyncMode)); + + u16SyncMode |= ((uint16_t)((uint32_t)u8TriggerDelay << ADC_SYNCCR_SYNCDLY_POS)) | u16SyncUnit; + MODIFY_REG16(CM_ADC1->SYNCCR, ADC_SYNCCR_SYNCMD | ADC_SYNCCR_SYNCDLY, u16SyncMode); +} + +/** + * @brief Enable or disable synchronous mode. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_SyncModeCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_ADC1->SYNCCR_b.SYNCEN, enNewState); +} + +/** + * @brief Configures analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u8Ch The channel that to be used as an analog watchdog channel. + * This parameter can be a value of @ref ADC_Channel + * @param [in] pstcAwd Pointer to a @ref stc_adc_awd_config_t structure value that + * contains the configuration information of the AWD. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcAwd == NULL. + */ +int32_t ADC_AWD_Config(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch, const stc_adc_awd_config_t *pstcAwd) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + + if (pstcAwd != NULL) { + DDL_ASSERT(IS_ADC_AWD_MD(pstcAwd->u16WatchdogMode)); + + (void)(u8AwdUnit); + MODIFY_REG16(ADCx->AWDCR, ADC_AWDCR_AWDMD, pstcAwd->u16WatchdogMode << ADC_AWDCR_AWDMD_POS); + WRITE_REG16(ADCx->AWDDR0, pstcAwd->u16LowThreshold); + WRITE_REG16(ADCx->AWDDR1, pstcAwd->u16HighThreshold); + SET_REG32_BIT(ADCx->AWDCHSR, 1UL << u8Ch); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Specifies the comapre mode of analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u16WatchdogMode Analog watchdog comapre mode. + * This parameter can be a value of @ref ADC_AWD_Mode + * @arg ADC_AWD_MD_CMP_OUT: ADCValue > HighThreshold or ADCValue < LowThreshold + * @arg ADC_AWD_MD_CMP_IN: LowThreshold < ADCValue < HighThreshold + * @retval None + */ +void ADC_AWD_SetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16WatchdogMode) +{ + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + DDL_ASSERT(IS_ADC_AWD_MD(u16WatchdogMode)); + + (void)(u8AwdUnit); + MODIFY_REG16(ADCx->AWDCR, ADC_AWDCR_AWDMD, u16WatchdogMode << ADC_AWDCR_AWDMD_POS); + +} + +/** + * @brief Get the comapre mode of analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @retval Analog watchdog compare mode. A value of @ref ADC_AWD_Mode + * - ADC_AWD_MD_CMP_OUT: ADCValue > HighThreshold or ADCValue < LowThreshold + * - ADC_AWD_MD_CMP_IN: LowThreshold < ADCValue < HighThreshold + */ +uint16_t ADC_AWD_GetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit) +{ + uint16_t u16RetMode; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + + (void)(u8AwdUnit); + u16RetMode = READ_REG16_BIT(ADCx->AWDCR, ADC_AWDCR_AWDMD) >> ADC_AWDCR_AWDMD_POS; + + return u16RetMode; +} + +/** + * @brief Specifies the low threshold and high threshold of analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u16LowThreshold Low threshold of analog watchdog. + * @param [in] u16HighThreshold High threshold of analog watchdog. + * @retval None + */ +void ADC_AWD_SetThreshold(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16LowThreshold, uint16_t u16HighThreshold) +{ + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + + (void)(u8AwdUnit); + WRITE_REG16(ADCx->AWDDR0, u16LowThreshold); + WRITE_REG16(ADCx->AWDDR1, u16HighThreshold); + +} + +/** + * @brief Select the specified ADC channel as an analog watchdog channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u8Ch The channel that to be used as an analog watchdog channel. + * This parameter can be a value of @ref ADC_Channel + * @retval None + */ +void ADC_AWD_SelectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch) +{ + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + (void)(u8AwdUnit); + SET_REG32_BIT(ADCx->AWDCHSR, 1UL << u8Ch); + +} + +/** + * @brief Deselects the specified ADC channel as an AWD channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u8Ch ADC channel. + * This parameter can be a value of @ref ADC_Channel + * @retval None + */ +void ADC_AWD_DeselectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch) +{ + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + (void)(u8AwdUnit); + CLR_REG32_BIT(ADCx->AWDCHSR, 1UL << u8Ch); +} + +/** + * @brief Enable or disable the specified analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be enabled or disabled. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_AWD_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&ADCx->AWDCR; + (void)(u8AwdUnit); + /* Enable bit position: ADC_AWDCR_AWDEN_POS */ + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, ADC_AWDCR_AWDEN_POS), enNewState); + +} + +/** + * @brief Enable or disable the specified analog watchdog interrupts. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16IntType Interrupt of AWD. + * This parameter can be a value of @ref ADC_AWD_Int_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_AWD_IntCmd(CM_ADC_TypeDef *ADCx, uint16_t u16IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD_INT(u16IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + static uint16_t u16AWDIntSeq = 0U; + if (enNewState == ENABLE) { + SET_REG16_BIT(ADCx->AWDCR, u16IntType | ADC_AWDCR_AWDIEN); + u16AWDIntSeq |= u16IntType; + } else { + u16AWDIntSeq &= ~u16IntType; + CLR_REG16_BIT(ADCx->AWDCR, u16IntType); + if (u16AWDIntSeq == 0U) { + CLR_REG16_BIT(ADCx->AWDCR, ADC_AWDCR_AWDIEN); + } + } + +} + +/** + * @brief Get the status of the specified analog watchdog flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u32Flag AWD status flag. + * This parameter can be values of @ref ADC_AWD_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ADC_AWD_GetStatus(const CM_ADC_TypeDef *ADCx, uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_ADC_AWD_FLAG(ADCx, u32Flag)); + if (READ_REG32_BIT(ADCx->AWDSR, u32Flag) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified analog watchdog flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u32Flag AWD status flag. + * This parameter can be values of @ref ADC_AWD_Status_Flag + * @retval None + */ +void ADC_AWD_ClearStatus(CM_ADC_TypeDef *ADCx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_ADC_AWD_FLAG(ADCx, u32Flag)); + CLR_REG32_BIT(ADCx->AWDSR, u32Flag); + +} + +/** + * @brief Configures the specified programmable gain amplifier. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8PgaUnit The PGA unit. + * This parameter can be a value of @ref ADC_PGA_Unit + * @param [in] u8Gain Gain of the specified PGA. + * This parameter can be a value of @ref ADC_PGA_Gain + * @arg ADC_PGA_GAIN_2: PGA gain factor is 2. + * @arg ADC_PGA_GAIN_2P133: PGA gain factor is 2.133. + * @arg ADC_PGA_GAIN_2P286: PGA gain factor is 2.286. + * @arg ADC_PGA_GAIN_2P667: PGA gain factor is 2.667. + * @arg ADC_PGA_GAIN_2P909: PGA gain factor is 2.909. + * @arg ADC_PGA_GAIN_3P2: PGA gain factor is 3.2. + * @arg ADC_PGA_GAIN_3P556: PGA gain factor is 2.556. + * @arg ADC_PGA_GAIN_4: PGA gain factor is 4. + * @arg ADC_PGA_GAIN_4P571: PGA gain factor is 4.571. + * @arg ADC_PGA_GAIN_5P333: PGA gain factor is 5.333. + * @arg ADC_PGA_GAIN_6P4: PGA gain factor is 6.4. + * @arg ADC_PGA_GAIN_8: PGA gain factor is 8. + * @arg ADC_PGA_GAIN_10P667: PGA gain factor is 10.667. + * @arg ADC_PGA_GAIN_16: PGA gain factor is 16. + * @arg ADC_PGA_GAIN_32: PGA gain factor is 32. + * @param [in] u8PgaVss VSS for the specified PGA. + * This parameter can be a value of @ref ADC_PGA_VSS + * @arg ADC_PGA_VSS_PGAVSS: Use pin PGAx_VSS as the reference GND of PGAx + * @arg ADC_PGA_VSS_AVSS: Use AVSS as the reference GND of PGAx. + * @retval None + */ +void ADC_PGA_Config(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, uint8_t u8Gain, uint8_t u8PgaVss) +{ + DDL_ASSERT(IS_ADC_PGA(ADCx, u8PgaUnit)); + DDL_ASSERT(IS_ADC_PGA_GAIN(u8Gain)); + DDL_ASSERT(IS_ADC_PGA_VSS(u8PgaVss)); + + (void)(u8PgaUnit); + WRITE_REG16(ADCx->PGAGSR, u8Gain); + WRITE_REG16(ADCx->PGAINSR1, u8PgaVss); + +} + +/** + * @brief Enable the specified programmable gain amplifier. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8PgaUnit The PGA unit. + * This parameter can be a value of @ref ADC_PGA_Unit + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_PGA_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, en_functional_state_t enNewState) +{ + const uint8_t au8Cmd[] = {ADC_PGA_DISABLE, ADC_PGA_ENABLE}; + + DDL_ASSERT(IS_ADC_PGA(ADCx, u8PgaUnit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + (void)(u8PgaUnit); + WRITE_REG16(ADCx->PGACR, au8Cmd[(uint8_t)enNewState]); + +} + +/** + * @brief Selects PGA input source. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC1 + * @param [in] u16PgaInputSrc PGA input source. + * This parameter can be a value of @ref ADC_PGA_Input_Src + * @retval None + */ +void ADC_PGA_SelectInputSrc(CM_ADC_TypeDef *ADCx, uint16_t u16PgaInputSrc) +{ + DDL_ASSERT(IS_PGA_ADC(ADCx)); + DDL_ASSERT(IS_ADC_PGA_INPUT_SRC(u16PgaInputSrc)); + WRITE_REG16(ADCx->PGAINSR0, u16PgaInputSrc); +} + +/** + * @brief Deselects PGA input source. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC1 + * @retval None + */ +void ADC_PGA_DeselectInputSrc(CM_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_PGA_ADC(ADCx)); + WRITE_REG16(ADCx->PGAINSR0, 0U); +} + +/** + * @brief Enable or disable automatically clear data register. + * The automatic clearing function is mainly used to detect whether the data register is updated. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_DataRegAutoClearCmd(CM_ADC_TypeDef *ADCx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(ADCx->CR0, ADC_CR0_CLREN); + } else { + CLR_REG16_BIT(ADCx->CR0, ADC_CR0_CLREN); + } +} + +/** + * @brief Sequence A restart channel selection. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16SeqAResumeMode Sequence A resume mode. + * This parameter can be a value of @ref ADC_SeqA_Resume_Mode + * @arg ADC_SEQA_RESUME_SCAN_CONT: Scanning will continue from the interrupted channel. + * @arg ADC_SEQA_RESUME_SCAN_RESTART: Scanning will start from the first channel. + * @retval None + */ +void ADC_SetSeqAResumeMode(CM_ADC_TypeDef *ADCx, uint16_t u16SeqAResumeMode) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQA_RESUME_MD(u16SeqAResumeMode)); + WRITE_REG16(ADCx->CR1, u16SeqAResumeMode); +} + +/** + * @} + */ + +#endif /* LL_ADC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_aes.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_aes.c new file mode 100644 index 0000000000..5cb70f7b0c --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_aes.c @@ -0,0 +1,271 @@ +/** + ******************************************************************************* + * @file hc32_ll_aes.c + * @brief This file provides firmware functions to manage the Advanced Encryption + * Standard(AES). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_aes.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_AES AES + * @brief AES Driver Library + * @{ + */ + +#if (LL_AES_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AES_Local_Macros AES Local Macros + * @{ + */ +/* Delay count for timeout */ +#define AES_TIMEOUT (30000UL) + +/* AES block size */ +#define AES_BLOCK_SIZE (16U) + +/** + * @defgroup AES_Check_Parameters_Validity AES Check Parameters Validity + * @{ + */ +#define IS_AES_KEY_SIZE(x) ((x) == AES_KEY_SIZE_16BYTE) + +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup AES_Local_Functions AES Local Functions + * @{ + */ +/** + * @brief Write the input buffer in data register. + * @param [in] pu8SrcData Point to the source data buffer. + * @retval None + */ +static void AES_WriteData(const uint8_t *pu8SrcData) +{ + uint8_t i; + __IO uint32_t *regDR = &CM_AES->DR0; + const uint32_t *pu32Data = (const uint32_t *)((uint32_t)pu8SrcData); + + for (i = 0U; i < 4U; i++) { + regDR[i] = pu32Data[i]; + } +} + +/** + * @brief Read the from data register. + * @param [out] pu8Result Point to the result buffer. + * @retval None + */ +static void AES_ReadData(uint8_t *pu8Result) +{ + uint8_t i; + __IO uint32_t *regDR = &CM_AES->DR0; + uint32_t *pu32Result = (uint32_t *)((uint32_t)pu8Result); + + for (i = 0U; i < 4U; i++) { + pu32Result[i] = regDR[i]; + } +} + +/** + * @brief Write the input buffer in key register. + * @param [in] pu8Key Pointer to the key buffer. + * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size + * @retval None + */ +static void AES_WriteKey(const uint8_t *pu8Key, uint8_t u8KeySize) +{ + uint8_t i; + uint8_t u8KeyWordSize = u8KeySize / 4U; + __IO uint32_t *regKR = &CM_AES->KR0; + const uint32_t *pu32Key = (const uint32_t *)((uint32_t)pu8Key); + + for (i = 0U; i < u8KeyWordSize; i++) { + regKR[i] = pu32Key[i]; + } +} + +/** + * @brief Wait AES operation done. + * @param None + * @retval None + */ +static int32_t AES_WaitDone(void) +{ + __IO uint32_t u32TimeCount = 0UL; + int32_t i32Ret = LL_OK; + + while (bCM_AES->CR_b.START != 0UL) { + if (u32TimeCount++ >= AES_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} +/** + * @} + */ + +/** + * @defgroup AES_Global_Functions AES Global Functions + * @{ + */ + +/** + * @brief AES encryption. + * @param [in] pu8Plaintext Buffer of the plaintext(the source data which will be encrypted). + * @param [in] u32PlaintextSize Length of plaintext in bytes. + * @param [in] pu8Key Pointer to the AES key. + * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size + * @param [out] pu8Ciphertext Buffer of the ciphertext. + * @retval int32_t: + * - LL_OK: Encrypt successfully. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_TIMEOUT: Encrypt timeout. + */ +int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Ciphertext) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32Index = 0UL; + + DDL_ASSERT(IS_AES_KEY_SIZE(u8KeySize)); + DDL_ASSERT((u32PlaintextSize % AES_BLOCK_SIZE) == 0U); + + if ((pu8Plaintext != NULL) && (u32PlaintextSize > 0UL) && \ + (pu8Key != NULL) && (pu8Ciphertext != NULL)) { + AES_WriteKey(pu8Key, u8KeySize); + /* Set AES encrypt. */ + WRITE_REG32(bCM_AES->CR_b.MODE, 0UL); + while (u32Index < u32PlaintextSize) { + AES_WriteData(&pu8Plaintext[u32Index]); + /* Start AES calculating. */ + WRITE_REG32(bCM_AES->CR_b.START, 1UL); + /* Wait for AES to stop */ + i32Ret = AES_WaitDone(); + if (i32Ret != LL_OK) { + break; + } + AES_ReadData(&pu8Ciphertext[u32Index]); + u32Index += AES_BLOCK_SIZE; + } + } + + return i32Ret; +} + +/** + * @brief AES decryption. + * @param [in] pu8Ciphertext Buffer of the Ciphertext(the source data which will be decrypted). + * @param [in] u32CiphertextSize Length of ciphertext in bytes. + * @param [in] pu8Key Pointer to the AES key. + * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size + * @param [out] pu8Plaintext Buffer of the plaintext. + * @retval int32_t: + * - LL_OK: Decrypt successfully. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_TIMEOUT: Decrypt timeout. + */ +int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Plaintext) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32Index = 0UL; + + DDL_ASSERT(IS_AES_KEY_SIZE(u8KeySize)); + DDL_ASSERT((u32CiphertextSize % AES_BLOCK_SIZE) == 0U); + + if ((pu8Plaintext != NULL) && (u32CiphertextSize > 0UL) && \ + (pu8Key != NULL) && (pu8Ciphertext != NULL)) { + AES_WriteKey(pu8Key, u8KeySize); + /* Set AES decrypt. */ + WRITE_REG32(bCM_AES->CR_b.MODE, 1UL); + while (u32Index < u32CiphertextSize) { + AES_WriteData(&pu8Ciphertext[u32Index]); + /* Start AES calculating. */ + WRITE_REG32(bCM_AES->CR_b.START, 1UL); + /* Wait for AES to stop */ + i32Ret = AES_WaitDone(); + if (i32Ret != LL_OK) { + break; + } + AES_ReadData(&pu8Plaintext[u32Index]); + u32Index += AES_BLOCK_SIZE; + } + } + + return i32Ret; +} +/** + * @} + */ + +#endif /* LL_AES_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_aos.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_aos.c new file mode 100644 index 0000000000..26e3f81a2d --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_aos.c @@ -0,0 +1,177 @@ +/** + ******************************************************************************* + * @file hc32_ll_aos.c + * @brief This file provides firmware functions to manage the AOS. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_aos.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_AOS AOS + * @brief AOS Driver Library + * @{ + */ + +#if (LL_AOS_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AOS_Local_Macros AOS Local Macros + * @{ + */ + +/** + * @defgroup AOS_Common_Trigger_ID_Validity AOS Common Trigger ID Validity + * @{ + */ +#define IS_AOS_COMM_TRIG(x) \ +( ((x) != 0UL) && \ + ((x) | AOS_COMM_TRIG_MASK) == AOS_COMM_TRIG_MASK) + +/** + * @} + */ + +/** + * @defgroup AOS_Trigger_Select_Validity AOS Trigger Select Validity + * @{ + */ +#define IS_AOS_TRIG_SEL(x) \ +( ((x) == AOS_DCU1) || \ + ((x) == AOS_DCU2) || \ + ((x) == AOS_DCU3) || \ + ((x) == AOS_DCU4) || \ + ((x) == AOS_DMA1_0) || \ + ((x) == AOS_DMA1_1) || \ + ((x) == AOS_DMA1_2) || \ + ((x) == AOS_DMA1_3) || \ + ((x) == AOS_DMA2_0) || \ + ((x) == AOS_DMA2_1) || \ + ((x) == AOS_DMA2_2) || \ + ((x) == AOS_DMA2_3) || \ + ((x) == AOS_DMA_RC) || \ + ((x) == AOS_TMR6_0) || \ + ((x) == AOS_TMR6_1) || \ + ((x) == AOS_TMR0) || \ + ((x) == AOS_EVTPORT12) || \ + ((x) == AOS_EVTPORT34) || \ + ((x) == AOS_TMRA_0) || \ + ((x) == AOS_TMRA_1) || \ + ((x) == AOS_OTS) || \ + ((x) == AOS_ADC1_0) || \ + ((x) == AOS_ADC1_1) || \ + ((x) == AOS_ADC2_0) || \ + ((x) == AOS_ADC2_1) || \ + ((x) == AOS_COMM_1) || \ + ((x) == AOS_COMM_2)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup AOS_Global_Functions AOS Global Functions + * @{ + */ + +/** + * @brief Event Port Hardware trigger common event function command + * @param [in] u32TriggerSel AOS trigger select, @ref AOS_Trigger_Select in details + * @param [in] u32CommonTrigger Common trigger ID + * This parameter can be one of the following values: + * @arg AOS_COMM_TRIG1: Common trigger 1. + * @arg AOS_COMM_TRIG2: Common trigger 2. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void AOS_CommonTriggerCmd(uint32_t u32TriggerSel, uint32_t u32CommonTrigger, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_AOS_TRIG_SEL(u32TriggerSel)); + DDL_ASSERT(IS_AOS_COMM_TRIG(u32CommonTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(*(__IO uint32_t *)u32TriggerSel, u32CommonTrigger); + } else { + CLR_REG32_BIT(*(__IO uint32_t *)u32TriggerSel, u32CommonTrigger); + } +} + +/** + * @brief Event Port Hardware trigger common event function command + * @param [in] u32TriggerSel AOS trigger select, @ref AOS_Trigger_Select in details + * @param [in] enEvent Event source configuration, @ref en_event_src_t in details + * @retval None + */ +void AOS_SetTriggerEventSrc(uint32_t u32TriggerSel, en_event_src_t enEvent) +{ + DDL_ASSERT(IS_AOS_TRIG_SEL(u32TriggerSel)); + + MODIFY_REG32(*(__IO uint32_t *)u32TriggerSel, AOS_TRIG_SEL_MASK, enEvent); +} + +/** + * @} + */ + +#endif /* LL_AOS_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_can.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_can.c new file mode 100644 index 0000000000..a4b12bcb9e --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_can.c @@ -0,0 +1,1357 @@ +/** + ******************************************************************************* + * @file hc32_ll_can.c + * @brief This file provides firmware functions to manage the CAN. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_can.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CAN CAN + * @brief CAN Driver Library + * @{ + */ + +#if (LL_CAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CAN_Local_Macros CAN Local Macros + * @{ + */ + +/** + * @defgroup CAN_Check_Parameters_Validity CAN Check Parameters Validity + * @{ + */ +#define IS_CAN_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +#define IS_CAN_FUNC_EN(x, en) (((x) == 0U) || ((x) == (en))) + +/* CAN unit */ +#define IS_CAN_UNIT(x) ((x) == CM_CAN) + +#define IS_CAN_BIT_TIME_PRESC(x) (((x) >= 1U) && ((x) <= 256U)) + +#define IS_CAN_WORK_MD(x) ((x) <= CAN_WORK_MD_ELB_SILENT) + +#define IS_CAN_TX_BUF_TYPE(x) (((x) == CAN_TX_BUF_PTB) || ((x) == CAN_TX_BUF_STB)) + +#define IS_CAN_PTB_SINGLESHOT_TX(x) IS_CAN_FUNC_EN(x, CAN_PTB_SINGLESHOT_TX_ENABLE) + +#define IS_CAN_STB_SINGLESHOT_TX(x) IS_CAN_FUNC_EN(x, CAN_STB_SINGLESHOT_TX_ENABLE) + +#define IS_CAN_STB_PRIO_MD(x) IS_CAN_FUNC_EN(x, CAN_STB_PRIO_MD_ENABLE) + +#define IS_CAN_TX_REQ(x) IS_CAN_BIT_MASK(x, CAN_TX_REQ_STB_ONE|CAN_TX_REQ_STB_ALL|CAN_TX_REQ_PTB) + +#define IS_CAN_RX_ALL_FRAME(x) IS_CAN_FUNC_EN(x, CAN_RX_ALL_FRAME_ENABLE) + +#define IS_CAN_RX_OVF_MD(x) (((x) == CAN_RX_OVF_SAVE_NEW) || ((x) == CAN_RX_OVF_DISCARD_NEW)) + +#define IS_CAN_SELF_ACK(x) IS_CAN_FUNC_EN(x, CAN_SELF_ACK_ENABLE) + +#define IS_CAN_INT(x) IS_CAN_BIT_MASK(x, CAN_INT_ALL) + +#define IS_CAN_FLAG(x) IS_CAN_BIT_MASK(x, CAN_FLAG_ALL) + +#define IS_CAN_ID(ide, x) \ +( (((ide) == 1U) && (((x) | 0x1FFFFFFFUL) == 0x1FFFFFFFUL)) || \ + (((ide) == 0U) && (((x) | 0x7FFUL) == 0x7FFUL))) + +#define IS_CAN_ID_MASK(x) (((x) | 0x1FFFFFFFUL) == 0x1FFFFFFFUL) + +#define IS_CAN_IDE(x) (((x) == 0U) || ((x) == 1U)) + +#define IS_CAN_FILTER(x) IS_CAN_BIT_MASK(x, CAN_FILTER_ALL) + +#define IS_CAN_RX_WARN(x) (((x) >= CAN_RX_WARN_MIN) && ((x) <= CAN_RX_WARN_MAX)) + +#define IS_CAN_ERR_WARN(x) ((x) < 16U) + +#define IS_TTCAN_TX_BUF_MD(x) (((x) == CAN_TTC_TX_BUF_MD_CAN) || ((x) == CAN_TTC_TX_BUF_MD_TTCAN)) + +#define IS_TTCAN_TX_BUF_SEL(x) ((x) <= CAN_TTC_TX_BUF_STB4) + +#define IS_TTCAN_INT(x) IS_CAN_BIT_MASK(x, CAN_TTC_INT_ALL) + +#define IS_TTCAN_FLAG(x) IS_CAN_BIT_MASK(x, CAN_TTC_FLAG_ALL) + +#define IS_TTCAN_TX_EN_WINDOW(x) (((x) > 0U) && ((x) <= 16U)) + +#define IS_TTCAN_NTU_PRESCALER(x) \ +( ((x) == CAN_TTC_NTU_PRESCALER1) || \ + ((x) == CAN_TTC_NTU_PRESCALER2) || \ + ((x) == CAN_TTC_NTU_PRESCALER4) || \ + ((x) == CAN_TTC_NTU_PRESCALER8)) + +#define IS_TTCAN_TRIG_TYPE(x) \ +( ((x) == CAN_TTC_TRIG_IMMED_TRIG) || \ + ((x) == CAN_TTC_TRIG_TIME_TRIG) || \ + ((x) == CAN_TTC_TRIG_SINGLESHOT_TX_TRIG) || \ + ((x) == CAN_TTC_TRIG_TX_START_TRIG) || \ + ((x) == CAN_TTC_TRIG_TX_STOP_TRIG)) + +#define IS_CAN_ID_TYPE(x) \ +( ((x) == CAN_ID_STD_EXT) || \ + ((x) == CAN_ID_STD) || \ + ((x) == CAN_ID_EXT)) + +#define IS_CAN_SBT(seg1, seg2, sjw) \ +( (((seg1) >= 2U) && ((seg1) <= 65U)) && \ + (((seg2) >= 1U) && ((seg2) <= 8U)) && \ + (((sjw) >= 1U) && ((sjw) <= 8U)) && \ + ((seg1) >= ((seg2) + 1U)) && \ + ((seg2) >= (sjw))) + +/* CAN Data Length Code(DLC) */ +#define IS_CAN20_DLC(fdf, dlc) (((fdf) == 0U) && ((dlc) <= CAN_DLC8)) + +/** + * @} + */ + +/** + * @defgroup CAN_Miscellaneous_Macros CAN Miscellaneous Macros + * @{ + */ +/* CAN buffer number */ +#define CAN_RX_BUF_NUM (10U) + +#define CAN_RX_WARN_MIN (1U) +#define CAN_RX_WARN_MAX (CAN_RX_BUF_NUM) + +#define CAN_ERRINT_FLAG_MASK (CAN_ERRINT_BEIF | CAN_ERRINT_ALIF | CAN_ERRINT_EPIF) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup CAN_Local_Variables CAN Local Variables + * @{ + */ +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CAN_Local_Functions CAN Local Functions + * @{ + */ + +#if defined __DEBUG +/** + * @brief Initialization parameter check. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcCanInit Pointer to a stc_can_init_t structure value that + * contains the configuration information for the CAN. + * @retval None + */ +static void CAN_InitParameterCheck(CM_CAN_TypeDef *CANx, const stc_can_init_t *pstcCanInit) +{ + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_WORK_MD(pstcCanInit->u8WorkMode)); + DDL_ASSERT(IS_CAN_PTB_SINGLESHOT_TX(pstcCanInit->u8PTBSingleShotTx)); + DDL_ASSERT(IS_CAN_STB_SINGLESHOT_TX(pstcCanInit->u8STBSingleShotTx)); + DDL_ASSERT(IS_CAN_STB_PRIO_MD(pstcCanInit->u8STBPrioMode)); + DDL_ASSERT(IS_CAN_RX_WARN(pstcCanInit->u8RxWarnLimit)); + DDL_ASSERT(IS_CAN_ERR_WARN(pstcCanInit->u8ErrorWarnLimit)); + DDL_ASSERT(IS_CAN_FILTER(pstcCanInit->u16FilterSelect)); + DDL_ASSERT(IS_CAN_RX_ALL_FRAME(pstcCanInit->u8RxAllFrame)); + DDL_ASSERT(IS_CAN_RX_OVF_MD(pstcCanInit->u8RxOvfMode)); + DDL_ASSERT(IS_CAN_SELF_ACK(pstcCanInit->u8SelfAck)); + + DDL_ASSERT(IS_CAN_BIT_TIME_PRESC(pstcCanInit->stcBitCfg.u32Prescaler)); + DDL_ASSERT(IS_CAN_SBT(pstcCanInit->stcBitCfg.u32TimeSeg1, + pstcCanInit->stcBitCfg.u32TimeSeg2, + pstcCanInit->stcBitCfg.u32SJW)); +} +#endif + +/** + * @brief Specifies work mode for the specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8WorkMode Work mode of CAN. + * This parameter can be a value of @ref CAN_Work_Mode + * @arg CAN_WORK_MD_NORMAL: Normal work mode. + * @arg CAN_WORK_MD_SILENT: Silent work mode. Prohibit data transmission. + * @arg CAN_WORK_MD_ILB: Internal loop back mode, just for self-test while developing. + * @arg CAN_WORK_MD_ELB: External loop back mode, just for self-test while developing. + * @arg CAN_WORK_MD_ELB_SILENT: External lopp back silent mode, just for self-test while developing. + * It is forbidden to respond to received frames and error frames, + * but data can be transmitted. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +static void CAN_SetWorkMode(CM_CAN_TypeDef *CANx, uint8_t u8WorkMode) +{ + uint8_t u8CFGSTAT = 0U; + uint8_t u8TCMD = 0U; + + switch (u8WorkMode) { + case CAN_WORK_MD_SILENT: + u8TCMD = CAN_TCMD_LOM; + break; + case CAN_WORK_MD_ILB: + u8CFGSTAT = CAN_CFG_STAT_LBMI; + break; + case CAN_WORK_MD_ELB: + u8CFGSTAT = CAN_CFG_STAT_LBME; + break; + case CAN_WORK_MD_ELB_SILENT: + u8TCMD = CAN_TCMD_LOM; + u8CFGSTAT = CAN_CFG_STAT_LBME; + break; + case CAN_WORK_MD_NORMAL: + default: + break; + } + + MODIFY_REG8(CANx->CFG_STAT, CAN_CFG_STAT_LBMI | CAN_CFG_STAT_LBME, u8CFGSTAT); + MODIFY_REG8(CANx->TCMD, CAN_TCMD_LOM, u8TCMD); +} + +/** + * @brief Configures acceptance filter. Set ID and ID mask for the specified acceptance filters. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16FilterSelect Acceptance filters selection. + * This parameter can be values of @ref CAN_Acceptance_Filter + * @param [in] pstcFilter Pointer to a stc_can_filter_config_t structure type array which contains ID and ID mask + * values for the acceptance filters specified by parameter u16FilterSelect. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: If one the following cases matches: + * - u16FilterSelect == 0U. + * - pstcFilter == NULL. + * @note Call this function when CFG_STAT.RESET is 1. + */ +static int32_t CAN_FilterConfig(CM_CAN_TypeDef *CANx, uint16_t u16FilterSelect, + const stc_can_filter_config_t *pstcFilter) +{ + uint8_t u8FilterAddr = 0U; + uint8_t i = 0U; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + if ((u16FilterSelect != 0U) && (pstcFilter != NULL)) { + while (u16FilterSelect != 0U) { + if ((u16FilterSelect & 0x1U) != 0U) { + DDL_ASSERT(IS_CAN_ID_TYPE(pstcFilter[i].u32IDType)); + DDL_ASSERT(IS_CAN_ID_MASK(pstcFilter[i].u32IDMask)); + WRITE_REG8(CANx->ACFCTRL, u8FilterAddr); + WRITE_REG32(CANx->ACF, pstcFilter[i].u32ID); + SET_REG8_BIT(CANx->ACFCTRL, CAN_ACFCTRL_SELMASK); + WRITE_REG32(CANx->ACF, pstcFilter[i].u32IDMask | pstcFilter[i].u32IDType); + i++; + } + u16FilterSelect >>= 1U; + u8FilterAddr++; + } + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Write TX buffer register in bytes. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcTx Pointer to a @ref stc_can_tx_frame_t structure. + * @retval None + */ +static void CAN_WriteTxBuf(CM_CAN_TypeDef *CANx, const stc_can_tx_frame_t *pstcTx) +{ + uint8_t i; + uint8_t u8WordLen; + __IO uint32_t *reg32TBUF; + uint32_t *pu32TxData = (uint32_t *)((uint32_t)(&pstcTx->au8Data[0U])); + + reg32TBUF = (__IO uint32_t *)((uint32_t)&CANx->TBUF); + reg32TBUF[0U] = pstcTx->u32ID; + reg32TBUF[1U] = pstcTx->u32Ctrl; + + if (pstcTx->DLC != CAN_DLC0) { + u8WordLen = (uint8_t)((pstcTx->DLC + 3U) / 4U); + for (i = 0U; i < u8WordLen; i++) { + reg32TBUF[2U + i] = pu32TxData[i]; + } + } +} + +/** + * @brief Read RX buffer register in bytes. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcRx Pointer to a @ref stc_can_rx_frame_t structure. + * @retval None + */ +static void CAN_ReadRxBuf(const CM_CAN_TypeDef *CANx, stc_can_rx_frame_t *pstcRx) +{ + __I uint32_t *reg32RBUF; + uint8_t i; + uint8_t u8WordLen; + uint32_t *pu32RxData = (uint32_t *)((uint32_t)(&pstcRx->au8Data[0U])); + + reg32RBUF = (__I uint32_t *)((uint32_t)&CANx->RBUF); + pstcRx->u32ID = reg32RBUF[0U]; + pstcRx->u32Ctrl = reg32RBUF[1U]; + + u8WordLen = (uint8_t)((pstcRx->DLC + 3U) / 4U); + for (i = 0U; i < u8WordLen; i++) { + pu32RxData[i] = reg32RBUF[2U + i]; + } +} + +/** + * @} + */ + +/** + * @defgroup CAN_Global_Functions CAN Global Functions + * @{ + */ + +/** + * @brief Initializes the specified CAN peripheral according to the specified parameters + * in the structure pstcCanInit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcCanInit Pointer to a @ref stc_can_init_t structure value that + * contains the configuration information for the CAN. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanInit == NULL + */ +int32_t CAN_Init(CM_CAN_TypeDef *CANx, const stc_can_init_t *pstcCanInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcCanInit != NULL) { +#if defined __DEBUG + CAN_InitParameterCheck(CANx, pstcCanInit); +#endif /* __DEBUG */ + + /* Software reset. */ + SET_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); + /* Configures nominal bit time. */ + WRITE_REG32(CANx->SBT, ((pstcCanInit->stcBitCfg.u32TimeSeg1 - 2U) | \ + ((pstcCanInit->stcBitCfg.u32TimeSeg2 - 1U) << CAN_SBT_S_SEG_2_POS) | \ + ((pstcCanInit->stcBitCfg.u32SJW - 1U) << CAN_SBT_S_SJW_POS) | \ + ((pstcCanInit->stcBitCfg.u32Prescaler - 1U) << CAN_SBT_S_PRESC_POS))); + /* Enable or disable STB priority mode. */ + MODIFY_REG8(CANx->TCTRL, CAN_TCTRL_TSMODE, pstcCanInit->u8STBPrioMode); + /* Configures acceptance filters. */ + (void)CAN_FilterConfig(CANx, pstcCanInit->u16FilterSelect, pstcCanInit->pstcFilter); + + /* Configures CAN-FD */ + + /* CAN enters normal communication mode. */ + CLR_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); + /* Specifies CAN work mode. */ + CAN_SetWorkMode(CANx, pstcCanInit->u8WorkMode); + /* Enable or disable single shot transmission mode of PTB and STB. */ + MODIFY_REG8(CANx->CFG_STAT, \ + (CAN_CFG_STAT_TPSS | CAN_CFG_STAT_TSSS), \ + (pstcCanInit->u8PTBSingleShotTx | pstcCanInit->u8STBSingleShotTx)); + /* Specifies receive buffer almost full warning limit. Specifies error warning limit. */ + WRITE_REG8(CANx->LIMIT, ((pstcCanInit->u8RxWarnLimit << CAN_LIMIT_AFWL_POS) | pstcCanInit->u8ErrorWarnLimit)); + + /* Enable or disable RX all frames(include frames with error). + Specifies receive overflow mode. In case of a full rx buffer when a new message is received. + Enable or disable self-acknowledge. */ + WRITE_REG8(CANx->RCTRL, pstcCanInit->u8RxAllFrame | \ + pstcCanInit->u8RxOvfMode | \ + pstcCanInit->u8SelfAck); + /* Enable acceptance filters that configured before. */ + WRITE_REG8(CANx->ACFEN, pstcCanInit->u16FilterSelect); + /* Configures TTCAN if needed. */ + if (pstcCanInit->pstcCanTtc != NULL) { + (void)CAN_TTC_Config(CANx, pstcCanInit->pstcCanTtc); + } + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set each @ref stc_can_init_t field to a default value. + * Classical CAN bit time configuration: + * Based on 40MHz CAN clock, TQ clock is CAN clock divided by 4. + * Bit rate 500Kbps, 1 bit time is 20TQs, sample point is 80%. + * CAN-FD bit time configuration: + * Based on 40MHz CAN clock, TQ clock is CAN clock divided by 1. + * Bit rate 2Mbps, 1 bit time is 20TQs, primary sample point is 80%, + * secondary sample point is 80%. + * @param [in] pstcCanInit Pointer to a @ref stc_can_init_t structure + * whose fields will be set to default values. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanInit == NULL. + */ +int32_t CAN_StructInit(stc_can_init_t *pstcCanInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcCanInit != NULL) { + /* + * Synchronization Segment(SS): Fixed as 1TQ + * Propagation Time Segment(PTS) and Phase Buffer Segment 1(PBS1): 15TQs + * Phase Buffer Segment 2(PBS2): 4TQs + * + * Field 'S_SEG_1' in register CAN_SBT contains SS, PTS and PBS1. + * Field 'S_SEG_2' in register CAN_SBT only contains PBS2. + * Sample point = (SS + PTS + PBS1) / (SS + PTS + PBS1 + PBS2) + * = (1 + 15) / (1 + 15 + 4) + * = 80%. + */ + pstcCanInit->stcBitCfg.u32Prescaler = 4U; + pstcCanInit->stcBitCfg.u32TimeSeg1 = 16U; + pstcCanInit->stcBitCfg.u32TimeSeg2 = 4U; + pstcCanInit->stcBitCfg.u32SJW = 2U; + pstcCanInit->pstcFilter = NULL; + pstcCanInit->u16FilterSelect = 0U; + pstcCanInit->u8WorkMode = CAN_WORK_MD_NORMAL; + pstcCanInit->u8PTBSingleShotTx = CAN_PTB_SINGLESHOT_TX_DISABLE; + pstcCanInit->u8STBSingleShotTx = CAN_STB_SINGLESHOT_TX_DISABLE; + pstcCanInit->u8STBPrioMode = CAN_STB_PRIO_MD_DISABLE; + pstcCanInit->u8RxWarnLimit = CAN_RX_WARN_MAX; + pstcCanInit->u8ErrorWarnLimit = 7U; + pstcCanInit->u8RxAllFrame = CAN_RX_ALL_FRAME_DISABLE; + pstcCanInit->u8RxOvfMode = CAN_RX_OVF_DISCARD_NEW; + pstcCanInit->u8SelfAck = CAN_SELF_ACK_DISABLE; + pstcCanInit->pstcCanTtc = NULL; + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Deinitializes the specified CAN peripheral registers to their default reset values. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval None + */ +void CAN_DeInit(CM_CAN_TypeDef *CANx) +{ + uint8_t i; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + CLR_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); + for (i = 0U; i < 2U; i++) { + WRITE_REG8(CANx->CFG_STAT, 0x80U); + WRITE_REG8(CANx->TCMD, 0x00U); + WRITE_REG8(CANx->TCTRL, 0x90U); + WRITE_REG8(CANx->RCTRL, 0x10U); + WRITE_REG8(CANx->RTIE, 0xFEU); + WRITE_REG8(CANx->RTIF, 0xFFU); + WRITE_REG8(CANx->ERRINT, 0xD5U); + WRITE_REG8(CANx->LIMIT, 0x1BU); + WRITE_REG32(CANx->SBT, 0x01020203UL); + WRITE_REG8(CANx->RECNT, 0x00U); + WRITE_REG8(CANx->TECNT, 0x00U); + WRITE_REG8(CANx->ACFCTRL, 0x00U); + WRITE_REG8(CANx->TBSLOT, 0x00U); + WRITE_REG8(CANx->TTCFG, 0xD8U); + WRITE_REG16(CANx->TRG_CFG, 0x00U); + WRITE_REG16(CANx->TT_TRIG, 0x00U); + WRITE_REG16(CANx->TT_WTRIG, 0x00U); + WRITE_REG8(CANx->ACFEN, 0x01U); + + SET_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); + } +} + +/** + * @brief Enable or disable specified interrupts. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u32IntType Interrupt of CAN. + * This parameter can be values of @ref CAN_Interrupt_Type + * @arg CAN_INT_ERR_INT: Register bit RTIE.EIE. Error interrupt. + * @arg CAN_INT_STB_TX: Register bit RTIE.TSIE. STB was transmitted successfully. + * @arg CAN_INT_PTB_TX: Register bit RTIE.TPIE. PTB was transmitted successfully. + * @arg CAN_INT_RX_BUF_WARN: Register bit RTIE.RAFIE. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * @arg CAN_INT_RX_BUF_FULL: Register bit RTIE.RFIE. The FIFO of receive buffer is full. + * @arg CAN_INT_RX_OVERRUN: Register bit RTIE.ROIE. Receive buffers are full and there is a further message to be stored. + * @arg CAN_INT_RX: Register bit RTIE.RIE. Received a valid data frame or remote frame. + * @arg CAN_INT_BUS_ERR: Register bit ERRINT.BEIE. Arbitration lost caused bus error + * @arg CAN_INT_ARBITR_LOST: Register bit ERRINT.ALIE. Arbitration lost. + * @arg CAN_INT_ERR_PASSIVE: Register bit ERRINT.EPIE. A change from error-passive to error-active or error-active to error-passive has occurred. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CAN_IntCmd(CM_CAN_TypeDef *CANx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint8_t u8RTIE; + uint8_t u8ERRINT; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u8RTIE = (uint8_t)u32IntType; + u8ERRINT = (uint8_t)(u32IntType >> 8U); + + if (enNewState == ENABLE) { + SET_REG8_BIT(CANx->RTIE, u8RTIE); + SET_REG8_BIT(CANx->ERRINT, u8ERRINT); + } else { + CLR_REG8_BIT(CANx->RTIE, u8RTIE); + CLR_REG8_BIT(CANx->ERRINT, u8ERRINT); + } +} + +/** + * @brief Fills transmit frame. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8TxBufType CAN transmit buffer type. + * This parameter can be a value of @ref CAN_Tx_Buf_Type + * @param [in] pstcTx Pointer to a @ref stc_can_tx_frame_t structure. + * @arg CAN_TX_BUF_PTB: Primary transmit buffer. + * @arg CAN_TX_BUF_STB: Secondary transmit buffer. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTx == NULL. + * - LL_ERR_BUF_FULL: The specified transmit buffer is full. + * - LL_ERR_BUSY: The specified transmit buffer is being transmitted. + */ +int32_t CAN_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType, const stc_can_tx_frame_t *pstcTx) +{ + uint32_t u32RegAddr; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TX_BUF_TYPE(u8TxBufType)); + + if (pstcTx != NULL) { + DDL_ASSERT(IS_CAN20_DLC(pstcTx->FDF, pstcTx->DLC)); + +#if defined __DEBUG + if (pstcTx->RTR == 1U) { + DDL_ASSERT(pstcTx->DLC != CAN_DLC0); + } +#endif + i32Ret = LL_OK; + + if (((pstcTx->FDF == 1U) && ((pstcTx->u32ID & 0x8UL) == 0x8UL)) || \ + ((pstcTx->RTR == 1U) && (pstcTx->DLC == CAN_DLC0))) { + i32Ret = LL_ERR_INVD_PARAM; + } + + if (i32Ret == LL_OK) { + if (u8TxBufType == CAN_TX_BUF_PTB) { + if (READ_REG8_BIT(CANx->TCMD, CAN_TCMD_TPE) != 0U) { + /* PTB is being transmitted. */ + i32Ret = LL_ERR_BUSY; + } + } else { + if (READ_REG8_BIT(CANx->TCMD, (CAN_TCMD_TSONE | CAN_TCMD_TSALL)) != 0U) { + /* STB is being transmitted. */ + i32Ret = LL_ERR_BUSY; + } else { + if (READ_REG8_BIT(CANx->RTIE, CAN_RTIE_TSFF) != 0U) { + /* All STBs are filled. */ + i32Ret = LL_ERR_BUF_FULL; + } + } + } + } + + if (i32Ret == LL_OK) { + /* Assert ID */ + DDL_ASSERT(IS_CAN_ID(pstcTx->IDE, pstcTx->u32ID)); + + /* Specifies the transmit buffer, PTB or STB. */ + u32RegAddr = (uint32_t)&CANx->TCMD; + WRITE_REG32(PERIPH_BIT_BAND(u32RegAddr, CAN_TCMD_TBSEL_POS), u8TxBufType); + + CAN_WriteTxBuf(CANx, pstcTx); + + if (u8TxBufType == CAN_TX_BUF_STB) { + /* After writes the data in transmit buffer(TB), sets the TSNEXT bit to indicate that the current + STB slot has been filled, so that the hardware will point TB to the next STB slot. */ + SET_REG8_BIT(CANx->TCTRL, CAN_TCTRL_TSNEXT); + } + } + } + + return i32Ret; +} + +/** + * @brief Starts transmission. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8TxRequest The transmit buffer to be transmitted. + * This parameter can be values of @ref CAN_Tx_Request + * @arg CAN_TX_REQ_STB_ONE: Transmit one STB frame. + * @arg CAN_TX_REQ_STB_ALL: Transmit all STB frames. + * @arg CAN_TX_REQ_PTB: Transmit PTB frame. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +void CAN_StartTx(CM_CAN_TypeDef *CANx, uint8_t u8TxRequest) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TX_REQ(u8TxRequest)); + SET_REG8_BIT(CANx->TCMD, u8TxRequest); +} + +/** + * @brief Abort the transmission of the specified transmit buffer. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8TxBufType The transmit buffer to be aborted. + * This parameter can be a value of @ref CAN_Tx_Buf_Type + * @arg CAN_TX_BUF_PTB: Abort PTB transmission. + * @arg CAN_TX_BUF_STB: Abort STB transmission. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +void CAN_AbortTx(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType) +{ + uint8_t au8Abort[] = {CAN_TCMD_TPA, CAN_TCMD_TSA}; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TX_BUF_TYPE(u8TxBufType)); + SET_REG8_BIT(CANx->TCMD, au8Abort[u8TxBufType]); +} + +/** + * @brief Get one received frame. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [out] pstcRx Pointer to a @ref stc_can_rx_frame_t structure. + * @retval int32_t: + * - LL_OK: Get one received frame successfully. + * - LL_ERR_BUF_EMPTY: Receive buffer is empty, and no frame has been read. + * - LL_ERR_INVD_PARAM: pstcRx == NULL. + */ +int32_t CAN_GetRxFrame(CM_CAN_TypeDef *CANx, stc_can_rx_frame_t *pstcRx) +{ + int32_t i32Ret = LL_ERR_BUF_EMPTY; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + if (pstcRx == NULL) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + if (READ_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RSTAT) != CAN_RX_BUF_EMPTY) { + CAN_ReadRxBuf(CANx, pstcRx); + /* Set RB to point to the next RB slot. */ + SET_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RREL); + + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Get the status of specified flag. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u32Flag CAN status flag. + * This parameter can be a value of @ref CAN_Status_Flag + * @arg CAN_FLAG_BUS_OFF: Register bit CFG_STAT.BUSOFF. CAN bus off. + * @arg CAN_FLAG_TX_GOING: Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. + * @arg CAN_FLAG_RX_GOING: Register bit CFG_STAT.RACTIVE. CAN bus is receiving. + * @arg CAN_FLAG_RX_BUF_OVF: Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost. + * @arg CAN_FLAG_TX_BUF_FULL: Register bit RTIE.TSFF. Transmit buffers are all full: + * TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled. + * TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled. + * @arg CAN_FLAG_TX_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. + * @arg CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter and the + * set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than + * the set value to greater than the set value, or from greater than the set value to less than the set value. + * @arg CAN_FLAG_STB_TX: Register bit RTIF.TSIF. STB was transmitted successfully. + * @arg CAN_FLAG_PTB_TX: Register bit RTIF.TPIF. PTB was transmitted successfully. + * @arg CAN_FLAG_RX_BUF_WARN: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * @arg CAN_FLAG_RX_BUF_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full. + * @arg CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. + * @arg CAN_FLAG_RX: Register bit RTIF.RIF. Received a valid data frame or remote frame. + * @arg CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. In case of an error, KOER and the error counters get updated. BEIF gets set if BEIE is enabled + * and the other error interrupt flags will act accordingly. + * @arg CAN_FLAG_ARBITR_LOST: Register bit ERRINT.ALIF. Arbitration lost. + * @arg CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. + * @arg CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node. + * @arg CAN_FLAG_TEC_REC_WARN: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CAN_GetStatus(const CM_CAN_TypeDef *CANx, uint32_t u32Flag) +{ + uint8_t u8CFGSTAT; + uint8_t u8RCTRL; + uint8_t u8RTIE; + uint8_t u8RTIF; + uint8_t u8ERRINT; + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_FLAG(u32Flag)); + + u8CFGSTAT = (uint8_t)(u32Flag); + u8RCTRL = (uint8_t)(u32Flag & CAN_FLAG_RX_BUF_OVF); + u8RTIE = (uint8_t)(u32Flag >> 8U); + u8RTIF = (uint8_t)(u32Flag >> 16U); + u8ERRINT = (uint8_t)(u32Flag >> 24U); + + u8CFGSTAT = READ_REG8_BIT(CANx->CFG_STAT, u8CFGSTAT); + u8RCTRL = READ_REG8_BIT(CANx->RCTRL, u8RCTRL); + u8RTIE = READ_REG8_BIT(CANx->RTIE, u8RTIE); + u8RTIF = READ_REG8_BIT(CANx->RTIF, u8RTIF); + u8ERRINT = READ_REG8_BIT(CANx->ERRINT, u8ERRINT); + + if ((u8CFGSTAT != 0U) || (u8RCTRL != 0U) || \ + (u8RTIE != 0U) || (u8RTIF != 0U) || (u8ERRINT != 0U)) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of specified flags. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u32Flag CAN status flag. + * This parameter can be values of @ref CAN_Status_Flag + * @arg CAN_FLAG_RX_BUF_OVF: Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost. + * @arg CAN_FLAG_TX_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. + * @arg CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter + * and the set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than + * the set value to greater than the set value, or from greater than the set value to less than the set value. + * @arg CAN_FLAG_STB_TX: Register bit RTIF.TSIF. STB was transmitted successfully. + * @arg CAN_FLAG_PTB_TX: Register bit RTIF.TPIF. PTB was transmitted successfully. + * @arg CAN_FLAG_RX_BUF_WARN: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * @arg CAN_FLAG_RX_BUF_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full. + * @arg CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. + * @arg CAN_FLAG_RX: Register bit RTIF.RIF. Received a valid data frame or remote frame. + * @arg CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. In case of an error, KOER and the error counters get updated. BEIF gets set if BEIE is enabled + * and the other error interrupt flags will act accordingly. + * @arg CAN_FLAG_ARBITR_LOST: Register bit ERRINT.ALIF. Arbitration lost. + * @arg CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. + * @arg CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node. + * @arg CAN_FLAG_TEC_REC_WARN: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. + * @retval None + */ +void CAN_ClearStatus(CM_CAN_TypeDef *CANx, uint32_t u32Flag) +{ + uint8_t u8RTIF; + uint8_t u8ERRINT; + uint8_t u8Reg; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_FLAG(u32Flag)); + + u32Flag &= CAN_FLAG_CLR_ALL; + u8RTIF = (uint8_t)(u32Flag >> 16U); + u8ERRINT = (uint8_t)(u32Flag >> 24U); + + if ((u32Flag & CAN_FLAG_RX_BUF_OVF) != 0U) { + SET_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RREL); + } + + WRITE_REG8(CANx->RTIF, u8RTIF); + + u8Reg = READ_REG8(CANx->ERRINT); + u8Reg &= (uint8_t)(~CAN_ERRINT_FLAG_MASK); + u8Reg |= u8ERRINT; + WRITE_REG8(CANx->ERRINT, u8Reg); +} + +/** + * @brief Get the value of CAN status. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval An uint32_t type value that includes the flowing status flags. + * - CAN_FLAG_BUS_OFF: Register bit CFG_STAT.BUSOFF. CAN bus off. + * - CAN_FLAG_TX_GOING: Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. + * - CAN_FLAG_RX_GOING: Register bit CFG_STAT.RACTIVE. CAN bus is receiving. + * - CAN_FLAG_RX_BUF_OVF: Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost. + * - CAN_FLAG_TX_BUF_FULL: Register bit RTIE.TSFF. Transmit buffers are all full: + * TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled. + * TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled. + * - CAN_FLAG_TX_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. + * - CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter and the + * set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than + * the set value to greater than the set value, or from greater than the set value to less than the set value. + * - CAN_FLAG_STB_TX: Register bit RTIF.TSIF. STB was transmitted successfully. + * - CAN_FLAG_PTB_TX: Register bit RTIF.TPIF. PTB was transmitted successfully. + * - CAN_FLAG_RX_BUF_WARN: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * - CAN_FLAG_RX_BUF_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full. + * - CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. + * - CAN_FLAG_RX: Register bit RTIF.RIF. Received a valid data frame or remote frame. + * - CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. In case of an error, KOER and the error counters get updated. BEIF gets set if BEIE is enabled + * and the other error interrupt flags will act accordingly. + * - CAN_FLAG_ARBITR_LOST: Register bit ERRINT.ALIF. Arbitration lost. + * - CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. + * - CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node. + * - CAN_FLAG_TEC_REC_WARN: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. + */ +uint32_t CAN_GetStatusValue(const CM_CAN_TypeDef *CANx) +{ + uint32_t u32RCTRL; + uint32_t u32RTIE; + uint32_t u32RTIF; + uint32_t u32ERRINT; + uint32_t u32RetVal; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + u32RetVal = CANx->CFG_STAT; + u32RCTRL = CANx->RCTRL; + u32RCTRL &= CAN_FLAG_RX_BUF_OVF; + u32RTIE = CANx->RTIE; + u32RTIF = CANx->RTIF; + u32ERRINT = CANx->ERRINT; + + u32RetVal |= (u32RCTRL | (u32RTIE << 8U) | (u32RTIF << 16U) | (u32ERRINT << 24U)); + u32RetVal &= CAN_FLAG_ALL; + + return u32RetVal; +} + +/** + * @brief Get the information of CAN errors. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [out] pstcErr Pointer to a @ref stc_can_error_info_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcErr == NULL. + */ +int32_t CAN_GetErrorInfo(const CM_CAN_TypeDef *CANx, stc_can_error_info_t *pstcErr) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + if (pstcErr != NULL) { + pstcErr->u8ArbitrLostPos = READ_REG8_BIT(CANx->EALCAP, CAN_EALCAP_ALC); + pstcErr->u8ErrorType = READ_REG8_BIT(CANx->EALCAP, CAN_EALCAP_KOER) >> CAN_EALCAP_KOER_POS; + pstcErr->u8RxErrorCount = READ_REG8(CANx->RECNT); + pstcErr->u8TxErrorCount = READ_REG8(CANx->TECNT); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Get status(full or empty) of transmit buffer. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval An uint8_t type value of status of transmit buffer. It can be a value of @ref CAN_Tx_Buf_Status + * - CAN_TX_BUF_EMPTY: TTCAN is disabled(TTEN == 0): STB is empty. + * TTCAN is disabled(TTEN == 1) and transmit buffer is specified by TBPTR and TTPTR(TTTBM == 1): + * PTB and STB are both empty. + * - CAN_TX_BUF_NOT_MORE_THAN_HALF: TTEN == 0: STB is not less than half full; + * TTEN == 1 && TTTBM == 1: PTB and STB are neither empty. + * - CAN_TX_BUF_MORE_THAN_HALF: TTEN == 0: STB is more than half full; + * TTEN == 1 && TTTBM == 1: reserved value. + * - CAN_TX_BUF_FULL: TTEN == 0: STB is full; + * TTEN == 1 && TTTBM == 1: PTB and STB are both full. + */ +uint8_t CAN_GetTxBufStatus(const CM_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (READ_REG8_BIT(CANx->TCTRL, CAN_TCTRL_TSSTAT)); +} + +/** + * @brief Get status(full or empty) of receive buffer. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval An uint8_t type value of status of receive buffer. It can be a value of @ref CAN_Rx_Buf_Status + * - CAN_RX_BUF_EMPTY: Receive buffer is empty. + * - CAN_RX_BUF_NOT_WARN: Receive buffer is not empty, but is less than almost full warning limit. + * - CAN_RX_BUF_WARN: Receive buffer is not full, but is more than or equal to almost full warning limit. + * - CAN_RX_BUF_FULL: Receive buffer is full. + */ +uint8_t CAN_GetRxBufStatus(const CM_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (READ_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RSTAT)); +} + +/** + * @brief Enable or disable the specified acceptance filters. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16FilterSelect Acceptance filters selection. + * This parameter can be values of @ref CAN_Acceptance_Filter + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CAN_FilterCmd(CM_CAN_TypeDef *CANx, uint16_t u16FilterSelect, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_FILTER(u16FilterSelect)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG8_BIT(CANx->ACFEN, u16FilterSelect); + } else { + CLR_REG8_BIT(CANx->ACFEN, u16FilterSelect); + } +} + +/** + * @brief Set receive buffer full warning limit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8RxWarnLimit: Receive buffer full warning limit. + * When the number of received frames reaches the value specified by + * parameter 'u8RxWarnLimit', register bit RTIF.RAFIF set and the + * interrupt occurred if it was enabled. + * @retval None + */ +void CAN_SetRxWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8RxWarnLimit) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_RX_WARN(u8RxWarnLimit)); + MODIFY_REG8(CANx->LIMIT, CAN_LIMIT_AFWL, u8RxWarnLimit << CAN_LIMIT_AFWL_POS); +} + +/** + * @brief Set error warning limit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8ErrorWarnLimit Programmable error warning limit. Range is [0, 15]. + * Error warning limit = (u8ErrorWarnLimit + 1) * 8. + * @retval None + */ +void CAN_SetErrorWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8ErrorWarnLimit) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_ERR_WARN(u8ErrorWarnLimit)); + MODIFY_REG8(CANx->LIMIT, CAN_LIMIT_EWL, u8ErrorWarnLimit); +} + +/** + * @brief Set each @ref stc_can_ttc_config_t field to a default value. + * @param [in] pstcCanTtc Pointer to a @ref stc_can_ttc_config_t structure value that + * contains the configuration information for TTCAN. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanTtc == NULL. + */ +int32_t CAN_TTC_StructInit(stc_can_ttc_config_t *pstcCanTtc) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcCanTtc != NULL) { + pstcCanTtc->u8NTUPrescaler = CAN_TTC_NTU_PRESCALER1; + pstcCanTtc->u32RefMsgID = 0x0UL; + pstcCanTtc->u32RefMsgIDE = 0U; + pstcCanTtc->u8TxBufMode = CAN_TTC_TX_BUF_MD_TTCAN; + pstcCanTtc->u16TriggerType = CAN_TTC_TRIG_SINGLESHOT_TX_TRIG; + pstcCanTtc->u16TxEnableWindow = 16U; + pstcCanTtc->u16TxTriggerTime = 0xFFFFU; + pstcCanTtc->u16WatchTriggerTime = 0xFFFFU; + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Configures the specified TTCAN according to the specified parameters + * in @ref stc_can_ttc_config_t type structure. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] pstcCanTtc Pointer to a @ref stc_can_ttc_config_t structure value that + * contains the configuration information for TTCAN. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanTtc == NULL. + */ +int32_t CAN_TTC_Config(CM_CAN_TypeDef *CANx, const stc_can_ttc_config_t *pstcCanTtc) +{ + uint32_t u32RefMsgID; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + if (pstcCanTtc != NULL) { + DDL_ASSERT(IS_TTCAN_TX_BUF_MD(pstcCanTtc->u8TxBufMode)); + DDL_ASSERT(IS_TTCAN_NTU_PRESCALER(pstcCanTtc->u8NTUPrescaler)); + DDL_ASSERT(IS_CAN_ID(pstcCanTtc->u32RefMsgIDE, pstcCanTtc->u32RefMsgID)); + DDL_ASSERT(IS_TTCAN_TRIG_TYPE(pstcCanTtc->u16TriggerType)); + DDL_ASSERT(IS_TTCAN_TX_EN_WINDOW(pstcCanTtc->u16TxEnableWindow)); + + u32RefMsgID = pstcCanTtc->u32RefMsgID & ((uint32_t)(~CAN_REF_MSG_REF_IDE)); + /* Specifies transmission buffer mode. */ + MODIFY_REG8(CANx->TCTRL, CAN_TCTRL_TTTBM, pstcCanTtc->u8TxBufMode); + /* Specifies Tx_Enable window and trigger type. */ + WRITE_REG16(CANx->TRG_CFG, pstcCanTtc->u16TriggerType | + ((pstcCanTtc->u16TxEnableWindow - 1U) << CAN_TRG_CFG_TEW_POS)); + /* Specifies ID of reference message and its extension bit. */ + WRITE_REG32(CANx->REF_MSG, (((pstcCanTtc->u32RefMsgIDE << CAN_REF_MSG_REF_IDE_POS) | u32RefMsgID))); + /* Specifies transmission trigger time. */ + WRITE_REG16(CANx->TT_TRIG, pstcCanTtc->u16TxTriggerTime); + /* Specifies watch trigger time. */ + WRITE_REG16(CANx->TT_WTRIG, pstcCanTtc->u16WatchTriggerTime); + /* Specifies NTU prescaler. */ + MODIFY_REG8(CANx->TTCFG, CAN_TTCFG_T_PRESC, pstcCanTtc->u8NTUPrescaler); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Enable or disable the specified interrupts of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8IntType Interrupt of TTCAN. + * This parameter can be values of @ref TTCAN_Interrupt_Type + * @arg CAN_TTC_INT_TIME_TRIG: Time trigger interrupt. + * @arg CAN_TTC_INT_WATCH_TRIG: Watch trigger interrupt. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CAN_TTC_IntCmd(CM_CAN_TypeDef *CANx, uint8_t u8IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_INT(u8IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG8_BIT(CANx->TTCFG, u8IntType); + } else { + CLR_REG8_BIT(CANx->TTCFG, u8IntType); + } +} + +/** + * @brief Enable or disable TTCAN of the specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +void CAN_TTC_Cmd(CM_CAN_TypeDef *CANx, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&CANx->TTCFG; + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, CAN_TTCFG_TTEN_POS), enNewState); +} + +/** + * @brief Get status of the sepcified TTCAN flag. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8Flag Status flag of TTCAN. + * This parameter can be values of @ref TTCAN_Status_Flag + * @arg CAN_TTC_FLAG_TIME_TRIG: Time trigger interrupt flag. + * @arg CAN_TTC_FLAG_TRIG_ERR: Trigger error interrupt flag. + * @arg CAN_TTC_FLAG_WATCH_TRIG: Watch trigger interrupt flag. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CAN_TTC_GetStatus(const CM_CAN_TypeDef *CANx, uint8_t u8Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_FLAG(u8Flag)); + + if (READ_REG8_BIT(CANx->TTCFG, (u8Flag & CAN_TTC_FLAG_ALL)) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of TTCAN flags. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8Flag Status flag of TTCAN. + * This parameter can be a value of @ref TTCAN_Status_Flag except CAN_TTC_FLAG_TRIG_ERR. + * @arg CAN_TTC_FLAG_TIME_TRIG: Time trigger interrupt flag. + * @arg CAN_TTC_FLAG_WATCH_TRIG: Watch trigger interrupt flag. + * @retval None + */ +void CAN_TTC_ClearStatus(CM_CAN_TypeDef *CANx, uint8_t u8Flag) +{ + uint8_t u8Reg; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_FLAG(u8Flag)); + + u8Reg = READ_REG8(CANx->TTCFG); + u8Reg &= (uint8_t)(~CAN_TTC_FLAG_ALL); + u8Reg |= u8Flag; + WRITE_REG8(CANx->TTCFG, u8Reg); +} + +/** + * @brief Get the status value of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @retval An uint8_t type value that includes the flowing status flags. + * - CAN_TTC_FLAG_TIME_TRIG: Time trigger interrupt flag. + * - CAN_TTC_FLAG_TRIG_ERR: Trigger error interrupt flag. + * - CAN_TTC_FLAG_WATCH_TRIG: Watch trigger interrupt flag. + */ +uint8_t CAN_TTC_GetStatusValue(const CM_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return READ_REG8_BIT(CANx->TTCFG, CAN_TTC_FLAG_ALL); +} + +/** + * @brief Specifies trigger type of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16TriggerType TTCAN trigger type. + * This parameter can be a value of @ref TTCAN_Trigger_Type + * @arg CAN_TTC_TRIG_IMMED_TRIG: Immediate trigger for immediate transmission. + * @arg CAN_TTC_TRIG_TIME_TRIG: Time trigger for receive triggers. + * @arg CAN_TTC_TRIG_SINGLESHOT_TX_TRIG: Single shot transmit trigger for exclusive time windows. + * @arg CAN_TTC_TRIG_TX_START_TRIG: Transmit start trigger for merged arbitrating time windows. + * @arg CAN_TTC_TRIG_TX_STOP_TRIG: Transmit stop trigger for merged arbitrating time windows. + * @retval None + */ +void CAN_TTC_SetTriggerType(CM_CAN_TypeDef *CANx, uint16_t u16TriggerType) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_TRIG_TYPE(u16TriggerType)); + MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TTYPE, u16TriggerType); +} + +/** + * @brief Specifies transmit enable window time of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16TxEnableWindow Number of NTU. Time period within which the transmit of a message may be started. + * @retval None + */ +void CAN_TTC_SetTxEnableWindow(CM_CAN_TypeDef *CANx, uint16_t u16TxEnableWindow) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_TX_EN_WINDOW(u16TxEnableWindow)); + MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TEW, (u16TxEnableWindow - 1U) << CAN_TRG_CFG_TEW_POS); +} + +/** + * @brief Specifies transmit trigger time of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16TxTriggerTime Transmit trigger time(number of NTU). + * @retval None + */ +void CAN_TTC_SetTxTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16TxTriggerTime) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + WRITE_REG16(CANx->TT_TRIG, u16TxTriggerTime); +} + +/** + * @brief TTCAN specifies watch-trigger time. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u16WatchTriggerTime Watch trigger time(number of NTU). + * @retval None + */ +void CAN_TTC_SetWatchTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16WatchTriggerTime) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + WRITE_REG16(CANx->TT_WTRIG, u16WatchTriggerTime); +} + +/** + * @brief TTCAN fill transmit frame. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [in] u8CANTTCTxBuf TTCAN transmit buffer selection. + * This parameter can be a value of @ref TTCAN_Tx_Buf_Sel + * @param [in] pstcTx Pointer to a @ref stc_can_tx_frame_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTx == NULL. + * - LL_ERR_BUF_FULL: The target transmit buffer is full. + */ +int32_t CAN_TTC_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8CANTTCTxBuf, const stc_can_tx_frame_t *pstcTx) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_TTCAN_TX_BUF_SEL(u8CANTTCTxBuf)); + + if (pstcTx != NULL) { + DDL_ASSERT(IS_CAN20_DLC(pstcTx->FDF, pstcTx->DLC)); + + if (READ_REG8_BIT(CANx->TCTRL, CAN_TX_BUF_FULL) == CAN_TX_BUF_FULL) { + i32Ret = LL_ERR_BUF_FULL; + } else { + WRITE_REG8(CANx->TBSLOT, u8CANTTCTxBuf); + MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TTPTR, u8CANTTCTxBuf); + CAN_WriteTxBuf(CANx, pstcTx); + + /* Set buffer as filled. */ + SET_REG8_BIT(CANx->TBSLOT, CAN_TBSLOT_TBF); + + /* Write MSB of TT_TRIG to transmit. */ + WRITE_REG16(CANx->TT_TRIG, CANx->TT_TRIG); + + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Get the configuration of TTCAN. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg CM_CAN or CM_CANx: CAN instance register base. + * @param [out] pstcCanTtc Pointer to a @ref stc_can_ttc_config_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcCanTtc == NULL. + */ +int32_t CAN_TTC_GetConfig(const CM_CAN_TypeDef *CANx, stc_can_ttc_config_t *pstcCanTtc) +{ + uint32_t u32Tmp; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcCanTtc != NULL) { + u32Tmp = READ_REG32(CANx->REF_MSG); + pstcCanTtc->u8TxBufMode = READ_REG8_BIT(CANx->TCTRL, CAN_TCTRL_TTTBM); + pstcCanTtc->u8NTUPrescaler = READ_REG8_BIT(CANx->TTCFG, CAN_TTCFG_T_PRESC); + pstcCanTtc->u32RefMsgIDE = (u32Tmp >> CAN_REF_MSG_REF_IDE_POS) & 0x1UL; + pstcCanTtc->u32RefMsgID = u32Tmp & 0x7FFFFFFFUL; + pstcCanTtc->u16TriggerType = READ_REG16_BIT(CANx->TRG_CFG, CAN_TRG_CFG_TTYPE); + pstcCanTtc->u16TxEnableWindow = (READ_REG16_BIT(CANx->TRG_CFG, CAN_TRG_CFG_TEW) >> CAN_TRG_CFG_TEW_POS) + 1U; + pstcCanTtc->u16TxTriggerTime = READ_REG16(CANx->TT_TRIG); + pstcCanTtc->u16WatchTriggerTime = READ_REG16(CANx->TT_WTRIG); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_CAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_clk.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_clk.c new file mode 100644 index 0000000000..428afe8cbf --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_clk.c @@ -0,0 +1,1715 @@ +/** + ******************************************************************************* + * @file hc32_ll_clk.c + * @brief This file provides firmware functions to manage the Clock(CLK). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_clk.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CLK CLK + * @brief Clock Driver Library + * @{ + */ + +#if (LL_CLK_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CLK_Local_Macros CLK Local Macros + * @{ + */ + +/** + * @brief CLK_FREQ Clock frequency definition + */ +#define CLK_FREQ_48M (48UL*1000UL*1000UL) +#define CLK_FREQ_64M (64UL*1000UL*1000UL) +#define CLK_FREQ_32M (32UL*1000UL*1000UL) + +/** + * @brief Be able to modify TIMEOUT according to board condition. + */ +#define CLK_TIMEOUT ((uint32_t)0x1000UL) +#define CLK_LRC_TIMEOUT ((uint32_t)0x200U) + +#define CLK_MRC_TIMEOUT ((uint32_t)0x200U) +#define CLK_XTAL32_TIMEOUT ((uint32_t)0x200U) + +/** + * @brief LRC State ON or OFF + */ +#define CLK_LRC_OFF (CMU_LRCCR_LRCSTP) +#define CLK_LRC_ON (0x00U) + +/** + * @brief MRC State ON or OFF + */ +#define CLK_MRC_OFF (CMU_MRCCR_MRCSTP) +#define CLK_MRC_ON (0x80U) + +/** + * @brief Clk PLL Relevant Parameter Range Definition + */ +#define CLK_PLLP_DEFAULT (0x01UL) +#define CLK_PLLQ_DEFAULT (0x01UL) +#define CLK_PLLR_DEFAULT (0x01UL) +#define CLK_PLLN_DEFAULT (0x13UL) +#define CLK_PLLM_DEFAULT (0x00UL) + +#define CLK_PLLR_DIV_MIN (2UL) +#define CLK_PLLR_DIV_MAX (16UL) +#define CLK_PLLQ_DIV_MIN (2UL) +#define CLK_PLLQ_DIV_MAX (16UL) +#define CLK_PLLP_DIV_MIN (2UL) +#define CLK_PLLP_DIV_MAX (16UL) + +#define CLK_PLLX_FREQ_MIN (15UL*1000UL*1000UL) +#define CLK_PLLX_VCO_IN_MIN (1UL*1000UL*1000UL) +#define CLK_PLLX_VCO_IN_MAX (25UL*1000UL*1000UL) +#define CLK_PLLX_VCO_OUT_MIN (240UL*1000UL*1000UL) +#define CLK_PLLX_VCO_OUT_MAX (480UL*1000UL*1000UL) +#define CLK_PLLXM_DIV_MIN (2UL) +#define CLK_PLLXM_DIV_MAX (24UL) +#define CLK_PLLXN_MULTI_MIN (20UL) +#define CLK_PLLXN_MULTI_MAX (480UL) +#define CLK_PLLXR_DIV_MIN (2UL) +#define CLK_PLLXR_DIV_MAX (16UL) +#define CLK_PLLXQ_DIV_MIN (2UL) +#define CLK_PLLXQ_DIV_MAX (16UL) +#define CLK_PLLXP_DIV_MIN (2UL) +#define CLK_PLLXP_DIV_MAX (16UL) +#define CLK_PLLXP_DEFAULT (0x01UL) +#define CLK_PLLXQ_DEFAULT (0x01UL) +#define CLK_PLLXR_DEFAULT (0x01UL) +#define CLK_PLLXN_DEFAULT (0x13UL) +#define CLK_PLLXM_DEFAULT (0x00UL) + +#define CLK_PLL_FREQ_MIN (15UL*1000UL*1000UL) +#define CLK_PLL_VCO_IN_MIN (1UL*1000UL*1000UL) +#define CLK_PLL_VCO_IN_MAX (25UL*1000UL*1000UL) +#define CLK_PLL_VCO_OUT_MIN (240UL*1000UL*1000UL) +#define CLK_PLL_VCO_OUT_MAX (480UL*1000UL*1000UL) +#define CLK_PLLM_DIV_MIN (1UL) +#define CLK_PLLM_DIV_MAX (24UL) +#define CLK_PLLN_MULTI_MIN (20UL) +#define CLK_PLLN_MULTI_MAX (480UL) +#define CLK_PLLX_FREQ_MAX (200UL*1000UL*1000UL) +#define CLK_PLL_FREQ_MAX (240UL*1000UL*1000UL) + +/** + * @brief Clk PLL Register Redefinition + */ +#define PLL_SRC_REG (CM_CMU->PLLCFGR) +#define PLL_SRC_BIT (CMU_PLLCFGR_PLLSRC) +#define PLL_SRC_POS (CMU_PLLCFGR_PLLSRC_POS) +#define PLL_SRC ((CM_CMU->PLLCFGR & CMU_PLLCFGR_PLLSRC) >> CMU_PLLCFGR_PLLSRC_POS) +#define PLL_EN_REG (CM_CMU->PLLCR) +#define PLLX_EN_REG (CM_CMU->UPLLCR) + +/** + * @brief Switch clock stable time + * @note Approx. 30us + */ +#define CLK_SYSCLK_SW_STB (HCLK_VALUE / 50000UL) + +/** + * @brief Clk FCG Default Value + */ +#define CLK_FCG0_DEFAULT (0xFFFFFA0EUL) +#define CLK_FCG1_DEFAULT (0xFFFFFFFFUL) +#define CLK_FCG2_DEFAULT (0xFFFFFFFFUL) +#define CLK_FCG3_DEFAULT (0xFFFFFFFFUL) + +/** + * @defgroup CLK_Check_Parameters_Validity CLK Check Parameters Validity + * @{ + */ +/* Check CLK register lock status. */ +#define IS_CLK_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB0) == PWC_FPRC_FPRCB0) + +/* Parameter valid check for XTAL state */ +#define IS_CLK_XTAL_STATE(x) \ +( ((x) == CLK_XTAL_OFF) || \ + ((x) == CLK_XTAL_ON)) + +/* Parameter valid check for XTAL mode */ +#define IS_CLK_XTAL_MD(x) \ +( ((x) == CLK_XTAL_MD_OSC) || \ + ((x) == CLK_XTAL_MD_EXCLK)) + +/* Parameter valid check for XTAL super drive state */ +#define IS_CLK_XTAL_SUPDRV_STATE(x) \ +( ((x) == CLK_XTAL_SUPDRV_ON) || \ + ((x) == CLK_XTAL_SUPDRV_OFF)) + +/* Parameter valid check for XTAL driver ability mode */ +#define IS_CLK_XTAL_DRV_MD(x) \ +( ((x) == CLK_XTAL_DRV_HIGH) || \ + ((x) == CLK_XTAL_DRV_MID) || \ + ((x) == CLK_XTAL_DRV_LOW) || \ + ((x) == CLK_XTAL_DRV_ULOW)) + +/* Parameter valid check for XTAL stable time selection */ +#define IS_CLK_XTAL_STB_SEL(x) \ +( ((x) == CLK_XTAL_STB_133US) || \ + ((x) == CLK_XTAL_STB_255US) || \ + ((x) == CLK_XTAL_STB_499US) || \ + ((x) == CLK_XTAL_STB_988US) || \ + ((x) == CLK_XTAL_STB_2MS) || \ + ((x) == CLK_XTAL_STB_4MS) || \ + ((x) == CLK_XTAL_STB_8MS) || \ + ((x) == CLK_XTAL_STB_16MS) || \ + ((x) == CLK_XTAL_STB_31MS)) + +/* Parameter valid check for XTALSTD state */ +#define IS_CLK_XTALSTD_STATE(x) \ +( ((x) == CLK_XTALSTD_OFF) || \ + ((x) == CLK_XTALSTD_ON)) + +/* Parameter valid check for XTALSTD mode */ +#define IS_CLK_XTALSTD_MD(x) \ +( ((x) == CLK_XTALSTD_MD_RST) || \ + ((x) == CLK_XTALSTD_MD_INT)) + +/* Parameter valid check for XTALSTD interrupt state */ +#define IS_CLK_XTALSTD_INT_STATE(x) \ +( ((x) == CLK_XTALSTD_INT_OFF) || \ + ((x) == CLK_XTALSTD_INT_ON)) + +/* Parameter valid check for XTALSTD reset state */ +#define IS_CLK_XTALSTD_RST_STATE(x) \ +( ((x) == CLK_XTALSTD_RST_OFF) || \ + ((x) == CLK_XTALSTD_RST_ON)) + +/* Parameter valid check for PLL state */ +#define IS_CLK_PLL_STATE(x) \ +( ((x) == CLK_PLL_OFF) || \ + ((x) == CLK_PLL_ON)) + +/* Parameter validity check for PLL input source */ +#define IS_CLK_PLL_SRC(x) \ +( ((x) == CLK_PLL_SRC_XTAL) || \ + ((x) == CLK_PLL_SRC_HRC)) + +/* Parameter validity check for PLL frequency range */ +#define IS_CLK_PLL_FREQ(x) \ +( ((x) <= CLK_PLL_FREQ_MAX) && \ + ((x) >= CLK_PLL_FREQ_MIN)) + +/* Parameter validity check for PLL M divide */ +#define IS_CLK_PLLM_DIV(x) \ +( ((x) <= CLK_PLLM_DIV_MAX) && \ + ((x) >= CLK_PLLM_DIV_MIN)) + +/* Parameter validity check for PLL N multi- */ +#define IS_CLK_PLLN_MULTI(x) \ +( ((x) <= CLK_PLLN_MULTI_MAX) && \ + ((x) >= CLK_PLLN_MULTI_MIN)) + +/* Parameter validity check for PLL P divide */ +#define IS_CLK_PLLP_DIV(x) \ +( ((x) <= CLK_PLLP_DIV_MAX) && \ + ((x) >= CLK_PLLP_DIV_MIN)) + +/* Parameter validity check for PLL_input freq./PLLM(vco_in) */ +#define IS_CLK_PLL_VCO_IN(x) \ +( ((x) <= CLK_PLL_VCO_IN_MAX) && \ + ((x) >= CLK_PLL_VCO_IN_MIN)) + +/* Parameter validity check for PLL vco_in*PLLN(vco_out) */ +#define IS_CLK_PLL_VCO_OUT(x) \ +( ((x) <= CLK_PLL_VCO_OUT_MAX) && \ + ((x) >= CLK_PLL_VCO_OUT_MIN)) + +/* Parameter validity check for PLL R divide */ +#define IS_CLK_PLLR_DIV(x) \ +( ((x) <= CLK_PLLR_DIV_MAX) && \ + ((x) >= CLK_PLLR_DIV_MIN)) + +/* Parameter validity check for PLL Q divede */ +#define IS_CLK_PLLQ_DIV(x) \ +( ((x) <= CLK_PLLQ_DIV_MAX) && \ + ((x) >= CLK_PLLQ_DIV_MIN)) + +/* Parameter valid check for PLLX state */ +#define IS_CLK_PLLX_STATE(x) \ +( ((x) == CLK_PLLX_OFF) || \ + ((x) == CLK_PLLX_ON)) + +/* Parameter validity check for PLLX frequency range */ +#define IS_CLK_PLLX_FREQ(x) \ +( (CLK_PLLX_FREQ_MIN <= (x)) && \ + (CLK_PLLX_FREQ_MAX >= (x))) + +/* Parameter validity check for PLLX M divide */ +#define IS_CLK_PLLXM_DIV(x) \ +( (CLK_PLLXM_DIV_MIN <= (x)) && \ + (CLK_PLLXM_DIV_MAX >= (x))) + +/* Parameter validity check for PLLX N multi- */ +#define IS_CLK_PLLXN_MULTI(x) \ +( (CLK_PLLXN_MULTI_MIN <= (x)) && \ + (CLK_PLLXN_MULTI_MAX >= (x))) + +/* Parameter validity check for PLLX R divide */ +#define IS_CLK_PLLXR_DIV(x) \ +( (CLK_PLLXR_DIV_MIN <= (x)) && \ + (CLK_PLLXR_DIV_MAX >= (x))) + +/* Parameter validity check for PLLX Q divede */ +#define IS_CLK_PLLXQ_DIV(x) \ +( (CLK_PLLXQ_DIV_MIN <= (x)) && \ + (CLK_PLLXQ_DIV_MAX >= (x))) + +/* Parameter validity check for PLLX P divide */ +#define IS_CLK_PLLXP_DIV(x) \ +( (CLK_PLLXP_DIV_MIN <= (x)) && \ + (CLK_PLLXP_DIV_MAX >= (x))) + +/* Parameter validity check for PLLX_input freq./PLLM(vco_in) */ +#define IS_CLK_PLLX_VCO_IN(x) \ +( (CLK_PLLX_VCO_IN_MIN <= (x)) && \ + (CLK_PLLX_VCO_IN_MAX >= (x))) + +/* Parameter validity check for PLLX vco_in*PLLN(vco_out) */ +#define IS_CLK_PLLX_VCO_OUT(x) \ +( (CLK_PLLX_VCO_OUT_MIN <= (x)) && \ + (CLK_PLLX_VCO_OUT_MAX >= (x))) + +/* Parameter valid check for XTAL32 state */ +#define IS_CLK_XTAL32_STATE(x) \ +( ((x) == CLK_XTAL32_OFF) || \ + ((x) == CLK_XTAL32_ON)) + +/* Parameter valid check for XTAL32 driver ability mode */ +#define IS_CLK_XTAL32_DRV_MD(x) \ +( ((x) == CLK_XTAL32_DRV_MID) || \ + ((x) == CLK_XTAL32_DRV_HIGH)) + +/* Parameter valid check for XTAL32 filtering selection */ +#define IS_CLK_XTAL32_FILT_SEL(x) \ +( ((x) == CLK_XTAL32_FILTER_ALL_MD) || \ + ((x) == CLK_XTAL32_FILTER_RUN_MD) || \ + ((x) == CLK_XTAL32_FILTER_OFF)) + +/* Parameter valid check for system clock source */ +#define IS_CLK_SYSCLK_SRC(x) \ +( ((x) == CLK_SYSCLK_SRC_HRC) || \ + ((x) == CLK_SYSCLK_SRC_MRC) || \ + ((x) == CLK_SYSCLK_SRC_LRC) || \ + ((x) == CLK_SYSCLK_SRC_XTAL) || \ + ((x) == CLK_SYSCLK_SRC_XTAL32) || \ + ((x) == CLK_SYSCLK_SRC_PLL)) + +/* Parameter valid check for CLK stable flag. */ +#define IS_CLK_STB_FLAG(x) \ +( ((x) != 0x00U) && \ + (((x) | CLK_STB_FLAG_MASK) == CLK_STB_FLAG_MASK)) + +/* Parameter valid check for bus clock category */ +#define IS_CLK_BUS_CLK_CATE(x) (((x) & CLK_BUS_CLK_ALL) != (0x00U)) + +/* Parameter valid check for HCLK divider */ +#define IS_CLK_HCLK_DIV(x) \ +( ((x) == CLK_HCLK_DIV1) || \ + ((x) == CLK_HCLK_DIV2) || \ + ((x) == CLK_HCLK_DIV4) || \ + ((x) == CLK_HCLK_DIV8) || \ + ((x) == CLK_HCLK_DIV16) || \ + ((x) == CLK_HCLK_DIV32) || \ + ((x) == CLK_HCLK_DIV64)) + +/* Parameter valid check for PCLK1 divider */ +#define IS_CLK_PCLK1_DIV(x) \ +( ((x) == CLK_PCLK1_DIV1) || \ + ((x) == CLK_PCLK1_DIV2) || \ + ((x) == CLK_PCLK1_DIV4) || \ + ((x) == CLK_PCLK1_DIV8) || \ + ((x) == CLK_PCLK1_DIV16) || \ + ((x) == CLK_PCLK1_DIV32) || \ + ((x) == CLK_PCLK1_DIV64)) + +/* Parameter valid check for PCLK4 divider */ +#define IS_CLK_PCLK4_DIV(x) \ +( ((x) == CLK_PCLK4_DIV1) || \ + ((x) == CLK_PCLK4_DIV2) || \ + ((x) == CLK_PCLK4_DIV4) || \ + ((x) == CLK_PCLK4_DIV8) || \ + ((x) == CLK_PCLK4_DIV16) || \ + ((x) == CLK_PCLK4_DIV32) || \ + ((x) == CLK_PCLK4_DIV64)) + +/* Parameter valid check for PCLK3 divider */ +#define IS_CLK_PCLK3_DIV(x) \ +( ((x) == CLK_PCLK3_DIV1) || \ + ((x) == CLK_PCLK3_DIV2) || \ + ((x) == CLK_PCLK3_DIV4) || \ + ((x) == CLK_PCLK3_DIV8) || \ + ((x) == CLK_PCLK3_DIV16) || \ + ((x) == CLK_PCLK3_DIV32) || \ + ((x) == CLK_PCLK3_DIV64)) + +/* Parameter valid check for EXCLK divider */ +#define IS_CLK_EXCLK_DIV(x) \ +( ((x) == CLK_EXCLK_DIV1) || \ + ((x) == CLK_EXCLK_DIV2) || \ + ((x) == CLK_EXCLK_DIV4) || \ + ((x) == CLK_EXCLK_DIV8) || \ + ((x) == CLK_EXCLK_DIV16) || \ + ((x) == CLK_EXCLK_DIV32) || \ + ((x) == CLK_EXCLK_DIV64)) + +/* Parameter valid check for PCLK0 divider */ +#define IS_CLK_PCLK0_DIV(x) \ +( ((x) == CLK_PCLK0_DIV1) || \ + ((x) == CLK_PCLK0_DIV2) || \ + ((x) == CLK_PCLK0_DIV4) || \ + ((x) == CLK_PCLK0_DIV8) || \ + ((x) == CLK_PCLK0_DIV16) || \ + ((x) == CLK_PCLK0_DIV32) || \ + ((x) == CLK_PCLK0_DIV64)) + +/* Parameter valid check for PCLK2 divider */ +#define IS_CLK_PCLK2_DIV(x) \ +( ((x) == CLK_PCLK2_DIV1) || \ + ((x) == CLK_PCLK2_DIV2) || \ + ((x) == CLK_PCLK2_DIV4) || \ + ((x) == CLK_PCLK2_DIV8) || \ + ((x) == CLK_PCLK2_DIV16) || \ + ((x) == CLK_PCLK2_DIV32) || \ + ((x) == CLK_PCLK2_DIV64)) + +/* Parameter valid check for bus clock */ +#define IS_CLK_BUS_CLK(x) \ +( ((x) == CLK_BUS_HCLK) || \ + ((x) == CLK_BUS_EXCLK) || \ + ((x) == CLK_BUS_PCLK0) || \ + ((x) == CLK_BUS_PCLK1) || \ + ((x) == CLK_BUS_PCLK2) || \ + ((x) == CLK_BUS_PCLK3) || \ + ((x) == CLK_BUS_PCLK4)) + +/* Parameter valid check for USB clock source */ +#define IS_CLK_USBCLK_SRC(x) \ +( ((x) == CLK_USBCLK_SYSCLK_DIV2) || \ + ((x) == CLK_USBCLK_SYSCLK_DIV3) || \ + ((x) == CLK_USBCLK_SYSCLK_DIV4) || \ + ((x) == CLK_USBCLK_PLLP) || \ + ((x) == CLK_USBCLK_PLLQ) || \ + ((x) == CLK_USBCLK_PLLR) || \ + ((x) == CLK_USBCLK_PLLXP) || \ + ((x) == CLK_USBCLK_PLLXQ) || \ + ((x) == CLK_USBCLK_PLLXR)) + +/* Parameter valid check for CAN channel for clock source config */ +#define IS_CLK_CAN_UNIT(x) \ +( ((x) == CLK_CAN1) || \ + ((x) == CLK_CAN2)) + +/* Parameter valid check for I2S channel for clock source config */ +#define IS_CLK_I2S_UNIT(x) \ +( ((x) == CLK_I2S1) || \ + ((x) == CLK_I2S2) || \ + ((x) == CLK_I2S3) || \ + ((x) == CLK_I2S4)) + +/* Parameter valid check for peripheral source */ +#define IS_CLK_PERIPHCLK_SRC(x) \ +( ((x) == CLK_PERIPHCLK_PCLK) || \ + ((x) == CLK_PERIPHCLK_PLLP) || \ + ((x) == CLK_PERIPHCLK_PLLQ) || \ + ((x) == CLK_PERIPHCLK_PLLR) || \ + ((x) == CLK_PERIPHCLK_PLLXP) || \ + ((x) == CLK_PERIPHCLK_PLLXQ) || \ + ((x) == CLK_PERIPHCLK_PLLXR)) + +/* Parameter valid check for TPIU clock divider */ +#define IS_CLK_TPIUCLK_DIV(x) \ +( ((x) == CLK_TPIUCLK_DIV1) || \ + ((x) == CLK_TPIUCLK_DIV2) || \ + ((x) == CLK_TPIUCLK_DIV4)) + +/* Parameter valid check for CLK MCO clock source . */ +#define IS_CLK_MCO_SRC(x) \ +( ((x) == CLK_MCO_SRC_HRC) || \ + ((x) == CLK_MCO_SRC_MRC) || \ + ((x) == CLK_MCO_SRC_LRC) || \ + ((x) == CLK_MCO_SRC_XTAL) || \ + ((x) == CLK_MCO_SRC_XTAL32) || \ + ((x) == CLK_MCO_SRC_PLLP) || \ + ((x) == CLK_MCO_SRC_PLLXP) || \ + ((x) == CLK_MCO_SRC_PLLQ) || \ + ((x) == CLK_MCO_SRC_PLLXQ) || \ + ((x) == CLK_MCO_SRC_HCLK)) + +/* Parameter valid check for CLK MCO clock divide. */ +#define IS_CLK_MCO_DIV(x) \ +( ((x) == CLK_MCO_DIV1) || \ + ((x) == CLK_MCO_DIV2) || \ + ((x) == CLK_MCO_DIV4) || \ + ((x) == CLK_MCO_DIV8) || \ + ((x) == CLK_MCO_DIV16) || \ + ((x) == CLK_MCO_DIV32) || \ + ((x) == CLK_MCO_DIV64) || \ + ((x) == CLK_MCO_DIV128)) + +/* Parameter valid check for CLK MCO channel. */ +#define IS_CLK_MCO_CH(x) \ +( ((x) == CLK_MCO1) || \ + ((x) == CLK_MCO2)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CLK_Local_Functions CLK Local Functions + * @{ + */ +/** + * @brief Clk delay function + * @param [in] u32Delay count + * @retval when switch clock srouce,shoud be delay some time to wait stable. + */ +static void CLK_Delay(uint32_t u32Delay) +{ + __IO uint32_t u32Timeout = 0UL; + + while (u32Timeout < u32Delay) { + u32Timeout++; + } +} + +/** + * @brief Wait clock stable flag. + * @param [in] u8Flag Specifies the stable flag to be wait. @ref CLK_STB_Flag + * @param [in] u32Time Specifies the time to wait while the flag not be set. + * @retval int32_t + */ +static int32_t CLK_WaitStable(uint8_t u8Flag, uint32_t u32Time) +{ + __IO uint32_t u32Timeout = 0UL; + int32_t i32Ret = LL_ERR_TIMEOUT; + + while (u32Timeout <= u32Time) { + if (SET == CLK_GetStableStatus(u8Flag)) { + i32Ret = LL_OK; + break; + } + u32Timeout++; + } + return i32Ret; +} +/** + * @} + */ + +/** + * @defgroup CLK_Local_Functions CLK Local Functions + * @{ + */ +#ifdef __DEBUG +/* + * @note The pll_input/PLLM (VCOIN) must between 1 ~ 24MHz. + * The VCOIN*PLLN (VCOOUT) is between 240 ~ 480MHz. + * The PLLx frequency (VCOOUT/PLLxP_Q_R) is between 15 ~ 240MHz. +*/ +static void PLLxParamCheck(const stc_clock_pllx_init_t *pstcPLLxInit) +{ + uint32_t vcoIn; + uint32_t vcoOut; + + DDL_ASSERT(IS_CLK_PLLXM_DIV(pstcPLLxInit->PLLCFGR_f.PLLM + 1UL)); + DDL_ASSERT(IS_CLK_PLLXN_MULTI(pstcPLLxInit->PLLCFGR_f.PLLN + 1UL)); + DDL_ASSERT(IS_CLK_PLLXR_DIV(pstcPLLxInit->PLLCFGR_f.PLLR + 1UL)); + DDL_ASSERT(IS_CLK_PLLXQ_DIV(pstcPLLxInit->PLLCFGR_f.PLLQ + 1UL)); + DDL_ASSERT(IS_CLK_PLLXP_DIV(pstcPLLxInit->PLLCFGR_f.PLLP + 1UL)); + + vcoIn = ((CLK_PLL_SRC_XTAL == PLL_SRC ? + XTAL_VALUE : HRC_VALUE) / (pstcPLLxInit->PLLCFGR_f.PLLM + 1UL)); + vcoOut = vcoIn * (pstcPLLxInit->PLLCFGR_f.PLLN + 1UL); + + DDL_ASSERT(IS_CLK_PLLX_VCO_IN(vcoIn)); + DDL_ASSERT(IS_CLK_PLLX_VCO_OUT(vcoOut)); + DDL_ASSERT(IS_CLK_PLLX_FREQ(vcoOut / (pstcPLLxInit->PLLCFGR_f.PLLR + 1UL))); + DDL_ASSERT(IS_CLK_PLLX_FREQ(vcoOut / (pstcPLLxInit->PLLCFGR_f.PLLQ + 1UL))); + DDL_ASSERT(IS_CLK_PLLX_FREQ(vcoOut / (pstcPLLxInit->PLLCFGR_f.PLLP + 1UL))); + DDL_ASSERT(IS_CLK_PLLX_STATE(pstcPLLxInit->u8PLLState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); +} +#endif /* __DEBUG */ + +static void SetSysClockSrc(uint8_t u8Src) +{ + uint8_t u8TmpFlag = 0U; + /* backup FCGx setting */ + __IO uint32_t fcg0 = CM_PWC->FCG0; + __IO uint32_t fcg1 = CM_PWC->FCG1; + __IO uint32_t fcg2 = CM_PWC->FCG2; + __IO uint32_t fcg3 = CM_PWC->FCG3; + + DDL_ASSERT(IS_CLK_SYSCLK_SRC(u8Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Only current system clock source or target system clock source is PLLH + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW) || (CLK_SYSCLK_SRC_PLL == u8Src)) { + u8TmpFlag = 1U; + /* FCG0 protect judgment */ + DDL_ASSERT((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0); + /* Close FCGx. */ + WRITE_REG32(CM_PWC->FCG0, CLK_FCG0_DEFAULT); + WRITE_REG32(CM_PWC->FCG1, CLK_FCG1_DEFAULT); + WRITE_REG32(CM_PWC->FCG2, CLK_FCG2_DEFAULT); + WRITE_REG32(CM_PWC->FCG3, CLK_FCG3_DEFAULT); + + /* Wait stable after close FCGx. */ + CLK_Delay(CLK_SYSCLK_SW_STB); + } + + /* Set system clock source */ + WRITE_REG8(CM_CMU->CKSWR, u8Src); + + /* Wait stable after setting system clock source */ + CLK_Delay(CLK_SYSCLK_SW_STB); + + if (1U == u8TmpFlag) { + WRITE_REG32(CM_PWC->FCG0, fcg0); + WRITE_REG32(CM_PWC->FCG1, fcg1); + WRITE_REG32(CM_PWC->FCG2, fcg2); + WRITE_REG32(CM_PWC->FCG3, fcg3); + /* Wait stable after open fcg. */ + CLK_Delay(CLK_SYSCLK_SW_STB); + } +} + +static void GetClockFreq(stc_clock_freq_t *pstcClockFreq) +{ + stc_clock_scale_t *pstcClockScale; + uint32_t u32HrcValue; + uint32_t plln; + uint32_t pllp; + uint32_t pllm; + + switch (READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + case CLK_SYSCLK_SRC_HRC: + /* HRC is used to system clock */ + pstcClockFreq->u32SysclkFreq = HRC_VALUE; + break; + case CLK_SYSCLK_SRC_MRC: + /* MRC is used to system clock */ + pstcClockFreq->u32SysclkFreq = MRC_VALUE; + break; + case CLK_SYSCLK_SRC_LRC: + /* LRC is used to system clock */ + pstcClockFreq->u32SysclkFreq = LRC_VALUE; + break; + case CLK_SYSCLK_SRC_XTAL: + /* XTAL is used to system clock */ + pstcClockFreq->u32SysclkFreq = XTAL_VALUE; + break; + case CLK_SYSCLK_SRC_XTAL32: + /* XTAL32 is used to system clock */ + pstcClockFreq->u32SysclkFreq = HRC_VALUE; + break; + case CLK_SYSCLK_SRC_PLL: + /* PLLHP is used as system clock. */ + pllp = (uint32_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLP) >> CMU_PLLCFGR_MPLLP_POS); + plln = (uint32_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLN) >> CMU_PLLCFGR_MPLLN_POS); + pllm = (uint32_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLM) >> CMU_PLLCFGR_MPLLM_POS); + + /* fpll = ((pllin / pllm) * plln) / pllp */ + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + pstcClockFreq->u32SysclkFreq = ((XTAL_VALUE / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL); + } else { + u32HrcValue = HRC_VALUE; + pstcClockFreq->u32SysclkFreq = ((u32HrcValue / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL); + } + break; + default: + break; + } + + pstcClockScale = (stc_clock_scale_t *)((uint32_t)&CM_CMU->SCFGR); + pstcClockScale->SCFGR = READ_REG32(CM_CMU->SCFGR); + /* Get hclk. */ + pstcClockFreq->u32HclkFreq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.HCLKS; + /* Get pclk1. */ + pstcClockFreq->u32Pclk1Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK1S; + /* Get pclk4. */ + pstcClockFreq->u32Pclk4Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK4S; + /* Get pclk3. */ + pstcClockFreq->u32Pclk3Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK3S; + /* Get exck. */ + pstcClockFreq->u32ExclkFreq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.EXCKS; + /* Get pclk0. */ + pstcClockFreq->u32Pclk0Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK0S; + /* Get pclk2. */ + pstcClockFreq->u32Pclk2Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK2S; +} + +static void SetSysClockDiv(uint32_t u32Clock, uint32_t u32Div) +{ + uint8_t u8TmpFlag = 0U; + + /* backup FCGx setting */ + __IO uint32_t fcg0 = CM_PWC->FCG0; + __IO uint32_t fcg1 = CM_PWC->FCG1; + __IO uint32_t fcg2 = CM_PWC->FCG2; + __IO uint32_t fcg3 = CM_PWC->FCG3; + + DDL_ASSERT(IS_CLK_HCLK_DIV(u32Div & CMU_SCFGR_HCLKS)); + DDL_ASSERT(IS_CLK_PCLK1_DIV(u32Div & CMU_SCFGR_PCLK1S)); + DDL_ASSERT(IS_CLK_PCLK4_DIV(u32Div & CMU_SCFGR_PCLK4S)); + + DDL_ASSERT(IS_CLK_EXCLK_DIV(u32Div & CMU_SCFGR_EXCKS)); + DDL_ASSERT(IS_CLK_PCLK0_DIV(u32Div & CMU_SCFGR_PCLK0S)); + DDL_ASSERT(IS_CLK_PCLK2_DIV(u32Div & CMU_SCFGR_PCLK2S)); + DDL_ASSERT(IS_CLK_PCLK3_DIV(u32Div & CMU_SCFGR_PCLK3S)); + + DDL_ASSERT(IS_CLK_BUS_CLK_CATE(u32Clock)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Only current system clock source or target system clock source is PLLH + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + u8TmpFlag = 1U; + DDL_ASSERT((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0); + /* Close FCGx. */ + WRITE_REG32(CM_PWC->FCG0, CLK_FCG0_DEFAULT); + WRITE_REG32(CM_PWC->FCG1, CLK_FCG1_DEFAULT); + WRITE_REG32(CM_PWC->FCG2, CLK_FCG2_DEFAULT); + WRITE_REG32(CM_PWC->FCG3, CLK_FCG3_DEFAULT); + /* Wait stable after close FCGx. */ + CLK_Delay(CLK_SYSCLK_SW_STB); + } + + MODIFY_REG32(CM_CMU->SCFGR, u32Clock, u32Div); + CLK_Delay(CLK_SYSCLK_SW_STB); + + if (1U == u8TmpFlag) { + WRITE_REG32(CM_PWC->FCG0, fcg0); + WRITE_REG32(CM_PWC->FCG1, fcg1); + WRITE_REG32(CM_PWC->FCG2, fcg2); + WRITE_REG32(CM_PWC->FCG3, fcg3); + /* Wait stable after open fcg. */ + CLK_Delay(CLK_SYSCLK_SW_STB); + } +} + +/** +* @} +*/ + +/** + * @defgroup CLK_Global_Functions CLK Global Functions + * @{ + */ +/** + * @brief LRC function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: LRC operate successfully + * - LL_ERR_BUSY: LRC is the system clock, CANNOT stop it. + * @note DO NOT STOP LRC while using it as system clock. + */ +int32_t CLK_LrcCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_LRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->LRCCR, CLK_LRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->LRCCR, CLK_LRC_ON); + + CLK_Delay(CLK_LRC_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief MRC function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: MRC operate successfully + * - LL_ERR_BUSY: MRC is the system clock, CANNOT stop it. + * @note DO NOT STOP MRC while using it as system clock. + */ +int32_t CLK_MrcCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_MRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->MRCCR, CLK_MRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->MRCCR, CLK_MRC_ON); + + CLK_Delay(CLK_MRC_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief HRC function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: HRC operate successfully + * - LL_ERR_BUSY: HRC is the system clock or as the PLL source clock, CANNOT stop it. + * - LL_ERR_TIMEOUT: HRC operate Timeout + * @note DO NOT STOP HRC while using it as system clock or as the PLL source clock. + */ +int32_t CLK_HrcCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_HRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else if (CLK_PLL_SRC_HRC == PLL_SRC) { + /* HRC as PLL clock source and PLL is working */ + if (0UL == PLL_EN_REG) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_HRC, CLK_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief Set HRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for HRC. + * @retval None + */ +void CLK_HrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->HRCTRM, i8TrimVal); +} + +/** + * @brief Set MRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for MRC. + * @retval None + */ +void CLK_MrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->MRCTRM, i8TrimVal); +} + +/** + * @brief Set LRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for LRC. + * @retval None + */ +void CLK_LrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->LRCTRM, i8TrimVal); +} + +/** + * @brief Init Xtal initial structure with default value. + * @param [in] pstcXtalInit specifies the Parameter of XTAL. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_XtalStructInit(stc_clock_xtal_init_t *pstcXtalInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcXtalInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcXtalInit->u8State = CLK_XTAL_OFF; + pstcXtalInit->u8Mode = CLK_XTAL_MD_OSC; + pstcXtalInit->u8Drv = CLK_XTAL_DRV_HIGH; + pstcXtalInit->u8SuperDrv = CLK_XTAL_SUPDRV_ON; + pstcXtalInit->u8StableTime = CLK_XTAL_STB_2MS; + } + return i32Ret; +} + +/** + * @brief XTAL initialize. + * @param [in] pstcXtalInit specifies the XTAL initial config. + * @arg u8State : The new state of the XTAL. + * @arg u8Drv : The XTAL drive ability. + * @arg u8Mode : The XTAL mode selection osc or exclk. + * @arg u8StableTime : The XTAL stable time selection. + * @retval int32_t: + * - LL_OK: XTAL initial successfully. + * - LL_ERR_TIMEOUT: XTAL operate timeout. + * - LL_ERR_BUSY: XTAL is the system clock, CANNOT stop it. + * - LL_ERR_INVD_PARAM: NULL pointer. + * @note DO NOT STOP XTAL while using it as system clock. + */ +int32_t CLK_XtalInit(const stc_clock_xtal_init_t *pstcXtalInit) +{ + int32_t i32Ret; + + if (NULL == pstcXtalInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_CLK_XTAL_STATE(pstcXtalInit->u8State)); + DDL_ASSERT(IS_CLK_XTAL_DRV_MD(pstcXtalInit->u8Drv)); + DDL_ASSERT(IS_CLK_XTAL_MD(pstcXtalInit->u8Mode)); + DDL_ASSERT(IS_CLK_XTAL_SUPDRV_STATE(pstcXtalInit->u8SuperDrv)); + DDL_ASSERT(IS_CLK_XTAL_STB_SEL(pstcXtalInit->u8StableTime)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->XTALSTBCR, pstcXtalInit->u8StableTime); + + WRITE_REG8(CM_CMU->XTALCFGR, (pstcXtalInit->u8SuperDrv | pstcXtalInit->u8Drv | pstcXtalInit->u8Mode)); + + if (CLK_XTAL_ON == pstcXtalInit->u8State) { + i32Ret = CLK_XtalCmd(ENABLE); + } else { + i32Ret = CLK_XtalCmd(DISABLE); + } + } + + return i32Ret; +} + +/** + * @brief XTAL function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: XTAL operate successfully + * - LL_ERR_BUSY: XTAL is the system clock or as the PLL source clock, CANNOT stop it. + * - LL_ERR_TIMEOUT: XTAL operate timeout. + * @note DO NOT STOP XTAL while using it as system clock or as the PLL source clock. + */ +int32_t CLK_XtalCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_XTAL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } + /* XTAL as PLL clock source and PLL is working */ + else if (CLK_PLL_SRC_XTAL == PLL_SRC) { + if (0UL == PLL_EN_REG) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_OFF); + } + } else { + WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_OFF); + } + } else { + WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_XTAL, CLK_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief Init XtalStd initial structure with default value. + * @param [in] pstcXtalStdInit specifies the Parameter of XTALSTD. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t CLK_XtalStdStructInit(stc_clock_xtalstd_init_t *pstcXtalStdInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcXtalStdInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcXtalStdInit->u8State = CLK_XTALSTD_OFF; + pstcXtalStdInit->u8Mode = CLK_XTALSTD_MD_INT; + pstcXtalStdInit->u8Int = CLK_XTALSTD_INT_OFF; + pstcXtalStdInit->u8Reset = CLK_XTALSTD_RST_OFF; + } + + return i32Ret; +} + +/** + * @brief Initialise the XTAL status detection. + * @param [in] pstcXtalStdInit specifies the Parameter of XTALSTD. + * @arg u8State: The new state of the XTALSTD. + * @arg u8Mode: The XTAL status detection occur interrupt or reset. + * @arg u8Int: The XTAL status detection interrupt on or off. + * @arg u8Reset: The XTAL status detection reset on or off. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t CLK_XtalStdInit(const stc_clock_xtalstd_init_t *pstcXtalStdInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcXtalStdInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter valid check */ + DDL_ASSERT(IS_CLK_XTALSTD_STATE(pstcXtalStdInit->u8State)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Parameter valid check */ + DDL_ASSERT(IS_CLK_XTALSTD_MD(pstcXtalStdInit->u8Mode)); + DDL_ASSERT(IS_CLK_XTALSTD_INT_STATE(pstcXtalStdInit->u8Int)); + DDL_ASSERT(IS_CLK_XTALSTD_RST_STATE(pstcXtalStdInit->u8Reset)); + + /* Configure and enable XTALSTD */ + WRITE_REG8(CM_CMU->XTALSTDCR, (pstcXtalStdInit->u8State | \ + pstcXtalStdInit->u8Mode | \ + pstcXtalStdInit->u8Int | \ + pstcXtalStdInit->u8Reset)); + } + + return i32Ret; +} + +/** + * @brief Clear the XTAL error flag. + * @param None + * @retval None + * @note The system clock should not be XTAL before call this function. + */ +void CLK_ClearXtalStdStatus(void) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (0x01U == READ_REG8(CM_CMU->XTALSTDSR)) { + /* Clear the XTAL STD flag */ + WRITE_REG8(CM_CMU->XTALSTDSR, 0x00U); + } +} + +/** + * @brief Get the XTAL error flag. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CLK_GetXtalStdStatus(void) +{ + return ((0x00U != READ_REG32(CM_CMU->XTALSTDSR)) ? SET : RESET); +} + +/** + * @brief Init Xtal32 initial structure with default value. + * @param [in] pstcXtal32Init specifies the Parameter of XTAL32. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_Xtal32StructInit(stc_clock_xtal32_init_t *pstcXtal32Init) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcXtal32Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcXtal32Init->u8State = CLK_XTAL32_ON; + pstcXtal32Init->u8Drv = CLK_XTAL32_DRV_MID; + pstcXtal32Init->u8Filter = CLK_XTAL32_FILTER_ALL_MD; + } + + return i32Ret; +} + +/** + * @brief XTAL32 initialize. + * @param [in] pstcXtal32Init specifies the XTAL32 initial config. + * @arg u8State : The new state of the XTAL32. + * @arg u8Drv : The XTAL32 drive capacity. + * @arg u8Filter : The XTAL32 noise filter on or off. + * @retval int32_t: + * - LL_OK: XTAL32 initial successfully. + * - LL_ERR_BUSY: XTAL32 is the system clock, CANNOT stop it. + * - LL_ERR_INVD_PARAM: NULL pointer. + * @note DO NOT STOP XTAL32 while using it as system clock. + */ +int32_t CLK_Xtal32Init(const stc_clock_xtal32_init_t *pstcXtal32Init) +{ + int32_t i32Ret; + + if (NULL == pstcXtal32Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameters check */ + DDL_ASSERT(IS_CLK_XTAL32_STATE(pstcXtal32Init->u8State)); + DDL_ASSERT(IS_CLK_XTAL32_DRV_MD(pstcXtal32Init->u8Drv)); + DDL_ASSERT(IS_CLK_XTAL32_FILT_SEL(pstcXtal32Init->u8Filter)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->XTAL32CFGR, pstcXtal32Init->u8Drv); + WRITE_REG8(CM_CMU->XTAL32NFR, pstcXtal32Init->u8Filter); + + if (CLK_XTAL32_ON == pstcXtal32Init->u8State) { + i32Ret = CLK_Xtal32Cmd(ENABLE); + } else { + i32Ret = CLK_Xtal32Cmd(DISABLE); + } + } + + return i32Ret; +} + +/** + * @brief XTAL32 function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: XTAL32 operate successfully + * - LL_ERR_BUSY: XTAL32 is the system clock, CANNOT stop it. + * @note DO NOT STOP XTAL32 while using it as system clock. + */ +int32_t CLK_Xtal32Cmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_XTAL32 == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->XTAL32CR, CLK_XTAL32_OFF); + } + } else { + WRITE_REG8(CM_CMU->XTAL32CR, CLK_XTAL32_ON); + /* wait stable*/ + CLK_Delay(CLK_XTAL32_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief Set PLL source clock. + * @param [in] u32PllSrc PLL source clock. + * @arg CLK_PLL_SRC_XTAL + * @arg CLK_PLL_SRC_HRC + * @retval None + */ +void CLK_SetPLLSrc(uint32_t u32PllSrc) +{ + DDL_ASSERT(IS_CLK_PLL_SRC(u32PllSrc)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG32(PLL_SRC_REG, PLL_SRC_BIT, u32PllSrc << PLL_SRC_POS); +} + +/** + * @brief Init PLL initial structure with default value. + * @param [in] pstcPLLInit specifies the Parameter of PLL. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_PLLStructInit(stc_clock_pll_init_t *pstcPLLInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPLLInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcPLLInit->PLLCFGR = 0UL; + pstcPLLInit->PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; + pstcPLLInit->PLLCFGR_f.PLLM = CLK_PLLM_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLN = CLK_PLLN_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLP = CLK_PLLP_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLQ = CLK_PLLQ_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLR = CLK_PLLR_DEFAULT; + pstcPLLInit->u8PLLState = CLK_PLL_OFF; + } + return i32Ret; +} + +/** + * @brief PLLH initialize. + * @param [in] pstcPLLInit specifies the structure of PLLH initial config. + * @arg u8PLLState : The new state of the PLLH. + * @arg PLLCFGR : PLLH config. + * @retval int32_t: + * - LL_OK: PLLH initial successfully + * - LL_ERR_TIMEOUT: PLLH initial timeout + * - LL_ERR_BUSY: PLLH is the source clock, CANNOT stop it. + * - LL_ERR_INVD_PARAM: NULL pointer + * @note The pll_input/PLLM (VCOIN) must between 8 ~ 24MHz. + * The VCOIN*PLLN (VCOOUT) is between 600 ~ 1200MHz. + * The PLLH frequency (VCOOUT/PLLHP_Q_R) is between 40 ~ 240MHz. + */ +int32_t CLK_PLLInit(const stc_clock_pll_init_t *pstcPLLInit) +{ + int32_t i32Ret; + +#ifdef __DEBUG + uint32_t vcoIn; + uint32_t vcoOut; +#endif + + if (NULL == pstcPLLInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { +#ifdef __DEBUG + DDL_ASSERT(IS_CLK_PLL_SRC(pstcPLLInit->PLLCFGR_f.PLLSRC)); + DDL_ASSERT(IS_CLK_PLLM_DIV(pstcPLLInit->PLLCFGR_f.PLLM + 1UL)); + DDL_ASSERT(IS_CLK_PLLN_MULTI(pstcPLLInit->PLLCFGR_f.PLLN + 1UL)); + DDL_ASSERT(IS_CLK_PLLP_DIV(pstcPLLInit->PLLCFGR_f.PLLP + 1UL)); + + vcoIn = ((CLK_PLL_SRC_XTAL == pstcPLLInit->PLLCFGR_f.PLLSRC ? + XTAL_VALUE : HRC_VALUE) / (pstcPLLInit->PLLCFGR_f.PLLM + 1UL)); + vcoOut = vcoIn * (pstcPLLInit->PLLCFGR_f.PLLN + 1UL); + + DDL_ASSERT(IS_CLK_PLL_VCO_IN(vcoIn)); + DDL_ASSERT(IS_CLK_PLL_VCO_OUT(vcoOut)); + DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLP + 1UL))); + DDL_ASSERT(IS_CLK_PLLQ_DIV(pstcPLLInit->PLLCFGR_f.PLLQ + 1UL)); + DDL_ASSERT(IS_CLK_PLLR_DIV(pstcPLLInit->PLLCFGR_f.PLLR + 1UL)); + DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLR + 1UL))); + DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLQ + 1UL))); + DDL_ASSERT(IS_CLK_PLL_STATE(pstcPLLInit->u8PLLState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); +#endif /* __DEBUG */ + + /* set PLL source in advance */ + MODIFY_REG32(PLL_SRC_REG, PLL_SRC_BIT, pstcPLLInit->PLLCFGR_f.PLLSRC << PLL_SRC_POS); + WRITE_REG32(CM_CMU->PLLCFGR, pstcPLLInit->PLLCFGR); + + if (CLK_PLL_ON == pstcPLLInit->u8PLLState) { + i32Ret = CLK_PLLCmd(ENABLE); + } else { + i32Ret = CLK_PLLCmd(DISABLE); + } + } + + return i32Ret; +} + +/** + * @brief PLL function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: PLL operate successfully + * - LL_ERR_BUSY: PLL is the system clock, CANNOT stop it. + * - LL_ERR_TIMEOUT: PLL operate timeout + * @note DO NOT STOP PLL while using it as system clock. + */ +int32_t CLK_PLLCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(PLL_EN_REG, CLK_PLL_OFF); + } + } else { + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + i32Ret = CLK_WaitStable(CLK_STB_FLAG_XTAL, CLK_TIMEOUT); + } else { + i32Ret = CLK_WaitStable(CLK_STB_FLAG_HRC, CLK_TIMEOUT); + } + if (LL_OK == i32Ret) { + WRITE_REG8(PLL_EN_REG, CLK_PLL_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_PLL, CLK_TIMEOUT); + } + } + + return i32Ret; +} + +/** + * @brief Init PLLx initial structure with default value. + * @param [in] pstcPLLxInit specifies the Parameter of PLLx. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + * @note Pllx for UPLL while HC32F460, HC32F451, HC32F452 + * Pllx for PLLA while HC32F4A0 + */ +int32_t CLK_PLLxStructInit(stc_clock_pllx_init_t *pstcPLLxInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPLLxInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcPLLxInit->PLLCFGR = 0UL; + pstcPLLxInit->u8PLLState = CLK_PLLX_OFF; + pstcPLLxInit->PLLCFGR_f.PLLP = CLK_PLLXP_DEFAULT; + pstcPLLxInit->PLLCFGR_f.PLLQ = CLK_PLLXQ_DEFAULT; + pstcPLLxInit->PLLCFGR_f.PLLR = CLK_PLLXR_DEFAULT; + pstcPLLxInit->PLLCFGR_f.PLLN = CLK_PLLXN_DEFAULT; + pstcPLLxInit->PLLCFGR_f.PLLM = CLK_PLLXM_DEFAULT; + } + return i32Ret; +} + +/** + * @brief PLLx Initialize. + * @param [in] pstcPLLxInit specifies the structure of UPLL initial config. + * @arg u8PLLState : The new state of the UPLL. + * @arg PLLCFGR : UPLL config. + * @retval int32_t: + * - LL_OK: UPLL initial successfully + * - LL_ERR_TIMEOUT: UPLL initial timeout + * - LL_ERR_INVD_PARAM: NULL pointer + * @note The pll_input/PLLM (VCOIN) must between 1 ~ 24MHz. + * The VCOIN*PLLN (VCOOUT) is between 240 ~ 480MHz. + * The UPLL frequency (VCOOUT/UPLLP_Q_R) is between 15 ~ 240MHz. + */ +int32_t CLK_PLLxInit(const stc_clock_pllx_init_t *pstcPLLxInit) +{ + int32_t i32Ret; + + if (NULL == pstcPLLxInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { +#ifdef __DEBUG + PLLxParamCheck(pstcPLLxInit); +#endif + + WRITE_REG32(CM_CMU->UPLLCFGR, pstcPLLxInit->PLLCFGR); + + if (CLK_PLLX_ON == pstcPLLxInit->u8PLLState) { + i32Ret = CLK_PLLxCmd(ENABLE); + } else { + i32Ret = CLK_PLLxCmd(DISABLE); + } + } + return i32Ret; +} + +/** + * @brief PLLx function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: UPLL operate successfully + * - LL_ERR_TIMEOUT: UPLL operate timeout + * @note PLLx for UPLL while HC32F460, HC32F451, HC32F452 + * PLLx for PLLA while HC32F4A0 + */ +int32_t CLK_PLLxCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + WRITE_REG8(PLLX_EN_REG, CLK_PLLX_OFF); + } else { + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + i32Ret = CLK_WaitStable(CLK_STB_FLAG_XTAL, CLK_TIMEOUT); + } else { + i32Ret = CLK_WaitStable(CLK_STB_FLAG_HRC, CLK_TIMEOUT); + } + if (LL_OK == i32Ret) { + WRITE_REG8(PLLX_EN_REG, CLK_PLLX_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_PLLX, CLK_TIMEOUT); + } + } + + return i32Ret; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param [in] u8Ch Specifies the MCO channel. @ref CLK_MCO_Channel_Sel + * @param [in] u8Src Specifies the clock source to output. @ref CLK_MCO_Clock_Source + * @param [in] u8Div Specifies the MCOx prescaler. @ref CLK_MCO_Clock_Prescaler + * @retval None + * @note MCO pin should be configured in alternate function 1 mode. + */ +void CLK_MCOConfig(uint8_t u8Ch, uint8_t u8Src, uint8_t u8Div) +{ + __IO uint8_t *MCOCFGRx; + + /* Check the parameters. */ + DDL_ASSERT(IS_CLK_MCO_SRC(u8Src)); + DDL_ASSERT(IS_CLK_MCO_DIV(u8Div)); + DDL_ASSERT(IS_CLK_MCO_CH(u8Ch)); + /* enable register write. */ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MCOCFGRx = &(*(__IO uint8_t *)((uint32_t)&CM_CMU->MCOCFGR1 + u8Ch)); + + /* Config the MCO */ + MODIFY_REG8(*MCOCFGRx, (CMU_MCOCFGR_MCOSEL | CMU_MCOCFGR_MCODIV), (u8Src | u8Div)); +} + +/** + * @brief Enable or disable the MCO1 output. + * @param [in] u8Ch Specifies the MCO channel. @ref CLK_MCO_Channel_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CLK_MCOCmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + __IO uint8_t *MCOCFGRx; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + DDL_ASSERT(IS_CLK_MCO_CH(u8Ch)); + + MCOCFGRx = &(*(__IO uint8_t *)((uint32_t)&CM_CMU->MCOCFGR1 + u8Ch)); + + /* Enable or disable clock output. */ + MODIFY_REG8(*MCOCFGRx, CMU_MCOCFGR_MCOEN, (uint8_t)enNewState << CMU_MCOCFGR_MCOEN_POS); +} + +/** + * @brief PLL/XTAL/HRC stable flag read. + * @param [in] u8Flag specifies the stable flag to be read. @ref CLK_STB_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CLK_GetStableStatus(uint8_t u8Flag) +{ + DDL_ASSERT(IS_CLK_STB_FLAG(u8Flag)); + + return ((0x00U != READ_REG8_BIT(CM_CMU->OSCSTBSR, u8Flag)) ? SET : RESET); +} + +/** + * @brief Set the system clock source. + * @param [in] u8Src specifies the source of system clock. @ref CLK_System_Clock_Source + * @retval None + */ +void CLK_SetSysClockSrc(uint8_t u8Src) +{ + /* Set system clock source */ + SetSysClockSrc(u8Src); + /* Update system clock */ + SystemCoreClockUpdate(); +} + +/** + * @brief Get bus clock frequency. + * @param [out] pstcClockFreq specifies the pointer to get bus frequency. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_GetClockFreq(stc_clock_freq_t *pstcClockFreq) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcClockFreq) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + GetClockFreq(pstcClockFreq); + } + return i32Ret; +} + +/** + * @brief Get bus clock frequency. + * @param [in] u32Clock specifies the bus clock to get frequency. @ref CLK_Bus_Clock_Sel + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +uint32_t CLK_GetBusClockFreq(uint32_t u32Clock) +{ + uint32_t u32ClockFreq; + DDL_ASSERT(IS_CLK_BUS_CLK(u32Clock)); + + switch (u32Clock) { + case CLK_BUS_HCLK: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS); + break; + case CLK_BUS_PCLK1: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS); + break; + case CLK_BUS_PCLK4: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK4S) >> CMU_SCFGR_PCLK4S_POS); + break; + case CLK_BUS_PCLK3: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK3S) >> CMU_SCFGR_PCLK3S_POS); + break; + case CLK_BUS_EXCLK: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_EXCKS) >> CMU_SCFGR_EXCKS_POS); + break; + case CLK_BUS_PCLK0: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK0S) >> CMU_SCFGR_PCLK0S_POS); + break; + case CLK_BUS_PCLK2: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK2S) >> CMU_SCFGR_PCLK2S_POS); + break; + default: + u32ClockFreq = SystemCoreClock; + break; + } + return u32ClockFreq; +} + +/** + * @brief Get PLL clock frequency. + * @param [out] pstcPllClkFreq specifies the pointer to get PLL frequency. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + * @note PLL for MPLL, PLLx for UPLL while HC32F460, HC32F451, HC32F452 + * PLL for PLLH, PLLx for PLLA while HC32F4A0 + */ +int32_t CLK_GetPLLClockFreq(stc_pll_clock_freq_t *pstcPllClkFreq) +{ + int32_t i32Ret = LL_OK; + uint32_t pllin; + uint32_t plln; + uint32_t pllm; + uint32_t pllp; + uint32_t pllq; + uint32_t pllr; + uint32_t pllxn; + uint32_t pllxm; + uint32_t pllxp; + uint32_t pllxq; + uint32_t pllxr; + + if (NULL == pstcPllClkFreq) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pllp = (uint32_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLP) >> CMU_PLLCFGR_MPLLP_POS); + pllq = (uint32_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLQ) >> CMU_PLLCFGR_MPLLQ_POS); + pllr = (uint32_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLR) >> CMU_PLLCFGR_MPLLR_POS); + plln = (uint32_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLN) >> CMU_PLLCFGR_MPLLN_POS); + pllm = (uint32_t)((CM_CMU->PLLCFGR & CMU_PLLCFGR_MPLLM) >> CMU_PLLCFGR_MPLLM_POS); + + pllxp = (uint32_t)((CM_CMU->UPLLCFGR & CMU_UPLLCFGR_UPLLP) >> CMU_UPLLCFGR_UPLLP_POS); + pllxq = (uint32_t)((CM_CMU->UPLLCFGR & CMU_UPLLCFGR_UPLLQ) >> CMU_UPLLCFGR_UPLLQ_POS); + pllxr = (uint32_t)((CM_CMU->UPLLCFGR & CMU_UPLLCFGR_UPLLR) >> CMU_UPLLCFGR_UPLLR_POS); + pllxn = (uint32_t)((CM_CMU->UPLLCFGR & CMU_UPLLCFGR_UPLLN) >> CMU_UPLLCFGR_UPLLN_POS); + pllxm = (uint32_t)((CM_CMU->UPLLCFGR & CMU_UPLLCFGR_UPLLM) >> CMU_UPLLCFGR_UPLLM_POS); + + /* PLLHP is used as system clock. */ + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + pllin = XTAL_VALUE; + } else { + pllin = HRC_VALUE; + } + + pstcPllClkFreq->u32PllVcin = (pllin / (pllm + 1UL)); + pstcPllClkFreq->u32PllVco = ((pllin / (pllm + 1UL)) * (plln + 1UL)); + pstcPllClkFreq->u32PllP = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL); + + pstcPllClkFreq->u32PllQ = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllq + 1UL); + pstcPllClkFreq->u32PllR = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllr + 1UL); + pstcPllClkFreq->u32PllxVcin = (pllin / (pllxm + 1UL)); + pstcPllClkFreq->u32PllxVco = ((pllin / (pllxm + 1UL)) * (pllxn + 1UL)); + pstcPllClkFreq->u32PllxP = ((pllin / (pllxm + 1UL)) * (pllxn + 1UL)) / (pllxp + 1UL); + pstcPllClkFreq->u32PllxQ = ((pllin / (pllxm + 1UL)) * (pllxn + 1UL)) / (pllxq + 1UL); + pstcPllClkFreq->u32PllxR = ((pllin / (pllxm + 1UL)) * (pllxn + 1UL)) / (pllxr + 1UL); + } + return i32Ret; +} + +/** + * @brief HCLK/PCLK divide setting. + * @param [in] u32Clock specifies the clock to be divided. @ref CLK_Bus_Clock_Sel + * @param [in] u32Div specifies the clock divide factor. @ref CLK_Clock_Divider + * @retval None + * @note u32Div could choose CLK_HCLK_Divider, CLK_PCLK0_Divider, CLK_PCLK1_Divider, + * CLK_PCLK2_Divider, CLK_PCLK3_Divider, CLK_PCLK4_Divider, CLK_EXCLK_Divider, according to the MCU + */ +void CLK_SetClockDiv(uint32_t u32Clock, uint32_t u32Div) +{ + /* Set clock divider */ + SetSysClockDiv(u32Clock, u32Div); + + /* Update system clock */ + SystemCoreClockUpdate(); +} + +/** + * @brief Set peripheral clock source. + * @param [in] u16Src specifies the peripheral clock source. @ref CLK_PERIPH_Sel + * @retval None + * @note peripheral for ADC/DAC/TRNG while HC32F460,HC32F4A0, HC32F451, HC32F452 + * peripheral only for ADC while HC32M423,HC32F120,HC32F160,HC32M120 + */ +void CLK_SetPeriClockSrc(uint16_t u16Src) +{ + DDL_ASSERT(IS_CLK_PERIPHCLK_SRC(u16Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->PERICKSEL, u16Src); +} + +/** + * @brief USB clock source config. + * @param [in] u8Src specifies the USB clock source. @ref CLK_USBCLK_Sel + * @retval None + */ +void CLK_SetUSBClockSrc(uint8_t u8Src) +{ + DDL_ASSERT(IS_CLK_USBCLK_SRC(u8Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->USBCKCFGR, u8Src); +} + +/** + * @brief I2S clock source config. + * @param [in] u8Unit specifies the I2S channel for clock source. @ref CLK_I2S_Sel + * @arg CLK_I2S1: I2S Channel 1 + * @arg CLK_I2S2: I2S Channel 2 + * @arg CLK_I2S3: I2S Channel 3 + * @arg CLK_I2S4: I2S Channel 4 + * @param [in] u8Src specifies the I2S clock source. @ref CLK_PERIPH_Sel + * @retval None + */ +void CLK_SetI2SClockSrc(uint8_t u8Unit, uint8_t u8Src) +{ + DDL_ASSERT(IS_CLK_I2S_UNIT(u8Unit)); + DDL_ASSERT(IS_CLK_PERIPHCLK_SRC(u8Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG16(CM_CMU->I2SCKSEL, (uint16_t)CMU_I2SCKSEL_I2S1CKSEL << (u8Unit * CMU_I2SCKSEL_I2S2CKSEL_POS), \ + (uint16_t)u8Src << (u8Unit * CMU_I2SCKSEL_I2S2CKSEL_POS)); +} + +/** + * @brief Enable or disable the TPIU clock. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CLK_TpiuClockCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG8(CM_CMU->TPIUCKCFGR, CMU_TPIUCKCFGR_TPIUCKOE, (uint8_t)enNewState << CMU_TPIUCKCFGR_TPIUCKOE_POS); +} + +/** + * @brief TPIU clock divider config. + * @param [in] u8Div specifies the TPIU clock divide factor. @ref CLK_TPIU_Divider + * @arg CLK_TPIUCLK_DIV1: TPIU clock no divide + * @arg CLK_TPIUCLK_DIV2: TPIU clock divide by 2 + * @arg CLK_TPIUCLK_DIV4: TPIU clock divide by 4 + * @retval None + */ +void CLK_SetTpiuClockDiv(uint8_t u8Div) +{ + DDL_ASSERT(IS_CLK_TPIUCLK_DIV(u8Div)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG8(CM_CMU->TPIUCKCFGR, CMU_TPIUCKCFGR_TPIUCKS, u8Div); +} +/** + * @} + */ + +#endif /* LL_CLK_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_cmp.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_cmp.c new file mode 100644 index 0000000000..43f9e30cab --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_cmp.c @@ -0,0 +1,698 @@ +/** + ******************************************************************************* + * @file hc32_ll_cmp.c + * @brief This file provides firmware functions to manage the Comparator(CMP). + * + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_cmp.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CMP CMP + * @brief CMP Driver Library + * @{ + */ + +#if (LL_CMP_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CMP_Local_Macros CMP Local Macros + * @{ + */ + +/** + * @defgroup CMP_Check_Parameters_Validity CMP Check Parameters Validity + * @{ + */ +#define IS_CMP_UNIT(x) \ +( ((x) == CM_CMP1) || \ + ((x) == CM_CMP2) || \ + ((x) == CM_CMP3)) + +#define CMP1_INP4_MASK (CMP1_POSITIVE_PGAO | \ + CMP1_POSITIVE_PGAO_BP | \ + CMP1_POSITIVE_CMP1_INP4) +#define CMP1_POSITIVE_MASK (CMP_POSITIVE_NONE | \ + CMP1_POSITIVE_CMP1_INP1 | \ + CMP1_POSITIVE_CMP1_INP2 | \ + CMP1_POSITIVE_CMP1_INP3 | \ + CMP1_INP4_MASK) + +#define CMP2_INP4_MASK (CMP2_POSITIVE_PGAO | \ + CMP2_POSITIVE_PGAO_BP) +#define CMP2_POSITIVE_MASK (CMP_POSITIVE_NONE | \ + CMP2_POSITIVE_CMP2_INP1 | \ + CMP2_POSITIVE_CMP2_INP2 | \ + CMP2_POSITIVE_CMP2_INP3 | \ + CMP2_INP4_MASK) + +#define CMP3_POSITIVE_MASK (CMP_POSITIVE_NONE | \ + CMP3_POSITIVE_CMP3_INP1 | \ + CMP3_POSITIVE_CMP3_INP2 | \ + CMP3_POSITIVE_CMP3_INP3 | \ + CMP3_POSITIVE_CMP3_INP4) + +#define IS_CMP1_POSITIVE_IN(x) \ +( (((x) & (~CMP1_POSITIVE_MASK)) == 0U) && \ + ((((x) & CMP1_INP4_MASK) == 0U) || \ + (((x) & CMP1_INP4_MASK) == CMP1_POSITIVE_PGAO) || \ + (((x) & CMP1_INP4_MASK) == CMP1_POSITIVE_PGAO_BP) || \ + (((x) & CMP1_INP4_MASK) == CMP1_POSITIVE_CMP1_INP4))) + +#define IS_CMP2_POSITIVE_IN(x) \ +( (((x) & (~CMP2_POSITIVE_MASK)) == 0U) && \ + ((((x) & CMP2_INP4_MASK) == 0U) || \ + (((x) & CMP2_INP4_MASK) == CMP2_POSITIVE_PGAO) || \ + (((x) & CMP2_INP4_MASK) == CMP2_POSITIVE_PGAO_BP))) + +#define IS_CMP3_POSITIVE_IN(x) \ +( ((x) & (~CMP3_POSITIVE_MASK)) == 0U) + +#define IS_CMP_NEGATIVE_IN(x) \ +( ((x) == CMP_NEGATIVE_NONE) || \ + ((x) == CMP1_NEGATIVE_CMP1_INM1) || \ + ((x) == CMP1_NEGATIVE_CMP1_INM2) || \ + ((x) == CMP1_NEGATIVE_DAC1) || \ + ((x) == CMP1_NEGATIVE_VREF)) + +#define IS_CMP_SCAN_STABLE(x) \ +( (x) < 16U) + +#define IS_CMP_SCAN_PERIOD(x) \ +( (x) >= 0xFU) + +#define IS_CMP_8_BIT_DAC_CH(x) \ +( ((x) == CMP_8BITDAC_CH1) || \ + ((x) == CMP_8BITDAC_CH2)) + +#define IS_CMP_8_BIT_DAC_DATA(x) \ +( (x) <= 0xFFU) + +#define IS_CMP_8_BIT_DAC_SW(x) \ +( ((x) == CMP_ADC_REF_VREF) || \ + ((x) == CMP_ADC_REF_DA2) || \ + ((x) == CMP_ADC_REF_DA1)) + +#define IS_CMP_OUT_POLARITY(x) \ +( ((x) == CMP_OUT_INVT_OFF) || \ + ((x) == CMP_OUT_INVT_ON)) + +#define IS_CMP_OUT_FILTER(x) \ +( ((x) == CMP_OUT_FILTER_NONE) || \ + ((x) == CMP_OUT_FILTER_CLK) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV2) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV4) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV8) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV16) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV32) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV64)) + +#define IS_CMP_OUT_DETECT_EDGE(x) \ +( ((x) == CMP_DETECT_EDGS_NONE) || \ + ((x) == CMP_DETECT_EDGS_RISING) || \ + ((x) == CMP_DETECT_EDGS_FALLING) || \ + ((x) == CMP_DETECT_EDGS_BOTH)) + +/** + * @} + */ +#define CMP_DADC_RVADC_REG_UNLOCK (0x5500U) +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CMP_Local_Functions CMP Local Functions + * @{ + */ + +/** + * @brief Delay function, delay us approximately + * @param [in] u32Count us + * @retval None + */ +static void CMP_DelayUS(uint32_t u32Count) +{ + __IO uint32_t i; + const uint32_t u32Cyc = HCLK_VALUE / 10000000UL; + + while (u32Count-- > 0UL) { + i = u32Cyc; + while (i-- > 0UL) { + ; + } + } +} + +/** + * @brief Get CMP function status and disable CMP + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval uint16_t The register value + */ +static uint16_t GetCmpFuncStatusAndDisFunc(CM_CMP_TypeDef *CMPx) +{ + uint16_t u16temp; + /* Read CMP status */ + u16temp = READ_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPON); + /* Stop CMP function */ + CLR_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPON); + return u16temp; +} + +/** + * @brief Revcover CMP function status + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16CmpFuncStatus CMP function status backup value + * @retval None + */ +static void RecoverCmpFuncStatus(CM_CMP_TypeDef *CMPx, uint16_t u16CmpFuncStatus) +{ + if (u16CmpFuncStatus != 0U) { + /* Recover CMP status */ + MODIFY_REG16(CMPx->CTRL, CMP_CTRL_CMPON, u16CmpFuncStatus); + /* Delay 1us */ + CMP_DelayUS(1U); + } +} + +/** + * @} + */ + +/** + * @defgroup CMP_Global_Functions CMP Global Functions + * @{ + */ + +/** + * @brief Initialize structure stc_cmp_init_t variable with default value. + * @param [in] pstcCmpInit Pointer to a structure variable which will be initialized. @ref stc_cmp_init_t + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_StructInit(stc_cmp_init_t *pstcCmpInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (pstcCmpInit != NULL) { + pstcCmpInit->u16PositiveInput = CMP_POSITIVE_NONE; + pstcCmpInit->u16NegativeInput = CMP_NEGATIVE_NONE; + pstcCmpInit->u16OutPolarity = CMP_OUT_INVT_OFF; + pstcCmpInit->u16OutDetectEdge = CMP_DETECT_EDGS_NONE; + pstcCmpInit->u16OutFilter = CMP_OUT_FILTER_NONE; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief De-initialize CMP unit + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval None + */ +void CMP_DeInit(CM_CMP_TypeDef *CMPx) +{ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + + CLR_REG16(CMPx->CTRL); + CLR_REG16(CMPx->VLTSEL); + WRITE_REG16(CMPx->CVSSTB, 0x0005U); + WRITE_REG16(CMPx->CVSPRD, 0x000FU); + CLR_REG16(CM_CMPCR->DADR1); + CLR_REG16(CM_CMPCR->DADR2); + CLR_REG16(CM_CMPCR->DACR); + CLR_REG16(CM_CMPCR->RVADC); +} + +/** + * @brief CMP normal mode initialize + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] pstcCmpInit CMP function base parameter structure + * @arg pstcCmpInit->u16PositiveInput: @ref CMP_Positive_Input_Select + * @arg pstcCmpInit->u16NegativeInput: @ref CMP_Negative_Input_Select + * @arg pstcCmpInit->u16OutPolarity: @ref CMP_Out_Polarity_Select + * @arg pstcCmpInit->u16OutDetectEdge: @ref CMP_Out_Detect_Edge_Select + * @arg pstcCmpInit->u16OutFilter: @ref CMP_Out_Filter + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_NormalModeInit(CM_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcCmpInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check CMPx instance and configuration structure*/ + if (NULL != pstcCmpInit) { + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_POLARITY(pstcCmpInit->u16OutPolarity)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(pstcCmpInit->u16OutDetectEdge)); + DDL_ASSERT(IS_CMP_OUT_FILTER(pstcCmpInit->u16OutFilter)); + if (CM_CMP1 == CMPx) { + DDL_ASSERT(IS_CMP1_POSITIVE_IN(pstcCmpInit->u16PositiveInput)); + } else if (CM_CMP2 == CMPx) { + DDL_ASSERT(IS_CMP2_POSITIVE_IN(pstcCmpInit->u16PositiveInput)); + } else { + DDL_ASSERT(IS_CMP3_POSITIVE_IN(pstcCmpInit->u16PositiveInput)); + } + DDL_ASSERT(IS_CMP_NEGATIVE_IN(pstcCmpInit->u16NegativeInput)); + + /* Stop CMP compare */ + CLR_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPON); + + /* Set voltage in */ + WRITE_REG16(CMPx->VLTSEL, pstcCmpInit->u16PositiveInput | pstcCmpInit->u16NegativeInput); + + /* Delay 1us*/ + CMP_DelayUS(1U); + /* Start CMP compare */ + SET_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPON); + /* Delay 1us*/ + CMP_DelayUS(1U); + /* Set output filter and output detect edge and output polarity */ + MODIFY_REG16(CMPx->CTRL, CMP_CTRL_FLTSL | CMP_CTRL_EDGSL | CMP_CTRL_INV, (pstcCmpInit->u16OutFilter | pstcCmpInit->u16OutDetectEdge | pstcCmpInit->u16OutPolarity)); + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Voltage compare function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_FuncCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check CMPx instance */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPON); + /* Delay 1us*/ + CMP_DelayUS(1U); + } else { + CLR_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPON); + } +} + +/** + * @brief Voltage compare interrupt function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_IntCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CMPx->CTRL, CMP_CTRL_IEN); + } else { + CLR_REG16_BIT(CMPx->CTRL, CMP_CTRL_IEN); + } +} + +/** + * @brief Voltage compare output command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_CompareOutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPOE); + } else { + CLR_REG16_BIT(CMPx->CTRL, CMP_CTRL_CMPOE); + } +} + +/** + * @brief Voltage compare output port VCOUT function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_PinVcoutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CMPx->CTRL, CMP_CTRL_OUTEN); + } else { + CLR_REG16_BIT(CMPx->CTRL, CMP_CTRL_OUTEN); + } +} + +/** + * @brief Voltage compare result flag read + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval An @ref en_flag_status_t enumeration type value. + * In normal mode + * - RESET: compare voltage < reference voltage + * - SET: compare voltage > reference voltage + * In Window mode + * - RESET: compare voltage < reference low voltage or compare voltage > reference high voltage + * - SET: reference low voltage < compare voltage < reference high voltage + */ +en_flag_status_t CMP_GetStatus(const CM_CMP_TypeDef *CMPx) +{ + en_flag_status_t i32Ret; + /* Check CMPx instance */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + i32Ret = (READ_REG16_BIT(CMPx->OUTMON, CMP_OUTMON_OMON) != 0U) ? SET : RESET; + return i32Ret; +} + +/** + * @brief Set output detect edge + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u8CmpEdges CMP output detect edge selection. @ref CMP_Out_Detect_Edge_Select + * @retval None + */ +void CMP_SetOutDetectEdge(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(u8CmpEdges)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* CMP output detect edge selection */ + MODIFY_REG16(CMPx->CTRL, CMP_CTRL_EDGSL, u8CmpEdges); + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set output filter + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u8CmpFilter CMP output filter selection. @ref CMP_Out_Filter + * @retval None + */ +void CMP_SetOutFilter(CM_CMP_TypeDef *CMPx, uint8_t u8CmpFilter) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_FILTER(u8CmpFilter)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + /* CMP output filter selection */ + MODIFY_REG16(CMPx->CTRL, CMP_CTRL_FLTSL, u8CmpFilter); + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set output polarity + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16CmpPolarity CMP output polarity selection. @ref CMP_Out_Polarity_Select + * @retval None + */ +void CMP_SetOutPolarity(CM_CMP_TypeDef *CMPx, uint16_t u16CmpPolarity) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_POLARITY(u16CmpPolarity)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* CMP output polarity selection */ + MODIFY_REG16(CMPx->CTRL, CMP_CTRL_INV, u16CmpPolarity); + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set positive in(compare voltage) + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16PositiveInput @ref CMP_Positive_Input_Select + * @retval None + */ +void CMP_SetPositiveInput(CM_CMP_TypeDef *CMPx, uint16_t u16PositiveInput) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + if (CM_CMP1 == CMPx) { + DDL_ASSERT(IS_CMP1_POSITIVE_IN(u16PositiveInput)); + } else if (CM_CMP2 == CMPx) { + DDL_ASSERT(IS_CMP2_POSITIVE_IN(u16PositiveInput)); + } else { + DDL_ASSERT(IS_CMP3_POSITIVE_IN(u16PositiveInput)); + } + + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* Set voltage in */ + MODIFY_REG16(CMPx->VLTSEL, (CMP_VLTSEL_CVSL | CMP_VLTSEL_C4SL), u16PositiveInput); + + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set negative in(reference voltage) + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16NegativeInput @ref CMP_Negative_Input_Select + * @retval None + */ +void CMP_SetNegativeInput(CM_CMP_TypeDef *CMPx, uint16_t u16NegativeInput) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_NEGATIVE_IN(u16NegativeInput)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* Set voltage in */ + MODIFY_REG16(CMPx->VLTSEL, CMP_VLTSEL_RVSL, u16NegativeInput); + + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Get CMP scan INP source + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval An uint16_t value @ref CMP_Scan_Inp_Status + */ +uint16_t CMP_GetScanInpSrc(CM_CMP_TypeDef *CMPx) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + return READ_REG16_BIT(CMPx->OUTMON, CMP_OUTMON_CVST); +} + +/** + * @brief Get CMP scan function stable time and period configuration + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u8ScanStable CMP scan stable value + * @arg u8ScanStable < 16 + * @param [in] u8ScanPeriod CMP scan period value + * @arg u8ScanPeriod range(0x0F ~ 0xFF) + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + * @note 1. u8ScanPeriod > (u8ScanStable + u16OutFilter * 4 + 5) + * u16OutFilter is configurate in CMP_NormalModeInit() function. + * 2. Scan stable time = u8ScanStable * T(pclk3) + * The typical value of Scan stable time is 100nS and Scan stable time < 200nS + */ +int32_t CMP_ScanTimeConfig(CM_CMP_TypeDef *CMPx, uint8_t u8ScanStable, uint8_t u8ScanPeriod) +{ + uint16_t u16Flts; + uint16_t u16FltslDiv; + int32_t i32Ret = LL_OK; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_SCAN_STABLE(u8ScanStable)); + DDL_ASSERT(IS_CMP_SCAN_PERIOD(u8ScanPeriod)); + + u16Flts = READ_REG16_BIT(CMPx->CTRL, CMP_CTRL_FLTSL); + if (0U != u16Flts) { + u16FltslDiv = ((uint16_t)1U << (u16Flts - 1U)); + } else { + u16FltslDiv = 0U; + } + + if (u8ScanPeriod <= (u8ScanStable + u16FltslDiv * 4U + 5U)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + WRITE_REG16(CMPx->CVSSTB, u8ScanStable); + WRITE_REG16(CMPx->CVSPRD, u8ScanPeriod); + } + return i32Ret; +} + +/** + * @brief CMP scan function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_ScanCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CMPx->CTRL, CMP_CTRL_CVSEN); + } else { + CLR_REG16_BIT(CMPx->CTRL, CMP_CTRL_CVSEN); + } +} + +/** + * @brief CMP 8 bit DAC reference voltage command + * @param [in] u8Ch The DAC channel @ref CMP_8Bit_Dac_Ch + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_8BitDAC_Cmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_8_BIT_DAC_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CM_CMPCR->DACR, u8Ch); + } else { + CLR_REG16_BIT(CM_CMPCR->DACR, u8Ch); + } +} + +/** + * @brief CMP 8 bit DAC connect to ADC reference voltage command + * @param [in] u16AdcRefSw @ref CMP_8BitDAC_Adc_Ref_Switch + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_8BitDAC_AdcRefCmd(uint16_t u16AdcRefSw, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_8_BIT_DAC_SW(u16AdcRefSw)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + uint16_t WrTmp; + if (ENABLE == enNewState) { + WrTmp = u16AdcRefSw; + } else { + WrTmp = 0U; + } + WRITE_REG16(CM_CMPCR->RVADC, CMP_DADC_RVADC_REG_UNLOCK); + WRITE_REG16(CM_CMPCR->RVADC, WrTmp); +} + +/** + * @brief Write raw data to DAC + * @param [in] u8Ch DAC channel @ref CMP_8Bit_Dac_Ch + * @param [in] u16DACData DAC voltage data + * @retval None + */ +void CMP_8BitDAC_WriteData(uint8_t u8Ch, uint16_t u16DACData) +{ + DDL_ASSERT(IS_CMP_8_BIT_DAC_CH(u8Ch)); + DDL_ASSERT(IS_CMP_8_BIT_DAC_DATA(u16DACData)); + + if (CMP_8BITDAC_CH1 == u8Ch) { + WRITE_REG16(CM_CMPCR->DADR1, u16DACData); + } else { + WRITE_REG16(CM_CMPCR->DADR2, u16DACData); + } +} + +/** + * @} + */ + +#endif /* LL_CMP_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_crc.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_crc.c new file mode 100644 index 0000000000..41c0af4092 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_crc.c @@ -0,0 +1,666 @@ +/** + ******************************************************************************* + * @file hc32_ll_crc.c + * @brief This file provides firmware functions to manage the Cyclic Redundancy + * Check(CRC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_crc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CRC CRC + * @brief Cyclic Redundancy Check Driver Library + * @{ + */ + +#if (LL_CRC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CRC_Local_Macros CRC Local Macros + * @{ + */ + +/** + * @defgroup CRC_Check_Parameters_Validity CRC Check Parameters Validity + * @{ + */ +/*! Parameter validity check for CRC protocol. */ +#define IS_CRC_PROTOCOL(x) \ +( ((x) == CRC_CRC16) || \ + ((x) == CRC_CRC32)) + +/*! Parameter validity check for CRC data width. */ +#define IS_CRC_DATA_WIDTH(x) \ +( ((x) == CRC_DATA_WIDTH_8BIT) || \ + ((x) == CRC_DATA_WIDTH_16BIT) || \ + ((x) == CRC_DATA_WIDTH_32BIT)) + +/*! Parameter validity check for REFIN. */ +#define IS_CRC_REFIN(x) \ +( ((x) == CRC_REFIN_ENABLE) || \ + ((x) == CRC_REFIN_DISABLE)) + +/*! Parameter validity check for REFOUT. */ +#define IS_CRC_REFOUT(x) \ +( ((x) == CRC_REFOUT_ENABLE) || \ + ((x) == CRC_REFOUT_DISABLE)) + +/*! Parameter validity check for XOROUT. */ +#define IS_CRC_XOROUT(x) \ +( ((x) == CRC_XOROUT_ENABLE) || \ + ((x) == CRC_XOROUT_DISABLE)) +/** + * @} + */ + +/** + * @defgroup CRC_Registers_Reset_Value_definition CRC Registers Reset Value + * @{ + */ +#define CRC_CR_RST_VALUE (0x001CUL) +/** + * @} + */ + +/** + * @defgroup CRC_DATA_Bit_Width CRC Data Bit Width + * @{ + */ +#define CRC_DATA_WIDTH_8BIT (1U) +#define CRC_DATA_WIDTH_16BIT (2U) +#define CRC_DATA_WIDTH_32BIT (4U) +/** + * @} + */ + +/** + * @defgroup CRC_Register_Address CRC Register Address + * @{ + */ +#define CRC_DATA_ADDR ((uint32_t)(&CM_CRC->DAT0)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CRC_Local_Functions CRC Local Functions + * @{ + */ + +/** + * @brief Convert CRC value. + * @param [in] u32CrcValue The CRC value of CRC16 or CRC32. + * @retval the converted CRC value + */ +static uint32_t CRC_ConvertCrcValue(uint32_t u32CrcValue) +{ + uint8_t i; + uint8_t u8Size; + uint8_t u8Offset; + uint32_t u32Temp; + uint32_t u32Config; + uint32_t u32FinalCrcValue = u32CrcValue; + const uint32_t u32ConvertFlag = (CRC_REFIN_ENABLE | CRC_REFOUT_ENABLE | CRC_XOROUT_ENABLE); + + u32Config = READ_REG32(CM_CRC->CR); + + if ((u32Config & u32ConvertFlag) != u32ConvertFlag) { + if ((u32Config & CRC_CR_CR) == CRC_CRC32) { + u8Size = 32U; + } else { + u8Size = 16U; + } + + if ((u32Config & CRC_CR_REFOUT) == CRC_REFOUT_DISABLE) { + u32FinalCrcValue = __RBIT(u32FinalCrcValue); /* Bits reversing. */ + if (u8Size == 16U) { + u32FinalCrcValue >>= 16U; + u32FinalCrcValue &= 0xFFFFUL; + } + } + + if ((u32Config & CRC_CR_XOROUT) == CRC_XOROUT_DISABLE) { + u32FinalCrcValue = ~u32FinalCrcValue; /* Bits NOT. */ + } + + if ((u32Config & CRC_CR_REFIN) == CRC_REFIN_DISABLE) { + u8Size /= 8U; + /* Bits reversing in bytes. */ + for (i = 0U; i < u8Size; i++) { + u8Offset = i * 8U; + u32Temp = (u32FinalCrcValue >> u8Offset) & 0xFFUL; + u32Temp = __RBIT(u32Temp); /* Bits reversing. */ + u32Temp = u32Temp >> (24U - u8Offset); + u32FinalCrcValue &= ~((uint32_t)0xFFUL << u8Offset); + u32FinalCrcValue |= u32Temp; + } + } + } + + return u32FinalCrcValue; +} + +/** + * @brief Calculate the CRC value of a 8-bit data buffer. + * @param [in] au8Data Pointer to the input data buffer. + * @param [in] u32Len The length(counted in byte) of the data to be calculated. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: The au8Data value is NULL or u32Len value is 0. + */ +static int32_t CRC_WriteData8(const uint8_t au8Data[], uint32_t u32Len) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + const uint32_t u32DataAddr = CRC_DATA_ADDR; + + if ((au8Data != NULL) && (u32Len != 0UL)) { + for (i = 0UL; i < u32Len; i++) { + RW_MEM8(u32DataAddr) = au8Data[i]; + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Calculate the CRC value of a 16-bit data buffer. + * @param [in] au16Data Pointer to the input data buffer. + * @param [in] u32Len The length(counted in half-word) of the data to be calculated. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: The au16Data value is NULL or u32Len value is 0. + */ +static int32_t CRC_WriteData16(const uint16_t au16Data[], uint32_t u32Len) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + const uint32_t u32DataAddr = CRC_DATA_ADDR; + + if ((au16Data != NULL) && (u32Len != 0UL)) { + for (i = 0UL; i < u32Len; i++) { + RW_MEM16(u32DataAddr) = au16Data[i]; + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Calculate the CRC value of a 32-bit data buffer. + * @param [in] au32Data Pointer to the input data buffer. + * @param [in] u32Len The length(counted in word) of the data to be calculated. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: The au32Data value is NULL or u32Len value is 0. + */ +static int32_t CRC_WriteData32(const uint32_t au32Data[], uint32_t u32Len) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + const uint32_t u32DataAddr = CRC_DATA_ADDR; + + if ((au32Data != NULL) && (u32Len != 0UL)) { + for (i = 0UL; i < u32Len; i++) { + RW_MEM32(u32DataAddr) = au32Data[i]; + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Calculate the CRC value and start with the previously calculated CRC as initial value. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the macros group @ref CRC_DATA_Bit_Width + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in bytes or half word or word, depending on + * the bit width) of the data to be calculated. + * @retval The CRC value. + * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth). + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +static uint32_t CRC_Accumulate(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((pvData != NULL) && (u32Len != 0UL)) { + DDL_ASSERT(IS_CRC_DATA_WIDTH(u8DataWidth)); + + /* Write data */ + if (CRC_DATA_WIDTH_32BIT == u8DataWidth) { + (void)CRC_WriteData32((const uint32_t *)pvData, u32Len); + } else if (CRC_DATA_WIDTH_16BIT == u8DataWidth) { + (void)CRC_WriteData16((const uint16_t *)pvData, u32Len); + } else { + (void)CRC_WriteData8((const uint8_t *)pvData, u32Len); + } + + /* Get checksum */ + if (READ_REG32_BIT(CM_CRC->CR, CRC_CR_CR) == CRC_CRC32) { + u32CrcValue = READ_REG32(CM_CRC->RESLT); + } else { + u32CrcValue = (READ_REG16(CM_CRC->RESLT) & CRC16_INIT_VALUE); + } + } + + return u32CrcValue; +} + +/** + * @brief Calculate the CRC value and start with the specified initial value(u32InitValue). + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the following values: + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be computed. + * @param [in] u32Len The length(counted in bytes or half word or word, depending on + * the bit width) of the data to be computed. + * @retval The CRC value. + * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth). + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +static uint32_t CRC_Calculate(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((pvData != NULL) && (u32Len != 0UL)) { + /* Set initial value */ + if (READ_REG32_BIT(CM_CRC->CR, CRC_CR_CR) == CRC_CRC32) { + WRITE_REG32(CM_CRC->RESLT, u32InitValue); + } else { + WRITE_REG16(CM_CRC->RESLT, (u32InitValue & CRC16_INIT_VALUE)); + } + + u32CrcValue = CRC_Accumulate(u8DataWidth, pvData, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Check the CRC calculating result with the expected value. + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the following values: + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be computed. + * @param [in] u32Len The length(counted in byte) of the data to be calculated. + * @param [in] u32ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + * @note The upper 16 bit of CRC result value and the expected value are ignored when using CRC16 + */ +static en_flag_status_t CRC_CheckData(uint32_t u32InitValue, uint8_t u8DataWidth, + const void *pvData, uint32_t u32Len, uint32_t u32ExpectValue) +{ + en_flag_status_t enStatus = RESET; + + if ((pvData != NULL) && (u32Len != 0UL)) { + (void)CRC_Calculate(u32InitValue, u8DataWidth, pvData, u32Len); + + u32ExpectValue = CRC_ConvertCrcValue(u32ExpectValue); + + if (READ_REG32_BIT(CM_CRC->CR, CRC_CR_CR) == CRC_CRC32) { + (void)CRC_WriteData32(&u32ExpectValue, 1UL); + } else { + (void)CRC_WriteData16((uint16_t *)((void *)&u32ExpectValue), 1UL); + } + + enStatus = CRC_GetResultStatus(); + } + + return enStatus; +} +/** + * @} + */ + +/** + * @defgroup CRC_Global_Functions CRC Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_crc_init_t to default values. + * @param [out] pstcCrcInit Pointer to a @ref stc_crc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCrcInit value is NULL. + */ +int32_t CRC_StructInit(stc_crc_init_t *pstcCrcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcCrcInit) { + pstcCrcInit->u32Protocol = CRC_CRC16; + pstcCrcInit->u32InitValue = CRC16_INIT_VALUE; + pstcCrcInit->u32RefIn = CRC_REFIN_ENABLE; + pstcCrcInit->u32RefOut = CRC_REFOUT_ENABLE; + pstcCrcInit->u32XorOut = CRC_XOROUT_ENABLE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize the CRC. + * @param [in] pstcCrcInit Pointer to a @ref stc_crc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCrcInit value is NULL. + */ +int32_t CRC_Init(const stc_crc_init_t *pstcCrcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcCrcInit) { + DDL_ASSERT(IS_CRC_PROTOCOL(pstcCrcInit->u32Protocol)); + CRC_DeInit(); + + DDL_ASSERT(IS_CRC_REFIN(pstcCrcInit->u32RefIn)); + DDL_ASSERT(IS_CRC_REFOUT(pstcCrcInit->u32RefOut)); + DDL_ASSERT(IS_CRC_XOROUT(pstcCrcInit->u32XorOut)); + + WRITE_REG32(CM_CRC->CR, (pstcCrcInit->u32RefIn | pstcCrcInit->u32RefOut | pstcCrcInit->u32XorOut)); + + MODIFY_REG32(CM_CRC->CR, CRC_CRC32, pstcCrcInit->u32Protocol); + + /* Set initial value */ + if (CRC_CRC32 == pstcCrcInit->u32Protocol) { + WRITE_REG32(CM_CRC->RESLT, pstcCrcInit->u32InitValue); + } else { + WRITE_REG16(CM_CRC->RESLT, pstcCrcInit->u32InitValue); + } + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief De-initialize the CRC. + * @param None + * @retval None + */ +void CRC_DeInit(void) +{ + WRITE_REG32(CM_CRC->CR, CRC_CR_RST_VALUE); +} + +/** + * @brief Get status of the CRC operation result. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CRC_GetResultStatus(void) +{ + uint32_t u32Status; + + if (READ_REG32_BIT(CM_CRC->CR, CRC_CR_CR) == CRC_CRC32) { + u32Status = READ_REG32_BIT(CM_CRC->FLG, CRC_FLG_CRCFLAG_32); + } else { + u32Status = READ_REG32_BIT(CM_CRC->RESLT, CRC_RESLT_CRCFLAG_16); + } + + return (u32Status > 0UL) ? SET : RESET; +} + +/** + * @brief Calculate the CRC value and start with the previously calculated CRC as initial value. + * @param [in] au8Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in bytes) of the data to be calculated. + * @retval The CRC value. + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +uint32_t CRC_AccumulateData8(const uint8_t au8Data[], uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((au8Data != NULL) && (u32Len != 0UL)) { + u32CrcValue = CRC_Accumulate(CRC_DATA_WIDTH_8BIT, au8Data, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Calculate the CRC value and start with the previously calculated CRC as initial value. + * @param [in] au16Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in half-word) of the data to be calculated. + * @retval The CRC value. + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +uint32_t CRC_AccumulateData16(const uint16_t au16Data[], uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((au16Data != NULL) && (u32Len != 0UL)) { + u32CrcValue = CRC_Accumulate(CRC_DATA_WIDTH_16BIT, au16Data, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Calculate the CRC value and start with the previously calculated CRC as initial value. + * @param [in] au32Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in word) of the data to be calculated. + * @retval The CRC value. + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +uint32_t CRC_AccumulateData32(const uint32_t au32Data[], uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((au32Data != NULL) && (u32Len != 0UL)) { + u32CrcValue = CRC_Accumulate(CRC_DATA_WIDTH_32BIT, au32Data, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Calculate the CRC value and start with the specified initial value(u32InitValue). + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] au8Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in byte) of the data to be calculated. + * @retval The CRC value. + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +uint32_t CRC_CalculateData8(uint32_t u32InitValue, const uint8_t au8Data[], uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((au8Data != NULL) && (u32Len != 0UL)) { + u32CrcValue = CRC_Calculate(u32InitValue, CRC_DATA_WIDTH_8BIT, au8Data, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Calculate the CRC value and start with the specified initial value(u32InitValue). + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] au16Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in half-word) of the data to be calculated. + * @retval The CRC value. + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +uint32_t CRC_CalculateData16(uint32_t u32InitValue, const uint16_t au16Data[], uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((au16Data != NULL) && (u32Len != 0UL)) { + u32CrcValue = CRC_Calculate(u32InitValue, CRC_DATA_WIDTH_16BIT, au16Data, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Calculate the CRC value and start with the specified initial value(u32InitValue). + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] au32Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in word) of the data to be calculated. + * @retval The CRC value. + * @note The upper 16 bit of CRC result value is ignored when using CRC16 + */ +uint32_t CRC_CalculateData32(uint32_t u32InitValue, const uint32_t au32Data[], uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((au32Data != NULL) && (u32Len != 0UL)) { + u32CrcValue = CRC_Calculate(u32InitValue, CRC_DATA_WIDTH_32BIT, au32Data, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Check the CRC calculating result with the expected value. + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] au8Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in byte) of the data to be calculated. + * @param [in] u32ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + * @note The upper 16 bit of CRC result value and the expected value are ignored when using CRC16 + */ +en_flag_status_t CRC_CheckData8(uint32_t u32InitValue, const uint8_t au8Data[], + uint32_t u32Len, uint32_t u32ExpectValue) +{ + en_flag_status_t enStatus = RESET; + + if ((au8Data != NULL) && (u32Len != 0UL)) { + enStatus = CRC_CheckData(u32InitValue, CRC_DATA_WIDTH_8BIT, au8Data, u32Len, u32ExpectValue); + } + + return enStatus; +} + +/** + * @brief Check the CRC calculating result with the expected value. + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] au16Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in half-word) of the data to be calculated. + * @param [in] u32ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + * @note The upper 16 bit of CRC result value and the expected value are ignored when using CRC16 + */ +en_flag_status_t CRC_CheckData16(uint32_t u32InitValue, const uint16_t au16Data[], + uint32_t u32Len, uint32_t u32ExpectValue) +{ + en_flag_status_t enStatus = RESET; + + if ((au16Data != NULL) && (u32Len != 0UL)) { + enStatus = CRC_CheckData(u32InitValue, CRC_DATA_WIDTH_16BIT, au16Data, u32Len, u32ExpectValue); + } + + return enStatus; +} + +/** + * @brief Check the CRC calculating result with the expected value. + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] au32Data Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in word) of the data to be calculated. + * @param [in] u32ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + * @note The upper 16 bit of CRC result value and the expected value are ignored when using CRC16 + */ +en_flag_status_t CRC_CheckData32(uint32_t u32InitValue, const uint32_t au32Data[], + uint32_t u32Len, uint32_t u32ExpectValue) +{ + en_flag_status_t enStatus = RESET; + + if ((au32Data != NULL) && (u32Len != 0UL)) { + enStatus = CRC_CheckData(u32InitValue, CRC_DATA_WIDTH_32BIT, au32Data, u32Len, u32ExpectValue); + } + + return enStatus; +} + +/** + * @} + */ + +#endif /* LL_CRC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_dcu.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_dcu.c new file mode 100644 index 0000000000..a4b297033b --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_dcu.c @@ -0,0 +1,537 @@ +/** + ******************************************************************************* + * @file hc32_ll_dcu.c + * @brief This file provides firmware functions to manage the DCU(Data Computing + * Unit). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_dcu.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_DCU DCU + * @brief DCU Driver Library + * @{ + */ + +#if (LL_DCU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DCU_Local_Macros DCU Local Macros + * @{ + */ + +/** + * @defgroup DCU_Check_Parameters_Validity DCU Check Parameters Validity + * @{ + */ + +#define IS_DCU_BASE_FUNC_UNIT(x) \ +( ((x) == CM_DCU1) || \ + ((x) == CM_DCU2) || \ + ((x) == CM_DCU3)) + +#define IS_DCU_UNIT(x) (IS_DCU_BASE_FUNC_UNIT(x)) + +#define IS_DCU_BASE_FUNC_UNIT_MD(x) \ +( ((x) == DCU_MD_CMP) || \ + ((x) == DCU_MD_ADD) || \ + ((x) == DCU_MD_SUB) || \ + ((x) == DCU_MD_HW_ADD) || \ + ((x) == DCU_MD_HW_SUB) || \ + ((x) == DCU_MD_INVD)) + +#define IS_DCU_BASE_FUNC_UNIT_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~DCU_BASE_FUNC_UNIT_FLAG_MASK)))) + +#define IS_DCU_CMP_COND(x) \ +( ((x) == DCU_CMP_TRIG_DATA0) || \ + ((x) == DCU_CMP_TRIG_DATA0_DATA1_DATA2)) + +#define IS_DCU_DATA_WIDTH(x) \ +( ((x) == DCU_DATA_WIDTH_8BIT) || \ + ((x) == DCU_DATA_WIDTH_16BIT) || \ + ((x) == DCU_DATA_WIDTH_32BIT)) + +#define IS_DCU_INT_CATEGORY(x) \ +( ((x) == DCU_CATEGORY_OP) || \ + ((x) == DCU_CATEGORY_CMP_WIN) || \ + ((x) == DCU_CATEGORY_CMP_NON_WIN)) + +#define IS_DCU_INT_OP(x) ((x) == DCU_INT_OP_CARRY) + +#define IS_DCU_INT_CMP_WIN(x) \ +( ((x) == DCU_INT_CMP_WIN_INSIDE) || \ + ((x) == DCU_INT_CMP_WIN_OUTSIDE)) + +#define IS_DCU_INT_CMP_NON_WIN(x) \ +( ((x) != 0UL) || \ + (((x) | DCU_INT_CMP_NON_WIN_ALL) == DCU_INT_CMP_NON_WIN_ALL)) + +#define IS_DCU_INT_WAVE_MD(x) \ +( ((x) != 0UL) && \ + (((x) | DCU_INT_WAVE_MD_ALL) == DCU_INT_WAVE_MD_ALL)) + +#define IS_DCU_DATA_REG(x) \ +( ((x) == DCU_DATA0_IDX) || \ + ((x) == DCU_DATA1_IDX) || \ + ((x) == DCU_DATA2_IDX)) + +#define IS_DCU_WAVE_UPPER_LIMIT(x) ((x) <= 0xFFFUL) + +#define IS_DCU_WAVE_LOWER_LIMIT(x) ((x) <= 0xFFFUL) + +#define IS_DCU_WAVE_STEP(x) ((x) <= 0xFFFUL) +/** + * @} + */ + +/** + * @defgroup DCU_Flag_Mask DCU Flag Mask + * @{ + */ +#define DCU_BASE_FUNC_UNIT_FLAG_MASK (0x0E7FUL) +/** + * @} + */ + +/** + * @defgroup DCU_Register_Address DCU Register Address + * @{ + */ +#define DCU_REG_ADDR(_REG_) ((uint32_t)(&(_REG_))) +#define DCU_DATA_REG_ADDR(_UNITx_, _IDX_) (DCU_REG_ADDR((_UNITx_)->DATA0) + ((_IDX_) << 2UL)) + +#define DCU_DATA_REG8(_UNITx_, _IDX_) (*(__IO uint8_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_)) +#define DCU_DATA_REG16(_UNITx_, _IDX_) (*(__IO uint16_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_)) +#define DCU_DATA_REG32(_UNITx_, _IDX_) (*(__IO uint32_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Functions DCU Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_dcu_init_t to default values. + * @param [out] pstcDcuInit Pointer to a @ref stc_dcu_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcDcuInit value is NULL. + */ +int32_t DCU_StructInit(stc_dcu_init_t *pstcDcuInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDcuInit) { + pstcDcuInit->u32Mode = DCU_MD_INVD; + pstcDcuInit->u32DataWidth = DCU_DATA_WIDTH_8BIT; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize DCU function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] pstcDcuInit Pointer to a @ref stc_dcu_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcDcuInit value is NULL. + */ +int32_t DCU_Init(CM_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcDcuInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDcuInit) { + DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_MD(pstcDcuInit->u32Mode)); + DDL_ASSERT(IS_DCU_DATA_WIDTH(pstcDcuInit->u32DataWidth)); + + /* Set register: CTL */ + WRITE_REG32(DCUx->CTL, (pstcDcuInit->u32Mode | pstcDcuInit->u32DataWidth)); + + /* Disable interrupt */ + WRITE_REG32(DCUx->INTSEL, 0x00000000UL); + + /* Clear Flag */ + WRITE_REG32(DCUx->FLAGCLR, 0x0000007FUL); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize DCU function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @retval None + */ +int32_t DCU_DeInit(CM_DCU_TypeDef *DCUx) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + + /* Configures the registers to reset value. */ + WRITE_REG32(DCUx->CTL, 0x00000000UL); + WRITE_REG32(DCUx->INTSEL, 0x00000000UL); + + /* Clear Flag */ + WRITE_REG32(DCUx->FLAGCLR, 0x0000007FUL); + return LL_OK; +} + +/** + * @brief Set DCU operation mode. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Mode DCU mode + * This parameter can be one of the macros group @ref DCU_Mode. + * @retval None + */ +void DCU_SetMode(CM_DCU_TypeDef *DCUx, uint32_t u32Mode) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_MD(u32Mode)); + + MODIFY_REG32(DCUx->CTL, DCU_CTL_MODE, u32Mode); +} + +/** + * @brief Set DCU data size. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataWidth DCU data width + * This parameter can be one of the macros group @ref DCU_Data_Width + * @arg DCU_DATA_WIDTH_8BIT: DCU data size 8 bit + * @arg DCU_DATA_WIDTH_16BIT: DCU data size 16 bit + * @arg DCU_DATA_WIDTH_32BIT: DCU data size 32 bit + * @retval None + */ +void DCU_SetDataWidth(CM_DCU_TypeDef *DCUx, uint32_t u32DataWidth) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_WIDTH(u32DataWidth)); + + MODIFY_REG32(DCUx->CTL, DCU_CTL_DATASIZE, u32DataWidth); +} + +/** + * @brief Set DCU compare trigger condition. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Cond DCU compare trigger condition + * This parameter can be one of the macros group @ref DCU_Compare_Trigger_Condition + * @arg DCU_CMP_TRIG_DATA0: DCU compare triggered by DATA0. + * @arg DCU_CMP_TRIG_DATA0_DATA1_DATA2: DCU compare triggered by DATA0 or DATA1 or DATA2. + * @retval None + */ +void DCU_SetCompareCond(CM_DCU_TypeDef *DCUx, uint32_t u32Cond) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_CMP_COND(u32Cond)); + + MODIFY_REG32(DCUx->CTL, DCU_CTL_COMP_TRG, u32Cond); +} + +/** + * @brief Get DCU flag. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Flag The specified DCU flag + * This parameter can be any composed value of the macros group @ref DCU_Flag. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t DCU_GetStatus(const CM_DCU_TypeDef *DCUx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_FLAG(u32Flag)); + + return (0UL == READ_REG32_BIT(DCUx->FLAG, u32Flag)) ? RESET : SET; +} + +/** + * @brief Clear DCU flag. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Flag The specified DCU flag + * This parameter can be any composed value of the macros group @ref DCU_Mode. + * @retval None + */ +void DCU_ClearStatus(CM_DCU_TypeDef *DCUx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_FLAG(u32Flag)); + + WRITE_REG32(DCUx->FLAGCLR, u32Flag); +} + +/** + * @brief Enable or disable DCU interupt function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DCU_GlobalIntCmd(CM_DCU_TypeDef *DCUx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(DCUx->CTL, DCU_CTL_INTEN); + } else { + CLR_REG32_BIT(DCUx->CTL, DCU_CTL_INTEN); + } +} + +/** + * @brief Enable/disable DCU the specified interrupt source. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32IntCategory DCU interrupt categorye + * This parameter can be one of the macros group @ref DCU_Category. + * @param [in] u32IntType DCU interrupt type + * This parameter can be one of the following case: + * a. this parameter can be one of the macros group @ref DCU_Operation_Interrupt when u32Category = DCU_CATEGORY_OP. + * b. this parameter can be one of the macros group @ref DCU_Window_Compare_Interrupt when u32Category = DCU_CATEGORY_CMP_WIN. + * c. this parameter can be one of the macros group @ref DCU_Compare_Interrupt when u32Category = DCU_CATEGORY_CMP_NON_WIN. + * d. this parameter can be one of the macros group @ref DCU_Wave_Mode_Interrupt when u32Category = DCU_CATEGORY_WAVE. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DCU_IntCmd(CM_DCU_TypeDef *DCUx, uint32_t u32IntCategory, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32Type; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_INT_CATEGORY(u32IntCategory)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DCU_CATEGORY_OP == u32IntCategory) { + DDL_ASSERT(IS_DCU_INT_OP(u32IntType)); + u32Type = (u32IntType & DCU_INT_OP_CARRY); + } else if (DCU_CATEGORY_CMP_WIN == u32IntCategory) { + DDL_ASSERT(IS_DCU_INT_CMP_WIN(u32IntType)); + u32Type = (u32IntType & DCU_INT_CMP_WIN_ALL); + } else if (DCU_CATEGORY_CMP_NON_WIN == u32IntCategory) { + DDL_ASSERT(IS_DCU_INT_CMP_NON_WIN(u32IntType)); + u32Type = (u32IntType & DCU_INT_CMP_NON_WIN_ALL); + } else { + u32Type = 0UL; + } + + if (ENABLE == enNewState) { + SET_REG32_BIT(DCUx->INTSEL, u32Type); + } else { + CLR_REG32_BIT(DCUx->INTSEL, u32Type); + } +} + +/** + * @brief Read DCU register DATA for byte. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for byte + */ +uint8_t DCU_ReadData8(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + return READ_REG8(DCU_DATA_REG8(DCUx, u32DataIndex)); +} + +/** + * @brief Write DCU register DATA for byte. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u8Data The data to write. + * @retval None + */ +void DCU_WriteData8(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint8_t u8Data) +{ + __IO uint8_t *DATA; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = &DCU_DATA_REG8(DCUx, u32DataIndex); + WRITE_REG8(*DATA, u8Data); +} + +/** + * @brief Read DCU register DATA for half-word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for half-word + */ +uint16_t DCU_ReadData16(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + return READ_REG16(DCU_DATA_REG16(DCUx, u32DataIndex)); +} + +/** + * @brief Write DCU register DATA for half-word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u16Data The data to write. + * @retval None + */ +void DCU_WriteData16(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint16_t u16Data) +{ + __IO uint16_t *DATA; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = &DCU_DATA_REG16(DCUx, u32DataIndex); + WRITE_REG16(*DATA, u16Data); +} + +/** + * @brief Read DCU register DATA for word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for word + */ +uint32_t DCU_ReadData32(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + return READ_REG32(DCU_DATA_REG32(DCUx, u32DataIndex)); +} + +/** + * @brief Write DCU register DATA0 for word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u32Data The data to write. + * @retval None + */ +void DCU_WriteData32(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint32_t u32Data) +{ + __IO uint32_t *DATA; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = &DCU_DATA_REG32(DCUx, u32DataIndex); + WRITE_REG32(*DATA, u32Data); +} + +/** + * @} + */ + +#endif /* LL_DCU_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_dma.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_dma.c new file mode 100644 index 0000000000..82d971678c --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_dma.c @@ -0,0 +1,1378 @@ +/** + ******************************************************************************* + * @file hc32_ll_dma.c + * @brief This file provides firmware functions to manage the Direct Memory + * Access (DMA). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_dma.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_DMA DMA + * @brief Direct Memory Access Driver Library + * @{ + */ + +#if (LL_DMA_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DMA_Local_Macros DMA Local Macros + * @{ + */ +#define DMA_CH_REG(reg_base, ch) (*(__IO uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL))) + +#define DMA_CNT (10U) +#define DMA_IDLE (0U) +#define DMA_BUSY (1U) +#define DMATIMEOUT1 (0x5000U) +#define DMATIMEOUT2 (0x1000u) + +/** + * @defgroup DMA_Check_Parameters_Validity DMA Check Parameters Validity + * @{ + */ +/* Parameter valid check for DMA unit. */ +#define IS_DMA_UNIT(x) \ +( ((x) == CM_DMA1) || \ + ((x) == CM_DMA2)) + +/* Parameter valid check for DMA channel. */ +#define IS_DMA_CH(x) ((x) <= DMA_CH3) + +/* Parameter valid check for DMA multiplex channel. */ +#define IS_DMA_MX_CH(x) \ +( ((x) != 0x00UL) && \ + (((x) | DMA_MX_CH_ALL) == DMA_MX_CH_ALL)) + +/* Parameter valid check for DMA block size. */ +#define IS_DMA_BLOCK_SIZE(x) ((x) < 1024U) + +/* Parameter valid check for DMA non-sequence transfer count. */ +#define IS_DMA_NON_SEQ_TRANS_CNT(x) ((x) < 4096U) + +/* Parameter valid check for DMA non-sequence offset. */ +#define IS_DMA_NON_SEQ_OFFSET(x) ((x) <= ((1UL << 20U) - 1UL)) + +/* Parameter valid check for DMA LLP function. */ +#define IS_DMA_LLP_EN(x) \ +( ((x) == DMA_LLP_ENABLE) || \ + ((x) == DMA_LLP_DISABLE)) + +/* Parameter valid check for DMA linked-list-pointer mode. */ +#define IS_DMA_LLP_MD(x) \ +( ((x) == DMA_LLP_RUN) || \ + ((x) == DMA_LLP_WAIT)) + +/* Parameter valid check for DMA error flag. */ +#define IS_DMA_ERR_FLAG(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_FLAG_ERR_MASK) == DMA_FLAG_ERR_MASK)) + +/* Parameter valid check for DMA transfer flag. */ +#define IS_DMA_TRANS_FLAG(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_FLAG_TRANS_MASK) == DMA_FLAG_TRANS_MASK)) + +/* Parameter valid check for DMA error interrupt. */ +#define IS_DMA_ERR_INT(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_INT_ERR_MASK) == DMA_INT_ERR_MASK)) + +/* Parameter valid check for DMA transfer interrupt. */ +#define IS_DMA_TRANS_INT(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_INT_TRANS_MASK) == DMA_INT_TRANS_MASK)) + +/* Parameter valid check for DMA request status. */ +#define IS_DMA_REQ_STAT(x) \ +( ((x) != 0x00000000UL) && \ + (((x) | DMA_STAT_REQ_MASK) == DMA_STAT_REQ_MASK)) + +/* Parameter valid check for DMA channel status. */ +#define IS_DMA_TRANS_STAT(x) \ +( ((x) != 0x00000000UL) && \ + (((x) | DMA_STAT_TRANS_MASK) == DMA_STAT_TRANS_MASK)) + +/* Parameter valid check for DMA transfer data width. */ +#define IS_DMA_DATA_WIDTH(x) \ +( ((x) == DMA_DATAWIDTH_8BIT) || \ + ((x) == DMA_DATAWIDTH_16BIT) || \ + ((x) == DMA_DATAWIDTH_32BIT)) + +/* Parameter valid check for DMA source address mode. */ +#define IS_DMA_SADDR_MD(x) \ +( ((x) == DMA_SRC_ADDR_FIX) || \ + ((x) == DMA_SRC_ADDR_INC) || \ + ((x) == DMA_SRC_ADDR_DEC)) + +/* Parameter valid check for DMA destination address mode. */ +#define IS_DMA_DADDR_MD(x) \ +( ((x) == DMA_DEST_ADDR_FIX) || \ + ((x) == DMA_DEST_ADDR_INC) || \ + ((x) == DMA_DEST_ADDR_DEC)) + +/* Parameter valid check for DMA repeat mode. */ +#define IS_DMA_RPT_MD(x) \ +( ((x) == DMA_RPT_NONE) || \ + ((x) == DMA_RPT_SRC) || \ + ((x) == DMA_RPT_DEST) || \ + ((x) == DMA_RPT_BOTH)) + +/* Parameter valid check for DMA non_sequence mode. */ +#define IS_DMA_NON_SEQ_MD(x) \ +( ((x) == DMA_NON_SEQ_NONE) || \ + ((x) == DMA_NON_SEQ_SRC) || \ + ((x) == DMA_NON_SEQ_DEST) || \ + ((x) == DMA_NON_SEQ_BOTH)) + +/* Parameter valid check for DMA global interrupt function. */ +#define IS_DMA_INT_FUNC(x) \ +( ((x) == DMA_INT_ENABLE) || \ + ((x) == DMA_INT_DISABLE)) + +/* Parameter valid check for DMA reconfig count mode. */ +#define IS_DMA_RC_CNT_MD(x) \ +( ((x) == DMA_RC_CNT_KEEP) || \ + ((x) == DMA_RC_CNT_SRC) || \ + ((x) == DMA_RC_CNT_DEST)) + +/* Parameter valid check for DMA reconfig destination address mode. */ +#define IS_DMA_RC_DA_MD(x) \ +( ((x) == DMA_RC_DEST_ADDR_KEEP) || \ + ((x) == DMA_RC_DEST_ADDR_NS) || \ + ((x) == DMA_RC_DEST_ADDR_RPT)) + +/* Parameter valid check for DMA reconfig source address mode. */ +#define IS_DMA_RC_SA_MD(x) \ +( ((x) == DMA_RC_SRC_ADDR_KEEP) || \ + ((x) == DMA_RC_SRC_ADDR_NS) || \ + ((x) == DMA_RC_SRC_ADDR_RPT)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Functions DMA Global Functions + * @{ + */ + +/** + * @brief DMA global function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_Cmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Global setting, ENABLE or DISABLE DMA */ + WRITE_REG32(DMAx->EN, enNewState); +} + +/** + * @brief DMA error IRQ function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32ErrInt DMA error IRQ flag. @ref DMA_Int_Request_Err_Sel, @ref DMA_Int_Trans_Err_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_ErrIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_INT(u32ErrInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE == enNewState) { + SET_REG32_BIT(DMAx->INTMASK0, u32ErrInt); + } else { + CLR_REG32_BIT(DMAx->INTMASK0, u32ErrInt); + } +} + +/** + * @brief Get DMA error flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA error IRQ flag. @ref DMA_Flag_Trans_Err_Sel, @ref DMA_Flag_Request_Err_Sel + * @retval An @ref en_flag_status_t enumeration type value. + * @note Include transfer error flag & request error flag + */ +en_flag_status_t DMA_GetErrStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_FLAG(u32Flag)); + + return (0U != READ_REG32_BIT(DMAx->INTSTAT0, u32Flag) ? SET : RESET); +} + +/** + * @brief Clear DMA error flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA error IRQ flag. @ref DMA_Flag_Trans_Err_Sel, @ref DMA_Flag_Request_Err_Sel + * @retval None + * @note Include transfer error flag & request error flag + */ +void DMA_ClearErrStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_FLAG(u32Flag)); + + SET_REG32_BIT(DMAx->INTCLR0, u32Flag); +} + +/** + * @brief DMA transfer IRQ function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32TransCompleteInt DMA transfer complete IRQ flag. @ref DMA_Int_Btc_Sel, @ref DMA_Int_Tc_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_TransCompleteIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32TransCompleteInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_INT(u32TransCompleteInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE == enNewState) { + SET_REG32_BIT(DMAx->INTMASK1, u32TransCompleteInt); + } else { + CLR_REG32_BIT(DMAx->INTMASK1, u32TransCompleteInt); + } +} + +/** + * @brief Get DMA transfer flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA transfer IRQ flag. @ref DMA_Flag_Btc_Sel, @ref DMA_Flag_Tc_Sel + * @retval An @ref en_flag_status_t enumeration type value. + * @note Include transfer complete flag & block transfer complete flag + */ +en_flag_status_t DMA_GetTransCompleteStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_TRANS_FLAG(u32Flag)); + return ((0U != READ_REG32_BIT(DMAx->INTSTAT1, u32Flag)) ? SET : RESET); +} + +/** + * @brief Clear DMA transfer flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA transfer complete flag. @ref DMA_Flag_Btc_Sel, @ref DMA_Flag_Tc_Sel + * @retval None + * @note Include transfer complete flag & block transfer complete flag + */ +void DMA_ClearTransCompleteStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_FLAG(u32Flag)); + + SET_REG32_BIT(DMAx->INTCLR1, u32Flag); +} + +/** + * @brief DMA channel function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t + */ +int32_t DMA_ChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + static __IO uint8_t u8DmaChEnState = DMA_IDLE; + + uint16_t u16Timeout = 0U; + uint32_t u32Temp; + uint32_t u32Count; + uint32_t u32MonCount; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DMA_IDLE == u8DmaChEnState) { + u8DmaChEnState = DMA_BUSY; + + /* Read back channel enable register except current channel */ + u32Temp = (DMAx->CHEN & (~(1UL << u8Ch))); + if (0UL != u32Temp) { + if (((DMAx->CHEN & DMA_CHEN_CHEN_0) == DMA_CHEN_CHEN_0) && (u8Ch != DMA_CH0)) { + u32Count = (DMAx->DTCTL0 & DMA_DTCTL_CNT) >> DMA_DTCTL_CNT_POS; + u32MonCount = (DMAx->MONDTCTL0 & DMA_MONDTCTL_CNT) >> DMA_MONDTCTL_CNT_POS; + if (u32MonCount > DMA_CNT) { + /* not wait. */ + } else if (u32MonCount < u32Count) { + while (0UL != (DMAx->CHEN & DMA_CHEN_CHEN_0)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT1) { + u8DmaChEnState = DMA_IDLE; + return LL_ERR_TIMEOUT; + } + } + } else { + /* else */ + } + } + if (((DMAx->CHEN & DMA_CHEN_CHEN_1) == DMA_CHEN_CHEN_1) && (u8Ch != DMA_CH1)) { + u32Count = (DMAx->DTCTL1 & DMA_DTCTL_CNT) >> DMA_DTCTL_CNT_POS; + u32MonCount = (DMAx->MONDTCTL1 & DMA_MONDTCTL_CNT) >> DMA_MONDTCTL_CNT_POS; + if (u32MonCount > DMA_CNT) { + /* not wait. */ + } else if (u32MonCount < u32Count) { + u16Timeout = 0U; + while (0UL != (DMAx->CHEN & DMA_CHEN_CHEN_1)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT1) { + u8DmaChEnState = DMA_IDLE; + return LL_ERR_TIMEOUT; + } + } + } else { + /* else */ + } + } + if (((DMAx->CHEN & DMA_CHEN_CHEN_2) == DMA_CHEN_CHEN_2) && (u8Ch != DMA_CH2)) { + u16Timeout = 0U; + u32Count = (DMAx->DTCTL2 & DMA_DTCTL_CNT) >> DMA_DTCTL_CNT_POS; + u32MonCount = (DMAx->MONDTCTL2 & DMA_MONDTCTL_CNT) >> DMA_MONDTCTL_CNT_POS; + if (u32MonCount > DMA_CNT) { + /* not wait. */ + } else if (u32MonCount < u32Count) { + while (0UL != (DMAx->CHEN & DMA_CHEN_CHEN_2)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT1) { + u8DmaChEnState = DMA_IDLE; + return LL_ERR_TIMEOUT; + } + } + } else { + /* else */ + } + } + if (((DMAx->CHEN & DMA_CHEN_CHEN_3) == DMA_CHEN_CHEN_3) && (u8Ch != DMA_CH3)) { + u16Timeout = 0U; + u32Count = (DMAx->DTCTL3 & DMA_DTCTL_CNT) >> DMA_DTCTL_CNT_POS; + u32MonCount = (DMAx->MONDTCTL3 & DMA_MONDTCTL_CNT) >> DMA_MONDTCTL_CNT_POS; + if (u32MonCount > DMA_CNT) { + /* not wait. */ + } else if (u32MonCount < u32Count) { + while (0UL != (DMAx->CHEN & DMA_CHEN_CHEN_3)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT1) { + u8DmaChEnState = DMA_IDLE; + return LL_ERR_TIMEOUT; + } + } + } else { + /* else */ + } + } + } + + if (ENABLE == enNewState) { + DMAx->CHEN |= (1UL << u8Ch) & DMA_CHEN_CHEN; + } else { + DMAx->CHEN &= (~(1UL << u8Ch)) & DMA_CHEN_CHEN; + } + + u8DmaChEnState = DMA_IDLE; + return LL_OK; + } + + return LL_ERR; +} + +/** + * @brief Get DMA transfer status. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Status DMA transfer status. @ref DMA_Trans_Status_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t DMA_GetTransStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_STAT(u32Status)); + + return ((0U != READ_REG32_BIT(DMAx->CHSTAT, u32Status)) ? SET : RESET); +} + +/** + * @brief Get DMA request status. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Status DMA request status. @ref DMA_Req_Status_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t DMA_GetRequestStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_REQ_STAT(u32Status)); + + return ((0U != READ_REG32_BIT(DMAx->REQSTAT, u32Status)) ? SET : RESET); +} + +/** + * @brief Config DMA source address. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Addr DMA source address. + * @retval int32_t + */ +int32_t DMA_SetSrcAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr) +{ + uint16_t u16Timeout = 0U; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), u32Addr); + + /* Ensure the address has been written */ + while (u32Addr != READ_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch))) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), u32Addr); + } + } + return LL_OK; +} + +/** + * @brief Config DMA destination address. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Addr DMA destination address. + * @retval int32_t + */ +int32_t DMA_SetDestAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr) +{ + uint16_t u16Timeout = 0U; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), u32Addr); + + /* Ensure the address has been written */ + while (u32Addr != READ_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch))) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), u32Addr); + } + } + return LL_OK; +} + +/** + * @brief Config DMA transfer count. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u16Count DMA transfer count (0: infinite, 1 ~ 65535). + * @retval int32_t + */ +int32_t DMA_SetTransCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Count) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *DTCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + DTCTLx = &DMA_CH_REG(DMAx->DTCTL0, u8Ch); + MODIFY_REG32(*DTCTLx, DMA_DTCTL_CNT, ((uint32_t)(u16Count) << DMA_DTCTL_CNT_POS)); + /* Ensure the transfer count has been written */ + while (u16Count != (READ_REG32_BIT(*DTCTLx, DMA_DTCTL_CNT) >> DMA_DTCTL_CNT_POS)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*DTCTLx, DMA_DTCTL_CNT, ((uint32_t)(u16Count) << DMA_DTCTL_CNT_POS)); + } + } + return LL_OK; +} + +/** + * @brief Config DMA block size per transfer. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u16Size DMA block size (range: 1~1024, 0 is for 1024). + * @retval int32_t + */ +int32_t DMA_SetBlockSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *DTCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(u16Size)); + + DTCTLx = &DMA_CH_REG(DMAx->DTCTL0, u8Ch); + MODIFY_REG32(*DTCTLx, DMA_DTCTL_BLKSIZE, u16Size); + + /* Ensure the block size has been written */ + while (u16Size != READ_REG32_BIT(*DTCTLx, DMA_DTCTL_BLKSIZE)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*DTCTLx, DMA_DTCTL_BLKSIZE, u16Size); + } + } + + return LL_OK; +} + +/** + * @brief Config DMA source repeat size. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u16Size DMA source repeat size (0, 1024: 1024, 1 ~ 1023). + * @retval int32_t + */ +int32_t DMA_SetSrcRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *RPTx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(u16Size)); + + RPTx = &DMA_CH_REG(DMAx->RPT0, u8Ch); + MODIFY_REG32(*RPTx, DMA_RPT_SRPT, ((uint32_t)(u16Size) << DMA_RPT_SRPT_POS)); + + /* Ensure the repeat size has been written */ + while (u16Size != (READ_REG32_BIT(*RPTx, DMA_RPT_SRPT) >> DMA_RPT_SRPT_POS)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*RPTx, DMA_RPT_SRPT, ((uint32_t)(u16Size) << DMA_RPT_SRPT_POS)); + } + } + + return LL_OK; +} + +/** + * @brief Config DMA destination repeat size. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u16Size DMA destination repeat size (0, 1024: 1024, 1 ~ 1023). + * @retval int32_t + */ +int32_t DMA_SetDestRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *RPTx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(u16Size)); + + RPTx = &DMA_CH_REG(DMAx->RPT0, u8Ch); + MODIFY_REG32(*RPTx, DMA_RPT_DRPT, ((uint32_t)(u16Size) << DMA_RPT_DRPT_POS)); + + /* Ensure the repeat size has been written */ + while (u16Size != (READ_REG32_BIT(*RPTx, DMA_RPT_DRPT) >> DMA_RPT_DRPT_POS)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*RPTx, DMA_RPT_DRPT, ((uint32_t)(u16Size) << DMA_RPT_DRPT_POS)); + } + } + + return LL_OK; +} + +/** + * @brief Config DMA source transfter count under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Count DMA source transfer count (0, 4096: 4096, 1 ~ 4095). + * @retval int32_t + */ +int32_t DMA_SetNonSeqSrcCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *SNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(u32Count)); + + SNSEQCTLx = &DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch); + MODIFY_REG32(*SNSEQCTLx, DMA_SNSEQCTL_SNSCNT, (u32Count << DMA_SNSEQCTL_SNSCNT_POS)); + + /* Ensure the count has been written */ + while (u32Count != (READ_REG32_BIT(*SNSEQCTLx, DMA_SNSEQCTL_SNSCNT) >> DMA_SNSEQCTL_SNSCNT_POS)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*SNSEQCTLx, DMA_SNSEQCTL_SNSCNT, (u32Count << DMA_SNSEQCTL_SNSCNT_POS)); + } + } + + return LL_OK; +} + +/** + * @brief Config DMA destination transfter count under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Count DMA destination transfer count (0, 4096: 4096, 1 ~ 4095). + * @retval int32_t + */ +int32_t DMA_SetNonSeqDestCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *DNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(u32Count)); + + DNSEQCTLx = &DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch); + MODIFY_REG32(*DNSEQCTLx, DMA_DNSEQCTL_DNSCNT, (u32Count << DMA_DNSEQCTL_DNSCNT_POS)); + + /* Ensure the count has been written */ + while (u32Count != (READ_REG32_BIT(*DNSEQCTLx, DMA_DNSEQCTL_DNSCNT) >> DMA_DNSEQCTL_DNSCNT_POS)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*DNSEQCTLx, DMA_DNSEQCTL_DNSCNT, (u32Count << DMA_DNSEQCTL_DNSCNT_POS)); + } + } + + return LL_OK; +} + +/** + * @brief Config DMA source offset number under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Offset DMA source offset (0 ~ 2^20 - 1). + * @retval int32_t + */ +int32_t DMA_SetNonSeqSrcOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *SNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(u32Offset)); + + SNSEQCTLx = &DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch); + MODIFY_REG32(*SNSEQCTLx, DMA_SNSEQCTL_SOFFSET, u32Offset); + + /* Ensure the offset has been written */ + while (u32Offset != READ_REG32_BIT(*SNSEQCTLx, DMA_SNSEQCTL_SOFFSET)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*SNSEQCTLx, DMA_SNSEQCTL_SOFFSET, u32Offset); + } + } + + return LL_OK; +} + +/** + * @brief Config DMA destination offset number under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Offset DMA destination offset (0 ~ 2^20 - 1). + * @retval int32_t + */ +int32_t DMA_SetNonSeqDestOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset) +{ + uint16_t u16Timeout = 0U; + __IO uint32_t *DNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(u32Offset)); + + DNSEQCTLx = &DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch); + MODIFY_REG32(*DNSEQCTLx, DMA_DNSEQCTL_DOFFSET, u32Offset); + + /* Ensure the offset has been written */ + while (u32Offset != READ_REG32_BIT(*DNSEQCTLx, DMA_DNSEQCTL_DOFFSET)) { + u16Timeout++; + if (u16Timeout > DMATIMEOUT2) { + return LL_ERR_TIMEOUT; + } else { + MODIFY_REG32(*DNSEQCTLx, DMA_DNSEQCTL_DOFFSET, u32Offset); + } + } + + return LL_OK; +} + +/** + * @brief De-Initialize DMA function. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval None + */ +void DMA_DeInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + /* Disable */ + CLR_REG32_BIT(DMAx->CHEN, DMA_CHEN_CHEN << u8Ch); + + /* Set default value. */ + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), 0UL); + WRITE_REG32(DMAx->INTMASK0, 0UL); + WRITE_REG32(DMAx->INTMASK1, 0UL); + WRITE_REG32(DMAx->INTCLR0, DMA_INTCLR0_CLRTRNERR | DMA_INTCLR0_CLRREQERR); + WRITE_REG32(DMAx->INTCLR1, DMA_INTCLR1_CLRTC | DMA_INTCLR1_CLRBTC); + + WRITE_REG32(DMA_CH_REG(DMAx->DTCTL0, u8Ch), 1UL); + WRITE_REG32(DMA_CH_REG(DMAx->CHCTL0, u8Ch), 0x00001000UL); + WRITE_REG32(DMA_CH_REG(DMAx->RPT0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), 0UL); + +} + +/** + * @brief Initialize DMA config structure. Fill each pstcDmaInit with default value + * @param [in] pstcDmaInit Pointer to a stc_dma_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_StructInit(stc_dma_init_t *pstcDmaInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaInit->u32IntEn = DMA_INT_DISABLE; + pstcDmaInit->u32SrcAddr = 0x00UL; + pstcDmaInit->u32DestAddr = 0x00UL; + pstcDmaInit->u32DataWidth = DMA_DATAWIDTH_8BIT; + pstcDmaInit->u32BlockSize = 0x00UL; + pstcDmaInit->u32TransCount = 0x01UL; + pstcDmaInit->u32SrcAddrInc = DMA_SRC_ADDR_FIX; + pstcDmaInit->u32DestAddrInc = DMA_DEST_ADDR_FIX; + } + return i32Ret; +} + +/** + * @brief DMA basic function initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaInit DMA config structure. + * @arg u32IntEn DMA interrupt ENABLE or DISABLE. + * @arg u32SrcAddr DMA source address. + * @arg u32DestAddr DMA destination address. + * @arg u32DataWidth DMA data width. + * @arg u32BlockSize DMA block size. + * @arg u32TransCount DMA transfer count. + * @arg u32SrcAddrInc DMA source address direction. + * @arg u32DestAddrInc DMA destination address direction. + * @retval int32_t: + * - LL_OK: DMA basic function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_Init(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_DATA_WIDTH(pstcDmaInit->u32DataWidth)); + DDL_ASSERT(IS_DMA_SADDR_MD(pstcDmaInit->u32SrcAddrInc)); + DDL_ASSERT(IS_DMA_DADDR_MD(pstcDmaInit->u32DestAddrInc)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(pstcDmaInit->u32BlockSize)); + DDL_ASSERT(IS_DMA_INT_FUNC(pstcDmaInit->u32IntEn)); + + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), pstcDmaInit->u32SrcAddr); + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), pstcDmaInit->u32DestAddr); + + WRITE_REG32(DMA_CH_REG(DMAx->DTCTL0, u8Ch), \ + (pstcDmaInit->u32BlockSize | (pstcDmaInit->u32TransCount << DMA_DTCTL_CNT_POS))); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SINC | DMA_CHCTL_DINC | DMA_CHCTL_HSIZE | DMA_CHCTL_IE), \ + (pstcDmaInit->u32IntEn | pstcDmaInit->u32DataWidth | pstcDmaInit->u32SrcAddrInc | \ + pstcDmaInit->u32DestAddrInc)); + + } + return i32Ret; +} + +/** + * @brief Initialize DMA repeat mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaRepeatInit Pointer to a stc_dma_repeat_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA repeat mode config structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_RepeatStructInit(stc_dma_repeat_init_t *pstcDmaRepeatInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaRepeatInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaRepeatInit->u32Mode = DMA_RPT_NONE; + pstcDmaRepeatInit->u32SrcCount = 0x00UL; + pstcDmaRepeatInit->u32DestCount = 0x00UL; + } + return i32Ret; +} + +/** + * @brief DMA repeat mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaRepeatInit DMA repeat mode config structure. + * @note Call this function after DMA_Init(); + */ +int32_t DMA_RepeatInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_repeat_init_t *pstcDmaRepeatInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaRepeatInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_RPT_MD(pstcDmaRepeatInit->u32Mode)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(pstcDmaRepeatInit->u32DestCount)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(pstcDmaRepeatInit->u32SrcCount)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SRPTEN | DMA_CHCTL_DRPTEN), pstcDmaRepeatInit->u32Mode); + + WRITE_REG32(DMA_CH_REG(DMAx->RPT0, u8Ch), \ + ((pstcDmaRepeatInit->u32DestCount << DMA_RPT_DRPT_POS) | pstcDmaRepeatInit->u32SrcCount)); + + } + return i32Ret; +} + +/** + * @brief Initialize DMA non-sequence mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaNonSeqInit Pointer to a stc_dma_nonseq_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA non-sequence mode structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaNonSeqInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaNonSeqInit->u32Mode = DMA_NON_SEQ_NONE; + pstcDmaNonSeqInit->u32SrcCount = 0x00UL; + pstcDmaNonSeqInit->u32SrcOffset = 0x00UL; + pstcDmaNonSeqInit->u32DestCount = 0x00UL; + pstcDmaNonSeqInit->u32DestOffset = 0x00UL; + } + return i32Ret; +} + +/** + * @brief DMA non-sequence mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaNonSeqInit DMA non-sequence mode config structure. + * @retval int32_t: + * - LL_OK: DMA non-sequence function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + * @note Call this function after DMA_Init(); + */ +int32_t DMA_NonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaNonSeqInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_NON_SEQ_MD(pstcDmaNonSeqInit->u32Mode)); + + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(pstcDmaNonSeqInit->u32SrcCount)); + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(pstcDmaNonSeqInit->u32DestCount)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(pstcDmaNonSeqInit->u32SrcOffset)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(pstcDmaNonSeqInit->u32DestOffset)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN), pstcDmaNonSeqInit->u32Mode); + + WRITE_REG32(DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch), ((pstcDmaNonSeqInit->u32SrcCount << DMA_SNSEQCTL_SNSCNT_POS) | \ + pstcDmaNonSeqInit->u32SrcOffset)); + WRITE_REG32(DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch), ((pstcDmaNonSeqInit->u32DestCount << DMA_DNSEQCTL_DNSCNT_POS) | \ + pstcDmaNonSeqInit->u32DestOffset)); + + } + return i32Ret; +} + +/** + * @brief Initialize DMA Linked List Pointer (hereafter, LLP) mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaLlpInit Pointer to a stc_dma_llp_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA LLP mode config structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaLlpInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaLlpInit->u32State = DMA_LLP_DISABLE; + pstcDmaLlpInit->u32Mode = DMA_LLP_WAIT; + pstcDmaLlpInit->u32Addr = 0x00UL; + } + return i32Ret; +} + +/** + * @brief DMA LLP mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaLlpInit DMA LLP config structure. + * @arg u32State DMA LLP ENABLE or DISABLE. + * @arg u32Mode DMA LLP auto-run or wait request. + * @arg u32Addr DMA LLP next list pointer address. + * @arg u32AddrSelect DMA LLP address mode. + * @retval int32_t: + * - LL_OK: DMA LLP function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + * @note Call this function after DMA_Init(); + */ +int32_t DMA_LlpInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaLlpInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_LLP_EN(pstcDmaLlpInit->u32State)); + DDL_ASSERT(IS_DMA_LLP_MD(pstcDmaLlpInit->u32Mode)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_LLPEN | DMA_CHCTL_LLPRUN), \ + (pstcDmaLlpInit->u32State | pstcDmaLlpInit->u32Mode)); + + WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), pstcDmaLlpInit->u32Addr & DMA_LLP_LLP); + + } + + return i32Ret; +} + +/** + * @brief Config DMA LLP value. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Addr Next link pointer address for DMA LLP mode. + * @retval None + */ +void DMA_SetLlpAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr) +{ + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), (u32Addr & DMA_LLP_LLP)); +} + +/** + * @brief DMA LLP ENABLE or DISABLE. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_LlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_LLPEN); + + } else { + CLR_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_LLPEN); + + } +} + +/** + * @brief DMA reconfig function ENABLE or DISABLE. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_ReconfigCmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(DMAx->RCFGCTL, 1UL); + } else { + CLR_REG32_BIT(DMAx->RCFGCTL, 1UL); + } +} + +/** + * @brief DMA LLP ENABLE or DISABLE for reconfig function. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_ReconfigLlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(DMAx->RCFGCTL, DMA_RCFGCTL_RCFGCHS | DMA_RCFGCTL_RCFGLLP, \ + ((uint32_t)(u8Ch) << DMA_RCFGCTL_RCFGCHS_POS) | ((uint32_t)enNewState << DMA_RCFGCTL_RCFGLLP_POS)); +} + +/** + * @brief Initialize DMA re-config mode config structure. + * Fill each pstcDmaRCInit with default value + * @param [in] pstcDmaRCInit Pointer to a stc_dma_reconfig_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA reconfig mode config structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_ReconfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaRCInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaRCInit->u32CountMode = DMA_RC_CNT_KEEP; + pstcDmaRCInit->u32DestAddrMode = DMA_RC_DEST_ADDR_KEEP; + pstcDmaRCInit->u32SrcAddrMode = DMA_RC_SRC_ADDR_KEEP; + } + return i32Ret; +} + +/** + * @brief DMA reconfig mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaRCInit DMA reconfig mode config structure + * @arg u32CountMode DMA reconfig count mode. + * @arg u32DestAddrMode DMA reconfig destination address mode. + * @arg u32SrcAddrMode DMA reconfig source address mode. + * @retval int32_t: + * - LL_OK: DMA reconfig function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer +*/ +int32_t DMA_ReconfigInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaRCInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_RC_CNT_MD(pstcDmaRCInit->u32CountMode)); + DDL_ASSERT(IS_DMA_RC_DA_MD(pstcDmaRCInit->u32DestAddrMode)); + DDL_ASSERT(IS_DMA_RC_SA_MD(pstcDmaRCInit->u32SrcAddrMode)); + + MODIFY_REG32(DMAx->RCFGCTL, \ + (DMA_RCFGCTL_RCFGCHS | DMA_RCFGCTL_SARMD | DMA_RCFGCTL_DARMD | DMA_RCFGCTL_CNTMD), \ + (pstcDmaRCInit->u32CountMode | pstcDmaRCInit->u32SrcAddrMode | \ + pstcDmaRCInit->u32DestAddrMode | ((uint32_t)(u8Ch) << DMA_RCFGCTL_RCFGCHS_POS))); + } + return i32Ret; +} + +/** + * @brief DMA get current source address + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source address. + */ +uint32_t DMA_GetSrcAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return READ_REG32(DMA_CH_REG(DMAx->MONSAR0, u8Ch)); +} + +/** + * @brief DMA get current destination address + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination address. + */ +uint32_t DMA_GetDestAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return READ_REG32(DMA_CH_REG(DMAx->MONDAR0, u8Ch)); +} + +/** + * @brief DMA get current transfer count + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current transfer count. + */ +uint32_t DMA_GetTransCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONDTCTL0, u8Ch)) >> DMA_DTCTL_CNT_POS) & 0xFFFFUL); +} + +/** + * @brief DMA get current block size + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current block size. + */ +uint32_t DMA_GetBlockSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONDTCTL0, u8Ch), DMA_DTCTL_BLKSIZE)); +} + +/** + * @brief DMA get current source repeat size + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source repeat size. + */ +uint32_t DMA_GetSrcRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONRPT0, u8Ch), DMA_RPT_SRPT)); +} + +/** + * @brief DMA get current destination repeat size + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination repeat size. + */ +uint32_t DMA_GetDestRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONRPT0, u8Ch)) >> DMA_RPT_DRPT_POS) & 0x3FFUL); +} + +/** + * @brief DMA get current source count in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source count in non-sequence mode. + */ +uint32_t DMA_GetNonSeqSrcCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONSNSEQCTL0, u8Ch)) >> DMA_SNSEQCTLB_SNSCNTB_POS) & 0xFFFUL); +} + +/** + * @brief DMA get current destination count in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA,, x can be 0-1 + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination count in non-sequence mode. + */ +uint32_t DMA_GetNonSeqDestCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONDNSEQCTL0, u8Ch)) >> DMA_DNSEQCTL_DNSCNT_POS) & 0xFFFUL); +} + +/** + * @brief DMA get current source offset in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source offset in non-sequence mode. + */ +uint32_t DMA_GetNonSeqSrcOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONSNSEQCTL0, u8Ch), DMA_SNSEQCTL_SOFFSET)); +} + +/** + * @brief DMA get current destination offset in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination offset in non-sequence mode. + */ +uint32_t DMA_GetNonSeqDestOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONDNSEQCTL0, u8Ch), DMA_DNSEQCTL_DOFFSET)); +} + +/** + * @} + */ + +#endif /* LL_DMA_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_efm.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_efm.c new file mode 100644 index 0000000000..6b034325fb --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_efm.c @@ -0,0 +1,1104 @@ +/** + ******************************************************************************* + * @file hc32_ll_efm.c + * @brief This file provides firmware functions to manage the Embedded Flash + * Memory unit (EFM). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_efm.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EFM EFM + * @brief Embedded Flash Management Driver Library + * @{ + */ + +#if (LL_EFM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EFM_Local_Macros EFM Local Macros + * @{ + */ +#define REG_LEN (32U) +#define EFM_TIMEOUT (HCLK_VALUE / 20000UL) /* EFM wait read timeout */ +#define EFM_PGM_TIMEOUT (HCLK_VALUE / 20000UL) /* EFM Program timeout max 53us */ +#define EFM_ERASE_TIMEOUT (HCLK_VALUE / 50UL) /* EFM Erase timeout max 20ms */ +#define EFM_SEQ_PGM_TIMEOUT (HCLK_VALUE / 62500UL) /* EFM Sequence Program timeout max 16us */ + +#define REMCR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_EFM->MMF_REMCR0) + (4UL * (x)))) + +/** + * @defgroup EFM_Configuration_Bit_Mask EFM Configuration Bit Mask + * @{ + */ +#define EFM_CACHE_ALL (EFM_FRMC_CRST | EFM_FRMC_CACHE) + +/** + * @} + */ + +/** + * @defgroup EFM_Check_Parameters_Validity EFM Check Parameters Validity + * @{ + */ +/* Parameter validity check for efm chip . */ +#define IS_EFM_CHIP(x) ((x) == EFM_CHIP_ALL) + +/* Parameter validity check for flash latency. */ +#define IS_EFM_WAIT_CYCLE(x) ((x) <= EFM_WAIT_CYCLE15) + +/* Parameter validity check for operate mode. */ +#define IS_EFM_OPERATE_MD(x) \ +( ((x) == EFM_MD_PGM_SINGLE) || \ + ((x) == EFM_MD_PGM_READBACK) || \ + ((x) == EFM_MD_PGM_SEQ) || \ + ((x) == EFM_MD_ERASE_SECTOR) || \ + ((x) == EFM_MD_ERASE_ALL_CHIP) || \ + ((x) == EFM_MD_READONLY)) + +/* Parameter validity check for flash interrupt select. */ +#define IS_EFM_INT_SEL(x) (((x) | EFM_INT_ALL) == EFM_INT_ALL) + +/* Parameter validity check for flash flag. */ +#define IS_EFM_FLAG(x) (((x) | EFM_FLAG_ALL) == EFM_FLAG_ALL) + +/* Parameter validity check for flash clear flag. */ +#define IS_EFM_CLRFLAG(x) (((x) | EFM_FLAG_ALL) == EFM_FLAG_ALL) + +/* Parameter validity check for bus status while flash program or erase. */ +#define IS_EFM_BUS_STATUS(x) \ +( ((x) == EFM_BUS_HOLD) || \ + ((x) == EFM_BUS_RELEASE)) + +/* Parameter validity check for efm address. */ +#define IS_EFM_ADDR(x) \ +( ((x) <= EFM_END_ADDR) || \ + (((x) >= EFM_OTP_START_ADDR) && ((x) <= EFM_OTP_END_ADDR))) + +/* Parameter validity check for efm erase address. */ +#define IS_EFM_ERASE_ADDR(x) ((x) <= EFM_END_ADDR) + +/* Parameter validity check for efm erase mode . */ +#define IS_EFM_ERASE_MD(x) \ +( ((x) == EFM_MD_ERASE_ONE_CHIP) || \ + ((x) == EFM_MD_ERASE_FULL)) + +/* Parameter validity check for EFM lock status. */ +#define IS_EFM_REG_UNLOCK() (CM_EFM->FAPRT == 0x00000001UL) + +/* Parameter validity check for EFM_FWMC register lock status. */ +#define IS_EFM_FWMC_UNLOCK() (bCM_EFM->FWMC_b.PEMODE == 1U) + +/* Parameter validity check for EFM remap lock status. */ +#define IS_EFM_REMAP_UNLOCK() (CM_EFM->MMF_REMPRT == 0x00000001UL) + +/* Parameter validity check for EFM remap index */ +#define IS_EFM_REMAP_IDX(x) \ +( ((x) == EFM_REMAP_IDX0) || \ + ((x) == EFM_REMAP_IDX1)) + +/* Parameter validity check for EFM remap size */ +#define IS_EFM_REMAP_SIZE(x) \ +( ((x) >= EFM_REMAP_4K) && \ + ((x) <= EFM_REMAP_512K)) + +/* Parameter validity check for EFM remap address */ +#define IS_EFM_REMAP_ADDR(x) \ +( ((x) <= EFM_REMAP_ROM_END_ADDR) || \ + (((x) >= EFM_REMAP_RAM_START_ADDR) && \ + ((x) <= EFM_REMAP_RAM_END_ADDR))) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup EFM_Local_Functions EFM Local Functions + * @{ + */ +/** + * @brief Wait EFM flag. + * @param [in] u32Flag Specifies the flag to be wait. @ref EFM_Flag_Sel + * @param [in] u32Time Specifies the time to wait while the flag not be set. + * @retval int32_t: + * - LL_OK: Flag was set. + * - LL_ERR_TIMEOUT: Flag was not set. + * @note None + */ +static int32_t EFM_WaitFlag(uint32_t u32Flag, uint32_t u32Time) +{ + __IO uint32_t u32Timeout = 0UL; + int32_t i32Ret = LL_OK; + + while (SET != EFM_GetStatus(u32Flag)) { + u32Timeout++; + if (u32Timeout > u32Time) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief Clear EFM flag. + * @param [in] u32Flag Specifies the flag to be wait. @ref EFM_Flag_Sel + * @retval int32_t: + * - LL_OK: Flag was set. + * - LL_ERR_TIMEOUT: Flag was not set. + * @note None + */ +static int32_t EFM_ClearFlag(uint32_t u32Flag) +{ + uint32_t u32Time = EFM_TIMEOUT; + __IO uint32_t u32Timeout = 0UL; + int32_t i32Ret = LL_OK; + + while (RESET != EFM_GetStatus(u32Flag)) { + EFM_ClearStatus(u32Flag); + u32Timeout++; + if (u32Timeout > u32Time) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @} + */ + +/** + * @defgroup EFM_Global_Functions EFM Global Functions + * @{ + */ + +/** + * @brief Enable or disable EFM. + * @param [in] u32Flash Specifies the FLASH. @ref EFM_Chip_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note + */ +void EFM_Cmd(uint32_t u32Flash, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_CHIP(u32Flash)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_EFM->FSTP, u32Flash); + } else { + SET_REG32_BIT(CM_EFM->FSTP, u32Flash); + } +} + +/** + * @brief Set the efm read wait cycles. + * @param [in] u32WaitCycle Specifies the efm read wait cycles. + * @arg This parameter can be of a value of @ref EFM_Wait_Cycle + * @retval int32_t: + * - LL_OK: Program successful... + * - LL_ERR_TIMEOUT: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_SetWaitCycle(uint32_t u32WaitCycle) +{ + uint32_t u32Timeout = 0UL; + + /* Param valid check */ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_WAIT_CYCLE(u32WaitCycle)); + + MODIFY_REG32(CM_EFM->FRMC, EFM_FRMC_FLWT, u32WaitCycle); + while (u32WaitCycle != READ_REG32_BIT(CM_EFM->FRMC, EFM_FRMC_FLWT)) { + u32Timeout++; + if (u32Timeout > EFM_TIMEOUT) { + return LL_ERR_TIMEOUT; + } + } + return LL_OK; +} + +/** + * @brief Enable or disable the flash data cache and instruction cache. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_CacheCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.CACHE, enNewState); +} + +/** + * @brief Enable or disable the Read of low-voltage mode. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_LowVoltageReadCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.SLPMD, enNewState); +} + +/** + * @brief Enable or disable the EFM swap function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: Program successful... + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_SwapCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + if (enNewState == ENABLE) { + /* Set Program single mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + /* Enable flash swap function */ + RW_MEM32(EFM_SWAP_ADDR) = EFM_SWAP_DATA; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + } else { + /* Set Sector erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR); + /* Disable flash switch function */ + RW_MEM32(EFM_SWAP_ADDR) = 0x0UL; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + } + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief Checks whether the swap function enable or disable. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EFM_GetSwapStatus(void) +{ + return ((0UL == READ_REG32(bCM_EFM->FSWP_b.FSWP)) ? RESET : SET); +} + +/** + * @brief Enable or disable the EFM low-voltage mode. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_LowVoltageCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_EFM->FRMC_b.LVM, enNewState); +} + +/** + * @brief Set the FLASH erase program mode . + * @param [in] u32Mode Specifies the FLASH erase program mode. + * @arg This parameter can be of a value of @ref EFM_OperateMode_Sel + * @retval int32_t: + * - LL_OK: Set mode successfull. + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note None + */ +int32_t EFM_SetOperateMode(uint32_t u32Mode) +{ + int32_t i32Ret = LL_OK; + DDL_ASSERT(IS_EFM_OPERATE_MD(u32Mode)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_SEQ_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + + if (i32Ret == LL_OK) { + /* Set the program or erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, u32Mode); + } + return i32Ret; +} + +/** + * @brief Enable or Disable EFM interrupt. + * @param [in] u32EfmInt Specifies the FLASH interrupt source and status. @ref EFM_Interrupt_Sel + * @arg EFM_INT_OPTEND: End of EFM Operation Interrupt source + * @arg EFM_INT_PEERR: Program/erase error Interrupt source + * @arg EFM_INT_COLERR: Read collide error Interrupt source + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_IntCmd(uint32_t u32EfmInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_INT_SEL(u32EfmInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_EFM->FITE, u32EfmInt); + } else { + CLR_REG32_BIT(CM_EFM->FITE, u32EfmInt); + } +} + +/** + * @brief Check any of the specified flag is set or not. + * @param [in] u32Flag Specifies the FLASH flag to check. + * @arg This parameter can be of a value of @ref EFM_Flag_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EFM_GetAnyStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_EFM_FLAG(u32Flag)); + + return ((0UL == READ_REG32_BIT(CM_EFM->FSR, u32Flag)) ? RESET : SET); +} + +/** + * @brief Check all the specified flag is set or not. + * @param [in] u32Flag Specifies the FLASH flag to check. + * @arg This parameter can be of a value of @ref EFM_Flag_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EFM_GetStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_EFM_FLAG(u32Flag)); + + return ((u32Flag == READ_REG32_BIT(CM_EFM->FSR, u32Flag)) ? SET : RESET); +} + +/** + * @brief Clear the flash flag. + * @param [in] u32Flag Specifies the FLASH flag to clear. + * @arg This parameter can be of a value of @ref EFM_Flag_Sel + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_CLRFLAG(u32Flag)); + + SET_REG32_BIT(CM_EFM->FSCLR, u32Flag); +} + +/** + * @brief Set bus status while flash program or erase. + * @param [in] u32Status Specifies the new bus status while flash program or erase. + * This parameter can be one of the following values: + * @arg EFM_BUS_HOLD: Bus busy while flash program or erase. + * @arg EFM_BUS_RELEASE: Bus release while flash program or erase. + * @retval None + * @note None + */ +void EFM_SetBusStatus(uint32_t u32Status) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_BUS_STATUS(u32Status)); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + WRITE_REG32(bCM_EFM->FWMC_b.BUSHLDCTL, u32Status); +} + +/** + * @brief EFM read byte. + * @param [in] u32Addr The specified address to read. + * @param [in] pu8ReadBuf The specified read buffer. + * @param [in] u32ByteLen The specified length to read. + * @retval int32_t: + * - LL_OK: Read successful.. + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note None. + */ +int32_t EFM_ReadByte(uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32ByteLen) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + __IO uint8_t *pu8Buf = (uint8_t *)u32Addr; + uint32_t u32Len = u32ByteLen; + uint32_t u32ReadyFlag = EFM_FLAG_RDY; + + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_EFM_ADDR(u32Addr + u32ByteLen * 4U)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + if (NULL != pu8ReadBuf) { + + if (LL_OK == EFM_WaitFlag(u32ReadyFlag, EFM_TIMEOUT)) { + while (0UL != u32Len) { + *(pu8ReadBuf++) = *(pu8Buf++); + u32Len--; + } + i32Ret = LL_OK; + } else { + i32Ret = LL_ERR_NOT_RDY; + } + } + + return i32Ret; +} + +/** + * @brief EFM program (single program mode). + * @param [in] u32Addr The specified program address. + * @param [in] pu8Buf The pointer of specified program data. + * @param [in] u32Len The length of specified program data. + * @retval int32_t: + * - LL_OK: Program successful. + * - LL_ERR_NOT_RDY: EFM if not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_Program(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + uint32_t u32LoopWords = u32Len >> 2UL; + uint32_t u32RemainBytes = u32Len % 4UL; + uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf; + uint32_t *u32pDest = (uint32_t *)u32Addr; + uint32_t u32LastWord; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_EFM_ADDR(u32Addr + u32Len)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + u8Shift = 0U; + + /* CLear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + + while (u32LoopWords-- > 0UL) { + /* program data. */ + *u32pDest++ = *u32pSource++; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + } + + if (0U != u32RemainBytes) { + u32LastWord = *u32pSource; + u32LastWord |= 0xFFFFFFFFUL << (u32RemainBytes * 8UL); + *u32pDest++ = u32LastWord; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + + } + + /* Recover CACHE function */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + return i32Ret; +} + +/** + * @brief EFM single program mode(Word). + * @param [in] u32Addr The specified program address. + * @param [in] u32Data The specified program data. + * @retval int32_t: + * - LL_OK: Program successful.. + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_ProgramWord(uint32_t u32Addr, uint32_t u32Data) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + /* Clear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE function */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + u8Shift = 0U; + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + /* Program data. */ + RW_MEM32(u32Addr) = u32Data; + + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* Recover CACHE function */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief EFM single program with read back(Word). + * @param [in] u32Addr The specified program address. + * @param [in] u32Data The specified program data. + * @retval int32_t: + * - LL_OK: Program successful.. + * - LL_ERR: program error + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_ProgramWordReadBack(uint32_t u32Addr, uint32_t u32Data) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + /* Clear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + u8Shift = 0U; + /* Set Program and read back mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_READBACK); + /* Program data. */ + RW_MEM32(u32Addr) = (uint32_t)u32Data; + + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + + /* Get the flag MISMTCH */ + if (SET == EFM_GetStatus(EFM_FLAG_PGMISMTCH << u8Shift)) { + /* Clear flag PGMISMTCH */ + EFM_ClearStatus(EFM_FLAG_PGMISMTCH << u8Shift); + i32Ret = LL_ERR; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* recover CACHE function */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief EFM program (sequence program mode). + * @param [in] u32Addr The specified program address. + * @param [in] pu8Buf The pointer of specified program data. + * @param [in] u32Len The length of specified program data. + * @retval int32_t: + * - LL_OK: Program successful.. + * - LL_ERR_TIMEOUT: program error timeout + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_SequenceProgram(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint32_t u32LoopWords = u32Len >> 2UL; + uint32_t u32RemainBytes = u32Len % 4UL; + uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf; + uint32_t *u32pDest = (uint32_t *)u32Addr; + uint8_t u8Shift = 0U; + uint32_t u32LastWord; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_EFM_ADDR(u32Addr + u32Len)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + /* CLear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set sequence program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SEQ); + + while (u32LoopWords-- > 0UL) { + /* program data. */ + *u32pDest++ = *u32pSource++; + /* wait for operation end flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_OPTEND << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_TIMEOUT; + } + /* Clear operation end flag */ + if (LL_ERR_TIMEOUT == EFM_ClearFlag(EFM_FLAG_OPTEND << u8Shift)) { + i32Ret = LL_ERR_TIMEOUT; + } + } + + if (0U != u32RemainBytes) { + u32LastWord = *u32pSource; + u32LastWord |= 0xFFFFFFFFUL << (u32RemainBytes * 8UL); + *u32pDest++ = u32LastWord; + + /* wait for operation end flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_OPTEND << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_TIMEOUT; + } + /* Clear operation end flag */ + if (LL_ERR_TIMEOUT == EFM_ClearFlag(EFM_FLAG_OPTEND << u8Shift)) { + i32Ret = LL_ERR_TIMEOUT; + } + + } + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + + /* Recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + return i32Ret; +} + +/** + * @brief EFM sector erase. + * @param [in] u32Addr The address in the specified sector. + * @retval int32_t: + * - LL_OK: Erase successful. + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_SectorErase(uint32_t u32Addr) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + + DDL_ASSERT(IS_EFM_ERASE_ADDR(u32Addr)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + /* CLear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + u8Shift = 0U; + /* Set sector erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR); + + /* Erase */ + RW_MEM32(u32Addr) = 0UL; + + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* Clear the operation end flag */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* Recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief EFM chip erase. + * @param [in] u8Chip Specifies the chip to be erased. + * @arg EFM_CHIP0 Chip0 + * @arg EFM_CHIP1 Chip1 + * @arg EFM_CHIP_ALL All Chip + * @retval int32_t: + * - LL_OK: Erase successful.. + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_ChipErase(uint8_t u8Chip) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint32_t u32Addr = 0UL; + uint8_t u8Shift; + + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_CHIP(u8Chip)); + + u8Shift = 0U; + + /* CLear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set chip erase mode. */ + if (EFM_CHIP_ALL == u8Chip) { + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_ALL_CHIP); + } else { + } + /* Erase */ + RW_MEM32(u32Addr) = 0UL; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + return i32Ret; +} + +/** + * @brief FWMC register write enable or disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note None + */ +void EFM_FWMC_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_EFM->FWMC_b.PEMODE, enNewState); +} + +/** + * @brief Set flash protect area. + * @param [in] u32StartAddr Start address of protect area. + * @param [in] u32EndAddr End address of protect area. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_SetWindowProtectAddr(uint32_t u32StartAddr, uint32_t u32EndAddr) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32StartAddr)); + DDL_ASSERT(IS_EFM_ADDR(u32EndAddr)); + /* Set protect area start address */ + WRITE_REG32(CM_EFM->FPMTSW, u32StartAddr); + /* Set protect area end address */ + WRITE_REG32(CM_EFM->FPMTEW, u32EndAddr); +} + +/** + * @brief EFM OTP lock. + * @param [in] u32Addr Specifies the OTP block + * @retval int32_t: + * - LL_OK: Lock successful.. + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note The address should be word align. + * Call EFM_REG_Unlock() and EFM_OTP_WP_Unlock() unlock EFM_FWMC register first. + */ +int32_t EFM_OTP_Lock(uint32_t u32Addr) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + + if ((u32Addr >= EFM_OTP_LOCK_ADDR_START) && (u32Addr < EFM_OTP_LOCK_ADDR_END)) { + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + + /* OTP latch */ + RW_MEM32(u32Addr) = (uint32_t)0UL; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* Recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + } + + return i32Ret; +} + +/** + * @brief Get unique ID. + * @param [out] pstcUID Unique ID struct + * @retval Returns the value of the unique ID + */ +void EFM_GetUID(stc_efm_unique_id_t *pstcUID) +{ + if (NULL != pstcUID) { + pstcUID->u32UniqueID0 = READ_REG32(CM_EFM->UQID0); + pstcUID->u32UniqueID1 = READ_REG32(CM_EFM->UQID1); + pstcUID->u32UniqueID2 = READ_REG32(CM_EFM->UQID2); + } +} + +/** + * @brief Init REMAP initial structure with default value. + * @param [in] pstcEfmRemapInit specifies the Parameter of REMAP. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EFM_REMAP_StructInit(stc_efm_remap_init_t *pstcEfmRemapInit) +{ + int32_t i32Ret = LL_OK; + if (NULL == pstcEfmRemapInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcEfmRemapInit->u32State = EFM_REMAP_OFF; + pstcEfmRemapInit->u32Addr = 0UL; + pstcEfmRemapInit->u32Size = EFM_REMAP_4K; + } + return i32Ret; +} + +/** + * @brief REMAP initialize. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] pstcEfmRemapInit specifies the Parameter of REMAP. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EFM_REMAP_Init(uint8_t u8RemapIdx, stc_efm_remap_init_t *pstcEfmRemapInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *REMCRx; + + if (NULL == pstcEfmRemapInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_EFM_REMAP_SIZE(pstcEfmRemapInit->u32Size)); + DDL_ASSERT(IS_EFM_REMAP_ADDR(pstcEfmRemapInit->u32Addr)); + if ((pstcEfmRemapInit->u32Addr % (1UL << pstcEfmRemapInit->u32Size)) != 0U) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + REMCRx = &REMCR_REG(u8RemapIdx); + MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_EN | EFM_MMF_REMCR_RMTADDR | EFM_MMF_REMCR_RMSIZE, \ + pstcEfmRemapInit->u32State | pstcEfmRemapInit->u32Addr | pstcEfmRemapInit->u32Size); + } + } + return i32Ret; +} + +/** + * @brief EFM REMAP de-initialize. + * @param None + * @retval None + */ +void EFM_REMAP_DeInit(void) +{ + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + + WRITE_REG32(CM_EFM->MMF_REMCR0, 0UL); + WRITE_REG32(CM_EFM->MMF_REMCR1, 0UL); +} + +/** + * @brief Enable or disable REMAP function. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EFM_REMAP_Cmd(uint8_t u8RemapIdx, en_functional_state_t enNewState) +{ + __IO uint32_t *REMCRx; + + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + REMCRx = &REMCR_REG(u8RemapIdx); + if (ENABLE == enNewState) { + SET_REG32_BIT(*REMCRx, EFM_MMF_REMCR_EN); + } else { + CLR_REG32_BIT(*REMCRx, EFM_MMF_REMCR_EN); + } +} + +/** + * @brief Set specified REMAP target address. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] u32Addr Specifies the target address. + * @retval None + */ +void EFM_REMAP_SetAddr(uint8_t u8RemapIdx, uint32_t u32Addr) +{ + __IO uint32_t *REMCRx; + + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_EFM_REMAP_ADDR(u32Addr)); + + REMCRx = &REMCR_REG(u8RemapIdx); + MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_RMTADDR, u32Addr); +} + +/** + * @brief Set specified REMAP size. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] u32Size Specifies the remap size. + * @retval None + */ +void EFM_REMAP_SetSize(uint8_t u8RemapIdx, uint32_t u32Size) +{ + __IO uint32_t *REMCRx; + + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_EFM_REMAP_SIZE(u32Size)); + + REMCRx = &REMCR_REG(u8RemapIdx); + MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_RMSIZE, u32Size); +} + +/** + * @} + */ + +#endif /* LL_EFM_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_emb.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_emb.c new file mode 100644 index 0000000000..dfcc7c30ac --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_emb.c @@ -0,0 +1,491 @@ +/** + ******************************************************************************* + * @file hc32_ll_emb.c + * @brief This file provides firmware functions to manage the EMB + * (Emergency Brake). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_emb.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EMB EMB + * @brief Emergency Brake Driver Library + * @{ + */ + +#if (LL_EMB_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EMB_Local_Macros EMB Local Macros + * @{ + */ + +/** + * @defgroup EMB_Check_Parameters_Validity EMB Check Parameters Validity + * @{ + */ +#define IS_EMB_GROUP(x) \ +( ((x) == CM_EMB0) || \ + ((x) == CM_EMB1) || \ + ((x) == CM_EMB2) || \ + ((x) == CM_EMB3)) +#define IS_EMB_TMR4_GROUP(x) \ +( ((x) == CM_EMB1) || \ + ((x) == CM_EMB2) || \ + ((x) == CM_EMB3)) +#define IS_EMB_TMR6_GROUP(x) ((x) == CM_EMB0) + +#define IS_EMB_OSC_STAT(x) \ +( ((x) == EMB_OSC_ENABLE) || \ + ((x) == EMB_OSC_DISABLE)) + +#define IS_EMB_TMR4_PWM_W_STAT(x) \ +( ((x) == EMB_TMR4_PWM_W_ENABLE) || \ + ((x) == EMB_TMR4_PWM_W_DISABLE)) + +#define IS_EMB_DETECT_TMR4_PWM_W_LVL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_W_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_W_BOTH_HIGH)) + +#define IS_EMB_TMR4_PWM_V_STAT(x) \ +( ((x) == EMB_TMR4_PWM_V_ENABLE) || \ + ((x) == EMB_TMR4_PWM_V_DISABLE)) + +#define IS_EMB_DETECT_TMR4_PWM_V_LVL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_V_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_V_BOTH_HIGH)) + +#define IS_EMB_TMR4_PWM_U_STAT(x) \ +( ((x) == EMB_TMR4_PWM_U_ENABLE) || \ + ((x) == EMB_TMR4_PWM_U_DISABLE)) + +#define IS_EMB_DETECT_TMR4_PWM_U_LVL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_U_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_U_BOTH_HIGH)) + +#define IS_EMB_CMP1_STAT(x) \ +( ((x) == EMB_CMP1_ENABLE) || \ + ((x) == EMB_CMP1_DISABLE)) + +#define IS_EMB_CMP2_STAT(x) \ +( ((x) == EMB_CMP2_ENABLE) || \ + ((x) == EMB_CMP2_DISABLE)) + +#define IS_EMB_CMP3_STAT(x) \ +( ((x) == EMB_CMP3_ENABLE) || \ + ((x) == EMB_CMP3_DISABLE)) + +#define IS_EMB_PORT1_STAT(x) \ +( ((x) == EMB_PORT1_ENABLE) || \ + ((x) == EMB_PORT1_DISABLE)) + +#define IS_EMB_PORT1_DETECT_LVL(x) \ +( ((x) == EMB_PORT1_DETECT_LVL_LOW) || \ + ((x) == EMB_PORT1_DETECT_LVL_HIGH)) + +#define IS_EMB_PORT1_FILTER_STAT(x) \ +( ((x) == EMB_PORT1_FILTER_ENABLE) || \ + ((x) == EMB_PORT1_FILTER_DISABLE)) + +#define IS_EMB_PORT1_FILTER_DIV(x) (((x) & (~EMB_PORT1_FILTER_CLK_DIV_MASK)) == 0UL) + +#define IS_EMB_TMR6_1_PWM_STAT(x) \ +( ((x) == EMB_TMR6_1_PWM_ENABLE) || \ + ((x) == EMB_TMR6_1_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_1_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_1_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_1_PWM_BOTH_HIGH)) + +#define IS_EMB_TMR6_2_PWM_STAT(x) \ +( ((x) == EMB_TMR6_2_PWM_ENABLE) || \ + ((x) == EMB_TMR6_2_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_2_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_2_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_2_PWM_BOTH_HIGH)) + +#define IS_EMB_TMR6_3_PWM_STAT(x) \ +( ((x) == EMB_TMR6_3_PWM_ENABLE) || \ + ((x) == EMB_TMR6_3_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_3_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_3_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_3_PWM_BOTH_HIGH)) + +#define IS_VALID_EMB_INT(x) \ +( ((x) != 0UL) && \ + (((x) | EMB_INT_ALL) == EMB_INT_ALL)) + +#define IS_EMB_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | EMB_FLAG_ALL) == EMB_FLAG_ALL)) + +/** + * @} + */ + +#define EMB_PORT1_FILTER_CLK_DIV_MASK EMB_PORT1_FILTER_CLK_DIV128 +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup EMB_Global_Functions EMB Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_emb_tmr4_init_t to default values + * @param [out] pstcEmbInit Pointer to a @ref stc_emb_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR4_StructInit(stc_emb_tmr4_init_t *pstcEmbInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + /* OSC */ + pstcEmbInit->stcOsc.u32OscState = EMB_OSC_DISABLE; + + /* CMP */ + pstcEmbInit->stcCmp.u32Cmp1State = EMB_CMP1_DISABLE; + pstcEmbInit->stcCmp.u32Cmp2State = EMB_CMP2_DISABLE; + pstcEmbInit->stcCmp.u32Cmp3State = EMB_CMP3_DISABLE; + + /* Port */ + pstcEmbInit->stcPort.stcPort1.u32PortState = EMB_PORT1_DISABLE; + pstcEmbInit->stcPort.stcPort1.u32PortLevel = EMB_PORT1_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv = EMB_PORT1_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort1.u32PortFilterState = EMB_PORT1_FILTER_DISABLE; + + /* PWM */ + pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState = EMB_TMR4_PWM_U_DISABLE; + pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel = EMB_DETECT_TMR4_PWM_U_BOTH_LOW; + pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState = EMB_TMR4_PWM_V_DISABLE; + pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel = EMB_DETECT_TMR4_PWM_V_BOTH_LOW; + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState = EMB_TMR4_PWM_W_DISABLE; + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel = EMB_DETECT_TMR4_PWM_W_BOTH_LOW; + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize EMB for TMR4. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] pstcEmbInit Pointer to a @ref stc_emb_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR4_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr4_init_t *pstcEmbInit) +{ + uint32_t u32Reg1Value; + uint32_t u32Reg2Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + DDL_ASSERT(IS_EMB_TMR4_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_OSC_STAT(pstcEmbInit->stcOsc.u32OscState)); + DDL_ASSERT(IS_EMB_CMP1_STAT(pstcEmbInit->stcCmp.u32Cmp1State)); + DDL_ASSERT(IS_EMB_CMP2_STAT(pstcEmbInit->stcCmp.u32Cmp2State)); + DDL_ASSERT(IS_EMB_CMP3_STAT(pstcEmbInit->stcCmp.u32Cmp3State)); + DDL_ASSERT(IS_EMB_PORT1_STAT(pstcEmbInit->stcPort.stcPort1.u32PortState)); + DDL_ASSERT(IS_EMB_PORT1_DETECT_LVL(pstcEmbInit->stcPort.stcPort1.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_DIV(pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_STAT(pstcEmbInit->stcPort.stcPort1.u32PortFilterState)); + DDL_ASSERT(IS_EMB_TMR4_PWM_U_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_U_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR4_PWM_V_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_V_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR4_PWM_W_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_W_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel)); + + /* OSC */ + u32Reg1Value = pstcEmbInit->stcOsc.u32OscState; + u32Reg2Value = 0UL; + + /* PWM */ + u32Reg1Value |= (pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState | pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState | \ + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState); + u32Reg2Value |= (pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel | pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel | \ + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel); + + /* CMP */ + u32Reg1Value |= (pstcEmbInit->stcCmp.u32Cmp1State | pstcEmbInit->stcCmp.u32Cmp2State); + u32Reg1Value |= pstcEmbInit->stcCmp.u32Cmp3State; + + /* PORT */ + u32Reg1Value |= (pstcEmbInit->stcPort.stcPort1.u32PortState | pstcEmbInit->stcPort.stcPort1.u32PortLevel | \ + pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort1.u32PortFilterState); + + EMB_DeInit(EMBx); + + WRITE_REG32(EMBx->PWMLV, u32Reg2Value); + WRITE_REG32(EMBx->CTL, u32Reg1Value); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_emb_tmr6_init_t to default values + * @param [out] pstcEmbInit Pointer to a @ref stc_emb_tmr6_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR6_StructInit(stc_emb_tmr6_init_t *pstcEmbInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + /* OSC */ + pstcEmbInit->stcOsc.u32OscState = EMB_OSC_DISABLE; + + /* CMP */ + pstcEmbInit->stcCmp.u32Cmp1State = EMB_CMP1_DISABLE; + pstcEmbInit->stcCmp.u32Cmp2State = EMB_CMP2_DISABLE; + pstcEmbInit->stcCmp.u32Cmp3State = EMB_CMP3_DISABLE; + + /* Port */ + pstcEmbInit->stcPort.stcPort1.u32PortState = EMB_PORT1_DISABLE; + pstcEmbInit->stcPort.stcPort1.u32PortLevel = EMB_PORT1_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv = EMB_PORT1_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort1.u32PortFilterState = EMB_PORT1_FILTER_DISABLE; + /* PWM */ + pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel = EMB_DETECT_TMR6_1_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState = EMB_TMR6_1_PWM_DISABLE; + pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel = EMB_DETECT_TMR6_2_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState = EMB_TMR6_2_PWM_DISABLE; + pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmLevel = EMB_DETECT_TMR6_3_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmState = EMB_TMR6_3_PWM_DISABLE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize EMB for TMR6. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] pstcEmbInit Pointer to a @ref stc_emb_tmr6_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR6_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr6_init_t *pstcEmbInit) +{ + uint32_t u32Reg1Value; + uint32_t u32Reg2Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + DDL_ASSERT(IS_EMB_TMR6_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_OSC_STAT(pstcEmbInit->stcOsc.u32OscState)); + DDL_ASSERT(IS_EMB_CMP1_STAT(pstcEmbInit->stcCmp.u32Cmp1State)); + DDL_ASSERT(IS_EMB_CMP2_STAT(pstcEmbInit->stcCmp.u32Cmp2State)); + DDL_ASSERT(IS_EMB_CMP3_STAT(pstcEmbInit->stcCmp.u32Cmp3State)); + DDL_ASSERT(IS_EMB_PORT1_STAT(pstcEmbInit->stcPort.stcPort1.u32PortState)); + DDL_ASSERT(IS_EMB_PORT1_DETECT_LVL(pstcEmbInit->stcPort.stcPort1.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_DIV(pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_STAT(pstcEmbInit->stcPort.stcPort1.u32PortFilterState)); + DDL_ASSERT(IS_EMB_TMR6_1_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_1_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR6_2_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_2_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR6_3_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_3_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmLevel)); + + /* OSC */ + u32Reg1Value = pstcEmbInit->stcOsc.u32OscState; + u32Reg2Value = 0UL; + + /* PWM */ + u32Reg1Value |= (pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState | pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState | \ + pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmState); + u32Reg2Value |= (pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel | pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel | \ + pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmLevel); + + /* CMP */ + u32Reg1Value |= (pstcEmbInit->stcCmp.u32Cmp1State | pstcEmbInit->stcCmp.u32Cmp2State | \ + pstcEmbInit->stcCmp.u32Cmp3State); + + /* PORT */ + u32Reg1Value |= (pstcEmbInit->stcPort.stcPort1.u32PortState | pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv | \ + pstcEmbInit->stcPort.stcPort1.u32PortLevel | pstcEmbInit->stcPort.stcPort1.u32PortFilterState); + + EMB_DeInit(EMBx); + + WRITE_REG32(EMBx->PWMLV, u32Reg2Value); + WRITE_REG32(EMBx->CTL, u32Reg1Value); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize EMB function + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @retval None + */ +void EMB_DeInit(CM_EMB_TypeDef *EMBx) +{ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + + WRITE_REG32(EMBx->SOE, 0x00UL); + WRITE_REG32(EMBx->INTEN, 0x00UL); +} + +/** + * @brief Set the EMB interrupt function + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] u32IntType EMB interrupt source + * This parameter can be any composed value of the macros group @ref EMB_Interrupt. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EMB_IntCmd(CM_EMB_TypeDef *EMBx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_VALID_EMB_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(EMBx->INTEN, u32IntType); + } else { + CLR_REG32_BIT(EMBx->INTEN, u32IntType); + } +} + +/** + * @brief Get EMB flag status. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] u32Flag EMB flag + * This parameter can be any composed value(prefix with EMB_FLAG) of the macros group @ref EMB_Flag_State. + * @retval None + * @note This parameter u32Flag prefix with EMB_FLAG(eg EMB_FLAG_CMP) of the macros group @ref EMB_Flag_State. + */ +void EMB_ClearStatus(CM_EMB_TypeDef *EMBx, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_FLAG(u32Flag)); + + SET_REG32_BIT(EMBx->STATCLR, u32Flag); +} + +/** + * @brief Clear EMB flag status. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] u32Flag EMB flag + * This parameter can be any composed value of the macros group @ref EMB_Flag_State. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EMB_GetStatus(const CM_EMB_TypeDef *EMBx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_FLAG(u32Flag)); + + return (READ_REG32_BIT(EMBx->STAT, u32Flag) == 0UL) ? RESET : SET; +} + +/** + * @brief Start/stop EMB brake by software control + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EMB_SWBrake(CM_EMB_TypeDef *EMBx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(EMBx->SOE, enNewState); +} + +/** + * @} + */ + +#endif /* LL_EMB_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_event_port.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_event_port.c new file mode 100644 index 0000000000..25fef9ada4 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_event_port.c @@ -0,0 +1,442 @@ +/** + ******************************************************************************* + * @file hc32_ll_event_port.c + * @brief This file provides firmware functions to manage the Event Port (EP). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_event_port.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EVENT_PORT EVENT_PORT + * @brief Event Port Driver Library + * @{ + */ + +#if (LL_EVENT_PORT_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EP_Local_Macros Event Port Local Macros + * @{ + */ +#define EP_OFFSET (0x1CUL) +#define PEVNTDIR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTDIRR1) + (EP_OFFSET * (x)))) +#define PEVNTIDR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTIDR1) + (EP_OFFSET * (x)))) +#define PEVNTODR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTODR1) + (EP_OFFSET * (x)))) +#define PEVNTORR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTORR1) + (EP_OFFSET * (x)))) +#define PEVNTOSR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTOSR1) + (EP_OFFSET * (x)))) +#define PEVNTRIS_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTRISR1) + (EP_OFFSET * (x)))) +#define PEVNTFAL_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTFAL1) + (EP_OFFSET * (x)))) +#define PEVNTTRGSR_RST_VALUE (0x1FFUL) +#define EP_PIN_MAX (16U) + +/** + * @defgroup EP_Check_Parameters_Validity Event Port Check Parameters Validity + * @{ + */ +/*! Parameter validity check for port group. */ +#define IS_EVENT_PORT(port) \ +( ((port) == EVT_PORT_1) || \ + ((port) == EVT_PORT_2) || \ + ((port) == EVT_PORT_3) || \ + ((port) == EVT_PORT_4)) + +/*! Parameter valid check for event port trigger edge. */ +#define IS_EP_TRIG_EDGE(edge) \ +( ((edge) == EP_TRIG_NONE) || \ + ((edge) == EP_TRIG_FALLING) || \ + ((edge) == EP_TRIG_RISING) || \ + ((edge) == EP_TRIG_BOTH)) + +/*! Parameter valid check for event port initial output state. */ +#define IS_EP_STATE(state) \ +( ((state) == EVT_PIN_RESET) || \ + ((state) == EVT_PIN_SET)) + +/*! Parameter valid check for event port filter function. */ +#define IS_EP_FILTER(filter) \ +( ((filter) == EP_FILTER_OFF) || \ + ((filter) == EP_FILTER_ON)) + +/*! Parameter validity check for pin. */ +#define IS_EVENT_PIN(pin) (((pin) & EVT_PIN_MASK ) != 0x0000U) + +/*! Parameter valid check for event port operation after triggered. */ +#define IS_EP_OPS(ops) \ +( ((ops) == EP_OPS_NONE) || \ + ((ops) == EP_OPS_LOW) || \ + ((ops) == EP_OPS_HIGH) || \ + ((ops) == EP_OPS_TOGGLE)) + +/*! Parameter valid check for event port direction. */ +#define IS_EP_DIR(dir) \ +( ((dir) == EP_DIR_IN) || \ + ((dir) == EP_DIR_OUT)) + +/*! Parameter valid check for event port filter clock div. */ +#define IS_EP_FILTER_CLK(clk) \ +( ((clk) == EP_FCLK_DIV1) || \ + ((clk) == EP_FCLK_DIV8) || \ + ((clk) == EP_FCLK_DIV32) || \ + ((clk) == EP_FCLK_DIV64)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EP_Global_Functions Event Port Global Functions + * @{ + */ + +/** + * @brief Initialize Event Port. + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP port peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] pstcEventPortInit Pointer to a stc_ep_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Event Port initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EP_Init(uint8_t u8EventPort, uint16_t u16EventPin, const stc_ep_init_t *pstcEventPortInit) +{ + uint16_t u16PinPos; + int32_t i32Ret = LL_OK; + + if (NULL == pstcEventPortInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_OPS(pstcEventPortInit->u32PinTriggerOps)); + DDL_ASSERT(IS_EP_DIR(pstcEventPortInit->u32PinDir)); + DDL_ASSERT(IS_EP_STATE(pstcEventPortInit->enPinState)); + DDL_ASSERT(IS_EP_TRIG_EDGE(pstcEventPortInit->u32Edge)); + DDL_ASSERT(IS_EP_FILTER(pstcEventPortInit->u32Filter)); + DDL_ASSERT(IS_EP_FILTER_CLK(pstcEventPortInit->u32FilterClock)); + + for (u16PinPos = 0U; u16PinPos < EP_PIN_MAX; u16PinPos++) { + if ((u16EventPin & (1UL << u16PinPos)) != 0U) { + /* Direction config */ + if (EP_DIR_OUT == pstcEventPortInit->u32PinDir) { + SET_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } else { + CLR_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } + /* Set pin initial output value */ + if (EVT_PIN_SET == pstcEventPortInit->enPinState) { + SET_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); + } else { + CLR_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); + } + /* Set Pin operation after triggered */ + (void)EP_SetTriggerOps(u8EventPort, u16EventPin, pstcEventPortInit->u32PinTriggerOps); + /* Set trigger edge */ + (void)EP_SetTriggerEdge(u8EventPort, u16EventPin, pstcEventPortInit->u32Edge); + } + MODIFY_REG32(CM_AOS->PEVNTNFCR, \ + ((AOS_PEVNTNFCR_NFEN1 | AOS_PEVNTNFCR_DIVS1) << (u8EventPort * 8UL)), \ + ((pstcEventPortInit->u32Filter | pstcEventPortInit->u32FilterClock) << (u8EventPort * 8UL))); + } + } + return i32Ret; +} + +/** + * @brief De-init Event Port register to default value + * @param None + * @retval None + */ +void EP_DeInit(void) +{ + uint8_t u8EventPort; + + /* Restore all registers to default value */ + WRITE_REG32(CM_AOS->PEVNTTRGSR12, PEVNTTRGSR_RST_VALUE); + WRITE_REG32(CM_AOS->PEVNTTRGSR34, PEVNTTRGSR_RST_VALUE); + WRITE_REG32(CM_AOS->PEVNTNFCR, 0UL); + for (u8EventPort = EVT_PORT_1; u8EventPort < EVT_PORT_4; u8EventPort++) { + WRITE_REG32(PEVNTDIR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTODR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTORR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTOSR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTRIS_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTFAL_REG(u8EventPort), 0UL); + } +} + +/** + * @brief Initialize Event Port config structure. Fill each pstcEventPortInit with default value + * @param [in] pstcEventPortInit: Pointer to a stc_ep_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Event Port structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EP_StructInit(stc_ep_init_t *pstcEventPortInit) +{ + int32_t i32Ret = LL_OK; + /* Check if pointer is NULL */ + if (NULL == pstcEventPortInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Reset Event Port init structure parameters values */ + pstcEventPortInit->u32PinDir = EP_DIR_IN; + pstcEventPortInit->enPinState = EVT_PIN_RESET; + pstcEventPortInit->u32PinTriggerOps = EP_OPS_NONE; + pstcEventPortInit->u32Edge = EP_TRIG_NONE; + pstcEventPortInit->u32Filter = EP_FILTER_OFF; + pstcEventPortInit->u32FilterClock = EP_FCLK_DIV1; + } + return i32Ret; +} + +/** + * @brief Set event port trigger edge. + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP port peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] u32Edge: Trigger edge, @ref EP_Trigger_Sel for details + * @retval int32_t: + * - LL_OK: Trigger edge set successful + * - LL_ERR_INVD_PARAM: Undefined edge + */ +int32_t EP_SetTriggerEdge(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Edge) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_TRIG_EDGE(u32Edge)); + + /* Set trigger edge */ + switch (u32Edge) { + case EP_TRIG_NONE: + CLR_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + case EP_TRIG_FALLING: + SET_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + case EP_TRIG_RISING: + CLR_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + case EP_TRIG_BOTH: + SET_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + default: + i32Ret = LL_ERR_INVD_PARAM; + break; + } + return i32Ret; +} + +/** + * @brief Set event port opeartion after triggered + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] u32Ops: The operation after triggered, @ref EP_TriggerOps_Sel for details + * @retval Specified Event port pin input value + */ +int32_t EP_SetTriggerOps(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Ops) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_OPS(u32Ops)); + + switch (u32Ops) { + case EP_OPS_NONE: + CLR_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + case EP_OPS_LOW: + SET_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + case EP_OPS_HIGH: + CLR_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + case EP_OPS_TOGGLE: + SET_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + default: + i32Ret = LL_ERR_INVD_PARAM; + break; + } + return i32Ret; +} + +/** + * @brief Read specified Event port input data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval Specified Event port pin input value + */ +en_ep_state_t EP_ReadInputPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + return ((READ_REG32(PEVNTIDR_REG(u8EventPort)) & (u16EventPin)) != 0UL) ? EVT_PIN_SET : EVT_PIN_RESET; +} + +/** + * @brief Read specified Event port input data port + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the Event Port peripheral + * @retval Specified Event Port input value + */ +uint16_t EP_ReadInputPort(uint8_t u8EventPort) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + + return (uint16_t)(READ_REG32(PEVNTIDR_REG(u8EventPort)) & 0xFFFFUL); +} + +/** + * @brief Read specified Event port output data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval Specified Event port pin output value + */ +en_ep_state_t EP_ReadOutputPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + return ((READ_REG32(PEVNTODR_REG(u8EventPort)) & (u16EventPin)) != 0UL) ? EVT_PIN_SET : EVT_PIN_RESET; +} + +/** + * @brief Read specified Event port output data port + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the Event Port peripheral + * @retval Specified Event Port output value + */ +uint16_t EP_ReadOutputPort(uint8_t u8EventPort) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + + return (uint16_t)(READ_REG32(PEVNTODR_REG(u8EventPort)) & 0xFFFFUL); +} + +/** + * @brief Set specified Event port output data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval None + */ +void EP_SetPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + SET_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); +} + +/** + * @brief Reset specified Event port output data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval None + */ +void EP_ResetPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + CLR_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); +} + +/** + * @brief Set specified Event port pins direction + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] u32Dir: Pin direction + * @arg EP_DIR_IN + * @arg EP_DIR_OUT + * @retval None + */ +void EP_SetDir(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Dir) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_DIR(u32Dir)); + + if (EP_DIR_OUT == u32Dir) { + SET_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } else { + CLR_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } +} + +/** + * @} + */ + +#endif /* LL_EVENT_PORT_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcg.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcg.c new file mode 100644 index 0000000000..5082bc462f --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcg.c @@ -0,0 +1,194 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcg.c + * @brief This file provides firmware functions to manage the Function Clock + * Gate (FCG). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_fcg.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_FCG FCG + * @brief FCG Driver Library + * @{ + */ + +#if (LL_FCG_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCG_Local_Macros FCG Local Macros + * @{ + */ +#define IS_FCG0_UNLOCKED() ((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0) + +/** + * @defgroup FCG_Check_Parameters_Validity FCG Check Parameters Validity + * @{ + */ +/* Parameter validity check for peripheral in fcg0. */ +#define IS_FCG0_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG0_PERIPH_MASK) == FCG_FCG0_PERIPH_MASK)) + +/* Parameter validity check for peripheral in fcg1. */ +#define IS_FCG1_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG1_PERIPH_MASK) == FCG_FCG1_PERIPH_MASK)) + +/* Parameter validity check for peripheral in fcg2. */ +#define IS_FCG2_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG2_PERIPH_MASK) == FCG_FCG2_PERIPH_MASK)) + +/* Parameter validity check for peripheral in fcg3. */ +#define IS_FCG3_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG3_PERIPH_MASK) == FCG_FCG3_PERIPH_MASK)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup FCG_Global_Functions FCG Global Functions + * @{ + */ + +/** + * @brief Enable or disable the FCG0 peripheral clock. + * @param [in] u32Fcg0Periph The peripheral in FCG0 @ref FCG_FCG0_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG0_PERIPH(u32Fcg0Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_FCG0_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG0, u32Fcg0Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG0, u32Fcg0Periph); + } +} + +/** + * @brief Enable or disable the FCG1 peripheral clock. + * @param [in] u32Fcg1Periph The peripheral in FCG1 @ref FCG_FCG1_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG1_PERIPH(u32Fcg1Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG1, u32Fcg1Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG1, u32Fcg1Periph); + } +} + +/** + * @brief Enable or disable the FCG2 peripheral clock. + * @param [in] u32Fcg2Periph The peripheral in FCG2 @ref FCG_FCG2_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG2_PERIPH(u32Fcg2Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG2, u32Fcg2Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG2, u32Fcg2Periph); + } +} + +/** + * @brief Enable or disable the FCG3 peripheral clock. + * @param [in] u32Fcg3Periph The peripheral in FCG3 @ref FCG_FCG3_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG3_PERIPH(u32Fcg3Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG3, u32Fcg3Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG3, u32Fcg3Periph); + } +} + +#endif /* LL_FCG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcm.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcm.c new file mode 100644 index 0000000000..a3f4410d49 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcm.c @@ -0,0 +1,383 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcm.c + * @brief This file provides firmware functions to manage the Frequency Clock + * Measurement (FCM). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_fcm.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_FCM FCM + * @brief FCM Driver Library + * @{ + */ + +#if (LL_FCM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCM_Local_Macros FCM Local Macros + * @{ + */ + +/* FCM Registers RESET Value */ +#define FCM_REG_RST_VALUE (0x00000000UL) + +/* FCM interrupt mask */ +#define FCM_INT_MASK (FCM_INT_OVF | FCM_INT_END | FCM_INT_ERR) +/* FCM status flag mask */ +#define FCM_FLAG_MASK (FCM_SR_ERRF | FCM_SR_MENDF | FCM_SR_OVF) + +/** + * @defgroup FCM_Check_Parameters_Validity FCM Check Parameters Validity + * @{ + */ + +/* Parameter validity check for FCM target and reference clock source. */ +#define IS_FCM_TARGET_SRC(x) \ +( ((x) == FCM_TARGET_CLK_XTAL) || \ + ((x) == FCM_TARGET_CLK_XTAL32) || \ + ((x) == FCM_TARGET_CLK_HRC) || \ + ((x) == FCM_TARGET_CLK_LRC) || \ + ((x) == FCM_TARGET_CLK_SWDTLRC) || \ + ((x) == FCM_TARGET_CLK_PCLK1) || \ + ((x) == FCM_TARGET_CLK_UPLLP) || \ + ((x) == FCM_TARGET_CLK_MRC) || \ + ((x) == FCM_TARGET_CLK_MPLLP)) + +#define IS_FCM_REF_SRC(x) \ +( ((x) == FCM_REF_CLK_XTAL) || \ + ((x) == FCM_REF_CLK_XTAL32) || \ + ((x) == FCM_REF_CLK_HRC) || \ + ((x) == FCM_REF_CLK_LRC) || \ + ((x) == FCM_REF_CLK_SWDTLRC) || \ + ((x) == FCM_REF_CLK_PCLK1) || \ + ((x) == FCM_REF_CLK_UPLLP) || \ + ((x) == FCM_REF_CLK_MRC) || \ + ((x) == FCM_REF_CLK_MPLLP)) + +/* Parameter validity check for FCM target clock division. */ +#define IS_FCM_TARGET_DIV(x) \ +( ((x) == FCM_TARGET_CLK_DIV1) || \ + ((x) == FCM_TARGET_CLK_DIV4) || \ + ((x) == FCM_TARGET_CLK_DIV8) || \ + ((x) == FCM_TARGET_CLK_DIV32)) + +/* Parameter validity check for FCM external reference input function. */ +#define IS_FCM_EXT_REF_FUNC(x) \ +( ((x) == FCM_EXT_REF_OFF) || \ + ((x) == FCM_EXT_REF_ON)) + +/* Parameter validity check for FCM reference clock edge. */ +#define IS_FCM_REF_EDGE(x) \ +( ((x) == FCM_REF_CLK_RISING) || \ + ((x) == FCM_REF_CLK_FALLING) || \ + ((x) == FCM_REF_CLK_BOTH)) + +/* Parameter validity check for FCM digital filter function. */ +#define IS_FCM_DIG_FILTER(x) \ +( ((x) == FCM_DIG_FILTER_OFF) || \ + ((x) == FCM_DIG_FILTER_DIV1) || \ + ((x) == FCM_DIG_FILTER_DIV4) || \ + ((x) == FCM_DIG_FILTER_DIV16)) + +/* Parameter validity check for FCM reference clock division. */ +#define IS_FCM_REF_DIV(x) \ +( ((x) == FCM_REF_CLK_DIV32) || \ + ((x) == FCM_REF_CLK_DIV128) || \ + ((x) == FCM_REF_CLK_DIV1024) || \ + ((x) == FCM_REF_CLK_DIV8192)) + +/* Parameter validity check for FCM exception type function. */ +#define IS_FCM_EXP_TYPE(x) \ +( ((x) == FCM_EXP_TYPE_INT) || \ + ((x) == FCM_EXP_TYPE_RST)) + +/* Parameter validity check for FCM interrupt. */ +#define IS_FCM_INT(x) (((x) | FCM_INT_MASK) == FCM_INT_MASK) + +/* Parameter validity check for FCM flag state. */ +#define IS_FCM_FLAG(x) \ +( ((x) != 0x00UL) && \ + (((x) | FCM_FLAG_MASK) == FCM_FLAG_MASK)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Functions FCM Global Functions + * @{ + */ + +/** + * @brief Initialize FCM. + * @param [in] pstcFcmInit Pointer to a @ref stc_fcm_init_t structure + * that contains configuration information. + * @retval int32_t: + * - LL_OK: FCM initialize successful + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t FCM_Init(const stc_fcm_init_t *pstcFcmInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcFcmInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_FCM_TARGET_SRC(pstcFcmInit->u32TargetClock)); + DDL_ASSERT(IS_FCM_TARGET_DIV(pstcFcmInit->u32TargetClockDiv)); + DDL_ASSERT(IS_FCM_EXT_REF_FUNC(pstcFcmInit->u32ExtRefClockEnable)); + DDL_ASSERT(IS_FCM_REF_EDGE(pstcFcmInit->u32RefClockEdge)); + DDL_ASSERT(IS_FCM_DIG_FILTER(pstcFcmInit->u32DigitalFilter)); + DDL_ASSERT(IS_FCM_REF_SRC(pstcFcmInit->u32RefClock)); + DDL_ASSERT(IS_FCM_REF_DIV(pstcFcmInit->u32RefClockDiv)); + DDL_ASSERT(IS_FCM_EXP_TYPE(pstcFcmInit->u32ExceptionType)); + + WRITE_REG32(CM_FCM->LVR, pstcFcmInit->u16LowerLimit); + WRITE_REG32(CM_FCM->UVR, pstcFcmInit->u16UpperLimit); + WRITE_REG32(CM_FCM->MCCR, (pstcFcmInit->u32TargetClock | pstcFcmInit->u32TargetClockDiv)); + WRITE_REG32(CM_FCM->RCCR, (pstcFcmInit->u32ExtRefClockEnable | pstcFcmInit->u32RefClockEdge | + pstcFcmInit->u32DigitalFilter | pstcFcmInit->u32RefClock | + pstcFcmInit->u32RefClockDiv)); + MODIFY_REG32(CM_FCM->RIER, FCM_RIER_ERRINTRS, pstcFcmInit->u32ExceptionType); + } + return i32Ret; +} + +/** + * @brief Initialize FCM structure. Fill each pstcFcmInit with default value. + * @param [in] pstcFcmInit Pointer to a @ref stc_fcm_init_t structure + * that contains configuration information. + * @retval int32_t: + * - LL_OK: FCM structure initialize successful + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcFcmInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* RESET FCM init structure parameters values */ + pstcFcmInit->u16LowerLimit = 0U; + pstcFcmInit->u16UpperLimit = 0U; + pstcFcmInit->u32TargetClock = FCM_TARGET_CLK_XTAL; + pstcFcmInit->u32TargetClockDiv = FCM_TARGET_CLK_DIV1; + pstcFcmInit->u32ExtRefClockEnable = FCM_EXT_REF_OFF; + pstcFcmInit->u32RefClockEdge = FCM_REF_CLK_RISING; + pstcFcmInit->u32DigitalFilter = FCM_DIG_FILTER_OFF; + pstcFcmInit->u32RefClock = FCM_REF_CLK_XTAL; + pstcFcmInit->u32RefClockDiv = FCM_REF_CLK_DIV32; + pstcFcmInit->u32ExceptionType = FCM_EXP_TYPE_INT; + } + return i32Ret; +} + +/** + * @brief De-Initialize FCM. + * @param None + * @retval None + */ +void FCM_DeInit(void) +{ + WRITE_REG32(CM_FCM->STR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->CLR, FCM_FLAG_MASK); + WRITE_REG32(CM_FCM->LVR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->UVR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->MCCR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->RCCR, FCM_REG_RST_VALUE); + WRITE_REG32(CM_FCM->RIER, FCM_REG_RST_VALUE); +} + +/** + * @brief Get FCM state, get FCM overflow, complete, error flag. + * @param [in] u32Flag FCM flags.This parameter can be one or any + * combination of the following values: @ref FCM_Flag_Sel + * @arg FCM_FLAG_ERR: FCM error. + * @arg FCM_FLAG_END: FCM measure end. + * @arg FCM_FLAG_OVF: FCM overflow. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t FCM_GetStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_FCM_FLAG(u32Flag)); + + return ((READ_REG32_BIT(CM_FCM->SR, u32Flag) != 0UL) ? SET : RESET); +} + +/** + * @brief Clear FCM state, Clear FCM overflow, complete, error flag. + * @param [in] u32Flag FCM flags.This parameter can be one or any + * combination of the following values: @ref FCM_Flag_Sel + * @arg FCM_FLAG_ERR: FCM error. + * @arg FCM_FLAG_END: FCM measure end. + * @arg FCM_FLAG_OVF: FCM overflow. + * @retval None. + */ +void FCM_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_FCM_FLAG(u32Flag)); + + SET_REG32_BIT(CM_FCM->CLR, u32Flag); +} + +/** + * @brief Get FCM counter value. + * @param None + * @retval FCM counter value. + */ +uint16_t FCM_GetCountValue(void) +{ + return (uint16_t)(READ_REG32(CM_FCM->CNTR) & 0xFFFFU); +} + +/** + * @brief FCM target clock type and division config. + * @param [in] u32ClockSrc Target clock type. @ref FCM_Target_Clock_Src + * @param [in] u32Div Target clock division. @ref FCM_Target_Clock_Div + * @arg FCM_TARGET_CLK_DIV1 + * @arg FCM_TARGET_CLK_DIV4 + * @arg FCM_TARGET_CLK_DIV8 + * @arg FCM_TARGET_CLK_DIV32 + * @retval None. + */ +void FCM_SetTargetClock(uint32_t u32ClockSrc, uint32_t u32Div) +{ + DDL_ASSERT(IS_FCM_TARGET_SRC(u32ClockSrc)); + DDL_ASSERT(IS_FCM_TARGET_DIV(u32Div)); + WRITE_REG32(CM_FCM->MCCR, (u32ClockSrc | u32Div)); +} + +/** + * @brief FCM reference clock type and division config. + * @param [in] u32ClockSrc Reference clock type. @ref FCM_Ref_Clock_Src + * @param [in] u32Div Reference clock division. @ref FCM_Ref_Clock_Div + * @arg FCM_REF_CLK_DIV32 + * @arg FCM_REF_CLK_DIV128 + * @arg FCM_REF_CLK_DIV1024 + * @arg FCM_REF_CLK_DIV8192 + * @retval None. + */ +void FCM_SetRefClock(uint32_t u32ClockSrc, uint32_t u32Div) +{ + DDL_ASSERT(IS_FCM_REF_SRC(u32ClockSrc)); + DDL_ASSERT(IS_FCM_REF_DIV(u32Div)); + MODIFY_REG32(CM_FCM->RCCR, (FCM_RCCR_INEXS | FCM_RCCR_RCKS | FCM_RCCR_RDIVS), (u32ClockSrc | u32Div)); +} + +/** + * @brief Enable or disable the FCM reset + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCM_ResetCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_FCM->RIER_b.ERRE, enNewState); +} + +/** + * @brief Enable or disable the FCM interrupt + * @param [in] u32IntType The FCM interrupt type. This parameter can be + * one or any combination @ref FCM_Int_Type + * @arg FCM_INT_OVF: FCM overflow interrupt + * @arg FCM_INT_END: FCM calculate end interrupt + * @arg FCM_INT_ERR: FCM frequency abnormal interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCM_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCM_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_FCM->RIER, u32IntType); + } else { + CLR_REG32_BIT(CM_FCM->RIER, u32IntType); + } +} + +/** + * @brief FCM function config. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None. + */ +void FCM_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_FCM->STR_b.START, enNewState); +} + +/** + * @} + */ + +#endif /* LL_FCM_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_gpio.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_gpio.c new file mode 100644 index 0000000000..2c0db1dc0b --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_gpio.c @@ -0,0 +1,631 @@ +/** + ******************************************************************************* + * @file hc32_ll_gpio.c + * @brief This file provides firmware functions to manage the General Purpose + * Input/Output(GPIO). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_gpio.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_GPIO GPIO + * @brief GPIO Driver Library + * @{ + */ + +#if (LL_GPIO_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup GPIO_Local_Types GPIO Local Typedefs + * @{ + */ +/** + * @brief GPIO port pin table definition + */ +typedef struct { + uint8_t u8Port; /*!< Set pin state to High or Low, @ref GPIO_PinState_Sel for details */ + uint16_t u16PinMask; /*!< Set pin state to High or Low, @ref GPIO_PinState_Sel for details */ +} stc_gpio_port_pin_tbl_t; +/** + * @} + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup GPIO_Local_Macros GPIO Local Macros + * @{ + */ +/** + * @defgroup GPIO_Registers_Setting_definition GPIO Registers setting definition + * @{ + */ +#define GPIO_PSPCR_RST_VALUE (0x001FU) + +#define GPIO_PCCR_RST_VALUE (0x4000U) + +#define GPIO_PINAER_RST_VALUE (0x0000U) + +#define GPIO_PIN_NUM_MAX (16U) +#define GPIO_PORT_OFFSET (0x40UL) +#define GPIO_PIN_OFFSET (0x04UL) +#define GPIO_REG_OFFSET (0x10UL) +#define GPIO_REG_TYPE uint16_t +#define GPIO_PIDR_BASE ((uint32_t)(&CM_GPIO->PIDRA)) +#define GPIO_PODR_BASE ((uint32_t)(&CM_GPIO->PODRA)) +#define GPIO_POSR_BASE ((uint32_t)(&CM_GPIO->POSRA)) +#define GPIO_PORR_BASE ((uint32_t)(&CM_GPIO->PORRA)) +#define GPIO_POTR_BASE ((uint32_t)(&CM_GPIO->POTRA)) +#define GPIO_POER_BASE ((uint32_t)(&CM_GPIO->POERA)) +#define GPIO_PCR_BASE ((uint32_t)(&CM_GPIO->PCRA0)) +#define GPIO_PFSR_BASE ((uint32_t)(&CM_GPIO->PFSRA0)) + +#define PIDR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PIDR_BASE + GPIO_REG_OFFSET * (x))) +#define PODR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PODR_BASE + GPIO_REG_OFFSET * (x))) +#define POSR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POSR_BASE + GPIO_REG_OFFSET * (x))) +#define PORR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PORR_BASE + GPIO_REG_OFFSET * (x))) +#define POTR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POTR_BASE + GPIO_REG_OFFSET * (x))) +#define POER_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POER_BASE + GPIO_REG_OFFSET * (x))) +#define PCR_REG(x, y) (*(__IO uint16_t *)(GPIO_PCR_BASE + (uint32_t)((x) * GPIO_PORT_OFFSET) + (y) * GPIO_PIN_OFFSET)) +#define PFSR_REG(x, y) (*(__IO uint16_t *)(GPIO_PFSR_BASE + (uint32_t)((x) * GPIO_PORT_OFFSET) + (y) * GPIO_PIN_OFFSET)) +/** + * @} + */ + +/** + * @defgroup GPIO_Check_Parameters_Validity GPIO Check Parameters Validity + * @{ + */ +/*! Parameter validity check for pin state. */ +#define IS_GPIO_PIN_STATE(state) \ +( ((state) == PIN_STAT_RST) || \ + ((state) == PIN_STAT_SET)) + +/*! Parameter validity check for pin direction. */ +#define IS_GPIO_DIR(dir) \ +( ((dir) == PIN_DIR_IN) || \ + ((dir) == PIN_DIR_OUT)) + +/*! Parameter validity check for pin output type. */ +#define IS_GPIO_OUT_TYPE(type) \ +( ((type) == PIN_OUT_TYPE_CMOS) || \ + ((type) == PIN_OUT_TYPE_NMOS)) + +/*! Parameter validity check for pin driver capacity. */ +#define IS_GPIO_PIN_DRV(drv) \ +( ((drv) == PIN_LOW_DRV) || \ + ((drv) == PIN_MID_DRV) || \ + ((drv) == PIN_HIGH_DRV)) + +/*! Parameter validity check for pin attribute. */ +#define IS_GPIO_ATTR(attr) \ +( ((attr) == PIN_ATTR_DIGITAL) || \ + ((attr) == PIN_ATTR_ANALOG)) + +/*! Parameter validity check for pin latch function. */ +#define IS_GPIO_LATCH(latch) \ +( ((latch) == PIN_LATCH_OFF) || \ + ((latch) == PIN_LATCH_ON)) + +/*! Parameter validity check for internal pull-up resistor. */ +#define IS_GPIO_PIN_PU(pu) \ +( ((pu) == PIN_PU_OFF) || \ + ((pu) == PIN_PU_ON)) + +/*! Parameter validity check for pin state invert. */ +#define IS_GPIO_PIN_INVERT(invert) \ +( ((invert) == PIN_INVT_OFF) || \ + ((invert) == PIN_INVT_ON)) + +/*! Parameter validity check for external interrupt function. */ +#define IS_GPIO_EXTINT(extint) \ +( ((extint) == PIN_EXTINT_OFF) || \ + ((extint) == PIN_EXTINT_ON)) + +/*! Parameter validity check for pin number. */ +#define IS_GPIO_PIN(pin) \ +( ((pin) != 0U) && \ + (((pin) & GPIO_PIN_ALL) != 0U)) + +/*! Parameter validity check for port source. */ +#define IS_GPIO_PORT(port) \ +( ((port) == GPIO_PORT_A) || \ + ((port) == GPIO_PORT_B) || \ + ((port) == GPIO_PORT_C) || \ + ((port) == GPIO_PORT_D) || \ + ((port) == GPIO_PORT_E) || \ + ((port) == GPIO_PORT_H)) + +/*! Parameter validity check for pin function. */ +#define IS_GPIO_FUNC(func) \ +( ((func) <= GPIO_FUNC_15) || \ + (((func) >= GPIO_FUNC_32) && ((func) <= GPIO_FUNC_59))) + +/*! Parameter validity check for debug pin definition. */ +#define IS_GPIO_DEBUG_PORT(port) \ +( ((port) != 0U) && \ + (((port) | GPIO_PIN_DEBUG) == GPIO_PIN_DEBUG)) + +/*! Parameter validity check for pin read wait cycle. */ +#define IS_GPIO_READ_WAIT(wait) \ +( ((wait) == GPIO_RD_WAIT0) || \ + ((wait) == GPIO_RD_WAIT1) || \ + ((wait) == GPIO_RD_WAIT2) || \ + ((wait) == GPIO_RD_WAIT3)) + +/*! Parameter validity check for Hrpwmp pin definition. */ + +/* Check GPIO register lock status. */ +#define IS_GPIO_UNLOCK() (GPIO_PWPR_WE == (CM_GPIO->PWPR & GPIO_PWPR_WE)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup GPIO_Local_Variables GPIO Local Variables + * @{ + */ +static const stc_gpio_port_pin_tbl_t m_astcGpioPortPinTbl[] = { + {GPIO_PORT_A, GPIO_PIN_A_ALL}, + {GPIO_PORT_B, GPIO_PIN_B_ALL}, + {GPIO_PORT_C, GPIO_PIN_C_ALL}, + {GPIO_PORT_D, GPIO_PIN_D_ALL}, + {GPIO_PORT_E, GPIO_PIN_E_ALL}, + {GPIO_PORT_H, GPIO_PIN_H_ALL}, + +}; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Functions GPIO Global Functions + * @{ + */ + +/** + * @brief Initialize GPIO. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: GPIO initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit) +{ + uint8_t u8PinPos; + uint16_t u16PCRVal; + uint16_t u16PCRMask; + int32_t i32Ret = LL_OK; + __IO uint16_t *PCRx; + + /* Check if pointer is NULL */ + if (NULL == pstcGpioInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_UNLOCK()); + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_GPIO_PIN_STATE(pstcGpioInit->u16PinState)); + DDL_ASSERT(IS_GPIO_DIR(pstcGpioInit->u16PinDir)); + DDL_ASSERT(IS_GPIO_OUT_TYPE(pstcGpioInit->u16PinOutputType)); + DDL_ASSERT(IS_GPIO_PIN_DRV(pstcGpioInit->u16PinDrv)); + DDL_ASSERT(IS_GPIO_LATCH(pstcGpioInit->u16Latch)); + DDL_ASSERT(IS_GPIO_PIN_PU(pstcGpioInit->u16PullUp)); + DDL_ASSERT(IS_GPIO_PIN_INVERT(pstcGpioInit->u16Invert)); + DDL_ASSERT(IS_GPIO_EXTINT(pstcGpioInit->u16ExtInt)); + DDL_ASSERT(IS_GPIO_ATTR(pstcGpioInit->u16PinAttr)); + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & (1UL << u8PinPos)) != 0U) { + u16PCRVal = pstcGpioInit->u16PinState | pstcGpioInit->u16PinDir | pstcGpioInit->u16PinOutputType | \ + pstcGpioInit->u16PinDrv | pstcGpioInit->u16PullUp | pstcGpioInit->u16Invert | \ + pstcGpioInit->u16ExtInt | pstcGpioInit->u16Latch; + + u16PCRMask = GPIO_PCR_POUT | GPIO_PCR_POUTE | GPIO_PCR_NOD | \ + GPIO_PCR_DRV | GPIO_PCR_PUU | GPIO_PCR_INVE | \ + GPIO_PCR_INTE | GPIO_PCR_LTE ; + u16PCRVal |= pstcGpioInit->u16PinAttr; + u16PCRMask |= GPIO_PCR_DDIS; + + PCRx = &PCR_REG(u8Port, u8PinPos); + MODIFY_REG16(*PCRx, u16PCRMask, u16PCRVal); + } + } + } + return i32Ret; +} + +/** + * @brief De-init GPIO register to default value + * @param None + * @retval None + */ +void GPIO_DeInit(void) +{ + stc_gpio_init_t stcGpioInit; + uint8_t i; + DDL_ASSERT(IS_GPIO_UNLOCK()); + + (void)GPIO_StructInit(&stcGpioInit); + + for (i = 0U; i < ARRAY_SZ(m_astcGpioPortPinTbl); i++) { + (void)GPIO_Init(m_astcGpioPortPinTbl[i].u8Port, m_astcGpioPortPinTbl[i].u16PinMask, &stcGpioInit); + } + /* GPIO global register reset */ + WRITE_REG16(CM_GPIO->PSPCR, GPIO_PSPCR_RST_VALUE); + WRITE_REG16(CM_GPIO->PCCR, GPIO_PCCR_RST_VALUE); + + WRITE_REG16(CM_GPIO->PINAER, GPIO_PINAER_RST_VALUE); +} + +/** + * @brief Initialize GPIO config structure. Fill each pstcGpioInit with default value + * @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: GPIO structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit) +{ + int32_t i32Ret = LL_OK; + /* Check if pointer is NULL */ + if (NULL == pstcGpioInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Reset GPIO init structure parameters values */ + pstcGpioInit->u16PinState = PIN_STAT_RST; + pstcGpioInit->u16PinDir = PIN_DIR_IN; + pstcGpioInit->u16PinDrv = PIN_LOW_DRV; + pstcGpioInit->u16PinAttr = PIN_ATTR_DIGITAL; + + pstcGpioInit->u16Latch = PIN_LATCH_OFF; + pstcGpioInit->u16PullUp = PIN_PU_OFF; + pstcGpioInit->u16Invert = PIN_INVT_OFF; + pstcGpioInit->u16ExtInt = PIN_EXTINT_OFF; + pstcGpioInit->u16PinOutputType = PIN_OUT_TYPE_CMOS; + } + return i32Ret; +} + +/** + * @brief GPIO debug port configure. Set debug pins to GPIO + * @param [in] u8DebugPort: @ref GPIO_DebugPin_Sel for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @arg ENABLE: set to debug port (SWD/JTAG) + * @arg DISABLE: set to GPIO + * @retval None + */ +void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_DEBUG_PORT(u8DebugPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CM_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE)); + } else { + CLR_REG16_BIT(CM_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE)); + } +} + +/** + * @brief Set specified Port Pin function + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] u16Func: GPIO_FUNC_x, x can be the suffix in @ref GPIO_Function_Sel for each product + * @retval None + */ +void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint16_t u16Func) +{ + uint8_t u8PinPos; + __IO uint16_t *PFSRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_GPIO_FUNC(u16Func)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & (uint16_t)(1UL << u8PinPos)) != 0U) { + PFSRx = &PFSR_REG(u8Port, u8PinPos); + WRITE_REG16(*PFSRx, u16Func); + } + } +} + +/** + * @brief GPIO pin sub-function ENABLE. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void GPIO_SubFuncCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState) +{ + uint8_t u8PinPos; + __IO uint16_t *PFSRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & (uint16_t)(1UL << u8PinPos)) != 0U) { + PFSRx = &PFSR_REG(u8Port, u8PinPos); + if (ENABLE == enNewState) { + SET_REG16_BIT(*PFSRx, PIN_SUBFUNC_ENABLE); + } else { + CLR_REG16_BIT(*PFSRx, PIN_SUBFUNC_ENABLE); + } + } + } +} + +/** + * @brief Set the sub-function, it's a global configuration + * @param [in] u8Func: GPIO_FUNC_x, x can be the suffix in @ref GPIO_Function_Sel for each product + * @retval None + */ +void GPIO_SetSubFunc(uint8_t u8Func) +{ + DDL_ASSERT(IS_GPIO_FUNC(u8Func)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + MODIFY_REG16(CM_GPIO->PCCR, GPIO_PCCR_BFSEL, u8Func); +} + +/** + * @brief GPIO output ENABLE. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void GPIO_OutputCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState) +{ + __IO GPIO_REG_TYPE *POERx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + POERx = &POER_REG(u8Port); + if (ENABLE == enNewState) { + SET_REG_BIT(*POERx, (GPIO_REG_TYPE)u16Pin); + } else { + CLR_REG_BIT(*POERx, (GPIO_REG_TYPE)u16Pin); + } +} + +/** + * @brief GPIO read wait cycle configure. + * @param [in] u16ReadWait: @ref GPIO_ReadCycle_Sel for each product + * @retval None + */ +void GPIO_SetReadWaitCycle(uint16_t u16ReadWait) +{ + DDL_ASSERT(IS_GPIO_READ_WAIT(u16ReadWait)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + MODIFY_REG16(CM_GPIO->PCCR, GPIO_PCCR_RDWT, u16ReadWait); +} + +/** + * @brief GPIO input MOS always ON configure. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @arg ENABLE: set input MOS always ON + * @arg DISABLE: set input MOS turns on while read operation + * @retval None + */ +void GPIO_InputMOSCmd(uint8_t u8Port, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CM_GPIO->PINAER, (1UL << u8Port)); + } else { + CLR_REG16_BIT(CM_GPIO->PINAER, (1UL << u8Port)); + } +} + +/** + * @brief Read specified GPIO input data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval Specified GPIO port pin input value + */ +en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + return ((READ_REG(PIDR_REG(u8Port)) & (u16Pin)) != 0U) ? PIN_SET : PIN_RESET; +} + +/** + * @brief Read specified GPIO input data port + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @retval Specified GPIO port input value + */ +uint16_t GPIO_ReadInputPort(uint8_t u8Port) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + + return READ_REG(PIDR_REG(u8Port)); +} + +/** + * @brief Read specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval Specified GPIO port pin output value + */ +en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + return ((READ_REG(PODR_REG(u8Port)) & (u16Pin)) != 0U) ? PIN_SET : PIN_RESET; +} + +/** + * @brief Read specified GPIO output data port + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @retval Specified GPIO port output value + */ +uint16_t GPIO_ReadOutputPort(uint8_t u8Port) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + + return READ_REG(PODR_REG(u8Port)); +} + +/** + * @brief Set specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval None + */ +void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO GPIO_REG_TYPE *POSRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + POSRx = &POSR_REG(u8Port); + SET_REG_BIT(*POSRx, (GPIO_REG_TYPE)u16Pin); +} + +/** + * @brief Reset specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval None + */ +void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO GPIO_REG_TYPE *PORRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + PORRx = &PORR_REG(u8Port); + SET_REG_BIT(*PORRx, (GPIO_REG_TYPE)u16Pin); +} + +/** + * @brief Write specified GPIO data port + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16PortVal: Pin output value + * @retval None + */ +void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal) +{ + __IO GPIO_REG_TYPE *PODRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + + PODRx = &PODR_REG(u8Port); + WRITE_REG(*PODRx, (GPIO_REG_TYPE)u16PortVal); +} +// +/** + * @brief Toggle specified GPIO output data port pin + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval None + */ +void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO GPIO_REG_TYPE *POTRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + POTRx = &POTR_REG(u8Port); + SET_REG_BIT(*POTRx, (GPIO_REG_TYPE)u16Pin); +} + +/** + * @} + */ + +#endif /* LL_GPIO_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_hash.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_hash.c new file mode 100644 index 0000000000..d50cbaaeb8 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_hash.c @@ -0,0 +1,317 @@ +/** + ******************************************************************************* + * @file hc32_ll_hash.c + * @brief This file provides firmware functions to manage the HASH + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_hash.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_HASH HASH + * @brief HASH Driver Library + * @{ + */ + +#if (LL_HASH_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup HASH_Local_Macros HASH Local Macros + * @{ + */ + +/** + * @defgroup HASH_Miscellaneous_Macros HASH Miscellaneous Macros + * @{ + */ +#define HASH_GROUP_SIZE (64U) +#define HASH_GROUP_SIZE_WORD (HASH_GROUP_SIZE / 4U) +#define HASH_LAST_GROUP_SIZE_MAX (56U) +#define HASH_TIMEOUT (6000U) +#define HASH_MSG_DIGEST_SIZE_WORD (8U) + +/** + * @} + */ + +/** + * @defgroup HASH_Action HASH Action + * @{ + */ +#define HASH_ACTION_START (HASH_CR_START) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup HASH_Local_Functions HASH Local Functions + * @{ + */ + +/** + * @brief Writes the input buffer in data register. + * @param [in] pu8Data The buffer for source data + * @retval None + */ +static void HASH_WriteData(const uint8_t *pu8Data) +{ + uint8_t i; + __IO uint32_t *regDR = &CM_HASH->DR15; + const uint32_t *pu32Data = (const uint32_t *)((uint32_t)pu8Data); + + for (i = 0U; i < HASH_GROUP_SIZE_WORD; i++) { + regDR[i] = __REV(pu32Data[i]); + } +} + +/** + * @brief Memory copy. + * @param [in] pu8Dest Pointer to a destination address. + * @param [in] pu8Src Pointer to a source address. + * @param [in] u32Size Data size. + * @retval None + */ +static void HASH_MemCopy(uint8_t *pu8Dest, const uint8_t *pu8Src, uint32_t u32Size) +{ + uint32_t i = 0UL; + while (i < u32Size) { + pu8Dest[i] = pu8Src[i]; + i++; + } +} + +/** + * @brief Memory set. + * @param [in] pu8Mem Pointer to an address. + * @param [in] u8Value Data value. + * @param [in] u32Size Data size. + * @retval None + */ +static void HASH_MemSet(uint8_t *pu8Mem, uint8_t u8Value, uint32_t u32Size) +{ + uint32_t i = 0UL; + while (i < u32Size) { + pu8Mem[i] = u8Value; + i++; + } +} + +/** + * @brief Wait for the HASH to stop + * @param [in] u32Action HASH action. This parameter can be a value of @ref HASH_Action. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: Works timeout + */ +static int32_t HASH_Wait(uint32_t u32Action) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32TimeCount = 0UL; + + /* Wait for the HASH to stop */ + while (READ_REG32_BIT(CM_HASH->CR, u32Action) != 0UL) { + if (u32TimeCount++ > HASH_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief HASH Filling data + * @param [in] pu8Data The source data buffer + * @param [in] u32DataSize Length of the input buffer in bytes + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: Works timeout + */ +static int32_t HASH_DoCalc(const uint8_t *pu8Data, uint32_t u32DataSize) +{ + uint8_t u8FillBuffer[HASH_GROUP_SIZE]; + uint32_t u32BitLenHigh; + uint32_t u32BitLenLow; + uint32_t u32Index = 0U; + uint8_t u8FirstGroup = 1U; + uint8_t u8HashEnd = 0U; + uint8_t u8DataEndMark = 0U; + int32_t i32Ret; + + u32BitLenHigh = (u32DataSize >> 29U) & 0x7U; + u32BitLenLow = (u32DataSize << 3U); + + /* Stop hash calculating. */ + i32Ret = HASH_Wait(HASH_ACTION_START); + + while ((i32Ret == LL_OK) && (u8HashEnd == 0U)) { + if (u32DataSize >= HASH_GROUP_SIZE) { + HASH_WriteData(&pu8Data[u32Index]); + u32DataSize -= HASH_GROUP_SIZE; + u32Index += HASH_GROUP_SIZE; + } else if (u32DataSize >= HASH_LAST_GROUP_SIZE_MAX) { + HASH_MemSet(u8FillBuffer, 0, HASH_GROUP_SIZE); + HASH_MemCopy(u8FillBuffer, &pu8Data[u32Index], u32DataSize); + u8FillBuffer[u32DataSize] = 0x80U; + u8DataEndMark = 1U; + HASH_WriteData(u8FillBuffer); + u32DataSize = 0U; + } else { + u8HashEnd = 1U; + } + + if (u8HashEnd != 0U) { + HASH_MemSet(u8FillBuffer, 0, HASH_GROUP_SIZE); + if (u32DataSize > 0U) { + HASH_MemCopy(u8FillBuffer, &pu8Data[u32Index], u32DataSize); + } + if (u8DataEndMark == 0U) { + u8FillBuffer[u32DataSize] = 0x80U; + } + u8FillBuffer[63U] = (uint8_t)(u32BitLenLow); + u8FillBuffer[62U] = (uint8_t)(u32BitLenLow >> 8U); + u8FillBuffer[61U] = (uint8_t)(u32BitLenLow >> 16U); + u8FillBuffer[60U] = (uint8_t)(u32BitLenLow >> 24U); + u8FillBuffer[59U] = (uint8_t)(u32BitLenHigh); + u8FillBuffer[58U] = (uint8_t)(u32BitLenHigh >> 8U); + u8FillBuffer[57U] = (uint8_t)(u32BitLenHigh >> 16U); + u8FillBuffer[56U] = (uint8_t)(u32BitLenHigh >> 24U); + HASH_WriteData(u8FillBuffer); + } + + /* First group and last group check */ + /* check if first group */ + if (u8FirstGroup != 0U) { + u8FirstGroup = 0U; + /* Set first group. */ + WRITE_REG32(bCM_HASH->CR_b.FST_GRP, 1U); + } else { + /* Set continuous group. */ + WRITE_REG32(bCM_HASH->CR_b.FST_GRP, 0U); + } + + /* Start hash calculating. */ + WRITE_REG32(bCM_HASH->CR_b.START, 1U); + i32Ret = HASH_Wait(HASH_ACTION_START); + } + /* Stop hash calculating. */ + WRITE_REG32(bCM_HASH->CR_b.START, 0U); + + return i32Ret; +} + +/** + * @brief Read message digest. + * @param [out] pu8MsgDigest Buffer for message digest. + * @retval None + */ +static void HASH_ReadMsgDigest(uint8_t *pu8MsgDigest) +{ + uint8_t i; + __IO uint32_t *regHR = &CM_HASH->HR7; + uint32_t *pu32MsgDigest = (uint32_t *)((uint32_t)pu8MsgDigest); + + for (i = 0U; i < HASH_MSG_DIGEST_SIZE_WORD; i++) { + pu32MsgDigest[i] = __REV(regHR[i]); + } +} + +/** + * @} + */ + +/** + * @defgroup HASH_Global_Functions HASH Global Functions + * @{ + */ + +/** + * @brief HASH calculate. + * @param [in] pu8SrcData Pointer to the source data buffer. + * @param [in] u32SrcDataSize Length of the source data buffer in bytes. + * @param [out] pu8MsgDigest Buffer of the digest. The size must be 32 bytes. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: Parameter error. + * - LL_ERR_TIMEOUT: Works timeout. + */ +int32_t HASH_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize, uint8_t *pu8MsgDigest) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pu8SrcData != NULL) && (u32SrcDataSize != 0UL) && (pu8MsgDigest != NULL)) { + /* Set HASH mode */ + i32Ret = HASH_DoCalc(pu8SrcData, u32SrcDataSize); + if (i32Ret == LL_OK) { + /* Get the message digest result */ + HASH_ReadMsgDigest(pu8MsgDigest); + } + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_HASH_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2c.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2c.c new file mode 100644 index 0000000000..6be7a4e798 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2c.c @@ -0,0 +1,1199 @@ +/** + ******************************************************************************* + * @file hc32_ll_i2c.c + * @brief This file provides firmware functions to manage the Inter-Integrated + * Circuit(I2C). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_i2c.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_I2C I2C + * @brief I2C Driver Library + * @{ + */ + +#if (LL_I2C_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup I2C_Local_Macros I2C Local Macros + * @{ + */ + +#define I2C_BAUDRATE_MAX (400000UL) + +#define I2C_SCL_HIGHT_LOW_LVL_SUM_MAX ((float32_t)0x3E) +#define I2C_7BIT_MAX (0x7FUL) +#define I2C_10BIT_MAX (0x3FFUL) + +/** + * @defgroup I2C_Check_Parameters_Validity I2C Check Parameters Validity + * @{ + */ + +#define IS_I2C_UNIT(x) (((x) == CM_I2C1) || ((x) == CM_I2C2) || ((x) == CM_I2C3)) + +#define IS_I2C_DIG_FILTER_CLK(x) ((x) <= I2C_DIG_FILTER_CLK_DIV4) + +#define IS_I2C_7BIT_ADDR(x) ((x) <= I2C_7BIT_MAX) +#define IS_I2C_10BIT_ADDR(x) ((x) <= I2C_10BIT_MAX) + +#define I2C_SRC_CLK (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_PCLK3S) >> CMU_SCFGR_PCLK3S_POS)) + +#define IS_I2C_SPEED(x) \ +( ((x) != 0U) && \ + ((x) <= I2C_BAUDRATE_MAX)) + +#define IS_I2C_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_FLAG_ALL) == I2C_FLAG_ALL)) + +#define IS_I2C_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_FLAG_CLR_ALL) == I2C_FLAG_CLR_ALL)) + +#define IS_I2C_INT_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_INT_ALL) == I2C_INT_ALL)) + +#define IS_I2C_SMBUS_CONFIG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_SMBUS_MATCH_ALL) == I2C_SMBUS_MATCH_ALL)) + +#define IS_I2C_ADDR(mode, addr) \ +( ((I2C_ADDR_7BIT == (mode)) && ((addr) <= 0x7FU)) || \ + ((I2C_ADDR_10BIT == (mode)) && ((addr) <= 0x3FFU)) || \ + (I2C_ADDR_DISABLE == (mode))) + +#define IS_I2C_ADDR_NUM(x) \ +( ((x) == I2C_ADDR0) || \ + ((x) == I2C_ADDR1)) + +#define IS_I2C_CLK_DIV(x) \ +( (x) <= I2C_CLK_DIV128) + +#define IS_I2C_TRANS_DIR(x) \ +( ((x) == I2C_DIR_TX) || \ + ((x) == I2C_DIR_RX)) + +#define IS_I2C_ACK_CONFIG(x) \ +( ((x) == I2C_ACK) || \ + ((x) == I2C_NACK)) + +#define IS_I2C_FLAG_STD(x) \ +( ((x) == RESET) || \ + ((x) == SET)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup I2C_Global_Functions I2C Global Functions + * @{ + */ + +/** + * @brief Try to wait a status of specified flags + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Flag Specify the flags to check, This parameter can be any combination of the member from + * @ref I2C_Flag values: + * @param [in] enStatus Expected status @ref en_flag_status_t + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_WaitStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_TIMEOUT; + uint32_t u32RegStatusBit; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_FLAG(u32Flag)); + DDL_ASSERT(IS_I2C_FLAG_STD(enStatus)); + + for (;;) { + u32RegStatusBit = (READ_REG32_BIT(I2Cx->SR, u32Flag)); + if (((enStatus == SET) && (u32Flag == u32RegStatusBit)) || ((enStatus == RESET) && (0UL == u32RegStatusBit))) { + i32Ret = LL_OK; + } + + if ((LL_OK == i32Ret) || (0UL == u32Timeout)) { + break; + } else { + u32Timeout--; + } + } + return i32Ret; +} + +/** + * @brief I2C generate start condition + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_GenerateStart(CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_START); +} + +/** + * @brief I2C generate restart condition + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_GenerateRestart(CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_RESTART); +} + +/** + * @brief I2C generate stop condition + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_GenerateStop(CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_STOP); +} + +/** + * @brief Set the baudrate for I2C peripheral. + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + * @arg pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + * step1: calculate div = (I2cSrcClk/Baudrate/(68+2*dnfsum+SclTime) + * I2cSrcClk -- I2c source clock + * Baudrate -- baudrate of i2c + * SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + * according to i2c bus hardware parameter. + * dnfsum -- 0 if digital filter off; + * Filter capacity if digital filter on(1 ~ 4) + * step2: chose a division item which is similar and bigger than div from @ref I2C_Clock_Division. + * @arg pstcI2cInit->u32Baudrate : Baudrate configuration + * @arg pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + * time, should be number of T(i2c clock period time) + * @param [out] pf32Error Baudrate error + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_BaudrateConfig(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error) +{ + int32_t i32Ret = LL_OK; + uint32_t I2cSrcClk; + uint32_t I2cDivClk; + uint32_t SclCnt; + uint32_t Baudrate; + uint32_t dnfsum = 0UL; + uint32_t divsum = 2UL; + uint32_t TheoryBaudrate; + float32_t WidthTotal; + float32_t SumTotal; + float32_t WidthHL; + float32_t fErr = 0.0F; + + if ((NULL == pstcI2cInit) || (NULL == pf32Error)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_I2C_CLK_DIV(pstcI2cInit->u32ClockDiv)); + + /* Get configuration for i2c */ + I2cSrcClk = I2C_SRC_CLK; + I2cDivClk = 1UL << pstcI2cInit->u32ClockDiv; + SclCnt = pstcI2cInit->u32SclTime; + Baudrate = pstcI2cInit->u32Baudrate; + + /* Judge digital filter status */ + if (0U != READ_REG32_BIT(I2Cx->FLTR, I2C_FLTR_DNFEN)) { + dnfsum = (READ_REG32_BIT(I2Cx->FLTR, I2C_FLTR_DNF) >> I2C_FLTR_DNF_POS) + 1U; + } + + /* Judge if clock divider on*/ + if (I2C_CLK_DIV1 == pstcI2cInit->u32ClockDiv) { + divsum = 3UL; + } + + if (I2cDivClk != 0UL) { + WidthTotal = (float32_t)I2cSrcClk / (float32_t)Baudrate / (float32_t)I2cDivClk; + SumTotal = (2.0F * (float32_t)divsum) + (2.0F * (float32_t)dnfsum) + (float32_t)SclCnt; + WidthHL = WidthTotal - SumTotal; + + /* Integer for WidthTotal, rounding off */ + if ((WidthTotal - (float32_t)((uint32_t)WidthTotal)) >= 0.5F) { + WidthTotal = (float32_t)((uint32_t)WidthTotal) + 1.0F; + } else { + WidthTotal = (float32_t)((uint32_t)WidthTotal); + } + + if (WidthTotal <= SumTotal) { + /* Err, Should set a smaller division value for pstcI2cInit->u32ClockDiv */ + i32Ret = LL_ERR_INVD_PARAM; + } else { + if (WidthHL > I2C_SCL_HIGHT_LOW_LVL_SUM_MAX) { + /* Err, Should set a bigger division value for pstcI2cInit->u32ClockDiv */ + i32Ret = LL_ERR_INVD_PARAM; + } else { + TheoryBaudrate = I2cSrcClk / (uint32_t)WidthTotal / I2cDivClk; + fErr = ((float32_t)Baudrate - (float32_t)TheoryBaudrate) / (float32_t)TheoryBaudrate; + WRITE_REG32(I2Cx->CCR, \ + (pstcI2cInit->u32ClockDiv << I2C_CCR_FREQ_POS) | \ + (((uint32_t)WidthHL / 2U) << I2C_CCR_SLOWW_POS) | \ + (((uint32_t)WidthHL - (((uint32_t)WidthHL) / 2U)) << I2C_CCR_SHIGHW_POS)); + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + } + + if ((NULL != pf32Error) && (LL_OK == i32Ret)) { + *pf32Error = fErr; + } + + return i32Ret; +} + +/** + * @brief De-initialize I2C unit + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_DeInit(CM_I2C_TypeDef *I2Cx) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + /* RESET peripheral register and internal status*/ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST); +} + +/** + * @brief Initialize I2C peripheral according to the structure + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + * @arg pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + * step1: calculate div = (I2cSrcClk/Baudrate/(68+2*dnfsum+SclTime) + * I2cSrcClk -- I2c source clock + * Baudrate -- baudrate of i2c + * SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + * according to i2c bus hardware parameter. + * dnfsum -- 0 if digital filter off; + * Filter capacity if digital filter on(1 ~ 4) + * step2: chose a division item which is similar and bigger than div + * from @ref I2C_Clock_Division. + * @arg pstcI2cInit->u32Baudrate : Baudrate configuration + * @arg pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + * time, should be number of T(i2c clock period time) + * @param [out] pf32Error Baudrate error + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_Init(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error) +{ + int32_t i32Ret; + + if (NULL == pstcI2cInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_I2C_CLK_DIV(pstcI2cInit->u32ClockDiv)); + + /* Register and internal status reset */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + + /* I2C baudrate config */ + i32Ret = I2C_BaudrateConfig(I2Cx, pstcI2cInit, pf32Error); + + /* Disable global broadcast address function */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_GCEN); + + /* Release software reset */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST); + /* Disable I2C peripheral */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + } + return i32Ret; +} + +/** + * @brief I2C slave address config + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32AddrNum I2C address 0 or address 1 @ref I2C_Address_Num + * @param [in] u32AddrMode Address mode configuration @ref I2C_Addr_Config + * @param [in] u32Addr The slave address + * @retval None + */ +void I2C_SlaveAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr) +{ + __IO uint32_t *const pu32SLRx = (__IO uint32_t *)((uint32_t)&I2Cx->SLR0 + (u32AddrNum * 4UL)); + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_ADDR_NUM(u32AddrNum)); + DDL_ASSERT(IS_I2C_ADDR(u32AddrMode, u32Addr)); + + if (I2C_ADDR_DISABLE == u32AddrMode) { + CLR_REG32_BIT(*pu32SLRx, I2C_SLR0_SLADDR0EN); + } else { + if (I2C_ADDR_10BIT == u32AddrMode) { + WRITE_REG32(*pu32SLRx, u32AddrMode + u32Addr); + } else { + WRITE_REG32(*pu32SLRx, u32AddrMode + (u32Addr << 1U)); + } + } +} + +/** + * @brief I2C function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_PE, (uint32_t)enNewState << I2C_CR1_PE_POS); +} + +/** + * @brief I2C fast ACK config + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_FastAckCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if (ENABLE == enNewState) { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + } else { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + } +} + +/** + * @brief I2C bus wait function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_BusWaitCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR4, I2C_CR4_BUSWAIT); + } else { + CLR_REG32_BIT(I2Cx->CR4, I2C_CR4_BUSWAIT); + } +} + +/** + * @brief I2C SMBUS function configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32SmbusConfig Indicate the SMBUS address match function configuration. @ref I2C_Smbus_Match_Config + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SmbusConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_SMBUS_CONFIG(u32SmbusConfig)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR1, u32SmbusConfig); + } else { + CLR_REG32_BIT(I2Cx->CR1, u32SmbusConfig); + } +} + +/** + * @brief I2C SMBUS function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SmbusCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_SMBUS, (uint32_t)enNewState << I2C_CR1_SMBUS_POS); +} + +/** + * @brief I2C digital filter function configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32FilterClock Chose the digital filter clock, @ref I2C_Digital_Filter_Clock + * @retval None + */ +void I2C_DigitalFilterConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32FilterClock) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_DIG_FILTER_CLK(u32FilterClock)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_DNF, u32FilterClock); +} + +/** + * @brief I2C digital filter command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_DigitalFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_DNFEN, (uint32_t)enNewState << I2C_FLTR_DNFEN_POS); +} + +/** + * @brief I2C analog filter function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_AnalogFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_ANFEN, (uint32_t)enNewState << I2C_FLTR_ANFEN_POS); +} + +/** + * @brief I2C general call command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_GeneralCallCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_GCEN, (uint32_t)enNewState << I2C_CR1_GCEN_POS); +} + +/** + * @brief I2C flags status get + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Flag Specify the flags to check, This parameter can be any combination of the member from + * @ref I2C_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t I2C_GetStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_FLAG(u32Flag)); + + return ((0UL != READ_REG32_BIT(I2Cx->SR, u32Flag)) ? SET : RESET); +} + +/** + * @brief Clear I2C flags + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Flag Specifies the flag to clear, This parameter + * can be any combination of the following values + * @arg I2C_FLAG_START : Start flag clear + * @arg I2C_FLAG_MATCH_ADDR0 : Address 0 detected flag clear + * @arg I2C_FLAG_MATCH_ADDR1 : Address 1 detected flag clear + * @arg I2C_FLAG_TX_CPLT : Transfer end flag clear + * @arg I2C_FLAG_STOP : Stop flag clear + * @arg I2C_FLAG_RX_FULL : Receive buffer full flag clear + * @arg I2C_FLAG_TX_EMPTY : Transfer buffer empty flag clear + * @arg I2C_FLAG_ARBITRATE_FAIL : Arbitration fails flag clear + * @arg I2C_FLAG_NACKF : Nack detected flag clear + * @arg I2C_FLAG_GENERAL_CALL : General call address detected flag clear + * @arg I2C_FLAG_SMBUS_DEFAULT_MATCH: Smbus default address detected flag clear + * @arg I2C_FLAG_SMBUS_HOST_MATCH : Smbus host address detected flag clear + * @arg I2C_FLAG_SMBUS_ALARM_MATCH : Smbus alarm address detected flag clear + * @retval None + */ +void I2C_ClearStatus(CM_I2C_TypeDef *I2Cx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_CLR_FLAG(u32Flag)); + + WRITE_REG32(I2Cx->CLR, u32Flag); +} + +/** + * @brief I2C software reset function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SWResetCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_SWRST, (uint32_t)enNewState << I2C_CR1_SWRST_POS); +} + +/** + * @brief I2C interrupt command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32IntType Specifies the I2C interrupts @ref I2C_Int_Flag + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_IntCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_INT_FLAG(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR2, u32IntType); + } else { + CLR_REG32_BIT(I2Cx->CR2, u32IntType); + } +} + +/** + * @brief I2C send data + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u8Data The data to be send + * @retval None + */ +void I2C_WriteData(CM_I2C_TypeDef *I2Cx, uint8_t u8Data) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + WRITE_REG8(I2Cx->DTR, u8Data); +} + +/** + * @brief I2C read data from register + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval uint8_t The value of the received data + */ +uint8_t I2C_ReadData(const CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + return READ_REG8(I2Cx->DRR); +} + +/** + * @brief I2C ACK status configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32AckConfig I2C ACK configurate. @ref I2C_Ack_Config + * @retval None + */ +void I2C_AckConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AckConfig) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_ACK_CONFIG(u32AckConfig)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_ACK, u32AckConfig); +} + +/** + * @brief I2C SCL high level timeout configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16TimeoutH Clock timeout period for high level + * @retval None + */ +void I2C_SCLHighTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutH) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + MODIFY_REG32(I2Cx->SLTR, I2C_SLTR_TOUTHIGH, (uint32_t)u16TimeoutH << I2C_SLTR_TOUTHIGH_POS); +} + +/** + * @brief I2C SCL low level timeout configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16TimeoutL Clock timeout period for low level + * @retval None + */ +void I2C_SCLLowTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutL) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + MODIFY_REG32(I2Cx->SLTR, I2C_SLTR_TOUTLOW, u16TimeoutL); +} + +/** + * @brief Enable or disable I2C SCL high level timeout function + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SCLHighTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_HTMOUT); + } else { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_HTMOUT); + } +} + +/** + * @brief Enable or disable I2C SCL low level timeout function + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SCLLowTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_LTMOUT); + } else { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_LTMOUT); + } +} + +/** + * @brief Enable or disable I2C SCL timeout function + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SCLTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_TMOUTEN); + } else { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_TMOUTEN); + } +} + +/** + * @brief I2Cx start + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_Start(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_BUSY, RESET, u32Timeout); + + if (LL_OK == i32Ret) { + /* generate start signal */ + I2C_GenerateStart(I2Cx); + /* Judge if start success*/ + i32Ret = I2C_WaitStatus(I2Cx, (I2C_FLAG_BUSY | I2C_FLAG_START), SET, u32Timeout); + } + + return i32Ret; +} + +/** + * @brief I2Cx restart + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_Restart(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + /* Clear start status flag */ + I2C_ClearStatus(I2Cx, I2C_FLAG_START); + /* Send restart condition */ + I2C_GenerateRestart(I2Cx); + /* Judge if start success*/ + i32Ret = I2C_WaitStatus(I2Cx, (I2C_FLAG_BUSY | I2C_FLAG_START), SET, u32Timeout); + + return i32Ret; +} + +/** + * @brief I2Cx send address + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16Addr The address to be sent + * @param [in] u8Dir Transfer direction, @ref I2C_Trans_Dir + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR: NACK received + */ +int32_t I2C_TransAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_TRANS_DIR(u8Dir)); + DDL_ASSERT(IS_I2C_7BIT_ADDR(u16Addr)); + + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* Send I2C address */ + I2C_WriteData(I2Cx, (uint8_t)(u16Addr << 1U) | u8Dir); + + if (I2C_DIR_TX == u8Dir) { + /* If in master transfer process, Need wait transfer end */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + } else { + /* If in master recevie process, wait I2C_FLAG_TRA changed to recevie */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TRA, RESET, u32Timeout); + } + + if (i32Ret == LL_OK) { + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief I2Cx send 10 bit address + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16Addr The address to be sent + * @param [in] u8Dir Transfer direction @ref I2C_Trans_Dir + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR: NACK received + */ +int32_t I2C_Trans10BitAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_TRANS_DIR(u8Dir)); + DDL_ASSERT(IS_I2C_10BIT_ADDR(u16Addr)); + + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* Write 11110 + SLA(bit9:8) + W#(1bit) */ + I2C_WriteData(I2Cx, (uint8_t)((u16Addr >> 7U) & 0x06U) | 0xF0U | I2C_DIR_TX); + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* If receive ACK */ + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == RESET) { + /* Write SLA(bit7:0)*/ + I2C_WriteData(I2Cx, (uint8_t)(u16Addr & 0xFFU)); + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + + if (LL_OK == i32Ret) { + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + i32Ret = LL_ERR; + } + } + } else { + i32Ret = LL_ERR; + } + } + } + + if ((u8Dir == I2C_DIR_RX) && (LL_OK == i32Ret)) { + /* Restart */ + I2C_ClearStatus(I2Cx, I2C_FLAG_START); + I2C_GenerateRestart(I2Cx); + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_START, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* Write 11110 + SLA(bit9:8) + R(1bit) */ + I2C_WriteData(I2Cx, (uint8_t)((u16Addr >> 7U) & 0x06U) | 0xF0U | I2C_DIR_RX); + /* If in master receive process, Need wait TRA flag */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TRA, RESET, u32Timeout); + + if (LL_OK == i32Ret) { + /* If receive NACK */ + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + i32Ret = LL_ERR; + } + } + } + } + + return i32Ret; +} + +/** + * @brief I2Cx send data + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] au8TxData The data array to be sent + * @param [in] u32Size Number of data in array pau8TxData + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_TransData(CM_I2C_TypeDef *I2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32Count = 0UL; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + if (au8TxData != NULL) { + while ((u32Count != u32Size) && (i32Ret == LL_OK)) { + /* Wait tx buffer empty */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout); + + if (i32Ret == LL_OK) { + /* Send one byte data */ + I2C_WriteData(I2Cx, au8TxData[u32Count]); + + /* Wait transfer end*/ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + + /* If receive NACK*/ + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + break; + } + u32Count++; + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + + return i32Ret; +} + +/** + * @brief I2Cx receive data + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [out] au8RxData Array to hold the received data + * @param [in] u32Size Number of data to be received + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_ReceiveData(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + if (au8RxData != NULL) { + uint32_t u32FastAckDis = READ_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + for (i = 0UL; i < u32Size; i++) { + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_RX_FULL, SET, u32Timeout); + + if (0UL == u32FastAckDis) { + if ((u32Size >= 2UL) && (i == (u32Size - 2UL))) { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } else { + if (i != (u32Size - 1UL)) { + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } + + if (i32Ret == LL_OK) { + /* read data from register */ + au8RxData[i] = I2C_ReadData(I2Cx); + } else { + break; + } + } + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + + return i32Ret; +} + +/** + * @brief I2Cx receive data and stop(for master) + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [out] au8RxData Array to hold the received data + * @param [in] u32Size Number of data to be received + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_MasterReceiveDataAndStop(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + if (au8RxData != NULL) { + uint32_t u32FastAckDis = READ_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + + for (i = 0UL; i < u32Size; i++) { + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_RX_FULL, SET, u32Timeout); + + if (0UL == u32FastAckDis) { + if ((u32Size >= 2UL) && (i == (u32Size - 2UL))) { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } else { + if (i != (u32Size - 1UL)) { + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } + + if (i32Ret == LL_OK) { + /* Stop before read last data */ + if (i == (u32Size - 1UL)) { + I2C_ClearStatus(I2Cx, I2C_FLAG_STOP); + I2C_GenerateStop(I2Cx); + } + /* read data from register */ + au8RxData[i] = I2C_ReadData(I2Cx); + + if (i == (u32Size - 1UL)) { + /* Wait stop flag after DRR read */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_STOP, SET, u32Timeout); + } + } else { + break; + } + } + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + + return i32Ret; +} + +/** + * @brief I2Cx stop + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_Stop(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + /* Clear stop flag */ + while ((SET == I2C_GetStatus(I2Cx, I2C_FLAG_STOP)) && (u32Timeout > 0UL)) { + I2C_ClearStatus(I2Cx, I2C_FLAG_STOP); + u32Timeout--; + } + I2C_GenerateStop(I2Cx); + /* Wait stop flag */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_STOP, SET, u32Timeout); + + return i32Ret; +} + +/** + * @brief Initialize structure stc_i2c_init_t variable with default value. + * @param [out] pstcI2cInit Pointer to a stc_i2c_init_t structure variable which will be initialized. + * @ref stc_i2c_init_t. + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_StructInit(stc_i2c_init_t *pstcI2cInit) +{ + int32_t i32Ret = LL_OK; + if (pstcI2cInit == NULL) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcI2cInit->u32Baudrate = 50000UL; + pstcI2cInit->u32SclTime = 0UL; + pstcI2cInit->u32ClockDiv = I2C_CLK_DIV1; + } + + return i32Ret; +} + +/** +* @} +*/ + +#endif /* LL_I2C_ENABLE */ + +/** +* @} +*/ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2s.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2s.c new file mode 100644 index 0000000000..130e43aaf6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2s.c @@ -0,0 +1,1031 @@ +/** + ******************************************************************************* + * @file hc32_ll_i2s.c + * @brief This file provides firmware functions to manage the Inter IC Sound Bus + * (I2S). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_i2s.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_I2S I2S + * @brief Inter IC Sound Bus Driver Library + * @{ + */ + +#if (LL_I2S_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup I2S_Local_Macros I2S Local Macros + * @{ + */ +/* CMU registers define */ +#define I2S_CLK_SRC_PCLK (0x00U << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLP (0x08U << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLQ (0x09U << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLR (0x0AU << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLXP (0x0BU << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLXQ (0x0CU << CMU_I2SCKSEL_I2S1CKSEL_POS) +#define I2S_CLK_SRC_PLLXR (0x0DU << CMU_I2SCKSEL_I2S1CKSEL_POS) + +#define I2S_CMU_PLLCFGR PLLCFGR +#define I2S_CMU_PLLCFGR_PLLSRC CMU_PLLCFGR_PLLSRC + +#define I2S_CMU_PLLXCFGR UPLLCFGR + +#define I2S_CMU_SCFGR SCFGR +#define I2S_CMU_SCFGR_PCLK CMU_SCFGR_PCLK1S +#define I2S_CMU_SCFGR_PCLK_POS CMU_SCFGR_PCLK1S_POS + +#define I2S_CMU_PLLCFGR_PLLM CMU_PLLCFGR_MPLLM +#define I2S_CMU_PLLCFGR_PLLM_POS CMU_PLLCFGR_MPLLM_POS +#define I2S_CMU_PLLCFGR_PLLN CMU_PLLCFGR_MPLLN +#define I2S_CMU_PLLCFGR_PLLN_POS CMU_PLLCFGR_MPLLN_POS +#define I2S_CMU_PLLCFGR_PLLP CMU_PLLCFGR_MPLLP +#define I2S_CMU_PLLCFGR_PLLP_POS CMU_PLLCFGR_MPLLP_POS +#define I2S_CMU_PLLCFGR_PLLQ CMU_PLLCFGR_MPLLQ +#define I2S_CMU_PLLCFGR_PLLQ_POS CMU_PLLCFGR_MPLLQ_POS +#define I2S_CMU_PLLCFGR_PLLR CMU_PLLCFGR_MPLLR +#define I2S_CMU_PLLCFGR_PLLR_POS CMU_PLLCFGR_MPLLR_POS + +#define I2S_CMU_PLLCFGR_PLLXM CMU_UPLLCFGR_UPLLM +#define I2S_CMU_PLLCFGR_PLLXM_POS CMU_UPLLCFGR_UPLLM_POS +#define I2S_CMU_PLLCFGR_PLLXN CMU_UPLLCFGR_UPLLN +#define I2S_CMU_PLLCFGR_PLLXN_POS CMU_UPLLCFGR_UPLLN_POS +#define I2S_CMU_PLLCFGR_PLLXP CMU_UPLLCFGR_UPLLP +#define I2S_CMU_PLLCFGR_PLLXP_POS CMU_UPLLCFGR_UPLLP_POS +#define I2S_CMU_PLLCFGR_PLLXQ CMU_UPLLCFGR_UPLLQ +#define I2S_CMU_PLLCFGR_PLLXQ_POS CMU_UPLLCFGR_UPLLQ_POS +#define I2S_CMU_PLLCFGR_PLLXR CMU_UPLLCFGR_UPLLR +#define I2S_CMU_PLLCFGR_PLLXR_POS CMU_UPLLCFGR_UPLLR_POS + +/* I2S CTRL register Mask */ +#define I2S_CTRL_CLR_MASK (I2S_CTRL_WMS | I2S_CTRL_ODD | I2S_CTRL_MCKOE | \ + I2S_CTRL_TXBIRQWL | I2S_CTRL_RXBIRQWL | I2S_CTRL_I2SPLLSEL | \ + I2S_CTRL_SDOE | I2S_CTRL_LRCKOE | I2S_CTRL_CKOE | \ + I2S_CTRL_DUPLEX | I2S_CTRL_CLKSEL) + +/** + * @defgroup I2S_Check_Parameters_Validity I2S Check Parameters Validity + * @{ + */ +#define IS_I2S_UNIT(x) \ +( ((x) == CM_I2S1) || \ + ((x) == CM_I2S2) || \ + ((x) == CM_I2S3) || \ + ((x) == CM_I2S4)) + +#define IS_I2S_CLK_SRC(x) \ +( ((x) == I2S_CLK_SRC_PLL) || \ + ((x) == I2S_CLK_SRC_EXT)) + +#define IS_I2S_MD(x) \ +( ((x) == I2S_MD_MASTER) || \ + ((x) == I2S_MD_SLAVE)) + +#define IS_I2S_PROTOCOL(x) \ +( ((x) == I2S_PROTOCOL_PHILLIPS) || \ + ((x) == I2S_PROTOCOL_MSB) || \ + ((x) == I2S_PROTOCOL_LSB) || \ + ((x) == I2S_PROTOCOL_PCM_SHORT) || \ + ((x) == I2S_PROTOCOL_PCM_LONG)) + +#define IS_I2S_TRANS_MD(x) \ +( ((x) == I2S_TRANS_MD_HALF_DUPLEX_RX) || \ + ((x) == I2S_TRANS_MD_HALF_DUPLEX_TX) || \ + ((x) == I2S_TRANS_MD_FULL_DUPLEX)) + +#define IS_I2S_AUDIO_FREQ(x) \ +( ((x) == I2S_AUDIO_FREQ_DEFAULT) || \ + (((x) >= I2S_AUDIO_FREQ_8K) && ((x) <= I2S_AUDIO_FREQ_192K))) + +#define IS_I2S_CH_LEN(x) \ +( ((x) == I2S_CH_LEN_16BIT) || \ + ((x) == I2S_CH_LEN_32BIT)) + +#define IS_I2S_DATA_LEN(x) \ +( ((x) == I2S_DATA_LEN_16BIT) || \ + ((x) == I2S_DATA_LEN_24BIT) || \ + ((x) == I2S_DATA_LEN_32BIT)) + +#define IS_I2S_MCK_OUTPUT(x) \ +( ((x) == I2S_MCK_OUTPUT_DISABLE) || \ + ((x) == I2S_MCK_OUTPUT_ENABLE)) + +#define IS_I2S_TRANS_LVL(x) \ +( ((x) == I2S_TRANS_LVL0) || \ + ((x) == I2S_TRANS_LVL1) || \ + ((x) == I2S_TRANS_LVL2)) + +#define IS_I2S_RECEIVE_LVL(x) \ +( ((x) == I2S_RECEIVE_LVL0) || \ + ((x) == I2S_RECEIVE_LVL1) || \ + ((x) == I2S_RECEIVE_LVL2)) + +#define IS_I2S_FUNC(x) \ +( ((x) != 0U) && \ + (((x) | I2S_FUNC_ALL) == I2S_FUNC_ALL)) + +#define IS_I2S_RST_TYPE(x) \ +( ((x) != 0U) && \ + (((x) | I2S_RST_TYPE_ALL) == I2S_RST_TYPE_ALL)) + +#define IS_I2S_INT(x) \ +( ((x) != 0U) && \ + (((x) | I2S_INT_ALL) == I2S_INT_ALL)) + +#define IS_I2S_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2S_FLAG_ALL) == I2S_FLAG_ALL)) + +#define IS_I2S_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2S_FLAG_CLR_ALL) == I2S_FLAG_CLR_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup I2S_Global_Functions I2S Global Functions + * @{ + */ + +/** + * @brief Get I2S clock frequency. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @retval uint32_t The I2S clock frequency + */ +static uint32_t I2S_GetClockFreq(const CM_I2S_TypeDef *I2Sx) +{ + uint32_t u32ClockShift; + uint16_t u16ClockSrc; + uint32_t u32ClockFreq; + uint32_t u32PllP; + uint32_t u32PllQ; + uint32_t u32PllR; + uint32_t u32PllN; + uint32_t u32PllM; + uint32_t u32PllIn; + uint32_t u32Temp; + + /* Get the offset of the I2S clock source in CMU_I2SCKSEL */ + if (CM_I2S1 == I2Sx) { + u32ClockShift = CMU_I2SCKSEL_I2S1CKSEL_POS; + } else if (CM_I2S2 == I2Sx) { + u32ClockShift = CMU_I2SCKSEL_I2S2CKSEL_POS; + } else if (CM_I2S3 == I2Sx) { + u32ClockShift = CMU_I2SCKSEL_I2S3CKSEL_POS; + } else if (CM_I2S4 == I2Sx) { + u32ClockShift = CMU_I2SCKSEL_I2S4CKSEL_POS; + } else { + u32ClockShift = 0UL; + } + + u16ClockSrc = (READ_REG16(CM_CMU->I2SCKSEL) >> u32ClockShift) & CMU_I2SCKSEL_I2S1CKSEL; + if (0UL != READ_REG32_BIT(CM_CMU->I2S_CMU_PLLCFGR, I2S_CMU_PLLCFGR_PLLSRC)) { + u32PllIn = HRC_VALUE; + } else { + u32PllIn = XTAL_VALUE; + } + /* Calculate the clock frequency */ + switch (u16ClockSrc) { + case I2S_CLK_SRC_PCLK: + u32ClockFreq = SystemCoreClock >> ((READ_REG32_BIT(CM_CMU->I2S_CMU_SCFGR, + I2S_CMU_SCFGR_PCLK) >> I2S_CMU_SCFGR_PCLK_POS)); + break; + case I2S_CLK_SRC_PLLP: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLM) >> I2S_CMU_PLLCFGR_PLLM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLN) >> I2S_CMU_PLLCFGR_PLLN_POS; + u32PllP = (u32Temp & I2S_CMU_PLLCFGR_PLLP) >> I2S_CMU_PLLCFGR_PLLP_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllP + 1UL); + break; + case I2S_CLK_SRC_PLLQ: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLM) >> I2S_CMU_PLLCFGR_PLLM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLN) >> I2S_CMU_PLLCFGR_PLLN_POS; + u32PllQ = (u32Temp & I2S_CMU_PLLCFGR_PLLQ) >> I2S_CMU_PLLCFGR_PLLQ_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllQ + 1UL); + break; + case I2S_CLK_SRC_PLLR: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLM) >> I2S_CMU_PLLCFGR_PLLM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLN) >> I2S_CMU_PLLCFGR_PLLN_POS; + u32PllR = (u32Temp & I2S_CMU_PLLCFGR_PLLR) >> I2S_CMU_PLLCFGR_PLLR_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllR + 1UL); + break; + case I2S_CLK_SRC_PLLXP: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLXCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLXM) >> I2S_CMU_PLLCFGR_PLLXM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLXN) >> I2S_CMU_PLLCFGR_PLLXN_POS; + u32PllP = (u32Temp & I2S_CMU_PLLCFGR_PLLXP) >> I2S_CMU_PLLCFGR_PLLXP_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllP + 1UL); + break; + case I2S_CLK_SRC_PLLXQ: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLXCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLXM) >> I2S_CMU_PLLCFGR_PLLXM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLXN) >> I2S_CMU_PLLCFGR_PLLXN_POS; + u32PllQ = (u32Temp & I2S_CMU_PLLCFGR_PLLXQ) >> I2S_CMU_PLLCFGR_PLLXQ_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllQ + 1UL); + break; + case I2S_CLK_SRC_PLLXR: + u32Temp = READ_REG32(CM_CMU->I2S_CMU_PLLXCFGR); + u32PllM = (u32Temp & I2S_CMU_PLLCFGR_PLLXM) >> I2S_CMU_PLLCFGR_PLLXM_POS; + u32PllN = (u32Temp & I2S_CMU_PLLCFGR_PLLXN) >> I2S_CMU_PLLCFGR_PLLXN_POS; + u32PllR = (u32Temp & I2S_CMU_PLLCFGR_PLLXR) >> I2S_CMU_PLLCFGR_PLLXR_POS; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllR + 1UL); + break; + default: + u32ClockFreq = 0UL; + break; + } + + return u32ClockFreq; +} + +/** + * @brief Wait for the flag status of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Flag I2S flag type + * This parameter can be one of the following values: + * @arg I2S_FLAG_TX_ALARM: Transfer buffer alarm flag + * @arg I2S_FLAG_RX_ALARM: Receive buffer alarm flag + * @arg I2S_FLAG_TX_EMPTY: Transfer buffer empty flag + * @arg I2S_FLAG_TX_FULL: Transfer buffer full flag + * @arg I2S_FLAG_RX_EMPTY: Receive buffer empty flag + * @arg I2S_FLAG_RX_FULL: Receive buffer full flag + * @arg I2S_FLAG_TX_ERR: Transfer overflow or underflow flag + * @arg I2S_FLAG_RX_ERR: Receive overflow flag + * @param [in] enStatus The flag status + * This parameter can be one of the following values: + * @arg SET: Wait for the flag to set + * @arg RESET: Wait for the flag to reset + * @param [in] u32Timeout Wait the flag timeout(ms) + * @retval int32_t: + * - LL_OK: Wait status success + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t I2S_WaitStatus(const CM_I2S_TypeDef *I2Sx, uint32_t u32Flag, + en_flag_status_t enStatus, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32Count; + + /* Waiting for the flag status to change to the enStatus */ + u32Count = u32Timeout * (HCLK_VALUE / 20000UL); + while (enStatus != I2S_GetStatus(I2Sx, u32Flag)) { + if (u32Count == 0UL) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @brief De-Initialize I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @retval None + */ +void I2S_DeInit(CM_I2S_TypeDef *I2Sx) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + /* Reset all registers of I2S */ + WRITE_REG32(I2Sx->CTRL, 0x00004400UL); + WRITE_REG32(I2Sx->ER, 0x00000003UL); + WRITE_REG32(I2Sx->CFGR, 0x00000000UL); + WRITE_REG32(I2Sx->PR, 0x00000002UL); + SET_REG32_BIT(I2Sx->CTRL, I2S_RST_TYPE_ALL); + CLR_REG32_BIT(I2Sx->CTRL, I2S_RST_TYPE_ALL); +} + +/** + * @brief Initialize I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] pstcI2sInit Pointer to a @ref stc_i2s_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR: Set frequency failed + */ +int32_t I2S_Init(CM_I2S_TypeDef *I2Sx, const stc_i2s_init_t *pstcI2sInit) +{ + int32_t i32Ret = LL_OK; + uint32_t u32I2sClk; + uint32_t u32Temp; + uint32_t u32I2sDiv = 2UL; + uint32_t u32I2sOdd = 0UL; + uint32_t u32ChWidth; + + if (NULL == pstcI2sInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_CLK_SRC(pstcI2sInit->u32ClockSrc)); + DDL_ASSERT(IS_I2S_MD(pstcI2sInit->u32Mode)); + DDL_ASSERT(IS_I2S_PROTOCOL(pstcI2sInit->u32Protocol)); + DDL_ASSERT(IS_I2S_TRANS_MD(pstcI2sInit->u32TransMode)); + DDL_ASSERT(IS_I2S_AUDIO_FREQ(pstcI2sInit->u32AudioFreq)); + DDL_ASSERT(IS_I2S_CH_LEN(pstcI2sInit->u32ChWidth)); + DDL_ASSERT(IS_I2S_DATA_LEN(pstcI2sInit->u32DataWidth)); + DDL_ASSERT(IS_I2S_MCK_OUTPUT(pstcI2sInit->u32MCKOutput)); + DDL_ASSERT(IS_I2S_TRANS_LVL(pstcI2sInit->u32TransFIFOLevel)); + DDL_ASSERT(IS_I2S_RECEIVE_LVL(pstcI2sInit->u32ReceiveFIFOLevel)); + + if (I2S_AUDIO_FREQ_DEFAULT != pstcI2sInit->u32AudioFreq) { + /* Get I2S source Clock frequency */ + if (I2S_CLK_SRC_EXT == pstcI2sInit->u32ClockSrc) { + /* If the external clock frequency is different from the default value, + you need to redefine the macro value (I2S_EXT_CLK_FREQ). */ + u32I2sClk = I2S_EXT_CLK_FREQ; + } else { + u32I2sClk = I2S_GetClockFreq(I2Sx); + } + /* The actual frequency division value is calculated according to the output state of MCK */ + if (I2S_CH_LEN_16BIT != pstcI2sInit->u32ChWidth) { + u32ChWidth = 32UL; + } else { + u32ChWidth = 16UL; + } + + if (I2S_MCK_OUTPUT_ENABLE == pstcI2sInit->u32MCKOutput) { + if (I2S_CH_LEN_16BIT != pstcI2sInit->u32ChWidth) { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U * 4U)) * 10U) / pstcI2sInit->u32AudioFreq) + 5U; + } else { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U * 8U)) * 10U) / pstcI2sInit->u32AudioFreq) + 5U; + } + } else { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U)) * 10U) / pstcI2sInit->u32AudioFreq) + 5U; + } + u32Temp = u32Temp / 10U; + u32I2sOdd = u32Temp & 0x01U; + u32I2sDiv = (u32Temp - u32I2sOdd) / 2U; + } + + if ((u32I2sDiv < 2U) || (u32I2sDiv > 0xFFU)) { + /* Set the default values */ + u32I2sOdd = 0U; + u32I2sDiv = 2U; + i32Ret = LL_ERR; + } + u32Temp = pstcI2sInit->u32ClockSrc | pstcI2sInit->u32Mode | + pstcI2sInit->u32Protocol | pstcI2sInit->u32TransMode | + pstcI2sInit->u32ChWidth | pstcI2sInit->u32DataWidth | + pstcI2sInit->u32MCKOutput | pstcI2sInit->u32TransFIFOLevel | + pstcI2sInit->u32ReceiveFIFOLevel | (u32I2sOdd << I2S_CTRL_ODD_POS); + if (I2S_MD_MASTER == pstcI2sInit->u32Mode) { + u32Temp |= (I2S_CTRL_CKOE | I2S_CTRL_LRCKOE); + } + /* Set I2S_CFGR register */ + WRITE_REG32(I2Sx->CFGR, (pstcI2sInit->u32Protocol | pstcI2sInit->u32ChWidth | pstcI2sInit->u32DataWidth)); + /* set I2S_PR register */ + WRITE_REG32(I2Sx->PR, u32I2sDiv); + /* Set I2S_CTRL register */ + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_CLR_MASK, u32Temp); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_i2s_init_t member with default value. + * @param [out] pstcI2sInit Pointer to a @ref stc_i2s_init_t structure + * @retval int32_t: + * - LL_OK: stc_i2s_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t I2S_StructInit(stc_i2s_init_t *pstcI2sInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcI2sInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcI2sInit->u32ClockSrc = I2S_CLK_SRC_PLL; + pstcI2sInit->u32Mode = I2S_MD_MASTER; + pstcI2sInit->u32Protocol = I2S_PROTOCOL_PHILLIPS; + pstcI2sInit->u32TransMode = I2S_TRANS_MD_HALF_DUPLEX_RX; + pstcI2sInit->u32AudioFreq = I2S_AUDIO_FREQ_DEFAULT; + pstcI2sInit->u32ChWidth = I2S_CH_LEN_16BIT; + pstcI2sInit->u32DataWidth = I2S_DATA_LEN_16BIT; + pstcI2sInit->u32MCKOutput = I2S_MCK_OUTPUT_DISABLE; + pstcI2sInit->u32TransFIFOLevel = I2S_TRANS_LVL2; + pstcI2sInit->u32ReceiveFIFOLevel = I2S_RECEIVE_LVL2; + } + + return i32Ret; +} + +/** + * @brief Software reset of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Type Software reset type + * This parameter can be one or any combination of the following values: + * @arg @ref I2S_Reset_Type + * @retval None + */ +void I2S_SWReset(CM_I2S_TypeDef *I2Sx, uint32_t u32Type) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_RST_TYPE(u32Type)); + + SET_REG32_BIT(I2Sx->CTRL, u32Type); + CLR_REG32_BIT(I2Sx->CTRL, u32Type); +} + +/** + * @brief Set the transfer mode for the I2S communication. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Mode Transfer mode + * This parameter can be one of the following values: + * @arg I2S_TRANS_MD_HALF_DUPLEX_RX: Receive only and half duplex mode + * @arg I2S_TRANS_MD_HALF_DUPLEX_TX: Send only and half duplex mode + * @arg I2S_TRANS_MD_FULL_DUPLEX: Full duplex mode + * @retval None + */ +void I2S_SetTransMode(CM_I2S_TypeDef *I2Sx, uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_TRANS_MD(u32Mode)); + + MODIFY_REG32(I2Sx->CTRL, (I2S_CTRL_DUPLEX | I2S_CTRL_SDOE), u32Mode); +} + +/** + * @brief Set the transfer FIFO level of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Level Transfer FIFO level + * This parameter can be one of the following values: + * @arg @ref I2S_Trans_Level + * @retval None + */ +void I2S_SetTransFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_TRANS_LVL(u32Level)); + + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_TXBIRQWL, u32Level); +} + +/** + * @brief Set the receive FIFO level of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Level Receive FIFO level + * This parameter can be one of the following values: + * @arg @ref I2S_Receive_Level + * @retval None + */ +void I2S_SetReceiveFIFOLevel(CM_I2S_TypeDef *I2Sx, uint32_t u32Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_RECEIVE_LVL(u32Level)); + + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_RXBIRQWL, u32Level); +} + +/** + * @brief Set the communication protocol of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Protocol Communication protocol + * This parameter can be one of the following values: + * @arg I2S_PROTOCOL_PHILLIPS: Phillips protocol + * @arg I2S_PROTOCOL_MSB: MSB justified protocol + * @arg I2S_PROTOCOL_LSB: LSB justified protocol + * @arg I2S_PROTOCOL_PCM_SHORT: PCM short-frame protocol + * @arg I2S_PROTOCOL_PCM_LONG: PCM long-frame protocol + * @retval None + */ +void I2S_SetProtocol(CM_I2S_TypeDef *I2Sx, uint32_t u32Protocol) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_PROTOCOL(u32Protocol)); + + MODIFY_REG32(I2Sx->CFGR, (I2S_CFGR_I2SSTD | I2S_CFGR_PCMSYNC), u32Protocol); +} + +/** + * @brief Set the audio frequency for the I2S communication. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Freq Audio frequency + * This parameter can be 'I2S_AUDIO_FREQ_DEFAULT' or between + * 'I2S_AUDIO_FREQ_8K' and 'I2S_AUDIO_FREQ_192K': + * @arg I2S_AUDIO_FREQ_192K: FS = 192000Hz + * @arg I2S_AUDIO_FREQ_8K: FS = 8000Hz + * @arg I2S_AUDIO_FREQ_DEFAULT + * @retval int32_t: + * - LL_OK: Set success + * - LL_ERR: Set frequency failed + */ +int32_t I2S_SetAudioFreq(CM_I2S_TypeDef *I2Sx, uint32_t u32Freq) +{ + int32_t i32Ret = LL_OK; + uint32_t u32I2sClk; + uint32_t u32Temp; + uint32_t u32I2sDiv = 2UL; + uint32_t u32I2sOdd = 0UL; + uint32_t u32ChWidth; + + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_AUDIO_FREQ(u32Freq)); + + if (I2S_AUDIO_FREQ_DEFAULT != u32Freq) { + /* Get I2S source Clock frequency */ + if (I2S_CLK_SRC_EXT == READ_REG32_BIT(I2Sx->CTRL, I2S_CTRL_CLKSEL)) { + /* If the external clock frequency is different from the default value, + you need to redefine the macro value (I2S_EXT_CLK_FREQ). */ + u32I2sClk = I2S_EXT_CLK_FREQ; + } else { + u32I2sClk = I2S_GetClockFreq(I2Sx); + } + /* The actual frequency division value is calculated according to the output state of MCK */ + if (I2S_CH_LEN_16BIT != READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_CHLEN)) { + u32ChWidth = 32UL; + } else { + u32ChWidth = 16UL; + } + + if (I2S_MCK_OUTPUT_ENABLE == READ_REG32_BIT(I2Sx->CTRL, I2S_CTRL_MCKOE)) { + if (I2S_CH_LEN_16BIT != READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_CHLEN)) { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U * 4U)) * 10U) / u32Freq) + 5U; + } else { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U * 8U)) * 10U) / u32Freq) + 5U; + } + } else { + u32Temp = (((u32I2sClk / (u32ChWidth * 2U)) * 10U) / u32Freq) + 5U; + } + u32Temp = u32Temp / 10U; + u32I2sOdd = u32Temp & 0x01U; + u32I2sDiv = (u32Temp - u32I2sOdd) / 2U; + } + + if ((u32I2sDiv < 2U) || (u32I2sDiv > 0xFFU)) { + i32Ret = LL_ERR; + } else { + /* Set clock division */ + WRITE_REG32(I2Sx->PR, u32I2sDiv); + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_ODD, (u32I2sOdd << I2S_CTRL_ODD_POS)); + } + + return i32Ret; +} + +/** + * @brief Enable or disable MCK clock output. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2S_MCKOutputCmd(CM_I2S_TypeDef *I2Sx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(I2Sx->CTRL, I2S_CTRL_MCKOE); + } else { + CLR_REG32_BIT(I2Sx->CTRL, I2S_CTRL_MCKOE); + } +} + +/** + * @brief Enable or disable the function of I2S. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Func I2S function + * This parameter can be one or any combination of the following values: + * @arg I2S_FUNC_TX: Transfer function + * @arg I2S_FUNC_RX: Receive function + * @arg I2S_FUNC_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2S_FuncCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32Func, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_FUNC(u32Func)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(I2Sx->CTRL, u32Func); + } else { + CLR_REG32_BIT(I2Sx->CTRL, u32Func); + } +} + +/** + * @brief I2S send data. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Data Send data + * @retval None + */ +void I2S_WriteData(CM_I2S_TypeDef *I2Sx, uint32_t u32Data) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + WRITE_REG32(I2Sx->TXBUF, u32Data); +} + +/** + * @brief I2S receive data. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @retval uint32_t Receive data + */ +uint32_t I2S_ReadData(const CM_I2S_TypeDef *I2Sx) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + return READ_REG32(I2Sx->RXBUF); +} + +/** + * @brief I2S transmit data in polling mode. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] pvTxBuf The pointer to data transmitted buffer + * @param [in] u32Len Data length + * @param [in] u32Timeout Transfer timeout(ms) + * @retval int32_t: + * - LL_OK: Transmit data success + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR_TIMEOUT: Transmission timeout + */ +int32_t I2S_Trans(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + uint32_t u32DataWidth; + + if ((NULL == pvTxBuf) || (0UL == u32Len)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + u32DataWidth = READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_DATLEN); + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + DDL_ASSERT(IS_ADDR_ALIGN_HALFWORD(&((const uint16_t *)pvTxBuf)[0])); + } else { + DDL_ASSERT(IS_ADDR_ALIGN_WORD(&((const uint32_t *)pvTxBuf)[0])); + } + + for (i = 0UL; i < u32Len; i++) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_TX_FULL, RESET, u32Timeout); + if (LL_OK != i32Ret) { + break; + } + + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + WRITE_REG32(I2Sx->TXBUF, ((const uint16_t *)pvTxBuf)[i]); + } else { + WRITE_REG32(I2Sx->TXBUF, ((const uint32_t *)pvTxBuf)[i]); + } + } + } + + return i32Ret; +} + +/** + * @brief I2S receive data in polling mode. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] pvRxBuf The pointer to data received buffer + * @param [in] u32Len Data length + * @param [in] u32Timeout Transfer timeout(ms) + * @retval int32_t: + * - LL_OK: Receive data success + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR_TIMEOUT: Transmission timeout + */ +int32_t I2S_Receive(const CM_I2S_TypeDef *I2Sx, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + uint32_t u32DataWidth; + uint32_t u32Temp; + + if ((NULL == pvRxBuf) || (0UL == u32Len)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + u32DataWidth = READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_DATLEN); + if (((I2S_DATA_LEN_16BIT == u32DataWidth) && IS_ADDR_ALIGN_HALFWORD(&((const uint16_t *)pvRxBuf)[0])) || + (IS_ADDR_ALIGN_WORD(&((const uint32_t *)pvRxBuf)[0]))) { + for (i = 0UL; i < u32Len; i++) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_RX_EMPTY, RESET, u32Timeout); + if (LL_OK != i32Ret) { + break; + } + + u32Temp = READ_REG32(I2Sx->RXBUF); + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + ((uint16_t *)pvRxBuf)[i] = (uint16_t)(u32Temp & 0xFFFFUL); + } else if (I2S_DATA_LEN_24BIT == u32DataWidth) { + ((uint32_t *)pvRxBuf)[i] = u32Temp & 0xFFFFFFUL; + } else { + ((uint32_t *)pvRxBuf)[i] = u32Temp; + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + } + + return i32Ret; +} + +/** + * @brief I2S transmit and receive data in polling mode. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] pvTxBuf The pointer to data transmitted buffer + * @param [in] pvRxBuf The pointer to data received buffer + * @param [in] u32Len Data length + * @param [in] u32Timeout Transfer timeout(ms) + * @retval int32_t: + * - LL_OK: Receive data success + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR_TIMEOUT: Transmission timeout + */ +int32_t I2S_TransReceive(CM_I2S_TypeDef *I2Sx, const void *pvTxBuf, + void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + int32_t i32Ret; + uint32_t u32TxCnt = 0U; + uint32_t u32RxCnt = 0U; + uint32_t u32DataWidth; + uint32_t u32Temp; + uint8_t u8BreakFlag = 0U; + + if ((NULL == pvTxBuf) || (NULL == pvRxBuf) || (0UL == u32Len)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + u32DataWidth = READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_DATLEN); + if (((I2S_DATA_LEN_16BIT == u32DataWidth) && IS_ADDR_ALIGN_HALFWORD(&((const uint16_t *)pvTxBuf)[0]) && IS_ADDR_ALIGN_HALFWORD(&((const uint16_t *)pvRxBuf)[0])) || + (IS_ADDR_ALIGN_WORD(&((const uint32_t *)pvTxBuf)[0]) && IS_ADDR_ALIGN_WORD(&((const uint32_t *)pvRxBuf)[0]))) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_TX_FULL, RESET, u32Timeout); + if (LL_OK == i32Ret) { + /* Preload data */ + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + WRITE_REG32(I2Sx->TXBUF, ((const uint16_t *)pvTxBuf)[u32TxCnt]); + } else { + WRITE_REG32(I2Sx->TXBUF, ((const uint32_t *)pvTxBuf)[u32TxCnt]); + } + u32TxCnt++; + + for (;;) { + /* Transmit data */ + if (u32TxCnt < u32Len) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_TX_FULL, RESET, u32Timeout); + if (LL_OK != i32Ret) { + u8BreakFlag = 1U; + } else { + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + WRITE_REG32(I2Sx->TXBUF, ((const uint16_t *)pvTxBuf)[u32TxCnt]); + } else { + WRITE_REG32(I2Sx->TXBUF, ((const uint32_t *)pvTxBuf)[u32TxCnt]); + } + u32TxCnt++; + } + } + /* Receive data */ + if ((1U != u8BreakFlag) && (u32RxCnt < u32Len)) { + i32Ret = I2S_WaitStatus(I2Sx, I2S_FLAG_RX_EMPTY, RESET, u32Timeout); + if (LL_OK != i32Ret) { + u8BreakFlag = 1U; + } else { + u32Temp = READ_REG32(I2Sx->RXBUF); + if (I2S_DATA_LEN_16BIT == u32DataWidth) { + ((uint16_t *)pvRxBuf)[u32RxCnt] = (uint16_t)(u32Temp & 0xFFFFUL); + } else if (I2S_DATA_LEN_24BIT == u32DataWidth) { + ((uint32_t *)pvRxBuf)[u32RxCnt] = u32Temp & 0xFFFFFFUL; + } else { + ((uint32_t *)pvRxBuf)[u32RxCnt] = u32Temp; + } + u32RxCnt++; + } + } + + /* Complete the transmission */ + if ((1U == u8BreakFlag) || ((u32Len == u32TxCnt) && (u32Len == u32RxCnt))) { + break; + } + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable specified I2S interrupt. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32IntType Interrupt type + * This parameter can be one or any combination of the following values: + * @arg I2S_INT_TX: Transfer interrupt + * @arg I2S_INT_RX: Receive interrupt + * @arg I2S_INT_ERR: Communication error interrupt + * @arg I2S_INT_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2S_IntCmd(CM_I2S_TypeDef *I2Sx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(I2Sx->CTRL, u32IntType); + } else { + CLR_REG32_BIT(I2Sx->CTRL, u32IntType); + } +} + +/** + * @brief Get I2S flag status. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Flag I2S flag type + * This parameter can be one or any combination of the following values: + * @arg I2S_FLAG_TX_ALARM: Transfer buffer alarm flag + * @arg I2S_FLAG_RX_ALARM: Receive buffer alarm flag + * @arg I2S_FLAG_TX_EMPTY: Transfer buffer empty flag + * @arg I2S_FLAG_TX_FULL: Transfer buffer full flag + * @arg I2S_FLAG_RX_EMPTY: Receive buffer empty flag + * @arg I2S_FLAG_RX_FULL: Receive buffer full flag + * @arg I2S_FLAG_TX_ERR: Transfer overflow or underflow flag + * @arg I2S_FLAG_RX_ERR: Receive overflow flag + * @arg I2S_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t I2S_GetStatus(const CM_I2S_TypeDef *I2Sx, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + uint32_t u32NormalFlag; + uint32_t u32ErrorFlag; + + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_FLAG(u32Flag)); + + u32NormalFlag = u32Flag & 0xFFFFUL; + u32ErrorFlag = u32Flag >> 16U; + if (0UL != u32NormalFlag) { + if (0UL != (READ_REG32_BIT(I2Sx->SR, u32NormalFlag))) { + enFlagSta = SET; + } + } + if ((RESET == enFlagSta) && (0UL != u32ErrorFlag)) { + if (0UL != (READ_REG32_BIT(I2Sx->ER, u32ErrorFlag))) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Clear I2S flag. + * @param [in] I2Sx Pointer to I2S unit instance + * This parameter can be one of the following values: + * @arg CM_I2Sx: I2S unit instance + * @param [in] u32Flag I2S flag type + * This parameter can be one or any combination of the following values: + * @arg I2S_FLAG_TX_ERR: Transfer overflow or underflow flag + * @arg I2S_FLAG_RX_ERR: Receive overflow flag + * @arg I2S_FLAG_CLR_ALL: All of the above + * @retval None + */ +void I2S_ClearStatus(CM_I2S_TypeDef *I2Sx, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_CLR_FLAG(u32Flag)); + + CLR_REG32_BIT(I2Sx->ER, u32Flag); +} + +/** + * @} + */ + +#endif /* LL_I2S_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_icg.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_icg.c new file mode 100644 index 0000000000..f820046809 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_icg.c @@ -0,0 +1,117 @@ +/** + ******************************************************************************* + * @file hc32_ll_icg.c + * @brief This file provides firmware functions to manage the Initial + * Configuration(ICG). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_icg.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_ICG ICG + * @brief Initial Configuration Driver Library + * @{ + */ + +#if (LL_ICG_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ICG_Local_Macros ICG Local Macros + * @{ + */ + +/** + * @brief ICG Start Address + */ +#define ICG_START_ADDR 0x400 +#define ICG_START_ADDR_AC6 ".ARM.__at_0x400" + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @brief ICG parameters configuration + */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +const uint32_t u32ICGValue[] __attribute__((section(ICG_START_ADDR_AC6))) = +#elif defined (__GNUC__) && !defined (__CC_ARM) +const uint32_t u32ICGValue[] __attribute__((section(".icg_sec"))) = +#elif defined (__CC_ARM) +const uint32_t u32ICGValue[] __attribute__((at(ICG_START_ADDR))) = +#elif defined (__ICCARM__) +#pragma location = ICG_START_ADDR +__root static const uint32_t u32ICGValue[] = +#else +#error "unsupported compiler!!" +#endif +{ + /* ICG 0~1 */ + ICG_REG_CFG0_CONST, + ICG_REG_CFG1_CONST, + /* Reserved 2~7 */ + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +#endif /* LL_ICG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_interrupts.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_interrupts.c new file mode 100644 index 0000000000..87cdafbdb2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_interrupts.c @@ -0,0 +1,1829 @@ +/** + ******************************************************************************* + * @file hc32_ll_interrupts.c + * @brief This file provides firmware functions to manage the Interrupt Controller + * (INTC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_interrupts.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_INTERRUPTS INTERRUPTS + * @brief INTC Driver Library + * @{ + */ + +#if (LL_INTERRUPTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup INTC_Local_Macros INTC Local Macros + * @{ + */ +/** + * @brief Maximum IRQ handler number + */ +#define IRQ_NUM_MAX (128U) +#define IRQn_MIN (INT000_IRQn) +#define IRQn_MAX (INT127_IRQn) +#define IRQn_OFFSET (0U) +#define EXTINT_CH_NUM_MAX (16U) +#define EIRQCFR_REG (CM_INTC->EIRQCFR) +#define NMICFR_REG (CM_INTC->NMICFR) +#define INTSEL_REG (uint32_t)(&CM_INTC->SEL0) +#define INTSEL_RST_VALUE (0x1FFUL) +#define IRQ_GRP_MOD (32UL) +#define IRQ_GRP_NUM (6UL) +#define IRQ_GRP_LOW (32UL) +#define IRQ_GRP_HIGH (37UL) +#define IRQ_GRP_BASE (32UL) + +/** + * @defgroup INTC_Check_Parameters_Validity INTC Check Parameters Validity + * @{ + */ +/*! Parameter validity check for wakeup source from stop mode. */ +#define IS_INTC_WKUP_SRC(src) \ +( ((src) != 0x00UL) && \ + (((src) | INTC_WUPEN_ALL) == INTC_WUPEN_ALL)) + +/*! Parameter validity check for event index. */ +#define IS_INTC_EVT(event) \ +( ((event) != 0x00UL) && \ + (((event) | INTC_EVT_ALL) == INTC_EVT_ALL)) + +/*! Parameter validity check for interrupt index. */ +#define IS_INTC_INT(it) \ +( ((it) != 0x00UL) && \ + (((it) | INTC_INT_ALL) == INTC_INT_ALL)) + +/*! Parameter validity check for software interrupt index. */ +#define IS_INTC_SWI(swi) \ +( ((swi) != 0x00UL) && \ + (((swi) | SWINT_ALL) == SWINT_ALL)) + +/*! Parameter validity check for NMI trigger source. */ +#define IS_NMI_SRC(src) \ +( ((src) != 0x00UL) && \ + (((src) | NMI_SRC_ALL) == NMI_SRC_ALL)) + +/*! Parameter validity check for NMI trigger edge. */ +#define IS_NMI_TRIG(trigger) \ +( ((trigger) == NMI_TRIG_FALLING) || \ + ((trigger) == NMI_TRIG_RISING)) + +/*! Parameter validity check for NMI filter A function. */ +#define IS_NMI_FAE(fae) \ +( ((fae) == NMI_FILTER_OFF) || \ + ((fae) == NMI_FILTER_ON)) + +/*! Parameter validity check for NMI filter A clock division. */ +#define IS_NMI_FACLK(faclk) \ +( ((faclk) == NMI_FCLK_DIV1) || \ + ((faclk) == NMI_FCLK_DIV8) || \ + ((faclk) == NMI_FCLK_DIV32) || \ + ((faclk) == NMI_FCLK_DIV64)) + +/*! Parameter validity check for EXTINT filter A function. */ +#define IS_EXTINT_FAE(fae) \ +( ((fae) == EXTINT_FILTER_OFF) || \ + ((fae) == EXTINT_FILTER_ON)) + +/*! Parameter validity check for EXTINT filter A clock division. */ +#define IS_EXTINT_FACLK(faclk) \ +( ((faclk) == EXTINT_FCLK_DIV1) || \ + ((faclk) == EXTINT_FCLK_DIV8) || \ + ((faclk) == EXTINT_FCLK_DIV32) || \ + ((faclk) == EXTINT_FCLK_DIV64)) + +/*! Parameter validity check for EXTINT trigger edge. */ +#define IS_EXTINT_TRIG(trigger) \ +( ((trigger) == EXTINT_TRIG_LOW) || \ + ((trigger) == EXTINT_TRIG_RISING) || \ + ((trigger) == EXTINT_TRIG_FALLING) || \ + ((trigger) == EXTINT_TRIG_BOTH)) + +/*! Parameter validity check for EXTINT channel. */ +#define IS_EXTINT_CH(ch) \ +( ((ch) != 0x00UL) && \ + (((ch) | EXTINT_CH_ALL) == EXTINT_CH_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +/** + * @defgroup INTC_Local_Variable INTC Local Variable + * @{ + */ +static func_ptr_t m_apfnIrqHandler[IRQ_NUM_MAX] = {NULL}; +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Functions INTC Global Functions + * @{ + */ +/** + * @brief IRQ sign in function + * @param [in] pstcIrqSignConfig: pointer of IRQ registration structure + * @arg enIntSrc: can be any value @ref en_int_src_t + * @arg enIRQn: can be any value from IRQn_MIN ~ IRQn_MAX for different product + * @arg pfnCallback: Callback function + * @retval int32_t: + * - LL_OK: IRQ register successfully + * - LL_ERR_INVD_PARAM: IRQ No. and Peripheral Int source are not match; NULL pointer. + * - LL_ERR_UNINIT: Specified IRQ entry was signed before. + */ +int32_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig) +{ + __IO uint32_t *INTC_SELx; + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcIrqSignConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(pstcIrqSignConfig->enIntSrc <= INT_SRC_MAX); + /* IRQ032~127 whether out of range */ + if ((((((uint32_t)pstcIrqSignConfig->enIntSrc / IRQ_GRP_MOD) * IRQ_GRP_NUM + IRQ_GRP_LOW) > \ + (uint32_t)pstcIrqSignConfig->enIRQn) || \ + ((((uint32_t)pstcIrqSignConfig->enIntSrc / IRQ_GRP_MOD) * IRQ_GRP_NUM + IRQ_GRP_HIGH) < \ + (uint32_t)pstcIrqSignConfig->enIRQn)) && \ + ((uint32_t)pstcIrqSignConfig->enIRQn >= IRQ_GRP_BASE)) { + i32Ret = LL_ERR_INVD_PARAM; + } + + else { + INTC_SELx = (__IO uint32_t *)(INTSEL_REG + (4U * (uint32_t)(pstcIrqSignConfig->enIRQn))); + /* for MISRAC2004-12.4 */ + if (INTSEL_RST_VALUE == ((*INTC_SELx) & INTSEL_RST_VALUE)) { + WRITE_REG32(*INTC_SELx, pstcIrqSignConfig->enIntSrc); + m_apfnIrqHandler[pstcIrqSignConfig->enIRQn] = pstcIrqSignConfig->pfnCallback; + } else if ((uint32_t)(pstcIrqSignConfig->enIntSrc) == ((*INTC_SELx) & INTSEL_RST_VALUE)) { + //WRITE_REG32(*INTC_SELx, pstcIrqSignConfig->enIntSrc); + m_apfnIrqHandler[pstcIrqSignConfig->enIRQn] = pstcIrqSignConfig->pfnCallback; + } else { + i32Ret = LL_ERR_UNINIT; + } + } + } + return i32Ret; +} + +/** + * @brief IRQ sign out function + * @param [in] enIRQn: can be any value from IRQn_MIN ~ IRQn_MAX for different product + * @retval int32_t: + * - LL_OK: IRQ sign out successfully + * - LL_ERR_INVD_PARAM: IRQ No. is out of range + */ +int32_t INTC_IrqSignOut(IRQn_Type enIRQn) +{ + __IO uint32_t *INTC_SELx; + int32_t i32Ret = LL_OK; + + if ((enIRQn < IRQn_MIN) || (enIRQn > IRQn_MAX)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + INTC_SELx = (__IO uint32_t *)(INTSEL_REG + (4UL * (uint32_t)enIRQn)); + WRITE_REG32(*INTC_SELx, INTSEL_RST_VALUE); + m_apfnIrqHandler[(uint8_t)enIRQn - IRQn_OFFSET] = NULL; + } + return i32Ret; +} + +/** + * @brief Stop mode wake-up source configure + * @param [in] u32WakeupSrc: Wake-up source, @ref INTC_Stop_Wakeup_Source_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_WKUP_SRC(u32WakeupSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->WUPEN, u32WakeupSrc); + } else { + CLR_REG32_BIT(CM_INTC->WUPEN, u32WakeupSrc); + } +} + +/** + * @brief Event or Interrupt output configure + * @param [in] u32Event: Event index, @ref INTC_Event_Channel_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_EVT(u32Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->EVTER, u32Event); + } else { + CLR_REG32_BIT(CM_INTC->EVTER, u32Event); + } +} + +/** + * @brief Interrupt function configure + * @param [in] u32Int: Interrupt index, @ref INT_Channel_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_INT(u32Int)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->IER, u32Int); + } else { + CLR_REG32_BIT(CM_INTC->IER, u32Int); + } +} + +/** + * @brief Software Interrupt initialize function + * @param [in] u32Ch: Software Interrupt channel, @ref SWINT_Channel_Sel for details + * @param [in] pfnCallback: Callback function + * @param [in] u32Priority: Software interrupt priority + * @retval None + */ +void INTC_SWIntInit(uint32_t u32Ch, const func_ptr_t pfnCallback, uint32_t u32Priority) +{ + stc_irq_signin_config_t stcIrqSignConfig; + + stcIrqSignConfig.enIRQn = (IRQn_Type)(__CLZ(__RBIT(u32Ch))); + stcIrqSignConfig.enIntSrc = (en_int_src_t)(__CLZ(__RBIT(u32Ch))); + /* Callback function */ + stcIrqSignConfig.pfnCallback = pfnCallback; + (void)INTC_IrqSignIn(&stcIrqSignConfig); + + NVIC_ClearPendingIRQ(stcIrqSignConfig.enIRQn); + NVIC_SetPriority(stcIrqSignConfig.enIRQn, u32Priority); + NVIC_EnableIRQ(stcIrqSignConfig.enIRQn); +} + +/** + * @brief Software Interrupt function configure + * @param [in] u32SWInt: Software Interrupt channel, @ref SWINT_Channel_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_SWIntCmd(uint32_t u32SWInt, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_SWI(u32SWInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->SWIER, u32SWInt); + } else { + CLR_REG32_BIT(CM_INTC->SWIER, u32SWInt); + } +} + +/** + * @brief Initialize NMI. Fill each pstcNmiInit with default value + * @param [in] pstcNmiInit: Pointer to a stc_nmi_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: NMI structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcNmiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcNmiInit->u32Src = 0UL; + pstcNmiInit->u32Edge = NMI_TRIG_FALLING; + pstcNmiInit->u32Filter = NMI_FILTER_OFF; + pstcNmiInit->u32FilterClock = NMI_FCLK_DIV1; + } + return i32Ret; +} + +/** + * @brief Initialize NMI. + * @param [in] pstcNmiInit: Pointer to a pstcNmiInit structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: NMI initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t NMI_Init(const stc_nmi_init_t *pstcNmiInit) +{ + int32_t i32Ret = LL_OK; + uint32_t u32NMICR = 0UL; + + /* Check if pointer is NULL */ + if (NULL == pstcNmiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(pstcNmiInit->u32Src)); + /* Clear all NMI trigger source before set */ + WRITE_REG32(NMICFR_REG, NMI_SRC_ALL); + + /* NMI trigger source configure */ + WRITE_REG32(CM_INTC->NMIENR, pstcNmiInit->u32Src); + + DDL_ASSERT(IS_NMI_TRIG(pstcNmiInit->u32Edge)); + DDL_ASSERT(IS_NMI_FAE(pstcNmiInit->u32Filter)); + DDL_ASSERT(IS_NMI_FACLK(pstcNmiInit->u32FilterClock)); + u32NMICR |= pstcNmiInit->u32Edge | pstcNmiInit->u32Filter | pstcNmiInit->u32FilterClock; + WRITE_REG32(CM_INTC->NMICR, u32NMICR); + } + return i32Ret; +} + +/** + * @brief Get NMI trigger source + * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for details + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t NMI_GetNmiStatus(uint32_t u32Src) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32Src)); + + return (((READ_REG32(CM_INTC->NMIFR) & u32Src)) != 0UL) ? SET : RESET; +} + +/** + * @brief Set NMI trigger source + * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void NMI_NmiSrcCmd(uint32_t u32Src, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32Src)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->NMIENR, u32Src); + } else { + CLR_REG32_BIT(CM_INTC->NMIENR, u32Src); + } +} + +/** + * @brief Clear specified NMI trigger source + * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for diff. MCU in details + * @retval None + */ +void NMI_ClearNmiStatus(uint32_t u32Src) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32Src)); + + SET_REG32_BIT(NMICFR_REG, u32Src); +} + +/** + * @brief Initialize External interrupt. + * @param [in] u32Ch: ExtInt channel. + * @param [in] pstcExtIntInit: Pointer to a stc_extint_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: EXTINT initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EXTINT_Init(uint32_t u32Ch, const stc_extint_init_t *pstcExtIntInit) +{ + uint8_t u8ExtIntPos; + int32_t i32Ret = LL_OK; + uint32_t EIRQCRVal; + __IO uint32_t *EIRQCRx; + + /* Check if pointer is NULL */ + if (NULL == pstcExtIntInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_EXTINT_CH(u32Ch)); + DDL_ASSERT(IS_EXTINT_FAE(pstcExtIntInit->u32Filter)); + DDL_ASSERT(IS_EXTINT_FACLK(pstcExtIntInit->u32FilterClock)); + DDL_ASSERT(IS_EXTINT_TRIG(pstcExtIntInit->u32Edge)); + for (u8ExtIntPos = 0U; u8ExtIntPos < EXTINT_CH_NUM_MAX; u8ExtIntPos++) { + if (0UL != (u32Ch & (1UL << u8ExtIntPos))) { + EIRQCRVal = pstcExtIntInit->u32Filter | pstcExtIntInit->u32FilterClock | \ + pstcExtIntInit->u32Edge; + EIRQCRx = (__IO uint32_t *)((uint32_t)&CM_INTC->EIRQCR0 + 4UL * u8ExtIntPos); + WRITE_REG32(*EIRQCRx, EIRQCRVal); + } + } + } + return i32Ret; +} + +/** + * @brief Initialize ExtInt. Fill each pstcExtIntInit with default value + * @param [in] pstcExtIntInit: Pointer to a stc_extint_init_t structure + * that contains configuration information. + * @retval int32_t: + * - LL_OK: EXTINT structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EXTINT_StructInit(stc_extint_init_t *pstcExtIntInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcExtIntInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcExtIntInit->u32Filter = EXTINT_FILTER_OFF; + pstcExtIntInit->u32FilterClock = EXTINT_FCLK_DIV1; + pstcExtIntInit->u32Edge = EXTINT_TRIG_FALLING; + } + return i32Ret; +} + +/** + * @brief Clear specified External interrupt trigger source + * @param [in] u32ExtIntCh: External interrupt channel, @ref EXTINT_Channel_Sel for details + * @retval None + */ +void EXTINT_ClearExtIntStatus(uint32_t u32ExtIntCh) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_EXTINT_CH(u32ExtIntCh)); + + SET_REG32_BIT(EIRQCFR_REG, u32ExtIntCh); +} + +/** + * @brief Get specified External interrupt trigger source + * @param [in] u32ExtIntCh: External interrupt channel, @ref EXTINT_Channel_Sel for details + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EXTINT_GetExtIntStatus(uint32_t u32ExtIntCh) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_EXTINT_CH(u32ExtIntCh)); + + return ((READ_REG16(CM_INTC->EIRQFR) & u32ExtIntCh) != 0U) ? SET : RESET; +} + +/** + * @brief Interrupt No.000 IRQ handler + * @param None + * @retval None + */ +void IRQ000_Handler(void) +{ + m_apfnIrqHandler[INT000_IRQn](); +} + +/** + * @brief Interrupt No.001 IRQ handler + * @param None + * @retval None + */ +void IRQ001_Handler(void) +{ + m_apfnIrqHandler[INT001_IRQn](); +} + +/** + * @brief Interrupt No.002 IRQ handler + * @param None + * @retval None + */ +void IRQ002_Handler(void) +{ + m_apfnIrqHandler[INT002_IRQn](); +} + +/** + * @brief Interrupt No.003 IRQ handler + * @param None + * @retval None + */ +void IRQ003_Handler(void) +{ + m_apfnIrqHandler[INT003_IRQn](); +} + +/** + * @brief Interrupt No.004 IRQ handler + * @param None + * @retval None + */ +void IRQ004_Handler(void) +{ + m_apfnIrqHandler[INT004_IRQn](); +} + +/** + * @brief Interrupt No.005 IRQ handler + * @param None + * @retval None + */ +void IRQ005_Handler(void) +{ + m_apfnIrqHandler[INT005_IRQn](); +} + +/** + * @brief Interrupt No.006 IRQ handler + * @param None + * @retval None + */ +void IRQ006_Handler(void) +{ + m_apfnIrqHandler[INT006_IRQn](); +} + +/** + * @brief Interrupt No.007 IRQ handler + * @param None + * @retval None + */ +void IRQ007_Handler(void) +{ + m_apfnIrqHandler[INT007_IRQn](); +} + +/** + * @brief Interrupt No.008 IRQ handler + * @param None + * @retval None + */ +void IRQ008_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT008_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.009 IRQ handler + * @param None + * @retval None + */ +void IRQ009_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT009_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.010 IRQ handler + * @param None + * @retval None + */ +void IRQ010_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT010_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.011 IRQ handler + * @param None + * @retval None + */ +void IRQ011_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT011_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.012 IRQ handler + * @param None + * @retval None + */ +void IRQ012_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT012_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.013 IRQ handler + * @param None + * @retval None + */ +void IRQ013_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT013_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.014 IRQ handler + * @param None + * @retval None + */ +void IRQ014_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT014_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.015 IRQ handler + * @param None + * @retval None + */ +void IRQ015_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT015_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.016 IRQ handler + * @param None + * @retval None + */ +void IRQ016_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT016_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.017 IRQ handler + * @param None + * @retval None + */ +void IRQ017_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT017_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.018 IRQ handler + * @param None + * @retval None + */ +void IRQ018_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT018_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.019 IRQ handler + * @param None + * @retval None + */ +void IRQ019_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT019_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.020 IRQ handler + * @param None + * @retval None + */ +void IRQ020_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT020_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.021 IRQ handler + * @param None + * @retval None + */ +void IRQ021_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT021_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.022 IRQ handler + * @param None + * @retval None + */ +void IRQ022_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT022_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.023 IRQ handler + * @param None + * @retval None + */ +void IRQ023_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT023_IRQn - IRQn_OFFSET](); +} + +/** + * @brief Interrupt No.024 IRQ handler + * @param None + * @retval None + */ +void IRQ024_Handler(void) +{ + m_apfnIrqHandler[INT024_IRQn](); +} + +/** + * @brief Interrupt No.025 IRQ handler + * @param None + * @retval None + */ +void IRQ025_Handler(void) +{ + m_apfnIrqHandler[INT025_IRQn](); +} + +/** + * @brief Interrupt No.026 IRQ handler + * @param None + * @retval None + */ +void IRQ026_Handler(void) +{ + m_apfnIrqHandler[INT026_IRQn](); +} + +/** + * @brief Interrupt No.027 IRQ handler + * @param None + * @retval None + */ +void IRQ027_Handler(void) +{ + m_apfnIrqHandler[INT027_IRQn](); +} + +/** + * @brief Interrupt No.028 IRQ handler + * @param None + * @retval None + */ +void IRQ028_Handler(void) +{ + m_apfnIrqHandler[INT028_IRQn](); +} + +/** + * @brief Interrupt No.029 IRQ handler + * @param None + * @retval None + */ +void IRQ029_Handler(void) +{ + m_apfnIrqHandler[INT029_IRQn](); +} + +/** + * @brief Interrupt No.030 IRQ handler + * @param None + * @retval None + */ +void IRQ030_Handler(void) +{ + m_apfnIrqHandler[INT030_IRQn](); +} + +/** + * @brief Interrupt No.031 IRQ handler + * @param None + * @retval None + */ +void IRQ031_Handler(void) +{ + m_apfnIrqHandler[INT031_IRQn](); +} + +/** + * @brief Interrupt No.032 IRQ handler + * @param None + * @retval None + */ +void IRQ032_Handler(void) +{ + m_apfnIrqHandler[INT032_IRQn](); +} + +/** + * @brief Interrupt No.033 IRQ handler + * @param None + * @retval None + */ +void IRQ033_Handler(void) +{ + m_apfnIrqHandler[INT033_IRQn](); +} + +/** + * @brief Interrupt No.034 IRQ handler + * @param None + * @retval None + */ +void IRQ034_Handler(void) +{ + m_apfnIrqHandler[INT034_IRQn](); +} + +/** + * @brief Interrupt No.035 IRQ handler + * @param None + * @retval None + */ +void IRQ035_Handler(void) +{ + m_apfnIrqHandler[INT035_IRQn](); +} + +/** + * @brief Interrupt No.036 IRQ handler + * @param None + * @retval None + */ +void IRQ036_Handler(void) +{ + m_apfnIrqHandler[INT036_IRQn](); +} + +/** + * @brief Interrupt No.037 IRQ handler + * @param None + * @retval None + */ +void IRQ037_Handler(void) +{ + m_apfnIrqHandler[INT037_IRQn](); +} + +/** + * @brief Interrupt No.038 IRQ handler + * @param None + * @retval None + */ +void IRQ038_Handler(void) +{ + m_apfnIrqHandler[INT038_IRQn](); +} + +/** + * @brief Interrupt No.039 IRQ handler + * @param None + * @retval None + */ +void IRQ039_Handler(void) +{ + m_apfnIrqHandler[INT039_IRQn](); +} + +/** + * @brief Interrupt No.040 IRQ handler + * @param None + * @retval None + */ +void IRQ040_Handler(void) +{ + m_apfnIrqHandler[INT040_IRQn](); +} + +/** + * @brief Interrupt No.041 IRQ handler + * @param None + * @retval None + */ +void IRQ041_Handler(void) +{ + m_apfnIrqHandler[INT041_IRQn](); +} + +/** + * @brief Interrupt No.042 IRQ handler + * @param None + * @retval None + */ +void IRQ042_Handler(void) +{ + m_apfnIrqHandler[INT042_IRQn](); +} + +/** + * @brief Interrupt No.043 IRQ handler + * @param None + * @retval None + */ +void IRQ043_Handler(void) +{ + m_apfnIrqHandler[INT043_IRQn](); +} + +/** + * @brief Interrupt No.044 IRQ handler + * @param None + * @retval None + */ +void IRQ044_Handler(void) +{ + m_apfnIrqHandler[INT044_IRQn](); +} + +/** + * @brief Interrupt No.045 IRQ handler + * @param None + * @retval None + */ +void IRQ045_Handler(void) +{ + m_apfnIrqHandler[INT045_IRQn](); +} + +/** + * @brief Interrupt No.046 IRQ handler + * @param None + * @retval None + */ +void IRQ046_Handler(void) +{ + m_apfnIrqHandler[INT046_IRQn](); +} + +/** + * @brief Interrupt No.047 IRQ handler + * @param None + * @retval None + */ +void IRQ047_Handler(void) +{ + m_apfnIrqHandler[INT047_IRQn](); +} + +/** + * @brief Interrupt No.048 IRQ handler + * @param None + * @retval None + */ +void IRQ048_Handler(void) +{ + m_apfnIrqHandler[INT048_IRQn](); +} + +/** + * @brief Interrupt No.049 IRQ handler + * @param None + * @retval None + */ +void IRQ049_Handler(void) +{ + m_apfnIrqHandler[INT049_IRQn](); +} + +/** + * @brief Interrupt No.050 IRQ handler + * @param None + * @retval None + */ +void IRQ050_Handler(void) +{ + m_apfnIrqHandler[INT050_IRQn](); +} + +/** + * @brief Interrupt No.051 IRQ handler + * @param None + * @retval None + */ +void IRQ051_Handler(void) +{ + m_apfnIrqHandler[INT051_IRQn](); +} + +/** + * @brief Interrupt No.052 IRQ handler + * @param None + * @retval None + */ +void IRQ052_Handler(void) +{ + m_apfnIrqHandler[INT052_IRQn](); +} + +/** + * @brief Interrupt No.053 IRQ handler + * @param None + * @retval None + */ +void IRQ053_Handler(void) +{ + m_apfnIrqHandler[INT053_IRQn](); +} + +/** + * @brief Interrupt No.054 IRQ handler + * @param None + * @retval None + */ +void IRQ054_Handler(void) +{ + m_apfnIrqHandler[INT054_IRQn](); +} + +/** + * @brief Interrupt No.055 IRQ handler + * @param None + * @retval None + */ +void IRQ055_Handler(void) +{ + m_apfnIrqHandler[INT055_IRQn](); +} + +/** + * @brief Interrupt No.056 IRQ handler + * @param None + * @retval None + */ +void IRQ056_Handler(void) +{ + m_apfnIrqHandler[INT056_IRQn](); +} + +/** + * @brief Interrupt No.057 IRQ handler + * @param None + * @retval None + */ +void IRQ057_Handler(void) +{ + m_apfnIrqHandler[INT057_IRQn](); +} + +/** + * @brief Interrupt No.058 IRQ handler + * @param None + * @retval None + */ +void IRQ058_Handler(void) +{ + m_apfnIrqHandler[INT058_IRQn](); +} + +/** + * @brief Interrupt No.059 IRQ handler + * @param None + * @retval None + */ +void IRQ059_Handler(void) +{ + m_apfnIrqHandler[INT059_IRQn](); +} + +/** + * @brief Interrupt No.060 IRQ handler + * @param None + * @retval None + */ +void IRQ060_Handler(void) +{ + m_apfnIrqHandler[INT060_IRQn](); +} + +/** + * @brief Interrupt No.061 IRQ handler + * @param None + * @retval None + */ +void IRQ061_Handler(void) +{ + m_apfnIrqHandler[INT061_IRQn](); +} + +/** + * @brief Interrupt No.062 IRQ handler + * @param None + * @retval None + */ +void IRQ062_Handler(void) +{ + m_apfnIrqHandler[INT062_IRQn](); +} + +/** + * @brief Interrupt No.063 IRQ handler + * @param None + * @retval None + */ +void IRQ063_Handler(void) +{ + m_apfnIrqHandler[INT063_IRQn](); +} + +/** + * @brief Interrupt No.064 IRQ handler + * @param None + * @retval None + */ +void IRQ064_Handler(void) +{ + m_apfnIrqHandler[INT064_IRQn](); +} + +/** + * @brief Interrupt No.065 IRQ handler + * @param None + * @retval None + */ +void IRQ065_Handler(void) +{ + m_apfnIrqHandler[INT065_IRQn](); +} + +/** + * @brief Interrupt No.066 IRQ handler + * @param None + * @retval None + */ +void IRQ066_Handler(void) +{ + m_apfnIrqHandler[INT066_IRQn](); +} + +/** + * @brief Interrupt No.067 IRQ handler + * @param None + * @retval None + */ +void IRQ067_Handler(void) +{ + m_apfnIrqHandler[INT067_IRQn](); +} + +/** + * @brief Interrupt No.068 IRQ handler + * @param None + * @retval None + */ +void IRQ068_Handler(void) +{ + m_apfnIrqHandler[INT068_IRQn](); +} + +/** + * @brief Interrupt No.069 IRQ handler + * @param None + * @retval None + */ +void IRQ069_Handler(void) +{ + m_apfnIrqHandler[INT069_IRQn](); +} + +/** + * @brief Interrupt No.070 IRQ handler + * @param None + * @retval None + */ +void IRQ070_Handler(void) +{ + m_apfnIrqHandler[INT070_IRQn](); +} + +/** + * @brief Interrupt No.071 IRQ handler + * @param None + * @retval None + */ +void IRQ071_Handler(void) +{ + m_apfnIrqHandler[INT071_IRQn](); +} + +/** + * @brief Interrupt No.072 IRQ handler + * @param None + * @retval None + */ +void IRQ072_Handler(void) +{ + m_apfnIrqHandler[INT072_IRQn](); +} + +/** + * @brief Interrupt No.073 IRQ handler + * @param None + * @retval None + */ +void IRQ073_Handler(void) +{ + m_apfnIrqHandler[INT073_IRQn](); +} + +/** + * @brief Interrupt No.074 IRQ handler + * @param None + * @retval None + */ +void IRQ074_Handler(void) +{ + m_apfnIrqHandler[INT074_IRQn](); +} + +/** + * @brief Interrupt No.075 IRQ handler + * @param None + * @retval None + */ +void IRQ075_Handler(void) +{ + m_apfnIrqHandler[INT075_IRQn](); +} + +/** + * @brief Interrupt No.076 IRQ handler + * @param None + * @retval None + */ +void IRQ076_Handler(void) +{ + m_apfnIrqHandler[INT076_IRQn](); +} + +/** + * @brief Interrupt No.077 IRQ handler + * @param None + * @retval None + */ +void IRQ077_Handler(void) +{ + m_apfnIrqHandler[INT077_IRQn](); +} + +/** + * @brief Interrupt No.078 IRQ handler + * @param None + * @retval None + */ +void IRQ078_Handler(void) +{ + m_apfnIrqHandler[INT078_IRQn](); +} + +/** + * @brief Interrupt No.079 IRQ handler + * @param None + * @retval None + */ +void IRQ079_Handler(void) +{ + m_apfnIrqHandler[INT079_IRQn](); +} + +/** + * @brief Interrupt No.080 IRQ handler + * @param None + * @retval None + */ +void IRQ080_Handler(void) +{ + m_apfnIrqHandler[INT080_IRQn](); +} + +/** + * @brief Interrupt No.081 IRQ handler + * @param None + * @retval None + */ +void IRQ081_Handler(void) +{ + m_apfnIrqHandler[INT081_IRQn](); +} + +/** + * @brief Interrupt No.082 IRQ handler + * @param None + * @retval None + */ +void IRQ082_Handler(void) +{ + m_apfnIrqHandler[INT082_IRQn](); +} + +/** + * @brief Interrupt No.083 IRQ handler + * @param None + * @retval None + */ +void IRQ083_Handler(void) +{ + m_apfnIrqHandler[INT083_IRQn](); +} + +/** + * @brief Interrupt No.084 IRQ handler + * @param None + * @retval None + */ +void IRQ084_Handler(void) +{ + m_apfnIrqHandler[INT084_IRQn](); +} + +/** + * @brief Interrupt No.085 IRQ handler + * @param None + * @retval None + */ +void IRQ085_Handler(void) +{ + m_apfnIrqHandler[INT085_IRQn](); +} + +/** + * @brief Interrupt No.086 IRQ handler + * @param None + * @retval None + */ +void IRQ086_Handler(void) +{ + m_apfnIrqHandler[INT086_IRQn](); +} + +/** + * @brief Interrupt No.087 IRQ handler + * @param None + * @retval None + */ +void IRQ087_Handler(void) +{ + m_apfnIrqHandler[INT087_IRQn](); +} + +/** + * @brief Interrupt No.088 IRQ handler + * @param None + * @retval None + */ +void IRQ088_Handler(void) +{ + m_apfnIrqHandler[INT088_IRQn](); +} + +/** + * @brief Interrupt No.089 IRQ handler + * @param None + * @retval None + */ +void IRQ089_Handler(void) +{ + m_apfnIrqHandler[INT089_IRQn](); +} + +/** + * @brief Interrupt No.090 IRQ handler + * @param None + * @retval None + */ +void IRQ090_Handler(void) +{ + m_apfnIrqHandler[INT090_IRQn](); +} + +/** + * @brief Interrupt No.091 IRQ handler + * @param None + * @retval None + */ +void IRQ091_Handler(void) +{ + m_apfnIrqHandler[INT091_IRQn](); +} + +/** + * @brief Interrupt No.092 IRQ handler + * @param None + * @retval None + */ +void IRQ092_Handler(void) +{ + m_apfnIrqHandler[INT092_IRQn](); +} + +/** + * @brief Interrupt No.093 IRQ handler + * @param None + * @retval None + */ +void IRQ093_Handler(void) +{ + m_apfnIrqHandler[INT093_IRQn](); +} + +/** + * @brief Interrupt No.094 IRQ handler + * @param None + * @retval None + */ +void IRQ094_Handler(void) +{ + m_apfnIrqHandler[INT094_IRQn](); +} + +/** + * @brief Interrupt No.095 IRQ handler + * @param None + * @retval None + */ +void IRQ095_Handler(void) +{ + m_apfnIrqHandler[INT095_IRQn](); +} + +/** + * @brief Interrupt No.096 IRQ handler + * @param None + * @retval None + */ +void IRQ096_Handler(void) +{ + m_apfnIrqHandler[INT096_IRQn](); +} + +/** + * @brief Interrupt No.097 IRQ handler + * @param None + * @retval None + */ +void IRQ097_Handler(void) +{ + m_apfnIrqHandler[INT097_IRQn](); +} + +/** + * @brief Interrupt No.098 IRQ handler + * @param None + * @retval None + */ +void IRQ098_Handler(void) +{ + m_apfnIrqHandler[INT098_IRQn](); +} + +/** + * @brief Interrupt No.099 IRQ handler + * @param None + * @retval None + */ +void IRQ099_Handler(void) +{ + m_apfnIrqHandler[INT099_IRQn](); +} + +/** + * @brief Interrupt No.100 IRQ handler + * @param None + * @retval None + */ +void IRQ100_Handler(void) +{ + m_apfnIrqHandler[INT100_IRQn](); +} + +/** + * @brief Interrupt No.101 IRQ handler + * @param None + * @retval None + */ +void IRQ101_Handler(void) +{ + m_apfnIrqHandler[INT101_IRQn](); +} + +/** + * @brief Interrupt No.102 IRQ handler + * @param None + * @retval None + */ +void IRQ102_Handler(void) +{ + m_apfnIrqHandler[INT102_IRQn](); +} + +/** + * @brief Interrupt No.103 IRQ handler + * @param None + * @retval None + */ +void IRQ103_Handler(void) +{ + m_apfnIrqHandler[INT103_IRQn](); +} + +/** + * @brief Interrupt No.104 IRQ handler + * @param None + * @retval None + */ +void IRQ104_Handler(void) +{ + m_apfnIrqHandler[INT104_IRQn](); +} + +/** + * @brief Interrupt No.105 IRQ handler + * @param None + * @retval None + */ +void IRQ105_Handler(void) +{ + m_apfnIrqHandler[INT105_IRQn](); +} + +/** + * @brief Interrupt No.106 IRQ handler + * @param None + * @retval None + */ +void IRQ106_Handler(void) +{ + m_apfnIrqHandler[INT106_IRQn](); +} + +/** + * @brief Interrupt No.107 IRQ handler + * @param None + * @retval None + */ +void IRQ107_Handler(void) +{ + m_apfnIrqHandler[INT107_IRQn](); +} + +/** + * @brief Interrupt No.108 IRQ handler + * @param None + * @retval None + */ +void IRQ108_Handler(void) +{ + m_apfnIrqHandler[INT108_IRQn](); +} + +/** + * @brief Interrupt No.109 IRQ handler + * @param None + * @retval None + */ +void IRQ109_Handler(void) +{ + m_apfnIrqHandler[INT109_IRQn](); +} + +/** + * @brief Interrupt No.110 IRQ handler + * @param None + * @retval None + */ +void IRQ110_Handler(void) +{ + m_apfnIrqHandler[INT110_IRQn](); +} + +/** + * @brief Interrupt No.111 IRQ handler + * @param None + * @retval None + */ +void IRQ111_Handler(void) +{ + m_apfnIrqHandler[INT111_IRQn](); +} + +/** + * @brief Interrupt No.112 IRQ handler + * @param None + * @retval None + */ +void IRQ112_Handler(void) +{ + m_apfnIrqHandler[INT112_IRQn](); +} + +/** + * @brief Interrupt No.113 IRQ handler + * @param None + * @retval None + */ +void IRQ113_Handler(void) +{ + m_apfnIrqHandler[INT113_IRQn](); +} + +/** + * @brief Interrupt No.114 IRQ handler + * @param None + * @retval None + */ +void IRQ114_Handler(void) +{ + m_apfnIrqHandler[INT114_IRQn](); +} + +/** + * @brief Interrupt No.115 IRQ handler + * @param None + * @retval None + */ +void IRQ115_Handler(void) +{ + m_apfnIrqHandler[INT115_IRQn](); +} + +/** + * @brief Interrupt No.116 IRQ handler + * @param None + * @retval None + */ +void IRQ116_Handler(void) +{ + m_apfnIrqHandler[INT116_IRQn](); +} + +/** + * @brief Interrupt No.117 IRQ handler + * @param None + * @retval None + */ +void IRQ117_Handler(void) +{ + m_apfnIrqHandler[INT117_IRQn](); +} + +/** + * @brief Interrupt No.118 IRQ handler + * @param None + * @retval None + */ +void IRQ118_Handler(void) +{ + m_apfnIrqHandler[INT118_IRQn](); +} + +/** + * @brief Interrupt No.119 IRQ handler + * @param None + * @retval None + */ +void IRQ119_Handler(void) +{ + m_apfnIrqHandler[INT119_IRQn](); +} + +/** + * @brief Interrupt No.120 IRQ handler + * @param None + * @retval None + */ +void IRQ120_Handler(void) +{ + m_apfnIrqHandler[INT120_IRQn](); +} + +/** + * @brief Interrupt No.121 IRQ handler + * @param None + * @retval None + */ +void IRQ121_Handler(void) +{ + m_apfnIrqHandler[INT121_IRQn](); +} + +/** + * @brief Interrupt No.122 IRQ handler + * @param None + * @retval None + */ +void IRQ122_Handler(void) +{ + m_apfnIrqHandler[INT122_IRQn](); +} + +/** + * @brief Interrupt No.123 IRQ handler + * @param None + * @retval None + */ +void IRQ123_Handler(void) +{ + m_apfnIrqHandler[INT123_IRQn](); +} + +/** + * @brief Interrupt No.124 IRQ handler + * @param None + * @retval None + */ +void IRQ124_Handler(void) +{ + m_apfnIrqHandler[INT124_IRQn](); +} + +/** + * @brief Interrupt No.125 IRQ handler + * @param None + * @retval None + */ +void IRQ125_Handler(void) +{ + m_apfnIrqHandler[INT125_IRQn](); +} + +/** + * @brief Interrupt No.126 IRQ handler + * @param None + * @retval None + */ +void IRQ126_Handler(void) +{ + m_apfnIrqHandler[INT126_IRQn](); +} + +/** + * @brief Interrupt No.127 IRQ handler + * @param None + * @retval None + */ +void IRQ127_Handler(void) +{ + m_apfnIrqHandler[INT127_IRQn](); +} + +/** + * @} + */ + +#endif /* LL_INTERRUPTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_keyscan.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_keyscan.c new file mode 100644 index 0000000000..bb3f1938ba --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_keyscan.c @@ -0,0 +1,227 @@ +/** + ******************************************************************************* + * @file hc32_ll_keyscan.c + * @brief This file provides firmware functions to manage the matrix keyscan + * function (KEYSCAN). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_keyscan.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_KEYSCAN KEYSCAN + * @brief Matrix keyscan Driver Library + * @{ + */ + +#if (LL_KEYSCAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Local_Macros KEYSCAN Local Macros + * @{ + */ + +/** + * @defgroup KEYSCAN_Check_Parameters_Validity KEYSCAN Check Parameters Validity + * @{ + */ +/*! Parameter valid check for KEYSCAN HiZ state cycles. */ +#define IS_KEYSCAN_HIZ_CYCLE(clc) \ +( ((clc) == KEYSCAN_HIZ_CYCLE_4) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_8) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_16) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_32) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_64) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_256) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_512) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_1024)) + +/*! Parameter valid check for KEYSCAN low level output cycles. */ +#define IS_KEYSCAN_LOW_CYCLE(clc) \ +( ((clc) == KEYSCAN_LOW_CYCLE_4) || \ + ((clc) == KEYSCAN_LOW_CYCLE_8) || \ + ((clc) == KEYSCAN_LOW_CYCLE_16) || \ + ((clc) == KEYSCAN_LOW_CYCLE_32) || \ + ((clc) == KEYSCAN_LOW_CYCLE_64) || \ + ((clc) == KEYSCAN_LOW_CYCLE_128) || \ + ((clc) == KEYSCAN_LOW_CYCLE_256) || \ + ((clc) == KEYSCAN_LOW_CYCLE_512) || \ + ((clc) == KEYSCAN_LOW_CYCLE_1K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_2K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_4K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_8K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_16K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_32K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_64K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_128K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_256K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_512K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_1M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_2M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_4M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_8M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_16M)) + +/*! Parameter valid check for KEYSCAN scan clock. */ +#define IS_KEYSCAN_CLK(clk) \ +( ((clk) == KEYSCAN_CLK_HCLK) || \ + ((clk) == KEYSCAN_CLK_LRC) || \ + ((clk) == KEYSCAN_CLK_XTAL32)) + +/*! Parameter valid check for KEYSCAN keyout pins. */ +#define IS_KEYSCAN_OUT(out) \ +( ((out) == KEYSCAN_OUT_0T1) || \ + ((out) == KEYSCAN_OUT_0T2) || \ + ((out) == KEYSCAN_OUT_0T3) || \ + ((out) == KEYSCAN_OUT_0T4) || \ + ((out) == KEYSCAN_OUT_0T5) || \ + ((out) == KEYSCAN_OUT_0T6) || \ + ((out) == KEYSCAN_OUT_0T7)) + +/*! Parameter valid check for KEYSCAN keyin(EIRQ) pins. */ +#define IS_KEYSCAN_IN(in) \ +( ((in) != 0x00U) && \ + (((in) | KEYSCAN_IN_ALL) == KEYSCAN_IN_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Functions KEYSCAN Global Functions + * @{ + */ + +/** + * @brief KEYSCAN function config. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void KEYSCAN_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(CM_KEYSCAN->SER, enNewState); +} + +/** + * @brief Initialize KEYSCAN config structure. Fill each pstcKeyscanInit with default value + * @param [in] pstcKeyscanInit Pointer to a stc_keyscan_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: KEYSCAN structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcKeyscanInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcKeyscanInit->u32HizCycle = KEYSCAN_HIZ_CYCLE_4; + pstcKeyscanInit->u32LowCycle = KEYSCAN_LOW_CYCLE_4; + pstcKeyscanInit->u32KeyClock = KEYSCAN_CLK_HCLK; + pstcKeyscanInit->u32KeyOut = KEYSCAN_OUT_0T1; + pstcKeyscanInit->u32KeyIn = KEYSCAN_IN_0; + } + return i32Ret; +} + +/** + * @brief KEYSCAN initialize. + * @param [in] pstcKeyscanInit KEYSCAN config structure. + * @arg u32HizCycle Hiz state keep cycles during low level output. + * @arg u32LowCycle Low level output cycles. + * @arg u32KeyClock Scan clock. + * @arg u32KeyOut KEYOUT selection. + * @arg u32KeyIn KEYIN(EIRQ) selection. + * @retval int32_t: + * - LL_OK: KEYSCAN function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcKeyscanInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_KEYSCAN_HIZ_CYCLE(pstcKeyscanInit->u32HizCycle)); + DDL_ASSERT(IS_KEYSCAN_LOW_CYCLE(pstcKeyscanInit->u32LowCycle)); + DDL_ASSERT(IS_KEYSCAN_CLK(pstcKeyscanInit->u32KeyClock)); + DDL_ASSERT(IS_KEYSCAN_OUT(pstcKeyscanInit->u32KeyOut)); + DDL_ASSERT(IS_KEYSCAN_IN(pstcKeyscanInit->u32KeyIn)); + + WRITE_REG32(CM_KEYSCAN->SCR, \ + (pstcKeyscanInit->u32HizCycle | pstcKeyscanInit->u32LowCycle | \ + pstcKeyscanInit->u32KeyClock | pstcKeyscanInit->u32KeyOut | \ + pstcKeyscanInit->u32KeyIn)); + } + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_KEYSCAN_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_mpu.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_mpu.c new file mode 100644 index 0000000000..b6a2930f78 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_mpu.c @@ -0,0 +1,891 @@ +/** + ******************************************************************************* + * @file hc32_ll_mpu.c + * @brief This file provides firmware functions to manage the Memory Protection + * Unit(MPU). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_mpu.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_MPU MPU + * @brief Memory Protection Unit Driver Library + * @{ + */ + +#if (LL_MPU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup MPU_Local_Macros MPU Local Macros + * @{ + */ + +/* Number of MPU region */ +#define MPU_REGION_MAX_NUM (16UL) + +/* Number of MPU unit */ +#define MPU_UNIT_MAX_NUM (3UL) +/* MPU Register Combination Mask */ +#define MPU_UNIT_CONFIG_MASK (MPU_CR_SMPU2BRP | MPU_CR_SMPU2BWP | MPU_CR_SMPU2ACT | \ + MPU_CR_SMPU1BRP | MPU_CR_SMPU1BWP | MPU_CR_SMPU1ACT | \ + MPU_CR_FMPUBRP | MPU_CR_FMPUBWP | MPU_CR_FMPUACT) +/* DMA units have 16 regions */ +#define MPU_16REGION_UNIT (MPU_UNIT_DMA1 | MPU_UNIT_DMA2) + +/* Get the specified register address of the MPU Intrusion Control */ +#define MPU_RGD_ADDR(__NUM__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->RGD0)) + ((uint32_t)(__NUM__) << 2U)) +#define MPU_RGCR_ADDR(__NUM__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->RGCR0)) + ((uint32_t)(__NUM__) << 2U)) + +/** + * @defgroup MPU_Check_Parameters_Validity MPU Check Parameters Validity + * @{ + */ +#define IS_MPU_UNIT(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_UNIT_ALL) == MPU_UNIT_ALL)) + +#define IS_MPU_REGION(x) ((x) <= MPU_REGION_NUM15) + +#define IS_MPU_UNIT_REGION(unit, region) \ +( (((unit) | MPU_16REGION_UNIT) == MPU_16REGION_UNIT) || \ + ((region) <= MPU_REGION_NUM7)) + +#define IS_MPU_BACKGROUND_WR(x) \ +( ((x) == MPU_BACKGROUND_WR_DISABLE) || \ + ((x) == MPU_BACKGROUND_WR_ENABLE)) + +#define IS_MPU_BACKGROUND_RD(x) \ +( ((x) == MPU_BACKGROUND_RD_DISABLE) || \ + ((x) == MPU_BACKGROUND_RD_ENABLE)) + +#define IS_MPU_EXP_TYPE(x) \ +( ((x) == MPU_EXP_TYPE_NONE) || \ + ((x) == MPU_EXP_TYPE_BUS_ERR) || \ + ((x) == MPU_EXP_TYPE_NMI) || \ + ((x) == MPU_EXP_TYPE_RST)) + +#define IS_MPU_REGION_WR(x) \ +( ((x) == MPU_REGION_WR_DISABLE) || \ + ((x) == MPU_REGION_WR_ENABLE)) + +#define IS_MPU_REGION_RD(x) \ +( ((x) == MPU_REGION_RD_DISABLE) || \ + ((x) == MPU_REGION_RD_ENABLE)) + +#define IS_MPU_REGION_SIZE(x) \ +( ((x) >= MPU_REGION_SIZE_32BYTE) && \ + ((x) <= MPU_REGION_SIZE_4GBYTE)) + +#define IS_MPU_REGION_BASE_ADDER(addr, size) \ +( ((addr) & ((uint32_t)(~((uint64_t)0xFFFFFFFFUL << ((size) + 1U))))) == 0UL) + +#define IS_MPU_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_FLAG_ALL) == MPU_FLAG_ALL)) + +#define IS_MPU_IP_TYPE(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_IP_ALL) == MPU_IP_ALL)) + +#define IS_MPU_IP_EXP_TYPE(x) \ +( ((x) == MPU_IP_EXP_TYPE_NONE) || \ + ((x) == MPU_IP_EXP_TYPE_BUS_ERR)) + +#define IS_MPU_UNLOCK() ((CM_MPU->WP & MPU_WP_MPUWE) == MPU_WP_MPUWE) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Functions MPU Global Functions + * @{ + */ + +/** + * @brief De-Initialize MPU. + * @param None + * @retval None + */ +void MPU_DeInit(void) +{ + uint32_t i; + __IO uint32_t *RGD; + __IO uint32_t *RGE; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + + for (i = 0UL; i < MPU_REGION_MAX_NUM; i++) { + RGD = MPU_RGD_ADDR(i); + WRITE_REG32(*RGD, 0UL); + RGE = MPU_RGCR_ADDR(i); + WRITE_REG32(*RGE, 0UL); + } + WRITE_REG32(CM_MPU->ECLR, MPU_FLAG_ALL); + WRITE_REG32(CM_MPU->IPPR, 0UL); + WRITE_REG32(CM_MPU->CR, 0UL); +} + +/** + * @brief Initialize MPU. + * @param [in] pstcMpuInit Pointer to a @ref stc_mpu_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_Init(const stc_mpu_init_t *pstcMpuInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcMpuInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcDma1.u32ExceptionType)); + DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcDma1.u32BackgroundWrite)); + DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcDma1.u32BackgroundRead)); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcDma2.u32ExceptionType)); + DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcDma2.u32BackgroundWrite)); + DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcDma2.u32BackgroundRead)); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcUsbFSDma.u32ExceptionType)); + DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcUsbFSDma.u32BackgroundWrite)); + DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcUsbFSDma.u32BackgroundRead)); + MODIFY_REG32(CM_MPU->CR, MPU_UNIT_CONFIG_MASK, + (pstcMpuInit->stcDma2.u32ExceptionType | pstcMpuInit->stcDma2.u32BackgroundWrite | + pstcMpuInit->stcDma2.u32BackgroundRead) | + ((pstcMpuInit->stcDma1.u32ExceptionType | pstcMpuInit->stcDma1.u32BackgroundWrite | + pstcMpuInit->stcDma1.u32BackgroundRead) << 8U) | + ((pstcMpuInit->stcUsbFSDma.u32ExceptionType | pstcMpuInit->stcUsbFSDma.u32BackgroundWrite | + pstcMpuInit->stcUsbFSDma.u32BackgroundRead) << 16U)); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_mpu_init_t member with default value. + * @param [out] pstcMpuInit Pointer to a @ref stc_mpu_init_t structure + * @retval int32_t: + * - LL_OK: stc_mpu_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcMpuInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcMpuInit->stcDma1.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcDma1.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE; + pstcMpuInit->stcDma1.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE; + pstcMpuInit->stcDma2.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcDma2.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE; + pstcMpuInit->stcDma2.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE; + pstcMpuInit->stcUsbFSDma.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcUsbFSDma.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE; + pstcMpuInit->stcUsbFSDma.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE; + } + + return i32Ret; +} + +/** + * @brief Set the exception type of the unit. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] u32Type Exception type of MPU unit. + * This parameter can be one of the following values: + * @arg MPU_EXP_TYPE_NONE: The host unit access protection regions will be ignored + * @arg MPU_EXP_TYPE_BUS_ERR: The host unit access protection regions will be ignored and a bus error will be triggered + * @arg MPU_EXP_TYPE_NMI: The host unit access protection regions will be ignored and a NMI interrupt will be triggered + * @arg MPU_EXP_TYPE_RST: The host unit access protection regions will trigger the reset + * @retval None + */ +void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32Type) +{ + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_EXP_TYPE(u32Type)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + MODIFY_REG32(CM_MPU->CR, MPU_CR_SMPU2ACT << (u32UnitPos << 3U), u32Type << (u32UnitPos << 3U)); + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the write of the unit for background space. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_BackgroundWriteCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_MPU->CR, MPU_CR_SMPU2BWP << (u32UnitPos << 3U)); + } else { + SET_REG32_BIT(CM_MPU->CR, MPU_CR_SMPU2BWP << (u32UnitPos << 3U)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the read of the unit for background space. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_BackgroundReadCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_MPU->CR, MPU_CR_SMPU2BRP << (u32UnitPos << 3U)); + } else { + SET_REG32_BIT(CM_MPU->CR, MPU_CR_SMPU2BRP << (u32UnitPos << 3U)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the access control of the unit. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + if (DISABLE != enNewState) { + SET_REG32_BIT(CM_MPU->CR, MPU_CR_SMPU2E << (u32UnitPos << 3U)); + } else { + CLR_REG32_BIT(CM_MPU->CR, MPU_CR_SMPU2E << (u32UnitPos << 3U)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Gets the status of MPU flag. + * @param [in] u32Flag The type of MPU flag. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t MPU_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_MPU->SR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear the flag of MPU. + * @param [in] u32Flag The type of MPU flag. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Flag + * @retval None + */ +void MPU_ClearStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_FLAG(u32Flag)); + + SET_REG32_BIT(CM_MPU->ECLR, u32Flag); +} + +/** + * @brief Initialize the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region, + * and the low 'u32Size+1' bits are fixed at 0. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] pstcRegionInit Pointer to a @ref stc_mpu_region_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *RGD; + __IO uint32_t *RGWP; + uint32_t i; + uint32_t u32UnitNum = MPU_UNIT_MAX_NUM; + stc_mpu_region_permission_t RegionBuffer[MPU_UNIT_MAX_NUM]; + + if (NULL == pstcRegionInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_REGION_SIZE(pstcRegionInit->u32Size)); + DDL_ASSERT(IS_MPU_REGION_BASE_ADDER(pstcRegionInit->u32BaseAddr, pstcRegionInit->u32Size)); + DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcDma1.u32RegionWrite)); + DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcDma1.u32RegionRead)); + DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcDma2.u32RegionWrite)); + DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcDma2.u32RegionRead)); + DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcUsbFSDma.u32RegionWrite)); + DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcUsbFSDma.u32RegionRead)); + + RGD = MPU_RGD_ADDR(u32Num); + WRITE_REG32(*RGD, (pstcRegionInit->u32Size | pstcRegionInit->u32BaseAddr)); + /* Configure the read/write permission for the region */ + RegionBuffer[0] = pstcRegionInit->stcDma1; + RegionBuffer[1] = pstcRegionInit->stcDma2; + RegionBuffer[2] = pstcRegionInit->stcUsbFSDma; + if ((u32Num >= MPU_REGION_NUM8) && (u32Num <= MPU_REGION_NUM15)) { + u32UnitNum = 2UL; + } + for (i = 0UL; i < u32UnitNum; i++) { + /* Configure the write permission for the region */ + RGWP = MPU_RGCR_ADDR(u32Num); + if (MPU_REGION_WR_DISABLE != RegionBuffer[i].u32RegionWrite) { + CLR_REG32_BIT(*RGWP, MPU_RGCR_S2RGWP << (i << 3U)); + } else { + SET_REG32_BIT(*RGWP, MPU_RGCR_S2RGWP << (i << 3U)); + } + /* Configure the read permission for the region */ + if (MPU_REGION_WR_DISABLE != RegionBuffer[i].u32RegionRead) { + CLR_REG32_BIT(*RGWP, MPU_RGCR_S2RGRP << (i << 3U)); + } else { + SET_REG32_BIT(*RGWP, MPU_RGCR_S2RGRP << (i << 3U)); + } + } + } + + return i32Ret; +} + +/** + * @brief Fills each stc_mpu_region_init_t member with default value. + * @param [out] pstcRegionInit Pointer to a @ref stc_mpu_region_init_t structure + * @retval int32_t: + * - LL_OK: stc_mpu_region_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRegionInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcRegionInit->u32BaseAddr = 0UL; + pstcRegionInit->u32Size = MPU_REGION_SIZE_32BYTE; + pstcRegionInit->stcDma1.u32RegionWrite = MPU_REGION_WR_DISABLE; + pstcRegionInit->stcDma1.u32RegionRead = MPU_REGION_RD_DISABLE; + pstcRegionInit->stcDma2.u32RegionWrite = MPU_REGION_WR_DISABLE; + pstcRegionInit->stcDma2.u32RegionRead = MPU_REGION_RD_DISABLE; + pstcRegionInit->stcUsbFSDma.u32RegionWrite = MPU_REGION_WR_DISABLE; + pstcRegionInit->stcUsbFSDma.u32RegionRead = MPU_REGION_RD_DISABLE; + } + + return i32Ret; +} + +/** + * @brief Set the base address of the region. + * @note The effective bits of the 'u32Addr' are related to the 'size' of the region, + * and the low 'size+1' bits are fixed at 0. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Addr The base address of the region. + * @retval None + */ +void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr) +{ + __IO uint32_t *RGD; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + + RGD = MPU_RGD_ADDR(u32Num); + /* Check parameters */ + DDL_ASSERT(IS_MPU_REGION_BASE_ADDER(u32Addr, READ_REG32_BIT(*RGD, MPU_RGD_MPURGSIZE))); + + MODIFY_REG32(*RGD, MPU_RGD_MPURGADDR, u32Addr); +} + +/** + * @brief Set the size of the region. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Size The size of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_SIZE_32BYTE: 32 Byte + * @arg MPU_REGION_SIZE_64BYTE: 64 Byte + * @arg MPU_REGION_SIZE_128BYTE: 126 Byte + * @arg MPU_REGION_SIZE_256BYTE: 256 Byte + * @arg MPU_REGION_SIZE_512BYTE: 512 Byte + * @arg MPU_REGION_SIZE_1KBYTE: 1K Byte + * @arg MPU_REGION_SIZE_2KBYTE: 2K Byte + * @arg MPU_REGION_SIZE_4KBYTE: 4K Byte + * @arg MPU_REGION_SIZE_8KBYTE: 8K Byte + * @arg MPU_REGION_SIZE_16KBYTE: 16K Byte + * @arg MPU_REGION_SIZE_32KBYTE: 32K Byte + * @arg MPU_REGION_SIZE_64KBYTE: 64K Byte + * @arg MPU_REGION_SIZE_128KBYTE: 128K Byte + * @arg MPU_REGION_SIZE_256KBYTE: 256K Byte + * @arg MPU_REGION_SIZE_512KBYTE: 512K Byte + * @arg MPU_REGION_SIZE_1MBYTE: 1M Byte + * @arg MPU_REGION_SIZE_2MBYTE: 2M Byte + * @arg MPU_REGION_SIZE_4MBYTE: 4M Byte + * @arg MPU_REGION_SIZE_8MBYTE: 8M Byte + * @arg MPU_REGION_SIZE_16MBYTE: 16M Byte + * @arg MPU_REGION_SIZE_32MBYTE: 32M Byte + * @arg MPU_REGION_SIZE_64MBYTE: 64M Byte + * @arg MPU_REGION_SIZE_128MBYTE: 128M Byte + * @arg MPU_REGION_SIZE_256MBYTE: 256M Byte + * @arg MPU_REGION_SIZE_512MBYTE: 512M Byte + * @arg MPU_REGION_SIZE_1GBYTE: 1G Byte + * @arg MPU_REGION_SIZE_2GBYTE: 2G Byte + * @arg MPU_REGION_SIZE_4GBYTE: 4G Byte + * @retval None + */ +void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size) +{ + __IO uint32_t *RGD; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_REGION_SIZE(u32Size)); + + RGD = MPU_RGD_ADDR(u32Num); + MODIFY_REG32(*RGD, MPU_RGD_MPURGSIZE, u32Size); +} + +/** + * @brief Enable or disable the write of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_RegionWriteCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGWP; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + RGWP = MPU_RGCR_ADDR(u32Num); + if (DISABLE != enNewState) { + CLR_REG32_BIT(*RGWP, MPU_RGCR_S2RGWP << (u32UnitPos << 3U)); + } else { + SET_REG32_BIT(*RGWP, MPU_RGCR_S2RGWP << (u32UnitPos << 3U)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the read of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_RegionReadCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGRP; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + RGRP = MPU_RGCR_ADDR(u32Num); + if (DISABLE != enNewState) { + CLR_REG32_BIT(*RGRP, MPU_RGCR_S2RGRP << (u32UnitPos << 3U)); + } else { + SET_REG32_BIT(*RGRP, MPU_RGCR_S2RGRP << (u32UnitPos << 3U)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the access control of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGE; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + RGE = MPU_RGCR_ADDR(u32Num); + if (DISABLE != enNewState) { + SET_REG32_BIT(*RGE, MPU_RGCR_S2RGE << (u32UnitPos << 3U)); + } else { + CLR_REG32_BIT(*RGE, MPU_RGCR_S2RGE << (u32UnitPos << 3U)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Set the type of exception to access the protected IP. + * @param [in] u32Type Exception type of MPU IP. + * This parameter can be one of the following values: + * @arg MPU_IP_EXP_TYPE_NONE: Access to the protected IP will be ignored + * @arg MPU_IP_EXP_TYPE_BUS_ERR: Access to the protected IP will trigger a bus error + * @retval None + */ +void MPU_IP_SetExceptionType(uint32_t u32Type) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_EXP_TYPE(u32Type)); + + WRITE_REG32(bCM_MPU->IPPR_b.BUSERRE, (u32Type >> MPU_IPPR_BUSERRE_POS)); +} + +/** + * @brief Enable or disable write for the IP. + * @param [in] u32Periph The peripheral of the chip. + * This parameter can be one or any combination of the following values: + * @arg MPU_IP_AES: AES module + * @arg MPU_IP_HASH: HASH module + * @arg MPU_IP_TRNG: TRNG module + * @arg MPU_IP_CRC: CRC module + * @arg MPU_IP_EFM: EFM module + * @arg MPU_IP_WDT: WDT module + * @arg MPU_IP_SWDT: SWDT module + * @arg MPU_IP_BKSRAM: BKSRAM module + * @arg MPU_IP_RTC: RTC module + * @arg MPU_IP_MPU: MPU module + * @arg MPU_IP_SRAMC: SRAMC module + * @arg MPU_IP_INTC: INTC module + * @arg MPU_IP_RMU_CMU_PWC: RMU, CMU and PWC modules + * @arg MPU_IP_FCG: PWR_FCG0/1/2/3 and PWR_FCG0PC registers + * @arg MPU_IP_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_IP_WriteCmd(uint32_t u32Periph, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_TYPE(u32Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_MPU->IPPR, (u32Periph << 1U)); + } else { + SET_REG32_BIT(CM_MPU->IPPR, (u32Periph << 1U)); + } +} + +/** + * @brief Enable or disable read for the IP. + * @param [in] u32Periph The peripheral of the chip. + * This parameter can be one or any combination of the following values: + * @arg MPU_IP_AES: AES module + * @arg MPU_IP_HASH: HASH module + * @arg MPU_IP_TRNG: TRNG module + * @arg MPU_IP_CRC: CRC module + * @arg MPU_IP_EFM: EFM module + * @arg MPU_IP_WDT: WDT module + * @arg MPU_IP_SWDT: SWDT module + * @arg MPU_IP_BKSRAM: BKSRAM module + * @arg MPU_IP_RTC: RTC module + * @arg MPU_IP_MPU: MPU module + * @arg MPU_IP_SRAMC: SRAMC module + * @arg MPU_IP_INTC: INTC module + * @arg MPU_IP_RMU_CMU_PWC: RMU, CMU and PWC modules + * @arg MPU_IP_FCG: PWR_FCG0/1/2/3 and PWR_FCG0PC registers + * @arg MPU_IP_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_IP_ReadCmd(uint32_t u32Periph, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_TYPE(u32Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_MPU->IPPR, u32Periph); + } else { + SET_REG32_BIT(CM_MPU->IPPR, u32Periph); + } +} + +/** + * @} + */ + +#endif /* LL_MPU_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_ots.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_ots.c new file mode 100644 index 0000000000..4e05d7c8f9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_ots.c @@ -0,0 +1,329 @@ +/** + ******************************************************************************* + * @file hc32_ll_ots.c + * @brief This file provides firmware functions to manage the OTS. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_ots.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_OTS OTS + * @brief OTS Driver Library + * @{ + */ + +#if (LL_OTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup OTS_Local_Macros OTS Local Macros + * @{ + */ + +/** + * @defgroup OTS_Configuration_Bit_Mask OTS Configuration Bit Mask + * @{ + */ +#define OTS_CTL_INIT_MSK (OTS_CTL_OTSCK | OTS_CTL_TSSTP) +/** + * @} + */ + +/** + * @defgroup OTS_Factor OTS Factor + * @{ + */ +#define OTS_DR1_FACTOR (1.0F) + +#define OTS_DR2_FACTOR (1.0F) +#define OTS_ECR_XTAL_FACTOR (1.0F) +/** + * @} + */ + +/** + * @defgroup OTS_Check_Parameters_Validity OTS check parameters validity + * @{ + */ +#define IS_OTS_CLK(x) (((x) == OTS_CLK_HRC) || ((x) == OTS_CLK_XTAL)) + +#define IS_OTS_AUTO_OFF_EN(x) (((x) == OTS_AUTO_OFF_DISABLE) || ((x) == OTS_AUTO_OFF_ENABLE)) +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup OTS_Local_Variables OTS Local Variables + * @{ + */ +static float32_t m_f32SlopeK = 0.0F; +static float32_t m_f32OffsetM = 0.0F; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup OTS_Global_Functions OTS Global Functions + * @{ + */ + +/** + * @brief Initializes OTS according to the specified parameters in the structure stc_ots_init_t. + * @param [in] pstcOTSInit Pointer to a stc_ots_init_t structure value that + * contains the configuration information for OTS. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcOTSInit == NULL. + */ +int32_t OTS_Init(const stc_ots_init_t *pstcOTSInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcOTSInit != NULL) { + DDL_ASSERT(IS_OTS_CLK(pstcOTSInit->u16ClockSrc)); + DDL_ASSERT(IS_OTS_AUTO_OFF_EN(pstcOTSInit->u16AutoOffEn)); + + /* Stop OTS sampling. */ + OTS_Stop(); + WRITE_REG16(CM_OTS->CTL, (pstcOTSInit->u16ClockSrc | pstcOTSInit->u16AutoOffEn)); + m_f32SlopeK = pstcOTSInit->f32SlopeK; + m_f32OffsetM = pstcOTSInit->f32OffsetM; + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set a default value for OTS initialization structure. + * @param [in] pstcOTSInit Pointer to a stc_ots_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcOTSInit == NULL. + */ +int32_t OTS_StructInit(stc_ots_init_t *pstcOTSInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcOTSInit != NULL) { + pstcOTSInit->u16ClockSrc = OTS_CLK_HRC; + pstcOTSInit->f32SlopeK = 0.0F; + pstcOTSInit->f32OffsetM = 0.0F; + pstcOTSInit->u16AutoOffEn = OTS_AUTO_OFF_ENABLE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initializes OTS peripheral. Reset the registers of OTS. + * @param None + * @retval None + */ +void OTS_DeInit(void) +{ + /* Stop OTS. */ + OTS_Stop(); + /* Set the value of all registers to the reset value. */ + WRITE_REG16(CM_OTS->CTL, 0U); + WRITE_REG16(CM_OTS->DR1, 0U); + WRITE_REG16(CM_OTS->DR2, 0U); + WRITE_REG16(CM_OTS->ECR, 0U); +} + +/** + * @brief Get temperature via normal mode. + * @param [out] pf32Temp Pointer to a float32_t type address that the temperature value to be stored. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Works timeout. + * - LL_ERR_INVD_PARAM: pf32Temp == NULL. + */ +int32_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout) +{ + __IO uint32_t u32TimeCount = u32Timeout; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pf32Temp != NULL) { + i32Ret = LL_ERR_TIMEOUT; + OTS_Start(); + while (u32TimeCount-- != 0U) { + if (READ_REG32(bCM_OTS->CTL_b.OTSST) == 0UL) { + *pf32Temp = OTS_CalculateTemp(); + i32Ret = LL_OK; + break; + } + } + OTS_Stop(); + } + + return i32Ret; +} + +/** + * @brief Enable or disable the OTS interrutp. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void OTS_IntCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_OTS->CTL_b.OTSIE, enNewState); +} + +/** + * @brief OTS scaling experiment. Get the value of the data register at the specified temperature to calculate K and M. + * @param [out] pu16Dr1: Pointer to an address to store the value of data register 1. + * @param [out] pu16Dr2: Pointer to an address to store the value of data register 2. + * @param [out] pu16Ecr: Pointer to an address to store the value of register ECR. + * @param [out] pf32A: Pointer to an address to store the parameter A. + * @param [in] u32Timeout: Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Works timeout. + * - LL_ERR_INVD_PARAM: If one the following cases matches: + * - pu16Dr1 == NULL. + * - pu16Dr2 == NULL. + * - pu16Ecr == NULL. + * - pf32A == NULL. + */ +int32_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, + uint16_t *pu16Ecr, float32_t *pf32A, + uint32_t u32Timeout) +{ + float32_t f32Dr1; + float32_t f32Dr2; + float32_t f32Ecr; + __IO uint32_t u32TimeCount = u32Timeout; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((NULL != pu16Dr1) && (NULL != pu16Dr2) && \ + (NULL != pu16Ecr) && (NULL != pf32A)) { + i32Ret = LL_ERR_TIMEOUT; + OTS_Start(); + while (u32TimeCount-- != 0U) { + if (READ_REG32(bCM_OTS->CTL_b.OTSST) == 0UL) { + i32Ret = LL_OK; + break; + } + } + OTS_Stop(); + + if (i32Ret == LL_OK) { + *pu16Dr1 = READ_REG16(CM_OTS->DR1); + *pu16Dr2 = READ_REG16(CM_OTS->DR2); + + f32Dr1 = (float32_t)(*pu16Dr1); + f32Dr2 = (float32_t)(*pu16Dr2); + + if (READ_REG8_BIT(CM_OTS->CTL, OTS_CTL_OTSCK) == OTS_CLK_HRC) { + *pu16Ecr = READ_REG16(CM_OTS->ECR); + f32Ecr = (float32_t)(*pu16Ecr); + } else { + *pu16Ecr = 1U; + f32Ecr = OTS_ECR_XTAL_FACTOR; + } + + if ((f32Dr1 != 0.0F) && (f32Dr2 != 0.0F) && (f32Ecr != 0.0F)) { + *pf32A = ((OTS_DR1_FACTOR / f32Dr1) - (OTS_DR2_FACTOR / f32Dr2)) * f32Ecr; + } + } + } + + return i32Ret; +} + +/** + * @brief Calculate the temperature value. + * @param None + * @retval A float32_t type value of temperature. + */ +float32_t OTS_CalculateTemp(void) +{ + float32_t f32Ret = 0.0F; + uint16_t u16Dr1 = READ_REG16(CM_OTS->DR1); + uint16_t u16Dr2 = READ_REG16(CM_OTS->DR2); + uint16_t u16Ecr = READ_REG16(CM_OTS->ECR); + float32_t f32Dr1 = (float32_t)u16Dr1; + float32_t f32Dr2 = (float32_t)u16Dr2; + float32_t f32Ecr = (float32_t)u16Ecr; + + if (READ_REG8_BIT(CM_OTS->CTL, OTS_CTL_OTSCK) == OTS_CLK_XTAL) { + f32Ecr = OTS_ECR_XTAL_FACTOR; + } + + if ((f32Dr1 != 0.0F) && (f32Dr2 != 0.0F) && (f32Ecr != 0.0F)) { + f32Ret = m_f32SlopeK * ((OTS_DR1_FACTOR / f32Dr1) - (OTS_DR2_FACTOR / f32Dr2)) * f32Ecr + m_f32OffsetM; + } + + return f32Ret; +} + +/** + * @} + */ + +#endif /* LL_OTS_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_pwc.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_pwc.c new file mode 100644 index 0000000000..b10eb20619 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_pwc.c @@ -0,0 +1,1648 @@ +/** + ******************************************************************************* + * @file hc32_ll_pwc.c + * @brief This file provides firmware functions to manage the Power Control(PWC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_pwc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_PWC PWC + * @brief Power Control Driver Library + * @{ + */ + +#if (LL_PWC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup PWC_Local_Macros PWC Local Macros + * @{ + */ + +/* Get the backup register address of PWC */ + +#define PWC_SYSCLK_SRC_HRC (0U) +#define PWC_SYSCLK_SRC_PLL (5U) + +#define PWC_MD_SWITCH_TIMEOUT (30UL) +#define PWC_MD_SWITCH_TIMEOUT2 (0x1000UL) +#define PWC_MD_SWITCH_CMD (0x10U) + +#define PWC_LVD_EN_REG (CM_PWC->PVDCR0) +#define PWC_LVD_EN_BIT (PWC_PVDCR0_PVD1EN) +#define PWC_LVD_EXT_INPUT_EN_REG (CM_PWC->PVDCR0) +#define PWC_LVD_EXT_INPUT_EN_BIT (PWC_PVDCR0_EXVCCINEN) +#define PWC_LVD_CMP_OUTPUT_EN_REG (CM_PWC->PVDCR1) +#define PWC_LVD_CMP_OUTPUT_EN_BIT (PWC_PVDCR1_PVD1CMPOE) +#define PWC_LVD_FILTER_EN_REG (CM_PWC->PVDFCR) +#define PWC_LVD_FILTER_EN_BIT (PWC_PVDFCR_PVD1NFDIS) +#define PWC_LVD_STATUS_REG (CM_PWC->PVDDSR) + +#define PWC_LVD2_POS (4U) +#define PWC_LVD_BIT_OFFSET(x) ((uint8_t)((x) * PWC_LVD2_POS)) +#define PWC_LVD_EN_BIT_OFFSET(x) (x) + +#define PWC_PRAM_MASK (PWC_RAM_PD_SRAM1 | PWC_RAM_PD_SDIO0 | \ + PWC_RAM_PD_SRAM2 | PWC_RAM_PD_SDIO1 | \ + PWC_RAM_PD_SRAM3 | PWC_RAM_PD_CAN | \ + PWC_RAM_PD_SRAMH | PWC_RAM_PD_CACHE | \ + PWC_RAM_PD_USBFS) + +#define PWC_LVD_FLAG_MASK (PWC_LVD1_FLAG_MON | PWC_LVD1_FLAG_DETECT | \ + PWC_LVD2_FLAG_MON | PWC_LVD2_FLAG_DETECT) + +#define PWC_LVD_EXP_NMI_POS (8U) + +/** + * @defgroup PWC_Check_Parameters_Validity PWC Check Parameters Validity + * @{ + */ +/* Check CLK register lock status. */ +#define IS_PWC_CLK_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB0) == PWC_FPRC_FPRCB0) + +/* Check PWC register lock status. */ +#define IS_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) +/* Check PWC LVD register lock status. */ +#define IS_PWC_LVD_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB3) == PWC_FPRC_FPRCB3) +/* Parameter validity check for EFM lock status. */ +#define IS_PWC_EFM_UNLOCKED() (CM_EFM->FAPRT == 0x00000001UL) + +#define IS_PWC_STOP_WKUP_SRC(x) \ +( ((x) == INT_SRC_USART1_WUPI) || \ + ((x) == INT_SRC_TMR0_1_CMP_A) || \ + ((x) == INT_SRC_RTC_ALM) || \ + ((x) == INT_SRC_RTC_PRD) || \ + ((x) == INT_SRC_WKTM_PRD) || \ + ((x) == INT_SRC_CMP1) || \ + ((x) == INT_SRC_LVD1) || \ + ((x) == INT_SRC_LVD2) || \ + ((x) == INT_SRC_SWDT_REFUDF) || \ + ((x) == INT_SRC_PORT_EIRQ0) || \ + ((x) == INT_SRC_PORT_EIRQ1) || \ + ((x) == INT_SRC_PORT_EIRQ2) || \ + ((x) == INT_SRC_PORT_EIRQ3) || \ + ((x) == INT_SRC_PORT_EIRQ4) || \ + ((x) == INT_SRC_PORT_EIRQ5) || \ + ((x) == INT_SRC_PORT_EIRQ6) || \ + ((x) == INT_SRC_PORT_EIRQ7) || \ + ((x) == INT_SRC_PORT_EIRQ8) || \ + ((x) == INT_SRC_PORT_EIRQ9) || \ + ((x) == INT_SRC_PORT_EIRQ10) || \ + ((x) == INT_SRC_PORT_EIRQ11) || \ + ((x) == INT_SRC_PORT_EIRQ12) || \ + ((x) == INT_SRC_PORT_EIRQ13) || \ + ((x) == INT_SRC_PORT_EIRQ14) || \ + ((x) == INT_SRC_PORT_EIRQ15)) + +/* Parameter validity check for peripheral RAM setting of power mode control */ +#define IS_PWC_PRAM_CONTROL(x) \ +( ((x) != 0x00UL) && \ + (((x) | PWC_PRAM_MASK) == PWC_PRAM_MASK)) + +/* Parameter validity check for RAM setting of MCU operating mode */ +#define IS_PWC_RAM_MD(x) \ +( ((x) == PWC_RAM_HIGH_SPEED) || \ + ((x) == PWC_RAM_ULOW_SPEED)) + +/* Parameter validity check for LVD channel. */ +#define IS_PWC_LVD_CH(x) \ +( ((x) == PWC_LVD_CH1) || \ + ((x) == PWC_LVD_CH2)) + +/* Parameter validity check for LVD function setting. */ +#define IS_PWC_LVD_EN(x) \ +( ((x) == PWC_LVD_ON) || \ + ((x) == PWC_LVD_OFF)) + +/* Parameter validity check for LVD compare output setting. */ +#define IS_PWC_LVD_CMP_EN(x) \ +( ((x) == PWC_LVD_CMP_ON) || \ + ((x) == PWC_LVD_CMP_OFF)) + +/* Parameter validity check for PWC LVD exception type. */ +#define IS_PWC_LVD_EXP_TYPE(x) \ +( ((x) == PWC_LVD_EXP_TYPE_NONE) || \ + ((x) == PWC_LVD_EXP_TYPE_INT) || \ + ((x) == PWC_LVD_EXP_TYPE_NMI) || \ + ((x) == PWC_LVD_EXP_TYPE_RST)) + +/* Parameter validity check for LVD digital noise filter function setting. */ +#define IS_PWC_LVD_FILTER_EN(x) \ +( ((x) == PWC_LVD_FILTER_ON) || \ + ((x) == PWC_LVD_FILTER_OFF)) + +/* Parameter validity check for LVD digital noise filter clock setting. */ +#define IS_PWC_LVD_FILTER_CLK(x) \ +( ((x) == PWC_LVD_FILTER_LRC_DIV1) || \ + ((x) == PWC_LVD_FILTER_LRC_DIV2) || \ + ((x) == PWC_LVD_FILTER_LRC_DIV4) || \ + ((x) == PWC_LVD_FILTER_LRC_MUL2)) + +/* Parameter validity check for LVD detect voltage setting. */ +#define IS_PWC_LVD_THRESHOLD_VOLTAGE(x) \ +( ((x) == PWC_LVD_THRESHOLD_LVL0) || \ + ((x) == PWC_LVD_THRESHOLD_LVL1) || \ + ((x) == PWC_LVD_THRESHOLD_LVL2) || \ + ((x) == PWC_LVD_THRESHOLD_LVL3) || \ + ((x) == PWC_LVD_THRESHOLD_LVL4) || \ + ((x) == PWC_LVD_THRESHOLD_LVL5) || \ + ((x) == PWC_LVD_THRESHOLD_LVL6) || \ + ((x) == PWC_LVD_THRESHOLD_LVL7)) + +/* Parameter validity check for LVD NMI function setting. */ +#define IS_PWC_LVD_NMI(x) \ +( ((x) == PWC_LVD_INT_MASK) || \ + ((x) == PWC_LVD_INT_NONMASK)) + +/* Parameter validity check for LVD trigger setting. */ +#define IS_PWC_LVD_TRIG_EDGE(x) \ +( ((x) == PWC_LVD_TRIG_FALLING) || \ + ((x) == PWC_LVD_TRIG_RISING) || \ + ((x) == PWC_LVD_TRIG_BOTH)) + +/* Parameter validity check for LVD trigger setting. */ +#define IS_PWC_LVD_CLR_FLAG(x) \ +( ((x) == PWC_LVD1_FLAG_DETECT) || \ + ((x) == PWC_LVD2_FLAG_DETECT)) + +/* Parameter validity check for LVD flag. */ +#define IS_PWC_LVD_GET_FLAG(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_LVD_FLAG_MASK) == PWC_LVD_FLAG_MASK)) + +/* Parameter validity check for power down mode wakeup event with trigger. */ +#define IS_PWC_WAKEUP_TRIG_EVT(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_PD_WKUP_TRIG_ALL) == PWC_PD_WKUP_TRIG_ALL)) + +/* Parameter validity check for power down mode wakeup trigger edge. */ +#define IS_PWC_WAKEUP_TRIG(x) \ +( ((x) == PWC_PD_WKUP_TRIG_FALLING) || \ + ((x) == PWC_PD_WKUP_TRIG_RISING)) + +/* Parameter validity check for wake up flag. */ +#define IS_PWC_WKUP_FLAG(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_PD_WKUP_FLAG_ALL) == PWC_PD_WKUP_FLAG_ALL)) + +/* Parameter validity check for stop mode drive capacity. */ +#define IS_PWC_STOP_DRV(drv) \ +( ((drv) == PWC_STOP_DRV_HIGH) || \ + ((drv) == PWC_STOP_DRV_LOW)) + +/* Parameter validity check for clock setting after wake-up from stop mode. */ +#define IS_PWC_STOP_CLK(x) \ +( ((x) == PWC_STOP_CLK_KEEP) || \ + ((x) == PWC_STOP_CLK_MRC)) + +/* Parameter validity check for flash wait setting after wake-up from stop mode. */ +#define IS_PWC_STOP_FLASH_WAIT(x) \ +( ((x)== PWC_STOP_FLASH_WAIT_ON) || \ + ((x)== PWC_STOP_FLASH_WAIT_OFF)) + +#define IS_PWC_LDO_SEL(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_LDO_MASK) == PWC_LDO_MASK)) + +/* Parameter validity check for WKT Clock Source. */ +#define IS_PWC_WKT_CLK_SRC(x) \ +( ((x)== PWC_WKT_CLK_SRC_64HZ) || \ + ((x)== PWC_WKT_CLK_SRC_XTAL32) || \ + ((x)== PWC_WKT_CLK_SRC_LRC)) + +/* Parameter validity check for WKT Comparision Value. */ +#define IS_PWC_WKT_COMPARISION_VALUE(x) ((x) <= 0x0FFFU) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup PWC_Local_Variables PWC Local Variables + * @{ + */ +static uint32_t NVIC_ISER_BAK[5]; +static uint8_t m_u8HrcState = 0U; +static uint8_t m_u8MrcState = 0U; +static uint8_t m_u8WkupIntCount = 0U; +static uint8_t m_u8StopFlag = 0U; +static uint8_t m_u8SysClockSrouce = 1U; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup PWC_Local_Functions PWC Local Functions + * @{ + */ + +/** + * @brief Select system clock source. + * @param u8SysSrc The system clock source. + * @retval None + * @note Must close all of the fcg register before switch system clock source. + ** This function only be called in func. PWC_ClockBackup and + ** PWC_ClockRecover. + ** If need to switch system clock please call CLK_SetSysClkSource. + */ +static void PWC_SetSysClk(uint8_t u8SysSrc) +{ + __IO uint32_t fcg0 = CM_PWC->FCG0; + __IO uint32_t fcg1 = CM_PWC->FCG1; + __IO uint32_t fcg2 = CM_PWC->FCG2; + __IO uint32_t fcg3 = CM_PWC->FCG3; + + DDL_ASSERT(IS_PWC_CLK_UNLOCKED()); + + /* Only current system clock source or target system clock source is MPLL + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if ((PWC_SYSCLK_SRC_PLL == (CM_CMU->CKSWR & CMU_CKSWR_CKSW)) || (PWC_SYSCLK_SRC_PLL == u8SysSrc)) { + /* Close fcg0~fcg3. */ + CM_PWC->FCG0 = 0xFFFFFAEEUL; + CM_PWC->FCG1 = 0xFFFFFFFFUL; + CM_PWC->FCG2 = 0xFFFFFFFFUL; + CM_PWC->FCG3 = 0xFFFFFFFFUL; + + DDL_DelayUS(1UL); + } + + WRITE_REG8(CM_CMU->CKSWR, u8SysSrc); + + /* update system clock frequency. */ + SystemCoreClockUpdate(); + + DDL_DelayUS(1UL); + + /* Open fcg0~fcg3. */ + CM_PWC->FCG0 = fcg0; + CM_PWC->FCG1 = fcg1; + CM_PWC->FCG2 = fcg2; + CM_PWC->FCG3 = fcg3; + + DDL_DelayUS(1UL); +} + +/** + * @brief Backup HRC/MRC state and system clock , enable HRC/MRC ,set MRC as + * system clock before enter stop mode. + * @param None + * @retval None + */ +static void PWC_ClockBackup(void) +{ + __IO uint32_t timeout = 0UL; + uint8_t u8State; + + DDL_ASSERT(IS_PWC_CLK_UNLOCKED()); + + /* HRC state backup. */ + m_u8HrcState = READ_REG8_BIT(CM_CMU->HRCCR, CMU_HRCCR_HRCSTP); + /* System clock backup*/ + m_u8SysClockSrouce = CM_CMU->CKSWR & CMU_CKSWR_CKSW; + + /* Enable HRC before enter stop mode. */ + if (0U != m_u8HrcState) { + CM_CMU->HRCCR = 0U; + do { + u8State = READ_REG8_BIT(CM_CMU->OSCSTBSR, CMU_OSCSTBSR_HRCSTBF); + timeout++; + } while ((timeout < 0x1000UL) && (u8State != CMU_OSCSTBSR_HRCSTBF)); + } + + /* When system clock source is HRC or MPLL, set MRC as system clock. . */ + if ((PWC_SYSCLK_SRC_HRC == m_u8SysClockSrouce) || (PWC_SYSCLK_SRC_PLL == m_u8SysClockSrouce)) { + if (0U == READ_REG8_BIT(CM_PWC->STPMCR, PWC_STPMCR_CKSMRC)) { + /* MRC state backup. */ + m_u8MrcState = READ_REG8_BIT(CM_CMU->MRCCR, CMU_MRCCR_MRCSTP); + if (0x80U != m_u8MrcState) { + CM_CMU->MRCCR = 0x80U; + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + } + } + PWC_SetSysClk(1U); + } +} + +/** + * @brief Recover HRC/MRC state and system clock after wakeup stop mode. + * @param None + * @retval None + */ +static void PWC_ClockRecover(void) +{ + DDL_ASSERT(IS_PWC_CLK_UNLOCKED()); + + if (0U == READ_REG8_BIT(CM_PWC->STPMCR, PWC_STPMCR_CKSMRC)) { + if ((PWC_SYSCLK_SRC_HRC == m_u8SysClockSrouce) || (PWC_SYSCLK_SRC_PLL == m_u8SysClockSrouce)) { + /* Recover MRC state & system clock source. */ + PWC_SetSysClk(m_u8SysClockSrouce); + MODIFY_REG8(CM_CMU->MRCCR, CMU_MRCCR_MRCSTP, m_u8MrcState); + } + /* Recover HRC state after wakeup stop mode. */ + WRITE_REG8(CM_CMU->HRCCR, m_u8HrcState); + } + /* Update system clock */ + SystemCoreClockUpdate(); +} +/** + * @} + */ + +/** + * @defgroup PWC_Global_Functions PWC Global Functions + * @{ + */ +/** + * @brief Enter power down mode. + * @param None + * @retval None + */ +__RAM_FUNC void PWC_PD_Enter(void) +{ + WRITE_REG16(CM_PWC->FPRC, PWC_UNLOCK_CODE1); + + CLR_REG8_BIT(CM_PWC->PVDCR1, PWC_PVDCR1_PVD1IRS | PWC_PVDCR1_PVD2IRS); + SET_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP); + + __disable_irq(); + SET_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN); + for (uint8_t i = 0U; i < 10U; i++) { + __NOP(); + } + __enable_irq(); + + __WFI(); +} + +/** + * @brief NVIC backup and disable before entry from stop mode + * @param None + * @retval None + */ +void PWC_STOP_NvicBackup(void) +{ + uint8_t u8Count; + __IO uint32_t *INTC_SELx; + uint32_t u32WakeupSrc; + + /* Backup NVIC set enable register for IRQ0~143*/ + for (u8Count = 0U; u8Count < sizeof(NVIC_ISER_BAK) / sizeof(uint32_t); u8Count++) { + NVIC_ISER_BAK[u8Count] = NVIC->ISER[u8Count]; + } + + /* Disable share vector */ + for (u8Count = 128U; u8Count < 144U; u8Count++) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + + for (u8Count = 0U; u8Count < 128U; u8Count++) { + INTC_SELx = (__IO uint32_t *)((uint32_t)(&CM_INTC->SEL0) + (4UL * u8Count)); + /* Disable NVIC if it is the wakeup-able source from stop mode */ + u32WakeupSrc = (uint32_t)(*INTC_SELx) & INTC_SEL_INTSEL; + if (IS_PWC_STOP_WKUP_SRC((en_int_src_t)u32WakeupSrc)) { + switch (u32WakeupSrc) { + case INT_SRC_USART1_WUPI: + if (0UL == bCM_INTC->WUPEN_b.RXWUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_TMR0_1_CMP_A: + if (0UL == bCM_INTC->WUPEN_b.TMR0WUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_RTC_ALM: + if (0UL == bCM_INTC->WUPEN_b.RTCALMWUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_RTC_PRD: + if (0UL == bCM_INTC->WUPEN_b.RTCPRDWUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_WKTM_PRD: + if (0UL == bCM_INTC->WUPEN_b.WKTMWUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_CMP1: + if (0UL == bCM_INTC->WUPEN_b.CMPI0WUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_LVD1: + if (0UL == bCM_INTC->WUPEN_b.PVD1WUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_LVD2: + if (0UL == bCM_INTC->WUPEN_b.PVD2WUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_SWDT_REFUDF: + if (0UL == bCM_INTC->WUPEN_b.SWDTWUEN) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ0: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN0) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ1: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN1) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ2: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN2) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ3: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN3) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ4: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN4) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ5: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN5) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ6: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN6) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ7: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN7) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ8: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN8) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ9: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN9) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ10: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN10) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ11: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN11) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ12: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN12) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ13: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN13) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ14: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN14) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + case INT_SRC_PORT_EIRQ15: + if (0UL == bCM_INTC->WUPEN_b.EIRQWUEN15) { + NVIC_DisableIRQ((IRQn_Type)u8Count); + } + break; + default: + break; + } + } else if ((uint32_t)INT_SRC_MAX != u32WakeupSrc) { + /* Disable NVIC for all none-wakeup source */ + NVIC_DisableIRQ((IRQn_Type)u8Count); + } else { + ; + } + } +} + +/** + * @brief NVIC recover after wakeup from stop mode + * @param None + * @retval None + */ +void PWC_STOP_NvicRecover(void) +{ + uint8_t u8Count; + + for (u8Count = 0U; u8Count < sizeof(NVIC_ISER_BAK) / sizeof(uint32_t); u8Count++) { + NVIC->ISER[u8Count] = NVIC_ISER_BAK[u8Count]; + } +} + +/** + * @brief Clock backup before enter stop mode and mark it. + * @param None + * @retval None + */ +void PWC_STOP_ClockBackup(void) +{ + /* Disable all interrupt to ensure the following operation continued. */ + __disable_irq(); + + /* HRC/MRC backup and switch system clock as MRC before entry from stop mode. */ + PWC_ClockBackup(); + + /* Mark the system clock has been switch as MRC, and will enter the stop mode. */ + m_u8StopFlag = 1U; + + /* Enable all interrupt. */ + __enable_irq(); +} + +/** + * @brief Clock recover after wakeup stop mode. + * @param None + * @retval None + */ +void PWC_STOP_ClockRecover(void) +{ + /* Disable all interrupt to ensure the following operation continued. */ + __disable_irq(); + + /* Mark the system clock will be switch as MRC, and has waked_up from stop mode. */ + m_u8StopFlag = 0U; + + /* Recover HRC/MRC state and system clock after wakeup stop mode. */ + PWC_ClockRecover(); + + /* Enable all interrupt. */ + __enable_irq(); +} + +/** + * @brief Clock backup before exit wakup interrupt. + * @param None + * @retval None + */ +void PWC_STOP_IrqClockBackup(void) +{ + if ((1UL == m_u8StopFlag) && (1UL == m_u8WkupIntCount)) { + /* HRC/MRC backup and switch system clock as MRC. */ + PWC_ClockBackup(); + } + m_u8WkupIntCount--; +} + +/** + * @brief Clock recover after enter wakeup interrupt. + * @param None + * @retval None + */ +void PWC_STOP_IrqClockRecover(void) +{ + /* The varibale to display how many waked_up interrupt has been occured + simultaneously and to decided whether backup clock before exit wake_up + interrupt. */ + m_u8WkupIntCount++; + + if (1UL == m_u8StopFlag) { + /* Recover HRC/MRC state and system clock. */ + PWC_ClockRecover(); + } +} + +/** + * @brief Enter stop mode. + * @param None + * @retval None + */ +void PWC_STOP_Enter(void) +{ + + DDL_ASSERT(IS_PWC_UNLOCKED()); + + /* NVIC backup and disable before entry from stop mode.*/ + PWC_STOP_NvicBackup(); + /* Clock backup and switch system clock as MRC before entry from stop mode. */ + PWC_STOP_ClockBackup(); + + SET_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP); + CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN); + + __WFI(); + + /* Recover HRC/MRC state and system clock after wakeup from stop mode. */ + PWC_STOP_ClockRecover(); + /* NVIC recover after wakeup from stop mode. */ + PWC_STOP_NvicRecover(); +} + +/** + * @brief Enter sleep mode. + * @param None + * @retval None + */ +void PWC_SLEEP_Enter(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + + CLR_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP); + CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN); + + __WFI(); +} + +/** + * @brief Configure ram run mode. + * @param [in] u16Mode Specifies the mode to run. + * @arg PWC_RAM_HIGH_SPEED + * @arg PWC_RAM_ULOW_SPEED + * @retval None + */ +void PWC_RamModeConfig(uint16_t u16Mode) +{ + DDL_ASSERT(IS_PWC_RAM_MD(u16Mode)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG16(CM_PWC->RAMOPM, u16Mode); +} + +/** + * @brief Initialize LVD config structure. Fill each pstcLvdInit with default value + * @param [in] pstcLvdInit Pointer to a stc_pwc_lvd_init_t structure that contains configuration information. + * @retval int32_t: + * - LL_OK: LVD structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_LVD_StructInit(stc_pwc_lvd_init_t *pstcLvdInit) +{ + int32_t i32Ret = LL_OK; + /* Check if pointer is NULL */ + if (NULL == pstcLvdInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* RESET LVD init structure parameters values */ + pstcLvdInit->u32State = PWC_LVD_OFF; + pstcLvdInit->u32CompareOutputState = PWC_LVD_CMP_OFF; + pstcLvdInit->u32ExceptionType = PWC_LVD_EXP_TYPE_NONE; + pstcLvdInit->u32Filter = PWC_LVD_FILTER_OFF; + pstcLvdInit->u32FilterClock = PWC_LVD_FILTER_LRC_MUL2; + pstcLvdInit->u32ThresholdVoltage = PWC_LVD_THRESHOLD_LVL0; + } + return i32Ret; +} + +/** + * @brief LVD configuration. + * @param [in] u8Ch LVD channel + * @arg PWC_LVD_CH1 + * @arg PWC_LVD_CH2 + * @param [in] pstcLvdInit Pointer to a stc_pwc_lvd_init_t structure that contains configuration information. + * @retval int32_t: + * - LL_OK: LVD initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_LVD_Init(uint8_t u8Ch, const stc_pwc_lvd_init_t *pstcLvdInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcLvdInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_EN(pstcLvdInit->u32State)); + DDL_ASSERT(IS_PWC_LVD_EXP_TYPE(pstcLvdInit->u32ExceptionType)); + DDL_ASSERT(IS_PWC_LVD_CMP_EN(pstcLvdInit->u32CompareOutputState)); + DDL_ASSERT(IS_PWC_LVD_FILTER_EN(pstcLvdInit->u32Filter)); + DDL_ASSERT(IS_PWC_LVD_FILTER_CLK(pstcLvdInit->u32FilterClock)); + DDL_ASSERT(IS_PWC_LVD_THRESHOLD_VOLTAGE(pstcLvdInit->u32ThresholdVoltage)); + + /* disable filter function in advance */ + SET_REG8_BIT(CM_PWC->PVDFCR, (PWC_PVDFCR_PVD1NFDIS << PWC_LVD_BIT_OFFSET(u8Ch))); + MODIFY_REG8(CM_PWC->PVDFCR, (PWC_PVDFCR_PVD1NFDIS | PWC_PVDFCR_PVD1NFCKS) << PWC_LVD_BIT_OFFSET(u8Ch), \ + (pstcLvdInit->u32Filter | pstcLvdInit->u32FilterClock) << PWC_LVD_BIT_OFFSET(u8Ch)); + /* Config LVD threshold voltage */ + MODIFY_REG8(CM_PWC->PVDLCR, PWC_PVDLCR_PVD1LVL << PWC_LVD_BIT_OFFSET(u8Ch), \ + pstcLvdInit->u32ThresholdVoltage << PWC_LVD_BIT_OFFSET(u8Ch)); + /* Enable LVD */ + MODIFY_REG8(CM_PWC->PVDCR0, PWC_PVDCR0_PVD1EN << u8Ch, pstcLvdInit->u32State << u8Ch); + /* Enable compare output */ + MODIFY_REG8(CM_PWC->PVDCR1, PWC_PVDCR1_PVD1CMPOE << PWC_LVD_BIT_OFFSET(u8Ch), \ + pstcLvdInit->u32CompareOutputState << PWC_LVD_BIT_OFFSET(u8Ch)); + /* config PVDIRE & PWC_PVDCR1_PVD1IRS while PVDEN & PVDCMPOE enable */ + MODIFY_REG8(CM_PWC->PVDCR1, (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS) << PWC_LVD_BIT_OFFSET(u8Ch), \ + (pstcLvdInit->u32ExceptionType & 0xFFU) << PWC_LVD_BIT_OFFSET(u8Ch)); + MODIFY_REG8(CM_PWC->PVDICR, PWC_PVDICR_PVD1NMIS << PWC_LVD_BIT_OFFSET(u8Ch), \ + ((pstcLvdInit->u32ExceptionType >> PWC_LVD_EXP_NMI_POS) & 0xFFU) << PWC_LVD_BIT_OFFSET(u8Ch)); + + } + return i32Ret; +} + +/** + * @brief Enable or disable LVD. + * @param [in] u8Ch Specifies whitch channel to operate. + * @arg PWC_LVD_CH1 + * @arg PWC_LVD_CH2 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LVD_Cmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG_BIT(PWC_LVD_EN_REG, PWC_LVD_EN_BIT << PWC_LVD_EN_BIT_OFFSET(u8Ch)); + } else { + CLR_REG_BIT(PWC_LVD_EN_REG, PWC_LVD_EN_BIT << PWC_LVD_EN_BIT_OFFSET(u8Ch)); + } +} + +/** + * @brief Enable or disable LVD external input. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note While enable external input, should choose PWC_LVD_CH2 to initialize, + * and threshold voltage must set PWC_LVD1_2V9_LVD2_1V1. + */ +void PWC_LVD_ExtInputCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG_BIT(PWC_LVD_EXT_INPUT_EN_REG, PWC_LVD_EXT_INPUT_EN_BIT); + } else { + CLR_REG_BIT(PWC_LVD_EXT_INPUT_EN_REG, PWC_LVD_EXT_INPUT_EN_BIT); + } +} + +/** + * @brief Enable or disable LVD compare output. + * @param [in] u8Ch Specifies whitch channel to operate. + * @arg PWC_LVD_CH1 + * @arg PWC_LVD_CH2 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LVD_CompareOutputCmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG_BIT(PWC_LVD_CMP_OUTPUT_EN_REG, PWC_LVD_CMP_OUTPUT_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } else { + CLR_REG_BIT(PWC_LVD_CMP_OUTPUT_EN_REG, PWC_LVD_CMP_OUTPUT_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } +} + +/** + * @brief Enable or disable LVD digital filter. + * @param [in] u8Ch Specifies whitch channel to operate. + * @arg PWC_LVD_CH1 + * @arg PWC_LVD_CH2 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LVD_DigitalFilterCmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG_BIT(PWC_LVD_FILTER_EN_REG, PWC_LVD_FILTER_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } else { + SET_REG_BIT(PWC_LVD_FILTER_EN_REG, PWC_LVD_FILTER_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } +} + +/** + * @brief Enable or disable LVD compare output. + * @param [in] u8Ch Specifies whitch channel to operate. + * @arg PWC_LVD_CH1 + * @arg PWC_LVD_CH2 + * @param [in] u32Clock Specifies filter clock. + * @arg PWC_LVD_FILTER_LRC_DIV4 + * @arg PWC_LVD_FILTER_LRC_DIV2 + * @arg PWC_LVD_FILTER_LRC_DIV1 + * @arg PWC_LVD_FILTER_LRC_MUL2 + * @retval None + */ +void PWC_LVD_SetFilterClock(uint8_t u8Ch, uint32_t u32Clock) +{ + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_FILTER_CLK(u32Clock)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + MODIFY_REG8(CM_PWC->PVDFCR, PWC_PVDFCR_PVD1NFCKS << PWC_LVD_BIT_OFFSET(u8Ch), \ + u32Clock << PWC_LVD_BIT_OFFSET(u8Ch)); +} + +/** + * @brief Enable or disable LVD compare output. + * @param [in] u8Ch Specifies whitch channel to operate. + * @arg PWC_LVD_CH1 + * @arg PWC_LVD_CH2 + * @param [in] u32Voltage Specifies threshold voltage. @ref PWC_LVD_Detection_Voltage_Sel + * @retval None + * @note While PWC_LVD_CH2, PWC_LVD1_2V9_LVD2_1V1 only valid while EXTINPUT enable. + */ +void PWC_LVD_SetThresholdVoltage(uint8_t u8Ch, uint32_t u32Voltage) +{ + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_THRESHOLD_VOLTAGE(u32Voltage)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PVDLCR, (PWC_PVDLCR_PVD1LVL << PWC_LVD_BIT_OFFSET(u8Ch)), \ + u32Voltage << PWC_LVD_BIT_OFFSET(u8Ch)); +} + +/** + * @brief Get LVD flag. + * @param [in] u8Flag LVD flag to be get @ref PWC_LVD_Flag + * @retval An @ref en_flag_status_t enumeration value + + * @note PVDxDETFLG is avaliable when PVDCR0.PVDxEN and PVDCR1.PVDxCMPOE are set to '1' + */ +en_flag_status_t PWC_LVD_GetStatus(uint8_t u8Flag) +{ + DDL_ASSERT(IS_PWC_LVD_GET_FLAG(u8Flag)); + return ((0x00U != READ_REG8_BIT(PWC_LVD_STATUS_REG, u8Flag)) ? SET : RESET); +} + +/** + * @brief Clear LVD flag. + * @param [in] u8Flag LVD flag to be get @ref PWC_LVD_Flag + * @arg PWC_LVD1_FLAG_DETECT + * @arg PWC_LVD2_FLAG_DETECT + * @retval None + * @note PWC_LVD2_FLAG_DETECT only valid while HC32F460, HC32M423, HC32F451, HC32F452 + * PWC_LVD1_FLAG_DETECT could clear both LVD1 & LVD2 flag while HC32F4A0 + */ +void PWC_LVD_ClearStatus(uint8_t u8Flag) +{ + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + DDL_ASSERT(IS_PWC_LVD_CLR_FLAG(u8Flag)); + + u8Flag = u8Flag >> PWC_PVDDSR_PVD1DETFLG_POS; + CLR_REG8_BIT(PWC_LVD_STATUS_REG, u8Flag); +} + +/** + * @brief LDO(HRC & PLL) command. + * @param [in] u16Ldo Specifies the ldo to command. + * @arg PWC_LDO_PLL + * @arg PWC_LDO_HRC + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LDO_Cmd(uint16_t u16Ldo, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LDO_SEL(u16Ldo)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG8_BIT(CM_PWC->PWRC1, u16Ldo); + } else { + SET_REG8_BIT(CM_PWC->PWRC1, u16Ldo); + } +} + +/** + * @brief Switch high speed to ultra low speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note Before calling this API, please switch system clock to the required + * low speed frequency in advance, and make sure NO any flash program + * or erase operation background. + */ +int32_t PWC_HighSpeedToLowSpeed(void) +{ + uint32_t u32To = PWC_MD_SWITCH_TIMEOUT2; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_EFM_UNLOCKED()); + + WRITE_REG32(bCM_EFM->FRMC_b.LVM, ENABLE); + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_ULOW_SPEED); + + while (PWC_RAM_ULOW_SPEED != READ_REG16(CM_PWC->RAMOPM)) { + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_ULOW_SPEED); + if (0UL == u32To--) { + return LL_ERR; + } + } + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (0UL == READ_REG32(bCM_EFM->FRMC_b.LVM)) { + WRITE_REG32(bCM_EFM->FRMC_b.LVM, ENABLE); + if (0UL == u32To--) { + return LL_ERR; + } + } + + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DDAS | PWC_PWRC2_DVS, PWC_PWRC2_DDAS_0 | PWC_PWRC2_DVS_1); + WRITE_REG8(CM_PWC->MDSWCR, PWC_MD_SWITCH_CMD); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + return LL_OK; +} + +/** + * @brief Switch ultra low speed to high speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note After calling this API, the system clock is able to switch high frequency. + */ +/** + * @brief Switch ultra low speed to high speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note After calling this API, the system clock is able to switch high frequency. + */ +int32_t PWC_LowSpeedToHighSpeed(void) +{ + uint32_t u32To = PWC_MD_SWITCH_TIMEOUT2; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_EFM_UNLOCKED()); + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DDAS | PWC_PWRC2_DVS, PWC_PWRC2_DDAS | PWC_PWRC2_DVS); + WRITE_REG8(CM_PWC->MDSWCR, PWC_MD_SWITCH_CMD); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + WRITE_REG32(bCM_EFM->FRMC_b.LVM, DISABLE); + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_HIGH_SPEED); + + while (PWC_RAM_HIGH_SPEED != READ_REG16(CM_PWC->RAMOPM)) { + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_HIGH_SPEED); + if (0UL == u32To--) { + return LL_ERR; + } + } + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (0UL != READ_REG32(bCM_EFM->FRMC_b.LVM)) { + WRITE_REG32(bCM_EFM->FRMC_b.LVM, DISABLE); + if (0UL == u32To--) { + return LL_ERR; + } + } + + return LL_OK; +} + +/** + * @brief Switch high speed to high performance, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note After calling this API, the system clock is able to switch high frequency.. + */ +int32_t PWC_HighSpeedToHighPerformance(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DDAS | PWC_PWRC2_DVS, PWC_PWRC2_DDAS); + WRITE_REG8(CM_PWC->MDSWCR, PWC_MD_SWITCH_CMD); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + return LL_OK; +} + +/** + * @brief Switch high performance to high speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note Before calling this API, please switch system clock to the required + * low speed frequency in advance, and make sure NO any flash program + * or erase operation background. + */ +int32_t PWC_HighPerformanceToHighSpeed(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DDAS | PWC_PWRC2_DVS, PWC_PWRC2_DDAS | PWC_PWRC2_DVS); + WRITE_REG8(CM_PWC->MDSWCR, PWC_MD_SWITCH_CMD); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + return LL_OK; +} + +/** + * @brief Switch low speed to high performance, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note After calling this API, the system clock is able to switch high frequency.. + */ +int32_t PWC_LowSpeedToHighPerformance(void) +{ + uint32_t u32To; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_EFM_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DDAS | PWC_PWRC2_DVS, PWC_PWRC2_DDAS); + WRITE_REG8(CM_PWC->MDSWCR, PWC_MD_SWITCH_CMD); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + WRITE_REG32(bCM_EFM->FRMC_b.LVM, DISABLE); + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_HIGH_SPEED); + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (PWC_RAM_HIGH_SPEED != READ_REG16(CM_PWC->RAMOPM)) { + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_HIGH_SPEED); + if (0UL == u32To--) { + return LL_ERR; + } + } + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (0UL != READ_REG32(bCM_EFM->FRMC_b.LVM)) { + WRITE_REG32(bCM_EFM->FRMC_b.LVM, DISABLE); + if (0UL == u32To--) { + return LL_ERR; + } + } + + return LL_OK; +} + +/** + * @brief Switch high performance to low speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note Before calling this API, please switch system clock to the required + * low speed frequency in advance, and make sure NO any flash program + * or erase operation background.. + */ +int32_t PWC_HighPerformanceToLowSpeed(void) +{ + uint32_t u32To; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_EFM_UNLOCKED()); + + WRITE_REG32(bCM_EFM->FRMC_b.LVM, ENABLE); + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_ULOW_SPEED); + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (PWC_RAM_ULOW_SPEED != READ_REG16(CM_PWC->RAMOPM)) { + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_ULOW_SPEED); + if (0UL == u32To--) { + return LL_ERR; + } + } + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (0UL == READ_REG32(bCM_EFM->FRMC_b.LVM)) { + WRITE_REG32(bCM_EFM->FRMC_b.LVM, ENABLE); + if (0UL == u32To--) { + return LL_ERR; + } + } + + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DDAS | PWC_PWRC2_DVS, PWC_PWRC2_DDAS_0 | PWC_PWRC2_DVS_0); + WRITE_REG8(CM_PWC->MDSWCR, PWC_MD_SWITCH_CMD); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + return LL_OK; +} + +/** + * @brief VDR area power down commond. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power down mode + * @arg DISABLE: Run mode + * @retval None + */ +void PWC_PD_VdrCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_VVDRSD); + } else { + CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_VVDRSD); + } +} + +/** + * @brief Ram area power down commond. + * @param [in] u32PeriphRam Specifies whitch ram to operate. @ref PWC_PD_Periph_Ram + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power down mode + * @arg DISABLE: Run mode + * @retval None + */ +void PWC_PD_PeriphRamCmd(uint32_t u32PeriphRam, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_PRAM_CONTROL(u32PeriphRam)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CM_PWC->RAMPC0 |= u32PeriphRam; + } else { + CM_PWC->RAMPC0 &= ~u32PeriphRam; + } +} + +/** + * @brief Initialize Power down mode config structure. Fill each pstcPDModeConfig with default value + * @param [in] pstcPDModeConfig Pointer to a stc_pwc_pd_mode_config_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Power down mode structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_PD_StructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPDModeConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcPDModeConfig->u8IOState = PWC_PD_IO_KEEP1; + pstcPDModeConfig->u8Mode = PWC_PD_MD1; + pstcPDModeConfig->u8VcapCtrl = PWC_PD_VCAP_0P1UF; + } + return i32Ret; +} + +/** + * @brief Power down mode config structure. + * @param [in] pstcPDModeConfig Pointer to a stc_pwc_pd_mode_config_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Power down mode config successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_PD_Config(const stc_pwc_pd_mode_config_t *pstcPDModeConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPDModeConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC0, (PWC_PWRC0_IORTN | PWC_PWRC0_PDMDS), \ + (pstcPDModeConfig->u8IOState | pstcPDModeConfig->u8Mode)); + MODIFY_REG8(CM_PWC->PWRC3, PWC_PWRC3_PDTS, pstcPDModeConfig->u8VcapCtrl << PWC_PWRC3_PDTS_POS); + } + return i32Ret; +} + +/** + * @brief Power down mode wake up event config. + * @param [in] u32Event Wakeup Event. @ref PWC_WKUP_Event_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_PD_WakeupCmd(uint32_t u32Event, en_functional_state_t enNewState) +{ + uint8_t u8Event0 = (uint8_t)u32Event; + uint8_t u8Event1 = (uint8_t)(u32Event >> PWC_PD_WKUP1_POS); + uint8_t u8Event2 = (uint8_t)(u32Event >> PWC_PD_WKUP2_POS); + if (ENABLE == enNewState) { + SET_REG8_BIT(CM_PWC->PDWKE0, u8Event0); + SET_REG8_BIT(CM_PWC->PDWKE1, u8Event1); + SET_REG8_BIT(CM_PWC->PDWKE2, u8Event2); + } else { + CLR_REG8_BIT(CM_PWC->PDWKE0, u8Event0); + CLR_REG8_BIT(CM_PWC->PDWKE1, u8Event1); + CLR_REG8_BIT(CM_PWC->PDWKE2, u8Event2); + } +} + +/** + * @brief Power down mode wake up event trigger config. + * @param [in] u8Event PVD and wakeup pin. @ref PWC_WKUP_Trigger_Event_Sel + * @param [in] u8TrigEdge The trigger edge. + * @arg PWC_PD_WKUP_TRIG_FALLING + * @arg PWC_PD_WKUP_TRIG_RISING + * @retval None + */ +void PWC_PD_SetWakeupTriggerEdge(uint8_t u8Event, uint8_t u8TrigEdge) +{ + DDL_ASSERT(IS_PWC_WAKEUP_TRIG_EVT(u8Event)); + DDL_ASSERT(IS_PWC_WAKEUP_TRIG(u8TrigEdge)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (PWC_PD_WKUP_TRIG_RISING == u8TrigEdge) { + SET_REG8_BIT(CM_PWC->PDWKES, u8Event); + } else { + CLR_REG8_BIT(CM_PWC->PDWKES, u8Event); + } +} + +/** + * @brief Get wake up event flag. + * @param [in] u16Flag Wake up event. @ref PWC_WKUP_Event_Flag_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t PWC_PD_GetWakeupStatus(uint16_t u16Flag) +{ + uint8_t u8Flag0; + uint8_t u8Flag1; + + DDL_ASSERT(IS_PWC_WKUP_FLAG(u16Flag)); + + u8Flag0 = READ_REG8_BIT(CM_PWC->PDWKF0, u16Flag); + u8Flag1 = READ_REG8_BIT(CM_PWC->PDWKF1, (u16Flag >> PWC_PD_WKUP_FLAG1_POS)); + + return (((0U != u8Flag0) || (0U != u8Flag1)) ? SET : RESET); +} + +/** + * @brief Get wake up event flag. + * @param [in] u16Flag Wake up event. @ref PWC_WKUP_Event_Flag_Sel + * @retval None + */ +void PWC_PD_ClearWakeupStatus(uint16_t u16Flag) +{ + uint8_t u8Flag0; + uint8_t u8Flag1; + + DDL_ASSERT(IS_PWC_WKUP_FLAG(u16Flag)); + + u8Flag0 = (uint8_t)u16Flag; + u8Flag1 = (uint8_t)(u16Flag >> PWC_PD_WKUP_FLAG1_POS); + + CLR_REG8_BIT(CM_PWC->PDWKF0, u8Flag0); + CLR_REG8_BIT(CM_PWC->PDWKF1, u8Flag1); +} + +/** + * @brief Stop mode config. + * @param [in] pstcStopConfig Chip config before entry stop mode. + * @arg u8StopDrv, MCU from which speed mode entry stop mode. + * @arg u16Clock, System clock setting after wake-up from stop mode. + * @arg u16FlashWait, Whether wait flash stable after wake-up from stop mode. + * @arg u16ExBusHold, ExBus status in stop mode. + * @retval int32_t: + * - LL_OK: Stop mode config successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_STOP_Config(const stc_pwc_stop_mode_config_t *pstcStopConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcStopConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_PWC_STOP_CLK(pstcStopConfig->u16Clock)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + DDL_ASSERT(IS_PWC_STOP_DRV(pstcStopConfig->u8StopDrv)); + MODIFY_REG8(CM_PWC->PWRC1, PWC_PWRC1_STPDAS, pstcStopConfig->u8StopDrv); + DDL_ASSERT(IS_PWC_STOP_FLASH_WAIT(pstcStopConfig->u16FlashWait)); + + MODIFY_REG16(CM_PWC->STPMCR, (PWC_STPMCR_CKSMRC | PWC_STPMCR_FLNWT), \ + (pstcStopConfig->u16Clock | pstcStopConfig->u16FlashWait)); + } + return i32Ret; +} + +/** + * @brief Initialize stop mode config structure. Fill each pstcStopConfig with default value + * @param [in] pstcStopConfig Pointer to a stc_pwc_stop_mode_config_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Stop down mode structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_STOP_StructInit(stc_pwc_stop_mode_config_t *pstcStopConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcStopConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcStopConfig->u16Clock = PWC_STOP_CLK_KEEP; + pstcStopConfig->u8StopDrv = PWC_STOP_DRV_HIGH; + pstcStopConfig->u16FlashWait = PWC_STOP_FLASH_WAIT_ON; + } + return i32Ret; +} + +/** + * @brief Stop mode wake up clock config. + * @param [in] u8Clock System clock setting after wake-up from stop mode. + * @arg PWC_STOP_CLK_KEEP + * @arg PWC_STOP_CLK_MRC or PWC_STOP_CLK_HRC + * @retval None + * @note PWC_STOP_CLK_HRC only valid while HC32F160. + */ +void PWC_STOP_ClockSelect(uint8_t u8Clock) +{ + DDL_ASSERT(IS_PWC_STOP_CLK(u8Clock)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG16(CM_PWC->STPMCR, PWC_STPMCR_CKSMRC, (uint16_t)u8Clock); + +} + +/** + * @brief Stop mode wake up flash wait config. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_STOP_FlashWaitCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + MODIFY_REG8(CM_PWC->STPMCR, PWC_STPMCR_FLNWT, PWC_STOP_FLASH_WAIT_ON); + } else { + MODIFY_REG8(CM_PWC->STPMCR, PWC_STPMCR_FLNWT, PWC_STOP_FLASH_WAIT_OFF); + } +} + +/** + * @brief Stop mode driver capacity config. + * @param [in] u8StopDrv Drive capacity while enter stop mode. + * @arg PWC_STOP_DRV_HIGH + * @arg PWC_STOP_DRV_LOW + * @retval None + */ +void PWC_STOP_SetDrv(uint8_t u8StopDrv) +{ + DDL_ASSERT(IS_PWC_STOP_DRV(u8StopDrv)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC1, PWC_PWRC1_STPDAS, u8StopDrv); +} + +/** + * @brief PWC power monitor command. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note This monitor power is used for ADC and output to REGC pin. + */ +void PWC_PowerMonitorCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + if (ENABLE == enNewState) { + SET_REG8_BIT(CM_PWC->PWCMR, PWC_PWCMR_ADBUFE); + } else { + CLR_REG8_BIT(CM_PWC->PWCMR, PWC_PWCMR_ADBUFE); + } + +} + +/** + * @brief WKT Timer Initialize. + * @param [in] u16ClkSrc Clock source. + * This parameter can be one of the following values: + * @arg PWC_WKT_CLK_SRC_64HZ: 64Hz Clock + * @arg PWC_WKT_CLK_SRC_XTAL32: XTAL32 Clock + * @arg PWC_WKT_CLK_SRC_RTCLRC: RTCLRC Clock + * @param [in] u16CmpVal Comparison value of the Counter. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0xFFF. + * @retval None + */ +void PWC_WKT_Config(uint16_t u16ClkSrc, uint16_t u16CmpVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_PWC_WKT_CLK_SRC(u16ClkSrc)); + DDL_ASSERT(IS_PWC_WKT_COMPARISION_VALUE(u16CmpVal)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG16(CM_PWC->WKTCR, (uint16_t)(u16ClkSrc | (u16CmpVal & PWC_WKTCR_WKTMCMP))); +} + +/** + * @brief SET WKT Timer compare value. + * @param [in] u16CmpVal Comparison value of the Counter. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0xFFF. + * @retval None + */ +void PWC_WKT_SetCompareValue(uint16_t u16CmpVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_PWC_WKT_COMPARISION_VALUE(u16CmpVal)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + MODIFY_REG16(CM_PWC->WKTCR, PWC_WKTCR_WKTMCMP, u16CmpVal); +} + +/** + * @brief Get WKT Timer compare value. + * @param None + * @retval uint16_t WKT Compara value + */ +uint16_t PWC_WKT_GetCompareValue(void) +{ + uint16_t u16CmpVal; + + u16CmpVal = READ_REG16_BIT(CM_PWC->WKTCR, PWC_WKTCR_WKTMCMP); + + return u16CmpVal; +} + +/** + * @brief ENABLE or DISABLE WKT Timer. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_WKT_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + MODIFY_REG16(CM_PWC->WKTCR, PWC_WKTCR_WKTCE, PWC_WKT_ON); + } else { + MODIFY_REG16(CM_PWC->WKTCR, PWC_WKTCR_WKTCE, PWC_WKT_OFF); + } + +} + +/** + * @brief Get WKT Timer count match flag. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. enumeration value: + + */ +en_flag_status_t PWC_WKT_GetStatus(void) +{ + en_flag_status_t enFlagState; + + enFlagState = (0U != READ_REG16_BIT(CM_PWC->WKTCR, PWC_WKTCR_WKOVF)) ? SET : RESET; + + return enFlagState; +} + +/** + * @brief Clear WKT Timer count match flag. + * @param None + * @retval None + */ +void PWC_WKT_ClearStatus(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + CLR_REG16_BIT(CM_PWC->WKTCR, PWC_WKTCR_WKOVF); +} + +/** + * @brief ENABLE or DISABLE XTAL32 power. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power on + * @arg DISABLE: Power off + * @retval None + */ +void PWC_XTAL32_PowerCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG8_BIT(CM_PWC->XTAL32CS, PWC_XTAL32CS_CSDIS); + } else { + SET_REG_BIT(CM_PWC->XTAL32CS, PWC_XTAL32CS_CSDIS); + } +} + +/** + * @brief Ret_Sram area power commond. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power on + * @arg DISABLE: Power off + * @retval None + */ +void PWC_RetSram_PowerCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_RETRAMSD); + } else { + SET_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_RETRAMSD); + } +} + +/** + * @} + */ + +#endif /* LL_PWC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_qspi.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_qspi.c new file mode 100644 index 0000000000..8d0cdb8fb2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_qspi.c @@ -0,0 +1,471 @@ +/** + ******************************************************************************* + * @file hc32_ll_qspi.c + * @brief This file provides firmware functions to manage the QSPI. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_qspi.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_QSPI QSPI + * @brief QSPI Driver Library + * @{ + */ + +#if (LL_QSPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup QSPI_Local_Macros QSPI Local Macros + * @{ + */ + +/* QSPI registers Mask */ +#define QSPI_CR_CLR_MASK (QSPI_CR_DIV | QSPI_CR_SPIMD3 | QSPI_CR_PFSAE | \ + QSPI_CR_PFE | QSPI_CR_MDSEL) +#define QSPI_FCR_CLR_MASK (QSPI_FCR_DUTY | QSPI_FCR_DMCYCN | QSPI_FCR_SSNLD | \ + QSPI_FCR_SSNHD | QSPI_FCR_FOUR_BIC | QSPI_FCR_AWSL) +#define QSPI_CUSTOM_MD_CLR_MASK (QSPI_CR_IPRSL | QSPI_CR_APRSL | QSPI_CR_DPRSL) + +/** + * @defgroup QSPI_Check_Parameters_Validity QSPI check parameters validity + * @{ + */ + +#define IS_QSPI_CLK_DIV(x) \ +( ((x) != 0U) && \ + (((x) | QSPI_CLK_DIV64) == QSPI_CLK_DIV64)) + +#define IS_QSPI_SPI_MD(x) \ +( ((x) == QSPI_SPI_MD0) || \ + ((x) == QSPI_SPI_MD3)) + +#define IS_QSPI_PREFETCH_MD(x) \ +( ((x) == QSPI_PREFETCH_MD_INVD) || \ + ((x) == QSPI_PREFETCH_MD_EDGE_STOP) || \ + ((x) == QSPI_PREFETCH_MD_IMMED_STOP)) + +#define IS_QSPI_READ_MD(x) \ +( ((x) == QSPI_RD_MD_STD_RD) || \ + ((x) == QSPI_RD_MD_FAST_RD) || \ + ((x) == QSPI_RD_MD_DUAL_OUTPUT_FAST_RD) || \ + ((x) == QSPI_RD_MD_DUAL_IO_FAST_RD) || \ + ((x) == QSPI_RD_MD_QUAD_OUTPUT_FAST_RD) || \ + ((x) == QSPI_RD_MD_QUAD_IO_FAST_RD) || \ + ((x) == QSPI_RD_MD_CUSTOM_STANDARD_RD) || \ + ((x) == QSPI_RD_MD_CUSTOM_FAST_RD)) + +#define IS_QSPI_DUMMY_CYCLE(x) (((x) | QSPI_DUMMY_CYCLE18) == QSPI_DUMMY_CYCLE18) + +#define IS_QSPI_ADDR_WIDTH(x) \ +( ((x) == QSPI_ADDR_WIDTH_8BIT) || \ + ((x) == QSPI_ADDR_WIDTH_16BIT) || \ + ((x) == QSPI_ADDR_WIDTH_24BIT) || \ + ((x) == QSPI_ADDR_WIDTH_32BIT_INSTR_24BIT) || \ + ((x) == QSPI_ADDR_WIDTH_32BIT_INSTR_32BIT)) + +#define IS_QSPI_QSSN_SETUP_TIME(x) \ +( ((x) == QSPI_QSSN_SETUP_ADVANCE_QSCK0P5) || \ + ((x) == QSPI_QSSN_SETUP_ADVANCE_QSCK1P5)) + +#define IS_QSPI_QSSN_RELEASE_TIME(x) \ +( ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK0P5) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK1P5) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK32) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK128) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_INFINITE)) + +#define IS_QSPI_QSSN_INTERVAL_TIME(x) ((x) <= QSPI_QSSN_INTERVAL_QSCK16) + +#define IS_QSPI_INSTR_PROTOCOL(x) \ +( ((x) == QSPI_INSTR_PROTOCOL_1LINE) || \ + ((x) == QSPI_INSTR_PROTOCOL_2LINE) || \ + ((x) == QSPI_INSTR_PROTOCOL_4LINE)) + +#define IS_QSPI_ADDR_PROTOCOL(x) \ +( ((x) == QSPI_ADDR_PROTOCOL_1LINE) || \ + ((x) == QSPI_ADDR_PROTOCOL_2LINE) || \ + ((x) == QSPI_ADDR_PROTOCOL_4LINE)) + +#define IS_QSPI_DATA_PROTOCOL(x) \ +( ((x) == QSPI_DATA_PROTOCOL_1LINE) || \ + ((x) == QSPI_DATA_PROTOCOL_2LINE) || \ + ((x) == QSPI_DATA_PROTOCOL_4LINE)) + +#define IS_QSPI_WP_PIN_LVL(x) \ +( ((x) == QSPI_WP_PIN_LOW) || \ + ((x) == QSPI_WP_PIN_HIGH)) + +#define IS_QSPI_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | QSPI_FLAG_ALL) == QSPI_FLAG_ALL)) + +#define IS_QSPI_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | QSPI_FLAG_CLR_ALL) == QSPI_FLAG_CLR_ALL)) + +#define IS_QSPI_BLOCK_SIZE(x) ((x) <= (QSPI_EXAR_EXADR >> QSPI_EXAR_EXADR_POS)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup QSPI_Local_Variable QSPI Local Variable + * @{ + */ + +/* Current read mode */ +static uint8_t m_u8ReadMode = 0U; + +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Functions QSPI Global Functions + * @{ + */ + +/** + * @brief De-initializes QSPI. + * @param None + * @retval None + */ +void QSPI_DeInit(void) +{ + WRITE_REG32(CM_QSPI->CR, 0x003F0000UL); + WRITE_REG32(CM_QSPI->CSCR, 0x0FUL); + WRITE_REG32(CM_QSPI->FCR, 0x80B3UL); + WRITE_REG32(CM_QSPI->CCMD, 0x0UL); + WRITE_REG32(CM_QSPI->XCMD, 0xFFUL); + WRITE_REG32(CM_QSPI->SR2, QSPI_FLAG_ROM_ACCESS_ERR); + WRITE_REG32(CM_QSPI->EXAR, 0UL); +} + +/** + * @brief Initialize QSPI. + * @param [in] pstcQspiInit Pointer to a @ref stc_qspi_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t QSPI_Init(const stc_qspi_init_t *pstcQspiInit) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Duty = 0UL; + + if (NULL == pstcQspiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_QSPI_CLK_DIV(pstcQspiInit->u32ClockDiv)); + DDL_ASSERT(IS_QSPI_SPI_MD(pstcQspiInit->u32SpiMode)); + DDL_ASSERT(IS_QSPI_PREFETCH_MD(pstcQspiInit->u32PrefetchMode)); + DDL_ASSERT(IS_QSPI_READ_MD(pstcQspiInit->u32ReadMode)); + DDL_ASSERT(IS_QSPI_DUMMY_CYCLE(pstcQspiInit->u32DummyCycle)); + DDL_ASSERT(IS_QSPI_ADDR_WIDTH(pstcQspiInit->u32AddrWidth)); + DDL_ASSERT(IS_QSPI_QSSN_SETUP_TIME(pstcQspiInit->u32SetupTime)); + DDL_ASSERT(IS_QSPI_QSSN_RELEASE_TIME(pstcQspiInit->u32ReleaseTime)); + DDL_ASSERT(IS_QSPI_QSSN_INTERVAL_TIME(pstcQspiInit->u32IntervalTime)); + + /* Duty cycle compensation */ + if (0UL == (pstcQspiInit->u32ClockDiv & QSPI_CLK_DIV2)) { + u32Duty = QSPI_FCR_DUTY; + } + MODIFY_REG32(CM_QSPI->CR, QSPI_CR_CLR_MASK, (pstcQspiInit->u32ClockDiv | pstcQspiInit->u32SpiMode | + pstcQspiInit->u32PrefetchMode | pstcQspiInit->u32ReadMode)); + WRITE_REG32(CM_QSPI->CSCR, ((pstcQspiInit->u32ReleaseTime >> 8U) | pstcQspiInit->u32IntervalTime)); + MODIFY_REG32(CM_QSPI->FCR, QSPI_FCR_CLR_MASK, (pstcQspiInit->u32DummyCycle | pstcQspiInit->u32AddrWidth | + pstcQspiInit->u32SetupTime | (pstcQspiInit->u32ReleaseTime & 0xFFU) | u32Duty)); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_qspi_init_t member with default value. + * @param [out] pstcQspiInit Pointer to a @ref stc_qspi_init_t structure + * @retval int32_t: + * - LL_OK: stc_qspi_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t QSPI_StructInit(stc_qspi_init_t *pstcQspiInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcQspiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcQspiInit->u32ClockDiv = QSPI_CLK_DIV2; + pstcQspiInit->u32SpiMode = QSPI_SPI_MD0; + pstcQspiInit->u32PrefetchMode = QSPI_PREFETCH_MD_INVD; + pstcQspiInit->u32ReadMode = QSPI_RD_MD_STD_RD; + pstcQspiInit->u32DummyCycle = QSPI_DUMMY_CYCLE3; + pstcQspiInit->u32AddrWidth = QSPI_ADDR_WIDTH_24BIT; + pstcQspiInit->u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5; + pstcQspiInit->u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK0P5; + pstcQspiInit->u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1; + } + + return i32Ret; +} + +/** + * @brief Set the level of WP pin. + * @param [in] u32Level The level value. + * This parameter can be one of the following values: + * @arg QSPI_WP_PIN_LOW: WP(QSIO2) pin output low + * @arg QSPI_WP_PIN_HIGH: WP(QSIO2) pin output high + * @retval None + */ +void QSPI_SetWpPinLevel(uint32_t u32Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_WP_PIN_LVL(u32Level)); + + MODIFY_REG32(CM_QSPI->FCR, QSPI_FCR_WPOL, u32Level); +} + +/** + * @brief Set the prefetch mode. + * @param [in] u32Mode The prefetch mode. + * This parameter can be one of the following values: + * @arg QSPI_PREFETCH_MD_INVD: Disable prefetch + * @arg QSPI_PREFETCH_MD_EDGE_STOP: Stop prefetch at the edge of byte + * @arg QSPI_PREFETCH_MD_IMMED_STOP: Stop prefetch at current position immediately + * @retval None + */ +void QSPI_SetPrefetchMode(uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_PREFETCH_MD(u32Mode)); + + MODIFY_REG32(CM_QSPI->CR, (QSPI_CR_PFE | QSPI_CR_PFSAE), u32Mode); +} + +/** + * @brief Selects the block to access. + * @param [in] u8Block Memory block number (range is 0 to 63) + * @retval None + */ +void QSPI_SelectMemoryBlock(uint8_t u8Block) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_BLOCK_SIZE(u8Block)); + + WRITE_REG32(CM_QSPI->EXAR, ((uint32_t)u8Block << QSPI_EXAR_EXADR_POS)); +} + +/** + * @brief Set the read mode. + * @param [in] u32Mode Read mode. + * This parameter can be one of the following values: + * @arg QSPI_RD_MD_STD_RD: Standard read mode (no dummy cycles) + * @arg QSPI_RD_MD_FAST_RD: Fast read mode (dummy cycles between address and data) + * @arg QSPI_RD_MD_DUAL_OUTPUT_FAST_RD: Fast read dual output mode (data on 2 lines) + * @arg QSPI_RD_MD_DUAL_IO_FAST_RD: Fast read dual I/O mode (address and data on 2 lines) + * @arg QSPI_RD_MD_QUAD_OUTPUT_FAST_RD: Fast read quad output mode (data on 4 lines) + * @arg QSPI_RD_MD_QUAD_IO_FAST_RD: Fast read quad I/O mode (address and data on 4 lines) + * @arg QSPI_RD_MD_CUSTOM_STANDARD_RD: Custom standard read mode + * @arg QSPI_RD_MD_CUSTOM_FAST_RD: Custom fast read mode + * @retval None + */ +void QSPI_SetReadMode(uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_READ_MD(u32Mode)); + + MODIFY_REG32(CM_QSPI->CR, QSPI_CR_MDSEL, u32Mode); +} + +/** + * @brief Configure the custom read. + * @param [in] pstcCustomMode Pointer to a @ref stc_qspi_custom_mode_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t QSPI_CustomReadConfig(const stc_qspi_custom_mode_t *pstcCustomMode) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcCustomMode) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_QSPI_INSTR_PROTOCOL(pstcCustomMode->u32InstrProtocol)); + DDL_ASSERT(IS_QSPI_ADDR_PROTOCOL(pstcCustomMode->u32AddrProtocol)); + DDL_ASSERT(IS_QSPI_DATA_PROTOCOL(pstcCustomMode->u32DataProtocol)); + + MODIFY_REG32(CM_QSPI->CR, QSPI_CUSTOM_MD_CLR_MASK, (pstcCustomMode->u32InstrProtocol | + pstcCustomMode->u32AddrProtocol | pstcCustomMode->u32DataProtocol)); + WRITE_REG32(CM_QSPI->CCMD, pstcCustomMode->u8InstrCode); + } + + return i32Ret; +} + +/** + * @brief Enable or disable XIP mode. + * @param [in] u8ModeCode Enter or exit XIP mode code + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void QSPI_XipModeCmd(uint8_t u8ModeCode, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(CM_QSPI->XCMD, u8ModeCode); + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_XIPE); + } else { + CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_XIPE); + } +} + +/** + * @brief Enter direct communication mode. + * @param None + * @retval None + */ +void QSPI_EnterDirectCommMode(void) +{ + /* Backup the read mode */ + m_u8ReadMode = (uint8_t)READ_REG32_BIT(CM_QSPI->CR, QSPI_CR_MDSEL); + /* Set standard read mode */ + CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_MDSEL); + /* Enter direct communication mode */ + SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); +} + +/** + * @brief Exit direct communication mode. + * @param None + * @retval None + */ +void QSPI_ExitDirectCommMode(void) +{ + /* Exit direct communication mode */ + CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); + /* Recovery the read mode */ + SET_REG32_BIT(CM_QSPI->CR, m_u8ReadMode); +} + +/** + * @brief Get the size of prefetched buffer. + * @param None + * @retval uint8_t Prefetched buffer size. + */ +uint8_t QSPI_GetPrefetchBufSize(void) +{ + return (uint8_t)(READ_REG32_BIT(CM_QSPI->SR, QSPI_SR_PFNUM) >> QSPI_SR_PFNUM_POS); +} + +/** + * @brief Get QSPI flag. + * @param [in] u32Flag QSPI flag type + * This parameter can be one or any combination of the following values: + * @arg QSPI_FLAG_DIRECT_COMM_BUSY: Serial transfer being processed + * @arg QSPI_FLAG_XIP_MD: XIP mode + * @arg QSPI_FLAG_ROM_ACCESS_ERR: ROM access detection status in direct communication mode + * @arg QSPI_FLAG_PREFETCH_BUF_FULL: Prefetch buffer is full + * @arg QSPI_FLAG_PREFETCH_STOP: Prefetch function operating + * @arg QSPI_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t QSPI_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_QSPI_FLAG(u32Flag)); + + if (0UL != READ_REG32_BIT(CM_QSPI->SR, u32Flag)) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear QSPI flag. + * @param [in] u32Flag QSPI flag type + * This parameter can be one or any combination of the following values: + * @arg QSPI_FLAG_ROM_ACCESS_ERR: ROM access detection status in direct communication mode + * @arg QSPI_FLAG_CLR_ALL: All of the above + * @retval None + */ +void QSPI_ClearStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_CLR_FLAG(u32Flag)); + + SET_REG32_BIT(CM_QSPI->SR2, u32Flag); +} + +/** + * @} + */ + +#endif /* LL_QSPI_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_rmu.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_rmu.c new file mode 100644 index 0000000000..3672b81a35 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_rmu.c @@ -0,0 +1,137 @@ +/** + ******************************************************************************* + * @file hc32_ll_rmu.c + * @brief This file provides firmware functions to manage the Reset Manage Unit + * (RMU). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_rmu.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_RMU RMU + * @brief RMU Driver Library + * @{ + */ + +#if (LL_RMU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RMU_Local_Macros RMU Local Macros + * @{ + */ + +/** + * @defgroup RMU_Check_Parameters_Validity RMU Check Parameters Validity + * @{ + */ + +/*! Parameter validity check for RMU reset cause. */ +#define IS_VALID_RMU_RST_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | RMU_FLAG_ALL) == RMU_FLAG_ALL)) + +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup RMU_Global_Functions RMU Global Functions + * @{ + */ + +/** + * @brief Get the reset cause. + * @param [in] u32RmuResetCause Reset flags that need to be queried, @ref RMU_ResetCause in details + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause) +{ + en_flag_status_t enStatus; + DDL_ASSERT(IS_VALID_RMU_RST_FLAG(u32RmuResetCause)); + + enStatus = ((0UL == READ_REG32_BIT(CM_RMU->RSTF0, u32RmuResetCause)) ? RESET : SET); + return enStatus; +} + +/** + * @brief Clear reset Status. + * @param None + * @retval NOne + * @note Clear reset flag should be done after read RMU_RSTF0 register. + * Call PWC_Unlock(PWC_UNLOCK_CODE_1) unlock RMU_RSTF0 register first. + */ +void RMU_ClearStatus(void) +{ + SET_REG_BIT(CM_RMU->RSTF0, RMU_RSTF0_CLRF); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); +} + +/** + * @} + */ + +#endif /* LL_RMU_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_rtc.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_rtc.c new file mode 100644 index 0000000000..ed9c3bf003 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_rtc.c @@ -0,0 +1,936 @@ +/** + ******************************************************************************* + * @file hc32_ll_rtc.c + * @brief This file provides firmware functions to manage the Real-Time + * Clock(RTC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_rtc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_RTC RTC + * @brief Real-Time Clock Driver Library + * @{ + */ + +#if (LL_RTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RTC_Local_Macros RTC Local Macros + * @{ + */ + +/* RTC software reset timeout(ms) */ +#define RTC_SW_RST_TIMEOUT (100UL) +/* RTC mode switch timeout(ms) */ +#define RTC_MD_SWITCH_TIMEOUT (100UL) + +/** + * @defgroup RTC_Check_Parameters_Validity RTC Check Parameters Validity + * @{ + */ +#define IS_RTC_DATA_FMT(x) \ +( ((x) == RTC_DATA_FMT_DEC) || \ + ((x) == RTC_DATA_FMT_BCD)) + +#define IS_RTC_CLK_SRC(x) \ +( ((x) == RTC_CLK_SRC_XTAL32) || \ + ((x) == RTC_CLK_SRC_LRC)) + +#define IS_RTC_HOUR_FMT(x) \ +( ((x) == RTC_HOUR_FMT_12H) || \ + ((x) == RTC_HOUR_FMT_24H)) + +#define IS_RTC_INT_PERIOD(x) \ +( ((x) == RTC_INT_PERIOD_INVD) || \ + ((x) == RTC_INT_PERIOD_PER_HALF_SEC) || \ + ((x) == RTC_INT_PERIOD_PER_SEC) || \ + ((x) == RTC_INT_PERIOD_PER_MINUTE) || \ + ((x) == RTC_INT_PERIOD_PER_HOUR) || \ + ((x) == RTC_INT_PERIOD_PER_DAY) || \ + ((x) == RTC_INT_PERIOD_PER_MONTH)) + +#define IS_RTC_CLK_COMPEN(x) \ +( ((x) == RTC_CLK_COMPEN_DISABLE) || \ + ((x) == RTC_CLK_COMPEN_ENABLE)) + +#define IS_RTC_CLK_COMPEN_MD(x) \ +( ((x) == RTC_CLK_COMPEN_MD_DISTRIBUTED) || \ + ((x) == RTC_CLK_COMPEN_MD_UNIFORM)) + +#define IS_RTC_HOUR_12H_AM_PM(x) \ +( ((x) == RTC_HOUR_12H_AM) || \ + ((x) == RTC_HOUR_12H_PM)) + +#define IS_RTC_GET_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | RTC_FLAG_ALL) == RTC_FLAG_ALL)) + +#define IS_RTC_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | RTC_FLAG_CLR_ALL) == RTC_FLAG_CLR_ALL)) + +#define IS_RTC_INT(x) \ +( ((x) != 0U) && \ + (((x) | RTC_INT_ALL) == RTC_INT_ALL)) + +#define IS_RTC_YEAR(x) ((x) <= 99U) + +#define IS_RTC_MONTH(x) (((x) >= 1U) && ((x) <= 12U)) + +#define IS_RTC_DAY(x) (((x) >= 1U) && ((x) <= 31U)) + +#define IS_RTC_HOUR_12H(x) (((x) >= 1U) && ((x) <= 12U)) + +#define IS_RTC_HOUR_24H(x) ((x) <= 23U) + +#define IS_RTC_MINUTE(x) ((x) <= 59U) + +#define IS_RTC_SEC(x) ((x) <= 59U) + +#define IS_RTC_WEEKDAY(x) ((x) <= 6U) + +#define IS_RTC_ALARM_WEEKDAY(x) (((x) >= 0x01U) && ((x) <= 0x7FU)) + +#define IS_RTC_COMPEN_VALUE(x) ((x) <= 0x1FFU) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Functions RTC Global Functions + * @{ + */ + +/** + * @brief De-Initialize RTC. + * @param None + * @retval int32_t: + * - LL_OK: De-Initialize success + * - LL_ERR_TIMEOUT: De-Initialize timeout + */ +int32_t RTC_DeInit(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + WRITE_REG32(bCM_RTC->CR0_b.RESET, RESET); + /* Waiting for normal count status or end of RTC software reset */ + u32Count = RTC_SW_RST_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR0_b.RESET)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + if (LL_OK == i32Ret) { + /* Reset all RTC registers */ + WRITE_REG32(bCM_RTC->CR0_b.RESET, SET); + /* Waiting for RTC software reset to complete */ + u32Count = RTC_SW_RST_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR0_b.RESET)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + + return i32Ret; +} + +/** + * @brief Initialize RTC. + * @param [in] pstcRtcInit Pointer to a @ref stc_rtc_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_Init(const stc_rtc_init_t *pstcRtcInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_CLK_SRC(pstcRtcInit->u8ClockSrc)); + DDL_ASSERT(IS_RTC_HOUR_FMT(pstcRtcInit->u8HourFormat)); + DDL_ASSERT(IS_RTC_INT_PERIOD(pstcRtcInit->u8IntPeriod)); + DDL_ASSERT(IS_RTC_CLK_COMPEN(pstcRtcInit->u8ClockCompen)); + DDL_ASSERT(IS_RTC_COMPEN_VALUE(pstcRtcInit->u16CompenValue)); + DDL_ASSERT(IS_RTC_CLK_COMPEN_MD(pstcRtcInit->u8CompenMode)); + + /* RTC CR3 Configuration */ + MODIFY_REG8(CM_RTC->CR3, (RTC_CR3_LRCEN | RTC_CR3_RCKSEL), pstcRtcInit->u8ClockSrc); + /* RTC CR1 Configuration */ + MODIFY_REG8(CM_RTC->CR1, (RTC_CR1_PRDS | RTC_CR1_AMPM | RTC_CR1_ONEHZSEL), + (pstcRtcInit->u8IntPeriod | pstcRtcInit->u8HourFormat | pstcRtcInit->u8CompenMode)); + /* RTC Compensation Configuration */ + MODIFY_REG8(CM_RTC->ERRCRH, (RTC_ERRCRH_COMPEN | RTC_ERRCRH_COMP8), + (pstcRtcInit->u8ClockCompen | (uint8_t)((pstcRtcInit->u16CompenValue >> 8U) & 0x01U))); + WRITE_REG8(CM_RTC->ERRCRL, (uint8_t)(pstcRtcInit->u16CompenValue & 0xFFU)); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_rtc_init_t member with default value. + * @param [out] pstcRtcInit Pointer to a @ref stc_rtc_init_t structure + * @retval int32_t: + * - LL_OK: stc_rtc_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcRtcInit->u8ClockSrc = RTC_CLK_SRC_LRC; + pstcRtcInit->u8HourFormat = RTC_HOUR_FMT_24H; + pstcRtcInit->u8IntPeriod = RTC_INT_PERIOD_INVD; + pstcRtcInit->u8ClockCompen = RTC_CLK_COMPEN_DISABLE; + pstcRtcInit->u8CompenMode = RTC_CLK_COMPEN_MD_DISTRIBUTED; + pstcRtcInit->u16CompenValue = 0U; + } + + return i32Ret; +} + +/** + * @brief Enter RTC read/write mode. + * @param None + * @retval int32_t: + * - LL_OK: Enter mode success + * - LL_ERR_TIMEOUT: Enter mode timeout + */ +int32_t RTC_EnterRwMode(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Mode switch when RTC is running */ + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + if (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, SET); + /* Waiting for RWEN bit set */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Exit RTC read/write mode. + * @param None + * @retval int32_t: + * - LL_OK: Exit mode success + * - LL_ERR_TIMEOUT: Exit mode timeout + */ +int32_t RTC_ExitRwMode(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Mode switch when RTC is running */ + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + if (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, RESET); + /* Waiting for RWEN bit reset */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Confirm the condition for RTC to enter low power mode. + * @param None + * @retval int32_t: + * - LL_OK: Can enter low power mode + * - LL_ERR_TIMEOUT: Can't enter low power mode + */ +int32_t RTC_ConfirmLPMCond(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Check RTC work status */ + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, SET); + /* Waiting for RTC RWEN bit set */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + if (LL_OK == i32Ret) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, RESET); + /* Waiting for RTC RWEN bit reset */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Set the RTC interrupt period. + * @param [in] u8Period Specifies the interrupt period. + * This parameter can be one of the following values: + * @arg RTC_INT_PERIOD_INVD: Period interrupt invalid + * @arg RTC_INT_PERIOD_PER_HALF_SEC: Interrupt per half second + * @arg RTC_INT_PERIOD_PER_SEC: Interrupt per second + * @arg RTC_INT_PERIOD_PER_MINUTE: Interrupt per minute + * @arg RTC_INT_PERIOD_PER_HOUR: Interrupt per hour + * @arg RTC_INT_PERIOD_PER_DAY: Interrupt per day + * @arg RTC_INT_PERIOD_PER_MONTH: Interrupt per month + * @retval None + */ +void RTC_SetIntPeriod(uint8_t u8Period) +{ + uint32_t u32RtcSta; + uint32_t u32IntSta; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_INT_PERIOD(u8Period)); + + u32RtcSta = READ_REG32(bCM_RTC->CR1_b.START); + u32IntSta = READ_REG32(bCM_RTC->CR2_b.PRDIE); + /* Disable period interrupt when START=1 and clear period flag after write */ + if ((0UL != u32IntSta) && (0UL != u32RtcSta)) { + WRITE_REG32(bCM_RTC->CR2_b.PRDIE, RESET); + } + + /* RTC CR1 Configuration */ + MODIFY_REG8(CM_RTC->CR1, RTC_CR1_PRDS, u8Period); + + if ((0UL != u32IntSta) && (0UL != u32RtcSta)) { + WRITE_REG32(bCM_RTC->CR2_b.PRDIE, SET); + } +} + +/** + * @brief Set the RTC clock source. + * @param [in] u8Src Specifies the clock source. + * This parameter can be one of the following values: + * @arg RTC_CLK_SRC_XTAL32: XTAL32 Cloc + * @arg RTC_CLK_SRC_LRC: LRC/RTCLRC Clock + * @retval None + */ +void RTC_SetClockSrc(uint8_t u8Src) +{ + /* Check parameters */ + DDL_ASSERT(IS_RTC_CLK_SRC(u8Src)); + + MODIFY_REG8(CM_RTC->CR3, (RTC_CR3_LRCEN | RTC_CR3_RCKSEL), u8Src); +} + +/** + * @brief Set RTC clock compensation value. + * @param [in] u16Value Specifies the clock compensation value of RTC. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF. + * @retval None + */ +void RTC_SetClockCompenValue(uint16_t u16Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_RTC_COMPEN_VALUE(u16Value)); + + WRITE_REG32(bCM_RTC->ERRCRH_b.COMP8, ((uint32_t)u16Value >> 8U) & 0x01U); + WRITE_REG8(CM_RTC->ERRCRL, (uint8_t)(u16Value & 0x00FFU)); +} + +/** + * @brief Get RTC counter status. + * @param None + * @retval An @ref en_functional_state_t enumeration value. + * - ENABLE: RTC counter started + * - DISABLE: RTC counter stopped + */ +en_functional_state_t RTC_GetCounterState(void) +{ + en_functional_state_t enState = DISABLE; + + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + enState = ENABLE; + } + + return enState; +} + +/** + * @brief Enable or disable RTC count. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR1_b.START, enNewState); +} + +/** + * @brief Enable or disable RTC LRC function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_LrcCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR3_b.LRCEN, enNewState); +} + +/** + * @brief Enable or disable RTC 1HZ output. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_OneHzOutputCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR1_b.ONEHZOE, enNewState); +} + +/** + * @brief Enable or disable clock compensation. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_ClockCompenCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->ERRCRH_b.COMPEN, enNewState); +} + +/** + * @brief Set RTC current date. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [in] pstcRtcDate Pointer to a @ref stc_rtc_date_t structure + * @retval int32_t: + * - LL_OK: Set date success + * - LL_ERR: Set date failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcDate) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + if (RTC_DATA_FMT_DEC != u8Format) { + DDL_ASSERT(IS_RTC_YEAR(RTC_BCD2DEC(pstcRtcDate->u8Year))); + DDL_ASSERT(IS_RTC_MONTH(RTC_BCD2DEC(pstcRtcDate->u8Month))); + DDL_ASSERT(IS_RTC_DAY(RTC_BCD2DEC(pstcRtcDate->u8Day))); + } else { + DDL_ASSERT(IS_RTC_YEAR(pstcRtcDate->u8Year)); + DDL_ASSERT(IS_RTC_MONTH(pstcRtcDate->u8Month)); + DDL_ASSERT(IS_RTC_DAY(pstcRtcDate->u8Day)); + } + DDL_ASSERT(IS_RTC_WEEKDAY(pstcRtcDate->u8Weekday)); + + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcDate->u8Year = RTC_DEC2BCD(pstcRtcDate->u8Year); + pstcRtcDate->u8Month = RTC_DEC2BCD(pstcRtcDate->u8Month); + pstcRtcDate->u8Day = RTC_DEC2BCD(pstcRtcDate->u8Day); + } + + WRITE_REG8(CM_RTC->YEAR, pstcRtcDate->u8Year); + WRITE_REG8(CM_RTC->MON, pstcRtcDate->u8Month); + WRITE_REG8(CM_RTC->DAY, pstcRtcDate->u8Day); + WRITE_REG8(CM_RTC->WEEK, pstcRtcDate->u8Weekday); + + /* Exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Get RTC current date. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [out] pstcRtcDate Pointer to a @ref stc_rtc_date_t structure + * @retval int32_t: + * - LL_OK: Get date success + * - LL_ERR: Get date failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcDate) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + /* Get RTC date registers */ + pstcRtcDate->u8Year = READ_REG8(CM_RTC->YEAR); + pstcRtcDate->u8Month = READ_REG8(CM_RTC->MON); + pstcRtcDate->u8Day = READ_REG8(CM_RTC->DAY); + pstcRtcDate->u8Weekday = READ_REG8(CM_RTC->WEEK); + + /* Check decimal format*/ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcDate->u8Year = RTC_BCD2DEC(pstcRtcDate->u8Year); + pstcRtcDate->u8Month = RTC_BCD2DEC(pstcRtcDate->u8Month); + pstcRtcDate->u8Day = RTC_BCD2DEC(pstcRtcDate->u8Day); + } + + /* exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Set RTC current time. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [in] pstcRtcTime Pointer to a @ref stc_rtc_time_t structure + * @retval int32_t: + * - LL_OK: Set time success + * - LL_ERR: Set time failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcTime) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + if (RTC_DATA_FMT_DEC != u8Format) { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(RTC_BCD2DEC(pstcRtcTime->u8Hour))); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcTime->u8AmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(RTC_BCD2DEC(pstcRtcTime->u8Hour))); + } + DDL_ASSERT(IS_RTC_MINUTE(RTC_BCD2DEC(pstcRtcTime->u8Minute))); + DDL_ASSERT(IS_RTC_SEC(RTC_BCD2DEC(pstcRtcTime->u8Second))); + } else { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(pstcRtcTime->u8Hour)); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcTime->u8AmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(pstcRtcTime->u8Hour)); + } + DDL_ASSERT(IS_RTC_MINUTE(pstcRtcTime->u8Minute)); + DDL_ASSERT(IS_RTC_SEC(pstcRtcTime->u8Second)); + } + + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcTime->u8Hour = RTC_DEC2BCD(pstcRtcTime->u8Hour); + pstcRtcTime->u8Minute = RTC_DEC2BCD(pstcRtcTime->u8Minute); + pstcRtcTime->u8Second = RTC_DEC2BCD(pstcRtcTime->u8Second); + } + if ((RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) && + (RTC_HOUR_12H_PM == pstcRtcTime->u8AmPm)) { + SET_REG8_BIT(pstcRtcTime->u8Hour, RTC_HOUR_12H_PM); + } + + WRITE_REG8(CM_RTC->HOUR, pstcRtcTime->u8Hour); + WRITE_REG8(CM_RTC->MIN, pstcRtcTime->u8Minute); + WRITE_REG8(CM_RTC->SEC, pstcRtcTime->u8Second); + + /* Exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Get RTC current time. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [out] pstcRtcTime Pointer to a @ref stc_rtc_time_t structure + * @retval int32_t: + * - LL_OK: Get time success + * - LL_ERR: Get time failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcTime) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + /* Get RTC time registers */ + pstcRtcTime->u8Hour = READ_REG8(CM_RTC->HOUR); + pstcRtcTime->u8Minute = READ_REG8(CM_RTC->MIN); + pstcRtcTime->u8Second = READ_REG8(CM_RTC->SEC); + + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + if (RTC_HOUR_12H_PM == (pstcRtcTime->u8Hour & RTC_HOUR_12H_PM)) { + CLR_REG8_BIT(pstcRtcTime->u8Hour, RTC_HOUR_12H_PM); + pstcRtcTime->u8AmPm = RTC_HOUR_12H_PM; + } else { + pstcRtcTime->u8AmPm = RTC_HOUR_12H_AM; + } + } else { + pstcRtcTime->u8AmPm = RTC_HOUR_24H; + } + + /* Check decimal format*/ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcTime->u8Hour = RTC_BCD2DEC(pstcRtcTime->u8Hour); + pstcRtcTime->u8Minute = RTC_BCD2DEC(pstcRtcTime->u8Minute); + pstcRtcTime->u8Second = RTC_BCD2DEC(pstcRtcTime->u8Second); + } + + /* exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Set RTC alarm time. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [in] pstcRtcAlarm Pointer to a @ref stc_rtc_alarm_t structure + * @retval int32_t: + * - LL_OK: Set RTC alarm time success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcAlarm) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + if (RTC_DATA_FMT_DEC != u8Format) { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour))); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcAlarm->u8AlarmAmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour))); + } + DDL_ASSERT(IS_RTC_MINUTE(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmMinute))); + } else { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(pstcRtcAlarm->u8AlarmHour)); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcAlarm->u8AlarmAmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(pstcRtcAlarm->u8AlarmHour)); + } + DDL_ASSERT(IS_RTC_MINUTE(pstcRtcAlarm->u8AlarmMinute)); + } + DDL_ASSERT(IS_RTC_ALARM_WEEKDAY(pstcRtcAlarm->u8AlarmWeekday)); + + /* Configure alarm registers */ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcAlarm->u8AlarmHour = RTC_DEC2BCD(pstcRtcAlarm->u8AlarmHour); + pstcRtcAlarm->u8AlarmMinute = RTC_DEC2BCD(pstcRtcAlarm->u8AlarmMinute); + } + if ((RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) && + (RTC_HOUR_12H_PM == pstcRtcAlarm->u8AlarmAmPm)) { + SET_REG8_BIT(pstcRtcAlarm->u8AlarmHour, RTC_HOUR_12H_PM); + } + + WRITE_REG8(CM_RTC->ALMHOUR, pstcRtcAlarm->u8AlarmHour); + WRITE_REG8(CM_RTC->ALMMIN, pstcRtcAlarm->u8AlarmMinute); + WRITE_REG8(CM_RTC->ALMWEEK, pstcRtcAlarm->u8AlarmWeekday); + } + + return i32Ret; +} + +/** + * @brief Get RTC alarm time. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [out] pstcRtcAlarm Pointer to a @ref stc_rtc_alarm_t structure + * @retval int32_t: + * - LL_OK: Get RTC alarm time success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcAlarm) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + + /* Get RTC date and time register */ + pstcRtcAlarm->u8AlarmWeekday = READ_REG8(CM_RTC->ALMWEEK); + pstcRtcAlarm->u8AlarmMinute = READ_REG8(CM_RTC->ALMMIN); + pstcRtcAlarm->u8AlarmHour = READ_REG8(CM_RTC->ALMHOUR); + + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + if (RTC_HOUR_12H_PM == (pstcRtcAlarm->u8AlarmHour & RTC_HOUR_12H_PM)) { + CLR_REG8_BIT(pstcRtcAlarm->u8AlarmHour, RTC_HOUR_12H_PM); + pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_12H_PM; + } else { + pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_12H_AM; + } + } else { + pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_24H; + } + + /* Check decimal format*/ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcAlarm->u8AlarmHour = RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour); + pstcRtcAlarm->u8AlarmMinute = RTC_BCD2DEC(pstcRtcAlarm->u8AlarmMinute); + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable RTC alarm. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_AlarmCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR2_b.ALME, enNewState); +} + +/** + * @brief Enable or disable specified RTC interrupt. + * @param [in] u32IntType Specifies the RTC interrupt source. + * This parameter can be one or any combination of the following values: + * @arg @ref RTC_Interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32IntTemp; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32IntTemp = u32IntType & 0x0000FFUL; + if (0UL != u32IntTemp) { + if (DISABLE != enNewState) { + SET_REG8_BIT(CM_RTC->CR2, u32IntTemp); + } else { + CLR_REG8_BIT(CM_RTC->CR2, u32IntTemp); + } + } + +} + +/** + * @brief Get RTC flag status. + * @param [in] u32Flag Specifies the RTC flag type. + * This parameter can be one or any combination of the following values: + * @arg @ref RTC_Flag + * @arg RTC_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t RTC_GetStatus(uint32_t u32Flag) +{ + uint8_t u8FlagTemp; + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_GET_FLAG(u32Flag)); + + u8FlagTemp = (uint8_t)(u32Flag & 0xFFU); + if (0U != u8FlagTemp) { + if (0U != (READ_REG8_BIT(CM_RTC->CR2, u8FlagTemp))) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Clear RTC flag. + * @param [in] u32Flag Specifies the RTC flag type. + * This parameter can be one or any combination of the following values: + * @arg @ref RTC_Flag + * @arg RTC_FLAG_CLR_ALL: All of the above + * @retval None + */ +void RTC_ClearStatus(uint32_t u32Flag) +{ + uint8_t u8FlagTemp; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_CLR_FLAG(u32Flag)); + + u8FlagTemp = (uint8_t)(u32Flag & 0xFFU); + if (0U != u8FlagTemp) { + CLR_REG8_BIT(CM_RTC->CR1, RTC_CR1_ALMFCLR); + } + +} + +/** + * @} + */ + +#endif /* LL_RTC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_sdioc.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_sdioc.c new file mode 100644 index 0000000000..2505afe08e --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_sdioc.c @@ -0,0 +1,2676 @@ +/** + ******************************************************************************* + * @file hc32_ll_sdioc.c + * @brief This file provides firmware functions to manage the Secure Digital + * Input and Output Controller(SDIOC). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_sdioc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SDIOC SDIOC + * @brief SDIOC Driver Library + * @{ + */ + +#if (LL_SDIOC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SDIOC_Local_Macros SDIOC Local Macros + * @{ + */ + +/* Masks for R6 Response */ +#define SDMMC_R6_GEN_UNKNOWN_ERR (0x00002000UL) +#define SDMMC_R6_ILLEGAL_CMD (0x00004000UL) +#define SDMMC_R6_COM_CRC_FAIL (0x00008000UL) + +/* SDMMC command parameters */ +#define SDMMC_CMD8_CHECK_PATTERN (0x000001AAUL) +/* 3.2V-3.3V */ +#define SDMMC_ACMD41_VOLT_WIN (0x80100000UL) + +/* Command send and response timeout(ms) */ +#define SDMMC_CMD_TIMEOUT (5000UL) +/* Max erase Timeout 60s */ +#define SDMMC_MAX_ERASE_TIMEOUT (60000UL) +/* SDIOC software reset timeout(ms) */ +#define SDIOC_SW_RST_TIMEOUT (50UL) + +/* SDIOC NORINTSGEN register Mask */ +#define SDIOC_NORINTSGEN_CLR_MASK (0x01F7U) +/* SDIOC ERRINTSGEN register Mask */ +#define SDIOC_ERRINTSGEN_CLR_MASK (0x017FU) + +/*!< Get the specified register address of the specified SDIOC unit */ +#define SDIOC_ARG_ADDR(__UNIT__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->ARG0))) +#define SDIOC_BUF_ADDR(__UNIT__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->BUF0))) +#define SDIOC_RESP_ADDR(__UNIT__, __RESP__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->RESP0)) + (__RESP__)) + +/** + * @defgroup SDIOC_Check_Parameters_Validity SDIOC Check Parameters Validity + * @{ + */ +#define IS_SDIOC_UNIT(x) \ +( ((x) == CM_SDIOC1) || \ + ((x) == CM_SDIOC2)) + +#define IS_SDIOC_MD(x) \ +( ((x) == SDIOC_MD_SD) || \ + ((x) == SDIOC_MD_MMC)) + +#define IS_SDIOC_CARD_DETECT_WAY(x) \ +( ((x) == SDIOC_CARD_DETECT_CD_PIN_LVL) || \ + ((x) == SDIOC_CARD_DETECT_TEST_SIGNAL)) + +#define IS_SDIOC_CARD_DETECT_TEST_LEVEL(x) \ +( ((x) == SDIOC_CARD_DETECT_TEST_LVL_LOW) || \ + ((x) == SDIOC_CARD_DETECT_TEST_LVL_HIGH)) + +#define IS_SDIOC_SPEED_MD(x) \ +( ((x) == SDIOC_SPEED_MD_NORMAL) || \ + ((x) == SDIOC_SPEED_MD_HIGH)) + +#define IS_SDIOC_BUS_WIDTH(x) \ +( ((x) == SDIOC_BUS_WIDTH_1BIT) || \ + ((x) == SDIOC_BUS_WIDTH_4BIT) || \ + ((x) == SDIOC_BUS_WIDTH_8BIT)) + +#define IS_SDIOC_CLK_DIV(x) \ +( ((x) == SDIOC_CLK_DIV1) || \ + ((x) == SDIOC_CLK_DIV2) || \ + ((x) == SDIOC_CLK_DIV4) || \ + ((x) == SDIOC_CLK_DIV8) || \ + ((x) == SDIOC_CLK_DIV16) || \ + ((x) == SDIOC_CLK_DIV32) || \ + ((x) == SDIOC_CLK_DIV64) || \ + ((x) == SDIOC_CLK_DIV128) || \ + ((x) == SDIOC_CLK_DIV256)) + +#define IS_SDIOC_CMD_TYPE(x) \ +( ((x) == SDIOC_CMD_TYPE_NORMAL) || \ + ((x) == SDIOC_CMD_TYPE_SUSPEND) || \ + ((x) == SDIOC_CMD_TYPE_RESUME) || \ + ((x) == SDIOC_CMD_TYPE_ABORT)) + +#define IS_SDIOC_DATA_LINE(x) \ +( ((x) == SDIOC_DATA_LINE_DISABLE) || \ + ((x) == SDIOC_DATA_LINE_ENABLE)) + +#define IS_SDIOC_TRANS_DIR(x) \ +( ((x) == SDIOC_TRANS_DIR_TO_CARD) || \ + ((x) == SDIOC_TRANS_DIR_TO_HOST)) + +#define IS_SDIOC_AUTO_SEND_CMD12(x) \ +( ((x) == SDIOC_AUTO_SEND_CMD12_DISABLE) || \ + ((x) == SDIOC_AUTO_SEND_CMD12_ENABLE)) + +#define IS_SDIOC_TRANS_MD(x) \ +( ((x) == SDIOC_TRANS_MD_SINGLE) || \ + ((x) == SDIOC_TRANS_MD_INFINITE) || \ + ((x) == SDIOC_TRANS_MD_MULTI) || \ + ((x) == SDIOC_TRANS_MD_STOP_MULTI)) + +#define IS_SDIOC_DATA_TIMEOUT_TIME(x) ((x) <= SDIOC_DATA_TIMEOUT_CLK_2E27) + +#define IS_SDIOC_RESP_REG(x) \ +( ((x) == SDIOC_RESP_REG_BIT0_31) || \ + ((x) == SDIOC_RESP_REG_BIT32_63) || \ + ((x) == SDIOC_RESP_REG_BIT64_95) || \ + ((x) == SDIOC_RESP_REG_BIT96_127)) + +#define IS_SDIOC_SW_RST_TYPE(x) \ +( ((x) == SDIOC_SW_RST_DATA_LINE) || \ + ((x) == SDIOC_SW_RST_CMD_LINE) || \ + ((x) == SDIOC_SW_RST_ALL)) + +#define IS_SDIOC_OUTPUT_CLK_FREQ(x) \ +( ((x) == SDIOC_OUTPUT_CLK_FREQ_400K) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_25M) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_26M) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_50M) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_52M)) + +#define IS_SDIOC_GET_HOST_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_HOST_FLAG_ALL) == SDIOC_HOST_FLAG_ALL)) + +#define IS_SDIOC_GET_INT_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_INT_FLAG_ALL) == SDIOC_INT_FLAG_ALL)) + +#define IS_SDIOC_CLR_INT_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_INT_FLAG_CLR_ALL) == SDIOC_INT_FLAG_CLR_ALL)) + +#define IS_SDIOC_INT(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_INT_ALL) == SDIOC_INT_ALL)) + +#define IS_SDIOC_AUTO_CMD_ERR_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_AUTO_CMD_ERR_FLAG_ALL) == SDIOC_AUTO_CMD_ERR_FLAG_ALL)) + +#define IS_SDIOC_FORCE_AUTO_CMD_ERR(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_FORCE_AUTO_CMD_ERR_ALL) == SDIOC_FORCE_AUTO_CMD_ERR_ALL)) + +#define IS_SDIOC_FORCE_ERR_INT(x) \ +( ((x) != 0UL) && \ + (((x) | SDIOC_FORCE_ERR_INT_ALL) == SDIOC_FORCE_ERR_INT_ALL)) + +#define IS_SDIOC_RESP_TYPE(x) \ +( ((x) == SDIOC_RESP_TYPE_NO) || \ + ((x) == SDIOC_RESP_TYPE_R2) || \ + ((x) == SDIOC_RESP_TYPE_R3_R4) || \ + ((x) == SDIOC_RESP_TYPE_R1_R5_R6_R7) || \ + ((x) == SDIOC_RESP_TYPE_R1B_R5B)) + +#define IS_SDIOC_CMD_INDEX(x) ((x) < 0x40U) + +#define IS_SDIOC_BLOCK_SIZE(x) (((x) >= 1U) && ((x) <= 512U)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SDIOC_Global_Functions SDIOC Global Functions + * @{ + */ + +/** + * @brief Wait for command response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32CheckFlag Check flags + * This parameter can be one or any combination the following values: + * @arg SDIOC_INT_FLAG_CC: Command Complete status + * @arg SDIOC_INT_FLAG_CIE: Command Index error status + * @arg SDIOC_INT_FLAG_CEBE: Command End Bit error status + * @arg SDIOC_INT_FLAG_CCE: Command CRC error status + * @arg SDIOC_INT_FLAG_CTOE: Command Timeout error status + * @param [in] u32Timeout Timeout time(ms) for waiting SDIOC + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_WaitResponse(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32CheckFlag, + uint32_t u32Timeout, uint32_t *pu32ErrStatus) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + uint32_t u32Temp; + + *pu32ErrStatus = 0UL; + /* The u32Timeout is expressed in ms */ + u32Count = u32Timeout * (HCLK_VALUE / 20000UL); + while (RESET == SDIOC_GetIntStatus(SDIOCx, u32CheckFlag)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + if (LL_OK == i32Ret) { + i32Ret = LL_ERR; + u32Temp = CLR_REG32_BIT(u32CheckFlag, SDIOC_INT_FLAG_CC); + if (RESET == SDIOC_GetIntStatus(SDIOCx, u32Temp)) { + /* No error flag set */ + *pu32ErrStatus = SDMMC_ERR_NONE; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_STATIC_FLAGS); + i32Ret = LL_OK; + } else if ((RESET != SDIOC_GetIntStatus(SDIOCx, SDIOC_INT_FLAG_CIE)) && + (SDIOC_INT_FLAG_CIE == (u32CheckFlag & SDIOC_INT_FLAG_CIE))) { + *pu32ErrStatus = SDMMC_ERR_CMD_INDEX; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_FLAG_CIE); + } else if ((RESET != SDIOC_GetIntStatus(SDIOCx, SDIOC_INT_FLAG_CEBE)) && + (SDIOC_INT_FLAG_CEBE == (u32CheckFlag & SDIOC_INT_FLAG_CEBE))) { + *pu32ErrStatus = SDMMC_ERR_CMD_STOP_BIT; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_FLAG_CEBE); + } else if ((RESET != SDIOC_GetIntStatus(SDIOCx, SDIOC_INT_FLAG_CCE)) && + (SDIOC_INT_FLAG_CCE == (u32CheckFlag & SDIOC_INT_FLAG_CCE))) { + *pu32ErrStatus = SDMMC_ERR_CMD_CRC_FAIL; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_FLAG_CCE); + } else { + *pu32ErrStatus = SDMMC_ERR_CMD_TIMEOUT; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_FLAG_CTOE); + } + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for no response command. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdError(CM_SDIOC_TypeDef *SDIOCx) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* The SDMMC_CMD_TIMEOUT is expressed in ms */ + u32Count = SDMMC_CMD_TIMEOUT * (HCLK_VALUE / 20000UL); + while (RESET == SDIOC_GetIntStatus(SDIOCx, SDIOC_INT_FLAG_CC)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + if (LL_OK == i32Ret) { + SDIOC_ClearIntStatus(SDIOCx, SDIOC_INT_STATIC_FLAGS); + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for R1 response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Timeout Timeout time(ms) for waiting SDIOC + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp1(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Timeout, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + uint32_t u32RespVal; + + i32Ret = SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE), u32Timeout, pu32ErrStatus); + if (LL_OK == i32Ret) { + /* Fetch has received a response. */ + (void)SDIOC_GetResponse(SDIOCx, SDIOC_RESP_REG_BIT0_31, &u32RespVal); + if (0UL != (u32RespVal & SDMMC_ERR_BITS_MASK)) { + *pu32ErrStatus = u32RespVal & SDMMC_ERR_BITS_MASK; + i32Ret = LL_ERR; + } + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for R1 response with busy. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Timeout Timeout time(ms) for waiting SDIOC + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp1Busy(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Timeout, uint32_t *pu32ErrStatus) +{ + __IO uint32_t u32Count; + int32_t i32Ret; + uint32_t u32RespVal; + + i32Ret = SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE), u32Timeout, pu32ErrStatus); + if (LL_OK == i32Ret) { + /* Fetch has received a response. */ + (void)SDIOC_GetResponse(SDIOCx, SDIOC_RESP_REG_BIT0_31, &u32RespVal); + if (0UL != (u32RespVal & SDMMC_ERR_BITS_MASK)) { + *pu32ErrStatus = u32RespVal & SDMMC_ERR_BITS_MASK; + i32Ret = LL_ERR; + } else { + /* Wait for busy status to release */ + u32Count = u32Timeout * (HCLK_VALUE / 20000UL); + while (RESET == SDIOC_GetHostStatus(SDIOCx, SDIOC_HOST_FLAG_DATL_D0)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for R2(CID or CSD) response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp2(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + return SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CEBE | SDIOC_INT_FLAG_CCE | + SDIOC_INT_FLAG_CTOE), SDMMC_CMD_TIMEOUT, pu32ErrStatus); +} + +/** + * @brief Checks for error conditions for R3(OCR) response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp3(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + return SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CEBE | SDIOC_INT_FLAG_CTOE), + SDMMC_CMD_TIMEOUT, pu32ErrStatus); +} + +/** + * @brief Checks for error conditions for R6(RCA) response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu16RCA Pointer to a value of device RCA + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp6(CM_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + uint32_t u32RespVal; + + i32Ret = SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE), SDMMC_CMD_TIMEOUT, pu32ErrStatus); + if (LL_OK == i32Ret) { + i32Ret = LL_ERR; + /* Fetch has received a response. */ + (void)SDIOC_GetResponse(SDIOCx, SDIOC_RESP_REG_BIT0_31, &u32RespVal); + if (0UL == (u32RespVal & (SDMMC_R6_GEN_UNKNOWN_ERR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAIL))) { + i32Ret = LL_OK; + *pu16RCA = (uint16_t)(u32RespVal >> 16U); + } else if (SDMMC_R6_GEN_UNKNOWN_ERR == (u32RespVal & SDMMC_R6_GEN_UNKNOWN_ERR)) { + *pu32ErrStatus = SDMMC_ERR_GENERAL_UNKNOWN_ERR; + } else if (SDMMC_R6_ILLEGAL_CMD == (u32RespVal & SDMMC_R6_ILLEGAL_CMD)) { + *pu32ErrStatus = SDMMC_ERR_ILLEGAL_CMD; + } else { + *pu32ErrStatus = SDMMC_ERR_COM_CRC_FAILED; + } + } + + return i32Ret; +} + +/** + * @brief Checks for error conditions for R7 response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: The response is normal received + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_TIMEOUT: Wait timeout + */ +static int32_t SDMMC_GetCmdResp7(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + return SDMMC_WaitResponse(SDIOCx, (SDIOC_INT_FLAG_CC | SDIOC_INT_FLAG_CIE | SDIOC_INT_FLAG_CEBE | + SDIOC_INT_FLAG_CCE | SDIOC_INT_FLAG_CTOE), SDMMC_CMD_TIMEOUT, pu32ErrStatus); +} + +/** + * @brief De-Initialize SDIOC. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval int32_t: + * - LL_OK: SDIOC De-Initialize success + * - LL_ERR_TIMEOUT: Software reset timeout + */ +int32_t SDIOC_DeInit(CM_SDIOC_TypeDef *SDIOCx) +{ + return SDIOC_SWReset(SDIOCx, SDIOC_SW_RST_ALL); +} + +/** + * @brief Initialize SDIOC. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] pstcSdiocInit Pointer to a @ref stc_sdioc_init_t structure + * @retval int32_t: + * - LL_OK: SDIOC Initialize success + * - LL_ERR_INVD_PARAM: pstcSdiocInit == NULL + */ +int32_t SDIOC_Init(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_init_t *pstcSdiocInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcSdiocInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_MD(pstcSdiocInit->u32Mode)); + DDL_ASSERT(IS_SDIOC_CARD_DETECT_WAY(pstcSdiocInit->u8CardDetect)); + DDL_ASSERT(IS_SDIOC_SPEED_MD(pstcSdiocInit->u8SpeedMode)); + DDL_ASSERT(IS_SDIOC_BUS_WIDTH(pstcSdiocInit->u8BusWidth)); + DDL_ASSERT(IS_SDIOC_CLK_DIV(pstcSdiocInit->u16ClockDiv)); + + /* Set the SDIOC mode */ + if (CM_SDIOC1 == SDIOCx) { + WRITE_REG32(bCM_PERIC->SDIOC_SYCTLREG_b.SELMMC1, pstcSdiocInit->u32Mode); + } else { + WRITE_REG32(bCM_PERIC->SDIOC_SYCTLREG_b.SELMMC2, pstcSdiocInit->u32Mode); + } + /* Set the SDIOC clock control value */ + WRITE_REG16(SDIOCx->CLKCON, (pstcSdiocInit->u16ClockDiv | SDIOC_CLKCON_ICE | SDIOC_CLKCON_CE)); + /* Set the SDIOC host control value */ + WRITE_REG8(SDIOCx->HOSTCON, (pstcSdiocInit->u8CardDetect | pstcSdiocInit->u8BusWidth | + pstcSdiocInit->u8SpeedMode)); + /* Enable normal interrupt status */ + WRITE_REG16(SDIOCx->NORINTSTEN, SDIOC_NORINTSGEN_CLR_MASK); + /* Enable error interrupt status */ + WRITE_REG16(SDIOCx->ERRINTSTEN, SDIOC_ERRINTSGEN_CLR_MASK); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_sdioc_init_t to default values. + * @param [out] pstcSdiocInit Pointer to a @ref stc_sdioc_init_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcSdiocInit == NULL + */ +int32_t SDIOC_StructInit(stc_sdioc_init_t *pstcSdiocInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcSdiocInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcSdiocInit->u32Mode = SDIOC_MD_SD; + pstcSdiocInit->u8CardDetect = SDIOC_CARD_DETECT_CD_PIN_LVL; + pstcSdiocInit->u8SpeedMode = SDIOC_SPEED_MD_NORMAL; + pstcSdiocInit->u8BusWidth = SDIOC_BUS_WIDTH_1BIT; + pstcSdiocInit->u16ClockDiv = SDIOC_CLK_DIV1; + } + + return i32Ret; +} + +/** + * @brief Set software reset. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8Type Software reset type + * This parameter can be one of the following values: + * @arg SDIOC_SW_RST_DATA_LINE: Only part of data circuit is reset + * @arg SDIOC_SW_RST_CMD_LINE: Only part of command circuit is reset + * @arg SDIOC_SW_RST_ALL: Reset the entire Host Controller except for the card detection circuit + * @retval int32_t: + * - LL_OK: Software reset success + * - LL_ERR_TIMEOUT: Software reset timeout + */ +int32_t SDIOC_SWReset(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Type) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32Count; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_SW_RST_TYPE(u8Type)); + + WRITE_REG8(SDIOCx->SFTRST, u8Type); + /* Wait for reset finish */ + u32Count = SDIOC_SW_RST_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0U != READ_REG8_BIT(SDIOCx->SFTRST, u8Type)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @brief Enable or disable power. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_PowerCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->PWRCON, SDIOC_PWRCON_PWON); + } else { + CLR_REG8_BIT(SDIOCx->PWRCON, SDIOC_PWRCON_PWON); + } +} + +/** + * @brief Get power state. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval An @ref en_functional_state_t enumeration value. + * - DISABLE: Power off or SDIOCx == NULL + * - ENABLE: Power on + */ +en_functional_state_t SDIOC_GetPowerState(const CM_SDIOC_TypeDef *SDIOCx) +{ + en_functional_state_t enPowerSta = DISABLE; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + if (0U != (READ_REG8_BIT(SDIOCx->PWRCON, SDIOC_PWRCON_PWON))) { + enPowerSta = ENABLE; + } + + return enPowerSta; +} + +/** + * @brief Get SDIOC work mode. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval uint32_t value: + * - SDIOC_MD_SD: SDIOCx selects SD mode + * - SDIOC_MD_MMC: SDIOCx selects MMC mode + */ +uint32_t SDIOC_GetMode(const CM_SDIOC_TypeDef *SDIOCx) +{ + uint32_t u32SdMode; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + u32SdMode = READ_REG32_BIT(CM_PERIC->SDIOC_SYCTLREG, ((CM_SDIOC1 == SDIOCx) ? + PERIC_SDIOC_SYCTLREG_SELMMC1 : PERIC_SDIOC_SYCTLREG_SELMMC2)); + if (0UL != u32SdMode) { /* MMC mode */ + u32SdMode = SDIOC_MD_MMC; + } else { + u32SdMode = SDIOC_MD_SD; + } + + return u32SdMode; +} + +/** + * @brief Enable or disable clock output. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_ClockCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->CLKCON, SDIOC_CLKCON_CE); + } else { + CLR_REG8_BIT(SDIOCx->CLKCON, SDIOC_CLKCON_CE); + } +} + +/** + * @brief Set clock division. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u16Div Clock division + * This parameter can be one of the following values: + * @arg SDIOC_CLK_DIV1: CLK1/1 + * @arg SDIOC_CLK_DIV2: CLK1/2 + * @arg SDIOC_CLK_DIV4: CLK1/4 + * @arg SDIOC_CLK_DIV8: CLK1/8 + * @arg SDIOC_CLK_DIV16: CLK1/16 + * @arg SDIOC_CLK_DIV32: CLK1/32 + * @arg SDIOC_CLK_DIV64: CLK1/64 + * @arg SDIOC_CLK_DIV128: CLK1/128 + * @arg SDIOC_CLK_DIV256: CLK1/256 + * @retval None + */ +void SDIOC_SetClockDiv(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Div) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CLK_DIV(u16Div)); + + MODIFY_REG16(SDIOCx->CLKCON, SDIOC_CLKCON_FS, u16Div); +} + +/** + * @brief Find the most suitable clock division for the set clock frequency. + * @note More clock values can be set as needed, but the maximum cannot exceed 50MHz. + * @param [in] u32ClockFreq SDIOCx_CK clock frequency + * This parameter can be one of the following values: + * @arg SDIOC_OUTPUT_CLK_FREQ_400K: SDIOC clock: 400KHz + * @arg SDIOC_OUTPUT_CLK_FREQ_25M: SDIOC clock: 25MHz + * @arg SDIOC_OUTPUT_CLK_FREQ_26M: SDIOC clock: 26MHz + * @arg SDIOC_OUTPUT_CLK_FREQ_50M: SDIOC clock: 50MHz + * @arg SDIOC_OUTPUT_CLK_FREQ_52M: SDIOC clock: 52MHz + * @arg Any other value + * @param [out] pu16Div Pointer to a value of clock division + * @retval int32_t: + * - LL_OK: SDIOC Initialize success + * - LL_ERR: The Bus clock frequency is too high + * - LL_ERR_INVD_PARAM: pu16Div == NULL or 0UL == u32ClockFreq + */ +int32_t SDIOC_GetOptimumClockDiv(uint32_t u32ClockFreq, uint16_t *pu16Div) +{ + int32_t i32Ret = LL_OK; + uint32_t u32BusClock; + uint32_t u32ClockDiv; + uint32_t u32Temp; + + if ((NULL == pu16Div) || (0UL == u32ClockFreq)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Get BUS frequency */ + u32BusClock = SystemCoreClock / (0x01UL << (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_EXCKS) >> CMU_SCFGR_EXCKS_POS)); + u32ClockDiv = u32BusClock / u32ClockFreq; + if (0UL != (u32BusClock % u32ClockFreq)) { + u32ClockDiv++; + } + /* Check the effectiveness of clock division */ + if (u32ClockDiv > 256U) { /* Maximum division is 256 */ + i32Ret = LL_ERR; + } else { + if (1U == u32ClockDiv) { + *pu16Div = SDIOC_CLK_DIV1; + } else { + for (u32Temp = SDIOC_CLK_DIV2; u32Temp <= SDIOC_CLK_DIV256; u32Temp <<= 1U) { + if (u32ClockDiv <= (u32Temp >> (SDIOC_CLKCON_FS_POS - 1U))) { + break; + } + } + *pu16Div = (uint16_t)u32Temp; + } + } + } + + return i32Ret; +} + +/** + * @brief Verify the validity of the clock division. + * @param [in] u32Mode SDIOC work mode + * This parameter can be one of the following values: + * @arg SDIOC_MD_SD: SDIOCx selects SD mode + * @arg SDIOC_MD_MMC: SDIOCx selects MMC mode + * @param [in] u8SpeedMode Speed mode + * This parameter can be one of the following values: + * @arg SDIOC_SPEED_MD_NORMAL: Normal speed mode + * @arg SDIOC_SPEED_MD_HIGH: High speed mode + * @param [in] u16ClockDiv Clock division + * This parameter can be one of the following values: + * @arg SDIOC_CLK_DIV1: CLK1/1 + * @arg SDIOC_CLK_DIV2: CLK1/2 + * @arg SDIOC_CLK_DIV4: CLK1/4 + * @arg SDIOC_CLK_DIV8: CLK1/8 + * @arg SDIOC_CLK_DIV16: CLK1/16 + * @arg SDIOC_CLK_DIV32: CLK1/32 + * @arg SDIOC_CLK_DIV64: CLK1/64 + * @arg SDIOC_CLK_DIV128: CLK1/128 + * @arg SDIOC_CLK_DIV256: CLK1/256 + * @retval int32_t: + * - LL_OK: The clock division is valid + * - LL_ERR: The Bus clock frequency is too high + */ +int32_t SDIOC_VerifyClockDiv(uint32_t u32Mode, uint8_t u8SpeedMode, uint16_t u16ClockDiv) +{ + int32_t i32Ret = LL_OK; + uint32_t u32BusClock; + uint32_t u32ClockFreq; + uint32_t u32MaxFreq; + uint32_t u32DivValue; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_MD(u32Mode)); + DDL_ASSERT(IS_SDIOC_SPEED_MD(u8SpeedMode)); + DDL_ASSERT(IS_SDIOC_CLK_DIV(u16ClockDiv)); + + /* Get Bus frequency */ + u32BusClock = SystemCoreClock / (0x01UL << (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_EXCKS) >> CMU_SCFGR_EXCKS_POS)); + u32DivValue = ((uint32_t)u16ClockDiv >> (SDIOC_CLKCON_FS_POS - 1U)); + if (0UL == u32DivValue) { + u32ClockFreq = u32BusClock; + } else { + u32ClockFreq = u32BusClock / u32DivValue; + } + + if (SDIOC_SPEED_MD_NORMAL == u8SpeedMode) { + if (SDIOC_MD_SD != u32Mode) { /* MMC mode */ + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_26M; + } else { + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_25M; + } + } else { + if (SDIOC_MD_SD != u32Mode) { /* MMC mode */ + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_52M; + } else { + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_50M; + } + } + if (u32ClockFreq > u32MaxFreq) { + i32Ret = LL_ERR; + } + + return i32Ret; +} + +/** + * @brief Get device insert status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SDIOC_GetInsertStatus(const CM_SDIOC_TypeDef *SDIOCx) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + if (0UL != (READ_REG32_BIT(SDIOCx->PSTAT, SDIOC_PSTAT_CSS))) { + if (0UL != (READ_REG32_BIT(SDIOCx->PSTAT, SDIOC_PSTAT_CIN))) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Set speed mode. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8SpeedMode Speed mode + * This parameter can be one of the following values: + * @arg SDIOC_SPEED_MD_NORMAL: Normal speed mode + * @arg SDIOC_SPEED_MD_HIGH: High speed mode + * @retval None + */ +void SDIOC_SetSpeedMode(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8SpeedMode) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_SPEED_MD(u8SpeedMode)); + + if (SDIOC_SPEED_MD_NORMAL != u8SpeedMode) { + SET_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_HSEN); + } else { + CLR_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_HSEN); + } +} + +/** + * @brief Set bus width. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8BusWidth Bus width + * This parameter can be one of the following values: + * @arg SDIOC_BUS_WIDTH_1BIT: The Bus width is 1 bit + * @arg SDIOC_BUS_WIDTH_4BIT: The Bus width is 4 bit + * @arg SDIOC_BUS_WIDTH_8BIT: The Bus width is 8 bit + * @retval None + */ +void SDIOC_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8BusWidth) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_BUS_WIDTH(u8BusWidth)); + + MODIFY_REG8(SDIOCx->HOSTCON, (SDIOC_HOSTCON_DW | SDIOC_HOSTCON_EXDW), u8BusWidth); +} + +/** + * @brief Set card detect line select. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8Src Card detect source + * This parameter can be one of the following values: + * @arg SDIOC_CARD_DETECT_CD_PIN_LVL: SDIOCx_CD(x=1~2) line is selected (for normal use) + * @arg SDIOC_CARD_DETECT_TEST_SIGNAL: The Card Detect Test Level is selected(for test purpose) + * @retval None + */ +void SDIOC_SetCardDetectSrc(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Src) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CARD_DETECT_WAY(u8Src)); + + if (SDIOC_CARD_DETECT_CD_PIN_LVL != u8Src) { + SET_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDSS); + } else { + CLR_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDSS); + } +} + +/** + * @brief Set card detect test level. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8Level Card test level + * This parameter can be one of the following values: + * @arg SDIOC_CARD_DETECT_TEST_LVL_LOW: Card identification test signal is low level (with device insertion) + * @arg SDIOC_CARD_DETECT_TEST_LVL_HIGH: Card identification test signal is high level (no device insertion) + * @retval None + */ +void SDIOC_SetCardDetectTestLevel(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CARD_DETECT_TEST_LEVEL(u8Level)); + + if (SDIOC_CARD_DETECT_TEST_LVL_LOW != u8Level) { + SET_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDTL); + } else { + CLR_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDTL); + } +} + +/** + * @brief Configure the SDIOCx command parameters. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] pstcCmdConfig Pointer to a @ref stc_sdioc_cmd_config_t structure + * @retval int32_t: + * - LL_OK: Configure SDIOCx command parameters success + * - LL_ERR_INVD_PARAM: pstcCmdConfig == NULL + */ +int32_t SDIOC_SendCommand(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_cmd_config_t *pstcCmdConfig) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *pu32Temp; + + if (NULL == pstcCmdConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CMD_INDEX(pstcCmdConfig->u16CmdIndex)); + DDL_ASSERT(IS_SDIOC_CMD_TYPE(pstcCmdConfig->u16CmdType)); + DDL_ASSERT(IS_SDIOC_DATA_LINE(pstcCmdConfig->u16DataLine)); + DDL_ASSERT(IS_SDIOC_RESP_TYPE(pstcCmdConfig->u16ResponseType)); + + /* Set the SDIOC Command parameters value */ + pu32Temp = SDIOC_ARG_ADDR(SDIOCx); + WRITE_REG32(*pu32Temp, pstcCmdConfig->u32Argument); + /* Set the SDIOC Command controller value */ + WRITE_REG16(SDIOCx->CMD, ((uint16_t)(pstcCmdConfig->u16CmdIndex << SDIOC_CMD_IDX_POS) | + pstcCmdConfig->u16CmdType | pstcCmdConfig->u16DataLine | + pstcCmdConfig->u16ResponseType)); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_sdioc_cmd_config_t to default values. + * @param [out] pstcCmdConfig Pointer to a @ref stc_sdioc_cmd_config_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcDataConfig == NULL + */ +int32_t SDIOC_CommandStructInit(stc_sdioc_cmd_config_t *pstcCmdConfig) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcCmdConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcCmdConfig->u32Argument = 0U; + pstcCmdConfig->u16CmdIndex = 0U; + pstcCmdConfig->u16CmdType = SDIOC_CMD_TYPE_NORMAL; + pstcCmdConfig->u16DataLine = SDIOC_DATA_LINE_DISABLE; + pstcCmdConfig->u16ResponseType = SDIOC_RESP_TYPE_NO; + } + + return i32Ret; +} + +/** + * @brief Get the response received from the card for the last command + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u8Reg SDIOC response register + * This parameter can be one of the following values: + * @arg SDIOC_RESP_REG_BIT0_31: Command Response Register 0-31bit + * @arg SDIOC_RESP_REG_BIT32_63: Command Response Register 32-63bit + * @arg SDIOC_RESP_REG_BIT64_95: Command Response Register 64-95bit + * @arg SDIOC_RESP_REG_BIT96_127: Command Response Register 96-127bit + * @param [out] pu32Value Pointer to a Response value + * @retval int32_t: + * - LL_OK: Get response success + * - LL_ERR_INVD_PARAM: pu32Value == NULL + */ +int32_t SDIOC_GetResponse(CM_SDIOC_TypeDef *SDIOCx, uint8_t u8Reg, uint32_t *pu32Value) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pu32Value) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_RESP_REG(u8Reg)); + + *pu32Value = READ_REG32(*SDIOC_RESP_ADDR(SDIOCx, u8Reg)); + } + + return i32Ret; +} + +/** + * @brief Configure the SDIOCx data parameters. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] pstcDataConfig Pointer to a @ref stc_sdioc_data_config_t structure + * @retval int32_t: + * - LL_OK: Configure SDIOCx data parameters success + * - LL_ERR_INVD_PARAM: pstcDataConfig == NULL + */ +int32_t SDIOC_ConfigData(CM_SDIOC_TypeDef *SDIOCx, const stc_sdioc_data_config_t *pstcDataConfig) +{ + int32_t i32Ret = LL_OK; + uint16_t u16BlkCnt; + + if (NULL == pstcDataConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_BLOCK_SIZE(pstcDataConfig->u16BlockSize)); + DDL_ASSERT(IS_SDIOC_TRANS_DIR(pstcDataConfig->u16TransDir)); + DDL_ASSERT(IS_SDIOC_AUTO_SEND_CMD12(pstcDataConfig->u16AutoCmd12)); + DDL_ASSERT(IS_SDIOC_TRANS_MD(pstcDataConfig->u16TransMode)); + DDL_ASSERT(IS_SDIOC_DATA_TIMEOUT_TIME(pstcDataConfig->u16DataTimeout)); + + if (SDIOC_TRANS_MD_STOP_MULTI == pstcDataConfig->u16TransMode) { + u16BlkCnt = 0U; + } else { + u16BlkCnt = pstcDataConfig->u16BlockCount; + } + /* Set the SDIOC Data Transfer Timeout value */ + WRITE_REG8(SDIOCx->TOUTCON, pstcDataConfig->u16DataTimeout); + /* Set the SDIOC Block Count value */ + WRITE_REG16(SDIOCx->BLKSIZE, pstcDataConfig->u16BlockSize); + /* Set the SDIOC Block Size value */ + WRITE_REG16(SDIOCx->BLKCNT, u16BlkCnt); + /* Set the SDIOC Data Transfer Mode */ + WRITE_REG16(SDIOCx->TRANSMODE, ((pstcDataConfig->u16TransDir | pstcDataConfig->u16AutoCmd12 | + pstcDataConfig->u16TransMode) & 0xFFU)); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_sdioc_data_config_t to default values. + * @param [out] pstcDataConfig Pointer to a @ref stc_sdioc_data_config_t structure + * @retval int32_t: + * - LL_OK: Structure Initialize success + * - LL_ERR_INVD_PARAM: pstcDataConfig == NULL + */ +int32_t SDIOC_DataStructInit(stc_sdioc_data_config_t *pstcDataConfig) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDataConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDataConfig->u16BlockSize = 512U; + pstcDataConfig->u16BlockCount = 0U; + pstcDataConfig->u16TransDir = SDIOC_TRANS_DIR_TO_CARD; + pstcDataConfig->u16AutoCmd12 = SDIOC_AUTO_SEND_CMD12_DISABLE; + pstcDataConfig->u16TransMode = SDIOC_TRANS_MD_SINGLE; + pstcDataConfig->u16DataTimeout = SDIOC_DATA_TIMEOUT_CLK_2E13; + } + + return i32Ret; +} + +/** + * @brief Read data from SDIOC FIFO. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] au8Data Pointer to the buffer + * @param [in] u32Len Data length + * @retval int32_t: + * - LL_OK: Read data success + * - LL_ERR_INVD_PARAM: NULL == au8Data or (u32Len % 4U) != 0 + */ +int32_t SDIOC_ReadBuffer(CM_SDIOC_TypeDef *SDIOCx, uint8_t au8Data[], uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + uint32_t u32Temp; + __IO uint32_t *BUF_REG; + + if ((NULL == au8Data) || (0U != (u32Len % 4U))) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + BUF_REG = SDIOC_BUF_ADDR(SDIOCx); + for (i = 0U; i < u32Len; i += 4U) { + u32Temp = READ_REG32(*BUF_REG); + au8Data[i] = (uint8_t)(u32Temp & 0xFFUL); + au8Data[i + 1U] = (uint8_t)((u32Temp >> 8U) & 0xFFUL); + au8Data[i + 2U] = (uint8_t)((u32Temp >> 16U) & 0xFFUL); + au8Data[i + 3U] = (uint8_t)((u32Temp >> 24U) & 0xFFUL); + } + } + + return i32Ret; +} + +/** + * @brief Write data to SDIOC FIFO. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] au8Data Pointer to the buffer + * @param [in] u32Len Data length + * @retval int32_t: + * - LL_OK: Write data success + * - LL_ERR_INVD_PARAM: NULL == au8Data or (u32Len % 4U) != 0 + */ +int32_t SDIOC_WriteBuffer(CM_SDIOC_TypeDef *SDIOCx, const uint8_t au8Data[], uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + uint32_t u32Temp; + __IO uint32_t *BUF_REG; + + if ((NULL == au8Data) || (0U != (u32Len % 4U))) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + BUF_REG = SDIOC_BUF_ADDR(SDIOCx); + for (i = 0U; i < u32Len; i += 4U) { + u32Temp = ((uint32_t)au8Data[i + 3U] << 24U) | ((uint32_t)au8Data[i + 2U] << 16U) | + ((uint32_t)au8Data[i + 1U] << 8U) | au8Data[i]; + WRITE_REG32(*BUF_REG, u32Temp); + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable block gap stop. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_BlockGapStopCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_SABGR); + } else { + CLR_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_SABGR); + } +} + +/** + * @brief Restart data transfer. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @retval None + */ +void SDIOC_RestartTrans(CM_SDIOC_TypeDef *SDIOCx) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_CR); +} + +/** + * @brief Enable or disable read wait. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_ReadWaitCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_RWC); + } else { + CLR_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_RWC); + } +} + +/** + * @brief Enable or disable data block gap interrupt. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_BlockGapIntCmd(CM_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_IABG); + } else { + CLR_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_IABG); + } +} + +/** + * @brief Enable or disable interrupt. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32IntType Normal and error interrupts source + * This parameter can be one or any combination of the following values: + * @arg SDIOC_INT_CINTSEN: Card interrupt + * @arg SDIOC_INT_CRMSEN: Card Removal interrupt + * @arg SDIOC_INT_CISTSEN: Card Insertion interrupt + * @arg SDIOC_INT_BRRSEN: Buffer Read Ready interrupt + * @arg SDIOC_INT_BWRSEN: Buffer Write Ready interrupt + * @arg SDIOC_INT_BGESEN: Block Gap Event interrupt + * @arg SDIOC_INT_TCSEN: Transfer Complete interrupt + * @arg SDIOC_INT_CCSEN: Command Complete interrupt + * @arg SDIOC_INT_ACESEN: Auto CMD12 error interrupt + * @arg SDIOC_INT_DEBESEN: Data End Bit error interrupt + * @arg SDIOC_INT_DCESEN: Data CRC error interrupt + * @arg SDIOC_INT_DTOESEN: Data Timeout error interrupt + * @arg SDIOC_INT_CIESEN: Command Index error interrupt + * @arg SDIOC_INT_CEBESEN: Command End Bit error interrupt + * @arg SDIOC_INT_CCESEN: Command CRC error interrupt + * @arg SDIOC_INT_CTOESEN: Command Timeout error interrupt + * @arg SDIOC_INT_ALL: All of the above + * @arg SDIOC_NORMAL_INT_ALL: All of the normal interrupt + * @arg SDIOC_ERR_INT_ALL: All of the error interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_IntCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint16_t u16NormalInt; + uint16_t u16ErrorInt; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u16NormalInt = (uint16_t)(u32IntType & 0xFFFFU); + u16ErrorInt = (uint16_t)(u32IntType >> 16U); + if (DISABLE != enNewState) { + if (0U != u16NormalInt) { + SET_REG16_BIT(SDIOCx->NORINTSGEN, u16NormalInt); + } + if (0U != u16ErrorInt) { + SET_REG16_BIT(SDIOCx->ERRINTSGEN, u16ErrorInt); + } + } else { + if (0U != u16NormalInt) { + CLR_REG16_BIT(SDIOCx->NORINTSGEN, u16NormalInt); + } + if (0U != u16ErrorInt) { + CLR_REG16_BIT(SDIOCx->ERRINTSGEN, u16ErrorInt); + } + } +} + +/** + * @brief Get interrupt enable state. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32IntType Normal and error interrupts source + * This parameter can be one or any combination of the following values: + * @arg SDIOC_INT_CINTSEN: Card interrupt + * @arg SDIOC_INT_CRMSEN: Card Removal interrupt + * @arg SDIOC_INT_CISTSEN: Card Insertion interrupt + * @arg SDIOC_INT_BRRSEN: Buffer Read Ready interrupt + * @arg SDIOC_INT_BWRSEN: Buffer Write Ready interrupt + * @arg SDIOC_INT_BGESEN: Block Gap Event interrupt + * @arg SDIOC_INT_TCSEN: Transfer Complete interrupt + * @arg SDIOC_INT_CCSEN: Command Complete interrupt + * @arg SDIOC_INT_ACESEN: Auto CMD12 error interrupt + * @arg SDIOC_INT_DEBESEN: Data End Bit error interrupt + * @arg SDIOC_INT_DCESEN: Data CRC error interrupt + * @arg SDIOC_INT_DTOESEN: Data Timeout error interrupt + * @arg SDIOC_INT_CIESEN: Command Index error interrupt + * @arg SDIOC_INT_CEBESEN: Command End Bit error interrupt + * @arg SDIOC_INT_CCESEN: Command CRC error interrupt + * @arg SDIOC_INT_CTOESEN: Command Timeout error interrupt + * @arg SDIOC_INT_ALL: All of the above + * @arg SDIOC_NORMAL_INT_ALL: All of the normal interrupt + * @arg SDIOC_ERR_INT_ALL: All of the error interrupt + * @retval An @ref en_functional_state_t enumeration value. + * - ENABLE: The interrupt is enable + * - DISABLE: The interrupt is disable + */ +en_functional_state_t SDIOC_GetIntEnableState(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType) +{ + uint16_t u16NormalInt; + uint16_t u16ErrorInt; + en_functional_state_t enIntSta = DISABLE; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_INT(u32IntType)); + + u16NormalInt = (uint16_t)(u32IntType & 0xFFFFU); + u16ErrorInt = (uint16_t)(u32IntType >> 16U); + if (0U != u16NormalInt) { + if (0U != (READ_REG16_BIT(SDIOCx->NORINTSGEN, u16NormalInt))) { + enIntSta = ENABLE; + } + } + if ((0U != u16ErrorInt) && (enIntSta != ENABLE)) { + if (0U != (READ_REG16_BIT(SDIOCx->ERRINTSGEN, u16ErrorInt))) { + enIntSta = ENABLE; + } + } + + return enIntSta; +} + +/** + * @brief Get interrupt flag status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Flag Normal and error interrupts flag + * This parameter can be one or any combination the following values: + * @arg SDIOC_INT_FLAG_EI: Error interrupt flag + * @arg SDIOC_INT_FLAG_CINT: Card interrupt flag + * @arg SDIOC_INT_FLAG_CRM: Card Removal flag + * @arg SDIOC_INT_FLAG_CIST: Card Insertion flag + * @arg SDIOC_INT_FLAG_BRR: Buffer Read Ready flag + * @arg SDIOC_INT_FLAG_BWR: Buffer Write Ready flag + * @arg SDIOC_INT_FLAG_BGE: Block Gap Event flag + * @arg SDIOC_INT_FLAG_TC: Transfer Complete flag + * @arg SDIOC_INT_FLAG_CC: Command Complete flag + * @arg SDIOC_INT_FLAG_ACE: Auto CMD12 error flag + * @arg SDIOC_INT_FLAG_DEBE: Data End Bit error flag + * @arg SDIOC_INT_FLAG_DCE: Data CRC error flag + * @arg SDIOC_INT_FLAG_DTOE: Data Timeout error flag + * @arg SDIOC_INT_FLAG_CIE: Command Index error flag + * @arg SDIOC_INT_FLAG_CEBE: Command End Bit error flag + * @arg SDIOC_INT_FLAG_CCE: Command CRC error flag + * @arg SDIOC_INT_FLAG_CTOE: Command Timeout error flag + * @arg SDIOC_INT_FLAG_ALL: All of the above + * @arg SDIOC_NORMAL_INT_FLAG_ALL: All of the normal interrupt flag + * @arg SDIOC_ERR_INT_FLAG_ALL: All of the error interrupt flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SDIOC_GetIntStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + uint16_t u16NormalFlag; + uint16_t u16ErrorFlag; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_GET_INT_FLAG(u32Flag)); + + u16NormalFlag = (uint16_t)(u32Flag & 0xFFFFU); + u16ErrorFlag = (uint16_t)(u32Flag >> 16U); + if (0U != u16NormalFlag) { + if (0U != (READ_REG16_BIT(SDIOCx->NORINTST, u16NormalFlag))) { + enFlagSta = SET; + } + } + if ((0U != u16ErrorFlag) && (enFlagSta != SET)) { + if (0U != (READ_REG16_BIT(SDIOCx->ERRINTST, u16ErrorFlag))) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Clear interrupt flag status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Flag Normal and error interrupts flag + * This parameter can be one or any combination of the following values: + * @arg SDIOC_INT_FLAG_CRM: Card Removal flag + * @arg SDIOC_INT_FLAG_CIST: Card Insertion flag + * @arg SDIOC_INT_FLAG_BRR: Buffer Read Ready flag + * @arg SDIOC_INT_FLAG_BWR: Buffer Write Ready flag + * @arg SDIOC_INT_FLAG_BGE: Block Gap Event flag + * @arg SDIOC_INT_FLAG_TC: Transfer Complete flag + * @arg SDIOC_INT_FLAG_CC: Command Complete flag + * @arg SDIOC_INT_FLAG_ACE: Auto CMD12 error flag + * @arg SDIOC_INT_FLAG_DEBE: Data End Bit error flag + * @arg SDIOC_INT_FLAG_DCE: Data CRC error flag + * @arg SDIOC_INT_FLAG_DTOE: Data Timeout error flag + * @arg SDIOC_INT_FLAG_CIE: Command Index error flag + * @arg SDIOC_INT_FLAG_CEBE: Command End Bit error flag + * @arg SDIOC_INT_FLAG_CCE: Command CRC error flag + * @arg SDIOC_INT_FLAG_CTOE: Command Timeout error flag + * @arg SDIOC_INT_FLAG_CLR_ALL: All of the above + * @retval None + */ +void SDIOC_ClearIntStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag) +{ + uint16_t u16NormalFlag; + uint16_t u16ErrorFlag; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CLR_INT_FLAG(u32Flag)); + + u16NormalFlag = (uint16_t)(u32Flag & 0xFFFFU); + u16ErrorFlag = (uint16_t)(u32Flag >> 16U); + if (0U != u16NormalFlag) { + WRITE_REG16(SDIOCx->NORINTST, u16NormalFlag); + } + if (0U != u16ErrorFlag) { + WRITE_REG16(SDIOCx->ERRINTST, u16ErrorFlag); + } +} + +/** + * @brief Enable or disable interrupt status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32IntType Normal and error interrupts source + * This parameter can be one or any combination of the following values: + * @arg SDIOC_INT_CINTSEN: Card interrupt + * @arg SDIOC_INT_CRMSEN: Card Removal interrupt + * @arg SDIOC_INT_CISTSEN: Card Insertion interrupt + * @arg SDIOC_INT_BRRSEN: Buffer Read Ready interrupt + * @arg SDIOC_INT_BWRSEN: Buffer Write Ready interrupt + * @arg SDIOC_INT_BGESEN: Block Gap Event interrupt + * @arg SDIOC_INT_TCSEN: Transfer Complete interrupt + * @arg SDIOC_INT_CCSEN: Command Complete interrupt + * @arg SDIOC_INT_ACESEN: Auto CMD12 error interrupt + * @arg SDIOC_INT_DEBESEN: Data End Bit error interrupt + * @arg SDIOC_INT_DCESEN: Data CRC error interrupt + * @arg SDIOC_INT_DTOESEN: Data Timeout error interrupt + * @arg SDIOC_INT_CIESEN: Command Index error interrupt + * @arg SDIOC_INT_CEBESEN: Command End Bit error interrupt + * @arg SDIOC_INT_CCESEN: Command CRC error interrupt + * @arg SDIOC_INT_CTOESEN: Command Timeout error interrupt + * @arg SDIOC_INT_ALL: All of the above + * @arg SDIOC_NORMAL_INT_ALL: All of the normal interrupt + * @arg SDIOC_ERR_INT_ALL: All of the error interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SDIOC_IntStatusCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint16_t u16NormalInt; + uint16_t u16ErrorInt; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u16NormalInt = (uint16_t)(u32IntType & 0xFFFFU); + u16ErrorInt = (uint16_t)(u32IntType >> 16U); + if (DISABLE != enNewState) { + if (0U != u16NormalInt) { + SET_REG16_BIT(SDIOCx->NORINTSTEN, u16NormalInt); + } + if (0U != u16ErrorInt) { + SET_REG16_BIT(SDIOCx->ERRINTSTEN, u16ErrorInt); + } + } else { + if (0U != u16NormalInt) { + CLR_REG16_BIT(SDIOCx->NORINTSTEN, u16NormalInt); + } + if (0U != u16ErrorInt) { + CLR_REG16_BIT(SDIOCx->ERRINTSTEN, u16ErrorInt); + } + } +} + +/** + * @brief Get Host status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Flag Host flag + * This parameter can be one or any combination the following values: + * @arg SDIOC_HOST_FLAG_CMDL: CMD Line Level flag + * @arg SDIOC_HOST_FLAG_DATL: DAT[3:0] Line Level flag + * @arg SDIOC_HOST_FLAG_DATL_D0: DAT[0] Line Level flag + * @arg SDIOC_HOST_FLAG_DATL_D1: DAT[1] Line Level flag + * @arg SDIOC_HOST_FLAG_DATL_D2: DAT[2] Line Level flag + * @arg SDIOC_HOST_FLAG_DATL_D3: DAT[3] Line Level flag + * @arg SDIOC_HOST_FLAG_WPL: Write Protect Line Level flag + * @arg SDIOC_HOST_FLAG_CDL: Card Detect Line Level flag + * @arg SDIOC_HOST_FLAG_CSS: Device Stable flag + * @arg SDIOC_HOST_FLAG_CIN: Device Inserted flag + * @arg SDIOC_HOST_FLAG_BRE: Data buffer full flag + * @arg SDIOC_HOST_FLAG_BWE: Data buffer empty flag + * @arg SDIOC_HOST_FLAG_RTA: Read operation flag + * @arg SDIOC_HOST_FLAG_WTA: Write operation flag + * @arg SDIOC_HOST_FLAG_DA: DAT Line transfer flag + * @arg SDIOC_HOST_FLAG_CID: Command Inhibit with data flag + * @arg SDIOC_HOST_FLAG_CIC: Command Inhibit flag + * @arg SDIOC_HOST_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SDIOC_GetHostStatus(const CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_GET_HOST_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(SDIOCx->PSTAT, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Get auto CMD12 error status. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u16Flag Auto CMD12 error flag + * This parameter can be one or any combination the following values: + * @arg SDIOC_AUTO_CMD_ERR_FLAG_CMDE: Command Not Issued By Auto CMD12 error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_IE: Auto CMD12 Index error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_EBE: Auto CMD12 End Bit error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_CE: Auto CMD12 CRC error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_TOE: Auto CMD12 Timeout error flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_NE: Auto CMD12 Not Executed flag + * @arg SDIOC_AUTO_CMD_ERR_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SDIOC_GetAutoCmdErrorStatus(const CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_AUTO_CMD_ERR_FLAG(u16Flag)); + + if (0U != (READ_REG16_BIT(SDIOCx->ATCERRST, u16Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Force the specified auto CMD12 error event. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u16Event Auto CMD12 error event + * This parameter can be one or any combination the following values: + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FCMDE: Force Event for Command Not Issued By Auto CMD12 error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FIE: Force Event for Auto CMD12 Index error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FEBE: Force Event for Auto CMD12 End Bit error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FCE: Force Event for Auto CMD12 CRC error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FTOE: Force Event for Auto CMD12 Timeout error + * @arg SDIOC_FORCE_AUTO_CMD_ERR_FNE: Force Event for Auto CMD12 Not Executed + * @arg SDIOC_FORCE_AUTO_CMD_ERR_ALL: All of the above + * @retval None + */ +void SDIOC_ForceAutoCmdErrorEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_FORCE_AUTO_CMD_ERR(u16Event)); + + WRITE_REG16(SDIOCx->FEA, u16Event); +} + +/** + * @brief Force the specified error interrupt event. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u16Event Error interrupt event + * This parameter can be one or any combination the following values: + * @arg SDIOC_FORCE_ERR_INT_FACE: Force Event for Auto CMD12 error + * @arg SDIOC_FORCE_ERR_INT_FDEBE: Force Event for Data End Bit error + * @arg SDIOC_FORCE_ERR_INT_FDCE: Force Event for Data CRC error + * @arg SDIOC_FORCE_ERR_INT_FDTOE: Force Event for Data Timeout error + * @arg SDIOC_FORCE_ERR_INT_FCIE: Force Event for Command Index error + * @arg SDIOC_FORCE_ERR_INT_FCEBE: Force Event for Command End Bit error + * @arg SDIOC_FORCE_ERR_INT_FCCE: Force Event for Command CRC error + * @arg SDIOC_FORCE_ERR_INT_FCTOE: Force Event for Command Timeout error + * @arg SDIOC_FORCE_ERR_INT_ALL: All of the above + * @retval None + */ +void SDIOC_ForceErrorIntEvent(CM_SDIOC_TypeDef *SDIOCx, uint16_t u16Event) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_FORCE_ERR_INT(u16Event)); + + WRITE_REG16(SDIOCx->FEE, u16Event); +} + +/** + * @brief Send the Go Idle State command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD0_GoIdleState(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + *pu32ErrStatus = SDMMC_ERR_NONE; + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_CMD0_GO_IDLE_STATE; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_NO; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdError(SDIOCx); + } + } + + return i32Ret; +} + +/** + * @brief Send the Send CID command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD2_AllSendCID(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_CMD2_ALL_SEND_CID; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R2; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp2(SDIOCx, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the command for asking the card to publish a new relative address(RCA). + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu16RCA Pointer to the new RCA value + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu16RCA == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD3_SendRelativeAddr(CM_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if ((NULL == pu16RCA) || (NULL == pu32ErrStatus)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_CMD3_SEND_RELATIVE_ADDR; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp6(SDIOCx, pu16RCA, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Checks switchable function and switch card function. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD6_SwitchFunc(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + uint32_t u32SdMode; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32Argument; + stcCmdConfig.u16CmdIndex = SDIOC_CMD6_SWITCH_FUNC; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + u32SdMode = SDIOC_GetMode(SDIOCx); + if (SDIOC_MD_SD != u32SdMode) { /* MMC mode */ + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1B_R5B; + } else { + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + } + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + if (SDIOC_MD_SD != u32SdMode) { /* MMC mode */ + i32Ret = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } else { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + } + + return i32Ret; +} + +/** + * @brief Send the Select Deselect command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32RCA Relative Card Address(RCA) + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD7_SelectDeselectCard(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32RCA; + stcCmdConfig.u16CmdIndex = SDIOC_CMD7_SELECT_DESELECT_CARD; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1B_R5B; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Interface Condition command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD8_SendInterfaceCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + uint32_t u32SdMode; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + stcCmdConfig.u32Argument = SDMMC_CMD8_CHECK_PATTERN; + stcCmdConfig.u16CmdIndex = SDIOC_CMD8_SEND_IF_COND; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + u32SdMode = SDIOC_GetMode(SDIOCx); + if (SDIOC_MD_SD != u32SdMode) { /* MMC mode */ + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + } else { + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + } + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + if (SDIOC_MD_SD != u32SdMode) { /* MMC mode */ + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } else { + i32Ret = SDMMC_GetCmdResp7(SDIOCx, pu32ErrStatus); + } + } + } + + return i32Ret; +} + +/** + * @brief Send the Send CSD command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32RCA Relative Card Address(RCA) + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD9_SendCSD(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32RCA; + stcCmdConfig.u16CmdIndex = SDIOC_CMD9_SEND_CSD; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R2; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp2(SDIOCx, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Stop Transfer command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD12_StopTrans(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_CMD12_STOP_TRANSMISSION; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1B_R5B; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_CMD_TIMEOUT * 1000UL, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Status command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32RCA Relative Card Address(RCA) + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32RCA; + stcCmdConfig.u16CmdIndex = SDIOC_CMD13_SEND_STATUS; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Data Block Length command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32BlockLen Block length + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD16_SetBlockLength(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BlockLen, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32BlockLen; + stcCmdConfig.u16CmdIndex = SDIOC_CMD16_SET_BLOCKLEN; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Read Single Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32ReadAddr Data address + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD17_ReadSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32ReadAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD17_READ_SINGLE_BLOCK; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Read Multi Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32ReadAddr Data address + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD18_ReadMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32ReadAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD18_READ_MULTI_BLOCK; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Write Single Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32WriteAddr Data address + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD24_WriteSingleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32WriteAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD24_WRITE_SINGLE_BLOCK; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Write Multi Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32WriteAddr Data address + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD25_WriteMultipleBlock(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32WriteAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD25_WRITE_MULTI_BLOCK; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Start Address Erase command for SD and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32StartAddr The start address will be erased + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD32_EraseBlockStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32StartAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD32_ERASE_WR_BLK_START; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the End Address Erase command for SD and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32EndAddr The end address will be erased + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD33_EraseBlockEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32EndAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD33_ERASE_WR_BLK_END; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Erase command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD38_Erase(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_CMD38_ERASE; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1B_R5B; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_MAX_ERASE_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Application command to verify that that the next command + * is an application specific command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD55_AppCmd(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32Argument; + stcCmdConfig.u16CmdIndex = SDIOC_CMD55_APP_CMD; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Bus Width command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32BusWidth The data bus width + * This parameter can be one of the following values: + * @arg SDMMC_SCR_BUS_WIDTH_1BIT: 1 bit bus + * @arg SDMMC_SCR_BUS_WIDTH_4BIT: 4 bits bus + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_ACMD6_SetBusWidth(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32BusWidth, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32BusWidth; + stcCmdConfig.u16CmdIndex = SDIOC_ACMD6_SET_BUS_WIDTH; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Status register command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_ACMD13_SendStatus(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_ACMD13_SD_STATUS; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the command asking the accessed card to send its operating condition register(OCR). + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_ACMD41_SendOperatCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32Argument | SDMMC_ACMD41_VOLT_WIN; + stcCmdConfig.u16CmdIndex = SDIOC_ACMD41_SD_APP_OP_COND; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R3_R4; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp3(SDIOCx, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Send SCR command and check the response. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_ACMD51_SendSCR(CM_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = 0UL; + stcCmdConfig.u16CmdIndex = SDIOC_ACMD51_SEND_SCR; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Sends host capacity support information command. + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD1_SendOperatCond(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32Argument; + stcCmdConfig.u16CmdIndex = SDIOC_CMD1_SEND_OP_COND; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R3_R4; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp3(SDIOCx, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the Start Address Erase command and check the response + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32StartAddr The start address will be erased + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD35_EraseGroupStartAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32StartAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD35_ERASE_GROUP_START; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @brief Send the End Address Erase command and check the response + * @param [in] SDIOCx Pointer to SDIOC unit instance + * This parameter can be one of the following values: + * @arg CM_SDIOC1: SDIOC unit 1 instance + * @arg CM_SDIOC2: SDIOC unit 2 instance + * @param [in] u32EndAddr The end address will be erased + * @param [out] pu32ErrStatus Pointer to the error state value + * @retval int32_t: + * - LL_OK: Command send completed + * - LL_ERR: Refer to pu32ErrStatus for the reason of error + * - LL_ERR_INVD_PARAM: SDIOCx == NULL or pu32ErrStatus == NULL + * - LL_ERR_TIMEOUT: Wait timeout + */ +int32_t SDMMC_CMD36_EraseGroupEndAddr(CM_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrStatus) +{ + int32_t i32Ret; + stc_sdioc_cmd_config_t stcCmdConfig; + + if (NULL == pu32ErrStatus) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + stcCmdConfig.u32Argument = u32EndAddr; + stcCmdConfig.u16CmdIndex = SDIOC_CMD36_ERASE_GROUP_END; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_DISABLE; + stcCmdConfig.u16ResponseType = SDIOC_RESP_TYPE_R1_R5_R6_R7; + i32Ret = SDIOC_SendCommand(SDIOCx, &stcCmdConfig); + /* Check for error conditions */ + if (LL_OK == i32Ret) { + i32Ret = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrStatus); + } + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_SDIOC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_spi.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_spi.c new file mode 100644 index 0000000000..18e73da87a --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_spi.c @@ -0,0 +1,882 @@ +/** + ******************************************************************************* + * @file hc32_ll_spi.c + * @brief This file provides firmware functions to manage the Serial Peripheral + * Interface(SPI). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_spi.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SPI SPI + * @brief Serial Peripheral Interface Driver Library + * @{ + */ + +#if (LL_SPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SPI_Local_Macros SPI Local Macros + * @{ + */ + +#define SPI_CFG1_DEFAULT (0x00000010UL) +#define SPI_CFG2_DEFAULT (0x00000F1DUL) + +#define SPI_SS0_VALID_CFG (0UL) +#define SPI_SS1_VALID_CFG (SPI_CFG2_SSA_0) +#define SPI_SS2_VALID_CFG (SPI_CFG2_SSA_1) +#define SPI_SS3_VALID_CFG (SPI_CFG2_SSA_0 | SPI_CFG2_SSA_1) + +#define SPI_SR_DEFAULT (0x00000020UL) + +/** + * @defgroup SPI_Check_Parameters_Validity SPI Check Parameters Validity + * @{ + */ + +/*! Parameter valid check for SPI peripheral */ +#define IS_VALID_SPI_UNIT(x) \ +( (CM_SPI1 == (x)) || \ + (CM_SPI2 == (x)) || \ + (CM_SPI3 == (x)) || \ + (CM_SPI4 == (x))) + +/*! Parameter valid check for SPI wire mode */ +#define IS_SPI_WIRE_MD(x) \ +( ((x) == SPI_4_WIRE) || \ + ((x) == SPI_3_WIRE)) + +/*! Parameter valid check for SPI transfer mode */ +#define IS_SPI_TRANS_MD(x) \ +( ((x) == SPI_FULL_DUPLEX) || \ + ((x) == SPI_SEND_ONLY)) + +/*! Parameter valid check for SPI master slave mode */ +#define IS_SPI_MASTER_SLAVE(x) \ +( ((x) == SPI_SLAVE) || \ + ((x) == SPI_MASTER)) + +/*! Parameter valid check for SPI loopback mode */ +#define IS_SPI_SPLPBK(x) \ +( ((x) == SPI_LOOPBACK_INVD) || \ + ((x) == SPI_LOOPBACK_MOSI_INVT) || \ + ((x) == SPI_LOOPBACK_MOSI)) + +/*! Parameter valid check for SPI communication suspend function status */ +#define IS_SPI_SUSPD_MD_STD(x) \ +( ((x) == SPI_COM_SUSP_FUNC_OFF) || \ + ((x) == SPI_COM_SUSP_FUNC_ON)) + +/*! Parameter valid check for SPI data frame level */ +#define IS_SPI_DATA_FRAME(x) \ +( ((x) == SPI_1_FRAME) || \ + ((x) == SPI_2_FRAME) || \ + ((x) == SPI_3_FRAME) || \ + ((x) == SPI_4_FRAME)) + +/*! Parameter valid check for SPI fault dectet function status */ +#define IS_SPI_MD_FAULT_DETECT_CMD(x) \ +( ((x) == SPI_MD_FAULT_DETECT_DISABLE) || \ + ((x) == SPI_MD_FAULT_DETECT_ENABLE)) + +/*! Parameter valid check for SPI parity check mode */ +#define IS_SPI_PARITY_CHECK(x) \ +( ((x) == SPI_PARITY_INVD) || \ + ((x) == SPI_PARITY_EVEN) || \ + ((x) == SPI_PARITY_ODD)) + +/*! Parameter valid check for SPI interval time delay */ +#define IS_SPI_INTERVAL_DELAY(x) \ +( ((x) == SPI_INTERVAL_TIME_1SCK) || \ + ((x) == SPI_INTERVAL_TIME_2SCK) || \ + ((x) == SPI_INTERVAL_TIME_3SCK) || \ + ((x) == SPI_INTERVAL_TIME_4SCK) || \ + ((x) == SPI_INTERVAL_TIME_5SCK) || \ + ((x) == SPI_INTERVAL_TIME_6SCK) || \ + ((x) == SPI_INTERVAL_TIME_7SCK) || \ + ((x) == SPI_INTERVAL_TIME_8SCK)) + +/*! Parameter valid check for SPI release time delay */ +#define IS_SPI_RELEASE_DELAY(x) \ +( ((x) == SPI_RELEASE_TIME_1SCK) || \ + ((x) == SPI_RELEASE_TIME_2SCK) || \ + ((x) == SPI_RELEASE_TIME_3SCK) || \ + ((x) == SPI_RELEASE_TIME_4SCK) || \ + ((x) == SPI_RELEASE_TIME_5SCK) || \ + ((x) == SPI_RELEASE_TIME_6SCK) || \ + ((x) == SPI_RELEASE_TIME_7SCK) || \ + ((x) == SPI_RELEASE_TIME_8SCK)) + +/*! Parameter valid check for SPI Setup time delay delay */ +#define IS_SPI_SETUP_DELAY(x) \ +( ((x) == SPI_SETUP_TIME_1SCK) || \ + ((x) == SPI_SETUP_TIME_2SCK) || \ + ((x) == SPI_SETUP_TIME_3SCK) || \ + ((x) == SPI_SETUP_TIME_4SCK) || \ + ((x) == SPI_SETUP_TIME_5SCK) || \ + ((x) == SPI_SETUP_TIME_6SCK) || \ + ((x) == SPI_SETUP_TIME_7SCK) || \ + ((x) == SPI_SETUP_TIME_8SCK)) + +/*! Parameter valid check for SPI read data register target buffer */ +#define IS_SPI_RD_TARGET_BUFF(x) \ +( ((x) == SPI_RD_TARGET_RD_BUF) || \ + ((x) == SPI_RD_TARGET_WR_BUF)) + +/*! Parameter valid check for SPI mode */ +#define IS_SPI_SPI_MD(x) \ +( ((x) == SPI_MD_0) || \ + ((x) == SPI_MD_1) || \ + ((x) == SPI_MD_2) || \ + ((x) == SPI_MD_3)) + +/*! Parameter valid check for SPI SS signal */ +#define IS_SPI_SS_PIN(x) \ +( ((x) == SPI_PIN_SS0) || \ + ((x) == SPI_PIN_SS1) || \ + ((x) == SPI_PIN_SS2) || \ + ((x) == SPI_PIN_SS3)) + +/*! Parameter valid check for SPI baudrate prescaler */ +#define IS_SPI_BIT_RATE_DIV(x) \ +( ((x) == SPI_BR_CLK_DIV2) || \ + ((x) == SPI_BR_CLK_DIV4) || \ + ((x) == SPI_BR_CLK_DIV8) || \ + ((x) == SPI_BR_CLK_DIV16) || \ + ((x) == SPI_BR_CLK_DIV32) || \ + ((x) == SPI_BR_CLK_DIV64) || \ + ((x) == SPI_BR_CLK_DIV128) || \ + ((x) == SPI_BR_CLK_DIV256)) + +/*! Parameter valid check for SPI data bits */ +#define IS_SPI_DATA_SIZE(x) \ +( ((x) == SPI_DATA_SIZE_4BIT) || \ + ((x) == SPI_DATA_SIZE_5BIT) || \ + ((x) == SPI_DATA_SIZE_6BIT) || \ + ((x) == SPI_DATA_SIZE_7BIT) || \ + ((x) == SPI_DATA_SIZE_8BIT) || \ + ((x) == SPI_DATA_SIZE_9BIT) || \ + ((x) == SPI_DATA_SIZE_10BIT) || \ + ((x) == SPI_DATA_SIZE_11BIT) || \ + ((x) == SPI_DATA_SIZE_12BIT) || \ + ((x) == SPI_DATA_SIZE_13BIT) || \ + ((x) == SPI_DATA_SIZE_14BIT) || \ + ((x) == SPI_DATA_SIZE_15BIT) || \ + ((x) == SPI_DATA_SIZE_16BIT) || \ + ((x) == SPI_DATA_SIZE_20BIT) || \ + ((x) == SPI_DATA_SIZE_24BIT) || \ + ((x) == SPI_DATA_SIZE_32BIT)) + +/*! Parameter valid check for SPI LSB MSB mode */ +#define IS_SPI_FIRST_BIT(x) \ +( ((x) == SPI_FIRST_MSB) || \ + ((x) == SPI_FIRST_LSB)) + +/*! Parameter valid check for SPI Communication mode */ +#define IS_SPI_COMM_MD(x) \ +( ((x) == SPI_COMM_MD_NORMAL) || \ + ((x) == SPI_COMM_MD_CONTINUE)) + +/*! Parameter valid check for interrupt flag */ +#define IS_SPI_INT(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_IRQ_ALL) == SPI_IRQ_ALL)) + +/*! Parameter valid check for SPI status flag */ +#define IS_SPI_STD_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_FLAG_ALL) == SPI_FLAG_ALL)) + +/*! Parameter valid check for SPI status flag for clear */ +#define IS_SPI_CLR_STD_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_FLAG_CLR_ALL) == SPI_FLAG_CLR_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SPI_Local_Func SPI Local Functions + * @{ + */ + +/** + * @brief SPI check status. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32FlagMask Bit mask of status flag. + * @param [in] u32Value Valid value of the status. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: SPI transmit timeout. + */ +static int32_t SPI_WaitStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32FlagMask, uint32_t u32Value, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + + while (READ_REG32_BIT(SPIx->SR, u32FlagMask) != u32Value) { + if (u32Timeout == 0UL) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Timeout--; + } + return i32Ret; +} + +/** + * @brief SPI transmit and receive data in full duplex mode. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [out] pvRxBuf The pointer to the buffer which the received data will be stored. + * @param [in] u32Len The length of the data in byte or half word. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI transmit and receive timeout. + */ +static int32_t SPI_TxRx(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t u32BitSize; + __IO uint32_t u32Count = 0U; + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + __UNUSED __IO uint32_t u32Read; + + /* Get data bit size, SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_32BIT */ + u32BitSize = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE); + + while (u32Count < u32Len) { + if (pvTxBuf != NULL) { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + WRITE_REG32(SPIx->DR, ((const uint8_t *)pvTxBuf)[u32Count]); + } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + WRITE_REG32(SPIx->DR, ((const uint16_t *)pvTxBuf)[u32Count]); + } else { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + WRITE_REG32(SPIx->DR, ((const uint32_t *)pvTxBuf)[u32Count]); + } + } else { + WRITE_REG32(SPIx->DR, 0xFFFFFFFFUL); + } + + /* Check RX buffer. */ + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_RX_BUF_FULL, SPI_FLAG_RX_BUF_FULL, u32Timeout); + if (i32Ret == LL_OK) { + u32Tmp = READ_REG32(SPIx->DR); + if (pvRxBuf != NULL) { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + ((uint8_t *)pvRxBuf)[u32Count] = (uint8_t)u32Tmp; + } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + ((uint16_t *)pvRxBuf)[u32Count] = (uint16_t)u32Tmp; + } else { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + ((uint32_t *)pvRxBuf)[u32Count] = (uint32_t)u32Tmp; + } + } else { + /* Dummy read */ + u32Read = READ_REG32(SPIx->DR); + } + u32Count++; + } + } + if (i32Ret == LL_OK) { + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_IDLE, 0UL, u32Timeout); + } + + return i32Ret; +} + +/** + * @brief SPI send data only. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [in] u32Len The length of the data in byte or half word or word. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: SPI transmit timeout. + */ +static int32_t SPI_Tx(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + __IO uint32_t u32Count = 0U; + uint32_t u32BitSize; + int32_t i32Ret = LL_OK; + + /* Get data bit size, SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_32BIT */ + u32BitSize = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE); + + while (u32Count < u32Len) { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + WRITE_REG32(SPIx->DR, ((const uint8_t *)pvTxBuf)[u32Count]); + } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + WRITE_REG32(SPIx->DR, ((const uint16_t *)pvTxBuf)[u32Count]); + } else { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + WRITE_REG32(SPIx->DR, ((const uint32_t *)pvTxBuf)[u32Count]); + } + + /* Wait TX buffer empty. */ + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_TX_BUF_EMPTY, SPI_FLAG_TX_BUF_EMPTY, u32Timeout); + if (i32Ret != LL_OK) { + break; + } + u32Count++; + } + if (i32Ret == LL_OK) { + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_IDLE, 0UL, u32Timeout); + } + + return i32Ret; +} + +/** + * @} + */ + +/** + * @defgroup SPI_Global_Functions SPI Global Functions + * @{ + */ + +/** + * @brief Initializes the SPI peripheral according to the specified parameters + * in the structure stc_spi_init. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pstcSpiInit Pointer to a stc_spi_init_t structure that contains + * the configuration information for the SPI. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_INVD_PARAM: pstcSpiInit == NULL or configuration parameter error. + */ + +int32_t SPI_Init(CM_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + if (NULL != pstcSpiInit) { + DDL_ASSERT(IS_SPI_WIRE_MD(pstcSpiInit->u32WireMode)); + DDL_ASSERT(IS_SPI_TRANS_MD(pstcSpiInit->u32TransMode)); + DDL_ASSERT(IS_SPI_MASTER_SLAVE(pstcSpiInit->u32MasterSlave)); + DDL_ASSERT(IS_SPI_MD_FAULT_DETECT_CMD(pstcSpiInit->u32ModeFaultDetect)); + DDL_ASSERT(IS_SPI_PARITY_CHECK(pstcSpiInit->u32Parity)); + DDL_ASSERT(IS_SPI_SPI_MD(pstcSpiInit->u32SpiMode)); + DDL_ASSERT(IS_SPI_BIT_RATE_DIV(pstcSpiInit->u32BaudRatePrescaler)); + DDL_ASSERT(IS_SPI_DATA_SIZE(pstcSpiInit->u32DataBits)); + DDL_ASSERT(IS_SPI_FIRST_BIT(pstcSpiInit->u32FirstBit)); + DDL_ASSERT(IS_SPI_SUSPD_MD_STD(pstcSpiInit->u32SuspendMode)); + DDL_ASSERT(IS_SPI_DATA_FRAME(pstcSpiInit->u32FrameLevel)); + + /* Configuration parameter check */ + if ((SPI_MASTER == pstcSpiInit->u32MasterSlave) && (SPI_MD_FAULT_DETECT_ENABLE == pstcSpiInit->u32ModeFaultDetect)) { + /* pstcSpiInit->u32ModeFaultDetect can not be SPI_MD_FAULT_DETECT_ENABLE in master mode */ + } else if ((SPI_3_WIRE == pstcSpiInit->u32WireMode) && (SPI_SLAVE == pstcSpiInit->u32MasterSlave) + && ((SPI_MD_0 == pstcSpiInit->u32SpiMode) || (SPI_MD_2 == pstcSpiInit->u32SpiMode))) { + /* SPI_3_WIRE can not support SPI_MD_0 and SPI_MD_2 */ + } else { + WRITE_REG32(SPIx->CR1, pstcSpiInit->u32WireMode | pstcSpiInit->u32TransMode | pstcSpiInit->u32MasterSlave + | pstcSpiInit->u32SuspendMode | pstcSpiInit->u32ModeFaultDetect | pstcSpiInit->u32Parity); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_FTHLV, pstcSpiInit->u32FrameLevel); + WRITE_REG32(SPIx->CFG2, pstcSpiInit->u32SpiMode | pstcSpiInit->u32BaudRatePrescaler | pstcSpiInit->u32DataBits + | pstcSpiInit->u32FirstBit); + i32Ret = LL_OK; + } + } + return i32Ret; +} + +/** + * @brief De-initializes the SPI peripheral. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @retval None + */ +void SPI_DeInit(CM_SPI_TypeDef *SPIx) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + WRITE_REG32(SPIx->CR1, 0UL); + WRITE_REG32(SPIx->CFG1, SPI_CFG1_DEFAULT); + WRITE_REG32(SPIx->CFG2, SPI_CFG2_DEFAULT); + WRITE_REG32(SPIx->SR, SPI_SR_DEFAULT); +} + +/** + * @brief Set a default value for the SPI initialization structure. + * @param [in] pstcSpiInit Pointer to a stc_spi_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcSpiInit == NULL. + */ +int32_t SPI_StructInit(stc_spi_init_t *pstcSpiInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSpiInit) { + pstcSpiInit->u32WireMode = SPI_4_WIRE; + pstcSpiInit->u32TransMode = SPI_FULL_DUPLEX; + pstcSpiInit->u32MasterSlave = SPI_MASTER; + pstcSpiInit->u32ModeFaultDetect = SPI_MD_FAULT_DETECT_DISABLE; + pstcSpiInit->u32Parity = SPI_PARITY_INVD; + pstcSpiInit->u32SpiMode = SPI_MD_0; + pstcSpiInit->u32BaudRatePrescaler = SPI_BR_CLK_DIV8; + pstcSpiInit->u32DataBits = SPI_DATA_SIZE_8BIT; + pstcSpiInit->u32FirstBit = SPI_FIRST_MSB; + pstcSpiInit->u32SuspendMode = SPI_COM_SUSP_FUNC_OFF; + pstcSpiInit->u32FrameLevel = SPI_1_FRAME; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Enable or disable SPI interrupt. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32IntType SPI interrupt type. Can be one or any + * combination of the parameter @ref SPI_Int_Type_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SPI_IntCmd(CM_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_SPI_INT(u32IntType)); + + if (enNewState == ENABLE) { + SET_REG32_BIT(SPIx->CR1, u32IntType); + } else { + CLR_REG32_BIT(SPIx->CR1, u32IntType); + } +} + +/** + * @brief SPI function enable or disable. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SPI_Cmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(SPIx->CR1, SPI_CR1_SPE); + } else { + CLR_REG32_BIT(SPIx->CR1, SPI_CR1_SPE); + } +} + +/** + * @brief Write SPI data register. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Data The data will be written to the data register. + * @retval None. + */ +void SPI_WriteData(CM_SPI_TypeDef *SPIx, uint32_t u32Data) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + WRITE_REG32(SPIx->DR, u32Data); +} + +/** + * @brief Read SPI data register. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @retval uint32_t A 32-bit data of SPI data register. + */ +uint32_t SPI_ReadData(const CM_SPI_TypeDef *SPIx) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return READ_REG32(SPIx->DR); +} + +/** + * @brief SPI get status flag. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Flag SPI state flag. Can be one or any + * combination of the parameter of @ref SPI_State_Flag_Define + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SPI_GetStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32Flag) +{ + en_flag_status_t enFlag = RESET; + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_STD_FLAG(u32Flag)); + + if (0U != READ_REG32_BIT(SPIx->SR, u32Flag)) { + enFlag = SET; + } + + return enFlag; +} + +/** + * @brief SPI clear state flag. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Flag SPI state flag. Can be one or any combination of the parameter below + * @arg SPI_FLAG_OVERLOAD + * @arg SPI_FLAG_MD_FAULT + * @arg SPI_FLAG_PARITY_ERR + * @arg SPI_FLAG_UNDERLOAD + * @retval None + */ +void SPI_ClearStatus(CM_SPI_TypeDef *SPIx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_CLR_STD_FLAG(u32Flag)); + + CLR_REG32_BIT(SPIx->SR, u32Flag); +} + +/** + * @brief SPI loopback function configuration. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Mode Loopback mode. Can be one parameter @ref SPI_Loopback_Selection_Define + * @retval None + */ +void SPI_LoopbackModeConfig(CM_SPI_TypeDef *SPIx, uint32_t u32Mode) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SPLPBK(u32Mode)); + + MODIFY_REG32(SPIx->CR1, SPI_CR1_SPLPBK | SPI_CR1_SPLPBK2, u32Mode); +} + +/** + * @brief SPI parity check error self diagnosis function enable or disable. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ + +void SPI_ParityCheckCmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(SPIx->CR1, SPI_CR1_PATE); + } else { + CLR_REG32_BIT(SPIx->CR1, SPI_CR1_PATE); + } +} + +/** + * @brief SPI signals delay time configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pstcDelayConfig Pointer to a stc_spi_delay_t structure that contains + * the configuration information for the SPI delay time. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_INVD_PARAM: pstcDelayConfig == NULL + */ +int32_t SPI_DelayTimeConfig(CM_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + if (NULL != pstcDelayConfig) { + DDL_ASSERT(IS_SPI_INTERVAL_DELAY(pstcDelayConfig->u32IntervalDelay)); + DDL_ASSERT(IS_SPI_RELEASE_DELAY(pstcDelayConfig->u32ReleaseDelay)); + DDL_ASSERT(IS_SPI_SETUP_DELAY(pstcDelayConfig->u32SetupDelay)); + + /* Interval delay */ + if (SPI_INTERVAL_TIME_1SCK == pstcDelayConfig->u32IntervalDelay) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MIDIE); + CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MIDI); + } else { + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MIDI, pstcDelayConfig->u32IntervalDelay); + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MIDIE); + } + + /* SCK release delay */ + if (SPI_RELEASE_TIME_1SCK == pstcDelayConfig->u32ReleaseDelay) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSDLE); + CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSDL); + } else { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSDLE); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MSSDL, pstcDelayConfig->u32ReleaseDelay); + } + + /* Setup delay */ + if (SPI_SETUP_TIME_1SCK == pstcDelayConfig->u32SetupDelay) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE); + CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSI); + } else { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MSSI, pstcDelayConfig->u32SetupDelay); + } + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set a default value for the SPI delay time configuration structure. + * @param [in] pstcDelayConfig Pointer to a stc_spi_delay_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcDelayConfig == NULL. + */ +int32_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDelayConfig) { + pstcDelayConfig->u32IntervalDelay = SPI_INTERVAL_TIME_1SCK; + pstcDelayConfig->u32ReleaseDelay = SPI_RELEASE_TIME_1SCK; + pstcDelayConfig->u32SetupDelay = SPI_SETUP_TIME_1SCK; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief SPI SS signal valid level configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32SSPin Specify the SS pin @ref SPI_SS_Pin_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SPI_SSValidLevelConfig(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SS_PIN(u32SSPin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(SPIx->CFG1, u32SSPin); + } else { + CLR_REG32_BIT(SPIx->CFG1, u32SSPin); + } +} + +/** + * @brief SPI valid SS signal configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32SSPin Specify the SS pin @ref SPI_SS_Pin_Define + * @retval None + */ +void SPI_SSPinSelect(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin) +{ + uint32_t u32RegConfig; + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SS_PIN(u32SSPin)); + + switch (u32SSPin) { + case SPI_PIN_SS0: + u32RegConfig = SPI_SS0_VALID_CFG; + break; + case SPI_PIN_SS1: + u32RegConfig = SPI_SS1_VALID_CFG; + break; + case SPI_PIN_SS2: + u32RegConfig = SPI_SS2_VALID_CFG; + break; + case SPI_PIN_SS3: + u32RegConfig = SPI_SS3_VALID_CFG; + break; + + default: + u32RegConfig = SPI_SS0_VALID_CFG; + break; + } + MODIFY_REG32(SPIx->CFG2, SPI_CFG2_SSA, u32RegConfig); +} + +/** + * @brief SPI read buffer configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32ReadBuf Target buffer for read operation @ref SPI_Read_Target_Buf_Define + * @retval None + */ +void SPI_ReadBufConfig(CM_SPI_TypeDef *SPIx, uint32_t u32ReadBuf) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_RD_TARGET_BUFF(u32ReadBuf)); + + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_SPRDTD, u32ReadBuf); +} + +/** + * @brief SPI transmit data. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [in] u32TxLen The length of the data to be sent. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI transmit timeout. + * - LL_ERR_INVD_PARAM: pvTxBuf == NULL or u32TxLen == 0U + * @note -No SS pin active and inactive operation in 3-wire mode. Add operations of SS pin depending on your application. + * -This function supports full duplex mode and send only mode. + */ +int32_t SPI_Trans(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLen, uint32_t u32Timeout) +{ + uint32_t u32Flags; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pvTxBuf != NULL) && (u32TxLen != 0U)) { + u32Flags = READ_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS); + if (u32Flags == SPI_SEND_ONLY) { + /* Transmit data in send only mode. */ + i32Ret = SPI_Tx(SPIx, pvTxBuf, u32TxLen, u32Timeout); + } else { + /* Transmit data in full duplex mode. */ + i32Ret = SPI_TxRx(SPIx, pvTxBuf, NULL, u32TxLen, u32Timeout); + } + } + return i32Ret; +} + +/** + * @brief SPI receive data. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvRxBuf The pointer to the buffer which the received data to be stored. + * @param [in] u32RxLen The length of the data to be received. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI receive timeout. + * - LL_ERR_INVD_PARAM: pvRxBuf == NULL or u32RxLen == 0U + * @note -No SS pin active and inactive operation in 3-wire mode. Add operations of SS pin depending on your application. + * -This function only works in full duplex master mode. + */ +int32_t SPI_Receive(CM_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLen, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pvRxBuf != NULL) && (u32RxLen != 0U)) { + /* Receives data in full duplex master mode. */ + i32Ret = SPI_TxRx(SPIx, NULL, pvRxBuf, u32RxLen, u32Timeout); + } + return i32Ret; +} + +/** + * @brief SPI transmit and receive data. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * If this pointer is NULL and the pvRxBuf is NOT NULL, the MOSI output high + * and the the received data will be stored in the buffer pointed by pvRxBuf. + * @param [out] pvRxBuf The pointer to the buffer which the received data will be stored. + * This for full duplex transfer. + * @param [in] u32Len The length of the data(in byte or half word) to be sent and received. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI transmit and receive timeout. + * - LL_ERR_INVD_PARAM: pvRxBuf == NULL or pvRxBuf == NULL or u32Len == 0U + * @note SPI receives data while sending data. Only works in full duplex master mode. + */ +int32_t SPI_TransReceive(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pvTxBuf != NULL) && (pvRxBuf != NULL) && (u32Len != 0U)) { + /* Transmit and receive data in full duplex master mode. */ + i32Ret = SPI_TxRx(SPIx, pvTxBuf, pvRxBuf, u32Len, u32Timeout); + } + return i32Ret; +} +/** + * @} + */ + +#endif /* LL_SPI_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_sram.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_sram.c new file mode 100644 index 0000000000..64f5da6e57 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_sram.c @@ -0,0 +1,301 @@ +/** + ******************************************************************************* + * @file hc32_ll_sram.c + * @brief This file provides firmware functions to manage the SRAM. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_sram.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SRAM SRAM + * @brief SRAM Driver Library + * @{ + */ + +#if (LL_SRAM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SRAM_Local_Macros SRAM Local Macros + * @{ + */ + +/** + * @defgroup SRAM_Configuration_Bits_Mask SRAM Configuration Bits Mask + * @{ + */ +#define SRAM_ECC_MD_MASK (SRAMC_CKCR_ECCMOD) +#define SRAM_CYCLE_MASK (0x00000007UL) +/** + * @} + */ + +/** + * @defgroup SRAM_Check_Parameters_Validity SRAM check parameters validity + * @{ + */ +#define IS_SRAM_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +#define IS_SRAM_ERR_MD(x) (((x) == SRAM_ERR_MD_NMI) || ((x) == SRAM_ERR_MD_RST)) + +#define IS_SRAM_WAIT_CYCLE(x) ((x) <= SRAM_WAIT_CYCLE7) + +#define IS_SRAM_SEL(x) IS_SRAM_BIT_MASK(x, SRAM_SRAM_ALL) + +#define IS_SRAM_ECC_SRAM(x) ((x) == SRAM_ECC_SRAM3) + +#define IS_SRAM_FLAG(x) IS_SRAM_BIT_MASK(x, SRAM_FLAG_ALL) + +#define IS_SRAM_WTPR_UNLOCK() (CM_SRAMC->WTPR == SRAM_REG_UNLOCK_KEY) + +#define IS_SRAM_CKPR_UNLOCK() (CM_SRAMC->CKPR == SRAM_REG_UNLOCK_KEY) + +#define IS_SRAM_ECC_MD(x) \ +( ((x) == SRAM_ECC_MD_INVD) || \ + ((x) == SRAM_ECC_MD1) || \ + ((x) == SRAM_ECC_MD2) || \ + ((x) == SRAM_ECC_MD3)) + +/* Error injection */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SRAM_Global_Functions SRAM Global Functions + * @{ + */ + +/** + * @brief Initializes SRAM. + * @param None + * @retval None + */ +void SRAM_Init(void) +{ + SET_REG32_BIT(CM_SRAMC->CKSR, SRAM_FLAG_ALL); +} + +/** + * @brief De-initializes SRAM. RESET the registers of SRAM. + * @param None + * @retval None + * @note Call SRAM_REG_Unlock to unlock registers WTCR and CKCR first. + */ +void SRAM_DeInit(void) +{ + /* Call SRAM_REG_Unlock to unlock register WTCR and CKCR. */ + DDL_ASSERT(IS_SRAM_WTPR_UNLOCK()); + DDL_ASSERT(IS_SRAM_CKPR_UNLOCK()); + + WRITE_REG32(CM_SRAMC->WTCR, 0U); + WRITE_REG32(CM_SRAMC->CKCR, 0U); + SET_REG32_BIT(CM_SRAMC->CKSR, SRAM_FLAG_ALL); +} + +/** + * @brief Specifies access wait cycle for SRAM. + * @param [in] u32SramSel The SRAM selection. + * This parameter can be values of @ref SRAM_Sel + * @param [in] u32WriteCycle The write access wait cycle for the specified SRAM + * This parameter can be a value of @ref SRAM_Access_Wait_Cycle + * @param [in] u32ReadCycle The read access wait cycle for the specified SRAM. + * This parameter can be a value of @ref SRAM_Access_Wait_Cycle + * @arg SRAM_WAIT_CYCLE0: Wait 0 CPU cycle. + * @arg SRAM_WAIT_CYCLE1: Wait 1 CPU cycle. + * @arg SRAM_WAIT_CYCLE2: Wait 2 CPU cycles. + * @arg SRAM_WAIT_CYCLE3: Wait 3 CPU cycles. + * @arg SRAM_WAIT_CYCLE4: Wait 4 CPU cycles. + * @arg SRAM_WAIT_CYCLE5: Wait 5 CPU cycles. + * @arg SRAM_WAIT_CYCLE6: Wait 6 CPU cycles. + * @arg SRAM_WAIT_CYCLE7: Wait 7 CPU cycles. + * @retval None + * @note Call SRAM_REG_Unlock to unlock register WTCR first. + */ +void SRAM_SetWaitCycle(uint32_t u32SramSel, uint32_t u32WriteCycle, uint32_t u32ReadCycle) +{ + uint8_t i = 0U; + uint8_t u8OfsWt; + uint8_t u8OfsRd; + + DDL_ASSERT(IS_SRAM_SEL(u32SramSel)); + DDL_ASSERT(IS_SRAM_WAIT_CYCLE(u32WriteCycle)); + DDL_ASSERT(IS_SRAM_WAIT_CYCLE(u32ReadCycle)); + DDL_ASSERT(IS_SRAM_WTPR_UNLOCK()); + + while (u32SramSel != 0UL) { + if ((u32SramSel & 0x1UL) != 0UL) { + u8OfsWt = i * 8U; + u8OfsRd = u8OfsWt + 4U; + MODIFY_REG32(CM_SRAMC->WTCR, + ((SRAM_CYCLE_MASK << u8OfsWt) | (SRAM_CYCLE_MASK << u8OfsRd)), + ((u32WriteCycle << u8OfsWt) | (u32ReadCycle << u8OfsRd))); + } + u32SramSel >>= 1U; + i++; + } +} + +/** + * @brief Specifies ECC mode. + * @param [in] u32SramSel The SRAM selection. This function is used to specify the + * ECC mode for members SRAM_ECC_XXXX of @ref SRAM_Sel + * @param [in] u32EccMode The ECC mode. + * This parameter can be a value of @ref SRAM_ECC_Mode + * @arg SRAM_ECC_MD_INVD: The ECC mode is invalid. + * @arg SRAM_ECC_MD1: When 1-bit error occurred: + * ECC error corrects. + * No 1-bit-error status flag setting, no interrupt or reset. + * When 2-bit error occurred: + * ECC error detects. + * 2-bit-error status flag sets and interrupt or reset occurred. + * @arg SRAM_ECC_MD2: When 1-bit error occurred: + * ECC error corrects. + * 1-bit-error status flag sets, no interrupt or reset. + * When 2-bit error occurred: + * ECC error detects. + * 2-bit-error status flag sets and interrupt or reset occurred. + * @arg SRAM_ECC_MD3: When 1-bit error occurred: + * ECC error corrects. + * 1-bit-error status flag sets and interrupt or reset occurred. + * When 2-bit error occurred: + * ECC error detects. + * 2-bit-error status flag sets and interrupt or reset occurred. + * @retval None + * @note Call SRAM_REG_Unlock to unlock register CKCR first. + */ +void SRAM_SetEccMode(uint32_t u32SramSel, uint32_t u32EccMode) +{ + DDL_ASSERT(IS_SRAM_ECC_SRAM(u32SramSel)); + DDL_ASSERT(IS_SRAM_ECC_MD(u32EccMode)); + DDL_ASSERT(IS_SRAM_CKPR_UNLOCK()); + + if ((u32SramSel & SRAM_SRAM3) != 0U) { + MODIFY_REG32(CM_SRAMC->CKCR, SRAM_ECC_MD_MASK, u32EccMode); + } + +} + +/** + * @brief Specifies the operation which is operated after check error occurred. + * @param [in] u32SramSel The SRAM selection. + * This parameter can be values of @ref SRAM_Sel + * @param [out] u32ErrMode The operation after check error occurred. + * This parameter can be a value of @ref SRAM_Err_Mode + * @arg SRAM_ERR_MD_NMI: Check error generates NMI(non-maskable interrupt). + * @arg SRAM_ERR_MD_RST: Check error generates system reset. + * @retval None + * @note Call SRAM_REG_Unlock to unlock register CKCR first. + */ +void SRAM_SetErrorMode(uint32_t u32SramSel, uint32_t u32ErrMode) +{ + DDL_ASSERT(IS_SRAM_SEL(u32SramSel)); + DDL_ASSERT(IS_SRAM_ERR_MD(u32ErrMode)); + DDL_ASSERT(IS_SRAM_CKPR_UNLOCK()); + + if ((u32SramSel & (SRAM_SRAM12 | SRAM_SRAMR | SRAM_SRAMH)) != 0U) { + WRITE_REG32(bCM_SRAMC->CKCR_b.PYOAD, u32ErrMode); + } + + if ((u32SramSel & SRAM_SRAM3) != 0U) { + WRITE_REG32(bCM_SRAMC->CKCR_b.ECCOAD, u32ErrMode); + } + +} + +/** + * @brief Get the status of the specified flag of SRAM. + * @param [in] u32Flag The flag of SRAM. + * This parameter can be a value of @ref SRAM_Err_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SRAM_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_SRAM_FLAG(u32Flag)); + if (READ_REG32_BIT(CM_SRAMC->CKSR, u32Flag) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified flag of SRAM. + * @param [in] u32Flag The flag of SRAM. + * This parameter can be values of @ref SRAM_Err_Status_Flag + * @retval None + */ +void SRAM_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_SRAM_FLAG(u32Flag)); + SET_REG32_BIT(CM_SRAMC->CKSR, u32Flag); +} + +/** + * @} + */ + +#endif /* LL_SRAM_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_swdt.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_swdt.c new file mode 100644 index 0000000000..e16fde24a6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_swdt.c @@ -0,0 +1,181 @@ +/** + ******************************************************************************* + * @file hc32_ll_swdt.c + * @brief This file provides firmware functions to manage the Specialized Watch + * Dog Timer(SWDT). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_swdt.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SWDT SWDT + * @brief Specialized Watch Dog Timer + * @{ + */ + +#if (LL_SWDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SWDT_Local_Macros SWDT Local Macros + * @{ + */ + +/* SWDT Refresh Key */ +#define SWDT_REFRESH_KEY_START (0x0123UL) +#define SWDT_REFRESH_KEY_END (0x3210UL) + +/* SWDT clear flag timeout(ms) */ +#define SWDT_CLR_FLAG_TIMEOUT (5UL) + +/** + * @defgroup SWDT_Check_Parameters_Validity SWDT Check Parameters Validity + * @{ + */ + +#define IS_SWDT_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SWDT_FLAG_ALL) == SWDT_FLAG_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @addtogroup SWDT_Global_Functions + * @{ + */ + +/** + * @brief SWDT feed dog. + * @note In software startup mode, Start counter when refreshing for the first time. + * @param None + * @retval None + */ +void SWDT_FeedDog(void) +{ + WRITE_REG32(CM_SWDT->RR, SWDT_REFRESH_KEY_START); + WRITE_REG32(CM_SWDT->RR, SWDT_REFRESH_KEY_END); +} + +/** + * @brief Get SWDT flag status. + * @param [in] u32Flag SWDT flag type + * This parameter can be one or any combination of the following values: + * @arg SWDT_FLAG_UDF: Count underflow flag + * @arg SWDT_FLAG_REFRESH: Refresh error flag + * @arg SWDT_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SWDT_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_SWDT_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_SWDT->SR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear SWDT flag. + * @param [in] u32Flag SWDT flag type + * This parameter can be one or any combination of the following values: + * @arg SWDT_FLAG_UDF: Count underflow flag + * @arg SWDT_FLAG_REFRESH: Refresh error flag + * @arg SWDT_FLAG_ALL: All of the above + * @retval int32_t: + * - LL_OK: Clear flag success + * - LL_ERR_TIMEOUT: Clear flag timeout + */ +int32_t SWDT_ClearStatus(uint32_t u32Flag) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Check parameters */ + DDL_ASSERT(IS_SWDT_FLAG(u32Flag)); + + CLR_REG32_BIT(CM_SWDT->SR, u32Flag); + /* Waiting for FLAG bit clear */ + u32Count = SWDT_CLR_FLAG_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32_BIT(CM_SWDT->SR, u32Flag)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_SWDT_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr0.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr0.c new file mode 100644 index 0000000000..0cb858b1fe --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr0.c @@ -0,0 +1,626 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr0.c + * @brief This file provides firmware functions to manage the TMR0 + * (TMR0). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmr0.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMR0 TMR0 + * @brief TMR0 Driver Library + * @{ + */ + +#if (LL_TMR0_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR0_Local_Macros TMR0 Local Macros + * @{ + */ +/* Max channel number */ +#define TMR0_CH_MAX (2UL) + +#define TMR0_CLK_SRC_MASK (TMR0_BCONR_SYNSA | TMR0_BCONR_SYNCLKA | TMR0_BCONR_ASYNCLKA) +#define TMR0_BCONR_CLR_MASK (TMR0_BCONR_CAPMDA | TMR0_BCONR_CKDIVA | TMR0_BCONR_HICPA | TMR0_CLK_SRC_MASK) + +/** + * @defgroup TMR0_Register_Address TMR0 Register Address + * @{ + */ +#define TMR0_CNTR_ADDR(__UNIT__, __CH__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->CNTAR)) + ((__CH__) << 2UL)) +#define TMR0_CMPR_ADDR(__UNIT__, __CH__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->CMPAR)) + ((__CH__) << 2UL)) +/** + * @} + */ +#define TMR0_CH_OFFSET(__CH__) ((__CH__) << 4U) + +/** + * @defgroup TMR0_Check_Parameters_Validity TMR0 Check Parameters Validity + * @{ + */ +#define IS_TMR0_UNIT(x) \ +( ((x) == CM_TMR0_1) || \ + ((x) == CM_TMR0_2)) + +#define IS_TMR0_CH(x) \ +( ((x) == TMR0_CH_A) || \ + ((x) == TMR0_CH_B)) + +#define IS_TMR0_CLK_SRC(x) \ +( ((x) == TMR0_CLK_SRC_INTERN_CLK) || \ + ((x) == TMR0_CLK_SRC_SPEC_EVT) || \ + ((x) == TMR0_CLK_SRC_LRC) || \ + ((x) == TMR0_CLK_SRC_XTAL32)) + +#define IS_TMR0_CLK_DIV(x) \ +( ((x) == TMR0_CLK_DIV1) || \ + ((x) == TMR0_CLK_DIV2) || \ + ((x) == TMR0_CLK_DIV4) || \ + ((x) == TMR0_CLK_DIV8) || \ + ((x) == TMR0_CLK_DIV16) || \ + ((x) == TMR0_CLK_DIV32) || \ + ((x) == TMR0_CLK_DIV64) || \ + ((x) == TMR0_CLK_DIV128) || \ + ((x) == TMR0_CLK_DIV256) || \ + ((x) == TMR0_CLK_DIV512) || \ + ((x) == TMR0_CLK_DIV1024)) + +#define IS_TMR0_FUNC(x) \ +( ((x) == TMR0_FUNC_CMP) || \ + ((x) == TMR0_FUNC_CAPT)) + +#define IS_TMR0_INT(x) \ +( ((x) != 0U) && \ + (((x) | TMR0_INT_ALL) == TMR0_INT_ALL)) + +#define IS_TMR0_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | TMR0_FLAG_ALL) == TMR0_FLAG_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TMR0_Global_Functions TMR0 Global Functions + * @{ + */ + +/** + * @brief De-Initialize TMR0 function + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @retval None + */ +void TMR0_DeInit(CM_TMR0_TypeDef *TMR0x) +{ + uint32_t u32Ch; + __IO uint32_t *CNTR; + __IO uint32_t *CMPR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + + WRITE_REG32(TMR0x->BCONR, 0UL); + WRITE_REG32(TMR0x->STFLR, 0UL); + for (u32Ch = 0UL; u32Ch < TMR0_CH_MAX; u32Ch++) { + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CNTR, 0UL); + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CMPR, 0x0000FFFFUL); + } +} + +/** + * @brief Initialize TMR0 function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] pstcTmr0Init Pointer to a @ref stc_tmr0_init_t. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: pstcTmr0Init is NULL + */ +int32_t TMR0_Init(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, const stc_tmr0_init_t *pstcTmr0Init) +{ + __IO uint32_t *CNTR; + __IO uint32_t *CMPR; + int32_t i32Ret = LL_OK; + + if (NULL == pstcTmr0Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_CLK_SRC(pstcTmr0Init->u32ClockSrc)); + DDL_ASSERT(IS_TMR0_CLK_DIV(pstcTmr0Init->u32ClockDiv)); + DDL_ASSERT(IS_TMR0_FUNC(pstcTmr0Init->u32Func)); + + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CNTR, 0UL); + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CMPR, pstcTmr0Init->u16CompareValue); + MODIFY_REG32(TMR0x->BCONR, (TMR0_BCONR_CLR_MASK << TMR0_CH_OFFSET(u32Ch)), + ((pstcTmr0Init->u32ClockSrc | pstcTmr0Init->u32ClockDiv | + pstcTmr0Init->u32Func) << TMR0_CH_OFFSET(u32Ch))); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr0_init_t to default values. + * @param [out] pstcTmr0Init Pointer to a @ref stc_tmr0_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: pstcTmr0Init is NULL + */ +int32_t TMR0_StructInit(stc_tmr0_init_t *pstcTmr0Init) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcTmr0Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcTmr0Init->u32ClockSrc = TMR0_CLK_SRC_INTERN_CLK; + pstcTmr0Init->u32ClockDiv = TMR0_CLK_DIV1; + pstcTmr0Init->u32Func = TMR0_FUNC_CMP; + pstcTmr0Init->u16CompareValue = 0xFFFFU; + } + return i32Ret; +} + +/** + * @brief Start TMR0. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval None + */ +void TMR0_Start(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_CSTA << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Stop TMR0. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval None + */ +void TMR0_Stop(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_CSTA << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Set Tmr0 counter value. + * @note Setting the count requires stop tmr0. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u16Value The data to write to the counter register + * @retval None + */ +void TMR0_SetCountValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint32_t *CNTR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CNTR, u16Value); +} + +/** + * @brief Get Tmr0 counter value. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval uint16_t The counter register data + */ +uint16_t TMR0_GetCountValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + __IO uint32_t *CNTR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + return (uint16_t)READ_REG32(*CNTR); +} + +/** + * @brief Set Tmr0 compare value. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u16Value The data to write to the compare register + * @retval None + */ +void TMR0_SetCompareValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint32_t *CMPR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CMPR, u16Value); +} + +/** + * @brief Get Tmr0 compare value. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval The compare register data + */ +uint16_t TMR0_GetCompareValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + __IO uint32_t *CMPR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + return (uint16_t)READ_REG32(*CMPR); +} + +/** + * @brief Set clock source. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u32Src Specifies the clock source + * This parameter can be a value of the following: + * @arg @ref TMR0_Clock_Source + * @retval None + */ +void TMR0_SetClockSrc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Src) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_CLK_SRC(u32Src)); + + MODIFY_REG32(TMR0x->BCONR, (TMR0_CLK_SRC_MASK << TMR0_CH_OFFSET(u32Ch)), (u32Src << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Set the division of clock. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u32Div Specifies the clock source division + * This parameter can be a value of the following: + * @arg TMR0_CLK_DIV1: Clock source / 1 + * @arg TMR0_CLK_DIV2: Clock source / 2 + * @arg TMR0_CLK_DIV4: Clock source / 4 + * @arg TMR0_CLK_DIV8: Clock source / 8 + * @arg TMR0_CLK_DIV16: Clock source / 16 + * @arg TMR0_CLK_DIV32: Clock source / 32 + * @arg TMR0_CLK_DIV64: Clock source / 64 + * @arg TMR0_CLK_DIV128: Clock source / 128 + * @arg TMR0_CLK_DIV256: Clock source / 256 + * @arg TMR0_CLK_DIV512: Clock source / 512 + * @arg TMR0_CLK_DIV1024: Clock source / 1024 + * @retval None. + */ +void TMR0_SetClockDiv(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Div) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_CLK_DIV(u32Div)); + + MODIFY_REG32(TMR0x->BCONR, (TMR0_BCONR_CKDIVA << TMR0_CH_OFFSET(u32Ch)), (u32Div << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Set Tmr0 Function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u32Func Select TMR0 function + * This parameter can be a value of the following: + * @arg TMR0_FUNC_CMP: Select the Compare function for TMR0 + * @arg TMR0_FUNC_CAPT: Select the Capture function for TMR0 + * @retval None + */ +void TMR0_SetFunc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Func) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_FUNC(u32Func)); + + MODIFY_REG32(TMR0x->BCONR, ((TMR0_BCONR_CAPMDA | TMR0_BCONR_HICPA) << TMR0_CH_OFFSET(u32Ch)), + (u32Func << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Enable or disable HardWare trigger capture function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWCaptureCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HICPA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HICPA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable HardWare trigger start function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWStartCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTAA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTAA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable HardWare trigger stop function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWStopCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTPA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTPA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable HardWare trigger clear function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWClearCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HCLEA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HCLEA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable specified Tmr0 interrupt. + * @note The comparison matching interrupt of channel 'TMR0_INT_CMP_A' in unit 'CM_TMR0_1' of 'HC32F460,HC32F451,HC32F452'. + * is only available in asynchronous counting mode. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32IntType TMR0 interrupt type + * This parameter can be any combination value of the following values: + * @arg @ref TMR0_Interrupt. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_IntCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(TMR0x->BCONR, u32IntType); + } else { + CLR_REG32_BIT(TMR0x->BCONR, u32IntType); + } +} + +/** + * @brief Get Tmr0 status. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Flag TMR0 flag type + * This parameter can be any combination value of the following values: + * @arg @ref TMR0_FLAG + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMR0_GetStatus(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(TMR0x->STFLR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear Tmr0 status. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Flag TMR0 flag type + * This parameter can be any combination value of the following values: + * @arg @ref TMR0_FLAG + * @retval None + */ +void TMR0_ClearStatus(CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_FLAG(u32Flag)); + + CLR_REG32_BIT(TMR0x->STFLR, u32Flag); +} + +/** + * @} + */ + +#endif /* LL_TMR0_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr4.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr4.c new file mode 100644 index 0000000000..d5bb84f977 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr4.c @@ -0,0 +1,2179 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr4.c + * @brief This file provides firmware functions to manage the TMR4(Timer4) + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmr4.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMR4 TMR4 + * @brief TMR4 Driver Library + * @{ + */ + +#if (LL_TMR4_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR4_Local_Macros TMR4 Local Macros + * @{ + */ + +/** + * @defgroup TMR4_Check_Parameters_Validity TMR4 Check Parameters Validity + * @{ + */ +#define IS_TMR4_UNIT(x) \ +( ((x) == CM_TMR4_1) || \ + ((x) == CM_TMR4_2) || \ + ((x) == CM_TMR4_3)) + +#define IS_TMR4_CLK_DIV(x) \ +( ((x) == TMR4_CLK_DIV1) || \ + ((x) == TMR4_CLK_DIV2) || \ + ((x) == TMR4_CLK_DIV4) || \ + ((x) == TMR4_CLK_DIV8) || \ + ((x) == TMR4_CLK_DIV16) || \ + ((x) == TMR4_CLK_DIV32) || \ + ((x) == TMR4_CLK_DIV64) || \ + ((x) == TMR4_CLK_DIV128) || \ + ((x) == TMR4_CLK_DIV256) || \ + ((x) == TMR4_CLK_DIV512) || \ + ((x) == TMR4_CLK_DIV1024)) + +#define IS_TMR4_MD(x) \ +( ((x) == TMR4_MD_SAWTOOTH) || \ + ((x) == TMR4_MD_TRIANGLE)) + +#define IS_TMR4_CLK_SRC(x) \ +( ((x) == TMR4_CLK_SRC_INTERNCLK) || \ + ((x) == TMR4_CLK_SRC_EXTCLK)) + +#define IS_TMR4_INT_CNT_MASKTIME(x) ((x) <= TMR4_INT_CNT_MASK15) + +#define IS_TMR4_INT_CNT(x) \ +( ((x) != 0UL) && \ + (((x) | TMR4_INT_CNT_MASK) == TMR4_INT_CNT_MASK)) + +#define IS_TMR4_INT(x) \ +( ((x) != 0UL) && \ + (((x) | TMR4_INT_ALL) == TMR4_INT_ALL)) + +#define IS_TMR4_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | TMR4_FLAG_ALL) == TMR4_FLAG_ALL)) + +#define IS_TMR4_OC_HIGH_CH(x) (((x) & 0x1UL) == 0UL) +#define IS_TMR4_OC_LOW_CH(x) (((x) & 0x1UL) == 1UL) + +#define IS_TMR4_OC_BUF_OBJECT(x) \ +( ((x) != 0U) || \ + (((x) | TMR4_OC_BUF_OBJECT_MASK) == TMR4_OC_BUF_OBJECT_MASK)) + +#define IS_TMR4_OC_BUF_COND(x) \ +( ((x) == TMR4_OC_BUF_COND_IMMED) || \ + ((x) == TMR4_OC_BUF_COND_PEAK) || \ + ((x) == TMR4_OC_BUF_COND_VALLEY) || \ + ((x) == TMR4_OC_BUF_COND_PEAK_VALLEY)) + +#define IS_TMR4_OC_INVD_POLARITY(x) \ +( ((x) == TMR4_OC_INVD_LOW) || \ + ((x) == TMR4_OC_INVD_HIGH)) + +#define IS_TMR4_PWM_MD(x) \ +( ((x) == TMR4_PWM_MD_THROUGH) || \ + ((x) == TMR4_PWM_MD_DEAD_TMR) || \ + ((x) == TMR4_PWM_MD_DEAD_TMR_FILTER)) + +#define IS_TMR4_PWM_POLARITY(x) \ +( ((x) == TMR4_PWM_OXH_HOLD_OXL_HOLD) || \ + ((x) == TMR4_PWM_OXH_INVT_OXL_HOLD) || \ + ((x) == TMR4_PWM_OXH_HOLD_OXL_INVT) || \ + ((x) == TMR4_PWM_OXH_INVT_OXL_INVT)) + +#define IS_TMR4_PWM_CLK_DIV(x) (((x) | TMR4_PWM_CLK_DIV128) == TMR4_PWM_CLK_DIV128) + +#define IS_TMR4_PWM_DEADTIME_REG_IDX(x) \ +( ((x) == TMR4_PWM_PDAR_IDX) || \ + ((x) == TMR4_PWM_PDBR_IDX)) + +#define IS_TMR4_PWM_OE_EFFECT(x) \ +( ((x) == TMR4_PWM_OE_EFFECT_IMMED) || \ + ((x) == TMR4_PWM_OE_EFFECT_COUNT_PEAK) || \ + ((x) == TMR4_PWM_OE_EFFECT_COUNT_VALLEY)) + +#define IS_TMR4_PWM_PIN_MD(x) \ +( ((x) == TMR4_PWM_PIN_OUTPUT_OS) || \ + ((x) == TMR4_PWM_PIN_OUTPUT_NORMAL)) + +#define IS_TMR4_EVT_CH(x) ((x) <= TMR4_EVT_CH_WL) + +#define IS_TMR4_EVT_MATCH_COND(x) (((x) | TMR4_EVT_MATCH_CNT_ALL) == TMR4_EVT_MATCH_CNT_ALL) + +#define IS_TMR4_EVT_MASK_TYPE(x) \ +( ((x) != 0U) || \ + (((x) | TMR4_EVT_MASK_TYPE_ALL) == TMR4_EVT_MASK_TYPE_ALL)) + +#define IS_TMR4_EVT_DELAY_OBJECT(x) \ +( ((x) == TMR4_EVT_DELAY_OCCRXH) || \ + ((x) == TMR4_EVT_DELAY_OCCRXL)) + +#define IS_TMR4_EVT_MD(x) \ +( ((x) == TMR4_EVT_MD_DELAY) || \ + ((x) == TMR4_EVT_MD_CMP)) + +#define IS_TMR4_EVT_MASK(x) (((x) | TMR4_EVT_MASK15) == TMR4_EVT_MASK15) + +#define IS_TMR4_EVT_BUF_COND(x) \ +( ((x) == TMR4_EVT_BUF_COND_IMMED) || \ + ((x) == TMR4_EVT_BUF_COND_PEAK) || \ + ((x) == TMR4_EVT_BUF_COND_VALLEY) || \ + ((x) == TMR4_EVT_BUF_COND_PEAK_VALLEY)) + +#define IS_TMR4_OC_CH(x) ((x) <= TMR4_OC_CH_WL) +#define IS_TMR4_PWM_CH(x) ((x) <= TMR4_PWM_CH_W) +#define IS_TMR4_PWM_PIN(x) ((x) <= TMR4_PWM_PIN_OWL) +#define IS_TMR4_EVT_OUTPUT_EVT(x) \ +( ((x) >> TMR4_SCSR_EVTOS_POS) <= (TMR4_EVT_OUTPUT_EVT5 >> TMR4_SCSR_EVTOS_POS)) +#define IS_TMR4_EVT_OUTPUT_SIGNAL(x) ((x) <= TMR4_EVT_OUTPUT_EVT5_SIGNAL) + +#define IS_TMR4_PWM_ABNORMAL_PIN_STAT(x) ((x) <= TMR4_PWM_ABNORMAL_PIN_HOLD) +/** + * @} + */ + +/** + * @defgroup TMR4_Flag_Interrupt_Mask TMR4 Flag and Interrupt Mask + * @{ + */ +#define TMR4_FLAG_CNT_MASK (TMR4_FLAG_CNT_PEAK | TMR4_FLAG_CNT_VALLEY) +#define TMR4_INT_CNT_MASK (TMR4_INT_CNT_PEAK | TMR4_INT_CNT_VALLEY) + +#define TMR4_FLAG_OC_MASK (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL | TMR4_FLAG_OC_CMP_VH | \ + TMR4_FLAG_OC_CMP_VL | TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL) +#define TMR4_INT_OC_MASK (TMR4_INT_OC_CMP_UH | TMR4_INT_OC_CMP_UL | TMR4_INT_OC_CMP_VH | \ + TMR4_INT_OC_CMP_VL | TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL) + +#define TMR4_FLAG_RELOAD_TMR_MASK (TMR4_FLAG_RELOAD_TMR_U | TMR4_FLAG_RELOAD_TMR_V | TMR4_FLAG_RELOAD_TMR_W) +#define TMR4_INT_RELOAD_TMR_MASK (TMR4_INT_RELOAD_TMR_U | TMR4_INT_RELOAD_TMR_V | TMR4_INT_RELOAD_TMR_W) + +/** + * @} + */ + +/** + * @defgroup TMR4_Registers_Reset_Value TMR4 Registers Reset Value + * @{ + */ +#define TMR4_CCSR_RST_VALUE (0x0040U) +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Buffer_Object_Mask TMR4 OC Buffer Object Mask + * @{ + */ +#define TMR4_OC_BUF_OBJECT_MASK (TMR4_OC_BUF_CMP_VALUE | TMR4_OC_BUF_CMP_MD) +/** + * @} + */ + +/** + * @defgroup TMR4_OCSR_Bit_Mask TMR4_OCSR Bit Mask + * @brief Get the specified TMR4_OCSR register bis value of the specified TMR4 OC channel + * @note The parameter CH value is TMR4_OC_CH_xy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_OCSR_OCEx_MASK(CH) (((uint16_t)TMR4_OCSR_OCEH) << ((CH) % 2UL)) +#define TMR4_OCSR_OCPx_MASK(CH) (((uint16_t)TMR4_OCSR_OCPH) << ((CH) % 2UL)) +#define TMR4_OCSR_OCIE_MASK (TMR4_OCSR_OCIEH | TMR4_OCSR_OCIEL) +#define TMR4_OCSR_OCF_MASK (TMR4_OCSR_OCFH | TMR4_OCSR_OCFL) +#define TMR4_OCSR_MASK(CH) \ +( ((uint16_t)(TMR4_OCSR_OCEH | TMR4_OCSR_OCPH | TMR4_OCSR_OCIEH | TMR4_OCSR_OCFH)) << (((CH) % 2UL))) +/** + * @} + */ + +/** + * @defgroup TMR4_OCSR_Bit TMR4_OCSR Bit + * @brief Get the specified TMR4_OCSR register bis value of the specified TMR4 OC channel + * @note The parameter CH value is TMR4_OC_CH_xy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_OCSR_OCEx(CH, OCEx) (((uint16_t)OCEx) << (((uint16_t)((CH) % 2UL)) + TMR4_OCSR_OCEH_POS)) +#define TMR4_OCSR_OCPx(CH, OCPx) (((uint16_t)OCPx) << ((CH) % 2UL)) +#define TMR4_OCSR_OCIEx(CH, OCIEx) (((uint16_t)OCIEx) << ((CH) % 2UL)) +#define TMR4_OCSR_OCFx(CH, OCFx) (((uint16_t)OCFx) << ((CH) % 2UL)) +/** + * @} + */ + +/** + * @defgroup TMR4_OCER_Bit_Mask TMR4_OCER Bit Mask + * @brief Get the specified TMR4_OCER register bis value of the specified TMR4 OC channel + * @note The parameter CH value is TMR4_OC_CH_xy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_OCER_CxBUFEN_MASK(CH) (((uint16_t)TMR4_OCER_CHBUFEN) << (((CH) % 2UL) << 1U)) +#define TMR4_OCER_MxBUFEN_MASK(CH) (((uint16_t)TMR4_OCER_MHBUFEN) << (((CH) % 2UL) << 1U)) +#define TMR4_OCER_LMCx_MASK(CH) (((uint16_t)TMR4_OCER_LMCH) << ((CH) % 2UL)) +#define TMR4_OCER_LMMx_MASK(CH) (((uint16_t)TMR4_OCER_LMMH) << ((CH) % 2UL)) +#define TMR4_OCER_MCECx_MASK(CH) (((uint16_t)TMR4_OCER_MCECH) << ((CH) % 2UL)) +#define TMR4_OCER_MASK(CH) \ +( (((uint16_t)(TMR4_OCER_CHBUFEN | TMR4_OCER_MHBUFEN)) << (((CH) % 2UL) << 1U)) | \ + (((uint16_t)(TMR4_OCER_LMCH | TMR4_OCER_LMMH | TMR4_OCER_MCECH)) << (((CH) % 2UL) << 1U))) +/** + * @} + */ + +/** + * @defgroup TMR4_OCER_Bit TMR4_OCER Bit + * @brief Get the specified TMR4_OCER register bis value of the specified TMR4 OC channel + * @note The parameter CH value is TMR4_OC_CH_xy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_OCER_CxBUFEN(CH, CxBUFEN) ((uint16_t)((uint16_t)(CxBUFEN) << ((((CH) % 2UL) << 1U) + TMR4_OCER_CHBUFEN_POS))) +#define TMR4_OCER_MxBUFEN(CH, MxBUFEN) ((uint16_t)((uint16_t)(MxBUFEN) << ((((CH) % 2UL) << 1U) + TMR4_OCER_MHBUFEN_POS))) +#define TMR4_OCER_LMCx(CH, LMCx) ((uint16_t)(LMCx) << ((((CH) % 2UL)) + TMR4_OCER_LMCH_POS)) +#define TMR4_OCER_LMMx(CH, LMMx) ((uint16_t)(LMMx) << ((((CH) % 2UL)) + TMR4_OCER_LMMH_POS)) +#define TMR4_OCER_MCECx(CH, MCECx) ((uint16_t)(MCECx) << ((((CH) % 2UL)) + TMR4_OCER_MCECH_POS)) +/** + * @} + */ + +/** + * @defgroup TMR4_RCSR_Bit_Mask TMR4_RCSR Bit Mask + * @brief Get the specified TMR4_RCSR register bis value of the specified TMR4 PWM channel + * @note The parameter CH value is TMR4_PWM_CH_x (x=U/V/W) + * @{ + */ +#define TMR4_RCSR_RTIDx_MASK(CH) ((uint16_t)(((uint16_t)TMR4_RCSR_RTIDU) << (CH))) +#define TMR4_RCSR_RTIFx_MASK(CH) ((uint16_t)(((uint16_t)TMR4_RCSR_RTIFU) << ((CH) << 2U))) +#define TMR4_RCSR_RTICx_MASK(CH) ((uint16_t)(((uint16_t)TMR4_RCSR_RTICU) << ((CH) << 2U))) +#define TMR4_RCSR_RTEx_MASK(CH) ((uint16_t)(((uint16_t)TMR4_RCSR_RTEU) << ((CH) << 2U))) +#define TMR4_RCSR_RTSx_MASK(CH) ((uint16_t)(((uint16_t)TMR4_RCSR_RTSU) << ((CH) << 2U))) +/** + * @} + */ + +/** + * @defgroup TMR4_Register TMR4 Register + * @{ + */ +#define TMR4_REG_ADDR(_REG_) ((uint32_t)(&(_REG_))) +#define TMR4_REG16(_ADDR_) ((__IO uint16_t *)(_ADDR_)) +#define TMR4_REG32(_ADDR_) ((__IO uint32_t *)(_ADDR_)) + +/** + * @defgroup TMR4_OC_Register_UVW TMR4 OC Register + * @brief Get the specified OC register address of the specified TMR4 unit + * @note The parameter CH value is TMR4_OC_xy (x=U/V/W, y=H/L) + * @{ + */ +#define _TMR4_OCCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCCRUH) + ((CH) << 2U)) +#define _TMR4_OCMR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCMRHUH) + ((CH) << 2U)) +#define _TMR4_OCER(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCERU) + (((CH) & 0x06UL) << 1U)) +#define _TMR4_OCSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCSRU) + (((CH) & 0x06UL) << 1U)) +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Register_UVW TMR4 PWM Register + * @brief Get the specified PWM register address of the specified TMR4 unit + * @note The parameter CH value is TMR4_PWM_CH_x (x=U/V/W) + * @{ + */ +#define _TMR4_RCSR(UNIT) TMR4_REG16(TMR4_REG_ADDR((UNIT)->RCSR)) +#define _TMR4_POCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->POCRU) + ((CH) << 2U)) +#define _TMR4_PFSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->PFSRU) + ((CH) << 3U)) +#define _TMR4_PDR(UNIT, CH, IDX) TMR4_REG16(TMR4_REG_ADDR((UNIT)->PDARU) + ((CH) << 3U) + ((IDX) << 1U)) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Register_UVW TMR4 Event Register + * @brief Get the specified event register address of the specified TMR4 unit + * @note The parameter CH value is TMR4_EVT_CH_xy (x=U/V/W, y=H/L) + * @{ + */ +#define _TMR4_SCCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCCRUH) + ((CH) << 2U)) +#define _TMR4_SCSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCSRUH) + ((CH) << 2U)) +#define _TMR4_SCMR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCMRUH) + ((CH) << 2U)) +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Register TMR4 OC Register + * @{ + */ +#define TMR4_OCCR(UNIT, CH) _TMR4_OCCR(UNIT, CH) +#define TMR4_OCMR(UNIT, CH) _TMR4_OCMR(UNIT, CH) +#define TMR4_OCER(UNIT, CH) _TMR4_OCER(UNIT, CH) +#define TMR4_OCSR(UNIT, CH) _TMR4_OCSR(UNIT, CH) +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Register TMR4 PWM Register + * @{ + */ +#define TMR4_RCSR(UNIT) _TMR4_RCSR(UNIT) +#define TMR4_POCR(UNIT, CH) _TMR4_POCR(UNIT, CH) +#define TMR4_PFSR(UNIT, CH) _TMR4_PFSR(UNIT, CH) +#define TMR4_PDR(UNIT, CH, IDX) _TMR4_PDR(UNIT, CH, IDX) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Register TMR4 Event Register + * @{ + */ +#define TMR4_SCCR(UNIT, CH) _TMR4_SCCR(UNIT, CH) +#define TMR4_SCSR(UNIT, CH) _TMR4_SCSR(UNIT, CH) +#define TMR4_SCMR(UNIT, CH) _TMR4_SCMR(UNIT, CH) +/** + * @} + */ + +/** + * @defgroup TMR4_ECER_Register EMB Expand Control Register + * @brief Get the specified EVT register address of the specified TMR4 unit + * @{ + */ +#define TMR4_ECER(UNITx) \ +( ((UNITx) == CM_TMR4_1) ? (&CM_TMR4CR->ECER1) : \ + (((UNITx) == CM_TMR4_2) ? (&CM_TMR4CR->ECER2) : (&CM_TMR4CR->ECER3))) +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup TMR4_Global_Functions TMR4 Global Functions + * @{ + */ + +/** + * @defgroup TMR4_Counter_Global_Functions TMR4 Counter Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_init_t to default values + * @param [out] pstcTmr4Init Pointer to a @ref stc_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCntInit value is NULL. + */ +int32_t TMR4_StructInit(stc_tmr4_init_t *pstcTmr4Init) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4Init) { + pstcTmr4Init->u16PeriodValue = 0xFFFFU; + pstcTmr4Init->u16CountMode = TMR4_MD_SAWTOOTH; + pstcTmr4Init->u16ClockSrc = TMR4_CLK_SRC_INTERNCLK; + pstcTmr4Init->u16ClockDiv = TMR4_CLK_DIV1; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] pstcTmr4Init Pointer to a @ref stc_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCntInit value is NULL. + */ +int32_t TMR4_Init(CM_TMR4_TypeDef *TMR4x, const stc_tmr4_init_t *pstcTmr4Init) +{ + uint16_t u16Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4Init) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_CLK_SRC(pstcTmr4Init->u16ClockSrc)); + DDL_ASSERT(IS_TMR4_CLK_DIV(pstcTmr4Init->u16ClockDiv)); + DDL_ASSERT(IS_TMR4_MD(pstcTmr4Init->u16CountMode)); + + /* Set TMR4_CCSR */ + u16Value = (pstcTmr4Init->u16ClockDiv | pstcTmr4Init->u16ClockSrc | \ + pstcTmr4Init->u16CountMode | TMR4_CCSR_CLEAR | TMR4_CCSR_STOP); + WRITE_REG16(TMR4x->CCSR, u16Value); + + /* Set TMR4_CVPR: default value */ + WRITE_REG16(TMR4x->CVPR, 0x0000U); + + /* Set TMR4 period */ + WRITE_REG16(TMR4x->CPSR, pstcTmr4Init->u16PeriodValue); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize TMR4 counter function + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval None + */ +void TMR4_DeInit(CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + /* Configures the registers to reset value. */ + WRITE_REG16(TMR4x->CCSR, TMR4_CCSR_RST_VALUE); + WRITE_REG16(TMR4x->CPSR, 0xFFFFU); + WRITE_REG16(TMR4x->CVPR, 0x0000U); +} + +/** + * @brief Set TMR4 counter clock source + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Src TMR4 counter clock source + * This parameter can be one of the macros group @ref TMR4_Count_Clock_Source + * @arg TMR4_CLK_SRC_INTERNCLK: Uses the internal clock as counter's count clock + * @arg TMR4_CLK_SRC_EXTCLK: Uses an external input clock as counter's count clock + * @retval None + * @note The clock division function is valid when clock source is internale clock. + */ +void TMR4_SetClockSrc(CM_TMR4_TypeDef *TMR4x, uint16_t u16Src) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_CLK_SRC(u16Src)); + + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_ECKEN, u16Src); +} + +/** + * @brief Set TMR4 counter clock division + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Div TMR4 clock division + * This parameter can be one of the macros group @ref TMR4_Count_Clock_Division + * @arg TMR4_CLK_DIV1: CLK + * @arg TMR4_CLK_DIV2: CLK/2 + * @arg TMR4_CLK_DIV4: CLK/4 + * @arg TMR4_CLK_DIV8: CLK/8 + * @arg TMR4_CLK_DIV16: CLK/16 + * @arg TMR4_CLK_DIV32: CLK/32 + * @arg TMR4_CLK_DIV64: CLK/64 + * @arg TMR4_CLK_DIV128: CLK/128 + * @arg TMR4_CLK_DIV256: CLK/256 + * @arg TMR4_CLK_DIV512: CLK/512 + * @arg TMR4_CLK_DIV1024: CLK/1024 + * @retval None + * @note The clock division function is valid when clock source is the internal clock. + */ +void TMR4_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint16_t u16Div) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_CLK_DIV(u16Div)); + + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_CKDIV, u16Div); +} + +/** + * @brief Set TMR4 counter count mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Mode TMR4 counter count mode + * This parameter can be one of the macros group @ref TMR4_Count_Mode + * @arg TMR4_MD_SAWTOOTH: TMR4 count mode sawtooth wave + * @arg TMR4_MD_TRIANGLE: TMR4 count mode triangular + * @retval None + */ +void TMR4_SetCountMode(CM_TMR4_TypeDef *TMR4x, uint16_t u16Mode) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_MD(u16Mode)); + + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_MODE, u16Mode); +} + +/** + * @brief Get the period value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval The period value of the TMR4 counter + */ +uint16_t TMR4_GetPeriodValue(const CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + return READ_REG16(TMR4x->CPSR); +} + +/** + * @brief Set the period value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Value The period value of the TMR4 counter + * @arg number of 16bit + * @retval None + */ +void TMR4_SetPeriodValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + WRITE_REG16(TMR4x->CPSR, u16Value); +} + +/** + * @brief Get the count value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval The count value of the TMR4 counter + */ +uint16_t TMR4_GetCountValue(const CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + return READ_REG16(TMR4x->CNTR); +} + +/** + * @brief Set the count value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Value The count value of the TMR4 counter + * @arg number of 16bit + * @retval None + */ +void TMR4_SetCountValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + WRITE_REG16(TMR4x->CNTR, u16Value); +} + +/** + * @brief Clear TMR4 counter count value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval None + */ +void TMR4_ClearCountValue(CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_CLEAR); +} + +/** + * @brief Start TMR4 counter + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval None + */ +void TMR4_Start(CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + CLR_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_STOP); +} + +/** + * @brief Stop TMR4 counter + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval None + */ +void TMR4_Stop(CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_STOP); +} + +/** + * @brief Clear TMR4 flag + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Flag TMR4 flag + * This parameter can be any composed value of the macros group @ref TMR4_Flag + * @retval None + */ +void TMR4_ClearStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag) +{ + uint32_t u32ClearFlag; + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_FLAG(u32Flag)); + + /* Counter flag */ + if ((u32Flag & TMR4_FLAG_CNT_MASK) > 0UL) { + CLR_REG16_BIT(TMR4x->CCSR, (u32Flag & TMR4_FLAG_CNT_MASK)); + } + + /* Output-compare flag */ + u32ClearFlag = (u32Flag & TMR4_FLAG_OC_MASK); + if (u32ClearFlag > 0UL) { + /* TMR4_OCSRU */ + u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL)) >> 10U); + if (u32ClearFlag > 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH); + CLR_REG16_BIT(*OCSR, u32ClearFlag); + } + + /* TMR4_OCSRV */ + u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL)) >> 12U); + if (u32ClearFlag > 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH); + CLR_REG16_BIT(*OCSR, u32ClearFlag); + } + + /* TMR4_OCSRW */ + u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL)) >> 14U); + if (u32ClearFlag > 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH); + CLR_REG16_BIT(*OCSR, u32ClearFlag); + } + } + + /* PWM reload timer flag */ + u32ClearFlag = ((u32Flag & TMR4_FLAG_RELOAD_TMR_MASK) << 5U); + if (u32ClearFlag > 0UL) { + SET_REG16_BIT(TMR4x->RCSR, u32ClearFlag); + } + +} + +/** + * @brief Get TMR4 flag + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Flag TMR4 flag + * This parameter can be any composed value of the macros group @ref TMR4_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMR4_GetStatus(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag) +{ + uint32_t u32ReadFlag; + uint8_t u8FlagSetCount = 0; + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_FLAG(u32Flag)); + + /* Counter flag status */ + if (READ_REG16_BIT(TMR4x->CCSR, (u32Flag & TMR4_FLAG_CNT_MASK)) > 0U) { + u8FlagSetCount++; + } + + /* Output-compare interrupt */ + u32ReadFlag = (u32Flag & TMR4_FLAG_OC_MASK); + if (u32ReadFlag > 0UL) { + /* TMR4_OCSRU */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL)) >> 10U); + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH); + if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + + /* TMR4_OCSRV */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL)) >> 12U); + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH); + if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + + /* TMR4_OCSRW */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL)) >> 14U); + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH); + if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + } + + /* PWM reload timer flag status */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_RELOAD_TMR_MASK)) << 4U); + if (READ_REG16_BIT(TMR4x->RCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + + return (u8FlagSetCount == 0U) ? RESET : SET; +} + +/** + * @brief Enable or disable the specified TMR4 interrupt + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32IntType TMR4 interrupt source + * This parameter can be any composed value of the macros group @ref TMR4_Interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_IntCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32Type; + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Counter interrupt */ + u32Type = (u32IntType & TMR4_INT_CNT_MASK); + if (u32Type > 0UL) { + (ENABLE == enNewState) ? SET_REG16_BIT(TMR4x->CCSR, u32Type) : CLR_REG16_BIT(TMR4x->CCSR, u32Type); + } + + /* Output-compare interrupt */ + u32Type = (u32IntType & TMR4_INT_OC_MASK); + if (u32Type > 0UL) { + /* TMR4_OCSRU */ + u32Type = ((u32IntType & (TMR4_INT_OC_CMP_UH | TMR4_INT_OC_CMP_UL)) >> 12U); + if (u32Type != 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH); + (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type); + } + + /* TMR4_OCSRV */ + u32Type = ((u32IntType & (TMR4_INT_OC_CMP_VH | TMR4_INT_OC_CMP_VL)) >> 14U); + if (u32Type != 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH); + (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type); + } + + /* TMR4_OCSRW */ + u32Type = ((u32IntType & (TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL)) >> 16U); + if (u32Type != 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH); + (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type); + } + } + + /* PWM reload timer interrupt */ + u32Type = (u32IntType & TMR4_INT_RELOAD_TMR_MASK); + if (u32Type > 0UL) { + (ENABLE == enNewState) ? CLR_REG16_BIT(TMR4x->RCSR, u32Type) : SET_REG16_BIT(TMR4x->RCSR, u32Type); + } + +} + +/** + * @brief Enable or disable the TMR4 counter period buffer function. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_PeriodBufCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_BUFEN); + } else { + CLR_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_BUFEN); + } +} + +/** + * @brief Get TMR4 count interrupt mask times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16IntType TMR4 interrupt source + * This parameter can be one of the following values: + * @arg TMR4_INT_CNT_PEAK: Count peak interrupt + * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt + * @retval Returned value can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time + * - TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak + * - TMR4_INT_CNT_MASK1: Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skiping 1 count) + * - TMR4_INT_CNT_MASK2: Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skiping 2 count) + * - TMR4_INT_CNT_MASK3: Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skiping 3 count) + * - TMR4_INT_CNT_MASK4: Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skiping 4 count) + * - TMR4_INT_CNT_MASK5: Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skiping 5 count) + * - TMR4_INT_CNT_MASK6: Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skiping 6 count) + * - TMR4_INT_CNT_MASK7: Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skiping 7 count) + * - TMR4_INT_CNT_MASK8: Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skiping 8 count) + * - TMR4_INT_CNT_MASK9: Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skiping 9 count) + * - TMR4_INT_CNT_MASK10: Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skiping 10 count) + * - TMR4_INT_CNT_MASK11: Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skiping 11 count) + * - TMR4_INT_CNT_MASK12: Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skiping 12 count) + * - TMR4_INT_CNT_MASK13: Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skiping 13 count) + * - TMR4_INT_CNT_MASK14: Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skiping 14 count) + * - TMR4_INT_CNT_MASK15: Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skiping 15 count) + */ +uint16_t TMR4_GetCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint16_t u16IntType) +{ + uint16_t u16MaskTimes; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT_CNT(u16IntType)); + + if (TMR4_INT_CNT_VALLEY == u16IntType) { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_ZIM) >> TMR4_CVPR_ZIM_POS); + } else { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_PIM) >> TMR4_CVPR_PIM_POS); + } + + return u16MaskTimes; +} + +/** + * @brief Set TMR4 counter interrupt mask times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32IntType TMR4 interrupt source + * This parameter can be one of the following values: + * @arg TMR4_INT_CNT_PEAK: Count peak interrupt + * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt + * @param [in] u16MaskTime TMR4 counter interrupt mask times + * This parameter can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time + * @arg TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak + * @arg TMR4_INT_CNT_MASK1: Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skiping 1 count) + * @arg TMR4_INT_CNT_MASK2: Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skiping 2 count) + * @arg TMR4_INT_CNT_MASK3: Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skiping 3 count) + * @arg TMR4_INT_CNT_MASK4: Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skiping 4 count) + * @arg TMR4_INT_CNT_MASK5: Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skiping 5 count) + * @arg TMR4_INT_CNT_MASK6: Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skiping 6 count) + * @arg TMR4_INT_CNT_MASK7: Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skiping 7 count) + * @arg TMR4_INT_CNT_MASK8: Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skiping 8 count) + * @arg TMR4_INT_CNT_MASK9: Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skiping 9 count) + * @arg TMR4_INT_CNT_MASK10: Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skiping 10 count) + * @arg TMR4_INT_CNT_MASK11: Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skiping 11 count) + * @arg TMR4_INT_CNT_MASK12: Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skiping 12 count) + * @arg TMR4_INT_CNT_MASK13: Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skiping 13 count) + * @arg TMR4_INT_CNT_MASK14: Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skiping 14 count) + * @arg TMR4_INT_CNT_MASK15: Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skiping 15 count) + * @retval None + */ +void TMR4_SetCountIntMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, uint16_t u16MaskTime) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT_CNT(u32IntType)); + DDL_ASSERT(IS_TMR4_INT_CNT_MASKTIME(u16MaskTime)); + + if (TMR4_INT_CNT_VALLEY == (u32IntType & TMR4_INT_CNT_VALLEY)) { + MODIFY_REG16(TMR4x->CVPR, TMR4_CVPR_ZIM, (u16MaskTime << TMR4_CVPR_ZIM_POS)); + } + + if (TMR4_INT_CNT_PEAK == (u32IntType & TMR4_INT_CNT_PEAK)) { + MODIFY_REG16(TMR4x->CVPR, TMR4_CVPR_PIM, (u16MaskTime << TMR4_CVPR_PIM_POS)); + } +} + +/** + * @brief Get TMR4 counter current interrupt mask times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16IntType TMR4 interrupt source + * This parameter can be one of the macros group @ref TMR4_Interrupt + * @arg TMR4_INT_CNT_PEAK: Count peak interrupt + * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt + * @retval Returned value can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time + * - TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for every counter count at "0x0000" or peak + * - TMR4_INT_CNT_MASK1: Counter interrupt flag is set once for 2 every counter counts at "0x0000" or peak (skiping 1 count) + * - TMR4_INT_CNT_MASK2: Counter interrupt flag is set once for 3 every counter counts at "0x0000" or peak (skiping 2 count) + * - TMR4_INT_CNT_MASK3: Counter interrupt flag is set once for 4 every counter counts at "0x0000" or peak (skiping 3 count) + * - TMR4_INT_CNT_MASK4: Counter interrupt flag is set once for 5 every counter counts at "0x0000" or peak (skiping 4 count) + * - TMR4_INT_CNT_MASK5: Counter interrupt flag is set once for 6 every counter counts at "0x0000" or peak (skiping 5 count) + * - TMR4_INT_CNT_MASK6: Counter interrupt flag is set once for 7 every counter counts at "0x0000" or peak (skiping 6 count) + * - TMR4_INT_CNT_MASK7: Counter interrupt flag is set once for 8 every counter counts at "0x0000" or peak (skiping 7 count) + * - TMR4_INT_CNT_MASK8: Counter interrupt flag is set once for 9 every counter counts at "0x0000" or peak (skiping 8 count) + * - TMR4_INT_CNT_MASK9: Counter interrupt flag is set once for 10 every counter counts at "0x0000" or peak (skiping 9 count) + * - TMR4_INT_CNT_MASK10: Counter interrupt flag is set once for 11 every counter counts at "0x0000" or peak (skiping 10 count) + * - TMR4_INT_CNT_MASK11: Counter interrupt flag is set once for 12 every counter counts at "0x0000" or peak (skiping 11 count) + * - TMR4_INT_CNT_MASK12: Counter interrupt flag is set once for 13 every counter counts at "0x0000" or peak (skiping 12 count) + * - TMR4_INT_CNT_MASK13: Counter interrupt flag is set once for 14 every counter counts at "0x0000" or peak (skiping 13 count) + * - TMR4_INT_CNT_MASK14: Counter interrupt flag is set once for 15 every counter counts at "0x0000" or peak (skiping 14 count) + * - TMR4_INT_CNT_MASK15: Counter interrupt flag is set once for 16 every counter counts at "0x0000" or peak (skiping 15 count) + */ +uint16_t TMR4_GetCurrentCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint16_t u16IntType) +{ + uint16_t u16MaskTimes; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT_CNT(u16IntType)); + + if (TMR4_INT_CNT_VALLEY == u16IntType) { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_ZIC) >> TMR4_CVPR_ZIC_POS); + } else { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_PIC) >> TMR4_CVPR_PIC_POS); + } + + return u16MaskTimes; +} + +/** + * @} + */ + +/** + * @defgroup TMR4_Output_Compare_Global_Functions TMR4 Output-Compare Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_oc_init_t to default values + * @param [out] pstcTmr4OcInit Pointer to a @ref stc_tmr4_oc_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4OcInit value is NULL. + */ +int32_t TMR4_OC_StructInit(stc_tmr4_oc_init_t *pstcTmr4OcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4OcInit) { + pstcTmr4OcInit->u16CompareValue = 0U; + pstcTmr4OcInit->u16OcInvalidPolarity = TMR4_OC_INVD_LOW; + pstcTmr4OcInit->u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED; + pstcTmr4OcInit->u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED; + pstcTmr4OcInit->u16BufLinkTransObject = 0U; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 OC + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] pstcTmr4OcInit Pointer to a @ref stc_tmr4_oc_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4OcInit value is NULL. + */ +int32_t TMR4_OC_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_oc_init_t *pstcTmr4OcInit) +{ + uint16_t u16Value; + __IO uint16_t *OCER; + __IO uint16_t *OCSR; + __IO uint16_t *OCCR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4OcInit) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_INVD_POLARITY(pstcTmr4OcInit->u16OcInvalidPolarity)); + DDL_ASSERT(IS_TMR4_OC_BUF_COND(pstcTmr4OcInit->u16CompareModeBufCond)); + DDL_ASSERT(IS_TMR4_OC_BUF_COND(pstcTmr4OcInit->u16CompareValueBufCond)); + DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(pstcTmr4OcInit->u16BufLinkTransObject)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + OCER = TMR4_OCER(TMR4x, u32Ch); + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + /* Set output polarity when OC is disabled. */ + MODIFY_REG16(*OCSR, TMR4_OCSR_MASK(u32Ch), TMR4_OCSR_OCPx(u32Ch, pstcTmr4OcInit->u16OcInvalidPolarity)); + + /* Set OCMR&&OCCR buffer function */ + u16Value = (TMR4_OCER_MxBUFEN(u32Ch, pstcTmr4OcInit->u16CompareModeBufCond) | \ + TMR4_OCER_CxBUFEN(u32Ch, pstcTmr4OcInit->u16CompareValueBufCond)); + if (TMR4_OC_BUF_CMP_VALUE == (pstcTmr4OcInit->u16BufLinkTransObject & TMR4_OC_BUF_CMP_VALUE)) { + u16Value |= TMR4_OCER_LMCx_MASK(u32Ch); + } + + if (TMR4_OC_BUF_CMP_MD == (pstcTmr4OcInit->u16BufLinkTransObject & TMR4_OC_BUF_CMP_MD)) { + u16Value |= TMR4_OCER_LMMx_MASK(u32Ch); + } + + MODIFY_REG16(*OCER, TMR4_OCER_MASK(u32Ch), u16Value); + + /* Set OC compare value */ + WRITE_REG16(*OCCR, pstcTmr4OcInit->u16CompareValue); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initialize TMR4 OC + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval None + */ +void TMR4_OC_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *OCER; + __IO uint16_t *OCSR; + __IO uint16_t *OCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + OCER = TMR4_OCER(TMR4x, u32Ch); + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + /* Clear bits: port output valid && OP level && interrupt */ + CLR_REG16_BIT(*OCSR, TMR4_OCSR_MASK(u32Ch)); + + /* Clear bits: OCMR&&OCCR buffer */ + CLR_REG16_BIT(*OCER, TMR4_OCER_MASK(u32Ch)); + + /* Set OC compare match value */ + WRITE_REG16(*OCCR, 0x0000U); +} + +/** + * @brief Get TMR4 OC OCCR compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval The compare value of the TMR4 OC OCCR register + */ +uint16_t TMR4_OC_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *OCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + return READ_REG16(*OCCR); +} + +/** + * @brief Set TMR4 OC compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Value The compare value of the TMR4 OC OCCR register + * @arg number of 16bit + * @retval None + */ +void TMR4_OC_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint16_t *OCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + WRITE_REG16(*OCCR, u16Value); +} + +/** + * @brief Enable or disable the TMR4 OC of the specified channel. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_OC_Cmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + + /* Set OCSR port output compare */ + MODIFY_REG16(*OCSR, TMR4_OCSR_OCEx_MASK(u32Ch), TMR4_OCSR_OCEx(u32Ch, enNewState)); +} + +/** + * @brief Extend the matching conditions of TMR4 OC channel + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_OC_ExtendControlCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint16_t *OCER; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get pointer of current channel OC register address */ + OCER = TMR4_OCER(TMR4x, u32Ch); + + /* Set OCER register: Extend match function */ + MODIFY_REG16(*OCER, TMR4_OCER_MCECx_MASK(u32Ch), TMR4_OCER_MCECx(u32Ch, enNewState)); +} + +/** + * @brief Set TMR4 OC OCCR/OCMR buffer interval response function + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Object TMR4 OC register buffer: OCCR/OCMR + * This parameter can be one of the macros group @ref TMR4_OC_Buffer_Object + * @arg TMR4_OC_BUF_CMP_VALUE: The register OCCR buffer function + * @arg TMR4_OC_BUF_CMP_MD: The register OCMR buffer function + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Enable the OCMR/OCMR register buffer function. + * @arg DISABLE: Disable the OCMR/OCMR register buffer function. + * @retval None + */ +void TMR4_OC_BufIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16Object, en_functional_state_t enNewState) +{ + __IO uint16_t *OCER; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(u16Object)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get pointer of current channel OC register address */ + OCER = TMR4_OCER(TMR4x, u32Ch); + + if (TMR4_OC_BUF_CMP_VALUE == (u16Object & TMR4_OC_BUF_CMP_VALUE)) { + /* Set OCER register: OCCR link transfer function */ + MODIFY_REG16(*OCER, TMR4_OCER_LMCx_MASK(u32Ch), TMR4_OCER_LMCx(u32Ch, enNewState)); + } + + if (TMR4_OC_BUF_CMP_MD == (u16Object & TMR4_OC_BUF_CMP_MD)) { + /* Set OCER register: OCMR link transfer function */ + MODIFY_REG16(*OCER, TMR4_OCER_LMMx_MASK(u32Ch), TMR4_OCER_LMMx(u32Ch, enNewState)); + } +} + +/** + * @brief Get TMR4 OC output current polarity + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval Returned value can be one of the macros group @ref TMR4_OC_Invalid_Output_Polarity + * - TMR4_OC_INVD_LOW: TMR4 OC output low level when OC is invalid + * - TMR4_OC_INVD_HIGH: TMR4 OC output high level when OC is invalid + */ +uint16_t TMR4_OC_GetPolarity(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *OCSR; + uint16_t u16Polarity; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + + /* Get OCSR register: OC output polarity */ + u16Polarity = READ_REG16_BIT(*OCSR, TMR4_OCSR_OCPx_MASK(u32Ch)); + return (u16Polarity >> (u32Ch % 2UL)); +} + +/** + * @brief Set TMR4 OC invalid output polarity + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Polarity TMR4 OC invalid output polarity. + * This parameter can be one of the macros group @ref TMR4_OC_Invalid_Output_Polarity + * @arg TMR4_OC_INVD_LOW: TMR4 OC output low level when OC is invalid + * @arg TMR4_OC_INVD_HIGH: TMR4 OC output high level when OC is invalid + * @retval None + */ +void TMR4_OC_SetOcInvalidPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity) +{ + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_INVD_POLARITY(u16Polarity)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + + /* Set OCSR register: OC invalid output polarity */ + MODIFY_REG16(*OCSR, TMR4_OCSR_OCPx_MASK(u32Ch), TMR4_OCSR_OCPx(u32Ch, u16Polarity)); +} + +/** + * @brief Set TMR4 OC OCCR/OCMR buffer transfer condition + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Object TMR4 OC register buffer type: OCCR/OCMR + * This parameter can be one of the macros group @ref TMR4_OC_Buffer_Object + * @arg TMR4_OC_BUF_CMP_VALUE: The register OCCR buffer function + * @arg TMR4_OC_BUF_CMP_MD: The register OCMR buffer function + * @param [in] u16BufCond TMR4 OC OCCR/OCMR buffer transfer condition + * This parameter can be one of the macros group @ref TMR4_OC_Buffer_Transfer_Condition + * @arg TMR4_OC_BUF_COND_IMMED: Buffer transfer is made when writing to the OCCR/OCMR register. + * @arg TMR4_OC_BUF_COND_VALLEY: Buffer transfer is made when counter count valley. + * @arg TMR4_OC_BUF_COND_PEAK: Buffer transfer is made when counter count peak. + * @arg TMR4_OC_BUF_COND_PEAK_VALLEY: Buffer transfer is made when counter count peak or valley. + * @retval None + */ +void TMR4_OC_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object, uint16_t u16BufCond) +{ + __IO uint16_t *OCER; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(u16Object)); + DDL_ASSERT(IS_TMR4_OC_BUF_COND(u16BufCond)); + + /* Get pointer of current channel OC register address */ + OCER = TMR4_OCER(TMR4x, u32Ch); + + if (TMR4_OC_BUF_CMP_VALUE == (u16Object & TMR4_OC_BUF_CMP_VALUE)) { + /* Set OCER register: OCCR buffer mode */ + MODIFY_REG16(*OCER, TMR4_OCER_CxBUFEN_MASK(u32Ch), TMR4_OCER_CxBUFEN(u32Ch, u16BufCond)); + } + + if (TMR4_OC_BUF_CMP_MD == (u16Object & TMR4_OC_BUF_CMP_MD)) { + /* Set OCER register: OCMR buffer mode */ + MODIFY_REG16(*OCER, TMR4_OCER_MxBUFEN_MASK(u32Ch), TMR4_OCER_MxBUFEN(u32Ch, u16BufCond)); + } +} + +/** + * @brief Get the TMR4 OC high channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the following values: + * @retval The TMR4 OC high channel mode + * @note The function only can get low channel mode:TMR4_OC_CH_xH(x = U/V/W) + */ +uint16_t TMR4_OC_GetHighChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *OCMRxH; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_HIGH_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxH = TMR4_OCMR(TMR4x, u32Ch); + return READ_REG16(*OCMRxH); +} + +/** + * @brief Set the TMR4 OC high channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the following values: + * @param [in] unTmr4Ocmrh The TMR4 OC high channel mode @ref un_tmr4_oc_ocmrh_t + * @retval None + * @note The function only can set low channel mode:TMR4_OC_CH_xH(x = U/V/W) + */ +void TMR4_OC_SetHighChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrh_t unTmr4Ocmrh) +{ + __IO uint16_t *OCMRxH; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_HIGH_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxH = TMR4_OCMR(TMR4x, u32Ch); + WRITE_REG16(*OCMRxH, unTmr4Ocmrh.OCMRx); +} + +/** + * @brief Get the TMR4 OC low channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the following values: + * @retval The TMR4 OC low channel mode + * @note The function only can get low channel mode:TMR4_OC_CH_xL(x = U/V/W) + */ +uint32_t TMR4_OC_GetLowChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint32_t *OCMRxL; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_LOW_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxL = (__IO uint32_t *)((uint32_t)TMR4_OCMR(TMR4x, u32Ch)); + return READ_REG32(*OCMRxL); +} + +/** + * @brief Set the TMR4 OC low channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the following values: + * @param [in] unTmr4Ocmrl The TMR4 OC low channel mode @ref un_tmr4_oc_ocmrl_t + * @retval None + * @note The function only can set low channel mode:TMR4_OC_CH_xL(x = U/V/W) + */ +void TMR4_OC_SetLowChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrl_t unTmr4Ocmrl) +{ + __IO uint32_t *OCMRxL; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_LOW_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxL = (__IO uint32_t *)((uint32_t)TMR4_OCMR(TMR4x, u32Ch)); + WRITE_REG32(*OCMRxL, unTmr4Ocmrl.OCMRx); +} + +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Global_Functions TMR4 PWM Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_pwm_init_t to default values + * @param [out] pstcTmr4PwmInit Pointer to a @ref stc_tmr4_pwm_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4PwmInit value is NULL. + */ +int32_t TMR4_PWM_StructInit(stc_tmr4_pwm_init_t *pstcTmr4PwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4PwmInit) { + pstcTmr4PwmInit->u16Mode = TMR4_PWM_MD_THROUGH; + pstcTmr4PwmInit->u16ClockDiv = TMR4_PWM_CLK_DIV1; + pstcTmr4PwmInit->u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] pstcTmr4PwmInit Pointer to a @ref stc_tmr4_pwm_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4PwmInit value is NULL. + */ +int32_t TMR4_PWM_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_pwm_init_t *pstcTmr4PwmInit) +{ + uint16_t u16Value; + __IO uint16_t *POCR; + __IO uint16_t *RCSR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4PwmInit) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_MD(pstcTmr4PwmInit->u16Mode)); + DDL_ASSERT(IS_TMR4_PWM_CLK_DIV(pstcTmr4PwmInit->u16ClockDiv)); + DDL_ASSERT(IS_TMR4_PWM_POLARITY(pstcTmr4PwmInit->u16Polarity)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + RCSR = TMR4_RCSR(TMR4x); + + /* Set POCR register */ + u16Value = (pstcTmr4PwmInit->u16Mode | pstcTmr4PwmInit->u16ClockDiv | pstcTmr4PwmInit->u16Polarity); + WRITE_REG16(*POCR, u16Value); + + /* Set RCSR register */ + u16Value = (TMR4_RCSR_RTSx_MASK(u32Ch) | TMR4_RCSR_RTIDx_MASK(u32Ch) | TMR4_RCSR_RTICx_MASK(u32Ch)); + MODIFY_REG16(*RCSR, TMR4_RCSR_RTEx_MASK(u32Ch), u16Value); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @retval None + */ +void TMR4_PWM_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *POCR; + __IO uint16_t *RCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + RCSR = TMR4_RCSR(TMR4x); + + /* Set POCR register */ + WRITE_REG16(*POCR, (TMR4_PWM_CLK_DIV1 | TMR4_PWM_MD_THROUGH | TMR4_PWM_OXH_HOLD_OXL_HOLD)); + + /* Set RCSR register */ + MODIFY_REG16(*RCSR, TMR4_RCSR_RTEx_MASK(u32Ch), \ + (TMR4_RCSR_RTIDx_MASK(u32Ch) | TMR4_RCSR_RTSx_MASK(u32Ch) | TMR4_RCSR_RTICx_MASK(u32Ch))); +} + +/** + * @brief Set TMR4 PWM clock division + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u16Div TMR4 PWM internal clock division + * This parameter can be one of the macros group @ref TMR4_PWM_Clock_Division + * @arg TMR4_PWM_CLK_DIV1: CLK + * @arg TMR4_PWM_CLK_DIV2: CLK/2 + * @arg TMR4_PWM_CLK_DIV4: CLK/4 + * @arg TMR4_PWM_CLK_DIV8: CLK/8 + * @arg TMR4_PWM_CLK_DIV16: CLK/16 + * @arg TMR4_PWM_CLK_DIV32: CLK/32 + * @arg TMR4_PWM_CLK_DIV64: CLK/64 + * @arg TMR4_PWM_CLK_DIV128: CLK/128 + * @retval None + */ +void TMR4_PWM_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Div) +{ + __IO uint16_t *POCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_CLK_DIV(u16Div)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + + MODIFY_REG16(*POCR, TMR4_POCR_DIVCK, u16Div); +} + +/** + * @brief Set TMR4 PWM output polarity. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u16Polarity TMR4 PWM output polarity + * This parameter can be one of the macros group @ref TMR4_PWM_Polarity + * @arg TMR4_PWM_OXH_HOLD_OXL_HOLD: Output PWML and PWMH signals without changing the level + * @arg TMR4_PWM_OXH_INVERT_OXL_INVERT: Output both PWML and PWMH signals reversed + * @arg TMR4_PWM_OXH_INVERT_OXL_HOLD: Output the PWMH signal reversed, outputs the PWML signal without changing the level + * @arg TMR4_PWM_OXH_HOLD_OXL_INVERT: Output the PWMH signal without changing the level, Outputs the PWML signal reversed + * @retval None + */ +void TMR4_PWM_SetPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity) +{ + __IO uint16_t *POCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_POLARITY(u16Polarity)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + + MODIFY_REG16(*POCR, TMR4_POCR_LVLS, u16Polarity); +} + +/** + * @brief Start TMR4 PWM reload-timer + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @retval None + */ +void TMR4_PWM_StartReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + SET_REG16_BIT(TMR4x->RCSR, TMR4_RCSR_RTEx_MASK(u32Ch)); +} + +/** + * @brief Stop TMR4 PWM reload-timer + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @retval None + */ +void TMR4_PWM_StopReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + SET_REG16_BIT(TMR4x->RCSR, TMR4_RCSR_RTSx_MASK(u32Ch)); +} + +/** + * @brief Set TMR4 PWM filter count value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u16Value TMR4 PWM filter count value + * @arg number of 16bit + * @retval None + */ +void TMR4_PWM_SetFilterCountValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint16_t *PFSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + PFSR = TMR4_PFSR(TMR4x, u32Ch); + + WRITE_REG16(*PFSR, u16Value); +} + +/** + * @brief Set TMR4 PWM dead time count + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u32DeadTimeIndex TMR4 PWM dead time register index + * This parameter can be one of the macros group @ref TMR4_PWM_Dead_Time_Register_Index + * @arg TMR4_PWM_PDAR_IDX: TMR4_PDARn + * @arg TMR4_PWM_PDBR_IDX: TMR4_PDBRn + * @param [in] u16Value TMR4 PWM dead time register value + * @arg number of 16bit + * @retval None + */ +void TMR4_PWM_SetDeadTimeValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex, uint16_t u16Value) +{ + __IO uint16_t *PDR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_DEADTIME_REG_IDX(u32DeadTimeIndex)); + + /* Get pointer of current channel PWM register address */ + PDR = TMR4_PDR(TMR4x, u32Ch, u32DeadTimeIndex); + + WRITE_REG16(*PDR, u16Value); +} + +/** + * @brief Get TMR4 PWM dead time count + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u32DeadTimeIndex TMR4 PWM dead time register index + * This parameter can be one of the macros group @ref TMR4_PWM_Dead_Time_Register_Index + * @arg TMR4_PWM_PDAR_IDX: TMR4_PDARn + * @arg TMR4_PWM_PDBR_IDX: TMR4_PDBRn + * @retval TMR4 PWM dead time register value + */ +uint16_t TMR4_PWM_GetDeadTimeValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex) +{ + __I uint16_t *PDR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_DEADTIME_REG_IDX(u32DeadTimeIndex)); + + /* Get pointer of current channel PWM register address */ + PDR = TMR4_PDR(TMR4x, u32Ch, u32DeadTimeIndex); + + return READ_REG16(*PDR); +} + +/** + * @brief Set TMR4 PWM pin status when below conditions occur:1.EMB 2.MOE=0 3.MOE=1&OExy=0 + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32PwmPin TMR4 PWM pin + * This parameter can be one of the macros group @ref TMR4_PWM_Pin + * @param [in] u32PinStatus TMR4 PWM pin status + * This parameter can be one of the macros group @ref TMR4_PWM_Abnormal_Pin_Status. + * @retval None + */ +void TMR4_PWM_SetAbnormalPinStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32PinStatus) +{ + __IO uint32_t *ECER; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_ABNORMAL_PIN_STAT(u32PinStatus)); + + (void)(u32PwmPin); + ECER = TMR4_ECER(TMR4x); + + if ((TMR4_PWM_ABNORMAL_PIN_HIZ == u32PinStatus) || \ + (TMR4_PWM_ABNORMAL_PIN_LOW == u32PinStatus) || \ + (TMR4_PWM_ABNORMAL_PIN_HIGH == u32PinStatus)) { + WRITE_REG32(*ECER, u32PinStatus); + } else { + if (TMR4_PWM_ABNORMAL_PIN_HOLD == u32PinStatus) { + SET_REG16_BIT(TMR4x->ECSR, TMR4_ECSR_HOLD); + } else { + CLR_REG16_BIT(TMR4x->ECSR, TMR4_ECSR_HOLD); + } + + WRITE_REG32(*ECER, 0UL); + } +} + +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Global_Functions TMR4 Event Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_evt_init_t to default values + * @param [in] pstcTmr4EventInit Pointer to a @ref stc_tmr4_evt_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4EventInit value is NULL. + */ +int32_t TMR4_EVT_StructInit(stc_tmr4_evt_init_t *pstcTmr4EventInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4EventInit) { + pstcTmr4EventInit->u16Mode = TMR4_EVT_MD_CMP; + pstcTmr4EventInit->u16CompareValue = 0U; + pstcTmr4EventInit->u16OutputEvent = TMR4_EVT_OUTPUT_EVT0; + pstcTmr4EventInit->u16MatchCond = 0U; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 event + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] pstcTmr4EventInit Pointer to a @ref stc_tmr4_evt_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4EventInit value is NULL. + */ +int32_t TMR4_EVT_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_evt_init_t *pstcTmr4EventInit) +{ + uint16_t u16Value; + __IO uint16_t *SCCR; + __IO uint16_t *SCSR; + __IO uint16_t *SCMR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4EventInit) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MD(pstcTmr4EventInit->u16Mode)); + DDL_ASSERT(IS_TMR4_EVT_OUTPUT_EVT(pstcTmr4EventInit->u16OutputEvent)); + DDL_ASSERT(IS_TMR4_EVT_MATCH_COND(pstcTmr4EventInit->u16MatchCond)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + SCSR = TMR4_SCSR(TMR4x, u32Ch); + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + /* Set SCSR register */ + u16Value = (pstcTmr4EventInit->u16Mode | pstcTmr4EventInit->u16OutputEvent | pstcTmr4EventInit->u16MatchCond); + WRITE_REG16(*SCSR, u16Value); + + /* Set SCMR register */ + WRITE_REG16(*SCMR, 0xFF00U); + + /* Set SCCR register: compare value */ + WRITE_REG16(*SCCR, pstcTmr4EventInit->u16CompareValue); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @retval None + */ +void TMR4_EVT_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *SCCR; + __IO uint16_t *SCSR; + __IO uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + SCSR = TMR4_SCSR(TMR4x, u32Ch); + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + /* Configure default parameter */ + WRITE_REG16(*SCCR, 0x0U); + WRITE_REG16(*SCSR, 0x0000U); + WRITE_REG16(*SCMR, 0xFF00U); +} + +/** + * @brief Set TMR4 event delay object + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Object TMR4 event delay object + * This parameter can be one of the macros group @ref TMR4_Event_Delay_Object + * @arg TMR4_EVT_DELAY_OCCRXH: TMR4 event delay object - OCCRxh + * @arg TMR4_EVT_DELAY_OCCRXL: TMR4 event delay object - OCCRxl + * @retval None + */ +void TMR4_EVT_SetDelayObject(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_DELAY_OBJECT(u16Object)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + /* Set SCSR register */ + MODIFY_REG16(*SCSR, TMR4_SCSR_EVTDS, u16Object); +} + +/** + * @brief Set TMR4 event trigger event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16MaskTime Mask times + * This parameter can be one of the macros group @ref TMR4_Event_Mask_Times + * @arg TMR4_EVT_MASK0: Mask 0 times + * @arg TMR4_EVT_MASK1: Mask 1 times + * @arg TMR4_EVT_MASK2: Mask 2 times + * @arg TMR4_EVT_MASK3: Mask 3 times + * @arg TMR4_EVT_MASK4: Mask 4 times + * @arg TMR4_EVT_MASK5: Mask 5 times + * @arg TMR4_EVT_MASK6: Mask 6 times + * @arg TMR4_EVT_MASK7: Mask 7 times + * @arg TMR4_EVT_MASK8: Mask 8 times + * @arg TMR4_EVT_MASK9: Mask 9 times + * @arg TMR4_EVT_MASK10: Mask 10 times + * @arg TMR4_EVT_MASK11: Mask 11 times + * @arg TMR4_EVT_MASK12: Mask 12 times + * @arg TMR4_EVT_MASK13: Mask 13 times + * @arg TMR4_EVT_MASK14: Mask 14 times + * @arg TMR4_EVT_MASK15: Mask 15 times + * @retval None + */ +void TMR4_EVT_SetMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16MaskTime) +{ + __IO uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MASK(u16MaskTime)); + + /* Get actual address of register list of current channel */ + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + /* Set SCMR register */ + MODIFY_REG16(*SCMR, TMR4_SCMR_AMC, u16MaskTime); +} + +/** + * @brief Get TMR4 event SCCR register value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @retval Returned value can be one of the macros group @ref TMR4_Event_Mask_Times + * - TMR4_EVT_MASK0: Mask 0 times + * - TMR4_EVT_MASK1: Mask 1 times + * - TMR4_EVT_MASK2: Mask 2 times + * - TMR4_EVT_MASK3: Mask 3 times + * - TMR4_EVT_MASK4: Mask 4 times + * - TMR4_EVT_MASK5: Mask 5 times + * - TMR4_EVT_MASK6: Mask 6 times + * - TMR4_EVT_MASK7: Mask 7 times + * - TMR4_EVT_MASK8: Mask 8 times + * - TMR4_EVT_MASK9: Mask 9 times + * - TMR4_EVT_MASK10: Mask 10 times + * - TMR4_EVT_MASK11: Mask 11 times + * - TMR4_EVT_MASK12: Mask 12 times + * - TMR4_EVT_MASK13: Mask 13 times + * - TMR4_EVT_MASK14: Mask 14 times + * - TMR4_EVT_MASK15: Mask 15 times + */ +uint16_t TMR4_EVT_GetMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + return READ_REG16_BIT(*SCMR, TMR4_SCMR_AMC); +} + +/** + * @brief Set TMR4 event compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Value SCCR register value + * @arg number of 16bit + * @retval None + */ +void TMR4_EVT_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint16_t *SCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + + /* Set SCCR register */ + WRITE_REG16(*SCCR, u16Value); +} + +/** + * @brief Get TMR4 event compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @retval SCCR register value + */ +uint16_t TMR4_EVT_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *SCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + + return READ_REG16(*SCCR); +} + +/** + * @brief Set TMR4 output event + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Event TMR4 event output event + * This parameter can be one of the macros group @ref TMR4_Event_Output_Event + * @retval None + */ +void TMR4_EVT_SetOutputEvent(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Event) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_OUTPUT_EVT(u16Event)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + /* Set SCSR register */ + MODIFY_REG16(*SCSR, TMR4_SCSR_EVTOS, u16Event); +} + +/** + * @brief Set the SCCR&SCMR buffer transfer condition + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16BufCond The buffer transfer condition + * This parameter can be one of the macros group @ref TMR4_Event_Buffer_Transfer_Condition + * @arg TMR4_EVT_BUF_COND_IMMED: Register SCCR&SCMR buffer transfer when writing to the SCCR&SCMR register + * @arg TMR4_EVT_BUF_COND_VALLEY: Register SCCR&SCMR buffer transfer when counter count valley + * @arg TMR4_EVT_BUF_COND_PEAK: Register SCCR&SCMR buffer transfer when counter count peak + * @arg TMR4_EVT_BUF_COND_PEAK_VALLEY: Register SCCR&SCMR buffer transfer when counter count peak or valley + * @retval None + */ +void TMR4_EVT_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16BufCond) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_BUF_COND(u16BufCond)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + MODIFY_REG16(*SCSR, TMR4_SCSR_BUFEN, u16BufCond); +} + +/** + * @brief Enable or disable the buffer interval response function of TMR4 event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_EVT_BufIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + if (ENABLE == enNewState) { + SET_REG16_BIT(*SCSR, TMR4_SCSR_LMC); + } else { + CLR_REG16_BIT(*SCSR, TMR4_SCSR_LMC); + } +} + +/** + * @brief Enable or disable the specified interval response of TMR4 event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16MaskType The specified mask compare type of TMR4 event + * This parameter can be any composed value of the macros group @ref TMR4_Event_Mask + * @arg TMR4_EVT_MASK_VALLEY: Compare with the counter valley interrupt mask counter + * @arg TMR4_EVT_MASK_PEAK: Compare with the counter peak interrupt mask counter + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_EVT_EventIntervalReponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16MaskType, en_functional_state_t enNewState) +{ + __IO uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MASK_TYPE(u16MaskType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get actual address of register list of current channel */ + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + if (ENABLE == enNewState) { + SET_REG16_BIT(*SCMR, u16MaskType); + } else { + CLR_REG16_BIT(*SCMR, u16MaskType); + } +} + +/** + * @brief Enable or disable the specified count compare type of TMR4 event + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Cond The specified count compare type of TMR4 event + * This parameter can be any composed value of the macros group @ref TMR4_Event_Match_Condition + * @arg TMR4_EVT_MATCH_CNT_UP: Start event operate when match with SCCR&SCMR and TMR4 counter count up + * @arg TMR4_EVT_MATCH_CNT_DOWN: Start event operate when match with SCCR&SCMR and TMR4 counter count down + * @arg TMR4_EVT_MATCH_CNT_VALLEY: Start event operate when match with SCCR&SCMR and TMR4 counter count valley + * @arg TMR4_EVT_MATCH_CNT_PEAK: Start event operate when match with SCCR&SCMR and TMR4 counter count peak + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_EVT_MatchCondCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MATCH_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + if (ENABLE == enNewState) { + SET_REG16_BIT(*SCSR, u16Cond); + } else { + CLR_REG16_BIT(*SCSR, u16Cond); + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LL_TMR4_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr6.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr6.c new file mode 100644 index 0000000000..da1f2027e7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr6.c @@ -0,0 +1,1693 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr6.c + * @brief This file provides firmware functions to manage the TMR6 (TMR6). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmr6.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMR6 TMR6 + * @brief TMR6 Driver Library + * @{ + */ + +#if (LL_TMR6_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR6_Local_Macros TMR6 Local Macros + * @{ + */ + +/* Timer6 registers reset value */ +#define TMR6_REG_RST_VALUE_U32 (0xFFFFFFFFUL) +#define TMR6_REG_RST_VALUE_U16 (0xFFFFU) +#define TMR6_REG_GCONR_RST_VALUE (0x00000100UL) + +/* Define for BCONR register configuration */ +#define BCONR_FUNC_CMD_MASK (0x01UL) +#define BCONR_GEN_CFG_MASK (0x00000002UL) +#define BCONR_GEN_CFG_CHB_OFS (0x02UL) +#define BCONR_PERIOD_CFG_MASK (0x00000002UL) +#define BCONR_PERIOD_CFG_OFS (0x08UL) +#define BCONR_SPECIAL_CFG_MASK (0x00000032UL) +#define BCONR_SPECIAL_CFG_CHA_OFS (0x10UL) +#define BCONR_SPECIAL_CFG_TRIG_CHA_OFS (0x12UL) +#define BCONR_SPECIAL_CFG_CHB_OFS (0x18UL) +#define BCONR_SPECIAL_CFG_TRIG_CHB_OFS (0x1AUL) + +/* Define mask value for PWM output configuration for register */ +#define PCONR_REG_CHB_SHIFT (16U) +#define PCONR_REG_CHA_OUTPUT_CFG_MASK (0x000000FFUL) +#define PCONR_REG_CHB_OUTPUT_CFG_MASK (PCONR_REG_CHA_OUTPUT_CFG_MASK << PCONR_REG_CHB_SHIFT) +#define PCONR_REG_POLARITY_START_STOP_MASK (0x01UL) +#define PCONR_REG_POLARITY_MASK (0x03UL) + +/* Define mask value for GCONR register */ +#define TMR6_INIT_MASK (TMR6_GCONR_DIR | TMR6_GCONR_MODE | TMR6_GCONR_CKDIV) +#define TMR6_ZMASK_CFG_MASK (TMR6_GCONR_ZMSKVAL | TMR6_GCONR_ZMSKPOS | TMR6_GCONR_ZMSKREV) + +/** + * @defgroup TMR6_Check_Param_Validity TMR6 Check Parameters Validity + * @{ + */ + +/*! Parameter valid check for normal timer6 unit */ +#define IS_VALID_TMR6_UNIT(x) \ +( ((x) == CM_TMR6_1) || \ + ((x) == CM_TMR6_2) || \ + ((x) == CM_TMR6_3)) + +/*! Parameter valid check for timer6 count source */ +#define IS_TMR6_CNT_SRC(x) \ +( ((x) == TMR6_CNT_SRC_SW) || \ + ((x) == TMR6_CNT_SRC_HW)) + +/*! Parameter valid check for interrupt source configuration */ +#define IS_VALID_IRQ(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_INT_ALL) == TMR6_INT_ALL)) + +/*! Parameter valid check for status bit read */ +#define IS_VALID_GET_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_FLAG_ALL) == TMR6_FLAG_ALL)) + +/*! Parameter valid check for status bit clear */ +#define IS_VALID_CLR_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_FLAG_CLR_ALL) == TMR6_FLAG_CLR_ALL)) + +/*! Parameter valid check for period register */ +#define IS_VALID_PERIOD_REG(x) \ +( (x) <= TMR6_PERIOD_REG_C) + +/*! Parameter valid check for general compare register */ +#define IS_VALID_CMP_REG(x) \ +( (x) <= TMR6_CMP_REG_F) + +/*! Parameter valid check for general/special compare channel */ +#define IS_VALID_CNT_CH(x) \ +( ((x) == TMR6_CH_A) || \ + ((x) == TMR6_CH_B)) + +/*! Parameter valid check for buffer function number */ +#define IS_VALID_BUF_NUM(x) \ +( ((x) == TMR6_BUF_SINGLE) || \ + ((x) == TMR6_BUF_DUAL)) + +/*! Parameter valid check for buffer transfer timer configuration */ +#define IS_VALID_BUF_TRANS_TRIG(x) \ +( ((x) == TMR6_BUF_TRANS_INVD) || \ + ((x) == TMR6_BUF_TRANS_OVF) || \ + ((x) == TMR6_BUF_TRANS_UDF) || \ + ((x) == TMR6_BUF_TRANS_OVF_UDF)) + +/*! Parameter valid check for count condition for valid period function */ +#define IS_VALID_PERIOD_CNT_COND(x) \ +( ((x) == TMR6_VALID_PERIOD_INVD) || \ + ((x) == TMR6_VALID_PERIOD_CNT_COND_UDF) || \ + ((x) == TMR6_VALID_PERIOD_CNT_COND_OVF) || \ + ((x) == TMR6_VALID_PERIOD_CNT_COND_OVF_UDF)) + +/*! Parameter valid check for count condition for valid period count */ +#define IS_VALID_PERIOD_CNT(x) \ +( ((x) == TMR6_VALID_PERIOD_CNT_INVD) || \ + ((x) == TMR6_VALID_PERIOD_CNT1) || \ + ((x) == TMR6_VALID_PERIOD_CNT2) || \ + ((x) == TMR6_VALID_PERIOD_CNT3) || \ + ((x) == TMR6_VALID_PERIOD_CNT4) || \ + ((x) == TMR6_VALID_PERIOD_CNT5) || \ + ((x) == TMR6_VALID_PERIOD_CNT6) || \ + ((x) == TMR6_VALID_PERIOD_CNT7)) + +/*! Parameter valid check for count register data range */ +#define IS_VALID_REG_RANGE_U16(x) ((x) <= 0xFFFFUL) + +/*! Parameter valid check for dead time register */ +#define IS_VALID_DEADTIME_REG(x) \ +( ((x) == TMR6_DEADTIME_REG_UP_A) || \ + ((x) == TMR6_DEADTIME_REG_DOWN_A) || \ + ((x) == TMR6_DEADTIME_REG_UP_B) || \ + ((x) == TMR6_DEADTIME_REG_DOWN_B)) + +/*! Parameter valid check for pin */ +#define IS_VALID_PIN(x) \ +( ((x) == TMR6_IO_PWMA) || \ + ((x) == TMR6_IO_PWMB) || \ + ((x) == TMR6_INPUT_TRIGA) || \ + ((x) == TMR6_INPUT_TRIGB)) + +/*! Parameter valid check for input pin filter clock */ +#define IS_VALID_FILTER_CLK(x) \ +( ((x) == TMR6_FILTER_CLK_DIV1) || \ + ((x) == TMR6_FILTER_CLK_DIV4) || \ + ((x) == TMR6_FILTER_CLK_DIV16) || \ + ((x) == TMR6_FILTER_CLK_DIV64)) + +/*! Parameter valid check for PWM pin status */ +#define IS_VALID_PWM_POLARITY(x) \ +( ((x) == TMR6_PWM_LOW) || \ + ((x) == TMR6_PWM_HIGH) || \ + ((x) == TMR6_PWM_HOLD) || \ + ((x) == TMR6_PWM_INVT)) + +/*! Parameter valid check for start stop hold for PWM output pin */ +#define IS_VALID_PWM_START_STOP_HOLD(x) \ +( ((x) == TMR6_PWM_START_STOP_HOLD) || \ + ((x) == TMR6_PWM_START_STOP_CHANGE)) + +/*! Parameter valid check for force PWM output pin */ + +/*! Parameter valid check for PWM pin status for count start and stop */ +#define IS_VALID_PWM_POLARITY_START_STOP(x) \ +( ((x) == TMR6_PWM_LOW) || \ + ((x) == TMR6_PWM_HIGH)) + +#define IS_VALID_CNT_STAT(x) \ +( ((x) == TMR6_STAT_START) || \ + ((x) == TMR6_STAT_STOP) || \ + ((x) == TMR6_STAT_MATCH_CMP) || \ + ((x) == TMR6_STAT_MATCH_PERIOD)) + +/*! Parameter valid check for pin mode */ +#define IS_VALID_PIN_MD(x) \ +( ((x) == TMR6_PIN_CMP_OUTPUT) || \ + ((x) == TMR6_PIN_CAPT_INPUT)) + +/*! Parameter valid check for pin output status when EMB event valid */ +#define IS_VALID_EMB_VALID_PIN_POLARITY(x) \ +( ((x) == TMR6_EMB_PIN_NORMAL) || \ + ((x) == TMR6_EMB_PIN_HIZ) || \ + ((x) == TMR6_EMB_PIN_LOW) || \ + ((x) == TMR6_EMB_PIN_HIGH)) + +/*! Parameter valid check for dead time buffer function for DTUAR and DTUBR register */ +#define IS_VALID_DEADTIME_BUF_FUNC_DTUAR_REG(x) \ +( ((x) == TMR6_DEADTIME_CNT_UP_BUF_OFF) || \ + ((x) == TMR6_DEADTIME_CNT_UP_BUF_ON)) + +/*! Parameter valid check for dead time buffer function for DTDAR and DTDBR register */ +#define IS_VALID_DEADTIME_BUF_FUNC_DTDAR_REG(x) \ +( ((x) == TMR6_DEADTIME_CNT_DOWN_BUF_OFF) || \ + ((x) == TMR6_DEADTIME_CNT_DOWN_BUF_ON)) + +/*! Parameter valid check for dead time equal function for DTUAR and DTDAR register */ +#define IS_VALID_DEADTIME_EQUAL_FUNC_REG(x) \ +( ((x) == TMR6_DEADTIME_EQUAL_OFF) || \ + ((x) == TMR6_DEADTIME_EQUAL_ON)) + +/*! Parameter valid check for start condition */ +#define IS_VALID_START_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_START_COND_ALL) == TMR6_START_COND_ALL)) + +/*! Parameter valid check for stop condition */ +#define IS_VALID_STOP_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_STOP_COND_ALL) == TMR6_STOP_COND_ALL)) + +/*! Parameter valid check for clear condition */ +#define IS_VALID_CLR_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CLR_COND_ALL) == TMR6_CLR_COND_ALL)) + +/*! Parameter valid check for capture condition */ +#define IS_VALID_CAPT_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CAPT_COND_ALL) == TMR6_CAPT_COND_ALL)) + +/*! Parameter valid check for hardware count up condition */ +#define IS_VALID_CNT_UP_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CNT_UP_COND_ALL) == TMR6_CNT_UP_COND_ALL)) + +/*! Parameter valid check for hardware count down condition */ +#define IS_VALID_CNT_DOWN_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CNT_DOWN_COND_ALL) == TMR6_CNT_DOWN_COND_ALL)) + +/*! Parameter valid check for count Mode */ +#define IS_VALID_CNT_MD(x) \ +( ((x) == TMR6_MD_SAWTOOTH) || \ + ((x) == TMR6_MD_TRIANGLE_A) || \ + ((x) == TMR6_MD_TRIANGLE_B)) + +/*! Parameter valid check for count direction */ +#define IS_VALID_CNT_DIR(x) \ +( ((x) == TMR6_CNT_UP) || \ + ((x) == TMR6_CNT_DOWN)) + +/*! Parameter valid check for count clock division */ +#define IS_VALID_CNT_CLK_DIV(x) \ +( ((x) == TMR6_CLK_DIV1) || \ + ((x) == TMR6_CLK_DIV2) || \ + ((x) == TMR6_CLK_DIV4) || \ + ((x) == TMR6_CLK_DIV8) || \ + ((x) == TMR6_CLK_DIV16) || \ + ((x) == TMR6_CLK_DIV64) || \ + ((x) == TMR6_CLK_DIV256) || \ + ((x) == TMR6_CLK_DIV1024)) + +/*! Parameter valid check for Z Mask input function mask cycles number */ +#define IS_VALID_ZMASK_CYCLES(x) \ +( ((x) == TMR6_ZMASK_FUNC_INVD) || \ + ((x) == TMR6_ZMASK_CYCLE_4) || \ + ((x) == TMR6_ZMASK_CYCLE_8) || \ + ((x) == TMR6_ZMASK_CYCLE_16)) + +/*! Parameter valid check for Z Mask function of timer6 position unit */ +#define IS_VALID_POS_UNIT_ZMASK_FUNC(x) \ +( ((x) == TMR6_POS_CLR_ZMASK_FUNC_OFF) || \ + ((x) == TMR6_POS_CLR_ZMASK_FUNC_ON)) + +/*! Parameter valid check for Z Mask function of timer6 revolution unit */ +#define IS_VALID_REVO_UNIT_ZMASK_FUNC(x) \ +( ((x) == TMR6_REVO_CNT_ZMASK_FUNC_OFF) || \ + ((x) == TMR6_REVO_CNT_ZMASK_FUNC_ON)) + +/*! Parameter valid check for software sync control unit */ +#define IS_VALID_SW_UNIT(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_SW_SYNC_ALL) == TMR6_SW_SYNC_ALL)) + +/*! Unit check for TMR6 which data width is 32 bit */ +#define IS_TMR6_32BIT_UNIT(x) \ +( ((x) == CM_TMR6_1) || \ + ((x) == CM_TMR6_2) || \ + ((x) == CM_TMR6_3) || \ + ((x) == CM_TMR6_4)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup TMR6_Global_Functions TMR6 Global Functions + * @{ + */ + +/** + * @brief Initialize the timer6 count function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcTmr6Init Pointer of configuration structure @ref stc_timer6_init_t + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_Init(CM_TMR6_TypeDef *TMR6x, const stc_timer6_init_t *pstcTmr6Init) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcTmr6Init) { + /* Check parameters */ + DDL_ASSERT(IS_TMR6_CNT_SRC(pstcTmr6Init->u8CountSrc)); + + if (pstcTmr6Init->u8CountSrc == TMR6_CNT_SRC_SW) { + /* Normal count */ + DDL_ASSERT(IS_VALID_CNT_MD(pstcTmr6Init->sw_count.u32CountMode)); + DDL_ASSERT(IS_VALID_CNT_DIR(pstcTmr6Init->sw_count.u32CountDir)); + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(pstcTmr6Init->sw_count.u32ClockDiv)); + + MODIFY_REG32(TMR6x->GCONR, TMR6_INIT_MASK, (pstcTmr6Init->sw_count.u32CountMode | pstcTmr6Init->sw_count.u32CountDir | \ + pstcTmr6Init->sw_count.u32ClockDiv)); + } else { + /* Hardware count */ + if (0U != pstcTmr6Init->hw_count.u32CountUpCond) { + DDL_ASSERT(IS_VALID_CNT_UP_COND(pstcTmr6Init->hw_count.u32CountUpCond)); + } + if (0U != pstcTmr6Init->hw_count.u32CountDownCond) { + DDL_ASSERT(IS_VALID_CNT_DOWN_COND(pstcTmr6Init->hw_count.u32CountDownCond)); + } + + WRITE_REG32(TMR6x->HCUPR, pstcTmr6Init->hw_count.u32CountUpCond); + WRITE_REG32(TMR6x->HCDOR, pstcTmr6Init->hw_count.u32CountDownCond); + } + + DDL_ASSERT(IS_VALID_REG_RANGE_U16(pstcTmr6Init->u32PeriodValue)); + WRITE_REG16(TMR6x->PERAR, pstcTmr6Init->u32PeriodValue); + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set timer6 base count mode + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Mode @ref TMR6_Count_Mode_Define + * @retval None + */ +void TMR6_SetCountMode(CM_TMR6_TypeDef *TMR6x, uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_MD(u32Mode)); + MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_MODE, u32Mode); +} + +/** + * @brief Set timer6 base count direction + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Dir @ref TMR6_Count_Dir_Define + * @retval None + */ +void TMR6_SetCountDir(CM_TMR6_TypeDef *TMR6x, uint32_t u32Dir) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_DIR(u32Dir)); + MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_DIR, u32Dir); +} + +/** + * @brief Set timer6 base count direction + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval uint32_t Count direction @ref TMR6_Count_Dir_Define + */ +uint32_t TMR6_GetCountDir(CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + return READ_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_DIR); +} + +/** + * @brief Set timer6 clock division + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Div @ref TMR6_Count_Clock_Define + * @retval None + */ +void TMR6_SetClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Div) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(u32Div)); + + MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_CKDIV, u32Div); +} + +/** + * @brief Hardware increase conditon command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware count, maybe one or any combination of the parameter + * @ref TMR6_HW_Count_Up_Cond_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_HWCountUpCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_UP_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HCUPR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HCUPR, u32Cond); + } +} + +/** + * @brief Hardware decrease condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware count, maybe one or any combination of the parameter + * @ref TMR6_HW_Count_Down_Cond_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_HWCountDownCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_DOWN_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HCDOR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HCDOR, u32Cond); + } +} + +/** + * @brief Initialize the timer6 hardware count function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] pstcPwmInit Pointer of initialize structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_PWM_Init(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_pwm_init_t *pstcPwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + + __IO uint32_t *TMR6_GCMxR = (__IO uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Ch); + + if (NULL != pstcPwmInit) { + DDL_ASSERT(IS_VALID_PWM_POLARITY_START_STOP(pstcPwmInit->u32StartPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY_START_STOP(pstcPwmInit->u32StopPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32CompareMatchPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32PeriodMatchPolarity)); + DDL_ASSERT(IS_VALID_PWM_START_STOP_HOLD(pstcPwmInit->u32StartStopHold)); + DDL_ASSERT(IS_VALID_REG_RANGE_U16(pstcPwmInit->u32CompareValue)); + WRITE_REG16(*TMR6_GCMxR, pstcPwmInit->u32CompareValue); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCONR, PCONR_REG_CHA_OUTPUT_CFG_MASK, \ + pstcPwmInit->u32CompareMatchPolarity << TMR6_PCONR_CMPCA_POS \ + | pstcPwmInit->u32PeriodMatchPolarity << TMR6_PCONR_PERCA_POS \ + | pstcPwmInit->u32StopPolarity << TMR6_PCONR_STPCA_POS \ + | pstcPwmInit->u32StartPolarity << TMR6_PCONR_STACA_POS \ + | pstcPwmInit->u32StartStopHold); + } else { + MODIFY_REG32(TMR6x->PCONR, PCONR_REG_CHB_OUTPUT_CFG_MASK, \ + pstcPwmInit->u32CompareMatchPolarity << TMR6_PCONR_CMPCB_POS \ + | pstcPwmInit->u32PeriodMatchPolarity << TMR6_PCONR_PERCB_POS \ + | pstcPwmInit->u32StopPolarity << TMR6_PCONR_STPCB_POS \ + | pstcPwmInit->u32StartPolarity << TMR6_PCONR_STACB_POS \ + | pstcPwmInit->u32StartStopHold); + } + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Timer6 PWM output command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_PWM_OutputCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32Tmp; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + u32Tmp = 0xFFFFFFFFUL; + } else { + u32Tmp = 0UL; + } + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_OUTENA, u32Tmp); + } else { + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_OUTENB, u32Tmp); + } +} + +/** + * @brief Timer6 set pin polarity + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] u32CountState Polarity set for @ref TMR6_Count_State_Define + * @param [in] u32Polarity @ref TMR6_Pin_Polarity_Define + * @retval None + */ +void TMR6_PWM_SetPolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32CountState, uint32_t u32Polarity) +{ + uint32_t u32PolarityMask = PCONR_REG_POLARITY_MASK; + + uint8_t au8Pos[4] = {TMR6_PCONR_STACA_POS, TMR6_PCONR_STPCA_POS, TMR6_PCONR_CMPCA_POS, TMR6_PCONR_PERCA_POS }; + DDL_ASSERT(IS_VALID_CNT_STAT(u32CountState)); + if ((TMR6_STAT_START == u32CountState) || (TMR6_STAT_STOP == u32CountState)) { + DDL_ASSERT(IS_VALID_PWM_POLARITY_START_STOP(u32Polarity)); + u32PolarityMask = PCONR_REG_POLARITY_START_STOP_MASK; + } else { + DDL_ASSERT(IS_VALID_PWM_POLARITY(u32Polarity)); + } + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + + u32Polarity <<= au8Pos[u32CountState]; + u32PolarityMask <<= au8Pos[u32CountState]; + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCONR, u32PolarityMask, u32Polarity); + } else { + MODIFY_REG32(TMR6x->PCONR, u32PolarityMask << PCONR_REG_CHB_SHIFT, u32Polarity << PCONR_REG_CHB_SHIFT); + } +} + +/** + * @brief Timer6 set force polarity when next period + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] u32HoldStatus @ref TMR6_Output_StaStp_Hold_Define + * @retval None + */ +void TMR6_PWM_SetStartStopHold(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32HoldStatus) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_PWM_START_STOP_HOLD(u32HoldStatus)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_STASTPSA, u32HoldStatus); + } else { + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_STASTPSB, u32HoldStatus << PCONR_REG_CHB_SHIFT); + } +} + +/** + * @brief Hardware capture condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Input pin select @ref TMR6_Count_Ch_Define + * @param [in] u32Cond Events source for hardware capture, maybe one or any combination of the parameter + * @ref TMR6_hardware_capture_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_HWCaptureCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_CAPT_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + __IO uint32_t *HCPxR = (__IO uint32_t *)((uint32_t)&TMR6x->HCPAR + (u32Ch * 4UL)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(*HCPxR, u32Cond); + } else { + CLR_REG32_BIT(*HCPxR, u32Cond); + } +} + +/** + * @brief Port input filter function configuration(Trig) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Pin Pin to be configured @ref TMR6_Pin_Define + * @param [in] u32Div Filter clock @ref TMR6_Input_Filter_Clock + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +int32_t TMR6_SetFilterClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, uint32_t u32Div) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PIN(u32Pin)); + DDL_ASSERT(IS_VALID_FILTER_CLK(u32Div)); + + switch (u32Pin) { + case TMR6_IO_PWMA: + MODIFY_REG32(TMR6x->FCONR, TMR6_FCONR_NOFICKGA, u32Div << TMR6_FCONR_NOFICKGA_POS); + break; + case TMR6_IO_PWMB: + MODIFY_REG32(TMR6x->FCONR, TMR6_FCONR_NOFICKGB, u32Div << TMR6_FCONR_NOFICKGB_POS); + break; + case TMR6_INPUT_TRIGA: + MODIFY_REG32(CM_TMR6_1->FCONR, TMR6_FCONR_NOFICKTA, u32Div << TMR6_FCONR_NOFICKTA_POS); + break; + case TMR6_INPUT_TRIGB: + MODIFY_REG32(CM_TMR6_1->FCONR, TMR6_FCONR_NOFICKTB, u32Div << TMR6_FCONR_NOFICKTB_POS); + break; + + default: + i32Ret = LL_ERR_INVD_PARAM; + break; + } + return i32Ret; +} + +/** + * @brief Port input filter function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Pin Input port to be configured @ref TMR6_Pin_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_FilterCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PIN(u32Pin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + switch (u32Pin) { + case TMR6_IO_PWMA: + MODIFY_REG32(TMR6x->FCONR, TMR6_FCONR_NOFIENGA, ((uint32_t)enNewState) << TMR6_FCONR_NOFIENGA_POS); + break; + case TMR6_IO_PWMB: + MODIFY_REG32(TMR6x->FCONR, TMR6_FCONR_NOFIENGB, ((uint32_t)enNewState) << TMR6_FCONR_NOFIENGB_POS); + break; + case TMR6_INPUT_TRIGA: + MODIFY_REG32(CM_TMR6_1->FCONR, TMR6_FCONR_NOFIENTA, ((uint32_t)enNewState) << TMR6_FCONR_NOFIENTA_POS); + break; + case TMR6_INPUT_TRIGB: + MODIFY_REG32(CM_TMR6_1->FCONR, TMR6_FCONR_NOFIENTB, ((uint32_t)enNewState) << TMR6_FCONR_NOFIENTB_POS); + break; + + default: + break; + } +} + +/** + * @brief Set channel function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Channel to be configured @ref TMR6_Count_Ch_Define + * @param [in] u32Func IO mode @ref TMR6_Pin_Mode_Define + * @retval None + */ +void TMR6_SetFunc(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Func) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_PIN_MD(u32Func)); + + switch (u32Ch) { + case TMR6_CH_A: + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_CAPMDA, u32Func); + break; + case TMR6_CH_B: + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_CAPMDB, u32Func << TMR6_PCONR_CAPMDB_POS); + break; + + default: + break; + } +} + +/** + * @brief Timer6 interrupt enable or disable + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32IntType Irq flag, Can be one or any combination of the values from + * @ref TMR6_Int_Flag_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_IntCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_IRQ(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->ICONR, u32IntType); + } else { + CLR_REG32_BIT(TMR6x->ICONR, u32IntType); + } +} + +/** + * @brief Get Timer6 status flag + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Flag Status bit to be read, Can be one or any combination of the values from + * @ref TMR6_Stat_Flag_Define + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMR6_GetStatus(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GET_FLAG(u32Flag)); + + if (0UL != READ_REG32_BIT(TMR6x->STFLR, u32Flag)) { + enStatus = SET; + } + return enStatus; +} + +/** + * @brief Clear Timer6 status flag + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Flag Status bit to be read, Can be one or any combination of the values from + * @ref TMR6_Stat_Flag_Define + * @retval None + */ +void TMR6_ClearStatus(CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CLR_FLAG(u32Flag)); + + CLR_REG32_BIT(TMR6x->STFLR, u32Flag); +} + +/** + * @brief Get Timer6 period number when valid period function enable + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval uint32_t Data for periods number + */ +uint32_t TMR6_GetPeriodNum(const CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + return (READ_REG32_BIT(TMR6x->STFLR, TMR6_STFLR_VPERNUM) >> TMR6_STFLR_VPERNUM_POS); +} + +/** + * @brief De-initialize the timer6 unit + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval None + */ +void TMR6_DeInit(CM_TMR6_TypeDef *TMR6x) +{ + uint32_t u32RefRegRstValue; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + u32RefRegRstValue = TMR6_REG_RST_VALUE_U16; + + WRITE_REG32(TMR6x->GCONR, TMR6_REG_GCONR_RST_VALUE); + WRITE_REG32(TMR6x->CNTER, 0UL); + WRITE_REG32(TMR6x->PERAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->PERBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->PERCR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMCR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMDR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMER, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMFR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMCR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMDR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMER, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMFR, u32RefRegRstValue); + WRITE_REG32(TMR6x->DTUAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->DTDAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->DTUBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->DTDBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->ICONR, 0UL); + WRITE_REG32(TMR6x->BCONR, 0UL); + WRITE_REG32(TMR6x->DCONR, 0UL); + WRITE_REG32(TMR6x->PCONR, 0UL); + WRITE_REG32(TMR6x->FCONR, 0UL); + WRITE_REG32(TMR6x->VPERR, 0UL); + WRITE_REG32(TMR6x->STFLR, 0UL); + WRITE_REG32(TMR6x->HSTAR, 0UL); + WRITE_REG32(TMR6x->HSTPR, 0UL); + WRITE_REG32(TMR6x->HCLRR, 0UL); + WRITE_REG32(TMR6x->HCPAR, 0UL); + WRITE_REG32(TMR6x->HCPBR, 0UL); + WRITE_REG32(TMR6x->HCUPR, 0UL); + WRITE_REG32(TMR6x->HCDOR, 0UL); + + WRITE_REG32(CM_TMR6CR->SSTAR, 0UL); + WRITE_REG32(CM_TMR6CR->SSTPR, 0UL); + WRITE_REG32(CM_TMR6CR->SCLRR, 0UL); +} + +/** + * @brief Timer6 count start + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval None + */ +void TMR6_Start(CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + SET_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_START); +} + +/** + * @brief Timer6 count stop + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval None + */ +void TMR6_Stop(CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + CLR_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_START); +} + +/** + * @brief Timer6 counter register set + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Value Counter value + * @retval None + */ +void TMR6_SetCountValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG16(TMR6x->CNTER, u32Value); +} + +/** + * @brief Timer6 get counter register value + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval uint32_t Data for the count register value + */ +uint32_t TMR6_GetCountValue(const CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + return READ_REG32(TMR6x->CNTER); +} + +/** + * @brief Timer6 set period register(A~C) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Period register to be write, @ref TMR6_Period_Reg_Index_Define + * @param [in] u32Value Period value for write + * @retval None + */ +void TMR6_SetPeriodValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_REG(u32Index)); + __IO uint32_t *TMR6_PERxR = (uint32_t *)((uint32_t)&TMR6x->PERAR + 4UL * u32Index); + + /* 16bit */ + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG16(*TMR6_PERxR, u32Value); +} + +/** + * @brief Timer6 set general compare register(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index General compare register to be write, @ref TMR6_Compare_Reg_Index_Define + * @param [in] u32Value Value for write + * @retval None + */ +void TMR6_SetCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + __IO uint32_t *TMR6_GCMxR = (__IO uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Index); + + /* 16bit */ + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG16(*TMR6_GCMxR, u32Value); +} + +/** + * @brief Timer6 set special compare register(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Special compare register to be write, @ref TMR6_Compare_Reg_Index_Define + * @param [in] u32Value Value for write + * @retval None + */ +void TMR6_SetSpecialCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + __IO uint32_t *TMR6_SCMxR = (uint32_t *)((uint32_t)&TMR6x->SCMAR + 4UL * u32Index); + + /* 16bit */ + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG16(*TMR6_SCMxR, u32Value); +} + +/** + * @brief Timer6 set dead time registerr + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Special compare register to be write, @ref TMR6_DeadTime_Reg_Define + * @param [in] u32Value Value for write + * @retval None + */ +void TMR6_SetDeadTimeValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_DEADTIME_REG(u32Index)); + __IO uint32_t *TMR6_DTxyR = (uint32_t *)((uint32_t)&TMR6x->DTUAR + 4UL * u32Index); + + /* 16bit */ + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG16(*TMR6_DTxyR, u32Value); +} + +/** + * @brief Timer6 get general compare registers value(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index General compare register to be read, @ref TMR6_Compare_Reg_Index_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + __IO uint32_t *TMR6_GCMxR = (uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Index); + + return READ_REG32(*TMR6_GCMxR); +} + +/** + * @brief Timer6 get special compare registers value(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Special compare register to be read, @ref TMR6_Compare_Reg_Index_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetSpecialCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + __IO uint32_t *TMR6_SCMxR = (uint32_t *)((uint32_t)&TMR6x->SCMAR + 4UL * u32Index); + + return READ_REG32(*TMR6_SCMxR); +} + +/** + * @brief Timer6 Get period register(A~C) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Period register to be write, @ref TMR6_Period_Reg_Index_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetPeriodValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_REG(u32Index)); + __IO uint32_t *TMR6_PERxR = (uint32_t *)((uint32_t)&TMR6x->PERAR + 4UL * u32Index); + + return READ_REG32(*TMR6_PERxR); +} + +/** + * @brief Timer6 get dead time register + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Dead time register to be write, @ref TMR6_DeadTime_Reg_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetDeadTimeValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_DEADTIME_REG(u32Index)); + __IO uint32_t *TMR6_DTxyR = (uint32_t *)((uint32_t)&TMR6x->DTUAR + 4UL * u32Index); + + return READ_REG32(*TMR6_DTxyR); +} + +/** + * @brief Timer6 general compare buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose @ref TMR6_Count_Ch_Define + * @param [in] u32BufNum Buffer number @ref TMR6_Buf_Num_Define + * @retval None + */ +void TMR6_SetGeneralBufNum(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32BufNum) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_BUF_NUM(u32BufNum)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_GEN_CFG_MASK, u32BufNum); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_GEN_CFG_MASK << BCONR_GEN_CFG_CHB_OFS, u32BufNum << BCONR_GEN_CFG_CHB_OFS); + } +} + +/** + * @brief Timer6 general compare buffer function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_GeneralBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK, enNewState); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_GEN_CFG_CHB_OFS, \ + ((uint32_t)enNewState) << BCONR_GEN_CFG_CHB_OFS); + } +} + +/** + * @brief Timer6 special compare buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Special compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] pstcBufConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_SpecialBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (NULL != pstcBufConfig) { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_BUF_NUM(pstcBufConfig->u32BufNum)); + DDL_ASSERT(IS_VALID_BUF_TRANS_TRIG(pstcBufConfig->u32BufTransCond)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_SPECIAL_CFG_MASK << BCONR_SPECIAL_CFG_CHA_OFS, \ + (pstcBufConfig->u32BufNum << BCONR_SPECIAL_CFG_CHA_OFS) \ + | (pstcBufConfig->u32BufTransCond << BCONR_SPECIAL_CFG_TRIG_CHA_OFS)); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_SPECIAL_CFG_MASK << BCONR_SPECIAL_CFG_CHB_OFS, \ + (pstcBufConfig->u32BufNum << BCONR_SPECIAL_CFG_CHB_OFS) | \ + (pstcBufConfig->u32BufTransCond << BCONR_SPECIAL_CFG_TRIG_CHB_OFS)); + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Timer6 special compare buffer function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_SpecialBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_SPECIAL_CFG_CHA_OFS, \ + ((uint32_t)enNewState) << BCONR_SPECIAL_CFG_CHA_OFS); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_SPECIAL_CFG_CHB_OFS, \ + ((uint32_t)enNewState) << BCONR_SPECIAL_CFG_CHB_OFS); + } +} + +/** + * @brief Timer6 period buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32BufNum Buffer number @ref TMR6_Buf_Num_Define + * @retval None + */ +void TMR6_SetPeriodBufNum(CM_TMR6_TypeDef *TMR6x, uint32_t u32BufNum) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_BUF_NUM(u32BufNum)); + + MODIFY_REG32(TMR6x->BCONR, BCONR_PERIOD_CFG_MASK << BCONR_PERIOD_CFG_OFS, u32BufNum << BCONR_PERIOD_CFG_OFS); +} + +/** + * @brief Timer6 period buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_PeriodBufCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_PERIOD_CFG_OFS, + ((uint32_t)enNewState) << BCONR_PERIOD_CFG_OFS); +} + +/** + * @brief Timer6 valid period function configuration for special compare function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcValidperiodConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ValidPeriodConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_valid_period_config_t *pstcValidperiodConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (NULL != pstcValidperiodConfig) { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_CNT_COND(pstcValidperiodConfig->u32CountCond)); + DDL_ASSERT(IS_VALID_PERIOD_CNT(pstcValidperiodConfig->u32PeriodInterval)); + + MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_PCNTS | TMR6_VPERR_PCNTE, \ + pstcValidperiodConfig->u32CountCond | pstcValidperiodConfig->u32PeriodInterval); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Timer6 valid period function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_ValidPeriodCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_SPPERIA, ((uint32_t)enNewState) << TMR6_VPERR_SPPERIA_POS); + } else { + MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_SPPERIB, ((uint32_t)enNewState) << TMR6_VPERR_SPPERIB_POS); + } +} + +/** + * @brief Timer6 dead time function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_DeadTimeFuncCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->DCONR, TMR6_DCONR_DTCEN); + } else { + CLR_REG32_BIT(TMR6x->DCONR, TMR6_DCONR_DTCEN); + } +} + +/** + * @brief DeadTime function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcDeadTimeConfig Timer6 dead time config pointer + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_DeadTimeConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_config_t *pstcDeadTimeConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcDeadTimeConfig) { + DDL_ASSERT(IS_VALID_DEADTIME_EQUAL_FUNC_REG(pstcDeadTimeConfig->u32EqualUpDown)); + DDL_ASSERT(IS_VALID_DEADTIME_BUF_FUNC_DTUAR_REG(pstcDeadTimeConfig->u32BufUp)); + DDL_ASSERT(IS_VALID_DEADTIME_BUF_FUNC_DTDAR_REG(pstcDeadTimeConfig->u32BufDown)); + WRITE_REG32(TMR6x->DCONR, pstcDeadTimeConfig->u32EqualUpDown | pstcDeadTimeConfig->u32BufUp \ + | pstcDeadTimeConfig->u32BufDown); + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Timer6 unit Z phase input mask config + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcZMaskConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ZMaskConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_config_t *pstcZMaskConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcZMaskConfig) { + DDL_ASSERT(IS_VALID_ZMASK_CYCLES(pstcZMaskConfig->u32ZMaskCycle)); + DDL_ASSERT(IS_VALID_POS_UNIT_ZMASK_FUNC(pstcZMaskConfig->u32PosCountMaskFunc)); + DDL_ASSERT(IS_VALID_REVO_UNIT_ZMASK_FUNC(pstcZMaskConfig->u32RevoCountMaskFunc)); + + MODIFY_REG32(TMR6x->GCONR, TMR6_ZMASK_CFG_MASK, pstcZMaskConfig->u32ZMaskCycle | \ + pstcZMaskConfig->u32PosCountMaskFunc | pstcZMaskConfig->u32RevoCountMaskFunc); + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief EMB function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Channel to be configured @ref TMR6_Count_Ch_Define + * @param [in] pstcEmbConfig Point EMB function Config Pointer + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_EMBConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_emb_config_t *pstcEmbConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcEmbConfig) { + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_EMB_VALID_PIN_POLARITY(pstcEmbConfig->u32PinStatus)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_EMBVALA, pstcEmbConfig->u32PinStatus); + } else { + MODIFY_REG32(TMR6x->PCONR, TMR6_PCONR_EMBVALB, pstcEmbConfig->u32PinStatus << (TMR6_PCONR_EMBVALB_POS - TMR6_PCONR_EMBVALA_POS)); + } + + i32Ret = LL_OK; + } + return i32Ret; + +} + +/** + * @brief Software Sync Start + * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter + * @ref TMR6_SW_Sync_Unit_define + * @retval None + */ +void TMR6_SWSyncStart(uint32_t u32Unit) +{ + DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit)); + WRITE_REG32(CM_TMR6CR->SSTAR, u32Unit); +} + +/** + * @brief Software Sync Stop + * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter + * @ref TMR6_SW_Sync_Unit_define + * @retval None + */ +void TMR6_SWSyncStop(uint32_t u32Unit) +{ + DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit)); + WRITE_REG32(CM_TMR6CR->SSTPR, u32Unit); +} + +/** + * @brief Software Sync clear + * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter + * @ref TMR6_SW_Sync_Unit_define + * @retval None + */ +void TMR6_SWSyncClear(uint32_t u32Unit) +{ + DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit)); + WRITE_REG32(CM_TMR6CR->SCLRR, u32Unit); +} + +/** + * @brief Hardware start function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWStartCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HSTAR, TMR6_HSTAR_STAS, ((uint32_t)enNewState) << TMR6_HSTAR_STAS_POS); +} + +/** + * @brief Hardware stop function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWStopCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HSTPR, TMR6_HSTPR_STPS, ((uint32_t)enNewState) << TMR6_HSTPR_STPS_POS); +} + +/** + * @brief Hardware clear function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWClearCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HCLRR, TMR6_HCLRR_CLES, ((uint32_t)enNewState) << TMR6_HCLRR_CLES_POS); +} + +/** + * @brief Hardware start condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware start, maybe one or any combination of the parameter + * @ref TMR6_hardware_start_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_HWStartCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_START_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HSTAR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HSTAR, u32Cond); + } +} + +/** + * @brief Hardware stop condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware stop, maybe one or any combination of the parameter + * @ref TMR6_hardware_stop_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_HWStopCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_STOP_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HSTPR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HSTPR, u32Cond); + } +} + +/** + * @brief Hardware clear condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware clear, maybe one or any combination of the parameter + * @ref TMR6_hardware_clear_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Please make sure that peripheral clock of CM_TMR6_1 is valid if The TRIGX pin is used. + */ +void TMR6_HWClearCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CLR_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HCLRR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HCLRR, u32Cond); + } +} + +/** + * @brief Set the fields of structure stc_timer6_init_t to default values + * @param [out] pstcTmr6Init Pointer to a @ref stc_timer6_init_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_StructInit(stc_timer6_init_t *pstcTmr6Init) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32RefRegRstValue; + + /* Check structure pointer */ + if (NULL != pstcTmr6Init) { + pstcTmr6Init->u8CountSrc = TMR6_CNT_SRC_SW; + pstcTmr6Init->sw_count.u32ClockDiv = TMR6_CLK_DIV1; + pstcTmr6Init->sw_count.u32CountMode = TMR6_MD_SAWTOOTH; + pstcTmr6Init->sw_count.u32CountDir = TMR6_CNT_UP; + + u32RefRegRstValue = TMR6_REG_RST_VALUE_U16; + pstcTmr6Init->u32PeriodValue = u32RefRegRstValue; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_buf_config_t to default values + * @param [out] pstcBufConfig Pointer to a @ref stc_tmr6_buf_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_BufFuncStructInit(stc_tmr6_buf_config_t *pstcBufConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcBufConfig) { + pstcBufConfig->u32BufNum = TMR6_BUF_SINGLE; + pstcBufConfig->u32BufTransCond = TMR6_BUF_TRANS_INVD; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_valid_period_config_t to default values + * @param [out] pstcValidperiodConfig Pointer to a @ref stc_tmr6_valid_period_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_config_t *pstcValidperiodConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcValidperiodConfig) { + pstcValidperiodConfig->u32CountCond = TMR6_VALID_PERIOD_INVD; + pstcValidperiodConfig->u32PeriodInterval = TMR6_VALID_PERIOD_CNT_INVD; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_emb_config_t to default values + * @param [out] pstcEmbConfig Pointer to a @ref stc_tmr6_emb_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_EMBConfigStructInit(stc_tmr6_emb_config_t *pstcEmbConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcEmbConfig) { + pstcEmbConfig->u32PinStatus = TMR6_EMB_PIN_NORMAL; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_deadtime_config_t to default values + * @param [out] pstcDeadTimeConfig Pointer to a @ref stc_tmr6_deadtime_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_DeadTimeStructInit(stc_tmr6_deadtime_config_t *pstcDeadTimeConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcDeadTimeConfig) { + pstcDeadTimeConfig->u32EqualUpDown = TMR6_DEADTIME_EQUAL_OFF; + pstcDeadTimeConfig->u32BufUp = TMR6_DEADTIME_CNT_UP_BUF_OFF; + pstcDeadTimeConfig->u32BufDown = TMR6_DEADTIME_CNT_DOWN_BUF_OFF; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_zmask_config_t to default values + * @param [out] pstcZMaskConfig Pointer to a @ref stc_tmr6_zmask_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ZMaskConfigStructInit(stc_tmr6_zmask_config_t *pstcZMaskConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcZMaskConfig) { + pstcZMaskConfig->u32ZMaskCycle = TMR6_ZMASK_FUNC_INVD; + pstcZMaskConfig->u32PosCountMaskFunc = TMR6_POS_CLR_ZMASK_FUNC_OFF; + pstcZMaskConfig->u32RevoCountMaskFunc = TMR6_REVO_CNT_ZMASK_FUNC_OFF; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_pwm_init_t to default values + * @param [out] pstcPwmInit Pointer to a @ref stc_tmr6_pwm_init_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_PWM_StructInit(stc_tmr6_pwm_init_t *pstcPwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32RefRegRstValue; + + /* Check structure pointer */ + if (NULL != pstcPwmInit) { + pstcPwmInit->u32StartPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32StopPolarity = TMR6_PWM_LOW; + + u32RefRegRstValue = TMR6_REG_RST_VALUE_U16; + pstcPwmInit->u32CompareMatchPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32PeriodMatchPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32StartStopHold = TMR6_PWM_START_STOP_CHANGE; + pstcPwmInit->u32CompareValue = u32RefRegRstValue; + i32Ret = LL_OK; + } + return i32Ret; +} +/** + * @} + */ + +#endif /* LL_TMR6_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmra.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmra.c new file mode 100644 index 0000000000..691034f9fe --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmra.c @@ -0,0 +1,1151 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmra.c + * @brief This file provides firmware functions to manage the TMRA(TimerA). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmra.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMRA TMRA + * @brief TMRA Driver Library + * @{ + */ + +#if (LL_TMRA_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMRA_Local_Macros TMRA Local Macros + * @{ + */ +/** + * @defgroup TMRA_Registers_Setting_definition TMRA Registers setting definition + * @{ + */ +#define TMRA_REG_TYPE uint16_t +#define TMRA_REG_VALUE_MAX (0xFFFFUL) + +#define SET_VAL_BY_ADDR(addr, v) (*(__IO TMRA_REG_TYPE *)(addr)) = (TMRA_REG_TYPE)(v) +#define GET_VAL_BY_ADDR(addr) (*(__IO TMRA_REG_TYPE *)(addr)) +/** + * @} + */ + +/** + * @defgroup TMRA_Configuration_Bit_Mask TMRA Configuration Bit Mask + * @{ + */ +#define TMRA_BCSTR_INT_MASK (TMRA_BCSTR_ITENUDF | TMRA_BCSTR_ITENOVF) +#define TMRA_BCSTR_FLAG_MASK (TMRA_BCSTR_UDFF | TMRA_BCSTR_OVFF) +#define TMRA_FCONR_FILTER_CLK_MASK (0x3UL) +#define TMRA_CCONR_FILTER_CLK_MASK (TMRA_CCONR_NOFICKCP) +#define TMRA_PWM_POLARITY_MASK (TMRA_PCONR_STAC) +/** + * @} + */ + +/** + * @defgroup TMRA_Filter_Pin_Max TMRA Pin With Filter Max + * @note TMRA_1 and TMRA_2 of HC32M423 do NOT contain pin TMRA_PIN_PWM2. + * @{ + */ +#define TMRA_PIN_MAX (TMRA_PIN_PWM8) +/** + * @} + */ + +/** + * @defgroup TMRA_Check_Parameters_Validity TMRA check parameters validity + * @{ + */ +#define IS_TMRA_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +/* Unit check */ +#define IS_TMRA_UNIT(x) \ +( ((x) == CM_TMRA_1) || \ + ((x) == CM_TMRA_2) || \ + ((x) == CM_TMRA_3) || \ + ((x) == CM_TMRA_4) || \ + ((x) == CM_TMRA_5) || \ + ((x) == CM_TMRA_6)) + +/* Sync unit check */ +#define IS_TMRA_SYNC_UNIT(x) \ +( ((x) == CM_TMRA_2) || \ + ((x) == CM_TMRA_3) || \ + ((x) == CM_TMRA_4) || \ + ((x) == CM_TMRA_5) || \ + ((x) == CM_TMRA_6)) + +#define IS_TMRA_CH(x) ((x) <= TMRA_CH8) + +/* Unit and channel */ +#define IS_TMRA_UNIT_CH(unit, ch) (IS_TMRA_UNIT(unit) && IS_TMRA_CH(ch)) + +#define IS_TMRA_CNT_SRC(x) (((x) == TMRA_CNT_SRC_SW) || ((x) == TMRA_CNT_SRC_HW)) + +#define IS_TMRA_FUNC(x) (((x) == TMRA_FUNC_CMP) || ((x) == TMRA_FUNC_CAPT)) + +#define IS_TMRA_DIR(x) (((x) == TMRA_DIR_DOWN) || ((x) == TMRA_DIR_UP)) + +#define IS_TMRA_MD(x) (((x) == TMRA_MD_SAWTOOTH) || ((x) == TMRA_MD_TRIANGLE)) + +/* Counter reload */ + +#define IS_TMRA_CMPVAL_BUF_CH(x) \ +( ((x) == TMRA_CH1) || ((x) == TMRA_CH3) || ((x) == TMRA_CH5) || ((x) == TMRA_CH7)) + +#define IS_TMRA_CLK_DIV(x) \ +( ((x) == TMRA_CLK_DIV1) || \ + ((x) == TMRA_CLK_DIV2) || \ + ((x) == TMRA_CLK_DIV4) || \ + ((x) == TMRA_CLK_DIV8) || \ + ((x) == TMRA_CLK_DIV16) || \ + ((x) == TMRA_CLK_DIV32) || \ + ((x) == TMRA_CLK_DIV64) || \ + ((x) == TMRA_CLK_DIV128) || \ + ((x) == TMRA_CLK_DIV256) || \ + ((x) == TMRA_CLK_DIV512) || \ + ((x) == TMRA_CLK_DIV1024)) + +#define IS_TMRA_FILTER_PIN(x) ((x) <= TMRA_PIN_MAX) + +#define IS_TMRA_CNT_UP_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CNT_UP_COND_ALL) + +#define IS_TMRA_CNT_DOWN_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CNT_DOWN_COND_ALL) + +#define IS_TMRA_INT(x) IS_TMRA_BIT_MASK(x, TMRA_INT_ALL) + +#define IS_TMRA_EVT(x) IS_TMRA_BIT_MASK(x, TMRA_EVT_ALL) + +#define IS_TMRA_FLAG(x) IS_TMRA_BIT_MASK(x, TMRA_FLAG_ALL) + +#define IS_TMRA_CAPT_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CAPT_COND_ALL) + +#define IS_TMRA_FILTER_CLK_DIV(x) ((x) <= TMRA_FILTER_CLK_DIV64) + +/* Special check of TMRA_1 & TMRA_2 of HC32M423 */ + +/* Unit and interrupt */ +#define IS_TMRA_UNIT_INT(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_INT(x)) + +/* Unit and event of channel */ +#define IS_TMRA_CH_EVT(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_EVT(x)) + +/* Unit and pin with filter */ +#define IS_TMRA_UNIT_FPIN(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_FILTER_PIN(x)) + +/* Unit and flag */ +#define IS_TMRA_UNIT_FLAG(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_FLAG(x)) + +#define IS_TMRA_CMPVAL_BUF_COND(x) \ +( ((x) == TMRA_BUF_TRANS_COND_OVF_UDF_CLR) || \ + ((x) == TMRA_BUF_TRANS_COND_PEAK) || \ + ((x) == TMRA_BUF_TRANS_COND_VALLEY) || \ + ((x) == TMRA_BUF_TRANS_COND_PEAK_VALLEY)) + +#define IS_TMRA_PWM_START_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD)) + +#define IS_TMRA_PWM_STOP_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD)) + +#define IS_TMRA_PWM_CMP_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD) || \ + ((x) == TMRA_PWM_INVT)) + +#define IS_TMRA_PWM_PERIOD_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD) || \ + ((x) == TMRA_PWM_INVT)) + +#define IS_TMRA_PWM_FORCE_POLARITY(x) \ +( ((x) == TMRA_PWM_FORCE_INVD) || \ + ((x) == TMRA_PWM_FORCE_LOW) || \ + ((x) == TMRA_PWM_FORCE_HIGH)) + +#define IS_TMRA_PWM_POLARITY(st, pol) \ +( (((st) == TMRA_CNT_STAT_START) && IS_TMRA_PWM_START_POLARITY(pol)) || \ + (((st) == TMRA_CNT_STAT_STOP) && IS_TMRA_PWM_STOP_POLARITY(pol)) || \ + (((st) == TMRA_CNT_STAT_MATCH_CMP) && IS_TMRA_PWM_CMP_POLARITY(pol)) || \ + (((st) == TMRA_CNT_STAT_MATCH_PERIOD) && IS_TMRA_PWM_PERIOD_POLARITY(pol))) + +#define IS_TMRA_START_COND(x) IS_TMRA_BIT_MASK((x), TMRA_START_COND_ALL) + +#define IS_TMRA_STOP_COND(x) IS_TMRA_BIT_MASK((x), TMRA_STOP_COND_ALL) + +#define IS_TMRA_CLR_COND(x) IS_TMRA_BIT_MASK((x), TMRA_CLR_COND_ALL) + +/** + * @} + */ + +/** + * @defgroup TMRA_Miscellaneous_Macros TMRA Miscellaneous Macros + * @{ + */ +#define TMRA_PIN_PWM_OFFSET (3U) + +#define TMRA_CH_NUM (8U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Functions TMRA Global Functions + * @{ + */ +/** + * @brief Initializes the specified TMRA peripheral according to the specified parameters + * in the structure stc_tmra_init_t + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] pstcTmraInit Pointer to a stc_tmra_init_t structure value that + * contains the configuration information for the TMRA. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTmraInit == NULL. + */ +int32_t TMRA_Init(CM_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcTmraInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + if (pstcTmraInit != NULL) { + DDL_ASSERT(IS_TMRA_CNT_SRC(pstcTmraInit->u8CountSrc)); + + if (pstcTmraInit->u8CountSrc == TMRA_CNT_SRC_SW) { + DDL_ASSERT(IS_TMRA_MD(pstcTmraInit->sw_count.u16CountMode)); + DDL_ASSERT(IS_TMRA_DIR(pstcTmraInit->sw_count.u16CountDir)); + DDL_ASSERT(IS_TMRA_CLK_DIV(pstcTmraInit->sw_count.u16ClockDiv)); + + WRITE_REG16(TMRAx->BCSTR, pstcTmraInit->sw_count.u16CountMode | \ + pstcTmraInit->sw_count.u16CountDir | \ + pstcTmraInit->sw_count.u16ClockDiv); + } else { + DDL_ASSERT(IS_TMRA_CNT_UP_COND(pstcTmraInit->hw_count.u16CountUpCond) || \ + (pstcTmraInit->hw_count.u16CountUpCond == TMRA_CNT_UP_COND_INVD)); + DDL_ASSERT(IS_TMRA_CNT_DOWN_COND(pstcTmraInit->hw_count.u16CountDownCond) || \ + (pstcTmraInit->hw_count.u16CountDownCond == TMRA_CNT_DOWN_COND_INVD)); + WRITE_REG16(TMRAx->HCUPR, pstcTmraInit->hw_count.u16CountUpCond); + WRITE_REG16(TMRAx->HCDOR, pstcTmraInit->hw_count.u16CountDownCond); + } + + /* Counter reload */ + + /* Specifies period value. */ + TMRA_SetPeriodValue(TMRAx, pstcTmraInit->u32PeriodValue); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set a default value for the TMRA initialization structure. + * @param [out] pstcTmraInit Pointer to a stc_tmra_init_t structure value that + * contains the configuration information for the TMRA. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTmraInit == NULL. + */ +int32_t TMRA_StructInit(stc_tmra_init_t *pstcTmraInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcTmraInit != NULL) { + pstcTmraInit->u8CountSrc = TMRA_CNT_SRC_SW; + pstcTmraInit->sw_count.u16ClockDiv = TMRA_CLK_DIV1; + pstcTmraInit->sw_count.u16CountMode = TMRA_MD_SAWTOOTH; + pstcTmraInit->sw_count.u16CountDir = TMRA_DIR_UP; + pstcTmraInit->u32PeriodValue = (TMRA_REG_TYPE)0xFFFFFFFFUL; + /* Counter reload */ + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Specifies the counting mode for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Mode Count mode. + * This parameter can be a value of @ref TMRA_Count_Mode + * @arg TMRA_MD_SAWTOOTH: Count mode is sawtooth wave. + * @arg TMRA_MD_TRIANGLE: Count mode is triangle wave. + * @retval None + */ +void TMRA_SetCountMode(CM_TMRA_TypeDef *TMRAx, uint16_t u16Mode) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_MD(u16Mode)); + MODIFY_REG16(TMRAx->BCSTR, TMRA_BCSTR_MODE, u16Mode); +} + +/** + * @brief Specifies the counting direction for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Dir Count direction. + * This parameter can be a value of @ref TMRA_Count_Dir + * @arg TMRA_DIR_DOWN: TMRA count down. + * @arg TMRA_DIR_UP: TMRA count up. + * @retval None + */ +void TMRA_SetCountDir(CM_TMRA_TypeDef *TMRAx, uint16_t u16Dir) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_DIR(u16Dir)); + MODIFY_REG16(TMRAx->BCSTR, TMRA_BCSTR_DIR, u16Dir); +} + +/** + * @brief Specifies the clcok divider for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Div Clcok divider. + * This parameter can be a value of @ref TMRA_Clock_Divider + * @retval None + */ +void TMRA_SetClockDiv(CM_TMRA_TypeDef *TMRAx, uint16_t u16Div) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CLK_DIV(u16Div)); + MODIFY_REG16(TMRAx->BCSTR, TMRA_BCSTR_CKDIV, u16Div); +} + +/** + * @brief Enable or disable the specified hardware count up condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware count up condition. + * This parameter can be values of @ref TMRA_Hard_Count_Up_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWCountUpCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CNT_UP_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCUPR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCUPR, u16Cond); + } +} + +/** + * @brief Enable or disable the specified hardware count down condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware count down condition. + * This parameter can be values of @ref TMRA_Hard_Count_Down_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWCountDownCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CNT_DOWN_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCDOR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCDOR, u16Cond); + } +} + +/** + * @brief Specifies function mode of TMRA. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Func Function mode of TRMA. + * This parameter can be a value of @ref TMRA_Function_Mode + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @retval None + */ +void TMRA_SetFunc(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Func) +{ + uint32_t u32CCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_FUNC(u16Func)); + + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (u32Ch * 4U); + MODIFY_REG16(RW_MEM16(u32CCONRAddr), TMRA_CCONR_CAPMD, u16Func); +} + +/** + * @brief Initializes the PWM according to the specified parameters + * in the structure stc_tmra_pwm_init_t + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] pstcPwmInit Pointer to a stc_tmra_pwm_init_t structure value that + * contains the configuration information for PWM. + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcPwmInit == NULL. + */ +int32_t TMRA_PWM_Init(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, const stc_tmra_pwm_init_t *pstcPwmInit) +{ + uint32_t u32CMPARAddr; + uint32_t u32PCONRAddr; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + + if (pstcPwmInit != NULL) { + DDL_ASSERT(IS_TMRA_PWM_START_POLARITY(pstcPwmInit->u16StartPolarity)); + DDL_ASSERT(IS_TMRA_PWM_STOP_POLARITY(pstcPwmInit->u16StopPolarity)); + DDL_ASSERT(IS_TMRA_PWM_CMP_POLARITY(pstcPwmInit->u16CompareMatchPolarity)); + DDL_ASSERT(IS_TMRA_PWM_PERIOD_POLARITY(pstcPwmInit->u16PeriodMatchPolarity)); + + u32Ch *= 4U; + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch; + SET_VAL_BY_ADDR(u32CMPARAddr, pstcPwmInit->u32CompareValue); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + u32Ch; + RW_MEM16(u32PCONRAddr) = (uint16_t)((pstcPwmInit->u16StartPolarity << TMRA_PCONR_STAC_POS) | \ + (pstcPwmInit->u16StopPolarity << TMRA_PCONR_STPC_POS) | \ + (pstcPwmInit->u16CompareMatchPolarity << TMRA_PCONR_CMPC_POS) | \ + (pstcPwmInit->u16PeriodMatchPolarity << TMRA_PCONR_PERC_POS)); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set a default value for the PWM initialization structure. + * @param [out] pstcPwmInit Pointer to a stc_tmra_pwm_init_t structure value that + * contains the configuration information for PWM. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcPwmInit == NULL. + */ +int32_t TMRA_PWM_StructInit(stc_tmra_pwm_init_t *pstcPwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcPwmInit != NULL) { + pstcPwmInit->u32CompareValue = TMRA_REG_VALUE_MAX; + pstcPwmInit->u16StartPolarity = TMRA_PWM_HIGH; + pstcPwmInit->u16StopPolarity = TMRA_PWM_LOW; + pstcPwmInit->u16CompareMatchPolarity = TMRA_PWM_INVT; + pstcPwmInit->u16PeriodMatchPolarity = TMRA_PWM_INVT; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Enable or disable the PWM ouput of the specified channel. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_PWM_OutputCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U); + WRITE_REG32(PERIPH_BIT_BAND(u32PCONRAddr, TMRA_PCONR_OUTEN_POS), enNewState); +} + +/** + * @brief Specifies the ouput polarity of the PWM at the specified state of counter. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value @ref TMRA_Channel + * @param [in] u8CountState TMRA counter state. + * This parameter can be a value @ref TMRA_Counter_State + * @param [in] u16Polarity The polarity of PWM. + * This parameter can be a value @ref TMRA_PWM_Polarity + * @retval None + * @note The polarity(high or low) of couting start is only valid when the clock is not divided(BCSTR.CKDIV == 0). + */ +void TMRA_PWM_SetPolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint8_t u8CountState, uint16_t u16Polarity) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_PWM_POLARITY(u8CountState, u16Polarity)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U); + MODIFY_REG16(RW_MEM16(u32PCONRAddr), + (uint16_t)TMRA_PWM_POLARITY_MASK << (u8CountState * 2U), + u16Polarity << (u8CountState * 2U)); +} + +/** + * @brief Specifies the force polarity of the PWM. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value @ref TMRA_Channel + * @param [in] u16Polarity The force polarity of PWM. + * This parameter can be a value @ref TMRA_PWM_Force_Polarity + * @retval None + */ +void TMRA_PWM_SetForcePolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Polarity) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_PWM_FORCE_POLARITY(u16Polarity)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U); + MODIFY_REG16(RW_MEM16(u32PCONRAddr), TMRA_PCONR_FORC, u16Polarity); +} + +/** + * @brief Enable or disable the specified capture condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value @ref TMRA_Channel + * @param [in] u16Cond The capture condition. + * This parameter can be a value @ref TMRA_Capture_Cond + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWCaptureCondCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState) +{ + uint32_t u32CCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_CAPT_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + +#if defined __DEBUG + if ((u16Cond & (TMRA_CAPT_COND_TRIG_RISING | TMRA_CAPT_COND_TRIG_FALLING)) != 0U) { + DDL_ASSERT(u32Ch == TMRA_CH3); + } +#endif + + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (u32Ch * 4U); + if (enNewState == ENABLE) { + SET_REG16_BIT(RW_MEM16(u32CCONRAddr), u16Cond); + } else { + CLR_REG16_BIT(RW_MEM16(u32CCONRAddr), u16Cond); + } +} + +/** + * @brief Enable or disable hardware start condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware start condition. + * This parameter can be a value @ref TMRA_Hardware_Start_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWStartCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_START_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCONR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCONR, u16Cond); + } +} + +/** + * @brief Enable or disable hardware stop condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware stop condition. + * This parameter can be a value @ref TMRA_Hardware_Stop_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWStopCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_STOP_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCONR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCONR, u16Cond); + } +} + +/** + * @brief Enable or disable hardware clear condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware clear condition. + * This parameter can be a value @ref TMRA_Hardware_Clear_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWClearCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CLR_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCONR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCONR, u16Cond); + } +} + +/** + * @brief Specifies the clock divider of filter. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Pin The pin with filter of TMRA. + * This parameter can be a value of @ref TMRA_Filter_Pin + * @param [in] u16Div The clock source divider of the filter. + * This parameter can be a value of @ref TMRA_Filter_Clock_Divider + * @arg TMRA_FILTER_CLK_DIV1: The filter clock is the clock of timerA / 1. + * @arg TMRA_FILTER_CLK_DIV4: The filter clock is the clock of timerA / 4. + * @arg TMRA_FILTER_CLK_DIV16: The filter clock is the clock of timerA / 16. + * @arg TMRA_FILTER_CLK_DIV64: The filter clock is the clock of timerA / 64. + * @retval None + */ +void TMRA_SetFilterClockDiv(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, uint16_t u16Div) +{ + uint32_t u32Ch; + uint32_t u32CCONRAddr; + const uint8_t au8Offset[] = { + TMRA_FCONR_NOFICKTG_POS, TMRA_FCONR_NOFICKCA_POS, TMRA_FCONR_NOFICKCB_POS, + }; + + DDL_ASSERT(IS_TMRA_UNIT_FPIN(TMRAx, u32Pin)); + DDL_ASSERT(IS_TMRA_FILTER_CLK_DIV(u16Div)); + + if (u32Pin < TMRA_PIN_PWM_OFFSET) { + MODIFY_REG16(TMRAx->FCONR, + (TMRA_FCONR_FILTER_CLK_MASK << au8Offset[u32Pin]), + (u16Div << au8Offset[u32Pin])); + } else { + u32Ch = u32Pin - TMRA_PIN_PWM_OFFSET; + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + u32Ch * 4U; + MODIFY_REG16(RW_MEM16(u32CCONRAddr), + TMRA_CCONR_FILTER_CLK_MASK, + (u16Div << TMRA_CCONR_NOFICKCP_POS)); + } +} + +/** + * @brief Enable or disable the filter function of the specified TMRA input pin. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Pin The pin with filter of TMRA. + * This parameter can be values of @ref TMRA_Filter_Pin + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_FilterCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, en_functional_state_t enNewState) +{ + uint8_t u8EnPos; + uint32_t u32Ch; + uint32_t u32RegAddr; + const uint8_t au8Offset[] = { + TMRA_FCONR_NOFIENTG_POS, TMRA_FCONR_NOFIENCA_POS, TMRA_FCONR_NOFIENCB_POS, + }; + + DDL_ASSERT(IS_TMRA_UNIT_FPIN(TMRAx, u32Pin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (u32Pin < TMRA_PIN_PWM_OFFSET) { + u32RegAddr = (uint32_t)&TMRAx->FCONR; + u8EnPos = au8Offset[u32Pin]; + } else { + u32Ch = u32Pin - TMRA_PIN_PWM_OFFSET; + u32RegAddr = (uint32_t)&TMRAx->CCONR1 + u32Ch * 4U; + u8EnPos = TMRA_CCONR_NOFIENCP_POS; + } + WRITE_REG32(PERIPH_BIT_BAND(u32RegAddr, u8EnPos), enNewState); +} + +/** + * @brief De-initializes the TMRA peripheral. Reset all registers of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval None + */ +void TMRA_DeInit(CM_TMRA_TypeDef *TMRAx) +{ + uint32_t i; + uint32_t u32ChNum = TMRA_CH_NUM; + uint32_t u32AddrOffset; + uint32_t u32PERARAddr; + uint32_t u32CNTERAddr; + uint32_t u32CMPARAddr; + uint32_t u32CCONRAddr; + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + + u32PERARAddr = (uint32_t)&TMRAx->PERAR; + u32CNTERAddr = (uint32_t)&TMRAx->CNTER; + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1; + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1; + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1; + + for (i = 0U; i < u32ChNum; i++) { + u32AddrOffset = i * 4U; + RW_MEM16(u32CMPARAddr + u32AddrOffset) = 0xFFFFU; + RW_MEM16(u32CCONRAddr + u32AddrOffset) = 0x0U; + RW_MEM16(u32PCONRAddr + u32AddrOffset) = 0x0U; + } + + SET_VAL_BY_ADDR(u32PERARAddr, 0xFFFFFFFFUL); + SET_VAL_BY_ADDR(u32CNTERAddr, 0x0U); + WRITE_REG16(TMRAx->BCSTR, 0x2U); + WRITE_REG16(TMRAx->ICONR, 0x0U); + WRITE_REG16(TMRAx->ECONR, 0x0U); + WRITE_REG16(TMRAx->FCONR, 0x0U); + WRITE_REG16(TMRAx->STFLR, 0x0U); + WRITE_REG16(TMRAx->HCONR, 0x0U); + WRITE_REG16(TMRAx->HCUPR, 0x0U); + WRITE_REG16(TMRAx->HCDOR, 0x0U); + + WRITE_REG16(TMRAx->BCONR1, 0x0U); + WRITE_REG16(TMRAx->BCONR2, 0x0U); + WRITE_REG16(TMRAx->BCONR3, 0x0U); + WRITE_REG16(TMRAx->BCONR4, 0x0U); +} + +/** + * @brief Get the counting direction of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval An uint16_t type value of counting direction. + * -TMRA_DIR_DOWN: TMRA count down. + * -TMRA_DIR_UP: TMRA count up. + */ +uint16_t TMRA_GetCountDir(const CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return READ_REG16_BIT(TMRAx->BCSTR, TMRA_BCSTR_DIR); +} + +/** + * @brief Set period value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Value The period value to be set. + * This parameter can be a number between: + * 0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472. + * 0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. + * @retval None + */ +void TMRA_SetPeriodValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value) +{ + uint32_t u32PERARAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + u32PERARAddr = (uint32_t)&TMRAx->PERAR; + SET_VAL_BY_ADDR(u32PERARAddr, u32Value); +} + +/** + * @brief Get period value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval An uint32_t type type value of period value between: + * - 0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472. + * - 0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. + */ +uint32_t TMRA_GetPeriodValue(const CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return (TMRAx->PERAR); +} + +/** + * @brief Set general counter value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Value The general counter value to be set. + * This parameter can be a number between: + * 0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472. + * 0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. + * @retval None + */ +void TMRA_SetCountValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value) +{ + uint32_t u32CNTERAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + u32CNTERAddr = (uint32_t)&TMRAx->CNTER; + SET_VAL_BY_ADDR(u32CNTERAddr, u32Value); +} + +/** + * @brief Get general counter value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval An uint32_t type type value of counter value between: + * - 0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472. + * - 0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. + */ +uint32_t TMRA_GetCountValue(const CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return (TMRAx->CNTER); +} + +/** + * @brief Set comparison value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @param [in] u32Value The comparison value to be set. + * This parameter can be a number between: + * 0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472. + * 0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. + * @retval None + */ +void TMRA_SetCompareValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint32_t u32Value) +{ + uint32_t u32CMPARAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch * 4U; + SET_VAL_BY_ADDR(u32CMPARAddr, u32Value); +} + +/** + * @brief Get comparison value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @retval An uint32_t type type value of comparison value value between: + * - 0UL and 0xFFFFFFFFUL for TimerA1 and TimerA2 of HC32F472. + * - 0UL and 0xFFFFUL for TimerA3/4/5/6 of HC32F472 and all TimerA units of other MCUs. + */ +uint32_t TMRA_GetCompareValue(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch) +{ + uint32_t u32CMPARAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch * 4U; + return GET_VAL_BY_ADDR(u32CMPARAddr); +} + +/* Sync start. */ +/** + * @brief Enable or disable synchronous-start. When an even unit enables synchronous-start function, + * start the symmetric odd unit can start the even unit at the same time. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x(x is an even number) + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_SyncStartCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_TMRA_SYNC_UNIT(TMRAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&TMRAx->BCSTR; + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, TMRA_BCSTR_SYNST_POS), enNewState); +} + +/* Reload and continue counting when overflow/underflow? */ + +/** + * @brief Specifies the condition of compare value buffer transmission. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be one of the odd channels of @ref TMRA_Channel + * @param [in] u16Cond Buffer condition of the specified TMRA unit. + * This parameter can be a value of @ref TMRA_Cmp_Value_Buf_Trans_Cond + * @arg TMRA_BUF_TRANS_COND_OVF_UDF_CLR: This configuration value applies to non-triangular wave counting mode. + * When counting overflow or underflow or counting register was cleared, + * transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). + * @arg TMRA_BUF_TRANS_COND_PEAK: In triangle wave count mode, when count reached peak, + * transfer CMMARm(m=2,4,6,8,...) to CMMARn(n=1,3,5,7,...). + * @arg TMRA_BUF_TRANS_COND_VALLEY: In triangle wave count mode, when count reached valley, + * transfer CMMARm(m=2,4,6,8,...) to CMMARn(n=1,3,5,7,...). + * @retval None + */ +void TMRA_SetCompareBufCond(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond) +{ + uint32_t u32BCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CMPVAL_BUF_CH(u32Ch)); + DDL_ASSERT(IS_TMRA_CMPVAL_BUF_COND(u16Cond)); + + u32BCONRAddr = (uint32_t)&TMRAx->BCONR1 + u32Ch * 4U; + MODIFY_REG16(RW_MEM16(u32BCONRAddr), TMRA_BUF_TRANS_COND_PEAK_VALLEY, u16Cond); +} + +/** + * @brief Enable or disable compare value buffer. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be one of the odd channels of @ref TMRA_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_CompareBufCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32BCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CMPVAL_BUF_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32BCONRAddr = (uint32_t)&TMRAx->BCONR1 + u32Ch * 4U; + WRITE_REG32(PERIPH_BIT_BAND(u32BCONRAddr, TMRA_BCONR_BEN_POS), enNewState); +} + +/** + * @brief Get the status of the specified flag. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Flag The status flags of TMRA. + * This parameter can be a value of @ref TMRA_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMRA_GetStatus(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag) +{ + uint16_t u16BCSTR; + uint16_t u16STFLR; + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_TMRA_UNIT_FLAG(TMRAx, u32Flag)); + + u16BCSTR = (uint16_t)(u32Flag & TMRA_BCSTR_FLAG_MASK); + u16STFLR = (uint16_t)(u32Flag >> 16U); + u16BCSTR = READ_REG16_BIT(TMRAx->BCSTR, u16BCSTR); + u16STFLR = READ_REG16_BIT(TMRAx->STFLR, u16STFLR); + + if ((u16BCSTR != 0U) || (u16STFLR != 0U)) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified flags. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Flag The status flags of TMRA. + * This parameter can be values of @ref TMRA_Status_Flag + * @retval None + */ +void TMRA_ClearStatus(CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_TMRA_UNIT_FLAG(TMRAx, u32Flag)); + + CLR_REG16_BIT(TMRAx->BCSTR, u32Flag & TMRA_BCSTR_FLAG_MASK); + CLR_REG16_BIT(TMRAx->STFLR, u32Flag >> 16U); +} + +/** + * @brief Enable of disable the specified interrupts of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32IntType The interrupt type of TMRA. + * This parameter can be values of @ref TMRA_Interrupt_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_IntCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32BCSTR; + uint32_t u32ICONR; + + DDL_ASSERT(IS_TMRA_UNIT_INT(TMRAx, u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32BCSTR = u32IntType & TMRA_BCSTR_INT_MASK; + u32ICONR = u32IntType >> 16U; + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->BCSTR, u32BCSTR); + SET_REG16_BIT(TMRAx->ICONR, u32ICONR); + } else { + CLR_REG16_BIT(TMRAx->BCSTR, u32BCSTR); + CLR_REG16_BIT(TMRAx->ICONR, u32ICONR); + } +} + +/** + * @brief Enable of disable the specified event of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32EventType The event type of TMRA. + * This parameter can be values of @ref TMRA_Event_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_EventCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32EventType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_CH_EVT(TMRAx, u32EventType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->ECONR, u32EventType); + } else { + CLR_REG16_BIT(TMRAx->ECONR, u32EventType); + } +} + +/** + * @brief Start the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval None + */ +void TMRA_Start(CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + SET_REG16_BIT(TMRAx->BCSTR, TMRA_BCSTR_START); +} + +/** + * @brief Stop the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval None + */ +void TMRA_Stop(CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + CLR_REG16_BIT(TMRAx->BCSTR, TMRA_BCSTR_START); +} +/** + * @} + */ + +#endif /* LL_TMRA_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_trng.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_trng.c new file mode 100644 index 0000000000..ef9ca161f5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_trng.c @@ -0,0 +1,216 @@ +/** + ******************************************************************************* + * @file hc32_ll_trng.c + * @brief This file provides firmware functions to manage the True Random + * Number Generator(TRNG). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_trng.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TRNG TRNG + * @brief TRNG Driver Library + * @{ + */ + +#if (LL_TRNG_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TRNG_Local_Macros TRNG Local Macros + * @{ + */ +#define TRNG_TIMEOUT (20000UL) + +/** + * @defgroup TRNG_Check_Parameters_Validity TRNG Check Parameters Validity + * @{ + */ +#define IS_TRNG_SHIFT_CNT(x) \ +( ((x) == TRNG_SHIFT_CNT32) || \ + ((x) == TRNG_SHIFT_CNT64) || \ + ((x) == TRNG_SHIFT_CNT128) || \ + ((x) == TRNG_SHIFT_CNT256)) + +#define IS_RNG_RELOAD_INIT_VAL_EN(x) \ +( ((x) == TRNG_RELOAD_INIT_VAL_ENABLE) || \ + ((x) == TRNG_RELOAD_INIT_VAL_DISABLE)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TRNG_Global_Functions TRNG Global Functions + * @{ + */ + +/** + * @brief Initializes TRNG. + * @param [in] u32ShiftCount TRNG shift control. This parameter can be a value of @ref TRNG_Shift_Ctrl + * @arg TRNG_SHIFT_CNT32: Shift 32 times when capturing random noise. + * @arg TRNG_SHIFT_CNT64: Shift 64 times when capturing random noise. + * @arg TRNG_SHIFT_CNT128: Shift 128 times when capturing random noise. + * @arg TRNG_SHIFT_CNT256: Shift 256 times when capturing random noise. + * @param [in] u32ReloadInitValueEn Enable or disable load new initial value. + * This parameter can be a value of @ref TRNG_Reload_Init_Value + * @arg TRNG_RELOAD_INIT_VAL_ENABLE: Enable load new initial value. + * @arg TRNG_RELOAD_INIT_VAL_DISABLE: Disable load new initial value. + * @retval None + */ +void TRNG_Init(uint32_t u32ShiftCount, uint32_t u32ReloadInitValueEn) +{ + DDL_ASSERT(IS_TRNG_SHIFT_CNT(u32ShiftCount)); + DDL_ASSERT(IS_RNG_RELOAD_INIT_VAL_EN(u32ReloadInitValueEn)); + WRITE_REG32(CM_TRNG->MR, u32ShiftCount | u32ReloadInitValueEn); +} + +/** + * @brief Start TRNG and get random number. + * @param [out] pu32Random The destination buffer to store the random number. + * @param [in] u8RandomLen The size(in word) of the destination buffer. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: Works timeout. + * - LL_ERR_INVD_PARAM: pu32Random == NULL or u8RandomLen == 0 + */ +int32_t TRNG_GenerateRandom(uint32_t *pu32Random, uint8_t u8RandomLen) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + __IO uint32_t u32TimeCount = TRNG_TIMEOUT; + + if ((pu32Random != NULL) && (u8RandomLen > 0U)) { + /* Enable TRNG circuit. */ + WRITE_REG32(bCM_TRNG->CR_b.EN, 1U); + /* Start TRNG */ + WRITE_REG32(bCM_TRNG->CR_b.RUN, 1U); + /* Wait generating done. */ + i32Ret = LL_ERR_TIMEOUT; + while (u32TimeCount-- != 0UL) { + if (READ_REG32(bCM_TRNG->CR_b.RUN) == 0U) { + i32Ret = LL_OK; + break; + } + } + + if (i32Ret == LL_OK) { + /* Get the random number. */ + pu32Random[0U] = READ_REG32(CM_TRNG->DR0); + if (u8RandomLen > 1U) { + pu32Random[1U] = READ_REG32(CM_TRNG->DR1); + } + } else { + /* Stop TRNG */ + WRITE_REG32(bCM_TRNG->CR_b.RUN, 0U); + } + /* Disable TRNG circuit. */ + CLR_REG32_BIT(CM_TRNG->CR, TRNG_CR_EN); + } + + return i32Ret; +} + +/** + * @brief Start TRNG + * @param None + * @retval None + */ +void TRNG_Start(void) +{ + /* Enable TRNG circuit. */ + WRITE_REG32(bCM_TRNG->CR_b.EN, 1U); + /* Start TRNG */ + WRITE_REG32(bCM_TRNG->CR_b.RUN, 1U); +} + +/** + * @brief Get random number. + * @param [out] pu32Random The destination buffer to store the random number. + * @param [in] u8RandomLen The size(in word) of the destination buffer. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pu32Random == NULL or u8RandomLen == 0 + */ +int32_t TRNG_GetRandom(uint32_t *pu32Random, uint8_t u8RandomLen) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pu32Random != NULL) && (u8RandomLen > 0U)) { + /* Get the random number. */ + pu32Random[0U] = READ_REG32(CM_TRNG->DR0); + if (u8RandomLen > 1U) { + pu32Random[1U] = READ_REG32(CM_TRNG->DR1); + } + /* Disable TRNG circuit. */ + CLR_REG32_BIT(CM_TRNG->CR, TRNG_CR_EN); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_TRNG_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_usart.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_usart.c new file mode 100644 index 0000000000..50266f9517 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_usart.c @@ -0,0 +1,1926 @@ +/** + ******************************************************************************* + * @file hc32_ll_usart.c + * @brief This file provides firmware functions to manage the USART(Universal + * Synchronous/Asynchronous Receiver Transmitter). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_usart.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_USART USART + * @brief USART Driver Library + * @{ + */ + +#if (LL_USART_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup USART_Local_Macros USART Local Macros + * @{ + */ + +/** + * @defgroup USART_Check_Parameters_Validity USART Check Parameters Validity + * @{ + */ + +/** + * @defgroup USART_Check_Parameters_Validity_Unit USART Check Parameters Validity Unit + * @{ + */ +#define IS_USART_UNIT(x) \ +( ((x) == CM_USART1) || \ + ((x) == CM_USART2) || \ + ((x) == CM_USART3) || \ + ((x) == CM_USART4)) +#define IS_USART_INTEGER_UNIT(x) (!IS_USART_UNIT(x)) +#define IS_USART_SMARTCARD_UNIT(x) (IS_USART_UNIT(x)) +#define IS_USART_TIMEOUT_UNIT(x) (IS_USART_UNIT(x)) + +/** + * @} + */ + +#define IS_USART_FUNC(x) \ +( ((x) != 0UL) && \ + (((x) | USART_FUNC_ALL) == USART_FUNC_ALL)) + +#define IS_USART_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | USART_FLAG_ALL) == USART_FLAG_ALL)) + +#define IS_USART_TRANS_TYPE(x) \ +( ((x) == USART_TRANS_ID) || \ + ((x) == USART_TRANS_DATA)) + +#define IS_USART_PARITY(x) \ +( ((x) == USART_PARITY_ODD) || \ + ((x) == USART_PARITY_EVEN) || \ + ((x) == USART_PARITY_NONE)) + +#define IS_USART_DATA_WIDTH(x) \ +( ((x) == USART_DATA_WIDTH_8BIT) || \ + ((x) == USART_DATA_WIDTH_9BIT)) + +#define IS_USART_STOPBIT(x) \ +( ((x) == USART_STOPBIT_1BIT) || \ + ((x) == USART_STOPBIT_2BIT)) + +#define IS_USART_FIRST_BIT(x) \ +( ((x) == USART_FIRST_BIT_MSB) || \ + ((x) == USART_FIRST_BIT_LSB)) + +#define IS_USART_OVER_SAMPLE_BIT(x) \ +( ((x) == USART_OVER_SAMPLE_8BIT) || \ + ((x) == USART_OVER_SAMPLE_16BIT)) + +#define IS_USART_START_BIT_POLARITY(x) \ +( ((x) == USART_START_BIT_LOW) || \ + ((x) == USART_START_BIT_FALLING)) + +#define IS_USART_CLK_SRC(x) \ +( ((x) == USART_CLK_SRC_EXTCLK) || \ + ((x) == USART_CLK_SRC_INTERNCLK)) + +#define IS_USART_CK_OUTPUT(x) \ +( ((x) == USART_CK_OUTPUT_ENABLE) || \ + ((x) == USART_CK_OUTPUT_DISABLE)) + +#define IS_USART_CLK_DIV(x) \ +( ((x) == USART_CLK_DIV1) || \ + ((x) == USART_CLK_DIV4) || \ + ((x) == USART_CLK_DIV16) || \ + ((x) == USART_CLK_DIV64)) + +#define IS_USART_DATA(x) ((x) <= 0x01FFUL) + +/** + * @defgroup USART_Check_Parameters_Validity_Hardware_Flow_Control USART Check Parameters Validity Hardware Flow Control + * @{ + */ +#define IS_USART_HW_FLOWCTRL(x) \ +( ((x) == USART_HW_FLOWCTRL_CTS) || \ + ((x) == USART_HW_FLOWCTRL_RTS)) +/** + * @} + */ + +/** + * @defgroup USART_Check_Parameters_Validity_Smartcard_Clock USART Check Parameters Validity Smartcard Clock + * @{ + */ +#define IS_USART_SMARTCARD_ETU_CLK(x) \ +( ((x) == USART_SC_ETU_CLK32) || \ + ((x) == USART_SC_ETU_CLK64) || \ + ((x) == USART_SC_ETU_CLK128) || \ + ((x) == USART_SC_ETU_CLK256) || \ + ((x) == USART_SC_ETU_CLK372)) +/** + * @} + */ + +/** + * @defgroup USART_Check_Parameters_Validity_Stopmode_Filter USART Check Parameters Validity Stopmode Filter + * @{ + */ +/** + * @} + */ + +/** + * @defgroup USART_Check_Parameters_Validity_Timeout_Function USART Check Parameters Validity Timeout Function + * @{ + */ +/** + * @} + */ + +/** + * @defgroup USART_Check_Parameters_Validity_LIN_Function USART Check Parameters Validity LIN Function + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup USART_Flag_Error_Mask USART Flag Error Mask + * @{ + */ +#define USART_FLAG_ERR_MASK (USART_FLAG_OVERRUN | \ + USART_FLAG_FRAME_ERR | \ + USART_FLAG_PARITY_ERR) +/** + * @} + */ + +/** + * @defgroup USART_Registers_Reset_Value_definition USART Registers Reset Value + * @{ + */ +#define USART_CR1_RST_VALUE (0x80000000UL) + +#define USART_CR2_RST_VALUE (0UL) +/** + * @} + */ + +/** + * @defgroup USART_Data_Register USART Data Register + * @{ + */ +#define USART_TXD_ADDR(_UNITx_) ((uint32_t)(&(_UNITx_)->DR)) +#define USART_RXD_ADDR(_UNITx_) ((uint32_t)(&(_UNITx_)->DR) + 2UL) + +#define USART_TXD(_UNITx_) ((__IO uint16_t *)USART_TXD_ADDR(_UNITx_)) +#define USART_RXD(_UNITx_) ((__IO uint16_t *)USART_RXD_ADDR(_UNITx_)) +/** + * @} + */ + +/** + * @defgroup USART_Redefine_Bits USART Redefine Bits + * @{ + */ +#define USART_CR_SCEN (0x00000020UL) +#define USART_CR_FBME (0x20000000UL) +#define USART_BRR_DIV_FRACTION_MASK (0x0000007FUL) +/** + * @} + */ + +/** + * @defgroup USART_BRR_Division_Max USART BRR Register Division Max + * @{ + */ +#define USART_BRR_DIV_INTEGER_MAX (0xFFUL) +#define USART_BRR_DIV_FRACTION_MAX (0x7FUL) +/** + * @} + */ + +/** + * @defgroup USART_Default_Baudrate USART Default Baudrate + * @{ + */ +#define USART_DEFAULT_BAUDRATE (9600UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup USART_Local_Functions USART Local Functions + * @{ + */ +/** + * @brief Try to wait the expected status of specified flags + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Flag USART flag + * This parameter can be one of the following values: + * @arg USART_FLAG_RX_FULL: Receive data register not empty flag + * @arg USART_FLAG_TX_CPLT: Transmission complete flag + * @arg USART_FLAG_TX_EMPTY: Transmit data register empty flag + * @arg USART_FLAG_OVERRUN: Overrun error flag + * @arg USART_FLAG_FRAME_ERR: Framing error flag + * @arg USART_FLAG_PARITY_ERR:Parity error flag + * @arg USART_FLAG_RX_TIMEOUT: Receive timeout flag + * @arg USART_FLAG_MX_PROCESSOR: Receive processor ID flag + * @arg USART_FLAG_LIN_ERR: LIN bus error flag + * @arg USART_FLAG_LIN_WKUP: LIN wakeup signal detection flag + * @arg USART_FLAG_LIN_BREAK: LIN break signal detection flag + * @param [in] enStatus Expected status + * This parameter can be one of the following values: + * @arg SET: Wait flag set + * @arg RESET: Wait flag reset + * @param [in] u32Timeout Maximum count(Max value @ref USART_Max_Timeout) of trying to get status + * @retval int32_t: + * - LL_OK: Complete wait the expected status of the specified flags. + * - LL_ERR_TIMEOUT: Wait timeout. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT. + */ +static int32_t USART_WaitStatus(const CM_USART_TypeDef *USARTx, + uint32_t u32Flag, + en_flag_status_t enStatus, + uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32To = 0UL; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FLAG(u32Flag)); + + while (USART_GetStatus(USARTx, u32Flag) != enStatus) { + /* Block checking flag if timeout value is USART_TIMEOUT_MAX */ + if ((u32To > u32Timeout) && (u32Timeout < USART_MAX_TIMEOUT)) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + + u32To++; + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate integer division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + */ +static int32_t UART_CalculateDivInteger(const CM_USART_TypeDef *USARTx, + uint32_t u32UsartClk, uint32_t u32Baudrate, + uint32_t *pu32DivInteger, float32_t *pf32Error) +{ + uint32_t B; + uint32_t C; + uint32_t OVER8; + uint64_t u64Temp; + uint32_t DIV_Integer; + float32_t f32Err; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((NULL != pu32DivInteger) && (C > 0UL) && (B > 0UL)) { + OVER8 = (0UL == READ_REG32_BIT(USARTx->CR1, USART_CR1_OVER8)) ? 0UL : 1UL; + + /* UART mode baudrate integer calculation formula: */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV_Integer = ((((C * 10UL) / (B * 8UL * (2UL - OVER8))) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */ + + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + *pu32DivInteger = DIV_Integer; + + if (NULL != pf32Error) { + /* E(%) = C / (8 * (2 - OVER8) * (DIV_Integer + 1) * B) - 1 */ + + /* u64Temp = (8 * (2 - OVER8) * (DIV_Integer + 1) * B) */ + u64Temp = (uint64_t)((uint64_t)8UL * ((uint64_t)2UL - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + \ + (uint64_t)1UL) * (uint64_t)B); + f32Err = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + + *pf32Error = f32Err; + } + + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate integer division for clock synchronization mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + */ +static int32_t ClockSync_CalculateDivInteger(const CM_USART_TypeDef *USARTx, + uint32_t u32UsartClk, uint32_t u32Baudrate, + uint32_t *pu32DivInteger, float32_t *pf32Error) +{ + uint32_t B; + uint32_t C; + float32_t f32Err; + uint64_t u64Temp; + uint32_t DIV_Integer; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((NULL != pu32DivInteger) && (C > 0UL) && (B > 0UL)) { + /* Clock sync mode baudrate integer calculation formula: */ + /* B = C / (4 * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 4)) - 1 */ + DIV_Integer = ((((C * 10UL) / (B * 4UL)) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */ + + if ((DIV_Integer > 0UL) && (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX)) { + *pu32DivInteger = DIV_Integer; + + if (NULL != pf32Error) { + /* E(%) = C / (4 * (DIV_Integer + 1) * B) - 1 */ + + /* u64Temp = 4 * (DIV_Integer + 1) * B */ + u64Temp = (uint64_t)((uint64_t)4U * ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B); + f32Err = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + + *pf32Error = f32Err; + } + + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate integer division for smart-card mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + */ +static int32_t SmartCard_CalculateDivInteger(const CM_USART_TypeDef *USARTx, + uint32_t u32UsartClk, uint32_t u32Baudrate, + uint32_t *pu32DivInteger, float32_t *pf32Error) +{ + uint32_t B; + uint32_t C; + uint32_t BCN; + uint64_t u64Temp; + uint32_t DIV_Integer; + const uint16_t au16EtuClkCnts[] = {32U, 64U, 93U, 128U, 186U, 256U, 372U, 512U}; + float32_t f32Err; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((NULL != pu32DivInteger) && (C > 0UL) && (B > 0UL)) { + /* Smartcard mode baudrate integer calculation formula: */ + /* B = C / (2 * BCN * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 2 * BCN)) - 1 */ + + BCN = READ_REG32_BIT(USARTx->CR3, USART_CR3_BCN); + DDL_ASSERT(IS_USART_SMARTCARD_ETU_CLK(BCN)); + BCN = au16EtuClkCnts[BCN >> USART_CR3_BCN_POS]; + + DIV_Integer = (((C * 10UL) / (B * BCN * 2UL) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */ + + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + *pu32DivInteger = DIV_Integer; + + if (NULL != pf32Error) { + /* E(%) = C / (2 * BCN * (DIV_Integer + 1) * B) - 1 */ + + /* u64Temp = 4 * (DIV_Integer + 1) * B */ + u64Temp = (uint64_t)((uint64_t)2UL * BCN * ((uint64_t)DIV_Integer + (uint64_t)1UL) * B); + f32Err = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + + *pf32Error = f32Err; + } + + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate fraction division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pu32DivFraction Pointer to BRR fraction divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + */ +static int32_t UART_CalculateDivFraction(const CM_USART_TypeDef *USARTx, uint32_t u32UsartClk, + uint32_t u32Baudrate, uint32_t *pu32DivInteger, + uint32_t *pu32DivFraction, float32_t *pf32Error) +{ + uint32_t B; + uint32_t C; + uint32_t OVER8; + float32_t f32Err; + uint64_t u64Temp; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_Fraction; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check parameter */ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((NULL != pu32DivInteger) && (NULL != pu32DivFraction) && (C > 0UL) && (B > 0UL)) { + OVER8 = (0UL == READ_REG32_BIT(USARTx->CR1, USART_CR1_OVER8)) ? 0UL : 1UL; + + /* UART mode baudrate integer calculation formula: */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV_Integer = (C / (B * 8UL * (2UL - OVER8))) - 1UL; + + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + /* UART mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (256 * (8 * (2 - OVER8) * (DIV_Integer + 1) * B) / C) - 128 */ + + /* u64Temp = (8 * (2 - OVER8) * (DIV_Integer + 1) * B) */ + u64Temp = (uint64_t)((uint64_t)8UL * ((uint64_t)2UL - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + \ + (uint64_t)1UL) * (uint64_t)B); + + DIV_Fraction = (uint32_t)(256UL * u64Temp / C - 128UL); + + if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) { + *pu32DivInteger = DIV_Integer; + *pu32DivFraction = DIV_Fraction; + + if (NULL != pf32Error) { + /* E(%) = C * (128 + DIV_Fraction) / (256 * (8 * (2 - OVER8) * (DIV_Integer + 1) * B)) - 1 */ + u64Temp *= (uint64_t)256UL; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32Err = (float32_t)((float64_t)(u64Dividend) / (float64_t)(u64Temp)) - 1.0F; + + *pf32Error = f32Err; + } + + i32Ret = LL_OK; + } + } + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate fraction division for clock synchronization mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pu32DivFraction Pointer to BRR fraction divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + */ +static int32_t ClockSync_CalculateDivFraction(const CM_USART_TypeDef *USARTx, uint32_t u32UsartClk, + uint32_t u32Baudrate, uint32_t *pu32DivInteger, + uint32_t *pu32DivFraction, float32_t *pf32Error) +{ + uint32_t B; + uint32_t C; + float32_t f32Err; + uint64_t u64Temp; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_Fraction; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check parameter */ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((NULL != pu32DivInteger) && (NULL != pu32DivFraction) && (C > 0UL) && (B > 0UL)) { + /* Clock sync mode baudrate integer calculation formula: */ + /* B = C / (4 * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 4)) - 1 */ + DIV_Integer = (C / (B * 4UL)) - 1UL; + + if ((DIV_Integer > 0UL) && (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX)) { + /* Clock sync mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = 256 * (4 * (DIV_Integer + 1) * B) / C - 128 */ + + /* u64Temp = (4 * (DIV_Integer + 1) * B) */ + u64Temp = (uint64_t)((uint64_t)4U * ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B); + + DIV_Fraction = (uint32_t)(256UL * u64Temp / C - 128UL); + + if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) { + *pu32DivInteger = DIV_Integer; + *pu32DivFraction = DIV_Fraction; + + if (NULL != pf32Error) { + /* E(%) = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * B * 256) - 1 */ + u64Temp *= (uint64_t)256UL; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32Err = (float32_t)((float64_t)(u64Dividend) / (float64_t)(u64Temp)) - 1.0F; + + *pf32Error = f32Err; + } + + i32Ret = LL_OK; + } + } + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate fraction division for clock synchronization mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pu32DivFraction Pointer to BRR fraction divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + */ +static int32_t SmartCard_CalculateDivFraction(const CM_USART_TypeDef *USARTx, uint32_t u32UsartClk, + uint32_t u32Baudrate, uint32_t *pu32DivInteger, + uint32_t *pu32DivFraction, float32_t *pf32Error) +{ + uint32_t B; + uint32_t C; + uint32_t BCN; + float32_t f32Err; + uint64_t u64Temp; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_Fraction; + const uint16_t au16EtuClkCnts[] = {32U, 64U, 93U, 128U, 186U, 256U, 372U, 512U}; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((NULL != pu32DivInteger) && (NULL != pu32DivFraction) && (C > 0UL) && (B > 0UL)) { + BCN = READ_REG32_BIT(USARTx->CR3, USART_CR3_BCN); + DDL_ASSERT(IS_USART_SMARTCARD_ETU_CLK(BCN)); + BCN = au16EtuClkCnts[BCN >> USART_CR3_BCN_POS]; + + /* Smartcard mode baudrate integer calculation formula: */ + /* B = C / (2 * BCN * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 2 * BCN)) - 1 */ + DIV_Integer = (C / (B * BCN * 2UL)) - 1UL; + + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + /* Smartcard mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / ((2 * BCN) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (256 * (2 * BCN * (DIV_Integer + 1) * B) / C) - 128 */ + + /* u64Temp = (2 * BCN * (DIV_Integer + 1) * B) */ + u64Temp = (uint64_t)((uint64_t)2UL * BCN * ((uint64_t)DIV_Integer + (uint64_t)1UL) * B); + + DIV_Fraction = (uint32_t)(256UL * u64Temp / C - 128UL); + if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) { + *pu32DivInteger = DIV_Integer; + *pu32DivFraction = DIV_Fraction; + + if (NULL != pf32Error) { + /* E(%) = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * B * 256) - 1 */ + u64Temp *= (uint64_t)256UL; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32Err = (float32_t)((float64_t)u64Dividend / (float64_t)(u64Temp)) - 1.0F; + + *pf32Error = f32Err; + } + i32Ret = LL_OK; + } + } + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate fraction division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pu32DivFraction Pointer to BRR fraction divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR: Set unsuccessfully. + * - LL_ERR_INVD_PARAM: The parameters invalid. + */ +static int32_t UART_CalculateDiv(const CM_USART_TypeDef *USARTx, uint32_t u32UsartClk, + uint32_t u32Baudrate, uint32_t *pu32DivInteger, + uint32_t *pu32DivFraction, float32_t *pf32Error) +{ + int32_t i32Ret = LL_ERR; + + if (!IS_USART_INTEGER_UNIT(USARTx)) { + i32Ret = UART_CalculateDivFraction(USARTx, u32UsartClk, u32Baudrate, pu32DivInteger, pu32DivFraction, pf32Error); + } + + if (LL_OK != i32Ret) { + i32Ret = UART_CalculateDivInteger(USARTx, u32UsartClk, u32Baudrate, pu32DivInteger, pf32Error); + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate fraction division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pu32DivFraction Pointer to BRR fraction divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR: Set unsuccessfully. + * - LL_ERR_INVD_PARAM: The parameters invalid. + */ +static int32_t ClockSync_CalculateDiv(const CM_USART_TypeDef *USARTx, uint32_t u32UsartClk, + uint32_t u32Baudrate, uint32_t *pu32DivInteger, + uint32_t *pu32DivFraction, float32_t *pf32Error) +{ + int32_t i32Ret = LL_ERR; + + if (!IS_USART_INTEGER_UNIT(USARTx)) { + i32Ret = ClockSync_CalculateDivFraction(USARTx, u32UsartClk, u32Baudrate, pu32DivInteger, pu32DivFraction, pf32Error); + } + + if (LL_OK != i32Ret) { + i32Ret = ClockSync_CalculateDivInteger(USARTx, u32UsartClk, u32Baudrate, pu32DivInteger, pf32Error); + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate fraction division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32DivInteger Pointer to BRR integer divsion value + * @param [out] pu32DivFraction Pointer to BRR fraction divsion value + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR: Set unsuccessfully. + * - LL_ERR_INVD_PARAM: The parameters invalid. + */ +static int32_t SmartCard_CalculateDiv(const CM_USART_TypeDef *USARTx, uint32_t u32UsartClk, + uint32_t u32Baudrate, uint32_t *pu32DivInteger, + uint32_t *pu32DivFraction, float32_t *pf32Error) +{ + int32_t i32Ret = LL_ERR; + + if (!IS_USART_INTEGER_UNIT(USARTx)) { + i32Ret = SmartCard_CalculateDivFraction(USARTx, u32UsartClk, u32Baudrate, pu32DivInteger, pu32DivFraction, pf32Error); + } + + if (LL_OK != i32Ret) { + i32Ret = SmartCard_CalculateDivInteger(USARTx, u32UsartClk, u32Baudrate, pu32DivInteger, pf32Error); + } + return i32Ret; +} + +/** + * @brief Get USART clock frequency value. + * @retval USART clock frequency value + */ +static uint32_t USART_GetBusClockFreq(void) +{ + uint32_t u32BusClock; + + u32BusClock = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS); + + return u32BusClock; +} + +/** + * @brief Get USART clock frequency value. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval USART clock frequency value + */ +static uint32_t USART_GetUsartClockFreq(const CM_USART_TypeDef *USARTx) +{ + uint32_t u32BusClock; + uint32_t u32UsartDiv; + uint32_t u32UsartClock; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + u32BusClock = USART_GetBusClockFreq(); + u32UsartDiv = (1UL << (READ_REG32_BIT((USARTx)->PR, USART_PR_PSC) * 2UL)); + + u32UsartClock = u32BusClock / u32UsartDiv; + return u32UsartClock; +} + +/** + * @} + */ + +/** + * @defgroup USART_Global_Functions USART Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_usart_clocksync_init_t to default values. + * @param [out] pstcClockSyncInit Pointer to a @ref stc_usart_clocksync_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcClockSyncInit value is NULL. + */ +int32_t USART_ClockSync_StructInit(stc_usart_clocksync_init_t *pstcClockSyncInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcClockSyncInit) { + pstcClockSyncInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK; + pstcClockSyncInit->u32ClockDiv = USART_CLK_DIV1; + pstcClockSyncInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcClockSyncInit->u32FirstBit = USART_FIRST_BIT_LSB; + pstcClockSyncInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize clock synchronization function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcClockSyncInit Pointer to a @ref stc_usart_clocksync_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcClockSyncInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_ClockSync_Init(CM_USART_TypeDef *USARTx, + const stc_usart_clocksync_init_t *pstcClockSyncInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcClockSyncInit) { + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(pstcClockSyncInit->u32ClockSrc)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcClockSyncInit->u32FirstBit)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcClockSyncInit->u32HWFlowControl)); + + u32CR1Value = (pstcClockSyncInit->u32FirstBit | USART_CR1_MS | USART_CR1_SBS); + u32CR2Value = (pstcClockSyncInit->u32ClockSrc | USART_CR2_RST_VALUE); + if (USART_CLK_SRC_INTERNCLK == pstcClockSyncInit->u32ClockSrc) { + u32CR2Value |= USART_CK_OUTPUT_ENABLE; + } + u32CR3Value = (pstcClockSyncInit->u32HWFlowControl == USART_HW_FLOWCTRL_CTS) ? USART_HW_FLOWCTRL_CTS : 0UL; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + if (USART_CLK_SRC_INTERNCLK == pstcClockSyncInit->u32ClockSrc) { + DDL_ASSERT(IS_USART_CLK_DIV(pstcClockSyncInit->u32ClockDiv)); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcClockSyncInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcClockSyncInit->u32Baudrate, pf32Error); + } else { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_usart_multiprocessor_init_t to default values. + * @param [out] pstcMultiProcessorInit Pointer to a @ref stc_usart_multiprocessor_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcMultiProcessorInit value is NULL. + */ +int32_t USART_MultiProcessor_StructInit(stc_usart_multiprocessor_init_t *pstcMultiProcessorInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcMultiProcessorInit) { + pstcMultiProcessorInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK; + pstcMultiProcessorInit->u32ClockDiv = USART_CLK_DIV1; + pstcMultiProcessorInit->u32CKOutput = USART_CK_OUTPUT_DISABLE; + pstcMultiProcessorInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcMultiProcessorInit->u32DataWidth = USART_DATA_WIDTH_8BIT; + pstcMultiProcessorInit->u32StopBit = USART_STOPBIT_1BIT; + pstcMultiProcessorInit->u32OverSampleBit = USART_OVER_SAMPLE_16BIT; + pstcMultiProcessorInit->u32FirstBit = USART_FIRST_BIT_LSB; + pstcMultiProcessorInit->u32StartBitPolarity = USART_START_BIT_FALLING; + pstcMultiProcessorInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize UART multiple processor function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcMultiProcessorInit Pointer to a @ref stc_usart_multiprocessor_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcMxProcessorInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_MultiProcessor_Init(CM_USART_TypeDef *USARTx, + const stc_usart_multiprocessor_init_t *pstcMultiProcessorInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcMultiProcessorInit) { + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(pstcMultiProcessorInit->u32ClockSrc)); + DDL_ASSERT(IS_USART_CK_OUTPUT(pstcMultiProcessorInit->u32CKOutput)); + DDL_ASSERT(IS_USART_DATA_WIDTH(pstcMultiProcessorInit->u32DataWidth)); + DDL_ASSERT(IS_USART_STOPBIT(pstcMultiProcessorInit->u32StopBit)); + DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(pstcMultiProcessorInit->u32OverSampleBit)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcMultiProcessorInit->u32FirstBit)); + DDL_ASSERT(IS_USART_START_BIT_POLARITY(pstcMultiProcessorInit->u32StartBitPolarity)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcMultiProcessorInit->u32HWFlowControl)); + + u32CR1Value = (pstcMultiProcessorInit->u32DataWidth | pstcMultiProcessorInit->u32OverSampleBit | \ + pstcMultiProcessorInit->u32FirstBit | pstcMultiProcessorInit->u32StartBitPolarity); + u32CR2Value = (USART_CR2_RST_VALUE | pstcMultiProcessorInit->u32ClockSrc | \ + pstcMultiProcessorInit->u32CKOutput | pstcMultiProcessorInit->u32StopBit); + u32CR3Value = (pstcMultiProcessorInit->u32HWFlowControl == USART_HW_FLOWCTRL_CTS) ? USART_HW_FLOWCTRL_CTS : 0UL; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + if (USART_CLK_SRC_INTERNCLK == pstcMultiProcessorInit->u32ClockSrc) { + DDL_ASSERT(IS_USART_CLK_DIV(pstcMultiProcessorInit->u32ClockDiv)); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcMultiProcessorInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcMultiProcessorInit->u32Baudrate, pf32Error); + } else { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_usart_uart_init_t to default values. + * @param [out] pstcUartInit Pointer to a @ref stc_usart_uart_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcUartInit value is NULL. + */ +int32_t USART_UART_StructInit(stc_usart_uart_init_t *pstcUartInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcUartInit) { + pstcUartInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK; + pstcUartInit->u32ClockDiv = USART_CLK_DIV1; + pstcUartInit->u32CKOutput = USART_CK_OUTPUT_DISABLE; + pstcUartInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcUartInit->u32DataWidth = USART_DATA_WIDTH_8BIT; + pstcUartInit->u32StopBit = USART_STOPBIT_1BIT; + pstcUartInit->u32Parity = USART_PARITY_NONE; + pstcUartInit->u32OverSampleBit = USART_OVER_SAMPLE_16BIT; + pstcUartInit->u32FirstBit = USART_FIRST_BIT_LSB; + pstcUartInit->u32StartBitPolarity = USART_START_BIT_FALLING; + pstcUartInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize UART function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcUartInit Pointer to a @ref stc_usart_uart_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcUartInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_UART_Init(CM_USART_TypeDef *USARTx, const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcUartInit) { + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(pstcUartInit->u32ClockSrc)); + DDL_ASSERT(IS_USART_CK_OUTPUT(pstcUartInit->u32CKOutput)); + DDL_ASSERT(IS_USART_PARITY(pstcUartInit->u32Parity)); + DDL_ASSERT(IS_USART_DATA_WIDTH(pstcUartInit->u32DataWidth)); + DDL_ASSERT(IS_USART_STOPBIT(pstcUartInit->u32StopBit)); + DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(pstcUartInit->u32OverSampleBit)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcUartInit->u32FirstBit)); + DDL_ASSERT(IS_USART_START_BIT_POLARITY(pstcUartInit->u32StartBitPolarity)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcUartInit->u32HWFlowControl)); + + u32CR1Value = (pstcUartInit->u32Parity | pstcUartInit->u32DataWidth | pstcUartInit->u32FirstBit | \ + pstcUartInit->u32OverSampleBit | pstcUartInit->u32StartBitPolarity); + u32CR2Value = (USART_CR2_RST_VALUE | pstcUartInit->u32ClockSrc | \ + pstcUartInit->u32CKOutput | pstcUartInit->u32StopBit); + u32CR3Value = (pstcUartInit->u32HWFlowControl == USART_HW_FLOWCTRL_CTS) ? USART_HW_FLOWCTRL_CTS : 0UL; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + if (USART_CLK_SRC_INTERNCLK == pstcUartInit->u32ClockSrc) { + DDL_ASSERT(IS_USART_CLK_DIV(pstcUartInit->u32ClockDiv)); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcUartInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcUartInit->u32Baudrate, pf32Error); + } else { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_usart_smartcard_init_t to default values. + * @param [out] pstcSmartCardInit Pointer to a @ref stc_usart_smartcard_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcSmartCardInit value is NULL. + */ +int32_t USART_SmartCard_StructInit(stc_usart_smartcard_init_t *pstcSmartCardInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSmartCardInit) { + pstcSmartCardInit->u32ClockDiv = USART_CLK_DIV1; + pstcSmartCardInit->u32CKOutput = USART_CK_OUTPUT_DISABLE; + pstcSmartCardInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcSmartCardInit->u32StopBit = USART_STOPBIT_1BIT; + pstcSmartCardInit->u32FirstBit = USART_FIRST_BIT_LSB; + i32Ret = LL_OK; + } + + return i32Ret; +} +/** + * @brief Initialize smartcard function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcSmartCardInit Pointer to a @ref stc_usart_smartcard_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcSmartCardInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_SmartCard_Init(CM_USART_TypeDef *USARTx, + const stc_usart_smartcard_init_t *pstcSmartCardInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSmartCardInit) { + DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CK_OUTPUT(pstcSmartCardInit->u32CKOutput)); + DDL_ASSERT(IS_USART_CLK_DIV(pstcSmartCardInit->u32ClockDiv)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcSmartCardInit->u32FirstBit)); + DDL_ASSERT(IS_USART_STOPBIT(pstcSmartCardInit->u32StopBit)); + + u32CR1Value = (pstcSmartCardInit->u32FirstBit | USART_CR1_PCE | USART_CR1_SBS); + u32CR2Value = (pstcSmartCardInit->u32CKOutput | pstcSmartCardInit->u32StopBit | USART_CR2_RST_VALUE); + u32CR3Value = USART_CR3_SCEN | USART_SC_ETU_CLK372; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcSmartCardInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcSmartCardInit->u32Baudrate, pf32Error); + } + + return i32Ret; +} + +/** + * @brief De-Initialize USART function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval None + */ +void USART_DeInit(CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + /* Configures the registers to reset value. */ + WRITE_REG32(USARTx->CR1, USART_CR1_RST_VALUE); + WRITE_REG32(USARTx->CR2, USART_CR2_RST_VALUE); + WRITE_REG32(USARTx->CR3, 0UL); + WRITE_REG32(USARTx->PR, 0UL); +} + +/** + * @brief Enable/disable USART Transmit/Receive Function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Func USART function type + * This parameter can be any composed value of the macros group @ref USART_Function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void USART_FuncCmd(CM_USART_TypeDef *USARTx, uint32_t u32Func, en_functional_state_t enNewState) +{ + uint32_t u32BaseFunc; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_USART_FUNC(u32Func)); + + u32BaseFunc = (u32Func & 0xFFFFUL); + if (u32BaseFunc > 0UL) { + (ENABLE == enNewState) ? SET_REG32_BIT(USARTx->CR1, u32BaseFunc) : CLR_REG32_BIT(USARTx->CR1, u32BaseFunc); + } + +} + +/** + * @brief Get USART flag. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Flag USART flag type + * This parameter can be any composed value of the macros group @ref USART_Flag. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t USART_GetStatus(const CM_USART_TypeDef *USARTx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FLAG(u32Flag)); + + return (0UL == (READ_REG32_BIT(USARTx->SR, u32Flag)) ? RESET : SET); +} + +/** + * @brief Get USART flag. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Flag USART flag type + * This parameter can be any composed value of the following values: + * @arg USART_FLAG_OVERRUN: Overrun error flag + * @arg USART_FLAG_FRAME_ERR: Framing error flag + * @arg USART_FLAG_PARITY_ERR:Parity error flag + * @arg USART_FLAG_RX_TIMEOUT: Receive timeout flag + * @arg USART_FLAG_LIN_ERR: LIN bus error flag + * @arg USART_FLAG_LIN_WKUP: LIN wakeup signal detection flag + * @arg USART_FLAG_LIN_BREAK: LIN break signal detection flag + * @retval None + * @note Check whether the paramter u32Flag value is valid by @ref USART_Flag. + */ +void USART_ClearStatus(CM_USART_TypeDef *USARTx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FLAG(u32Flag)); + + if ((u32Flag & USART_FLAG_ERR_MASK) > 0UL) { + SET_REG32_BIT(USARTx->CR1, (u32Flag & USART_FLAG_ERR_MASK) << USART_CR1_CPE_POS); + } + + /* Timeout flag */ + if ((u32Flag & USART_FLAG_RX_TIMEOUT) > 0UL) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_CRTOF); + } + +} + +/** + * @brief Set USART parity. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Parity USART parity + * This parameter can be one of the macros group @ref USART_Parity_Control + * @arg USART_PARITY_NONE: Parity control disabled + * @arg USART_PARITY_ODD: Parity control enabled and Odd Parity is selected + * @arg USART_PARITY_EVEN: Parity control enabled and Even Parity is selected + * @retval None + */ +void USART_SetParity(CM_USART_TypeDef *USARTx, uint32_t u32Parity) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_PARITY(u32Parity)); + + MODIFY_REG32(USARTx->CR1, (USART_CR1_PS | USART_CR1_PCE), u32Parity); +} + +/** + * @brief Set USART bit direction. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32FirstBit USART bit direction + * This parameter can be one of the macros group @ref USART_First_Bit + * @arg USART_FIRST_BIT_MSB: MSB(Most Significant Bit) + * @arg USART_FIRST_BIT_LSB: LSB(Least Significant Bit) + * @retval None + */ +void USART_SetFirstBit(CM_USART_TypeDef *USARTx, uint32_t u32FirstBit) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FIRST_BIT(u32FirstBit)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_ML, u32FirstBit); +} + +/** + * @brief Set USART stop bit. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32StopBit USART stop bits + * This parameter can be one of the macros group @ref USART_Stop_Bit + * @arg USART_STOPBIT_1BIT: 1 stop bit + * @arg USART_STOPBIT_2BIT: 2 stop bit + * @retval None + */ +void USART_SetStopBit(CM_USART_TypeDef *USARTx, uint32_t u32StopBit) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_STOPBIT(u32StopBit)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_STOP, u32StopBit); +} + +/** + * @brief Set USART data width. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32DataWidth USART data width + * This parameter can be one of the macros group @ref USART_Data_Width_Bit + * @arg USART_DATA_WIDTH_8BIT: 8 bits word width + * @arg USART_DATA_WIDTH_9BIT: 9 bits word width + * @retval None + */ +void USART_SetDataWidth(CM_USART_TypeDef *USARTx, uint32_t u32DataWidth) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_DATA_WIDTH(u32DataWidth)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_M, u32DataWidth); +} + +/** + * @brief Set USART oversampling bits. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32OverSampleBit USART over sample bit + * This parameter can be one of the macros group @ref USART_Over_Sample_Bit + * @arg USART_OVER_SAMPLE_8BIT: Oversampling by 8 bit + * @arg USART_OVER_SAMPLE_16BIT: Oversampling by 16 bit + * @retval None + */ +void USART_SetOverSampleBit(CM_USART_TypeDef *USARTx, uint32_t u32OverSampleBit) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(u32OverSampleBit)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_OVER8, u32OverSampleBit); +} + +/** + * @brief Set USART start bit detect polarity. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Polarity USART start bit detect polarity + * This parameter can be one of the macros group @ref USART_Start_Bit_Polarity + * @arg USART_START_BIT_LOW: Detect RX pin low level + * @arg USART_START_BIT_FALLING: Detect RX pin falling edge + * @retval None + */ +void USART_SetStartBitPolarity(CM_USART_TypeDef *USARTx, uint32_t u32Polarity) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_START_BIT_POLARITY(u32Polarity)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_SBS, u32Polarity); +} + +/** + * @brief Set USART transmission type. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Type USART transmission content type + * This parameter can be one of the macros group @ref USART_Transmission_Type + * @arg USART_TRANS_ID: USART transmission content type is processor ID + * @arg USART_TRANS_DATA: USART transmission content type is frame data + * @retval None + */ +void USART_SetTransType(CM_USART_TypeDef *USARTx, uint32_t u32Type) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_TRANS_TYPE(u32Type)); + + MODIFY_REG32(USARTx->DR, USART_DR_MPID, u32Type); +} + +/** + * @brief Set USART clock prescaler division. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32ClockDiv USART clock prescaler division. + * This parameter can be one of the macros group @ref USART_Clock_Division + * @arg USART_CLK_DIV1: CLK + * @arg USART_CLK_DIV4: CLK/4 + * @arg USART_CLK_DIV16: CLK/16 + * @arg USART_CLK_DIV64: CLK/64 + * @retval None + * @note The clock division function is valid only when clock source is internal clock. + */ +void USART_SetClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_DIV(u32ClockDiv)); + + MODIFY_REG32(USARTx->PR, USART_PR_PSC, u32ClockDiv); +} + +/** + * @brief Get USART clock prescaler division. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval Returned value can be one of the following values: + * - USART_CLK_DIV1: CLK + * - USART_CLK_DIV4: CLK/4 + * - USART_CLK_DIV16: CLK/16 + * - USART_CLK_DIV64: CLK/64 + * @note The clock division function is valid only when clock source is internal clock. + */ +uint32_t USART_GetClockDiv(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + return READ_REG32_BIT(USARTx->PR, USART_PR_PSC); +} + +/** + * @brief Set USART clock source. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32ClockSrc USART clock source + * This parameter can be one of the macros group @ref USART_Clock_Source + * @arg USART_CLK_SRC_EXTCLK: Clock source is external clock(USART_CK). + * @arg USART_CLK_SRC_INTERNCLK: Clock source is internal clock. + * @retval None + */ +void USART_SetClockSrc(CM_USART_TypeDef *USARTx, uint32_t u32ClockSrc) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(u32ClockSrc)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_CLKC_1, u32ClockSrc); +} + +/** + * @brief Get USART clock source. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval Returned value can be one of the following values: + * - USART_CLK_SRC_EXTCLK: Clock source is external clock(USART_CK). + * - USART_CLK_SRC_INTERNCLK: Clock source is internal clock. + */ +uint32_t USART_GetClockSrc(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + return READ_REG32_BIT(USARTx->CR2, USART_CR2_CLKC_1); +} + +/** + * @brief Enable or disable USART noise filter. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void USART_FilterCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_NFE); + } else { + CLR_REG32_BIT(USARTx->CR1, USART_CR1_NFE); + } +} + +/** + * @brief Enable or disable USART silence. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void USART_SilenceCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_SLME); + } else { + CLR_REG32_BIT(USARTx->CR1, USART_CR1_SLME); + } +} + +/** + * @brief Set UART hardware flow control CTS/RTS selection. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32HWFlowControl USART hardware flow control CTS/RTS selection + * This parameter can be one of the macros group @ref USART_Hardware_Flow_Control. + * @retval None + */ +void USART_SetHWFlowControl(CM_USART_TypeDef *USARTx, uint32_t u32HWFlowControl) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(u32HWFlowControl)); + + if (USART_HW_FLOWCTRL_CTS == u32HWFlowControl) { + SET_REG32_BIT(USARTx->CR3, USART_CR3_CTSE); + } else { + CLR_REG32_BIT(USARTx->CR3, USART_CR3_CTSE); + } +} + +/** + * @brief USART receive data. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval Receive data + */ +uint16_t USART_ReadData(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + return READ_REG16(*USART_RXD(USARTx)); +} + +/** + * @brief USART send data. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u16Data Transmit data + * @retval None + */ +void USART_WriteData(CM_USART_TypeDef *USARTx, uint16_t u16Data) +{ + __IO uint16_t *TXD = USART_TXD(USARTx); + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_DATA(u16Data)); + + WRITE_REG16(*TXD, u16Data); +} + +/** + * @brief USART send processor ID. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + ** @param [in] u16ID Processor ID + * @retval None + */ +void USART_WriteID(CM_USART_TypeDef *USARTx, uint16_t u16ID) +{ + __IO uint16_t *TXD = USART_TXD(USARTx); + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_DATA(u16ID)); + + WRITE_REG16(*TXD, (USART_DR_MPID | u16ID)); +} + +/** + * @brief Set USART baudrate. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Baudrate UART baudrate + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + * @note The function uses fraction division to ensure baudrate accuracy if USART unit supports baudrate fraction division. + */ +int32_t USART_SetBaudrate(CM_USART_TypeDef *USARTx, uint32_t u32Baudrate, float32_t *pf32Error) +{ + uint32_t u32Mode; + uint32_t u32UsartClock; + uint32_t u32Integer = 0UL; + uint32_t u32Fraction = 0xFFFFUL; + int32_t i32Ret; + + DDL_ASSERT(u32Baudrate > 0UL); + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + /* Get USART clock frequency */ + u32UsartClock = USART_GetUsartClockFreq(USARTx); + + /* Calculate baudrate for BRR */ + u32Mode = READ_REG32_BIT(USARTx->CR1, USART_CR1_MS); + if (0UL == u32Mode) { + u32Mode = READ_REG32_BIT(USARTx->CR3, USART_CR_SCEN); + if (0UL == u32Mode) { + i32Ret = UART_CalculateDiv(USARTx, u32UsartClock, u32Baudrate, &u32Integer, &u32Fraction, pf32Error); + } else { + /* Smartcard function */ + i32Ret = SmartCard_CalculateDiv(USARTx, u32UsartClock, u32Baudrate, &u32Integer, &u32Fraction, pf32Error); + } + } else { + i32Ret = ClockSync_CalculateDiv(USARTx, u32UsartClock, u32Baudrate, &u32Integer, &u32Fraction, pf32Error); + } + + if (LL_OK == i32Ret) { + MODIFY_REG32(USARTx->BRR, USART_BRR_DIV_INTEGER, (u32Integer << USART_BRR_DIV_INTEGER_POS)); + + if (u32Fraction <= USART_BRR_DIV_FRACTION_MASK) { + SET_REG32_BIT(USARTx->CR1, USART_CR_FBME); + MODIFY_REG32(USARTx->BRR, USART_BRR_DIV_FRACTION_MASK, u32Fraction); + } + } + + return i32Ret; +} + +/** + * @brief Set USART Smartcard ETU Clock. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32EtuClock USART Smartcard ETU Clock. + * This parameter can be one of the macros group @ref USART_Smartcard_ETU_Clock + * @arg USART_SC_ETU_CLK32: 1 etu = 32/f + * @arg USART_SC_ETU_CLK64: 1 etu = 64/f + * @arg USART_SC_ETU_CLK128: 1 etu = 128/f + * @arg USART_SC_ETU_CLK256: 1 etu = 256/f + * @arg USART_SC_ETU_CLK372: 1 etu = 372/f + * @retval None + */ +void USART_SmartCard_SetEtuClock(CM_USART_TypeDef *USARTx, uint32_t u32EtuClock) +{ + DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx)); + DDL_ASSERT(IS_USART_SMARTCARD_ETU_CLK(u32EtuClock)); + + MODIFY_REG32(USARTx->CR3, USART_CR3_BCN, u32EtuClock); +} + +/** + * @brief UART transmit data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [out] pvBuf The pointer to data transmitted buffer + * @param [in] u32Len Amount of frame to be sent. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or pvBuf is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT + */ +int32_t USART_UART_Trans(CM_USART_TypeDef *USARTx, const void *pvBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + uint32_t u32DataWidth; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != pvBuf) && (u32Len > 0UL)) { + u32DataWidth = READ_REG32_BIT(USARTx->CR1, USART_CR1_M); + + if ((USART_DATA_WIDTH_8BIT == u32DataWidth) || (USART_DATA_WIDTH_9BIT == u32DataWidth)) { + for (i = 0UL; i < u32Len; i++) { + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + if (LL_OK != i32Ret) { + break; + } + + if (u32DataWidth == USART_DATA_WIDTH_8BIT) { + USART_WriteData(USARTx, ((const uint8_t *)pvBuf)[i]); + } else { + USART_WriteData(USARTx, ((const uint16_t *)pvBuf)[i]); + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + } + + return i32Ret; +} + +/** + * @brief UART receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [out] pvBuf The pointer to data received buffer + * @param [in] u32Len Amount of frame to be received. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer pvBuf value is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT + */ +int32_t USART_UART_Receive(const CM_USART_TypeDef *USARTx, void *pvBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t u32Count; + uint32_t u32DataWidth; + uint16_t u16ReceiveData; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != pvBuf) && (u32Len > 0UL)) { + u32DataWidth = READ_REG32_BIT(USARTx->CR1, USART_CR1_M); + + for (u32Count = 0UL; u32Count < u32Len; u32Count++) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + u16ReceiveData = USART_ReadData(USARTx); + if (USART_DATA_WIDTH_8BIT == u32DataWidth) { + ((uint8_t *)pvBuf)[u32Count] = (uint8_t)(u16ReceiveData & 0xFFU); + } else { + ((uint16_t *)pvBuf)[u32Count] = (uint16_t)(u16ReceiveData & 0x1FFU); + } + } else { + break; + } + } + } + + return i32Ret; +} + +/** + * @brief Clock sync transmit && receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] au8Buf The pointer to data transmitted buffer + * @param [in] u32Len Amount of data to be transmitted. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer au8Buf value is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT + */ +int32_t USART_ClockSync_Trans(CM_USART_TypeDef *USARTx, const uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != au8Buf) && (u32Len > 0UL)) { + for (i = 0UL; i < u32Len; i++) { + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + if (LL_OK == i32Ret) { + USART_WriteData(USARTx, au8Buf[i]); + if (READ_REG32_BIT(USARTx->CR1, USART_RX) != 0UL) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + (void)USART_ReadData(USARTx); + } + } + } + + if (LL_OK != i32Ret) { + break; + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + + return i32Ret; +} + +/** + * @brief Clock sync receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [out] au8Buf The pointer to data received buffer + * @param [in] u32Len Amount of data to be sent and received. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer au8Buf value is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT. + */ +int32_t USART_ClockSync_Receive(CM_USART_TypeDef *USARTx, uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + en_functional_state_t enTX; + en_functional_state_t enMasterMode; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != au8Buf) && (u32Len > 0UL)) { + i32Ret = LL_OK; + enTX = (READ_REG32_BIT(USARTx->CR1, USART_TX) == 0UL) ? DISABLE : ENABLE; + enMasterMode = (USART_CLK_SRC_EXTCLK == READ_REG32_BIT(USARTx->CR2, USART_CR2_CLKC)) ? DISABLE : ENABLE; + + for (i = 0UL; i < u32Len; i++) { + if ((ENABLE == enMasterMode) || (ENABLE == enTX)) { + USART_WriteData(USARTx, 0xFFU); + + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + au8Buf[i] = (uint8_t)USART_ReadData(USARTx); + } + } + + if (LL_OK != i32Ret) { + break; + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + + return i32Ret; +} + +/** + * @brief Clock sync transmit && receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] au8TxBuf The pointer to data transmitted buffer + * @param [out] au8RxBuf The pointer to data received buffer + * @param [in] u32Len Amount of data to be sent and received. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT. + */ +int32_t USART_ClockSync_TransReceive(CM_USART_TypeDef *USARTx, const uint8_t au8TxBuf[], uint8_t au8RxBuf[], + uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + uint8_t u8ReceiveData; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if (u32Len > 0UL) { + for (i = 0UL; i < u32Len; i++) { + if (NULL != au8TxBuf) { + USART_WriteData(USARTx, au8TxBuf[i]); + } else { + USART_WriteData(USARTx, 0xFFU); + } + + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + u8ReceiveData = (uint8_t)USART_ReadData(USARTx); + if (NULL != au8RxBuf) { + au8RxBuf[i] = u8ReceiveData; + } + } + } + + if (LL_OK != i32Ret) { + break; + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_USART_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_usb.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_usb.c new file mode 100644 index 0000000000..58df342929 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_usb.c @@ -0,0 +1,1311 @@ +/** + ******************************************************************************* + * @file hc32_ll_usb.c + * @brief USB core driver + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_usb.h" +#include "usb_bsp.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_USB USB + * @brief USB Driver Library + * @{ + */ + +#if (LL_USB_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_hoststop(LL_USB_TypeDef *USBx, uint8_t u8ChNum); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup USB_Global_Functions USB Global Functions + * @{ + */ + +/** + * @brief core software reset + * @param [in] USBx usb instance + * @retval None + */ +void usb_coresoftrst(LL_USB_TypeDef *USBx) +{ + __IO uint8_t u8Status = USB_OK;; + __IO uint32_t u32grstctl = 0UL; + __IO uint32_t u32Count = 0UL; + + /* Wait for AHB master to be idle. */ + do { + usb_udelay(1UL); + u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL); + if (++u32Count > 100000UL) { + u8Status = USB_ERROR; + } + } while (0UL == (u32grstctl & USBFS_GRSTCTL_AHBIDL)); + + if (USB_OK == u8Status) { + /* Write the Core Soft Reset bit to reset the USB core */ + u32Count = 0UL; + u32grstctl |= USBFS_GRSTCTL_CSRST; + WRITE_REG32(USBx->GREGS->GRSTCTL, u32grstctl); + + /* Wait for the reset finishing */ + do { + u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL); + if (u32Count > 100000UL) { + break; + } + u32Count++; + usb_udelay(1UL); + } while (0UL != (u32grstctl & USBFS_GRSTCTL_CSRST)); + /* Wait for at least 3 PHY clocks after the core resets */ + usb_udelay(3UL); + } +} + +/** + * @brief Writes a packet whose byte number is len into the Tx FIFO associated + * with the EP + * @param [in] USBx usb instance + * @param [in] src source pointer used to hold the transmited data + * @param [in] ch_ep_num end point index + * @param [in] len length in bytes + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_wrpkt(LL_USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t u8DmaEn) +{ + __IO uint32_t u32pAddr; + __IO uint32_t *fifo; + uint32_t u32Count32b; + uint32_t u32Tmp; + if (u8DmaEn == 0U) { + u32Count32b = (len + 3UL); + u32Count32b = u32Count32b >> 2U; + fifo = USBx->DFIFO[ch_ep_num]; + u32Tmp = 0UL; + while (u32Tmp < u32Count32b) { + WRITE_REG32(*fifo, *((uint32_t *)src)); + u32pAddr = (uint32_t)src; + src = (uint8_t *)(u32pAddr + 4U); + u32Tmp++; + } + } +} + +/** + * @brief Reads a packet whose byte number is len from the Rx FIFO + * @param [in] USBx usb instance + * @param [in] dest destination pointer that point to the received data + * @param [in] len number of bytes + * @retval None + */ +void usb_rdpkt(LL_USB_TypeDef *USBx, uint8_t *dest, uint16_t len) +{ + uint32_t u32Tmp; + __IO uint32_t u32Count32b; + __IO uint32_t u32pAddr; + + __IO uint32_t *fifo = USBx->DFIFO[0]; + u32Count32b = (len + 3UL); + u32Count32b = u32Count32b >> 2U; + u32pAddr = 0UL; + u32Tmp = 0UL; + while (u32Tmp < u32Count32b) { + *(uint32_t *)dest = READ_REG32(*fifo); + u32pAddr = (uint32_t)dest; + dest = (uint8_t *)(u32pAddr + 4U); + u32Tmp++; + } +} + +/** + * @brief Initialize the addresses of the core registers. + * @param [in] USBx usb instance + * @param [in] basic_cfgs usb core basic cfgs + * @retval None + */ +void usb_setregaddr(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs) +{ + uint32_t u32Tmp = 0UL; + uint32_t u32baseAddr; + + basic_cfgs->dmaen = 0U; + /* initialize device cfg following its address */ + basic_cfgs->host_chnum = USB_MAX_CH_NUM; + basic_cfgs->dev_epnum = USB_MAX_EP_NUM; + basic_cfgs->core_type = 0U; /* FS */ + basic_cfgs->phy_type = 0U; +#ifdef USB_FS_MODE + u32baseAddr = CM_USBFS_BASE; + basic_cfgs->core_type = 0U; /* FS */ +#endif /* USB_FS_MODE */ + +#ifdef USB_HS_MODE + u32baseAddr = CM_USBHS_BASE; + basic_cfgs->core_type = 1U; /* HS */ +#ifdef USB_HS_EXTERNAL_PHY + basic_cfgs->phy_type = 1U; +#endif +#endif /* USB_HS_MODE */ + + USBx->GREGS = (USB_CORE_GREGS *)(u32baseAddr + 0UL); + USBx->DREGS = (USB_CORE_DREGS *)(u32baseAddr + 0x800UL); + + while (u32Tmp < basic_cfgs->dev_epnum) { + USBx->INEP_REGS[u32Tmp] = (USB_CORE_INEPREGS *)(u32baseAddr + 0x900UL + (u32Tmp * 0x20UL)); + USBx->OUTEP_REGS[u32Tmp] = (USB_CORE_OUTEPREGS *)(u32baseAddr + 0xb00UL + (u32Tmp * 0x20UL)); + u32Tmp++; + } + u32Tmp = 0UL; + while (u32Tmp < basic_cfgs->dev_epnum) { + USBx->DFIFO[u32Tmp] = (uint32_t *)(u32baseAddr + 0x1000UL + (u32Tmp * 0x1000UL)); + u32Tmp++; + } + USBx->GCCTL = (uint32_t *)(u32baseAddr + 0xe00UL); +#ifdef USE_HOST_MODE /* if the application mode is host */ + USBx->HREGS = (USB_CORE_HREGS *)(u32baseAddr + 0x400UL); + USBx->HPRT = (uint32_t *)(u32baseAddr + 0x440UL); + u32Tmp = 0UL; + while (u32Tmp < basic_cfgs->host_chnum) { + USBx->HC_REGS[u32Tmp] = (USB_CORE_HC_REGS *)(u32baseAddr + 0x500UL + (u32Tmp * 0x20UL)); + u32Tmp++; + } +#endif /* USE_HOST_MODE */ +} + +/** + * @brief Initializes the USB controller registers and prepares the core + * device mode or host mode operation. + * @param [in] USBx usb instance + * @param [in] basic_cfgs usb core basic cfgs + * @retval None + */ +void usb_initusbcore(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs) +{ + /* reset the core through core soft reset */ + usb_coresoftrst(USBx); + + /* Select PHY for USB core*/ + usb_PhySelect(USBx, basic_cfgs->phy_type); + /* reset the core through core soft reset */ + usb_coresoftrst(USBx); + usb_mdelay(20UL); + if (basic_cfgs->dmaen == 1U) { + /* burst length/type(HBstLen) 64-words x32-bit, core operates in a DMA mode*/ + usb_BurstLenConfig(USBx, 5U); + usb_DmaCmd(USBx, 1U); + } +} + +/** + * @brief Flush a Tx FIFO whose index is num + * @param [in] USBx usb instance + * @param [in] num txFIFO index + * @retval None + */ +void usb_txfifoflush(LL_USB_TypeDef *USBx, uint32_t num) +{ + __IO uint32_t u32grstctl; + __IO uint32_t u32Tmp = 0UL; + + u32grstctl = USBFS_GRSTCTL_TXFFLSH | ((num & 0x1FUL) << USBFS_GRSTCTL_TXFNUM_POS); + /* set the TxFIFO Flush bit, set TxFIFO Number */ + WRITE_REG32(USBx->GREGS->GRSTCTL, u32grstctl); + + /* wait for the finishing of txFIFO flushing */ + do { + u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL); + if (u32Tmp <= 200000UL) { + u32Tmp++; + } else { + break; + } + usb_udelay(1UL); + } while (0UL != (u32grstctl & USBFS_GRSTCTL_TXFFLSH)); + /* Wait for at least 3 PHY clocks after the txfifo has been flushed */ + usb_udelay(3UL); +} + +/** + * @brief Flush the whole rxFIFO + * @param [in] USBx usb instance + * @retval None + */ +void usb_rxfifoflush(LL_USB_TypeDef *USBx) +{ + __IO uint32_t u32grstctl; + __IO uint32_t u32Tmp = 0UL; + + u32grstctl = USBFS_GRSTCTL_RXFFLSH; /* set the RxFIFO Flush bit */ + WRITE_REG32(USBx->GREGS->GRSTCTL, u32grstctl); + /* wait for the finishing of rxFIFO flushing */ + do { + u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL); + if (u32Tmp <= 200000UL) { + u32Tmp++; + } else { + break; + } + usb_udelay(1UL); + } while (0UL != (u32grstctl & USBFS_GRSTCTL_RXFFLSH)); + /* Wait for at least 3 PHY clocks after the rxfifo has been flushed */ + usb_udelay(3UL); +} + +/** + * @brief set the core to be host mode or device mode through the second + * input parameter. + * @param [in] USBx usb instance + * @param [in] mode mode of HOST_MODE or DEVICE_MODE that the core would be + * @retval None + */ +void usb_modeset(LL_USB_TypeDef *USBx, uint8_t mode) +{ + if (mode == HOST_MODE) { + MODIFY_REG32(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_FHMOD | USBFS_GUSBCFG_FDMOD, USBFS_GUSBCFG_FHMOD); + } else { + MODIFY_REG32(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_FHMOD | USBFS_GUSBCFG_FDMOD, USBFS_GUSBCFG_FDMOD); + } + /* wate for the change to take effect */ + usb_mdelay(50UL); +} + +#ifdef USE_DEVICE_MODE + +/** + * @brief initializes the initial status of all endpoints of the device to be + * disable. + * @param [in] USBx usb instance + * @param [in] u8EpNum EP number + * @retval None + */ +void usb_devepdis(LL_USB_TypeDef *USBx, uint8_t u8EpNum) +{ + uint8_t u8Tmp = 0U; + + while (u8Tmp < u8EpNum) { + if (0UL != READ_REG32_BIT(USBx->INEP_REGS[u8Tmp]->DIEPCTL, USBFS_DIEPCTL_EPENA)) { + WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPCTL, USBFS_DIEPCTL_EPDIS | USBFS_DIEPCTL_SNAK); + } else { + WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPCTL, 0UL); + } + WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPTSIZ, 0UL); + WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPINT, 0xFFUL); + u8Tmp++; + } + + u8Tmp = 0U; + while (u8Tmp < u8EpNum) { + if (0UL != READ_REG32_BIT(USBx->OUTEP_REGS[u8Tmp]->DOEPCTL, USBFS_DOEPCTL_EPENA)) { + WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPCTL, USBFS_DOEPCTL_EPDIS | USBFS_DOEPCTL_SNAK); + } else { + WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPCTL, 0UL); + } + WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPTSIZ, 0UL); + WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPINT, 0xFFUL); + u8Tmp++; + } +} + +#ifdef USB_FS_MODE +static void usb_DevFSFifoConfig(LL_USB_TypeDef *USBx) +{ + uint32_t u32StardAddr; + + WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); + /* set txFIFO and rxFIFO size of EP0 */ + u32StardAddr = RX_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->HNPTXFSIZ, + (RX_FIFO_FS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS) | (TX0_FIFO_FS_SIZE << USBFS_HNPTXFSIZ_NPTXFD_POS)); + /* set txFIFO size of EP1 */ + u32StardAddr += TX0_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[0], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX1_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP2 */ + u32StardAddr += TX1_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[1], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX2_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP3 */ + u32StardAddr += TX2_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[2], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX3_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP4 */ + u32StardAddr += TX3_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[3], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX4_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP5 */ + u32StardAddr += TX4_FIFO_FS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[4], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX5_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); +} +#endif + +#ifdef USB_HS_MODE +static void usb_DevHSFifoConfig(LL_USB_TypeDef *USBx) +{ + uint32_t u32StardAddr; + + WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); + /* set txFIFO and rxFIFO size of EP0 */ + u32StardAddr = RX_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->HNPTXFSIZ, + (RX_FIFO_HS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS) | (TX0_FIFO_HS_SIZE << USBFS_HNPTXFSIZ_NPTXFD_POS)); + /* set txFIFO size of EP1 */ + u32StardAddr += TX0_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[0], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX1_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP2 */ + u32StardAddr += TX1_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[1], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX2_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP3 */ + u32StardAddr += TX2_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[2], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX3_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP4 */ + u32StardAddr += TX3_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[3], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX4_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP5 */ + u32StardAddr += TX4_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[4], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX5_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP6 */ + u32StardAddr += TX5_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[5], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX6_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP7 */ + u32StardAddr += TX6_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[6], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX7_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP8 */ + u32StardAddr += TX7_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[7], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX8_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP9 */ + u32StardAddr += TX8_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[8], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX9_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP10 */ + u32StardAddr += TX9_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[9], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX10_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP11 */ + u32StardAddr += TX10_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[10], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX11_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP12 */ + u32StardAddr += TX11_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[11], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX12_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP13 */ + u32StardAddr += TX12_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[12], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX13_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP14 */ + u32StardAddr += TX13_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[13], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX14_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); + /* set txFIFO size of EP15 */ + u32StardAddr += TX14_FIFO_HS_SIZE; + WRITE_REG32(USBx->GREGS->DIEPTXF[14], + (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX15_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS)); +} +#endif + +/** + * @brief initializes the USB controller, include the size of txFIFO, rxFIFO + * status of endpoints, interrupt register etc. Details are shown as + * follows. + * @param [in] USBx usb instance + * @param [in] basic_cfgs usb core basic cfgs + * @retval None + */ +void usb_devmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs) +{ + usb_FrameIntervalConfig(USBx, USB_FRAME_INTERVAL_80); + usb_DevPhySelect(USBx, basic_cfgs->phy_type); + + if (basic_cfgs->core_type == 0U) { +#ifdef USB_FS_MODE + usb_DevFSFifoConfig(USBx); +#endif + } else { +#ifdef USB_HS_MODE + usb_DevHSFifoConfig(USBx); +#endif + } + + usb_clrandmskepint(USBx); + usb_devepdis(USBx, basic_cfgs->dev_epnum); + usb_coreconn(USBx); + usb_devinten(USBx, basic_cfgs->dmaen); +} + +/** + * @brief Enable the interrupt setting when in device mode. + * @param [in] USBx usb instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_devinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn) +{ + uint32_t u32gintmskTmp = 0UL; + + WRITE_REG32(USBx->GREGS->GINTMSK, 0UL); + WRITE_REG32(USBx->GREGS->GINTSTS, 0xBFFFFFFFUL); + /* Enable the normal interrupt setting */ + usb_normalinten(USBx); + if (u8DmaEn == 0U) { + u32gintmskTmp |= USBFS_GINTMSK_RXFNEM; + } + /* Enable interrupts bits corresponding to the Device mode */ + u32gintmskTmp |= (USBFS_GINTMSK_USBSUSPM | USBFS_GINTMSK_USBRSTM | USBFS_GINTMSK_ENUMDNEM + | USBFS_GINTMSK_IEPIM | USBFS_GINTMSK_OEPIM | USBFS_GINTMSK_SOFM + | USBFS_GINTMSK_IISOIXFRM | USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM); +#ifdef VBUS_SENSING_ENABLED + u32gintmskTmp |= USBFS_GINTMSK_VBUSVIM; +#endif + SET_REG32_BIT(USBx->GREGS->GINTMSK, u32gintmskTmp); +} + +/** + * @brief get the working status of endpoint. + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval current status of the endpoint + */ +uint32_t usb_epstatusget(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + __IO uint32_t u32Status = 0UL; + uint32_t u32dxepctl; + + if (ep->ep_dir == 1U) { + u32dxepctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL); + + if (0UL != (u32dxepctl & USBFS_DIEPCTL_STALL)) { + u32Status = USB_EP_TX_STALL; + } else if (0UL != (u32dxepctl & USBFS_DIEPCTL_NAKSTS)) { + u32Status = USB_EP_TX_NAK; + } else { + u32Status = USB_EP_TX_VALID; + } + } else { + u32dxepctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL); + if (0UL != (u32dxepctl & USBFS_DOEPCTL_STALL)) { + u32Status = USB_EP_RX_STALL; + } else if (0UL != (u32dxepctl & USBFS_DOEPCTL_NAKSTS)) { + u32Status = USB_EP_RX_NAK; + } else { + u32Status = USB_EP_RX_VALID; + } + } + + return u32Status; +} + +/** + * @brief set the working status of endpoint. + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @param [in] Status new Status that the endpoint would be + * @retval None + */ +void usb_epstatusset(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint32_t Status) +{ + uint32_t u32dxepctl; + uint8_t u8RetFlag = 0U; + + if (ep->ep_dir == 1U) { + u32dxepctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL); + + switch (Status) { + case USB_EP_TX_STALL: + usb_setepstall(USBx, ep); + u8RetFlag = 1U; + break; + case USB_EP_TX_NAK: + u32dxepctl |= USBFS_DIEPCTL_SNAK; + break; + case USB_EP_TX_VALID: + if (0UL != (u32dxepctl & USBFS_DIEPCTL_STALL)) { + ep->datax_pid = 0U; + usb_clearepstall(USBx, ep); + u8RetFlag = 1U; + } + u32dxepctl |= (USBFS_DIEPCTL_CNAK | USBFS_DIEPCTL_USBAEP | USBFS_DIEPCTL_EPENA); + break; + case USB_EP_TX_DIS: + u32dxepctl &= (~USBFS_DIEPCTL_USBAEP); + break; + default: + break; + } + /* Write register */ + if (1U != u8RetFlag) { + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL, u32dxepctl); + } + } else { + u32dxepctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL); + + switch (Status) { + case USB_EP_RX_STALL: + u32dxepctl |= USBFS_DOEPCTL_STALL; + break; + case USB_EP_RX_NAK: + u32dxepctl |= USBFS_DOEPCTL_SNAK; + break; + case USB_EP_RX_VALID: + if (0UL != (u32dxepctl & USBFS_DOEPCTL_STALL)) { + ep->datax_pid = 0U; + usb_clearepstall(USBx, ep); + u8RetFlag = 1U; + } + u32dxepctl |= (USBFS_DOEPCTL_CNAK | USBFS_DOEPCTL_USBAEP | USBFS_DOEPCTL_EPENA); + break; + case USB_EP_RX_DIS: + u32dxepctl &= (~USBFS_DOEPCTL_USBAEP); + break; + default: + break; + } + /* Write register */ + if (1U != u8RetFlag) { + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32dxepctl); + } + } +} + +/** + * @brief enable the EP0 to be actiove + * @param [in] USBx usb instance + * @retval None + */ +void usb_ep0activate(LL_USB_TypeDef *USBx) +{ + uint32_t u32EnumSpeed; + uint32_t u32DiepctlTmp; + + u32EnumSpeed = READ_REG32(USBx->DREGS->DSTS) & USBFS_DSTS_ENUMSPD; + u32DiepctlTmp = READ_REG32(USBx->INEP_REGS[0]->DIEPCTL); + /* Set the MPS of the DIEPCTL0 based on the enumeration speed */ + if ((DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ == u32EnumSpeed) + || (DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ == u32EnumSpeed) + || (DSTS_ENUMSPD_FS_PHY_48MHZ == u32EnumSpeed)) { + u32DiepctlTmp &= (~USBFS_DIEPCTL_MPSIZ); + } else if (DSTS_ENUMSPD_LS_PHY_6MHZ == u32EnumSpeed) { + u32DiepctlTmp &= (~USBFS_DIEPCTL_MPSIZ); + u32DiepctlTmp |= (3UL << USBFS_DIEPCTL_MPSIZ_POS); + } else { + ; + } + WRITE_REG32(USBx->INEP_REGS[0]->DIEPCTL, u32DiepctlTmp); + SET_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_CGINAK); +} + +/** + * @brief enable an EP to be active + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval None + */ +void usb_epactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + uint32_t u32Addr; + uint32_t u32dxepctl; + uint32_t u32Daintmsk; + + if (ep->ep_dir == 1U) { + u32Addr = (uint32_t)(&(USBx->INEP_REGS[ep->epidx]->DIEPCTL)); + u32Daintmsk = 1UL << ep->epidx; + } else { + u32Addr = (uint32_t)(&(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL)); + u32Daintmsk = 1UL << (USBFS_DAINTMSK_OEPINTM_POS + ep->epidx); + } + u32dxepctl = READ_REG32(*(__IO uint32_t *)u32Addr); + if (0UL == (u32dxepctl & USBFS_DIEPCTL_USBAEP)) { + u32dxepctl = ((ep->maxpacket << USBFS_DIEPCTL_MPSIZ_POS) + | (((uint32_t)ep->trans_type) << USBFS_DIEPCTL_EPTYP_POS) + | (((uint32_t)ep->tx_fifo_num) << USBFS_DIEPCTL_TXFNUM_POS) + | USBFS_DIEPCTL_SD0PID_SEVNFRM + | USBFS_DIEPCTL_USBAEP); + + WRITE_REG32(*(__IO uint32_t *)u32Addr, u32dxepctl); + } + SET_REG32_BIT(USBx->DREGS->DAINTMSK, u32Daintmsk); +} + +/** + * @brief enable an EP to be deactive state if it is active + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval None + */ +void usb_epdeactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + uint32_t u32Daintmsk; + + if (ep->ep_dir == 1U) { + CLR_REG32_BIT(USBx->INEP_REGS[ep->epidx]->DIEPCTL, USBFS_DIEPCTL_USBAEP); + u32Daintmsk = 1UL << ep->epidx; + } else { + CLR_REG32_BIT(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, USBFS_DOEPCTL_USBAEP); + u32Daintmsk = 1UL << (USBFS_DAINTMSK_OEPINTM_POS + ep->epidx); + } + CLR_REG32_BIT(USBx->DREGS->DAINTMSK, u32Daintmsk); +} + +/** + * @brief Setup the data into the EP and begin to transmit data. + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_epntransbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn) +{ + uint32_t u32depctl; + uint32_t u32DeptsizTmp; + uint32_t u32Pktcnt; + uint32_t u32Xfersize; + + if (ep->ep_dir == 1U) { + u32depctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL); + /* Zero Length Packet? */ + if (ep->xfer_len == 0UL) { + u32Xfersize = 0UL; + u32Pktcnt = 1UL; + u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS); + } else { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + u32Xfersize = ep->xfer_len; + u32Pktcnt = (ep->xfer_len - 1U + ep->maxpacket) / ep->maxpacket; + u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS); + } + MODIFY_REG32(USBx->INEP_REGS[ep->epidx]->DIEPTSIZ, USBFS_DIEPTSIZ_XFRSIZ | USBFS_DIEPTSIZ_PKTCNT, u32DeptsizTmp); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPDMA, ep->dma_addr); + } else { + if (ep->trans_type != EP_TYPE_ISOC) { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) { + SET_REG32_BIT(USBx->DREGS->DIEPEMPMSK, 1UL << ep->epidx); + } + } + } + + if (ep->trans_type == EP_TYPE_ISOC) { + if (((READ_REG32(USBx->DREGS->DSTS) >> USBFS_DSTS_FNSOF_POS) & 0x1U) == 0U) { + u32depctl |= USBFS_DIEPCTL_SODDFRM; + } else { + u32depctl |= USBFS_DIEPCTL_SD0PID_SEVNFRM; + } + } + + u32depctl |= (USBFS_DIEPCTL_CNAK | USBFS_DIEPCTL_EPENA); + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL, u32depctl); + + if (ep->trans_type == EP_TYPE_ISOC) { + usb_wrpkt(USBx, ep->xfer_buff, ep->epidx, (uint16_t)ep->xfer_len, u8DmaEn); + } + } else { + u32depctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL); + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + if (ep->xfer_len == 0U) { + u32Xfersize = ep->maxpacket; + u32Pktcnt = 1UL; + u32DeptsizTmp = (u32Xfersize << USBFS_DOEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DOEPTSIZ_PKTCNT_POS); + } else { + u32Pktcnt = (ep->xfer_len + (ep->maxpacket - 1U)) / ep->maxpacket; + u32Xfersize = u32Pktcnt * ep->maxpacket; + u32DeptsizTmp = (u32Xfersize << USBFS_DOEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DOEPTSIZ_PKTCNT_POS); + ep->xfer_len = u32Xfersize; + } + MODIFY_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPTSIZ, USBFS_DOEPTSIZ_XFRSIZ | USBFS_DOEPTSIZ_PKTCNT, u32DeptsizTmp); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPDMA, ep->dma_addr); + } + + if (ep->trans_type == EP_TYPE_ISOC) { + if (0U != ep->datax_pid) { + u32depctl |= USBFS_DOEPCTL_SD1PID; + } else { + u32depctl |= USBFS_DOEPCTL_SD0PID; + } + } + u32depctl |= (USBFS_DOEPCTL_CNAK | USBFS_DOEPCTL_EPENA); + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32depctl); + } +} + +/** + * @brief Setup the data into the EP0 and begin to transmit data. + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_ep0transbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn) +{ + uint32_t u32depctl; + uint32_t u32DeptsizTmp; + uint32_t u32Pktcnt; + uint32_t u32Xfersize; + + if (ep->ep_dir == 1U) { + u32depctl = READ_REG32(USBx->INEP_REGS[0]->DIEPCTL); + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) { + u32Xfersize = 0UL; + u32Pktcnt = 1UL; + u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS); + } else { + if (ep->xfer_len > ep->maxpacket) { + ep->xfer_len = ep->maxpacket; + u32Xfersize = ep->maxpacket; + } else { + u32Xfersize = ep->xfer_len; + } + u32Pktcnt = 1UL; + u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS); + } + MODIFY_REG32(USBx->INEP_REGS[0]->DIEPTSIZ, USBFS_DIEPTSIZ_XFRSIZ | USBFS_DIEPTSIZ_PKTCNT, u32DeptsizTmp); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPDMA, ep->dma_addr); + } + + u32depctl |= (USBFS_DIEPCTL_CNAK | USBFS_DIEPCTL_EPENA); + WRITE_REG32(USBx->INEP_REGS[0]->DIEPCTL, u32depctl); + + if (u8DmaEn == 0U) { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) { + SET_REG32_BIT(USBx->DREGS->DIEPEMPMSK, 1UL << ep->epidx); + } + } + } else { + u32depctl = READ_REG32(USBx->OUTEP_REGS[0]->DOEPCTL); + /* Program the transfer size and packet count as follows: + * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) + * pktcnt = N */ + if (ep->xfer_len == 0U) { + u32Xfersize = 0UL; + u32Pktcnt = 1UL; + } else { + ep->xfer_len = LL_MIN(ep->rem_data_len, ep->maxpacket); + u32Xfersize = ep->xfer_len; + u32Pktcnt = 1UL; + } + u32DeptsizTmp = (u32Xfersize << USBFS_DOEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DOEPTSIZ_PKTCNT_POS); + MODIFY_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPTSIZ, USBFS_DOEPTSIZ_XFRSIZ | USBFS_DOEPTSIZ_PKTCNT, u32DeptsizTmp); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPDMA, ep->dma_addr); + } + u32depctl |= (USBFS_DOEPCTL_CNAK | USBFS_DOEPCTL_EPENA); + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32depctl); + } +} + +/** + * @brief Set the EP to be stall status + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval None + */ +void usb_setepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + uint32_t u32depctl; + + if (ep->ep_dir == 1U) { + u32depctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL); + if (0UL != (u32depctl & USBFS_DIEPCTL_EPENA)) { + u32depctl |= USBFS_DIEPCTL_EPDIS; + } + u32depctl |= USBFS_DIEPCTL_STALL; + WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL, u32depctl); + } else { + u32depctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL); + u32depctl |= USBFS_DOEPCTL_STALL; + WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32depctl); + } +} + +/** + * @brief clear the stall status of a EP + * @param [in] USBx usb instance + * @param [in] ep endpoint instance + * @retval None + */ +void usb_clearepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep) +{ + uint32_t tmp_depctl_addr; + uint32_t u32depctl; + + if (ep->ep_dir == 1U) { + tmp_depctl_addr = (uint32_t)(&(USBx->INEP_REGS[ep->epidx]->DIEPCTL)); + } else { + tmp_depctl_addr = (uint32_t)(&(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL)); + } + u32depctl = READ_REG32(tmp_depctl_addr); + + u32depctl &= (~USBFS_DIEPCTL_STALL); + if ((ep->trans_type == EP_TYPE_INTR) || (ep->trans_type == EP_TYPE_BULK)) { + u32depctl |= USBFS_DIEPCTL_SD0PID_SEVNFRM; + } + + WRITE_REG32(*(__IO uint32_t *)tmp_depctl_addr, u32depctl); +} + +/** + * @brief configure the EPO to receive data packets + * @param [in] USBx usb instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_ep0revcfg(LL_USB_TypeDef *USBx, uint8_t u8DmaEn, uint8_t *u8RevBuf) +{ + uint32_t u32deptsize; + uint32_t u32doepctl; + + u32deptsize = (3UL << USBFS_DOEPTSIZ0_STUPCNT_POS) + | (1UL << USBFS_DOEPTSIZ0_PKTCNT_POS) + | (64UL << USBFS_DOEPTSIZ0_XFRSIZ_POS); + + WRITE_REG32(USBx->OUTEP_REGS[0]->DOEPTSIZ, u32deptsize); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->OUTEP_REGS[0]->DOEPDMA, (uint32_t)&u8RevBuf); + u32doepctl = READ_REG32(USBx->OUTEP_REGS[0]->DOEPCTL); + u32doepctl |= (USBFS_DOEPCTL_EPENA | USBFS_DOEPCTL_USBAEP); + WRITE_REG32(USBx->OUTEP_REGS[0]->DOEPCTL, u32doepctl); + } +} + +/** + * @brief enable remote wakeup active + * @param [in] USBx usb instance + * @retval None + */ +void usb_remotewakeupen(LL_USB_TypeDef *USBx) +{ + uint32_t u32dsts; + + u32dsts = READ_REG32(USBx->DREGS->DSTS); + if (0UL != (u32dsts & USBFS_DSTS_SUSPSTS)) { + /* un-gate USB Core clock */ + CLR_REG32_BIT(*USBx->GCCTL, USBFS_GCCTL_GATEHCLK | USBFS_GCCTL_STPPCLK); + } + + SET_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_RWUSIG); + usb_mdelay(5UL); + CLR_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_RWUSIG); +} + +/** + * @brief control the device to connect or disconnect + * @param [in] USBx usb instance + * @param [in] link 0(conn) or 1(disconn) + * @retval None + */ +void usb_ctrldevconnect(LL_USB_TypeDef *USBx, uint8_t link) +{ + if (0U == link) { + CLR_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_SDIS); + } else { + SET_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_SDIS); + } + usb_mdelay(3UL); +} +#endif + +#ifdef USE_HOST_MODE +/** + * @brief Initializes the USB controller when it is host mode + * @param [in] USBx usb instance + * @param [in] basic_cfgs usb core basic cfgs + * @retval None + */ +void usb_hostmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs) +{ + __IO uint8_t u8Tmp = 0U; + WRITE_REG32(*USBx->GCCTL, 0UL); /* reset the register-GCCTL */ +#ifdef USB_HS_EXTERNAL_PHY + usb_fslspclkselset(USBx, HCFG_30_60_MHZ); /* PHY clock is running at 6MHz */ +#else + usb_fslspclkselset(USBx, HCFG_6_MHZ); /* PHY clock is running at 6MHz */ +#endif + usb_hprtrst(USBx); /* reset the port */ + usb_enumspeed(USBx); /* FS or LS bases on the maximum speed supported by the connected device */ + usb_sethostfifo(USBx); + /* Flush all the txFIFO and the whole rxFIFO */ + usb_txfifoflush(USBx, 0x10UL); + usb_rxfifoflush(USBx); + /* Clear all HC Interrupt bits that are pending */ + while (u8Tmp < basic_cfgs->host_chnum) { + WRITE_REG32(USBx->HC_REGS[u8Tmp]->HCINT, 0xFFFFFFFFUL); + WRITE_REG32(USBx->HC_REGS[u8Tmp]->HCINTMSK, 0UL); + u8Tmp++; + } + usb_hostinten(USBx, basic_cfgs->dmaen); +} + +/** + * @brief set the vbus if state is 1 or reset the vbus if state is 0. + * @param [in] USBx usb instance + * @param [in] u8State the vbus state it would be. + * @retval None + */ +void usb_vbusctrl(LL_USB_TypeDef *USBx, uint8_t u8State) +{ + uint32_t u32hprt; + + /* enable or disable the external charge pump */ + usb_bsp_drivevbus(USBx, u8State); + u32hprt = usb_rdhprt(USBx); + if ((0UL == (u32hprt & USBFS_HPRT_PWPR)) && (1U == u8State)) { + u32hprt |= USBFS_HPRT_PWPR; + WRITE_REG32(*USBx->HPRT, u32hprt); + } + if ((0UL != (u32hprt & USBFS_HPRT_PWPR)) && (0U == u8State)) { + u32hprt &= (~USBFS_HPRT_PWPR); + WRITE_REG32(*USBx->HPRT, u32hprt); + } +} + +/** + * @brief Enables the related interrupts when the core is host mode + * @param [in] USBx usb instance + * @param [in] u8DmaEn USB DMA status + * @retval None + */ +void usb_hostinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn) +{ + uint32_t u32gIntmsk = 0UL; + WRITE_REG32(USBx->GREGS->GINTMSK, 0UL); + /* Clear the pending interrupt bits */ + WRITE_REG32(USBx->GREGS->GINTSTS, 0xFFFFFFFFUL); + + /* Enable the normal interrupt bits */ + usb_normalinten(USBx); + + if (u8DmaEn == 0U) { + u32gIntmsk |= USBFS_GINTMSK_RXFNEM; + } + u32gIntmsk |= (USBFS_GINTMSK_HPRTIM + | USBFS_GINTMSK_HCIM + | USBFS_GINTMSK_DISCIM + | USBFS_GINTMSK_SOFM + | USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM); + SET_REG32_BIT(USBx->GREGS->GINTMSK, u32gIntmsk); +} + +/** + * @brief Reset the port, the 1'b0 state must last at lease 10ms. + * @param [in] USBx usb instance + * @retval None + */ +void usb_hprtrst(LL_USB_TypeDef *USBx) +{ + uint32_t u32hprt; + u32hprt = usb_rdhprt(USBx); + u32hprt |= USBFS_HPRT_PRST; + WRITE_REG32(*USBx->HPRT, u32hprt); + usb_mdelay(10UL); + u32hprt &= ~USBFS_HPRT_PRST; + WRITE_REG32(*USBx->HPRT, u32hprt); + usb_mdelay(20UL); + + //SET_REG32_BIT(*USBx->HPRT, USBFS_HPRT_PRST); + //usb_mdelay(10UL); + //CLR_REG32_BIT(*USBx->HPRT, USBFS_HPRT_PRST); + //usb_mdelay(20UL); +} + +/** + * @brief Prepares transferring packets on a host channel + * @param [in] USBx usb instance + * @param [in] hc_num channel index + * @param [in] pCh channel structure + * @param [in] u8DmaEn USB DMA status + * @retval status in byte + */ +uint8_t usb_inithch(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn) +{ + uint32_t u32hcintmsk = 0UL; + uint32_t u32hcchar = 0UL; + + WRITE_REG32(USBx->HC_REGS[hc_num]->HCINT, 0xFFFFFFFFUL); + switch (pCh->ep_type) { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + u32hcintmsk |= (USBFS_HCINTMSK_XFRCM + | USBFS_HCINTMSK_STALLM + | USBFS_HCINTMSK_TXERRM + | USBFS_HCINTMSK_DTERRM + | USBFS_HCINTMSK_NAKM); + if (0U != pCh->is_epin) { + u32hcintmsk |= USBFS_HCINTMSK_BBERRM; + } else { + if (0U != pCh->do_ping) { + u32hcintmsk |= USBFS_HCINTMSK_ACKM; + } + } + break; + case EP_TYPE_INTR: + u32hcintmsk |= (USBFS_HCINTMSK_XFRCM + | USBFS_HCINTMSK_NAKM + | USBFS_HCINTMSK_STALLM + | USBFS_HCINTMSK_TXERRM + | USBFS_HCINTMSK_DTERRM + | USBFS_HCINTMSK_FRMORM); + if (0U != pCh->is_epin) { + u32hcintmsk |= USBFS_HCINTMSK_BBERRM; + } + break; + case EP_TYPE_ISOC: + u32hcintmsk |= (USBFS_HCINTMSK_XFRCM + | USBFS_HCINTMSK_FRMORM + | USBFS_HCINTMSK_ACKM); + + if (0U != pCh->is_epin) { + u32hcintmsk |= (USBFS_HCINTMSK_TXERRM | USBFS_HCINTMSK_BBERRM); + } + break; + default: + break; + } + + WRITE_REG32(USBx->HC_REGS[hc_num]->HCINTMSK, u32hcintmsk); + SET_REG32_BIT(USBx->HREGS->HAINTMSK, 1UL << hc_num); + + /* enable the host channel interrupts */ + SET_REG32_BIT(USBx->GREGS->GINTMSK, USBFS_GINTMSK_HCIM); + + /* modify HCCHAR */ + u32hcchar |= (((uint32_t)pCh->dev_addr) << USBFS_HCCHAR_DAD_POS); + u32hcchar |= (((uint32_t)pCh->ep_idx) << USBFS_HCCHAR_EPNUM_POS); + u32hcchar |= (((uint32_t)pCh->is_epin) << USBFS_HCCHAR_EPDIR_POS); + u32hcchar |= (((uint32_t)pCh->ep_type) << USBFS_HCCHAR_EPTYP_POS); + u32hcchar |= (((uint32_t)pCh->max_packet) << USBFS_HCCHAR_MPSIZ_POS); + if (PRTSPD_LOW_SPEED == pCh->ch_speed) { + u32hcchar |= USBFS_HCCHAR_LSDEV; + } else { + u32hcchar &= ~USBFS_HCCHAR_LSDEV; + } + + if (pCh->ep_type == EP_TYPE_INTR) { + u32hcchar |= USBFS_HCCHAR_ODDFRM; + } + WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar); + return USB_OK; +} + +/** + * @brief Start transfer on the channel whose index is hc_num. + * @param [in] USBx usb instance + * @param [in] hc_num channel index + * @param [in] pCh channel structure + * @param [in] u8DmaEn USB DMA status + * @retval status in 8 bits + */ +uint8_t usb_hchtransbegin(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn) +{ + uint32_t u32hcchar; + uint32_t u32hctsiz = 0UL; + uint32_t u32hnptxsts; + uint32_t u32hptxsts; + uint16_t u16LenWords; + uint16_t u16NumPacket; + uint16_t u16MaxHcPktCount = 256U; + + /* Compute the expected number of packets associated to the transfer */ + if (pCh->xfer_len > 0U) { + u16NumPacket = (uint16_t)((pCh->xfer_len + + (uint32_t)pCh->max_packet - 1UL) / (uint32_t)pCh->max_packet); + + if (u16NumPacket > u16MaxHcPktCount) { + u16NumPacket = u16MaxHcPktCount; + pCh->xfer_len = (uint32_t)u16NumPacket * (uint32_t)pCh->max_packet; + } + } else { + u16NumPacket = 1U; + } + if (0U != pCh->is_epin) { + pCh->xfer_len = (uint32_t)u16NumPacket * (uint32_t)pCh->max_packet; + } + + u32hctsiz |= (((uint32_t)pCh->xfer_len) << USBFS_HCTSIZ_XFRSIZ_POS); + u32hctsiz |= (((uint32_t)u16NumPacket) << USBFS_HCTSIZ_PKTCNT_POS); + u32hctsiz |= (((uint32_t)pCh->pid_type) << USBFS_HCTSIZ_DPID_POS); + WRITE_REG32(USBx->HC_REGS[hc_num]->HCTSIZ, u32hctsiz); + + if (u8DmaEn == 1U) { + WRITE_REG32(USBx->HC_REGS[hc_num]->HCDMA, pCh->xfer_buff); + } + + u32hcchar = READ_REG32(USBx->HC_REGS[hc_num]->HCCHAR); + u32hcchar |= (usb_ifevenframe(USBx) << USBFS_HCCHAR_ODDFRM_POS); + + /* enable this host channel whose number is hc_num */ + u32hcchar |= USBFS_HCCHAR_CHENA; + u32hcchar &= ~USBFS_HCCHAR_CHDIS; + WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar); + + if (u8DmaEn == 0U) { + if ((pCh->is_epin == 0U) && (pCh->xfer_len > 0U)) { + switch (pCh->ep_type) { + /* Non-periodic transmit */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + u32hnptxsts = READ_REG32(USBx->GREGS->HNPTXSTS); + u16LenWords = (uint16_t)((pCh->xfer_len + 3UL) / 4UL); + /* check if the amount of free space available in the non-periodic txFIFO is enough */ + if (u16LenWords > ((u32hnptxsts & USBFS_HNPTXSTS_NPTXFSAV) >> USBFS_HNPTXSTS_NPTXFSAV_POS)) { + /* enable interrrupt of nptxfempty of GINTMSK*/ + SET_REG32_BIT(USBx->GREGS->GINTMSK, USBFS_GINTMSK_NPTXFEM); + } + break; + /* Periodic trnsmit */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + u32hptxsts = READ_REG32(USBx->HREGS->HPTXSTS); + u16LenWords = (uint16_t)((pCh->xfer_len + 3UL) / 4UL); + /* check if the space of periodic TxFIFO is enough */ + if (u16LenWords > ((u32hptxsts & USBFS_HPTXSTS_PTXFSAVL) >> USBFS_HPTXSTS_PTXFSAVL_POS)) { + /* enable interrrupt of ptxfempty of GINTMSK */ + SET_REG32_BIT(USBx->GREGS->GINTMSK, USBFS_GINTMSK_PTXFEM); + } + break; + default: + break; + } + + usb_wrpkt(USBx, pCh->xfer_buff, hc_num, (uint16_t)pCh->xfer_len, u8DmaEn); + } + } + return USB_OK; +} + +/** + * @brief Stop the host and flush all the txFIFOs and the whole rxFIFO. + * @param [in] USBx usb instance + * @param [in] u8ChNum Host channel number + * @retval None + */ +void usb_hoststop(LL_USB_TypeDef *USBx, uint8_t u8ChNum) +{ + __IO uint32_t u32Tmp = 0UL; + + WRITE_REG32(USBx->HREGS->HAINTMSK, 0UL); + WRITE_REG32(USBx->HREGS->HAINT, 0xFFFFFFFFUL); + + do { + usb_chrst(USBx, (uint8_t)u32Tmp); + u32Tmp++; + } while (u32Tmp < u8ChNum); + /* flush all the txFIFOs and the whole rxFIFO */ + usb_rxfifoflush(USBx); + usb_txfifoflush(USBx, 0x10UL); +} + +/** + * @brief make the channel to halt + * @param [in] USBx usb instance + * @param [in] hc_num channel index + * @retval None + */ +void usb_hchstop(LL_USB_TypeDef *USBx, uint8_t hc_num) +{ + uint32_t u32hcchar; + + u32hcchar = READ_REG32(USBx->HC_REGS[hc_num]->HCCHAR); + u32hcchar |= (USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS); + /* Check for space in the request queue to issue the halt. */ + if ((EP_TYPE_CTRL == ((u32hcchar & USBFS_HCCHAR_EPTYP) >> USBFS_HCCHAR_EPTYP_POS)) + || (EP_TYPE_BULK == ((u32hcchar & USBFS_HCCHAR_EPTYP) >> USBFS_HCCHAR_EPTYP_POS))) { + if (0UL == (READ_REG32(USBx->GREGS->HNPTXSTS) & USBFS_HNPTXSTS_NPTQXSAV)) { + u32hcchar &= (~USBFS_HCCHAR_CHENA); + } + } else { + if (0UL == (READ_REG32(USBx->HREGS->HPTXSTS) & USBFS_HPTXSTS_PTXQSAV)) { + u32hcchar &= (~USBFS_HCCHAR_CHENA); + } + } + WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar); +} + +#endif + +/** + * @} +*/ + +#endif /* LL_USB_ENABLE */ + +/** + * @} +*/ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_utility.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_utility.c new file mode 100644 index 0000000000..0900b3232b --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_utility.c @@ -0,0 +1,396 @@ +/** + ******************************************************************************* + * @file hc32_ll_utility.c + * @brief This file provides utility functions for DDL. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_UTILITY UTILITY + * @brief DDL Utility Driver + * @{ + */ + +#if (LL_UTILITY_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup UTILITY_Local_Variables UTILITY Local Variables + * @{ + */ + +static uint32_t m_u32TickStep = 0UL; +static __IO uint32_t m_u32TickCount = 0UL; + +#if (LL_PRINT_ENABLE == DDL_ON) +static void *m_pvPrintDevice = NULL; +static uint32_t m_u32PrintTimeout = 0UL; +#endif + +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup UTILITY_Local_Functions UTILITY Local Functions + * @{ + */ +#if (LL_PRINT_ENABLE == DDL_ON) + +/** + * @brief Set print device. + * @param [in] pvPrintDevice Pointer to print device + * @retval None + */ +__STATIC_INLINE void LL_SetPrintDevice(void *pvPrintDevice) +{ + m_pvPrintDevice = pvPrintDevice; +} + +/** + * @brief Get print device. + * @param None + * @retval Pointer to print device + */ +__STATIC_INLINE void *LL_GetPrintDevice(void) +{ + return m_pvPrintDevice; +} + +/** + * @brief Set print timeout. + * @param [in] u32Timeout Print timeout value + * @retval None + */ +__STATIC_INLINE void LL_SetPrintTimeout(uint32_t u32Timeout) +{ + m_u32PrintTimeout = u32Timeout; +} + +/** + * @brief Get print timeout. + * @param None + * @retval Print timeout value + */ +__STATIC_INLINE uint32_t LL_GetPrintTimeout(void) +{ + return m_u32PrintTimeout; +} +#endif /* LL_PRINT_ENABLE */ + +/** + * @} + */ + +/** + * @defgroup UTILITY_Global_Functions UTILITY Global Functions + * @{ + */ + +/** + * @brief Delay function, delay ms approximately + * @param [in] u32Count ms + * @retval None + */ +void DDL_DelayMS(uint32_t u32Count) +{ + __IO uint32_t i; + const uint32_t u32Cyc = (HCLK_VALUE + 10000UL - 1UL) / 10000UL; + + while (u32Count-- > 0UL) { + i = u32Cyc; + while (i-- > 0UL) { + } + } +} + +/** + * @brief Delay function, delay us approximately + * @param [in] u32Count us + * @retval None + */ +void DDL_DelayUS(uint32_t u32Count) +{ + __IO uint32_t i; + const uint32_t u32Cyc = (HCLK_VALUE + 10000000UL - 1UL) / 10000000UL; + + while (u32Count-- > 0UL) { + i = u32Cyc; + while (i-- > 0UL) { + } + } +} + +/** + * @brief This function Initializes the interrupt frequency of the SysTick. + * @param [in] u32Freq SysTick interrupt frequency (1 to 1000). + * @retval int32_t: + * - LL_OK: SysTick Initializes succeed + * - LL_ERR: SysTick Initializes failed + */ +__WEAKDEF int32_t SysTick_Init(uint32_t u32Freq) +{ + int32_t i32Ret = LL_ERR; + + if ((0UL != u32Freq) && (u32Freq <= 1000UL)) { + m_u32TickStep = 1000UL / u32Freq; + /* Configure the SysTick interrupt */ + if (0UL == SysTick_Config(HCLK_VALUE / u32Freq)) { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief This function provides minimum delay (in milliseconds). + * @param [in] u32Delay Delay specifies the delay time. + * @retval None + */ +__WEAKDEF void SysTick_Delay(uint32_t u32Delay) +{ + const uint32_t tickStart = SysTick_GetTick(); + uint32_t tickEnd = u32Delay; + uint32_t tickMax; + + if (m_u32TickStep != 0UL) { + tickMax = 0xFFFFFFFFUL / m_u32TickStep * m_u32TickStep; + /* Add a freq to guarantee minimum wait */ + if ((u32Delay >= tickMax) || ((tickMax - u32Delay) < m_u32TickStep)) { + tickEnd = tickMax; + } + while ((SysTick_GetTick() - tickStart) < tickEnd) { + } + } +} + +/** + * @brief This function is called to increment a global variable "u32TickCount". + * @note This variable is incremented in SysTick ISR. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_IncTick(void) +{ + m_u32TickCount += m_u32TickStep; +} + +/** + * @brief Provides a tick value in millisecond. + * @param None + * @retval Tick value + */ +__WEAKDEF uint32_t SysTick_GetTick(void) +{ + return m_u32TickCount; +} + +/** + * @brief Suspend SysTick increment. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_Suspend(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume SysTick increment. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_Resume(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +#ifdef __DEBUG +/** + * @brief DDL assert error handle function + * @param [in] file Point to the current assert the wrong file. + * @param [in] line Point line assert the wrong file in the current. + * @retval None + */ +__WEAKDEF void DDL_AssertHandler(const char *file, int line) +{ + /* Users can re-implement this function to print information */ + DDL_Printf("Wrong parameters value: file %s on line %d\r\n", file, line); + + for (;;) { + } +} +#endif /* __DEBUG */ + +#if (LL_PRINT_ENABLE == DDL_ON) + +#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \ + (defined (__ICCARM__)) || (defined (__CC_ARM)) +/** + * @brief Re-target fputc function. + * @param [in] ch + * @param [in] f + * @retval int32_t + */ +int32_t fputc(int32_t ch, FILE *f) +{ + (void)f; /* Prevent unused argument compilation warning */ + + return (LL_OK == DDL_ConsoleOutputChar((char)ch)) ? ch : -1; +} + +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) +/** + * @brief Re-target _write function. + * @param [in] fd + * @param [in] data + * @param [in] size + * @retval int32_t + */ +int32_t _write(int fd, char data[], int32_t size) +{ + int32_t i = -1; + + if (NULL != data) { + (void)fd; /* Prevent unused argument compilation warning */ + + for (i = 0; i < size; i++) { + if (LL_OK != DDL_ConsoleOutputChar(data[i])) { + break; + } + } + } + + return i ? i : -1; +} +#endif + +/** + * @brief Initialize printf function + * @param [in] vpDevice Pointer to print device + * @param [in] u32Param Print device parameter + * @param [in] pfnPreinit The function pointer for initializing clock, port, print device etc. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR: The callback function pfnPreinit occurs error. + * - LL_ERR_INVD_PARAM: The pointer pfnPreinit is NULL. + */ +int32_t LL_PrintfInit(void *vpDevice, uint32_t u32Param, int32_t (*pfnPreinit)(void *vpDevice, uint32_t u32Param)) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pfnPreinit) { + i32Ret = pfnPreinit(vpDevice, u32Param); /* The callback function initialize clock, port, print device etc */ + if (LL_OK == i32Ret) { + LL_SetPrintDevice(vpDevice); + LL_SetPrintTimeout((u32Param == 0UL) ? 0UL : (HCLK_VALUE / u32Param)); + } else { + i32Ret = LL_ERR; + DDL_ASSERT(i32Ret == LL_OK); /* Initialize unsuccessfully */ + } + } + + return i32Ret; +} + +/** + * @brief Transmit character. + * @param [in] cData The character for transmitting + * @retval int32_t: + * - LL_OK: Transmit successfully. + * - LL_ERR_TIMEOUT: Transmit timeout. + * - LL_ERR_INVD_PARAM: The print device is invalid. + */ +__WEAKDEF int32_t DDL_ConsoleOutputChar(char cData) +{ + uint32_t u32TxEmpty = 0UL; + __IO uint32_t u32TmpCount = 0UL; + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32Timeout = LL_GetPrintTimeout(); + CM_USART_TypeDef *USARTx = (CM_USART_TypeDef *)LL_GetPrintDevice(); + + if (NULL != USARTx) { + /* Wait TX data register empty */ + while ((u32TmpCount <= u32Timeout) && (0UL == u32TxEmpty)) { + u32TxEmpty = READ_REG32_BIT(USARTx->SR, USART_SR_TXE); + u32TmpCount++; + } + + if (0UL != u32TxEmpty) { + WRITE_REG32(USARTx->DR, (uint32_t)cData); + i32Ret = LL_OK; + } else { + i32Ret = LL_ERR_TIMEOUT; + } + } + + return i32Ret; +} + +#endif /* LL_PRINT_ENABLE */ + +/** + * @} + */ + +#endif /* LL_UTILITY_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_wdt.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_wdt.c new file mode 100644 index 0000000000..b16d46024d --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32_ll_wdt.c @@ -0,0 +1,256 @@ +/** + ******************************************************************************* + * @file hc32_ll_wdt.c + * @brief This file provides firmware functions to manage the General Watch Dog + * Timer(WDT). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_wdt.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_WDT WDT + * @brief General Watch Dog Timer + * @{ + */ + +#if (LL_WDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup WDT_Local_Macros WDT Local Macros + * @{ + */ + +/* WDT Refresh Key */ +#define WDT_REFRESH_KEY_START (0x0123UL) +#define WDT_REFRESH_KEY_END (0x3210UL) + +/* WDT clear flag timeout(ms) */ +#define WDT_CLR_FLAG_TIMEOUT (5UL) + +/* WDT Registers Clear Mask */ +#define WDT_CR_CLR_MASK (WDT_CR_PERI | WDT_CR_CKS | WDT_CR_WDPT | \ + WDT_CR_SLPOFF | WDT_CR_ITS) + +/** + * @defgroup WDT_Check_Parameters_Validity WDT Check Parameters Validity + * @{ + */ +#define IS_WDT_CNT_PERIOD(x) \ +( ((x) == WDT_CNT_PERIOD256) || \ + ((x) == WDT_CNT_PERIOD4096) || \ + ((x) == WDT_CNT_PERIOD16384) || \ + ((x) == WDT_CNT_PERIOD65536)) + +#define IS_WDT_CLK_DIV(x) \ +( ((x) == WDT_CLK_DIV4) || \ + ((x) == WDT_CLK_DIV64) || \ + ((x) == WDT_CLK_DIV128) || \ + ((x) == WDT_CLK_DIV256) || \ + ((x) == WDT_CLK_DIV512) || \ + ((x) == WDT_CLK_DIV1024) || \ + ((x) == WDT_CLK_DIV2048) || \ + ((x) == WDT_CLK_DIV8192)) + +#define IS_WDT_REFRESH_RANGE(x) \ +( ((x) == WDT_RANGE_0TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT) || \ + ((x) == WDT_RANGE_25TO50PCT) || \ + ((x) == WDT_RANGE_0TO50PCT) || \ + ((x) == WDT_RANGE_50TO75PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_50TO75PCT) || \ + ((x) == WDT_RANGE_25TO75PCT) || \ + ((x) == WDT_RANGE_0TO75PCT) || \ + ((x) == WDT_RANGE_75TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_25TO50PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_0TO50PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_50TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_50TO100PCT) || \ + ((x) == WDT_RANGE_25TO100PCT)) + +#define IS_WDT_LPM_CNT(x) \ +( ((x) == WDT_LPM_CNT_CONTINUE) || \ + ((x) == WDT_LPM_CNT_STOP)) + +#define IS_WDT_EXP_TYPE(x) \ +( ((x) == WDT_EXP_TYPE_INT) || \ + ((x) == WDT_EXP_TYPE_RST)) + +#define IS_WDT_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | WDT_FLAG_ALL) == WDT_FLAG_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Functions WDT Global Functions + * @{ + */ + +/** + * @brief Initializes WDT. + * @param [in] pstcWdtInit Pointer to a @ref stc_wdt_init_t structure + * @retval int32_t: + * - LL_OK: Initializes success + * - LL_ERR_INVD_PARAM: pstcWdtInit == NULL + */ +int32_t WDT_Init(const stc_wdt_init_t *pstcWdtInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcWdtInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_WDT_CNT_PERIOD(pstcWdtInit->u32CountPeriod)); + DDL_ASSERT(IS_WDT_CLK_DIV(pstcWdtInit->u32ClockDiv)); + DDL_ASSERT(IS_WDT_REFRESH_RANGE(pstcWdtInit->u32RefreshRange)); + DDL_ASSERT(IS_WDT_LPM_CNT(pstcWdtInit->u32LPMCount)); + DDL_ASSERT(IS_WDT_EXP_TYPE(pstcWdtInit->u32ExceptionType)); + + /* WDT CR Configuration(Software Start Mode) */ + MODIFY_REG32(CM_WDT->CR, WDT_CR_CLR_MASK, + (pstcWdtInit->u32CountPeriod | pstcWdtInit->u32ClockDiv | + pstcWdtInit->u32RefreshRange | pstcWdtInit->u32LPMCount | + pstcWdtInit->u32ExceptionType)); + } + + return i32Ret; +} + +/** + * @brief WDT feed dog. + * @note In software startup mode, Start counter when refreshing for the first time. + * @param None + * @retval None + */ +void WDT_FeedDog(void) +{ + WRITE_REG32(CM_WDT->RR, WDT_REFRESH_KEY_START); + WRITE_REG32(CM_WDT->RR, WDT_REFRESH_KEY_END); +} + +/** + * @brief Get WDT flag status. + * @param [in] u32Flag WDT flag type + * This parameter can be one or any combination of the following values: + * @arg WDT_FLAG_UDF: Count underflow flag + * @arg WDT_FLAG_REFRESH: Refresh error flag + * @arg WDT_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t WDT_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_WDT_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_WDT->SR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear WDT flag. + * @param [in] u32Flag WDT flag type + * This parameter can be one or any combination of the following values: + * @arg WDT_FLAG_UDF: Count underflow flag + * @arg WDT_FLAG_REFRESH: Refresh error flag + * @arg WDT_FLAG_ALL: All of the above + * @retval int32_t: + * - LL_OK: Clear flag success + * - LL_ERR_TIMEOUT: Clear flag timeout + */ +int32_t WDT_ClearStatus(uint32_t u32Flag) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Check parameters */ + DDL_ASSERT(IS_WDT_FLAG(u32Flag)); + + CLR_REG32_BIT(CM_WDT->SR, u32Flag); + /* Waiting for FLAG bit clear */ + u32Count = WDT_CLR_FLAG_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32_BIT(CM_WDT->SR, u32Flag)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_WDT_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32f460_ll_interrupts_share.c b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32f460_ll_interrupts_share.c new file mode 100644 index 0000000000..12ef540b2c --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/drivers/hc32_ll_driver/src/hc32f460_ll_interrupts_share.c @@ -0,0 +1,2188 @@ +/** + ******************************************************************************* + * @file hc32f460_ll_interrupts_share.c + * @brief This file provides firmware functions to manage the Share Interrupt + * Controller (SHARE_INTERRUPTS). + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f460_ll_interrupts_share.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_HC32F460_SHARE_INTERRUPTS SHARE_INTERRUPTS + * @brief Share Interrupts Driver Library + * @{ + */ + +#if (LL_INTERRUPTS_SHARE_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup Share_Interrupts_Global_Functions Share Interrupts Global Functions + * @{ + */ +/** + * @brief Share IRQ configure + * @param [in] enIntSrc: Peripheral interrupt source @ref en_int_src_t + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: Share IRQ configure successfully + */ +int32_t INTC_ShareIrqCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState) +{ + __IO uint32_t *INTC_VSSELx; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + INTC_VSSELx = (__IO uint32_t *)(((uint32_t)&CM_INTC->VSSEL128) + (4U * ((uint32_t)enIntSrc / 0x20U))); + if (ENABLE == enNewState) { + SET_REG32_BIT(*INTC_VSSELx, (1UL << ((uint32_t)enIntSrc & 0x1FUL))); + } else { + CLR_REG32_BIT(*INTC_VSSELx, (1UL << ((uint32_t)enIntSrc & 0x1FUL))); + } + return LL_OK; +} + +/** + * @brief Interrupt No.128 share IRQ handler + * @param None + * @retval None + */ +void IRQ128_Handler(void) +{ + const uint32_t VSSEL128 = CM_INTC->VSSEL128; + + /* external interrupt 00 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR0) && (0UL != (VSSEL128 & BIT_MASK_00))) { + EXTINT00_IrqHandler(); + } + /* external interrupt 01 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR1) && (0UL != (VSSEL128 & BIT_MASK_01))) { + EXTINT01_IrqHandler(); + } + /* external interrupt 02 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR2) && (0UL != (VSSEL128 & BIT_MASK_02))) { + EXTINT02_IrqHandler(); + } + /* external interrupt 03 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR3) && (0UL != (VSSEL128 & BIT_MASK_03))) { + EXTINT03_IrqHandler(); + } + /* external interrupt 04 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR4) && (0UL != (VSSEL128 & BIT_MASK_04))) { + EXTINT04_IrqHandler(); + } + /* external interrupt 05 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR5) && (0UL != (VSSEL128 & BIT_MASK_05))) { + EXTINT05_IrqHandler(); + } + /* external interrupt 06 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR6) && (0UL != (VSSEL128 & BIT_MASK_06))) { + EXTINT06_IrqHandler(); + } + /* external interrupt 07 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR7) && (0UL != (VSSEL128 & BIT_MASK_07))) { + EXTINT07_IrqHandler(); + } + /* external interrupt 08 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR8) && (0UL != (VSSEL128 & BIT_MASK_08))) { + EXTINT08_IrqHandler(); + } + /* external interrupt 09 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR9) && (0UL != (VSSEL128 & BIT_MASK_09))) { + EXTINT09_IrqHandler(); + } + /* external interrupt 10 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR10) && (0UL != (VSSEL128 & BIT_MASK_10))) { + EXTINT10_IrqHandler(); + } + /* external interrupt 11 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR11) && (0UL != (VSSEL128 & BIT_MASK_11))) { + EXTINT11_IrqHandler(); + } + /* external interrupt 12 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR12) && (0UL != (VSSEL128 & BIT_MASK_12))) { + EXTINT12_IrqHandler(); + } + /* external interrupt 13 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR13) && (0UL != (VSSEL128 & BIT_MASK_13))) { + EXTINT13_IrqHandler(); + } + /* external interrupt 14 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR14) && (0UL != (VSSEL128 & BIT_MASK_14))) { + EXTINT14_IrqHandler(); + } + /* external interrupt 15 */ + if ((1UL == bCM_INTC->EIRQFR_b.EIRQFR15) && (0UL != (VSSEL128 & BIT_MASK_15))) { + EXTINT15_IrqHandler(); + } +} + +/** + * @brief Interrupt No.129 share IRQ handler + * @param None + * @retval None + */ +void IRQ129_Handler(void) +{ + const uint32_t VSSEL129 = CM_INTC->VSSEL129; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + + /* DMA1 Ch.0 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL0_b.IE) { + /* DMA1 Ch.0 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC0) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC0) && (0UL != (VSSEL129 & BIT_MASK_00))) { + DMA1_TC0_IrqHandler(); + } + } + /* DMA1 ch.0 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC0) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC0) && (0UL != (VSSEL129 & BIT_MASK_08))) { + DMA1_BTC0_IrqHandler(); + } + } + /* DMA1 ch.0 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_00 | BIT_MASK_16); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_00 | BIT_MASK_16)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error0_IrqHandler(); + } + } + /* DMA1 Ch.1 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL1_b.IE) { + /* DMA1 Ch.1 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC1) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC1) && (0UL != (VSSEL129 & BIT_MASK_01))) { + DMA1_TC1_IrqHandler(); + } + } + /* DMA1 ch.1 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC1) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC1) && (0UL != (VSSEL129 & BIT_MASK_09))) { + DMA1_BTC1_IrqHandler(); + } + } + /* DMA1 ch.1 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_01 | BIT_MASK_17); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_01 | BIT_MASK_17)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error1_IrqHandler(); + } + } + /* DMA1 Ch.2 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL2_b.IE) { + /* DMA1 Ch.2 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC2) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC2) && (0UL != (VSSEL129 & BIT_MASK_02))) { + DMA1_TC2_IrqHandler(); + } + } + /* DMA1 ch.2 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC2) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC2) && (0UL != (VSSEL129 & BIT_MASK_10))) { + DMA1_BTC2_IrqHandler(); + } + } + /* DMA1 ch.2 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_02 | BIT_MASK_18); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_02 | BIT_MASK_18)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error2_IrqHandler(); + } + } + /* DMA1 Ch.3 interrupt enabled */ + if (1UL == bCM_DMA1->CHCTL3_b.IE) { + /* DMA1 Ch.3 Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKTC3) { + if ((1UL == bCM_DMA1->INTSTAT1_b.TC3) && (0UL != (VSSEL129 & BIT_MASK_03))) { + DMA1_TC3_IrqHandler(); + } + } + /* DMA1 ch.3 Block Tx completed */ + if (0UL == bCM_DMA1->INTMASK1_b.MSKBTC3) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC3) && (0UL != (VSSEL129 & BIT_MASK_11))) { + DMA1_BTC3_IrqHandler(); + } + } + /* DMA1 ch.3 Transfer/Request Error */ + u32Tmp1 = CM_DMA1->INTSTAT0 & (BIT_MASK_03 | BIT_MASK_19); + u32Tmp2 = (uint32_t)(~(CM_DMA1->INTMASK0) & (BIT_MASK_03 | BIT_MASK_19)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) { + DMA1_Error3_IrqHandler(); + } + } + /* DMA2 Ch.0 interrupt enabled */ + if (1UL == bCM_DMA2->CHCTL0_b.IE) { + /* DMA2 ch.0 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC0) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC0) && (0UL != (VSSEL129 & BIT_MASK_04))) { + DMA2_TC0_IrqHandler(); + } + } + /* DMA2 ch.0 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC0) { + if ((1UL == bCM_DMA2->INTSTAT1_b.BTC0) && (0UL != (VSSEL129 & BIT_MASK_12))) { + DMA2_BTC0_IrqHandler(); + } + } + /* DMA2 Ch.0 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_00 | BIT_MASK_16); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_00 | BIT_MASK_16)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_17))) { + DMA2_Error0_IrqHandler(); + } + } + if (1UL == bCM_DMA2->CHCTL1_b.IE) { + /* DMA2 ch.1 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC1) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC1) && (0UL != (VSSEL129 & BIT_MASK_05))) { + DMA2_TC1_IrqHandler(); + } + } + /* DMA2 ch.1 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC1) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC1) && (0UL != (VSSEL129 & BIT_MASK_13))) { + DMA2_BTC1_IrqHandler(); + } + } + /* DMA2 Ch.1 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_01 | BIT_MASK_17); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_01 | BIT_MASK_17)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_17))) { + DMA2_Error1_IrqHandler(); + } + } + if (1UL == bCM_DMA2->CHCTL2_b.IE) { + /* DMA2 ch.2 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC2) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC2) && (0UL != (VSSEL129 & BIT_MASK_06))) { + DMA2_TC2_IrqHandler(); + } + } + /* DMA2 ch.2 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC2) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC2) && (0UL != (VSSEL129 & BIT_MASK_14))) { + DMA2_BTC2_IrqHandler(); + } + } + /* DMA2 Ch.2 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_02 | BIT_MASK_18); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_02 | BIT_MASK_18)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_17))) { + DMA2_Error2_IrqHandler(); + } + } + if (1UL == bCM_DMA2->CHCTL3_b.IE) { + /* DMA2 ch.3 Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKTC3) { + if ((1UL == bCM_DMA2->INTSTAT1_b.TC3) && (0UL != (VSSEL129 & BIT_MASK_07))) { + DMA2_TC3_IrqHandler(); + } + } + /* DMA2 ch.3 Block Tx completed */ + if (0UL == bCM_DMA2->INTMASK1_b.MSKBTC3) { + if ((1UL == bCM_DMA1->INTSTAT1_b.BTC3) && (0UL != (VSSEL129 & BIT_MASK_15))) { + DMA2_BTC3_IrqHandler(); + } + } + /* DMA2 Ch.3 Transfer/Request Error */ + u32Tmp1 = CM_DMA2->INTSTAT0 & (BIT_MASK_03 | BIT_MASK_19); + u32Tmp2 = (uint32_t)(~(CM_DMA2->INTMASK0) & (BIT_MASK_03 | BIT_MASK_19)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_17))) { + DMA2_Error3_IrqHandler(); + } + } + /* EFM program/erase Error */ + if (1UL == bCM_EFM->FITE_b.PEERRITE) { + if ((0UL != (CM_EFM->FSR & 0x0FU)) && (0UL != (VSSEL129 & BIT_MASK_18))) { + EFM_ProgramEraseError_IrqHandler(); + } + } + /* EFM read collision error*/ + if (1UL == bCM_EFM->FITE_b.COLERRITE) { + /* EFM read collision */ + if ((1UL == bCM_EFM->FSR_b.COLERR) && (0UL != (VSSEL129 & BIT_MASK_19))) { + EFM_ColError_IrqHandler(); + } + } + /* EFM operate end */ + if (1UL == bCM_EFM->FITE_b.OPTENDITE) { + /* EFM operate end */ + if ((1UL == bCM_EFM->FSR_b.OPTEND) && (0UL != (VSSEL129 & BIT_MASK_20))) { + EFM_OpEnd_IrqHandler(); + } + } + /* QSPI access error */ + if ((0UL != (CM_QSPI->SR & QSPI_SR_RAER)) && (0UL != (VSSEL129 & BIT_MASK_22))) { + QSPI_Error_IrqHandler(); + } + /*DCU1 */ + u32Tmp1 = CM_DCU1->INTSEL; + u32Tmp2 = CM_DCU1->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x7FUL)) && (0UL != (VSSEL129 & BIT_MASK_23))) { + DCU1_IrqHandler(); + } + /*DCU2 */ + u32Tmp1 = CM_DCU2->INTSEL; + u32Tmp2 = CM_DCU2->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x7FUL)) && (0UL != (VSSEL129 & BIT_MASK_24))) { + DCU2_IrqHandler(); + } + /*DCU3 */ + u32Tmp1 = CM_DCU3->INTSEL; + u32Tmp2 = CM_DCU3->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x7FUL)) && (0UL != (VSSEL129 & BIT_MASK_25))) { + DCU3_IrqHandler(); + } + /*DCU4 */ + u32Tmp1 = CM_DCU4->INTSEL; + u32Tmp2 = CM_DCU4->FLAG; + if ((0UL != (u32Tmp1 & u32Tmp2 & 0x7FUL)) && (0UL != (VSSEL129 & BIT_MASK_26))) { + DCU4_IrqHandler(); + } +} + +/** + * @brief Interrupt No.130 share IRQ handler + * @param None + * @retval None + */ +void IRQ130_Handler(void) +{ + const uint32_t VSSEL130 = CM_INTC->VSSEL130; + /* Timer0 Ch. 1 A compare match */ + if (1UL == bCM_TMR0_1->BCONR_b.INTENA) { + if ((1UL == bCM_TMR0_1->STFLR_b.CMFA) && (0UL != (VSSEL130 & BIT_MASK_00))) { + TMR0_1_CmpA_IrqHandler(); + } + } + /* Timer0 Ch. 1 B compare match */ + if (1UL == bCM_TMR0_1->BCONR_b.INTENB) { + if ((1UL == bCM_TMR0_1->STFLR_b.CMFB) && (0UL != (VSSEL130 & BIT_MASK_01))) { + TMR0_1_CmpB_IrqHandler(); + } + } + /* Timer0 Ch. 2 A compare match */ + if (1UL == bCM_TMR0_2->BCONR_b.INTENA) { + if ((1UL == bCM_TMR0_2->STFLR_b.CMFA) && (0UL != (VSSEL130 & BIT_MASK_02))) { + TMR0_2_CmpA_IrqHandler(); + } + } + /* Timer0 Ch. 2 B compare match */ + if (1UL == bCM_TMR0_2->BCONR_b.INTENB) { + if ((1UL == bCM_TMR0_2->STFLR_b.CMFB) && (0UL != (VSSEL130 & BIT_MASK_03))) { + TMR0_2_CmpB_IrqHandler(); + } + } + /* Main-OSC stop */ + if (CMU_XTALSTDCR_XTALSTDIE == READ_REG8_BIT(CM_CMU->XTALSTDCR, CMU_XTALSTDCR_XTALSTDIE)) { + if ((CMU_XTALSTDSR_XTALSTDF == READ_REG8_BIT(CM_CMU->XTALSTDSR, CMU_XTALSTDSR_XTALSTDF)) && \ + (0UL != (VSSEL130 & BIT_MASK_21))) { + CLK_XtalStop_IrqHandler(); + } + } + /* Wakeup timer */ + if ((PWC_WKTCR_WKOVF == READ_REG16_BIT(CM_PWC->WKTCR, PWC_WKTCR_WKOVF)) && (0UL != (VSSEL130 & BIT_MASK_22))) { + PWC_WakeupTimer_IrqHandler(); + } + /* SWDT */ + if ((0UL != (CM_SWDT->SR & (BIT_MASK_16 | BIT_MASK_17))) && (0UL != (VSSEL130 & BIT_MASK_23))) { + SWDT_IrqHandler(); + } +} + +/** + * @brief Interrupt No.131 share IRQ handler + * @param None + * @retval None + */ +void IRQ131_Handler(void) +{ + const uint32_t VSSEL131 = CM_INTC->VSSEL131; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + /* Timer6 Ch.1 A compare match */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENA) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMAF) && (0UL != (VSSEL131 & BIT_MASK_00))) { + TMR6_1_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.1 B compare match */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENB) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMBF) && (0UL != (VSSEL131 & BIT_MASK_01))) { + TMR6_1_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.1 C compare match */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENC) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMCF) && (0UL != (VSSEL131 & BIT_MASK_02))) { + TMR6_1_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.1 D compare match */ + if (1UL == bCM_TMR6_1->ICONR_b.INTEND) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMDF) && (0UL != (VSSEL131 & BIT_MASK_03))) { + TMR6_1_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.1 E compare match */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENE) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMEF) && (0UL != (VSSEL131 & BIT_MASK_04))) { + TMR6_1_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.1 F compare match */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENF) { + if ((1UL == bCM_TMR6_1->STFLR_b.CMFF) && (0UL != (VSSEL131 & BIT_MASK_05))) { + TMR6_1_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.1 overflow */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENOVF) { + if ((1UL == bCM_TMR6_1->STFLR_b.OVFF) && (0UL != (VSSEL131 & BIT_MASK_06))) { + TMR6_1_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.1 underflow */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENUDF) { + if ((1UL == bCM_TMR6_1->STFLR_b.UDFF) && (0UL != (VSSEL131 & BIT_MASK_07))) { + TMR6_1_GUdf_IrqHandler(); + } + } + /* Timer6 Ch.1 dead time */ + if (1UL == bCM_TMR6_1->ICONR_b.INTENDTE) { + if (((1UL == bCM_TMR6_1->STFLR_b.DTEF)) && (0UL != (VSSEL131 & BIT_MASK_08))) { + TMR6_1_GDte_IrqHandler(); + } + } + /* Timer6 Ch.1 A up-down compare match */ + u32Tmp1 = (CM_TMR6_1->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7U; + u32Tmp2 = CM_TMR6_1->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL131 & BIT_MASK_11))) { + TMR6_1_SCmpA_IrqHandler(); + } + /* Timer6 Ch.1 B up-down compare match */ + u32Tmp1 = (CM_TMR6_1->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7U; + u32Tmp2 = CM_TMR6_1->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL131 & BIT_MASK_12))) { + TMR6_1_SCmpB_IrqHandler(); + } + /* Timer6 Ch.2 A compare match */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENA) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMAF) && (0UL != (VSSEL131 & BIT_MASK_16))) { + TMR6_2_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.2 B compare match */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENB) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMBF) && (0UL != (VSSEL131 & BIT_MASK_17))) { + TMR6_2_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.2 C compare match */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENC) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMCF) && (0UL != (VSSEL131 & BIT_MASK_18))) { + TMR6_2_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.2 D compare match */ + if (1UL == bCM_TMR6_2->ICONR_b.INTEND) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMDF) && (0UL != (VSSEL131 & BIT_MASK_19))) { + TMR6_2_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.2 E compare match */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENE) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMEF) && (0UL != (VSSEL131 & BIT_MASK_20))) { + TMR6_2_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.2 F compare match */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENF) { + if ((1UL == bCM_TMR6_2->STFLR_b.CMFF) && (0UL != (VSSEL131 & BIT_MASK_21))) { + TMR6_2_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.2 overflow */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENOVF) { + if ((1UL == bCM_TMR6_2->STFLR_b.OVFF) && (0UL != (VSSEL131 & BIT_MASK_22))) { + TMR6_2_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.2 underflow */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENUDF) { + if ((1UL == bCM_TMR6_2->STFLR_b.UDFF) && (0UL != (VSSEL131 & BIT_MASK_23))) { + TMR6_2_GUdf_IrqHandler(); + } + } + /* Timer6 Ch.2 dead time */ + if (1UL == bCM_TMR6_2->ICONR_b.INTENDTE) { + if ((1UL == bCM_TMR6_2->STFLR_b.DTEF) && (0UL != (VSSEL131 & BIT_MASK_24))) { + TMR6_2_GDte_IrqHandler(); + } + } + /* Timer6 Ch.2 A up-down compare match */ + u32Tmp1 = (CM_TMR6_2->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7U; + u32Tmp2 = CM_TMR6_2->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL131 & BIT_MASK_27))) { + TMR6_2_SCmpA_IrqHandler(); + } + /* Timer6 Ch.2 B up-down compare match */ + u32Tmp1 = (CM_TMR6_2->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7U; + u32Tmp2 = CM_TMR6_2->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL131 & BIT_MASK_28))) { + TMR6_2_SCmpB_IrqHandler(); + } +} + +/** + * @brief Interrupt No.132 share IRQ handler + * @param None + * @retval None + */ +void IRQ132_Handler(void) +{ + const uint32_t VSSEL132 = CM_INTC->VSSEL132; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + /* Timer6 Ch.3 A compare match */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENA) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMAF) && (0UL != (VSSEL132 & BIT_MASK_00))) { + TMR6_3_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.3 B compare match */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENB) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMBF) && (0UL != (VSSEL132 & BIT_MASK_01))) { + TMR6_3_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.3 C compare match */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENC) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMCF) && (0UL != (VSSEL132 & BIT_MASK_02))) { + TMR6_3_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.3 D compare match */ + if (1UL == bCM_TMR6_3->ICONR_b.INTEND) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMDF) && (0UL != (VSSEL132 & BIT_MASK_03))) { + TMR6_3_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.3 E compare match */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENE) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMEF) && (0UL != (VSSEL132 & BIT_MASK_04))) { + TMR6_3_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.3 F compare match */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENF) { + if ((1UL == bCM_TMR6_3->STFLR_b.CMFF) && (0UL != (VSSEL132 & BIT_MASK_05))) { + TMR6_3_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.3 overflow */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENOVF) { + if ((1UL == bCM_TMR6_3->STFLR_b.OVFF) && (0UL != (VSSEL132 & BIT_MASK_06))) { + TMR6_3_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.3 underflow */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENUDF) { + if ((1UL == bCM_TMR6_3->STFLR_b.UDFF) && (0UL != (VSSEL132 & BIT_MASK_07))) { + TMR6_3_GUdf_IrqHandler(); + } + } + /* Timer6 Ch.3 dead time */ + if (1UL == bCM_TMR6_3->ICONR_b.INTENDTE) { + if ((1UL == bCM_TMR6_3->STFLR_b.DTEF) && (0UL != (VSSEL132 & BIT_MASK_08))) { + TMR6_3_GDte_IrqHandler(); + } + } + /* Timer6 Ch.3 A up-down compare match */ + u32Tmp1 = (CM_TMR6_3->ICONR & (BIT_MASK_16 | BIT_MASK_17)) >> 7U; + u32Tmp2 = CM_TMR6_3->STFLR & (BIT_MASK_09 | BIT_MASK_10); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (0UL != (VSSEL132 & BIT_MASK_11)))) { + TMR6_3_SCmpA_IrqHandler(); + } + /* Timer6 Ch.3 B up-down compare match */ + u32Tmp1 = (CM_TMR6_3->ICONR & (BIT_MASK_18 | BIT_MASK_19)) >> 7U; + u32Tmp2 = CM_TMR6_3->STFLR & (BIT_MASK_11 | BIT_MASK_12); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (0UL != (VSSEL132 & BIT_MASK_12)))) { + TMR6_3_SCmpB_IrqHandler(); + } +} + +/** + * @brief Interrupt No.136 share IRQ handler + * @param None + * @retval None + */ +void IRQ136_Handler(void) +{ + uint32_t u32Tmp1; + uint32_t u32Tmp2; + const uint32_t VSSEL136 = CM_INTC->VSSEL136; + + u32Tmp1 = CM_TMRA_1->BCSTR; + /* TimerA Ch.1 overflow */ + if ((0UL != (u32Tmp1 & BIT_MASK_12)) && (0UL != (u32Tmp1 & BIT_MASK_14)) && (0UL != (VSSEL136 & BIT_MASK_00))) { + TMRA_1_Ovf_IrqHandler(); + } + /* TimerA Ch.1 underflow */ + if ((0UL != (u32Tmp1 & BIT_MASK_13)) && (0UL != (u32Tmp1 & BIT_MASK_15)) && (0UL != (VSSEL136 & BIT_MASK_01))) { + TMRA_1_Udf_IrqHandler(); + } + u32Tmp1 = CM_TMRA_1->ICONR; + u32Tmp2 = CM_TMRA_1->STFLR; + /* TimerA Ch.1 compare match */ + if ((0UL != (u32Tmp1 & u32Tmp2 & 0xFFUL)) && (0UL != (0xFFUL & VSSEL136))) { + TMRA_1_Cmp_IrqHandler(); + } + + u32Tmp1 = CM_TMRA_2->BCSTR; + /* TimerA Ch.2 overflow */ + if ((0UL != (u32Tmp1 & BIT_MASK_12)) && (0UL != (u32Tmp1 & BIT_MASK_14)) && (0UL != (VSSEL136 & BIT_MASK_03))) { + TMRA_2_Ovf_IrqHandler(); + } + /* TimerA Ch.2 underflow */ + if ((0UL != (u32Tmp1 & BIT_MASK_13)) && (0UL != (u32Tmp1 & BIT_MASK_15)) && (0UL != (VSSEL136 & BIT_MASK_04))) { + TMRA_2_Udf_IrqHandler(); + } + u32Tmp1 = CM_TMRA_2->ICONR; + u32Tmp2 = CM_TMRA_2->STFLR; + /* TimerA Ch.2 compare match */ + if ((0UL != (u32Tmp1 & u32Tmp2 & 0xFFUL)) && (0UL != (0xFFUL & VSSEL136))) { + TMRA_2_Cmp_IrqHandler(); + } + + u32Tmp1 = CM_TMRA_3->BCSTR; + /* TimerA Ch.3 overflow */ + if ((0UL != (u32Tmp1 & BIT_MASK_12)) && (0UL != (u32Tmp1 & BIT_MASK_14)) && (0UL != (VSSEL136 & BIT_MASK_06))) { + TMRA_3_Ovf_IrqHandler(); + } + /* TimerA Ch.3 underflow */ + if ((0UL != (u32Tmp1 & BIT_MASK_13)) && (0UL != (u32Tmp1 & BIT_MASK_15)) && (0UL != (VSSEL136 & BIT_MASK_07))) { + TMRA_3_Udf_IrqHandler(); + } + u32Tmp1 = CM_TMRA_3->ICONR; + u32Tmp2 = CM_TMRA_3->STFLR; + /* TimerA Ch.3 compare match */ + if ((0UL != (u32Tmp1 & u32Tmp2 & 0xFFUL)) && (0UL != (0xFFUL & VSSEL136))) { + TMRA_3_Cmp_IrqHandler(); + } + + u32Tmp1 = CM_TMRA_4->BCSTR; + /* TimerA Ch.4 overflow */ + if ((0UL != (u32Tmp1 & BIT_MASK_12)) && (0UL != (u32Tmp1 & BIT_MASK_14)) && (0UL != (VSSEL136 & BIT_MASK_09))) { + TMRA_4_Ovf_IrqHandler(); + } + /* TimerA Ch.4 underflow */ + if ((0UL != (u32Tmp1 & BIT_MASK_13)) && (0UL != (u32Tmp1 & BIT_MASK_15)) && (0UL != (VSSEL136 & BIT_MASK_10))) { + TMRA_4_Udf_IrqHandler(); + } + u32Tmp1 = CM_TMRA_4->ICONR; + u32Tmp2 = CM_TMRA_4->STFLR; + /* TimerA Ch.4 compare match */ + if ((0UL != (u32Tmp1 & u32Tmp2 & 0xFFUL)) && (0UL != (0xFFUL & VSSEL136))) { + TMRA_4_Cmp_IrqHandler(); + } + + u32Tmp1 = CM_TMRA_5->BCSTR; + /* TimerA Ch.5 overflow */ + if ((0UL != (u32Tmp1 & BIT_MASK_12)) && (0UL != (u32Tmp1 & BIT_MASK_14)) && (0UL != (VSSEL136 & BIT_MASK_12))) { + TMRA_5_Ovf_IrqHandler(); + } + /* TimerA Ch.5 underflow */ + if ((0UL != (u32Tmp1 & BIT_MASK_13)) && (0UL != (u32Tmp1 & BIT_MASK_15)) && (0UL != (VSSEL136 & BIT_MASK_13))) { + TMRA_5_Udf_IrqHandler(); + } + u32Tmp1 = CM_TMRA_5->ICONR; + u32Tmp2 = CM_TMRA_5->STFLR; + /* TimerA Ch.5 compare match */ + if ((0UL != (u32Tmp1 & u32Tmp2 & 0xFFUL)) && (0UL != (0xFFUL & VSSEL136))) { + TMRA_5_Cmp_IrqHandler(); + } + + u32Tmp1 = CM_TMRA_6->BCSTR; + /* TimerA Ch.6 overflow */ + if ((0UL != (u32Tmp1 & BIT_MASK_12)) && (0UL != (u32Tmp1 & BIT_MASK_14)) && (0UL != (VSSEL136 & BIT_MASK_16))) { + TMRA_6_Ovf_IrqHandler(); + } + /* TimerA Ch.6 underflow */ + if ((0UL != (u32Tmp1 & BIT_MASK_13)) && (0UL != (u32Tmp1 & BIT_MASK_15)) && (0UL != (VSSEL136 & BIT_MASK_17))) { + TMRA_6_Udf_IrqHandler(); + } + u32Tmp1 = CM_TMRA_6->ICONR; + u32Tmp2 = CM_TMRA_6->STFLR; + /* TimerA Ch.6 compare match */ + if ((0UL != (u32Tmp1 & u32Tmp2 & 0xFFUL)) && (0UL != (0xFFUL & VSSEL136))) { + TMRA_6_Cmp_IrqHandler(); + } + /* USBFS global interrupt */ + if (1UL == bCM_USBFS->GAHBCFG_b.GINTMSK) { + u32Tmp1 = CM_USBFS->GINTMSK & 0xF77CFCFBUL; + u32Tmp2 = CM_USBFS->GINTSTS & 0xF77CFCFBUL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL136 & BIT_MASK_19))) { + USBFS_Global_IrqHandler(); + } + } + + u32Tmp1 = CM_USART1->SR; + u32Tmp2 = CM_USART1->CR1; + /* USART Ch.1 Receive error */ + if ((0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03))) && \ + (0UL != (VSSEL136 & BIT_MASK_22))) { + USART1_RxError_IrqHandler(); + } + /* USART Ch.1 Receive completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_05)) && (0UL != (BIT_MASK_05 & VSSEL136))) { + USART1_RxFull_IrqHandler(); + } + /* USART Ch.1 Transmit data empty */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_07)) && (0UL != (BIT_MASK_07 & VSSEL136))) { + USART1_TxEmpty_IrqHandler(); + } + /* USART Ch.1 Transmit completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_06)) && (0UL != (BIT_MASK_06 & VSSEL136))) { + USART1_TxComplete_IrqHandler(); + } + /* USART Ch.1 Receive timeout */ + if ((0UL != (u32Tmp2 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_08)) && (0UL != (VSSEL136 & BIT_MASK_26))) { + USART1_RxTO_IrqHandler(); + } + + u32Tmp1 = CM_USART2->SR; + u32Tmp2 = CM_USART2->CR1; + /* USART Ch.2 Receive error */ + if ((0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03))) && \ + (0UL != (VSSEL136 & BIT_MASK_27))) { + USART2_RxError_IrqHandler(); + } + /* USART Ch.2 Receive completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_05)) && (0UL != (BIT_MASK_05 & VSSEL136))) { + USART2_RxFull_IrqHandler(); + } + /* USART Ch.2 Transmit data empty */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_07)) && (0UL != (BIT_MASK_07 & VSSEL136))) { + USART2_TxEmpty_IrqHandler(); + } + /* USART Ch.2 Transmit completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_06)) && (0UL != (BIT_MASK_06 & VSSEL136))) { + USART2_TxComplete_IrqHandler(); + } + /* USART Ch.2 Receive timeout */ + if ((0UL != (u32Tmp2 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_08)) && (0UL != (VSSEL136 & BIT_MASK_31))) { + USART2_RxTO_IrqHandler(); + } +} + +/** + * @brief Interrupt No.137 share IRQ handler + * @param None + * @retval None + */ +void IRQ137_Handler(void) +{ + uint32_t u32Tmp1; + uint32_t u32Tmp2; + const uint32_t VSSEL137 = CM_INTC->VSSEL137; + + u32Tmp1 = CM_USART3->SR; + u32Tmp2 = CM_USART3->CR1; + /* USART Ch.3 Receive error */ + if ((0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03))) && \ + (0UL != (VSSEL137 & BIT_MASK_00))) { + USART3_RxError_IrqHandler(); + } + /* USART Ch.3 Receive completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_05)) && (0UL != (BIT_MASK_05 & VSSEL137))) { + USART3_RxFull_IrqHandler(); + } + /* USART Ch.3 Transmit data empty */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_07)) && (0UL != (BIT_MASK_07 & VSSEL137))) { + USART3_TxEmpty_IrqHandler(); + } + /* USART Ch.3 Transmit completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_06)) && (0UL != (BIT_MASK_06 & VSSEL137))) { + USART3_TxComplete_IrqHandler(); + } + /* USART Ch.3 Receive timeout */ + if ((0UL != (u32Tmp2 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_08)) && (0UL != (VSSEL137 & BIT_MASK_04))) { + USART3_RxTO_IrqHandler(); + } + + u32Tmp1 = CM_USART4->SR; + u32Tmp2 = CM_USART4->CR1; + /* USART Ch.4 Receive error */ + if ((0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (u32Tmp1 & (BIT_MASK_00 | BIT_MASK_01 | BIT_MASK_03))) && \ + (0UL != (VSSEL137 & BIT_MASK_05))) { + USART4_RxError_IrqHandler(); + } + /* USART Ch.4 Receive completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_05)) && (0UL != (BIT_MASK_05 & VSSEL137))) { + USART4_RxFull_IrqHandler(); + } + /* USART Ch.4 Transmit data empty */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_07)) && (0UL != (BIT_MASK_07 & VSSEL137))) { + USART4_TxEmpty_IrqHandler(); + } + /* USART Ch.4 Transmit completed */ + if ((0UL != (u32Tmp2 & u32Tmp1 & BIT_MASK_06)) && (0UL != (BIT_MASK_06 & VSSEL137))) { + USART4_TxComplete_IrqHandler(); + } + /* USART Ch.4 Receive timeout */ + if ((0UL != (u32Tmp2 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_08)) && (0UL != (VSSEL137 & BIT_MASK_09))) { + USART4_RxTO_IrqHandler(); + } + + u32Tmp1 = CM_SPI1->CR1; + u32Tmp2 = CM_SPI1->SR; + /* SPI Ch.1 Receive completed */ + if ((0UL != (u32Tmp1 & BIT_MASK_10)) && (0UL != (u32Tmp2 & BIT_MASK_07)) && (0UL != (VSSEL137 & BIT_MASK_11))) { + SPI1_RxFull_IrqHandler(); + } + /* SPI Ch.1 Transmit buf empty */ + if ((0UL != (u32Tmp1 & BIT_MASK_09)) && (0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (VSSEL137 & BIT_MASK_12))) { + SPI1_TxEmpty_IrqHandler(); + } + /* SPI Ch.1 bus idle */ + if ((0UL != (u32Tmp1 & BIT_MASK_11)) && (0UL == (u32Tmp2 & BIT_MASK_01)) && (0UL != (VSSEL137 & BIT_MASK_13))) { + SPI1_Idle_IrqHandler(); + } + /* SPI Ch.1 parity/overflow/underflow/mode error */ + if ((0UL != (u32Tmp1 & BIT_MASK_08)) && \ + (0UL != ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04)))) && \ + (0UL != (VSSEL137 & BIT_MASK_14))) { + SPI1_Error_IrqHandler(); + } + + u32Tmp1 = CM_SPI2->CR1; + u32Tmp2 = CM_SPI2->SR; + /* SPI Ch.2 Receive completed */ + if ((0UL != (u32Tmp1 & BIT_MASK_10)) && (0UL != (u32Tmp2 & BIT_MASK_07)) && (0UL != (VSSEL137 & BIT_MASK_16))) { + SPI2_RxFull_IrqHandler(); + } + /* SPI Ch.2 Transmit buf empty */ + if ((0UL != (u32Tmp1 & BIT_MASK_09)) && (0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (VSSEL137 & BIT_MASK_17))) { + SPI2_TxEmpty_IrqHandler(); + } + /* SPI Ch.2 bus idle */ + if ((0UL != (u32Tmp1 & BIT_MASK_11)) && (0UL == (u32Tmp2 & BIT_MASK_01)) && (0UL != (VSSEL137 & BIT_MASK_18))) { + SPI2_Idle_IrqHandler(); + } + /* SPI Ch.2 parity/overflow/underflow/mode error */ + if ((0UL != (u32Tmp1 & BIT_MASK_08)) && \ + (0UL != ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04)))) && \ + (0UL != (VSSEL137 & BIT_MASK_19))) { + SPI2_Error_IrqHandler(); + } + + u32Tmp1 = CM_SPI3->CR1; + u32Tmp2 = CM_SPI3->SR; + /* SPI Ch.3 Receive completed */ + if ((0UL != (u32Tmp1 & BIT_MASK_10)) && (0UL != (u32Tmp2 & BIT_MASK_07)) && (0UL != (VSSEL137 & BIT_MASK_21))) { + SPI3_RxFull_IrqHandler(); + } + /* SPI Ch.3 Transmit buf empty */ + if ((0UL != (u32Tmp1 & BIT_MASK_09)) && (0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (VSSEL137 & BIT_MASK_22))) { + SPI3_TxEmpty_IrqHandler(); + } + /* SPI Ch.3 bus idle */ + if ((0UL != (u32Tmp1 & BIT_MASK_11)) && (0UL == (u32Tmp2 & BIT_MASK_01)) && (0UL != (VSSEL137 & BIT_MASK_23))) { + SPI3_Idle_IrqHandler(); + } + /* SPI Ch.3 parity/overflow/underflow/mode error */ + if ((0UL != (u32Tmp1 & BIT_MASK_08)) && \ + (0UL != ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04)))) && \ + (0UL != (VSSEL137 & BIT_MASK_24))) { + SPI3_Error_IrqHandler(); + } + + u32Tmp1 = CM_SPI4->CR1; + u32Tmp2 = CM_SPI4->SR; + /* SPI Ch.4 Receive completed */ + if ((0UL != (u32Tmp1 & BIT_MASK_10)) && (0UL != (u32Tmp2 & BIT_MASK_07)) && (0UL != (VSSEL137 & BIT_MASK_26))) { + SPI4_RxFull_IrqHandler(); + } + /* SPI Ch.4 Transmit buf empty */ + if ((0UL != (u32Tmp1 & BIT_MASK_09)) && (0UL != (u32Tmp2 & BIT_MASK_05)) && (0UL != (VSSEL137 & BIT_MASK_27))) { + SPI4_TxEmpty_IrqHandler(); + } + /* SPI Ch.4 bus idle */ + if ((0UL != (u32Tmp1 & BIT_MASK_11)) && (0UL == (u32Tmp2 & BIT_MASK_01)) && (0UL != (VSSEL137 & BIT_MASK_28))) { + SPI4_Idle_IrqHandler(); + } + /* SPI Ch.4 parity/overflow/underflow/mode error */ + if ((0UL != (u32Tmp1 & BIT_MASK_08)) && \ + (0UL != ((u32Tmp2 & (BIT_MASK_00 | BIT_MASK_02 | BIT_MASK_03 | BIT_MASK_04)))) && \ + (0UL != (VSSEL137 & BIT_MASK_29))) { + SPI4_Error_IrqHandler(); + } +} + +/** + * @brief Interrupt No.138 share IRQ handler + * @param None + * @retval None + */ +void IRQ138_Handler(void) +{ + const uint32_t VSSEL138 = CM_INTC->VSSEL138; + uint32_t u32Tmp1; + + u32Tmp1 = CM_TMR4_1->OCSRU; + /* Timer4 Ch.1 U phase higher compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_00)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_1_GCmpUH_IrqHandler(); + } + /* Timer4 Ch.1 U phase lower compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_1_GCmpUL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_1->OCSRV; + /* Timer4 Ch.1 V phase higher compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_02)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_1_GCmpVH_IrqHandler(); + } + /* Timer4 Ch.1 V phase lower compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_03)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_1_GCmpVL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_1->OCSRW; + /* Timer4 Ch.1 W phase higher compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_1_GCmpWH_IrqHandler(); + } + /* Timer4 Ch.1 W phase lower compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_1_GCmpWL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_1->CCSR; + /* Timer4 Ch.1 overflow */ + if ((0UL != (VSSEL138 & BIT_MASK_06)) && (0UL != (u32Tmp1 & BIT_MASK_08)) && (0UL != (u32Tmp1 & BIT_MASK_09))) { + TMR4_1_GOvf_IrqHandler(); + } + /* Timer4 Ch.1 underflow */ + if ((0UL != (VSSEL138 & BIT_MASK_07)) && (0UL != (u32Tmp1 & BIT_MASK_13)) && (0UL != (u32Tmp1 & BIT_MASK_14))) { + TMR4_1_GUdf_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_1->RCSR; + /* Timer4 Ch.1 U phase reload */ + if ((0UL != (VSSEL138 & BIT_MASK_08)) && (0UL == (u32Tmp1 & BIT_MASK_00)) && (0UL != (u32Tmp1 & BIT_MASK_04))) { + TMR4_1_ReloadU_IrqHandler(); + } + /* Timer4 Ch.1 V phase reload */ + if ((0UL != (VSSEL138 & BIT_MASK_09)) && (0UL == (u32Tmp1 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_08))) { + TMR4_1_ReloadV_IrqHandler(); + } + /* Timer4 Ch.1 W phase reload */ + if ((0UL != (VSSEL138 & BIT_MASK_10)) && (0UL == (u32Tmp1 & BIT_MASK_02)) && (0UL != (u32Tmp1 & BIT_MASK_12))) { + TMR4_1_ReloadW_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_2->OCSRU; + /* Timer4 Ch.2 U phase higher compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_16)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_1_GCmpUH_IrqHandler(); + } + /* Timer4 Ch.2 U phase lower compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_17)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_1_GCmpUL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_2->OCSRV; + /* Timer4 Ch.2 V phase higher compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_18)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_2_GCmpVH_IrqHandler(); + } + /* Timer4 Ch.2 V phase lower compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_19)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_2_GCmpVL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_2->OCSRW; + /* Timer4 Ch.2 W phase higher compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_20)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_2_GCmpWH_IrqHandler(); + } + /* Timer4 Ch.2 W phase lower compare match */ + if ((0UL != (VSSEL138 & BIT_MASK_21)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_2_GCmpWL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_2->CCSR; + /* Timer4 Ch.2 overflow */ + if ((0UL != (VSSEL138 & BIT_MASK_22)) && (0UL != (u32Tmp1 & BIT_MASK_08)) && (0UL != (u32Tmp1 & BIT_MASK_09))) { + TMR4_2_GOvf_IrqHandler(); + } + /* Timer4 Ch.2 underflow */ + if ((0UL != (VSSEL138 & BIT_MASK_23)) && (0UL != (u32Tmp1 & BIT_MASK_13)) && (0UL != (u32Tmp1 & BIT_MASK_14))) { + TMR4_2_GUdf_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_2->RCSR; + /* Timer4 Ch.2 U phase reload */ + if ((0UL != (VSSEL138 & BIT_MASK_24)) && (0UL == (u32Tmp1 & BIT_MASK_00)) && (0UL != (u32Tmp1 & BIT_MASK_04))) { + TMR4_2_ReloadU_IrqHandler(); + } + /* Timer4 Ch.2 V phase reload */ + if ((0UL != (VSSEL138 & BIT_MASK_25)) && (0UL == (u32Tmp1 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_08))) { + TMR4_2_ReloadV_IrqHandler(); + } + /* Timer4 Ch.2 W phase reload */ + if ((0UL != (VSSEL138 & BIT_MASK_26)) && (0UL == (u32Tmp1 & BIT_MASK_02)) && (0UL != (u32Tmp1 & BIT_MASK_12))) { + TMR4_2_ReloadW_IrqHandler(); + } +} + +/** + * @brief Interrupt No.139 share IRQ handler + * @param None + * @retval None + */ +void IRQ139_Handler(void) +{ + uint32_t u32Tmp1; + const uint32_t VSSEL139 = CM_INTC->VSSEL139; + + u32Tmp1 = CM_TMR4_3->OCSRU; + /* Timer4 Ch.3 U phase higher compare match */ + if ((0UL != (VSSEL139 & BIT_MASK_00)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_3_GCmpUH_IrqHandler(); + } + /* Timer4 Ch.3 U phase lower compare match */ + if ((0UL != (VSSEL139 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_3_GCmpUL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_3->OCSRV; + /* Timer4 Ch.3 V phase higher compare match */ + if ((0UL != (VSSEL139 & BIT_MASK_02)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_3_GCmpVH_IrqHandler(); + } + /* Timer4 Ch.3 V phase lower compare match */ + if ((0UL != (VSSEL139 & BIT_MASK_03)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_3_GCmpVL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_3->OCSRW; + /* Timer4 Ch.3 W phase higher compare match */ + if ((0UL != (VSSEL139 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_04)) && (0UL != (u32Tmp1 & BIT_MASK_06))) { + TMR4_3_GCmpWH_IrqHandler(); + } + /* Timer4 Ch.3 W phase lower compare match */ + if ((0UL != (VSSEL139 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_05)) && (0UL != (u32Tmp1 & BIT_MASK_07))) { + TMR4_3_GCmpWL_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_3->CCSR; + /* Timer4 Ch.3 overflow */ + if ((0UL != (VSSEL139 & BIT_MASK_06)) && (0UL != (u32Tmp1 & BIT_MASK_08)) && (0UL != (u32Tmp1 & BIT_MASK_09))) { + TMR4_3_GOvf_IrqHandler(); + } + /* Timer4 Ch.3 underflow */ + if ((0UL != (VSSEL139 & BIT_MASK_07)) && (0UL != (u32Tmp1 & BIT_MASK_13)) && (0UL != (u32Tmp1 & BIT_MASK_14))) { + TMR4_3_GUdf_IrqHandler(); + } + + u32Tmp1 = CM_TMR4_3->RCSR; + /* Timer4 Ch.3 U phase reload */ + if ((0UL != (VSSEL139 & BIT_MASK_08)) && (0UL == (u32Tmp1 & BIT_MASK_00)) && (0UL != (u32Tmp1 & BIT_MASK_04))) { + TMR4_1_ReloadU_IrqHandler(); + } + /* Timer4 Ch.3 V phase reload */ + if ((0UL != (VSSEL139 & BIT_MASK_09)) && (0UL == (u32Tmp1 & BIT_MASK_01)) && (0UL != (u32Tmp1 & BIT_MASK_08))) { + TMR4_3_ReloadV_IrqHandler(); + } + /* Timer4 Ch.3 W phase reload */ + if ((0UL != (VSSEL139 & BIT_MASK_10)) && (0UL == (u32Tmp1 & BIT_MASK_02)) && (0UL != (u32Tmp1 & BIT_MASK_12))) { + TMR4_3_ReloadW_IrqHandler(); + } +} + +/** + * @brief Interrupt No.140 share IRQ handler + * @param None + * @retval None + */ +void IRQ140_Handler(void) +{ + const uint32_t VSSEL140 = CM_INTC->VSSEL140; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + /* EMB0 */ + u32Tmp1 = CM_EMB0->STAT & 0x0000000FUL; + u32Tmp2 = CM_EMB0->INTEN & 0x0000000FUL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL140 & BIT_MASK_06))) { + EMB_GR0_IrqHandler(); + } + /* EMB1 */ + u32Tmp1 = CM_EMB1->STAT & 0x0000000FUL; + u32Tmp2 = CM_EMB1->INTEN & 0x0000000FUL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL140 & BIT_MASK_07))) { + EMB_GR1_IrqHandler(); + } + /* EMB2 */ + u32Tmp1 = CM_EMB2->STAT & 0x0000000FUL; + u32Tmp2 = CM_EMB2->INTEN & 0x0000000FUL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL140 & BIT_MASK_08))) { + EMB_GR2_IrqHandler(); + } + /* EMB3 */ + u32Tmp1 = CM_EMB3->STAT & 0x0000000FUL; + u32Tmp2 = CM_EMB3->INTEN & 0x0000000FUL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL140 & BIT_MASK_09))) { + EMB_GR3_IrqHandler(); + } + + /* I2S Ch.1 Transmit */ + if (1UL == bCM_I2S1->CTRL_b.TXIE) { + if ((1UL == bCM_I2S1->SR_b.TXBA) && (0UL != (VSSEL140 & BIT_MASK_16))) { + I2S1_Tx_IrqHandler(); + } + } + /* I2S Ch.1 Receive */ + if (1UL == bCM_I2S1->CTRL_b.RXIE) { + if ((1UL == bCM_I2S1->SR_b.RXBA) && (0UL != (VSSEL140 & BIT_MASK_17))) { + I2S1_Rx_IrqHandler(); + } + } + /* I2S Ch.1 Error */ + if (1UL == bCM_I2S1->CTRL_b.EIE) { + if (0UL != ((CM_I2S1->ER & (BIT_MASK_00 | BIT_MASK_01))) && (0UL != (VSSEL140 & BIT_MASK_18))) { + I2S1_Error_IrqHandler(); + } + } + /* I2S Ch.2 Transmit */ + if (1UL == bCM_I2S2->CTRL_b.TXIE) { + if ((1UL == bCM_I2S2->SR_b.TXBA) && (0UL != (VSSEL140 & BIT_MASK_19))) { + I2S2_Tx_IrqHandler(); + } + } + /* I2S Ch.2 Receive */ + if (1UL == bCM_I2S2->CTRL_b.RXIE) { + if ((1UL == bCM_I2S2->SR_b.RXBA) && (0UL != (VSSEL140 & BIT_MASK_20))) { + I2S2_Rx_IrqHandler(); + } + } + /* I2S Ch.2 Error */ + if (1UL == bCM_I2S2->CTRL_b.EIE) { + if (0UL != ((CM_I2S2->ER & (BIT_MASK_00 | BIT_MASK_01))) && (0UL != (VSSEL140 & BIT_MASK_21))) { + I2S2_Error_IrqHandler(); + } + } + /* I2S Ch.3 Transmit */ + if (1UL == bCM_I2S3->CTRL_b.TXIE) { + if ((1UL == bCM_I2S3->SR_b.TXBA) && (0UL != (VSSEL140 & BIT_MASK_22))) { + I2S3_Tx_IrqHandler(); + } + } + /* I2S Ch.3 Receive */ + if (1UL == bCM_I2S3->CTRL_b.RXIE) { + if ((1UL == bCM_I2S3->SR_b.RXBA) && (0UL != (VSSEL140 & BIT_MASK_23))) { + I2S3_Rx_IrqHandler(); + } + } + /* I2S Ch.3 Error */ + if (1UL == bCM_I2S3->CTRL_b.EIE) { + if (0UL != ((CM_I2S3->ER & (BIT_MASK_00 | BIT_MASK_01))) && (0UL != (VSSEL140 & BIT_MASK_24))) { + I2S3_Error_IrqHandler(); + } + } + /* I2S Ch.4 Transmit */ + if (1UL == bCM_I2S4->CTRL_b.TXIE) { + if ((1UL == bCM_I2S4->SR_b.TXBA) && (0UL != (VSSEL140 & BIT_MASK_25))) { + I2S4_Tx_IrqHandler(); + } + } + /* I2S Ch.4 Receive */ + if (1UL == bCM_I2S4->CTRL_b.RXIE) { + if ((1UL == bCM_I2S4->SR_b.RXBA) && (0UL != (VSSEL140 & BIT_MASK_26))) { + I2S4_Rx_IrqHandler(); + } + } + /* I2S Ch.4 Error */ + if (1UL == bCM_I2S4->CTRL_b.EIE) { + if (0UL != ((CM_I2S4->ER & (BIT_MASK_00 | BIT_MASK_01))) && (0UL != (VSSEL140 & BIT_MASK_27))) { + I2S4_Error_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.141 share IRQ handler + * @param None + * @retval None + */ +void IRQ141_Handler(void) +{ + uint32_t VSSEL141 = CM_INTC->VSSEL141; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + /* I2C Ch.1 Receive completed */ + if (1UL == bCM_I2C1->CR2_b.RFULLIE) { + if ((1UL == bCM_I2C1->SR_b.RFULLF) && (0UL != (VSSEL141 & BIT_MASK_04))) { + I2C1_RxFull_IrqHandler(); + } + } + /* I2C Ch.1 Transmit data empty */ + if (1UL == bCM_I2C1->CR2_b.TEMPTYIE) { + if ((1UL == bCM_I2C1->SR_b.TEMPTYF) && (0UL != (VSSEL141 & BIT_MASK_05))) { + I2C1_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.1 Transmit completed */ + if (1UL == bCM_I2C1->CR2_b.TENDIE) { + if ((1UL == bCM_I2C1->SR_b.TENDF) && (0UL != (VSSEL141 & BIT_MASK_06))) { + I2C1_TxComplete_IrqHandler(); + } + } + /* I2C Ch.1 Error */ + u32Tmp1 = CM_I2C1->CR2 & 0x00F05217UL; + u32Tmp2 = CM_I2C1->SR & 0x00F05217UL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL141 & BIT_MASK_07))) { + I2C1_Error_IrqHandler(); + } + /* I2C Ch.2 Receive completed */ + if (1UL == bCM_I2C2->CR2_b.RFULLIE) { + if ((1UL == bCM_I2C2->SR_b.RFULLF) && (0UL != (VSSEL141 & BIT_MASK_08))) { + I2C2_RxFull_IrqHandler(); + } + } + /* I2C Ch.2 Transmit data empty */ + if (1UL == bCM_I2C2->CR2_b.TEMPTYIE) { + if ((1UL == bCM_I2C2->SR_b.TEMPTYF) && (0UL != (VSSEL141 & BIT_MASK_09))) { + I2C2_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.2 Transmit completed */ + if (1UL == bCM_I2C2->CR2_b.TENDIE) { + if ((1UL == bCM_I2C2->SR_b.TENDF) && (0UL != (VSSEL141 & BIT_MASK_10))) { + I2C2_TxComplete_IrqHandler(); + } + } + /* I2C Ch.2 Error */ + u32Tmp1 = CM_I2C2->CR2 & 0x00F05217UL; + u32Tmp2 = CM_I2C2->SR & 0x00F05217UL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL141 & BIT_MASK_11))) { + I2C2_Error_IrqHandler(); + } + /* I2C Ch.3 Receive completed */ + if (1UL == bCM_I2C3->CR2_b.RFULLIE) { + if ((1UL == bCM_I2C3->SR_b.RFULLF) && (0UL != (VSSEL141 & BIT_MASK_12))) { + I2C3_RxFull_IrqHandler(); + } + } + /* I2C Ch.3 Transmit data empty */ + if (1UL == bCM_I2C3->CR2_b.TEMPTYIE) { + if ((1UL == bCM_I2C3->SR_b.TEMPTYF) && (0UL != (VSSEL141 & BIT_MASK_13))) { + I2C3_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.3 Transmit completed */ + if (1UL == bCM_I2C3->CR2_b.TENDIE) { + if ((1UL == bCM_I2C3->SR_b.TENDF) && (0UL != (VSSEL141 & BIT_MASK_14))) { + I2C3_TxComplete_IrqHandler(); + } + } + /* I2C Ch.3 Error */ + u32Tmp1 = CM_I2C3->CR2 & 0x00F05217UL; + u32Tmp2 = CM_I2C3->SR & 0x00F05217UL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL141 & BIT_MASK_15))) { + I2C3_Error_IrqHandler(); + } + /* LVD Ch.1 detected */ + if (PWC_PVDCR1_PVD1IRE == READ_REG8_BIT(CM_PWC->PVDCR1, PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS)) { + if ((PWC_PVDDSR_PVD1DETFLG == READ_REG8_BIT(CM_PWC->PVDDSR, PWC_PVDDSR_PVD1DETFLG)) && \ + (0UL != (VSSEL141 & BIT_MASK_17))) { + PWC_LVD1_IrqHandler(); + } + } + if (PWC_PVDCR1_PVD2IRE == READ_REG8_BIT(CM_PWC->PVDCR1, PWC_PVDCR1_PVD2IRE | PWC_PVDCR1_PVD2IRS)) { + /* LVD Ch.2 detected */ + if ((PWC_PVDDSR_PVD2DETFLG == READ_REG8_BIT(CM_PWC->PVDDSR, PWC_PVDDSR_PVD2DETFLG)) && \ + (0UL != (VSSEL141 & BIT_MASK_18))) { + PWC_LVD2_IrqHandler(); + } + } + /* Freq. calculate error detected */ + if (1UL == bCM_FCM->RIER_b.ERRIE) { + if ((1UL == bCM_FCM->SR_b.ERRF) && (0UL != (VSSEL141 & BIT_MASK_20))) { + FCM_Error_IrqHandler(); + } + } + /* Freq. calculate completed */ + if (1UL == bCM_FCM->RIER_b.MENDIE) { + if ((1UL == bCM_FCM->SR_b.MENDF) && (0UL != (VSSEL141 & BIT_MASK_21))) { + FCM_End_IrqHandler(); + } + } + /* Freq. calculate overflow */ + if (1UL == bCM_FCM->RIER_b.OVFIE) { + if ((1UL == bCM_FCM->SR_b.OVF) && (0UL != (VSSEL141 & BIT_MASK_22))) { + FCM_Ovf_IrqHandler(); + } + } + + /* WDT */ + if ((0UL != (CM_WDT->SR & (BIT_MASK_16 | BIT_MASK_17))) && (0UL != (VSSEL141 & BIT_MASK_23))) { + WDT_IrqHandler(); + } +} + +/** + * @brief Interrupt No.142 share IRQ handler + * @param None + * @retval None + */ +void IRQ142_Handler(void) +{ + uint32_t u32VSSEL142 = CM_INTC->VSSEL142; + /* ADC unit.1 seq. A */ + if (1UL == bCM_ADC1->ICR_b.EOCAIEN) { + if ((1UL == bCM_ADC1->ISR_b.EOCAF) && (0UL != (u32VSSEL142 & BIT_MASK_00))) { + ADC1_SeqA_IrqHandler(); + } + } + /* ADC unit.1 seq. B */ + if (1UL == bCM_ADC1->ICR_b.EOCBIEN) { + if ((1UL == bCM_ADC1->ISR_b.EOCBF) && (0UL != (u32VSSEL142 & BIT_MASK_01))) { + ADC1_SeqB_IrqHandler(); + } + } + /* ADC unit.1 ADW channel compare */ + if (1UL == bCM_ADC1->AWDCR_b.AWDIEN) { + if ((0UL != (CM_ADC1->AWDSR & 0x1FFFFU)) && (0UL != (u32VSSEL142 & BIT_MASK_02))) { + ADC1_ChCmp_IrqHandler(); + } + } + /* ADC unit.1 AWD Seq. compare */ + if (1UL == bCM_ADC1->AWDCR_b.AWDIEN) { + if ((0UL != (CM_ADC1->AWDSR & 0x1FFFFU)) && (0UL != (u32VSSEL142 & BIT_MASK_03))) { + ADC1_SeqCmp_IrqHandler(); + } + } + + /* ADC unit.2 seq. A */ + if (1UL == bCM_ADC2->ICR_b.EOCAIEN) { + if ((1UL == bCM_ADC2->ISR_b.EOCAF) && (0UL != (u32VSSEL142 & BIT_MASK_04))) { + ADC2_SeqA_IrqHandler(); + } + } + /* ADC unit.2 seq. B */ + if (1UL == bCM_ADC2->ICR_b.EOCBIEN) { + if ((1UL == bCM_ADC2->ISR_b.EOCBF) && (0UL != (u32VSSEL142 & BIT_MASK_05))) { + ADC2_SeqB_IrqHandler(); + } + } + /* ADC unit.2 ADW channel compare */ + if (1UL == bCM_ADC2->AWDCR_b.AWDIEN) { + if ((0UL != (CM_ADC2->AWDSR & 0x1FFU)) && (0UL != (u32VSSEL142 & BIT_MASK_06))) { + ADC2_ChCmp_IrqHandler(); + } + } + /* ADC unit.2 AWD Seq. compare */ + if (1UL == bCM_ADC2->AWDCR_b.AWDIEN) { + if ((0UL != (CM_ADC2->AWDSR & 0x1FFU)) && (0UL != (u32VSSEL142 & BIT_MASK_07))) { + ADC2_SeqCmp_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.143 share IRQ handler + * @param None + * @retval None + */ +void IRQ143_Handler(void) +{ + uint8_t RTIF; + uint8_t RTIE; + uint8_t ERRINT; + uint8_t TTCFG; + uint16_t NORINTST; + uint16_t NORINTSGEN; + uint16_t ERRINTST; + uint16_t ERRINTSGEN; + + /* SDIO Ch.1 */ + if (1UL == bCM_INTC->VSSEL143_b.VSEL2) { + NORINTST = CM_SDIOC1->NORINTST; + NORINTSGEN = CM_SDIOC1->NORINTSGEN; + ERRINTST = CM_SDIOC1->ERRINTST; + ERRINTSGEN = CM_SDIOC1->ERRINTSGEN; + + if ((0U != (NORINTST & NORINTSGEN & 0x01F7U)) || (0U != (ERRINTST & ERRINTSGEN & 0x017FU))) { + SDIOC1_IrqHandler(); + } + } + + /* SDIO Ch.2 */ + if (1UL == bCM_INTC->VSSEL143_b.VSEL5) { + NORINTST = CM_SDIOC2->NORINTST; + NORINTSGEN = CM_SDIOC2->NORINTSGEN; + ERRINTST = CM_SDIOC2->ERRINTST; + ERRINTSGEN = CM_SDIOC2->ERRINTSGEN; + + if ((0U != (NORINTST & NORINTSGEN & 0x01F7U)) || (0U != (ERRINTST & ERRINTSGEN & 0x017FU))) { + SDIOC2_IrqHandler(); + } + } + + /* CAN */ + if (1UL == bCM_INTC->VSSEL143_b.VSEL6) { + RTIF = CM_CAN->RTIF; + RTIE = CM_CAN->RTIE; + ERRINT = CM_CAN->ERRINT; + TTCFG = CM_CAN->TTCFG; + if (((0U != (TTCFG & BIT_MASK_05)) || \ + (0U != (RTIF & BIT_MASK_00)) || \ + (0U != (RTIF & RTIE & 0xFEU)) || \ + ((0U != (ERRINT & BIT_MASK_00)) && (0U != (ERRINT & BIT_MASK_01))) || \ + ((0U != (ERRINT & BIT_MASK_02)) && (0U != (ERRINT & BIT_MASK_03))) || \ + ((0U != (ERRINT & BIT_MASK_04)) && (0U != (ERRINT & BIT_MASK_05))) || \ + ((0U != (TTCFG & BIT_MASK_03)) && (0U != (TTCFG & BIT_MASK_04))) || \ + ((0U != (TTCFG & BIT_MASK_06)) && (0U != (TTCFG & BIT_MASK_07)))) != 0U) { + CAN_IrqHandler(); + } + } +} +/** + * @} + */ + +/** + * @defgroup Share_Interrupts_Weakdef_Prototypes Share Interrupts weak function prototypes + * @{ + */ +__WEAKDEF void EXTINT00_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT01_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT02_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT03_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT04_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT05_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT06_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT07_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT08_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT09_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT10_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT11_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT12_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT13_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT14_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT15_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC0_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC1_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC2_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_TC3_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC0_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC1_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC2_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_TC3_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC0_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC1_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC2_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_BTC3_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC0_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC1_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC2_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_BTC3_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error0_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error1_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error2_IrqHandler(void) +{ +} +__WEAKDEF void DMA1_Error3_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error0_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error1_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error2_IrqHandler(void) +{ +} +__WEAKDEF void DMA2_Error3_IrqHandler(void) +{ +} +__WEAKDEF void EFM_ProgramEraseError_IrqHandler(void) +{ +} +__WEAKDEF void EFM_ColError_IrqHandler(void) +{ +} +__WEAKDEF void EFM_OpEnd_IrqHandler(void) +{ +} +__WEAKDEF void QSPI_Error_IrqHandler(void) +{ +} +__WEAKDEF void DCU1_IrqHandler(void) +{ +} +__WEAKDEF void DCU2_IrqHandler(void) +{ +} +__WEAKDEF void DCU3_IrqHandler(void) +{ +} +__WEAKDEF void DCU4_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_1_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_1_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_2_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_2_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void CLK_XtalStop_IrqHandler(void) +{ +} +__WEAKDEF void PWC_WakeupTimer_IrqHandler(void) +{ +} +__WEAKDEF void SWDT_IrqHandler(void) +{ +} +__WEAKDEF void WDT_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GDte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_SCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_SCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GDte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_SCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_SCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GDte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_SCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_SCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Cmp_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Cmp_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Cmp_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Cmp_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Cmp_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Cmp_IrqHandler(void) +{ +} +__WEAKDEF void USBFS_Global_IrqHandler(void) +{ +} +__WEAKDEF void USART1_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART1_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART1_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART1_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART1_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void USART2_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART2_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART2_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART2_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART2_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void USART3_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART3_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART3_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART3_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART3_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void USART4_RxError_IrqHandler(void) +{ +} +__WEAKDEF void USART4_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void USART4_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART4_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void USART4_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void SPI1_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void SPI1_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI1_Error_IrqHandler(void) +{ +} +__WEAKDEF void SPI1_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI2_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void SPI2_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI2_Error_IrqHandler(void) +{ +} +__WEAKDEF void SPI2_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI3_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void SPI3_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI3_Error_IrqHandler(void) +{ +} +__WEAKDEF void SPI3_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI4_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void SPI4_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI4_Error_IrqHandler(void) +{ +} +__WEAKDEF void SPI4_Idle_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpUH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpUL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpVH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpVL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpWH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpWL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_ReloadU_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_ReloadV_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_ReloadW_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpUH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpUL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpVH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpVL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpWH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpWL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_ReloadU_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_ReloadV_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_ReloadW_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpUH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpUL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpVH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpVL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpWH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpWL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_ReloadU_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_ReloadV_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_ReloadW_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR0_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR1_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR2_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR3_IrqHandler(void) +{ +} +__WEAKDEF void I2S1_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S1_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S1_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2S2_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S2_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S2_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2S3_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S3_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S3_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2S4_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S4_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S4_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2C1_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void I2C1_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void I2C1_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C1_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2C2_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void I2C2_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void I2C2_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C2_Error_IrqHandler(void) +{ +} +__WEAKDEF void I2C3_RxFull_IrqHandler(void) +{ +} +__WEAKDEF void I2C3_TxComplete_IrqHandler(void) +{ +} +__WEAKDEF void I2C3_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C3_Error_IrqHandler(void) +{ +} +__WEAKDEF void PWC_LVD1_IrqHandler(void) +{ +} +__WEAKDEF void PWC_LVD2_IrqHandler(void) +{ +} +__WEAKDEF void FCM_Error_IrqHandler(void) +{ +} +__WEAKDEF void FCM_End_IrqHandler(void) +{ +} +__WEAKDEF void FCM_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void ADC1_SeqA_IrqHandler(void) +{ +} +__WEAKDEF void ADC1_SeqB_IrqHandler(void) +{ +} +__WEAKDEF void ADC1_ChCmp_IrqHandler(void) +{ +} +__WEAKDEF void ADC1_SeqCmp_IrqHandler(void) +{ +} +__WEAKDEF void ADC2_SeqA_IrqHandler(void) +{ +} +__WEAKDEF void ADC2_SeqB_IrqHandler(void) +{ +} +__WEAKDEF void ADC2_ChCmp_IrqHandler(void) +{ +} +__WEAKDEF void ADC2_SeqCmp_IrqHandler(void) +{ +} +__WEAKDEF void SDIOC1_IrqHandler(void) +{ +} +__WEAKDEF void SDIOC2_IrqHandler(void) +{ +} +__WEAKDEF void CAN_IrqHandler(void) +{ +} +/** + * @} + */ + +#endif /* LL_INTERRUPTS_SHARE_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h new file mode 100644 index 0000000000..948134508f --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h @@ -0,0 +1,145 @@ +/** + ******************************************************************************* + * @file stl_common.h + * @brief This file contains STL common definitions: enumeration, macros and + * structures definitions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_COMMON_H__ +#define __STL_COMMON_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup IEC60730_STL + * @{ + */ + +/** + * @addtogroup IEC60730_STL_Common + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup STL_Common_Global_Macros STL Common Global Macros + * @{ + */ + +/** + * @defgroup STL_Generic_Error_Codes STL Generic Error Codes + * @{ + */ +#define STL_OK (0UL) /*!< No error occurs */ +#define STL_ERR (1UL) /*!< Error occurs */ +/** + * @} + */ + +/** + * @defgroup STL_Module_Switch STL Module Switch + * @{ + */ +#define STL_ON (1U) +#define STL_OFF (0U) +/** + * @} + */ + +/** + * @defgroup Compiler_Macros Compiler Macros + * @{ + */ +#ifdef __CC_ARM /*!< ARM Compiler */ +/* CPU will start executing at the program entry label __main when the CPU is reset */ +extern void __main(void); + +/* CC */ +#define STL_SECTION(x) __attribute__((section(x))) +#define STL_UNUSED __attribute__((unused)) +#define STL_USED __attribute__((used)) +#define STL_ALIGN(n) __attribute__((aligned(n))) +#define STL_WEAK __WEAKDEF +#define STL_INLINE static __inline + +#define CallApplicationStartUp( ) __main() + +#elif defined (__ICCARM__) /*!< IAR Compiler */ +/* CPU will start executing at the program entry label __iar_program_start when the CPU is reset */ +extern void __iar_program_start(void); + +/* CC */ +#define STL_SECTION(x) @ x +#define STL_UNUSED +#define STL_USED __root +#define STL_PRAGMA(x) _Pragma(#x) +#define STL_ALIGN(n) STL_PRAGMA(data_alignment=n) +#define STL_WEAK __WEAKDEF +#define STL_INLINE static inline + +#define CallApplicationStartUp( ) __iar_program_start() +#else +#error Unsupported tool chain +#endif +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_COMMON_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h new file mode 100644 index 0000000000..ff08ef50f5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h @@ -0,0 +1,106 @@ +/** + ******************************************************************************* + * @file stl_conf.h + * @brief This file contains STL resource configure. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_CONF_H__ +#define __STL_CONF_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_bsp_conf.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup IEC60730_STL + * @{ + */ + +/** + * @addtogroup IEC60730_STL_Configure + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup IEC60730_STL_Configure_ROM_CRC32_Parameters IEC60730 STL Configure ROM CRC32 Parameters + * @{ + */ +#define STL_ROM_CRC32_START (STL_ROM_START) +#define STL_ROM_CRC32_END ((uint32_t)&__checksum - 1UL) +#define STL_ROM_CRC32_SIZE (STL_ROM_CRC32_END - STL_ROM_CRC32_START + 1UL) +#define STL_ROM_CRC32_BLOCK_SIZE (128UL) +#define STL_ROM_CRC32_CC_CHECKSUM (__checksum) +/** + * @} + */ + +/** + * @defgroup IEC60730_STL_Configure_RAM_Parameters IEC60730 STL Configure RAM Parameters + * @{ + */ +#define STL_MARCH_RAM_SIZE (32UL) +#define STL_MARCH_RAM_WORDS (STL_MARCH_RAM_SIZE >> 2) +#define STL_MARCH_RAM_BUF_SIZE (16UL) +#define STL_MARCH_RAM_BUF_WORDS (STL_MARCH_RAM_BUF_SIZE >> 2) + +#define STL_MARCH_RAM_BCKGRND (0x00000000UL) +#define STL_MARCH_RAM_INVBCKGRND (0xFFFFFFFFUL) + +#define STL_STACK_BOUNDARY_WORDS (4UL) +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h new file mode 100644 index 0000000000..6e5a06539c --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h @@ -0,0 +1,95 @@ +/** + ******************************************************************************* + * @file stl_test_flash.h + * @brief This file contains all the functions prototypes of the flash test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_SW_CRC32_H__ +#define __STL_SW_CRC32_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_CRC32 + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_CRC32_Global_Macros STL IEC60730 CRC32 Global Macros + * @{ + */ +#define STL_CRC32_INIT_VALUE (0xFFFFFFFFUL) +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_CRC32_Global_Functions + * @{ + */ +uint32_t STL_CalculateCRC32Value(uint32_t u32Crc32Value, uint8_t *pu8Data, uint32_t u32Len); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +{ +#endif + + +#endif /* __STL_SW_CRC32_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h new file mode 100644 index 0000000000..0a5bfdd362 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h @@ -0,0 +1,86 @@ +/** + ******************************************************************************* + * @file stl_test_cpu.h + * @brief This file contains all the functions prototypes of the CPU test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_CPU_H__ +#define __STL_TEST_CPU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_CPU + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_CPU_Global_Functions + * @{ + */ +uint32_t STL_CpuTestStartup(void); +uint32_t STL_CpuTestRuntime(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +{ +#endif + + +#endif /* __STL_TEST_CPU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h new file mode 100644 index 0000000000..a13b329f0b --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h @@ -0,0 +1,87 @@ +/** + ******************************************************************************* + * @file stl_test_flash.h + * @brief This file contains all the functions prototypes of the flash test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_FLASH_H__ +#define __STL_TEST_FLASH_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_Flash + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_Flash_Global_Functions + * @{ + */ +uint32_t STL_FlashStartupTest(void); +uint32_t STL_FlashRuntimeTest(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +{ +#endif + + +#endif /* __STL_TEST_FLASH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h new file mode 100644 index 0000000000..a3c6ce396a --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h @@ -0,0 +1,100 @@ +/** + ******************************************************************************* + * @file stl_test_interrupt.h + * @brief This file contains all the functions prototypes of the interrupt test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_INTERRUPT_H__ +#define __STL_TEST_INTERRUPT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_Interrupt + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ +/** + * @defgroup STL_IEC60730_Interrupt_Global_Type STL IEC60730 Interrupt Global Type + * @{ + */ +typedef struct stc_stl_int_params { + uint32_t u32FreqInitVal; + uint32_t u32FreqLowerVal; + uint32_t u32FreqUpperVal; + uint32_t u32PrivateParam; +} stc_stl_int_params_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_Interrupt_Global_Functions + * @{ + */ +uint32_t STL_IntRuntimeTableInit(stc_stl_int_params_t *pstcParamsTable, uint32_t u32TableSize); +uint32_t STL_IntRuntimeTest(void); +void STL_IntUpdateCount(uint8_t u8ParamIndex); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +{ +#endif + + +#endif /* __STL_TEST_INTERRUPT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h new file mode 100644 index 0000000000..834d26d4f1 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h @@ -0,0 +1,85 @@ +/** + ******************************************************************************* + * @file stl_test_pc.h + * @brief This file contains all the functions prototypes of the PC test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_PC_H__ +#define __STL_TEST_PC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_PC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_PC_Global_Functions + * @{ + */ +uint32_t STL_PcTest(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +{ +#endif + + +#endif /* __STL_TEST_PC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h new file mode 100644 index 0000000000..f104dc8b4f --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h @@ -0,0 +1,89 @@ +/** + ******************************************************************************* + * @file stl_test_ram.h + * @brief This file contains all the functions prototypes of the RAM test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_RAM_H__ +#define __STL_TEST_RAM_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_RAM + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_RAM_Global_Functions + * @{ + */ +uint32_t STL_StackRuntimeInit(void); +uint32_t STL_StackRuntimeTest(void); +uint32_t STL_RamRuntimeInit(void); +uint32_t STL_RamRuntimeTest(void); +uint32_t STL_FullRamTestStartup(uint32_t u32StartAddr, uint32_t u32EndAddr); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +{ +#endif + + +#endif /* __STL_TEST_RAM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s new file mode 100644 index 0000000000..199c25c3ff --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s @@ -0,0 +1,245 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for IAR */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + + SECTION constdata:CONST(2) +data0xAAAAAAAA DCD 0xAAAAAAAA +data0x55555555 DCD 0x55555555 + + ; Exported function + EXPORT STL_CpuTestRuntime + +;******************************************************************************* +; Function Name : STL_CpuTestRuntime +; Description : Test CPU at run-time +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + THUMB + SECTION .text:CODE(2) +STL_CpuTestRuntime: + PUSH {R4-R7} ; Save registers + + ; Register R1 + LDR R0, =data0xAAAAAAAA + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_fail + MOVS R1, #0x1 + + ; Register R2 + LDR R0, =data0xAAAAAAAA + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_fail + MOVS R2, #0x2 + + ; Register R3 + LDR R0, =data0xAAAAAAAA + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_fail + MOVS R3, #0x3 + + ; Register R4 + LDR R0, =data0xAAAAAAAA + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_fail + MOVS R4, #0x4 + + ; Register R5 + LDR R0, =data0xAAAAAAAA + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_fail + MOVS R5, #0x5 + + ; Register R6 + LDR R0, =data0xAAAAAAAA + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_fail + MOVS R6, #0x6 + + ; Register R7 + LDR R0, =data0xAAAAAAAA + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_fail + MOVS R7, #0x7 + + ; Register R8 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_fail + MOVS R0, #0x08 + MOV R8, R0 + + BAL _test_cpu_continue + +_test_cpu_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_continue + ; Register R9 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_fail + MOVS R0, #0x09 + MOV R9, R0 + + ; Register R10 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_fail + MOVS R0, #0x0A + MOV R10, R0 + + ; Register R11 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_fail + MOVS R0, #0x0B + MOV R11, R0 + + ; Register R12 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_fail + MOVS R0, #0x0C + MOV R12, R0 + LDR R0, =_test_cpu_continue + + ; pattern verification (R0 is not tested) + CMP R1, #0x01 + BNE _test_cpu_fail + CMP R2, #0x02 + BNE _test_cpu_fail + CMP R3, #0x03 + BNE _test_cpu_fail + CMP R4, #0x04 + BNE _test_cpu_fail + CMP R5, #0x05 + BNE _test_cpu_fail + CMP R6, #0x06 + BNE _test_cpu_fail + CMP R7, #0x07 + BNE _test_cpu_fail + MOVS R0, #0x08 + CMP R0, R8 + BNE _test_cpu_fail + MOVS R0, #0x09 + CMP R0, R9 + BNE _test_cpu_fail + MOVS R0, #0x0A + CMP R0, R10 + BNE _test_cpu_fail + MOVS R0, #0x0B + CMP R0, R11 + BNE _test_cpu_fail + MOVS R0, #0x0C + CMP R0, R12 + BNE _test_cpu_fail + + ; Link register R14 + ; test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK +_test_exit + POP {R4-R7} ; Restore registers + BX LR ; return + + END diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_startup.s b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_startup.s new file mode 100644 index 0000000000..186c49e205 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_startup.s @@ -0,0 +1,357 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for IAR */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + + SECTION constdata:CONST(2) +data0xAAAAAAAA DCD 0xAAAAAAAA +data0x55555555 DCD 0x55555555 +data0x80000000 DCD 0x80000000 +data0xAAAAAAA8 DCD 0xAAAAAAA8 +data0x55555554 DCD 0x55555554 +data0x00000000 DCD 0x00000000 +data0x00000001 DCD 0x00000001 + + ; Exported function + EXPORT STL_CpuTestStartup + +;******************************************************************************* +; Function Name : STL_CpuTestStartup +; Description : Test CPU at start-up +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + THUMB + SECTION .text:CODE(2) +STL_CpuTestStartup: + PUSH {R4-R7} ; Save registers + +_test_cpu_reg0_reg8 + MOVS R0, #0x00 + UXTB R0, R0 + ADDS R0, #0 ; Set Z(ero) Flag + BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + SUBS R0, #1 ; Set N(egative) Flag + BPL _test_cpu_reg0_reg13_fail ; Fails if N clear + ADDS R0, #2 ; Set C(arry) Flag and do not set Z + BCC _test_cpu_reg0_reg13_fail ; Fails if C clear + BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + + LDR R0, =data0x80000000 ; Prepares Overflow test + LDR R0, [R0] + ADDS R0, R0, R0 ; Set V(overflow) Flag + BVC _test_cpu_reg0_reg13_fail ; Fails if V clear + + ; Register R1 + LDR R0, =data0xAAAAAAAA + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + MOVS R1, #0x1 + + ; Register R2 + LDR R0, =data0xAAAAAAAA + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + MOVS R2, #0x2 + + ; Register R3 + LDR R0, =data0xAAAAAAAA + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + MOVS R3, #0x3 + + ; Register R4 + LDR R0, =data0xAAAAAAAA + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + MOVS R4, #0x4 + + ; Register R5 + LDR R0, =data0xAAAAAAAA + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + MOVS R5, #0x5 + + ; Register R6 + LDR R0, =data0xAAAAAAAA + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + MOVS R6, #0x6 + + ; Register R7 + LDR R0, =data0xAAAAAAAA + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + MOVS R7, #0x7 + + ; Register R8 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + MOV R8, R0 + + BAL _test_cpu_continue + +_test_cpu_reg0_reg13_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_continue + ; Register R9 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + MOV R9, R0 + + ; Register R10 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + MOV R10, R0 + + ; Register R11 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + MOV R11, R0 + + ; Register R12 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + MOV R12, R0 + LDR R0, =_test_cpu_continue + + ; pattern verification (R0 is not tested) + CMP R1, #0x01 + BNE _test_cpu_reg0_reg13_fail + CMP R2, #0x02 + BNE _test_cpu_reg0_reg13_fail + CMP R3, #0x03 + BNE _test_cpu_reg0_reg13_fail + CMP R4, #0x04 + BNE _test_cpu_reg0_reg13_fail + CMP R5, #0x05 + BNE _test_cpu_reg0_reg13_fail + CMP R6, #0x06 + BNE _test_cpu_reg0_reg13_fail + CMP R7, #0x07 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + + ; Process Stack pointer (banked Register R13) + MRS R0, PSP ; Save process stack value + LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + MSR PSP, R0 ; Restore process stack value + + ; Stack pointer (Register R13) + MRS R0, MSP ; Save stack pointer value + LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR MSP, R1 ; load SP value + MRS R2, MSP ; Get back SP value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 + LDR R1, [R1] ; load SP value + MSR MSP, R1 ; Get back SP value + MRS R2, MSP ; Verify value + CMP R2, R1 + BNE _test_cpu_reg0_reg13_fail + MSR MSP, R0 ; Restore stack pointer value + +_test_cpu_r14_sfr + ; Link register R14 + MOV R1, LR + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + MOV LR, R1 + + ; PRIMASK register + MRS R1, PRIMASK + LDR R0, =data0x00000000 + LDR R0, [R0] + MSR PRIMASK, R0 + MRS R2, PRIMASK + MOVS R3, #1 + ANDS R2, R3 + CMP R2, #0 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0x00000001 + LDR R0, [R0] + MSR PRIMASK, R0 + MRS R2, PRIMASK + MOVS R3, #1 + ANDS R2, R3 + CMP R2, #1 + BNE _test_cpu_r14_sfr_fail + MSR PRIMASK, R1 + B _test_cpu_pass + +_test_cpu_r14_sfr_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_pass + ; test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK + B _test_exit + +_test_exit + POP {R4-R7} ; Restore registers + BX LR + + END diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s new file mode 100644 index 0000000000..1c9addd769 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s @@ -0,0 +1,186 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for IAR */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + SECTION constdata:CONST(2) +data0x00000000 DCD 0x00000000 +data0xFFFFFFFF DCD 0xFFFFFFFF + + ; Exported function + EXPORT STL_FullRamTestStartup + +;******************************************************************************* +; Function Name : STL_FullRamTestStartup +; Description : Full RAM test at start-up +; Input : R0 .. RAM begin address +; R1 .. RAM end address +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + THUMB + SECTION .text:CODE(2) +STL_FullRamTestStartup: + MOVS R4, #0x0 ; STL_OK:Test success status by default + + LDR R2, =data0x00000000 ; Prepares background pattern + LDR R2, [R2] + LDR R3, =data0xFFFFFFFF ; Prepares inverted background pattern + LDR R3, [R3] + + ; *** Step 1 *** + ; Write background pattern with addresses increasing + MOVS R5, R0 +_step1_loop: + CMP R5, R1 + BHI _step_2 + STR R2, [R5, #+0] + ADDS R5, R5, #+4 + B _step1_loop + + ; *** Step 2 *** + ; Verify background and write inverted background with addresses increasing +_step_2: + MOVS R5, R0 +_step_2_loop: + CMP R5, R1 + BHI _step_3 + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+0] + LDR R6, [R5, #+4] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+4] + + LDR R6, [R5, #+8] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+8] + LDR R6, [R5, #+12] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+12] + + ADDS R5, R5, #+16 + B _step_2_loop + + ; *** Step 3 *** + ; Verify inverted background and write background with addresses increasing +_step_3: + MOVS R5, R0 +_step_3_loop: + CMP R5, R1 + BHI _step_4 + LDR R6, [R5, #+0] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+0] + LDR R6, [R5, #+4] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+4] + + LDR R6, [R5, #+8] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+8] + LDR R6, [R5, #+12] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+12] + + ADDS R5, R5, #+16 + B _step_3_loop + + ; *** Step 4 *** + ; Verify background and write inverted background with addresses decreasing +_step_4: + MOVS R5, R1 + SUBS R5, R5, #+15 +_step_4_loop: + CMP R5, R0 + BLO _step_5 + + LDR R6, [R5, #+12] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+12] + LDR R6, [R5, #+8] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+8] + + LDR R6, [R5, #+4] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+4] + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+0] + + SUBS R5, R5, #+16 + B _step_4_loop + + ; *** Step 5 *** + ; Verify inverted background and write background with addresses decreasing +_step_5: + MOVS R5, R1 + SUBS R5, R5, #+15 +_step_5_loop: + CMP R5, R0 + BLO _step_6 + + LDR R6, [R5, #+12] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+12] + LDR R6, [R5, #+8] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+8] + + LDR R6, [R5, #+4] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+4] + LDR R6, [R5, #+0] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+0] + SUBS R5, R5, #+16 + B _step_5_loop + + ; *** Step 6 *** + ; Verify background with addresses increasing +_step_6: + MOVS R5, R0 +_step_6_loop: + CMP R5, R1 + BHI _full_ram1_test_pass + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + ADDS R5, R5, #+4 + B _step_6_loop + +_full_ram1_test_fail: + MOVS R4, #1 ; STL_ERR + +_full_ram1_test_pass: + MOVS R0, R4 + BX LR ; return to the caller + + END diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s new file mode 100644 index 0000000000..5704246cc0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s @@ -0,0 +1,147 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for IAR */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + + ; Exported function + EXPORT STL_PcTest + +;******************************************************************************* +; Function Name : STL_PcTest +; Description : Test PC +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + + SECTION .text:CODE(2) + THUMB +STL_PcTest + PUSH {R4-R7} ; Save registers + MOVS R0, #0 + MOVS R1, #0 ; clr R0,R1 + MOV R3, LR + +_subroutine_1 + LDR R0, =_return_pc_test_addr_1 + BL _return_pc_test_addr_1 + CMP R0, R1 ; verify return address? + BEQ _subroutine_2 + B _pc_test_fail + +_subroutine_2 + LDR R0, =_return_pc_test_addr_2 + BL _return_pc_test_addr_2 + CMP R0, R1 ; verify return address? + BEQ _subroutine_3 + B _pc_test_fail + +_subroutine_3 + LDR R0, =_return_pc_test_addr_3 + BL _return_pc_test_addr_3 + CMP R0, R1 ; verify return address? + BEQ _subroutine_4 + B _pc_test_fail + +_subroutine_4 + LDR R0, =_return_pc_test_addr_4 + BL _return_pc_test_addr_4 + CMP R0, R1 ; verify return address? + BEQ _subroutine_5 + B _pc_test_fail + +_subroutine_5 + LDR R0, =_return_pc_test_addr_5 + BL _return_pc_test_addr_5 + CMP R0, R1 ; verify return address? + BEQ _subroutine_6 + B _pc_test_fail + +_subroutine_6 + LDR R0, =_return_pc_test_addr_6 + BL _return_pc_test_addr_6 + CMP R0, R1 ; verify return address? + BEQ _subroutine_7 + B _pc_test_fail + +_subroutine_7 + LDR R0, =_return_pc_test_addr_7 + BL _return_pc_test_addr_7 + CMP R0, R1 ; verify return address? + BEQ _subroutine_8 + B _pc_test_fail + +_subroutine_8 + LDR R0, =_return_pc_test_addr_8 + BL _return_pc_test_addr_8 + CMP R0, R1 ; verify return address? + BEQ _pc_test_pass + B _pc_test_fail + +_pc_test_fail + ; when test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _pc_test_exit + +_pc_test_pass + ; when test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK + B _pc_test_exit + +_pc_test_exit: + POP {R4-R7} ; Restore registers + BX R3 ; return + + SECTION .pctestaddr1:CODE(2) +_return_pc_test_addr_1 + LDR R1, =_return_pc_test_addr_1 ; store subrouitne address in R1 + BX LR + + SECTION .pctestaddr2:CODE(2) +_return_pc_test_addr_2 + LDR R1, =_return_pc_test_addr_2 ; store subrouitne address in R1 + BX LR + + SECTION .pctestaddr3:CODE(2) +_return_pc_test_addr_3 + LDR R1, =_return_pc_test_addr_3 ; store subrouitne address in R1 + BX LR + + SECTION .pctestaddr4:CODE(2) +_return_pc_test_addr_4 + LDR R1, =_return_pc_test_addr_4 ; store subrouitne address in R1 + BX LR + + SECTION .pctestaddr5:CODE(2) +_return_pc_test_addr_5 + LDR R1, =_return_pc_test_addr_5 ; store subrouitne address in R1 + BX LR + + SECTION .pctestaddr6:CODE(2) +_return_pc_test_addr_6 + LDR R1, =_return_pc_test_addr_6 ; store subrouitne address in R1 + BX LR + + SECTION .pctestaddr7:CODE(2) +_return_pc_test_addr_7 + LDR R1, =_return_pc_test_addr_7 ; store subrouitne address in R1 + BX LR + + SECTION .pctestaddr8:CODE(2) +_return_pc_test_addr_8 + LDR R1, =_return_pc_test_addr_8 ; store subrouitne address in R1 + BX LR + + END diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s new file mode 100644 index 0000000000..c20034361b --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s @@ -0,0 +1,251 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for MDK */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 + +data0xAAAAAAAA DCD 0xAAAAAAAA +data0x55555555 DCD 0x55555555 + +;******************************************************************************* +; Function Name : STL_CpuTestRuntime +; Description : Test CPU at run-time +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ +STL_CpuTestRuntime PROC + EXPORT STL_CpuTestRuntime + + PUSH {R4-R7} ; Save registers + + ; Register R1 + LDR R0, =data0xAAAAAAAA + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_fail + MOVS R1, #0x1 + + ; Register R2 + LDR R0, =data0xAAAAAAAA + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_fail + MOVS R2, #0x2 + + ; Register R3 + LDR R0, =data0xAAAAAAAA + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_fail + MOVS R3, #0x3 + + ; Register R4 + LDR R0, =data0xAAAAAAAA + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_fail + MOVS R4, #0x4 + + ; Register R5 + LDR R0, =data0xAAAAAAAA + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_fail + MOVS R5, #0x5 + + ; Register R6 + LDR R0, =data0xAAAAAAAA + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_fail + MOVS R6, #0x6 + + ; Register R7 + LDR R0, =data0xAAAAAAAA + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_fail + MOVS R7, #0x7 + + ; Register R8 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_fail + MOVS R0, #0x08 + MOV R8, R0 + + BAL _test_cpu_continue + +_test_cpu_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_continue + ; Register R9 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_fail + MOVS R0, #0x09 + MOV R9, R0 + + ; Register R10 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_fail + MOVS R0, #0x0A + MOV R10, R0 + + ; Register R11 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_fail + MOVS R0, #0x0B + MOV R11, R0 + + ; Register R12 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_fail + MOVS R0, #0x0C + MOV R12, R0 + LDR R0, =_test_cpu_continue + + ; pattern verification (R0 is not tested) + CMP R1, #0x01 + BNE _test_cpu_fail + CMP R2, #0x02 + BNE _test_cpu_fail + CMP R3, #0x03 + BNE _test_cpu_fail + CMP R4, #0x04 + BNE _test_cpu_fail + CMP R5, #0x05 + BNE _test_cpu_fail + CMP R6, #0x06 + BNE _test_cpu_fail + CMP R7, #0x07 + BNE _test_cpu_fail + MOVS R0, #0x08 + CMP R0, R8 + BNE _test_cpu_fail + MOVS R0, #0x09 + CMP R0, R9 + BNE _test_cpu_fail + MOVS R0, #0x0A + CMP R0, R10 + BNE _test_cpu_fail + MOVS R0, #0x0B + CMP R0, R11 + BNE _test_cpu_fail + MOVS R0, #0x0C + CMP R0, R12 + BNE _test_cpu_fail + + ; Link register R14 + ; test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK +_test_exit + POP {R4-R7} ; Restore registers + BX LR ; return + + ENDP + + ALIGN + + END diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_startup.s b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_startup.s new file mode 100644 index 0000000000..cf779fb02b --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_startup.s @@ -0,0 +1,363 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for MDK */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 + +data0xAAAAAAAA DCD 0xAAAAAAAA +data0x55555555 DCD 0x55555555 +data0x80000000 DCD 0x80000000 +data0xAAAAAAA8 DCD 0xAAAAAAA8 +data0x55555554 DCD 0x55555554 +data0x00000000 DCD 0x00000000 +data0x00000001 DCD 0x00000001 + +;******************************************************************************* +; Function Name : STL_CpuTestStartup +; Description : Test CPU at start-up +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ +STL_CpuTestStartup PROC + EXPORT STL_CpuTestStartup + + PUSH {R4-R7} ; Save registers + +_test_cpu_reg0_reg8 + MOVS R0, #0x00 + UXTB R0, R0 + ADDS R0, #0 ; Set Z(ero) Flag + BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + SUBS R0, #1 ; Set N(egative) Flag + BPL _test_cpu_reg0_reg13_fail ; Fails if N clear + ADDS R0, #2 ; Set C(arry) Flag and do not set Z + BCC _test_cpu_reg0_reg13_fail ; Fails if C clear + BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + + LDR R0, =data0x80000000 ; Prepares Overflow test + LDR R0, [R0] + ADDS R0, R0, R0 ; Set V(overflow) Flag + BVC _test_cpu_reg0_reg13_fail ; Fails if V clear + + ; Register R1 + LDR R0, =data0xAAAAAAAA + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + MOVS R1, #0x1 + + ; Register R2 + LDR R0, =data0xAAAAAAAA + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + MOVS R2, #0x2 + + ; Register R3 + LDR R0, =data0xAAAAAAAA + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + MOVS R3, #0x3 + + ; Register R4 + LDR R0, =data0xAAAAAAAA + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + MOVS R4, #0x4 + + ; Register R5 + LDR R0, =data0xAAAAAAAA + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + MOVS R5, #0x5 + + ; Register R6 + LDR R0, =data0xAAAAAAAA + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + MOVS R6, #0x6 + + ; Register R7 + LDR R0, =data0xAAAAAAAA + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + MOVS R7, #0x7 + + ; Register R8 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + MOV R8, R0 + + BAL _test_cpu_continue + +_test_cpu_reg0_reg13_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_continue + ; Register R9 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + MOV R9, R0 + + ; Register R10 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + MOV R10, R0 + + ; Register R11 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + MOV R11, R0 + + ; Register R12 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + MOV R12, R0 + LDR R0, =_test_cpu_continue + + ; pattern verification (R0 is not tested) + CMP R1, #0x01 + BNE _test_cpu_reg0_reg13_fail + CMP R2, #0x02 + BNE _test_cpu_reg0_reg13_fail + CMP R3, #0x03 + BNE _test_cpu_reg0_reg13_fail + CMP R4, #0x04 + BNE _test_cpu_reg0_reg13_fail + CMP R5, #0x05 + BNE _test_cpu_reg0_reg13_fail + CMP R6, #0x06 + BNE _test_cpu_reg0_reg13_fail + CMP R7, #0x07 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + + ; Process Stack pointer (banked Register R13) + MRS R0, PSP ; Save process stack value + LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + MSR PSP, R0 ; Restore process stack value + + ; Stack pointer (Register R13) + MRS R0, MSP ; Save stack pointer value + LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR MSP, R1 ; load SP value + MRS R2, MSP ; Get back SP value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 + LDR R1, [R1] ; load SP value + MSR MSP, R1 ; Get back SP value + MRS R2, MSP ; Verify value + CMP R2, R1 + BNE _test_cpu_reg0_reg13_fail + MSR MSP, R0 ; Restore stack pointer value + +_test_cpu_r14_sfr + ; Link register R14 + MOV R1, LR + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + MOV LR, R1 + + ; PRIMASK register + MRS R1, PRIMASK + LDR R0, =data0x00000000 + LDR R0, [R0] + MSR PRIMASK, R0 + MRS R2, PRIMASK + MOVS R3, #1 + ANDS R2, R3 + CMP R2, #0 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0x00000001 + LDR R0, [R0] + MSR PRIMASK, R0 + MRS R2, PRIMASK + MOVS R3, #1 + ANDS R2, R3 + CMP R2, #1 + BNE _test_cpu_r14_sfr_fail + MSR PRIMASK, R1 + B _test_cpu_pass + +_test_cpu_r14_sfr_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_pass + ; test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK + B _test_exit + +_test_exit + POP {R4-R7} ; Restore registers + BX LR + + ENDP + + ALIGN + + END diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s new file mode 100644 index 0000000000..b5d6501147 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s @@ -0,0 +1,191 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for MDK */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 +data0x00000000 DCD 0x00000000 +data0xFFFFFFFF DCD 0xFFFFFFFF + +;******************************************************************************* +; Function Name : STL_FullRamTestStartup +; Description : Full RAM test at start-up +; Input : R0 .. RAM begin address +; R1 .. RAM end address +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ +STL_FullRamTestStartup PROC + EXPORT STL_FullRamTestStartup + + MOVS R4, #0x0 ; STL_OK:Test success status by default + + LDR R2, =data0x00000000 ; Prepares background pattern + LDR R2, [R2] + LDR R3, =data0xFFFFFFFF ; Prepares inverted background pattern + LDR R3, [R3] + + ; *** Step 1 *** + ; Write background pattern with addresses increasing + MOVS R5, R0 +_step1_loop + CMP R5, R1 + BHI _step_2 + STR R2, [R5, #+0] + ADDS R5, R5, #+4 + B _step1_loop + + ; *** Step 2 *** + ; Verify background and write inverted background with addresses increasing +_step_2 + MOVS R5, R0 +_step_2_loop + CMP R5, R1 + BHI _step_3 + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+0] + LDR R6, [R5, #+4] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+4] + + LDR R6, [R5, #+8] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+8] + LDR R6, [R5, #+12] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+12] + + ADDS R5, R5, #+16 + B _step_2_loop + + ; *** Step 3 *** + ; Verify inverted background and write background with addresses increasing +_step_3 + MOVS R5, R0 +_step_3_loop + CMP R5, R1 + BHI _step_4 + LDR R6, [R5, #+0] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+0] + LDR R6, [R5, #+4] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+4] + + LDR R6, [R5, #+8] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+8] + LDR R6, [R5, #+12] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+12] + + ADDS R5, R5, #+16 + B _step_3_loop + + ; *** Step 4 *** + ; Verify background and write inverted background with addresses decreasing +_step_4 + MOVS R5, R1 + SUBS R5, R5, #+15 +_step_4_loop + CMP R5, R0 + BLO _step_5 + + LDR R6, [R5, #+12] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+12] + LDR R6, [R5, #+8] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+8] + + LDR R6, [R5, #+4] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+4] + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+0] + + SUBS R5, R5, #+16 + B _step_4_loop + + ; *** Step 5 *** + ; Verify inverted background and write background with addresses decreasing +_step_5 + MOVS R5, R1 + SUBS R5, R5, #+15 +_step_5_loop + CMP R5, R0 + BLO _step_6 + + LDR R6, [R5, #+12] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+12] + LDR R6, [R5, #+8] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+8] + + LDR R6, [R5, #+4] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+4] + LDR R6, [R5, #+0] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+0] + SUBS R5, R5, #+16 + B _step_5_loop + + ; *** Step 6 *** + ; Verify background with addresses increasing +_step_6 + MOVS R5, R0 +_step_6_loop + CMP R5, R1 + BHI _full_ram1_test_pass + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + ADDS R5, R5, #+4 + B _step_6_loop + +_full_ram1_test_fail + MOVS R4, #1 ; STL_ERR + +_full_ram1_test_pass + MOVS R0, R4 + BX LR ; return to the caller + + ENDP + + ALIGN + + END diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s new file mode 100644 index 0000000000..598d9ebd6f --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s @@ -0,0 +1,146 @@ +;/***************************************************************************** +; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for MDK */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 + +;******************************************************************************* +; Function Name : STL_PcTest +; Description : Test PC +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + +STL_PcTest PROC + EXPORT STL_PcTest + + PUSH {R4-R7} ; Save registers + MOVS R0, #0 + MOVS R1, #0 ; clr R0,R1 + MOV R3, LR + +_subroutine_1 + LDR R0, =_return_pc_test_addr_1 + BL _return_pc_test_addr_1 + CMP R0, R1 ; verify return address? + BEQ _subroutine_2 + B _pc_test_fail + +_subroutine_2 + LDR R0, =_return_pc_test_addr_2 + BL _return_pc_test_addr_2 + CMP R0, R1 ; verify return address? + BEQ _subroutine_3 + B _pc_test_fail + +_subroutine_3 + LDR R0, =_return_pc_test_addr_3 + BL _return_pc_test_addr_3 + CMP R0, R1 ; verify return address? + BEQ _subroutine_4 + B _pc_test_fail + +_subroutine_4 + LDR R0, =_return_pc_test_addr_4 + BL _return_pc_test_addr_4 + CMP R0, R1 ; verify return address? + BEQ _subroutine_5 + B _pc_test_fail + +_subroutine_5 + LDR R0, =_return_pc_test_addr_5 + BL _return_pc_test_addr_5 + CMP R0, R1 ; verify return address? + BEQ _subroutine_6 + B _pc_test_fail + +_subroutine_6 + LDR R0, =_return_pc_test_addr_6 + BL _return_pc_test_addr_6 + CMP R0, R1 ; verify return address? + BEQ _subroutine_7 + B _pc_test_fail + +_subroutine_7 + LDR R0, =_return_pc_test_addr_7 + BL _return_pc_test_addr_7 + CMP R0, R1 ; verify return address? + BEQ _subroutine_8 + B _pc_test_fail + +_subroutine_8 + LDR R0, =_return_pc_test_addr_8 + BL _return_pc_test_addr_8 + CMP R0, R1 ; verify return address? + BEQ _pc_test_pass + B _pc_test_fail + +_pc_test_fail + ; when test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _pc_test_exit + +_pc_test_pass + ; when test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK + B _pc_test_exit + +_pc_test_exit + POP {R4-R7} ; Restore registers + BX R3 ; return + +_return_pc_test_addr_1 + LDR R1, =_return_pc_test_addr_1 ; store subrouitne address in R1 + BX LR + +_return_pc_test_addr_2 + LDR R1, =_return_pc_test_addr_2 ; store subrouitne address in R1 + BX LR + +_return_pc_test_addr_3 + LDR R1, =_return_pc_test_addr_3 ; store subrouitne address in R1 + BX LR + +_return_pc_test_addr_4 + LDR R1, =_return_pc_test_addr_4 ; store subrouitne address in R1 + BX LR + +_return_pc_test_addr_5 + LDR R1, =_return_pc_test_addr_5 ; store subrouitne address in R1 + BX LR + +_return_pc_test_addr_6 + LDR R1, =_return_pc_test_addr_6 ; store subrouitne address in R1 + BX LR + +_return_pc_test_addr_7 + LDR R1, =_return_pc_test_addr_7 ; store subrouitne address in R1 + BX LR + +_return_pc_test_addr_8 + LDR R1, =_return_pc_test_addr_8 ; store subrouitne address in R1 + BX LR + + ENDP + + ALIGN + + END diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c new file mode 100644 index 0000000000..15a1021b82 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c @@ -0,0 +1,156 @@ +/** + ******************************************************************************* + * @file stl_sw_crc32.c + * @brief This file provides firmware functions to manage the software CRC32. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_sw_crc32.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_CRC32 STL IEC60730 CRC32 + * @brief IEC60730 software CRC32 + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_CRC32_Local_Variables STL IEC60730 CRC32 Local Variables + * @{ + */ +static const uint32_t m_au32Crc32Table[256] = { + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F, + 0xE963A535, 0x9E6495A3, 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, 0x1DB71064, 0x6AB020F2, + 0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9, + 0xFA0F3D63, 0x8D080DF5, 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, 0x35B5A8FA, 0x42B2986C, + 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59, + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423, + 0xCFBA9599, 0xB8BDA50F, 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, 0x76DC4190, 0x01DB7106, + 0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433, + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, + 0x91646C97, 0xE6635C01, 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, 0x65B0D9C6, 0x12B7E950, + 0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, + 0xA4D1C46D, 0xD3D6F4FB, 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, 0x5005713C, 0x270241AA, + 0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F, + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81, + 0xB7BD5C3B, 0xC0BA6CAD, 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, 0xE3630B12, 0x94643B84, + 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1, + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB, + 0x196C3671, 0x6E6B06E7, 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, 0xD6D6A3E8, 0xA1D1937E, + 0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B, + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55, + 0x316E8EEF, 0x4669BE79, 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, 0xC5BA3BBE, 0xB2BD0B28, + 0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F, + 0x72076785, 0x05005713, 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, 0x86D3D2D4, 0xF1D4E242, + 0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777, + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69, + 0x616BFFD3, 0x166CCF45, 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, 0xAED16A4A, 0xD9D65ADC, + 0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693, + 0x54DE5729, 0x23D967BF, 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D +}; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_CRC32_Global_Functions STL IEC60730 CRC32 Global Functions + * @{ + */ + +/** + * @brief Calculate CRC32 value. + * @param [in] u32Crc32Value CRC32 value + * @param [in] pu8Data Pointer to data buffer + * @param [in] u32Len Data length + * @retval None + * @note Poly=0x04C11DB7, Init=0xFFFFFFFF, RefIn=true, RefOut=true, XorOut=0x00000000 + */ +uint32_t STL_CalculateCRC32Value(uint32_t u32Crc32Value, uint8_t *pu8Data, uint32_t u32Len) +{ + uint8_t octet; + const uint8_t *p, *q; + uint32_t u32CurrCrc32Value = u32Crc32Value; + + q = pu8Data + u32Len; + for (p = pu8Data; p < q; p++) { + octet = *p; + u32CurrCrc32Value = (u32CurrCrc32Value >> 8) ^ m_au32Crc32Table[(u32CurrCrc32Value & 0xFFUL) ^ octet]; + } + + return u32CurrCrc32Value; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c new file mode 100644 index 0000000000..ed6c344807 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c @@ -0,0 +1,164 @@ +/** + ******************************************************************************* + * @file stl_test_flash.c + * @brief This file provides firmware functions to manage the flash test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_conf.h" +#include "stl_utility.h" +#include "stl_sw_crc32.h" +#include "stl_test_flash.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_Flash STL IEC60730 Flash + * @brief IEC60730 flash test + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CC_BULID_CRC32_VALUE (*(volatile uint32_t *)(&STL_ROM_CRC32_CC_CHECKSUM)) + +#if defined (__CC_ARM) /* keil Compiler */ +#define STL_CRC32_XOR_VALUE (0xFFFFFFFFUL) +#elif defined (__IAR_SYSTEMS_ICC__) /* IAR Compiler */ +#define STL_CRC32_XOR_VALUE (0x00000000UL) +#endif + +#define SW_CRC32_VALUE_XOR(x) ((x) ^ STL_CRC32_XOR_VALUE) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/** + * @defgroup STL_IEC60730_Flash_Local_Variables STL IEC60730 Flash Local Variables + * @{ + */ +STL_USED const uint32_t __checksum STL_SECTION(".checksum") = 0UL; +/** + * @} + */ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Flash_Global_Functions STL IEC60730 Flash Global Functions + * @{ + */ + +/** + * @brief Flash test in startup. + * @param None + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Flash CRC value error. + */ +uint32_t STL_FlashStartupTest(void) +{ + uint32_t u32CalcCrc32Value; + uint32_t u32Ret = STL_ERR; + + u32CalcCrc32Value = STL_CalculateCRC32Value(STL_CRC32_INIT_VALUE, (uint8_t *)STL_ROM_CRC32_START, STL_ROM_CRC32_SIZE); + u32CalcCrc32Value = SW_CRC32_VALUE_XOR(u32CalcCrc32Value); + if (CC_BULID_CRC32_VALUE == u32CalcCrc32Value) { + u32Ret = STL_OK; + } + + return u32Ret; +} + +/** + * @brief Flash test in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_OK: Flash CRC32 value error. + */ +uint32_t STL_FlashRuntimeTest(void) +{ + uint32_t u32Ret = STL_OK; + const uint32_t u32CheckEndAddr = STL_ROM_CRC32_END + 4UL - STL_ROM_CRC32_BLOCK_SIZE; + static uint32_t u32CalcLen; + static uint32_t u32CheckAddr = STL_ROM_CRC32_START; + static uint32_t u32CalcCrc32Value = STL_CRC32_INIT_VALUE; + + if (u32CheckAddr < STL_ROM_CRC32_END) { + if (u32CheckAddr == STL_ROM_CRC32_START) { + u32CalcCrc32Value = STL_CRC32_INIT_VALUE; /* Update CRC32 init value */ + } + + if (u32CheckAddr < u32CheckEndAddr) { + u32CalcLen = STL_ROM_CRC32_BLOCK_SIZE; + } else { + u32CalcLen = STL_ROM_CRC32_END - u32CheckAddr + 1UL; + } + u32CalcCrc32Value = STL_CalculateCRC32Value(u32CalcCrc32Value, (uint8_t *)u32CheckAddr, u32CalcLen); + + u32CheckAddr += u32CalcLen; /* Update address */ + } else { + u32CheckAddr = STL_ROM_CRC32_START; /* Update address */ + u32CalcCrc32Value = SW_CRC32_VALUE_XOR(u32CalcCrc32Value); + if (CC_BULID_CRC32_VALUE == u32CalcCrc32Value) { + STL_Printf("******** CRC32 verify ok in runtime ********\r\n"); + } else { + STL_Printf("******** CRC32 verify error in runtime ********\r\n"); + STL_Printf("* Calc_CRC32= 0x%x:CC Build_CRC32= 0x%x *\r\n", u32CalcCrc32Value, CC_BULID_CRC32_VALUE); + u32Ret = STL_ERR; + } + } + + return u32Ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c new file mode 100644 index 0000000000..837fc8e25b --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c @@ -0,0 +1,169 @@ +/** + ******************************************************************************* + * @file stl_test_interrupt.c + * @brief This file provides firmware functions to manage the interrupt test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_conf.h" +#include "stl_test_interrupt.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_Interrupt_Runtime STL IEC60730 Interrupt Runtime + * @brief IEC60730 interrupt runtime test + * @{ + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup STL_IEC60730_RAM_Local_Variables STL IEC60730 RAM Local Variables + * @{ + */ +static uint32_t m_u32TestParamTableSize; +static stc_stl_int_params_t *m_pstcTestParamTable; +/** + * @} + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Interrupt_Global_Functions STL IEC60730 Interrupt Global Functions + * @{ + */ + +/** + * @brief Interrupt test table initialize in runtime. + * @param [in] pstcParamsTable Test case table + * @param [in] u32TableSize Test case size + * @retval uint32_t: + * - STL_OK: Initialize successfully. + * - STL_ERR: Initialize unsuccessfully. + */ +uint32_t STL_IntRuntimeTableInit(stc_stl_int_params_t *pstcParamsTable, uint32_t u32TableSize) +{ + uint32_t i; + uint32_t u32Ret = STL_ERR; + + if ((pstcParamsTable != NULL) && (u32TableSize != 0UL)) { + for (i = 0UL; i < u32TableSize; i++) { + pstcParamsTable[i].u32PrivateParam = 0UL; + } + + m_pstcTestParamTable = pstcParamsTable; + m_u32TestParamTableSize = u32TableSize; + u32Ret = STL_OK; + } + + return u32Ret; +} + +/** + * @brief Interrupt test initialize in runtime. + * @param [in] pstcParamsTable Test case table + * @param [in] u32TableSize Test case size + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Test error. + */ +uint32_t STL_IntRuntimeTest(void) +{ + uint32_t i; + uint32_t u32Ret = STL_OK; + stc_stl_int_params_t *pstcTestParam; + static uint32_t u32SystickCount; + + if (++u32SystickCount == STL_SYSTICK_TICK_FREQ) { + for (i = 0UL; i < m_u32TestParamTableSize; i++) { + pstcTestParam = &m_pstcTestParamTable[i]; + + if ((pstcTestParam->u32PrivateParam < pstcTestParam->u32FreqLowerVal) || \ + (pstcTestParam->u32PrivateParam > pstcTestParam->u32FreqUpperVal)) { + u32Ret = STL_ERR; + } + pstcTestParam->u32PrivateParam = 0UL; + } + u32SystickCount = 0UL; + } + + return u32Ret; +} + +/** + * @brief Update interrupt count in runtime. + * @param [in] u8Num Params index + * @param [in] u32TableSize Test case size + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Test error. + */ +void STL_IntUpdateCount(uint8_t u8ParamIndex) +{ + stc_stl_int_params_t *pstcTestParam; + + if (u8ParamIndex < m_u32TestParamTableSize) { + pstcTestParam = &m_pstcTestParamTable[u8ParamIndex]; + pstcTestParam->u32PrivateParam++; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c new file mode 100644 index 0000000000..3a550caaf3 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c @@ -0,0 +1,268 @@ +/** + ******************************************************************************* + * @file stl_test_ram_runtime.c + * @brief This file provides firmware functions to manage the RAM test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_conf.h" +#include "stl_test_ram.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_RAM_Runtime STL IEC60730 RAM Runtime + * @brief IEC60730 RAM runtime test + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup STL_IEC60730_RAM_Local_Variables STL IEC60730 RAM Local Variables + * @{ + */ +STL_USED uint32_t m_au32MarchRAM[STL_MARCH_RAM_WORDS] STL_SECTION(".march_ram"); +STL_USED uint32_t m_au32MarchRAMBuf[STL_MARCH_RAM_BUF_WORDS] STL_SECTION(".march_ram_buf"); +STL_USED uint32_t *m_pu32MarchRAM STL_SECTION(".march_ram_pointer"); +STL_USED uint32_t m_au32StackBoundary[STL_STACK_BOUNDARY_WORDS] STL_SECTION(".stack_boundary"); +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_RAM_Global_Functions STL IEC60730 RAM Global Functions + * @{ + */ + +/** + * @brief Stack test initialize in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Initialization pass. + */ +uint32_t STL_StackRuntimeInit(void) +{ + m_au32StackBoundary[0] = 0x5A5A5A5AUL; + m_au32StackBoundary[1] = 0xA5A5A5A5UL; + m_au32StackBoundary[2] = 0xAAAAAAAAUL; + m_au32StackBoundary[3] = 0x55555555UL; + return STL_OK; +} + +/** + * @brief Stack test in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Stack boundary value error. + */ +uint32_t STL_StackRuntimeTest(void) +{ + if ((m_au32StackBoundary[0] != 0x5A5A5A5AUL) || \ + (m_au32StackBoundary[1] != 0xA5A5A5A5UL) || \ + (m_au32StackBoundary[2] != 0xAAAAAAAAUL) || \ + (m_au32StackBoundary[3] != 0x55555555UL)) { + return STL_ERR; + } + + return STL_OK; +} + +/** + * @brief RAM test initialize in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Initialization pass. + */ +uint32_t STL_RamRuntimeInit(void) +{ + m_pu32MarchRAM = (uint32_t *)STL_MARCH_RAM_START; + return STL_OK; +} + +/** + * @brief RAM test in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Test fail. + */ +uint32_t STL_RamRuntimeTest(void) +{ + uint32_t i; /* Index for RAM physical addressing */ + uint32_t u32Ret = STL_OK; + + if (m_pu32MarchRAM >= (uint32_t *)STL_MARCH_RAM_END) { + /*------------- March C- to the RAM Buffer itself --------------- */ + m_pu32MarchRAM = &m_au32MarchRAMBuf[0]; + + /*---------------------------- STEP 1 --------------------------------- */ + /* Write background with addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + *(m_pu32MarchRAM + i) = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 2 --------------------------------- */ + /* Verify background and write inverted background addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (*(m_pu32MarchRAM + i) != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i) = STL_MARCH_RAM_INVBCKGRND; + } + + /*---------------------------- STEP 3 --------------------------------- */ + /* Verify inverted background and write background addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (*(m_pu32MarchRAM + i) != STL_MARCH_RAM_INVBCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i) = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 4 --------------------------------- */ + /* Verify background and write inverted background addresses decreasing */ + for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL ; --i) { + if (*(m_pu32MarchRAM + i - 1UL) != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i - 1UL) = STL_MARCH_RAM_INVBCKGRND; + } + + /*---------------------------- STEP 5 --------------------------------- */ + /* Verify inverted background and write background addresses decreasing */ + for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL ; --i) { + if (*(m_pu32MarchRAM + i - 1UL) != STL_MARCH_RAM_INVBCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i - 1UL) = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 6 --------------------------------- */ + /* Verify background with addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (*(m_pu32MarchRAM + i) != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + } + + /* Prepare next Tranparent RAM test from the beginning of Class A area */ + m_pu32MarchRAM = (uint32_t *)STL_MARCH_RAM_START; + } else { + /*---------------------------- STEP 1 --------------------------------- */ + /* Save the content of the 6 words to be tested and start MarchC - + Write background with addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + m_au32MarchRAMBuf[i] = *(m_pu32MarchRAM + i); + *(m_pu32MarchRAM + i) = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 2 --------------------------------- */ + /* Verify background and write inverted background addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (*(m_pu32MarchRAM + i) != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i) = STL_MARCH_RAM_INVBCKGRND; + } + + /*---------------------------- STEP 3 --------------------------------- */ + /* Verify inverted background and write background addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (*(m_pu32MarchRAM + i) != STL_MARCH_RAM_INVBCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i) = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 4 --------------------------------- */ + /* Verify background and write inverted background addresses decreasing */ + for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL; --i) { + if (*(m_pu32MarchRAM + i - 1UL) != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i - 1UL) = STL_MARCH_RAM_INVBCKGRND; + } + + /*---------------------------- STEP 5 --------------------------------- */ + /* Verify inverted background and write background addresses decreasing */ + for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL; --i) { + if (*(m_pu32MarchRAM + i - 1UL) != STL_MARCH_RAM_INVBCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i - 1UL) = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 6 --------------------------------- */ + /* Verify background with addresses increasing */ + /* and restore the content of the 6 tested words */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (*(m_pu32MarchRAM + i) != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + *(m_pu32MarchRAM + i) = m_au32MarchRAMBuf[i]; + } + + /* Prepare next Row Tranparent RAM test */ + m_pu32MarchRAM += STL_MARCH_RAM_BUF_WORDS; + } + + return u32Ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c new file mode 100644 index 0000000000..9ec2bf7100 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c @@ -0,0 +1,138 @@ +/** + ******************************************************************************* + * @file stl_test_runtime.c + * @brief This file provides firmware functions to manage the runtime self-test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_test_runtime.h" +#include "stl_conf.h" +#include "stl_utility.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_Runtime STL IEC60730 Runtime + * @brief IEC60730 runtime test + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Runtime_Global_Macros STL IEC60730 Runtime Global Macros + * @{ + */ + +/** + * @brief Self-test initialization in runtime. + * @param [in] pstcCaseTable Test case table + * @param [in] u32TableSize Test case size + * @retval None + */ +void STL_RuntimeTestInit(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize) +{ + uint32_t i; + +#if (STL_PRINT_ENABLE == STL_ON) + (void)STL_PrintfInit(); /* startup debug print */ +#endif + + STL_Printf("******** Self-test runtime initialize ********\r\n"); + + if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) { + for (i = 0UL; i < u32TableSize; i++) { + if (pstcCaseTable[i].pfnInit != NULL) { + if (pstcCaseTable[i].pfnInit() != STL_OK) { + STL_Printf("%s test initialization unsuccessfully in runtime\r\n", pstcCaseTable[i].pcCaseName); + } + } + } + } +} + +/** + * @brief Self-test on runtime. + * @param [in] pstcCaseTable Test case table + * @param [in] u32TableSize Test case size + * @retval None + */ +void STL_RuntimeTestCase(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize) +{ + uint32_t i; + + if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) { + for (i = 0UL; i < u32TableSize; i++) { + if (pstcCaseTable[i].pfnTest != NULL) { + if (pstcCaseTable[i].pfnTest() != STL_OK) { + STL_Printf("******** %s test fail in runtime ********\r\n", pstcCaseTable[i].pcCaseName); + + if (pstcCaseTable[i].pfnFailHandler != NULL) { + pstcCaseTable[i].pfnFailHandler(); + } + } + } + + if (pstcCaseTable[i].pfnFeedDog != NULL) { + pstcCaseTable[i].pfnFeedDog(); + } + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h new file mode 100644 index 0000000000..e98b6c1a6b --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h @@ -0,0 +1,116 @@ +/** + ******************************************************************************* + * @file stl_test_runtime.h + * @brief This file contains all the functions prototypes of runtime test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_RUNTIME_H__ +#define __STL_TEST_RUNTIME_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_Runtime + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Runtime_Global_Type STL IEC60730 Runtime Global Type + * @{ + */ +typedef struct stc_stl_case_runtime { + const char *pcCaseName; + uint32_t (*pfnInit)(void); + uint32_t (*pfnTest)(void); + + void (*pfnFeedDog)(void); + void (*pfnFailHandler)(void); +} stc_stl_case_runtime_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Runtime_Case STL IEC60730 Runtime Case + * @{ + */ +#define STL_RUNTIME_CASE(CaseName, pfnInit, pfnTest, pfnFeedDog, pfnFailHandler) \ + { #CaseName, pfnInit, pfnTest, pfnFeedDog, pfnFailHandler } +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_Runtime_Global_Functions + * @{ + */ + +void STL_RuntimeTestInit(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize); +void STL_RuntimeTestCase(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +{ +#endif + + +#endif /* #include "stl_common.h" */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c new file mode 100644 index 0000000000..3b22da222e --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c @@ -0,0 +1,120 @@ +/** + ******************************************************************************* + * @file stl_test_startup.c + * @brief This file provides firmware functions to manage the startup test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" +#include "stl_conf.h" +#include "stl_utility.h" +#include "stl_test_startup.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_Startup STL IEC60730 Startup + * @brief IEC60730 startup test + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Startup_Global_Macros STL IEC60730 Startup Global Macros + * @{ + */ + +/** + * @brief Power on self-test. + * @param None + * @retval None + */ +STL_WEAK void STL_StartupTest(void) +{ + /* please implement this function. */ + for (;;) { + } +} + +/** + * @brief Power on self-test. + * @param [in] pstcCaseTable Test case table + * @param [in] u32TableSize Test case size + * @retval None + */ +void STL_StartupTestCase(const stc_stl_case_startup_t *pstcCaseTable, uint32_t u32TableSize) +{ + uint32_t i; + + if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) { + for (i = 0UL; i < u32TableSize; i++) { + if (pstcCaseTable[i].pfnTest != NULL) { + if (pstcCaseTable[i].pfnTest() != STL_OK) { + STL_Printf("%s test fail in startup\r\n", pstcCaseTable[i].pcCaseName); + + if (pstcCaseTable[i].pfnFailHandler != NULL) { + pstcCaseTable[i].pfnFailHandler(); + } + } + } + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h new file mode 100644 index 0000000000..fb877e8ff0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h @@ -0,0 +1,111 @@ +/** + ******************************************************************************* + * @file stl_test_startup.h + * @brief This file contains all the functions prototypes of startup test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_STARTUP_H__ +#define __STL_TEST_STARTUP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" +#include "stl_conf.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_Startup + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Runtime_Global_Type STL IEC60730 Runtime Global Type + * @{ + */ +typedef struct stc_stl_case_startup { + const char *pcCaseName; + uint32_t (*pfnTest)(void); + + void (*pfnFailHandler)(void); +} stc_stl_case_startup_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Startup_Case STL IEC60730 Startup Case + * @{ + */ +#define STL_STARTUP_CASE(CaseName, pfnTest, pfnFailHandler) \ + { #CaseName, pfnTest, pfnFailHandler } +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_Startup_Global_Functions + * @{ + */ +void STL_StartupTest(void); +void STL_StartupTestCase(const stc_stl_case_startup_t *pstcCaseTable, uint32_t u32TableSize); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_TEST_STARTUP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c new file mode 100644 index 0000000000..1c9a152432 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c @@ -0,0 +1,234 @@ +/** + ******************************************************************************* + * @file stl_utility.c + * @brief This file provides utility functions for STL. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_utility.h" +#include "hc32_ll_fcg.h" +#include "hc32_ll_gpio.h" +#include "hc32_ll_usart.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup IEC60730_STL + * @{ + */ + +/** + * @defgroup IEC60730_STL_Utility IEC60730 STL Utility + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Utility_Global_Functions STL IEC60730 Utility Global Functions + * @{ + */ + +/** + * @brief Delay function, delay us approximately + * @param [in] u32Count us + * @retval None + */ +void STL_DelayUS(uint32_t u32Count) +{ + DDL_DelayUS(u32Count); +} + +/** + * @brief Delay function, delay ms approximately + * @param [in] u32Count ms + * @retval None + */ +void STL_DelayMS(uint32_t u32Count) +{ + DDL_DelayMS(u32Count); +} + +/** + * @brief STL test safety failure handle + * @param None + * @retval None + */ +void STL_SafetyFailure(void) +{ +#if (STL_RESET_AT_FAILURE == STL_ON) + NVIC_SystemReset(); /* Generate system reset */ +#endif +} + +#if (STL_PRINT_ENABLE == STL_ON) + +/** + * @brief Transmit character. + * @param [in] cData The character for transmitting + * @retval uint32_t: + * - STL_OK: Transmit successfully. + * - STL_ERR: Transmit timeout. + */ +__WEAKDEF uint32_t STL_ConsoleOutputChar(char cData) +{ + uint32_t u32Ret = STL_ERR; + uint32_t u32TxEmpty = 0UL; + __IO uint32_t u32TmpCount = 0UL; + uint32_t u32Timeout = 10000UL; + + /* Wait TX data register empty */ + while ((u32TmpCount <= u32Timeout) && (0UL == u32TxEmpty)) { + u32TxEmpty = READ_REG32_BIT(STL_PRINTF_DEVICE->SR, USART_SR_TXE); + u32TmpCount++; + } + + if (0UL != u32TxEmpty) { + WRITE_REG32(STL_PRINTF_DEVICE->DR, (uint32_t)cData); + u32Ret = STL_OK; + } + + return u32Ret; +} + +#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \ + (defined (__ICCARM__)) || (defined (__CC_ARM)) +/** + * @brief Re-target fputc function. + * @param [in] ch + * @param [in] f + * @retval int32_t + */ +int32_t fputc(int32_t ch, FILE *f) +{ + (void)f; /* Prevent unused argument compilation warning */ + + return (STL_OK == STL_ConsoleOutputChar((char)ch)) ? ch : -1; +} + +#elif defined (__GNUC__) && !defined (__CC_ARM) +/** + * @brief Re-target _write function. + * @param [in] fd + * @param [in] data + * @param [in] size + * @retval int32_t + */ +int32_t _write(int fd, char data[], int32_t size) +{ + int32_t i = -1; + + if (NULL != data) { + (void)fd; /* Prevent unused argument compilation warning */ + + for (i = 0; i < size; i++) { + if (STL_OK != STL_ConsoleOutputChar(data[i])) { + break; + } + } + } + + return i ? i : -1; +} +#endif + +/** + * @brief Initialize printf function + * @param None + * @retval None + */ +uint32_t STL_PrintfInit(void) +{ + uint32_t u32Div; + float32_t f32Error; + uint32_t u32Ret = STL_ERR; + stc_usart_uart_init_t stcUartInit; + + /* Set TX port function */ + GPIO_SetFunc(STL_PRINTF_PORT, STL_PRINTF_PIN, STL_PRINTF_PORT_FUNC); + + /* Enable clock */ + STL_PRINTF_DEVICE_FCG_ENALBE(); + + /*************************************************************************** + * Configure UART + *************************************************************************** + * Baud rate: STL_PRINTF_BAUDRATE + * Bit direction: LSB + * Data bits: 8 + * Stop bits: 1 + * Parity: None + * Sampling bits: 8 + **************************************************************************/ + /* Configure UART */ + (void)USART_UART_StructInit(&stcUartInit); + stcUartInit.u32OverSampleBit = USART_OVER_SAMPLE_8BIT; + (void)USART_UART_Init(STL_PRINTF_DEVICE, &stcUartInit, NULL); + + for (u32Div = 0UL; u32Div <= USART_CLK_DIV64; u32Div++) { + USART_SetClockDiv(STL_PRINTF_DEVICE, u32Div); + if ((LL_OK == USART_SetBaudrate(STL_PRINTF_DEVICE, STL_PRINTF_BAUDRATE, &f32Error)) && \ + ((-STL_PRINTF_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= STL_PRINTF_BAUDRATE_ERR_MAX))) { + USART_FuncCmd(STL_PRINTF_DEVICE, USART_TX, ENABLE); + u32Ret = STL_OK; + break; + } + } + + return u32Ret; +} + +#endif /* STL_PRINT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h new file mode 100644 index 0000000000..1dd50c4357 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h @@ -0,0 +1,107 @@ +/** + ******************************************************************************* + * @file stl_utility.h + * @brief This file contains all the functions prototypes of utility. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_UTILITY_H__ +#define __STL_UTILITY_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" +#include "stl_conf.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup IEC60730_STL + * @{ + */ + +/** + * @addtogroup IEC60730_STL_Utility + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @addtogroup STL_UTILITY_Global_Functions + * @{ + */ + +#if (STL_PRINT_ENABLE == STL_ON) +#include +uint32_t STL_ConsoleOutputChar(char cData); +#define STL_Printf (void)printf +#else +#define STL_Printf(...) +#endif + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @addgroup STL_Utility_Global_Functions + * @{ + */ +void STL_DelayUS(uint32_t u32Count); +void STL_DelayMS(uint32_t u32Count); + +void STL_SafetyFailure(void); + +uint32_t STL_PrintfInit(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_UTILITY_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.c new file mode 100644 index 0000000000..0da412ed76 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.c @@ -0,0 +1,334 @@ +/** + ******************************************************************************* + * @file usb_dev_cdc_msc_wrapper.c + * @brief USB composite functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_cdc_class.h" +#include "usb_dev_msc_class.h" +#include "usb_dev_cdc_msc_wrapper.h" +#include "usb_dev_desc.h" +#include "usb_dev_stdreq.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS LL USB Device Class + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CDC_MSC_COMPOSITE USB Device CDC MSC Composite + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_dev_msc_cdc_init(void *pdev); +void usb_dev_msc_cdc_deinit(void *pdev); +uint8_t usb_dev_msc_cdc_setup(void *pdev, USB_SETUP_REQ *req); +void usb_dev_msc_cdc_datain(void *pdev, uint8_t epnum); +void usb_dev_msc_cdc_dataout(void *pdev, uint8_t epnum); +uint8_t *usb_dev_msc_cdc_getcfgdesc(uint16_t *length); +uint8_t usb_dev_msc_cdc_sof(void *pdev); +void usb_dev_msc_cdc_ctrlep_rxready(void *pdev); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_dev_class_func usb_dev_composite_cbk = { + &usb_dev_msc_cdc_init, + &usb_dev_msc_cdc_deinit, + &usb_dev_msc_cdc_setup, + NULL, + &usb_dev_msc_cdc_ctrlep_rxready, + &usb_dev_msc_cdc_getcfgdesc, + &usb_dev_msc_cdc_sof, + &usb_dev_msc_cdc_datain, + &usb_dev_msc_cdc_dataout, + NULL, + NULL, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__USB_ALIGN_BEGIN static uint8_t usb_dev_msc_cdc_cfgdesc[USB_MSC_CDC_CONFIG_DESC_SIZ] = { + 0x09, /* bLength: Configuration Descriptor size */ + USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_MSC_CDC_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */ + 0x00, + 0x03, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ + + /* IAD for CDC configuration descriptor */ + 0x08, /* bLength */ + 0x0B, /* bDescriptorType */ + 0x00, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0x02, /* bFunctionClass */ + 0x02, /* bFunctionSubClass */ + 0x01, /* bFunctionProtocol */ + 0x00, /* iFunction (Index of string descriptor describing this function) */ + /* CDC configuration descriptor */ + /* interface descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: Interface */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + /* Call Management Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + /* ACM Functional Descriptor */ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + /* Endpoint 2 Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0xFF, /* bInterval: */ + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(MAX_CDC_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(MAX_CDC_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(MAX_CDC_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(MAX_CDC_PACKET_SIZE), + 0x00, + + /* Mass Storage interface ********************/ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x02, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ + /* Mass Storage Endpoints ********************/ + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_IN_EP, /* Endpoint address (IN, address 1) */ + 0x02, /* Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00, /* Polling interval in milliseconds */ + + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_OUT_EP, /* Endpoint address (OUT, address 1) */ + 0x02, /* Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00 /* Polling interval in milliseconds*/ +} ; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initialize the composite device of MSC-HID interface + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_msc_cdc_init(void *pdev) +{ + usb_dev_cdc_init(pdev); + usb_dev_msc_init(pdev); +} + +/** + * @brief de-initialize the composite device of MSC-HID interface + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_msc_cdc_deinit(void *pdev) +{ + usb_dev_cdc_deinit(pdev); + usb_dev_msc_deinit(pdev); +} + +/** + * @brief process the setup requests + * @param [in] pdev device instance + * @param [in] req setup request + * @retval status + */ +uint8_t usb_dev_msc_cdc_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint8_t u8Res = USB_DEV_OK; + switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) { + case USB_REQ_RECIPIENT_INTERFACE: + if (req->wIndex == 0x02U) { + u8Res = usb_dev_msc_setup(pdev, req); + } else { + u8Res = usb_dev_cdc_setup(pdev, req); + } + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + if (req->wIndex == CDC_IN_EP) { + u8Res = usb_dev_cdc_setup(pdev, req); + } else { + u8Res = usb_dev_msc_setup(pdev, req); + } + break; + default: + break; + } + return u8Res; +} + +/** + * @brief Data received on control endpoint + * @param [in] pdev device device instance + * @retval None + */ +void usb_dev_msc_cdc_ctrlep_rxready(void *pdev) +{ + usb_dev_cdc_ctrlep_rxready(pdev); +} + +/** + * @brief process the sof + * @param [in] pdev device instance + * @retval status + */ +uint8_t usb_dev_msc_cdc_sof(void *pdev) +{ + return usb_dev_cdc_sof(pdev); +} + +/** + * @brief process data IN DATA + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_msc_cdc_datain(void *pdev, uint8_t epnum) +{ + if (epnum == (uint8_t)(MSC_IN_EP & ((uint8_t)~0x80U))) { + usb_dev_msc_datain(pdev, epnum); + } else { + usb_dev_cdc_datain(pdev, epnum); + } +} + +/** + * @brief process data OUT DATA + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_msc_cdc_dataout(void *pdev, uint8_t epnum) +{ + if (epnum == (uint8_t)(MSC_OUT_EP & ((uint8_t)~0x80U))) { + usb_dev_msc_dataout(pdev, epnum); + } else { + usb_dev_cdc_dataout(pdev, epnum); + } +} + +/** + * @brief get the configuration descriptor + * @param [in] length length of data butter in bytes + * @retval buffer pointer + */ +uint8_t *usb_dev_msc_cdc_getcfgdesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(usb_dev_msc_cdc_cfgdesc); + return usb_dev_msc_cdc_cfgdesc; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.h new file mode 100644 index 0000000000..a10762e898 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.h @@ -0,0 +1,79 @@ +/** + ******************************************************************************* + * @file usb_dev_cdc_msc_wrapper.h + * @brief header file for the usb_dev_cdc_msc_wrapper.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_CDC_MSC_WRAPPER_H__ +#define __USB_DEV_CDC_MSC_WRAPPER_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_ctrleptrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_CDC_MSC_COMPOSITE + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_MSC_CDC_CONFIG_DESC_SIZ (USB_CDC_CONFIG_DESC_SIZ - 9U + USB_MSC_CONFIG_DESC_SIZ) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_dev_class_func usb_dev_composite_cbk; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_CDC_MSC_WRAPPER_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.c new file mode 100644 index 0000000000..76c55e7e08 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.c @@ -0,0 +1,381 @@ +/** + ******************************************************************************* + * @file usb_dev_custom_hid_class.c + * @brief CUSTOM HID core functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_custom_hid_class.h" +#include "usb_dev_desc.h" +#include "usb_dev_stdreq.h" +#include "usb_dev_driver.h" +#include "usb_bsp.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CUSTOM_HID USB Device Custom HID + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_dev_hid_init(void *pdev); +void usb_dev_hid_deinit(void *pdev); +uint8_t usb_dev_hid_setup(void *pdev, USB_SETUP_REQ *req); +uint8_t *usb_dev_hid_getcfgdesc(uint16_t *length); +void usb_dev_hid_datain(void *pdev, uint8_t epnum); +void usb_dev_hid_dataout(void *pdev, uint8_t epnum); +void usb_dev_hid_ctrlep_rxready(void *pdev); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +uint8_t Report_buf[64]; +uint8_t Send_Buf[64]; +static __IO uint32_t IsReportAvailable = 0UL; + +usb_dev_class_func class_customhid_cbk = { + &usb_dev_hid_init, + &usb_dev_hid_deinit, + &usb_dev_hid_setup, + NULL, + &usb_dev_hid_ctrlep_rxready, + &usb_dev_hid_getcfgdesc, + NULL, + &usb_dev_hid_datain, + &usb_dev_hid_dataout, + NULL, + NULL, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__USB_ALIGN_BEGIN static uint32_t USB_DEV_HID_AltSet = 0UL; + +__USB_ALIGN_BEGIN static uint32_t USB_DEV_HID_Protocol = 0UL; + +__USB_ALIGN_BEGIN static uint32_t USB_DEV_HID_IdleState = 0UL; + +__USB_ALIGN_BEGIN static uint8_t usb_dev_hid_cfgdesc[USB_CUSTOM_HID_CONFIG_DESC_SIZ] = { + 0x09, + USB_CFG_DESCRIPTOR_TYPE, + USB_CUSTOM_HID_CONFIG_DESC_SIZ, + 0x00, + 0x01, + 0x01, + 0x00, + 0xC0, + 0x32, + + 0x09, + USB_INTERFACE_DESCRIPTOR_TYPE, + 0x00, + 0x00, + 0x02, + 0x03, + 0x00, + 0x00, + 0x00, + + 0x09, + CUSTOM_HID_DESCRIPTOR_TYPE, + 0x10, + 0x01, + 0x21, + 0x01, + 0x22, + CUSTOM_HID_REPORT_DESC_SIZE, + 0x00, + + 0x07, + USB_ENDPOINT_DESCRIPTOR_TYPE, + HID_IN_EP, + 0x03, + HID_IN_PACKET, + 0x00, + 0x0A, + + 0x07, + USB_ENDPOINT_DESCRIPTOR_TYPE, + + HID_OUT_EP, + 0x03, + HID_OUT_PACKET, + 0x00, + 0x0A, +} ; + + +__USB_ALIGN_BEGIN static uint8_t CUSTOM_HID_ReportDesc[CUSTOM_HID_REPORT_DESC_SIZE] = { + 0x05, 0x8C, 0x09, 0x06, 0xA1, 0x01, 0x09, 0x06, 0x15, 0x00, 0x26, 0x00, + 0xFF, 0x75, 0x08, 0x95, 0x40, 0x91, 0x82, 0x09, 0x06, 0x15, 0x00, 0x26, + 0x00, 0xFF, 0x75, 0x08, 0x95, 0X40, 0x81, 0x82, 0xC0 +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initialize the HID application + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_hid_init(void *pdev) +{ + usb_opendevep(pdev, HID_IN_EP, HID_IN_PACKET, EP_TYPE_INTR); + usb_opendevep(pdev, HID_OUT_EP, HID_OUT_PACKET, EP_TYPE_INTR); + usb_readytorx(pdev, HID_OUT_EP, Report_buf, HID_OUT_PACKET); + usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID); +} + +/** + * @brief Deinitialize the HID application + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_hid_deinit(void *pdev) +{ + usb_shutdevep(pdev, HID_IN_EP); + usb_shutdevep(pdev, HID_OUT_EP); +} + +/** + * @brief Handle the setup requests + * @param [in] pdev Device instance + * @param [in] req usb requests + * @retval status + */ +uint8_t usb_dev_hid_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint8_t hid_report_length; + uint16_t len = 0U; + uint8_t *pbuf = NULL; + uint8_t u8Ret = USB_DEV_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) { + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) { + case CUSTOM_HID_REQ_SET_PROTOCOL: + USB_DEV_HID_Protocol = (uint8_t)(req->wValue); + break; + case CUSTOM_HID_REQ_GET_PROTOCOL: + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_HID_Protocol, 1U); + break; + case CUSTOM_HID_REQ_SET_IDLE: + USB_DEV_HID_IdleState = (uint8_t)(req->wValue >> 8); + break; + case CUSTOM_HID_REQ_GET_IDLE: + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_HID_IdleState, 1U); + break; + case CUSTOM_HID_REQ_SET_REPORT: + IsReportAvailable = 1UL; + hid_report_length = (uint8_t)(req->wLength); + usb_ctrldatarx(pdev, Report_buf, (uint16_t)hid_report_length); + break; + default: + usb_ctrlerr(pdev); + u8Ret = USB_DEV_FAIL; + break; + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) { + case USB_REQ_GET_DESCRIPTOR: + if (req->wValue >> 8U == CUSTOM_HID_REPORT_DESC) { + len = LL_MIN((uint16_t)CUSTOM_HID_REPORT_DESC_SIZE, req->wLength); + pbuf = (uint8_t *)CUSTOM_HID_ReportDesc; + } else if (req->wValue >> 8U == CUSTOM_HID_DESCRIPTOR_TYPE) { + pbuf = (uint8_t *)usb_dev_hid_cfgdesc + 0x12U; + len = LL_MIN(USB_CUSTOM_HID_DESC_SIZ, req->wLength); + } else { + ; + } + + usb_ctrldatatx(pdev, pbuf, len); + break; + case USB_REQ_GET_INTERFACE : + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_HID_AltSet, 1U); + break; + case USB_REQ_SET_INTERFACE : + USB_DEV_HID_AltSet = (uint8_t)(req->wValue); + break; + default: + break; + } + break; + default: + break; + } + return u8Ret; +} + +/** + * @brief Send HID Report + * @param [in] pdev Device instance + * @param [in] report pointer to report + * @param [in] len the length in bytes would be sent + * @retval status + */ +uint8_t usb_dev_hid_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len) +{ + if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) { + usb_deveptx(pdev, HID_IN_EP, report, (uint32_t)len); + } + return USB_DEV_OK; +} + +/** + * @brief return configuration descriptor + * @param [in] length length of configuration descriptor in bytes + * @retval pointer to configuration descriptor buffer + */ +uint8_t *usb_dev_hid_getcfgdesc(uint16_t *length) +{ + *length = (uint8_t)sizeof(usb_dev_hid_cfgdesc); + return usb_dev_hid_cfgdesc; +} + +/** + * @brief processing for data in + * @param [in] pdev Device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_hid_datain(void *pdev, uint8_t epnum) +{ + usb_flsdevep(pdev, HID_IN_EP); + + if (epnum == (HID_IN_EP & (uint8_t)~0x80U)) { + PrevXferDone = 1U; + } +} + +/** + * @brief processing for data out + * @param [in] pdev Device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_hid_dataout(void *pdev, uint8_t epnum) +{ + if (epnum == HID_OUT_EP) { + switch (Report_buf[0]) { + case 1: /* Led 1 */ + if (Report_buf[1U] == 0U) { + /* RED LED on */ + BSP_LED_Off(LED_RED); + } else { + /* RED LED off */ + BSP_LED_On(LED_RED); + } + break; + + case 2: /* Led 2 */ + if (Report_buf[1U] == 0U) { + /* BLUE LED on */ + BSP_LED_Off(LED_BLUE); + } else { + /* BLUE LED off */ + BSP_LED_On(LED_BLUE); + } + break; + default: + BSP_LED_Off(LED_RED); + BSP_LED_Off(LED_BLUE); + break; + } + } + + usb_readytorx(pdev, HID_OUT_EP, Report_buf, 2U); + usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID); + usb_deveptx(pdev, HID_IN_EP, Report_buf, 2); +} + +/** + * @brief processing for request data in control endpoint + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_hid_ctrlep_rxready(void *pdev) +{ + if (IsReportAvailable == 1UL) { + IsReportAvailable = 0UL; + switch (Report_buf[0]) { + case 1: /* Led 1 */ + if (Report_buf[1] == 0U) { + /* RED LED on */ + BSP_LED_Off(LED_RED); + } else { + /* RED LED off */ + BSP_LED_On(LED_RED); + } + break; + + case 2: /* Led 2 */ + if (Report_buf[1] == 0U) { + /* BLUE LED on */ + BSP_LED_Off(LED_BLUE); + } else { + /* BLUE LED off */ + BSP_LED_On(LED_BLUE); + } + break; + default: + BSP_LED_Off(LED_RED); + BSP_LED_Off(LED_BLUE); + break; + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.h new file mode 100644 index 0000000000..022eefdae8 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.h @@ -0,0 +1,130 @@ +/** + ******************************************************************************* + * @file usb_dev_custom_hid_class.h + * @brief Head file for usb_dev_custom_hid_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_CUSTOMHID_HID_CORE_H__ +#define __USB_DEV_CUSTOMHID_HID_CORE_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_ctrleptrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CUSTOM_HID + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CUSTOM_HID_REPORT_DESC_SIZE (0x21) + +#define USB_CUSTOM_HID_CONFIG_DESC_SIZ (41U) +#define USB_CUSTOM_HID_DESC_SIZ (9U) + +#define CUSTOM_HID_DESCRIPTOR_TYPE (0x21U) +#define CUSTOM_HID_REPORT_DESC (0x22U) + +#define CUSTOM_HID_REQ_SET_PROTOCOL (0x0BU) +#define CUSTOM_HID_REQ_GET_PROTOCOL (0x03U) + +#define CUSTOM_HID_REQ_SET_IDLE (0x0AU) +#define CUSTOM_HID_REQ_GET_IDLE (0x02U) + +#define CUSTOM_HID_REQ_SET_REPORT (0x09U) +#define CUSTOM_HID_REQ_GET_REPORT (0x01U) + +#define LED1_REPORT_ID (0x01U) +#define LED1_REPORT_COUNT (0x01U) + +#define LED2_REPORT_ID (0x02U) +#define LED2_REPORT_COUNT (0x01U) + +#define LED3_REPORT_ID (0x03U) +#define LED3_REPORT_COUNT (0x01U) + +#define LED4_REPORT_ID (0x04U) +#define LED4_REPORT_COUNT (0x01U) + +#define KEY_REPORT_ID (0x05U) +#define TAMPER_REPORT_ID (0x06U) +#define ADC_REPORT_ID (0x07U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_dev_class_func class_customhid_cbk; +extern uint8_t Report_buf[64]; +extern uint8_t Send_Buf[64]; +extern uint8_t usb_dev_hid_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len); + +/* HID Device library callbacks */ +extern void usb_dev_hid_init(void *pdev); +extern void usb_dev_hid_deinit(void *pdev); +extern uint8_t usb_dev_hid_setup(void *pdev, USB_SETUP_REQ *req); +extern uint8_t *usb_dev_hid_getcfgdesc(uint16_t *length); +extern void usb_dev_hid_datain(void *pdev, uint8_t epnum); +extern void usb_dev_hid_dataout(void *pdev, uint8_t epnum); +extern void usb_dev_hid_ctrlep_rxready(void *pdev); + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_CUSTOMHID_HID_CORE_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.c new file mode 100644 index 0000000000..d984583767 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.c @@ -0,0 +1,364 @@ +/** + ******************************************************************************* + * @file usb_dev_hid_cdc_wrapper.c + * @brief HID CDC composite functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_custom_hid_class.h" +#include "usb_dev_cdc_class.h" +#include "usb_dev_hid_cdc_wrapper.h" +#include "usb_dev_desc.h" +#include "usb_dev_stdreq.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_CDC_COMPOSITE USB Device HID CDC Composite + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_COMPOSITE_CFGDESC_SIZE (USB_CUSTOM_HID_CONFIG_DESC_SIZ - 9U + USB_CDC_CONFIG_DESC_SIZ + 8U) + +#define HID_INTERFACE (0x0U) +#define CDC_COM_INTERFACE (0x1U) + + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_dev_composite_init(void *pdev); +void usb_dev_composite_deinit(void *pdev); +uint8_t usb_dev_composite_setup(void *pdev, USB_SETUP_REQ *req); +void usb_dev_composite_rxready(void *pdev); +void usb_dev_composite_datain(void *pdev, uint8_t epnum); +void usb_dev_composite_dataout(void *pdev, uint8_t epnum); +uint8_t usb_dev_composite_sof(void *pdev); +uint8_t *usb_dev_composite_getcfgdesc(uint16_t *length); + + +/******************************************************************************* + * Global variable definitions + ******************************************************************************/ +usb_dev_class_func class_composite_cbk = { + &usb_dev_composite_init, + &usb_dev_composite_deinit, + &usb_dev_composite_setup, + NULL, + &usb_dev_composite_rxready, + &usb_dev_composite_getcfgdesc, + &usb_dev_composite_sof, + &usb_dev_composite_datain, + &usb_dev_composite_dataout, + NULL, + NULL, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__USB_ALIGN_BEGIN static uint8_t usb_dev_composite_cfgdesc[USB_COMPOSITE_CFGDESC_SIZE] = { + 0x09, /* bLength: Configuration Descriptor size */ + USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_COMPOSITE_CFGDESC_SIZE, /* wTotalLength: Bytes returned */ + 0x00, + 0x03, /* bNumInterfaces: 3 interfaces (2 for CDC, 1 for HID) */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xE0, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ + /* 09 */ + /************** Descriptor of HID interface ****************/ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface descriptor type */ + HID_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0x00, /* iInterface: Index of string descriptor */ + /* 18 */ + /******************** Descriptor of HID ********************/ + 0x09, /* bLength: HID Descriptor size */ + CUSTOM_HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID*/ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + CUSTOM_HID_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /* 27 */ + /******************** Descriptor of HID endpoint ********************/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_IN_PACKET, /* wMaxPacketSize: 64 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms) */ + /* 34 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_OUT_PACKET, /* wMaxPacketSize: 64 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms) */ + /* 41 */ + /******** IAD should be positioned just before the CDC interfaces *******/ + 0x08, /* bLength */ + 0x0B, /* bDescriptorType */ + 0x01, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0x02, /* bFunctionClass */ + 0x02, /* bFunctionSubClass */ + 0x01, /* bFunctionProtocol */ + 0x00, /* iFunction (Index of string descriptor describing this function) */ + /*49*/ + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ + CDC_COM_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x01, /* iInterface: */ + /*58*/ + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + /*63*/ + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x02, /* bDataInterface: 2 */ + /*68*/ + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + /*72*/ + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x01, /* bMasterInterface: Communication class interface */ + 0x02, /* bSlaveInterface0: Data Class Interface */ + /*77*/ + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_CMD_PACKET_SIZE), + 0xFF, /* bInterval: */ + /*84*/ + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ + 0x02, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + /*93*/ + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(MAX_CDC_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(MAX_CDC_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + /*100*/ + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(MAX_CDC_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(MAX_CDC_PACKET_SIZE), + 0x00, /* bInterval */ + /*107*/ +} ; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initialize the composite app + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_composite_init(void *pdev) +{ + usb_dev_hid_init(pdev); + usb_dev_cdc_init(pdev); +} + +/** + * @brief Deinitialize the composite app + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_composite_deinit(void *pdev) +{ + usb_dev_hid_deinit(pdev); + usb_dev_cdc_deinit(pdev); +} + +/** + * @brief Handle the setup requests + * @param [in] pdev Device instance + * @param [in] req usb requests + * @retval status + */ +uint8_t usb_dev_composite_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint8_t u8Res = USB_DEV_OK; + switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) { + case USB_REQ_RECIPIENT_INTERFACE: + if (req->wIndex == HID_INTERFACE) { + u8Res = usb_dev_hid_setup(pdev, req); + } else { + u8Res = usb_dev_cdc_setup(pdev, req); + } + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + if (req->wIndex == HID_IN_EP) { + u8Res = usb_dev_hid_setup(pdev, req); + } else { + u8Res = usb_dev_cdc_setup(pdev, req); + } + break; + default: + break; + } + return u8Res; +} + +/** + * @brief get the configuration descriptor and return the its pointer + * @param [in] length length of configuration descriptor + * @retval the pointer of configuration descriptor buffer + */ +uint8_t *usb_dev_composite_getcfgdesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(usb_dev_composite_cfgdesc); + return usb_dev_composite_cfgdesc; +} + +/** + * @brief processing for data in + * @param [in] pdev Device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_composite_datain(void *pdev, uint8_t epnum) +{ + if (epnum == ((uint8_t)CDC_IN_EP & ((uint8_t)~0x80U))) { + usb_dev_cdc_datain(pdev, epnum); + } else { + usb_dev_hid_datain(pdev, epnum); + } +} + +/** + * @brief processing for data out + * @param [in] pdev Device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_composite_dataout(void *pdev, uint8_t epnum) +{ + if (epnum == ((uint8_t)CDC_OUT_EP & (uint8_t)~0x80U)) { + usb_dev_cdc_dataout(pdev, epnum); + } else { + usb_dev_hid_dataout(pdev, epnum); + } +} + +/** + * @brief processing for sof + * @param [in] pdev Device instance + * @retval status + */ +uint8_t usb_dev_composite_sof(void *pdev) + +{ + return (usb_dev_cdc_sof(pdev)); +} + +/** + * @brief processing for rxready of control endpoint + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_composite_rxready(void *pdev) +{ + usb_dev_cdc_ctrlep_rxready(pdev); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.h new file mode 100644 index 0000000000..1f9a5468aa --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.h @@ -0,0 +1,74 @@ +/** + ******************************************************************************* + * @file usb_dev_hid_cdc_wrapper.h + * @brief Head file for usb_dev_hid_cdc_wrapper.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_HID_CDC_WRAPPER_H_ +#define __USB_DEV_HID_CDC_WRAPPER_H_ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_ctrleptrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_CDC_COMPOSITE + * @{ + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_dev_class_func class_composite_cbk; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_HID_CDC_WRAPPER_H_ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.c new file mode 100644 index 0000000000..fcb8efd20c --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.c @@ -0,0 +1,330 @@ +/** + ******************************************************************************* + * @file usb_dev_keyboard_class.c + * @brief HID keyboard functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_keyboard_class.h" +#include "usb_dev_desc.h" +#include "usb_dev_stdreq.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_KEYBOARD USB Device HID Keyboard + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_dev_keyboard_init(void *pdev); +void usb_dev_keyboard_deinit(void *pdev); +uint8_t usb_dev_keyboard_setup(void *pdev, USB_SETUP_REQ *req); +uint8_t *usb_dev_keyboard_getcfgdesc(uint16_t *length); +void usb_dev_keyboard_datain(void *pdev, uint8_t epnum); +void usb_dev_keyboard_dataout(void *pdev, uint8_t epnum); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_dev_class_func usb_dev_keyboard_cbk = { + &usb_dev_keyboard_init, + &usb_dev_keyboard_deinit, + &usb_dev_keyboard_setup, + NULL, + NULL, + &usb_dev_keyboard_getcfgdesc, + NULL, + &usb_dev_keyboard_datain, + &usb_dev_keyboard_dataout, + NULL, + NULL +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__USB_ALIGN_BEGIN static uint32_t USB_DEV_KEYBOARD_AltSet = 0UL; +__USB_ALIGN_BEGIN static uint32_t USB_DEV_KEYBOARD_Protocol = 0UL; +__USB_ALIGN_BEGIN static uint32_t USB_DEV_KEYBOARD_IdleState = 0UL; + +/* USB HID device Configuration Descriptor */ +__USB_ALIGN_BEGIN static uint8_t USB_DEV_KEYBOARD_CfgDesc[KEYBOARD_CFGDESC_SIZE] = { + 0x09, /* bLength: Configuration Descriptor size */ + USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + KEYBOARD_CFGDESC_SIZE, /* wTotalLength: Bytes returned */ + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0x80, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus*/ + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0x00, /* iInterface: Index of string descriptor */ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + KEYBOARD_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x10, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x21, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + 0x08, /* wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms)*/ + /* 34 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType:*/ + HID_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_OUT_PACKET, /* wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms)*/ + /* 41 */ +} ; + +__USB_ALIGN_BEGIN static uint8_t HID_KEYBOARD_ReportDesc[KEYBOARD_REPORT_DESC_SIZE] = { + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x06, /* USAGE (Keyboard) */ + 0xA1, 0x01, /* COLLECTION (Application) */ + 0x05, 0x07, /* USAGE_PAGE (Keyboard) */ + 0x19, 0x00, /* USAGE_MINIMUM (Reserved (no event indicated)) */ + 0x29, 0x00, /* USAGE_MAXIMUM (Reserved (no event indicated)) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x81, 0x03, /* INPUT (Cnst,Var,Abs) */ + 0x95, 0x06, /* REPORT_COUNT (6) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x26, 0xFF, 0x00, /* LOGICAL_MAXIMUM (255) */ + 0x05, 0x07, /* USAGE_PAGE (Keyboard) */ + 0x19, 0x00, /* USAGE_MINIMUM (Reserved (no event indicated)) */ + 0x29, 0xE7, /* USAGE_MAXIMUM (Keyboard Right GUI) */ + 0x81, 0x00, /* INPUT (Data,Ary,Abs) */ + 0x15, 0x01, /* LOGICAL_MINIMUM (1) */ + 0x95, 0x05, /* REPORT_COUNT (5) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0x05, 0x08, /* USAGE_PAGE (LEDs) */ + 0x19, 0x01, /* USAGE_MINIMUM (Num Lock) */ + 0x29, 0x05, /* USAGE_MAXIMUM (Kana) */ + 0x91, 0x02, /* OUTPUT (Data,Var,Abs) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x75, 0x03, /* REPORT_SIZE (3) */ + 0x91, 0x03, /* OUTPUT (Cnst,Var,Abs) */ + 0xC0 /* END_COLLECTION */ +}; + +__IO static uint8_t u8KeyRevBuf[64]; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initialize the interface of KEYBOARD HID + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_keyboard_init(void *pdev) +{ + usb_opendevep(pdev, HID_IN_EP, 8U, EP_TYPE_INTR); + usb_opendevep(pdev, HID_OUT_EP, HID_OUT_PACKET, EP_TYPE_INTR); + usb_readytorx(pdev, HID_OUT_EP, (uint8_t *)u8KeyRevBuf, 64U); + usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID); +} + +/** + * @brief DeInitialize the interface of KEYBOARD HID + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_keyboard_deinit(void *pdev) +{ + usb_shutdevep(pdev, HID_IN_EP); + usb_shutdevep(pdev, HID_OUT_EP); +} + +/** + * @brief Handle the KEYBOARD HID SETUP request + * @param [in] pdev device instance + * @param [in] req usb requests + * @retval status + */ +uint8_t usb_dev_keyboard_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint16_t len = 0U; + uint8_t *pbuf = NULL; + uint8_t u8Res = USB_DEV_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) { + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) { + case KEYBOARD_REQ_SET_PROTOCOL: + USB_DEV_KEYBOARD_Protocol = (uint8_t)(req->wValue); + break; + case KEYBOARD_REQ_GET_PROTOCOL: + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_KEYBOARD_Protocol, 1U); + break; + case KEYBOARD_REQ_SET_IDLE: + USB_DEV_KEYBOARD_IdleState = (uint8_t)(req->wValue >> 8U); + break; + case KEYBOARD_REQ_GET_IDLE: + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_KEYBOARD_IdleState, 1U); + break; + default: + usb_ctrlerr(pdev); + u8Res = USB_DEV_FAIL; + break; + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) { + case USB_REQ_GET_DESCRIPTOR: + if ((req->wValue >> 8U) == (uint16_t)KEYBOARD_REPORT_DESC) { + len = (uint16_t)LL_MIN(KEYBOARD_REPORT_DESC_SIZE, req->wLength); + pbuf = HID_KEYBOARD_ReportDesc; + } else if ((req->wValue >> 8U) == (uint16_t)KEYBOARD_DESCRIPTOR_TYPE) { + pbuf = USB_DEV_KEYBOARD_CfgDesc + 0x12; + len = (uint16_t)LL_MIN(KEYBOARD_DESC_SIZE, req->wLength); + } else { + ; + } + usb_ctrldatatx(pdev, pbuf, len); + break; + case USB_REQ_GET_INTERFACE : + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_KEYBOARD_AltSet, 1U); + break; + case USB_REQ_SET_INTERFACE : + USB_DEV_KEYBOARD_AltSet = (uint8_t)(req->wValue); + break; + default: + break; + } + break; + default: + break; + } + return u8Res; +} + +/** + * @brief Send KEYBOARD HID report to the host + * @param [in] pdev device instance + * @param [in] report pointer to the report buffer + * @param [in] len the length of the report buffer in bytes + * @retval status + */ +uint8_t usb_dev_mouse_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len) +{ + if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) { + usb_deveptx(pdev, HID_IN_EP, report, (uint32_t)len); + } + return USB_DEV_OK; +} + +/** + * @brief get the configuration descriptor + * @param [in] length pointer data length of the configuration descriptor in bytes + * @retval pointer of configuration descriptor buffer + */ +uint8_t *usb_dev_keyboard_getcfgdesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(USB_DEV_KEYBOARD_CfgDesc); + return USB_DEV_KEYBOARD_CfgDesc; +} + +/** + * @brief handle the IN data Stage + * @param [in] pdev Device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_keyboard_datain(void *pdev, uint8_t epnum) +{ + usb_flsdevep(pdev, HID_IN_EP); +} + +/** + * @brief handle the OUT data Stage + * @param [in] pdev Device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_keyboard_dataout(void *pdev, uint8_t epnum) +{ + usb_readytorx(pdev, HID_OUT_EP, (uint8_t *)u8KeyRevBuf, 64U); + usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.h new file mode 100644 index 0000000000..be1ac78613 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.h @@ -0,0 +1,101 @@ +/** + ******************************************************************************* + * @file usb_dev_keyboard_class.h + * @brief Head file for usb_dev_keyboard_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_KEYBOARD_CLASS_H__ +#define __USB_DEV_KEYBOARD_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_ctrleptrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_KEYBOARD + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define KEYBOARD_CFGDESC_SIZE (41U) +#define KEYBOARD_DESC_SIZE (9U) +#define KEYBOARD_REPORT_DESC_SIZE (66U) + +#define KEYBOARD_DESCRIPTOR_TYPE (0x21U) +#define KEYBOARD_REPORT_DESC (0x22U) + + +#define KEYBOARD_REQ_SET_PROTOCOL (0x0BU) +#define KEYBOARD_REQ_GET_PROTOCOL (0x03U) + +#define KEYBOARD_REQ_SET_IDLE (0x0AU) +#define KEYBOARD_REQ_GET_IDLE (0x02U) + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_dev_class_func usb_dev_keyboard_cbk; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern uint8_t usb_dev_mouse_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_KEYBOARD_CLASS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.c new file mode 100644 index 0000000000..df92d3caaf --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.c @@ -0,0 +1,345 @@ +/** + ******************************************************************************* + * @file usb_dev_mouse_class.c + * @brief HID mouse functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_mouse_class.h" +#include "usb_dev_driver.h" +#include "usb_dev_ctrleptrans.h" +#include "usb_dev_stdreq.h" +#include "usb_dev_desc.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_MOUSE USB Device HID Mouse + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_dev_mouse_init(void *pdev); +void usb_dev_mouse_deinit(void *pdev); +uint8_t usb_dev_mouse_setup(void *pdev, USB_SETUP_REQ *req); +uint8_t *usb_dev_mouse_getcfgdesc(uint16_t *length); +void usb_dev_mouse_datain(void *pdev, uint8_t epnum); +void usb_dev_mouse_dataout(void *pdev, uint8_t epnum); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_dev_class_func usb_dev_mouse_cbk = { + &usb_dev_mouse_init, + &usb_dev_mouse_deinit, + &usb_dev_mouse_setup, + NULL, + NULL, + &usb_dev_mouse_getcfgdesc, + NULL, + &usb_dev_mouse_datain, + &usb_dev_mouse_dataout, + NULL, + NULL +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__USB_ALIGN_BEGIN static uint32_t USB_DEV_MOUSE_AltSet = 0UL; +__USB_ALIGN_BEGIN static uint32_t USB_DEV_MOUSE_Protocol = 0UL; +__USB_ALIGN_BEGIN static uint32_t USB_DEV_MOUSE_IdleState = 0UL; + +/* USB HID device Configuration Descriptor */ +__USB_ALIGN_BEGIN static uint8_t USB_DEV_MOUSE_CfgDesc[MOUSE_CFGDESC_SIZE] = { + 0x09, /* bLength: Configuration Descriptor size */ + USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + MOUSE_CFGDESC_SIZE, /* wTotalLength: Bytes returned */ + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0x80, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0x00, /* iInterface: Index of string descriptor */ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + MOUSE_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_IN_PACKET, /* wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms) */ + /* 34 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_OUT_PACKET, /* wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms) */ + /* 41 */ +} ; + +__USB_ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[MOUSE_REPORT_DESC_SIZE] = { + 0x05, 0x01, + 0x09, 0x02, + 0xA1, 0x01, + 0x09, 0x01, + + 0xA1, 0x00, + 0x05, 0x09, + 0x19, 0x01, + 0x29, 0x03, + + 0x15, 0x00, + 0x25, 0x01, + 0x95, 0x03, + 0x75, 0x01, + + 0x81, 0x02, + 0x95, 0x01, + 0x75, 0x05, + 0x81, 0x01, + + 0x05, 0x01, + 0x09, 0x30, + 0x09, 0x31, + 0x09, 0x38, + + 0x15, 0x81, + 0x25, 0x7F, + 0x75, 0x08, + 0x95, 0x03, + + 0x81, 0x06, + 0xC0, 0x09, + 0x3C, 0x05, + 0xFF, 0x09, + + 0x01, 0x15, + 0x00, 0x25, + 0x01, 0x75, + 0x01, 0x95, + + 0x02, 0xB1, + 0x22, 0x75, + 0x06, 0x95, + 0x01, 0xB1, + + 0x01, 0xC0 +}; + +static uint8_t u8HidRevBuf[4]; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initialize the interface of MOUSE HID + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_mouse_init(void *pdev) +{ + usb_opendevep(pdev, HID_IN_EP, HID_IN_PACKET, EP_TYPE_INTR); + usb_opendevep(pdev, HID_OUT_EP, HID_OUT_PACKET, EP_TYPE_INTR); + usb_readytorx(pdev, HID_OUT_EP, u8HidRevBuf, (uint16_t)(sizeof(u8HidRevBuf) / sizeof(uint8_t))); + usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID); +} + +/** + * @brief DeInitialize the interface of MOUSE HID + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_mouse_deinit(void *pdev) +{ + usb_shutdevep(pdev, HID_IN_EP); + usb_shutdevep(pdev, HID_OUT_EP); +} + +/** + * @brief Handle the MOUSE HID SETUP request + * @param [in] pdev device instance + * @param [in] req: usb requests + * @retval status + */ +uint8_t usb_dev_mouse_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint16_t len = 0U; + uint8_t *pbuf = NULL; + uint8_t u8Res = USB_DEV_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) { + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) { + case MOUSE_REQ_SET_PROTOCOL: + USB_DEV_MOUSE_Protocol = (uint8_t)(req->wValue); + break; + case MOUSE_REQ_GET_PROTOCOL: + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_MOUSE_Protocol, 1U); + break; + case MOUSE_REQ_SET_IDLE: + USB_DEV_MOUSE_IdleState = (uint8_t)(req->wValue >> 8U); + break; + case MOUSE_REQ_GET_IDLE: + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_MOUSE_IdleState, 1U); + break; + default: + usb_ctrlerr(pdev); + u8Res = USB_DEV_FAIL; + break; + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) { + case USB_REQ_GET_DESCRIPTOR: + if ((req->wValue >> 8U) == (uint16_t)MOUSE_REPORT_DESC) { + len = (uint16_t)LL_MIN(MOUSE_REPORT_DESC_SIZE, req->wLength); + pbuf = HID_MOUSE_ReportDesc; + } else if ((req->wValue >> 8U) == (uint16_t)MOUSE_DESCRIPTOR_TYPE) { + pbuf = USB_DEV_MOUSE_CfgDesc + 0x12; + len = (uint16_t)LL_MIN(MOUSE_DESC_SIZE, req->wLength); + } else { + ; + } + usb_ctrldatatx(pdev, pbuf, len); + break; + case USB_REQ_GET_INTERFACE : + usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_MOUSE_AltSet, 1U); + break; + case USB_REQ_SET_INTERFACE : + USB_DEV_MOUSE_AltSet = (uint8_t)(req->wValue); + break; + default: + break; + } + break; + default: + break; + } + return u8Res; +} + +/** + * @brief Send MOUSE HID report to the host + * @param [in] pdev device instance + * @param [in] report pointer to the report buffer + * @param [in] length the length of the report buffer in bytes + * @retval status + */ +uint8_t usb_dev_mouse_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t length) +{ + if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) { + usb_deveptx(pdev, HID_IN_EP, report, (uint32_t)length); + } + return USB_DEV_OK; +} + +/** + * @brief get the configuration descriptor + * @param [in] length pointer data length of the configuration descriptor in bytes + * @retval pointer of configuration descriptor buffer + */ +uint8_t *usb_dev_mouse_getcfgdesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(USB_DEV_MOUSE_CfgDesc); + return USB_DEV_MOUSE_CfgDesc; +} + +/** + * @brief handle the IN data Stage + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_mouse_datain(void *pdev, uint8_t epnum) +{ + usb_flsdevep(pdev, HID_IN_EP); +} + +/** + * @brief handle the OUT data Stage + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_mouse_dataout(void *pdev, uint8_t epnum) +{ + usb_readytorx(pdev, HID_OUT_EP, u8HidRevBuf, (uint16_t)(sizeof(u8HidRevBuf) / sizeof(uint8_t))); + usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.h new file mode 100644 index 0000000000..9a6dbb6806 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.h @@ -0,0 +1,101 @@ +/** + ******************************************************************************* + * @file usb_dev_mouse_class.h + * @brief header file for the usb_dev_mouse_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_MOUSE_CLASS_H__ +#define __USB_DEV_MOUSE_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_MOUSE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define MOUSE_CFGDESC_SIZE (41U) +#define MOUSE_DESC_SIZE (9U) +#define MOUSE_REPORT_DESC_SIZE (74U) + +#define MOUSE_DESCRIPTOR_TYPE (0x21U) +#define MOUSE_REPORT_DESC (0x22U) + + +#define MOUSE_REQ_SET_PROTOCOL (0x0BU) +#define MOUSE_REQ_GET_PROTOCOL (0x03U) + +#define MOUSE_REQ_SET_IDLE (0x0AU) +#define MOUSE_REQ_GET_IDLE (0x02U) + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_dev_class_func usb_dev_mouse_cbk; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern uint8_t usb_dev_mouse_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_MOUSE_CLASS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.c new file mode 100644 index 0000000000..1151aa2161 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.c @@ -0,0 +1,273 @@ +/** + ******************************************************************************* + * @file usb_dev_hid_msc_wrapper.c + * @brief MSC_HID composite functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_custom_hid_class.h" +#include "usb_dev_msc_class.h" +#include "usb_dev_hid_msc_wrapper.h" +#include "usb_dev_desc.h" +#include "usb_dev_stdreq.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_MSC_COMPOSITE USB Device HID MSC Composite + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_dev_msc_hid_init(void *pdev); +void usb_dev_msc_hid_deinit(void *pdev); +uint8_t usb_dev_msc_hid_setup(void *pdev, USB_SETUP_REQ *req); +void usb_dev_msc_hid_datain(void *pdev, uint8_t epnum); +void usb_dev_msc_hid_dataout(void *pdev, uint8_t epnum); +uint8_t *usb_dev_msc_hid_getcfgdesc(uint16_t *length); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_dev_class_func usb_dev_composite_cbk = { + &usb_dev_msc_hid_init, + &usb_dev_msc_hid_deinit, + &usb_dev_msc_hid_setup, + NULL, + NULL, + &usb_dev_msc_hid_getcfgdesc, + NULL, + &usb_dev_msc_hid_datain, + &usb_dev_msc_hid_dataout, + NULL, + NULL, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__USB_ALIGN_BEGIN static uint8_t usb_dev_msc_hid_cfgdesc[USB_MSC_HID_CONFIG_DESC_SIZ] = { + 0x09, /* bLength: Configuration Descriptor size */ + USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ + USB_MSC_HID_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */ + 0x00, + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xE0, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ + /************** Descriptor of HID interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ + /******************** Descriptor of HID ********************/ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + CUSTOM_HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + CUSTOM_HID_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of HID endpoint ********************/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_IN_PACKET, /* wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /* bInterval: Polling Interval (10 ms) */ + /* 34 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */ + HID_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_OUT_PACKET, /* wMaxPacketSize: 4 Byte max */ + 0x00, + 0x0A, /*bInterval: Polling Interval (10 ms)*/ + /* 41 */ + /******************** Mass Storage interface ********************/ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ + /******************** Mass Storage Endpoints ********************/ + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_IN_EP, /* Endpoint address (IN, address 1) */ + 0x02, /* Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00, /* Polling interval in milliseconds */ + + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_OUT_EP, /* Endpoint address (OUT, address 1) */ + 0x02, /* Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00 /* Polling interval in milliseconds */ +} ; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initialize the composite device of MSC-HID interface + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_msc_hid_init(void *pdev) +{ + usb_dev_hid_init(pdev); + usb_dev_msc_init(pdev); +} + +/** + * @brief de-initialize the composite device of MSC-HID interface + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_msc_hid_deinit(void *pdev) +{ + usb_dev_hid_deinit(pdev); + usb_dev_msc_deinit(pdev); +} + +/** + * @brief process the setup requests + * @param [in] pdev device instance + * @param [in] req setup request + * @retval status + */ +uint8_t usb_dev_msc_hid_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint8_t u8Res = USB_DEV_OK; + switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) { + case USB_REQ_RECIPIENT_INTERFACE: + if (req->wIndex == 0U) { + u8Res = usb_dev_hid_setup(pdev, req); + } else { + u8Res = usb_dev_msc_setup(pdev, req); + } + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + if (req->wIndex == HID_IN_EP) { + u8Res = usb_dev_hid_setup(pdev, req); + } else { + u8Res = usb_dev_msc_setup(pdev, req); + } + break; + default: + break; + } + return u8Res; +} + +/** + * @brief process data IN DATA + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_msc_hid_datain(void *pdev, uint8_t epnum) +{ + if (epnum == (uint8_t)(MSC_IN_EP & ((uint8_t)~0x80U))) { + usb_dev_msc_datain(pdev, epnum); + } else { + usb_dev_hid_datain(pdev, epnum); + } +} + +/** + * @brief process data OUT DATA + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_msc_hid_dataout(void *pdev, uint8_t epnum) +{ + if (epnum == (uint8_t)(MSC_OUT_EP & ((uint8_t)~0x80U))) { + usb_dev_msc_dataout(pdev, epnum); + } else { + usb_dev_hid_dataout(pdev, epnum); + } +} + +/** + * @brief get the configuration descriptor + * @param [in] length length of data butter in bytes + * @retval buffer pointer + */ +uint8_t *usb_dev_msc_hid_getcfgdesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(usb_dev_msc_hid_cfgdesc); + return usb_dev_msc_hid_cfgdesc; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.h new file mode 100644 index 0000000000..dfcf66c191 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.h @@ -0,0 +1,80 @@ +/** + ******************************************************************************* + * @file usb_dev_hid_msc_wrapper.h + * @brief header file for the usb_dev_hid_msc_wrapper.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_HID_MSC_WRAPPER_H__ +#define __USB_DEV_HID_MSC_WRAPPER_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_ctrleptrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_HID_MSC_COMPOSITE + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#define USB_MSC_HID_CONFIG_DESC_SIZ (USB_CUSTOM_HID_CONFIG_DESC_SIZ - 9U + USB_MSC_CONFIG_DESC_SIZ) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_dev_class_func usb_dev_composite_cbk; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_HID_MSC_WRAPPER_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.c new file mode 100644 index 0000000000..9917749fcb --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.c @@ -0,0 +1,267 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_bot.c + * @brief USB DEV bulk only transfer functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_msc_bot.h" +#include "usb_dev_msc_scsi.h" +#include "usb_dev_ctrleptrans.h" +#include "usb_dev_msc_mem.h" +#include "usb_dev_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC USB Device MSC + * @{ + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +uint16_t MSC_BOT_DataLen; +uint8_t MSC_BOT_State; +static uint8_t MSC_BOT_Status; + +__USB_ALIGN_BEGIN uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET]; + +__USB_ALIGN_BEGIN MSC_BOT_CBW_TypeDef MSC_BOT_cbw; + +__USB_ALIGN_BEGIN MSC_BOT_CSW_TypeDef MSC_BOT_csw; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Send the requested data + * @param [in] pdev device instance + * @param [in] buf pointer for data buffer + * @param [in] length data Length in bytes + * @retval None + */ +static void msc_bot_txdata(usb_core_instance *pdev, uint8_t *buf, uint16_t length) +{ + length = (uint16_t)LL_MIN(MSC_BOT_cbw.dDataLength, length); + MSC_BOT_csw.dDataResidue -= length; + MSC_BOT_csw.bStatus = CSW_CMD_PASSED; + MSC_BOT_State = BOT_SEND_DATA; + usb_deveptx(pdev, MSC_IN_EP, buf, (uint32_t)length); +} + +/** + * @brief abort current transfer + * @param [in] pdev device instance + * @retval None + */ +static void msc_bot_abort(usb_core_instance *pdev) +{ + if ((MSC_BOT_cbw.bmFlags == (uint8_t)0) && + (MSC_BOT_cbw.dDataLength != (uint32_t)0) && + (MSC_BOT_Status == BOT_STATE_NORMAL)) { + usb_stalldevep(pdev, MSC_OUT_EP); + } + usb_stalldevep(pdev, MSC_IN_EP); + if (MSC_BOT_Status == BOT_STATE_ERROR) { + usb_readytorx(pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH); + } +} + +/** + * @brief decodes the CBW command and set the BOT state machine accordingly + * @param [in] pdev device instance + * @retval None + */ +static void msc_bot_decode_cbw(usb_core_instance *pdev) +{ + + MSC_BOT_csw.dTag = MSC_BOT_cbw.dTag; + MSC_BOT_csw.dDataResidue = MSC_BOT_cbw.dDataLength; + + if ((usb_getrxcnt(pdev, MSC_OUT_EP) != BOT_CBW_LENGTH) || + (MSC_BOT_cbw.dSignature != BOT_CBW_SIGNATURE) || + (MSC_BOT_cbw.bLUN > 1U) || + (MSC_BOT_cbw.bCBLength < 1U) || + (MSC_BOT_cbw.bCBLength > 16U)) { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB); + MSC_BOT_Status = BOT_STATE_ERROR; + msc_bot_abort(pdev); + + } else { + if (scsi_cmdprocess(pdev, MSC_BOT_cbw.bLUN, &MSC_BOT_cbw.CB[0]) < 0) { + msc_bot_abort(pdev); + } else if ((MSC_BOT_State != BOT_DATA_IN) && + (MSC_BOT_State != BOT_DATA_OUT) && + (MSC_BOT_State != BOT_LAST_DATA_IN)) { + if (MSC_BOT_DataLen > (uint16_t)0) { + msc_bot_txdata(pdev, MSC_BOT_Data, MSC_BOT_DataLen); + } else { + msc_bot_txcsw(pdev, CSW_CMD_PASSED); + } + } else { + ; + } + } +} + +/** + * @brief initialize the BOT Process + * @param [in] pdev device instance + * @retval None + */ +void msc_bot_init(usb_core_instance *pdev) +{ + MSC_BOT_State = BOT_IDLE; + MSC_BOT_Status = BOT_STATE_NORMAL; + msc_fops->Init(0U); + + usb_flsdevep(pdev, MSC_OUT_EP); + usb_flsdevep(pdev, MSC_IN_EP); + /* Prapare EP to Receive First BOT command */ + usb_readytorx(pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH); +} + +/** + * @brief resets the BOT Machine + * @param [in] pdev device instance + * @retval None + */ +void msc_bot_rst(usb_core_instance *pdev) +{ + MSC_BOT_State = BOT_IDLE; + MSC_BOT_Status = BOT_STATE_RECOVERY; + /* Prapare OUT EP to Receive First BOT command */ + usb_readytorx(pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH); +} + +/** + * @brief deinitialize the BOT Machine + * @param [in] pdev device instance + * @retval None + */ +void msc_bot_deinit(usb_core_instance *pdev) +{ + MSC_BOT_State = BOT_IDLE; +} + +/** + * @brief process BOT IN data stage + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void msc_bot_datain(usb_core_instance *pdev, uint8_t epnum) +{ + switch (MSC_BOT_State) { + case BOT_DATA_IN: + if (scsi_cmdprocess(pdev, MSC_BOT_cbw.bLUN, &MSC_BOT_cbw.CB[0]) < 0) { + msc_bot_txcsw(pdev, CSW_CMD_FAILED); + } + break; + case BOT_SEND_DATA: + case BOT_LAST_DATA_IN: + msc_bot_txcsw(pdev, CSW_CMD_PASSED); + break; + default: + break; + } +} + +/** + * @brief proccess MSC OUT data stage + * @param [in] pdev device instance + * @param [in] epnum endpoint number + * @retval None + */ +void msc_bot_dataout(usb_core_instance *pdev, uint8_t epnum) +{ + switch (MSC_BOT_State) { + case BOT_IDLE: + msc_bot_decode_cbw(pdev); + break; + case BOT_DATA_OUT: + if (scsi_cmdprocess(pdev, MSC_BOT_cbw.bLUN, &MSC_BOT_cbw.CB[0]) < 0) { + msc_bot_txcsw(pdev, CSW_CMD_FAILED); + } + break; + default: + break; + } +} + +/** + * @brief send the Command Status Wrapper + * @param [in] pdev device instance + * @param [in] CSW_Status CSW status + * @retval None + */ +void msc_bot_txcsw(usb_core_instance *pdev, uint8_t CSW_Status) +{ + MSC_BOT_csw.dSignature = BOT_CSW_SIGNATURE; + MSC_BOT_csw.bStatus = CSW_Status; + MSC_BOT_State = BOT_IDLE; + usb_deveptx(pdev, MSC_IN_EP, (uint8_t *)&MSC_BOT_csw, BOT_CSW_LENGTH); + /* Prapare EP to Receive next Cmd */ + usb_readytorx(pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH); +} + +/** + * @brief Complete the clear feature request + * @param [in] pdev device instance + * @param [in] epnum endpoint number + * @retval None + */ +void msc_bot_complete_clearfeature(usb_core_instance *pdev, uint8_t epnum) +{ + if (MSC_BOT_Status == BOT_STATE_ERROR) { + usb_stalldevep(pdev, MSC_IN_EP); + MSC_BOT_Status = BOT_STATE_NORMAL; + } else if (((epnum & 0x80U) == 0x80U) && (MSC_BOT_Status != BOT_STATE_RECOVERY)) { + msc_bot_txcsw(pdev, CSW_CMD_FAILED); + } else { + ; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.h new file mode 100644 index 0000000000..a9fb1d0c33 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.h @@ -0,0 +1,137 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_bot.h + * @brief header file for the usb_dev_msc_bot.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_MSC_BOT_H__ +#define __USB_DEV_MSC_BOT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_core.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef struct { + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataLength; + uint8_t bmFlags; + uint8_t bLUN; + uint8_t bCBLength; + uint8_t CB[16]; +} MSC_BOT_CBW_TypeDef; + +typedef struct { + uint32_t dSignature; + uint32_t dTag; + uint32_t dDataResidue; + uint8_t bStatus; +} MSC_BOT_CSW_TypeDef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define BOT_IDLE (0U) /* Idle state */ +#define BOT_DATA_OUT (1U) /* Data Out state */ +#define BOT_DATA_IN (2U) /* Data In state */ +#define BOT_LAST_DATA_IN (3U) /* Last Data In Last */ +#define BOT_SEND_DATA (4U) /* Send Immediate data */ + +#define BOT_CBW_SIGNATURE (0x43425355UL) +#define BOT_CSW_SIGNATURE (0x53425355UL) +#define BOT_CBW_LENGTH (31U) +#define BOT_CSW_LENGTH (13U) + +/* CSW Status Definitions */ +#define CSW_CMD_PASSED (0x00U) +#define CSW_CMD_FAILED (0x01U) +#define CSW_PHASE_ERROR (0x02U) + +/* BOT Status */ +#define BOT_STATE_NORMAL (0U) +#define BOT_STATE_RECOVERY (1U) +#define BOT_STATE_ERROR (2U) + +#define DIR_IN (0U) +#define DIR_OUT (1U) +#define BOTH_DIR (2U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET]; +extern uint16_t MSC_BOT_DataLen; +extern uint8_t MSC_BOT_State; +extern MSC_BOT_CBW_TypeDef MSC_BOT_cbw; +extern MSC_BOT_CSW_TypeDef MSC_BOT_csw; + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern void msc_bot_init(usb_core_instance *pdev); +extern void msc_bot_rst(usb_core_instance *pdev); +extern void msc_bot_deinit(usb_core_instance *pdev); +extern void msc_bot_datain(usb_core_instance *pdev, uint8_t epnum); +extern void msc_bot_dataout(usb_core_instance *pdev, uint8_t epnum); +extern void msc_bot_txcsw(usb_core_instance *pdev, uint8_t CSW_Status); +extern void msc_bot_complete_clearfeature(usb_core_instance *pdev, uint8_t epnum); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_MSC_BOT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.c new file mode 100644 index 0000000000..2254ddf68e --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.c @@ -0,0 +1,264 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_class.c + * @brief USB MSC device class + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_msc_mem.h" +#include "usb_dev_msc_class.h" +#include "usb_dev_msc_bot.h" +#include "usb_dev_stdreq.h" +#include "usb_dev_driver.h" +#include "usb_dev_ctrleptrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +uint8_t *usb_dev_msc_getcfgdesc(uint16_t *length); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_dev_class_func usb_dev_msc_cbk = { + &usb_dev_msc_init, + &usb_dev_msc_deinit, + &usb_dev_msc_setup, + NULL, + NULL, + &usb_dev_msc_getcfgdesc, + NULL, + &usb_dev_msc_datain, + &usb_dev_msc_dataout, + NULL, + NULL, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static uint8_t dev_msc_maxlun = 0U; +static uint8_t dev_msc_altset = 0U; + +__USB_ALIGN_BEGIN static uint8_t usb_dev_msc_cfgdesc[USB_MSC_CONFIG_DESC_SIZ] = { + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_MSC_CONFIG_DESC_SIZ, + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ + /******************** Mass Storage interface descriptor**********/ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ + /******************** Mass Storage Endpoints descriptor**********/ + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_IN_EP, /* Endpoint address (IN, address 1) */ + 0x02, /* Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00, /* Polling interval in milliseconds */ + + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_OUT_EP, /* Endpoint address (OUT, address 1) */ + 0x02, /* Bulk endpoint type */ + LOBYTE(MSC_MAX_PACKET), + HIBYTE(MSC_MAX_PACKET), + 0x00 /* Polling interval in milliseconds */ +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initialize the mass storage interface configuration + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_msc_init(void *pdev) +{ + usb_dev_msc_deinit(pdev); + usb_opendevep(pdev, MSC_IN_EP, MSC_EPIN_SIZE, EP_TYPE_BULK); + usb_opendevep(pdev, MSC_OUT_EP, MSC_EPOUT_SIZE, EP_TYPE_BULK); + msc_bot_init(pdev); +} + +/** + * @brief deinitilaize the mass storage interface configuration + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_msc_deinit(void *pdev) +{ + usb_shutdevep(pdev, MSC_IN_EP); + usb_shutdevep(pdev, MSC_OUT_EP); + msc_bot_deinit(pdev); +} + +/** + * @brief process the msc setup requests + * @param [in] pdev device instance + * @param [in] req setup request + * @retval status + */ +uint8_t usb_dev_msc_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint8_t u8Res = USB_DEV_OK; + switch (req->bmRequest & USB_REQ_TYPE_MASK) { + case USB_REQ_TYPE_CLASS: + switch (req->bRequest) { + case BOT_GET_MAX_LUN: + if ((req->wValue == (uint16_t)0) && + (req->wLength == (uint16_t)1) && + ((req->bmRequest & 0x80U) == (uint8_t)0x80)) { + dev_msc_maxlun = msc_fops->GetMaxLun(); + if (dev_msc_maxlun > 0U) { + usb_ctrldatatx(pdev, &dev_msc_maxlun, 1U); + } else { + usb_ctrlerr(pdev); + u8Res = USB_DEV_FAIL; + } + } else { + usb_ctrlerr(pdev); + u8Res = USB_DEV_FAIL; + } + break; + case BOT_RESET: + if ((req->wValue == (uint16_t)0) && + (req->wLength == (uint16_t)0) && + ((req->bmRequest & 0x80U) != (uint8_t)0x80)) { + msc_bot_rst(pdev); + } else { + usb_ctrlerr(pdev); + u8Res = USB_DEV_FAIL; + } + break; + default: + usb_ctrlerr(pdev); + u8Res = USB_DEV_FAIL; + break; + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) { + case USB_REQ_GET_INTERFACE: + usb_ctrldatatx(pdev, &dev_msc_altset, 1U); + break; + case USB_REQ_SET_INTERFACE: + dev_msc_altset = (uint8_t)(req->wValue); + break; + case USB_REQ_CLEAR_FEATURE: + usb_flsdevep(pdev, (uint8_t)req->wIndex); + usb_shutdevep(pdev, (uint8_t)req->wIndex); + if ((((uint8_t)req->wIndex) & (uint16_t)0x80U) == (uint16_t)0x80) { + usb_opendevep(pdev, ((uint8_t)req->wIndex), MSC_EPIN_SIZE, EP_TYPE_BULK); + } else { + usb_opendevep(pdev, ((uint8_t)req->wIndex), MSC_EPOUT_SIZE, EP_TYPE_BULK); + } + msc_bot_complete_clearfeature(pdev, (uint8_t)req->wIndex); + break; + default: + break; + } + break; + default: + break; + } + return u8Res; +} + +/** + * @brief process data IN DATA + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_msc_datain(void *pdev, uint8_t epnum) +{ + msc_bot_datain(pdev, epnum); +} + +/** + * @brief process data OUT DATA + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_msc_dataout(void *pdev, uint8_t epnum) +{ + msc_bot_dataout(pdev, epnum); +} + +/** + * @brief get the configuration descriptor + * @param [in] length length of data butter in bytes + * @retval buffer pointer + */ +uint8_t *usb_dev_msc_getcfgdesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(usb_dev_msc_cfgdesc); + return usb_dev_msc_cfgdesc; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.h new file mode 100644 index 0000000000..81f8b1cd57 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.h @@ -0,0 +1,94 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_class.h + * @brief header file for the usb_dev_msc_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_MSC_CLASS_H__ +#define __USB_DEV_MSC_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define BOT_GET_MAX_LUN (0xFEU) +#define BOT_RESET (0xFFU) +#define USB_MSC_CONFIG_DESC_SIZ (32U) + +#define MSC_EPIN_SIZE (MSC_MAX_PACKET) +#define MSC_EPOUT_SIZE (MSC_MAX_PACKET) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern usb_dev_class_func usb_dev_msc_cbk; + +/* MSC Device library callbacks */ +extern void usb_dev_msc_init(void *pdev); +extern void usb_dev_msc_deinit(void *pdev); +extern uint8_t usb_dev_msc_setup(void *pdev, USB_SETUP_REQ *req); +extern void usb_dev_msc_datain(void *pdev, uint8_t epnum); +extern void usb_dev_msc_dataout(void *pdev, uint8_t epnum); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_MSC_CLASS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.c new file mode 100644 index 0000000000..a29cec1307 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.c @@ -0,0 +1,111 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_data.c + * @brief This file provides all the vital inquiry pages and sense data. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_msc_data.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/* USB Mass storage Page 0 Inquiry Data */ +const uint8_t MSC_Page00_Inquiry_Data[] = { /* 7 */ + 0x00, + 0x00, + 0x00, + (LENGTH_INQUIRY_PAGE00 - 4U), + 0x00, + 0x80, + 0x83 +}; +/* USB Mass storage sense 6 Data */ +const uint8_t MSC_Mode_Sense6_data[] = { + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; +/* USB Mass storage sense 10 Data */ +const uint8_t MSC_Mode_Sense10_data[] = { + 0x00, + 0x06, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 +}; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.h new file mode 100644 index 0000000000..5f9c8b2c80 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.h @@ -0,0 +1,92 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_data.h + * @brief header file for the usb_dev_msc_data.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_MSC_DATA_H__ +#define __USB_DEV_MSC_DATA_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define MODE_SENSE6_LEN (8U) +#define MODE_SENSE10_LEN (8U) +#define LENGTH_INQUIRY_PAGE00 (7U) +#define LENGTH_FORMAT_CAPACITIES (20U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern const uint8_t MSC_Page00_Inquiry_Data[LENGTH_INQUIRY_PAGE00]; +extern const uint8_t MSC_Mode_Sense6_data[MODE_SENSE6_LEN]; +extern const uint8_t MSC_Mode_Sense10_data[MODE_SENSE10_LEN]; + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_MSC_DATA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_mem.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_mem.h new file mode 100644 index 0000000000..b301967a89 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_mem.h @@ -0,0 +1,90 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_mem.h + * @brief header file for the usb_dev_msc_mem.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_MSC_MEM_H__ +#define __USB_DEV_MSC_MEM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef struct { + int8_t (* Init)(uint8_t lun); + int8_t (* GetCapacity)(uint8_t lun, uint32_t *block_num, uint32_t *block_size); + int8_t (* GetMaxLun)(void); + int8_t (* IsReady)(uint8_t lun); + int8_t (* Read)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); + int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); + int8_t (* IsWriteProtected)(uint8_t lun); + int8_t *pInquiry; +} USB_DEV_MSC_cbk_TypeDef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_DEV_INQUIRY_LENGTH (36U) + +extern USB_DEV_MSC_cbk_TypeDef *msc_fops; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_MSC_MEM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.c new file mode 100644 index 0000000000..bdbda3a025 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.c @@ -0,0 +1,553 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_scsi.c + * @brief This file provides all the USBD SCSI layer functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_msc_bot.h" +#include "usb_dev_msc_scsi.h" +#include "usb_dev_msc_mem.h" +#include "usb_dev_msc_data.h" +#include "usb_dev_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static uint32_t SCSI_blk_size; +static uint32_t SCSI_blk_nbr; +static uint64_t SCSI_blk_addr; +static uint32_t SCSI_blk_len; +static usb_core_instance *cdev; + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +SCSI_Sense_TypeDef SCSI_Sense[SENSE_LIST_DEEPTH]; +uint8_t SCSI_Sense_Head; +uint8_t SCSI_Sense_Tail; + +/******************************************************************************* + * Local function prototypes + ******************************************************************************/ +int8_t scsi_testunitready(uint8_t lun); +int8_t scsi_inquiry(uint8_t lun, uint8_t *params); +int8_t scsi_readformatcapacity(uint8_t lun); +int8_t scsi_readcapacity10(uint8_t lun); +int8_t scsi_requestsense(uint8_t *params); +int8_t scsi_startstopuint(void); +int8_t scsi_modesense6(uint8_t lun); +int8_t scsi_modesense10(void); +int8_t scsi_write10(uint8_t lun, uint8_t *params); +int8_t scsi_read10(uint8_t lun, uint8_t *params); +int8_t scsi_verify10(uint8_t lun, uint8_t *params); +int8_t scsi_addressrangecheck(uint32_t blk_offset, uint16_t blk_nbr); +int8_t scsi_processread(uint8_t lun); +int8_t scsi_processwrite(uint8_t lun); + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Processes SCSI commands + * @param [in] pdev device instance + * @param [in] lun number of logical unit + * @param [in] params command + * @retval status + */ +int8_t scsi_cmdprocess(usb_core_instance *pdev, uint8_t lun, uint8_t *params) +{ + int8_t Res; + cdev = pdev; + + if (params[0] == SCSI_TEST_UNIT_READY) { + Res = scsi_testunitready(lun); + } else if (params[0] == SCSI_REQUEST_SENSE) { + Res = scsi_requestsense(params); + } else if (params[0] == SCSI_INQUIRY) { + Res = scsi_inquiry(lun, params); + } else if (params[0] == SCSI_START_STOP_UNIT) { + Res = scsi_startstopuint(); + } else if (params[0] == SCSI_ALLOW_MEDIUM_REMOVAL) { + Res = scsi_startstopuint(); + } else if (params[0] == SCSI_MODE_SENSE6) { + Res = scsi_modesense6(lun); + } else if (params[0] == SCSI_MODE_SENSE10) { + Res = scsi_modesense10(); + } else if (params[0] == SCSI_READ_FORMAT_CAPACITIES) { + Res = scsi_readformatcapacity(lun); + } else if (params[0] == SCSI_READ_CAPACITY10) { + Res = scsi_readcapacity10(lun); + } else if (params[0] == SCSI_READ10) { + Res = scsi_read10(lun, params); + } else if (params[0] == SCSI_WRITE10) { + Res = scsi_write10(lun, params); + } else if (params[0] == SCSI_VERIFY10) { + Res = scsi_verify10(lun, params); + } else { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB); + Res = (int8_t) -1; + } + return Res; +} + +/** + * @brief Processes SCSI Test Unit Ready Command + * @param [in] lun number of logical unit + * @retval status + */ +int8_t scsi_testunitready(uint8_t lun) +{ + int8_t i8Ret; + i8Ret = (int8_t)0; + /* case 9 : Hi > D0 */ + if (MSC_BOT_cbw.dDataLength != 0U) { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB); + i8Ret = (int8_t) -1; + } else { + if (msc_fops->IsReady(lun) != 0U) { + scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT); + i8Ret = (int8_t) -1; + } else { + MSC_BOT_DataLen = 0U; + } + } + return i8Ret; +} + +/** + * @brief Processes inquiry command + * @param [in] lun number of logical unit + * @param [in] params command + * @retval status + */ +int8_t scsi_inquiry(uint8_t lun, uint8_t *params) +{ + const uint8_t *pPage; + uint16_t len; + + if ((params[1] & 0x01U) != 0U) { + pPage = (const uint8_t *)MSC_Page00_Inquiry_Data; + len = LENGTH_INQUIRY_PAGE00; + } else { + + pPage = (uint8_t *)&msc_fops->pInquiry[lun * USB_DEV_INQUIRY_LENGTH]; + len = (uint16_t)pPage[4] + (uint16_t)5; + + if (params[4] <= len) { + len = params[4]; + } + } + MSC_BOT_DataLen = len; + + while (len != 0U) { + len--; + MSC_BOT_Data[len] = pPage[len]; + } + return (int8_t)0; +} + +/** + * @brief Processes Read Capacity10 command + * @param [in] lun number of logical unit + * @retval status + */ +int8_t scsi_readcapacity10(uint8_t lun) +{ + int8_t i8Ret = (int8_t)0; + if (msc_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0U) { + scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT); + i8Ret = (int8_t) -1; + } else { + MSC_BOT_Data[0] = (uint8_t)((SCSI_blk_nbr - 1U) >> 24U); + MSC_BOT_Data[1] = (uint8_t)((SCSI_blk_nbr - 1U) >> 16U); + MSC_BOT_Data[2] = (uint8_t)((SCSI_blk_nbr - 1U) >> 8U); + MSC_BOT_Data[3] = (uint8_t)(SCSI_blk_nbr - 1U); + + MSC_BOT_Data[4] = (uint8_t)(SCSI_blk_size >> 24U); + MSC_BOT_Data[5] = (uint8_t)(SCSI_blk_size >> 16U); + MSC_BOT_Data[6] = (uint8_t)(SCSI_blk_size >> 8U); + MSC_BOT_Data[7] = (uint8_t)(SCSI_blk_size); + MSC_BOT_DataLen = 8U; + } + return i8Ret; +} + +/** + * @brief Processes Read Format Capacity command + * @param [in] lun number of logical unit + * @retval status + */ +int8_t scsi_readformatcapacity(uint8_t lun) +{ + int8_t i8Ret = (int8_t)0; + uint32_t blk_size; + uint32_t blk_nbr; + uint16_t i; + + i = 0U; + while (i < 12U) { + MSC_BOT_Data[i++] = 0U; + } + + if (msc_fops->GetCapacity(lun, &blk_nbr, &blk_size) != 0U) { + scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT); + i8Ret = (int8_t) -1; + } else { + MSC_BOT_Data[3] = 0x08U; + MSC_BOT_Data[4] = (uint8_t)((blk_nbr - 1U) >> 24U); + MSC_BOT_Data[5] = (uint8_t)((blk_nbr - 1U) >> 16U); + MSC_BOT_Data[6] = (uint8_t)((blk_nbr - 1U) >> 8U); + MSC_BOT_Data[7] = (uint8_t)(blk_nbr - 1U); + + MSC_BOT_Data[8] = 0x02U; + MSC_BOT_Data[9] = (uint8_t)(blk_size >> 16U); + MSC_BOT_Data[10] = (uint8_t)(blk_size >> 8U); + MSC_BOT_Data[11] = (uint8_t)(blk_size); + + MSC_BOT_DataLen = 12U; + } + return i8Ret; +} + +/** + * @brief Processes Mode Sense6 command + * @param [in] lun number of logical unit + * @retval status + */ +int8_t scsi_modesense6(uint8_t lun) +{ + uint16_t len; + len = 8U; + MSC_BOT_DataLen = len; + while (0U != len) { + len--; + MSC_BOT_Data[len] = MSC_Mode_Sense6_data[len]; + } + return (int8_t)0; +} + +/** + * @brief processes Mode Sense10 command + * @param None + * @retval status + */ +int8_t scsi_modesense10(void) +{ + uint16_t len = 8U; + + MSC_BOT_DataLen = len; + while (0U != len) { + len--; + MSC_BOT_Data[len] = MSC_Mode_Sense10_data[len]; + } + return (int8_t)0; +} + +/** + * @brief processes Request Sense command + * @param [in] params command + * @retval status + */ +int8_t scsi_requestsense(uint8_t *params) +{ + uint8_t i; + + i = 0U; + while (i < REQUEST_SENSE_DATA_LEN) { + MSC_BOT_Data[i++] = 0U; + } + MSC_BOT_Data[0] = 0x70U; + MSC_BOT_Data[7] = REQUEST_SENSE_DATA_LEN - 6U; + if ((SCSI_Sense_Head != SCSI_Sense_Tail)) { + MSC_BOT_Data[2] = (uint8_t)SCSI_Sense[SCSI_Sense_Head].Skey; + MSC_BOT_Data[12] = (uint8_t)SCSI_Sense[SCSI_Sense_Head].w.b.ASCQ; + MSC_BOT_Data[13] = (uint8_t)SCSI_Sense[SCSI_Sense_Head].w.b.ASC; + SCSI_Sense_Head++; + if (SCSI_Sense_Head == SENSE_LIST_DEEPTH) { + SCSI_Sense_Head = 0U; + } + } + MSC_BOT_DataLen = REQUEST_SENSE_DATA_LEN; + if (params[4] <= REQUEST_SENSE_DATA_LEN) { + MSC_BOT_DataLen = params[4]; + } + return (int8_t)0; +} + +/** + * @brief Loads the last error code in the error list + * @param [in] sKey Sense Key + * @param [in] ASC Additional Sense Key + * @retval None + */ +void scsi_sensecode(uint8_t sKey, uint8_t ASC) +{ + SCSI_Sense[SCSI_Sense_Tail].Skey = (char)sKey; + SCSI_Sense[SCSI_Sense_Tail].w.ASC = (uint32_t)ASC << 8U; + SCSI_Sense_Tail++; + if (SCSI_Sense_Tail == SENSE_LIST_DEEPTH) { + SCSI_Sense_Tail = 0U; + } +} + +/** + * @brief processes Start Stop Unit command + * @param None + * @retval status + */ +int8_t scsi_startstopuint(void) +{ + MSC_BOT_DataLen = 0U; + return (int8_t)0; +} + +/** + * @brief processes Read10 command + * @param [in] lun number of logical unit + * @param [in] params command + * @retval status + */ +int8_t scsi_read10(uint8_t lun, uint8_t *params) +{ + int8_t i8Ret = (int8_t)0; + if (MSC_BOT_State == BOT_IDLE) { + /* case 10 : Ho <> Di */ + if ((MSC_BOT_cbw.bmFlags & 0x80U) != 0x80U) { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB); + i8Ret = (int8_t) -1; + } else if (msc_fops->IsReady(lun) != 0U) { + scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT); + i8Ret = (int8_t) -1; + } else { + SCSI_blk_addr = ((uint64_t)params[2] << 24U) | \ + ((uint64_t)params[3] << 16U) | \ + ((uint64_t)params[4] << 8U) | \ + (uint64_t)params[5]; + + SCSI_blk_len = ((uint32_t)params[7] << 8U) | \ + (uint32_t)params[8]; + + + if (scsi_addressrangecheck((uint32_t)SCSI_blk_addr, (uint16_t)SCSI_blk_len) < 0) { + i8Ret = (int8_t) -1; /* error */ + } else { + MSC_BOT_State = BOT_DATA_IN; + SCSI_blk_addr *= SCSI_blk_size; + SCSI_blk_len *= SCSI_blk_size; + /* cases 4,5 : Hi <> Dn */ + if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB); + i8Ret = (int8_t) -1; + } + } + } + } + if (((int8_t) -1) != i8Ret) { + MSC_BOT_DataLen = (uint16_t)MSC_MEDIA_PACKET; + i8Ret = scsi_processread(lun); + } + return i8Ret; +} + +/** + * @brief processes Write10 command + * @param [in] lun number of logical unit + * @param [in] params command + * @retval status + */ +int8_t scsi_write10(uint8_t lun, uint8_t *params) +{ + int8_t i8Ret = (int8_t)0; + if (MSC_BOT_State == BOT_IDLE) { + /* case 8 : Hi <> Do */ + if ((MSC_BOT_cbw.bmFlags & 0x80U) == 0x80U) { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB); + i8Ret = (int8_t) -1; + } else { + if (msc_fops->IsReady(lun) != 0U) { + scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT); + i8Ret = (int8_t) -1; + } + /* Check If media is write-protected */ + else if (msc_fops->IsWriteProtected(lun) != 0U) { + scsi_sensecode(NOT_READY, WRITE_PROTECTED); + i8Ret = (int8_t) -1; + } else { + SCSI_blk_addr = ((uint64_t)params[2] << 24U) | \ + ((uint64_t)params[3] << 16U) | \ + ((uint64_t)params[4] << 8U) | \ + (uint64_t)params[5]; + SCSI_blk_len = ((uint32_t)params[7] << 8U) | \ + (uint32_t)params[8]; + /* check if LBA address is in the right range */ + if (scsi_addressrangecheck((uint32_t)SCSI_blk_addr, (uint16_t)SCSI_blk_len) < 0) { + i8Ret = (int8_t) -1; /* error */ + } else { + SCSI_blk_addr *= SCSI_blk_size; + SCSI_blk_len *= SCSI_blk_size; + /* cases 3,11,13 : Hn,Ho <> D0 */ + if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB); + i8Ret = (int8_t) -1; + } else { + /* Prepare EP to receive first data packet */ + MSC_BOT_State = BOT_DATA_OUT; + usb_readytorx(cdev, MSC_OUT_EP, MSC_BOT_Data, (uint16_t)LL_MIN(SCSI_blk_len, MSC_MEDIA_PACKET)); + } + } + } + } + } else { /* Write Process ongoing */ + i8Ret = scsi_processwrite(lun); + } + return i8Ret; +} + +/** + * @brief processes Verify10 command + * @param [in] lun number of logical unit + * @param [in] params command + * @retval status + */ +int8_t scsi_verify10(uint8_t lun, uint8_t *params) +{ + int8_t i8Ret; + + i8Ret = (int8_t)0; + if ((params[1] & 0x02U) == 0x02U) { + scsi_sensecode(ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND); + i8Ret = (int8_t) -1; /* Error, Verify Mode Not supported */ + } else if (scsi_addressrangecheck((uint32_t)SCSI_blk_addr, (uint16_t)SCSI_blk_len) < (int8_t)0) { + i8Ret = (int8_t) -1; /* error */ + } else { + MSC_BOT_DataLen = 0U; + } + return i8Ret; +} + +/** + * @brief checks the address range + * @param [in] blk_offset first block address + * @param [in] blk_nbr number of block to be processed + * @retval status + */ +int8_t scsi_addressrangecheck(uint32_t blk_offset, uint16_t blk_nbr) +{ + int8_t i8Ret = (int8_t)0; + if ((blk_offset + blk_nbr) > SCSI_blk_nbr) { + scsi_sensecode(ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE); + i8Ret = (int8_t) -1; + } + return i8Ret; +} + +/** + * @brief handles Read Process + * @param [in] lun number of logical unit + * @retval status + */ +int8_t scsi_processread(uint8_t lun) +{ + uint32_t len; + int8_t i8Ret = (int8_t)0; + + len = LL_MIN(SCSI_blk_len, MSC_MEDIA_PACKET); + + if (SCSI_blk_size == 0U) { + i8Ret = (int8_t) -1; + } else if (msc_fops->Read(lun, MSC_BOT_Data, SCSI_blk_addr / SCSI_blk_size, len / SCSI_blk_size) < 0) { + scsi_sensecode(HARDWARE_ERROR, UNRECOVERED_READ_ERROR); + i8Ret = (int8_t) -1; + } else { + usb_deveptx(cdev, MSC_IN_EP, MSC_BOT_Data, len); + SCSI_blk_addr += len; + SCSI_blk_len -= len; + /* case 6 : Hi = Di */ + MSC_BOT_csw.dDataResidue -= len; + if (SCSI_blk_len == 0U) { + MSC_BOT_State = BOT_LAST_DATA_IN; + } + } + return i8Ret; +} + +/** + * @brief handles Write Process + * @param [in] lun number of logical unit + * @retval status + */ +int8_t scsi_processwrite(uint8_t lun) +{ + uint32_t len; + int8_t i8Ret = (int8_t)0; + + len = LL_MIN(SCSI_blk_len, MSC_MEDIA_PACKET); + + if (SCSI_blk_size == 0U) { + i8Ret = (int8_t) -1; + } else if (msc_fops->Write(lun, MSC_BOT_Data, SCSI_blk_addr / SCSI_blk_size, len / SCSI_blk_size) < 0) { + scsi_sensecode(HARDWARE_ERROR, WRITE_FAULT); + i8Ret = (int8_t) -1; + } else { + SCSI_blk_addr += len; + SCSI_blk_len -= len; + /* case 12 : Ho = Do */ + MSC_BOT_csw.dDataResidue -= len; + if (SCSI_blk_len == 0U) { + msc_bot_txcsw(cdev, CSW_CMD_PASSED); + } else { + /* Prapare EP to Receive next packet */ + usb_readytorx(cdev, MSC_OUT_EP, MSC_BOT_Data, (uint16_t)LL_MIN(SCSI_blk_len, MSC_MEDIA_PACKET)); + } + } + return i8Ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.h new file mode 100644 index 0000000000..e8b62cdbb0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.h @@ -0,0 +1,167 @@ +/** + ******************************************************************************* + * @file usb_dev_msc_scsi.h + * @brief header file for the usb_dev_msc_scsi.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_MSC_SCSI_H__ +#define __USB_DEV_MSC_SCSI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_MSC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef struct _SENSE_ITEM { + char Skey; + union { + struct _ASCs { + char ASC; + char ASCQ; + } b; + unsigned int ASC; + char *pData; + } w; +} SCSI_Sense_TypeDef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define SENSE_LIST_DEEPTH (4U) + +/* SCSI Commands */ +#define SCSI_FORMAT_UNIT (0x04U) +#define SCSI_INQUIRY (0x12U) +#define SCSI_MODE_SELECT6 (0x15U) +#define SCSI_MODE_SELECT10 (0x55U) +#define SCSI_MODE_SENSE6 (0x1AU) +#define SCSI_MODE_SENSE10 (0x5AU) +#define SCSI_ALLOW_MEDIUM_REMOVAL (0x1EU) +#define SCSI_READ6 (0x08U) +#define SCSI_READ10 (0x28U) +#define SCSI_READ12 (0xA8U) +#define SCSI_READ16 (0x88U) + +#define SCSI_READ_CAPACITY10 (0x25U) +#define SCSI_READ_CAPACITY16 (0x9EU) + +#define SCSI_REQUEST_SENSE (0x03U) +#define SCSI_START_STOP_UNIT (0x1BU) +#define SCSI_TEST_UNIT_READY (0x00U) +#define SCSI_WRITE6 (0x0AU) +#define SCSI_WRITE10 (0x2AU) +#define SCSI_WRITE12 (0xAAU) +#define SCSI_WRITE16 (0x8AU) + +#define SCSI_VERIFY10 (0x2FU) +#define SCSI_VERIFY12 (0xAFU) +#define SCSI_VERIFY16 (0x8FU) + +#define SCSI_SEND_DIAGNOSTIC (0x1DU) +#define SCSI_READ_FORMAT_CAPACITIES (0x23U) + +#define NO_SENSE (0U) +#define RECOVERED_ERROR (1U) +#define NOT_READY (2U) +#define MEDIUM_ERROR (3U) +#define HARDWARE_ERROR (4U) +#define ILLEGAL_REQUEST (5U) +#define UNIT_ATTENTION (6U) +#define DATA_PROTECT (7U) +#define BLANK_CHECK (8U) +#define VENDOR_SPECIFIC (9U) +#define COPY_ABORTED (10U) +#define ABORTED_COMMAND (11U) +#define VOLUME_OVERFLOW (13U) +#define MISCOMPARE (14U) + +#define INVALID_CDB (0x20U) +#define INVALID_FIELED_IN_COMMAND (0x24U) +#define PARAMETER_LIST_LENGTH_ERROR (0x1AU) +#define INVALID_FIELD_IN_PARAMETER_LIST (0x26U) +#define ADDRESS_OUT_OF_RANGE (0x21U) +#define MEDIUM_NOT_PRESENT (0x3AU) +#define MEDIUM_HAVE_CHANGED (0x28U) +#define WRITE_PROTECTED (0x27U) +#define UNRECOVERED_READ_ERROR (0x11U) +#define WRITE_FAULT (0x03U) + +#define READ_FORMAT_CAPACITY_DATA_LEN (0x0Cu) +#define READ_CAPACITY10_DATA_LEN (0x08U) +#define MODE_SENSE10_DATA_LEN (0x08U) +#define MODE_SENSE6_DATA_LEN (0x04U) +#define REQUEST_SENSE_DATA_LEN (0x12U) +#define STANDARD_INQUIRY_DATA_LEN (0x24U) +#define BLKVFY (0x04U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; +extern uint8_t SCSI_Sense_Head; +extern uint8_t SCSI_Sense_Tail; + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +extern int8_t scsi_cmdprocess(usb_core_instance *pdev, uint8_t lun, uint8_t *params); +extern void scsi_sensecode(uint8_t sKey, uint8_t ASC); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_MSC_SCSI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.c new file mode 100644 index 0000000000..aabb0371e6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.c @@ -0,0 +1,427 @@ +/** + ******************************************************************************* + * @file usb_dev_cdc_class.c + * @brief The CDC VCP core functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_cdc_class.h" +#include "usb_dev_driver.h" +#include "usb_dev_ctrleptrans.h" +#include "usb_dev_stdreq.h" +#include "usb_dev_desc.h" +#include "cdc_data_process.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_SINGLE_CDC USB Device CDC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +uint8_t *usb_dev_cdc_getcfgdesc(uint16_t *length); +void process_asynchdata_uart2usb(void *pdev); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_dev_class_func class_cdc_cbk = { + &usb_dev_cdc_init, + &usb_dev_cdc_deinit, + &usb_dev_cdc_setup, + NULL, + &usb_dev_cdc_ctrlep_rxready, + &usb_dev_cdc_getcfgdesc, + &usb_dev_cdc_sof, + &usb_dev_cdc_datain, + &usb_dev_cdc_dataout, + NULL, + NULL, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__USB_ALIGN_BEGIN static uint32_t alternate_setting = 0UL; +__USB_ALIGN_BEGIN static uint8_t usb_rx_buffer[MAX_CDC_PACKET_SIZE]; +uint8_t uart_rx_buffer[APP_RX_DATA_SIZE]; /* used as a buffer for receiving data from uart port */ +__USB_ALIGN_BEGIN static uint8_t CmdBuff[CDC_CMD_PACKET_SIZE]; +uint32_t APP_Rx_ptr_in = 0UL; +uint32_t APP_Rx_ptr_out = 0UL; +static uint32_t APP_Rx_length = 0UL; +static uint8_t USB_Tx_State = 0U; +static uint32_t cdcCmd = 0xFFUL; +static uint32_t cdcLen = 0UL; +static uint32_t LastPackLen = 0UL; + +__USB_ALIGN_BEGIN static uint8_t usb_dev_cdc_cfgdesc[USB_CDC_CONFIG_DESC_SIZ] = { + 0x09, + USB_CFG_DESCRIPTOR_TYPE, + USB_CDC_CONFIG_DESC_SIZ, + 0x00, + 0x02, + 0x01, + 0x00, + 0xC0, + 0x32, + + 0x08, + 0x0B, + 0x00, + 0x02, + 0x02, + 0x02, + 0x01, + 0x04, + + 0x09, + USB_INTERFACE_DESCRIPTOR_TYPE, + 0x00, + 0x00, + 0x01, + 0x02, + 0x02, + 0x01, + 0x00, + + 0x05, + 0x24, + 0x00, + 0x10, + 0x01, + + 0x05, + 0x24, + 0x01, + 0x00, + 0x01, + + 0x04, + 0x24, + 0x02, + 0x02, + + 0x05, + 0x24, + 0x06, + 0x00, + 0x01, + + 0x07, + USB_ENDPOINT_DESCRIPTOR_TYPE, + CDC_CMD_EP, + 0x03, + LOBYTE(CDC_CMD_PACKET_SIZE), + HIBYTE(CDC_CMD_PACKET_SIZE), + 0xFF, + + 0x09, + USB_INTERFACE_DESCRIPTOR_TYPE, + 0x01, + 0x00, + 0x02, + 0x0A, + 0x00, + 0x00, + 0x00, + + 0x07, + USB_ENDPOINT_DESCRIPTOR_TYPE, + CDC_OUT_EP, + 0x02, + LOBYTE(MAX_CDC_PACKET_SIZE), + HIBYTE(MAX_CDC_PACKET_SIZE), + 0x00, + + 0x07, + USB_ENDPOINT_DESCRIPTOR_TYPE, + CDC_IN_EP, + 0x02, + LOBYTE(MAX_CDC_PACKET_SIZE), + HIBYTE(MAX_CDC_PACKET_SIZE), + 0x00 +} ; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief Initilaize the CDC application + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_cdc_init(void *pdev) +{ + usb_opendevep(pdev, CDC_IN_EP, MAX_CDC_IN_PACKET_SIZE, EP_TYPE_BULK); + usb_opendevep(pdev, CDC_OUT_EP, MAX_CDC_OUT_PACKET_SIZE, EP_TYPE_BULK); + usb_opendevep(pdev, CDC_CMD_EP, CDC_CMD_PACKET_SIZE, EP_TYPE_INTR); + vcp_init(); + usb_readytorx(pdev, CDC_OUT_EP, (uint8_t *)(usb_rx_buffer), MAX_CDC_OUT_PACKET_SIZE); +} + +/** + * @brief Deinitialize the CDC application + * @param [in] pdev Device instance + * @retval None + */ +void usb_dev_cdc_deinit(void *pdev) +{ + usb_shutdevep(pdev, CDC_IN_EP); + usb_shutdevep(pdev, CDC_OUT_EP); + usb_shutdevep(pdev, CDC_CMD_EP); + vcp_deinit(); +} + +/** + * @brief Handle the setup requests + * @param [in] pdev Device instance + * @param [in] req usb requests + * @retval status + */ +uint8_t usb_dev_cdc_setup(void *pdev, USB_SETUP_REQ *req) +{ + uint16_t len = USB_CDC_DESC_SIZ; + uint8_t *pbuf = usb_dev_cdc_cfgdesc + 9; + uint8_t u8Res = USB_DEV_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) { + case USB_REQ_TYPE_CLASS : + if (req->wLength != 0U) { + if ((req->bmRequest & 0x80U) != 0U) { + vcp_ctrlpare(req->bRequest, CmdBuff, req->wLength); + usb_ctrldatatx(pdev, CmdBuff, req->wLength); + } else { + cdcCmd = req->bRequest; + cdcLen = req->wLength; + usb_ctrldatarx(pdev, CmdBuff, req->wLength); + } + } else { + vcp_ctrlpare(req->bRequest, NULL, 0UL); + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) { + case USB_REQ_GET_DESCRIPTOR: + if ((req->wValue >> 8) == CDC_DESCRIPTOR_TYPE) { + pbuf = usb_dev_cdc_cfgdesc + 9U + (9U * USBD_ITF_MAX_NUM); + len = LL_MIN(USB_CDC_DESC_SIZ, req->wLength); + } + usb_ctrldatatx(pdev, pbuf, len); + break; + + case USB_REQ_GET_INTERFACE : + usb_ctrldatatx(pdev, (uint8_t *)&alternate_setting, 1U); + break; + + case USB_REQ_SET_INTERFACE : + if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM) { + alternate_setting = (uint8_t)(req->wValue); + } else { + usb_ctrlerr(pdev); + } + break; + default: + break; + } + break; + + default: + usb_ctrlerr(pdev); + u8Res = USB_DEV_FAIL; + break; + } + return u8Res; +} + +/** + * @brief Data received on control endpoint + * @param [in] pdev device device instance + * @retval None + */ +void usb_dev_cdc_ctrlep_rxready(void *pdev) +{ + if (cdcCmd != NO_CMD) { + vcp_ctrlpare(cdcCmd, CmdBuff, cdcLen); + cdcCmd = NO_CMD; + } +} + +/** + * @brief Data sent on non-control IN endpoint + * @param [in] pdev Device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_cdc_datain(void *pdev, uint8_t epnum) +{ + uint16_t tx2usb_ptr; + uint16_t tx2usb_length; + + if (USB_Tx_State == 1U) { + if (APP_Rx_length == 0U) { + if (LastPackLen == MAX_CDC_IN_PACKET_SIZE) { + usb_deveptx(pdev, CDC_IN_EP, NULL, 0UL); + LastPackLen = 0UL; + } else { + USB_Tx_State = 0U; + } + } else { + if (APP_Rx_length >= MAX_CDC_IN_PACKET_SIZE) { + tx2usb_ptr = (uint16_t)APP_Rx_ptr_out; + tx2usb_length = (uint16_t)MAX_CDC_IN_PACKET_SIZE - 1U; + APP_Rx_ptr_out += MAX_CDC_IN_PACKET_SIZE - 1U; + APP_Rx_length -= MAX_CDC_IN_PACKET_SIZE - 1U; + } else { + tx2usb_ptr = (uint16_t)APP_Rx_ptr_out; + tx2usb_length = (uint16_t)APP_Rx_length; + APP_Rx_ptr_out += APP_Rx_length; + APP_Rx_length = 0U; + } + usb_deveptx(pdev, + CDC_IN_EP, + (uint8_t *)&uart_rx_buffer[tx2usb_ptr], + (uint32_t)tx2usb_length); + LastPackLen = (uint32_t)tx2usb_length; + } + } +} + +/** + * @brief Data received on non-control Out endpoint + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dev_cdc_dataout(void *pdev, uint8_t epnum) +{ + uint16_t usb_rx_cnt; + + usb_rx_cnt = (uint16_t)((usb_core_instance *)pdev)->dev.out_ep[epnum].xfer_count; + vcp_rxdata(usb_rx_buffer, usb_rx_cnt); + usb_readytorx(pdev, CDC_OUT_EP, (uint8_t *)(usb_rx_buffer), MAX_CDC_OUT_PACKET_SIZE); +} + +/** + * @brief Start Of Frame event management + * @param [in] pdev Device instance + * @retval status + */ +uint8_t usb_dev_cdc_sof(void *pdev) +{ + static uint32_t FrameCount = 0UL; + + if (FrameCount++ == CDC_IN_FRAME_INTERVAL) { + FrameCount = 0UL; + process_asynchdata_uart2usb(pdev); + } + return USB_DEV_OK; +} + +/** + * @brief process the data received from usart and send through USB to host + * @param [in] pdev device instance + * @retval None + */ +void process_asynchdata_uart2usb(void *pdev) +{ + uint16_t tx2usb_ptr; /* the location of the pointer in buffer that would be sent to USB */ + uint16_t tx2usb_length; /* the length in bytes that would be sent to USB */ + + if (USB_Tx_State != 1U) { + if (APP_Rx_ptr_out == APP_RX_DATA_SIZE) { + APP_Rx_ptr_out = 0UL; + } + if (APP_Rx_ptr_out == APP_Rx_ptr_in) { + USB_Tx_State = 0U; + } else { + if (APP_Rx_ptr_out > APP_Rx_ptr_in) { + APP_Rx_length = APP_RX_DATA_SIZE - APP_Rx_ptr_out; + } else { + APP_Rx_length = APP_Rx_ptr_in - APP_Rx_ptr_out; + } + + if (APP_Rx_length >= MAX_CDC_IN_PACKET_SIZE) { + tx2usb_ptr = (uint16_t)APP_Rx_ptr_out; + tx2usb_length = MAX_CDC_IN_PACKET_SIZE - 1U; + + APP_Rx_ptr_out += MAX_CDC_IN_PACKET_SIZE - 1UL; + APP_Rx_length -= MAX_CDC_IN_PACKET_SIZE - 1UL; + } else { + tx2usb_ptr = (uint16_t)APP_Rx_ptr_out; + tx2usb_length = (uint16_t)APP_Rx_length; + + APP_Rx_ptr_out += APP_Rx_length; + APP_Rx_length = 0UL; + } + USB_Tx_State = 1U; + + usb_deveptx(pdev, + CDC_IN_EP, + (uint8_t *)&uart_rx_buffer[tx2usb_ptr], + (uint32_t)tx2usb_length); + LastPackLen = (uint32_t)tx2usb_length; + } + } +} + +/** + * @brief get the configuration descriptor + * @param [in] length length of configuration descriptor in bytes + * @retval the pointer to configuration descriptor buffer + */ +uint8_t *usb_dev_cdc_getcfgdesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(usb_dev_cdc_cfgdesc); + return usb_dev_cdc_cfgdesc; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.h new file mode 100644 index 0000000000..5d19559dfc --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.h @@ -0,0 +1,121 @@ +/** + ******************************************************************************* + * @file usb_dev_cdc_class.h + * @brief Head file for usb_dev_cdc_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_CDC_CLASS_H__ +#define __USB_DEV_CDC_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_SINGLE_CDC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_CDC_CONFIG_DESC_SIZ (75U) +#define USB_CDC_DESC_SIZ (75U-9U) + +#define CDC_DESCRIPTOR_TYPE (0x21U) + +#define DEVICE_CLASS_CDC (0x02U) +#define DEVICE_SUBCLASS_CDC (0x00U) + +#define STANDARD_ENDPOINT_DESC_SIZE (0x09U) + +#define MAX_CDC_IN_PACKET_SIZE (MAX_CDC_PACKET_SIZE) + +#define MAX_CDC_OUT_PACKET_SIZE (MAX_CDC_PACKET_SIZE) + +/**************************************************/ +/* CDC Requests */ +/**************************************************/ +#define SEND_ENCAPSULATED_COMMAND (0x00U) +#define GET_ENCAPSULATED_RESPONSE (0x01U) +#define SET_COMM_FEATURE (0x02U) +#define GET_COMM_FEATURE (0x03U) +#define CLEAR_COMM_FEATURE (0x04U) +#define SET_LINE_CODING (0x20U) +#define GET_LINE_CODING (0x21U) +#define SET_CONTROL_LINE_STATE (0x22U) +#define SEND_BREAK (0x23U) +#define NO_CMD (0xFFU) + +extern uint8_t uart_rx_buffer[APP_RX_DATA_SIZE]; +extern uint32_t APP_Rx_ptr_in; +extern uint32_t APP_Rx_ptr_out; +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_dev_class_func class_cdc_cbk; + +/* CDC Device library callbacks */ +extern void usb_dev_cdc_init(void *pdev);; +extern void usb_dev_cdc_deinit(void *pdev); +extern uint8_t usb_dev_cdc_setup(void *pdev, USB_SETUP_REQ *req); +extern void usb_dev_cdc_datain(void *pdev, uint8_t epnum); +extern void usb_dev_cdc_dataout(void *pdev, uint8_t epnum); +extern void usb_dev_cdc_ctrlep_rxready(void *pdev); +extern uint8_t usb_dev_cdc_sof(void *pdev); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_CDC_CLASS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.c new file mode 100644 index 0000000000..c22ad83280 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.c @@ -0,0 +1,339 @@ +/** + ******************************************************************************* + * @file usb_dev_core.c + * @brief USBD core functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_core.h" +#include "usb_dev_stdreq.h" +#include "usb_dev_ctrleptrans.h" +#include "usb_dev_driver.h" +#include "usb_dev_int.h" +#include "usb_bsp.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE LL USB Device Core + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_setup_process(usb_core_instance *pdev); +void usb_dataout_process(usb_core_instance *pdev, uint8_t epnum); +void usb_datain_process(usb_core_instance *pdev, uint8_t epnum); +void usb_sof_process(usb_core_instance *pdev); +void usb_dev_rst(usb_core_instance *pdev); +void usb_dev_susp(usb_core_instance *pdev); +void usb_dev_resume(usb_core_instance *pdev); +void usb_ctrlconn(usb_core_instance *pdev, uint8_t conn); +void usb_isoinincomplt_process(usb_core_instance *pdev); +void usb_isooutincomplt_process(usb_core_instance *pdev); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +__IO uint32_t SET_TEST_MODE; +static usb_dev_int_cbk_typedef dev_int_cbk = { + &usb_dev_rst, + &usb_ctrlconn, + &usb_dev_susp, + &usb_dev_resume, + &usb_sof_process, + &usb_setup_process, + &usb_dataout_process, + &usb_datain_process, + &usb_isoinincomplt_process, + &usb_isooutincomplt_process +}; + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_dev_int_cbk_typedef *dev_int_cbkpr = &dev_int_cbk; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Initailizes the device stack and load the class driver + * @param [in] pdev device instance + * @param [in] pdesc Device Descriptor + * @param [in] class_cb Class callback structure address + * @param [in] usr_cb User callback structure address + * @retval None + */ +void usb_dev_init(usb_core_instance *pdev, + usb_dev_desc_func *pdesc, + usb_dev_class_func *class_cb, + usb_dev_user_func *usr_cb) +{ + usb_bsp_init(pdev); + pdev->dev.class_callback = class_cb; + pdev->dev.user_callback = usr_cb; + pdev->dev.desc_callback = pdesc; + usb_initdev(pdev); + pdev->dev.user_callback->user_init(); + pdev->dev.device_state = USB_EP0_IDLE; + usb_bsp_nvicconfig(); +} + +/** + * @brief De-initailizes the device stack and load the class driver + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_deinit(usb_core_instance *pdev) +{ + (void)(pdev); +} + +/** + * @brief Handle Reset event + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_rst(usb_core_instance *pdev) +{ + usb_opendevep(pdev, 0x00U, USB_MAX_EP0_SIZE, EP_TYPE_CTRL); + usb_opendevep(pdev, 0x80U, USB_MAX_EP0_SIZE, EP_TYPE_CTRL); + pdev->dev.device_cur_status = USB_DEV_DEFAULT; + pdev->dev.user_callback->user_devrst(); +} + +/** + * @brief Handle device connection and disconnection event + * @param [in] pdev device instance + * @param [in] conn 1 or 0 + * @retval None + */ +void usb_ctrlconn(usb_core_instance *pdev, uint8_t conn) +{ + __IO uint8_t tmp_1; + tmp_1 = conn; + if (tmp_1 != 0U) { + pdev->dev.user_callback->user_devconn(); + pdev->dev.connection_status = 1U; + } else { + pdev->dev.user_callback->user_devdisconn(); + pdev->dev.class_callback->class_deinit(pdev); + pdev->dev.connection_status = 0U; + } +} + +/** + * @brief Handle Suspend event + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_susp(usb_core_instance *pdev) +{ + pdev->dev.device_old_status = pdev->dev.device_cur_status; + pdev->dev.device_cur_status = USB_DEV_SUSPENDED; + pdev->dev.user_callback->user_devsusp(); +} + +/** + * @brief Handle Resume event + * @param [in] pdev device instance + * @retval None + */ +void usb_dev_resume(usb_core_instance *pdev) +{ + pdev->dev.user_callback->user_devresume(); + pdev->dev.device_cur_status = pdev->dev.device_old_status; + pdev->dev.device_cur_status = USB_DEV_CONFIGURED; +} + +/** + * @brief Handle SOF event + * @param [in] pdev device instance + * @retval None + */ +void usb_sof_process(usb_core_instance *pdev) +{ + if (0U != pdev->dev.class_callback->class_sof) { + pdev->dev.class_callback->class_sof(pdev); + } +} + +/** + * @brief Handle the setup stage + * @param [in] pdev device instance + * @retval None + */ +void usb_setup_process(usb_core_instance *pdev) +{ + USB_SETUP_REQ req; + + usb_parsesetupreq(pdev, &req); + + switch (req.bmRequest & 0x1FU) { + case USB_REQ_RECIPIENT_DEVICE: + usb_standarddevreq(pdev, &req); + break; + + case USB_REQ_RECIPIENT_INTERFACE: + usb_standarditfreq(pdev, &req); + break; + + case USB_REQ_RECIPIENT_ENDPOINT: + usb_standardepreq(pdev, &req); + break; + + default: + usb_stalldevep(pdev, req.bmRequest & 0x80U); + break; + } +} + +/** + * @brief Handle data out stage + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_dataout_process(usb_core_instance *pdev, uint8_t epnum) +{ + USB_DEV_EP *ep; + + if (epnum == 0U) { + ep = &pdev->dev.out_ep[0]; + if (pdev->dev.device_state == USB_EP0_DATA_OUT) { + if (ep->rem_data_len > ep->maxpacket) { + ep->rem_data_len -= ep->maxpacket; + + if (pdev->basic_cfgs.dmaen == 1U) { + /* in slave mode this, is handled by the RxSTSQLvl ISR */ + ep->xfer_buff += ep->maxpacket; + } + usb_readytorx(pdev, 0U, ep->xfer_buff, (uint16_t)LL_MIN(ep->rem_data_len, ep->maxpacket)); + } else { + if (ep->xfer_count > ep->rem_data_len) { + + } + ep->rem_data_len = 0UL; + if ((pdev->dev.class_callback->ep0_dataout != NULL) && + (pdev->dev.device_cur_status == USB_DEV_CONFIGURED)) { + pdev->dev.class_callback->ep0_dataout(pdev); + } + usb_ctrlstatustx(pdev); + } + } + } else if ((pdev->dev.class_callback->class_dataout != NULL) && (pdev->dev.device_cur_status == USB_DEV_CONFIGURED)) { + pdev->dev.class_callback->class_dataout(pdev, epnum); + } else { + ; + } +} + +/** + * @brief Handle data in stage + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval None + */ +void usb_datain_process(usb_core_instance *pdev, uint8_t epnum) +{ + USB_DEV_EP *ep; + + if (epnum == 0U) { + ep = &pdev->dev.in_ep[0]; + if (pdev->dev.device_state == USB_EP0_DATA_IN) { + if (ep->rem_data_len > ep->maxpacket) { + ep->rem_data_len -= ep->maxpacket; + if (pdev->basic_cfgs.dmaen == 1U) { + /* in slave mode this, is handled by the TxFifoEmpty ISR */ + ep->xfer_buff += ep->maxpacket; + } + usb_deveptx(pdev, 0U, ep->xfer_buff, ep->rem_data_len); + } else { + /* last packet is MPS multiple, so send ZLP packet */ + if ((ep->total_data_len % ep->maxpacket == 0U) && + (ep->total_data_len >= ep->maxpacket) && + (ep->total_data_len < ep->ctl_data_len)) { + usb_deveptx(pdev, 0U, NULL, 0UL); + ep->ctl_data_len = 0UL; + } else { + if ((pdev->dev.class_callback->ep0_datain != NULL) && + (pdev->dev.device_cur_status == USB_DEV_CONFIGURED)) { + pdev->dev.class_callback->ep0_datain(pdev); + } + usb_ctrlstatusrx(pdev); + } + } + } + if (pdev->dev.test_mode == 1U) { + usb_runtestmode(&pdev->regs, SET_TEST_MODE); + pdev->dev.test_mode = 0U; + } else { + } + } else if ((pdev->dev.class_callback->class_datain != NULL) && (pdev->dev.device_cur_status == USB_DEV_CONFIGURED)) { + pdev->dev.class_callback->class_datain(pdev, epnum); + } else { + ; + } +} + +/** + * @brief Handle iso in incomplete event + * @param [in] pdev device instance + * @retval None + */ +void usb_isoinincomplt_process(usb_core_instance *pdev) +{ + pdev->dev.class_callback->class_syn_in_incomplt(pdev); +} + +/** + * @brief Handle iso out incomplete event + * @param [in] pdev device instance + * @retval None + */ +void usb_isooutincomplt_process(usb_core_instance *pdev) +{ + pdev->dev.class_callback->class_syn_out_incomplt(pdev); +} + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.h new file mode 100644 index 0000000000..92a5590268 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.h @@ -0,0 +1,82 @@ +/** + ******************************************************************************* + * @file usb_dev_core.h + * @brief header file for the usb_dev_core.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_CORE_H__ +#define __USB_DEV_CORE_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern __IO uint32_t SET_TEST_MODE; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern void usb_dev_init(usb_core_instance *pdev, + usb_dev_desc_func *pdesc, + usb_dev_class_func *class_cb, + usb_dev_user_func *usr_cb); +extern void usb_dev_deinit(usb_core_instance *pdev); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_CORE_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.c new file mode 100644 index 0000000000..87aa1eae41 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.c @@ -0,0 +1,159 @@ +/** + ******************************************************************************* + * @file usb_dev_ctrleptrans.c + * @brief The IO requests APIs for control endpoints. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_ctrleptrans.h" +#include "usb_dev_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief send data on the ctl pipe + * @param [in] pdev device instance + * @param [in] pbuf pointer to data buffer + * @param [in] len length of data to be sent + * @retval None + */ +void usb_ctrldatatx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len) +{ + pdev->dev.in_ep[0].total_data_len = (uint32_t)len; + pdev->dev.in_ep[0].rem_data_len = (uint32_t)len; + pdev->dev.device_state = USB_EP0_DATA_IN; + + usb_deveptx(pdev, 0U, pbuf, (uint32_t)len); +} + +/** + * @brief continue sending data on the ctl pipe + * @param [in] pdev device instance + * @param [in] pbuf pointer to data buffer + * @param [in] len length of data to be sent + * @retval None + */ +void usb_ctrldatacontinuetx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len) +{ + usb_deveptx(pdev, 0U, pbuf, (uint32_t)len); +} + +/** + * @brief receive data on the ctl pipe + * @param [in] pdev device instance + * @param [in] pbuf pointer to data buffer + * @param [in] len length of data to be received + * @retval status + */ +void usb_ctrldatarx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len) +{ + pdev->dev.out_ep[0].total_data_len = len; + pdev->dev.out_ep[0].rem_data_len = len; + pdev->dev.device_state = USB_EP0_DATA_OUT; + + usb_readytorx(pdev, 0U, pbuf, len); +} + +/** + * @brief continue receive data on the ctl pipe + * @param [in] pdev device instance + * @param [in] pbuf pointer to data buffer + * @param [in] len length of data to be received + * @retval status + */ +void usb_ctrldatacontinuerx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len) +{ + usb_readytorx(pdev, 0U, pbuf, len); +} +/** + * @brief send zero lzngth packet on the ctl pipe + * @param [in] pdev device instance + * @retval None + */ +void usb_ctrlstatustx(usb_core_instance *pdev) +{ + pdev->dev.device_state = USB_EP0_STATUS_IN; + usb_deveptx(pdev, 0U, pdev->dev.setup_pkt_buf, 0U); +} + +/** + * @brief receive zero lzngth packet on the ctl pipe + * @param [in] pdev device instance + * @retval None + */ +void usb_ctrlstatusrx(usb_core_instance *pdev) +{ + pdev->dev.device_state = USB_EP0_STATUS_OUT; + usb_readytorx(pdev, 0U, pdev->dev.setup_pkt_buf, 0U); +} + +/** + * @brief get the received data length + * @param [in] pdev device instance + * @param [in] epnum endpoint index + * @retval Rx Data blength + */ +uint16_t usb_getrxcnt(usb_core_instance *pdev, uint8_t epnum) +{ + return (uint16_t)pdev->dev.out_ep[epnum].xfer_count; +} + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.h new file mode 100644 index 0000000000..087d6c9565 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.h @@ -0,0 +1,83 @@ +/** + ******************************************************************************* + * @file usb_dev_ctrleptrans.h + * @brief header file for the usb_dev_ctrleptrans.c file + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_CTRLEPTRANS_H__ +#define __USB_DEV_CTRLEPTRANS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern void usb_ctrldatatx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len); +extern void usb_ctrldatacontinuetx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len); +extern void usb_ctrldatarx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len); +extern void usb_ctrldatacontinuerx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len); +extern void usb_ctrlstatustx(usb_core_instance *pdev); +extern void usb_ctrlstatusrx(usb_core_instance *pdev); +extern uint16_t usb_getrxcnt(usb_core_instance *pdev, uint8_t epnum); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_CTRLEPTRANS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_def.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_def.h new file mode 100644 index 0000000000..0e1f4c62a2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_def.h @@ -0,0 +1,155 @@ +/** + ******************************************************************************* + * @file usb_dev_def.h + * @brief general defines for the usb device library + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_DEF_H__ +#define __USB_DEV_DEF_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_lib.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#ifndef NULL +#define NULL (0U) +#endif + +/* Function return status */ +#define USB_DEV_OK (0U) +#define USB_DEV_BUSY (1U) +#define USB_DEV_FAIL (2U) + +/* Device Status */ +#define USB_DEV_DEFAULT (1U) +#define USB_DEV_ADDRESSED (2U) +#define USB_DEV_CONFIGURED (3U) +#define USB_DEV_SUSPENDED (4U) + +/* String descriptor type */ +#define LANGID_STR_IDX (0x00U) +#define MFC_STR_IDX (0x01U) +#define PRODUCT_STR_IDX (0x02U) +#define SERIAL_STR_IDX (0x03U) +#define CONFIG_STR_IDX (0x04U) +#define INTERFACE_STR_IDX (0x05U) + +/* Request type */ +#define USB_REQ_TYPE_STANDARD (0x00U) +#define USB_REQ_TYPE_CLASS (0x20U) +#define USB_REQ_TYPE_VENDOR (0x40U) +#define USB_REQ_TYPE_MASK (0x60U) + +/* Request recipient */ +#define USB_REQ_RECIPIENT_DEVICE (0x00U) +#define USB_REQ_RECIPIENT_INTERFACE (0x01U) +#define USB_REQ_RECIPIENT_ENDPOINT (0x02U) +#define USB_REQ_RECIPIENT_MASK (0x03U) + +/* Standart request type */ +#define USB_REQ_GET_STATUS (0x00U) +#define USB_REQ_CLEAR_FEATURE (0x01U) +#define USB_REQ_SET_FEATURE (0x03U) +#define USB_REQ_SET_ADDRESS (0x05U) +#define USB_REQ_GET_DESCRIPTOR (0x06U) +#define USB_REQ_SET_DESCRIPTOR (0x07U) +#define USB_REQ_GET_CONFIGURATION (0x08U) +#define USB_REQ_SET_CONFIGURATION (0x09U) +#define USB_REQ_GET_INTERFACE (0x0AU) +#define USB_REQ_SET_INTERFACE (0x0BU) +#define USB_REQ_SYNCH_FRAME (0x0CU) + +/* Descriptor type */ +#define USB_DESC_TYPE_DEVICE (1U) +#define USB_DESC_TYPE_CONFIGURATION (2U) +#define USB_DESC_TYPE_STRING (3U) +#define USB_DESC_TYPE_INTERFACE (4U) +#define USB_DESC_TYPE_ENDPOINT (5U) +#define USB_DESC_TYPE_DEVICE_QUALIFIER (6U) +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION (7U) + +/* Configuration status */ +#define USB_CONFIG_REMOTE_WAKEUP (2U) +#define USB_CONFIG_SELF_POWERED (1U) + +/* USB device feature */ +#define USB_FEATURE_EP_HALT (0U) +#define USB_FEATURE_REMOTE_WAKEUP (1U) +#define USB_FEATURE_TEST_MODE (2U) + +/* USB device configuration status */ +#define USB_DEV_CONFIG_CLEAR (0U) +#define USB_DEV_CONFIG_SET (1U) +#define USB_DEV_CONFIG_GET (2U) + +/* USB EP0 state */ +#define USB_EP0_IDLE (0U) +#define USB_EP0_SETUP (1U) +#define USB_EP0_DATA_IN (2U) +#define USB_EP0_DATA_OUT (3U) +#define USB_EP0_STATUS_IN (4U) +#define USB_EP0_STATUS_OUT (5U) +#define USB_EP0_STALL (6U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_DEF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.c new file mode 100644 index 0000000000..9fe480605d --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.c @@ -0,0 +1,400 @@ +/** + ******************************************************************************* + * @file usb_dev_driver.c + * @brief Peripheral Device Interface Layer + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief Device intialize + * @param [in] pdev device instance + * @retval None + */ +void usb_initdev(usb_core_instance *pdev) +{ + uint32_t tmp_1; + USB_DEV_EP *iep, *oep; + + usb_setregaddr(&pdev->regs, &pdev->basic_cfgs); + pdev->dev.device_cur_status = (uint8_t)USB_DEV_DEFAULT; + pdev->dev.device_address = 0U; + tmp_1 = 0UL; + do { + iep = &pdev->dev.in_ep[tmp_1]; + oep = &pdev->dev.out_ep[tmp_1]; + iep->ep_dir = 1U; + oep->ep_dir = 0U; + iep->epidx = (uint8_t)tmp_1; + oep->epidx = iep->epidx; + iep->tx_fifo_num = (uint16_t)tmp_1; + oep->tx_fifo_num = iep->tx_fifo_num; + iep->trans_type = EP_TYPE_CTRL; + oep->trans_type = iep->trans_type; + iep->maxpacket = USB_MAX_EP0_SIZE; + oep->maxpacket = iep->maxpacket; + iep->xfer_buff = 0U; + oep->xfer_buff = iep->xfer_buff; + iep->xfer_len = 0UL; + oep->xfer_len = iep->xfer_len; + tmp_1++; + } while (tmp_1 < pdev->basic_cfgs.dev_epnum); + + usb_gintdis(&pdev->regs); + /*Init the Core (common init.) */ + usb_initusbcore(&pdev->regs, &pdev->basic_cfgs); + /* Force Device Mode*/ + usb_modeset(&pdev->regs, DEVICE_MODE); + /* Init Device */ + usb_devmodeinit(&pdev->regs, &pdev->basic_cfgs); + /* Enable USB Global interrupt */ + usb_ginten(&pdev->regs); +} + +/** + * @brief Configure and open an endpoint + * @param [in] pdev device instance + * @param [in] ep_addr endpoint address + * @param [in] ep_mps endpoint mps + * @param [in] ep_type endpoint type + * @retval None + */ +void usb_opendevep(usb_core_instance *pdev, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +{ + USB_DEV_EP *ep; + __IO uint8_t tmp_1, tmp_2; + + tmp_1 = ep_addr >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + tmp_2 = ep_addr & 0x7FU; /* EP number */ + if (tmp_1 == 1U) { + ep = &pdev->dev.in_ep[tmp_2]; + } else { + ep = &pdev->dev.out_ep[tmp_2]; + } + + ep->epidx = tmp_2; + + ep->ep_dir = tmp_1; + ep->maxpacket = ep_mps; + ep->trans_type = ep_type; + if (tmp_1 == 1U) { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = tmp_2; + } + /* Set initial data PID. */ + if (ep_type == EP_TYPE_BULK) { + ep->data_pid_start = 0U; + } + usb_epactive(&pdev->regs, ep); +} + +/** + * @brief called when an EP is disabled + * @param [in] pdev device instance + * @param [in] ep_addr endpoint address + * @retval None + */ +void usb_shutdevep(usb_core_instance *pdev, uint8_t ep_addr) +{ + USB_DEV_EP *ep; + __IO uint8_t tmp_1, tmp_2; + + tmp_1 = ep_addr >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + tmp_2 = ep_addr & 0x7FU; /* EP number */ + if (tmp_1 == 1U) { + ep = &pdev->dev.in_ep[tmp_2]; + } else { + ep = &pdev->dev.out_ep[tmp_2]; + } + ep->epidx = tmp_2; + ep->ep_dir = tmp_1; + usb_epdeactive(&pdev->regs, ep); +} + +/** + * @brief usb_readytorx + * @param [in] pdev device instance + * @param [in] ep_addr endpoint address + * @param [out] pbuf pointer to Rx buffer + * @param [in] buf_len data length + * @retval status + */ +void usb_readytorx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) +{ + USB_DEV_EP *ep; + __IO uint8_t tmp_1; + + tmp_1 = ep_addr & 0x7FU; /* EP number */ + ep = &pdev->dev.out_ep[tmp_1]; + /*setup and start the Xfer */ + ep->xfer_buff = pbuf; + ep->xfer_len = (uint32_t)buf_len; + ep->xfer_count = 0UL; + ep->ep_dir = 0U; + ep->epidx = tmp_1; + + if (pdev->basic_cfgs.dmaen == 1U) { + ep->dma_addr = (uint32_t)pbuf; + } + + if (tmp_1 == 0U) { + usb_ep0transbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen); + } else { + usb_epntransbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen); + } +} + +/** + * @brief configures EPO to receive SETUP packets from host + * @param [in] pdev device instance + * @retval None + */ +void usb_ep0outstart(usb_core_instance *pdev) +{ + pdev->dev.out_ep[0].xfer_len = 64U; + pdev->dev.out_ep[0].rem_data_len = 64U; + pdev->dev.out_ep[0].total_data_len = 64U; + usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf); +} + +/** + * @brief Transmit data over USB + * @param [in] pdev device instance + * @param [in] ep_addr endpoint address + * @param [in] pbuf pointer to Tx buffer + * @param [in] buf_len data length + * @retval None + */ +void usb_deveptx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len) +{ + USB_DEV_EP *ep; + __IO uint8_t tmp_1; + + tmp_1 = ep_addr & 0x7FU; /* EP number */ + ep = &pdev->dev.in_ep[tmp_1]; + + /* Setup and start the Transfer */ + ep->ep_dir = 1U; + ep->epidx = tmp_1; + ep->xfer_buff = pbuf; + ep->dma_addr = (uint32_t)pbuf; + ep->xfer_count = 0UL; + ep->xfer_len = buf_len; + + if (tmp_1 == 0U) { + usb_ep0transbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen); + } else { + usb_epntransbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen); + } +} + +/** + * @brief Stall an endpoint. + * @param [in] pdev device instance + * @param [in] epnum endpoint address + * @retval None + */ +void usb_stalldevep(usb_core_instance *pdev, uint8_t epnum) +{ + USB_DEV_EP *ep; + __IO uint8_t tmp_1, tmp_2; + + tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + tmp_2 = epnum & 0x7FU; /* EP number */ + + if (tmp_1 != 0U) { + ep = &pdev->dev.in_ep[tmp_2]; + } else { + ep = &pdev->dev.out_ep[tmp_2]; + } + + ep->ep_stall = 1U; + ep->epidx = tmp_2; + if (tmp_1 != 0U) { + ep->ep_dir = 1U; + } else { + ep->ep_dir = 0U; + } + + usb_setepstall(&pdev->regs, ep); +} + +/** + * @brief Clear stall condition on endpoints. + * @param [in] pdev device instance + * @param [in] epnum endpoint address + * @retval status + */ +void usb_clrstall(usb_core_instance *pdev, uint8_t epnum) +{ + USB_DEV_EP *ep; + __IO uint8_t tmp_1, tmp_2; + + tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + tmp_2 = epnum & 0x7FU; /* EP number */ + if (tmp_1 != 0U) { + ep = &pdev->dev.in_ep[tmp_2]; + } else { + ep = &pdev->dev.out_ep[tmp_2]; + } + + ep->ep_stall = 0U; + ep->epidx = tmp_2; + if (tmp_1 != 0U) { + ep->ep_dir = 1U; + } else { + ep->ep_dir = 0U; + } + + usb_clearepstall(&pdev->regs, ep); +} + +/** + * @brief This Function flushes the FIFOs. + * @param [in] pdev device instance + * @param [in] epnum endpoint address + * @retval status + */ +void usb_flsdevep(usb_core_instance *pdev, uint8_t epnum) +{ + __IO uint8_t tmp_1; + + tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + if (tmp_1 != 0U) { + usb_txfifoflush(&pdev->regs, (uint32_t)epnum & (uint32_t)0x7F); + } else { + usb_rxfifoflush(&pdev->regs); + } +} + +/** + * @brief This Function set USB device address + * @param [in] pdev device instance + * @param [in] devaddr new device address + * @retval None + */ +void usb_addrset(usb_core_instance *pdev, uint8_t devaddr) +{ + usb_devaddrset(&pdev->regs, devaddr); +} + +/** + * @brief control device connect or disconnect + * @param [in] pdev device instance + * @param [in] link 0(conn) or 1(disconn) + * @retval None + */ +void usb_conndevctrl(usb_core_instance *pdev, uint8_t link) +{ + usb_ctrldevconnect(&pdev->regs, link); +} + +/** + * @brief returns the EP Status + * @param [in] pdev device instance + * @param [in] epnum endpoint address + * @retval EP status + */ +uint32_t usb_devepstatusget(usb_core_instance *pdev, uint8_t epnum) +{ + USB_DEV_EP *ep; + uint32_t Status; + __IO uint8_t tmp_1, tmp_2; + + tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + tmp_2 = epnum & 0x7FU; /* EP number */ + if (tmp_1 != 0U) { + ep = &pdev->dev.in_ep[tmp_2]; + } else { + ep = &pdev->dev.out_ep[tmp_2]; + } + + Status = usb_epstatusget(&pdev->regs, ep); + /* Return the current status */ + return Status; +} + +/** + * @brief Set the EP Status + * @param [in] pdev device instance + * @param [in] status new Status + * @param [in] epnum EP address + * @retval None + */ +void usb_devepstatusset(usb_core_instance *pdev, uint8_t epnum, uint32_t status) +{ + USB_DEV_EP *ep; + __IO uint8_t tmp_1, tmp_2; + + tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + tmp_2 = epnum & 0x7FU; /* EP number */ + if (tmp_1 != 0U) { + ep = &pdev->dev.in_ep[tmp_2]; + } else { + ep = &pdev->dev.out_ep[tmp_2]; + } + + usb_epstatusset(&pdev->regs, ep, status); +} + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.h new file mode 100644 index 0000000000..2cb904a73c --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.h @@ -0,0 +1,89 @@ +/** + ******************************************************************************* + * @file usb_dev_driver.h + * @brief Peripheral Driver Header file + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_DRIVER_H__ +#define __USB_DEV_DRIVER_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern void usb_initdev(usb_core_instance *pdev); +extern void usb_conndevctrl(usb_core_instance *pdev, uint8_t link); +extern void usb_addrset(usb_core_instance *pdev, uint8_t devaddr); +extern void usb_opendevep(usb_core_instance *pdev, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +extern void usb_shutdevep(usb_core_instance *pdev, uint8_t ep_addr); +extern void usb_readytorx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); +extern void usb_ep0outstart(usb_core_instance *pdev); +extern void usb_deveptx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len); +extern void usb_stalldevep(usb_core_instance *pdev, uint8_t epnum); +extern void usb_clrstall(usb_core_instance *pdev, uint8_t epnum); +extern void usb_flsdevep(usb_core_instance *pdev, uint8_t epnum); +extern uint32_t usb_devepstatusget(usb_core_instance *pdev, uint8_t epnum); +extern void usb_devepstatusset(usb_core_instance *pdev, uint8_t epnum, uint32_t status); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_DRIVER_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.c new file mode 100644 index 0000000000..fa53d98549 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.c @@ -0,0 +1,456 @@ +/** + ******************************************************************************* + * @file usb_dev_int.c + * @brief Peripheral Device interrupt subroutines. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_int.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief read the endpoint flags + * @param [in] pdev device instance + * @param [in] epnum endpoint number + * @retval status + */ +static uint32_t usb_rddevinep(usb_core_instance *pdev, uint8_t epnum) +{ + uint32_t u32diepmsk; + uint32_t u32diepempmsk; + u32diepmsk = READ_REG32(pdev->regs.DREGS->DIEPMSK); + u32diepempmsk = READ_REG32(pdev->regs.DREGS->DIEPEMPMSK); + u32diepmsk |= (((u32diepempmsk >> epnum) & 0x1UL) << 7U); + return (READ_REG32(pdev->regs.INEP_REGS[epnum]->DIEPINT) & u32diepmsk); +} + +/** + * @brief check FIFO for the next packet to be loaded + * @param [in] pdev device instance + * @param [in] epnum endpoint number + * @retval None + */ +static void usb_wrblanktxfifo(usb_core_instance *pdev, uint32_t epnum) +{ + USB_DEV_EP *ep; + uint32_t u32Len; + uint32_t u32Len32b; + uint16_t u16spclen; + uint32_t u32diepempmsk; + + ep = &pdev->dev.in_ep[epnum]; + u32Len = ep->xfer_len - ep->xfer_count; + if (u32Len > ep->maxpacket) { + u32Len = ep->maxpacket; + } + u32Len32b = (u32Len + 3UL) >> 2; + u16spclen = usb_rdineptxfspcavail(pdev, epnum); + while ((u16spclen >= u32Len32b) && (ep->xfer_count < ep->xfer_len)) { + u32Len = ep->xfer_len - ep->xfer_count; + + if (u32Len > ep->maxpacket) { + u32Len = ep->maxpacket; + } + u32Len32b = (u32Len + 3UL) >> 2; + usb_wrpkt(&pdev->regs, ep->xfer_buff, (uint8_t)epnum, (uint16_t)u32Len, pdev->basic_cfgs.dmaen); + ep->xfer_buff += u32Len; + ep->xfer_count += u32Len; + u16spclen = usb_rdineptxfspcavail(pdev, epnum); + } + + if (u32Len == 0UL) { + u32diepempmsk = 0x01UL << epnum; + CLR_REG32_BIT(pdev->regs.DREGS->DIEPEMPMSK, u32diepempmsk); + } +} + +#ifdef VBUS_SENSING_ENABLED +/** + * @brief Indicates that the USB_OTG controller has detected a connection + * @param [in] pdev device instance + * @retval None + */ +static void usb_sessionrequest_isr(usb_core_instance *pdev) +{ + dev_int_cbkpr->devctrlconnect(pdev, 1U); + + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_VBUSVINT); + + if (0U != pdev->basic_cfgs.low_power) { + CLR_REG32_BIT(*pdev->regs.GCCTL, USBFS_GCCTL_STPPCLK | USBFS_GCCTL_GATEHCLK); + } +} +#endif + +/** + * @brief Indicates that the controller has detected a resume or remote Wake-up sequence + * @param [in] pdev device instance + * @retval None + */ +static void usb_resume_isr(usb_core_instance *pdev) +{ + if (0U != pdev->basic_cfgs.low_power) { + CLR_REG32_BIT(*pdev->regs.GCCTL, USBFS_GCCTL_STPPCLK | USBFS_GCCTL_GATEHCLK); + } + + CLR_REG32_BIT(pdev->regs.DREGS->DCTL, USBFS_DCTL_RWUSIG); + + dev_int_cbkpr->Resume(pdev); + + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_WKUINT); +} + +/** + * @brief Indicates that SUSPEND state has been detected on the USB + * @param [in] pdev device instance + * @retval None + */ +static void usb_susp_isr(usb_core_instance *pdev) +{ + uint32_t u32dsts; + uint8_t u8PrevStatus; + + dev_int_cbkpr->Suspend(pdev); + u32dsts = READ_REG32(pdev->regs.DREGS->DSTS); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_USBSUSP); + + u8PrevStatus = pdev->dev.device_cur_status; + if ((u8PrevStatus == USB_DEV_CONFIGURED) && + (0U != pdev->basic_cfgs.low_power) && ((u32dsts & 1UL) != 0UL) && + (pdev->dev.connection_status == 1U)) { + SET_REG32_BIT(*pdev->regs.GCCTL, USBFS_GCCTL_STPPCLK); + SET_REG32_BIT(*pdev->regs.GCCTL, USBFS_GCCTL_GATEHCLK); + } +} + +/** + * @brief Indicates that at leadt one IN EP has a pending interrupt + * @param [in] pdev device instance + * @retval None + */ +static void usb_inep_isr(usb_core_instance *pdev) +{ + uint32_t u32diepint; + uint32_t u32EpIntr; + uint8_t u8epnum; + uint32_t u32diepempmsk; + + u32EpIntr = usb_getalliepintr(&pdev->regs); + u8epnum = 0U; + while ((0U != u32EpIntr) && (u8epnum <= USB_MAX_TX_FIFOS)) { + if ((u32EpIntr & 0x1UL) != 0UL) { + u32diepint = usb_rddevinep(pdev, u8epnum); + if ((u32diepint & XFER_COMPL) != 0UL) { + u32diepempmsk = 1UL << u8epnum; + CLR_REG32_BIT(pdev->regs.DREGS->DIEPEMPMSK, u32diepempmsk); + WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, XFER_COMPL); + dev_int_cbkpr->DataInStage(pdev, u8epnum); + if (pdev->basic_cfgs.dmaen == 1U) { + if ((u8epnum == 0U) && (pdev->dev.device_state == USB_EP0_STATUS_IN)) { + pdev->dev.out_ep[0].xfer_len = 64U; + pdev->dev.out_ep[0].rem_data_len = 64U; + pdev->dev.out_ep[0].total_data_len = 64U; + usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf); + pdev->dev.device_state = USB_EP0_IDLE; + } + } + } + if ((u32diepint & EPDISABLED) != 0UL) { + WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, EPDISABLED); + } + if ((u32diepint & TIME_OUT) != 0UL) { + WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, TIME_OUT); + } + if ((u32diepint & INTKNTXFEMP) != 0UL) { + WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, INTKNTXFEMP); + } + if ((u32diepint & INEPNAKEFF) != 0UL) { + WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, INEPNAKEFF); + } + if ((u32diepint & TXFEMP) != 0UL) { + usb_wrblanktxfifo(pdev, u8epnum); + WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, TXFEMP); + } + } + u8epnum++; + u32EpIntr >>= 1U; + } +} + +/** + * @brief Indicates that an OUT EP has a pending Interrupt + * @param [in] pdev device instance + * @retval None + */ +static void usb_outep_isr(usb_core_instance *pdev) +{ + uint32_t u32EpIntr; + uint32_t u32doepint; + uint8_t u8epnum = 0U; + uint32_t u8Xfer; + uint32_t u32ReadEpSize; + + u32EpIntr = usb_getalloepintr(&pdev->regs); + while ((u32EpIntr != 0UL) && (u8epnum <= USB_MAX_TX_FIFOS)) { + if ((u32EpIntr & 0x1UL) != 0UL) { + u32doepint = usb_getoepintbit(&pdev->regs, u8epnum); + if ((u32doepint & XFER_COMPL) != 0UL) { + WRITE_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPINT, XFER_COMPL); + if (pdev->basic_cfgs.dmaen == 1U) { + u32ReadEpSize = (READ_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPTSIZ) & USBFS_DOEPTSIZ_XFRSIZ); + u8Xfer = LL_MIN(pdev->dev.out_ep[u8epnum].maxpacket, pdev->dev.out_ep[u8epnum].xfer_len); + pdev->dev.out_ep[u8epnum].xfer_count = u8Xfer - u32ReadEpSize; + if (u8epnum != 0U) { + pdev->dev.out_ep[u8epnum].xfer_count = pdev->dev.out_ep[u8epnum].xfer_len - u32ReadEpSize; + } + } + dev_int_cbkpr->DataOutStage(pdev, u8epnum); + if (pdev->basic_cfgs.dmaen == 1U) { + if ((u8epnum == 0U) && (pdev->dev.device_state == USB_EP0_STATUS_OUT)) { + pdev->dev.out_ep[0].xfer_len = 64U; + pdev->dev.out_ep[0].rem_data_len = 64U; + pdev->dev.out_ep[0].total_data_len = 64U; + usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf); + pdev->dev.device_state = USB_EP0_IDLE; + } + } + } + if ((u32doepint & EPDISABLED) != 0UL) { + WRITE_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPINT, EPDISABLED); + } + if (u8epnum == 0U) { + u32doepint = usb_getoepintbit(&pdev->regs, u8epnum); + if ((u32doepint & SETUP_BIT) != 0UL) { + dev_int_cbkpr->SetupStage(pdev); + WRITE_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPINT, SETUP_BIT); + } + } + } + u8epnum++; + u32EpIntr >>= 1U; + } +} + +/** + * @brief Handles the SOF Interrupts + * @param [in] pdev device instance + * @retval None + */ +static void usb_sof_isr(usb_core_instance *pdev) +{ + dev_int_cbkpr->SOF(pdev); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_SOF); +} + +/** + * @brief Handles the Rx Status Queue Level Interrupt + * @param [in] pdev device instance + * @retval status + */ +static void usb_rxstsqlvl_isr(usb_core_instance *pdev) +{ + uint32_t u32grxsts; + USB_DEV_EP *ep; + uint8_t u8epnum; + uint8_t u8PktStatus; + uint16_t u16ByteCnt; + + CLR_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTMSK_RXFNEM); + + u32grxsts = READ_REG32(pdev->regs.GREGS->GRXSTSP); + u8epnum = (uint8_t)(u32grxsts & USBFS_GRXSTSP_CHNUM_EPNUM); + u8PktStatus = (uint8_t)((u32grxsts & USBFS_GRXSTSP_PKTSTS) >> USBFS_GRXSTSP_PKTSTS_POS); + u16ByteCnt = (uint16_t)((u32grxsts & USBFS_GRXSTSP_BCNT) >> USBFS_GRXSTSP_BCNT_POS); + ep = &pdev->dev.out_ep[u8epnum]; + switch (u8PktStatus) { + case STS_DATA_UPDT: + if (0U != u16ByteCnt) { + usb_rdpkt(&pdev->regs, ep->xfer_buff, u16ByteCnt); + ep->xfer_buff += u16ByteCnt; + ep->xfer_count += u16ByteCnt; + } else { + ; + } + break; + case STS_SETUP_UPDT: + /* Copy the setup packet received in FIFO into the setup buffer in RAM */ + usb_rdpkt(&pdev->regs, pdev->dev.setup_pkt_buf, 8U); + ep->xfer_count += u16ByteCnt; + break; + case STS_GOUT_NAK: + case STS_XFER_COMP: + case STS_SETUP_COMP: + break; + default: + break; + } + SET_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTMSK_RXFNEM); +} + +/** + * @brief This interrupt occurs when a USB Reset is detected + * @param [in] pdev device instance + * @retval None + */ +static void usb_reset_isr(usb_core_instance *pdev) +{ + uint32_t i; + + CLR_REG32_BIT(pdev->regs.DREGS->DCTL, USBFS_DCTL_RWUSIG); + usb_txfifoflush(&pdev->regs, 0UL); + for (i = 0UL; i < pdev->basic_cfgs.dev_epnum ; i++) { + WRITE_REG32(pdev->regs.INEP_REGS[i]->DIEPINT, 0xFFUL); + WRITE_REG32(pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFFUL); + } + WRITE_REG32(pdev->regs.DREGS->DAINT, 0xFFFFFFFFUL); + WRITE_REG32(pdev->regs.DREGS->DAINTMSK, 1UL | (1UL << USBFS_DAINTMSK_OEPINTM_POS)); + //todo: bit5 if need be set? + WRITE_REG32(pdev->regs.DREGS->DOEPMSK, USBFS_DOEPMSK_STUPM | USBFS_DOEPMSK_XFRCM | USBFS_DOEPMSK_EPDM); +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + WRITE_REG32(pdev->regs.DREGS->DOUTEP1MSK, USBFS_DOEPMSK_STUPM | USBFS_DOEPMSK_XFRCM | USBFS_DOEPMSK_EPDM); +#endif + + WRITE_REG32(pdev->regs.DREGS->DIEPMSK, USBFS_DIEPMSK_XFRCM | USBFS_DIEPMSK_TOM | USBFS_DIEPMSK_EPDM); +#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED + WRITE_REG32(pdev->regs.DREGS->DINEP1MSK, USBFS_DIEPMSK_XFRCM | USBFS_DIEPMSK_TOM | USBFS_DIEPMSK_EPDM); +#endif + + CLR_REG32_BIT(pdev->regs.DREGS->DCFG, USBFS_DCFG_DAD); + pdev->dev.out_ep[0].xfer_len = 64U; + pdev->dev.out_ep[0].rem_data_len = 64U; + pdev->dev.out_ep[0].total_data_len = 64U; + usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_USBRST); + + dev_int_cbkpr->Reset(pdev); +} + +/** + * @brief Read the device status register and set the device speed + * @param [in] pdev device instance + * @retval None + */ +static void usb_enumfinish_isr(usb_core_instance *pdev) +{ + usb_ep0activate(&pdev->regs); + usb_setaroundtim(pdev); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_ENUMDNE); +} + +/** + * @brief handle the ISO IN incomplete interrupt + * @param [in] pdev device instance + * @retval None + */ +static void usb_isoinincomplt_isr(usb_core_instance *pdev) +{ + dev_int_cbkpr->IsoINIncomplete(pdev); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_IISOIXFR); +} + +/** + * @brief handle the ISO OUT incomplete interrupt + * @param [in] pdev device instance + * @retval None + */ +static void usb_isooutincomplt_isr(usb_core_instance *pdev) +{ + dev_int_cbkpr->IsoOUTIncomplete(pdev); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_IPXFR_INCOMPISOOUT); +} + +/** + * @brief handles all USB Interrupts + * @param [in] pdev device instance + * @retval None + */ +void usb_isr_handler(usb_core_instance *pdev) +{ + uint32_t u32gintsts; + + if (0U == usb_getcurmod(&pdev->regs)) { + u32gintsts = usb_getcoreintr(&pdev->regs); + if (u32gintsts == 0UL) { + return; + } + if ((u32gintsts & OUTEP_INT) != 0UL) { + usb_outep_isr(pdev); + } + if ((u32gintsts & INEP_INT) != 0UL) { + usb_inep_isr(pdev); + } + if ((u32gintsts & MODEMIS_INT) != 0UL) { + WRITE_REG32(pdev->regs.GREGS->GINTSTS, MODEMIS_INT); + } + if ((u32gintsts & WAKEUP_INT) != 0UL) { + usb_resume_isr(pdev); + } + if ((u32gintsts & USBSUSP_INT) != 0UL) { + usb_susp_isr(pdev); + } + if ((u32gintsts & SOF_INT) != 0UL) { + usb_sof_isr(pdev); + } + if ((u32gintsts & RXFLVL_INT) != 0UL) { + usb_rxstsqlvl_isr(pdev); + } + if ((u32gintsts & USBRST_INT) != 0UL) { + usb_reset_isr(pdev); + } + if ((u32gintsts & ENUMDONE_INT) != 0UL) { + usb_enumfinish_isr(pdev); + } + if ((u32gintsts & INCOMPLSOIN) != 0UL) { + usb_isoinincomplt_isr(pdev); + } + if ((u32gintsts & INCOMPLSOOUT) != 0UL) { + usb_isooutincomplt_isr(pdev); + } +#ifdef VBUS_SENSING_ENABLED + if ((u32gintsts & VBUSV_INT) != 0UL) { + usb_sessionrequest_isr(pdev); + } +#endif + } +} + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.h new file mode 100644 index 0000000000..f8b2deea19 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.h @@ -0,0 +1,136 @@ +/** + ******************************************************************************* + * @file usb_dev_int.h + * @brief Peripheral Device Interface Layer + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_INT_H__ +#define __USB_DEV_INT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* The bit of the diepint/doepint */ +#define XFER_COMPL (1UL) +#define EPDISABLED (1UL<<1) +#define TIME_OUT (1UL<<3) +#define SETUP_BIT (1UL<<3) +#define INTKNTXFEMP (1UL<<4) +#define INEPNAKEFF (1UL<<6) +#define TXFEMP (1UL<<7) + +/* The bit of the GINTSTS */ +#define MODEMIS_INT (1UL<<1) +#define SOF_INT (1UL<<3) +#define RXFLVL_INT (1UL<<4) +#define USBSUSP_INT (1UL<<11) +#define USBRST_INT (1UL<<12) +#define ENUMDONE_INT (1UL<<13) +#define INEP_INT (1UL<<18) +#define OUTEP_INT (1UL<<19) +#define INCOMPLSOIN (1UL<<20) +#define INCOMPLSOOUT (1UL<<21) +#define VBUSV_INT (1UL<<30) +#define WAKEUP_INT (1UL<<31) + +/* Data packet status for device mode */ +#define STS_GOUT_NAK (1U) +#define STS_DATA_UPDT (2U) +#define STS_XFER_COMP (3U) +#define STS_SETUP_COMP (4U) +#define STS_SETUP_UPDT (6U) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef struct { + void (* Reset)(usb_core_instance *pdev); + void (* devctrlconnect)(usb_core_instance *pdev, uint8_t conn); + void (* Suspend)(usb_core_instance *pdev); + void (* Resume)(usb_core_instance *pdev); + void (* SOF)(usb_core_instance *pdev); + void (* SetupStage)(usb_core_instance *pdev); + void (* DataOutStage)(usb_core_instance *pdev, uint8_t epnum); + void (* DataInStage)(usb_core_instance *pdev, uint8_t epnum); + void (* IsoINIncomplete)(usb_core_instance *pdev); + void (* IsoOUTIncomplete)(usb_core_instance *pdev); +} usb_dev_int_cbk_typedef; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @brief get the IN Endpoint TxFIFO avail space + * @param [in] pdev device instance + * @param [in] epnum endpoint number + * @retval the avail space in 32-bit words + */ +__STATIC_INLINE uint16_t usb_rdineptxfspcavail(usb_core_instance *pdev, uint32_t epnum) +{ + return (uint16_t)(READ_REG32(pdev->regs.INEP_REGS[epnum]->DTXFSTS) & USBFS_DTXFSTS_INEPTFSAV); +} + +/** + * @brief set the USB turn around time + * @param [in] pdev device instance + * @retval None + */ +__STATIC_INLINE void usb_setaroundtim(usb_core_instance *pdev) +{ + SET_REG32_BIT(pdev->regs.GREGS->GUSBCFG, USBFS_GUSBCFG_TRDT); +} + +extern usb_dev_int_cbk_typedef *dev_int_cbkpr; +extern void usb_isr_handler(usb_core_instance *pdev); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_INT_H__ */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.c new file mode 100644 index 0000000000..c1e7cf7f3a --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.c @@ -0,0 +1,606 @@ +/** + ******************************************************************************* + * @file usb_dev_stdreq.c + * @brief The standard USB requests following chapter 9. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "usb_dev_core.h" +#include "usb_dev_stdreq.h" +#include "usb_dev_driver.h" +#include "usb_dev_ctrleptrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +static __USB_ALIGN_BEGIN uint32_t dev_ep_status = 0UL; +static __USB_ALIGN_BEGIN uint32_t dev_default_cfg = 0UL; +static __USB_ALIGN_BEGIN uint32_t dev_cfg_status = 0UL; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_getdesc(usb_core_instance *pdev, const USB_SETUP_REQ *req); +void usb_setaddr(usb_core_instance *pdev, const USB_SETUP_REQ *req); +void usb_setconfig(usb_core_instance *pdev, const USB_SETUP_REQ *req); +void usb_getconfig(usb_core_instance *pdev, const USB_SETUP_REQ *req); +void usb_getstatus(usb_core_instance *pdev, const USB_SETUP_REQ *req); +void usb_getintf(usb_core_instance *pdev); +void usb_setfeature(usb_core_instance *pdev, USB_SETUP_REQ *req); +void usb_clrfeature(usb_core_instance *pdev, USB_SETUP_REQ *req); +uint8_t usb_getlength(uint8_t *buf); +void usb_dev_ctrlconfig(usb_core_instance *pdev, uint8_t cfgidx, uint8_t action); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Handle standard usb device requests + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_standarddevreq(usb_core_instance *pdev, USB_SETUP_REQ *req) +{ + if (req->bRequest == USB_REQ_GET_DESCRIPTOR) { + usb_getdesc(pdev, req) ; + } else if (req->bRequest == USB_REQ_SET_ADDRESS) { + usb_setaddr(pdev, req); + } else if (req->bRequest == USB_REQ_SET_CONFIGURATION) { + usb_setconfig(pdev, req); + } else if (req->bRequest == USB_REQ_GET_CONFIGURATION) { + usb_getconfig(pdev, req); + } else if (req->bRequest == USB_REQ_GET_STATUS) { + usb_getstatus(pdev, req); + } else if (req->bRequest == USB_REQ_SET_FEATURE) { + usb_setfeature(pdev, req); + } else if (req->bRequest == USB_REQ_CLEAR_FEATURE) { + usb_clrfeature(pdev, req); + } else { + if (0U != pdev->dev.class_callback->ep0_setup(pdev, req)) { + usb_ctrlerr(pdev); + } + } +} + +/** + * @brief Handle standard usb interface requests + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_standarditfreq(usb_core_instance *pdev, USB_SETUP_REQ *req) +{ + uint8_t u8RetFlag = 0U; + + if (req->bRequest == USB_REQ_GET_STATUS) { + usb_getstatus(pdev, req); + u8RetFlag = 1U; + } else if (req->bRequest == USB_REQ_GET_INTERFACE) { + if (req->bmRequest != 0x21U) { + usb_getintf(pdev); + u8RetFlag = 1U; + } + } else if (req->bRequest == 0xFEU) { + usb_getintf(pdev); + u8RetFlag = 1U; + } else { + ; + } + + if (1U != u8RetFlag) { + if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) { + if (LOBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { + pdev->dev.class_callback->ep0_setup(pdev, req); + if (req->wLength == 0U) { + usb_ctrlstatustx(pdev); + } + } else { + usb_ctrlerr(pdev); + } + } else { + usb_ctrlerr(pdev); + } + } +} + +/** + * @brief Handle standard usb endpoint requests + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_standardepreq(usb_core_instance *pdev, USB_SETUP_REQ *req) +{ + __IO uint8_t ep_addr; + ep_addr = LOBYTE(req->wIndex); + + switch (req->bRequest) { + case USB_REQ_SET_FEATURE : + switch (pdev->dev.device_cur_status) { + case USB_DEV_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) { + usb_stalldevep(pdev, ep_addr); + } + break; + case USB_DEV_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) { + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) { + usb_stalldevep(pdev, ep_addr); + } + } + pdev->dev.class_callback->ep0_setup(pdev, req); + usb_ctrlstatustx(pdev); + break; + default: + usb_ctrlerr(pdev); + break; + } + break; + case USB_REQ_CLEAR_FEATURE : + switch (pdev->dev.device_cur_status) { + case USB_DEV_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) { + usb_stalldevep(pdev, ep_addr); + } + break; + case USB_DEV_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) { + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) { + usb_clrstall(pdev, ep_addr); + pdev->dev.class_callback->ep0_setup(pdev, req); + } + usb_ctrlstatustx(pdev); + } + break; + default: + usb_ctrlerr(pdev); + break; + } + break; + case USB_REQ_GET_STATUS: + switch (pdev->dev.device_cur_status) { + case USB_DEV_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) { + usb_stalldevep(pdev, ep_addr); + } + break; + case USB_DEV_CONFIGURED: + if ((ep_addr & 0x80U) == 0x80U) { + if (0U != pdev->dev.in_ep[ep_addr % USB_MAX_TX_FIFOS].ep_stall) { + dev_ep_status = 0x0001U; + } else { + dev_ep_status = 0x0000U; + } + } else if ((ep_addr & 0x80U) == 0x00U) { + if (0U != pdev->dev.out_ep[ep_addr % USB_MAX_TX_FIFOS].ep_stall) { + dev_ep_status = 0x0001U; + } else { + dev_ep_status = 0x0000U; + } + } else { + ; + } + usb_ctrldatatx(pdev, (uint8_t *)&dev_ep_status, 2U); + break; + + default: + usb_ctrlerr(pdev); + break; + } + break; + default: + break; + } +} + +/** + * @brief Handle Get Descriptor requests + * @param [in] pdev device instance + * @param [in] req usb request + * @retval status + */ +void usb_getdesc(usb_core_instance *pdev, const USB_SETUP_REQ *req) +{ + uint16_t len = 0U; + uint8_t *pbuf = NULL; + uint8_t u8ErrFlag = 0U; + + switch (req->wValue >> 8U) { + case USB_DESC_TYPE_DEVICE: + pbuf = pdev->dev.desc_callback->get_dev_desc(&len); + break; + case USB_DESC_TYPE_CONFIGURATION: + pbuf = (uint8_t *)pdev->dev.class_callback->class_getconfigdesc(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + break; + case USB_DESC_TYPE_STRING: + switch ((uint8_t)(req->wValue)) { + case LANGID_STR_IDX: + pbuf = pdev->dev.desc_callback->get_dev_langiddesc(&len); + break; + case MFC_STR_IDX: + pbuf = pdev->dev.desc_callback->get_dev_manufacturerstr(&len); + break; + case PRODUCT_STR_IDX: + pbuf = pdev->dev.desc_callback->get_dev_productstr(&len); + break; + case SERIAL_STR_IDX: + pbuf = pdev->dev.desc_callback->get_dev_serialstr(&len); + break; + case CONFIG_STR_IDX: + pbuf = pdev->dev.desc_callback->get_dev_configstr(&len); + break; + case INTERFACE_STR_IDX: + pbuf = pdev->dev.desc_callback->get_dev_interfacestr(&len); + break; + default: + usb_ctrlerr(pdev); + u8ErrFlag = 1U; + break; + } + break; + case USB_DESC_TYPE_DEVICE_QUALIFIER: + usb_ctrlerr(pdev); + u8ErrFlag = 1U; + break; + case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: + usb_ctrlerr(pdev); + u8ErrFlag = 1U; + break; + default: + usb_ctrlerr(pdev); + u8ErrFlag = 1U; + break; + } + + if (0U == u8ErrFlag) { + if ((len != 0U) && (req->wLength != 0U)) { + len = LL_MIN(len, req->wLength); + usb_ctrldatatx(pdev, pbuf, len); + } + } +} + +/** + * @brief Set device address + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_setaddr(usb_core_instance *pdev, const USB_SETUP_REQ *req) +{ + uint8_t dev_addr; + + if ((req->wIndex == 0U) && (req->wLength == 0U)) { + dev_addr = (uint8_t)(req->wValue) & 0x7Fu; + + if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) { + usb_ctrlerr(pdev); + } else { + pdev->dev.device_address = dev_addr; + usb_addrset(pdev, dev_addr); + usb_ctrlstatustx(pdev); + + if (dev_addr != 0U) { + pdev->dev.device_cur_status = USB_DEV_ADDRESSED; + } else { + pdev->dev.device_cur_status = USB_DEV_DEFAULT; + } + } + } else { + usb_ctrlerr(pdev); + } +} + +/** + * @brief Handle Set device configuration request + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_setconfig(usb_core_instance *pdev, const USB_SETUP_REQ *req) +{ + static uint8_t tmp_cfgidx; + + tmp_cfgidx = (uint8_t)(req->wValue); + + if (tmp_cfgidx > DEV_MAX_CFG_NUM) { + usb_ctrlerr(pdev); + } else { + switch (pdev->dev.device_cur_status) { + case USB_DEV_ADDRESSED: + if (0U != tmp_cfgidx) { + pdev->dev.device_config = tmp_cfgidx; + pdev->dev.device_cur_status = USB_DEV_CONFIGURED; + usb_dev_ctrlconfig(pdev, tmp_cfgidx, USB_DEV_CONFIG_SET); + usb_ctrlstatustx(pdev); + } else { + usb_ctrlstatustx(pdev); + } + break; + case USB_DEV_CONFIGURED: + if (tmp_cfgidx == 0U) { + pdev->dev.device_cur_status = USB_DEV_ADDRESSED; + pdev->dev.device_config = tmp_cfgidx; + usb_dev_ctrlconfig(pdev, tmp_cfgidx, USB_DEV_CONFIG_CLEAR); + usb_ctrlstatustx(pdev); + } else if (tmp_cfgidx != pdev->dev.device_config) { + /* Clear old configuration */ + usb_dev_ctrlconfig(pdev, pdev->dev.device_config, USB_DEV_CONFIG_CLEAR); + /* set new configuration */ + pdev->dev.device_config = tmp_cfgidx; + usb_dev_ctrlconfig(pdev, tmp_cfgidx, USB_DEV_CONFIG_SET); + usb_ctrlstatustx(pdev); + } else { + usb_ctrlstatustx(pdev); + } + break; + case USB_DEV_SUSPENDED: + + break; + default: + usb_ctrlerr(pdev); + break; + } + } +} + +/** + * @brief Handle Get device configuration request + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_getconfig(usb_core_instance *pdev, const USB_SETUP_REQ *req) +{ + if (req->wLength != 1U) { + usb_ctrlerr(pdev); + } else { + switch (pdev->dev.device_cur_status) { + case USB_DEV_ADDRESSED: + usb_ctrldatatx(pdev, (uint8_t *)&dev_default_cfg, 1U); + break; + case USB_DEV_CONFIGURED: + usb_ctrldatatx(pdev, (uint8_t *)&pdev->dev.device_config, 1U); + break; + default: + usb_ctrlerr(pdev); + break; + } + } +} + +/** + * @brief Handle Get Status request + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_getstatus(usb_core_instance *pdev, const USB_SETUP_REQ *req) +{ + (void)(req); + switch (pdev->dev.device_cur_status) { + case USB_DEV_ADDRESSED: + case USB_DEV_CONFIGURED: +#ifdef SELF_POWER + dev_cfg_status = USB_CONFIG_SELF_POWERED; +#else + dev_cfg_status = 0x00U; +#endif + if (0U != pdev->dev.device_remote_wakeup) { + dev_cfg_status |= USB_CONFIG_REMOTE_WAKEUP; + } + usb_ctrldatatx(pdev, (uint8_t *)&dev_cfg_status, 2U); + break; + default : + usb_ctrlerr(pdev); + break; + } +} + +/** + * @brief usb_getintf + * @param [in] pdev device instance + * @retval None + */ +void usb_getintf(usb_core_instance *pdev) +{ + dev_cfg_status = 0U; + usb_ctrldatatx(pdev, (uint8_t *)&dev_cfg_status, 1U); +} + +/** + * @brief Handle Set device feature request + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_setfeature(usb_core_instance *pdev, USB_SETUP_REQ *req) +{ + uint32_t dctl; + uint8_t test_mode; + + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) { + pdev->dev.device_remote_wakeup = 1U; + pdev->dev.class_callback->ep0_setup(pdev, req); + usb_ctrlstatustx(pdev); + } else if ((req->wValue == USB_FEATURE_TEST_MODE) && ((req->wIndex & 0xFFU) == 0U)) { + dctl = READ_REG32(pdev->regs.DREGS->DCTL); + test_mode = (uint8_t)req->wIndex >> 8U; + test_mode = test_mode & (uint8_t)(~0xF8U); + dctl = (uint32_t)test_mode << 4U; + SET_TEST_MODE = dctl; + pdev->dev.test_mode = 1U; + usb_ctrlstatustx(pdev); + } else { + ; + } +} + +/** + * @brief Handle clear device feature request + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_clrfeature(usb_core_instance *pdev, USB_SETUP_REQ *req) +{ + switch (pdev->dev.device_cur_status) { + case USB_DEV_ADDRESSED: + case USB_DEV_CONFIGURED: + if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) { + pdev->dev.device_remote_wakeup = 0U; + pdev->dev.class_callback->ep0_setup(pdev, req); + usb_ctrlstatustx(pdev); + } + break; + default : + usb_ctrlerr(pdev); + break; + } +} + +/** + * @brief Copy buffer into setup structure + * @param [in] pdev device instance + * @param [in] req usb request + * @retval None + */ +void usb_parsesetupreq(usb_core_instance *pdev, USB_SETUP_REQ *req) +{ + req->bmRequest = *(uint8_t *)(pdev->dev.setup_pkt_buf); + req->bRequest = *(uint8_t *)(pdev->dev.setup_pkt_buf + 1U); + req->wValue = SWAPBYTE(pdev->dev.setup_pkt_buf + 2U); + req->wIndex = SWAPBYTE(pdev->dev.setup_pkt_buf + 4U); + req->wLength = SWAPBYTE(pdev->dev.setup_pkt_buf + 6U); + + pdev->dev.in_ep[0].ctl_data_len = req->wLength; + pdev->dev.device_state = USB_EP0_SETUP; +} + +/** + * @brief Handle USB low level Error + * @param [in] pdev device instance + * @retval None + */ +void usb_ctrlerr(usb_core_instance *pdev) +{ + usb_stalldevep(pdev, 0x80U); + usb_stalldevep(pdev, 0U); + usb_ep0outstart(pdev); +} + +/** + * @brief Convert Ascii string into unicode one + * @param [in] desc descriptor buffer + * @param [in] unicode Formatted string buffer (unicode) + * @param [in] len descriptor length + * @retval None + */ +void usb_getstring(uint8_t *desc, uint8_t *unicode, uint16_t *len) +{ + uint8_t tmp_idx = 0U; + + if (desc != NULL) { + *len = (uint16_t)usb_getlength(desc) * 2U + 2U; + unicode[tmp_idx++] = (uint8_t) * len; + unicode[tmp_idx++] = USB_DESC_TYPE_STRING; + + while (*desc != (uint8_t)0U) { + unicode[tmp_idx++] = *desc++; + unicode[tmp_idx++] = 0x00U; + } + } +} + +/** + * @brief get the string length + * @param [in] buf pointer to the ascii string buffer + * @retval string length + */ +uint8_t usb_getlength(uint8_t *buf) +{ + uint8_t tmp_len = 0U; + + while (*buf != (uint8_t)0U) { + tmp_len++; + buf++; + } + return tmp_len; +} + +/** + * @brief set current configuration or clear current configuration + * @param [in] pdev device instance + * @param [in] cfgidx configuration index + * @param [in] action USB_DEV_CONFIG_SET or USB_DEV_CONFIG_CLEAR + * @retval None + */ +void usb_dev_ctrlconfig(usb_core_instance *pdev, uint8_t cfgidx, uint8_t action) +{ + __IO uint8_t tmp_1; + + (void)(cfgidx); + tmp_1 = action; + if (tmp_1 == USB_DEV_CONFIG_SET) { /* set configuration */ + pdev->dev.class_callback->class_init(pdev); + pdev->dev.user_callback->user_devconfig(); + } else if (tmp_1 == USB_DEV_CONFIG_CLEAR) { /* clear configuration */ + pdev->dev.class_callback->class_deinit(pdev); + } else { + ; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.h new file mode 100644 index 0000000000..1b95c5de38 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.h @@ -0,0 +1,82 @@ +/** + ******************************************************************************* + * @file usb_dev_stdreq.h + * @brief header file for the usb_dev_stdreq.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_DEV_STDREQ_H__ +#define __USB_DEV_STDREQ_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_dev_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_DEV_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +void usb_standarddevreq(usb_core_instance *pdev, USB_SETUP_REQ *req); +void usb_standarditfreq(usb_core_instance *pdev, USB_SETUP_REQ *req); +void usb_standardepreq(usb_core_instance *pdev, USB_SETUP_REQ *req); +void usb_parsesetupreq(usb_core_instance *pdev, USB_SETUP_REQ *req); +void usb_ctrlerr(usb_core_instance *pdev); +void usb_getstring(uint8_t *desc, uint8_t *unicode, uint16_t *len); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_DEV_STDREQ_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.c new file mode 100644 index 0000000000..38f730f606 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.c @@ -0,0 +1,693 @@ +/** + ******************************************************************************* + * @file usb_host_cdc_class.c + * @brief cdc class related functions + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_cdc_class.h" +#include "usb_host_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CDC USB Host CDC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +CDC_Requests CDC_ReqState; +CDC_Usercb_TypeDef UserCb; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined(__ICCARM__) /*!< IAR Compiler */ +#pragma data_alignment = 4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN static CDC_Machine_TypeDef CDC_Machine; + +static CDC_Xfer_TypeDef CDC_TxParam; +static CDC_Xfer_TypeDef CDC_RxParam; + +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined(__ICCARM__) /*!< IAR Compiler */ +#pragma data_alignment = 4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN static uint8_t TxBuf[CDC_BUFFER_SIZE]; + +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined(__ICCARM__) /*!< IAR Compiler */ +#pragma data_alignment = 4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN static uint8_t RxBuf[CDC_BUFFER_SIZE]; + +static uint8_t RX_Enabled = 0; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void usb_host_cdc_txrxparam_init(void); + +static void usb_host_cdc_receivedata(CDC_Xfer_TypeDef *cdc_Data); + +static void usb_host_cdc_senddata_process(usb_core_instance *pdev, USBH_HOST *phost); + +static void usb_host_cdc_receivedata_process(usb_core_instance *pdev, USBH_HOST *phost); + +static HOST_STATUS usb_host_cdc_interface_init(usb_core_instance *pdev, void *phost); + +void usb_host_cdc_interface_deinit(usb_core_instance *pdev); + +static HOST_STATUS usb_host_cdc_class_process(usb_core_instance *pdev, void *phost); + +static HOST_STATUS usb_host_cdc_class_request(usb_core_instance *pdev, void *phost); + +usb_host_class_callback_func CDC_cb = { + usb_host_cdc_interface_init, + usb_host_cdc_interface_deinit, + usb_host_cdc_class_request, + usb_host_cdc_class_process +}; + +/** + * @brief init the vendor interface + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +static HOST_STATUS usb_host_cdc_vendor_interface_init(usb_core_instance *pdev, void *phost) +{ + USBH_HOST *pphost = phost; + HOST_STATUS status = HSTATUS_UNSUPPORTED; + uint8_t idxep; + uint8_t bulk_inep_cnt, bulk_inep_idx = 0U; + uint8_t bulk_outep_cnt, bulk_outep_idx = 0U; + uint8_t intr_inep_cnt = 0U, intr_inep_idx = 0U; + /* try to support vendor cdc device */ + if (pphost->device_prop.devitfdesc[0].bInterfaceClass == VENDOR_SPECIFIC) { + if (pphost->device_prop.devitfdesc[0].bNumEndpoints < 2U) { + return HSTATUS_UNSUPPORTED; + } + bulk_inep_cnt = 0; + bulk_outep_cnt = 0; + for (idxep = 0; idxep < pphost->device_prop.devitfdesc[0].bNumEndpoints; idxep++) { + if ((pphost->device_prop.devepdesc[0][idxep].bmAttributes & EP_TYPE_MSK) == EP_TYPE_BULK) { + if (0U != (pphost->device_prop.devepdesc[0][idxep].bEndpointAddress & 0x80U)) { + bulk_inep_cnt++; + bulk_inep_idx = idxep; + } else { + bulk_outep_cnt++; + bulk_outep_idx = idxep; + } + } else if ((pphost->device_prop.devepdesc[0][idxep].bmAttributes & EP_TYPE_MSK) == EP_TYPE_INTR) { + if (0U != (pphost->device_prop.devepdesc[0][idxep].bEndpointAddress & 0x80U)) { + intr_inep_cnt++; + intr_inep_idx = idxep; + } + } else { + ; + } + } + if ((bulk_inep_cnt != 1U) || (bulk_outep_cnt != 1U)) { + return HSTATUS_UNSUPPORTED; + } + + if (bulk_inep_cnt == 1U) { + /* fill the communication endpoint address and length */ + CDC_Machine.CDC_CommItf.ep_addr = pphost->device_prop.devepdesc[0][intr_inep_idx].bEndpointAddress; + CDC_Machine.CDC_CommItf.length = pphost->device_prop.devepdesc[0][intr_inep_idx].wMaxPacketSize; + + if (0U != (pphost->device_prop.devepdesc[0][intr_inep_idx].bEndpointAddress & 0x80U)) { + CDC_Machine.CDC_CommItf.notificationEp = + (pphost->device_prop.devepdesc[0][intr_inep_idx].bEndpointAddress); + } + /* distribute a channel for communication endpoint */ + CDC_Machine.CDC_CommItf.hc_num_in = usb_host_distrch(pdev, + CDC_Machine.CDC_CommItf.notificationEp); + + /* open channel for communication endpoint */ + usb_host_chopen(pdev, + CDC_Machine.CDC_CommItf.hc_num_in, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_INTR, + CDC_Machine.CDC_CommItf.length); + } + + /* fill cdc data endpoint address and length */ + CDC_Machine.CDC_DataItf.ep_addr = pphost->device_prop.devepdesc[0][bulk_inep_idx].bEndpointAddress; + CDC_Machine.CDC_DataItf.length = pphost->device_prop.devepdesc[0][bulk_inep_idx].wMaxPacketSize; + + CDC_Machine.CDC_DataItf.cdcInEp = (pphost->device_prop.devepdesc[0][bulk_inep_idx].bEndpointAddress); + CDC_Machine.CDC_DataItf.cdcOutEp = (pphost->device_prop.devepdesc[0][bulk_outep_idx].bEndpointAddress); + + /* distribute channels for cdc data endpoints */ + CDC_Machine.CDC_DataItf.hc_num_out = usb_host_distrch(pdev, + CDC_Machine.CDC_DataItf.cdcOutEp); + + CDC_Machine.CDC_DataItf.hc_num_in = usb_host_distrch(pdev, + CDC_Machine.CDC_DataItf.cdcInEp); + + /* open cdc data endpoints */ + usb_host_chopen(pdev, + CDC_Machine.CDC_DataItf.hc_num_out, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_BULK, + CDC_Machine.CDC_DataItf.length); + + usb_host_chopen(pdev, + CDC_Machine.CDC_DataItf.hc_num_in, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_BULK, + CDC_Machine.CDC_DataItf.length); + + /* txrx parms init */ + usb_host_cdc_txrxparam_init(); + + /* host next state is HOST_CLASS_REQ, so set cdc request to GET_LINE_CODING */ + CDC_ReqState = CDC_GET_LINE_CODING_RQUEST; + + status = HSTATUS_OK; + } + return status; +} + +/** + * @brief init the std cdc interface + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +static HOST_STATUS usb_host_cdc_interface_init(usb_core_instance *pdev, void *phost) +{ + USBH_HOST *pphost = phost; + HOST_STATUS status = HSTATUS_OK; + uint8_t unsupport_cnt = 0; + + /* Communication Interface */ + if ((pphost->device_prop.devitfdesc[0].bInterfaceClass == COMMUNICATION_DEVICE_CLASS_CODE) && + (pphost->device_prop.devitfdesc[0].bInterfaceSubClass == ABSTRACT_CONTROL_MODEL) && + (pphost->device_prop.devitfdesc[0].bInterfaceProtocol == COMMON_AT_COMMAND)) { + /* fill the communication endpoint address and length */ + CDC_Machine.CDC_CommItf.ep_addr = pphost->device_prop.devepdesc[0][0].bEndpointAddress; + CDC_Machine.CDC_CommItf.length = pphost->device_prop.devepdesc[0][0].wMaxPacketSize; + + if (0U != (pphost->device_prop.devepdesc[0][0].bEndpointAddress & 0x80U)) { + CDC_Machine.CDC_CommItf.notificationEp = + (pphost->device_prop.devepdesc[0][0].bEndpointAddress); + } + /* distribute a channel for communication endpoint */ + CDC_Machine.CDC_CommItf.hc_num_in = usb_host_distrch(pdev, + CDC_Machine.CDC_CommItf.notificationEp); + + /* open channel for communication endpoint */ + usb_host_chopen(pdev, + CDC_Machine.CDC_CommItf.hc_num_in, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_INTR, + CDC_Machine.CDC_CommItf.length); + } else { + pphost->user_callbk->huser_devunsupported(); + unsupport_cnt++; + } + + /* Data Interface */ + if ((pphost->device_prop.devitfdesc[1].bInterfaceClass == DATA_INTERFACE_CLASS_CODE) && + (pphost->device_prop.devitfdesc[1].bInterfaceSubClass == RESERVED) && + (pphost->device_prop.devitfdesc[1].bInterfaceProtocol == NO_CLASS_SPECIFIC_PROTOCOL_CODE)) { + /* fill cdc data endpoint address and length */ + CDC_Machine.CDC_DataItf.ep_addr = pphost->device_prop.devepdesc[1][0].bEndpointAddress; + CDC_Machine.CDC_DataItf.length = pphost->device_prop.devepdesc[1][0].wMaxPacketSize; + + if (0U != (pphost->device_prop.devepdesc[1][0].bEndpointAddress & 0x80U)) { + CDC_Machine.CDC_DataItf.cdcInEp = (pphost->device_prop.devepdesc[1][0].bEndpointAddress); + } else { + CDC_Machine.CDC_DataItf.cdcOutEp = (pphost->device_prop.devepdesc[1][0].bEndpointAddress); + } + + if (0U != (pphost->device_prop.devepdesc[1][1].bEndpointAddress & 0x80U)) { + CDC_Machine.CDC_DataItf.cdcInEp = (pphost->device_prop.devepdesc[1][1].bEndpointAddress); + } else { + CDC_Machine.CDC_DataItf.cdcOutEp = (pphost->device_prop.devepdesc[1][1].bEndpointAddress); + } + + /* distribute channels for cdc data endpoints */ + CDC_Machine.CDC_DataItf.hc_num_out = usb_host_distrch(pdev, + CDC_Machine.CDC_DataItf.cdcOutEp); + + CDC_Machine.CDC_DataItf.hc_num_in = usb_host_distrch(pdev, + CDC_Machine.CDC_DataItf.cdcInEp); + + /* open cdc data endpoints */ + usb_host_chopen(pdev, + CDC_Machine.CDC_DataItf.hc_num_out, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_BULK, + CDC_Machine.CDC_DataItf.length); + + usb_host_chopen(pdev, + CDC_Machine.CDC_DataItf.hc_num_in, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_BULK, + CDC_Machine.CDC_DataItf.length); + + /* txrx parms init */ + usb_host_cdc_txrxparam_init(); + + /* host next state is HOST_CLASS_REQ, so set cdc request to GET_LINE_CODING */ + CDC_ReqState = CDC_GET_LINE_CODING_RQUEST; + } else { + pphost->user_callbk->huser_devunsupported(); + unsupport_cnt++; + } + + /* not a stand CDC ACM device */ + if (2U == unsupport_cnt) { + if (HSTATUS_OK != usb_host_cdc_vendor_interface_init(pdev, phost)) { + pphost->user_callbk->huser_devunsupported(); + } + } + + return status; +} + +/** + * @brief deinit the cdc interface + * @param [in] pdev device instance + * @retval None + */ +void usb_host_cdc_interface_deinit(usb_core_instance *pdev) +{ + /* halt and free all channels */ + if (0U != CDC_Machine.CDC_CommItf.hc_num_in) { + usb_hchstop(&pdev->regs, CDC_Machine.CDC_CommItf.hc_num_in); + (void)usb_host_freech(pdev, CDC_Machine.CDC_CommItf.hc_num_in); + CDC_Machine.CDC_CommItf.hc_num_in = 0; + } + + if (0U != CDC_Machine.CDC_DataItf.hc_num_out) { + usb_hchstop(&pdev->regs, CDC_Machine.CDC_DataItf.hc_num_out); + (void)usb_host_freech(pdev, CDC_Machine.CDC_DataItf.hc_num_out); + CDC_Machine.CDC_DataItf.hc_num_out = 0; + } + + if (0U != CDC_Machine.CDC_DataItf.hc_num_in) { + usb_hchstop(&pdev->regs, CDC_Machine.CDC_DataItf.hc_num_in); + (void)usb_host_freech(pdev, CDC_Machine.CDC_DataItf.hc_num_in); + CDC_Machine.CDC_DataItf.hc_num_in = 0; + } +} + +/** + * @brief handing host class request state + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +static HOST_STATUS usb_host_cdc_class_request(usb_core_instance *pdev, void *phost) +{ + USBH_HOST *pphost = phost; + + HOST_STATUS status = HSTATUS_BUSY; + HOST_STATUS ClassReqStatus; + + switch (CDC_ReqState) { + + case CDC_GET_LINE_CODING_RQUEST: + + ClassReqStatus = usb_host_cdc_getlinecoding(pdev, phost); + if (ClassReqStatus == HSTATUS_OK) { + CDC_ReqState = CDC_SET_CONTROL_LINE_STATE_REQUEST; + } + break; + + case CDC_SET_LINE_CODING_RQUEST: + + ClassReqStatus = usb_host_cdc_setlinecoding(pdev, phost); + if (ClassReqStatus == HSTATUS_OK) { + CDC_ReqState = CDC_GET_LINE_CODING_RQUEST; + } + if (ClassReqStatus == HSTATUS_UNSUPPORTED) { + /* Clear Feature should be issued */ + CDC_ReqState = CDC_ERROR_STATE; + } + break; + + case CDC_SET_CONTROL_LINE_STATE_REQUEST: + + ClassReqStatus = usb_host_cdc_setcontrollinestate(pdev, phost); + if (ClassReqStatus == HSTATUS_OK) { + /* change state to itself */ + CDC_ReqState = CDC_SET_CONTROL_LINE_STATE_REQUEST; + /* change rx state to CDC_IDLE */ + CDC_RxParam.CDCState = CDC_IDLE; + + status = HSTATUS_OK; + } + break; + + case CDC_ERROR_STATE: + + ClassReqStatus = usb_host_clrfeature(pdev, + phost, + 0x00, + pphost->ctrlparam.hc_num_out); + + if (ClassReqStatus == HSTATUS_OK) { + /* change state to GET_LINE_CODING */ + CDC_ReqState = CDC_GET_LINE_CODING_RQUEST; + } + break; + default: + break; + } + + return status; +} + +/** + * @brief process the cdc data send/receive state machine and user application + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +static HOST_STATUS usb_host_cdc_class_process(usb_core_instance *pdev, void *phost) +{ + HOST_STATUS status = HSTATUS_OK; + USBH_HOST *pphost = phost; + + /* application process */ + pphost->user_callbk->huser_application(); + + /* send data process */ + usb_host_cdc_senddata_process(pdev, pphost); + + /* receive data process */ + usb_host_cdc_receivedata_process(pdev, pphost); + + return status; +} + +/** + * @brief process the cdc data send state machine + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval None + */ +void usb_host_cdc_senddata_process(usb_core_instance *pdev, USBH_HOST *phost) +{ + static uint16_t len; + HOST_CH_XFER_STATE URB_StatusTx; + + URB_StatusTx = host_driver_getxferstate(pdev, CDC_Machine.CDC_DataItf.hc_num_out); + + switch (CDC_TxParam.CDCState) { + case CDC_IDLE: + break; + + case CDC_SEND_DATA: + + if ((URB_StatusTx == HOST_CH_XFER_DONE) || (URB_StatusTx == HOST_CH_XFER_IDLE)) { + /* check if send data len exceed CDC_DataItf.length */ + if (CDC_TxParam.DataLength > CDC_Machine.CDC_DataItf.length) { + + len = CDC_Machine.CDC_DataItf.length; + /* send data */ + usb_host_sendbulkdata(pdev, + CDC_TxParam.pRxTxBuff, + len, + CDC_Machine.CDC_DataItf.hc_num_out); + } else { + len = CDC_TxParam.DataLength; + /* send all the remaining data */ + usb_host_sendbulkdata(pdev, + CDC_TxParam.pRxTxBuff, + len, + CDC_Machine.CDC_DataItf.hc_num_out); + } + CDC_TxParam.CDCState = CDC_DATA_SENT; + } + + break; + + case CDC_DATA_SENT: + /* check send complete */ + if (URB_StatusTx == HOST_CH_XFER_DONE) { + /* move txbuffer point */ + CDC_TxParam.pRxTxBuff += len; + + /* ecrease data length */ + CDC_TxParam.DataLength -= len; + + if (CDC_TxParam.DataLength == 0U) { + CDC_TxParam.CDCState = CDC_IDLE; + } else { + CDC_TxParam.CDCState = CDC_SEND_DATA; + } + } else if (URB_StatusTx == HOST_CH_XFER_UNREADY) { + /* send again */ + usb_host_sendbulkdata(pdev, + (CDC_TxParam.pRxTxBuff), + len, + CDC_Machine.CDC_DataItf.hc_num_out); + } else { + ; + } + + break; + + case CDC_READ_DATA: + break; + + case CDC_BUSY: + break; + + case CDC_GET_DATA: + break; + + case CDC_POLL: + break; + + case CDC_CTRL_STATE: + break; + default: + break; + } +} + +/** + * @brief process the cdc data receive state machine + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval None + */ +static void usb_host_cdc_receivedata_process(usb_core_instance *pdev, USBH_HOST *phost) +{ + + if (RX_Enabled == 1U) { + HOST_CH_XFER_STATE URB_StatusRx = host_driver_getxferstate(pdev, CDC_Machine.CDC_DataItf.hc_num_in); + + switch (CDC_RxParam.CDCState) { + + case CDC_IDLE: + + /* check if free rxbuf exceed CDC_DataItf.length */ + if (CDC_RxParam.DataLength < (CDC_RxParam.BufferLen - CDC_Machine.CDC_DataItf.length)) { + /* receive data */ + usb_host_recvbulkdata(pdev, + CDC_RxParam.pFillBuff, + CDC_Machine.CDC_DataItf.length, + CDC_Machine.CDC_DataItf.hc_num_in); + + /* change sate to wait receive complete */ + CDC_RxParam.CDCState = CDC_GET_DATA; + } + break; + + case CDC_GET_DATA: + /* check XFER_DONE */ + if (URB_StatusRx == HOST_CH_XFER_DONE) { + /* increase rx data len */ + CDC_RxParam.DataLength += (uint16_t)pdev->host.hc[CDC_Machine.CDC_DataItf.hc_num_in].xfer_count; + /* move rxbuff poinit */ + CDC_RxParam.pFillBuff += pdev->host.hc[CDC_Machine.CDC_DataItf.hc_num_in].xfer_count; + + /* process the received data */ + usb_host_cdc_receivedata(&CDC_RxParam); + + /* chage state back to CDC_IDLE */ + CDC_RxParam.CDCState = CDC_IDLE; + } + break; + + case CDC_READ_DATA: + + break; + + case CDC_BUSY: + + break; + + case CDC_SEND_DATA: + + break; + + case CDC_DATA_SENT: + + break; + + case CDC_POLL: + + break; + + case CDC_CTRL_STATE: + + break; + default: + break; + } + } +} + +/** + * @brief init tx rx buffer for cdc + * @param None + * @retval None + */ +static void usb_host_cdc_txrxparam_init(void) +{ + /* init tx buffer */ + CDC_TxParam.CDCState = CDC_IDLE; + CDC_TxParam.DataLength = 0; + CDC_TxParam.pRxTxBuff = TxBuf; + + /* init rx buffer */ + CDC_RxParam.CDCState = CDC_IDLE; + CDC_RxParam.DataLength = 0; + CDC_RxParam.pFillBuff = RxBuf; + CDC_RxParam.pEmptyBuff = RxBuf; + CDC_RxParam.BufferLen = sizeof(RxBuf); +} + +/** + * @brief call user callback fucntion to process the received data + * @param [in] cdc_Data type of CDC_Xfer_TypeDef + * @retval None + */ +static void usb_host_cdc_receivedata(CDC_Xfer_TypeDef *cdc_Data) +{ + uint8_t *ptr; + + if (cdc_Data->pEmptyBuff < cdc_Data->pFillBuff) { + ptr = cdc_Data->pFillBuff; + *ptr = 0x00; + + /* callback user function to process received data */ + UserCb.Receive(cdc_Data->pEmptyBuff, cdc_Data->DataLength); + + cdc_Data->pFillBuff = cdc_Data->pEmptyBuff; + cdc_Data->DataLength = 0; + } +} + +/** + * @brief user call this function to send data to cdc device + * @param [in] data send data buffer + * @param [in] length send length + * @retval None + */ +void usb_host_cdc_senddata(uint8_t *data, uint16_t length) +{ + + if (CDC_TxParam.CDCState == CDC_IDLE) { + CDC_TxParam.pRxTxBuff = data; + CDC_TxParam.DataLength = length; + CDC_TxParam.CDCState = CDC_SEND_DATA; + } +} + +/** + * @brief user call this function to enable receive data from device + * @param [in] pdev device instance + * @retval None + */ +void usb_host_cdc_enable_receive(usb_core_instance *pdev) +{ + RX_Enabled = 1; +} + +/** + * @brief user call this function to disable receive data from device + * @param [in] pdev device instance + * @retval None + */ +void usb_host_cdc_disable_receive(usb_core_instance *pdev) +{ + RX_Enabled = 0; + usb_hchstop(&pdev->regs, CDC_Machine.CDC_DataItf.hc_num_in); + (void)usb_host_freech(pdev, CDC_Machine.CDC_DataItf.hc_num_in); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.h new file mode 100644 index 0000000000..fe03e0ba61 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.h @@ -0,0 +1,169 @@ +/** + ******************************************************************************* + * @file usb_host_cdc_class.h + * @brief Head file for usb_host_cdc_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_CDC_CLASS_H__ +#define __USB_HOST_CDC_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_cdc_ctrl.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CDC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef enum { + CDC_IDLE = 0, + CDC_READ_DATA, + CDC_SEND_DATA, + CDC_DATA_SENT, + CDC_BUSY, + CDC_GET_DATA, + CDC_POLL, + CDC_CTRL_STATE +} +CDC_State; + +typedef struct _CDCXfer { + volatile CDC_State CDCState; + uint8_t *pRxTxBuff; + uint8_t *pFillBuff; + uint8_t *pEmptyBuff; + uint32_t BufferLen; + uint16_t DataLength; +} CDC_Xfer_TypeDef; + +typedef struct CDC_UserCb { + void (*Send)(uint8_t *); + void (*Receive)(uint8_t *, uint32_t len); + +} CDC_Usercb_TypeDef; + +typedef struct _CDC_CommInterface { + uint8_t hc_num_in; + uint8_t hc_num_out; + uint8_t notificationEp; + CDC_State state; + uint8_t buff[8]; + uint16_t length; + uint8_t ep_addr; +} +CDC_CommInterface_Typedef ; + +typedef struct _CDC_DataInterface { + uint8_t hc_num_in; + uint8_t hc_num_out; + uint8_t cdcOutEp; + uint8_t cdcInEp; + CDC_State state; + uint8_t buff[8]; + uint16_t length; + uint8_t ep_addr; +} +CDC_DataInterface_Typedef ; + +typedef struct _CDC_Process { + CDC_CommInterface_Typedef CDC_CommItf; + CDC_DataInterface_Typedef CDC_DataItf; +} +CDC_Machine_TypeDef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define COMMUNICATION_DEVICE_CLASS_CODE (0x02U) +#define COMMUNICATION_INTERFACE_CLASS_CODE (0x02U) + +#define DATA_INTERFACE_CLASS_CODE (0x0AU) + +#define RESERVED (0x00U) +#define DIRECT_LINE_CONTROL_MODEL (0x01U) +#define ABSTRACT_CONTROL_MODEL (0x02U) +#define TELEPHONE_CONTROL_MODEL (0x03U) +#define MULTICHANNEL_CONTROL_MODEL (0x04U) +#define CAPI_CONTROL_MODEL (0x05U) +#define ETHERNET_NETWORKING_CONTROL_MODEL (0x06U) +#define ATM_NETWORKING_CONTROL_MODEL (0x07U) + + +#define NO_CLASS_SPECIFIC_PROTOCOL_CODE (0x00U) +#define COMMON_AT_COMMAND (0x01U) +#define VENDOR_SPECIFIC (0xFFU) + + +#define CS_INTERFACE (0x24U) +#define CDC_PAGE_SIZE_64 (0x40U) + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_host_class_callback_func CDC_cb; +extern CDC_Usercb_TypeDef UserCb; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +void usb_host_cdc_senddata(uint8_t *data, uint16_t length); +void usb_host_cdc_enable_receive(usb_core_instance *pdev); +void usb_host_cdc_disable_receive(usb_core_instance *pdev); + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_CDC_CLASS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.c new file mode 100644 index 0000000000..6a805d26d3 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.c @@ -0,0 +1,175 @@ +/** + ******************************************************************************* + * @file usb_host_cdc_ctrl.c + * @brief The CDC ctrl functions + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_cdc_ctrl.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CDC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +extern CDC_Requests CDC_ReqState; +CDC_LineCodingTypeDef CDC_SetLineCode; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static CDC_InterfaceDesc_Typedef CDC_Desc; +static CDC_LineCodingTypeDef CDC_GetLineCode; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief host send ctrl request to get line coding + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status define by HOST_STATUS + */ +HOST_STATUS usb_host_cdc_getlinecoding(usb_core_instance *pdev, USBH_HOST *phost) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | \ + USB_REQ_RECIPIENT_INTERFACE; + + phost->ctrlparam.setup.b.bRequest = CDC_GET_LINE_CODING; + phost->ctrlparam.setup.b.wValue.w = 0; + phost->ctrlparam.setup.b.wIndex.w = CDC_Desc.CDC_UnionFuncDesc.bControlInterface; + phost->ctrlparam.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE; + + + return usb_host_ctrlreq(pdev, phost, CDC_GetLineCode.Array, LINE_CODING_STRUCTURE_SIZE); +} + +/** + * @brief host send ctrl request to set line coding + * to config Baud rate/Stop bits/Parity/Data bits + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status define by HOST_STATUS + */ +HOST_STATUS usb_host_cdc_setlinecoding(usb_core_instance *pdev, USBH_HOST *phost) +{ + + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | \ + USB_REQ_RECIPIENT_INTERFACE; + + phost->ctrlparam.setup.b.bRequest = CDC_SET_LINE_CODING; + phost->ctrlparam.setup.b.wValue.w = 0; + + phost->ctrlparam.setup.b.wIndex.w = CDC_Desc.CDC_UnionFuncDesc.bControlInterface; + + phost->ctrlparam.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE; + + return usb_host_ctrlreq(pdev, phost, CDC_SetLineCode.Array, LINE_CODING_STRUCTURE_SIZE); +} + +/** + * @brief host send ctrl request to set control line state + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status define by HOST_STATUS + */ +HOST_STATUS usb_host_cdc_setcontrollinestate(usb_core_instance *pdev, USBH_HOST *phost) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | \ + USB_REQ_RECIPIENT_INTERFACE; + + phost->ctrlparam.setup.b.bRequest = CDC_SET_CONTROL_LINE_STATE; + + phost->ctrlparam.setup.b.wValue.w = CDC_DEACTIVATE_CARRIER_SIGNAL_RTS | \ + CDC_DEACTIVATE_SIGNAL_DTR; + + phost->ctrlparam.setup.b.wIndex.w = CDC_Desc.CDC_UnionFuncDesc.bControlInterface; + + phost->ctrlparam.setup.b.wLength.w = 0; + + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief user call this function to issue set line coding request + * before call this funtion user need fill CDC_SetLineCode with config params + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval None + */ +void usb_host_cdc_issue_setlinecoding(usb_core_instance *pdev, USBH_HOST *phost) +{ + phost->host_state_backup = phost->host_state ; + phost->host_state = HOST_CLASS_REQ; + CDC_ReqState = CDC_SET_LINE_CODING_RQUEST; +} + +/** + * @brief user call this function to issue get line coding request + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval None + */ +void usb_host_cdc_issue_getlinecoding(usb_core_instance *pdev, USBH_HOST *phost) +{ + phost->host_state_backup = phost->host_state ; + phost->host_state = HOST_CLASS_REQ; + CDC_ReqState = CDC_GET_LINE_CODING_RQUEST; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.h new file mode 100644 index 0000000000..1d27faea41 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.h @@ -0,0 +1,221 @@ +/** + ******************************************************************************* + * @file usb_host_cdc_ctrl.h + * @brief Head file for usb_host_cdc_ctrl.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __USB_HOST_CDC_CTRL_H__ +#define __USB_HOST_CDC_CTRL_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_core.h" +#include "usb_host_stdreq.h" +#include "usb_host_ctrltrans.h" +#include "usb_host_cfgch.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CDC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef enum { + CDC_SET_LINE_CODING_RQUEST = 0, + CDC_GET_LINE_CODING_RQUEST, + CDC_SET_CONTROL_LINE_STATE_REQUEST, + CDC_ERROR_STATE +} +CDC_Requests; + +#define LINE_CODING_STRUCTURE_SIZE (0x07U) +typedef union _CDC_LineCodingStructure { + uint8_t Array[LINE_CODING_STRUCTURE_SIZE]; + + struct { + + uint32_t dwDTERate; /* Data terminal rate, in bits per second */ + /* Data terminal rate: + such as 9600, 115200, ... */ + + uint8_t bCharFormat; /* Stop bits */ + /* Stop bits: + 0 - 1 Stop bit + 1 - 1.5 Stop bits + 2 - 2 Stop bits */ + + uint8_t bParityType; /* Parity */ + /* Parity: + 0 - None + 1 - Odd + 2 - Even + 3 - Mark + 4 - Space */ + + uint8_t bDataBits; /* Data bits */ + /* Data bits: + (5, 6, 7, 8 or 16) */ + } b; +} +CDC_LineCodingTypeDef; + +typedef struct _FunctionalDescriptorHeader { + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE(24h) descriptor type */ + uint8_t bDescriptorSubType; /* Header functional descriptor subtype */ + uint16_t bcdCDC; /* USB Class Definitions for Communications + Devices Specification release number in + binary-coded decima */ +} +CDC_HeaderFuncDesc_TypeDef; + +typedef struct _CallMgmtFunctionalDescriptor { + uint8_t bLength; /* Size of this functional descriptor, in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE(24h) */ + uint8_t bDescriptorSubType; /* Call Management functional descriptor subtype */ + uint8_t bmCapabilities; /* The capabilities that this configuration supports */ + /* capabilities: + D7..D2: RESERVED (Reset to zero) + D1: 0 - Device sends/receives call management + information only over the Communications Class + interface. + 1 - Device can send/receive call management + information over a Data Class interface. + D0: 0 - Device does not handle call management + itself. + 1 - Device handles call management itself + The previous bits, in combination, identify which call + management scenario is used. If bit D0 is reset to 0, then the + value of bit D1 is ignored. In this case, bit D1 is reset to zero + for future compatibility.*/ + uint8_t bDataInterface; /* Interface number of Data Class interface optionally used for call management */ + /* Interface number: + Zero based index of the interface in this configuration */ +} +CDC_CallMgmtFuncDesc_TypeDef; + +typedef struct _AbstractCntrlMgmtFunctionalDescriptor { + uint8_t bLength; /* Size of this functional descriptor, in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE(24h) */ + uint8_t bDescriptorSubType; /* Abstract Control Management functional descriptor subtype */ + uint8_t bmCapabilities; /* The capabilities that this configuration supports */ + /* capabilities:(A bit valueof zero means that the request is not supported) + D7..D4: RESERVED (Reset to zero) + D3: 1 - Device supports the notification + Network_Connection. + D2: 1 - Device supports the request Send_Break + D1: 1 - Device supports the request combination of + Set_Line_Coding, Set_Control_Line_State, + Get_Line_Coding, and the notification + Serial_State. + D0: 1 - Device supports the request combination of + Set_Comm_Feature, Clear_Comm_Feature, and + Get_Comm_Feature. + The previous bits, in combination, identify which + requests/notifications are supported by a + CommunicationsClass interface with the SubClass code of + Abstract Control Model. */ +} +CDC_AbstCntrlMgmtFuncDesc_TypeDef; + +typedef struct _UnionFunctionalDescriptor { + uint8_t bLength; /* Size of this functional descriptor, in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE(24h) */ + uint8_t bDescriptorSubType; /* Union Functional Descriptor SubType */ + uint8_t bControlInterface; /* The interface number of the Communications + or Data Class interface, designated as the + controlling interface for the union.*/ + uint8_t bSubordinateInterface0; /* Interface number of first subordinate interfacein the union. */ + /* ... */ + /* uint8_t bSubordinateInterfaceN-1; */ /* Interface number of N-1 subordinate interfacein the union. */ +} +CDC_UnionFuncDesc_TypeDef; + +typedef struct _USBH_CDCInterfaceDesc { + CDC_HeaderFuncDesc_TypeDef CDC_HeaderFuncDesc; + CDC_CallMgmtFuncDesc_TypeDef CDC_CallMgmtFuncDesc; + CDC_AbstCntrlMgmtFuncDesc_TypeDef CDC_AbstCntrlMgmtFuncDesc; + CDC_UnionFuncDesc_TypeDef CDC_UnionFuncDesc; +} +CDC_InterfaceDesc_Typedef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define CDC_SET_LINE_CODING (0x20U) +#define CDC_GET_LINE_CODING (0x21U) +#define CDC_SET_CONTROL_LINE_STATE (0x22U) + +#define CDC_ACTIVATE_CARRIER_SIGNAL_RTS (0x0002U) +#define CDC_DEACTIVATE_CARRIER_SIGNAL_RTS (0x0000U) +#define CDC_ACTIVATE_SIGNAL_DTR (0x0001U) +#define CDC_DEACTIVATE_SIGNAL_DTR (0x0000U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern CDC_LineCodingTypeDef CDC_SetLineCode; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +HOST_STATUS usb_host_cdc_getlinecoding(usb_core_instance *pdev, USBH_HOST *phost); +HOST_STATUS usb_host_cdc_setlinecoding(usb_core_instance *pdev, USBH_HOST *phost); +HOST_STATUS usb_host_cdc_setcontrollinestate(usb_core_instance *pdev, USBH_HOST *phost); +void usb_host_cdc_issue_setlinecoding(usb_core_instance *pdev, USBH_HOST *phost); +void usb_host_cdc_issue_getlinecoding(usb_core_instance *pdev, USBH_HOST *phost); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_CDC_CTRL_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.c new file mode 100644 index 0000000000..683f91a9bb --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.c @@ -0,0 +1,443 @@ +/** + ******************************************************************************* + * @file usb_host_hid_class.c + * @brief The HID Layer Handlers for USB Host HID class. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_hid_class.h" +#include "usb_host_hid_mouseapp.h" +#include "usb_host_hid_keyboardapp.h" +#include "usb_host_driver.h" +#include "usb_host_cfgch.h" +#include "usb_host_ctrltrans.h" +#include "usb_host_stdreq.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS LL USB Host Class + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_HID USB Host HID + * @{ + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +HOST_STATUS usb_host_hid_itfinit(usb_core_instance *pdev, void *phost); +void usb_host_hid_itfdeinit(usb_core_instance *pdev); +void usb_host_parse_hiddesc(USB_HOST_HIDDesc_TypeDef *desc, uint8_t *buf); +HOST_STATUS usb_host_hid_process(usb_core_instance *pdev, void *phost); +HOST_STATUS usb_host_hid_classreq(usb_core_instance *pdev, void *phost); +HOST_STATUS usb_host_get_hidreportdesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length); +HOST_STATUS usb_host_get_hiddesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length); +HOST_STATUS usb_host_set_hididle(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t duration, + uint8_t reportId); +HOST_STATUS usb_host_set_hidprotocol(usb_core_instance *pdev, USBH_HOST *phost, uint8_t protocol); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +usb_host_class_callback_func USBH_HID_cb = { + usb_host_hid_itfinit, + usb_host_hid_itfdeinit, + usb_host_hid_classreq, + usb_host_hid_process +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN static HID_Machine_TypeDef HID_Machine; + +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN static USB_HOST_HIDDesc_TypeDef HID_Desc; + +__IO static uint8_t start_toggle = 0U; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief initialize the hid class + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defination by HOST_STATUS + */ +HOST_STATUS usb_host_hid_itfinit(usb_core_instance *pdev, void *phost) +{ + uint8_t maxEP; + USBH_HOST *pphost = phost; + + uint8_t epnum; + HOST_STATUS status = HSTATUS_BUSY ; + HID_Machine.state = HID_ERROR; + + if (pphost->device_prop.devitfdesc[0].bInterfaceSubClass == HID_BOOT_CODE) { + switch (pphost->device_prop.devitfdesc[0].bInterfaceProtocol) { + case HID_MOUSE_BOOT_CODE: + HID_Machine.cb = &HID_MOUSE_cb; + break; + case HID_KEYBRD_BOOT_CODE: + HID_Machine.cb = &HID_KEYBRD_cb; + break; + default: + break; + } + HID_Machine.state = HID_IDLE; + HID_Machine.ctl_state = HID_REQ_IDLE; + HID_Machine.ep_addr = pphost->device_prop.devepdesc[0][0].bEndpointAddress; + HID_Machine.length = pphost->device_prop.devepdesc[0][0].wMaxPacketSize; + HID_Machine.poll = pphost->device_prop.devepdesc[0][0].bInterval ; + + if (HID_Machine.poll < HID_MIN_POLL) { + HID_Machine.poll = HID_MIN_POLL; + } + + /* Check fo available number of endpoints */ + /* Find the number of EPs in the Interface Descriptor */ + /* Choose the lower number in order not to overrun the buffer allocated */ + maxEP = ((pphost->device_prop.devitfdesc[0].bNumEndpoints <= USBH_MAX_NUM_ENDPOINTS) ? + pphost->device_prop.devitfdesc[0].bNumEndpoints : + USBH_MAX_NUM_ENDPOINTS); + + /* Decode endpoint IN and OUT address from interface descriptor */ + for (epnum = 0U; epnum < maxEP; epnum++) { + if (0U != (pphost->device_prop.devepdesc[0][epnum].bEndpointAddress & 0x80U)) { + HID_Machine.HIDIntInEp = (pphost->device_prop.devepdesc[0][epnum].bEndpointAddress); + HID_Machine.hc_num_in = usb_host_distrch(pdev, + pphost->device_prop.devepdesc[0][epnum].bEndpointAddress); + usb_host_chopen(pdev, + HID_Machine.hc_num_in, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_INTR, + HID_Machine.length); + } else { + HID_Machine.HIDIntOutEp = (pphost->device_prop.devepdesc[0][epnum].bEndpointAddress); + HID_Machine.hc_num_out = usb_host_distrch(pdev, + pphost->device_prop.devepdesc[0][epnum].bEndpointAddress); + usb_host_chopen(pdev, + HID_Machine.hc_num_out, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_INTR, + HID_Machine.length); + } + } + start_toggle = 0U; + status = HSTATUS_OK; + } else { + pphost->user_callbk->huser_devunsupported(); + } + return status; +} + +/** + * @brief deinitialize the channels for the hid class + * @param [in] pdev device instance + * @retval None + */ +void usb_host_hid_itfdeinit(usb_core_instance *pdev) +{ + if (HID_Machine.hc_num_in != 0x00U) { + usb_hchstop(&pdev->regs, HID_Machine.hc_num_in); + (void)usb_host_freech(pdev, HID_Machine.hc_num_in); + HID_Machine.hc_num_in = 0U; + } + + if (HID_Machine.hc_num_out != 0x00U) { + usb_hchstop(&pdev->regs, HID_Machine.hc_num_out); + (void)usb_host_freech(pdev, HID_Machine.hc_num_out); + HID_Machine.hc_num_out = 0U; + } + start_toggle = 0U; +} + +/** + * @brief This function is responsible for handling requests about HID class. + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_hid_classreq(usb_core_instance *pdev, void *phost) +{ + HOST_STATUS status; + HOST_STATUS classReqStatus; + USBH_HOST *pphost = phost; + status = HSTATUS_BUSY; + switch (HID_Machine.ctl_state) { + case HID_IDLE: + case HID_REQ_GET_HID_DESC: + if (usb_host_get_hiddesc(pdev, pphost, USB_HID_DESC_SIZE) == HSTATUS_OK) { + usb_host_parse_hiddesc(&HID_Desc, pdev->host.Rx_Buffer); + HID_Machine.ctl_state = HID_REQ_GET_REPORT_DESC; + } + break; + case HID_REQ_GET_REPORT_DESC: + if (usb_host_get_hidreportdesc(pdev, pphost, HID_Desc.wItemLength) == HSTATUS_OK) { + HID_Machine.ctl_state = HID_REQ_SET_IDLE; + } + break; + case HID_REQ_SET_IDLE: + classReqStatus = usb_host_set_hididle(pdev, pphost, 0U, 0U); + if (classReqStatus == HSTATUS_OK) { + HID_Machine.ctl_state = HID_REQ_SET_PROTOCOL; + } else if (classReqStatus == HSTATUS_UNSUPPORTED) { + HID_Machine.ctl_state = HID_REQ_SET_PROTOCOL; + } else { + /*reserved*/ + } + break; + case HID_REQ_SET_PROTOCOL: + if (usb_host_set_hidprotocol(pdev, pphost, 0U) == HSTATUS_OK) { + HID_Machine.ctl_state = HID_REQ_IDLE; + status = HSTATUS_OK; + } + break; + default: + break; + } + return status; +} + +/** + * @brief This function is to process the state machine for HID data transmitting + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_hid_process(usb_core_instance *pdev, void *phost) +{ + HOST_STATUS status; + USBH_HOST *pphost = phost; + status = HSTATUS_OK; + switch (HID_Machine.state) { + case HID_IDLE: + HID_Machine.cb->Init(); + HID_Machine.state = HID_SYNC; + case HID_SYNC: + if (usb_ifevenframe(&pdev->regs) == TRUE) { + HID_Machine.state = HID_GET_DATA; + } + break; + case HID_GET_DATA: + usb_host_recvintdata(pdev, + HID_Machine.buff, + HID_Machine.length, + HID_Machine.hc_num_in); + start_toggle = 1U; + HID_Machine.state = HID_POLL; + HID_Machine.timer = (uint16_t)host_driver_getcurrentfrm(pdev); + break; + case HID_POLL: + if ((host_driver_getcurrentfrm(pdev) - HID_Machine.timer) >= HID_Machine.poll) { + HID_Machine.state = HID_GET_DATA; + } else if (host_driver_getxferstate(pdev, HID_Machine.hc_num_in) == HOST_CH_XFER_DONE) { + if (start_toggle == 1U) { + start_toggle = 0U; + HID_Machine.cb->Decode(HID_Machine.buff); + } + } else if (host_driver_getxferstate(pdev, HID_Machine.hc_num_in) == HOST_CH_XFER_STALL) { + /* Issue Clear Feature on interrupt IN endpoint */ + if ((usb_host_clrfeature(pdev, + pphost, + HID_Machine.ep_addr, + HID_Machine.hc_num_in)) == HSTATUS_OK) { + HID_Machine.state = HID_GET_DATA; + } + } else { + /*reserved*/ + } + break; + default: + break; + } + return status; +} + +/** + * @brief Issue hid report descriptor command to the device, parse the report + * descriptor and update the status once the response received. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] length the length of the hid descriptor in bytes + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_get_hidreportdesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length) +{ + HOST_STATUS status; + status = usb_host_getdesc(pdev, + phost, + USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_STANDARD, + USB_DESC_HID_REPORT, + pdev->host.Rx_Buffer, + length); + return status; +} + +/** + * @brief Issue HID descriptor command to the device, parse the descriptor + * and update the status once the response received. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] length length of HID descriptor in bytes + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_get_hiddesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length) +{ + HOST_STATUS status; + status = usb_host_getdesc(pdev, + phost, + USB_REQ_RECIPIENT_INTERFACE + | USB_REQ_TYPE_STANDARD, + USB_DESC_HID, + pdev->host.Rx_Buffer, + length); + return status; +} + +/** + * @brief Set hid application to be idle status. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] duration Duration for HID Idle request + * @param [in] reportId Targetted report ID for Set Idle request + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_set_hididle(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t duration, + uint8_t reportId) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_CLASS; + + phost->ctrlparam.setup.b.bRequest = USB_HID_SET_IDLE; + phost->ctrlparam.setup.b.wValue.w = ((uint16_t)duration << 8) | (uint16_t)reportId; + + phost->ctrlparam.setup.b.wIndex.w = 0U; + phost->ctrlparam.setup.b.wLength.w = 0U; + + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief Issues a command to set report + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] reportType the report type to be sent + * @param [in] reportId target report ID for set report request + * @param [in] reportLen length of data of report to be sent in bytes + * @param [in] reportBuff report buffer + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_set_hidreport(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t reportType, + uint8_t reportId, + uint8_t reportLen, + uint8_t *reportBuff) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_CLASS; + phost->ctrlparam.setup.b.bRequest = USB_HID_SET_REPORT; + phost->ctrlparam.setup.b.wValue.w = ((uint16_t)reportType << 8) | (uint16_t)reportId; + phost->ctrlparam.setup.b.wIndex.w = 0U; + phost->ctrlparam.setup.b.wLength.w = reportLen; + return usb_host_ctrlreq(pdev, phost, reportBuff, reportLen); +} + +/** + * @brief Set protocol state of the hid application. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] protocol protocol for HID application + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_set_hidprotocol(usb_core_instance *pdev, USBH_HOST *phost, uint8_t protocol) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_CLASS; + phost->ctrlparam.setup.b.bRequest = USB_HID_SET_PROTOCOL; + if (protocol != 0U) { + /* Boot Protocol */ + phost->ctrlparam.setup.b.wValue.w = 0U; + } else { + /* Report Protocol */ + phost->ctrlparam.setup.b.wValue.w = 1U; + } + phost->ctrlparam.setup.b.wIndex.w = 0U; + phost->ctrlparam.setup.b.wLength.w = 0U; + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief parse the HID descriptor + * @param [in] desc used to get the fields parsed from the data buffer + * @param [in] buf Buffer where the source descriptor is available + * @retval None + */ +void usb_host_parse_hiddesc(USB_HOST_HIDDesc_TypeDef *desc, uint8_t *buf) +{ + desc->bLength = *(uint8_t *)(buf + 0); + desc->bDescriptorType = *(uint8_t *)(buf + 1); + desc->bcdHID = SMALL_END(buf + 2); + desc->bCountryCode = *(uint8_t *)(buf + 4); + desc->bNumDescriptors = *(uint8_t *)(buf + 5); + desc->bReportDescriptorType = *(uint8_t *)(buf + 6); + desc->wItemLength = SMALL_END(buf + 7); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.h new file mode 100644 index 0000000000..101792f3f6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.h @@ -0,0 +1,167 @@ +/** + ******************************************************************************* + * @file usb_host_hid_class.h + * @brief header file for the usb_host_hid_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_HID_CLASS_H__ +#define __USB_HOST_HID_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_HID + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/* States for HID State Machine */ +typedef enum { + HID_IDLE = 0, + HID_SEND_DATA, + HID_BUSY, + HID_GET_DATA, + HID_SYNC, + HID_POLL, + HID_ERROR, +} +HID_State; + +typedef enum { + HID_REQ_IDLE = 0, + HID_REQ_GET_REPORT_DESC, + HID_REQ_GET_HID_DESC, + HID_REQ_SET_IDLE, + HID_REQ_SET_PROTOCOL, + HID_REQ_SET_REPORT, + +} +HID_CtlState; + +typedef struct { + void (*Init)(void); + void (*Decode)(uint8_t *data); + +} HID_cb_TypeDef; + +typedef struct { + uint8_t ReportID; + uint8_t ReportType; + uint16_t UsagePage; + uint32_t Usage[2]; + uint32_t NbrUsage; + uint32_t UsageMin; + uint32_t UsageMax; + int32_t LogMin; + int32_t LogMax; + int32_t PhyMin; + int32_t PhyMax; + int32_t UnitExp; + uint32_t Unit; + uint32_t ReportSize; + uint32_t ReportCnt; + uint32_t Flag; + uint32_t PhyUsage; + uint32_t AppUsage; + uint32_t LogUsage; +} HID_Report_TypeDef; + +/* Structure for HID process */ +typedef struct { + uint8_t buff[64]; + uint8_t hc_num_in; + uint8_t hc_num_out; + HID_State state; + uint8_t HIDIntOutEp; + uint8_t HIDIntInEp; + HID_CtlState ctl_state; + uint16_t length; + uint8_t ep_addr; + uint16_t poll; + __IO uint16_t timer; + HID_cb_TypeDef *cb; +} HID_Machine_TypeDef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_HID_REQ_GET_REPORT (0x01) +#define USB_HID_GET_IDLE (0x02) +#define USB_HID_GET_PROTOCOL (0x03) +#define USB_HID_SET_REPORT (0x09) +#define USB_HID_SET_IDLE (0x0A) +#define USB_HID_SET_PROTOCOL (0x0B) + +#define HID_MIN_POLL (10U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_host_class_callback_func USBH_HID_cb; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern HOST_STATUS usb_host_set_hidreport(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t reportType, + uint8_t reportId, + uint8_t reportLen, + uint8_t *reportBuff); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_HID_CLASS_H__ */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.c new file mode 100644 index 0000000000..114b53c2fa --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.c @@ -0,0 +1,277 @@ +/** + ******************************************************************************* + * @file usb_host_hid_keyboardapp.c + * @brief The application layer for USB Host HID Keyboard handling + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_hid_keyboardapp.h" +#include "usb_host_user.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_HID + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void keyboard_init(void); +void keyboard_decode(uint8_t *pbuf); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined (__CC_ARM) /*!< ARM Compiler */ +__align(4) +#elif defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#elif defined (__GNUC__) /*!< GNU Compiler */ +#pragma pack(4) +#endif /* __CC_ARM */ +#endif + +HID_cb_TypeDef HID_KEYBRD_cb = { + keyboard_init, + keyboard_decode +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static const uint8_t HID_KEYBRD_Codes[] = { + 0, 0, 0, 0, 31, 50, 48, 33, + 19, 34, 35, 36, 24, 37, 38, 39, /* 0x00 - 0x0F */ + 52, 51, 25, 26, 17, 20, 32, 21, + 23, 49, 18, 47, 22, 46, 2, 3, /* 0x10 - 0x1F */ + 4, 5, 6, 7, 8, 9, 10, 11, + 43, 110, 15, 16, 61, 12, 13, 27, /* 0x20 - 0x2F */ + 28, 29, 42, 40, 41, 1, 53, 54, + 55, 30, 112, 113, 114, 115, 116, 117, /* 0x30 - 0x3F */ + 118, 119, 120, 121, 122, 123, 124, 125, + 126, 75, 80, 85, 76, 81, 86, 89, /* 0x40 - 0x4F */ + 79, 84, 83, 90, 95, 100, 105, 106, + 108, 93, 98, 103, 92, 97, 102, 91, /* 0x50 - 0x5F */ + 96, 101, 99, 104, 45, 129, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x60 - 0x6F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x70 - 0x7F */ + 0, 0, 0, 0, 0, 107, 0, 56, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x80 - 0x8F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x90 - 0x9F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xA0 - 0xAF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xB0 - 0xBF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xC0 - 0xCF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xD0 - 0xDF */ + 58, 44, 60, 127, 64, 57, 62, 128 /* 0xE0 - 0xE7 */ +}; + +#ifdef QWERTY_KEYBOARD +static const uint8_t HID_KEYBRD_Key[] = { + '\0', '`', '1', '2', '3', '4', '5', '6', + '7', '8', '9', '0', '-', '=', '\0', '\r', + '\t', 'q', 'w', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', + '\0', 'a', 's', 'd', 'f', 'g', 'h', 'j', + 'k', 'l', ';', '\'', '\0', '\n', + '\0', '\0', 'z', 'x', 'c', 'v', 'b', 'n', + 'm', ',', '.', '/', '\0', '\0', + '\0', '\0', '\0', ' ', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '7', '4', '1', + '\0', '/', '8', '5', '2', + '0', '*', '9', '6', '3', + '.', '-', '+', '\0', '\n', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0' +}; + +static const uint8_t HID_KEYBRD_ShiftKey[] = { + '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', + '_', '+', '\0', '\0', '\0', 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', + 'I', 'O', 'P', '{', '}', '|', '\0', 'A', 'S', 'D', 'F', 'G', + 'H', 'J', 'K', 'L', ':', '"', '\0', '\n', '\0', '\0', 'Z', 'X', + 'C', 'V', 'B', 'N', 'M', '<', '>', '?', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +#else + +static const uint8_t HID_KEYBRD_Key[] = { + '\0', '`', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', + '-', '=', '\0', '\r', '\t', 'a', 'z', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', '\0', 'q', 's', 'd', 'f', 'g', + 'h', 'j', 'k', 'l', 'm', '\0', '\0', '\n', '\0', '\0', 'w', 'x', + 'c', 'v', 'b', 'n', ',', ';', ':', '!', '\0', '\0', '\0', '\0', + '\0', ' ', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '7', '4', '1', '\0', '/', + '8', '5', '2', '0', '*', '9', '6', '3', '.', '-', '+', '\0', + '\n', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +static const uint8_t HID_KEYBRD_ShiftKey[] = { + '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', + '+', '\0', '\0', '\0', 'A', 'Z', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', + 'P', '{', '}', '*', '\0', 'Q', 'S', 'D', 'F', 'G', 'H', 'J', 'K', + 'L', 'M', '%', '\0', '\n', '\0', '\0', 'W', 'X', 'C', 'V', 'B', 'N', + '?', '.', '/', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; +#endif + +/** + * @brief Initialize the keyboard function. + * @param None + * @retval None + */ +void keyboard_init(void) +{ + user_keyboard_init(); +} + +/** + * @brief The function is to decode the pressed keys when receives key value. + * @param [in] pbuf buffer contain the HID IN report data. + * @retval None + */ +void keyboard_decode(uint8_t *pbuf) +{ + static uint8_t shift; + static uint8_t keys[KBR_MAX_NBR_PRESSED]; + static uint8_t keys_new[KBR_MAX_NBR_PRESSED]; + static uint8_t keys_last[KBR_MAX_NBR_PRESSED]; + static uint8_t key_newest; + static uint8_t nbr_keys; + static uint8_t nbr_keys_new; + static uint8_t nbr_keys_last; + uint8_t ix; + uint8_t jx; + uint8_t error; + uint8_t output; + + nbr_keys = 0U; + nbr_keys_new = 0U; + nbr_keys_last = 0U; + key_newest = 0U; + + /* Check if Shift key is pressed */ + if ((pbuf[0] == KBD_LEFT_SHIFT) || (pbuf[0] == KBD_RIGHT_SHIFT)) { + shift = TRUE; + } else { + shift = FALSE; + } + + error = FALSE; + /* Check for the value of pressed key */ + for (ix = 2U; ix < 2U + KBR_MAX_NBR_PRESSED; ix++) { + if ((pbuf[ix] == 0x01U) || (pbuf[ix] == 0x02U) || (pbuf[ix] == 0x03U)) { + error = TRUE; + } + } + if (error == TRUE) { + return; + } + nbr_keys = 0U; + nbr_keys_new = 0U; + for (ix = 2U; ix < 2U + KBR_MAX_NBR_PRESSED; ix++) { + if (pbuf[ix] != 0U) { + keys[nbr_keys] = pbuf[ix]; + nbr_keys++; + for (jx = 0U; jx < nbr_keys_last; jx++) { + if (pbuf[ix] == keys_last[jx]) { + break; + } + } + if (jx == nbr_keys_last) { + keys_new[nbr_keys_new] = pbuf[ix]; + nbr_keys_new++; + } + } + } + if (nbr_keys_new == 1U) { + key_newest = keys_new[0]; + + if (shift == TRUE) { + output = HID_KEYBRD_ShiftKey[HID_KEYBRD_Codes[key_newest]]; + } else { + output = HID_KEYBRD_Key[HID_KEYBRD_Codes[key_newest]]; + } + /* call user process handle */ + user_keyboard_dataprocess(output); + } else { + key_newest = 0x00U; + } + nbr_keys_last = nbr_keys; + for (ix = 0U; ix < KBR_MAX_NBR_PRESSED; ix++) { + keys_last[ix] = keys[ix]; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.h new file mode 100644 index 0000000000..8e662c1a19 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.h @@ -0,0 +1,99 @@ +/** + ******************************************************************************* + * @file usb_host_hid_keyboardapp.h + * @brief Head file for usb_host_hid_keyboardapp.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_HID_KEYBOARDAPP_H__ +#define __USB_HOST_HID_KEYBOARDAPP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_hid_class.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_HID + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define QWERTY_KEYBOARD +/* #define AZERTY_KEYBOARD */ + +#define KBD_LEFT_CTRL (0x01U) +#define KBD_LEFT_SHIFT (0x02U) +#define KBD_LEFT_ALT (0x04U) +#define KBD_LEFT_GUI (0x08U) +#define KBD_RIGHT_CTRL (0x10U) +#define KBD_RIGHT_SHIFT (0x20U) +#define KBD_RIGHT_ALT (0x40U) +#define KBD_RIGHT_GUI (0x80U) + +#define KBR_MAX_NBR_PRESSED (6U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern HID_cb_TypeDef HID_KEYBRD_cb; + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_HID_KEYBOARDAPP_H__ */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.c new file mode 100644 index 0000000000..418db2c623 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.c @@ -0,0 +1,122 @@ +/** + ******************************************************************************* + * @file usb_host_hid_mouseapp.c + * @brief The application layer for USB Host HID Mouse Handling. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_hid_mouseapp.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_HID + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +void mouse_init(void); +void mouse_decode(uint8_t *data); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined (__CC_ARM) /*!< ARM Compiler */ +__align(4) +#elif defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#elif defined (__GNUC__) /*!< GNU Compiler */ +#pragma pack(4) +#elif defined (__TASKING__) /*!< TASKING Compiler */ +__align(4) +#endif /* __CC_ARM */ +#endif + +HID_MOUSE_Data_TypeDef HID_MOUSE_Data; +HID_cb_TypeDef HID_MOUSE_cb = { + mouse_init, + mouse_decode, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief initialize the mouse application of the hid class + * @param None + * @retval None + */ +void mouse_init(void) +{ + /* Call User Init*/ + user_mouse_init(); +} + +/** + * @brief decode the mouse report data + * @param [in] data buffer of the hid report data + * @retval None + */ +void mouse_decode(uint8_t *data) +{ + HID_MOUSE_Data.button = data[0]; + HID_MOUSE_Data.x = data[1]; + HID_MOUSE_Data.y = data[2]; + user_mouse_dataprocess(&HID_MOUSE_Data); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.h new file mode 100644 index 0000000000..284eeba129 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.h @@ -0,0 +1,92 @@ +/** + ******************************************************************************* + * @file usb_host_hid_mouseapp.h + * @brief Head file for usb_host_hid_mouseapp.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_HID_MOUSEAPP_H__ +#define __USB_HOST_HID_MOUSEAPP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_hid_class.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_HID + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef struct _HID_MOUSE_Data { + uint8_t z; + uint8_t button; + uint8_t x; /* Not Supported */ + uint8_t y; +} +HID_MOUSE_Data_TypeDef; + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern HID_cb_TypeDef HID_MOUSE_cb; +extern HID_MOUSE_Data_TypeDef HID_MOUSE_Data; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +void user_mouse_init(void); +void user_mouse_dataprocess(HID_MOUSE_Data_TypeDef *data); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_HID_MOUSEAPP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.c new file mode 100644 index 0000000000..a01939e9df --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.c @@ -0,0 +1,449 @@ +/** + ******************************************************************************* + * @file usb_host_msc_bot.c + * @brief mass storage related functions + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_msc_class.h" +#include "usb_host_msc_scsi.h" +#include "usb_host_msc_bot.h" +#include "usb_host_ctrltrans.h" +#include "usb_host_def.h" +#include "usb_host_int.h" +#include "usb_host_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_MSC USB Host MSC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN HOST_CSW_PACKET_TypeDef USBH_MSC_CSWData; + +USB_HOST_BOTXFER_TypeDef USBH_MSC_BOTXferParam; + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN HostCBWPkt_TypeDef USBH_MSC_CBWData; + +static uint32_t BOTStallErrorCount; /* Keeps count of STALL Error Cases*/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief initializes original state of the mass storage parameters + * @param [in] pdev device instance + * @retval None + */ +void usb_host_msc_init(usb_core_instance *pdev) +{ + if (host_driver_ifdevconnected(pdev) != 0UL) { + USBH_MSC_CBWData.field.CBWSignature = HOST_MSC_BOT_CBW_SIGNATURE; + USBH_MSC_CBWData.field.CBWTag = HOST_MSC_BOT_CBW_TAG; + USBH_MSC_CBWData.field.CBWLUN = 0U; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + } + BOTStallErrorCount = 0UL; + MSCErrorCount = 0U; +} + +/** + * @brief manages the different states of BOT transfer and updates the + * status for the upper layer. + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval None + */ +void usb_host_msc_botxferprocess(usb_core_instance *pdev, USBH_HOST *phost) +{ + uint8_t xferDirection, index; + static uint32_t remainingDataLength; + static uint8_t *datapointer, *datapointer_prev; + static uint8_t error_direction; + HOST_STATUS status; + + HOST_CH_XFER_STATE URB_Status; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + + switch (USBH_MSC_BOTXferParam.BOTState) { + case HOST_MSC_SEND_CBW: + /* send a CBW */ + usb_host_sendbulkdata(pdev, + &USBH_MSC_CBWData.CBWArray[0], + HOST_MSC_BOT_CBW_PACKET_LENGTH, + MSC_Machine.hc_num_out); + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_SEND_CBW; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SENT_CBW; + break; + case HOST_MSC_SENT_CBW: + URB_Status = host_driver_getxferstate(pdev, MSC_Machine.hc_num_out); + switch (URB_Status) { + case HOST_CH_XFER_DONE: + BOTStallErrorCount = 0U; + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_SENT_CBW; + /* If the CBW packet is sent successful, then update the state */ + xferDirection = (USBH_MSC_CBWData.field.CBWFlags & USB_REQ_DIR_MASK); + if (USBH_MSC_CBWData.field.CBWTransferLength != 0UL) { + remainingDataLength = USBH_MSC_CBWData.field.CBWTransferLength ; + datapointer = USBH_MSC_BOTXferParam.pRxTxBuff; + datapointer_prev = datapointer; + /* If there has data transfer stage, update the direction whether it is D2H or H2D */ + if (xferDirection == USB_D2H) { + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_DATAIN_STATE; + } else { + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_DATAOUT_STATE; + } + } else { + /* If there has not data transfer stage also update the state */ + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_RECEIVE_CSW_STATE; + } + break; + case HOST_CH_XFER_UNREADY: + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; + break; + case HOST_CH_XFER_STALL: + error_direction = HOST_MSC_DIR_OUT; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_OUT; + break; + default: + break; + } + break; + + case HOST_MSC_BOT_DATAIN_STATE: + URB_Status = host_driver_getxferstate(pdev, MSC_Machine.hc_num_in); + if ((URB_Status == HOST_CH_XFER_DONE) \ + || (USBH_MSC_BOTXferParam.BOTStateBkp != HOST_MSC_BOT_DATAIN_STATE)) { + BOTStallErrorCount = 0U; + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_BOT_DATAIN_STATE; + + if (remainingDataLength > MSC_Machine.MSC_BulkInEpSize) { + usb_host_recvbulkdata(pdev, + datapointer, + MSC_Machine.MSC_BulkInEpSize, + MSC_Machine.hc_num_in); + remainingDataLength -= MSC_Machine.MSC_BulkInEpSize; + datapointer = datapointer + MSC_Machine.MSC_BulkInEpSize; + } else if (remainingDataLength == 0UL) { + /* If value was 0, and successful transfer, then change the state */ + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_RECEIVE_CSW_STATE; + } else { + usb_host_recvbulkdata(pdev, + datapointer, + (uint16_t)remainingDataLength, + MSC_Machine.hc_num_in); + remainingDataLength = 0UL; + } + } else if (URB_Status == HOST_CH_XFER_STALL) { + error_direction = HOST_MSC_DIR_IN; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_IN; + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_RECEIVE_CSW_STATE; + } else { + ; + } + break; + case HOST_MSC_BOT_DATAOUT_STATE: + URB_Status = host_driver_getxferstate(pdev, MSC_Machine.hc_num_out); + if (URB_Status == HOST_CH_XFER_DONE) { + BOTStallErrorCount = 0UL; + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_BOT_DATAOUT_STATE; + if (remainingDataLength > MSC_Machine.MSC_BulkOutEpSize) { + usb_host_sendbulkdata(pdev, + datapointer, + MSC_Machine.MSC_BulkOutEpSize, + MSC_Machine.hc_num_out); + datapointer_prev = datapointer; + datapointer = datapointer + MSC_Machine.MSC_BulkOutEpSize; + + remainingDataLength = remainingDataLength - MSC_Machine.MSC_BulkOutEpSize; + } else if (remainingDataLength == 0UL) { + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_RECEIVE_CSW_STATE; + } else { + usb_host_sendbulkdata(pdev, + datapointer, + (uint16_t)remainingDataLength, + MSC_Machine.hc_num_out); + remainingDataLength = 0UL; + } + } else if (URB_Status == HOST_CH_XFER_UNREADY) { + if (datapointer != datapointer_prev) { + usb_host_sendbulkdata(pdev, + (datapointer - MSC_Machine.MSC_BulkOutEpSize), + MSC_Machine.MSC_BulkOutEpSize, + MSC_Machine.hc_num_out); + } else { + usb_host_sendbulkdata(pdev, + datapointer, + MSC_Machine.MSC_BulkOutEpSize, + MSC_Machine.hc_num_out); + } + } else if (URB_Status == HOST_CH_XFER_STALL) { + error_direction = HOST_MSC_DIR_OUT; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_OUT; + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_RECEIVE_CSW_STATE; + } else { + ; + } + break; + + case HOST_MSC_RECEIVE_CSW_STATE: + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_RECEIVE_CSW_STATE; + USBH_MSC_BOTXferParam.pRxTxBuff = USBH_MSC_CSWData.CSWArray; + USBH_MSC_BOTXferParam.DataLength = HOST_MSC_CSW_MAX_LENGTH; + for (index = 0U; index < HOST_MSC_CSW_LENGTH; index++) { + USBH_MSC_CSWData.CSWArray[index] = 0U; + } + + USBH_MSC_CSWData.CSWArray[0] = 0U; + usb_host_recvbulkdata(pdev, + USBH_MSC_BOTXferParam.pRxTxBuff, + HOST_MSC_CSW_MAX_LENGTH, + MSC_Machine.hc_num_in); + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_DECODE_CSW; + + break; + + case HOST_MSC_DECODE_CSW: + URB_Status = host_driver_getxferstate(pdev, MSC_Machine.hc_num_in); + if (URB_Status == HOST_CH_XFER_DONE) { + BOTStallErrorCount = 0UL; + USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_RECEIVE_CSW_STATE; + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateCurrent ; + USBH_MSC_BOTXferParam.BOTXferStatus = usb_host_msc_cswdecode(pdev, phost); + } else if (URB_Status == HOST_CH_XFER_STALL) { + error_direction = HOST_MSC_DIR_IN; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_IN; + } else { + ; + } + break; + + case HOST_MSC_BOT_ERROR_IN: + status = usb_host_msc_botabort(pdev, phost, HOST_MSC_DIR_IN); + if (status == HSTATUS_OK) { + if (error_direction == HOST_MSC_BOTH_DIR) { + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_OUT; + } else { + /* switch back to the original state */ + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; + } + } else if (status == HSTATUS_UNRECOVERED_ERROR) { + /* This means that there is a STALL Error limit, Do Reset Recovery */ + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_PHASE_ERROR; + } else { + ; + } + break; + case HOST_MSC_BOT_ERROR_OUT: + status = usb_host_msc_botabort(pdev, phost, HOST_MSC_DIR_OUT); + if (status == HSTATUS_OK) { + /* switch back to the original state */ + USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; + } else if (status == HSTATUS_UNRECOVERED_ERROR) { + /* This means that there is a STALL Error limit, Do Reset Recovery */ + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_PHASE_ERROR; + } else { + ; + } + break; + + default: + break; + } + } +} + +/** + * @brief manages the different Error handling for STALL + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] direction IN / OUT + * @retval None + */ +HOST_STATUS usb_host_msc_botabort(usb_core_instance *pdev, USBH_HOST *phost, uint8_t direction) +{ + HOST_STATUS status; + + status = HSTATUS_BUSY; + + switch (direction) { + case HOST_MSC_DIR_IN: + /* send ClrFeture on Bulk IN endpoint */ + status = usb_host_clrfeature(pdev, + phost, + MSC_Machine.MSC_BulkInEp, + MSC_Machine.hc_num_in); + break; + case HOST_MSC_DIR_OUT: + /* send ClrFeature on Bulk OUT endpoint */ + status = usb_host_clrfeature(pdev, + phost, + MSC_Machine.MSC_BulkOutEp, + MSC_Machine.hc_num_out); + break; + default: + break; + } + BOTStallErrorCount++; + if (BOTStallErrorCount > 4UL) { + status = HSTATUS_UNRECOVERED_ERROR; + } + return status; +} + +/** + * @brief Decodes the CSW received by the device and updates the same to upper layer + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval On success USB_HOST_MSC_OK, on failure USB_HOST_MSC_FAIL + */ +uint8_t usb_host_msc_cswdecode(usb_core_instance *pdev, USBH_HOST *phost) +{ + USB_HOST_MSC_STATUS status; + uint32_t dataXferCount; + status = USB_HOST_MSC_FAIL; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + dataXferCount = host_driver_getxfercnt(pdev, MSC_Machine.hc_num_in); + if (dataXferCount != HOST_MSC_CSW_LENGTH) { + /*(4) Hi > Dn (Host expects to receive data from the device, + Device intends to transfer no data) + (5) Hi > Di (Host expects to receive data from the device, + Device intends to send data to the host) + (9) Ho > Dn (Host expects to send data to the device, + Device intends to transfer no data) + (11) Ho > Do (Host expects to send data to the device, + Device intends to receive data from the host)*/ + status = USB_HOST_MSC_PHASE_ERROR; + } else { + /* CSW length is Correct */ + + /* Check validity of the CSW Signature and CSWStatus */ + if (USBH_MSC_CSWData.field.dCSWSignature == HOST_MSC_BOT_CSW_SIGNATURE) { + /* Check Condition 1. dCSWSignature is equal to 53425355h */ + if (USBH_MSC_CSWData.field.dCSWTag == USBH_MSC_CBWData.field.CBWTag) { + /* Check Condition 3. dCSWTag matches the dCBWTag from the + corresponding CBW */ + if (USBH_MSC_CSWData.field.dCSWStatus == (uint8_t)USB_HOST_MSC_OK) { + /* Refer to USB Mass-Storage Class : BOT (www.usb.org) + + Hn Host expects no data transfers + Hi Host expects to receive data from the device + Ho Host expects to send data to the device + + Dn Device intends to transfer no data + Di Device intends to send data to the host + Do Device intends to receive data from the host + + Section 6.7 + (1) Hn = Dn (Host expects no data transfers, + Device intends to transfer no data) + (6) Hi = Di (Host expects to receive data from the device, + Device intends to send data to the host) + (12) Ho = Do (Host expects to send data to the device, + Device intends to receive data from the host) + */ + status = USB_HOST_MSC_OK; + } else if (USBH_MSC_CSWData.field.dCSWStatus == (uint8_t)USB_HOST_MSC_FAIL) { + status = USB_HOST_MSC_FAIL; + } else if (USBH_MSC_CSWData.field.dCSWStatus == (uint8_t)USB_HOST_MSC_PHASE_ERROR) { + /* Refer to USB Mass-Storage Class : BOT (www.usb.org) + Section 6.7 + (2) Hn < Di ( Host expects no data transfers, + Device intends to send data to the host) + (3) Hn < Do ( Host expects no data transfers, + Device intends to receive data from the host) + (7) Hi < Di ( Host expects to receive data from the device, + Device intends to send data to the host) + (8) Hi <> Do ( Host expects to receive data from the device, + Device intends to receive data from the host) + (10) Ho <> Di (Host expects to send data to the device, + Di Device intends to send data to the host) + (13) Ho < Do (Host expects to send data to the device, + Device intends to receive data from the host) + */ + status = USB_HOST_MSC_PHASE_ERROR; + } else { + ; + } + } + } else { + status = USB_HOST_MSC_PHASE_ERROR; + } + } + } + + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)status; + return (uint8_t)status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.h new file mode 100644 index 0000000000..b51cc3bbd9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.h @@ -0,0 +1,162 @@ +/** + ******************************************************************************* + * @file usb_host_msc_bot.h + * @brief Head file for usb_host_msc_bot.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_MSC_BOT_H__ +#define __USB_HOST_MSC_BOT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_stdreq.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_MSC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +typedef union _USBH_CBW_Block { + struct __CBW { + uint32_t CBWSignature; + uint32_t CBWTag; + uint32_t CBWTransferLength; + uint8_t CBWFlags; + uint8_t CBWLUN; + uint8_t CBWLength; + uint8_t CBWCB[16]; + } field; + uint8_t CBWArray[31]; +} HostCBWPkt_TypeDef; + +typedef struct { + uint8_t MSCState; + uint8_t MSCStateBkp; + uint8_t MSCStateCurrent; + uint8_t CmdStateMachine; + uint8_t BOTState; + uint8_t BOTStateBkp; + uint8_t *pRxTxBuff; + uint16_t DataLength; + uint8_t BOTXferStatus; +} USB_HOST_BOTXFER_TypeDef; + +typedef union { + struct { + uint32_t dCSWSignature; + uint32_t dCSWTag; + uint32_t dCSWDataResidue; + uint8_t dCSWStatus; + } field; + uint8_t CSWArray[13]; +} HOST_CSW_PACKET_TypeDef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define HOST_MSC_BOT_INIT_STATE (0U) +#define HOST_MSC_BOT_RESET (1U) +#define HOST_MSC_GET_MAX_LUN (2U) +#define HOST_MSC_TEST_UNIT_READY (3U) +#define HOST_MSC_READ_CAPACITY10 (4U) +#define HOST_MSC_MODE_SENSE6 (5U) +#define HOST_MSC_REQUEST_SENSE (6U) +#define HOST_MSC_BOT_USB_TRANSFERS (7U) +#define HOST_MSC_DEFAULT_APPLI_STATE (8U) +#define HOST_MSC_CTRL_ERROR_STATE (9U) +#define HOST_MSC_UNRECOVERED_STATE (10U) + +#define HOST_MSC_SEND_CBW (1U) +#define HOST_MSC_SENT_CBW (2U) +#define HOST_MSC_BOT_DATAIN_STATE (3U) +#define HOST_MSC_BOT_DATAOUT_STATE (4U) +#define HOST_MSC_RECEIVE_CSW_STATE (5U) +#define HOST_MSC_DECODE_CSW (6U) +#define HOST_MSC_BOT_ERROR_IN (7U) +#define HOST_MSC_BOT_ERROR_OUT (8U) + +#define HOST_MSC_BOT_CBW_SIGNATURE (0x43425355UL) +#define HOST_MSC_BOT_CBW_TAG (0x20304050UL) +#define HOST_MSC_BOT_CSW_SIGNATURE (0x53425355UL) +#define HOST_MSC_CSW_DATA_LENGTH (13U) +#define HOST_MSC_BOT_CBW_PACKET_LENGTH (31U) +#define HOST_MSC_CSW_LENGTH (13U) +#define HOST_MSC_CSW_MAX_LENGTH (63U) +#define HOST_MSC_DIR_IN (0U) +#define HOST_MSC_DIR_OUT (1U) +#define HOST_MSC_BOTH_DIR (2U) +#define HOST_MSC_PAGE_LENGTH (512UL) + +#define CBW_CB_LENGTH (16U) +#define CBW_LENGTH (10U) +#define CBW_LENGTH_TEST_UNIT_READY (6U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern USB_HOST_BOTXFER_TypeDef USBH_MSC_BOTXferParam; +extern HostCBWPkt_TypeDef USBH_MSC_CBWData; +extern HOST_CSW_PACKET_TypeDef USBH_MSC_CSWData; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern void usb_host_msc_init(usb_core_instance *pdev); +extern void usb_host_msc_botxferprocess(usb_core_instance *pdev, USBH_HOST *phost); +extern uint8_t usb_host_msc_cswdecode(usb_core_instance *pdev, USBH_HOST *phost); +extern HOST_STATUS usb_host_msc_botabort(usb_core_instance *pdev, USBH_HOST *phost, uint8_t direction); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_MSC_BOT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.c new file mode 100644 index 0000000000..b1fe4e0d49 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.c @@ -0,0 +1,395 @@ +/** + ******************************************************************************* + * @file usb_host_msc_class.c + * @brief The MSC class driver functions + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_msc_class.h" +#include "usb_host_msc_scsi.h" +#include "usb_host_msc_bot.h" +#include "usb_host_core.h" +#include "usb_host_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_MSC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USBH_MSC_ERROR_RETRY_LIMIT (10U) + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +HOST_STATUS usb_host_msc_itfinit(usb_core_instance *pdev, void *phost); +void usb_host_msc_itfdeinit(usb_core_instance *pdev); +HOST_STATUS usb_host_msc_process(usb_core_instance *pdev, void *phost); +HOST_STATUS usb_host_msc_classreq(usb_core_instance *pdev, void *phost); + +HOST_STATUS usb_host_msc_bot_reset(usb_core_instance *pdev, USBH_HOST *phost); +HOST_STATUS usb_host_msc_maxlun_get(usb_core_instance *pdev, USBH_HOST *phost); +void usb_host_msc_error_process(USB_HOST_MSC_STATUS status); + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +__USB_ALIGN_BEGIN MSC_Machine_TypeDef MSC_Machine; + +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +#endif /* USB_INTERNAL_DMA_ENABLED */ +uint8_t MSCErrorCount = 0U; + +usb_host_class_callback_func USBH_MSC_cb = { + &usb_host_msc_itfinit, + &usb_host_msc_itfdeinit, + &usb_host_msc_classreq, + &usb_host_msc_process, +}; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief This request is used to issue a request to reset the msc device and + * its related interface. This class-specific request shall prepare the + * device for the next CBW from the host. + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status define by HOST_STATUS + */ +HOST_STATUS usb_host_msc_bot_reset(usb_core_instance *pdev, USBH_HOST *phost) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | \ + USB_REQ_RECIPIENT_INTERFACE; + phost->ctrlparam.setup.b.bRequest = USB_REQ_BOT_RESET; + phost->ctrlparam.setup.b.wValue.w = 0U; + phost->ctrlparam.setup.b.wIndex.w = 0U; + phost->ctrlparam.setup.b.wLength.w = 0U; + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief this request is used to issue a request to get the max logic unit of + * the msc device. + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_msc_maxlun_get(usb_core_instance *pdev, USBH_HOST *phost) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | \ + USB_REQ_RECIPIENT_INTERFACE; + + phost->ctrlparam.setup.b.bRequest = USB_REQ_GET_MAX_LUN; + phost->ctrlparam.setup.b.wValue.w = 0U; + phost->ctrlparam.setup.b.wIndex.w = 0U; + phost->ctrlparam.setup.b.wLength.w = 1U; + return usb_host_ctrlreq(pdev, phost, MSC_Machine.buff, 1U); +} + +/** + * @brief The function is used for handling errors during processing the MSC + * state machine + * @param [in] status + * @retval None + */ +void usb_host_msc_error_process(USB_HOST_MSC_STATUS status) +{ + switch (status) { + case USB_HOST_MSC_FAIL: + MSCErrorCount++; + if (MSCErrorCount < USBH_MSC_ERROR_RETRY_LIMIT) { + /* Try MSC level error recovery, Issue the request Sense to get + driver error reason */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_REQUEST_SENSE; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + } else { + /* Error trials exceeded the limit, go to unrecovered state */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_UNRECOVERED_STATE; + } + break; + case USB_HOST_MSC_PHASE_ERROR: + /* Phase error, Go to Unrecoovered state */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_UNRECOVERED_STATE; + break; + default: + break; + } +} + +/** + * @brief Interface initialization for msc class application, the channels for + * the IN and OUT EP will be distributed. + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_msc_itfinit(usb_core_instance *pdev, void *phost) +{ + USBH_HOST *pphost = phost; + + if ((pphost->device_prop.devitfdesc[0].bInterfaceClass == MSC_CLASS) && \ + (pphost->device_prop.devitfdesc[0].bInterfaceProtocol == MSC_PROTOCOL)) { + if ((pphost->device_prop.devepdesc[0][0].bEndpointAddress & 0x80U) == 0x80U) { + MSC_Machine.MSC_BulkInEp = (pphost->device_prop.devepdesc[0][0].bEndpointAddress); + MSC_Machine.MSC_BulkInEpSize = pphost->device_prop.devepdesc[0][0].wMaxPacketSize; + } else { + MSC_Machine.MSC_BulkOutEp = (pphost->device_prop.devepdesc[0][0].bEndpointAddress); + MSC_Machine.MSC_BulkOutEpSize = pphost->device_prop.devepdesc[0] [0].wMaxPacketSize; + } + if ((pphost->device_prop.devepdesc[0][1].bEndpointAddress & 0x80U) == 0x80U) { + MSC_Machine.MSC_BulkInEp = (pphost->device_prop.devepdesc[0][1].bEndpointAddress); + MSC_Machine.MSC_BulkInEpSize = pphost->device_prop.devepdesc[0][1].wMaxPacketSize; + } else { + MSC_Machine.MSC_BulkOutEp = (pphost->device_prop.devepdesc[0][1].bEndpointAddress); + MSC_Machine.MSC_BulkOutEpSize = pphost->device_prop.devepdesc[0][1].wMaxPacketSize; + } + /* distribute the channels for the EPs */ + MSC_Machine.hc_num_out = usb_host_distrch(pdev, MSC_Machine.MSC_BulkOutEp); + MSC_Machine.hc_num_in = usb_host_distrch(pdev, MSC_Machine.MSC_BulkInEp); + /* open the channels that have distributed */ + usb_host_chopen(pdev, + MSC_Machine.hc_num_out, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_BULK, + MSC_Machine.MSC_BulkOutEpSize); + usb_host_chopen(pdev, + MSC_Machine.hc_num_in, + pphost->device_prop.devaddr, + pphost->device_prop.devspeed, + EP_TYPE_BULK, + MSC_Machine.MSC_BulkInEpSize); + } else { + pphost->user_callbk->huser_devunsupported(); + } + return HSTATUS_OK ; +} + +/** + * @brief deinitialize interface of msc class by freeing host channels + * @param [in] pdev device instance + * @retval None + */ +void usb_host_msc_itfdeinit(usb_core_instance *pdev) +{ + if (MSC_Machine.hc_num_out != 0U) { + usb_hchstop(&pdev->regs, MSC_Machine.hc_num_out); + (void)usb_host_freech(pdev, MSC_Machine.hc_num_out); + MSC_Machine.hc_num_out = 0U; + } + if (MSC_Machine.hc_num_in != 0U) { + usb_hchstop(&pdev->regs, MSC_Machine.hc_num_in); + (void)usb_host_freech(pdev, MSC_Machine.hc_num_in); + MSC_Machine.hc_num_in = 0U; + } +} + +/** + * @brief initialize the msc state machine + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_msc_classreq(usb_core_instance *pdev, void *phost) +{ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_INIT_STATE; + return HSTATUS_OK; +} + +/** + * @brief process the msc state machine + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status defined by HOST_STATUS + */ +HOST_STATUS usb_host_msc_process(usb_core_instance *pdev, void *phost) +{ + USBH_HOST *pphost = phost; + HOST_STATUS status = HSTATUS_BUSY; + USB_HOST_MSC_STATUS mscStatus; + uint8_t appliStatus; + static uint8_t maxLunExceed = FALSE; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + switch (USBH_MSC_BOTXferParam.MSCState) { + case HOST_MSC_BOT_INIT_STATE: + usb_host_msc_init(pdev); + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_RESET; + break; + case HOST_MSC_BOT_RESET: + /* issue a request to reset the bot. */ + status = usb_host_msc_bot_reset(pdev, phost); + if (status == HSTATUS_OK) { + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_GET_MAX_LUN; + } + if (status == HSTATUS_UNSUPPORTED) { + /* if the request fails, it needs to move to next state and should save the next state as backup */ + USBH_MSC_BOTXferParam.MSCStateBkp = HOST_MSC_GET_MAX_LUN; + /* a clear feature should be issued if the request fails. */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_CTRL_ERROR_STATE; + } + break; + case HOST_MSC_GET_MAX_LUN: + /* issue a request to get the max logical unit(MAXLUN). */ + status = usb_host_msc_maxlun_get(pdev, phost); + if (status == HSTATUS_OK) { + MSC_Machine.maxLun = *(MSC_Machine.buff) ; + if ((MSC_Machine.maxLun > 0U) && (maxLunExceed == FALSE)) { + maxLunExceed = TRUE; + pphost->user_callbk->huser_devunsupported(); + break; + } + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_TEST_UNIT_READY; + } + + if (status == HSTATUS_UNSUPPORTED) { + /* if the request fails, it needs to move to next state and should save the next state as backup */ + USBH_MSC_BOTXferParam.MSCStateBkp = HOST_MSC_TEST_UNIT_READY; + /* a clear feature should be issued if the request fails. */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_CTRL_ERROR_STATE; + } + break; + case HOST_MSC_CTRL_ERROR_STATE: + /* issue a request to clear feature */ + status = usb_host_clrfeature(pdev, + phost, + 0x00U, + pphost->ctrlparam.hc_num_out); + if (status == HSTATUS_OK) { + /* If GetMaxLun Request not support, assume Single LUN configuration */ + MSC_Machine.maxLun = 0U; + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateBkp; + } + break; + case HOST_MSC_TEST_UNIT_READY: + /* issue the request Test Unit Ready[0] of SCSI command */ + mscStatus = usb_host_msc_TestUnitReady(pdev); + + if (mscStatus == USB_HOST_MSC_OK) { + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_READ_CAPACITY10; + MSCErrorCount = 0U; + status = HSTATUS_OK; + } else { + usb_host_msc_error_process(mscStatus); + } + break; + + case HOST_MSC_READ_CAPACITY10: + /* issue the request Read Capacity[0] of SCSI command. */ + mscStatus = usb_host_msc_ReadCapacity10(pdev); + if (mscStatus == USB_HOST_MSC_OK) { + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_MODE_SENSE6; + MSCErrorCount = 0U; + status = HSTATUS_OK; + } else { + usb_host_msc_error_process(mscStatus); + } + break; + case HOST_MSC_MODE_SENSE6: + /* issue the request ModeSense6 of SCSI command for detecting whelth the deviec is write-protected. */ + mscStatus = usb_host_msc_ModeSense6(pdev); + if (mscStatus == USB_HOST_MSC_OK) { + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_DEFAULT_APPLI_STATE; + MSCErrorCount = 0U; + status = HSTATUS_OK; + } else { + usb_host_msc_error_process(mscStatus); + } + break; + case HOST_MSC_REQUEST_SENSE: + /* issue the request RequestSense of SCSI command for retreiving error code. */ + mscStatus = usb_host_msc_RequestSense(pdev); + if (mscStatus == USB_HOST_MSC_OK) { + USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateBkp; + status = HSTATUS_OK; + } else { + usb_host_msc_error_process(mscStatus); + } + break; + case HOST_MSC_BOT_USB_TRANSFERS: + /* handle the BOT state machine. */ + usb_host_msc_botxferprocess(pdev, phost); + break; + case HOST_MSC_DEFAULT_APPLI_STATE: + /* handle the user callback for the msc application. */ + appliStatus = pphost->user_callbk->huser_application(); + if (appliStatus == 0U) { + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_DEFAULT_APPLI_STATE; + } else if (appliStatus == 1U) { + /* deinit requested from the application layer. */ + status = HSTATUS_APP_DEINIT; + } else { + ; + } + break; + case HOST_MSC_UNRECOVERED_STATE: + status = HSTATUS_UNRECOVERED_ERROR; + break; + default: + break; + } + } + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.h new file mode 100644 index 0000000000..d37111ce7e --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.h @@ -0,0 +1,113 @@ +/** + ******************************************************************************* + * @file usb_host_msc_class.h + * @brief Head file for usb_host_msc_class.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_MSC_CLASS_H__ +#define __USB_HOST_MSC_CLASS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_core.h" +#include "usb_host_stdreq.h" +#include "usb_bsp.h" +#include "usb_host_ctrltrans.h" +#include "usb_host_cfgch.h" +#include "usb_host_msc_class.h" +#include "usb_host_msc_scsi.h" +#include "usb_host_msc_bot.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_MSC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/* Structure for MSC process */ +typedef struct { + uint8_t hc_num_in; + uint8_t hc_num_out; + uint8_t MSC_BulkOutEp; + uint8_t MSC_BulkInEp; + uint16_t MSC_BulkInEpSize; + uint16_t MSC_BulkOutEpSize; + uint8_t buff[USBH_MSC_MPS_SIZE]; + uint8_t maxLun; +} MSC_Machine_TypeDef; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_REQ_BOT_RESET (0xFFU) +#define USB_REQ_GET_MAX_LUN (0xFEU) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern usb_host_class_callback_func USBH_MSC_cb; +extern MSC_Machine_TypeDef MSC_Machine; +extern uint8_t MSCErrorCount; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_MSC_CLASS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + + + diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_fatfs.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_fatfs.c new file mode 100644 index 0000000000..d1e68d978c --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_fatfs.c @@ -0,0 +1,241 @@ +/** + ******************************************************************************* + * @file usb_host_msc_fatfs.c + * @brief The fatfs functions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_app_conf.h" +#include "usb_host_driver.h" +#ifdef USB_MSC_FAT_VALID +#include "ff.h" +#include "diskio.h" +#include "usb_host_msc_class.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_MSC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static volatile DSTATUS Stat = STA_NOINIT; /* Disk status */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +extern usb_core_instance usb_app_instance; +extern USBH_HOST usb_app_host; + +/** + * @brief Initialize Disk Drive + * @param [in] drv Physical drive number (0) + * @retval DSTATUS + */ +DSTATUS disk_initialize(BYTE drv) +{ + if (host_driver_ifdevconnected(&usb_app_instance) != 0UL) { + Stat &= (DSTATUS)~STA_NOINIT; + } + return Stat; +} + +/** + * @brief Get Disk Status + * @param [in] drv Physical drive number (0) + * @retval DSTATUS + */ +DSTATUS disk_status(BYTE drv) +{ + DSTATUS status = Stat; + if (drv != 0U) { + status = STA_NOINIT; /* Supports only single drive */ + } + return status; +} + +/** + * @brief Read Sector(s) + * @param [in] drv Physical drive number (0) + * @param [in] buff Pointer to the data buffer to store read data + * @param [in] sector Start sector number (LBA) + * @param [in] count Sector count (1..255) + * @retval DSTATUS + */ +DRESULT disk_read(BYTE pdrv, BYTE *buff, LBA_t sector, UINT count) +{ + USB_HOST_MSC_STATUS status = USB_HOST_MSC_OK; + + if ((pdrv != 0U) || (count == 0UL)) { + return RES_PARERR; + } + if ((Stat & STA_NOINIT) == STA_NOINIT) { + return RES_NOTRDY; + } + + if (host_driver_ifdevconnected(&usb_app_instance) != 0UL) { + + do { + status = usb_host_msc_Read10(&usb_app_instance, buff, sector, 512UL * (uint32_t)count); + usb_host_msc_botxferprocess(&usb_app_instance, &usb_app_host); + + if (host_driver_ifdevconnected(&usb_app_instance) == 0UL) { + return RES_ERROR; + } + } while (status == USB_HOST_MSC_BUSY); + } + + if (status == USB_HOST_MSC_OK) { + return RES_OK; + } + return RES_ERROR; + +} + + +#if _READONLY == 0 +/** + * @brief Write Sector(s) + * @param [in] drv Physical drive number (0) + * @param [in] buff Pointer to the data to be written + * @param [in] sector Start sector number (LBA) + * @param [in] count Sector count (1..255) + * @retval DSTATUS + */ +DRESULT disk_write(BYTE pdrv, const BYTE *buff, LBA_t sector, UINT count) +{ + USB_HOST_MSC_STATUS status = USB_HOST_MSC_OK; + + if ((pdrv != 0U) || (count == 0UL)) { + return RES_PARERR; + } + if ((Stat & STA_NOINIT) == STA_NOINIT) { + return RES_NOTRDY; + } + if ((Stat & STA_PROTECT) == STA_PROTECT) { + return RES_WRPRT; + } + if (host_driver_ifdevconnected(&usb_app_instance) != 0UL) { + do { + status = usb_host_msc_Write10(&usb_app_instance, (BYTE *)buff, sector, 512UL * (uint32_t)count); + usb_host_msc_botxferprocess(&usb_app_instance, &usb_app_host); + + if (host_driver_ifdevconnected(&usb_app_instance) == 0UL) { + return RES_ERROR; + } + } while (status == USB_HOST_MSC_BUSY); + } + + if (status == USB_HOST_MSC_OK) { + return RES_OK; + } + return RES_ERROR; +} +#endif /* _READONLY == 0 */ + +//#if _USE_IOCTL != 0 +/** + * @brief Miscellaneous Functions + * @param [in] drv Physical drive number (0) + * @param [in] ctrl Control code + * @param [in] buff Buffer to send/receive control data + ** + * @retval DSTATUS + */ +DRESULT disk_ioctl(BYTE pdrv, BYTE cmd, void *buff) +{ + DRESULT res; + + if (pdrv != 0U) { + return RES_PARERR; + } + + res = RES_ERROR; + + if ((Stat & STA_NOINIT) == STA_NOINIT) { + return RES_NOTRDY; + } + + switch (cmd) { + case CTRL_SYNC : /* Make sure that no pending write process */ + res = RES_OK; + break; + case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ + *(DWORD *)buff = (DWORD) USB_HOST_MSC_Param.MSC_Capacity; + res = RES_OK; + break; + case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ + *(WORD *)buff = 512U; + res = RES_OK; + break; + case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ + *(DWORD *)buff = 512UL; + break; + default: + res = RES_PARERR; + break; + } + return res; +} +//#endif +#endif /* _USE_IOCTL != 0 */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.c new file mode 100644 index 0000000000..f37a8871e3 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.c @@ -0,0 +1,528 @@ +/** + ******************************************************************************* + * @file usb_host_msc_scsi.c + * @brief The SCSI commands。 + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_msc_class.h" +#include "usb_host_msc_scsi.h" +#include "usb_host_msc_bot.h" +#include "usb_host_ctrltrans.h" +#include "usb_host_def.h" +#include "usb_host_driver.h" +#include + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_MSC + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +MSC_PARAMETER USB_HOST_MSC_Param; + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +#ifdef USB_INTERNAL_DMA_ENABLED +#if defined ( __ICCARM__ ) +#pragma data_alignment=4 +#endif +#endif +__USB_ALIGN_BEGIN static uint8_t USB_HOST_DataInBuf[512]; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief Issues 'Test Unit Ready' command to the device. Once the response + * received, it updates the status to upper layer, the length of the + * command are 31bytes. + * @param [in] pdev device instance + * @retval status define by USB_HOST_MSC_STATUS + */ +USB_HOST_MSC_STATUS usb_host_msc_TestUnitReady(usb_core_instance *pdev) +{ + uint8_t index; + USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + switch (USBH_MSC_BOTXferParam.CmdStateMachine) { + case USB_HOST_MSC_CMD_SEND: + USBH_MSC_CBWData.field.CBWTransferLength = 0UL; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_OUT; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH_TEST_UNIT_READY; + USBH_MSC_BOTXferParam.pRxTxBuff = USBH_MSC_CSWData.CSWArray; + USBH_MSC_BOTXferParam.DataLength = HOST_MSC_CSW_MAX_LENGTH; + USBH_MSC_BOTXferParam.MSCStateCurrent = HOST_MSC_TEST_UNIT_READY; + for (index = 0U; index < CBW_CB_LENGTH; index++) { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00U; + } + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_TEST_UNIT_READY; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW; + /* Start the transfer, then let the state machine magage the other transactions */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT; + + status = USB_HOST_MSC_BUSY; + break; + + case USB_HOST_MSC_CMD_WAIT: + switch (USBH_MSC_BOTXferParam.BOTXferStatus) { + case USB_HOST_MSC_OK: + /* Commands successfully sent and Response Received */ + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_OK; + break; + case USB_HOST_MSC_FAIL: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_FAIL; + break; + case USB_HOST_MSC_PHASE_ERROR: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_PHASE_ERROR; + break; + default: + break; + } + break; + default: + break; + } + } + return status; +} + +/** + * @brief Issue the 'Read capacity10' command to the device. Once the response + * received, it updates the status to upper layer + * @param [in] pdev device instance + * @retval status define by USB_HOST_MSC_STATUS + */ +USB_HOST_MSC_STATUS usb_host_msc_ReadCapacity10(usb_core_instance *pdev) +{ + uint8_t index; + USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + switch (USBH_MSC_BOTXferParam.CmdStateMachine) { + case USB_HOST_MSC_CMD_SEND: + /*Prepare the CBW and relevent field*/ + USBH_MSC_CBWData.field.CBWTransferLength = XFER_LEN_READ_CAPACITY10; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + USBH_MSC_BOTXferParam.pRxTxBuff = USB_HOST_DataInBuf; + USBH_MSC_BOTXferParam.MSCStateCurrent = HOST_MSC_READ_CAPACITY10; + for (index = 0U; index < CBW_CB_LENGTH; index++) { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00U; + } + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_READ_CAPACITY10; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW; + /* Start the transfer, then let the state machine manage the other + transactions */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT; + status = USB_HOST_MSC_BUSY; + break; + + case USB_HOST_MSC_CMD_WAIT: + switch (USBH_MSC_BOTXferParam.BOTXferStatus) { + case USB_HOST_MSC_OK: + /*assign the capacity*/ + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Capacity)[3]) = USB_HOST_DataInBuf[0]; + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Capacity)[2]) = USB_HOST_DataInBuf[1]; + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Capacity)[1]) = USB_HOST_DataInBuf[2]; + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Capacity)[0]) = USB_HOST_DataInBuf[3]; + /*assign the page length*/ + (((uint8_t *)&USB_HOST_MSC_Param.MSC_PageLength)[1]) = USB_HOST_DataInBuf[6]; + (((uint8_t *)&USB_HOST_MSC_Param.MSC_PageLength)[0]) = USB_HOST_DataInBuf[7]; + /* Commands successfully sent and Response Received */ + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_OK; + break; + case USB_HOST_MSC_FAIL: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_FAIL; + break; + case USB_HOST_MSC_PHASE_ERROR: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_PHASE_ERROR; + break; + default: + break; + } + break; + + default: + break; + } + } + return status; +} + +/** + * @brief Issue the 'Mode Sense6' Command to the device. This function is used + * for reading the WriteProtect Status of the MSC device. + * @param [in] pdev device instance + * @retval status by USB_HOST_MSC_STATUS + */ +USB_HOST_MSC_STATUS usb_host_msc_ModeSense6(usb_core_instance *pdev) +{ + uint8_t index; + USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + switch (USBH_MSC_BOTXferParam.CmdStateMachine) { + case USB_HOST_MSC_CMD_SEND: + /*Prepare the CBW and relevent field*/ + USBH_MSC_CBWData.field.CBWTransferLength = XFER_LEN_MODE_SENSE6; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + + USBH_MSC_BOTXferParam.pRxTxBuff = USB_HOST_DataInBuf; + USBH_MSC_BOTXferParam.MSCStateCurrent = HOST_MSC_MODE_SENSE6; + + for (index = 0U; index < CBW_CB_LENGTH; index++) { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00U; + } + + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_MODE_SENSE6; + USBH_MSC_CBWData.field.CBWCB[2] = MODE_SENSE_PAGE_CONTROL_FIELD | \ + MODE_SENSE_PAGE_CODE; + + USBH_MSC_CBWData.field.CBWCB[4] = XFER_LEN_MODE_SENSE6; + + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW; + + /* Start the transfer, then let the state machine manage the other + transactions */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT; + + status = USB_HOST_MSC_BUSY; + break; + + case USB_HOST_MSC_CMD_WAIT: + switch (USBH_MSC_BOTXferParam.BOTXferStatus) { + case USB_HOST_MSC_OK: + /* Assign the Write Protect status */ + /* If WriteProtect = 0, Writing is allowed + If WriteProtect != 0, Disk is Write Protected */ + if (0U != (USB_HOST_DataInBuf[2] & MASK_MODE_SENSE_WRITE_PROTECT)) { + USB_HOST_MSC_Param.MSC_WriteProtect = DISK_WRITE_PROTECTED; + } else { + USB_HOST_MSC_Param.MSC_WriteProtect = 0U; + } + + /* Commands successfully sent and Response Received */ + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_OK; + break; + case USB_HOST_MSC_FAIL: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_FAIL; + break; + case USB_HOST_MSC_PHASE_ERROR: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_PHASE_ERROR; + break; + default: + break; + } + break; + + default: + break; + } + } + return status; +} + +/** + * @brief usb_host_msc_RequestSense + * Issues the Request Sense command to the device. Once the response + * received, it updates the status to upper layer + * @param [in] pdev device instance + * @retval status defined by USB_HOST_MSC_STATUS + */ +USB_HOST_MSC_STATUS usb_host_msc_RequestSense(usb_core_instance *pdev) +{ + USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY; + uint8_t index; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + switch (USBH_MSC_BOTXferParam.CmdStateMachine) { + case USB_HOST_MSC_CMD_SEND: + /*Prepare the CBW and relevent field*/ + USBH_MSC_CBWData.field.CBWTransferLength = \ + ALLOCATION_LENGTH_REQUEST_SENSE; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + + USBH_MSC_BOTXferParam.pRxTxBuff = USB_HOST_DataInBuf; + USBH_MSC_BOTXferParam.MSCStateBkp = USBH_MSC_BOTXferParam.MSCStateCurrent; + USBH_MSC_BOTXferParam.MSCStateCurrent = HOST_MSC_REQUEST_SENSE; + + for (index = 0U; index < CBW_CB_LENGTH; index++) { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00U; + } + + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_REQUEST_SENSE; + USBH_MSC_CBWData.field.CBWCB[1] = DESC_REQUEST_SENSE; + USBH_MSC_CBWData.field.CBWCB[4] = ALLOCATION_LENGTH_REQUEST_SENSE; + + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW; + /* Start the transfer, then let the state machine magage + the other transactions */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT; + status = USB_HOST_MSC_BUSY; + break; + + case USB_HOST_MSC_CMD_WAIT: + switch (USBH_MSC_BOTXferParam.BOTXferStatus) { + case USB_HOST_MSC_OK: + /* Get Sense data*/ + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Sense)[3]) = USB_HOST_DataInBuf[0]; + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Sense)[2]) = USB_HOST_DataInBuf[1]; + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Sense)[1]) = USB_HOST_DataInBuf[2]; + (((uint8_t *)&USB_HOST_MSC_Param.MSC_Sense)[0]) = USB_HOST_DataInBuf[3]; + + /* Commands successfully sent and Response Received */ + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_OK; + break; + case USB_HOST_MSC_FAIL: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_FAIL; + break; + case USB_HOST_MSC_PHASE_ERROR: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_PHASE_ERROR; + break; + default: + break; + } + break; + + default: + break; + } + } + return status; +} + +/** + * @brief issue the 'Write10 ' command to the device. Once the response received, + * it updates the status to upper layer + * @param [in] pdev device instance + * @param [in] dataBuffer data buffer contains the data to write + * @param [in] address address to which the data will be written + * @param [in] nbOfbytes NbOfbytes to be written + * @retval status define by USB_HOST_MSC_STATUS + */ +USB_HOST_MSC_STATUS usb_host_msc_Write10(usb_core_instance *pdev, + uint8_t *dataBuffer, + uint32_t address, + uint32_t nbOfbytes) +{ + uint8_t index; + USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY; + uint16_t nbOfPages; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + switch (USBH_MSC_BOTXferParam.CmdStateMachine) { + case USB_HOST_MSC_CMD_SEND: + USBH_MSC_CBWData.field.CBWTransferLength = nbOfbytes; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_OUT; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + USBH_MSC_BOTXferParam.pRxTxBuff = dataBuffer; + + for (index = 0U; index < CBW_CB_LENGTH; index++) { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00U; + } + + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_WRITE10; + /*logical block address*/ + USBH_MSC_CBWData.field.CBWCB[2] = (((uint8_t *)&address)[3]) ; + USBH_MSC_CBWData.field.CBWCB[3] = (((uint8_t *)&address)[2]); + USBH_MSC_CBWData.field.CBWCB[4] = (((uint8_t *)&address)[1]); + USBH_MSC_CBWData.field.CBWCB[5] = (((uint8_t *)&address)[0]); + + /*HOST_MSC_PAGE_LENGTH = 512*/ + nbOfPages = (uint16_t)(nbOfbytes / HOST_MSC_PAGE_LENGTH); + + /*Tranfer length */ + USBH_MSC_CBWData.field.CBWCB[7] = (((uint8_t *)&nbOfPages)[1]) ; + USBH_MSC_CBWData.field.CBWCB[8] = (((uint8_t *)&nbOfPages)[0]) ; + + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW; + /* Start the transfer, then let the state machine + magage the other transactions */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT; + + status = USB_HOST_MSC_BUSY; + break; + + case USB_HOST_MSC_CMD_WAIT: + switch (USBH_MSC_BOTXferParam.BOTXferStatus) { + case USB_HOST_MSC_OK: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_OK; + break; + case USB_HOST_MSC_FAIL: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + break; + case USB_HOST_MSC_PHASE_ERROR: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_PHASE_ERROR; + break; + default: + break; + } + break; + + default: + break; + } + } + return status; +} + +/** + * @brief issue the read command to the device. Once the response received, + * it updates the status to upper layer + * @param [in] pdev device instance + * @param [in] dataBuffer data buffer will contain the data to be read + * @param [in] address Address from which the data will be read + * @param [in] nbOfbytes number of bytes to be read + * @retval status defined by USB_HOST_MSC_STATUS + */ +USB_HOST_MSC_STATUS usb_host_msc_Read10(usb_core_instance *pdev, + uint8_t *dataBuffer, + uint32_t address, + uint32_t nbOfbytes) +{ + uint8_t index; + static USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY; + uint16_t nbOfPages; + status = USB_HOST_MSC_BUSY; + + if (host_driver_ifdevconnected(pdev) != 0UL) { + switch (USBH_MSC_BOTXferParam.CmdStateMachine) { + case USB_HOST_MSC_CMD_SEND: + /*Prepare the CBW and relevent field*/ + USBH_MSC_CBWData.field.CBWTransferLength = nbOfbytes; + USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; + USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; + + USBH_MSC_BOTXferParam.pRxTxBuff = dataBuffer; + + for (index = 0U; index < CBW_CB_LENGTH; index++) { + USBH_MSC_CBWData.field.CBWCB[index] = 0x00U; + } + + USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_READ10; + + /*logical block address*/ + USBH_MSC_CBWData.field.CBWCB[2] = (((uint8_t *)&address)[3]); + USBH_MSC_CBWData.field.CBWCB[3] = (((uint8_t *)&address)[2]); + USBH_MSC_CBWData.field.CBWCB[4] = (((uint8_t *)&address)[1]); + USBH_MSC_CBWData.field.CBWCB[5] = (((uint8_t *)&address)[0]); + /*HOST_MSC_PAGE_LENGTH = 512*/ + nbOfPages = (uint16_t)(nbOfbytes / HOST_MSC_PAGE_LENGTH); + /*Tranfer length */ + USBH_MSC_CBWData.field.CBWCB[7] = (((uint8_t *)&nbOfPages)[1]) ; + USBH_MSC_CBWData.field.CBWCB[8] = (((uint8_t *)&nbOfPages)[0]) ; + USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW; + /* Start the transfer, then let the state machine + magage the other transactions */ + USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS; + USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY; + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT; + status = USB_HOST_MSC_BUSY; + break; + + case USB_HOST_MSC_CMD_WAIT: + switch (USBH_MSC_BOTXferParam.BOTXferStatus) { + case USB_HOST_MSC_OK: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_OK; + break; + case USB_HOST_MSC_FAIL: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + break; + case USB_HOST_MSC_PHASE_ERROR: + USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND; + status = USB_HOST_MSC_PHASE_ERROR; + break; + default: + break; + } + break; + + default: + break; + } + } + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.h new file mode 100644 index 0000000000..3f05b985cf --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.h @@ -0,0 +1,136 @@ +/** + ******************************************************************************* + * @file usb_host_msc_scsi.h + * @brief Head file for usb_host_msc_scsi.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_MSC_SCSI_H__ +#define __USB_HOST_MSC_SCSI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_stdreq.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CLASS + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_MSC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/* USBH_MSC_SCSI_Exported_Types */ +typedef enum { + USB_HOST_MSC_OK = 0U, + USB_HOST_MSC_FAIL, + USB_HOST_MSC_PHASE_ERROR, + USB_HOST_MSC_BUSY +} USB_HOST_MSC_STATUS; + +typedef struct { + uint32_t MSC_Capacity; + uint32_t MSC_Sense; + uint16_t MSC_PageLength; + uint8_t MSC_BulkOutEP; + uint8_t MSC_BulkInEP; + uint8_t MSC_WriteProtect; +} MSC_PARAMETER; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define USB_HOST_MSC_CMD_SEND (1) +#define USB_HOST_MSC_CMD_WAIT (2) + +#define OPCODE_TEST_UNIT_READY (0x00U) +#define OPCODE_READ_CAPACITY10 (0x25U) +#define OPCODE_MODE_SENSE6 (0x1AU) +#define OPCODE_READ10 (0x28U) +#define OPCODE_WRITE10 (0x2AU) +#define OPCODE_REQUEST_SENSE (0x03U) + +#define DESC_REQUEST_SENSE (0x00U) +#define ALLOCATION_LENGTH_REQUEST_SENSE (63U) +#define XFER_LEN_READ_CAPACITY10 (8U) +#define XFER_LEN_MODE_SENSE6 (63U) + +#define MASK_MODE_SENSE_WRITE_PROTECT (0x80U) +#define MODE_SENSE_PAGE_CONTROL_FIELD (0x00U) +#define MODE_SENSE_PAGE_CODE (0x3FU) +#define DISK_WRITE_PROTECTED (0x01U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +extern MSC_PARAMETER USB_HOST_MSC_Param; + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern USB_HOST_MSC_STATUS usb_host_msc_TestUnitReady(usb_core_instance *pdev); +extern USB_HOST_MSC_STATUS usb_host_msc_ReadCapacity10(usb_core_instance *pdev); +extern USB_HOST_MSC_STATUS usb_host_msc_ModeSense6(usb_core_instance *pdev); +extern USB_HOST_MSC_STATUS usb_host_msc_RequestSense(usb_core_instance *pdev); +extern USB_HOST_MSC_STATUS usb_host_msc_Write10(usb_core_instance *pdev, + uint8_t *dataBuffer, + uint32_t address, + uint32_t nbOfbytes); +extern USB_HOST_MSC_STATUS usb_host_msc_Read10(usb_core_instance *pdev, + uint8_t *dataBuffer, + uint32_t address, + uint32_t nbOfbytes); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_MSC_SCSI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.c new file mode 100644 index 0000000000..3c4406566c --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.c @@ -0,0 +1,202 @@ +/** + ******************************************************************************* + * @file usb_host_cfgch.c + * @brief Functions for opening and closing host channels + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_cfgch.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE LL USB Host Core + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +uint16_t usb_host_getfreech(usb_core_instance *pdev); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief configure and open a pipe + * @param [in] pdev device instance + * @param [in] hc_num host channel index + * @param [in] dev_address USB Device address allocated to attached device + * @param [in] speed core speed + * @param [in] ep_type communication type of the EP + * @param [in] mps max size of the packet + * @retval None + */ +void usb_host_chopen(usb_core_instance *pdev, + uint8_t hc_num, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps) +{ + pdev->host.hc[hc_num].ep_idx = (uint8_t) pdev->host.channel[hc_num] & 0x7Fu; + pdev->host.hc[hc_num].is_epin = (uint8_t)((pdev->host.channel[hc_num] & 0x80U) == 0x80U); + pdev->host.hc[hc_num].dev_addr = dev_address; + pdev->host.hc[hc_num].ep_type = ep_type; + pdev->host.hc[hc_num].max_packet = mps; + pdev->host.hc[hc_num].ch_speed = speed; + pdev->host.hc[hc_num].in_toggle = 0U; + pdev->host.hc[hc_num].out_toggle = 0U; + + (void)usb_inithch(&pdev->regs, hc_num, &pdev->host.hc[hc_num], pdev->basic_cfgs.dmaen); +} + +/** + * @brief change a pipe on host + * @param [in] pdev device instance + * @param [in] hc_num host channel index + * @param [in] dev_address USB Device address allocated to attached device + * @param [in] speed core speed + * @param [in] ep_type communication type of EP + * @param [in] mps max size of packet + * @retval None + */ +void usb_host_mdfch(usb_core_instance *pdev, + uint8_t hc_num, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps) +{ + (void)(ep_type); + if (dev_address != 0U) { + pdev->host.hc[hc_num].dev_addr = dev_address; + } + if ((pdev->host.hc[hc_num].max_packet != mps) && (mps != 0U)) { + pdev->host.hc[hc_num].max_packet = mps; + } + if ((pdev->host.hc[hc_num].ch_speed != speed) && (speed != 0U)) { + pdev->host.hc[hc_num].ch_speed = speed; + } + + (void)usb_inithch(&pdev->regs, hc_num, &pdev->host.hc[hc_num], pdev->basic_cfgs.dmaen); +} + +/** + * @brief distribute a new channel for the pipe + * @param [in] pdev device instance + * @param [in] ep_addr EP index the channel distributed for + * @retval hc_num host channel index + */ +uint8_t usb_host_distrch(usb_core_instance *pdev, uint8_t ep_addr) +{ + __IO uint16_t hc_num; + + hc_num = usb_host_getfreech(pdev); + if (hc_num != HC_ERROR) { + pdev->host.channel[hc_num & (USB_MAX_TX_FIFOS - 1U)] = HC_USED | ep_addr; + } + return (uint8_t)hc_num; +} + +/** + * @brief free the USB host channel assigned by idx + * @param [in] pdev device instance + * @param [in] idx Channel number to be freed + * @retval Status + */ +uint8_t usb_host_freech(usb_core_instance *pdev, uint8_t idx) +{ + if (idx < MAX_CHNUM) { + pdev->host.channel[idx & (USB_MAX_TX_FIFOS - 1U)] &= HC_USED_MASK; + } + return (uint8_t)HSTATUS_OK; +} + +/** + * @brief free all the USB host channels + * @param [in] pdev device instance + * @retval None + */ +void usb_host_dedistrallch(usb_core_instance *pdev) +{ + uint8_t idx; + + for (idx = 2U; idx < MAX_CHNUM ; idx ++) { + pdev->host.channel[idx & (USB_MAX_TX_FIFOS - 1U)] = 0U; + } +} + +/** + * @brief Get a free channel number so that can be distributed to a device endpoint + * @param [in] pdev device instance + * @retval idx the free channel index + */ +uint16_t usb_host_getfreech(usb_core_instance *pdev) +{ + uint8_t tmp_idx; + uint16_t u16Ret = HC_ERROR; + + for (tmp_idx = 0U ; tmp_idx < MAX_CHNUM ; tmp_idx++) { + if ((pdev->host.channel[tmp_idx & (USB_MAX_TX_FIFOS - 1U)] & HC_USED) == 0U) { + u16Ret = HC_OK; + break; + } + } + + if (u16Ret == HC_OK) { + u16Ret = tmp_idx; + } else { + u16Ret = HC_ERROR; + } + + return u16Ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.h new file mode 100644 index 0000000000..0f641ef520 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.h @@ -0,0 +1,103 @@ +/** + ******************************************************************************* + * @file usb_host_cfgch.h + * @brief header file for the usb_host_cfgch.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_CFGCH_H__ +#define __USB_HOST_CFGCH_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/* USBH_HCS_Exported_Defines */ +#define MAX_CHNUM (12U) + +#define HC_OK (0x0000U) +#define HC_USED (0x8000U) +#define HC_ERROR (0xFFFFU) +#define HC_USED_MASK (0x7FFFU) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern uint8_t usb_host_distrch(usb_core_instance *pdev, uint8_t ep_addr); + +extern uint8_t usb_host_freech(usb_core_instance *pdev, uint8_t idx); + +extern void usb_host_dedistrallch(usb_core_instance *pdev); + +extern void usb_host_chopen(usb_core_instance *pdev, + uint8_t hc_num, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps); + +extern void usb_host_mdfch(usb_core_instance *pdev, + uint8_t hc_num, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_CFGCH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.c new file mode 100644 index 0000000000..5eac906f57 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.c @@ -0,0 +1,537 @@ +/** + ******************************************************************************* + * @file usb_host_core.c + * @brief The core state machine process the enumeration and the control transfer process + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "usb_host_core.h" +#include "usb_host_cfgch.h" +#include "usb_host_ctrltrans.h" +#include "usb_host_driver.h" +#include "usb_host_stdreq.h" +#include "usb_host_int.h" +#include "usb_bsp.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +HOST_STATUS usb_host_ctrlprocess(usb_core_instance *pdev, USBH_HOST *phost); +HOST_STATUS usb_host_enumprocess(usb_core_instance *pdev, USBH_HOST *phost); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static uint8_t Local_Buffer[ENUM_LOCAL_BUF]; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief initialization for the host application + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] class_cbk the call back function for the class application + * @param [in] user_cbk the call back function for user + * @retval None + */ +void usb_host_init(usb_core_instance *pdev, + USBH_HOST *phost, + usb_host_class_callback_func *class_cbk, + usb_host_user_callback_func *user_cbk) +{ + usb_bsp_init(pdev); + usb_host_deinit(pdev, phost); + phost->class_callbk = class_cbk; + phost->user_callbk = user_cbk; + host_driver_init(pdev); + phost->user_callbk->huser_init(); + usb_bsp_nvicconfig(); +} + +/** + * @brief deinitialize the host application + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval None + */ +void usb_host_deinit(usb_core_instance *pdev, USBH_HOST *phost) +{ + phost->host_state = HOST_IDLE; + phost->host_state_backup = HOST_IDLE; + phost->enum_state = ENUM_IDLE; + phost->req_state = REQ_CMD_TX; + + phost->ctrlparam.ctrl_state = CTRL_SETUP; + phost->ctrlparam.ctrlmaxsize = USB_MAX_EP0_SIZE; + + phost->device_prop.devaddr = DEV_DEFAULT_ADDRESS; + phost->device_prop.devspeed = PRTSPD_FULL_SPEED; + + (void)usb_host_freech(pdev, phost->ctrlparam.hc_num_in); + (void)usb_host_freech(pdev, phost->ctrlparam.hc_num_out); +} + +/** + * @brief This is the main process function for the host core, it will process + * the main machine, such as connect,disconnect, emunation etc. + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval None + */ +void usb_host_mainprocess(usb_core_instance *pdev, USBH_HOST *phost) +{ + __IO HOST_STATUS tmp_status; + tmp_status = HSTATUS_FAIL; + HOST_HANDLE_STATE tmp_host_state; + + if ((host_driver_ifdevconnected(pdev) == 0UL) && (phost->host_state != HOST_IDLE)) { + if (phost->host_state != HOST_DEV_DISCONNECTED) { + phost->host_state = HOST_DEV_DISCONNECTED; + } + } + + if ((host_driver_ifdevconnected(pdev) == 0UL) && (phost->host_state == HOST_IDLE) + && (host_driver_getvbusdrivestate(pdev) == 0UL)) { + phost->host_state = HOST_DEV_DISCONNECTED; + } + + tmp_host_state = phost->host_state; + if (tmp_host_state == HOST_IDLE) { + if (0U != host_driver_ifdevconnected(pdev)) { + phost->host_state = HOST_DEV_CONNECTED; + usb_mdelay(50UL); + } + } else if (tmp_host_state == HOST_DEV_CONNECTED) { +#ifdef MSC_HID_COMPOSITE + if (host_driver_getcurrentspd(pdev) == 2) { + host_driver_init(pdev); + } +#endif /* MSC_HID_COMPOSITE */ + phost->user_callbk->huser_devattached(); + phost->ctrlparam.hc_num_out = usb_host_distrch(pdev, 0x00U); + phost->ctrlparam.hc_num_in = usb_host_distrch(pdev, 0x80U); + host_driver_portrst(pdev); + phost->user_callbk->huser_devreset(); + phost->device_prop.devspeed = (uint8_t)host_driver_getcurrentspd(pdev); + phost->host_state = HOST_ENUM; + phost->user_callbk->huser_devspddetected(phost->device_prop.devspeed); + usb_host_chopen(pdev, + phost->ctrlparam.hc_num_in, + phost->device_prop.devaddr, + phost->device_prop.devspeed, + EP_TYPE_CTRL, + (uint16_t)phost->ctrlparam.ctrlmaxsize); + usb_host_chopen(pdev, + phost->ctrlparam.hc_num_out, + phost->device_prop.devaddr, + phost->device_prop.devspeed, + EP_TYPE_CTRL, + (uint16_t)phost->ctrlparam.ctrlmaxsize); + } else if (tmp_host_state == HOST_ENUM) { + if (usb_host_enumprocess(pdev, phost) == HSTATUS_OK) { + phost->user_callbk->huser_enumcompl(); + phost->host_state = HOST_USER_INPUT; + } + } else if (tmp_host_state == HOST_USER_INPUT) { + if ((phost->class_callbk->host_class_init(pdev, phost)) == HSTATUS_OK) { + phost->host_state = HOST_CLASS_REQ; + } + } else if (tmp_host_state == HOST_CLASS_REQ) { + tmp_status = phost->class_callbk->host_class_request(pdev, phost); + if (tmp_status == HSTATUS_OK) { + phost->host_state = HOST_CLASS_PROCESS; + } else { + usb_host_errorprocess(phost, tmp_status); + } + } else if (tmp_host_state == HOST_CLASS_PROCESS) { + tmp_status = phost->class_callbk->host_class_process(pdev, phost); + usb_host_errorprocess(phost, tmp_status); + } else if (tmp_host_state == HOST_CTRL_TRANSMIT) { + (void)usb_host_ctrlprocess(pdev, phost); + } else if (tmp_host_state == HOST_ERROR_STATE) { + usb_host_deinit(pdev, phost); + phost->user_callbk->huser_deinit(); + phost->class_callbk->host_class_deinit(pdev); + } else if (tmp_host_state == HOST_DEV_DISCONNECTED) { + phost->user_callbk->huser_devdisconn(); + usb_host_deinit(pdev, phost); + phost->user_callbk->huser_deinit(); + phost->class_callbk->host_class_deinit(pdev); + usb_host_dedistrallch(pdev); + phost->host_state = HOST_IDLE; + + host_driver_init(pdev); + } else { + ; + } +} + +/** + * @brief process the status when related error status happens. + * @param [in] phost host state set + * @param [in] errType host status + * @retval None + */ +void usb_host_errorprocess(USBH_HOST *phost, HOST_STATUS errType) +{ + switch (errType) { + case HSTATUS_APP_DEINIT: + phost->host_state = HOST_ERROR_STATE; + phost->user_callbk->huser_init(); + break; + case HSTATUS_SPEED_UNKNOWN: + case HSTATUS_UNRECOVERED_ERROR: + phost->user_callbk->huser_unrecoverederror(); + phost->host_state = HOST_ERROR_STATE; + break; + default: + break; + } +} + +/** + * @brief this function process all the emunation steps. + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status + */ +HOST_STATUS usb_host_enumprocess(usb_core_instance *pdev, USBH_HOST *phost) +{ + HOST_STATUS tmp_status; + + ENUM_HANDLE_STATE tmp_enum_state; + tmp_status = HSTATUS_BUSY; + tmp_enum_state = phost->enum_state; + if (tmp_enum_state == ENUM_IDLE) { + if (usb_host_getdevdesc(pdev, phost, 8U) == HSTATUS_OK) { + phost->ctrlparam.ctrlmaxsize = phost->device_prop.devdesc.bMaxPacketSize0; + host_driver_portrst(pdev); + phost->enum_state = ENUM_GET_FULL_DEVDESC; + usb_host_mdfch(pdev, + phost->ctrlparam.hc_num_out, + 0U, + 0U, + 0U, + (uint16_t)phost->ctrlparam.ctrlmaxsize); + usb_host_mdfch(pdev, + phost->ctrlparam.hc_num_in, + 0U, + 0U, + 0U, + (uint16_t)phost->ctrlparam.ctrlmaxsize); + } + } + if (tmp_enum_state == ENUM_GET_FULL_DEVDESC) { + if (usb_host_getdevdesc(pdev, phost, USB_DEVICE_DESC_SIZE) == HSTATUS_OK) { + phost->user_callbk->huser_devdescavailable(&phost->device_prop.devdesc); + phost->enum_state = ENUM_SET_DEVADDR; + } + } + if (tmp_enum_state == ENUM_SET_DEVADDR) { + if (usb_host_setdevaddr(pdev, phost, DEV_ASSIGNED_ADDRESS) == HSTATUS_OK) { + usb_mdelay(2UL); + phost->device_prop.devaddr = DEV_ASSIGNED_ADDRESS; + phost->user_callbk->huser_devaddrdistributed(); + phost->enum_state = ENUM_GET_CFGDESC; + usb_host_mdfch(pdev, + phost->ctrlparam.hc_num_in, + phost->device_prop.devaddr, + 0U, + 0U, + 0U); + + usb_host_mdfch(pdev, + phost->ctrlparam.hc_num_out, + phost->device_prop.devaddr, + 0U, + 0U, + 0U); + } + } + if (tmp_enum_state == ENUM_GET_CFGDESC) { + if (usb_host_getcfgdesc(pdev, phost, USB_CONFIGURATION_DESC_SIZE) == HSTATUS_OK) { + phost->enum_state = ENUM_GET_FULL_CFGDESC; + } + } + if (tmp_enum_state == ENUM_GET_FULL_CFGDESC) { + if (usb_host_getcfgdesc(pdev, phost, phost->device_prop.devcfgdesc.wTotalLength) == HSTATUS_OK) { + phost->user_callbk->huser_cfgdescavailable(&phost->device_prop.devcfgdesc, + phost->device_prop.devitfdesc, + phost->device_prop.devepdesc[0]); + phost->enum_state = ENUM_GET_MFCSTRINGDESC; + } + } + if (tmp_enum_state == ENUM_GET_MFCSTRINGDESC) { + if (phost->device_prop.devdesc.iManufacturer != (uint8_t)0) { + if (usb_host_getstringdesc(pdev, + phost, + phost->device_prop.devdesc.iManufacturer, + Local_Buffer, + 0xffu) == HSTATUS_OK) { + phost->user_callbk->huser_mfcstring(Local_Buffer); + phost->enum_state = ENUM_GET_PRODUCT_STRINGDESC; + } + } else { + phost->user_callbk->huser_mfcstring("N/A"); + phost->enum_state = ENUM_GET_PRODUCT_STRINGDESC; + } + } + if (tmp_enum_state == ENUM_GET_PRODUCT_STRINGDESC) { + if (phost->device_prop.devdesc.iProduct != (uint8_t)0) { + if (usb_host_getstringdesc(pdev, + phost, + phost->device_prop.devdesc.iProduct, + Local_Buffer, + 0xffu) == HSTATUS_OK) { + phost->user_callbk->huser_productstring(Local_Buffer); + phost->enum_state = ENUM_GET_SERIALNUM_STRINGDESC; + } + } else { + phost->user_callbk->huser_productstring("N/A"); + phost->enum_state = ENUM_GET_SERIALNUM_STRINGDESC; + } + } + if (tmp_enum_state == ENUM_GET_SERIALNUM_STRINGDESC) { + if (phost->device_prop.devdesc.iSerialNumber != (uint8_t)0) { + if (usb_host_getstringdesc(pdev, + phost, + phost->device_prop.devdesc.iSerialNumber, + Local_Buffer, + 0xffu) == HSTATUS_OK) { + phost->user_callbk->huser_serialnum(Local_Buffer); + phost->enum_state = ENUM_SET_CFG; + } + } else { + phost->user_callbk->huser_serialnum("N/A"); + phost->enum_state = ENUM_SET_CFG; + } + } + if (tmp_enum_state == ENUM_SET_CFG) { + if (usb_host_setconfig(pdev, phost, + (uint16_t)phost->device_prop.devcfgdesc.bConfigurationValue) == HSTATUS_OK) { + phost->enum_state = ENUM_DEV_CFG_OVER; + } + } + if (tmp_enum_state == ENUM_DEV_CFG_OVER) { + tmp_status = HSTATUS_OK; + } else { + ; + } + return tmp_status; +} + + +/** + * @brief process the state machine of control transfer + * @param [in] pdev device instance + * @param [in] phost host state set + * @retval status + */ +HOST_STATUS usb_host_ctrlprocess(usb_core_instance *pdev, USBH_HOST *phost) +{ + uint8_t direction; + CTRL_HANDLE_STATE tmp_ctrl_state; + static uint16_t timeout = 0; + HOST_STATUS status = HSTATUS_OK; + HOST_CH_XFER_STATE URB_Status; + + phost->ctrlparam.ctrl_status = CTRL_START; + tmp_ctrl_state = phost->ctrlparam.ctrl_state; + + if (tmp_ctrl_state == CTRL_SETUP) { + /* transmit a setup packet to the device */ + usb_host_sendctrlsetup(pdev, phost->ctrlparam.setup.d8, phost->ctrlparam.hc_num_out); + phost->ctrlparam.ctrl_state = CTRL_SETUP_WAIT; + timeout = DATA_STAGE_TIMEOUT * 6U; + phost->ctrlparam.sof_num = (uint16_t)host_driver_getcurrentfrm(pdev); + } else if (tmp_ctrl_state == CTRL_SETUP_WAIT) { + URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_out); + /* case SETUP packet sent successfully */ + if (URB_Status == HOST_CH_XFER_DONE) { + /* parse the direction of the request from the setup just sent */ + direction = (phost->ctrlparam.setup.b.bmRequestType & USB_REQ_DIR_MASK); + /* judge if there is a data stage, if wLength is not zero, there may be a in or out + data stage */ + if (phost->ctrlparam.setup.b.wLength.w != 0U) { + timeout = DATA_STAGE_TIMEOUT; + if (direction == USB_D2H) { + /* Data Direction is IN, device should send data in */ + phost->ctrlparam.ctrl_state = CTRL_DATA_IN; + } else { + /* Data Direction is OUT, host will send data out for device */ + phost->ctrlparam.ctrl_state = CTRL_DATA_OUT; + } + } + /* No DATA stage */ + else { + timeout = NODATA_STAGE_TIMEOUT; + /* If there is No Data Transfer Stage */ + if (direction == USB_D2H) { + /* Data Direction is IN */ + phost->ctrlparam.ctrl_state = CTRL_STATUS_OUT; + } else { + /* Data Direction is OUT */ + phost->ctrlparam.ctrl_state = CTRL_STATUS_IN; + } + } + /* Set the delay timer to enable timeout for data stage completion */ + phost->ctrlparam.sof_num = (uint16_t)host_driver_getcurrentfrm(pdev); + } else if (URB_Status == HOST_CH_XFER_ERROR) { + phost->ctrlparam.ctrl_state = CTRL_ERROR; + phost->ctrlparam.ctrl_status = CTRL_XACTERR; + } else if ((host_driver_getcurrentfrm(pdev) - phost->ctrlparam.sof_num) > timeout) { +#if (LL_PRINT_ENABLE == DDL_ON) + DDL_Printf("Device not responding\r\n"); +#endif + } else { + ; + } + } else if (tmp_ctrl_state == CTRL_DATA_IN) { + /* Issue an IN token */ + usb_host_recvctrldata(pdev, phost->ctrlparam.buff, phost->ctrlparam.length, phost->ctrlparam.hc_num_in); + phost->ctrlparam.ctrl_state = CTRL_DATA_IN_WAIT; + } else if (tmp_ctrl_state == CTRL_DATA_IN_WAIT) { + URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_in); + /* check is DATA packet transfered successfully */ + if (URB_Status == HOST_CH_XFER_DONE) { + phost->ctrlparam.ctrl_state = CTRL_STATUS_OUT; + } + /* manage error cases*/ + if (URB_Status == HOST_CH_XFER_STALL) { + /* In stall case, return to previous machine state*/ + phost->host_state = phost->host_state_backup; + } else if (URB_Status == HOST_CH_XFER_ERROR) { + /* Device error */ + phost->ctrlparam.ctrl_state = CTRL_ERROR; + } else if ((host_driver_getcurrentfrm(pdev) - phost->ctrlparam.sof_num) > timeout) { + /* timeout for IN transfer */ + phost->ctrlparam.ctrl_state = CTRL_ERROR; + } else { + ; + } + } else if (tmp_ctrl_state == CTRL_DATA_OUT) { + /* Start DATA out transfer (only one DATA packet)*/ + pdev->host.hc[phost->ctrlparam.hc_num_out].out_toggle = 1; + + usb_host_sendctrldata(pdev, + phost->ctrlparam.buff, + phost->ctrlparam.length, + phost->ctrlparam.hc_num_out); + phost->ctrlparam.ctrl_state = CTRL_DATA_OUT_WAIT; + } else if (tmp_ctrl_state == CTRL_DATA_OUT_WAIT) { + URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_out); + switch (URB_Status) { + case HOST_CH_XFER_DONE: + phost->ctrlparam.ctrl_state = CTRL_STATUS_IN; + break; + case HOST_CH_XFER_STALL: + phost->host_state = phost->host_state_backup; + phost->ctrlparam.ctrl_state = CTRL_STALLED; + break; + case HOST_CH_XFER_UNREADY: + phost->ctrlparam.ctrl_state = CTRL_DATA_OUT; + break; + case HOST_CH_XFER_ERROR: + phost->ctrlparam.ctrl_state = CTRL_ERROR; + break; + default: + break; + } + } else if (tmp_ctrl_state == CTRL_STATUS_IN) { + /* receive a packet with 0 byte */ + usb_host_recvctrldata(pdev, NULL, 0U, phost->ctrlparam.hc_num_in); + phost->ctrlparam.ctrl_state = CTRL_STATUS_IN_WAIT; + } else if (tmp_ctrl_state == CTRL_STATUS_IN_WAIT) { + URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_in); + if (URB_Status == HOST_CH_XFER_DONE) { + /* Control transfers completed, Exit the State Machine */ + phost->host_state = phost->host_state_backup; + phost->ctrlparam.ctrl_state = CTRL_COMPLETE; + } else if (URB_Status == HOST_CH_XFER_ERROR) { + phost->ctrlparam.ctrl_state = CTRL_ERROR; + } else if ((host_driver_getcurrentfrm(pdev) - phost->ctrlparam.sof_num) > timeout) { + phost->ctrlparam.ctrl_state = CTRL_ERROR; + } else if (URB_Status == HOST_CH_XFER_STALL) { + /* Control transfers completed, Exit the State Machine */ + phost->host_state = phost->host_state_backup; + phost->ctrlparam.ctrl_status = CTRL_STALL; + status = HSTATUS_UNSUPPORTED; + } else { + ; + } + } else if (tmp_ctrl_state == CTRL_STATUS_OUT) { + pdev->host.hc[phost->ctrlparam.hc_num_out].out_toggle ^= 1U; + usb_host_sendctrldata(pdev, NULL, 0U, phost->ctrlparam.hc_num_out); + phost->ctrlparam.ctrl_state = CTRL_STATUS_OUT_WAIT; + } else if (tmp_ctrl_state == CTRL_STATUS_OUT_WAIT) { + URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_out); + switch (URB_Status) { + case HOST_CH_XFER_DONE: + phost->host_state = phost->host_state_backup; + phost->ctrlparam.ctrl_state = CTRL_COMPLETE; + break; + case HOST_CH_XFER_UNREADY: + phost->ctrlparam.ctrl_state = CTRL_STATUS_OUT; + break; + case HOST_CH_XFER_ERROR: + phost->ctrlparam.ctrl_state = CTRL_ERROR; + break; + default: + break; + } + } else if (tmp_ctrl_state == CTRL_ERROR) { + if (++ phost->ctrlparam.err_cnt <= HOST_MAX_ERROR_CNT) { + /* re-start the transmission, starting from SETUP packet */ + phost->ctrlparam.ctrl_state = CTRL_SETUP; + } else { + phost->ctrlparam.ctrl_status = CTRL_FAIL; + phost->host_state = phost->host_state_backup; + + status = HSTATUS_FAIL; + } + } else { + ; + } + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.h new file mode 100644 index 0000000000..1641d441b0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.h @@ -0,0 +1,95 @@ +/** + ******************************************************************************* + * @file usb_host_core.h + * @brief header file for the usb_host_core.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_CORE_H__ +#define __USB_HOST_CORE_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* USBH_CORE_Exported_Defines */ +#define MSC_CLASS (0x08U) +#define HID_CLASS (0x03U) +#define MSC_PROTOCOL (0x50U) +#define CBI_PROTOCOL (0x01U) + +#define DEV_DEFAULT_ADDRESS (0U) +#define DEV_ASSIGNED_ADDRESS (1U) + +#define HOST_MAX_ERROR_CNT (2U) + +#define ENUM_LOCAL_BUF (256U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern void usb_host_init(usb_core_instance *pdev, + USBH_HOST *phost, + usb_host_class_callback_func *class_cbk, + usb_host_user_callback_func *user_cbk); +extern void usb_host_deinit(usb_core_instance *pdev, USBH_HOST *phost); +extern void usb_host_mainprocess(usb_core_instance *pdev, USBH_HOST *phost); +extern void usb_host_errorprocess(USBH_HOST *phost, HOST_STATUS errType); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_CORE_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.c new file mode 100644 index 0000000000..24411527a2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.c @@ -0,0 +1,320 @@ +/** + ******************************************************************************* + * @file usb_host_ctrltrans.c + * @brief This file handles the issuing of the USB transactions + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_ctrltrans.h" +#include "usb_host_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_host_submitsetupreq(USBH_HOST *phost, uint8_t *buff, uint16_t length); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief Start a setup transfer by changing the state-machine and + * initializing the required variables needed for the Control Transfer + * @param [in] phost host state set + * @param [in] buff data buffer used for setup request + * @param [in] length data length in byte + * @retval status + */ +void usb_host_submitsetupreq(USBH_HOST *phost, uint8_t *buff, uint16_t length) +{ + /* Save Global State */ + phost->host_state_backup = phost->host_state; + /* Prepare the Transactions */ + phost->host_state = HOST_CTRL_TRANSMIT; + phost->ctrlparam.buff = buff; + phost->ctrlparam.length = length; + phost->ctrlparam.ctrl_state = CTRL_SETUP; +} + +/** + * @brief send a control request and update the status after the request sent. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] buff data buffer whose data will be sent in the control pipe. + * @param [in] length length of the data sent. + * @retval status + */ +HOST_STATUS usb_host_ctrlreq(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t *buff, + uint16_t length) +{ + HOST_STATUS status; + REQ_HANDLE_STATE tmp_req_state; + (void)(pdev); + status = HSTATUS_BUSY; + tmp_req_state = phost->req_state; + if (tmp_req_state == REQ_CMD_TX) { + /* prepare a setup packet for transferring */ + usb_host_submitsetupreq(phost, buff, length); + /* update the request state */ + phost->req_state = REQ_CMD_WAIT; + /* The status would be returned in this function */ + status = HSTATUS_BUSY; + } else if (tmp_req_state == REQ_CMD_WAIT) { + switch (phost->ctrlparam.ctrl_state) { + case CTRL_COMPLETE: + /* Commands have been successfully sent and Responses have been Received */ + phost->req_state = REQ_CMD_TX; + /* update the control state */ + phost->ctrlparam.ctrl_state = CTRL_IDLE; + status = HSTATUS_OK; + break; + case CTRL_ERROR: + /* fail transfer */ + phost->req_state = REQ_CMD_TX; + status = HSTATUS_FAIL; + break; + case CTRL_STALLED: + /* Commands have been successfully sent and Responses have been Received */ + phost->req_state = REQ_CMD_TX; + status = HSTATUS_UNSUPPORTED; + break; + default: + break; + } + } else { + ; + } + return status; +} + +/** + * @brief sends a setup packet to the control EP of the USB device + * @param [in] pdev device instance + * @param [in] buff data buffer whose data will be sent in the control pipe to the control EP of the device. + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_sendctrlsetup(usb_core_instance *pdev, uint8_t *buff, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = 0U; + pdev->host.hc[hc_num].pid_type = PID_SETUP; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = 8; + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief sends a data packet to the USB device + * @param [in] pdev device instance + * @param [in] buff data buffer whose data will be sent to the USB device + * @param [in] length the data length in byte that would be sent + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_sendctrldata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = 0; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + if (length == 0U) { + /* For Status OUT stage, Length==0, Status Out PID = 1 always */ + pdev->host.hc[hc_num].out_toggle = 1; + } + /* Set the Data Toggle bit */ + if (pdev->host.hc[hc_num].out_toggle == 0U) { + pdev->host.hc[hc_num].pid_type = PID_DATA0; + } else { + pdev->host.hc[hc_num].pid_type = PID_DATA1 ; + } + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief Receives the response data to the setup packet + * @param [in] pdev device instance + * @param [in] buff data buffer when received data. + * @param [in] length the length data in byte have received. + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_recvctrldata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = (uint8_t)1; + pdev->host.hc[hc_num].pid_type = PID_DATA1; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief sent the bulk packet to the device + * @param [in] pdev device instance + * @param [in] buff data buffer whose data will be sent + * @param [in] length data length in byte + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_sendbulkdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = 0; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + /* Set the Data Toggle bit */ + if (pdev->host.hc[hc_num].out_toggle == 0U) { + pdev->host.hc[hc_num].pid_type = PID_DATA0; + } else { + pdev->host.hc[hc_num].pid_type = PID_DATA1 ; + } + + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief receives bulk packet from device + * @param [in] pdev device instance + * @param [in] buff buffer to save the data received from the device + * @param [in] length data length in byte + * @param [in] hc_num host channel index + * @retval status + */ +void usb_host_recvbulkdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = (uint8_t)1; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + + + if (pdev->host.hc[hc_num].in_toggle == (uint8_t)0) { + pdev->host.hc[hc_num].pid_type = PID_DATA0; + } else { + pdev->host.hc[hc_num].pid_type = PID_DATA1; + } + + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief receives the device response to the Interrupt IN token + * @param [in] pdev device instance + * @param [in] buff buffer to save the data received from the device + * @param [in] length data length in byte + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_recvintdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = (uint8_t)1; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + if (pdev->host.hc[hc_num].in_toggle == (uint8_t)0) { + pdev->host.hc[hc_num].pid_type = PID_DATA0; + } else { + pdev->host.hc[hc_num].pid_type = PID_DATA1; + } + /* toggle the DATA PID */ + pdev->host.hc[hc_num].in_toggle ^= (uint8_t)1; + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief send the data on Interrupt OUT Endpoint + * @param [in] pdev device instance + * @param [in] buff data buffer whose data will be sent + * @param [in] length data length in byte + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_sentintdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = (uint8_t)0; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + + if (pdev->host.hc[hc_num].in_toggle == (uint8_t)0) { + pdev->host.hc[hc_num].pid_type = PID_DATA0; + } else { + pdev->host.hc[hc_num].pid_type = PID_DATA1; + } + + pdev->host.hc[hc_num].in_toggle ^= (uint8_t)1; + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief receives the Device Response to the Isochronous IN token + * @param [in] pdev device instance + * @param [in] buff buffer to save the data received from the device + * @param [in] length data length in byte + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_recvisocdata(usb_core_instance *pdev, uint8_t *buff, uint32_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = (uint8_t)1; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + pdev->host.hc[hc_num].pid_type = PID_DATA0; + + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @brief Sends the data through Isochronous OUT Endpoint + * @param [in] pdev device instance + * @param [in] buff data buffer whose data will be sent + * @param [in] length data length in byte + * @param [in] hc_num host channel index + * @retval None + */ +void usb_host_sendisocdata(usb_core_instance *pdev, uint8_t *buff, uint32_t length, uint8_t hc_num) +{ + pdev->host.hc[hc_num].is_epin = (uint8_t)0; + pdev->host.hc[hc_num].xfer_buff = buff; + pdev->host.hc[hc_num].xfer_len = length; + pdev->host.hc[hc_num].pid_type = PID_DATA0; + (void)host_driver_submitrequest(pdev, hc_num); +} + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.h new file mode 100644 index 0000000000..f3d8525c53 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.h @@ -0,0 +1,86 @@ +/** + ******************************************************************************* + * @file usb_host_ctrltrans.h + * @brief header file for the usb_host_ctrltrans.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_CTRLTRANS_H__ +#define __USB_HOST_CTRLTRANS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern void usb_host_sendctrlsetup(usb_core_instance *pdev, uint8_t *buff, uint8_t hc_num); +extern void usb_host_sendctrldata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num); +extern void usb_host_recvctrldata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num); +extern void usb_host_recvbulkdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num); +extern void usb_host_sendbulkdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num); +extern void usb_host_recvintdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num); +extern void usb_host_sentintdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num); +extern HOST_STATUS usb_host_ctrlreq(usb_core_instance *pdev, USBH_HOST *phost, uint8_t *buff, uint16_t length); +extern void usb_host_recvisocdata(usb_core_instance *pdev, uint8_t *buff, uint32_t length, uint8_t hc_num); +extern void usb_host_sendisocdata(usb_core_instance *pdev, uint8_t *buff, uint32_t length, uint8_t hc_num); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_CTRLTRANS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_def.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_def.h new file mode 100644 index 0000000000..c4df0492a0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_def.h @@ -0,0 +1,430 @@ +/** + ******************************************************************************* + * @file usb_host_def.h + * @brief Definitions used in the USB host library + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_DEF_H__ +#define __USB_HOST_DEF_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "usb_app_conf.h" +#include "usb_lib.h" +#include "hc32_ll.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/* This Union is copied from usb_core.h */ +typedef union { + uint16_t w; + struct BW { + uint8_t msb; + uint8_t lsb; + } + bw; +} uint16_t_uint8_t; +/* standard setup packet defination */ +typedef union { + uint8_t d8[8]; + struct _SetupPkt_Struc { + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t_uint8_t wValue; + uint16_t_uint8_t wIndex; + uint16_t_uint8_t wLength; + } b; +} usb_setup_typedef; + +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; +} USB_HOST_DescHeader_TypeDef; + +/* Standard Device Descriptor */ +typedef struct { + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* Device descriptor type */ + uint16_t bcdUSB; /* USB Specification Release Numbrer in Binary-Coded Decimal(i.e.,2.10 is 210H) */ + uint8_t bDeviceClass; /* Class code(assigned by the USB-IF) */ + uint8_t bDeviceSubClass; /* Subclass code(assigned by the USB-IF) this code is qualified by the value of the \ + bDeviceClass field. */ + uint8_t bDeviceProtocol; /* Protocol code(assigned by the USB-IF), this code is qualified by the value of the \ + bDeviceClass and the bDeviceSubClass fields. */ + uint8_t bMaxPacketSize0; /* Maximum packet size for EP0 */ + uint16_t idVendor; /* Vendor ID (assigned by the USB-IF) */ + uint16_t idProduct; /* Product ID (assigned by manufacturer) */ + uint16_t bcdDevice; /* Device Release Number in binary-coded decimal */ + uint8_t iManufacturer; /* Index of string descriptor describing manufacturer */ + uint8_t iProduct; /* Index of string descriptor describing product */ + uint8_t iSerialNumber; /* Index of string descriptor describing the device's serial number */ + uint8_t bNumConfigurations; /* Number of possible configurations */ +} usb_host_devdesc_typedef; + +/* Standard Configuration Descriptor */ +typedef struct { + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CONFIGURATION descriptor type */ + uint16_t wTotalLength; /* Total length of data returned for this configuration */ + uint8_t bNumInterfaces; /* Number of interfaces supported by this configuration */ + uint8_t bConfigurationValue; /* Value to use as an argument to the SetConfiguration() request to select this configuration */ + uint8_t iConfiguration; /* Index of string descriptor describing this configuration */ + uint8_t bmAttributes; /* Configuration characteristics: D7:Reserved(set to one) D6:Self-powered D5:Remote Wakeup D4..0 Reserved(set to zero) */ + uint8_t bMaxPower; /* Maximum power consumption of the device from the bus in this specific configuration when the device is fully operational */ +} usb_host_cfgdesc_typedef; + +typedef struct { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; /* indicates what endpoint this descriptor is describing */ + uint8_t bCountryCode; /* specifies the transfer type. */ + uint8_t bNumDescriptors; /* specifies the transfer type. */ + uint8_t bReportDescriptorType; /* Maximum Packet Size this endpoint is capable of sending or receiving */ + uint16_t wItemLength; /* is used to specify the polling interval of certain transfers. */ +} USB_HOST_HIDDesc_TypeDef; + +/* Standard Interface Descriptor */ +typedef struct { + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* INTERFACE Descriptor Type */ + uint8_t bInterfaceNumber; /* Number of this interface */ + uint8_t bAlternateSetting; /* Value used to select this alternate setting for the interface identifiled in the \ + prior field */ + uint8_t bNumEndpoints; /* Number of Endpoints used by this interface */ + uint8_t bInterfaceClass; /* Class code (assigned by the USB-IF) */ + uint8_t bInterfaceSubClass; /* Subclass code (assigned by the USB-IF) */ + uint8_t bInterfaceProtocol; /* Protocol code (assigned by the USB) */ + uint8_t iInterface; /* Index of string descriptor describing this interface */ +} usb_host_itfdesc_typedef; + +/* Standard Endpoint Descriptor */ +typedef struct { + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* ENDPOINT descriptor type */ + uint8_t bEndpointAddress; /* The address of the endpoint on the device described by this descriptor */ + uint8_t bmAttributes; /* refer to the related standard of USB 2.0 */ + uint16_t wMaxPacketSize; /* Maximum Packet Size this endpoint is capable of sending or receiving when this \ + configuration is selected */ + uint8_t bInterval; /* Interval for servicing the endpoint for data transfers */ +} USB_HOST_EPDesc_TypeDef; + +/* USBH_CORE_Exported_Types */ +/* Host status */ +typedef enum { + HSTATUS_OK = 0, + HSTATUS_BUSY, + HSTATUS_FAIL, + HSTATUS_UNSUPPORTED, + HSTATUS_UNRECOVERED_ERROR, + HSTATUS_SPEED_UNKNOWN, + HSTATUS_APP_DEINIT +} HOST_STATUS; + +/* states about the handle stages on the host side */ +typedef enum { + HOST_IDLE = 0, + HOST_DEV_CONNECTED, + HOST_DEV_DISCONNECTED, + HOST_GET_DEVSPEED, + HOST_ENUM, + HOST_CLASS_REQ, + HOST_CLASS_PROCESS, + HOST_CTRL_TRANSMIT, + HOST_USER_INPUT, + HOST_SUSPENDED, + HOST_ERROR_STATE +} HOST_HANDLE_STATE; + + +/* states of the enumeration stage on the host side */ +typedef enum { + ENUM_IDLE = 0, + ENUM_GET_FULL_DEVDESC, + ENUM_SET_DEVADDR, + ENUM_GET_CFGDESC, + ENUM_GET_FULL_CFGDESC, + ENUM_GET_MFCSTRINGDESC, + ENUM_GET_PRODUCT_STRINGDESC, + ENUM_GET_SERIALNUM_STRINGDESC, + ENUM_SET_CFG, + ENUM_DEV_CFG_OVER +} ENUM_HANDLE_STATE; + +/* states of the control stages on the host side */ +typedef enum { + CTRL_IDLE = 0, + CTRL_SETUP, + CTRL_SETUP_WAIT, + CTRL_DATA_IN, + CTRL_DATA_IN_WAIT, + CTRL_DATA_OUT, + CTRL_DATA_OUT_WAIT, + CTRL_STATUS_IN, + CTRL_STATUS_IN_WAIT, + CTRL_STATUS_OUT, + CTRL_STATUS_OUT_WAIT, + CTRL_ERROR, + CTRL_STALLED, + CTRL_COMPLETE +} CTRL_HANDLE_STATE; + +/* Following states are state machine for the request transferring */ +typedef enum { + REQ_CMD_IDLE = 0, + REQ_CMD_TX, + REQ_CMD_WAIT +} REQ_HANDLE_STATE; + +typedef enum { + USER_HAVE_RESP = 0, + USER_NONE_RESP +} HOST_USER_STATUS; + +typedef struct { + uint8_t hc_num_in; /* channel number for the IN EP */ + uint8_t hc_num_out; /* channel number for the OUT EP */ + uint8_t ctrlmaxsize; /* the max size of EP0 parsed from the device descriptor */ + uint8_t err_cnt; /* the error counter */ + uint16_t sof_num; /* the frame number for sof packet */ + uint16_t length; /* length of data in byte */ + uint8_t *buff; /* data buffer */ + CTRL_HANDLE_STATUS ctrl_status; /* status of control pipe */ + CTRL_HANDLE_STATE ctrl_state; /* running state of the control transfer */ + usb_setup_typedef setup; /* setup packet */ +} usb_host_ctrl_param; + +/* Device information parsed from the related descriptors requested from the connected device + the following data are all parsed from the data sent by the connnected device */ +typedef struct { + uint8_t devaddr; /* the address of the connected device */ + uint8_t devspeed; /* the core speed of the connected device */ + usb_host_devdesc_typedef devdesc; /* the device descriptor parsed from the data sent by device */ + usb_host_cfgdesc_typedef devcfgdesc; /* the device configuration descriptor parsed from the data sent by device */ + usb_host_itfdesc_typedef devitfdesc[USBH_MAX_NUM_INTERFACES]; /* the interface descritpor */ + USB_HOST_EPDesc_TypeDef devepdesc[USBH_MAX_NUM_INTERFACES][USBH_MAX_NUM_ENDPOINTS]; /* the endpoint descriptor */ + USB_HOST_HIDDesc_TypeDef hiddesc; /* the hid descriptor */ +} usb_host_devinformation; + +typedef struct { + HOST_STATUS(*host_class_init)(usb_core_instance *pdev, void *phost); + void (*host_class_deinit)(usb_core_instance *pdev); + HOST_STATUS(*host_class_request)(usb_core_instance *pdev, void *phost); + HOST_STATUS(*host_class_process)(usb_core_instance *pdev, void *phost); +} usb_host_class_callback_func; + +typedef struct { + void (*huser_init)(void); + void (*huser_deinit)(void); + void (*huser_devattached)(void); + void (*huser_devreset)(void); + void (*huser_devdisconn)(void); + void (*huser_overcurrent)(void); + void (*huser_devspddetected)(uint8_t DeviceSpeed); + void (*huser_devdescavailable)(void *); + void (*huser_devaddrdistributed)(void); + void (*huser_cfgdescavailable)(usb_host_cfgdesc_typedef *, + usb_host_itfdesc_typedef *, + USB_HOST_EPDesc_TypeDef *); + /* Configuration Descriptor available */ + void (*huser_mfcstring)(void *); + void (*huser_productstring)(void *); + void (*huser_serialnum)(void *); + void (*huser_enumcompl)(void); + HOST_USER_STATUS(*huser_userinput)(void); + int (*huser_application)(void); + void (*huser_devunsupported)(void); + void (*huser_unrecoverederror)(void); +} usb_host_user_callback_func; + +typedef struct { + /* states for the host, enumeration, request */ + REQ_HANDLE_STATE req_state; /* value of state machine about the request */ + ENUM_HANDLE_STATE enum_state; /* state machine while enumerating */ + HOST_HANDLE_STATE host_state_backup; /* backup value of state machine about the host */ + HOST_HANDLE_STATE host_state; /* value of state machine about the host */ + /* control informations */ + usb_host_ctrl_param ctrlparam; /* values about the control parameters */ + /* device information parsed from the descriptors from the device */ + usb_host_devinformation device_prop; + /* functions: call back functions for the class and user */ + usb_host_class_callback_func *class_callbk; + usb_host_user_callback_func *user_callbk; +} USBH_HOST; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef TRUE +#define TRUE 1U +#endif + +/* Get a 16bits data from buffer in little end mode. */ +#define SMALL_END(addr) (((uint16_t)(*((uint8_t *)(addr)))) + (((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) + +#define USB_LEN_CFG_DESC (0x09U) + +/* bmRequestType +D7: Data transfer direction + 0 = Host-to-device + 1 = Device-to-host +*/ +#define USB_REQ_DIR_MASK (0x80U) +#define USB_H2D (0x00U) +#define USB_D2H (0x80U) + +/* bmRequestType +D6...5: Type + 0 = Standard + 1 = Class + 2 = Vendor + 3 = Reserved +*/ +#define USB_REQ_TYPE_STANDARD (0x00U) +#define USB_REQ_TYPE_CLASS (0x20U) +#define USB_REQ_TYPE_VENDOR (0x40U) +#define USB_REQ_TYPE_RESERVED (0x60U) + +/* bmRequestType +D4...0: Recipient + 0 = Device + 1 = Interface + 2 = Endpoint + 3 = Other + 4...31 = Reserved +*/ +#define USB_REQ_RECIPIENT_DEVICE (0x00U) +#define USB_REQ_RECIPIENT_INTERFACE (0x01U) +#define USB_REQ_RECIPIENT_ENDPOINT (0x02U) +#define USB_REQ_RECIPIENT_OTHER (0x03U) + +/* Table 9-4. Standard Request Codes [USB Specification] */ +/* bRequest Value */ +#define USB_REQ_GET_STATUS (0x00U) +#define USB_REQ_CLEAR_FEATURE (0x01U) +#define USB_REQ_SET_FEATURE (0x03U) +#define USB_REQ_SET_ADDRESS (0x05U) +#define USB_REQ_GET_DESCRIPTOR (0x06U) +#define USB_REQ_SET_DESCRIPTOR (0x07U) +#define USB_REQ_GET_CONFIGURATION (0x08U) +#define USB_REQ_SET_CONFIGURATION (0x09U) +#define USB_REQ_GET_INTERFACE (0x0AU) +#define USB_REQ_SET_INTERFACE (0x0BU) +#define USB_REQ_SYNCH_FRAME (0x0Cu) + +/* Table 9-5. Descriptor Types [USB Specification] */ +/* Descriptor Types Value */ +#define USB_DESC_TYPE_DEVICE (1U) +#define USB_DESC_TYPE_CONFIGURATION (2U) +#define USB_DESC_TYPE_STRING (3U) +#define USB_DESC_TYPE_INTERFACE (4U) +#define USB_DESC_TYPE_ENDPOINT (5U) +#define USB_DESC_TYPE_DEVICE_QUALIFIER (6U) +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION (7U) +#define USB_DESC_TYPE_INTERFACE_POWER (8U) +#define USB_DESC_TYPE_HID (0x21U) +#define USB_DESC_TYPE_HID_REPORT (0x22U) + +#define USB_DEVICE_DESC_SIZE (18U) +#define USB_CONFIGURATION_DESC_SIZE (9U) +#define USB_HID_DESC_SIZE (9U) +#define USB_INTERFACE_DESC_SIZE (9U) +#define USB_ENDPOINT_DESC_SIZE (7U) + +/* Descriptor Type and Descriptor Index */ +/* Use the following values when calling the function usb_host_getdesc */ +#define USB_DESC_DEVICE (((uint16_t)USB_DESC_TYPE_DEVICE << 8U) & 0xFF00U) +#define USB_DESC_CONFIGURATION (((uint16_t)USB_DESC_TYPE_CONFIGURATION << 8U) & 0xFF00U) +#define USB_DESC_STRING (((uint16_t)USB_DESC_TYPE_STRING << 8U) & 0xFF00U) +#define USB_DESC_INTERFACE (((uint16_t)USB_DESC_TYPE_INTERFACE << 8U) & 0xFF00U) +#define USB_DESC_ENDPOINT (((uint16_t)USB_DESC_TYPE_INTERFACE << 8U) & 0xFF00U) +#define USB_DESC_DEVICE_QUALIFIER (((uint16_t)USB_DESC_TYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U) +#define USB_DESC_OTHER_SPEED_CONFIGURATION (((uint16_t)USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U) +#define USB_DESC_INTERFACE_POWER (((uint16_t)USB_DESC_TYPE_INTERFACE_POWER << 8U) & 0xFF00U) +#define USB_DESC_HID_REPORT (((uint16_t)USB_DESC_TYPE_HID_REPORT << 8U) & 0xFF00U) +#define USB_DESC_HID (((uint16_t)USB_DESC_TYPE_HID << 8U) & 0xFF00U) + +#define USB_EP_DIR_OUT (0x00U) +#define USB_EP_DIR_IN (0x80U) +#define USB_EP_DIR_MSK (0x80U) + +/* supported classes */ +#define USB_MSC_CLASS (0x08U) +#define USB_HID_CLASS (0x03U) + +/* Interface Descriptor field values for HID Boot Protocol */ +#define HID_BOOT_CODE (0x01U) +#define HID_KEYBRD_BOOT_CODE (0x01U) +#define HID_MOUSE_BOOT_CODE (0x02U) + +/* As per USB specs 9.2.6.4 :Standard request with data request timeout: 5sec + Standard request with no data stage timeout : 50ms */ +#define DATA_STAGE_TIMEOUT (5000U) +#define NODATA_STAGE_TIMEOUT (50U) + +/* Macro definations for host mode */ +#define PID_DATA0 (0U) +#define PID_DATA2 (1U) +#define PID_DATA1 (2U) +#define PID_SETUP (3U) +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_DEF_H__ */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.c new file mode 100644 index 0000000000..6ebc74afe7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.c @@ -0,0 +1,231 @@ +/** + ******************************************************************************* + * @file usb_host_driver.c + * @brief Host Interface Layer. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_driver.h" +#include "usb_bsp.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief Initialize the driver for the host mode + * @param [in] pdev device instance + * @retval None + */ +void host_driver_init(usb_core_instance *pdev) +{ + uint8_t i; + + pdev->host.is_dev_connect = 0U; + for (i = 0U; i < USB_MAX_TX_FIFOS; i++) { + pdev->host.ErrCnt[i] = 0U; + pdev->host.XferCnt[i] = 0U; + pdev->host.HC_Status[i] = HOST_CH_IDLE; + } + pdev->host.hc[0].max_packet = 8U; + + usb_setregaddr(&pdev->regs, &pdev->basic_cfgs);; + + usb_gintdis(&pdev->regs); + usb_initusbcore(&pdev->regs, &pdev->basic_cfgs); + /* force to work in host mode*/ + usb_modeset(&pdev->regs, HOST_MODE); + /* configure charge pump IO */ + usb_bsp_cfgvbus(&pdev->regs); + usb_vbusctrl(&pdev->regs, 1U); + usb_mdelay(50UL); + + usb_hostmodeinit(&pdev->regs, &pdev->basic_cfgs); + usb_ginten(&pdev->regs); +} + +/** + * @brief get current speed when in host mode + * @param [in] pdev device instance + * @retval current speed + */ +uint32_t host_driver_getcurrentspd(usb_core_instance *pdev) +{ + uint32_t u32hppt; + u32hppt = READ_REG32(*pdev->regs.HPRT); + return ((u32hppt & USBFS_HPRT_PSPD) >> USBFS_HPRT_PSPD_POS); +} + +/** + * @brief get current DM DP state + * @param [in] pdev device instance + * @retval DM DP state + * 0x00 DM L, DP L + * 0x01 DM L, DP H + * 0x02 DM H, DP L + * 0x03 DM H, DP H + */ +uint32_t host_driver_getdmdpstate(usb_core_instance *pdev) +{ + uint32_t u32hppt; + u32hppt = READ_REG32(*pdev->regs.HPRT); + return ((u32hppt & USBFS_HPRT_PLSTS) >> USBFS_HPRT_PLSTS_POS); +} + +/** + * @brief get vbus drive state + * @param [in] pdev device instance + * @retval vbus driver state + * 0x00 vbus driver disable + * 0x01 vbus driver enable + */ +uint32_t host_driver_getvbusdrivestate(usb_core_instance *pdev) +{ + uint32_t u32hppt; + u32hppt = READ_REG32(*pdev->regs.HPRT); + return ((u32hppt & USBFS_HPRT_PWPR) >> USBFS_HPRT_PWPR_POS); +} + +/** + * @brief reset the port + * @param [in] pdev device instance + * @retval None + */ +void host_driver_portrst(usb_core_instance *pdev) +{ + usb_hprtrst(&pdev->regs); +} + +/** + * @brief get the connected status of the device + * @param [in] pdev device instance + * @retval 1 connected or 0 disconnected + */ +uint32_t host_driver_ifdevconnected(usb_core_instance *pdev) +{ + return (pdev->host.is_dev_connect); +} + +/** + * @brief gets the frame number for of sof packet + * @param [in] pdev device instance + * @retval number of frame + */ +uint32_t host_driver_getcurrentfrm(usb_core_instance *pdev) +{ + return (READ_REG32(pdev->regs.HREGS->HFNUM) & 0xFFFFUL) ; +} + +/** + * @brief gets the last xfer state + * @param [in] pdev device instance + * @param [in] ch_num channel number + * @retval HOST_CH_XFER_STATE + */ +HOST_CH_XFER_STATE host_driver_getxferstate(usb_core_instance *pdev, uint8_t ch_num) +{ + return pdev->host.URB_State[ch_num] ; +} + +/** + * @brief gets the xfer count + * @param [in] pdev device instance + * @param [in] ch_num channel number + * @retval number of data trandmitted in bytes + */ +uint32_t host_driver_getxfercnt(usb_core_instance *pdev, uint8_t ch_num) +{ + return pdev->host.XferCnt[ch_num] ; +} + +/** + * @brief gets the host channel status + * @param [in] pdev device instance + * @param [in] ch_num channel number + * @retval HOST_CH_STATUS + */ +HOST_CH_STATUS host_driver_gethostchstate(usb_core_instance *pdev, uint8_t ch_num) +{ + return pdev->host.HC_Status[ch_num] ; +} + +/** + * @brief prepare a host channel and start a transfer + * @param [in] pdev device instance + * @param [in] hc_num channel number + * @retval status + */ +uint32_t host_driver_hostch_init(usb_core_instance *pdev, uint8_t hc_num) +{ + return usb_inithch(&pdev->regs, hc_num, &pdev->host.hc[hc_num], pdev->basic_cfgs.dmaen); +} + +/** + * @brief prepare a host channel and start a transfer + * @param [in] pdev device instance + * @param [in] hc_num channel number + * @retval status + */ +uint32_t host_driver_submitrequest(usb_core_instance *pdev, uint8_t hc_num) +{ + pdev->host.URB_State[hc_num] = HOST_CH_XFER_IDLE; + pdev->host.hc[hc_num].xfer_count = 0U ; + return usb_hchtransbegin(&pdev->regs, hc_num, &pdev->host.hc[hc_num], pdev->basic_cfgs.dmaen); +} + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.h new file mode 100644 index 0000000000..31bff9112c --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.h @@ -0,0 +1,90 @@ +/** + ******************************************************************************* + * @file usb_host_driver.h + * @brief Head file for usb_host_driver.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_DRIVER_H__ +#define __USB_HOST_DRIVER_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern void host_driver_init(usb_core_instance *pdev); +extern uint32_t host_driver_hostch_init(usb_core_instance *pdev, uint8_t hc_num); +extern uint32_t host_driver_submitrequest(usb_core_instance *pdev, uint8_t hc_num); +extern uint32_t host_driver_getcurrentspd(usb_core_instance *pdev); +extern uint32_t host_driver_getdmdpstate(usb_core_instance *pdev); +extern uint32_t host_driver_getvbusdrivestate(usb_core_instance *pdev); +extern void host_driver_portrst(usb_core_instance *pdev); +extern uint32_t host_driver_ifdevconnected(usb_core_instance *pdev); +extern uint32_t host_driver_getcurrentfrm(usb_core_instance *pdev); +extern HOST_CH_XFER_STATE host_driver_getxferstate(usb_core_instance *pdev, uint8_t ch_num); +extern uint32_t host_driver_getxfercnt(usb_core_instance *pdev, uint8_t ch_num); +extern HOST_CH_STATUS host_driver_gethostchstate(usb_core_instance *pdev, uint8_t ch_num); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_DRIVER_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.c new file mode 100644 index 0000000000..a547fefce9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.c @@ -0,0 +1,575 @@ +/** + ******************************************************************************* + * @file usb_host_int.c + * @brief Host driver interrupt subroutines. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_int.h" +#include "usb_host_driver.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +void usb_host_hc_isr(usb_core_instance *pdev); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief processes interrupt for a specific host channel which is used for OUT EP + * @param [in] pdev device instance + * @param [in] chnum channel index + * @retval None + */ +static void usb_host_chx_out_isr(usb_core_instance *pdev, uint8_t chnum) +{ + uint32_t u32hcchar; + uint32_t u32hcint; + uint32_t u32hcintmsk; + + u32hcchar = READ_REG32(pdev->regs.HC_REGS[chnum]->HCCHAR); + u32hcint = READ_REG32(pdev->regs.HC_REGS[chnum]->HCINT); + u32hcintmsk = READ_REG32(pdev->regs.HC_REGS[chnum]->HCINTMSK); + u32hcint = u32hcint & u32hcintmsk; + + if (0UL != (u32hcint & USBFS_HCINT_ACK)) { + usb_host_clrint(pdev, chnum, USBFS_HCINT_ACK); + } +#if defined (HC32F4A0) + else if (0UL != (u32hcint & USBFS_HCINT_AHBERR)) { + usb_host_clrint(pdev, chnum, USBFS_HCINT_AHBERR); + usb_host_int_unmskchhltd(pdev, chnum); + } +#endif + else if (0UL != (u32hcint & USBFS_HCINT_FRMOR)) { + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_FRMOR); + } else if (0UL != (u32hcint & USBFS_HCINT_XFRC)) { + pdev->host.ErrCnt[chnum] = 0U; + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_XFRC); + pdev->host.HC_Status[chnum] = HOST_CH_XFERCOMPL; + } else if (0UL != (u32hcint & USBFS_HCINT_STALL)) { + usb_host_clrint(pdev, chnum, USBFS_HCINT_STALL); + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + pdev->host.HC_Status[chnum] = HOST_CH_STALL; + } else if (0UL != (u32hcint & USBFS_HCINT_NAK)) { + pdev->host.ErrCnt[chnum] = 0U; + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK); + pdev->host.HC_Status[chnum] = HOST_CH_NAK; + } else if (0UL != (u32hcint & USBFS_HCINT_TXERR)) { + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + pdev->host.ErrCnt[chnum] ++; + pdev->host.HC_Status[chnum] = HOST_CH_XACTERR; + usb_host_clrint(pdev, chnum, USBFS_HCINT_TXERR); + } else if (0UL != (u32hcint & HCINT_NYET)) { + pdev->host.ErrCnt[chnum] = 0U; + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, HCINT_NYET); + pdev->host.HC_Status[chnum] = HOST_CH_NYET; + } else if (0UL != (u32hcint & USBFS_HCINT_DTERR)) { + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK); + pdev->host.HC_Status[chnum] = HOST_CH_DATATGLERR; + usb_host_clrint(pdev, chnum, USBFS_HCINT_DTERR); + } else if (0UL != (u32hcint & USBFS_HCINT_CHH)) { + usb_host_int_mskchhltd(pdev, chnum); + if (pdev->host.HC_Status[chnum] == HOST_CH_XFERCOMPL) { + pdev->host.URB_State[chnum] = HOST_CH_XFER_DONE; + + if (((u32hcchar & USBFS_HCCHAR_EPTYP) >> USBFS_HCCHAR_EPTYP_POS) == EP_TYPE_BULK) { + pdev->host.hc[chnum].out_toggle ^= 1U; + } + } else if (pdev->host.HC_Status[chnum] == HOST_CH_NAK) { + pdev->host.URB_State[chnum] = HOST_CH_XFER_UNREADY; + } else if (pdev->host.HC_Status[chnum] == HOST_CH_NYET) { + if (pdev->host.hc[chnum].do_ping == 1U) { + usb_pingtokenissue(&pdev->regs, chnum); + } + pdev->host.URB_State[chnum] = HOST_CH_XFER_UNREADY; + } else if (pdev->host.HC_Status[chnum] == HOST_CH_STALL) { + pdev->host.URB_State[chnum] = HOST_CH_XFER_STALL; + } else if (pdev->host.HC_Status[chnum] == HOST_CH_XACTERR) { + if (pdev->host.ErrCnt[chnum] == 3UL) { + pdev->host.URB_State[chnum] = HOST_CH_XFER_ERROR; + pdev->host.ErrCnt[chnum] = 0UL; + } + } else { + ; + } + usb_host_clrint(pdev, chnum, USBFS_HCINT_CHH); + } else { + ; + } +} + +/** + * @brief processes interrupt for a specific host Channel which is used for IN EP + * @param [in] pdev device instance + * @param [in] chnum channel index + * @retval None + */ +static void usb_host_chx_in_isr(usb_core_instance *pdev, uint8_t chnum) +{ + uint32_t u32hcchar; + uint32_t u32hctsiz; + uint32_t u32eptypetmp; + uint32_t u32hcint; + uint32_t u32hcintmsk; + + u32hcchar = READ_REG32(pdev->regs.HC_REGS[chnum]->HCCHAR); + u32hcint = READ_REG32(pdev->regs.HC_REGS[chnum]->HCINT); + u32hcintmsk = READ_REG32(pdev->regs.HC_REGS[chnum]->HCINTMSK); + u32hcint = u32hcint & u32hcintmsk; + + u32eptypetmp = (u32hcchar & USBFS_HCCHAR_EPTYP) >> USBFS_HCCHAR_EPTYP_POS; + if (0UL != (u32hcint & USBFS_HCINT_ACK)) { + usb_host_clrint(pdev, chnum, USBFS_HCINT_ACK); + } +#if defined (HC32F4A0) + else if (0UL != (u32hcint & USBFS_HCINT_AHBERR)) { + usb_host_clrint(pdev, chnum, USBFS_HCINT_AHBERR); + usb_host_int_unmskchhltd(pdev, chnum); + } +#endif + else if (0UL != (u32hcint & USBFS_HCINT_STALL)) { + usb_host_int_unmskchhltd(pdev, chnum); + pdev->host.HC_Status[chnum] = HOST_CH_STALL; + usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK); + usb_host_clrint(pdev, chnum, USBFS_HCINT_STALL); + usb_hchstop(&pdev->regs, chnum); + } else if (0UL != (u32hcint & USBFS_HCINT_DTERR)) { + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK); + pdev->host.HC_Status[chnum] = HOST_CH_DATATGLERR; + usb_host_clrint(pdev, chnum, USBFS_HCINT_DTERR); + } else if (0UL != (u32hcint & USBFS_HCINT_FRMOR)) { + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_FRMOR); + } else if (0UL != (u32hcint & USBFS_HCINT_XFRC)) { + if (pdev->basic_cfgs.dmaen == 1U) { + u32hctsiz = READ_REG32(pdev->regs.HC_REGS[chnum]->HCTSIZ); + pdev->host.XferCnt[chnum] = pdev->host.hc[chnum].xfer_len - (u32hctsiz & USBFS_HCTSIZ_XFRSIZ); + } + pdev->host.HC_Status[chnum] = HOST_CH_XFERCOMPL; + pdev->host.ErrCnt [chnum] = 0U; + usb_host_clrint(pdev, chnum, USBFS_HCINT_XFRC); + switch (u32eptypetmp) { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK); + pdev->host.hc[chnum].in_toggle ^= (uint8_t)1; + break; + case EP_TYPE_INTR: + u32hcchar |= USBFS_HCCHAR_ODDFRM; + WRITE_REG32(pdev->regs.HC_REGS[chnum]->HCCHAR, u32hcchar); + pdev->host.URB_State[chnum] = HOST_CH_XFER_DONE; + break; + case EP_TYPE_ISOC: + if (pdev->host.HC_Status[chnum] == HOST_CH_XFERCOMPL) { + pdev->host.URB_State[chnum] = HOST_CH_XFER_DONE; + } + break; + default: + break; + } + } else if (0UL != (u32hcint & USBFS_HCINT_CHH)) { + usb_host_int_mskchhltd(pdev, chnum); + if (pdev->host.HC_Status[chnum] == HOST_CH_XFERCOMPL) { + pdev->host.URB_State[chnum] = HOST_CH_XFER_DONE; + } else if (pdev->host.HC_Status[chnum] == HOST_CH_STALL) { + pdev->host.URB_State[chnum] = HOST_CH_XFER_STALL; + } else if (pdev->host.HC_Status[chnum] == HOST_CH_XACTERR) { + pdev->host.ErrCnt[chnum] = 0U; + pdev->host.URB_State[chnum] = HOST_CH_XFER_ERROR; + } else if (pdev->host.HC_Status[chnum] == HOST_CH_DATATGLERR) { + pdev->host.ErrCnt[chnum] = 0U; + pdev->host.URB_State[chnum] = HOST_CH_XFER_ERROR; + } else if (u32eptypetmp == EP_TYPE_INTR) { + pdev->host.hc[chnum].in_toggle ^= (uint8_t)1; + } else { + ; + } + usb_host_clrint(pdev, chnum, USBFS_HCINT_CHH); + } else if (0UL != (u32hcint & USBFS_HCINT_TXERR)) { + usb_host_int_unmskchhltd(pdev, chnum); + pdev->host.ErrCnt[chnum] ++; + pdev->host.HC_Status[chnum] = HOST_CH_XACTERR; + usb_hchstop(&pdev->regs, chnum); + usb_host_clrint(pdev, chnum, USBFS_HCINT_TXERR); + } else if (0UL != (u32hcint & USBFS_HCINT_NAK)) { + if (u32eptypetmp == EP_TYPE_INTR) { + usb_host_int_unmskchhltd(pdev, chnum); + usb_hchstop(&pdev->regs, chnum); + } else if ((u32eptypetmp == EP_TYPE_CTRL) || (u32eptypetmp == EP_TYPE_BULK)) { + u32hcchar |= USBFS_HCCHAR_CHENA; + u32hcchar &= ~USBFS_HCCHAR_CHDIS; + WRITE_REG32(pdev->regs.HC_REGS[chnum]->HCCHAR, u32hcchar); + } else { + ; + } + pdev->host.HC_Status[chnum] = HOST_CH_NAK; + usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK); + } else { + ; + } +} + +/** + * @brief this function processes the channel interrupt + * @param [in] pdev device instance + * @retval None + */ +void usb_host_hc_isr(usb_core_instance *pdev) +{ + uint32_t u32hcchar; + uint8_t u8Cnt; + uint32_t u32haint; + + u32haint = READ_REG32(pdev->regs.HREGS->HAINT); + for (u8Cnt = 0U; u8Cnt < pdev->basic_cfgs.host_chnum; u8Cnt++) { + if (0UL != (u32haint & (1UL << u8Cnt))) { + u32hcchar = READ_REG32(pdev->regs.HC_REGS[u8Cnt]->HCCHAR); + if (0UL != ((u32hcchar & USBFS_HCCHAR_EPDIR) >> USBFS_HCCHAR_EPDIR_POS)) { + usb_host_chx_in_isr(pdev, u8Cnt); + } else { + usb_host_chx_out_isr(pdev, u8Cnt); + } + } + } +} + +/** + * @brief process the start-of-frame interrupt in host mode. + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_sof_isr(usb_core_instance *pdev) +{ + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_SOF); +} + +/** + * @brief processes disconnect interrupt + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_disconn_isr(usb_core_instance *pdev) +{ + usb_gintdis(&pdev->regs); + usb_vbusctrl(&pdev->regs, 0U); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_DISCINT); + + pdev->host.is_dev_connect = 0U; +} + +#define USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM_POS (27U) +#define USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM (0x78000000UL) +/** + * @brief processes non-periodic txFIFO empty interrupt. + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_nptxfifoempty_isr(usb_core_instance *pdev) +{ + uint32_t u32hnptxsts; + uint16_t u16LenWord; + uint16_t u16Len; + uint8_t u8ChNum; + + u32hnptxsts = READ_REG32(pdev->regs.GREGS->HNPTXSTS); + u8ChNum = (uint8_t)((u32hnptxsts & USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM) >> USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM_POS); + + u16LenWord = (uint16_t)((pdev->host.hc[u8ChNum].xfer_len + 3UL) / 4UL); + while (((u32hnptxsts & USBFS_HNPTXSTS_NPTXFSAV) > u16LenWord) && (pdev->host.hc[u8ChNum].xfer_len != 0U)) { + u16Len = (uint16_t)((u32hnptxsts & USBFS_HNPTXSTS_NPTXFSAV) * 4UL); + if (u16Len > pdev->host.hc[u8ChNum].xfer_len) { + u16Len = (uint16_t)pdev->host.hc[u8ChNum].xfer_len; + CLR_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTSTS_NPTXFE); + } + u16LenWord = (uint16_t)((pdev->host.hc[u8ChNum].xfer_len + 3UL) / 4UL); + usb_wrpkt(&pdev->regs, pdev->host.hc[u8ChNum].xfer_buff, u8ChNum, u16Len, pdev->basic_cfgs.dmaen); + pdev->host.hc[u8ChNum].xfer_buff += u16Len; + pdev->host.hc[u8ChNum].xfer_len -= u16Len; + pdev->host.hc[u8ChNum].xfer_count += u16Len; + u32hnptxsts = READ_REG32(pdev->regs.GREGS->HNPTXSTS); + } +} +#define USBFS_HPTXSTS_PTXQTOP_CHNUM_POS (27U) +#define USBFS_HPTXSTS_PTXQTOP_CHNUM (0x78000000UL) +/** + * @brief processes periodic txFIFO empty interrupt + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_ptxfifoempty_isr(usb_core_instance *pdev) +{ + uint32_t u32hptxsts; + uint16_t u16LenWord; + uint16_t u16Len; + uint8_t u8ChNum; + + u32hptxsts = READ_REG32(pdev->regs.HREGS->HPTXSTS); + u8ChNum = (uint8_t)((u32hptxsts & USBFS_HPTXSTS_PTXQTOP_CHNUM) >> USBFS_HPTXSTS_PTXQTOP_CHNUM_POS); + u16LenWord = (uint16_t)((pdev->host.hc[u8ChNum].xfer_len + 3UL) / 4UL); + while ((((u32hptxsts & USBFS_HPTXSTS_PTXFSAVL)) > u16LenWord) && (pdev->host.hc[u8ChNum].xfer_len != 0U)) { + u16Len = (uint16_t)((u32hptxsts & USBFS_HPTXSTS_PTXFSAVL) * 4UL); + if (u16Len > pdev->host.hc[u8ChNum].xfer_len) { + u16Len = (uint16_t)pdev->host.hc[u8ChNum].xfer_len; + CLR_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTMSK_PTXFEM); + } + u16LenWord = (uint16_t)((pdev->host.hc[u8ChNum].xfer_len + 3UL) / 4UL); + usb_wrpkt(&pdev->regs, pdev->host.hc[u8ChNum].xfer_buff, u8ChNum, u16Len, pdev->basic_cfgs.dmaen); + pdev->host.hc[u8ChNum].xfer_buff += u16Len; + pdev->host.hc[u8ChNum].xfer_len -= u16Len; + pdev->host.hc[u8ChNum].xfer_count += u16Len; + u32hptxsts = READ_REG32(pdev->regs.HREGS->HPTXSTS); + } +} + +/** + * @brief This function determines which interrupt conditions have occurred + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_port_isr(usb_core_instance *pdev) +{ + uint32_t u32hprt; + uint32_t u32hprt_bk; + uint8_t u8fslspclksel; + uint32_t do_reset = 0UL; + uint8_t u8PortSpeed; + + u32hprt = READ_REG32(*pdev->regs.HPRT); + u32hprt_bk = u32hprt; + /* Clear the interrupt bits in GINTSTS */ + //tmp_hprt_bk.b.prtovrcurrchng = 0U; //todo don't have this bit + u32hprt_bk &= ~(USBFS_HPRT_PENA | USBFS_HPRT_PCDET | USBFS_HPRT_PENCHNG); + + /* check if a port connect have been detected */ + if ((u32hprt & USBFS_HPRT_PCDET) != 0UL) { + u32hprt_bk |= USBFS_HPRT_PCDET; + if (host_driver_getvbusdrivestate(pdev) != 0UL) { + pdev->host.is_dev_connect = 1U; + } + } + /* check if port enable or disable change */ + if ((u32hprt & USBFS_HPRT_PENCHNG) != 0UL) { + u32hprt_bk |= USBFS_HPRT_PENCHNG; + + if ((u32hprt & USBFS_HPRT_PENA) != 0UL) { + u8PortSpeed = (uint8_t)((u32hprt & USBFS_HPRT_PSPD) >> USBFS_HPRT_PSPD_POS); + if ((u8PortSpeed == PRTSPD_LOW_SPEED) || (u8PortSpeed == PRTSPD_FULL_SPEED)) { + u8fslspclksel = (uint8_t)(READ_REG32(pdev->regs.HREGS->HCFG) & USBFS_HCFG_FSLSPCS); + if (u8PortSpeed == PRTSPD_LOW_SPEED) { + if (u8fslspclksel != HCFG_6_MHZ) { + do_reset = 1U; + } + } else { + /* 1ms*(PHY clock frequency for FS/LS)-1 */ + WRITE_REG32(pdev->regs.HREGS->HFIR, 48000UL); + if (u8fslspclksel != HCFG_48_MHZ) { + usb_fslspclkselset(&pdev->regs, HCFG_48_MHZ); + do_reset = 1U; + } + } + } else { + do_reset = 1U; + } + } + } + + //todo don't have this bit + //if ((u32hprt & USBFS_HPRT_PRTOVRCURRCHNG) != 0UL) { + // u32hprt_bk |= USBFS_HPRT_PRTOVRCURRCHNG; + //} + + if (0UL != do_reset) { + usb_hprtrst(&pdev->regs); + } + WRITE_REG32(*pdev->regs.HPRT, u32hprt_bk); +} + +/** + * @brief processes the rxFIFO non-empty interrupt + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_rxflvl_isr(usb_core_instance *pdev) +{ + uint32_t u32grxsts; + uint32_t u32hctsiz; + uint32_t u32hcchar; + uint8_t u8chnum; + uint8_t *pu8Tmp; + uint16_t u16bcnt; + + CLR_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTSTS_RXFNE); + + u32grxsts = READ_REG32(pdev->regs.GREGS->GRXSTSP); + u8chnum = (uint8_t)(u32grxsts & USBFS_GRXSTSP_CHNUM_EPNUM); + u16bcnt = (uint16_t)((u32grxsts & USBFS_GRXSTSP_BCNT) >> USBFS_GRXSTSP_BCNT_POS); + u32hcchar = READ_REG32(pdev->regs.HC_REGS[u8chnum]->HCCHAR); + + switch ((u32grxsts & USBFS_GRXSTSP_PKTSTS) >> USBFS_GRXSTSP_PKTSTS_POS) { + case 2: /* IN dat packet received */ + pu8Tmp = pdev->host.hc[u8chnum].xfer_buff; + if ((u16bcnt > 0U) && (pu8Tmp != (void *)0U)) { + usb_rdpkt(&pdev->regs, pdev->host.hc[u8chnum].xfer_buff, u16bcnt); + pdev->host.hc[u8chnum].xfer_buff += u16bcnt; + pdev->host.hc[u8chnum].xfer_count += u16bcnt; + pdev->host.XferCnt[u8chnum] = pdev->host.hc[u8chnum].xfer_count; + + u32hctsiz = READ_REG32(pdev->regs.HC_REGS[u8chnum]->HCTSIZ); + if (((u32hctsiz & USBFS_HCTSIZ_PKTCNT) >> USBFS_HCTSIZ_PKTCNT_POS) > 0U) { + u32hcchar |= USBFS_HCCHAR_CHENA; + u32hcchar &= ~USBFS_HCCHAR_CHDIS; + WRITE_REG32(pdev->regs.HC_REGS[u8chnum]->HCCHAR, u32hcchar); + } + } + break; + + case 3: /* IN transfer completed(trigger an interrupt) */ + break; + case 5: /* Daat toggle error(trigger an interrupt) */ + break; + case 7: /* Channel halted(trigger an interrupt) */ + break; + default: + break; + } + + SET_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTSTS_RXFNE); +} + +/** + * @brief process the incomplete periodic transfer interrupt(incompIP) + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_incomplisoout_isr(usb_core_instance *pdev) +{ + SET_REG32_BIT(pdev->regs.HC_REGS[0]->HCCHAR, USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS); + WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_IPXFR_INCOMPISOOUT); +} + +/** + * @brief process the resume/remote wakeup detected interrupt(WkUpInt) + * @param [in] pdev device instance + * @retval None + */ +static void usb_host_wkupint_isr(usb_core_instance *pdev) +{ + uint32_t u32hprt; + u32hprt = usb_rdhprt(&pdev->regs); + u32hprt &= ~USBFS_HPRT_PRES; + WRITE_REG32(*pdev->regs.HPRT, u32hprt); +} + +/** + * @brief This function process all interrupt of USB in host mode + * @param [in] pdev device instance + * @retval None + */ +void usb_host_isr(usb_core_instance *pdev) +{ + uint32_t gintstsval; + if (0U != usb_getcurmod(&pdev->regs)) { + gintstsval = usb_getcoreintr(&pdev->regs); + if (0UL != (gintstsval & USBFS_GINTSTS_SOF)) { + usb_host_sof_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_RXFNE)) { + usb_host_rxflvl_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_NPTXFE)) { + usb_host_nptxfifoempty_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_PTXFE)) { + usb_host_ptxfifoempty_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_HCINT)) { + usb_host_hc_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_HPRTINT)) { + usb_host_port_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_DISCINT)) { + usb_host_disconn_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_IPXFR_INCOMPISOOUT)) { + usb_host_incomplisoout_isr(pdev); + } + if (0UL != (gintstsval & USBFS_GINTSTS_WKUINT)) { + usb_host_wkupint_isr(pdev); + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.h new file mode 100644 index 0000000000..4d3093fbd1 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.h @@ -0,0 +1,128 @@ +/** + ******************************************************************************* + * @file usb_host_int.h + * @brief Head file for usb_host_int.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_INT_H__ +#define __USB_HOST_INT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define HCINT_NYET (1UL << 6) + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @brief clear the interrupt flag bit + * @param [in] pdev device instance + * @param [in] ch_num the channel index + * @param [in] intbit the interrupt bit of the register HCINTn + * @retval None + */ +__STATIC_INLINE void usb_host_clrint(usb_core_instance *pdev, uint32_t ch_num, uint32_t intbit) +{ + WRITE_REG32(pdev->regs.HC_REGS[ch_num]->HCINT, intbit); +} + +/** + * @brief mask the interrupt of ChHltd + * @param [in] pdev device instance + * @param [in] ch_num channel index of the host application + * @retval None + */ +__STATIC_INLINE void usb_host_int_mskchhltd(usb_core_instance *pdev, uint32_t ch_num) +{ + CLR_REG32_BIT(pdev->regs.HC_REGS[ch_num]->HCINTMSK, USBFS_HCINTMSK_CHHM); +} + +/** + * @brief unmask the interrupt of ChHltd + * @param [in] pdev device instance + * @param [in] ch_num channel index of the host application + * @retval None + */ +__STATIC_INLINE void usb_host_int_unmskchhltd(usb_core_instance *pdev, uint32_t ch_num) +{ + SET_REG32_BIT(pdev->regs.HC_REGS[ch_num]->HCINTMSK, USBFS_HCINTMSK_CHHM); +} + +/** + * @brief mask the interrupt of ACK + * @param [in] pdev device instance + * @param [in] ch_num channel index of the host application + * @retval None + */ +__STATIC_INLINE void usb_host_int_mskack(usb_core_instance *pdev, uint32_t ch_num) +{ + CLR_REG32_BIT(pdev->regs.HC_REGS[ch_num]->HCINTMSK, USBFS_HCINTMSK_ACKM); +} + +/** + * @brief unmask the interrupt of ACK + * @param [in] pdev device instance + * @param [in] ch_num channel index of the host application + * @retval None + */ +__STATIC_INLINE void usb_host_int_unmskack(usb_core_instance *pdev, uint32_t ch_num) +{ + SET_REG32_BIT(pdev->regs.HC_REGS[ch_num]->HCINTMSK, USBFS_HCINTMSK_ACKM); +} + +void usb_host_isr(usb_core_instance *pdev); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_INT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + + diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.c b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.c new file mode 100644 index 0000000000..e24712a2f4 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.c @@ -0,0 +1,482 @@ +/** + ******************************************************************************* + * @file usb_host_stdreq.c + * @brief Standard requests for device enumeration + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_stdreq.h" +#include "usb_host_ctrltrans.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes declared in the last part. + ******************************************************************************/ +void usb_host_parsedevdesc(usb_host_devdesc_typedef *, uint8_t *buf, uint16_t length); + +void usb_host_parsecfgdesc(usb_host_cfgdesc_typedef *cfg_desc, + usb_host_itfdesc_typedef *itf_desc, + USB_HOST_EPDesc_TypeDef ep_desc[][USBH_MAX_NUM_ENDPOINTS], + uint8_t *buf, + uint16_t length); +void usb_host_parseitfdesc(usb_host_itfdesc_typedef *if_descriptor, uint8_t *buf); +void usb_host_parseepdesc(USB_HOST_EPDesc_TypeDef *ep_descriptor, uint8_t *buf); +void usb_host_parsestringdesc(uint8_t *psrc, uint8_t *pdest, uint16_t length); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @brief issue a command descriptor from the connected device. parses the + * descriptor and updates the status once the response has been received. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] req_type type of the descriptor + * @param [in] value_idx wValue of setup for the request to get Descriptr + * @param [in] buff: buffer to save the the descriptor + * @param [in] length the length of the description. + * @retval status + */ +HOST_STATUS usb_host_getdesc(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t req_type, + uint16_t value_idx, + uint8_t *buff, + uint16_t length) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_D2H | req_type; + phost->ctrlparam.setup.b.bRequest = USB_REQ_GET_DESCRIPTOR; + phost->ctrlparam.setup.b.wValue.w = value_idx; + + if ((value_idx & 0xff00U) == USB_DESC_STRING) { + phost->ctrlparam.setup.b.wIndex.w = 0x0409U; + } else { + phost->ctrlparam.setup.b.wIndex.w = 0U; + } + phost->ctrlparam.setup.b.wLength.w = length; + return usb_host_ctrlreq(pdev, phost, buff, length); +} + +/** + * @brief Issue command to the device to get the device discription. it parses + * the device descriptor and updates the status once getting the device + * description. + * @param [in] pdev device instance + * @param [in] phost host state set. + * @param [in] length the length of the description. + * @retval status + */ +HOST_STATUS usb_host_getdevdesc(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t length) +{ + HOST_STATUS status; + status = usb_host_getdesc(pdev, + phost, + (uint8_t)(USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD), + USB_DESC_DEVICE, + pdev->host.Rx_Buffer, + (uint16_t)length); + if (status == HSTATUS_OK) { + /* Commands successfully sent and Response Received */ + usb_host_parsedevdesc(&phost->device_prop.devdesc, pdev->host.Rx_Buffer, (uint16_t)length); + } + return status; +} + +/** + * @brief Issue a command to get the configuration description from the device + * connected, parse the configuration descriptor and update the + * status once the response has been received. + * @param [in] pdev device instance + * @param [in] phost host state set. + * @param [in] length the length of the description. + * @retval status + */ +HOST_STATUS usb_host_getcfgdesc(usb_core_instance *pdev, + USBH_HOST *phost, + uint16_t length) +{ + HOST_STATUS status; + + status = usb_host_getdesc(pdev, + phost, + USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, + USB_DESC_CONFIGURATION, + pdev->host.Rx_Buffer, + length); + if (status == HSTATUS_OK) { + usb_host_parsecfgdesc(&phost->device_prop.devcfgdesc, + phost->device_prop.devitfdesc, + phost->device_prop.devepdesc, + pdev->host.Rx_Buffer, + length); + } + return status; +} + +/** + * @brief Issues string Descriptor command to the device. Once the response + * received, it parses the string descriptor and updates the status. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] string_index the index for the string + * @param [in] buff buffer to save the the string descriptor + * @param [in] length the length of the description. + * @retval status + */ +HOST_STATUS usb_host_getstringdesc(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t string_index, + uint8_t *buff, + uint16_t length) +{ + HOST_STATUS status; + status = usb_host_getdesc(pdev, + phost, + USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, + USB_DESC_STRING | string_index, + pdev->host.Rx_Buffer, + length); + if (status == HSTATUS_OK) { + usb_host_parsestringdesc(pdev->host.Rx_Buffer, buff, length); + } + return status; +} + +/** + * @brief issue a command to set the address for the device that have connected. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] DeviceAddress Device address which would be set to the conected device + * @retval status + */ +HOST_STATUS usb_host_setdevaddr(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t DeviceAddress) +{ + /* + Refer to table9-3 of 9.4 + */ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD; + phost->ctrlparam.setup.b.bRequest = USB_REQ_SET_ADDRESS; + phost->ctrlparam.setup.b.wValue.w = (uint16_t)DeviceAddress; + phost->ctrlparam.setup.b.wIndex.w = 0U; + phost->ctrlparam.setup.b.wLength.w = 0U; + + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief issue a command to set the configuration to the connected device. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] cfg_idx value for the configuration setup + * @retval status + */ +HOST_STATUS usb_host_setconfig(usb_core_instance *pdev, + USBH_HOST *phost, + uint16_t cfg_idx) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD; + phost->ctrlparam.setup.b.bRequest = USB_REQ_SET_CONFIGURATION; + phost->ctrlparam.setup.b.wValue.w = cfg_idx; + phost->ctrlparam.setup.b.wIndex.w = 0U; + phost->ctrlparam.setup.b.wLength.w = 0U; + + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief issue a command to set the Interface value to the connected device + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] ep_num the index of the endpoint + * @param [in] altSetting the value for the setup of set interface + * @retval status + */ +HOST_STATUS usb_host_setintf(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t ep_num, + uint8_t altSetting) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_STANDARD; + + phost->ctrlparam.setup.b.bRequest = USB_REQ_SET_INTERFACE; + phost->ctrlparam.setup.b.wValue.w = altSetting; + phost->ctrlparam.setup.b.wIndex.w = ep_num; + phost->ctrlparam.setup.b.wLength.w = 0U; + + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief issue a comman to clear or disable a specific feature in the device. + * @param [in] pdev device instance + * @param [in] phost host state set + * @param [in] ep_num index of the endpoint + * @param [in] hc_num host channel index + * @retval status + */ +HOST_STATUS usb_host_clrfeature(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t ep_num, + uint8_t hc_num) +{ + phost->ctrlparam.setup.b.bmRequestType = USB_H2D | + USB_REQ_RECIPIENT_ENDPOINT | + USB_REQ_TYPE_STANDARD; + + phost->ctrlparam.setup.b.bRequest = USB_REQ_CLEAR_FEATURE; + phost->ctrlparam.setup.b.wValue.w = FEATURE_SELECTOR_ENDPOINT; + phost->ctrlparam.setup.b.wIndex.w = ep_num; + phost->ctrlparam.setup.b.wLength.w = 0U; + + if ((ep_num & USB_REQ_DIR_MASK) == USB_D2H) { + pdev->host.hc[hc_num].in_toggle = 0U; + } else { + pdev->host.hc[hc_num].out_toggle = 0U; + } + + return usb_host_ctrlreq(pdev, phost, NULL, 0U); +} + +/** + * @brief parse the data frame of device descriptor + * @param [in] dev_desc the structure of the device descriptor + * @param [in] buf buffer where the source descriptor is save + * @param [in] length Length of the descriptor in byte + * @retval None + */ +void usb_host_parsedevdesc(usb_host_devdesc_typedef *dev_desc, + uint8_t *buf, + uint16_t length) +{ + dev_desc->bLength = *(uint8_t *)(buf + 0U); + dev_desc->bDescriptorType = *(uint8_t *)(buf + 1U); + dev_desc->bcdUSB = SMALL_END(buf + 2U); + dev_desc->bDeviceClass = *(uint8_t *)(buf + 4U); + dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5U); + dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6U); + dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7U); + + if (length > (uint16_t)8) { + dev_desc->idVendor = SMALL_END(buf + 8U); + dev_desc->idProduct = SMALL_END(buf + 10U); + dev_desc->bcdDevice = SMALL_END(buf + 12U); + dev_desc->iManufacturer = *(uint8_t *)(buf + 14U); + dev_desc->iProduct = *(uint8_t *)(buf + 15U); + dev_desc->iSerialNumber = *(uint8_t *)(buf + 16U); + dev_desc->bNumConfigurations = *(uint8_t *)(buf + 17U); + } +} + +/** + * @brief This function Parses the configuration descriptor from the received buffer + * @param [in] cfg_desc the structure of configuration descriptor + * @param [in] itf_desc the structure of interface descriptor + * @param [in] ep_desc the structure of endpoint descriptor + * @param [in] buf buffer where the source descriptor is save + * @param [in] length Length of the descriptor in byte + * @retval None + */ +void usb_host_parsecfgdesc(usb_host_cfgdesc_typedef *cfg_desc, + usb_host_itfdesc_typedef *itf_desc, + USB_HOST_EPDesc_TypeDef ep_desc[][USBH_MAX_NUM_ENDPOINTS], + uint8_t *buf, + uint16_t length) +{ + usb_host_itfdesc_typedef *pif ; + usb_host_itfdesc_typedef temp_pif ; + USB_HOST_EPDesc_TypeDef *pep; + USB_HOST_DescHeader_TypeDef *pdesc = (USB_HOST_DescHeader_TypeDef *)buf; + uint16_t ptr; + int8_t if_ix; + int8_t ep_ix; + static uint16_t prev_ep_size = 0U; + static uint8_t prev_itf = 0U; + + /* Parse the configuration descriptor */ + cfg_desc->bLength = *(uint8_t *)(buf + 0U); + cfg_desc->bDescriptorType = *(uint8_t *)(buf + 1U); + cfg_desc->wTotalLength = SMALL_END(buf + 2U); + cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4U); + cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5U); + cfg_desc->iConfiguration = *(uint8_t *)(buf + 6U); + cfg_desc->bmAttributes = *(uint8_t *)(buf + 7U); + cfg_desc->bMaxPower = *(uint8_t *)(buf + 8U); + + if (length > USB_CONFIGURATION_DESC_SIZE) { + ptr = USB_LEN_CFG_DESC; + + if (cfg_desc->bNumInterfaces <= USBH_MAX_NUM_INTERFACES) { + + while (ptr < cfg_desc->wTotalLength) { + pdesc = usb_host_getnextdesc((uint8_t *)pdesc, &ptr); + if (pdesc->bDescriptorType == USB_DESC_TYPE_INTERFACE) { + if_ix = (int8_t) * (((uint8_t *)pdesc) + 2U); + pif = &itf_desc[if_ix]; + + if ((*((uint8_t *)pdesc + 3U)) < 3U) { + usb_host_parseitfdesc(&temp_pif, (uint8_t *)pdesc); + ep_ix = (int8_t)0; + + /* Parse Ep descriptors relative to the current interface */ + if (temp_pif.bNumEndpoints <= USBH_MAX_NUM_ENDPOINTS) { + while (ep_ix < (int8_t)temp_pif.bNumEndpoints) { + pdesc = usb_host_getnextdesc((void *)pdesc, &ptr); + if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) { + pep = &ep_desc[if_ix][ep_ix]; + + if (prev_itf != (uint8_t)if_ix) { + prev_itf = (uint8_t)if_ix; + usb_host_parseitfdesc(pif, (uint8_t *)&temp_pif); + } else { + if (prev_ep_size > SMALL_END((uint8_t *)pdesc + 4U)) { + break; + } else { + usb_host_parseitfdesc(pif, (uint8_t *)&temp_pif); + } + } + usb_host_parseepdesc(pep, (uint8_t *)pdesc); + prev_ep_size = SMALL_END((uint8_t *)pdesc + 4U); + ep_ix++; + } + } + } + } + } + } + } + prev_ep_size = 0U; + prev_itf = 0U; + } +} + +/** + * @brief This function parses the interface descriptor from the received buffer. + * @param [in] if_descriptor structure of interface descriptor + * @param [in] buf buffer where the source descriptor is save + * @retval None + */ +void usb_host_parseitfdesc(usb_host_itfdesc_typedef *if_descriptor, uint8_t *buf) +{ + if_descriptor->bLength = *(uint8_t *)(buf + 0U); + if_descriptor->bDescriptorType = *(uint8_t *)(buf + 1U); + if_descriptor->bInterfaceNumber = *(uint8_t *)(buf + 2U); + if_descriptor->bAlternateSetting = *(uint8_t *)(buf + 3U); + if_descriptor->bNumEndpoints = *(uint8_t *)(buf + 4U); + if_descriptor->bInterfaceClass = *(uint8_t *)(buf + 5U); + if_descriptor->bInterfaceSubClass = *(uint8_t *)(buf + 6U); + if_descriptor->bInterfaceProtocol = *(uint8_t *)(buf + 7U); + if_descriptor->iInterface = *(uint8_t *)(buf + 8U); +} + +/** + * @brief This function parses the endpoint descriptor from the received buffer. + * @param [in] ep_descriptor the structure of endpoint descriptor. + * @param [in] buf buffer where the source descriptor is save + * @retval None + */ +void usb_host_parseepdesc(USB_HOST_EPDesc_TypeDef *ep_descriptor, uint8_t *buf) +{ + ep_descriptor->bLength = *(uint8_t *)(buf + 0U); + ep_descriptor->bDescriptorType = *(uint8_t *)(buf + 1U); + ep_descriptor->bEndpointAddress = *(uint8_t *)(buf + 2U); + ep_descriptor->bmAttributes = *(uint8_t *)(buf + 3U); + ep_descriptor->wMaxPacketSize = SMALL_END(buf + 4U); + ep_descriptor->bInterval = *(uint8_t *)(buf + 6U); +} + +/** + * @brief This function parses the string descriptor from the received buffer. + * @param [in] psrc source data + * @param [in] pdest destination data + * @param [in] length Length of the descriptor in byte + * @retval None + */ +void usb_host_parsestringdesc(uint8_t *psrc, uint8_t *pdest, uint16_t length) +{ + uint16_t strlength; + uint16_t tmp_idx; + /* + The describ of String Desctipor refers to 9.6.8 + psrc[0] = bLength bLength = N+2 + psrc[1] = bDescriptorType STRING Descriptor Type + ... + */ + if (psrc[1] == USB_DESC_TYPE_STRING) { + strlength = ((((uint16_t)psrc[0]) - 2U) <= length) ? (((uint16_t)psrc[0]) - 2U) : length; + psrc += 2U; + for (tmp_idx = 0U; tmp_idx < strlength; tmp_idx += 2U) { + *pdest = psrc[tmp_idx]; + pdest++; + } + *pdest = 0U; + } +} + +/** + * @brief This function gets the header of next descriptor. + * @param [in] pbuf buffer where the configuration descriptor is contained. + * @param [in] ptr data popinter inside the cfg descriptor + * @retval header of next descriptor + */ +USB_HOST_DescHeader_TypeDef *usb_host_getnextdesc(uint8_t *pbuf, uint16_t *ptr) +{ + USB_HOST_DescHeader_TypeDef *pnext; + + *ptr += ((USB_HOST_DescHeader_TypeDef *)pbuf)->bLength; + pnext = (USB_HOST_DescHeader_TypeDef *)((uint8_t *)pbuf + ((USB_HOST_DescHeader_TypeDef *)pbuf)->bLength); + + return (pnext); +} + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.h new file mode 100644 index 0000000000..8046d96a87 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.h @@ -0,0 +1,107 @@ +/** + ******************************************************************************* + * @file usb_host_stdreq.h + * @brief Header file for usb_host_stdreq.c + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_HOST_STDREQ_H__ +#define __USB_HOST_STDREQ_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "usb_host_def.h" + +/** + * @addtogroup LL_USB_LIB + * @{ + */ + +/** + * @addtogroup LL_USB_HOST_CORE + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/* USBH_STDREQ_Exported_Defines */ +/* Standard Feature Selector for clear feature command */ +#define FEATURE_SELECTOR_ENDPOINT (0x00U) +#define FEATURE_SELECTOR_DEVICE (0x01U) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +extern HOST_STATUS usb_host_getdesc(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t req_type, + uint16_t value_idx, + uint8_t *buff, + uint16_t length); + +extern HOST_STATUS usb_host_getdevdesc(usb_core_instance *pdev, USBH_HOST *phost, uint8_t length); + +HOST_STATUS usb_host_getstringdesc(usb_core_instance *pdev, + USBH_HOST *phost, + uint8_t string_index, + uint8_t *buff, + uint16_t length); + +extern HOST_STATUS usb_host_setconfig(usb_core_instance *pdev, USBH_HOST *phost, uint16_t cfg_idx); + +extern HOST_STATUS usb_host_getcfgdesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length); + +extern HOST_STATUS usb_host_setdevaddr(usb_core_instance *pdev, USBH_HOST *phost, uint8_t DeviceAddress); + +extern HOST_STATUS usb_host_clrfeature(usb_core_instance *pdev, USBH_HOST *phost, uint8_t ep_num, uint8_t hc_num); + +extern HOST_STATUS usb_host_setintf(usb_core_instance *pdev, USBH_HOST *phost, uint8_t ep_num, uint8_t altSetting); + +extern USB_HOST_DescHeader_TypeDef *usb_host_getnextdesc(uint8_t *pbuf, uint16_t *ptr); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_HOST_STDREQ_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_lib.h b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_lib.h new file mode 100644 index 0000000000..dc2a0cbc82 --- /dev/null +++ b/bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_lib.h @@ -0,0 +1,199 @@ +/** + ******************************************************************************* + * @file usb_lib.h + * @brief Header of the Core Layer Driver + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __USB_LIB_H__ +#define __USB_LIB_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_usb.h" +#include "hc32_ll.h" + +/** + * @addtogroup LL_USB_LIB LL USB Lib + * @{ + */ + +/** + * @addtogroup LL_USB_LIB_DEF LL USB Lib Define + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#define MAX_DATA_LENGTH (0x200U) + + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/* status of the host channel */ +typedef enum { + HOST_CH_IDLE = 0U, + HOST_CH_XFERCOMPL, + HOST_CH_CHHLTD, + HOST_CH_NAK, + HOST_CH_NYET, + HOST_CH_STALL, + HOST_CH_XACTERR, + HOST_CH_BBLERR, + HOST_CH_DATATGLERR, + HOST_CH_AHBERR, + HOST_CH_FRMOVRUN, + HOST_CH_BNAINTR, + HOST_CH_XCS_XACT_ERR, + HOST_CH_DESC_LST_ROLLINTR +} HOST_CH_STATUS; + +typedef enum { + HOST_CH_XFER_IDLE = 0U, + HOST_CH_XFER_DONE, + HOST_CH_XFER_UNREADY, + HOST_CH_XFER_ERROR, + HOST_CH_XFER_STALL +} HOST_CH_XFER_STATE; + +typedef enum { + CTRL_START = 0U, + CTRL_XFRC, + CTRL_HALTED, + CTRL_NAK, + CTRL_STALL, + CTRL_XACTERR, + CTRL_BBLERR, + CTRL_DATATGLERR, + CTRL_FAIL +} CTRL_HANDLE_STATUS; + +typedef struct { + uint8_t bmRequest; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ; + +typedef struct { + uint8_t *(*get_dev_desc)(uint16_t *length); + uint8_t *(*get_dev_langiddesc)(uint16_t *length); + uint8_t *(*get_dev_manufacturerstr)(uint16_t *length); + uint8_t *(*get_dev_productstr)(uint16_t *length); + uint8_t *(*get_dev_serialstr)(uint16_t *length); + uint8_t *(*get_dev_configstr)(uint16_t *length); + uint8_t *(*get_dev_interfacestr)(uint16_t *length); +} usb_dev_desc_func; + +typedef struct { + void (*class_init)(void *pdev); + void (*class_deinit)(void *pdev); + uint8_t (*ep0_setup)(void *pdev, USB_SETUP_REQ *req); + void (*ep0_datain)(void *pdev); + void (*ep0_dataout)(void *pdev); + uint8_t *(*class_getconfigdesc)(uint16_t *length); + uint8_t (*class_sof)(void *pdev); + void (*class_datain)(void *pdev, uint8_t epnum); + void (*class_dataout)(void *pdev, uint8_t epnum); + void (*class_syn_in_incomplt)(void *pdev); + void (*class_syn_out_incomplt)(void *pdev); +} usb_dev_class_func; + +typedef struct { + void (*user_init)(void); + void (*user_devrst)(void); + void (*user_devconfig)(void); + void (*user_devsusp)(void); + void (*user_devresume)(void); + void (*user_devconn)(void); + void (*user_devdisconn)(void); +} usb_dev_user_func; + +typedef struct { + __IO uint8_t device_config; + __IO uint8_t device_address; + __IO uint8_t device_state; + __IO uint8_t device_old_status; + __IO uint8_t device_cur_status; + __IO uint8_t connection_status; + __IO uint8_t device_remote_wakeup; + __IO uint8_t test_mode; + USB_DEV_EP in_ep[USB_MAX_TX_FIFOS]; + USB_DEV_EP out_ep[USB_MAX_TX_FIFOS]; + uint8_t setup_pkt_buf[24]; + usb_dev_class_func *class_callback; + usb_dev_user_func *user_callback; + usb_dev_desc_func *desc_callback; +} USB_DEV_PARAM; + +typedef struct { + uint16_t channel[USB_MAX_TX_FIFOS]; + USB_HOST_CH hc[USB_MAX_TX_FIFOS]; + __IO uint32_t is_dev_connect; + uint8_t Rx_Buffer[MAX_DATA_LENGTH]; + __IO uint32_t ErrCnt[USB_MAX_TX_FIFOS]; + __IO uint32_t XferCnt[USB_MAX_TX_FIFOS]; + __IO HOST_CH_STATUS HC_Status[USB_MAX_TX_FIFOS]; + __IO HOST_CH_XFER_STATE URB_State[USB_MAX_TX_FIFOS]; +} USB_HOST_PARAM; + +typedef struct { + USB_CORE_BASIC_CFGS basic_cfgs; + LL_USB_TypeDef regs; +#ifdef USE_DEVICE_MODE + USB_DEV_PARAM dev; +#endif +#ifdef USE_HOST_MODE + USB_HOST_PARAM host; +#endif +} usb_core_instance; + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_LIB_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/

F(oW1KL*$FKD;^h7@tDnJ&f9X#PQ&Ah)UO-cqg5OH*uRRa5d3V|sd+f>sM&9&|(% z`8r_r@npyDbfE>i{Z0lJt}7 z4PyB4xR23`Gj}(*chU`w$PL}|K{XT}PZBz8wJqD>-UTCuy=}Jz+lHiUN-}*SA>*$n z@uf3fJ}*`~tCqI^@gtX5`{B?@V zGST~Ynlu{jF05$a?z;fbsl14Jb<_vE0LOt9&WD@A2?y(c*aG>%l>BE#7C$InXp9-& zxHi9PSSb-M35toHW6IgJUJl(r^q1l3Cw)!i4jX zESstx;!U1`nBQ1!m&g5I?r+e<&|ApS$sfN$g;{)a{a4tZ)6oio>KiJd3s4+gyQ zxOiD36aIHGR4Gpkji#&JTU3Mi!vWKb{*&r$2{iGi-#9jeS$9`FrvfK91$We6yyU4jo1nxd2GVIB^1K0PnRZba_<3v=h#K{s3WIvai#~DJ_tkWg@+5OXV}kH#tk9pes)lI-vQaR+j7tRBk0O)A8a;hvgI|`jVRqCb9!`xn|SstQ0v}i*Bk&FArs$^Evfeti$wg&SAQ1+t5scu z#TUL|zAMoYxt}wCh|B3{p6NZpQC+MWEEpFiYlyr8o>OIcKgp9Q9vW}3@#OnEvrx~( z2RhOQoHF#Z5%FNps9_`~cl(^DyIM{hM?mEkj)jUuQ)hb`R*W;X3)ICq<~UN^XZ0|e zH{UgAW&VXh1lo3t|IWn@v>c`qfB0R9qJs-@K3kpH8FnHoJ2#pJx{n{9T<`AgjV#Jm z@y~&$vt3I(+yr=iZ|tME-*tR3cxLZjV*4X4iTt zAg`mn<{VpWwK?DNvv$A>Z#}$&?5D`9ynM*G*W}9n-!ERMZh&2B9hSu1-<>+9kA2?q z8r;l`UcWXt$r}*(T0IRp>77+$cxDOlRw*}POhM`v-`r5PSABjkod)Q9n@QF~p<@4` zVz6q3E$hvyaW2~EOY^4DBeuleF8bUl?!swWdbKD-!O~YFlLm5c#nYZw%_$~M&{-yS zDOgELq)v%r2WDL>K0$*LYscy8+kLn;^@eWL?tm4a+5GF83=*Y`=wRl5MK~@xHy}dB z=Xs?%`zO6y=YMz!l~_D`sY9eB78y!MQvoO~jNOCFXJfdHxG(8I^*9*q?#opMb^7>+ zQVSGm-{@J@+QW<%0+oRBo`vX;HQZa-4&?{a&W)Gxr)t&Roc8X#G#3&6g_G~w?v{5< zHMg~QJhOLhm3*H~CZkJw13=H z<|r_^6n@z`RYXC^6BJ@u1rvL!FmoXmSX;Psvg10)4EuppGxt}@in4a2LkvJ>?cv$> z+4$m_!N*`XCc|Z92ZO`Xlf=VuPNkraL{Ry=M93N@e-e5bjZZvY``(?fuk2y0&{vIQ#VxKnzYr2@@s6_Y53+#Rgm-2i5?d95DZ*E z?Q^zLy1&?j`-0nH3+iB0Kcha{#leSN8Q>{!3CZ>@k+gPmF{smLYFkB*6JuINblJWfkI>mS(JTCqVU!i6RLy;G^e1hXe zyT!z~WWrUrWq1JMMFda8YZUIwxmP>Bte5a@hfBHxKG~QR;`f)>urf!GN@1u`k zGg4OmqIF+~YdQ!bz@y2(Lvg~cyPOp?Pr}Yhb?ybSIrse)JP$I^2`^{Sssz zYu#I-V1&ar^I6y`F+yi$wh(&3iuJlOF}59DZ@b&-NYOdZy5=_O_0=Gtisw^|>R`*N zjT&Up_fe&eHQ33%uXsTxvArMv1B1A*lh3Op4{eE;nn!^Gb`@U(7+PZ4x8>URfo}_H zVwgL8BH7ckZS(F-xY8eMuQG8}Y(Zuu8uSmJYOZ_PR-H`iipN5gknb`zc^|wXl=ZlS z%Z>`>n5kxlUm3?g_m0w;tn-km9yOo6?Bu!A=zLv=j%*z4*l6uY&&$ncsYN+8^u2#j zd>XuYQ03zo$@JmNPBE*SzJ01T{2RlN8bM$x49l##9b2#Rp8fmIVyRfu!Fci#MWQ;W z%B+VcwY>TQyS`W-I(*rpF9rSBe zh@;e;O9e^feih>7_`X1(m+Ry5hmBg*Bt8J!->Wf_Ys1}WB4$_j*R!Fowa>_p^=EwK zz$2>2GGtY>Sw~-Qf2Mw}=_F}&`Pvg9AyUEgFb&7j%Wm(oRE!6hVrSZ@K+|zYZ{h<6fYn_1<%;*H^nCgHr>3d*2UktY)_;%B&~j#{5w2zg z4vf!c^+Mq_at6`e@Z)qZuQWes*~)esXtXXMJ_@<~Ldc=|DWlXM`_eJK|_TC}LhjF91~=Yby>Cf}y%>M*D$b&KVs$tle6g&aw-<9~q)x zWte&D*lckZ&VEkq^3FGxA*E2%5FMr3}MYbtquix3Z*b8pj`~XyHM^Jo@|7je)-b7S2-Se)?uZZuu7I8ckq_&tTPTxGCr1V$?bez0 zwwK_GnUzE`eC}X&jMJPKq~K81<=2@0>MCTsLh}j;lyX=!*&J^6ADSL1b_^Cj9i7-O=!@E&O5-i1LV%pzbh?=2lZ9qj z6*GQH$D;-shBF8MR6Ft{kKHo$+FxTt`-d%9AfNl-g8g5B^3DV6qJ!qsRBd{qrybf6 zb=D7Sl{;S)s53h1nR47fFW4p}w-i}5(Fc)x{I>JoS%6cf4orPkFEP5uL-pRqiD!Eb zK_C;l^1BKR!U7zl=@mH;gMrAZ5BpkGL|GTOs~JypFBEBmRjvLP(S`PDDrpj58!nw^RMYueBGm#m#kvclTi zsJ|8ghDD#mJliKrz|^)^0$PncSC=i3mxx<|Xp42n-|dbKJTLBp3x8%z1Byqk0}Ke| zwxEFiaw%e@SxBOAV9ZHwZ6|#Sf5Cg;M~P`yUAnS3h6f`e0jZ_8pp49imE=;~=N0Fk zOKi|Cnf>d=r^8~e`7JB!HbRqcEjhPss;R8dr$q6NK}H_SaFG9zyd+ei2| zEI1t7i`quc(|xuTUxh1Rx~+zg$*lf|X46jcb96=;?6q@m7ly~ zXgGm!Z%+=p-K4GZVZ@9_!@GkN&-6zo^aiPs;)$w+dB03sj+-_>$Mfu}V~t<9S@nF2 zzb|Zu{~J6*Fl|YA$`riP`$E_>x}%GS$1C+pm|#;fJG`!Sx^AcIsOc5cd*HM3p1!l5 zZj;wq?ZL;{egh&YY;D7tFpX5FxJwEF3bBfRY2R>M>4HQ2()4QBC_}0~cj{vvuKa5$^ zWx{EC5i8RM6&fA`ZlZ}VGc#*7V_SV3mH(m-0esN%Y9+B1#tB=-rWiQ(3s67QT$wb3rte~|LKEMVysRfgBX*mGr8>Rdk{RF*Hg@I|2} zpR#`5RSK013N;lSDujaQQNM0$kxekkymztECw^<(KJ3qS6gWVMoUdX(e*Ep~wrU^X zd4(mK_T<$uk4M9^W$7&j!&$97d~s(AAsiu9rsI`cLk+@Hj z$I#SSM-6&}35@)FsI+~lQ)Ql3>}0&6Zd65)r1Y>$g2hzT=_h;o$T2N?4lsDv3@)-n z6>gl1oFQw59lHi~Vt;=%OU!k!S7CU~Gv@ms?=UFxHYkoM^GO|jp6Od`yXLwfM_MGi zR%!@kvu`V`>|;>s)MO2YiSBOK_S{KXoT_~n5oPp<{9!B9+R{x6N4TY`cbx`Ij@f9f znZYf{wg-sS)YRz?mdVBt?*2;Rs)eHpkLAEA13c;SY*;(Db+vXc@z;vtgJ3VQjjI+f zW+&vab~^xSK@I~c#oo9-!X4nHv3n-#d;m$m5jK}#5k(|V^I$`8lV9FbyZ{HW+8R(w z0RO2c)#=oUO6B8j#vfRX z;;rxOXK}&`^c02`*-&W>_=i8cXK4m|#vV&+p;IWnRiQ3xQoE9sDuAWgB`>=_Gpvca zLJci8-8_ESh6Ku)x2|}K{H|H^mlm}5V9U#H8YiK(iXG3g!E+3!O04vJb)4$-MF(b4 zCJoMmYz*tH{6r0Ox2+ko6o_bPa~x;rjd4^tyY-UMN%-dfy)gTg{2`zx|2OqoOLhc@ zXcNe!gOXATx1^J5dFxOycWkA&Gk)CNTw8{aRmA#7O8V2;%))OEth-Xbc>1z{ks|7m zyul6++NEq{rmWtDD6Rh96IvqT&x9WWQrW|zQ5v$8^a)}htC0No2Gj2-zoUuXc&QUK z%@29|Gmkp#d%->A^&}XWni21$3H$W~j-P z2!ZC#DO88;mml}y)L)vap;b$rHDPi_K%*g*_>Ml}Pfzg1!16h8%4?4u8nNppVGDG> zKlgut7uIGNwb5`z&1p|=M~WGq1%B_JV_;?RVkGzq;{t23Bo=)fPhsq*yR3MmSJ4;J zdBYcqSXSIoBO#R#zq>%jbH9u?&vDB9V&9#RbUHd1;-tLm-52dGfA73M-j^jtXTx6fxKr!YD(LK)UZ zKR@*cwHxte3yg8HRSXB)7@Hn0-_-k8n1Mc+X4K^5D>WwCr(*WAGc&Rzet73Pd^`0$ zGYttT5P9@OL&MH=7b}TfaHqxewk^K95c&Dg)cuh(0!p{-)B0bvE&qo>IdsU6Isgmtlr|;ptx6V`V3@cY0MHO$Isc$BH0z2R-p+IrTROBKI_oOQsdg-J~SaT z?pQs?oar6t;b_CltB^3{!YuL}v|wLyVSL)K$ZI(y+Kr;NJy8aobqBCL~K67%@YgTi|#G8{%_G7xdw0Vy#OS(;Z($wFiSqF(W9b zm{0lVLCi>c$S``0R2*eRI$h|z;?XkL2daaR32TV>=mgR%h%`Dla?JnqISj({qguT6 z-t3Rnm*6S@x_;rM~n-=7oDy%#Iz5ykf_{iP9Yc%yqpd`@GKL0zY9-9ewU1pT_2 z?5`S(UqeBNPD;w(^X*2>#OW`FR)bu=n4i$;_LXW(@i43$59Xc*6`D4Ce3mQh6#Qlr z`Iq4uy787K%<>+6q`YvjDYdq;nFY-~KBI?tsBA#e!pcubepp$~-zMl0V@^L7V#?#% z6wD5;zrGMF?bS+ZPe!|_CQAnq9ud$o(Qtp~{yza;mJ56ZubV`w=L&_%O{a`}Bo+zd zO(q#R{+sX{k5vu(tIx8O7si10& zBS%}F4*REiYQ>8*_1t^zPg+3M1dpGYfLMDwRhs?^dS}wM+SF%M$_dIebBtwr@j%Ak zt@EUpETkFkjBoEgY#)o~5+lb)4lzu3PX)`@1Z9{D*;+=%REgZh&&b zX6~X>PY(@v)5PCi!03I`U_=s}WSkliX}B0F@+8s96S%M*e9=(HW5Rl@R<_d9!}O83 zpQ!56`rNwLF@G36>?{l3vPQZg)VU#Hy#7Gz`CBU9TpM-WB;uPerd0!h-%Ow`^Jij` zIiE$vaV-X2VAM^1O^%OEOjRV7JA^6@wls^ujfw)&QA6Cfm0mtnlDR>{=}m9(iSC=z zV~@3aLE5KF3zSFCgJk7qXT(z#I?}4_--&4YOx7shK;%rqZTdYm<2hNhrP{G>*=)Ac z{`BtH=MZ5oE!2ZF=Gbn+RFnX(rnl6lAB1WZrJf)kKH(3rB-jmfWotRenp5?Ib_D*M z?P@D!v(uR@-_VBWM$eR5t<k<1L1y3_uts^-qP>NMLLBVV8tAhPqUtwXDa6Olf>^D0a;cJ|NS)7>RRpg;kivUmUq+T{-c0fC;M$Qd&@1T z`LoA6b#sQNryqgWXAkPq-y;r!Y4FDPfxSk#_uqNdX@$gJtf<ET*g8Xz&3e1 zn~YFh4P7ny{7Zg7ip{iTO*Kpp!t=JbkuG{8T32izWv8q5=x5R-hkF{ItRT=7SF3m0 z$)}VF1P%B@0$j1c8eN?Wdvl@1Ozo4IIOao)K~Bpp++v0$_YtvurJ>aCFi@RBV^h6U zK(lF%S~q}n$|zk=o=*5ZOsi0NV@xvdhr5BE|Q7v3D$M0&Xo2`y<-;pT% zWCx)WAYhJjvwsIKTL|diD}e(38rM^x1(^g>@SQdWaltQZ7amCxM%R<$8bV9qlvwUT zpUnSWt7XA2=kkoDj>M_OYT3$;ro*In4cRG|S(6L5cO+fcIHv@lU;SlXjJb^__QKg= zm>@paEToNYk|E+%v7a7md!y73+mT8t+p%JM$s=8iFa_nWj?ey*ua{*%`K-2xqG3;F zNDJeEXcd#*wd*S)m(D=jDQUs?h631E)}c9J%GjW^H_9x_NW1yA--RYH_d?@J8cIrb zoh5$+Nq(1#s9}%)k>PrUTKNTy-r$dZADP86jK^u zn0LJyEH;hNpB~RT@nLrtA7U!NsYGfZ6Z~Pc+>jNdxNaAsxy^AS!v&v44-)8}sF}r7 zAi-g7lv7|uT|e2aG@r@r{#u70`5n#HHP<4!LF10icyDOmU5EYpVW#ueJBY8@NYh)r zse{w?nLN99=Hc&BoGt(l7@`upbv7p@x|i_$uTy&-`oVZ9phgPEm<93~L9Gn+zZHJ_ zD9X19HamxCkarkRlfZj%fLdI~Ej!Y$c+`aso!T5aJMiy;c{vt;wk!U_2v7s$KaB=T zm$WJ3aZo&?cs45k)FSSweQEV0EkIVbpP;~|#sri`WDJ8ABX|dQ8(odX6!AS?9|DiM zS3PPYw9H;cXwkI2^^~8Ld9y&|i;}sAV0u(2=2qV;YK8dC zt~o&wiabCu;9Iy$J0dUZ^4A*bKrOWo3?AKDqdsu5CFpprW7JCypg7y8agUXvI4n>d zYMBCX>ePfgAzg28onKdZZeNG`NLA@u1-mnoc=1gDMHs>={zkoQwuyF;__0tm)B@L^ zzulhh5Bs!pUV9p_5b}Jjkw?jm$yz;`%rNqcG6vPB+_)y~tk{x=UGDh3=%#th=`D)--_mJ~R4sM>dWR!*a}NWB-J_ zs%5Bm-^V+kgDD3heL%#`O`e^;?#mtQ^%7>P^&=F|UyAI1FM+!&=aS3FIdI)*) zRbU@L{aoXCmD(R(D0UjLG^s-~GmrZ=uJWE2p%q*4yVBIUqV&7L!&LkZU2&dAevqGM z90#91R?L%b3BUW%jo%N2>uLbWbM~Mk+%I%7w5yM}YT#q_ z6>dlP#ygc$axRM{mJhJkY*b>#Ha}Vdu+h`hfC)2ulXRQ9w!sKB{xOjB(*jZ`BEvfF zHr&*RtFJ3}OQkEv%t33W(2w?8^Udwq_OtT-kIZXp{q(O_CroO`$(pnRwj(Mh$<>?r zNcId~RgB?9Q51)(j7*ZtZ@YGj1qSpFH@&|rv>GgJuCOEfzGr4950t-tUtK51Mg1yU zjb=05%?a%~m^Uy*0;ZqdFJBWvcp0xDW}UR+ru`+Ctbs24hosmx2A+b62FO!aq1j(C zf7Ytm@FI<9qhSH?ozCFkT2(5GoqcXrdtW5i@<&6wUI1~6R{OVF znWbNg8L}@lWU7(G(4v-w6pJVC4FtRS8gJ*e=qfShm<4M( zj!3_YD3$l@3q)5%P;m7V;ZzzcSl9qwQ;$qSPK4A=)YJ?(K*NN#wH%ImOx~}bTE9C? zBaI27HlF?)seMU=|nrPpK`AbJCpf^J{8_U~09<7{CmigwjV!Ap@xIruUzZ@rBI z{g=v**j!vItC$V5kpzON$>~5>NaN1~1h^Jzf@X|n0fbT24JB@xSwIiIEsG(Yxx1{7 z&x>b9e&y~ z{fQ7mO%rCDn_b8XRul5&WbTP&d{$hZT0{Wrcqf?4)kl^oU>0&M>y5c`rL98hXf}t zjytd)`jhdhyJPB_Cbp7GzAV&z0O+Fc10i5?bbs*4g5$Wsh1%j&Ja6>E^xWa_V}`AH z9|7A@lzPor@013MWV&fqx)1Zw)g`2CW&}BDGpoaTYVEKrlL!0dU%kB(yrR=`@)sgH z(KWKpZlOlIR!cN_)oXafytCH&cl`3-!?HuRE_pvGT>8oT7+!=(Qdu2bf$qw^bNd{o zC(2lFWi_sMk@nS&81TI$e@**WJOsOK(v>v^nkzG9Uy8m16`QUCxKZdRk34kszOf~e z2b(#L;cyo}zzD&udN9?=%vwtKjLI%J;h}LPA zah|BaZ2*eJp>5tZ+C73rW;s)Cl0fH)zE`ly10%LUAK%twFteat78Po+6?KRhfl+k$ zBHeuJfyme>xRs5;{mgcMhEcJl=5>mOz#$g3BvzVxGIkp4^f#hceZu@R{Jdz(`CAQCE%gF+HgHaZJ#H;9`c#2#x z$OPYz^2FK&%`V@UuOai;njq)!%MC72it$bcy;bZt_P!xcljZcMV(*U=c#A!P%T)%S zr09&M$kv97(O(E$hQOT_3r>T^L7xwmcg5+g3{HdVZ7fB*y2@83Ip!uH8F-a~^!RDX zXzQ3%XnVZKp(``yX$Bnan6w^1X4F49fafoj;5E_S$8scA)6I}@ULL=s*h6FI3%dwq zBncj)tJ=cVGcI8U`y4nbG|6ldlNK@`!3YqD5Pe+<8)1J!LsEGI5p+s}LuIp{oirdA zgP&$=jJ#h}^c*r%_!GP(0gMnOh& zF8znA*Wde`WF2vKl27FCru?M+F)j`MeoP{Ttz8z@=(>;Fys;jHxowy&wPX&_ zIaEE}B$j6H>;#CuF>^R*V^bW}4DN0U>z7hdsc$L~*$6zDSXxRicpi27a1BEg+LxV#5&0CJkvYY(pnCJJiN>!SjTZ8>e$D4m^pH@oC-1l~!F^Ae36}a-NrZl!&fcj)>x?eo`*VOfa@5zgb3TzK zA=m5DT^84v?Ea!E{Uy zoyOZ(ZtJhh1*Sh*lgRE`kTYnzU2O>;FB%JkD&XIc8GyaWsAh<|?fCr3+2L8Wv&!0~ z-a+o^e;7g7(boC@!ZZI(@R_z$^ZoQg!d~zN5o)0NQILK(&4O)EnZ;srKyR1F1fhP{ zWsG}*%HD4gD}c>Mv~V7oa`Qy94xK0TG~p@n~A%c9oso6~lCnS5L3*qJFe zr$fB?aG-ndJ6%>lNi>1Y2fkOQ5N6`emX{mj#LY*kO!6e3)C8Sh$K?SepBH<7zhmPf z{FEXq&%G$@DKFa(GZb2h%Xbew zFkb6&@uvuK%BOGGLOeWU6(vz`P&lPW7jnjNf`oP3S@w8g>_}SlkgW0KKKjYzcXvN5 zCQq*G@HAtLw|^&NyuWj{(?@RY^|5b(DVv?&&(mH^9FxE3W2rc4aYU52bB@^(wcXje z)Jf&}d4=b^v!}DK`k_Zeb61E z2MA)?sk!DOOH!SU0^vF}GZR_-GaZK7^!h_w_QRs1@!O+SJHBgB2D)^!g}puFB}aX# zC>l5edn!adT@}uaD;`SJIM&K}wZ6Y9Wv-zU2l`})#U&!|X;%4aI<*I2z;lBF>_%nr_*%X$iW(nf~U0uNB7U4_8JNBN;& zkQ0nmZVq2#7G3_=H_-T5{w$84dHQpJW2V86&@whK$EkSRrn5N|I_TS6P_Z@B8pq2NWv1hhjU3C%OY;|_q%;ws_3> z2aTYW*>(DTa?l*!zCL%asNbF5nzl^R*%lRcqHfZJgG}O}<8~+hAq5AaVA?52Ul{L) zJHsfGp8kH9nB3bxVX6duj|Vm}w>1_LnI1UUaBx{R;FuGYSB^&D$px%?_-n-9)ZCD8 zFejLc9cjHST8tvp+wazs_|e0~6n$0(;YZG*1+TVddr#(!on*L(~65|^@nd8CO-52$SRVH}~93!}-fD>H{8ex{xw0VKPnrN!*!`o#b ztc^m_z&hzAy`t95j9sp?NGf zVZP|Pe+0P#1#y7^b6eK+JZVzS1fD6Lsb}08T;$2;hUM5Kp+bY<1r{$SqQNbQ9!P1x z8mj4DPQitujB7f0-v0WRUVA1SBY0)2Yg#8uMlSOn?ExOzxNI^&2hvXrDqD2`ODr8Wp1oj_Qx*eG!FpZ;J$>Q18fA`k$)U+k_R*z_ zNe`7ee3y}CtG25%Lyay$d49>cb$N(u^(x3V3WX}#`&z5%mQC^y=re5sid*}-XbU^>&4->agePpB~0 zZX^8q@A&7UGTj0a7Ydc5ggN8dV7!ct@~>KKO#8O~VJ!9`Bd&Y?>7bnDx}K;WC2h3v z?w`u|6-#UBXa?ZNlU)H*S2xO!m;WvPf1LpPhDgpvC!~bJM6i05m)MI--d24DlOo*( zF1z;$)-qGUL!DadR_~JW-Cntn8B4}(d)2s>L2L)~Ygh%`;AoBQ&WFOUX$!m~p z!cay{6b|=Me9!)kk#7LKwdcU0nQ4udk)^Bb?m=Uu$!%{JkPv>}3PwJ){SV^oP+dV` zy@b@gi1`ml$3@>v*gNgwdIjr}cBZgD+H6>`1>`I}zw3SIy*op2W+nS&R)>2a?$~kW zkAz6DbqQMjiwTXGPJ_^kS;{Y^iMXL(+=awqmWAmMuBa~Jee{h<@99O58NpqKhE z!a7)A-6;lbCbxEEO>k&1sjoj9()pEak?e6V`#&i$(jVkj^JM5UlDDPlQs>&weLwm` zacFjq>kEbKoED}mjyvK&#zJa`YWnc-xApVmvY8g~aEtx1^8dL}dfSFe-pLmMXS39C z^p)LKjfW*uIP&|5^2=CnBl4acmItR~68l;H!#D(nk!NZ48qloK+{ppk_w|YA(Mzl9|d!IP|D{(s)Mzby?L1Of+Is_)ChsLS6 zn}(q;OOhUbnXYue!8SdQFOQ0k#{%BkUR2D2Xq%J7tg0>FF~{6CEubg@%Za-Jh18vwQ+UO_cf4-Mkc?C+73>k zWR!QpdfXv&5+-c(6%8=OkR_ciwMQ+Wno$KyqWm*~yfDmTD--qJ_ZikohakQDNt$Hx zXfL`VLfU@Vq`{bsH*VkfSU97cW;Em}5WW6lQGffF(x)6EhIM zvF&Thcx%QcHcdEn$yPzrn*-9WzIL=}3{&4#sq{4I>>2+P6kg4xxvw$`)E(~BIwLWiw!}sp=yK`ah z*ow$wn!CrR7RWO7>@basQ2rwN+=adG-^}gy{b19c&67t*N7F;up@h)pYIOgE{kNP$ zl79DUC(^|Flcy5BQG|K=m1|4=2&-rdMnH{wSIt>W`oW2^y47@S5j#u=7WNn6lmp_xmLu$s^Ci9|2-dixkVk(bI5hQy7AIcC&0Mp?76#5+u>%X)UtEm>+KqMyb$D#211i=ffJ>BDqPH}Z^?P} zP2zD1wEGo$lqpNW#|V0a6T(0<4~QDq;a8}^ciA!%+2$xO_-wyxt{mXW{DCZdL)Vv( z{3TuwKhJZ6HC8mcDMA<^gsO(3iTZPa&cpi4Pz(D$QbV+2;>K^$ ziI>$w_aZ>2hD-*%?|VO^G$W4GR86OUN7z9V4G)GB$)t>aJ9Zj$a2zd~G_WI7f-{zj zlHI}e|~>2>xQre6NCRA`;O09jlIxai3{4FQ-6RI=J! zy!5&+h4k*k(=UAtNZ|MyXV3QO^R9FC#pD{%SkKZQPA_RY^G+&0WeF8aP`TPiHFW6QQOH%Wxffu?V&^ zFG$%G$W*v|pS4!+jh5B`0NHz_mS0{pm@1 z6XwAd@=!ohC9;0O@_w~~p`Sk1^z3RS^H$PWr>^hKQ+mfz|1zuD0Uks~q0-La`Ofo^ zqI&ad+bfklY~pms{PF)V^r6kpAFI0xVghr0+%-~0JMcbbNAw@j z=5Y@_yGjBQ(GMo9hH54~2(zEps=m=pI=ol*StA35QZePo~y1%nX! zZY^92%}9VTI*#ft|D2ap4`Hc0G%KYf?vsDe-4i7>1**!+WU=R^vIa{`ylK*7lNpnI zYxlCr#awFlpp0i3r!R~uEq=#U)G3uqlCqN) z#YyBJ$e?y)dI{HFhb<%nWB|+;0FK(O4H1ipbyQLV$-Q>hv!|2EAp6=opO$lG-PFCM zY>5b(f&<9pWsn9xqj{;^t`Na*7k$ZJ0-9Lk+X8g5bvoXkI5=QpLaa?^l!_6)eEUT7 z?GZDNLFB?fS@i;mNHH3>e+P!6^S@3n&r}rqqXvv)=*m~x{(d#O`zQRr=-7w`x4+ zm+l7Wqq;^Vm}TXy9m@+8=8YtW16iH7dB8SfA4P!EMUYM&fZKy|X1`RbI|ufr>Hmh+ zd*)*z`WoyTSX=qyybSNrL#J?togzD2+&w(bGr*hL+HJ-D`2 zs#rfm92rRy+l;*kaR4umI_t4sh~XtVg`1+Xy8owrYT-Dc^D5wxDX4O3*QtZ}^RHLu zasw5jOkT4P^9D)0ni=4_sZj}#mv06=r_AZj8dgJvw2N*@PkaTZ@-# zr)oN~S9EV>PZ<>uTKnm|JR`?%Lm|klFK)Mc-AS;dCg!CchYXNQXo~_@ zCZT|4TO^0dQQ<3{jlb5Ei*gRAq!oYA`~pL`ffnq|1#jpiv_wZY@WrT`O%p>-P^^!f zKxgWw@M)IUm&8BW=j@0OesGF{kR$qqOG#i$QbK6U7pu*!o!R|M*J(V}hlQ=iV#V^4 zSx_s4m5U*;4&&pk5J)iG%B<`7h%U(qCeq)5h^aZ}WqzfVsN+DRubKSz(1__%8U@Mg zD!(|o2^ppzuZxhNnp3$D)U6OQ*Vzv4UnpfgDcqrMq8&s{RTUsq7!fG!<2m@w;4KvP zS%i+c4y>x(gNjELAVkbZfnozN?iX)$UMT3jbgt%D!_#z|D9e$GB(!AMZ4<2Ru?W`$ z2X8<5yqnw4CP7BQ2)MQ3F_hB@muq5c(M(@25*B*8!vPaKDCvsKT7G1-^;uz+CZK`O24!E9sc`wmP($G1#gc}0fZ#Jy;iM*n4jYd0@mjP`dKa+<&m z(!KW%RhKw_X*{^*A10)w4_iQ!B^`2cKQcvp$qiJKrDBrN#r9;?@FAb^PGU_}h`^ns z>@n`vf3#650eP~}RcZcq@rII>&IzhkeK z_Ip!d4z|#-tu-a5{KCz=lDXC3$3lnpFkA0CAATXSs2a{KsAd-No?)o&Sg|tLbB+ngRUsZXbEE~?qMgD~g4CaJD`+R~i zwDW_j!%Ss2O8G+%D$e$-*U=Uaezd?&r^NmGwlHH){Lk01D6EAF^HqQHS=;nzzg@wx z>3ia%k$HT-b(v#i5%e*5L49DcGmH?jbfQ%&du<*Q&@DJM&w690wrf`KtW*j6gCwa! zmdr1j$c7O>QcG-BvYGVo$HLpEV@RQK8;lZuvgVIPJNbsE8 zC07C0jO?RxV!D*Ej+P7#=SF`Up)-nrQsp(7k(x=o&JF^_(c6QngAsnc;}pY40u1A$ z;KWzWvei2jR;9Q?;h>@sQJD!R;PJ%1c6o@vXI(p=Yu{J!OqbqOTUMH5(Z0~_;j`&} zaVR!xxx}W_CzL>bK`6S`wa>qgJe%)#g63?W1{)oxn_s{~670YprF+KSp43F22TOn~ zIJJ6tCt?XBlfK%GmUfR$3uqdAkB`-p8(4}vHZ$mH=rq`OX1+L+&C`%AhgSZqn?QUu zMQ734|G3tTUU2th{gi@=zlBA*&}74VNc%Wq0DJiJF6jxO8LA4Ev^FB%6)%$q-8_)G zUO(qyf*nfeJG|2$+!TDLwdP{7-#SHwQEqO4j6;TrLsRR0p|W5*E#q~8l|~b$13TLI z4363gvU2WZt%ey7N2!l$V`Um;4JzcGe$|qsR&`=6!=^E?HO7%riDu>qt!{2+B8BFe z*N>szCToC&(|Rw|chrnEx~wh2728M>+TYWx|-OMy1>6jkpD_LZbqD zfJ*u^ZKe2v`yXYoXrD-j71PA*BNsv&juu4Ebn0BTK)E*>zun)Hp634Dk{0cBaAomQ z9Syo1*|J{UCw)dFgx#P82NX1+-2^94E50YR!8qWBeVKkwPhd~?J8ht_rvx5KJ)8vz ziX8v+3wwof)o;OwWdqe;6N59*i4D^0sIT2o-Fo01#!;ICD6jdyJQsNs)<)-i-BXlq z?O2RR+9|V^*h%MLkZ4I^#b%7-8v9ow>1X>dbBY#J)mB;HO`R!Z!M`JuoVU|$wDK?P z2zmr{Q@TQIiCNR$XrO(;APKOYdKV%B9X+BlsW9R|(I4|SrzgMX2gk1uZ#=td!;Xnfwqym3nkvGB%(eoX@wKbz4F z|Fawk%`E8}qr@l&Kc*@EuPfD!cwO>k*9{GG#3_NsM8A`>SoClQW^`(}u#sy1o%)Jf z>iD32wwz4`pm%jc^-61mh=s1A(7%*a_5~r!YQqE39UqACligb5HDl$T{6?8^?_hzQ zApV9Ol^%PIvk_&Qms{L8rqEZ3AXRSLvTS-pdSMzA@3fGw9!d+afe)>h7dFM_)#p~1 zpk8SWZPX=x*Tz@27a^2a79SPG7FvjOVEBRU@%KU%%>CqxkBFNt%&m`bYJT+DHnKR2 zw)3j%ZtxEvHX z#(0}!(Y#kmOyx_CN|}CfJsyIkf3q#no+L)o>p279M|aPqD&e)+?x^Ud-$FZ&X7b>J zKEorWSZxI}f|u+*z}s1#f63pH!U4cexD9fCj-ZZo=FS~RkH5$JLfXLj0mjFRi`k8I zJap4Tq4MVLBZ|xBN{!YVkJnJW{o09)U73bvFAQ-^7&(ev#}dmh2rak92ry0HURu`U zGSaF;h4^p7WL&5V?}-|nR@;kne{w3$#QCmzthi4x)};l`(e%Jq%a^;|73%y!yPASNyGuOf&|zpMXC*y~sI5QuLu) zFj`83pp(I0>O+JV1k4zbUX`&0wdrKePmYWJBcdXO6gf3ElXVMWjS8~GtR6;Hf=X6g z2w?m7_$K2AOOwzBzMt)pyML_F4!hz*wDS)}C=E{1CsBP}Up15ymG2Nxas-{i=rm1* z7)z6GyN_d4X5`XXmNAE0pwT@p`+23hgK#^f&$hw319jF(|6pF$s2|ebf~CFRu}7KH zD~!C#GV!mYqfGlaO@MVhx)i@bo;g)bqMU8mzu0?2Dl zs#k+%3W|8io4?^NJS}4ei3jd5)Zh|jW>?2d`C{^@a zh?7Wa_%rIdHgP?9PRkKKT?e}dbMHerD%xu_PJxLpuRdbt1eF4kI5B@c)O1F)Z)!8= zKl=StnmfTE!x*YVIwh22UTU~0D)6gV`4Tw&UTN*)+>K4%h&XDb8QCy5Hf8M$U%U8n z-<_m_5ZyN4)BxGleztZc`lym=;?GDBh!H0K&gf0=%8GjIWPP|2x~-+)y2UntEP^%J zO;hUaoly37oli84<0LRmxk0>eN!)aZhh2Tt)Rp2q;)#jyCqdYP!uOr5X+&$d35QZ; zo(0cbI^}jzdFy@vK)BXfSw`I4I-L>X`Faaovr6l^n_C2kOp)WjEv@5k&!kG-Kh@C? z2N$@CuHfl`V@!o0SL?m%lXnDybgC?m+OY?T-vpk7__}zz+E|Yajif+ZS4EJ-a%~__ zQ+`ebY)&q5n%vI?Sv7NMZ$6s~AC{VnM4}hb|K{!Ks2EhQmD|(?VWV@j*}!TuNVMAF z+OgX@!l;9cfI&wy@fj}rgKB6E)d7ha>|3V)9e}UVKR4Q-uM1vP8igJiT1+h>ipOp4 z-s@5r`^pF5-Ol0|7Y?@zjUBdv#E*EH-1QG(@c=EnO#BOVWq-Y%}HjbBg3YX_+mhF!U zbs4aDs_Rd+R!P+tp|Q*$vG~~xP9->UaPrA_(*%U1CNsTJLt9A}#8hWiMI<@6Zkkb!nA&KV1 zX$G>S;RW0aX_{xwv3Tl7jq4J|FNSW^kSpO}cfS`sqsM3{E z2*1*iyqQ|!Gg#Am!@=p$B=669C;Mv&ZzAcf4*Q=tnk#b=Mfc?22keJ+P{Z)u*gPmC zsmLu%va(Pi>|vDY9vN`V6OFcfk-7(vkwV%Iurf?lCb9x=W$~YUq%GmcS)owq5W50A zJdUmY^GU#loLyJqOpxEkU_qGbjcsz?wa3_N8;ZxX72bIz*J$m0brYxNX#nbIAv?4K zx@)JthHCM^E~M!A{4HWZo8WnNj}m$I7W`i>!}Y)5N2GP_n~!9WSINx}`}7)KQxLMq zK+Hkqh-W@|jQL1h1jQMA{-jD!wGJ7fuaai4LfglZk)<9P0K~Q1AKp~zHHiW0Af(}= z^P|iBvj9kf^~3aCO`Y1~dF5TK?RLT@JwnuBVpS;CT!!^vNdok-z4fTFb5|XqS_0|} zDd6=aTeDA?DH%3h9(ob(ZZkh|12Oe%mY&Z^RJrp6yp+41OwE7utjsLjhc`pNyB)>W z^@`i3l%6;)=9-uP$tN>RgsgYPZa6;CtKZNLar69*eXRKhuWb=@1g9YRQl$;&i5__+ zZY~^c-IG{!SG9^C6|$g*d|Yc7K~4?qY6>gdlWHBg&4`1GK_hon7ojd$!aC8K^hQG~ zs2eW6hI&YY4l{>_8lM)vFvhd-=Py}S{{2k-!xChj2IFTqrF+*Wr@7&GP-SItRcHaW zSK+e6rAf@>UK!pMnpR5n(9NT`EC;XynEB8khVK3WH}kogoW}j47mQ0kU7C(^sp$fp z@|9EGdK#WtA%r#J;w|FpR$mk{ethx^H+I?6OB_>Jy0P*#>g`#z3;90Kmbte@ukO#c zzBA4Lw_YYHavakj^|K6Sk7~B&HY>sg1r<;4q@P14js^Rt{Gl^lg2f1{H6rev!`U%D zVHe`@YDvRJ;#RaR1v3c?%~~Sn1He8Dv*GVY;FozOmaPNppe_yRf%VKS2g=2GHtQF3 ziPO_M%=)jDqW?W-#-v&LKgA!S@WPg?CAExQ3Di4Zd98pM9-Ohb1o+UxF`lLBD7RV6nu)Ox z7LY6!w>JJH^Uz*kp6i^pU1jKT{Z3q}kyLx2-$`REo4}g7X_p+i zYNw1KyXPGp2)=8r`j%EF8Ou13MmWHODfaDVS5A$YlXXCKWBIR z6izzxZhZ9)CmVU7XjY3HF}LV~J3${O_FC#JpEWo*5w5#V9xxS~p4JW|B}vsIu0q z89>e!=X&T0;Nqg|(eNX;piLXaOuY1!+M4`kW*|0B!cn&@bPiWvOVjM-P(ZRbjw;MB zwTwUtgM)M9CB@gg(UHO@*LB{|N7z6ROIK`vRg+m$Wxx($TvqgTkVEG}<+Lcjpj-F) zx&K>>Z%lN0^Slhtr2foeV*Av5U9M~W~Fp0i*=bCD53Nd$QlTx=QQ63x9vQ43wax1{G67sUQmxrab)%s*D~$R|6}Pa zgW77lE{qf?r4%Xd?(S~IDemrGpm@7!8vqZ%pWdn`Q!)l}b+MM}?VE%a;sP`#y6GZa3+XMPN6m`nt!3e{hp=EVxun z45kR~Qz~W9@K34zS{^PS&yrcsX~CNF0d0rezuL@VjJd2MU~yZuuAnH%Ds$JS2&1y& zsfol!Uv^&hn8pz~{B0Ft4W73QN}hQu$6TmA-}ZNIL-ilZ_K5JND2f77uiX$IDO@FP z8tXhNAGYg^pobQYTe3i4t#AgUTkd+h#!4h*9BceU`QhuAmr9s?sNu3$jDMHBBKWg} zqGqg&dYb?XnTE9zlanQnQ>PPS+<&K2AGEF+3djR!Yc`;PcoQZU-`Pw_|8w*9eEf$( zRVV)P;?05#i+!nPSG}-tMr8wpq@80YB@&7i+EbxZ9|URMC<-#j3I=p_!|_`5rE37H1ct|xaOkd{q(?pDECi{e!BY@HbO zdZWCjhPFwc;R4OIGREou1_8x5Jo?$HMP&d9QT4~E2;ju+W7y&N)JbBeCN0+TXQj&q z`?$q9tNT&}1W%&PyyanzfsnlZ_4JTL_xQaDB4&nEK>T|4)rJL5$`~SZ;m-L|Ipt<9 z4;QI+o_~0`icPl39n6xxyksbeCfMbKG<8hrGcEoH$VFH)-onh)k)x~JxOaIazP^GM zKkBKctJ4=#gHW%8{NG?si5}=?LjznVGB^Wc5VdgoiEx{_%j+;kCBQp;QC}d&V;dEn zDv6s-VL)(@9xMGvvB`_wZ1aR9SgYsuGzjENeAL%usi(+4;m(jl{<6y9tWJ3}hAAX_ zc|a02U6^svw#EX-%l7=^C5FMrowtR8QsgQ3dC<-2T{3rq*nDUXLRP5WyD?}`FY?`d z{k4xa$EA*1<9vF8#Szcv%K|GH00N43sW^bMPHBkIAt?y{8r^z@p>Ret+%L=;NCArXQlER3^%m`?VPW!*r7gXjRPoUfM*N0+nw((X zP{0f>j!V;itm%YPyR8jbDUqz?m>G^vv7<##5SMTq zm=}a3P*EU zM_RXc4f9v{SM?u07mvc#L-U zKxPipuCEuF4@Csh;Kdt6*3W$`60?CfUnF36$o;@{dpOQ|(AW$~V6J6D?8fd2a$w&$ zH)&LiPN2z_XSo=CG|%|ON8wp3cNT-(zqw)lc6&*37Ov1+X4&dh8BvP$+&lGnEWsJ^81FV zXNp7}*OWoc3ZRCM%6Lsj(b#z_@(C_2ODme|3IbbcM$P6H9$`Uw3)-n^wdX6lzHS68 zGRyYqU|XxC5;QlGaHuwHOBe-mmFDVhVQM2TfwK7NuyK-?%LGxW4#&!N>Rq~Uh@AKG z3!-oDO)?;LIZE1yV6WHau`7wphQ_=Z9RM|hrRDRE+!G$nN4`qtE1TMNB+qw#Q@yaH z|JJ@o#`%{!klqD*mrcf_NKffwfhAbS^C(_T4J*V{!(&e;#P8?OhaiOr3ZB2K zp*`2V{WznC5c%hZk&!6C9VzEGT}IENLI3ED=Q7e z+MP@Z@Qw8Q-yJy)!^eYB1xLgBA2qSP;wkpF%UEk%#5Jcrq|zL=e3(u%X?cN)g& zFx?;c2zG2rS8Z5L`foRH!y??c#%l0&DA&wHY~4Gt5T9wCkcXP#f(sLzr&QgKFIq)T$_?<&I_@1wD6H znXD<=bPk%_(Ubr+S8gXs8ky+-A1sbUExMx#U)BhB>13385JU`;LR{( z-+BUEMgY4Sayg@Ee%+ZJ+Ur_wUM!RJtxz!G(@zxI&k<(1hB%frtJnVRp-hB#WB< z>Q6@Vn~wd#y2if;!(t)L_6L$(h!&mA+{+nDTtKBQwO)$Ygq5CeNOyEPb*8y=k~%he zl*Rsa$jo5>b`)Sk=80`|*v&QfS92_YEIC%p@hLG`t)&mnJiU56h}$wa^v2^1Z^gd9;2j9n10m^r^uDz28PN%_{un`3ip!>ZY)Cjr&i_jaw!fg(7HktF=<(?67N_J2h` z9!15Ehg+OQj-7XM9^GWS7PLO;p9|geGlakKs{wRcS_tkQ5k-7ajU#Oxfw%4K`tP*X zOzHC##%}Cy$-Fra?)(59RS2aORJs7jNJ9EJ9@5 z!CE3##;b?m_Wd5sV~@K!8@x*9A3CfwSMad>ki)QWJjCcANBDa;t1o?pIl+(Gj=_sU zPD^9LMhp8CC<`Pn1bwNOE=u`}+Y-{;otH0NK{eswu4b0)W%#^DSXmW4U5k2G_q(7{ zC5l<9sdhP3o#syF65abWE#r~SzLM&zjyNyxBM@Q?G$lK=wD9NRkE}3q>DH*}DX7## zc*9j%kgk$k&Ta8yun*CP0X{Ut&?p9RnV2P6woA~FeK-&vJ0m9G3On1)+Hf#y-Ad?| z=2j+~&((=1%8v7+yj0lqG1JSvP7hr-G<}T)>1n&&0rta{FW zVpvog(NlUWgi9=`tk8-UL`>y+Wgtf(FkrBOvOmb$exj#Y6&?m~nuFI}SFo|tksW@n zLZ_ExPfku9wr5Nwd3>?eFSy^Kyy`$;2S>{z!@0k#g(ig|{KHB?GrU2pFsRaEBEY@~ z5Bhp~Vc&IMN4&YHbB6tHnCCZkNdc3=>q2(Q(_4S@Et$Dq*!B#t9}xF;s(zDC8EzUx z!^os(DQ4bg!cI$4$>b64;s42>VXdACGs;e+q<>7fkhR3R*mBlb2HwpWL%<9u6dZRt01@6 zGw}bXyAP?puaKBpDFoA;*xdaEYBWioLt^ya5wqySn! z=AQZf))JkrNN%fFD^F-GZNX!Dw&0) z|8g*8iH!LW0;4}Kfa?nMZU3Q28DXwYTYbo7uh-!#nAq=sTdc+rgdyY=%YR*~AS&)H z$~P7ns|7k14vlMg2dMHvkV0l9nn7>dqnz9yt|>xUfeQbDj~Q6$CgjwwO2AyoqX|aY zACu-(Ne~x!?E z0UQ$ySD$vX2wzISl$IZ9`SZSHtvH(a9VP5l_|~^$-|-vI$J^8Reht_nV4P5c)5Jk# zr(|U`eDN}n-M&Cl$0j#ZuX{r5fxBwC?5l~>=9C+oDBFI;J(NJHD5Lk$1O!w4&M<%% zegOH0lBXXuHud1+)+wVj|2p-wLxhiOd!9a0K^`RRw5)-T zUJXqTHwUgT4{NS04{`)i7%nWCFfDLZ=hww;r!3o}=g^f;wOnf5gp?7oG5;R}iM`oT z+ENwks|$@^D@+!Q{OK%}n|zvZ9&5J2N$HfSuHtzmTg~lCAmEQ#o>k%QgU&z=CXaXC zP(dDB(74i9Yr+6}<+09}l*L{GM|fjJF(_UB|$xC9!8%x4ouV3 zgc?KyaCD`zydmQ5aW4T|KAHTm!L?&Gd0WK#NQTP>={Rk+1Slsg z;4rCzosvr~_e!D8Fo6SUA?J3Ktr}flDI_+AbAmUC2N|5U7Dm`>EF)_Xf>?QepXyd- zHgyL3J0f>HUoRKDthhehj=P^_X6gN2Nr$PpnISEI_#C)+!#fTVv@}O7!fw6T&K?@G z8n6GM)O3_|YVfWy75Ayg508EilYLM7(Pv9=53|!7zQ135Wednr!1Kw|K;oUU%dhJq zBBpqsxVy@IflngoMx`gb+{j%om8s6?n}=oSuZ=V96#>GB1P5^ppig6+55yv*=k5o! zP%}uIU19IxZcYCvXbnr9K<8LWss!B@prSRPq1b@tP$2`C;j$z7zQ=(Yb-EKHa z{(T(B9q$APF^xCvHGxa_Z1HS9U0#vJy|j?i*f!3?a>M-iejyF#dQFt$72CZWxk2-K zhj$U2SJ+J=E8Cwk$;&9s)YA*E+MCYsn`mm1DOmXa6Ic>;&LbTyd-FmYF-Bj8(6*cd zNlP7W32Czh=}r1`)H1c~s9Q38V}qbspiSYqInCl@ogJPF3o_a+^;eE>(8SRK1XWp1 zsgXcO(oBD^+MtzDsG9vN64aYi%1}9sPg|u$_g~*@F>D-@YtelRjVFbf8^HsQ4XoTL zzNLSBHeI>dtFm-|2q>kl+wh-MR*;H^vDSO0&JjIZhc)eI#o5f+g3-z1s3qtDqkvR? zeGss~mlG7v1z;J~)~=<756DH=FzP-JDXCvi;cwXE$GL(e(2D6rPzp^>3H$j?rQMHDEF*%&{y5 zE$PZXH1kH9h(Bad@Wkl*i6QRPMMC?_8ihmShGTwMtt|O*|e~`^QG0VCU}Kf5<}va9Y*zp*{A04fTs%hS39|g*;7IjnvAeqlG7hU%VTc zw>b;n!J->)V*8GZH?`XC=XT>$7pgp}lUhi(?qm_8o3c_W4M6%WurmpRJ7-)pH2xXR zP0Y=YdY@wUt9J@+u_-V@vATaB!}!Q_xYu2@oEME}*e?Q62OsHIdrEj-Gk(#P1G@hEa^e^I6P!lT`TS&pN3-atrVlTcDGN!^C&%|DcOrGi3Vnx#L;;@T~93wKZsp+##S(pVfkfS&D;yoK~mVZ<-bX(f`KJl%Bu{7Fm zUG{sp3(&_o2F`+WVY|*4Vx3j|vhwZGwz>B{HZdzyWtMhotoOGy#NpW+QNI8>W(0Bg zx#Dg~u%_&xRP9UES3`D#vohIa(mqmKsQhiAP%GS*6`g$cSOD>a&NsTzxOKq$0%R?^ zz=!6iJ7#@fS5W?;G!s6Iq+-cQNnU2_XAyKt;O`MXSaCP(oZilB9$oTuuJ{$pR^6oy zF{JIS6iJM_*{M@}JXAXy?R|kEzv1E@NBUbT(f?D$L=DzuFTBMc^fInK7XrR;?OYoY}Q147_4Lb!EHg4&gom?Ssl4NV|bp&UC7=$Mp*q# zN0y&wC4S%gFcH&w#$K1X_y+)P^5rv1XbThbMn$Vke~9!&^T&bO(kq$VI)|kDkGe`m zl|xwTV%fz>Gd5{#1>0|a#EI)gq^TZgEe&Ik;Lj*ry+FZxuT~)^6OZgerXm-RKVVY> z-Y_h%RT!3LMqTa_Tgt>F2_X$(Z?!KqYMss8XMG(31=c(Z*eFZfZujqSZ(#lEkt=Z9 zxwctBcjt7+$nx$Y&W&o%(s()EvcwKW=_%J*4! z5D+mth?Vn&W^9KCBPLg8TEjnTdwT^oY_CXGF-K5x##)MzSrH5IU!l9*o~MZ8iC9so zHYA43{;vqLMJ^9^uJ)bW{xvroCd2Om3n zQ+^2I4RW86sNW(b8E|e6IkAm1wIas7H7Tf9r*4|TM4`D>wo{H8rXH#LDu72Q|85R{ zsI9?pcys8EcAR!`qRNuH^e0wEt~f|zpcryS$FQ80djB5jI*dDh`wLrl{hL`m;#w(a zV;2S!Njp$}=(`fDdT1kz>Z+IX6ry>O;?Iy*d|g29A6QcP%fsdHQ_JGB$Yk|6Nz}u0 z7R?{$yMHL1Ut2Z*HI2jj069rUH?TAz;rl|)qLBhNxPJDd4mnP3=?UA+@4`1)4^A)g_XAU}m zTx5kiz<~K_KY8Luf%wJXrFIu7l--vpTrcVK5$>}OqDK_wr#&%8(}~9O{qM72VU{~` zZsg)ha{paw#iPTHaKD>K1_~UE*;M8cQcz$s* zao0m!Ec_KP_Dcg$c$G)%3paRtL6Mi!9mb-vrPtlXsRhp6LNf8JItM8=cT8`(xjlLC z-&TyX1W@+3%xWPQVJivcCP8D0uz=L?c_#jKcM69EH>rtr2gBD^%9P9UxSRZTb{I|H zs9ff{`G+#`^crn^&RYItTaccvE``sOkuIq_zM!qbK}Cvj4$S&m z8#Ikkig2DbyBSVk{SIQ+dtAD=i&0O5nv!_}uwzkLnEcf#nCkv9c{NiELtSehS^^*d7^|0|s z7MgUKRlY1!Ugol6z9hC|x`Sv`>FRcmK2Vs0j7Ca?s=ql5RcG^FJS=lcwC`*Dud(7; z8BsYM{AJ3@a`_($Z^hT`4DFx?l20}YPl;)x_@bR0caWIZGfTr$Z(^XMH;og!{4T34 zpP{@ATWT&OYURxfI|iTCO4{lYM#S-5#0iz3__WZZW+9ITTGC@sfcLq{D{G0c*xuYR zJ(Ez1;_4)Hd0-w%EAt6OEjU^>s0}EV>U9*%+8=cH6j!_(5Xv>-UM4Q_3w{;Z4x}-z zvhR05$!jfQSQjY?)KgTpQ}aCOZe(Yi>ozEwt0`#m?;b+-rmvM6X_u@7sx2RHH$%s~ z6o0yM{U@b5jJ^`X^wvuQIoQg#WzD?Jm^hSZIf6FdQT>|}EMLjqbVF8G+Ag<1bW`S$ zo2gA31$uMLqVb}4nir!W)i>}{#1|?>#WeC>qnKjpuqJhLGdr$94_P|kZ}sqUypZV> za20)qO>s8PI%6*jZyp+TclG$;(*NGVNk6UjPr|^W>DDwC6cA^)p%o2k01BaGbNEcT z@bZ)%Nh0>2cdz2{Q_#aFk?TkL1Z|WY<_9FMdpk7vwCyk zdfCe!ht95nr+VAiNKCc5S2lnPd<_Ex8T6CIn1YA-*&5aHm= z;T3INQSiSE8a`wcGQr%var#g20UXPsSP1g@XbVx*7Kf2Pl~qDf=59;nau~p2DEC@rLrMdbxr>Lbf_g&ussU3gSgT(<{$Twc zFIH<{6n#TOE~fE?&Ku}TBWo$UmW0yLw4QFOP8Zp(UIh3I6O)d^>0kYfJ=IT6aNp}! zfw@0>k4?)K4tR7R0VzgA`_gsVGh*(^TD#)~R)G;Uu81O5dOON^&W0lUlQNJpQGsB6 zHk5tB0hP1fJ6~I$?38A@T3bI0JPh_9trk3qjDKw12mM?4e~HC!!?hY3D3nvI;Or<; zF|ux~>4zp0PU!#okn4lU1Hev=?pKi@7&cW&pZ;-{bO}j?1bz?S*XMx58figT@6>>9 z&+HYwouo$(IRR_ju015iC~%^S&4^AF45 zAGdn8+}7w8af{>aS1iW6@a!E8xaQ6DQD>^K@=60YPkp^7kH3Zv_*4i}#3mBO>~rl( zWzjB!5Ik9coxuQk8oy$$;n$L?T}^g9UXE*^KX9<+|Do=oA`KPw zn6dHBT>A@1p@lN!r$BR0bEN4}!|izoi#wA``6dH;La9?ri0K;=MfT zid;7Z`lLPt2g+yIYfTONl^S=Uo$!E3_d z#QZQd^4O;m^_%Ge{1+BfIY(h21++1kB&<^dxl%ZRS2rQVS)uX?oa*+G#&{+=0jp1U zL|tZN=DIv^f*KK4?>oT*NGskV@)7Tj8o3da`f!of3hl!rg$YLmf09|v=tbl@VooE1si_9bJp%o`@`_W=u@~oc2l8O z)M|WJ=-9R7KlT1oiKC}MB@bz3xL>&WX#gnep`r8`mkXhAuHv8mt|@t{Iy@_V{HKFr zC-Z$Ls*wZEWFFM0GbUQ-KLJ*+ggvtImW&#qtoKW|=(g}_`2Z~2)@%C-8S@3MwnCO? zQ2G6 zM#$&RPRW>QYM3lhoDFeo|8i$HJO~*oszIvPxZLcoQ?0#>Avu-iJY!J_$UMqTf6g!w0D7Hw9<&{J zZNiC<7fh4GHj!8wy3Dj1WUzHcQ7i+a9;C|s`+2L~f6YZ<*DX~j-L&Tc9NsBRhstI~aQ(?H8r4RIcA%?PDdMnk98HA7b#Thoft;rLIGOLs3MpH(Np{*;}CtmWSG&6Nqy_8JY#~i}XC?bvppO6p8QRLV|3j+8rH~VhngIyHq zi7A{y+or=&Ews6h8Cg2OpeUTkAGeMRrJVtZBNp}A;aC6^JcqZ=QLXLqByxDew_Gfi zkPmH0l`7@cn*p)VcY$tv%C-IP;OH|2j>wsQirqq>EvRAM5ffd|3uob2U5YHks|ZdJ zr4A%}9S5Bu8y4qF!kY>n%ydrIgDwAF5lsUGW*XR~WKgR&#l1fI>PaV>Z(bJAypL^L z90%n*dmwANvhE7Kz3nCtanO(#D<3@CT^Dwz2-JlQQQbeX z0;+TMw1HAja9)`{Ds3_%8$0AQRe9z?()o4 z$PL0(-_`jW&HLj&iaAG^q}Tn^Hz7IjFPp1+V^|cN^x1oe(`zOS4YmNA=T(%5Hv2HF z>HM*+%-DT_viwnK>#d<%_4p@enm+|ng2A$s0)@f|(FyCq2kGPEyQ8E-3DSbL9nxpp zxgA|E+lDc8UsnPSVjlSyZOTO*XQGGh6N!#nzDVDv56#YE{Q_Ho1G;e5+{VzKAFXh7 zv9fmjyT3tJi~^*C#L%J}Rp*c#ZsGF{_M<$i`aNwVXITMt%x&LcUmYL0P`B{IA?)iJ z7nPgb^72vdMuI~Ep0_v_epwaK^yW8l{^mve=*?Id6lGkx5UV43&?@Gf{0}20k!w^z zlZ}X-=@!xyp>@I2axY?QTnNvg&3gtYGFfn1qmFr*R-wPM*zS5&*aUcb7^X}wDE?Ac zX}@n!By_*PZ5l=)eK3)!g-Z4ZFDlLhrIg_2uF_HMdgJw;^g!|1n6F?QQd zSm2i5!voB19XhXEv#OeZF!H}VP_&8f!=wHZj-(P|XQY44L9I2jJGl{a6agnGC@@~; zWnALrp2?~r$^A6&(-j@IFY%?GbFf3&BW~Q3$U56t_dMJLo;jBD+e=uRwd7r~Fc60( zB{Em3dM`Qu_3+}&<0|8jI4`+QCp^)}8_^+#9C4^U&g5)ZRPFULYsqo@UUvV|&ULg9 zyMhLF8cm6NDRjEht%nti%&T?}m@N-dE6^m@f7fjkw>|u&%rPane*6{bkrGv~!`H1G zZ?HTbG-;$U$3J;0J9L#YC~t~n*16hpqIiox7fVSw`Eh~ZQWUmS6vP=4}=p(<9~iU4QB5%-0P!-fL z9;27=rfHH4&dS_zozcFms&c{^h7Nv;NEJ(IsI%T$336bC*}dk}NXBYembbn=8zkp$ z>}|CxxA9`6ynwc8r#f#5B~a&w=pUQ5oDFBzJfpKmg%wXEgehys_^V_Xq0_vxSM|`> zYAQEpoZ(M2hSgU;Rrfg=;nZz!5s@cBu}lN5@v6ctxm2GU300tH2j@hu%=hUC2DP&D zS7VE&FOoo&r&b1itB0Dr@6t@$dV_>SO+2jLoe8o(j08!dXmc!G5&zT}HpM|~Y~P#@ zPO0`y2Zv7AZ1&gRTnE$NIDS4L=<~lB+mIv9#$fW;I#74eAU2*Kl&7ULbGu783g{+n ztVkkXz${EAV5IN4&xg)X4l2}bTMcc8y5}H|%guk1WCKcc?Qam8I5PhbL*UEOH2Lfhg$Pp_mANz^JYe9FM`k} zu*%upidf>sDcC8O(6j6^b9s2egg&XE2d0B&)J>J_5v|9T0#8bL&)}T2?a8PgDQBwB z`eso(T>_KergLo+QKWX%>RsdiGCvjHcpTaoCUH{UeUtx(LLg1%H;x^-bNdfvoZ2%? zLu>UP3Zp+B*O`pR+|9Pas!rOhYN}0tM*(JHm@P{R8CZsnYoMGY<33A(Ke$e;drwj8 zBxc~*7_q5`?1qDKWx0^)h@jdtLergmPihXJ>7(T#;4aL-&QqyCT;yqxf)<26O1C^! zbx2k^B)ywFHeI88Afl%|Q8;C(w>oK7P%4_5)T*`D~q+=xetPA!7j0e5XW?95q53Cuar1Z7LEw!$0Ji6^ugkyX}QOmbbl} ze2*4U#q~%5w=4gG=~mg@+S>7*r}TE9w+mSgOImOpa4pnX_4K#2*ZO+)pwFGHm=%vC z81l$rl*9Xhk3Lq-DrEM@;EGlwHHyf`W2?UM`F)V&RL^Z8^=)ON$t=z+bNO_-iNf6E z87i02l3+c_cMXq0no7)M<8=CxS&;&KycDT*M1C;6y?P!2V718f;oL#&GU?-USvus8O}VU`qJ<|4;vvjsl+q%d!;JVK zme0RJt?6)8y2K7P)Ml?~eMyl+OMSi7h{Y)ybvTanmz#>_ATL~qH^;m8NVRfYj?Hgv z#lMw}#Zej7<5{C=S!3LKOup{xhPm*(*P18a8{q%?->21>SMm2Y(6v{rnyb8RRp4E% z&JGiT_>u`(5v+#c&mHgS7I;8XZZLeO&WMFtLool~LM4%oy0z6nzdhbE@%q`P@*mY# zMTQM%Z{=}a2~|Ee%U39O+QuC-pNBHNN|QJ9NM%TuKc{&=xTt6c5_!KG9RGf0CD^bR zmKMN8j6TjrD8hYP7+V>dVWKLX4ELG{?o2`c7|@2twOcxInl$iw{Eid39sLjM+cNf} zReVI0})Os@7TPm>v(1VyR z-o4(vSVOctr0^4~VOYxcrWl|pu`$+U00!I~ysO!=O+vG>Eequ~*6PY?g;3Y-p#rvO zz~!6;Aa&tNQX++VZKAJg=|3;=9n7Iw#NSr^iGNYjLJQ%QQjN!`PoF8mv}Jpdy5*gM z`p{hF{bCv58O9ManoCP&vdIPmU(bo(#mI391h8vSSHI?d3Ck8xCjBK;3#fj#LAfTju(MzIJq`Wz4V(fuc-yj z;Plht@nTtv_HvoH8ID^3B)-eFjX=Ab8nA-*f#(svGZIt})EC9BfetVexXslRgQ#r3 z&d|5ED$CUh>nOS}o604aekuyLg%jFr$%xTi2{$uPX5XcKSh@SN)kETd$7e1hNy=2Z zG)COEP75f?8=k4s1nSS|td$c~P8&CT;1a3Y0F5J$5Un=k4v;bwf(Nb}>o7bqi!{JkKBK$Ii08lJsQ zMIMy1SW2sCKHOG8tYHVP=UfPgJxjba0P7G4yH;uCG1bC>mv$CGQbq8K||n z`*iZl-F}*6H_hs!Tw5We`S0$tWKST=Ls;0TN^E_yQ1u{7=p1F*ZV(83qg#J^joHuU zR3W8dKdo#%@ef4+ebRgz3%oyAQTLLu;dteL$NGdUhI4R=4Z`m4)d0!lQJj#jep6mp ze{)M7jf*LW^QIcrJ>MCUFpfUZ?%Y&q!zA708O100toAh-5eTK_+2*NqtV39+jm41P zgh_mwr1@SN;7I3BY!)>zMklX2DVaRM(}OHuE(NRft|Hqfodg7NedeQDy&m5vKVPFW zVSv1TTNBa59A=#Ds9AH=i4Hg}`PH5~)pB=af^er6_$r6O7rqb`NlL4c{jW4sDAvu3WUdKNM z^L_4m_oz~Pckiu}>PB+A5sWKCBDjktt)g59oHuc~%zUH%LN6YbhigUD^@p#7$P0G8 z=G-q;C#q|UgE8;fG(TAFDzyc6M^g4{A;KhG%9!$O%mX>t#5=Y)7k!i!!3LRb5}^;~ zkT*qVyeY|g%#JpkYnfG5=N)Soqd&tQ|Dnj-BZrXPFs|nyuUX@TbcMcoFe~Xi*QzmU znN)GR83{AEyz7GUb5(_d>o|!d_ z4!Ax@sSW*5S{uj>KI8mFv>3_ckVWcy)X1`>4DK+>k||4l&Q?^?Q>(=%Db&)z#bRXo z@OxBNpdH85->7x5>mlHzS(QKx&rp*}FRJ)Fb9~cN>^J-$in%8dO5h#hdtL4aRHfaN zEw5B4xwP}Fo_Rx@trz;kw->an>UfG2tGg9i_D)s4K`+VQx!bzW*%&W?(r9$skUzn+ zEN&0w6)}|-KLg-yq7XrO9OZYF{AjHO2K#N4G~KCRd%6$-A`g0x&)%duu$3GTw2&@n zh*rdn!T}Ac$*M7bBgiOk9j_cjZ=kvqYUqPXp2PMs={tzzK}urPxb6D`CtpbB^A%y` z=f8i;!(gw!O?55SJwlrwU_4dXXWU5j;|v4SbEWS+QzHY)(Mrq5t$J#5bjQQ z{5qLOMyZpQf((?0A2I_+aKp2hon(bysj=~Sa9TvF&%2lTG4KGB)IQ4@`M61PAbW|YS z*>ToJ70LzY9(4^ECCUf-m)loA7pmsi-*vNH)hLSJ7x{*Ri07x=3FaCk{ex0g-Lo}l zMg);Q)8meSOug>G$|&Y&aU*qer6Q66ZTt}3xyrRLW5>EB^TRa` zxhMHXs%AimMzwkKOBu4~ca^?rd#H7X%n#BCQlN{$?hRGyT<%**HCq!UA&7KCCMTgX zHVYdf4wauTZUr)Bb&8ZIK0u2jM{OF;fc{165kkA2+u7DQt%h?B1Y zG4nS0hoY*OqKrH=IUr&js%;{^ygzK{5gt$bkk)ZNC1cXB+HhG8CbPa%J0Gp5^nlnc zW0r;`ss4#XMkXgv0co*#X@i1or$R}dGZ4c?7X7!3qcvxZokO?^?V<{DGUOa_RMjnS zQzQoq@et!)lOeL>)*@%t;JbLPKen!z`C*d$?U`mtWEr{H3GC=8b#BWq*n}q;%wtbx zW$A!ngc59~@|a9`J9u=OCv7r}76Lx?4KR;zOzmD~RK~11!(-m*Zl6=h@$c!@MLh<% zGSBap+PeCZkI%zGrbJ1C!42W%WkInI!Ab2y+sbBsisd9uuZW+QT{W9mRXjbFKtX9%pq77Y6`4r$&E@v(Qx6ZkS zfP@f}3qU-n^1Km9P|e#nB-oy`nm=vbV`$W@9yNNB35D3`QPJU!zJV-R2y~z-;s!$oJ907^BVbYy1IIlK zcKYmcmFK}jyu4?4sOD_^dI2o}<)&yOL(HCsDR%J;R}x-pG!G#2`sxq!eT@gZzpl!) z_KC!@*~b-OFy;DijB_d~?4bCOQ_z1u7}4lUMa0+#B1EBKm~h=hb0SyAc(n+^X*xL^ z`pb?r?|55!uP^?O?vi;L<%?5vJ>7|1HKLA1FEDpORBB}}`wyOdI%fv=3+YY>TmsW9 zOg2tPuC`v5*Nl!c8r~4Ap+yU$gQ!Gp!D4}f{HxQQxS!sK(}b!*&4 zZ@1@HqH|Zj$ZkCFX{Xt+^>e~IXlo%wmZ8q)!NiG~Y59hq=5%m7CXOHMeqmK*#W0O< z3>))%jPGgJOHE5BI#D{JXKgSorEVU*|CD0agecU%dA$M`^2boM%8-s7o(|<-wpz7Z z*^jen&y|1m8v~2rx*+?C_bb7>YiLKQM)!9z%Zvigh*vaa_phZCqhli;CwJj3M|Jgn z>y;g8VsxsR!&P-Z<K-R#w_M>y}N_lVR6Ldp?JXf+1AC9rB;qjKg zzlaBbmHL{clP`>`b;RuW(R%SydOoh4&u4e7D39hAbcW26jJL> z!5E8B(QStay~-NJRv0=fNoG2F-Pr2uFBdQKtO3kQ+`a~zANdPi zUW_E6#bJHV=(mgYnqhzMBm7lIh-M)0D7dp?CXFmNAw;2|A)lR1#jk3UmPGpWFN4(} z!n7eAkgd(U+qDEhG9b+`;RbF?=!z#DpZV$drs24iBBV=EJE`*|ehQCFesS1y77(}< z>V-SINpZDXOP=63o?&|9ewkK&>}jOKS?ql~z~aV$e$EL(+>)lCmF%3GwIx;+=e*`H zt-c~uZ{E7hB-<46Dgn)Qf!Ks*@6S|f&O-E)M&QbWD$BzvS3_u<=dzIGNiWuCozpQn zWcz%*PzVcsnYqi!0^d_L)$(@#dfZUQ^?P8f`)~1o(f9!)<|CGXLELPTj94C@81oDWzh(!G*>GH7jHI+JQ$>qg*EG~VecuN(ySfK6JS4;p*%qQ@dx`5g@E~D* zK6YFll0Azu^@J8}>Lk|jqOVZgJXV<)dYL;{U?#CVEJ-DA(f)$1=$8YyIR6W|9?dA< zTX|;%B9LqaSs%o66WVhm@v=Qr7+_H)X`2Poh{@ThpOhJul2C=r0S*(37JeItx7qHu zktxatyDaGFbmJJ4D8-tg0g|tqgbC|9o1O{{=+E3YKXAGY!AOLRDSvCz4~QhFn40XI zE#hdhtn9-AcE7Y~bLu>@iP^tp-bc?{6q=o+b$q|6J06MY~PQ z2@0qpDk+wZ3b4^2CR4AwtSo19Faorc<3)@9-c9Biio>w7-1Ik(58`V#d!nu)M|(le z1B#hpl*K?^zpU$yVe1lduE1*$9-8*Iuf44&a${YdC9y&2RfNpMZf1!8?2t2U#Q={` zG2>(gj}#y)7n>^ZTBzHg6)uWct5ychlu z!-NJiB<+|G3FP@fH3jqJ1~UX`!}N9_k@|z(%OVXEq@1+L@1np_b7LjAhU)yv^t6@y z%HH=RgA%9m+Q>2{!&|Wn_)z$?ONz95McD7co|N6MYsfxTDJS zB5+|Gx4QL)z{w{n=Eb*#N-Z*}!b^SQC*#^@thd|FkuwV6bodH}57DdM*WZJ|HI#sq zvh#fzuUb<>mNLa)CPMjf#`jhF+NAK1=BgAGj=A}v8ci^qo1~H$rv)Mr&+{hF9_PY% z@jOKld9{h9mD4TTS-E9T8k~UtE#S;4#PDJa$_lvt7$k7oS^Sfy*Vf-QIzhgLHul(j z^t&S4o?f#SOVLq~wRbv2`1m6`WHEJ~c{W6+iAAsFl`Xjj@c}GHe@pn@;XU_?^dmI* z(3~~Z{I~*ls?EZ-q=&m{32-33 z2ll9jg!?}C0u-NMAH?RcCqio)jNt2C*acgnO--m7BuHz7o3#f&b=8VCn<<1N))8yA zZDxu-NMj`t`0U06bAg2f9EoQx!udWGAm>+auUGQ?!OGKTYOe1#wJj57E-A{YA__K; zZyOo+B}>>d@S+T^Uz+Y*t6CpnfsO#SAJSQBoq0d_1B&uP=W<-7!{Bj{J@m}Q63aa& zYwn)GiSPw$^1y8&SJZuFaL%`%py%|O&uOnv0C&@_fOA@MLIv;h2&I}vuI0Eb3$NYG zAHDqGJ!_!-lE?ipRTnUz2hct1k`=bri$?s_9&>`&-r}FSPZZ5hhy=Xw2$oUdb1Q z=%@PJh@XQ-BlX9APJ@y*%d-i!sZMnjkPEir@kJaGG`Av}?LJF0)3ASHmUw;`)e-Dk z=`!(C8w9!KHtK2i4RQ(>XP{=#^|+t@+8}jWDH&b%na1yTTmnrk73*QwITYx&SVk)< z&<%D`1!G}}|NNECF>a;|Cg>5Xp{jw~%ARv$45oExU~5+D0Ss+*V|e+o4VdEtdh#FTQ}cO;_;r1atT)^;Hm`RooxCo4 zelinxOin!&G!_NAq|Yrc;;2ywiOC`u@VlCy}wC;9>QtI1sS?U1ps;IkD`U9VlN! z3P(HZy=3@GxJ(RZNF()^s#ukzywHUzK2`-wyi~Y6(I67E=s2U z)m;JB=7+Pqcs%(|q~WAkE7N+g#$|qa{-<3ZrBLBOhu?c zeoPf`FWK=0m-SZV_%{NQ~QobN-j^C&A4|V4ItKv zp=BQ-aUTY%`0FO}C$Sg_$JBe-X+gcGL2W=_0v@vOhb)yr#)p6YpM6wV=X3N}B=pj_-ex9dK$E;F4nNx-!Nu6&m>$|Xc9flmyy$tiOTWavAwzy5h=;JOgp&MjZ$ z&@8lFoJcz5slby=sO;5E4Okdd9&}XZY z0aR*mnvN_;5K*VT-N*^YnwhmB`si|kU*WCd2lJ?zF$8veOotO+Y><;JEye01jX?N=lZ7oyj|C2P17ydr^0Khp>|QGO^!BD~`X#OfP{}dl zMWfSwpw#>|;5{R)$H%>0aqC0k!t`a`hlqg0hSC#5!A`8bRC|DYGtP~+53wNeF;MKm+b3J7yexIQLG$l@@Tp{P!|K#(8)NYO(Z;neJ@jKNzU zAiUUfDhj1~H+p^xcuuB$9rdwdX%{h!BPeB{%S#zUY#X!>+WAGQHawUOe>=fDZQn+K z$#y1S3Lq)ROqF9`F0J) z5BzrPoyrW;ltRsEcDc1moKMA?|CAV&9EC%8oYYeZLco0<%uI8oj-~n~$7B5v`yD3E zb$OI~lt(Te30zVDPY&`tbbQ%LeCKJ@xH8xs3E0swO2bs(aUXQ_vZ}6=8Q(}DLSAb) zhwHTevEojPf!f8GppSKb`3(=ub9IV=k5O`}$vBd&#x&SEzb(~Jgj&mL=YP1LDn*yX zZJ~a(gJ0t4;&>@wNXJX}%h`22Zq|D3=}dX8krpnD5<9;w3<>uHD= zB`}Yxc-c)`^a;1$C#u0WF@5@34x0^1Xf-~*!YP|qYe0*ho7UbFo z2!kR=Lj_Lff^?h57k|%54{>_eI}EzMJ4#;lrC%tQc6ahE3mn0Jp68KY`E9PvtL(yt-a=Q z=kS31xfR3nf?5_3Z3fX=7?uS2bNqO8D^n+b$??| zbv<6IeN}Wgbz}coiWM}cQJd{O!g=wONSj{k`+1)$a;&@nv31*4zEs{OcO4Ogehcu8 zunU2Fhc6ODHufp$r#&|M8?yq9~K_|gdPjg1y0FJLAJhUJgKg_VcN@Ge)setdA5xjurF$i#|;X*hlsM$j6i<-l`G zq0Sm*>Usw#Cz0^|kHesemW3h3w<$Ed1d%IOr3Md{f~u|Dht<+tj>=reF4q#Gz>;kD zD*A!G_CkX$@W*VIFS+cc_J6y7DNtr6VlMZ(Wm#Rd3loIP?{r5%O4y>)yih$4& z(y-pnv)?~x23RdnNhY%d|MY-zl#iMHDdEi^5aHuIxfcn&uuRnZ4*?zW3-56a{>1s1 zlOjK?=B?hN^sD6xU%K&*8Si|z@UExrr0k#64ypW_o%X<@g0@@4;okB|y$}R8U_Rg7 znND++=H8RxsuO|Vd&(elQ_Amdv)8Uxa~B#|BTlM47B8X%k`flss;#4|9oeZ?713=i zm}2PQhjC)D%wfwi58K(A-i}WCBR4H)4T}+oHu0Y_BleP4tg6s7>j`0r2Y%=YJ@iBn z(zEb9a(u*Ucu7(50GH~KFax_=yNa(gtPEy52&4=@Mi?DCM&$gC%fA2cVkBF^826A{ zDg&R~(WfF(;Kie9nE8s^b#RwgW!DBErzF6NZYZVM+`;sK&DSrIZ5owLd%yJPtG;w! z$bys>6^ZbF2o$I(FgVD+$Qt0cz;Ei_1sz-UA+l**=KXN+dG$;!@-vV09oM}r+xm&P zf6MMEzoAu%9IE(uTJ_J!f)D3@|sa&1l9VU|(nN{UDSN7zm!E3Cvz!NBA zwd_3NUvB{Y-^UnT@f%aFTsX`4u;XbVUainTvsmo#Iu-3kEz!i#3^Mg*{?;IKSIQ@K z|LF0DZ0;CR4o`w5ZL!Yb4smf$<4)CBJy9mr9mvMwpj|7SjP(q*``;oD_7@1`i;c6I z?2pMd<$ZAsu^1A(-XbQOA^P+`_S$_DwD^XDsq=aW6f}yO(HH_}PY>5!5AU zUPy}Q5dPh8sGD--z?Z6TU|{_U%XMn94=Y*d?L+dN`i&{~OD7FXJfMSo10Nw~YZaOTv@0XjUG^2;L1JgZwZ zP4l|oWDZlv$SVJs68s}svuQWJJ<1&WhtkS5n2?~;=Lhte>Aafw&5`s_`+m6`Mjj0u zew?Mo^J(-d6#-@Rn${|J!~1vI@I(}tZ7-K>t{^IdJhq9SvLW*F`a-WL4GJXyd1wlR zJg-A}00~a{k!!a0EmANt#F;0RFaVlM0hxkRawnU(4)d_23&l{rKEeXOf zHLXVrOJw z?4&}u{aZea1|~m0$S~fejD~ZryCjHV_oay4(n1F2a_`R@EPQ7tTzJ1VR~;k1(D*oF zB(KTO&8-Ux^5VpFxKpCxu}gKSGp0t2pUo;H6VcwCa*RzT zvvJ&rb$8ku!$z<=#+mAJ5glc}!ME~kR*Dx&*Gl+)TDfM}uQTIFr3+`$KHm99 z+SATu#J%k^y>zSFJ&PqqQD6rWW=8xxcHK`@LyQ-avFFB}bGb(f465!$eOxa|Y| zuE4k3g=$K0fEe_Iw>yynz@K@2JiNR*rQWv1=Cj1UhIZ(*JwGU7pH;V{?9Y4fjRf z%&uJTeJaE#9Sg ztSCno##38K2CgMVFtN$Xe?K;txjqo0VUU^Es*07-%rJv6#}tmk3__>p%d?;U4TMx35V;ene3WL zy94cO`DgL=@-*w{yk+D;mQadVD;A<}*crg7N#VnI$R8_!PaE8&8Wm`BR0N&h(v;vG zso>GvMayYjx=`rPPQ$>^97qP!f4fKNbciQG7~_E>Vxel6*Dei^La^F=>;e}LxBOhi ztfF!689h;fs+wZEtq>10dO*Jf243RT%iO*~aWO9dYpk%Q)80_yNoA2=k(;y^G}URpx-k48qy+9J;EsaE8(q zr+XZPv40)yAA^g;Ey*1^K;ODz6`&)->(HO?EFy+ClWL#lr=HX0+@>eHN>O5WU%9wH z59Lp43U7EXQ9<;;)Q4MhJ%Tq4r2)krk4|K)Ax=%-etu%r5^l!8m71jdma;zWemGy1 zHB~j(Y&Lg9?de|yW^1B<&q(z~(L;A3Ht6{KF8o4Q0I*Lu5TFOTXES*}R99&K!^@(E zT!IOa{58LtUzUtunde0c5|I1rTp7U^#@4x3R9n22+{d49rO++b}$R zd8}y2B1(;$acS4A0C&toToZ0_w+SEMBC)UDK|$Brre^1N7knP_@m{1ypAzU>ZojST zMyVH%KFoS4kMsWy&*fi-*=@3P&4|hV&Eb1`)i$sFfKf50jyO~xm&N>p`(yyFTDsD!Cuc+)Vk!<6mXKRs zH=qee9tFAeRh6$rzXxNMoie%pE^6!FjKWT+DbH-xk9)KfyDK#W zr0s*4hM*d;O`f@U7vSDW{0@oB;G2<82korkdQ&XH^Phq z%pPuYFz80}@uq)sAg7Vq2Rm);G0st=Ar4?l_YD)nJqdqgL4U3re9hDi(hn~qXdOko zr(aKAn$05mOfA?=_}-!#<{B`k;eS0c9+;P*7Wau|a;yuhZN|U$H+rX8ez7}{G~l~N zhNx{_9Dcg>J!NfPn6oiAhtXK-59B^VAlNehq4mO*@=Q>t~ z^%_^nA_f`JD^Z^GKT#Fx&@_;0ZTf*!&HmT~rsL!z@VN8}-$u8z`S-_{7XZztpjf~y z^v@LFC~q`ZuWNv=Ft&_r@n3=`3!c{TQQTia0M165QAPDTFL(!HX@bBsR?X~|XZVu9x`SvRQtqF1$6>*Lc zj>Y%_{Lrqe(|qFY`!u1Ud(&2|$>{PL9?IEqP%~6^M}L9*$#Y7uG#UPAhr_LOdWxV`^jUCUZ?`OX|pdRT%glB>7_&0Pvc3B>=h7biGDCWt%mhJ2tHBi;9isv0w)m? z<-t|V2Iu~&iK85=woL7kbrkE2+w@OO_WqQldrx)UN=BdO35Iy$v%j24*{?;=^lG@_ zD|gV=-PQh6Q7rx*0yexdU8#quLA>SzQJxFKs0UB%fJ3UY;@|*FAqT2;!yO&vc0(_# z#}>uG)89yUdgkKlXwfqYe@NgPH8p4gbZY~FpjZZs8&9q9Jw)P#@DyJT$kb`kdsJ;e zSgb7U|FMy2@dF`k4wiI}lWR{G-tY`hVa0N^iQ z!3!KzqBU*g&Kn;=Jo;^G!+SUH+*S?sr1x6*R|7~k75i$oRDRx*p+KvL!d8*tNXdyo zBR4|K6Rc0X5o-c!bs%E7dc<;D@DnV8C5uG;rQ{asRK~CGM93i<6 zd9MRu?lDS5W?DbkDXUuoSp8FCw|%eUJQB!v69 z1p>F^9=_n}y2TzsC)XgnopyB`bw{o{k!0~`6(+H%#`;W>F?tV|iqAr+Sc`luRgdt# zYLn)g`1g6=V$0QAx7}Z?nwRq8=Uy&$+;;}?=J>Hp&O)}@-kzCBKIX)gsK8w4iD(VP z&2o1*x8>Z_N=cx+d!ww~R>Aw+R(vHs{k5)1fU)%3oB~6l9hN*@5+oNyV+hjA<58o9 zbi0TO9R$wqzV3SWSALpsA7@sf-ys#Ji&YD*9Q{7P0K@^TAVaz!jA0N(o&^IR6R~+w zV)`LM>Ydi-`v5<+~~wgVT{3v>_E|uFWI_x+dJbOCcL+w zZf!^ztTS{BQ#``?6}KS4oD-?zJbj*MuBJs_;H-n5eBsGm)pXziZ)aE?U&X77d79zi z2a4LIzi+*}vB#SBA5W~5X9RH%w;*YRJ}uCbumWB&K{<$3<-zuWnuqmka&=|K>SBBw`0Yt;!r||TET2ltBK>|(LfVozL-uK~; zPltW6jBcvp$%(-YAM0$~s5DoTrzpSIUbdkQE1=IgnHmjvAXS%t^_noOAH}_%3k*7K zu|}&VmtL_0*Zg=eqcU2&Q>wk-*ltWHA%0Dke4s^g_(yva_@jZgSEe2D0rl(|dUD-! z8q@HKseIO#{NZC8*=}f@#-YH&y$8x7w9JwW{YHPYym*J%LODpH|0IAVO@6e$SF*CM0*NpxR&QrV1YNn+F$~o1!*z zr(di7D6pO-$mCL{c0I8-L5TPq+qlwsYe z4(Y7)9G^6LVrOdOa49Cf7m^okLvvcdIiK;?nAATdAwak$y%1du$=Cb)t)AGrP}%?X z$|gY{Aa$;!cA!G$r$>(Zl(mxHuYO#&v(?4Bw!`C8my*zk0!*ciUA5ec$|>Y*zEhR) zt&(_W9l*(nf{?+QA=**Jd}!~digUB`w|(+=*e})ZS3L?}kSd%X8djHTA)0E9hWimS z;6Mz%`UV9F$XM|TYj$2R+f6qE~6! z@GZzg1@eh-x;ETy9RK#jn5l|1S`CMZzrK~aOQKKG3Hz6Arn3K5nswS1XpW;D|wR1H6}Gm)qGCrhW43vCF^7@Poe;5?WBKWc1<@ zB8!agY_en_ZDcscKM`YnbsN=fu41^gV5;UKaXy+Efl4;cFL{iF>MwnQ^%V1c7 z)4Y&96z|wyz(44J|C)rRO2i%m`%Ql=x#1b$9)9*`5nKBlc-w47CWgchseyDPWz->Z)~hwe9JP2}*5{d56vX zrm7hLk2?Fqs-Cc~fY)r0O2sOen1uMku|yRRHZyDvw@CR39VJG2d>X1WHh@L*Wkj+b z=jgH$z9UzzWtfcW45~%-!lj{9vW~||QqwDgsRu0SnoXPNI`B9N`DB{)W}I9S91G=H zMy?Xk*f*0mLX9I=?oV-#brG@`0%k7u`nD%|J1+H`cwDUJicMGkfKuW~b9|XVhoK2Q z>9-%s@3ZD-CoXldwB}0KbZQsaT4$e%9elR(%$t^v6g#E!5L(mmaNaImCYv<*Vvh3t?N%QVI zS>McTIpR+!{@E59ingw4f&0#nzYLZDa%Z=IBS1-xCj0!-96EHV*39H!>D7VSK(z16 zCM`Nm=qm?0GDOCY*R@a9QhFM-A$!amtM5H?WvF?8A2=2KWr5rQL=Ya_1ZcVQc_4Uo zrqUK}ZGE&ZjCX;!^||idc+se^CZ;x~V#*B)Yr#CK2?pU;Cyks-Q#blxT9ME}Oo26g zRe`L9W@N+b^Zv1wt$|`YBGb@fNFxm3tm;KtXG{c7Io=SRP%SO%#-$g&gg$& z3Ice;G|<(~j;{5T5{L0X{P<(aoO<%g>wC>S$=H>W>|qu7*h&ZbECET2E%NM(b-R)F zB-)FWB4Gp6NTYcEa@2aMy0yEp+#Z(qXei?|X}`|%Ov4sMLk<4t+48Xok`Gh~4xo`L zSly(taNt<~+B+1xnZmE>PZiIfc^H{J#aA+BK_*=-9!D@CMkmH3#xTMcJQr{p1xC%k zxjC~VmS5x9skDyLezSz+zm%8$ld#7Ie~cN_hpOZQ=U6n3X|DZ~pV9$Xf){71Zz9|u z0st}XdxvsVXcGZ=y0W` znPrb;h~@Mf!xi*weLzAuN<}=or5-@lmUh1KA-|II8~jE5Lw+8=e#AK@LpMt zrx2oI0oGNgeQIF|`V2+WSESIvC{HI@o+fPo&>NnGq!@2N)3J_VY43bK!b;c*en=BHK(j zsR}imXQPw-?YHoE?Mu^Ql#cyp>B1+~Ff9jP z!>MfEyt3|f*V_kl(N>UTRW{GvmiY|VRtZ97Oa(S(JHjljtdP&&G0r4;+CuCcTv=#$ zcphExl>!mN=wGkMDit)b;U)<@%B1o*&mQ5e&^Tzn`oTkk#i=t5X8N3v)~| z#8H&TX*4iwiaIcq%L2m5#hOe3`ZG+u#Udy1$^<8FbEA#ANGHlELAy~CLu`jB%4x;G z+=v9ljDEf6BRS!kYE8AbCOB%NuX*3(yqI&tc9+*iSWvXTmTUXHVVvD_>Cs3HT&c|6 zX*xiwAZC1bbIp?sOtLwrE=K{_#=^*b{*}?Gvn4s41#&?x(+6YrmueNy*;CJLyL1e7o_MjFNPZ%D;*(vk3aa17V+i?CVE!1oXZ(N$Z z#PWV=4w&FV1L{zXIO!9$JU$=};i6QasUK~Set(h0BpqD0hYz>c-5H9ntg-sVsy+6*t0=i>4?2= zx}%Tx)Nl(sPV_zq=a82s=&`cS4r1veLAsJxldJI%b!EIfg(EJHF?Q{0(C^Hwzw37~ zc}B0m{LY%>uu&HHRp^t`#(xOMB0V#Pa9r}*lobzzX1lQ+;aV0z?fF)X>P0DL;~=qq zo6gwarqNA|%Vpf#zYcskRG-M9_OqCNtCQGSk`{73!1UD`_-jTVwy1YuDg*Kiz*Pjb z$k-6pj#pjb*W;S?Ol)jc*-QvJ+Oii;zJBVRY~ z(dyd3fX;gfw4w||UNiSSmq@>tcP5n36?I(C7x|KID0(qnQ%ylw^Yf#Ng-sW=k8D=o zdr`dd?49gEr*#V=jX!=Oyn{79XYUeK+6UTtG8lfRb-m4w(u(GhYUS?IjC$k!va+&8 z62~(NRfdG`H8u7RM?ZSorfYP`M>cREq+xqW7^g;RouK@WFP-}OwqfE!_KuS0bhnby z>UWm^iuEpb#={Zofy!y>e2BM0LEvaE&V`_4Xa<^6JoUpSR~PS2oW-x~88qFA_!-+t z*mDIW=61UKl@8WZ8fpvam^XENEnD3@4034t9mJ@gZ7Uj;qp{%gqcC6Z#{+casM#C z2IdSIPyjvEK{U!t4Sxbc0xi5koS)hPTR6&eU&m6+kwiZm`rOa>M>%i&`Otrm)Bf6xVgZD`m#KQ!K8 z7jQ6?=K4V5h)5b{5T>d5Eg@s6k0m7fy>wAsS~SVUBy_Rt_))j?HJt2iQKpb^{j*Bf z(0G+(4V}(@2`((?HzV2}g}!>H-7!+3-=&#Voc5xK=HzzZ7u?Y#{+9y@`r+{{oB}0F zFk60^Q@>tbvjIEn6}!t#b&swtTlzQ8(#$p<5^L3&KU^Q7An0y8bQwCfCC2Hkyv}vY(H76a zRx+=$a*2sHe|{gl{;xb|1}eF+PF2FePZ5YqjtI$I`cyzY+LKYTrgjtI#|9(~ZFsD) z#RSgr!3jn7p{bd0K*5sivEfH2+F?ABV!2jiucYLwLd1VwA@zm<$aD8ocH%659<&+J z7fY#m2*Vn|svb3cb#!q4Ima5VS21#ruMaB(wPb9r<)i2)uiDr~Sde?22X zkw*v4)^}n_Ow||y`Y8Ps+}4h89L~fbGir3HvrT4tYlAa27lBpH(RQvQI$w{20@x|_ z!@c7^(h=n=0Pcq8-6zelJ>PR-Pn?b9g^F)@o6WXRABLKwuA2HnySif^tXL~s=&tnU zGrmRWJ*Us%W@iX)#Q|$-r!kE=caZ6(zfTXP&KG?7!D}W4VTO6ifllVSzZBblpUcp{ z2-Vzd-kh~B0LY)YF>1-B=AUWJ6EACY=b~rhz5s4-tk5UF;BLf1lx9qWO2A=e@Om!| ze3Mxg5ICi~s+t~PQGJmZz|mJ}HtgPTpO2yOt601^yO|m}0nWDaJe~da&GMxL7K&Z- z(+zk{e8Fh#U$y+@I4kXgl=}s~+%ARFRkubHX`%O&W$@7#2wMmj=t7Mpp#R#kZ78Y| zH{9%E3nBC>O^~^u0ddXtf*bD(wOYu?aL0OZlT+!zxvp=q-AZ$H=Y|i1ZF(~=fyIRc zO#?ZVv^4uK6vd3aAJa+6T1gg~!%1?Wy&0=TnAeJMRlUh@YNbBepptR^P6ph)e!3y z5J{hhWo!92_d>S>u0fvx`DO#InHNk0pv$>Rg*si4e-oXAw0o?WP?4yw7B5PdIfWie z&(q&cUlA3M9wCN?!u|KmrVDQWrp~f+T$l#0>U`^3-9|y@xJY04f*&fPfPrwOYKTa> zI}^{Y10N`J_<^!1c1ATAQ3tcRfO&R(gJMm|TSNjn(`$ncb*z_zS%$6Ka`bV~PR)KmUEH{H=8 z-b^f_9}6fR0&cUt z(C)-`63~W<2TKZ?rg3b&~27Q;S~|EK;#Qd;sSHRol*ZB4=MU3qtC%Bljty z5ot@d(mz*U2Eg!5RN5>xUTy3ADvYZus^zVUn0s%q)#coSk~FbIL~p^NPp?#@Pf+W3 z#FG#B6s~HO-%9MDksq$X zoyyeTZW?zIg>jPOsiRUxY5_#vCtu%;+JGE(8juRm;}4TLz+Q*gE@%8yrO{Z6;y>@} zESMQPxKLI9nX`m1pc=f;f+vgC*g5AR&r-UByALlkwT7*KuVDs(MQ%iu_l@%g4Yhc&l*`Yf5UxMKc&DOWuKz>G5R``#CqeZ12ZI~s+Ao{0RAztD@=6WF zZ(y5u+`dfzA4}c%e^@HqE=3@F9D)hwc;-ci?O;~$bDTQ7j_@C+M4-PJ7+KgEVpg-^ z+#eFFC#-Kx?IB8u^axvgqQhuqP*Zp0J7Tu}v|AXWO5z=#h#JSuP(8u7_iCAymxGhH zSr*CMqAq~jdb@>Yu5SCMGUk*9akTFEXm%WV>NN0=_MA%l3tUf!maT{ltkD`~#BK?r z&n}O20BA~RdsAw!XE46lvOxOuAslWCMir>}E-iW4=;+6CW?+Gmoi`KT0e7egd?s{t z3Htpw?cqHUDQaL1bR`}U-bO{D12eQqpcf;+>IEaw@yc#ba*#3}58f}hu~??)swHEO zU9kGWLHsT#*L3If+I;Xi{a*?d7Yet=ab&$JzgLH-E2$4XH%n>4eFv8y7 zmxlNc5qsNbQfYx?EESre|Ko;#gK5Aw`UQqL9YH{$pk&!C#TcWw&H?7Q(%ylrkxzBB zC2+`4fmW*<(zG(Qe$A~GgIx!CRifYpYD>0vV|NlIIatyctSOkyQTORBse-gNRDm7G9fT z7EXfTODY#W-J$9YpQLHVS#n6#-aIElebYJI~<_i-TcYEQBiQD%1Uan_NM@MJW`;{Ox>A~-@~|@ySmTy zRSU!p^A!2AIBd8g+|wM8uqB#`51Pm7yQB;tMTCJBdbW-UG<-Wu4tx=vVLMOTPbbmwM|A)Q61(Sx18-$wK zt5w>o!&16RRKUzr{Eh5R3Z?7k>Ysa#^{%cq7Rn~Sk}75S`HP()f}ZjrMFDOQ$0tol z=*~l4S*EIO#>$xlcC(f3eqBai-GcbC7l+wL=us^(%0qwDuT5Y?)fswb%!J$y*8cVK z6NxQn&h@EJ2uZ1l!^+Y5E?LKJa}`ExZ_Jl{>gstZa@Y-4-)Ih&o=c zW=xGd_Vtftd{36-B|EwJC&iTNlBst+82_Y}M!*?-hB<|RTS|z|wM?V~fo?%_IjiFS z0L$QM_^jVUng@!waI%-VkGD*)@#iX_mf51(eAry!2RB}9O1SI8^PyMH{A|1(52yYF zDlP-tXkf}>MKY>lX3m@u5r(w;OdRA^9oo7DT{(3U8sVXXMOakr8aV06uAZ#PCeLxH zhXd>#bY{71QWQR@vUr7yI)8w9exEO(FW~)WA~j=b-?i1rVCC<9EjYR8r0>0_%_ILZ zjg%u|5<7n8^(X6sZi2P&p^efwZ|U?)$wSFp3D-gkBzx8ni|>`!On$b7C9Qoj>ANRU z9O@`;`p?WUzB!G=acpZ4{h4p#Sy7nbdKmvBtI+JL%Tpp-F2dRsk;`gp-1^iz<6-K+ z3_oP9Hpd9y31HNcO(<(X0XhfbJu8NG@{+k4Q7{DP$%XKVs2Uk0<*HVsizWoiw{uqd zTrqhP@gmG{PEk>CfyL&{<~tx89|y33a)n$;IsdN?NDc^%65H5;V6K2b--wNs(LXeyaq`H-ijH2C=t2~iR;%2FVepilB^ZL zF=5m165*0Ru$KL_n4qjBtwJn-+ax4N5pU!%^pU4FkB)<<;5Jv?`?Hz8vVvxf2VOBl z;26g~S<3IEcnNVeJ3wMS*6E00^65*G=lNiK77x{kk39i^|3wLHD8`#?y9)#>f5 z=S*FI6ZqByG~7;yxlrryv?88W$E&1(^q%q&Q%cWcSd+#?jDnu_nRz$BcN08cP+bKm zfz0fMux^t0rt0%yTjplG6GO%;($S^an5G47lV$3VRnWn(1r5`Na5AdlmAL#oV&Y?%r|0<5eg!#SiAZzhZB;ff_`rql;QVlB6yY2 zGF=EsyP=>7OU>k7n-Xw0{RvOYtftCgZ!)j`goGugylFqPOJO?OVZ*r76Q@>f58u%3 zdc>^;-!T0ht*nH)?@OJ;jha~wigv|owytod%a$YD&BCNj$Lc~}fW?KQMZ-{UJM|<3 zQT_L8?N3K}bJaKO-se#re>;3%9<6nC9MKXmq2xfaUS=O>(KJFr#Cq^$wDGKXV-ivZ zpBO&#ao}}Awe|E^^a2?oQaIvTjT)xT*UiB`2Oz^SKh<%cVz~;LKr~6*j{d4l9jz;o zAHwn)zS6@jjRSGO7vkvkXYLB5Pm_@d65G6lePSviDNJ)iTJF%|=F;VLt-mcXOw({p zK<5(W1-Zor4fFsEY&tdJ{vk_KIezu*D)`>qzMR@gSL>LQ*N#j)!j2Ex6Sq19)$@Q|cQ=r1wtPI%R4+|`kC zBPIyBG~Tl53suhbon{cw?#wK+nAhm8!`yeuq@7DcOsb%n@q-?}Ep||CbnOxG93X?H zR6G6;OQ?vF+(3tE3%xy8C&7Bj+Tc6tMhjx<8e{>T3B|VB_wKZ{Fj; z(LZQV>WN{lY!Pi3lr{PUBz|sf*}l&7g8Y#*zCw%VjtWtindnr;(Wyai;-zdTViB!r zLrdh?I{`iqNAz*P@J_aO6~Tyf?~bKA#J6%D-@G$lwQ1H|J+{^u%vyk0UKdX~KjDvC z1vVDsi+gPeD0m)9r7ra)6)|f?28JMNIp|cEq<5VgVUE`D#WqN1e;HWHCCzHuvA8fP zLQ}=e=76?dNyO>(3Z*@oE$c1)>vrgdn* zUds+YW6Cz!s4_QcP^iccMcAq<^#{0@re^~#<3NP=e5VRQ8Hm+ubzk9j8_^OLXaRYc zeh_^%g70-gvA23j3vx=GYj&BmJ=jJMoo7^364R(NOGj70C*i7~o#i8n(%MW^NOu7b zJhf>PHa~5?+gZ|HJ9TNkQ&ak7j5e#8Qj&H6N3{#RKiQJ*A}% zwLX6qfYD46S#~djX2wrfd7GH8$jOC>6uf!PomWSot4nUde!6d{=1kB)PL|L1_d4zX zk*-1xdW0WU*mPs9HaTp11pP0>1uVW^pZ%(eSk9#bho)YGAoGR38=y?}*45_pE%4W! z$b;MjPJxOvCxp~~5J1bwV&5q0G|iek=nr3SOBZ?3c-o?f&e*pe)@n3XNjdo4?pwL+ zh1X@k>$dQu+IzAUme)UVqFJ-nU+EcUFMWBgE>fS);QVj~1vpUl5!k!LB;6Gfr}KNuI%JY8K&9;cBT zmwQTIoMruBIIc@8$f3DF3o#-%!JFBi0kEmc=EA=>xtfcn*3HgAu*{faIPy}YHwX|a z4IZ7Z^oq>x4Y^wbQ(fK0EAGdf*on`>5|p}>M(Rv0_+xiAnX+Oc^HZ}zw~o0!dAyxi zAfAyb-bx(!U(4Y}DJk~bi-e0XXKgtdfY#JMakPP|Ln6_97!h;`kP29Vm%_luQ=K<_ z7v1SD`cux$ma26;$C_jIM3YYP=8as4107eBcmncEGd>fB2HlLa9rP zmJbJ3T4+y?7W#UWxo1p~I)shtk#J&^u8)l>Op5k z2*f62{?vx^w`^{XJlYR(V^N8s5*u_Jg8Q%uZGm7=VP1N z(ujv#g5?At^84Qo(C*b391M#o2nh;uajoC2DVU-mVdWo}0qEIL%QL4~6#Nn#K%i!_ z8{62#qOz&}S4Qw<#6c7Ti9Nl}uQi2PK+cSpI-4oyw&s?kuJpqeoe{N$=)aOlQ$|<% z77H8KIj4AehUmh6>+r~;9``fdjyHc-Jl+++c&YAPp}VOhut}ppqSE%S$MH9PW}5D^ z4MX+>)?U|*Xm%rPBL8r^!l97jXvxfr3%Y;xFQ!ZE@1qcx_lD+_mhA?%>mrn(DH&^M zV1M;Hb$1bz7e-CKCwgoetJ1n>ZjMfGA#KTThptTDm& z!Sy&L%{a4H*#p_BE7R3kG5VyA(W!5#SkxH?32Snw3wOmKdd_@Vosg%yg!k;l2(AICd27HmVOpT{^<@gRx=)>mAWGNri1V+5pz zKzoJEzQKEQp(BXKU$C`>Y`)*qR|}{6?(X$3z@$jxBbJF(5HlC|C?P>aox$IggpWyS z7?+Q5FDqpoJJ!p8?Z?9XP$6h0oTjQHL+$!TTc_!dxI^#HOP3lA=rQkMjCJWm zi_wgNe(?I?%MI3nXTo>Zq#FZa={13T;LP(i46YsX{1#FeA=$4#Zj|yY$f(&=5qdGE zlRFSOFjn)`$x{#vYSP=a)N#XnzHTCx!L3{NZOG_&S3-aj>47yLy-=7+hTcLt6Osxo z5NGa}&E0bDPCiXe*xHH4L4G6OpIyf6u{h+=>mR||Uh=kKU*=U0=og4NJYu*8&pp|^ z0-YsnD1K@V_zU3MNIChKKfo#julEmDsI*n6DQ*^yLzwjurbAb48l=)p_T@px?J%TdI$GK7pz?D8)`(Pq!LvAzs7 za^MS}DASi;8hiQD$SiNg7?JnA7fR_u7}5c^`@A-Raj1*U`AeMfKz2tBqQ>BiwZe43iUT3ALDq9X=HSRWkwK1q)e90@s{YHH0Jg+Q?%^ zEiu_IW>D2M9$cr0CcS}4ug+m}Os^{EdxlWup-hIsCHTB;1zVnQ;`2if!K_pL#kXX@ zFxS17SBgzX6N=YJj&wK=KG6UedIOn%nuIOQ%i4i2Q3)cP(a0VjBcE%1_|0@AfbzHCb47zz8{6bV*eX)Hx7{Oh-FlbD}+ za6A!ag|EB>vp7u%4q;z@fg4ffK5}xoEz9MiOgR0dgv`uX(J#-9O#jaTiFN}U$L1IF zC$f>%Q|nLPgDO_)PF>J<+`0@kT`*6l4+E}1^eR5dbZJKAnEu?s$TtxN+gRzI?vqZV zJnAw|sM{&uKf1gaB4&pkd;s3P8phT?bSf(W69bzMHr8v`Ys>7_xd+-*Vxy z6Bzkz7*xA_`Lg#%(DQ9;Xf*79w)IjN0G8S)^P zYpIi=Ko7)&78o`so(itxu~3G%Ee@eC`E(-CY>w_K>|Ycjc>A(L-YGQz~FQ9)WZJq zil46j&fI=mDaGvZ(2g|UT+aU<>q zyxQ$-o>!T-*frP<*w>`%nW1T=j8rSQLz88Yfqwqi)8VlfyNmD$msQJ>u(l9!U)T|m zihA%L@UE|>P?nj3mI2htIy0*J3~{p;u_opvMA(iWr3DU_ zBkuVZXlgEeyK*=1JJd#PHRNYAjgHzuj|GfAzS#)r@Tb_x09Jr*z-in?fVPy{`4s8B zwyWU+A~V?gtdI}9%XEvDd(>HA*yc>>@61c|&~iQ8JaY?@|F$hQkXx8S2=RH^agbp0 zz(ich7d`=5ORZszXn>I(&GoHb{o%Lh=w=>s@Ajl%QaPPi){R^JP$8lR=y1;akl{AR z@Fys>SUA*VZk^T~a+AXZ(cE^b;c5&<$|abFmV6n|s57PxLV1i1q|Gm_+B5Y3;wu;7 zk$roEU@U&i76zpx!g4+RUUgPF&1zS8+)C6k9Mo301XBNmgtK-q9ez<$=+3dtyOK#Ag~x1*G-`bwc8r_Y6qq`j z{@dKIvEjTxQJu;KRJ|Ky(3itmWRiwGmMoFB<7(MLC~djTij=(Gd-uK?hEo;iYrg_d zZH9?yYr4kkbo)2O4;X7?sb}Vr3U+%?&%P;8G2np>iFHy5P?1;{C(FYey6Jbp5o(_l zhFoherm-!4b~19b{v6Ie#}iUFZvvKvMQ$ zm13ZUQK~+G7yNmu?mK6kX}F8B{~ytPqNJ#R2#khvq2KFX&i)~k0jZ?7^9(ka$7(ft zxr9ZOzN=tmY62nQ{oRzJ`U6YGcV%hCpiE!CcFNj{!97_9M69G!G|)Smn9;>M~|mq-1(Lc9TbP3deUsnVZLUe zPN-D=VK@t|e7_5!R(nU{_Hlas2_H@G_AAk7g&IY~UwWU>A5os~8nC=Z2}NOcj8ozX zlgn#{p!sLP$rwV8+aT%ti@~EFo!Gs0wwM&j|0f0iTl;^M zAY#pz$RA4AlP$PMemtS*jb#F?!WP~NB$I@ocy)O>QgXYE{S;RC(X~y9H?qydSSCZb zu5Gh;{^b*Wtb;vOE6%UVk!PBS&#HQ@K>QN+XzHrASZ`o&vD z0^#g*mlhc>|GK)iNWt!L)eOuU)IGPfTIdaK_Unhb8I+kT~L z&=vB&-t}Za$Af>zLe-x+k&|0zETAK1nE7LfQT#TLkbLrDl>;MeGw~Ch{d`8BrcNPEv zDn}@KSAK`4w#w1PJ(-y8bab!h1|>f3#NcMjl9p12<%{KKgWr5}GE9hpo$cQUhQY*g zuHd8Hq>W|3uLUdfTsbdK;@u8Swo*MvZUZ_N_0w#W&OeaS4xaVGa)vSnHCN%8Re`zF zgGL@RGGV&hzNV!nns|#lDwD*L?LuK9n15WgVt9nnd)-d+FPJgNtmc6$2v64#&#f$n z>tNuD&y~Wv)}5@#7d4-$WS9+{+A| zmvK=zuec&bmx9f0@&Zd;- z6~MQuuii{kPk1NTlB9_z+o~(puZO2B881;WQcmd_|2{GFey17V@k*l5n)}lxrwn;t zTLp7Bi|B&Pc5ot}(mGe!tzH1>k?v>J-bm&`rTK!erN0Kxdjst^BxsTda!Tr zBxMWqN*jC3;Mk}+b6=r!7`p%o?o10aGMq3zs6XseI)0~G=}ZI(4(9@+G~}J~EL2A+ z>7uf!a1SdPZJ_{EHbn+`L1K17GDv@N5EKSL4WuYm5!X}=mS06L=+RFYRBBE1y zmtSmac@Y%{GgIhL#CZ7(Dp5&=n>2W*VRqv+i?PC9`#wzas*my#JfNN1m!1Mn9CPhj zA!jFir=*FMf%?=|D zU;#!34{X>0>O8eM*_cHh=>#h z0FHA`j5H_4*)BgEgJeO*sg4#AQh_l#og3{9d(d==u_)J0eUb{DK*P5tVef}lVj%oy z#wpFl$|K*Yx)F*^+AbCTJXd%YE8&uGtk9Vw9(sxwE3j5 z{>W@q-y?=Zg*#!UETbyIK+Ze3{Cx%u?>AkNJ@~!#3F|>Z;{yZTE>^8bo^7c*nJ&xR)^^vn*0yW0f-=vUjTyXOY+=vEmL0uahn1p=8 zE3ijfqh%0j8uB;W?q|Bo@I*t3<2K~A@ITUk5EOlNv&yV2JE~Ok(#kgt#k5CyOPw@9 zlN_lUDH1LC2APdLa)z``7*x0ep4=6#4g`+WWEo_=eD>te0A^f78o(v8dt5153 z|Ag84ikIuQaX9N0HnqAG zXi`*g?qyFa%~Pir7jPKtSB^UwUb8!S8rc~CrDRQa20)CT@5qG5ur333eG=WH!T&II_vW{(=QV#zG5K{0Xd|sG-K=Z&5;~q{oHzN+mgmca zl0^htfAv&$Y)>(lGDnJZfj(zMwFGkVr-SL;fb7nwFKW6ZYFgpTta2#wgom=Q&e zsK7X8Mwwvp54+%CyN0#DjlBgva&pcRJWdM9KlcYYYdJewng3vEyni#|vS4WFGnvuQ z+82~q`~IMkt^8TZxTgViw=kpmds}-!`n(;7_3PU=EhPbG=~d{TQsZ=0X1m4*B=5#d ztdQC`Y&AH=bp31gUP;D`u3D;$9R1kq71XygGryH>hplE{M#V_BgXzd*$tdp{{YCy> z#blGnSTUv>Z9bU1Kk_s<(lVmZA(F{su2B8^27teUjW<`dP9n!FBt^bPy6uN9@fl!_ zhmB$cqKb;G^ZBJpd3&VbzgN4D-yGEWt|D3{)v9r8;JwwC#sWJvqBJCG;ADAi1YHVe zvlDarAk!Fc6o8?|cReLyIRO7VyeL!`y$a;< zA5#i=n{MaXb4CLQFCD}2%SR|PY}vXLjHo~}$GpgBF3J^sko2$0`M6A*mjowJp~h8G zk!XD^@ zrF^Y9KW- zd&RKp8OmsDdNvCl<=RQ~Pz#S7=fo@l)G*Y3|3FwBMrpg`{FY zn*tipRe!FKRbs<}{GG9RT2RcpEBTdWKJo~WC-a#T6V02%M|FnI%vHH``h82uqC8uzo@7I(>$9BTLIO@a*f!-sHrQ-ZWii2~ z@>O>imZ`VWQOX5$fvITn$ZC>3JVp6=DSys^$iAgcY7J5SVCFO}+5+RSLxMh=&wU6S zZO5A$qIcfYf~I^u9l%25qO8w$HM)6-fU-Nff-^5sF%_jbl<7Kl{Am6TGZlZEmFYD& z7@EP8ba}OgPeOUKtL6iJoqd}vD_QcHXMy0I z&Ew44yf|v(nQEW8ncwsOm{O>jq zzeFY8aq1~^hbg=h)GGYTjCIGq%r-$OHi-5J!UrYfOF$rcU_}MB^f0r_gn(gXvNY*c zZ=b$TYeBzqOKbEqq%i#sO+Bt6q(2U1ZOY~$xY15>cy(a))MsC+o_CQj8V_r-FPQZE zsdcpp3mL9mk00lK2+=q1LGY8+u6kQoqi-d+u_nTew6HeO)wJFXn;*SrGy{Z_#XPgiC6o>M7h=yuX^o9#{~=}4)qOZ3*eLr^A}=OclD85dE96nX?Pgd{_ow2m2c_+I zRg7zcp4AW8IZ|P>u8sD!6F)^99oTAV3Bu8mb#R#@tmxDb_!B1#PYXT;B&Boc@5idU~e^lY#|$!!|u& zMyEJoGxvV;l`rldoZI`>vpiiDT{XtZ*Sm4IV-gTt>kb`yLa)t7?P48(a~d{LDOP%H!BwFSH|Fq;C3(PbwHlYa}E1=H2yf zAxAiscWpUP9%v3zgtARjb{6mF+e6t-``0lGl&fF6>o>^0E^-gAzGYGuk+;XK#z4l{ z$F>c5y)RaAR#0>+<&}vZ=oRfQ30MWTW98YCtbm*1cFfeOB{+zgMja617L7%LpJbGH z(w8oX_m!dTe5p42+|0~y3f*fep(8EZkBrp8GUxbIFqCtUHo|ubtTI#A*ApSFmRw6r zj{YSxX1$xJDJ$!O@xj@mHc{VOA($T1`PKKQ--bZ$-hPIdwH%ZzCnWcDRuf9f z3;??+yxIu-thdtk;4OFkLaFprB`EGM{HUz#`b}h8(3U|Fh!8$GMn%OPJoWmceRV2v zfDa+qPM$D+zN?TkpT4vF&R|WM_oqhvf}0!6&0dR7AurAx%ErDnS|VZ+6dH&AXE$Eh z0PZve_l(>wD{lD^%(+R8!T`IJ3tI_Fvu&4;JIq>l1KF6t}w`Vz}*Hc-oc- z-S&f^22)RTC(I?r5V4coQ_^Szj>`43d3$G~?&p`Mobteirw^eY^>0rOsAaMYmW*Uc zg&2jYK4|^PD|9IN1g*`G?rz?MNkN0>pThFP_@#fk)jM|s?G~(Zw)Xb!#Lb^tGPpS> zUrbXpig6#0rqN_4_J+l)`wu02cp(79dBBMnchq-yEI`v#nUPZ&7j_XO5yu{9;b#s$ z;tIyUxyx#Lv8;C(q4Sg`j^jyzIlV_Y!D$Ga6#NjL1TTeezKHu$&6+=&Z*2{Xe-&Ol z2iIv$T$-fEW=)LN8)3dDc`UrbJYh3JN3fK1_1!UjNe$rC0n9pHciL)ZD|!@5>h6Zy9pjaz4*Qn)_96>RkURK zr^6LwYEnyQey;nx8r!80IPz!CTzIz?7{<}$14#>n&Y8D#v&`tBS_nD2=iKN*{smU~ z1>D=x(KGMLThd$La`>aN`s}kRj+#2HPxU=!dmmBlYQ(<_@=JJtf4Yj zt)EtI=rqzv(NL>NneWV~b#nr##XeMe=lrETCCq!}DN(G21)Hq$fUa+?Bu`J*e#%&E z+C{39Zc6A1Cn2L_Y^>$Q)l3-7>MzY$D?YLAiBoLE23Jnzt#uw&{$(wE{uE$1gVugd z2TirMhXS&E5k@0fK-xK_EsxB}?#vhNL*}N|ZKm|gw$R!GYfizB7}5o(b)M)YE`xgT zENDz4EU+PPZE25P`WuDAP{xH+z;*Ell**^lhD+vY`QyX)^b4VVw&a=|E{rTAtA{1N z5YcW}a4>D+>9%TnUr%S`JxNA(aNv3tKu%kN_x3W&J|d!GKgG^&vd)}eM3|&V zH`&N;{f5cCOMHyT$8iw|K~N*hk5qir+NI-|{h~$58S;!k4r^rpZ4l=R1<{+yPl&^K zu`NYHe;&YUYInG}a*h83q_|av1NYjzrfh`<^hzXX2L0t46a|$ddNUVmVGJJq;Fc)_ zliP>eTcbjsSSnQrc8Fni`(envPedE;19mw)niF+?QimZbuq3z;2zzjFv5*oJr@oU` zN%Zq4b^L*aZl|1GWLfR?vMj!w(0>}}shQfi?>nBSd z4l7ZlT{{w>a$oWfbSwJ_{8v^NLV?w@v`92Mwb)6=K^7zZ)y}8d9 z+)8PyU{|U>g-mxMaT0HwWBYKwsx>hJK@C*myRr=5wCoc9TDX=)XrWp956WQEN9x^O ztDpb43peZIxZR{Qa(k0nIF)%R2!BX>&1m>~-#t0}K`t`?CXF0!lNa<_C}kYLeD^`| zU&DGmNj=DgdOg-&?U5y4_|X{c@Dq3PKYWdrTejg|dJ-K9+O<710Qve?g27`0;CF)& z!W7Wj5Nw>sjs_2sIc1_RsKXR_m@ZYGOao$(C43QK7$n+9eXk{?>2-@>$M|5Ajfr^N zg_l&B75h6ZyUi1y_Rv!V2M#7ihtHjn;Crp{| z?EiUssTo%jJm!pqk~%uJW*(l9g~X4v^3}SSt5D1Hi#=HqqTQyqzaHk>?2?JL;?dGE zzepMKC70fEue)lnNY%&a)I74N3-$@}S=2F-jE|M9^3`erx=z6*37aeRH8d_)O;xGDV$gHg=;-ag343Cp@G_E|(?+`#8k?qDeaW62H8uykI z;Rq3@IiXRNhj-iXU*Mw;X}M%v7#sUzbk64cbn`Jd=uu{%tGs-Z`fB-I$HT7~u<`>j zH^_&^2DO(FqB1LlcYewb!3N>gCoX#UQ$>s{ceL9#O>6KtIscjVo55!h@M%T0MrZ9d6?yCX0o;2%U@K8G077rEq?n$Wt|m01>gmg)7Wq$)x=l8QQo*>Ie?J7BcKTLUr*xCVe6@W8KAGe*M#;SN zBE{mlx%rflLeVX)`h%1B)FH|c{1x<0DR`e782Vd(=hf{3A%Rey8NS!p*ftyC8O>-* zAtFCY5~37msFQ&V_y)uj-qtSgl)jq2>c4(~*+Ab;iM{$m+=r^19nHH6FUhui7FCD& zwawzBgHk&u1j^^#?`Oi}O1*+lK$D>9o4Fg2OXK%JP~Yp^Gj-p_K}th`5o{GY!|+A5 zyE}?la~~-Kp*z#4HZpwsEP8f}vzwWlsd+FR->XAdgm9REjnkfWXX)a=YRmHF8&ti2 zC(37PvJ zp2{KWdoz5{R0voF((bgCntP>FOxtPKom`{tc{$~3AV+bbZR##h#|`48M~T@nV7~rG zRH;l8SSL`@ud=D=IT^p)52~`M{32{7x!g& zZT0mFvxG$+#M9ztmgHf%C-XcLVI(D`b;%ls?BRX=ZE~%%3@>F;ZW_j2MT|vh5R~j(3h&iN)7zRT#Y2#oa75YXaV_V5a0Bgyz~^5B}28p zjBn$-?g#BACiRL9LVC}pw{VjNMh$>S*9*7OkQi5G_7F=U08-03 zG9D%me}+UIuqsmh2QkjKvP-DAoZ;TymZ~nr8-6-`TAA}`^hw5FP7R~_5vd5JMC5=b zBtviz2mvrCzH%=7WcsnM++~pW*}~I1%uYhl8Vzk;{g(dr#U7b3K-w-Up`&UgT1aQoc5Vwk<}=c9Ur#`-x3I z!4o{goSvLGPTLXtf{?>s@!g~pxaye4;33Y~v?GX7JYteZ6i&Co%oQ2BT-mZiCYx$~ z6+bKD{D-tZgcj{JBY}s5DuGP+4ROL%&e2*Xgt}_Ma|YKBAXv&2nlcXOV42Bh)n(&d zE*(ZW^Uk{Sf@JkxGryjn&HDmoF1bNj=Pb90e!mG+*YvC~YkuLY0x0c~)~<@A41NP7 zfv$M7TyBE<29Wg}9}MA%FRY6`zprR7v+M-f%B5H3jyv8Sid;q=ci0UxtnGO=oad|) zX}U2YeND#pv0mLOjZxUn9KZtvmAHFtqU~u z<7o2pl8t`V?s_q!9}R~#EAZ+^%z`Ob1l;$fxt(KdHma6rZF@j+L80WB?L1h9XG!npfT!S%$XGIS$_*&M?&g6%xTFMxLjFVQ_Qgy{-zHDK;(ZG;C zWX=b@Gky>ln0d-h;%7t?@n~YATy;Xy)%kSZo#*NO1~~}rl&9ZVHm@Ya>b*(95#NL{o&q5=l|>(@`Km2!&q}?WOIQI@crBwNvo>& z=1#=tZJmz2g5QYWlr>T=$)qyrZS^{0;d1gJvJ}n;q#I#0r_F3;h0vnk&0*9z{~?)B zCZC5_;P3Q+L{Mw8r5^2{oW8n?md(8IHL$@E=IkQeHx_%Wkiuo?D4yI=(7CH3Xe@eg%Qx(1DBUgUZgF-$*Luw z%Bz~f$wz2ahNqPNgi-y2wJsuD3ymy8$E-b!@6{a9r0w*82-}I5UVl>I^m^YfS;UF{ zM=Kq%hF)aKXQnW$h|Dve->2q;A-3@|LhjFYSyq9})wWM<7=UgF^Y$r^@&2TLsj-#$v?kV?h2EFL&DTu@`P=)KmQ8Dkysuhqc7&(U z#~ksGhMml#btHgJQP{Df1WCAo$J<2GXx!1Y!ke|hjfUZWhK&SzD<)5NiKY(GsXs2X zgZbH>1+ZL+|6r!cZI9X&8gP>@q6=>yhzzIIa&aimgo{2l2xufd;H!Nq5N5pzVOONlSqa{HdGi?iVTpOesDA)Sz>KW+x`Bu-C#yVKQ!G020N2$p6^azv5CrC;?7xBGgsjKW9U_pQ-QNHcx3 z`$23kow$l%+@@ulbUfdaRIO`IJ=*D}g*&UfVi*UQTSGu{$ew87!QA=+?|Tm5_T1)p z3KW=#j!(B}a;7!Sja$a;NqI*3PC7*P)E|6sph_Tbp;+yz-;#U!Mz47U{YKX_9Yxek z+F#ALd(@jzMens`BJJotTkeo+DA`*` zmChixsdzMY78qchI$L6^jLp%w@B3`CFM2uvX+ltc58bv1#|CS6PYH(I_cm{unNL}{ zAj&^Ru~$q!_EOZzqJkV{Uri!43j+qk;!yiK>YIemxtZNRvXx&_Z2UT|>v5+t@oinf ze9g8U$0!OBO9Xs-iTdFq!+bApgykBLL-3loiq%rmq@<6pmGfEWS4uO6taDJU(Kaz- zk7$lgZbS2D)$wGyv2*VoO`P{DfYr>GjKx+XR-tpEb`*7{VzLa#%j}AbNtk*+F84?+J)&%v-Lr)9KctDk_l1{>Z~>!X3y-b! zO3=X7&Fz>04*u3`ld}Mw;DkNL3Qv?6$TyVRuPqnZ!5&M$&R>F}0J}AjZ()~h>eVM{ zD-}!!n+oM9(wGDepv*Q5|DcSxoT5j%vG%#22~G~>H8K$f8s*q)WlC^Hu`XG;M z2A>>`YpsdZfIZoW?2>9TAfcrF!MLylUqwSU^Nq&x$MwhKw8Nv1Zv~_b3Q~qt?#LU` zSVh>k1x0^7mb$O}9W(ifpFGikP8cJHu~%E|x=do!qoT%?;Pf9-Fu0J5GW(A@%|F9W zzPQ~#^u-V9|7{3VV@4bqXvG`0Y@u@Te`-4AHzL+;i{wP{+ddmaG3bj^F=Nu7F7wit zt67zL_8HS7^Ffu+`#n$XHp(|z9z=9teKbO1g9BP?K1dOLhoPRe62eeF5RB>bFomL@ zuz!ii)6Zw<5_c~w4V(uMMC%bvNXwc;COFv5{YXGUFGJh+DB(<|Pw{_1Q8FaK^gmX` z=h({vfk_OyiFV9qa;mr+rq$l*rTHMe!7^bq()i1)-yjuY$BZIgB8PnVC0ec{abo3f zIqHDw&^%^iP)cPYVN(aae#Jl?j=y-ri9l0&mOKSLrod*hs{$Z~^EP!V8KFg-p>#baHt)*y@Z|QWg#~RQo93%I zx<`-%Aw(YQ-QGDpqk7s!)2xxF!C%&AYH$4t@P59bd+_Plpd-4)HUjC?T%+^}(~&kd zl;Oa(Chfn2CGm%tY$VjMd1Y2 zv+;AYkB%-#jcgnGlE__F;hr>&-=|WX-yl&v?|nohU0)WUofZ$BhMg5yIt8J;HlqAV z469I;SxHk;4#+#Y-AzW~GD5BOp#DgJvEU_;!fwE`9QHnpvw!z=15qMXd1k?7u}gaY zYs+dg(3q@qrDGi}dSDe)ZpusAfg8wsE5nul#!fo=dCDb+I_hfu&vORdqz!n873lF} zD~i@jvih~a!?70vb?&;akQ?o663tKxfA=3!SQ}1*csQyCc~o-Atvy)UI_*85EPM){ zRywoiSU5eD214!Ha*Hwn+AUdMkFzbc*nGq$<7RkTT8Am>!f_N8^I(7f78ibTU=E5M zql3}Fcp89Kfw|z zv$A=Eu9?$)4~2i4u9}Z~*L_`E>#Qx6+I8#_erKhihFz=K-$ByST5mOM0^jA0zmGqAvTBdu7&l57rn8wt%$C*h5-FiO{_;PaT^#govae< z)JcJ`P9G~}CTgl6caeN>g{y`bZ~R{I8@9j8bLa#0Q z87u5sbdj>O<6wh<43m!*_I!uMrsq77JnA4{4Om9 z7m1hwrVF83-zSb7717q5=`yZ0?(P2mRa0GtD8T3ZJ?J8JljzMywymD_WZEVh#6SN5 zfHq}PYsZuROv6LHBja#e%Oyp@U@-uad60hC<%Pt*uGwkSo5fEi;&hxLrYE=*8!wED z29v?Xmsjwu32eAjZ0lJ9b-YMET1DQk```b8{!rswviN4dzd2GZ_o2Uy*?m$VtG_T_ z38>D7zgHn-SaaHWZvE(n=J0i=Qs$)2&^+NO48z(YLgS&<9CJpEb?d)o=57dMl z{v$JmIux>|T1+u?B`(>q2vWss#66PKF~nN4eQqayRIf=^5udc|#VfqUo2J!(|NREv zL0DaiBB8ADC&m7=6+fJ70kJbdhBg+g8{1DidfN}t&T_<=0BZ0k&gM|(aEYY@^&8ke zb0GxLu?vDiA#Az`vR=f4e$&#~{53zU3T0^h4^L%V0_<{9?Mg)|x@PB_QiNY1tbIO* z0_m)kh7bVeV+JDj)j8SUWRyvRHW1v}Cg=A9*Xhlcmy#BH8yX)OW&mLRC%D9eR2kOUxpbr%lomg^1Rw<6HK*e+n{h z7t49+1H@n{Pd4?=twOs5Qw#~9 zMYb4mI!$G{6ei95i22cX0`cOpZ(%|%1^sGaTtoamR$R(!+^qO})|SrA9*s!JFJK`t zLb5Sk86=drN$acdt9A~E#|a1_$G2O5vidszj*vXRg_k}?Vbr*4^4$Cpx0ruPJl_?l z<4n*f9b||+zAD+-_a~U>;t#GCDXNamw2Xw@(_CV0E>egaNNzM_DCo;Jt>hPY0c2BJ zxwxR`VyL>Q`}vsdn(0l5O;9{F>yknOpSq!gHt{Fg}9!AadZ;F<0!1YzrNuzpi zLS5r^{yYx@L0r|3gc2PQ)4}WMxaRy~W&-}MxlLSprP7-*r!y4J2>{ z+S?o1X|(x>m>+RrAJHq0_U|4K2?bK>xt`&0=`NjSv>}H%@_bh}u(s(ps;dXJPI_AK zCqX?tWJM zL)2H|N(cyM2A~i=rOdf7XsR*7TdC9R&<91d>8$#0a}00Gdy`Ak_m`on)iR}4jTU6M zE(=DJ`vbe_c#=R9%By4m^v_k9%l1Y+CYZ88opo|}8*j4MfSt2i+EUI6`;~NQeV$O& zlgi)wg%6Uf)i8Uf_4V{EOBa>B|Bw{(b<^&w1wDK06ow=6M~uq>M8&o5Gee5~yhj** z`ay4IZ+OjspMOi*l=P=IoMWAY@`15jwnAU4{%O`&Zj^A>V}*FB3ofXLe{;7e2=|ge zi|;vk5Ie|?opIN&K%iinFq>08LDS#+MFq|s-yu7+CW~&TMK%`s*-P|M%By{J!O8EOQ6)`lno}9J*FruXnb{|}#pU|tpY=}pwmXh4U>=Wz zU-avW!i&`l#YcL>Xq?`6y70dgg5jdzFadKj#_l|#Ia`leXGNoKL~+D+D9jSf9Ri+8 z;vI6vTN2Eqa_`(LWZ%)XC9pvBDw;K$2MTUVFQ4-9Zo_i5TmuiZC0|Zbww$dd&rBy- z4r*DYex-QC>^#T|+lEs|gbN`eIfzbF6moEPUCWHNhZ&%W1M*FxWpu>Kn)fht3} z14XNL>Thpn9OVBT2{uUjo##5$LL{LgCD8K22&FSOp<5O^&sD^pjP`MUf11 zQ$S&Qr@$p?wP{Xbf1?XaWj^oa*wROn+xQ`!^1}{X`Z7O3fGlPn8RVbp&P>Q_STyX|^0qla*RzZ;h&9FVx^3$i*r6 zbcRebi}McCb?b@~sM3tu26G6I%%ZTtyzboEDXCPE9e$<3nK1$ZYtl3G{mRlgK4M( zh_n!B+|9zXx+f7N;f2fv3!#U@e1b_kgvnP5h-W)Qo+F!Q(-8{%v2dd}al3PW)penY zRML3t@CCt)=B}dInnekeyCo!QLxyOPMe~USB3V5EO?HE+x3?E~K6<;mGv?b?61$^%_&E_6 zf+7J3lJTk5@}5+TIo{p=qDr^cEX~U)SjW|Q2-OC03*&IlNYLxJOD%6t$Sv}}GlLwH zg}KO-?G_?${s~F{ILiDZy=CrZG1wH6FlYE5LSAULg;u1BXYE+^_Lhs^_xC5=MgVmN zf?K>P3S@*!MYQY#;w@UPo2mUi8pLv=|3%%zLPhR0g#e*oZCC@aw`)%plq}MC&nk!+ zd!_$s%w_Kpr2UE5zv@Ye$OiGol4J)Is%tfY&q0U-11=PLg=kvJdGQ}Gm~@u}en`(g z(Noq^*_Cp%<&{2*gI8yzta@Ob8=VXIzpF_?zN{Xr_2w7q zmpRbZ%9=+BU+R8doZuy$8JU%DSK2LuIzm&R4N&v1(&^HiH%-S~L;cQ`YLS_pIy{I4 zhxCWy4royyJ@pL&d zzl9!0Jkq(pKHI~My5q1SXclw{N?S8m4G2_P@o>NYXj81>B=& zo?kc0T+oKfZ42v%UBG_BW+BS(KtD)-C@U{QNvya~ATYGP=A#EP2e_mA6{A$3?u=i! z{fIup<9dif(oMdiuQ(58hQb~FqSnwJXj`3Au^xmgQ(%}IkfP(N)N8tvSG50I(m_>qTr2#Cc9>c1 zV~qqGQ}IV=8PIcvQp^-?Hsf`>S4$DJ*mogt5z9{bMrNw1;fvQ&j)TuC*G2xrU6771 zt2fs^6$2-?YXJ>xg2R8_Y79-7_p?wbmf0>^pU8~|6X*mBpbicM=?S1s@!I188Gto`LRG+o zP$B5fl5l`UjhFb;GxnIq^ZK|l&glGP7Vc~j`LrsLR{I}9ih>oSgY@L9sw&id}rbT!UUDJ{aXRWpS8u8(s+k8;n^LYbj~= zdC%$AXfxRH+|^t_)S;&ue{j8xfm8u<&imNKoBO+hxcHOIGPDBjJscJpW`<>*oOgwC zpKpp8f+n)FB#1ZtQm6df8Rwg&1QcsIP-nCi>I6i1FJ!iAxbnS)f5Bf%Fc2DuJ7@4e zgnEFbHn?%&Ytu~mXwckOqPFh%qgT?fKUzrs82l&*SDQROy7<|PAvqr-oqhzihW-2~ zth_NEMx}(})a-&@d#(}brf3@;C`ur}A*~+t2t|a-I-b-u4R!?rFI6~#hN#MernjGZ z*Gi0PQ%$-m%`%pKr1HwaAX#!Q2hdN_$z4*%qG2%)K}rqK_5SGgA#LhTKnEluEjeY} zTM+rLpLDbp!e9Rgt}bV~Q?9Do=br?5hc;6+F*ji}e*Zqwk>;_O0gjFyCW3}h2kg2X z^a^)|+K%j1qn;wGz8CfR3J{Uo;*KQjF}~6_FRGcUxJuAvWpP#?PZzCuxN4G}Mly?&nRw(hkGNaDP;`Wf-&V4Q4njswwRJM!VjtuMY3mv}^)UwnkIE|YcxDOAki42pUALJElu3d*}qFA=Tpp)z?rrwB&_u%RRCQNBE#v=^j3w*Kry>$}-^fFIFSAlx~3 z;_4O$^8uWjd5&%BCZX_CgW#Hw&hivn|91v~r%J7gu z$LIX+O7Zd{J11?Z%$gjtvr#Uw&?r@NLL2;l+;r8juLQ)@oh9kRkmUamGCixeXHKQ( z%(3_1#1-Oio6GM#B5zZYii`_!|B$qd82-(gJ*KDp>By?{YWd~`&%}J4Hz{rl3Ci%K zTr9E!t20myYJKJHj3=V|B6>?ij&dFbOuP6^E^!b^Wwv?mFK`LC3yeu-l97u{GAZio zGs#dj3k2o)E5eZG!wU+t1AG=sD#sNUmC)yasko{ z0YmF|t!6I5?W}EscKBxE+8cDUe#~X0+aEru*f+RXe9O@2*yPH;r@OCA;>w*)nB|>b z-7h$4YS#Y!5(U38t5DMuPcA1Dls)+Meq-ugFO7D_*p@fUXkl~_ap}AECE8)0;)<%p z;I8-arK0YTMYPRS8SF_qBRhUkrcOCDL!l_C&R+tarn^aVb~b66F9!`* z8||J+4Rx2dw_o&_)MiF$6S4i`foFM&mOk&wAtUVe&j8by3y5Jy;Ndihi5kGL%&)q&3Nm{*rvueAYg;4l;xuXiuvy}a;1h@71h|9V9 z9&Mi(2!9LD6V)j|MS!)7ImM}cyQsDi3O4yB&1npnz0rkegah5>=6yp<@*m8pRb+*7 z?W5Oni`HERXZDVf@5nd#o@nW1CkS%ig?LiM%t^`gLY7hor|O{&J9o@Q0;k0g`JQ~` zrmO3jJE+3k(cPT(c(7Qlz^u0wLLZ&Zp*Z-W;O*O+S%^8DFhUGjp!&SxVGF@JQgTJ; z?R}moRA*RoWTzu|kUgs1ag$xJE~$;-qIU%KJe3Q|yk!zG2Po)juiAKT=;cj76B>7C z+vdDxL|NW1PrlQN$BsdA76nhHVGo_EGs~@KowN>aSbaYd$sPafJw2EywwgR1pIp>R zpr$!Ae9At|2zO?~rM=D~DV(`bwgu~Ebw4i#$nHf;K=lTXEGkKpD6fgogp=a^)`xhT zCn0wmcP^oUUn}CgvKH@a(pus^@@S93mpb`H4l(5XafPGppW$y@FUH>Zt4H1U9LjP| zHyn?R)M=SDE*|Vr30Eo5v4j-Oc`6koavd-<`dd_uabaWhUijPJFrl5`hE2Y^0qTON z`V(jaMDe@=a*%J^+uH7IXflW|*|jkGbADE7Ft>PiRCZ&zwYenix-T~((u9Wrr z_xRI-#Nx51&bEe<$Yo({HP9HjO}6d{AlJ9ct}>zisJ18S7W{zk*z<`(^c5d+1V7s) z9~kvyJK5l=kz)Bcbx8=nJ#Ycpf9#ZPUB#DQ)x2`)OhQL5Vh+C_#t`)*g!*w?bBa-= zKqj;x7bF``^>ZBUI@-SF9d$ZAH ztS6@Q%XBww<0%AL(0)>8=vHC99dKWJ8B(fZc-kB=uAx&$iZn!5Aa1i$F1)Ojd0ayw z$;-w&=I{nI1we%2YDJ&+{hYyi(~5!*t%~s)>MczV{forFhDd#1-?tDPjt#*Z_{|9R z25-E~72BoA@QijZpZ7Aj~sEzN!0lZYw1bb z@fGcUAm!IlfWU$NJxd!zU$tO;t<;?}?Pe?hXR-H!&zXVaBY+*r#mUJXq)^dK<)GaPKhpU5ntpFz5yds)9y%ER8O1j~;>OJx;LI|7SPf528OrekvYg znG+B9@jZ$G{p4n;{-E=`2J!jrlOot{F0>Y1L_Kctk z%wtZ5=ypa+nkYJSuDGW=U0v<{SiQ~d43|Bhe&PCUr+|jrggR{8)6+*(=B}wDjvz)_ zA+;xTzU-N3w!ci$zgGjFkyuzl zEZSPm6Qm31JJKO4>tq)fu95j0_&Q?q;2^XRnYXK$ZIhd9t2GTd?=hj`cd0mq!*DKw zXs5dpxJEJlU`~kQ7$TUlw;yay)7#g>awFI|kKbTI_yHZ|lZf``g(+$M>^SW3=yN#p z`b~KV!ddvk5Y`SpTXE=hm0$kI)!bs2RPJIH?1YUNnTe>6y?>fIldN7SdLDZa3)>RP zf_edO7P*<6xBb#iSAvF5o5UW#>Q1hPqpO!%yF*q&tD^6sdMU^_3x&rg!sq-^WxFRR zl+f>u30WX}r^6*=(pjD7K@F7vd1D;GvwpK|3!8yeQZ;MA?OD~#RCnIH1;#H3oV~mD zViCR7dlHF_1>nwtH?NJ|F=z{r{R&6bUD39FluMv>tjMpiEnVhGY04rIMeKy zLPabmLx!%fScVH?wIdQko#UUgcY5!7=|`)O+i)_w#95jww$+>~LUrf>$VVZ+kcBU9 zt4)xqN-7C7yd2#&4wV?a<-%{>HP4gSZ=`2SXrZRsu<8Uz#zJe~`k#F8qEN?=yPeG* zn>POK%ohn~ou*qvgDUv1iBFfU87+3r8=Pra^1Ws6mzQh*OEjVKq|(yUZIZJW3P~Vq z8ZF_u3~(3>>Y(gNcMs`n-WlyMH^ym1RJPfAzDA=`bwWIu%Ar_TMUd?=ZKP-j{ttob zw8j{^@o2mf^a}k6|NL8U(lC!h8LBm&>O>D6JI ztDOt{;8XCTr0g)mRF=TxP>i~=$*(_1!awps_KJ!*YgmRSlqO;B-EtfXZb0Yu5hTs^ z(5*Xe=vTjHGFfmM=wAx!U!KaQ2G1Uez`bC~VcF!)1V^EJ;QRbR7d9s+KH~~( z%D%SM`CF_tUa_5zl(@mFvuuCForB0?rDGDD>oZdb2XfGkjMGfo_4Wtd;J1tDflNc_W z@Ig&NR&lp>CTvr1rB^;Ma-MHr@AE>UarqCyDRC-|VaEx<+wn_RbPtrd;-J#QCs-4L z&5kZeDYVV*u4;-IXVl0$U#rR=MC<$z&m+_%Ev;JMd4FLs;zb0H(XY3B?2t!0*w=vkmC}Pq1Cz$LeG0GY zp+Ymv5f`(z#w_Sr#!&{USsbo2;q?X;P+O?o*P}s-DcCIpDEibwk4i zJd9j>p-ENT0&i5~;2oj&t`4gONa6d#RQYyk2>J!RGwHnoEwh4_Y~hPI3SN~R2V8Ogqumx^Si}|VBh)s{5TZS9)Xr-n=22g#@S=8A1-wuc0{BmIpwt>TA*<(SN0XQ~n=UH6^de6pYxlN0byw-} zb{37<26d#|WYL(zjLoMlmQ-U*>&~44zD1)f6;UfX@h*roYkFWppz7mC{L~+mT(f~4 z?>@c7A=CYB7KfSDs!KiF)Lt2W>R6>QUSWMFTH3t61ND0a;2Ptmb#`JXy?yx);munb{P^az|2Y3hoh#JucRu%gLvOUw~<_m+A`wK>UsXlmvklhFJ&kwLa)bqU`jrDq@p7z!JD@x zb1VYRs zwT#B<%&~-)rE5HEN75DOx;{jfJ(1)hNaHflVDy!aDG-Y1-JF~Pl|a%U!glBZ7}ee6 zS2KfCmvrqxu&R-EES(5b*3o@dF0TdGgu!?5B{YuI=HP^jSw;^>Ih%jaCCzxWtGXU zQ!BtvyL%NVHTa;Uo4k)1R*6(i%NN7h(|h}o8pG^A1U1@*Nx^63 zO4co5eG^ceR0Amf2k*-eTCrB<+-Ie0&xWjdsu-q_P9LF&6<40jyH_*CvmJm7=13y) z0h1QyNIw$3&h21;MUs z2(jq694@_c9q9X5^-8(88%Z$ea>I7?9=C6`thX%m{h`?k9xi~z zLDxe;l)ke|N*(JqPE1C&_rS#IH09X38Jkp`gfs?&3WCCu-!<60SYwdmX-i0g2{p(f zs?3$O8SCBr56>RBD!R(SX`emLSnHt%@S+!mcPVM_oX|!DZdXduy#hvx%jA%DST z+S7HYs`=@PBM-A?kplH8_)PO3Qil6(t65dKO4C)!R-qj+NAcp=ibV@3yav=?UAk8! zY{RXTIVWQrYP2_}5bcNr$kmE8%~k~lFk9-E002+t`{+Hb&xdRy9wP>oezTx?DqK}R zC=hDx3DrGK_z!{R_d(ZvS3?VV9z9+gD13<#IlS-oX8}pHvxv8UT2Geo!BT~VT&=Mr zQ_q*P5T%-Fkf?wu>P<7Z#7|dHf|{nVaSxYvqp;eZ>TCW>#J`L~x$HPoy(qzI7bVR; zwdnW_IPR%u z%}JJ?=}dRJBbd^d;y36LkiRMp4=BAmvWzkc(#NhD()ciXeCs}An zCol}1VpqGhb+0?;vAl$wmrI)*y~E8kF>1ZO?1)&~%wtO=BPjWolJG(M5Y_B=qh*1V z<+4N_h!YLmqm)`QmtfHCPqwWX<=AD&sD$QpqG<1sx7*NHx8F5aMkD%7zD-qe$#79R zn>x>g8JLpkE-fa=2CabuwclwyH;qmC;P&gRESu5=sef>m2P#l(RobN0YU?@5#X>k& z!==(%actlx!Hmx0RdC>fiBRR$Ta;u@*>t!ueedfZjG=G=hjWV<#ti@LL`$s@34rIE zu*v;}v2*-)mAvxUx#d(Ty3iTzTk&sN63Po!k`ymB%Tz^GjXdXKy#FD1ZD_xzbs*%^ z^~+58NSzUg@nI&?Nd%IW`PnZ+0daK?m_D(^ZyKD5mo z6`|kgy%6TJrdE0QGUCNwG?#A^LWy0Q)vLx;;BBtFFBf>%^!b2l7GXR{UU8hR3F2mu zY_l>QwDg+GjaxRuV1@Ih`C|hEWZwcc>tz5Xm4z9Wiu$hK_WUH`)b)cVaZZ)VmWUyq znSzf$_><+8fGm)$am+);@cm8(J9EJ~4jX`Ax+Kp+VL50BxM%wbd{gYUuz4P{;X%df zkszs~Ov`pEz#T1B8FlS%>7lKJgGWY38#9vZ0Dr*5mY+EkT4 zs;-#T<3jd4fwRqlk^PVIW9|s{KfgyFiLa=6OK|kM1bpDu#m%9DlN0o-lv+@-v31w% zC-A#{VV8fSOcO1Q`|Jr z$9fVz0y*`%?wyr92cvN%+W|@mAe|fDjlX=MzOuCIk-)n#-rYzJLkHQH=_FSfq04Yx zM!j!`-7jwNvNP!q`W*W8TX#RS+@{;gvlbkOuc5QGd@CxSptWed7AA~|V--FPGZJLF#tgSdY05s}6@}v7L`cEs!9t7{Y z8J=$u*e)VB*Z>MO(aoM!^I)>pHX&^JV>RSp3CI~Q8dX{rT709Acg5)vs#Nl{QB?aG zkF7}E;L`J4wEH~S?RM?iT(Xw!OcS23SW3hkGU9Ll9Rb67Tu0D9vbf?rK(D2*VQa+o z?rM_>%Uhw`;DPZ)Od~PgiG`!|IdtCoSn{tk+gd2^-z$#-^#O2Cc6B}#8{Q}ol?ZhKna>6o$~*&X7@(x#g;|tDzZ3N<%}iOK&NI+)_7i&8*8_L;WeaJ1 zIcsf<)ACbf$nr$J3Y%5Rli~hfZ7BgnJR!+e^DBi42VQ3sei%`3LF{z^!RKPiIrL#Q ziPlT6V4{oSAPP6a<&^5oW;=P0l_$)%uhx-LcB|Y}1wZLU=9aZ%8)xNI^?Y75Rs{@-EBw$O$WecP^#v@3*nUp-4J8S=4B{6L==L#A;H)VHu5t5Lwfj_Ni;&%{I+pFoo18@0HR+ae1 zC9va-8i{?s6$^&=k0jb{Ha2kvgV#h(!MzX9-mgNdULCKDsUfa|DJ+;fO>S4h|q*p-7E|4Ex|nt{oPfiV=Wi$HKH8Z`vCS^Gc_`O_z7ap z?n%wZM)-i&o6K9pU06&Ez$w@wc%gab)L)#-l#3hc#WpgQKnc|ol)b1p6qT>sr;eaf zi~{~TiWX#Gv9|0iWvP35&*pn>(dUZaVqe2i9tg<#+{E@1lc$OzeFuBI_B{Q)JiKpw zXd}x*WUv+i4}6r+hJoeF;4`An5B3fRNjG44vHMZuhUSx0@3k^Afhn4~JI^wFt)^wE zSbs3ag+SkQ%y_^gIfCTp_$;Nr#vAC7WbwY2l6mU*B6zNHIMHTfIRH3M3bguomssz6 z)mh%RXbijr-sD*AcG?G-Lp_7?Yfe2uiSh4Kp}s(q&N68|Ic-hqIUM=}$&}6w&42cWIxYwc@tk8U5B#)urciVU z_n){_c{n-TN!z-~_Fu83u;P`L3<-cvEy3r`2PXZ|3xj=59G$1Dbi_*(mO!x}`QpmW zCf~YgRR^oj}s9EyO_b51}w1Mb%uF(58>VR}Dp>Z;eP-wg|l zB1xo5=|YNIPT(AgTav71lT|I;1&rCuT9wqv7qZPm=4M>wlSM6jP;rRyn+r4nY-<=Q z2t~Zw)aL2@;PJ=!*gng@jm=qC^&aMxn5f=56Z`o~<^`Ms5-R!gloZaj@MtOPhfrt@ z4N4n#CtV#TWry2FhZAy!;3Cvm^hp!T|CU)D$G{Qpg^g@@+>>9~n%)Vb`_R&>VXXxn zDy6O$vs@}KNG*|hUFCwrcifcTmx6~rO}LqddPf=Q8|gK8>bL|Z$Bg05^G-DitImeY zSltUAp#%ntROOgH=X@=wW3Z;@m##(Ep>8vwjD47FB95c8OR5yc&m;Y3=jUrvnXbts zP!&i)LBq6SdIrohR^bZtb_u^b)N7wsL-4mkG%)#EeR8|&p>iHS#IH^qfHHgzzpBsH z$?}I-{kQj(SUscYgpUt1(e0e~B(Ouv;zo~9{-CUrBz)1D7aqij0CE>E~v!USMyAE7DT`;tIO-d%)<3AdbT{w!{se<_mCMp3GKIT`Wup|{bl`ZX{je=C%5a8gvA~-s!PL?;e~Jbn ziy?$%toCe-NQtz3!yR~MqnAaJwO*e7Ddq7mbIZHOvWF4G;1|5-Q?O+L zGuTfzMt!-<=`N4M-Ad_@Az6Q`&cR-5%tIRenNJFr8YMY|UJdpWP9Op<%_UJonj!Q3 znZx4^@ zg?;DNVMkQ;73Kh1R)*ECERpysHIAzd|IMh}DSY8#wAOCI#@7#AX<^E=_O+dxxpP2Zc@x!!xVU?o#2uWnOKp6WV(L2@Spk&2#y z``jf8=Z`EzCZ)&{&JVtGV~MWiWEz5e6|LwNv~}8dN0Io`CQ-(z*{Ja-Xa_qCL`Li3 zAb?>5-s&0Umj>@-1o?$&l-;K_HyKg<1{vUOl-AnTjjkm|hzJpZ<3jVXH`_W9gBuEq z(t}MyquD2iuH5%~6MET%I{|@)MDqJ}S-+%k_tT5Jm^~@>tcfZXUW&*4wam?DeKUPkNDYHv%{Herj@4?+NNsW6)4p=%VUA zbXBjd9|i&!H8;2JEOfl;9w=(R!+@f6R|9Nb)I$B)YOK2$)^ zm>DeD)C7EJsB46v4cy_knoMzoJG{OWGwN}av{nTGx5_-YtOCAj-e0MKxTXo!X%^gMr|RwY3xSxSH;tz$VAVeIqK5z~$2?7u^Xw z03GpSc+nBc3>R7o|Gz)5w&KIo^)KHTPaiFuVSlVh-<$y2YvG^zo62gh9?Dy~UqHOS ze(z0__1{3*&gY;VAYhK_y0pMx8+M6UE^}6wG8Vm;A_g6ND&;;Nq`qudR#`sA)aXa> z&r!-7yfB;*)KLbIo43p(6D|mXpDHO~&x#Q)!{*Vh_IC-I4B>Wh@!6`vhGi_yc{(HX z1M-ej)3^)p7||4z8S2?6dm2gupf@R)7vf@oBLLN0Ca!FAI@8NpxD4A{MyHxT=Z39w zh-!@gh3d{z`E~aXWgnT-jh^i8s&U*PvAvhnG0!cw#JH9@SJiFSvA6H%EuFl<-x_b9 zVC3xCu1F?y2weQ1kj@Q`*U{blA)cJgm- zjnq+sm(}l-0&OuQ7~-Dvy54@79kB4%-lnBW#8LVOO7i--Mnse1hpcf^uc;NurIHNI zsMx?g6Lr38I_)%fkB>ji<8xAM<#s6=uji2=O6!fC*Fv}pjB|ro*qjU>=6&lJyro+( z35bGq=TpJ?3$fp{Y<173>lx6l^y04$qbN9RPW4)c>aq%okJA-s%Ow9r#+H9;@^$AD z?2fS*HZ__P=|Y#TnvSQAB*Sk!<&qb zY(sO&_Yk*ka21y-fgOTDT~OQ5@({C&c2cHR@Lq2AZwBmIuG~fIw9S;-%Nf8%J!z0Q z!dJRaQ6jxdlqJGN0N45L&9p9-!I_gJMR=L6j&PjE-xIq`#iPV7v@*(+r2`sFw^HV| zJz;Qh&*>1KyT%O|V!Gzm+*RP*=p#phuD(X_AA*1TM_HF)2rBUK2eYppY0@BGQ~TMY z)_V^c%La8UDReEjc1}M_q!=HM+$#2g#C>CvJ#$UkzV@>3dTHr)NB%g8T4_`NM*Os# z)66dO@3J3?jh62*l`Yj18S^i|G_f*9oeku3|G*7jt)zsIS89+Old|z*8HyW^KS8() z1z#y)38nika`JtiO)8aR?603^SzmsBv|@4AwseUl+StTA$cm@)5V%Dm10=AO%lbO99~=S$Tg}$cvA4F$|rX9VV}>bO=L%H(sXOC2%djR^81nZ1Fj_s z=A_fZO4?wHnNa*wb0EsZQdYB-<2t<;tA4Kz}!; zhH?7lrS^HFD*H`yae?2Ux8ETDw!C$nYd*Ch#lV;>QUzZuMSJ%jHp>am7=_GN>68L9 zAN+Ibu6s?m`f^Gj&F^z1C%+~!03G70195Yno%@xVC{&~4eftmLQ8rPXCtBGkiju*j zfb2tBq|AWK+DG?MSkyXnSMy8$R2@}q55ELV37<=?L=Pr#d<*{VeAunDyGK8;4Cl*+ zo>EHuj}M0z3IP6xFq4EL7y`c3y-n^xuRi-Dq2V{(E#kU}2v2;rtwX`5>cRjVro`nS+=D7uMhLtW*6x;>NtOIdJzoMzI>@t73ImjAft$Pc zEe%T77UBD4hn^40F)|L)h#_4ujqcJMX5QVLl90zQv&lIn^IUxvS!AsU^Phybb7eEN zLy9kk>w@fd-RmC2%C@u{jPW9=(i#dj`VEFSc+zBfHU3nXHme(rz%1je^M@1rg1dYL5( z#xboq8Wf#@)hxv7PwHt|XgzSlMzP zVp3tH1D`2Uevfc_2kCh8`VV2L1d<}Wk^bgh$LL9F;ZMj=__9LDt(?)-$_r9rY zu&uS1E5q`{7qZ;}(!{WK{lb!75Gv(oAm@qMj8!Z}#EB*p{%4CT)wsZo|G=1R`&R-W zdDLnbdlS|6YF29z3zTbaAmhXTJpfR*NZcvIjjfAhI?VA`0 z8p-3zqmGZXd~jYe`#EI0%?wO;A!} z!<@yrRhDr)$&sI4^`{L*xHjoQ`P#`%tdW&+c%4))3<85f4vJ!OB_2VVb49MI;K_=z zF>8Sgblc>O5UN6Nu+zvNyPE5rBlaFzlN0&(d!%5QXIT_B7+jSvoLmix0H&~pXsQs` zFr{GUG@80@{4X&f|?Z%Bs8UcB8MyLlDUmaM0m<aJuIsZ^|#OSX)6?w*{h+- zoHVdxhN?~H-+(mQJWt??m-9`XOHO(Qq0^`UqO1cqLnIpu!g?Ikfr-b?KcJ5wH>^D$ zPynu3DAwKJ2#RYw+YCK2{jDR8$sQui>2H+vI-Z)|{0_rlKx-q9b!6n%XK%$%V|c5B z@X}gvPv73G%7*!T-st4M%Gpe;}aa><3lh}0m2n#{t%l>=IJ-3 zRr`UB?!vQi(e_$dA5PFXV)<} zEh-)Dx*bFBo$9sNcfKnvzB+8Z<8%9;=Mo3R1YJ00BRxWSnwhZQUO?CAZ&Xc%1Dc59 zJhxQH)~J~Yfz2fiCVOzh^XGC`#j6)Df)_pXd7(X+mHw$TOCASK1OU+pv;g`{jiVo%$Zebu9Z}Z$y-Bh*)ed<|6p@&SM zBV1KU`neGMD=HjS8W2HIyua zFGy(XjxOC{*}Z4>;=n+=K3$kC8+f5COBcC}c(q-@_fADa)Qt^ZNU871jq48*bY^eSuKDVk*aWuxxmx)M>%)}c+XNc#?PGhUB(nI{LA8(nW`S`ct)_t$X*O zHKd~T)ncoGJ}L?mC(cQF-fk4*AC}ak&k1 z-Kh;Z9IX?pMRj4wtEwZ~C|_>bp!_A(q=`Ohw-kL-1iXMBKX*a6i#u82m^iQ;g|`Za z#?L`YqBxU>nI*ii_Q{XO{IWm>0XMo>f#$zN+Jqeglwn%J3`JqHO}+V`XF43{gynpm z+oo3k>ffds|M9l-)dTsQ`I?$%Nq{%~7rw*D?1=g>f2yXcUFRFFq6S&UuC>oPMpZh^ zjY4cnZq=WXi2up%GW2`dJ4V}ly0@5&c(Nf9HCpqO{lg|^h{cvPUi|&5`rePxb28`sp>)KzhJ6 z>D?PD&IYy+@u+j9iL3A?BJBY9EVNTJ09h;0@axqkk$>0xg5>?e+BIdq<5Q}aK?R;Z z^(?$i=DY5Ke@#2kho1GPM&bPjj#YiiW`c>D||Z^lee($H#RmvxB6xifG|w_ z_AX$PIU>(C?YR#at9fo}YAQ;9$WV(&8|#u>^p)kS*W4d&=mMOp0&*qxnkHAm)CiYP zByWjpIm}hc^Ne9m1K4d-3hiIpA05Jrpfw}if0(+d*lt+ptqPdNb-fU#nyHaDOoNFn zxcn@btt2FPtC^HCW?<*IfpQ~Q*IGCs2Q5@}2@m989#bs#X>h~5tD~59ZdTnVvWhYH zjzGkh;fUIqb*OA9rfaB#xmtZM@eBx^%)upXM8kEq;BG+*ANlX&z^7npv`d4*H!tbj z{h%JmVSf&|Zm`jzGj{XNZ~c|SHHwv2b6e{D!R1;y0x71cD#pGv4BE`TJx+(lo&X?Kf9Z-vBIxHpVdd_XvoxcHD zw?%peR(U9X8t-!L6BK^|!M)(5kr$hvhqHxx!)NKeFlLxes0lWM+*9KROx0^9ce7qU zX^OHi1W*GX|A}P&8`c>Xg_|*8IiQkRJg6bmvhjk~#gMzo_=2}PzqPVE`>cuQ9uvRR z>ylDbXm4iTX(Yp5xj7~BenIuGIi<(5bLr|3rke6eTy8@E-YqgW+jj+%ymWeXMUGV? z*eE!YCCZv4Taoclpu|X6V_c^!Ta}&QN|Pe1GgkG0?Gk@R@^20*mA5ji_NU@rx8!SE z_j9$nYuQ}A@lT=Jw*qCDKME0r#yZVvjdfBJ<9F_oHfySdX_$cV9{z!Refh_rA zL=Ro48mjl0_Sk*6L;5H!%Q5`_5%rY;QMBLNpdbnYN;gP%NjK8nT}pR~un0>?cXxM6 zcS?76t<+KivJ1k(!t&IVl>C<(AJB{GL(^laJVkLRsx~{DM@}gIxih5Caf?Oz2LcG56fn658zK(OV12#b z-qj*c`j;v(ouPM$BktAbgwsK34z$wp%)UvVL~>WoB$|7>-x63&78LjCERUtMGzU^; zunTxLrUqE@=4Xo}s3mNo^*U)v%pzjMw-fPIsOP??145G?*kRx2rHZEaweMAvDnBSD zF>iGp z1$>%2ZwM;yMhGH!(@<5?sLz+~f3r@C#dsznV$`5#GShkqTu^zlQ~2ZG55eo_btQa) z^NKb6wK>R7tyLD8cOw?%kThy|64+rSkn`&tD>g$S%G9em2Z}ob?jbCE+0b{fPkw(` zd4-u|vaQ}_C(H&;H`huefC|qZBGNNodZF)>uEHKrFz{*@90$a< zyc`Zbv`x$%_97qpkEx+lMO6c5RQEHRQ~A2EI96OjBuOdF5o(q+Q)HcF zJ3*PCy4ElLLUM3zl%7LaS$BitfhO8PL&5p%Kb=CdNZG#9l> zX4CeNr=YQhqtMcksnH@s>-m^uclwM%sD8A_lTcb=7kSQOp+@a+%DhPkk6h4loF4?W zgYL;hZtFPMnYOO}>gLEcR_Y8|yJR#r`J+<5%m6C7XZ5XrT13UH8j)P*;U@H&LFSBv z+Fe_5?oU$RGS&SSl|~WJ=y>IF$;UO5_wuZ*_zbrWkdu~Uw!fm`c2{)N|50>3b<=N> zP$P&p0=NYGT7a%*7`K+%zO7zGZ*B|WDHv%C&HWJ<(`zznPg2J%8-Zb7YxS4>3_ z7D?h&!GR5pA98)= z0@?3!B*|2t*Yitd;&Am~p1tCIj*->PFMY)zC4xi)4`bh(=_OU1bBbIJS?0p82@L1P zf=7_-o`kxSf~@z582#nXU5mDAIJQCTZ&jT9>Lurgl?AZl(#;UK z)7b?_@>z!*Y*NV4jM;x=Ly&FNO@dSFYsE6ml(BD^82F<0Fk9-rYQS8H-h~!nh#hdfY36M>jxAFL;{N#`aY+UuPY+SoMH?QJ5 zX@AZ9FSf;k*{y_itaBAD_Tp0{GZ;~)nW-=Hl%Y4$RqN}BXHvJ8qt3AM{@s_qx8EDhA^g!%^TD+ihipGABgBq>~UhZ2j_2zcn* zwbs5^>_u0v=KLwnq0*(l+j>zfH`BamYlk0skB&y*TFApsP$(|up@(H1TV)coO`_$y zSomWP;;iRC+m7#7^OyDYfnNQexHyG)LNl@aYS~y!0t)k9^1;-v9 zvt5`;Fw;aMR{p`yo+?>XdBD>sUrK|}BDzxk5NE>_nbX*7H$gUsJir8HXa%x40HcWb z6c02OGKY58rb3h`vfsmm>$=e>zRa7kKI1Rxj^HlaKH@K?41tB?KL2&=iEFYTCEvNH zFNz_FpHlfi=ZI2iUveQNO>4a=cq6Ops3H=3ZoT|LYz*)e*)@eFygM#3bSa9g6>OXYXXww|!liJ&)aFyZwnmDetv_kAqLxs1vF z9O~cVDu&6>so4yw&+!v=`wa~(jSpEb^wL?_FN*DO2G~erni3%|f=KIraSCg{6{1x< zc|bl}JS*4DWg+LF81rHU2x1o1 zVEle4NzJIW6uJr~4fk zoyY8%X}c#HW9x1RwUBt$bj;WLUuE`Q7i%nbSX@Wg=`CIH)qyuh__pqN->DjKn>4oD z=uCaZBtfV5b^Z#&7Y+XF&M$TFBC2EoF@@+q%#*P|j==3Q50aeuLRZT}cZEe;Vt?uL zSwx-5kyP%t-bc=WU7!x@dztU3jy_hL+^NvR&CQ~$KkPDJI8n$(Yw`d!-#m3l4y{~2 z8zb>UlxlWcE9E&ep5(HY4!97ETsl^JYFJQsud4pzFze7k$8Z&EdOIq9ln^~3Bx@W( zMc91LqPCVMmOw2KqqDkcyjJT?kQmeMsLo0qe}>iAcp z`U)cU|9<)DQDKo>rzvO3=WdDBOxlCh(SxJX@@HWh<^`qHmX~%vJ2!z0DP_z>KVruA z7}5UKqT(cuzdH0CNcwN0oV3n*Tr-4c*HkRAVh zIK9JLUc&tkUcT-BTmB8kSH`!296I zQ@Q{9o$mY}X^cAe_s+%kA$8|{#KTy^6E)j) zfU?81jBMB}O{G`fZ26ZWBu=^)rCe0un4;0zCmS*=8JB2m=>WFMHgUm%!5%g93Akvb zYatza=8vOnH~2|=NF$r;#~0}-529vWL}bKA7b`o{U)^JBAlYP()j`tt_V#0bZ_%iK zv0Xn>D+SI{f$ev}rl5jZk(P7LIQj=;V-rI;_8#KY3q4Q6j0*gT())ICY~I`?=OA3q z#h&Y;O|T}|2sC86tQMA60nIx)Y+q12nQch527g#2hL?o8bkS z*&AO$94|KMRO2lce<#aEH*@H^t?jM1dK7&xZ)@Lr_6AnrCLD5vUh=H}?10F--O-=j z7rwSS8&zQAUf(ta;dGYbc zwiVIa2iWgpBo#@$e6hkW!8h5V!cG0j0Rq3J<#W1=_hHQ zYyPcw#yxcYkbHCVRfWt;eo1a+GCB~e$d7A56qYSl`5&Ai^enjp@kn#-vQ9xRU7Y;i zcRvjc(Pl5%ZrV~c2&fIDYNsR1i(4p+{3u~4|QImdPSVY9V zu@P@Ov-cbvxm7?O1Rf{k05wjM6FG(Ge3irSFSz!cC|!_Pz-x@6LBl?rlY^kuirkCB z%;8$UI18_Jqybb9B}N`Ujb$StUl2uQr-JEzBPoNw%6n^2--vzkpvKJ3PBCv8U$XZ2 z8*MA|43>jlxWctN7FxwsrWPCr`8rzLZmvlB%js^5I}+&>=ro;Qmk9_(HgeM?`ClAg zi8z8meG9Fj{VV0G&aRiPj6lq*l$*M)Cczt{;W*9V6$hC$ju$Z`E;D<(4r`qJPtso@ z9|N?VGRq8$`jQEPNzV{n9V$OWy3mPb^Ae8!3WRKJn& zUA;7#onRQk3g^XJq<3u*eQ#iVt5?pmL<)15s*b1YEnfm2#K5>q9>gCWS7w^?op~dg zT;=DxkkLBnVX8g|d${@>@2SJsrs3%RmfHjbF(G{TkW1D(ycMLenyKA?PV+dbM>V}C z_QT;hH;8N+A#GyT%ScJu0$(8JcQdYvjh%SN-&zM{ayUVbJ8s|k+^ zeu*)lC=bDU_V9rPPW*?GN91>v&OgIsSYXlC($Q_EzYAslb8}J>n>jV4?j;s4q}>8> zJ!Xn{J<-0k-3iOJ+~CRppezNlpl+lX^iVRBeKOOz~jV#MwGk=5Ov>9z5ZQ z>WQVv+GSMAIho6+k{bQO#{;?yJh8({J!Q9?HU?B zdQY0=`>&#F44LoaY3^G0C419+B+Q+->K!y$6T)08&dfwe^N=0ROMO(EBh2Bp0S8hL!$4tHWk*gS#9Ci^|WI%tCp+!_uOn zIv*+sy99|=V)NBB3DNW7_bSF{VUE&pxzMUxYdrZ##m^3Mh3i*+GRzzKEUpi9&mKS{ z9IDUIE=sS#dVHizql1d9#kYD0TEw~7+4CK*poargYDq+HMTu` z>4^&8C@9etOHaR`bvKBjpLC;yh4^e++zqY+!+Q1vHmUBm`N5{7u`+UrtQ+9sYFrv}P{ix8sm##P|Bt+Z(H$tz;?@BqR9l=3a%y+`>Nk z;Qj6jmtWk`N>8#_(r~!8Ua8H7K9BT>0|e5ioVmp;m>$KO$17|dZLj&@JlSLTwaPrm zo1_?`53CSw#1B=#5G%_Y+r*+XT-5Muca-tsnGW$9s=kFZJsKfXBT6>aMpCI5UOTP< z&IjpJAZ;M~0y%Y@Fu`E}i#9Q%R*xqC^2IWv#*71dyTB-9-+`dEZyzPl$)_+U#;kj?g~qz_I}c{7e&^jlHw9Q zIPVPkRlz0#$IEq7Jnnd<<>brZuZuGuC6;RsR||Zyr0v+@mEe)) zv@-g!uL?(!&^=f{>+#W5?w*UrxL;-2Mb`FKw=?GlalN%(mZ@Xa3MzB#1WxF7rtBR# z)lCZA4mPMkuYuECYKpBfMHYF>&d+?OFS9^jxG|=7YSDuU8*G0wk`iMzbC6T;wycxb zCeWjNlGC}=zLawLmJ01F-EmwEe-r$s^3&P7a4H_8I8wxVc;3oQbv}@fE^g(b;tgv+ zisTR=khz(7!>>$vy;Ebh~H&zl~NX6@lXnpdgNaLd3b#Mq5Fr*Hz?8Z`4D!@+>)wr;Wzgp znr=GL??&ZpY&`zrIVdj?O0}SH`#t5i{1vKUYZcQ{h=@?llvc<~2zct=uhwoF`?U4= z-V7NyS59bakuK5>eU(;E{vXPC%gQ0(uG1`6{s~T>xb|oE#~zD$Ze?J`Tj4)ziL%jY z2014dvri^)6F8RilDC@x=%p5HEu)2`V@F+EL+KdMF?O~}S*^bW?8oOMn3od5Nq&Dz z8mxWu-D|Q%>Tg}4(AA$;PKAeH5#(pAn981*NhVe8Ixq4jPUeph&v6MfY zakal&TRVKXfgD>P4-Ami0P7gxHhm|uOjg=;Q9Z+|fKSuz+0(&guA*MLS zER*=>|IeD19^V7^>&L2*60km^UZ<-=pi!pGG({vtS?@KPc6lq`Bn;*}Y~P>UZODnY z%e%>t(iq1&$Cu_7iapqh?k{SqX`k5COQT<%z-2`A9||qh3@Oq^h&ffU>)j57an*mh zZIUR6YAE~}Gx-oUVswLL7|f40yZpGE6u!`e=f-YcRSfc5H5X@L4+S^48?WoDfcTt1 zOr5Zm*6!+T)g@7P1RK7ofnC}V?KrY(#3-sbE@GT&y^%dagJ%BL<)36d!3Y0gWs{yC z6?mxEl>^#0l8E6Mtv{`gqlwK5w_che*RN_Z7Ltb=O%v87=^d5oObtz0I27Wf3bB>1 zAK^?(r*vP(B3P*z4$5IZSh;=(}(zki2?VX)uwrz@{ z)VTOnQX_{xX5*oYS3yn(M>D_Gvm`H1F#cAK1^;+};aLky+62-@kCcGOO7%GC<*Cr< z3{FYsWq=7%**K`53OQH^N-&eEcoxYBFHE$zabEEDA(<=vo}X3;_5z*j!?rClj0-aB zO{NszYY&JM#dQ5xNk}mMZnMjB#V$_*VM;xRWIeldtlVO)iw#w_&Rj&FW_SjC=~Qth z;3~eMtwt&PNCmR?>wG`-ex93BMDZX{8l3_Y^TPOhAPz#u(`{~#eds{z@pFhmvG zhu#P89a7e{OuxiZYJII}m{;lCfndg)SLSUu+xe3_|HG#q5(7KYPRgGGc07GRZ z_Vb}Mux|qcs(ZuKa29QKc90?UL0pmc!o`K|nZX@q`oBYANv8@a0zk5$n#cmu$n$?> z?DZjOZF^^A0=v=HGO*k+do*aEjEGl=;+yL~rt%;0<|^=SFLMtyo~t#C($fxI{5%-9 ztO-?*Hb@o9t_;Szlblm>VL-0Ikr@IDq!!Z#c9CM5n9RjN5=bx1B>CKJjLyihdUF$k zCqnU^=E}Xt?#@rwWkU1s?>;w81^KXGox0k7pIS@5_$P?3K1ag}rrz!RIc7tV5HvY$ zgc(0q7RW3~-!Bj-mVclLi^y`*UsBOyZoh+zX_eVGvQ|~;DEpg*tCI!3k5|(ioB1PB zkKD6^-b9@H7>6aLzMJG=>Tc0gh$#0#B>PPDe}Iw&rtTxy;DDVqF`RhP#_j7Cxlxhr z)4s`s`^9*&QS~$Z8c)+_ZjSrg#*`6!n8MtEU{%@lg;_92PoeP=45%(UCHQp5kO%Eh z{)t=KC5GQ>-|%z}S^ca-alKxqvy1@pE-q-WO@_wO6U&gNfx6?FgIcv>xdcIiEX9IN zpBVrxxR4vmhVoU|$%2D3bb4X__P7w^Lje9crB|cgTBJ)JLjYK0p4Nr!O714B$zOZN z-ITrB|K>#>B83uFdv>byywa4$iAQVvi8rGLjKly(r89f>v17yz}%!E@6AzFNqc2Pua2e6ms4R8fy&Bb>!*htuVScRac zW97eGsrvV{FZG!mb(|wdl}d95ut1RfK(5w=DM?^U7~((Ppiw; z=YJ@>Bu>1$MTbcv0(I7q&6P4W4#g%W>!Cfip3FUAta`t+2YVIAUywFm7{Iw^ z*V4;pdM^8NC-oIKE>Mc7?d+@Bj49~R+o8t2Zt>Tm^EVU64^!W$OKJQU$~1tvuhLN+*|Slds)uO} zAtq)om^iGnqF-$UXG6tN&!zUk?R?5LiUH);=5it=c_v6NsX(DuA@aSwIwOW6!jtR$ zzFQB54jkiT#1w8^>Ncj?WF_;oJw5Hn(y%Z1;9+oDe<*^GeAeqv{?j5Z{KtO{8enwL zx6E->(Vnl!ar~iETh<(xqe^dz)@Kec$SH7 z^7zj4sLj4Bxn546Kh-LayI;!VLHT~lK9Ytf3dW+$09_@ijz$-)7!uaQf+6x9E_?8BnYG1Aj z9hDPB0uY_V`6M{5o;8$n`z??MC_ZLWXc#82gw&ord(IbQE)2UV?m#RPnp9&p2g~32 zAVEu!g;u=`T3vVx9OHNs)O7hD%1l2zLBeFsZF5HUo0F6Mg7J_(`^0!QU-u84iPK^I z)Cp55D404Z2u17;{24OCe%Ce7wMabG3{L5`TR`)a?*c)cobfc`0=Sw-+DYwy#*1|p zW*j_SO4?om*?`vXn32BZ0%xDi#^@^c|P>$}n7J{PwGL1{+LOhrHhoa6ZQ8 z7&z`%c8>_G;e{IiDG6SGDWxX3egz1&Dw!NIhs4|?L%Kb+Mt-3zc_2M>Nq?iJ&M1g0 zQl75%^5}i9to)LS&fCLmoa3f8gJGVh&RRHt@fKAIHz4w_II#CnZ=84>qi<>ub=KH{ z5b8fnsZItbbJukc@IU_`3?KwDE)ArMYbbW( zkCq1iP1tmmeVafa0y#L`q-9CBm;>;zhfUd(3)D><^irld>Sr&nTTv@6@h~ZhVP>U{ zW<>_W76YlJ_({V{_#BLDh8t`EdRT)qO|J=L-!#U=e6PvkHxY*JiMe1+xiR=gNNpeR z5wgjAQU@me?@Yz652*6pY+B?Uo&$YE_vr0EWB$i{gBe& z<=kRqj@6)KE2SIo-G4w`EYw$#{f8P;y;?uLrICUeu3=`E1_0VnkJ@{ltGBf{5P z)0WaT3k))1biD6zRnaZf{@0u_EkcgN&Fb>AyL1#DC}Vj#w{jhmSzbiyold*_T@8YQ zV+$JB&JU#gEy%%6-D*&$F-~d0_WDk~`kyOwLnqTRx76R05>Bzc*4ST>DSq){H%|fl zyYt0@Fck@|9Sc5tnyN0TsVI_>2Pl7Wy^{#_F}*l6iQHwRZc;xxQ={~u!g%NM)&uID zEINyk%`Fy0`Jm@sO*FZ`LF%HFz@oy;*;@E2P1N=Ke!XRDE9~L)-_a_I(ViB;q9W_B zs7IQ2TV&bq1jb2g#*lkuTN{e2A76Z-=~~Xl-wawdSU(JI8SaaOVI0}^BPIY9$>Iay zGVSqHzFu3elak&>MY!-$EWI_pyc|X4xALhhI?{=W;i=3o{JS@jOu)$zaM*0i?K;lx znG;X-+H}B|xfLbqw#(78Q!HVQNYu5t-|`q<;}|RYh$D6z>Z!t4j~HERZ-mP?9vATZ zDjqtLJaqE*xI?z=^ft zKZ_iyK;TW>`t_gbab%_{?h8^eOjSl&1K88(dsBXknfE4!>Z-8NP{reM$cg`K0ZzJ& z$3l*q2b0E$XO8E~vu2#LMgJn)oF|*M#4%Q$*cey&)WBG+YDWdt z(3Wj+9ZFpdE-xJ9JhHA6_A2WT!ei=~o}Fs$^y4O>!m%_!bA$<3ZatZ@$DSyZyXZVk znS!GO_9j_0(>wl$cXd%$1LnSrw7wqa@*``lwCz9R+!#@-_Vg+bx)J}rhWJ zd`B7^9tX>xSuk}@k99mZvmVBTWJ|dvcazlZ0=AGpd#_ctf&MjF|1nuBHDV%xpDW`w zCr)HeZKYt_omCfhg1AORHSyTZW_sH@LTV>vw^|3jGs&{4wF)%29O z$kK!sLlxX6x7|-|aSjs)768u^l;Y6D`uHQ~m6q83o5MU2~^)n0#L8$nDYc z&sDp3leN)A0`ll!0W`(gU>``~xMG{UE_=V+jRoSi1#A#<4Ck5#e{&N+e7T_is8pzc z=98jmh%U{rG==fX%81_6Na~Rf!nSYZ$}Zu61fJ!&;;qQ06^W|46Op{A?1_q&mabLy zpD$sbYnVG*+U2k`2TCe7EAZ7|Xj?QI`W&GDP$Wiy_+{yYxn0u)`BfK6szXC#M~|E$ zSAu?8`u9~d&U%Kefp+Lju@e3;aGX~;!))4DG>td1zNPnB7LlLde3GUT{z_Kv<7bvAevz`E#5apmHWECUMGYOc zol&JPX~6>SJ3bnA$GvKFwpd#Z`d$+Sz!CDZ19fK8**k}|CXj{x{N*ZE7F~y$?W)Xa zZDgauAjTtmnd$XsX?^+ga8F8nd{YP|P@y!yQX0Vj>V=x&kKa8!fP!x;kCO#e-mqJ@ z-`odLQf3N)O?cm-zosiEnTm=tIhwesgg!j&-1gY5B+@J2ZVDx$(_mK)H(pN^5}&Lc z+GUG1Iskv~@<6jSdTwUZ<>HV`@2OkKc4_GCe<<5Ke5%Dp%p+Rc9|`x<%wIIb>i{B$ zxpxKJb7DtOmHw$-OJ-z7rQ<)puT)Ag({~y5;xmYcq4CBCT!Q2vy0mo#R}^*|w(*BA z@ya44H1i%(H!`4dN}XxHIRCkNQ1orfg*iFfxGNc(y|dW)fuV}up zpts?&9r@&gvN9J{e*dbv6Foh5C&i&1s@l_k3|w0d8Q_PiQ|gr*4m0oee&ZPAfvgco zAm;Kq#@kJga1rsadsrS#Xy6lnjxA<#a-}^?*MKs|4~|j=fFi8=+hn0Od+54w9ra13 zcI{}PO8qaY@-{*`CILR`otPO!zfjj^ljsJ&|?&U~En92t1e3uly$AorrfFY({GxZ$RdPJe_eB}O3MmO%E z>|Rze1}v(wcl{Er>jY_1 zwsA7cMI{!13T+C!cqH@8RaPa1kPF|vD(sCJ;3gyDVcYMgum)aEv6V(okJg4ru$N{p zR?yJD*-1TApovEQ0zT%1EMIcr5W9kEh=5|(&kcBMjq6rweN;SX0~)3!B&-7FXzV>b zU$}ToN&JSn_`t@VJd;~gU2&t;^$ro8eADB`G{euxjg2|t| zVQszkUF~UC5fAbOY?>J5i}K52WPOz2ufn=aLyg-4)?*_b>y?h10BCwz{85JZ_ONl@ z>-}ONp^TSNi{*t(&D(7FCrec#LBJQV1LK*091mZi_bq2j{68;h#Klu49;zO3Hj_eA zrhmnA$?LM>#xI+w0*yTibel#c~ZU{16_8R3!m(W*?kAvRS_ny|b zZnd|xHIL>^DffrNE=1;0hY7-9U4-!^a4;sY(Xz_zU#v=_CarJu9HZ+u_%{oqt))>K zr{0V^I}{)u;mXvr)E@!rLddF$P{mi4m)wDhtYI%d6Z;wL5nN<3nwoSh1P2ult;12% z8v%dIfoU{Zx$uil#?t&wn#!^dI764@%K#cJQY3 zn$ zm0`;=V^_xksML6~2FuI2tQwi=YOi#a^V)vT`yS_Qt2WpU6pd;_x%^EbqGCofNvBmx za*QuaoR_X6!{MbRq!{di%mo6KV9@;`nI*m)E*^(n z9P%6fEdy44KlwgpDQ+nD>>XY)o^@%YiPZ-jv2n43)(lqaIQExrrqVn5L`;M9O?FM# zuhtU65${77iIw7&j7mN;0*t2qw7~Rd^Q9Xu0fdZNTllD&TFd$UP1eT2O|g4z?93v# zrwYP8R~~EiS%*@h*pm?=2z()RkjiAA5^`Xty^iwo;|Q-oWB}GV^iE*A zKDa=|_ailtGc1!SldUSHbb0eHAr0G{J9kW6vDTIhqm-pJ zH?GgozlQ#@iE{rQ=|){%Yttt`w3nD}L0%w-+L0q|$OQNRYzaas?Q)R!$J(2CJJ8#c z*>UzenNH`HfN!&+;)~yu%q27k1-SZ_;X=H7jNDhg+`a86zsAq!KR-uV-TPMf9gQ znE=;jc2$YbMQVJ0R4M!uK{7@ogjYsOGe@=2=AMtknkq+B(BdW z>hnTWZU9XzP4Vjb2~Q1i|3Ygx|2jP*|I1U;L^j8!({BuYl=vnVpGgcZbwVM&>L+Yl zK{r~7(HE@=RGdU6H0$S;y?#=K`;vDm0{GHu${ zre+SDb=!uow4B2#%N2SbU%HfGV*8^!fmHj-PXf3SdJ0z)TLJ+C)Mdgi^C;5%+cv>b z@}P(rqSdaDISWVJKKTxZ^gOHB)Gpf(bwow1zRpaK?Bzh^=n+*d+cEUsg9*iz2|Gh}e3z-A3*E zV)GD_R*WWP)R)$Z#4R94I zHi+Lm@$6YzzfVHYEf<*t2+u`zgsz>Ah53dU`IIP>?5@Iu!g`k(S}~xd~x{GVDr^WrZ|2!%5T4> zV`zMLKQf*THP#6&L4MlUkEjxpYq3SyLh{>uw874x<P?wUm!Ou0e~h<8EDRTU$du(@bwterO#8oWDFuj5|9#Er`t#z4 z8iAC*DG4TZc)#uN`*{+6_d!oajVXvWS$=|dx zb7jT#Yr?R|ODXR@-j2>Z(mfJZexR<3W|pMg#eP%^2ZZ(pWt zBMc=G0*ZmbzlIa0zOMiQhq)KXK}$Swg(-U_l)#SP!^`uS>|mj5LS%jK$3VoKDD@Q1QK*yDxXRI3@0|Ta;I_LRdAQplcI$Pc7Xl}9a z^Xk9_M~mKbydmlXt%BMJwh?BC#Dw_Y{jp&VQg|eG0flk5%Dd#iBUTONq()II-SwtW z+?d<7qv-k&Y4X~H_4t)7ypYGCSqMBS-(tQe=cs@K@o9GQZkkxaOaxq2&7Lf_+IGPr zsi#~24lugX1n~Z>v!vjs@Ta{YWMh&*FcPxlUjxmv#YK#BFwGjH@04sf{1WT_IJq`x zV!tZb{x0mE?t{|dFbW%lby9XFTqw5it<(NQ|1l5p>9AiM1YXlyY8A)(55=M*d+Nqo zL?~sYrPVMn0DFnDGESWkVGT5^nS+GGMO3vz+reLT4PvNEAly5NxIVz;vxmFJ9rjBY zo}0UOn5c08;$f(djb5 z#L^_8wq<#sfZ$})Xtmk}s+;Ie3v=3*~M7Zm~{bvaqM=l%4E=l6bquX99|2b9haXBHXe zCjCtvCatNZakl8o9#h*A2;$Vsdhe(h)(Zf~|J8Qo)uKi29HdP(5? zWDlH?7~s{4YzE}AdIia1VNgo--*NKTGV^^)>#aE>SoF~;>Gf|Yt98T6Z)jXn0TkHJ z#{d1^HppafREG3O$2<-4)0{*bOQD~aVWw26rO`wGb745gJYX0wM33npI?qAcN}wdj zTB}%oE8aH2^Wh&gaxX4v*?;NCVRM%}(i*O6e?<$cxGb%t{+TcCIsK~4m8jJD8h83X zlo}Jn@r*J0vWlDCt8Q?5Jzl=R@H80H`$oeUJf_t~sr0mW*ZzeV_0sZ9(R9DfMRlOP znXJ=Zr)%ozMOyfLEuZl7Li#dQ_l`_EQi5E6HpvSUX5{=I%BcV<5KXsVeOf+6Z^M*4 zPL{X%4`1uI0z2UGc!ZJuABtcgZ%=>u33ckGLWVaM7lQ@EPVdgjjplegeYu@tNthVc>jb+?t+^(b>j;Vwwy*%JoQS>`9X=&34+Q_vUbj&i$M#4|3kUoD8E;IJy9<*mFtL zRhy`ZEy~bjONJRIr5#+0EV=f2YK@t+y=@Tdr>@yYn6A&e6L^e zOUs?*-Kp5L}wc3AQYk%~uu6ZF9 zo2ZWT*}AGfAJNa3cHFP+uF_iC=+>bppD*%`CxpR@-b7lYG@?CfB$G^AncU8S3rVH93|vA_!9$u|Vf z0cNdczg-5|@^WB7JZpvE2)!%Hjm#@+a)2-=(MM7vjO=WMFZEXqDuq~UX~)MQikDG-k2S5^)zeW4*IsF{}k93ln!hPQnSu;%TA z`a9|v$5%}E$_73NQbbj8WY4c!u+y(nQw?waO2EaHN2#cS@AgCNsMOn1eyPuanG~TO z3*D-f*!zmUK+3vp93trmR~#gxjhuor+-3Tj5Ae;nYJn)YQ}fJz8*%Q(IgQ;FycA;7 zR^Q-hdED|y{A_O^o;){4ss4{^7Izw#0U}2sAfnz6s`^FYF#OP!s~N$V8Lh$1S@}Hy3@Mj#z^HUKMZN5y!(4MnUkek$Ya+QH;%cY9UDuO&!|id-y#IH6&Axb zo#fqiCMcpYZ&8YV-q);49=}G8c^%^lBNAqO&fju*W~)+ISxLHHeRq{qk=+ftMF5R)Ud0V`)a9mtCxa3v)v6_!@L-=dHOru)% zV3N)jUY%1(%l`>A>G{|-5^K}El5arcMXknGb+u{Eh#M^HA9UI{J!(Q z`Yu?DE7ls$d)|5Wes&DhI(L4x^{9!ad^wi(rK1dYT()}mGe^*oC)XfF7nTSCnRd+u zL*Oz+wHLhXomDEI;Gy@fl*(Q?@smv zGXW{$mvPRj?mr_{V8(&>CH}TXGb*8m$AHrY-|83!g<59}s`TcsFRaXMxD7V;t1XT% z<`Ic)z8EEJ$E+mV$@;|Rs)9N^R$Z>q3kx#N2RdT^-pcTvg}paVl12E0GbkQzaH^K3 z>@6FnzOl^od7Upzl@r04QCu$I8k0B{)^#Tt01uy*Hina@LAYDjbq;kv4Cy-6|5Ej&hSGG*S~>db3gi_e>G_r3MumzfLVsTx+&p~altgABhrK34o%B}n_qLL@vKp%za)$NL z;~ia4(&|s9>b?U_Quau-F%IY}7F{~&&#(aGp>nDNa$wn)K+J7rrPyWwZXw9P^=bAk zCh61i$y@V6bv{!S`Auh8BNEJSV*XBCAu1{V-s~`JxbdHMT7|Zz(P%oFXZE%)4K{P1 zxlEvc7*6{SWlS2B*!GdOUyzg}hR;>`NBwu$X%#{N01T!F%{+)tuweDUCFvHKtlz~u zhMkG+@@tak%Ai0U6zm{g9$9^NN%Sp{=v!aakSHM4^Iy`_7`x|iPELxa>r_43rbMZ1 zkPkYgyOt%zqNZwoOOJDBp;KvQ59ffd-M;sogCwA2G7H&w zF5sg-`v~7~zD(dIo4k{HPudfc-{51i^o=Lo3`178CT#jGr9MZYx;^`mG+-4jY=Cza z@s`3xAl#X)qn{}$mb0i0PzaNi!Euaie2!?VH?xR``x5sR31=Zo+Dz|IE7}+bMI#bh z+0eCzC4FoT?-w4wX;hazCBLu7bOgR;?ai~dq2MU}tQl*Q{Ub)RIEs41T#YrpmabOs zJKv^GO5bsIM^o{gA>RGlP?7T9XhRHTSvKkXfFJ74e=e{`dq*-szC|lHUmkG*|>d)jYq5mjA zpNEI0r_Y@=%r>;VKWyOBC?55jeePf_IvkoZ8!i;4V7_C95MQ6(T~;jZG2edAl$vAk zL8pw?EvOJf*b@%S_Blu4`F_FS0&X7Q=j;{(lcUHj%6d{Y7>m3#&9*ecQeYSLPnb3G z0r?w_-M`Ay%pJXaQ{$AsVbQ)w9hb<)O$p(si$FucEq?m=IOkjn^pb=2;YQ)y(}=IN z=G!G)%$xoh7H%T6IyzWEg6 zA&;z%d{Ykf<1WQijS+fe^E8|i(#0He*zX;mZ37+QnbGn6HLgT3)C`B`l3YR z*?Du|9=Q)WY=8-Lf$Po)U(p*yimVY1oG9pD(>%4={~3GGLr~r z%Dv;%Yq};xyr$wLt*))CKL2@#&r&|_L3w0+Dsk&lzI!Nalx|>Ey8|{;+c@iWjLmy- zp1wd-qSF(8fW7=6pFWEBpA7+|iaKt*yCKS4BmL zXZw(G8w~?RHw<#v{je}Qr8N-7xnUp`BK0ElOyl#Y{vOE?bWpbyKGR$Sa+(m2Zq9CB zW0&d}9q|3Z@UO+#Q@=7;LfFzZ0<}c~FE#f4o0a46Ppc47UKs)3X`;uOVjJW-43c-y z-Kt6B#)&V_S>JQc#H?27h|x@_>QwU)N3vD4G&Y;0wY{I(j- zR1P~&nvUtK3HA4|Rmzm~8AdgTmYzg^Q5bNhpK+bSbJrFr!0^ z?ZanL`K{jfsPi9+MZZZwK3B3u&30CKN}ED9zDE5Q((HVqtX5wB@EIFW2^TlzUO(%byv8XgooXWg z@>0FW93Sfto?M?>rsyyDHW;yZU=E0Whjh&IJi!YcR3?@lgnFi4yx<7_#!$YDpV)sD zW$c(76d724%^n%&`i?9#m%|1QE4@Vz50fAi;G~`qwl<}{Re$s>F#T@UWuK%s_?Y@Y z*k`l@^Gl$uxxB@2z+)>(mH_)AL+2LXXXjwnY+(qm%RkMmj_r)w3m=W%7Jjl+&T#*0 zH4!bwJC^}LRuY%$4?9Bl(=^tw;UKGwDule>63^KuZy_iZ<8@jrnD~}dcQv&49_m2W zJ#}lNiwHCDWGBY_ql`)OABt;cqrf294^B1V`u48&e+@QY(nUwceW`P7NCkyUu6QRSAT=P?=sV!S*GQlaxsy$y|K`6bKUp2C?HZ?od}7aN8X7ut%{{Q`f; z05In+eBWY5E>JJwqslpL-6(p})v2M{l=qiB-1MtcX9Xs;Tn)nb;b4g9tF~TydPT|y zWx36REDKB@(HfTW+S-{-+xKjX#e7Jr&}>+`)zoT~!>M!A+xFG( zWz`+-k=*^m<$4xWDd;i~l_Tu0Z06l&Ga3s-PeOj0RF?u-zv?N)CSt7m;trjS{Vi2^#HVKODw8-4Eud_)l zsIjO*@LAv~Svi%}UN zZiw{lIXiF2GQvgV^Whf9Ne5`Zeesvax&wXUVzFXhh{36V>8ESlPO)pd6b5VFFyF9G zr{TrDi-_Z?w38M~ioLGg>K82-T3NL$5W(|YkWXM%=-Ymi2N8mog_0Wb-_{ENChFY5 zX!c8Os!6O_y=YKaMf@Ayrn51P#WF!_6%<2S-u7*@9bARKw9qYWnDuy=>f&$sQ)fy& zqCl@Z8y^G)RY9VI#+bWFRDfh5H80DFsVRyduW0lc{Ch1CjR-%)yHb$8q8A;a)HSF9 zwyEjo=b7AAE^WhfblCikt`LcCD^^{<$>Z7c~#N3i=GqdMUvl?a!o2_*g}+|8|( z5*|?Sov?>e$Eht{Sic8v2=KIm=VkaCFZ~RGU!7Z)grRrI!b=X~zJg=e66NhVc&{lI z%H$4y_UYsKe5A7BqTw0IdH#4t3s3)AVF?0ys-f#ivDtbi2i^Ir%E{PoVt)y!WAUM0 z3r*#@iA7`Po-m@>6&xtW9G?-IyYO3T*IQ^o4B|)M(VQGm)qG{FZ^Je4rmoK<*3u>* zzEBAllsRT@*L(pr42MDy%zY_y9V=CHXs7Pj1+W-cz@Tbq{eQe{(MOejW((jQ=?Onx>hOpvBn`(1#?I)oX zfw~d=FxH^>IeZwpimyjv8IPjdS^jF_ezF7*JU!STl>0>Ge2L!rF)0XGInxE-Qp2#= zCGYL|OOa1;sQ6YpIQN5mG+gUsCTp-?=++v)%+sWHje3Gex zI(WDpZ4pjzdf(jl%eB2wKwGIe@+ll!*!tr6{3HF8HC^5BgMA#k_bwE?qfxz~OY#4X z%H_vkM1AFtW{`~eJn!#+%N<*ZbLtqJr%VaMRakLC4%hw{(b+aAUN5Jn^ z7Gywo{vV3e$B6cCZoO2LDg0-Bel)qP&sr(VF=^@>7IV)~MC_DgACjTuW2)WHe0Ia_ ziZZPj;Z;AEAzYI5rEk||^=UWzy%$5=KQ@w)T1!tR-?+*rTsH@oWvtbnD9W_0g}TyA zbTH1$?!M~*nD?0cxBse_+LFM!hSF`V(37d8ggN`glO(b{-NY%`kEcDw2Oo!Sp+sAw zlYWf<7u*YZEU8I)l!8OTNwS-X-<6Rz^{GE^C}U3@<$4rKjU{YLK7jJ%2PLGqFSxyj zbKg+5C)?BNMPhJ&GyEDD4eoOH$YKz>ZPS!?SRylezso?ehWj5%dI;(|_#4%S4D$07 zp z5M#l&w0Tx~0+gyejpzoNYep4&XtxiJS`jPSf!vfCy7c=%JwaAn#&ZB@%OipV0P=JB zuVgPF(Qdh*u!_r1zB{t_{}a9LAci55VU7qM?P)3E8+S^s0P@#4-Mxy=E58&}8OL-s zj6LqpG)9YcsS`3Nh^`Boc~17eN`r}sqSMM^42_H~)s{kmFnp`nI@e;2ZzjZ(XEo;K z=QkEcRg_4xcs=zB%H=4zZL*WKw_vg& zr8oaFn%+#*kv>{!lD&K4TKEkEFf5B)jQ=YuWQaUkpFhx%LbC5~P$^R?4Z6;?Pr78d z%=#GUY*MADq%S{o16E_NF^tNWc7qNpzR*55zqv0FfbH9%TKC0EZ_Q#Hob^HgQDHb_QW-OTwV0 zEsa*!oF)+dgs6aTGtdN${%Se{S82XS++1mj@xZy=7BH}Kc5cm>tg5xFTdIuciQti1 zz{^8eKZY@2{)dvxF4s2g=36VaXP1RTiq$REuk=34o_OjCQPbct_B5e}dZwi|_OJ(H zek2BnVeiIMAde#ZU+C7r^5QgRnQ%KNRVMqepg2rVLFScXyg9jDW6ul4~-uL5qJ z5f-o~VMQCM8E!f_s7uHHEJt}@tT%)a0rK$1LLO+BJoivjhjfmB!sbM3^e-<9H2G>u z#*DG}*MfIa^MieiK8o`4&R2q}Co%xwkiI&dq$ z)fKChsaE+TwMaJ9$_Oq-P*1~Wo7hY=UG@jp>JsDGf;@4arwl_TqjS44w22iUUT@LO zN|_At`boSo3w%ej=OTSt$LPu!s&kFz#A9-pHw90F-V>?fx90K4>iuLplRvnV4J!F{ zU2VuB`>p$YwEkm)lT?q)wfzL;Twog^Cgul$FN=za4xUX7Jw-VSeer7H-@9T&+RI^P z6-MfPo)0Xs_ckw8{jv*A-|=sm@qPx)Yf6eX0^N66 zXVUJmlVtb~hY#zTn)9K-J^Ic)zSw;RCA45Bttr{oJ0Sezr?tQ)A_X2k89QyfC{p4O zXoXEk`aUi5f-w%`V5}BAb(k-&F_h4lf`@B~7^-CghGS`;;%&mKi6+Y|a&{&S)UYI) zDS}zesa(pFLNLBE?WZ}AHqMLG~=7e7XB*5f>Q`? z)FZ?9OzOVHctp$#J@x9%?7JchNG&=AzdiUS2xGOHTUKdL*i(q;6B-wZ@792oJ6yws z8yCZRUQwwC4YdCn-}6-m-WsIDy7gHX;m#bF2`}!v4`hO--o5{rV}!mmpNgvWxDwmRQI7Z1h%QYm$f(XdPpC?wB(++k z(VBaG;@0DR$OlTF>fg5~E&uqUjdnvi%g>qY9Qz|^@!9Z2NE$hJ#@s!OqP3w8H+BsFGIk5s@k#XfeHb>XD42e!J*!zSwg0j;_Wp@BnWKd*g*TB{G?#CNXQn zi$-Q6zOl+*PXd3nBltfQM~<7>iH(FuuXif>1c!}~qY$J{SVDJ8{)HF@`TZtiT?E#U zDHi_y@f&ot9E*@TPBx=#NWpv(Yb(*i$ z)AXiD>>1=Fp*Bf=PU<$mHLco&2-lkn=|fl^LU^1PUP3`-x>fSD8GIRwf^FpT9BAJZ zHbp~S1JaI;1b62NViyTdwO z9Dp2!i{|#{Aq<^9arYNnWlYZ}h%Rv_-o=OF7pGY14v!R(Q1WWGb=sdKY5o*p@apad z!@DNaPJnKoV0h3ek>%zNsPkAg{Y`|weP>JZq33|&+SfPZ*ktkS@;>jr_Z>nn@Y=!m z3Y&0Z`lQSl@G!O)L3qW`5QnFIKmhtTgUsw^rqrr#xxJy}JxCY_Y{2%gk*leh!L0w| z_0z}VMk=XOyazmUQ}SpYQQLb%BCfXr&+#7cjQq; zWsuyQ(&PdeM#z+DibOgKKC8=@@UqJf05 zt7pEh(l{O4O4 z)_?yO-=KhkK1@)bfwM12lkd@~jJ=7IZ80^0BCTqbvu49GLW)B*|{rZbdkX^`zj>vnXZ~1QQ7Y)9T&WCT+{>`hb z`h65%;n%%!0JZMD7M|{-c{^%V;WZ8sbjiNjvIJ>QF+4BKthjhIJy#kY$M4~&rPoZM z*WqR{rqa>Kx0kIDsr*`l1woMejjM-Fg}2jQTF7h4!>%k}2{*rvzD3XSuELf~aBbj0 zq}x@zlD{ywnK9!#8aWjd)6k8>o$*V=@Mud99N?J@VQ#%!9epoD1*hQZ0qzb?hD2AW z?~`bGEYK6dA7mSSUYIZCt^I)!0A1zdfbG}Fg9^G{4XywsPpW7RPgFV^{d;@OFv-!< zuGrIt`+264pkqJn$n-_d=??s_7wcIs_h8q7m(*a<5ocv^uJ4xF&^-|@`Dzu%b54chu54=--|64tf4vL)e#rz>dx1gf%U`794^qHSGSkhKa#cFhtf71QT96@ zbsisr4;vkzTuRy z2PSEfx`Msd(ZX}j+!sxi;X(rc-&yDumAP_DPrxlN?+vH=_&z!A3zP;m{Va|O8u)3(tOr$ug}QbctvBU-{Q0ZBPoeTTtt*Xm`7nOV)HEv>%=RR0fKhLu zIw)7j^gsaEr8JRo^Q?2>e=HjOUQ&z0p6{S~J*x*q=C5(f@JT~eiK2n@QJ2xugWoDg z1$%)vqGbO5vz2Cu;t3%H!6jV>H)j?TQCbG!M*`RyK-aF9~MVU(*U{5W?KFXa^ zPYZpA$iJ3B?l&LScBYE6G&e9tTS?j<>JfZJNqRgA^SY?Ge0oL0ds%f6(h*8Ujk~36 z&|egG1%7aptnl{ydfU=mvqf@i^al5}m7JzDa*P5RnEHNwLohOw)$Z>rQ*5%HiJX({ zt6>{rb8QButTe2PXUuC?;~`(H~Gbhwj7eiz~fWIj{A9W1t>CY0&C0cL}`6=BssmwLCV;ex>k78!_g^ z{KvW=XkaW0!q4L;p($`WV?G*6w8h%%Qjw-7^m=dv+t#Y!Z;uS2(Yeo!&*oqk9D;mo zQ>T=!6+L7rI_{een$>z@CUVO*5+S6Jqn{=BW{N4XfB(|BhRVn%QGQG)g%1g7fms9b z1%1<^ste6tyh2x_FbOvhOQ2Xf#W*2RCS8=7r@%KH&u>@*^?KC4$N*CuQBe(s2+G4h;UM0u(Wh;nlj%f<*qaf-q|JiW z<>7@I`ol6Tk1_r9QM>U3L|A%{owT>`rNgrqvKv_n(~N`D7D8Ad0_~R6m9Jmc=RFLa z>h)_Rm&sM%H2OI5Nl9PMnV{t$=0Ri?fb~~w%l|q_Vsg-@Qy$w>^lnB~A_lcy|9p{i zcWl#?faDhEE)OAvushn}0b+?KMe;kNCCJ1*R`Z%TUA#|vlwHlf57(v2?VP`QCuWn_ z!(a+V(|e>Kf5Lt4s$uQ~gAq|scolL%&Slaq!64i4ZPDu{hC~|1(AJ*c{EotC(}{=@ zz;>q#Yxobv5N@3pGT_B;ZNNoNZ26jIs30M*lE2Cy4=E=lAd{1JF!^q{=f%&EA%q=G zG`PrI15TD#uZCUKkr?2?uGO$#$kA`$$J}?|5UF#tCcx)r6HH3^t~>rOF53NhB)@9b zU@8o9)W2;8doDWMcsb-5zld+Ok=0cdOmeV1MnA4r7g+1{MaNM~V1Gu$Lw|9D$Qckaz4yALz)_2_FG&)HyVL>4b(1ZC$H-eUV!qpLA^#%9e;YuPa z*$%`Izl4RP2{f++o6I+YgXCQZS{Sea30}&9ox$$m1j>WU4lzm|qMDt>ATnlJD%wpS zYz_{S`wjH2(@BB7Kg9q`DW-|&_!N$n-C-@{jEqZFY9?tM+0{4M6z<;JG??SRqdH&< z01s262J#lk9FsToM}sXv@zCjY;pb*&+aljSXV3QwM2}Yl6lP`HF%fqYA7A%A^ee^j zN)41)!Y}&MPrb`sePnB-d$5+jzc-^KBJ|Sl`TH@3NuM!xJj|};i!80CNrh#%#e4tr zF3H?1eqPmZ#2A6JLL)*#4&J}gE1h!8zDu^ARVx}PR^o5>R;l4Mq6_7_FZ#g|HrY?& z#Dp6!6~H6y5@w93*EWaHg}H56TmMX#yxyb=gkF&fCw^w)7&vY02)G)%RtF_&vnHKd z!xM6VVMilp3Igu0sB>WnTv1?8hQZzk!3=dNI9@F?Kgn(2OpY=jq^!rSbb*oM$my^W z*wa?Sr@~a)=7|hp7a1;rA2M{Z)y54Evp$=U?{OSw-=Z6bWD3*ax)kSno04CKdC4FT zM31!!8VK0VXq@0IWwi~}jHJn6Kc;l=W?n6^*%4Wsx^p>;&y&HMDU&}NP-e=Icgu;w z1#n&~l_oofbU~I{Zv&f=bS)l|B}&@2xp}W-zVN1kel7QxR;mdX1W2jm$oINFX8X&8 zQ8}XG3`3p#!#a2%A)vYRG^^6G7qM}LsGUC}?Drz6M6yvA+%%o^j=)aVO^n7ZC_sjn zMOO36`H-~cv!Jd#UuzD8*Gzs#by<_E$hyx&cz_RATwcx3KdMY+dmpeJc6;ayjJok2 z0_=9jdhW>DfOFGOY`-MT%k*sH3KTGTee&XZ=@mdz66_-JHF^H~T)%S}mT_eyIJ9fB zRl8o&2QOb6aRWX)&Ys%=)EqoVKWQ-5*^IX2Kd&aXWplAF{>D1aye>{wrAHJ2^sF7i z<{(_))XHcsWURsM%1p~h;!8BcQRb<^4c+;iaU-S{`mGDgT6t$)mD1gyZp<#;&i1C2 zK>HVc2UNG=fF`q%+k52R>e2CGN_IPrWW|w$33tcC1#|ZEzcUTW*i}NK~039(dIrY>-p@e{qOeqUDK!ZEq#^M1`qrGz|u5*ABIeF#%|qxtz37MoKvT? za8V!xWT?^pk4#3VPl1={Ns!{mCMCQ#w>gqTp!wG+g%5gkDORUx&3Af2ZGmO*jE@OC zRQLFt7|uKUY_-%*Z4D=e`p>!Q8U^MUC_SxA&DWUxsfsA2I}%bE)NK7m`&#|*lKxrN zwb&f_2L{ZLQ{sMG!yh*-e6qJFo!@Zi?{YO8dGJh%G;q5XH|@q79;*-6;TI zNvbw)p=3w%i9fAQZmDQaqbrdqp@AYcp8P_I+o68`+ClWZPu!l!0~|gC8!`YOYCu0M z{OHv{jdEky2Wr<)W!>zR@CGw0cAxnlMAsP9QKVGHX|*-)@)C!W>6W}RykU;wv`3<; z$lW97i+%_~?id}enRI_*+T=+?6}Xp6Sz@G$TRuwQg}46R>hOnHB?b;b!32a4a?IvO zzzf3CUh2iUl5~M6goDVC*VHN=eYQF^Lc@3Ckx+8rd4vR-;BS~8wf40Q)72yn%1bNnoQ8sl_~8?lV< z18jl+q5QY4+?`u#K&_?ptxluR$BurpyQ*H^o%a;AsIqd$BAzdU>cVptlOX}bDTKYWx;D32;M!pwOoUA*6U$0aCE4#6TbvLJ4-#E2aU^mp6%U7RglP!7IA7%+ z@UA@B!62$I|NQz&1FO;bDE?ZZ8a!96CufnVP?kNip{@f7(I_Q-G!YdC-7=~CRLHjphi!ck0A6;s)as|cO9q}c%YW7K!hFj z7Zvrc?n<6m_lZ6{r$klGPC=OeL*cL1JuVRmk-=HzjkEe51g>^=nBE*Zp*ijZ@EOl@ zFoGABFwIetZ-yt@t8q?Jp|672T!X$5N|)Ysxr^95(kfsZT`a-L{S^~FV+KT>io%;` z7#?98@?DF*>Z(pa(RyQ~)#)dwmfo}(Ap{$jveGknk>AJDV|-yRlkxO|atK34a|5$Nr;XdPjT+*NvHpCg%tq|#QRKyG}s*6YbQLRJGIuEHXGBewf=0$X4G_tP@)*C=yOxnYMVKo!|1g9$!rEZ|=t33qTbk0)-$z&fc{+%M@#PfLpHTHeA zYd{;DcJkRJ?%7pUskK9hV8%2uq7UfOsZBal; zfcD){Df9VCtcS7f7oZEM@Q{Hw&$@&#;`J`78B*4P6yKc6)>1#g-gTzkS7<)1-AjWP z!Ug-Yj%T_4>||$KY4rdX7g_ePg{G*ofc440FP<(nW4@8C%bKAae^KSJ83p+-_76W_ zhAbj(8$jg7aH0_ehm|(B%Rkbrh-`DOx(TTz`TnUvaw^i^+b3@r*cge{sijZd6XrMn zP>@I6EA^FFWH1z8iA$J{u?<57c`$1yrZt9Jv8F>l0FwM$^I!-gwfGW$_Ks11x>}Us zZ4z-DX|n<(S(ZJ>4}9bp8+J#j*?8ON3(j8q&TN?FWXy4LO{hvzv%ho$En_98+uD`M zy!Y>21*WWm+X0?GTV|UeSJn4@tEuh3e@AuG#S;dQOcxja4WkW?E;)ICuyUDXf+#Le zCj%rdjvpNHFaF9S@U=Ttxyf;*(-uPv2~HbIP#9f}VnYl=^(r}E1OYBnj(NId37tYi zxjRyc6xwW#O0_Sxn&g}3@ttoR@DyIO%dKvZ>hioCZSu$HwXF^LQJF=?(}0b#XcxIG zIiG$7{d9OPXxKF$jU+O)wA#`>k-h4KDg7;5W7PjzTJJkvw9G$+iD|WSZQ;80(F^({MZ6pu ztgKiSD$hg*C~5p(2@Ow`)4@c(m<)^+A_qvtxzaXUY__ZD#TID^@41#_cy0zIxsi(% zn#AmfOnjE9BLATz(iPGNPHN=~7x%p-TW#XzO^ZyZW?lSPargNIqLx_1u%ipyR@@*L zVVS8C4$$bYbmLf)nDyUd#P2EE-Hmr8JhbX_T%t9^@_T|*K&;1~t^glM;o?$8)7BFH zwE7K&pNy%;j~lF_A+9>MSuQ7pU0QmH_-p+v%%xu%&UJn-5gv6S0v4OZ_w=l|O~fvh z#X+b4p|qwyL+VM5O@&rAZvK@1LE9?-B5mhvZJ!xnpM7R5JlquhjKGId2xE8&{TI2ULT&6wbkd`9-MG4&9YLA zqj}q0RCa7PejQcS~^yS>`S3 zE>-f9M@JWOe`zp4;jM4QrTvzOF^jdC^+-AYc;!NJ=;)o~b&a{}pq=>EhHJo`4~|EZ zr+O-Eh#?yP%~LwcMyDl>mgIB`oQhok9jaL-!x#Obln|~LWoap6M6FRBIOqFv@tvNy zEwZRmu0a|58iq#S!z&eLt3q5kL~E&A4AfO`>$T0alkE$2H|$1bfdM}v(NLl-Zrq(I zk?gCUgSW!44{NGa3cZ?bty1A!!`a)91f3C)S8j%FMz8b z>K=Bp#aQwcF;qC=&5f@8p1ToUagEciYt@fK0T1R$ z$^x$r{7!@L43%WB3Fh0PUFaMiGP5xu&IDdTyB!)gP;mFM2V-_51H=$p#0mrZMM+A} z_xg5CaZ7ED!AP_>z9PwHE<|*wj#vS7#GOO6=SfxSQ)K6EQXOEr?W{~%5=9FG9~m4f z(b;MhdM1b4qEPwM-vMahkU>)SHUpso6lIPS&oNR1BfQf%S9>}lSO3c!0zAXNv}yTP z6*Y)19Zh1m^ek-fw*p}gq*#^oqMSK!j6%L_++&i=vfrn0@XTY3Ba|8ZZ0)it?X_$S zXMFZiQ(gWL-Ed3AYev>xG-9DTs;pB(9#_kCT#Dk!Kwz>V5ZH+d%x7?z^pQyCii{L; ztj1!KYw(LIbq|9q_D7hSfsog-LAxK;p0E%UyCh&b_hxKKS{ofWJ|E|VshVX@?!r^I z?OPUjojR7d=aD0>41qRoPPaH6hx7uO&DFL})Q|eCF)aU~=r_&sF@AD`DJ#OY3mjKv zctQpc>5{$VnuB@Vihut@(e1fG71-D$P0v1Ivia(yL-31JUt?l76?5%11&T8jXu3Hk zB(~;{Q73I-m_6LE<2UKzd3zkunMOSN^Ff8=NC4AQv}}n}?NsJL z7u?X-w}HM7#X4I{ZJKhrk8(j?8Z<)-==2q)w0(y(x9J*i7%T4&3;BHTFsi`CpIZoGoLX5)+6OL@;eeOs=D!VEIxPC} z1YOgt`koyhPe7W6D`qoHgk39DQNx%Y)xtw)v{>@sPPkFvEn7 zEa!~dG7D|wM88$1(dFT{ae(==4xGK z*Xq8F1l}D%05uw$_EAEipqU_?FHr9dk^q81C+i6>7exi1hljU%` z>qN&JF7&kT;Y)jsBFa;JPl#iaO!FE;Nx_SNfj})A&23n~x4IF0InQpx;@14Z$=me_v3#<&RUE%3m9p&Ctbaj`c7PME-=m$f~yzl_SgK za+H2cL#VV#dHT4YwUCvX@M=xg=?UwShkSZ4hJBSJznNVds28~0&8iwpa&P`5Elg7? za@AzJ5!V}t)>BlvY$1Hm{r>RzX-cO9hq4Mew1B)l&h0-ghfvNjsAVuUu_wohN_=ow;MkTjZv zSjdg0Ij=F{gP7mGJ{b-^zovW=t3pX`wi60j%CehQ@I+J9)sgfzu&Q7RKrJ^$|2H2) zx{0=WbrN4D%(>xf9OIUG`zAeJh2-HoMPqgEmoz!QTXnEWW%3>)@OXc7%A4H1s0iB% z`q1HeF{7?p)mfyW6_eN?O8o=t`(4>i6G@}xcbowXQIuzjGF(OmdD~JM!GFmdceIGH zEr9zPfTPcof0MfT{Vi!$Km?*ZxlSix-p zn9?rH-bFM3=|x7B70seAOv$jo$dS?+r~O)Y(3m>;X$q!LbD`*JT@s#kJ?-BG=vH0^ zU_9MEw}lJW_L=AOlBaI|DzGxDqJNt1HG`7VRjI2R`M>iOh?xJua|~>SC+~oi)5}Av zTKs<}X316MRwEv`7Qy)9l)cqfxl))_Jp4E>*|)WMGKdG6h1kaZQ=O8Lh!(NlhuPX$h-bQZwHuMWMm5j4}NySeI#OnwKhICe_oj|cX*uAi5#KZpy= z$J(Xt(QC-r44NZHJW!jgbw4*(7iNL-JEgGg^rD~UQPhndotow4bbY9*-SYR8LyVS^Kz5K&WCKm0()MS8|b35|9G zpNMZ|D1@*Md~`pvy+c{g)B0TRMpm_>2RDR{epZt@%9EN(vBvzkwEwJ&upee?pD|uM z*YxwyTbJ+oj7Df$5JOl|hNBZ_ygb;LJu`IZnyC6b~n1(G)n0 z0pb&qI9HJ=2q#1Z5Y@zLfe41h5Fg>cRAV4JM(>>L-<)EonyRG^usg+Q#D7z-5zafx ztyO7v^hgdfhr2!dP{Ep{jHpT`Z5mZ;W=Y3trJG4K-z16Yl@+8`i9ZC4y=6}ETKH-| zCUq_{hy;|gg)y3F`Y@|JgsK<*z(1{){`{Y_%r*Iy*9>xIMx}52_XIBx&!feX-jdH_ z$KYeyR2k85-jHU$BkO5eZiVU-@k;26&6mSY@v17Ryw&L~!u;{s`VjBj)}bG>*LUwI zT9rad3=rl}vf_|Ap|Ud9fNYucm49L1x>oafN_)eXg~^izC37a2nev!7IdoS4ro=>v zPG&Y}!(3q|Id5A-eVc^t#OOE^Hlm$pve^lZ(6%p*o7Xqd9 zgDe}JDu)pg9f_anL88b5($22KOOEFckfT>+II!X>m$I=#2^^mN%)B`z%iqze4!_Hy z_(_3`?%ccsY|*W@j4051)NYB#65%lWbeZF~GF+!v1dHOogsurX4GSJ?p2bD?pYN=W zr^qAoiDK!9gJw8_NnZ5m9Lz8rO!!{jKdKc+)}X4#6U3I$O128%G2vG*ba#AdZ754V zw#8RnFImK4E6+I<9O&0LjIc_W__49W;F9UVgB02LgQ+&n1-3PaUz;5=pJmRY^sOGVQ}H|)$tTXHvFId!JZ zjKCj6BKVKy-zg`4E%|6`C95q8jK^Z&;{}}PQ96E_Buy)e2M+J1k#yLC+ zIs17JyA)$!R_ubJ%YdtDZbTOtF*GBSA?iHE!KDo0p zUxBEIRCzG+73M<68QIv35i(a%euPi?)|o+g-Vp0b`2 zTDSf zC#*~?>;U$*igk^`%pg)JvGCdoz zW^{N6%<9iq6ko{MNN{R&30jQ*P^P~N#BH&;%BMMSu!wgI2-yX=r*lM(1ER?3;PHu7 zBY8|M>5@?;s*NqR!_qkj=v%H5dBd)5uee(RkAdWdeMHtFzpwOCI!lY5YQI~h6l2>JfHz#)H zn~DlAH3O8&n$uwWsqUVQ_x=RKm~f1lGGE29QheyQV3psv-#c%O&>jUoh?syEWU{Pb zE$5QO%Bhlh)u%>$+nTH=5=GMN7xpI;ger0wpV#Yfs0CRFnZ)v(Xez6A3VWN6@a}-^ z{!wQ%_zw?bcm9IO-?GnJG?}**UsFiy7C+*PzQc)p*E(toqO$)FB{S^9;%xes44)*# zd(zOnC@wGJwjCG{6&L+)K(29^x&fA_)3+ARh$nG{QPkTF8Uss4_|3ME+|rT zKc}H+-vBwLZcH$7xiMk_G_xU-Pb1&8o`4cUx}*U9QhT+!_?g;=D#}|ZgI`n5s%*1$ zC1vfk+EFu)!pK0++HPwwVjfX;n1w8w_f6s6Ubk>f*FLcd@@xhPKaR2IPLA#Uu81Fb z6hb&cQM-Hpeq%6)upm2*xQ+ffF7T+EZ734FyC583ez};#Flk!!PKIo-@>-E@SkKfCn+@l!Be?RBKhJ@S{&Mm+(1^eV_ zh!ns&GyU(2z)4sGH(-~q{rW~ukIglL9dQVHryoME0j!~(eQ2ivx_RAitzDf{hm^iE zb`IUB@1K3Z&QEZ)U6=F{64?J1mZVy`^zLNw9*0ZS<s_4GrG==!`2oUU?T~Jva(CO} z2g&T3$xI#l>J9fhd!?3-`U6_jqo~^Ci zPuBc3;S7lfWh!R5GqgGz*04V`W{)t7m@Coudw3YQ}2s-hSCx zX^!!sEYv(mjkwMA#>U&EKth+pV{Z33cL3S&JxkWw3nizf6SX3Nx13q^FG9QLP8}S? zOL=+!Ty&a_v2;PC1?P%BAxDt2u;En{@{IQq*$xdX0bp)yKW(d)sOT{t7^;5HSn9j2 z`ur#N;Bzdl{3ZmR0GC0WAlqPC&2>!-Jwv96POUd;miV-ch1mN;wyrXfCuh%Ph*-6> z{Jg}F4_BcBpI+jB=yDXW>D$f+1~$C#HPT6;&9`Mu#Xkp$=5`FyI`^#oMyX}O4}`OJ zj_LiLvQ@?!E(FResBh*Laqy3V_nTJBgSl{@{+o>-nKTQQA65>^m|*u`PJTJ|bV)>K z^)%NcoDCB~LWIwyI5gv?(kS^*E^rj*{*f-D;}S<>QR=kH4X@tJY!u+*gO$RZbs$%z z^!l=WC5_5Qm~_^SVc2=GPX&pzhXvhz$f4*aFX;9It$+5``R0J}Oof6rcl>SU3P(}R zEfCA=(gt9O)qw1DTA2p+dBO)(QsUTuAGsg|lz#@7XYTQoF^5`HH89K5C2pCR@miH^ zP5#?>Ld3Vwy?-_aD$cdDoPvZj@RS3=r0M5aS(&}{KHS)3(txxBT%_Xk4GLhOa?F>8 z9ERd)n6|)9GBLgliet4kr1hl9m-FDg$+$ks)O<_Fiu5I+f`^bfBY@CgkwnGvEi7ik z*9(VgVvYh75wcRlqJvhlaK(8E?X>3v=a+THI4)|YhssJUdO>JX0zO4^PA@i*B01#O zJmbg?T_qO?=$4EIMy>IE;<_x`Ei210jkM+vNO^mG}qSjh(&yQ@{2`+Hx9UYlT>_5pD&CFNa*k0elh4KNc5D3u_|>a7gr6# zzfJ=IO;oD~6CMIE>@XtTFQdjoFQY=rb$NNUi}Np1W~okqJVz^=H7+!}YXRI2XqN|C zXSc_nUsOz5-44^CnmsXxY&9;(L96h96CPo39;k z?&_a?mJjt%OXLhBf6}k2hNz1l3`7HmQlhHn=Kg5sA=m;Ct)~kzdm6PCE@5Viom3Zt z21b3xpCbji2--ThC%#6%tBom`nf7;nKS{K|Gs6>piv3~FHU9&gE?=L3%gQCg?H+X3 z*xX1qSMUa>Zp0#8LUdbymtDzCvrEEG-cGnfgsKIV{y>KqN9{_5`2wF&DH=I8xx`io z^92=&hV8L!3yZ1dxAls@rs*3cvZ3;~j$*gZEcsh~LACZtX=_Ktd10oofGj^3l%;BB zSd>omS2`qU*@_CAyCTvXs>z#TB#e>jVBc*8$Nz|-7{Et88*`W|Ua$O{%(ad^Kr(Dy zp|SNEm8*~l-_Npd8C>S^6qa-==4H!Enrq-?=#EH#)8F#OOr$Pq-@PqRQ@j)RhFir{ zBO%mD8b@xRWvwE8f(w$6+V(w7^{`Dr@r7wABz3F*^AF8(US@^ua|TMuguuj@tb_Mx zEB_puIM}Ibg+J89&x^cr?Oc4u`J$i4+v%UyyEQs9Oy)_^j3lr$D#dU1-pSYbmV9hg z`V{@Xj>q%*HkbFbqmwHDQ>Nxrjg(_^kfKpa^58WKe5lh;rrdWUAcx?SWO2NTWXt{i zpLew6j5=<}WY~PASHrKp&yV#q0(hPiTTNl)swV)lRIyj-_5OBZ;z9*IttHw%J|c%Z1E+;roA^O{c5;s9O9X%oL9V z{68=w^puX%!sXuQu}k7*#tV5CC{RtZe+oBQ8?tIpGCMr0fRT~HBXt~5eiL$p_;(u4 z_3RAX_7VazQl!rxj%@D*U-TQbWuM#-#<8Wp1+%jq;Hp5FvOgX(Dv#zwvhtVBU5B4? zU#^c#&d44VDl>Og{GOAix8GzxL*p?QX%UVpn)WBCyKd{8 zR%PY4yD%4kY*DR#YZt5JA)&13RgOA|4v}TE=YMFeX(6#q!26R^%QYnU#Eb}Kd4AMD z>=7mr0d+V_6H$pFmHK`Y4;MeJD{3=z=PqD+enm` z1fW?z##p+BpK&8v8cvX33KxFJ03T;C`%f0ct{ideMa*D?R$+QX?ZpSP9bcbjmma@v zYVcxREzJ5s2sux3X|Ph2O0*9$q$}EFCr#6Y?Zdsm5d~4e>!QKFAC!9R#D8+~iudVKA=pDRz3zJga{?7VJtz>B z>}pf#k8-A@49WK*t6Sjs^`$=?$>x)QHEJhLL)iYHMBY#;hi~1J)P)42*487v?UaGu zTPGKls3Ve;C|pMYi3%raZ$lQ*n*L)sr7DzI(Cvc@T2E7r3jZW-@E+?_i6&f(DYYMt z(aRwH=yK=rwVG%8L7L*(*WlS_czQo4Jg2M37M9dzaRCYjjGQ|T+@17l^qkKHV5vsD zP^pGY^m0F-NbG|$Rr*;JrvveF^yu9_hk|&U(izV_N7EqLV%hgXC|)Qk3elfJU@HCl zypiSW-1s!@pS0yXD`V;($&)l^nQZSia{oi4529s;A zlGDBVeQY+vT-}W5PqqCjgSxM_ocP)xWxZY*(ojX^FGYIdAZFKkB|@~7;qhUsL0H7T z;lQ&a04};(vTT=TonTf`QXTi^B`G;eecz9o<#82kO!xS&sqbny42DiU{#Y^GH5Z`% zM2Nx#kQv9_$REh>E6RB#kO7uvnReVtN~bq<_G&o78tB@R)C~^pZK{D*38pSl7mmz> zuQ|@9$cW-(JGK7(5&+v2n`o z1*P{I)KXskbE(N5nt&1PZNnMGb9HFE>|rJ})2aPuw34M;_J{SF)Uct`E9zgf3hh#rNN44u&gP zL>=;8q28?5uH?U{v`9mV1ft<9q!Ep7H8Z>(MMnzVy&WWDp7a!=(N*8XPAM0orq@e? z3%h?Xw8@2*%G4qZssL*BhzpcIUbnkjZA!olU_Rb+EAjG<_jO7dRmg|<>r54*6OL)7 z$`y2!FA^S~6ZX*}MdH~6Q4W?6upp=hw1EAY2mG3Ag-X(ljH;%7a**v1zt06%@=%>1 z=tXm8A7dY0?-FoRA^t=AP$*a0_gEPoaN&)vv0^8OvEBRecqt=aK{O4wwT%lyZe&=S z$L%eM+}KXZ744O~k%v5%#eu8G#*uXQxDk&j#8Tz+(E)D7>XrOftD*ZfS;fnBwq)Iv zpn`JYGWN3Mee#oXG9}XmYNGrxP|W-BgJYw-Z)G<$ls$E?v;xbESo78x@l>2@aP%yV z`nT{_n+{9m8RR5=Fy91&{KV>5i$GczHlM=*$H6n&#PoCxV%|CxTd`mlsd7MpEQ zVg*9xo9(d`w^?KpN?_ZSq~8;5KHlFvrAK_ZAN5#SUc)n@epbhoXytn#_+%z@3@B*)uE+@O5mkz(XLM0 zQ%go3IYdb9U7VyKrkdw@X$TZw}1pYGV!bG_Rva6N}@Q$PH7GYenga9S}BN))Yo-sO4Kklg>EyW=OSKj$P7+4 zQF=TaruLS>F#Ag7T zfzNF_)rNb7JJ!f~l@iuL>fSN91qEecH1nivE4+6tOx5-j`iI zsbu}f&2wABDu||A{TeSmrZ?d(+!g2s%lRil&t=f>?&M**7bmjslkApHG}Jo!zwsXS zb*r&tlb#rTPr{&pF2>Ug)}#3Gl6>%E!BLUYdZr!W?Aoxyu?tI9xmlA-|rGGi;+ZGXgQ={zK-{X-l$-(p} zARwECQ5F1bB+VF{tkEK!ccGtM!{`6iIt8BZV z{7fUe?B*<4M%s8fe~br(yvP%)!#_3bSUK#GFeG;CPOVd4zgLi-5dAoiAQX~B;Haq8 zOHC|9%;cUkO(|sU45x{S`vh$?m?P@Fb6mXL!ZpcY*H_0jGM&)Vy+;sa@e5%!&HJ#O7{>D|_nbsARf!yx%h}r3|5*BIG z)r4eL+e|$@Oys*EOltE8DFn>i{t~MbVVUjKd}pU>CmIX3vn4@tO{Rtu8m)9(Ph0eR z=xdR{Car-??YKF7O=>Ka9rNn-^B?5U@ZRYwQ_q=%D6@ZQsT3@Hte|zP|Mhp_;2URyjyMvzjCc}KlJeBQxBy4;i&Xmn*uvf|(@Q~px;=)R{Y z^Lu8uW$R!%jmpYkx?-ggZuZH^N7zK$@4bBS6R>rJaneCVf~pYwn*WzXBQhhQ)~VM@ zn%MJ`w!;C*Y7uSev5WFgLzC0gOr8P*K1ePdqHz~vqnjhyR`gW7miboXCc5SP zaVT=Q{4lLlSL4yqaIxE<2PL>1ci>-G%z_%`ZnQOm8N)RLXBN$+e$<8!$08GS5Y+@k zT=Ju{5~zWQe-u240O=Mv<029=S^HTar3%G;0D0e#>N>_%0(;I*XZ019Oe5Y|tEK@7 zPK>zprOz~Tzb602J)Cobg%{mk^CW#T_p13Nk!M=v^!4S>r_zi>$1I!s;7$q0BFuXK zS3>ez7muhF$iuE$gmdW@;%S!Rk>)BkfKe_dd&7jJ!dJCm&E_vXlYuMEMRozTWOivS ziO|~$e@dgac-Ke$y3cyd5Y*cLXa34gYYE%uzq6F8wZ9xe)sUyg8{PUlD~^n`jgCE| z5?ol?*k|F}3-iNzK-Fqm6CgSc#Xsl++i6A_mr>WnGR%wW3ZXC82f*QtyRLsh ziCr6%MKRqmlgeFj;z6*Rgv2qBZ%WIR#7S6@D3v!1%AY00rv;AFRoV+R1LsZP$XwF+nt^_^x|X1;c=azt|p7SF~AdkbVw{=#}# z(5=)pc?Wk>VoQ6# zLB-UF`VD%TA*b=nU#&5)9=OXiG8`5gku=u|s>|^6jS|=V6c;%Z7z-3j5#e98wnmeX zp{Drs)#Yp3>tm@r3_|Q1rqWp=CJJ%fRbk01x1-2QqrFe`FBL4m9^$00A_9Xya!uch zo=_>EX0748&rNdn&2CE30mtmv`wt#@i15CY;af4&|Ih|=dg0O=bboFIRDr60i7^oz zJILW=-LRNNPIq>bUZGh}#=T90#f{f(*}sfCS$p~0a8Q+qpHh5GpN-{-KLfeLs4sJ< z3TEahf42*LNl!51mYLg2{w-ZhhP9hV9iMYFsHi0EVDpeM(s~XG5TddYz*&&`5&WsN z?nB#T^-P-OE8b%tXWSB#OCzmdqKw9F*R1`@JjCeie`u+qLq`28$UJC@;5P6_Prk*) zocg8{VP^*Cj);5tavWHj!mHY$pv^N-Q?-5Nj+m&osnztWx(XlH zXa+T|PE(q}Hln<^ts&E~-UuT*cy=p!?z4W|YO}|{(CpQH+8lknvAwQil0}rLJUB%@ z`^JI z{rqELX$5BHUnwDKWwQM#GXACM02YeU0L3mpA>5$-gU+aH%3r^y05w*&O+)`lnk73g zH?cl^t@mzyq2W`KNRyT10?3oFf4hsM6o~uHbQ3(8aqBfzs4#Jg;*dW!6;}Ww@6Y+_ z5&EBtFF<~)8R%!`s-1UCr4N+(w?ebCpW=AAC*(x;7Y5UT8#CG2!$obsK+*$Y_T9yE zX}ujiUy3+LZVeTJ5HSmOREctcMRXtt< zjJY}qwVp-@a_eQ>=`Lj_Hn@XX@HE4*pTyo5F-rdyoSI;LD#m9}=-tI7x0DIvLvtAyuMi^C)USIOpy4{5L-wX-U%!q3MopqxS%RotlXW zeW2)e$_n#+z2S8%K0{`?jADv6&n*Y)uTQFN4Fmx{Ugsh&Yq!m(mK$3Z9nwvubuk9? zJ~`t4M4zq`xG7Hw-#&cyRV;Zj^h-gEO5=cYJd3PWk$=la1uy}89eF&g`N_8|@5t74 zA|S7qKHTY?I`5$JwCSdK*kBvr09wcV*}ade^yweE($|j%h}7HYz6rwZlt=2dVB$if z)E4~biAjWr=uW3wg>5RalEW8L-fZ=gThD93CbhFF9GBK8oJ>Jp)YP`;7l3T0hp@&z zZ`?#-Em-&*q`@ReOGKcVW*)Yo*-smW7p1Mmk$3VV zrQ(NFbafxBUXshKqY+jM*ooNq7cbQ8v=n2wD3EboI4S6AwHq1ytC3;9nb?_eSXtX# zEV)T+qv)j52JyY0Mg+jrwbuE>f}^Z4$bs>2J>dvJUs4%lvf@1^C`QErhh!W#bMFIx zTb*}Pi0E;UcQcP0*)c&cUJB`%|4VwF0<%;l+Ns*pSVB1&;970lW{}b9vvjWSRW&uo z>s6gQC+xlz2KiQ;YdyQbY(QDOylF{iX%PNN1)B82QU-b?0D37ojp7o*_M&Pg>-Nt? zgA(=5$y-%Z=Y*I+lhhF{`eW!|kNUnlv>3gxQH08~&(pJa!t8~|37!ng(shMdg_W$q zaL=cA-)`)gb(rfEL`Is&2Pcf>aUY__P=ey{DP2g^2@UZPoEALSwNPup)238r0Sv;S zQtGV6j=QC|y z(?3~eCVr2Vdm@A%5CJB$Kntj!m%yc}A)2G`xWq5a9P zw;Gqtax&A(X>mtuUU^a8PJz>h&5#QSmE&v9or^Fv_;3Mo79{wC1du%xoz=lNMSN&S z|L?GAjZ|y8>H%LJ!wHR9FnnG(e4Y%5&Yl#1gU!;S8vXDFr^I zQTc#+t^g>k3HP1_Y`);{{kFv@b83UPg`iN9592e;DJZ?pl(Tg^!Vy@;uaWUu-HZ{p zSmoI^e4azA83OP^lp><>yP=`jtdBz(9_RH$Y}*wB3zS8YEs}3cLb9pL47u`l1vh1> zL*}aGD_l*?JrV>Vqe3+Wb2?QVv>gd*tNe1@@!+_9yO`chbO;@E-&jk2d) zJRO$?x+|aSs}6j~)9ih`{3btZr|Sj7NiPoaf<`bI56-aig7=~w5vVdIHc4AZ{p^JN z0T1!jaII3s6lrO3vYKRicilqA{hi!$#RnO-?tvJu|3z-CmjF(%XRT$K?OHOOmeQeu z@C!<$)F%STb5(**;+0Jth;*BzPxRAVnjj2L#fBOtj+lp z`by-HhuP=*hW^DTXTh|gFYpH0;_yO|ZWIaS6yl~MV&=NB4B)3RC;yynkZIza=t(Tgx+X&+RZYavVB~%Ii zL6pb6A(aqF+c}G7*-qu4*W6gC6?j#p$NwPz(1j76EoGccX^(%&Vixz2Ya=Ae-9U%O zBJL`1P)={k;34B1r^f1kXyf*B?P-@oEIum6p3GT|Xcy`Q4&*FPSO^=`P3` ztVw16TYUO!X*6I2S3yE&ZT~~#_A_Rzq4Pu7L~Q?+2us{JA|EVB~(YQ zNs)`1=_6MiOzByFXo3z)b2kCCwHD@`QG7McH?6KK@x=smxL7Uh>H}`_F%NGVRF8g)fsHAWR5%Jhi%~cvkeJ)7~?jXF^{&?v~ z2tap2y*LepJ~l+!Q@6I0$?&2*zMh&bV@$Y{efHU#c^6W7%)yIzH|Si%hS%Z`ZO1<> z_L;k4cxnkL)Gh~5%oJ%vfwzkq5kC+ts6-M7*aUQUH|r0IMh+GBr0;#=!^R6Dg7io_ zq0iuIYUHJ=dTZiTcOnSj8nC}G`*Ul>WvRJJ*Gnh?yBo=l>nBa?Ww>E4#!AN*(_%e# zv_q*dpv&qPV#?|mGc8#Ay$tH4TR@DQgH0qLGU|aFa5jUbTXrv@Ifb7IS*ASF0Kf#Z z+?(i1IXQwB;aMq(2nMbb%ij-T=S-y`IdvE9z+$6exYEDM#;@B+E4#vtNp0KaV{iZE zmg8e9>iBrPv`lXui!hYPvll}`S$LHO=%oz_*19R3j*4Pz;Yzg|qbQ6YJ; zf}C`7W4q=~{MLzuwG;W3j%aV_p^f8s&t+-0 znO5q%MeG^ujrPAbIr^!VZ~@gWeZ^oe40QVQH{gF!>%?GGq8O?*pv(Az;zonIga#phb*xNW8 z=;bgsxCn$YzTnU{Ofbs2L2VFV8zx}*)Ly`{&^0^48=>We>;;4dmkH*G z8p$&gQ#IMTqJ4n`NU8{?v(8=5u_GH`6saL#D9SJbjD=&&EtI(i@q#ue9n&Fj3c+-R z<^-djTBGt1%b}TqvaYV_nI!4`XYX#f0nB2i8#F*yDB8zOykoAMMs=a*V~jVwN{)+O zwMtK-jyttNd1VhGDPDeRyN08t6(WZ373&dZ81Ao^%b|ZC%`*7jQ+r|XS)lsP$y(G5 zm=9PtD_^yfkay1f?H7oum0+{hNa+!~bS?~t(Q>l&&EZRkN!>5m91^YPqmFO^*Ec1Y zX}1uZpr^3=(3;S;Z(}(^+VUyW4;42L?dS>+AWJ?zU*CujvQNWe zRHlFM#lV$&m2Y_^|0s{}L7+IfVk;t9s1s7Ph1H`f?5x#g-!yyoTRqdGcZSgwKy!hl z_1CwDo+8|4Uz`6;xIMz$pS6JfGa$blsPuULu7xY38B478WAl&iF}Qmml1+5@pBdkb z4X0VLN|MKY!e`^|Lcci$9|YT@@~IwqM#n*8nUjhs_;2#G-Apnm{r9N-y z`Skfa7Mgd{+Z|LMF=n_!czR>6#?L|5NGNMPsy9WQZzi)la0;!Lx46qTsyd)ysSI^x zS4^AkZ)-magy%`GkHWqexzNpCBc{XOqr^`b(Dg`d`SaJI$L=$Y{?~v{H3>#97$jST zaMW*fUs8i=9Z2;O)cNy6?g*1AlAOb}8CBS-d6{}4qfLg#Z7EC$h%OQp+&i2<&|;r{ zHGb@39*Fqxvz*;YD~a7z`K{{rO?xrycpe1FLfp6K*xjDRW@Q$Rpi zUICl*kC=Vx*v-pVxT;m5HR1CLdwYoFjkz0CXmhrk#|2UK_8FAN0cesSH8POc51%pqELfyV}PpB4$xN*}%HEAd-?upho1`$|ZNVIF+gkoX^3WzWFv*}2b=R@Mu` zpnr5y>O-l>8C2zsf$J20wuS2O%e9_0{ZW6R#rDFE4$r8|PLgCLq)zONc_^@N{Wwiw zERtXS4e{6;KQIS2S#p)f)(>MR$2S;+XtgLemXjLkt@N99oqcO-l=zNrAV^4-0{7jH z2)4zFBPc_OvIGN@l`5yjTnOGhDDNFr@q5Ug*;a0Hgaso`c)b3?8ei+$vC}?uOHl5>MnO=P$PMoUL@FExwpTZDb!IKH{orpEdmvlaP4m}hcy^kx^5S( zt_d^2`h<`#ISUkD<$9VF4(>HGJA02D)Pz3T)fJZ`r$i|z$3suWIE<4}+o`anhLCY^ zxFx{iAKeM+{6i=4gZ8h}a5JSsT!JYIF?T$$>g9g&kHLkfqQCzWMU$hA4k-CUjVn3i zcVy79GuU5`kfhV&dWUr&LST7egv==Um$Fj}=x5OdZ`SA6vg|88T`6mo-fkmEsI(#ACS1 zrsPu+OgD>n_3Z)RQp35R5D6WScBlV#Vd4wn`0e9VYq5U<(_?-Q*alW@KbIIZ#nBl% zrPPi?-nUvmUAG8rcVfJ#eR*{x~3UarR0z#mfZ+wfq1kUos(Bclaf_W`N=AC)>C#gRlbt`vZ<$fvzKo`7D|Syv=hT1 z0mS*$%CpaZXtO99z@3^$#zl_#+L$-wn+)BzS0(^F|HF9md=MV2poG?cH|Z{PJ^=xz zD7urh5e^GQn0y!x^e}5`zsB zx?iX8;#0jHYTJUgWDR@B=210AHAf{HQI!K=W;UVP+kw?F!A`*eKvG3cng>BacJ|TV z8;5vZW46W`$0;)@!eKsc0tiW1f@+54>hjCp>@828%efBK197PpiInJ>2%`krj!IwV zFLS8`-tdLvX5{f-XmL){z{ROSvpK>>J$AjXuN%%yq2~3LLG6HMQsj+ljS*XIv1>WR%JrwIE!oZFXD z=uB&+!6iA>tTp#XBepLL#|s-1mi1buI$Ge&R!YivQ9xO_)n7uh-0baz zh2G5#4)p^o=ECNx)Fj~X*yhR@nGs~XSWG)@mx(^PkBuU-`TgSX?(C3CD8a%oBfoCdhm zncRG$6mJ$i0wl2PzN4e}yk`sDR+=8a{hILXlRvj@11&DHg~x)Lt{Q~=tOc~HbLWw+2##j-1 z9VKW*4->{;@Cgy|z(!nK`fOoa#qqa((mLiCx6nk>&Q+|6v^a&Yk>aXf4Qb1LhB)u9 z5tG;RjXJQGfA!%aInG`Ip|uto&J1@42ft#go5%=U@3TTKE_`y2iU$i1{plC=PrNE3 zyN;kd-c-6Wo5(_3BQl_nr(HKyILqbW-(23tmz9zN>&}Tw%*XyJzXn!0s@A3-(y!gJ z--2_2M;uzpN^4cOcnj=Fvz>=I$_hJ9Y@biGFbbpmW}-flF5TU7RCf(^2ebolthbtA zN-XT2Jd<*_Pd@+hOsdBf)73-C2b+LlBOYAfzhKs+y4WHq(_fk==6nP4 z|0yG&FtXBspTa2?ip=SklVRY2Z-BXJK9GsbbCwg6>`|kk8irtoJ2@D7O z5_+-@m&mqP=@+YJemqcRF$K_?=)SNzxA2g!B;>fA@z&Ss0a%+i|M*nHfA$|5_0i*? zrj$t1E^8jNg7k6iF`Y}Xis(NyL3}B8`jrblnP*D`9~?tPXI_>EF|w}%`%P&ySn%jK zW~Zf21u-Q0XD<2iV1I2l>ufwILvtqcl_)t0|8~(5qPF(g81igB)74ktyKTJ%&;y8) zFU1K1c`swH!v+b1>Nq!&!HR#bTfs2Zw=Lu2r2Wgnbnq#-^*flv%I3>>Y|$Au+GMrQh7GBio9x*Zla>mQju8>}(Ze%+UOL zh63a7c2Sv<8|wOUJWxuM(|#Doff2=!*+)$C`6?Ax7Z?U=lT~}OQIzIyc3O`{y{m`S zoKS4@($j2!l1wVH0#y|=mxj58aJ+b2^xbl{{fcUVHEz0-wu~10+k5h7RKUnVJI+_{ z?<$o(vEh3XSs)V<@--$rzdsB#gX!{$Gx}uHr2ZmYVQ#u}CtDsY9sQBpEv7hT8f9}t zneVvFi3gSSom;z^Mv4g~-80XM!jbiD$ci;tCa+FB&%n z$0GF&d$L^BfI=XHU$G@3;KYc(j4ky0FbS7H3QuLzh z0gv~(A)HV4lmVriAc6^wCr`RF={LAPpEdJw^JSlyRwtW%`4|=PE^sHV|i*x+L<8uOSNpe~)Yi3Yuv?H10n+t0z@GKKo~HhYB19Q@J#hI>#|}CH$`ABGCo%GiMAvBi`ZV9f?>A z{}|3(fo7r|n_pqZqxNW3vAT^SxHj)bUO-s7T&mjdjz17Hd83O!#^Uc}#6P;GemFDF z8VN5`Rl`%#-*1&K#%A+*wFLFCY|XcN&`Rd z6m-9(38!N%7_b>t+`G5o0p_C!r5FC#C{=|Ekq;iS^-x&dbfehro5L!I)HOECtTE?d z|DOEs6DL1Kdx|V!JTvWM5Z%Tw+rYxGR$R8CpK}}X$X9pCGQ#-%xgw2; z7LO2%wDC>rK7Z%OI9-qB%?O5k#H$%uc*3JizEpeo|FUrSA&6YJdp+~bbK08DG*7CP zTyht}7xvrHbr7D{Gq*?uyQO-8_o6!w!|>#JSomy;gihHHlFF{yaH$bBW5$*Ss7oh( z>;CU1gl7wi1+1wOBfZf79~uve4%^80?6dHpB}#7PbEEgRt3X$$E%6VaQuaqqduw;o zl(@oQKU79_1@XmkaWc5W=u2)F=A>!=T1)Y&{RQ6%&_M+%JSZpQP1mun@=WSAoKuV5ql+We}21t982 z{ttP2t`&c)M%|}Izv`s9%;m&}{hdZ(>rvJi^X{B*j+|);;kC}j^b6E1GJX6NPIcD9 z_;@uLcP4erkLbYFns-UJg#}GsJ+f>e2xvC4)&x$M!+l4`Zwc9(WF7QjpwM4%6BK4w z3Q$xcYKu2Wy-3SU`ebK^T?bU|L_|vu)UA`Rx0);Z;M57pHIt^9!W*^NMfV}XuXN=< zmB)JO^oBg0Qov&}P9!D6`F{QN)q)l(-(1&cp%_CpPRMVCNTs(e8uB&Aqgc=@L z`*eJlrt^m!RDu7ja1{M6msbSu!_)Ucdq&+>Y~Vfbb?!z*f?bu*2l7;(XOw4W4bm=n$NrjOOwLZ`v<9Wviw5dHbL%jx2AZx>B`(W@XH*EuQ~Niyz{ zB2tOVqHN`qx^F1|-v7A)W01mLuLmYTAn)>Om3iawB>prKv{t<^!|dDM+ZG2~G8odo zXr!a>zoN`UdpdH>27*@4eHx3hych=4vUr%fG1cLM(chFQe4%HP$#)aW#9qQ-hT-#a z>Yl=~B4KY7yc6@UMli+LsSgwC2fckMf+Je( zOt8+x$)P?iuXmmGd+SQwZ`VS3wb_&JHos5-%I0OPb{)#kH4|X}R2&oAa+&UuBU*ye zFooap$%@>*Jpg@tJ74*0{*M3s-f%PT_fXq%@fwPHpuIMwS1}*cm*dL8-N$iy7K=+z zs?uvnlihvARN5yYZ{lyE7RNDw&V14$wVrp1vbBO_A4`f8(kf+u%_|OU%sM`Jy+1KE z4p36GSiWJu_xI8w?bucox? zixvYftWiYZ+`}O+8HD=d#JgGTza(efu3d+snBLxE6Vcl*veoC%Uh#>>3)3grE<+;w{&wFx3FoZla6KRcXF zVenS$TO?pZgW~NE$!L8oDYsmr2z>dbzbMjiI9$1D&j2|DD=aV%E3ItQG5r+A^C|H*rLc~VbfOgZwNRA4>IAb(5` zN$(7V#ii0woEvwor<1n!K91S6?Y!fZQ4u~iXr<~KIXa)GBuG|~QWsby^u{D|pV*&? zL?p)5ZGO;l{W@)QFJypP>&~*k=hXU%>`DIsrR}Z0C&d#My^&&nwG#EUnJ^4h#}-;; zPw|IQwoySLA>%QQHNRxAk39UX%$QtilXh5br-Yhc{`#LS zQ6c}SF=%3Iklzh@QJYnx!SDDG@n|y|21Je=U92Ol_SGVB!|-IPtgx)n`rxt zRaXXc{Wxn+<)80i`tH#3P=>G)b3Y*vYhpXrVirFhiBf?>JYh7`nQ)@ZvV5m zz^uy!mC)@byRHdS>0YNZeDx&;z-a#Fb>aXViS}lr)f`T}XG%;yq6uw!M37&RZu8KY z!S&-DKbuC#IrgNs7bf^nW#|-%6p_oGoLzNT;Dqyx)89U~axZ7?uR1Ed3D}FQ_;NI) zs`m9rb749tXd(3YAOD#}QrKFB4E;<*afOq03NV&Hmgy?!8hKm^eNI8ZPu&){cC;LW z@!J}4*Ozk(2}+6dUrQ&OfE+ZdHHf$so{FA};c?+bHt@8BiZEATxqkNm#p0wpDC?w@ z8m9D0P;QC-n0>5>#?|M&pvt%RzcEhe#KSBs!z_W3PcxwVa_8Xis$P@ywXr`vx>`mn zsjrZrHSNieiQ>ws#D}Q+{%4=MN$~xU;UZ6`EVqj&T*aQUTbgstS^w+vqd4vR3?ny0JAq&L|o zze??da%ww1-1ASL5^W7NdpkRRGAWouV~xtXik;b6TdgVv{f;aQ$$n)1OKKMS*ZkyH zm^Hh5Xe>m&SCVf=(ge4SWouF${WJkXx9u8yM{}9lVd*~)y{Axix8#H`Lh7fiveuvL zx80S?nQ{jurj_5m{{ZLmz?HNI?Bc6gLFu=>a4OCmXnuY1rD!Q*S_+TD3a(_|ii-TP zRfK;r2gkz|bA$1or-=Pnst5o;t!Or=J5rt<@l>i}QbaYV;!j^3iB#`O(5!XqEmBQq zP&!;TR#V+uOwhE!=ZsY#DuA^m`!yRO_>R~T3(u^fn~Due*gRlz5yfy7w;c-*MLt!? zTQtf|TFnZ_XQxXU8-DWlklWZG7~0b5H7nbl{RL#~9^;q%Ymx{-%QWsd`VfKMv!D5= z6>c9+!5QwXp`FMiAFVot?LZW6PreoNS8KrEVaOH7*B3 z$9{}DWdj`g?&Wb4$y-NH`NW-XU70+a=U+E@7t5CR#Tr=er1kGEocs=XdW8}mv;gz* z8)UseZ}+Js@x}BSb(W*7+Ie?Zm&`g;dY!`BYcr!qCHz3`Jc%J@4E63w+PNU(%_%|x zfKJt@Ki4F|7yaiaT7@m&VL^dZhy;2^bMbtS$oS%_NWU5eH5H|Qr_qY5$fi`NG*P&( zemieWRdT--2^#=Fr&^Epu~tc?`LkHjU`stZ@I!C*xCqpWmahHx`Si$`0?0mx@}{Jo zb+L<8)fH0a)tL~3vdW{VW(Q(7u2C^dNe`X}o275B`Eke8$^l3yWM@4|4_$|Vr3Fqg z0ckSxE~_t6D<0Sj}f`` zQ4yV9p+XbL8V&ybnIo}f!?QHdG%N2f`9A*uPt@(bE2WO@+%wdKWhZJ>9lGG=Q2Am9 z;}lOR0;;4Qf|Tp>%%H@pP$Pihfv0i$@j~TPalkkfB%UMRzqTs1StbS6gpI{$EARAT zt%YYhl{?n7@7P!M;;Qh*Bq2c!P5SiuJUy{iQRKw@q&{Po=l*g+=U=zcqEvfG^aYRA zo1o@73rMYu}Q(jlA*s6aI0-SiX=mp_+Bo%JHx6>L46Y z@jnsey*X6ZB`fa%c!&>;Ea!%0z0|Z@Ar-4J{V$*y8T};(h?d>ts~UDKRvX79MGjaT zR^^V)TS#>MMt@sIo8Z&+7N{^Dq6?0tR33!?0Cs#(;Zz)A>q@yAcB5FYpkQN=d?fMc zNBLgEVmB2B6jSIA$^QTJL;pkA$I0hKSIq zKCEmw(=XG+OPIEdqFw-)&GCngxgd9}yHjD_+qO#G&{v9MCghu{?Oesw!lF5I{SHo&RweJIbN>K2Womqf`FLdVf0?dsMyaf6 zwlmpXMHoi)WC3I`$1{lvQoLD6C*tZeA5J}CxCHLm;R+Og`V7ey<^3Fe6NU*{F3yZJlh{{YH4bvuc5O&eXm zzQ45!f*+~N{m%y{i!cSqQ_+t7u=s$+za3UEF`1PzAI%Rx{$6Qclh>bLPf}HsB+GUvdib%CX+dHQD-$iR9+ONf1a2FT_s7fy%V5 z=M8tDozn{+$~3r)TwLnf1-~kh9G9^Ip!MbO)O!w?(*rbYpOX;EYaX+pH8_H8uoPR63~l>4-c0P)&!|pYxov#V_W= zEwU(ubS))gT2Lx1Bn1j7L9p0m+L2PA;b^{(i{zle*qD?mv8@xJJvOdX9JY$As_@LJ z(MXLOuJj=F1%2?PA8U2>rH@6{+(_~$hSus{lPxGMuD{Es(Mo>T*<;Y)R7%_%Z%ank z-J*^nA+o-fp{>{*t*(!FtF&?*)9kmy(N&e7K$d$es2%MdLf4ic4rwQO?fVHSyCB+C zAI(F7Q7>&hq>$?RJkiYZL`)OVwY}B9?L#Q*$LI0H-Uk(4EiAS4^>q7)ZDfhn+S=;v zE$%HRUBO0TyoYp=HeuI#jFP8S^BJigW&^~HQ%_QT{w!4w>v@v2{{R#aM}N}#c&E|R z0=6H_`~LvW(OtXhdVlc*Vz#iinL!QyC?Kh*BU975{OB;+^GCsZ=GbW^zno>akxwKs zYZ`oJy~uPbSKoc{;-qkjs%Kh9mVYxZBhoc}FU_|RpD^CdrdZ7ew`m*AI#bjVG+$F#%6&^ z8FACfEpXLFPdxIUlYcOL`KjCabIX2Xh}~RJm(<8Ty5OQaCq2d$@^sk2bOivN2 zZ=Co!rXFkjvHZ&NpO|6t3;BZEQq}IwxUzjd{{T*w3%{&vh8AU3Vd8l0Lz6hAbxa0f zMqSDFkNFe%sjPXAR`Mm+nQS!av=jd2wJW_w!8H3`fqBj8)~v^hjysz67zPv6F*=B< z`8V<(^FPj)T7|Zi=G`I-eKu2WZ|*f+G+NwFf4hp^l?is2_ICN?zb`I{mZC99G@r_! z%$-+4)V%9+=G`Yv(=@xMu$$}pg@kfTa;wYHf{_(xJt$ajkLAb=PO3Llg3-S#e>Jt= zF5h|n-(0h{(kxk!E$#l56!%6kSp}-`D96+eAF^0Q6AQ|=27`NwMupUaCcI%;~o)wZ{Bqg-k;`Iu`~M$!wY*!otjW$BJf zDEI>_bu}k8qe~MTC!?+W(c`M>`PW(U6#94Nrn;cMj zBa)cv2yiy!+|7A(6wEx3u1-`knNEo0^j&wzI(5h8q+WmWjXV|J0MsThIxrXTZ={{WUZ9zcUj)_)}Y$v&&)*`to$ z>r?$Rre7?#jDgu&KS&F1BD_$kbJoB=cXk7oqGGem)q#fdvh{&9BuQ-jI6WBIGj7xvnP z-m9sx(;>UCMb*+9a0R;nhv1;47vkk#9NB4O9u4>0^K}}#GT1(3^2W2~3(v{_0L&#I zCH=OqrAuizmdBJaJFpPFQ-dOQ4e@fR%zgpDOOcS)ScH^b>+$|TOKl91L#o5)0A;*Z zu|BH3w&B*Ene@T+;o*+*B$9UKKv?7_iwcUC8-4jWz?L(W z2c&2|PS?ECr)vIL^30NtI;N(QTR)goO!^HmA)-D(UZRAr160e;Mmqzuc&6CKNi zn;?}$SRGGyx%s)~A2I7Q-|CuonMsV#e>~Tgr~<54CPV6QQL>QL6b6*rFl8pSCS8;Z%XacEQG19 zP_{=8m~8|RNo`+QxwG+A)``Hte;-vg!57%HoA8*(I?@6v*ppl$M zADJ$ry0ntUVWZvoas;=!x`5V8sb@bBS$@;TMLT9jT}UG0;^NX6nmoPypB#DH^Ha?_ zrQWH0>!c%U+JxGqoGeO)o@EKa954$QRRL+R`JBR(xc76hz+)UC73D9@ePhZoX`0@i z_EPKmed*NVu)ENUT8p1ep&#jDatf?$SRNqq$i$FsIUptoEE~-lozI;0Tkkb%k;VE; zP`H}zaRSmmR#z@~1G@YdV}meb_IWKj#_$06u)cWw38LSoxaQO%dJ7 zhg6dUyEC&N{!8^j$W}%*W+@U?tRz zBTDNcfLdL+@+OC2Md&g*U8nCxs#PD0(0}J0{{S=m#iRL-%gPIXs+|(^%P?NOrk8yk ziv4CFs%DmFmI1*)fA?UkGSm@~h!$H&u=QKU);#g9{%GDb?!!m&Tx|l~>XGVi3S1ZX zMA6M~wQ77|Nw@NfjLp)Tk@pu9KGZzlo*qT=*POihq|4;*%d6W4O)`_+M|J62$|RWb zZ%v73l?4E;7L})b*NE}*b_QZQmStn1{&s10cHUhtro(4%B!U*WXz3eDeliIM?H;rS zxDJ|f=#i+0H>2tQ0Fs}d8tlKLt~HH1IAp51wGhg|X}ROYcJ0?7J1F%F{G}1q@4DWf z`RVyVp=57jjdN*y(2)Mbiw^i>tTU_jzZfG89aNGCHRqc9g-za8!% z)xu_l+w<2=n@q5^jvvtRPsX&lo@sf>UWB6Tqrpc{9H0jJDp&U>P;k;DaKjm*MG)eP z<3MYM%h33)7O8RuvxO;@o4532cm$G35N9^N*J-{HLw!8V-um zy``P~)wE_;S7Nb9%DkC&CV*E76x$hF)jYb@(=8&X5eUHHS`)WlY_dF>Wz8QsN>l<6 z5xLutrt}|yp4b%!Dq9aR`Fg|6$A*O3wSrzWGc~am{{UH0F%%7ZAv&*7Ob$LD8M3N%NWi7y;OojWu_d18oIgk5gtQDd1H-@Hyqq4 zKXJU|!WYT=kqglzTL8wS&Z>76?S05;X8^G%A4s^@KSKUzYPzMt)-?~TLvadBNp+DN0;Z^T{{SmvnQ*BN zAX+Mky~EP)Y=1K?5cxOrFY^lZHSKO&m~@*9T|Ux5Ev!gOPch+G)PQP6!{0VHV{+np zPtrL)3H;KrI$x6ft)>YikQcp4S;o%F?NQ-C-3DRjjYHz)Y4;?T&THvPfZYUo&@R+8 z8+FZXIebJXnthCEZR=XX7HKCjmmg>-q1c-7uZY7;fhFzF<}WqO6loXJ#t;uyiwIv~ z@h4v#SeAD-spcqjf73ct(Vat|AutGKj)H^*;l!Vi>5CVSY9E?kn0j`#Y3A#HFx^>e zS}H%(ukC=enH0Ap6=Dg@5&>YqsT&=QFc|SSMA3g={{ZukADFivoFA6HRQ%G^Vm9}> z-j8W@aS&>#mC$;GPys^KBVo2s8_U`-q1dajS7NXK();;}yA^!r{{T5)yuT~;!%Fdv zGxs>kbMhYW-Gl0WR4D!25Yxl1+gHDaS0>`bzcfGR3~c`ZFmSkGUN>pM{7R ze=!zb5*UBZ4|%ej{{Y2WJ0G-Zr(JDL>t2734-^&fknw-cBYC#UStXCndNk5g({k2# zDkuij_`EP2(PS{KkN$B>&X%Q|d5c8_cVO0+RU^inw;zTN8Z5>n&L8>54?DGF9&FKL zQh7TrpFIHkHK#fs3{GgN#{CBW0Gu!UoVxt9zP;2u)vLv-+}xy=C+ha*DE&GHCy8d= zjXTq748_%F1~eP7;x%KM@67vT)Abv7uq=jY_%Q5?3owWS*KNnkY`3xv$h3B*(SBur z&Tk`H&0{RIGX|PQB-ek1cO8Hur_VOWo28E@=5Hc_)hfzC6zNmclm2}&=1H82RSz=c zvaLKl>+Ru-5{+vOz zn01XyP_~Vg(mR`nc!MaQZY1%j@uhMQ#~7O&(;{Wf*B5uq7<-wTrAhll5IO_>GS(a+ zhF^&#W=VN92q2PJ8h4?sG3L%71}Sx=L|@fpRyEjycKMuCmUp0DN+wH*N~8%#W^aTN zzBnm~G{t`~HC-}$kE~tDX#g@PUa~XO;T`BHzD!UJQaop656bT}-Rhob(B@Y}Hd>9W zupy%r<0vJmw%$I~IhCWItT_6dbrbG=C;tFBM{4i+-{+(@<|*G&ibE5%565jASANI0 zwpXe8&%GL7PB8kr@~iTv^C$9aNz?Vu%fC2_e?DvaT$<*Y<>Lf*8gmBF>T9-T%fF-Zx%c>_esX+{RU zfE_afENHoUX>p75eyI67&sQF3v#{4bu*<5wowcRZTnOaW@T6%d08n#9USLz>1ozBg zvzaV!a`IN6b$xpTqg_BA;cm8Q&J_?$}_hwe}O z<2BOU{#x5wvJ|)$MME(J@kv}M0fxjH{W&KZPh&c)ms$+AcMCPd_VK(?B07TPf(1^) z;qS2DBqMEdH272UKIvxv0Gx=`*)6`Q%gceY08xz*m-WRQeVjL%qQ}%{H+ww zXKyP}kJgq*+4v#i&LQRM7}WJ(C^Er{RmIV-#*NbglgqlS8f<=Mn!?~{@=k41^u|Oj zFkVJ5{R>liWqxe9ha~UJf0o{D@{W(C`NPdRJ>7u+^`Z5`FO)#gi>+3eYyLmrDv5G&5t}U%)T6opkLtXGv9)F_h^J!P> z6`I2Kta%t*2T2qi)YhbJwR+=AZ>j$P=Mpthsd?JS-ZibPmiqOY+sWx9X&hYH7zU+x z9Y=h#PHJJr)qN%5zn#?7KQsK}J&=>?l53Z2o~n9m>JH3M?iA9a#1L}bN7Py1`a=Qc zUa4-}RBa@KZNHRz`{gajv{0%NoK#c*O(;H(*NUQ}j-!91pX|j`7~=>)Pl{twIc}=I z%+%-yZyZ$y0M1dp zj-zX&TzNaqP|0~5(`d8#lHXO3H>p*&3h7V_Py{js_;#jZ$As_8;^b0Q2B-f3IS&_} zAk@6|`4#28Z_F*H`c_c^rx+})-P@bAvGZv8(U;?5djM-pu*Na#Y`j6k{I)O(PePDje;~lQjuK0r~&UrUIhCPE8;O_z{z+->mALst1Z0BWR6O4 z_(sQV$RO-TTKiyPMJTmZi|$8{L5daKmABiaN3ik!%vI2@Ag(A)N!#wlS;v?E04_D3 zG1)GuqlNDSs?$enRr3m$6^T73P@I+d)wbkRrdYt%#0b@haQ~~erPaHtqiF}t49*l0kV4{LNT7z$w zf1YIqB@m@*8m!a?jQvQjd{Cy56>pBUUW2n&@WoeNUs`Ff3;kr2TC%Fdiqgu|s8mxx z0IgV_n5rL2^A4Y_Otw~SHMPqh-K6NF)HM4l>cx3@D*;}{xTce}P61k>c#=R>q3hng zzg8%H2mb&#%YFH!Y3FI~{{ZJ6e5t1Sqg-@FWz^t_jAroSLxC3$;W`n{T8tn%7P6w!#8p^i0TOBx^M2)$U>jz9>V z_xsyDHjUNvZ~4hYk68ZqRw5CU&#dQG-QzN!}?~02;ffC#d)z;sEAI6woR>kjpO?yS=ou zpd*g8qBpk2cq`Bj$Eu%!{u&%owbI$GAhNog+-Q>gI&Pvt4Q#;eZ$DO5Q?Ms^&x#yX z?4R?E8uyVrqvu)fKRi;Y6_kmkT+3*0Y@oVhL348o8nVVK)8VfE8Ih+VCd-Ye;v$3S zfBDEC%#X@{GwTd~VgbUFU67_}SFGXH7EXsM4xy!W@GB$R; zjs~C6j8}ba_~i93%76L7{{YIb%s(pW-hG?$$4tMr)S+9bE@JZ*p=6Rm;;PF6tCU*R zL3Rw~OK}33&1(C9773huB$3XAyNGB^{;5+Z)xYNkzbdQ}NgwiuPV@i=lKHPxMlL?W ztc;$ThUiPsZ}x{=r~ME>Z^18r3up3Y^zHc(`AGIK{(51K) z*X|i^Y5I#^82UkDURSdHD3Z&2DuiGMFeo`wb?8YnJ7sY!$|nB+Mjl>QyVK_eD)8A9 zni_AoJA+P{C1W$*T+Ky!OUPKL3_$?+fz$5AT`kS^kV#>49Gk|jk%AmB_<;x8`r~P~ zcWwE1ZuU{!-QU(z8Zm^S1am(KpzB|sY&MH|*1M(8q24~9X#SM2I+cA%O*0 zAG-x9-SiHxH=Tbu>|66cRhB(g`$N%fze!HOM>ASOF}H?7ssNFP`?2;t>6Qq~F6|c_ zTXJL`UjG1`ar3vDHFeRo2GjJ5Q>8(!T+xetR1A&9AF6FIkvghH7n0gO`3Y15koqwa(OAq2^@HkN!(!=Nm*wQ z=hfmYp1g8FJV`7^lya#&k(3&2d+*SXn97^NXK8$s#=17UD0P*68(X=k%P()MT$B4$ z+Br|!`z^f=MVB|V`CsxY&f4aS7O*YjZ!EzD+pezDa~fjVty+(f$tVQ)_j5h%AyiZiQC*Wv-_`hp< zWo86!$~j_9JhojISh!K^`AbQ0K~Gmukgy&f6I5c()DM?#&eHieLoNPY`~LvVSZ!=O z{55#MljO||9>m^AN8TEk+PD4_)c_y!rs%H;F^}QM z*BeEzPbptgtK_{L4$`>9`^E3H^($`YAyts|a z@u`YQM0Q7w`&Kg_jpYpOUbsZc0MGums@{@UH zYdfz|#dZ;&P{-+mN=aJOa^f;`$_#0uSWgz+OXaV~cqa0Xo;(9SZ)-(&fS6T7|cJ^A8`&zb%rQOE` zy{+}T#?stT)DBEVM-oZg_c^ySj7L*`Zlqv7Z;br8`2po^JI~f$Uh|#DlBV+GM%VLe zc6VBYmQ%MshR${PS{Ib=cPgvXax(x!gx~i5ueHyXLSsVj&F_|9m=SqH^Cf)U`IDsR zI;!b&Qyho_!KC$+v9q%VM^viGR88p<4PpLqkF4)?&r%tnb*F1 z{I=5Ww4FCd^FE`c>Zz>iR@ZUc-OFtNSt6CAJfi^r0C(_EwMoI2VO{yjaUD^|UTkU?ep5tmvk4t#oKF=OHP{mq$j z%O`sx{GHbIShP)JLi6so)H;rZFzk6vdvy|+cGFt6A%jUE5y^`8FX@2 zHk^_5SO)qOPn7)AqwC+4k$D4Nw(_Q(r0FnfBm6OWre8^WJIKz~&jjI#E?A1VBd^7< z##tgGUxDyN5i5RvCy}O-FwgmIZ5X9~Ek;_8Z?bb#2Ya?M1F3zjqDT46zn4+nSpHpT z7oJeI&~G$Gw3k;$np+8_4APr(AdtxueU}P2f%Z1dfXN~%x_SPp`(1dBJ}a|#`0Da4 zT0M4e$$cZpQ+`m}N1+XB=I+~3lTm(iTML^hQN3Ib2ScZy z9exSLQ@e5Bq&xF`PrCB#ZcZ_*Aw=3ZkO4rdteL&@YzlkmUg(kp+=d;b6k@GlVW zQ-360FT$UffOvnV$baTuHoJGHx_bGmL0cHK&nn&84Kn4gEK)5-MO$lzpfbcgJ(z$i zzWE_0xkMCxo92%^=z2!0{s-k6QjX2xJYVWK(1KiXXQo^Q*DU`4NNI8r^^0L4iO=~_$OCY3*zq9r zWg`G8MYD^YfAaoe!q3ZEln09f-=-E$q!n-Xm<_iCWW_b`&%At*cAjATymnCDS=9ua z0MY9z2|hJzeX?N$NOd13MR9%Py+8NY-c!~DUME{tr@7+>-!rybeocHbJx9sCGxH}* z({3){^1ZBj2A&`+iFIintu^d|gVMN`K)g`z$AYL{yPfhj$U|;-_AtrqMD~*1#SCzV zMq(oeh%7f0>+ONkh_$?qYs$Xj&wH6YCd}4&iNO74`(0SGEFHpQs=6k0Lcb&AoJ5?XI=^=G`%ze-x&>eo#3 z!7O(XqjBOw@MUB0k=LaLXU9`HM|U1LL{87kANj`1tIsa}U}}1fk95{|5&3gcc-Dma zp=ng1sGuJauhExiqs2D8chT_=PyCzwwAMVstZAQ^9#x0R*IFiA79crLLWK)Nsm$F5Q8{(w;cBBmd({5`=MQub%DX?v-|-dYmaAd;g{aGY z%Tm+trG|Tjg5}m9+w_%DC^!@&YSyi`1ZH4%bL9|rDeaG%yv?Ip`4>^pHBC-^L(Mn3 zjg0c#!#1w5i(yo8Xtb&dR#_@NC99f^vnLj)nFu4f}_?y3Rmp)Ic)VH^0th6adeM@-^+T}<*uzC=Bzq~ zxqqwqLM?g|E~|DTw7B}Yo6?RV;T=JtS7m4AP)8HCAk@s7y_@5TAo6}kzKP{y0$y8d zT8^6oD1SxmCY(eFuM;9L3|xyEapy8Octy~dXPU?QQrtbb*)31D$=J4rdss3Jh%G&1YPf9kG z^)xRdcC6G=es~Ol>d%|ZJnR1eIOXRbCu*PJoordd<{4o6)9K$|j!URv+|qtO3bw~$ z-raJUif0#vi(OMmm11#mZB|vNEUUjyh;5MM+08l8BPI!bL&$oBR<*DB^{z;AVJ>f= zG*@G$!PTh>ld$+yZTRL!FyhOaa8Zd@hzhsFMSlVOa$Jy~Xqp<#66QGImgKaIizs#h z5|!iz!*fLkt_4C)>tQ^s&i3*pRJ00Oqvu|qF_Hl`#dY}NzPFNK(ny|>jh1FR@3>xG zKd%x6C@OY;^Ng2s=<)fk+s(dK({3(L`Zk$1u)kby@>_r*B>w;*jdG6;#fKne=z#L~ z=JONeA-oi6R> zS(ZR|S62Xn4_f8%lU$DPNBqBCNAmvwU$FC)zKwAt_Dv@kipvi%A`~F9gRuvuN+*Qd zPC>>gGQ8IHo2VhNxbl^?!a}74uRY9CIOI>ou@x2VgCOEI$^wS$@5DS&y0Rf(+w#=uCE!t^9m(ZTvUWF$6ZA7g*caV$^fUoPEg_o79+(k-r4 z;w1`EJ@-EqNX)%=(+_ivqCZo_u75QA`(tJ6Mdn>d7~%m5bu{Pz+*jLt!W^8seUbkF zIYpt|k1A;Qw|6i~kl#ZY5Q4Jvo)z7VDb}_5=4NyIi}yPHC3u7~kI0WK+DYWQadNEB z^@+J~a-y{x(0J20twz33$Uu5*dSFGofBthnM$>d{3q^S$GD9r#mIhL+S!wZe?M&MC zZlL7HB74J!n;!(Ib$(<|<~=~%t^Ky4c$X0?MHGhSLg^W=z^__`p*vQYuo6CPVjy&V z0q0pFlk&sJ%Nr8P*QJ35p}Dt@PbnS-I!)czC`Jd)e3Z?T%0SEmd zRM4KnfOWu1cmvTbZY{jmZ*bmVu(q0LD%{5?tH^GC16+ZU)jv&tApZd8;9hV1vGSIS z`CFs;Yfre+bQ@&0hDN%R){-UY8lr=(YBL;?8^na4PHDgM^=n9+Cz*Vedv1yS;kUVp zS|4ih#7x>uL+fwKuldeD%MZ=FDfJx+?t50TF%3c+#8{-XGMX=_rK(2XX#*`cu1wCk zqlNYKOkH`@FgvMUgdUkDDwwPP)BE{~yA^!z{{T5x{{WJ|UZ?xzf8t{(&&Yejb{=oa zn=*YHa197u>*4%z66V@o@8x|^tZ8hXn~2;7cV0rBd~+WlZN_PtO?0B-cvWi@QLLP+ zMPl^$f7Jsj;cO)#XqkkO*_I0RjD)CAgizPpzrG$2p^AN6mPoEeBX$8uQrpXn& z*D4T76eU@Kqee(19;8!z#>#BdnTufakIzeXx72NJp(L_S9F!f3RcTS}-`g|$AXJO3 z?L+B)OMlL7JKnNt6MoxC)b3c2%sz_O>CMFUE|M?JQ2}5ZalYM0`ID9gMUaH&AEy5R zYlz&AiP(MkP=>c#gf}rl#yHhhN{1@71OxQb@9BW@L4L`9&N4t_@+Xs-g#o>3E8S}C zPxiB-)BOYB==B`S@<0A^8YhqQPtFM?0bOeFw}2j@@XmiP)P3&v2hcswBq!669Ez`j z?lKI5Yhf6s5JWH%^r6AoUze7qohORcs2c6(?j%id6w>bF&)U1o+QWc%2`h?b@)fa zwrtL#g*XEY?2unD{$gF|9%9ra)O?+yK7pc`pi`y`=`KK-Yt6*Y0|3U9PJ*3x%p!P; zla2->blm*vf`f01-ws!ghDIy&nSB$tu|5tVi^Zo~JZ(<6__^dlJ#7GhTO{{SU< zFIfD^TbcCbhSyK9wvzVl@>4mED54c&LbI`;@D=PUkTRsCepJzC^M1Q;>GAXjh?jyy?ZlX(wUTMK_NSR|JkMe9tKcS>Ch?FBty9A(KOFv>|g zZ%Wr}M6F~gT75a!PPV(WvD9L)mQD>N)g)PEKoy!ZK-^UIS`aHr*CraLyWhVn{{Sic z!o$ouo~*haou_$bIOf!@HJdN5Np8}zDj0Hq**pkhIdGl!`a2C_H78X5f?*8=B_R6bKyLT$+GM z4+sAMoT>b}^N*A~?5EDU-QK%(sp$~k*-xx6{UZ&g;UKt-9xCy$BjDM-*IMScR4BPx zX^PqQ27%_kFr7C~^CqKWvc9EhYj-rUsg>%{sA4#p2itW!*EMn^7iU2AWSVd1Pv$R@ z@8a_(m0;8L8z4=xTWV3G(b}9n5nEcxUYZr$~k-b#Dk)pVZprcoko` z03rO#=bOJG*=c@V^MhDVsGFH(is`M=0|AhZCZD`Kx1x^{apI=F7u4tTb64_`SXeXy zJ7W?f0ykm*0F#R)_x$8-=B*@l?$h~78RuxF zNfjNfPwj$vI_w*MRqLA_A+UcP&K|IE$Kw2(Sqjf}89gqp0S91zc-e_AWy&0o=Wn~e zOd&2s1dc|V^*<~Ul?w*LV0j}}*UQTdZWu(k6vw?A5qp_1vO z1)v2Aro(M=`V`t_#ipQ>&#FxXVOdS8 zpWG~9oxlUft{qI`VL$r~m>y94!1Jb&plG&`=srU7rFC2RHEYzkd%109 zl2&-#>9mCY?lk*E*D^d&DR0Td@a2v^_o?4`>p}DH=4OZawdKpp2rPW(WqD(&TT6Kw zT-iD+BC|+nBX&wqbm^Cjpb$e532>N{7w1RhPv!pr<~En8{%h$TX}FHx%9=A;K@^tg z_Saug976qfm&Yrx;>3?+u4}bfc;x5lp}-%JSDtE;E190s(hGI|Rvdt+ttfW;@_^h> zFXugTP-yM%wHuGC3NNJ;o|U*~_VU>eb(;BNv(IqQ+U;)JP<2Rz>!h1uXbbD4+GZ~LoqV1rx+&PjakmkI}Yc;2Vvh8MNH=0 zh$0GaTmx325h?C|f3h)Dm9A|edzD}z_$z_DZdP4AI10U%pTduo0aoe1erz>n91 zj3mBM?QGWB+2$JyEMHuIb=|tAkNo4=)2?i_U(Js=X_}ALp)Y$Lt*1+EGgJnY zLv0e=fG9}clI`(z%yA-rggHD#H}bcZ{{S!U{K0cSoapleD-fa@7w!2W?pASUI*Nc`Xe+rGhjFMu&$sqXGsK}Dd>0VQflTBxt zXpK8GWSV?50FXQh!Wc=AY!4w;+)%Fj;=!_55)Rch8~BV>%%R(qYe1XS(2{9RovVtY zY&AQ}0LiD_O>874s~eODwP-LHf|l-YCAgGo7ZONhs1eB0yE1XBk* zVbv(nHlujsixd8k`}l+N!Xg&ZdwZ*$I!2ztd97rn3qZ`QMJu@nz8YIbjdxPIgu{QR z-8@n)9U6HV8C$3-Nd$P;Bf=KfL#p0K7u79p?iSQ?0yUMEGEdsr8VZiSI7C9)UaGM) zY=VI+$J)QI=aNH8?&gi(sjWW#z+$a1QlwI#nvuA!)cNA9W6rilc8>W4Vz&(w0BgsQ zt$s(LK0S8DSdN*dTwhNdT5_|!RsI_MG+=oWI#Qq06?>$N9zx-Fa?As4N4XfQD*Uy! z@~zjJCSS~7J!(Ifx>>hHYyC1QWRl{gf6@N{c0o{S$d(MEm8MscC%Ly6dn@Tb^NQM6 zoG&iC>*xOfJo&dm5W?2C7Q>knFmF`cOrabtK=jcSPj+KLk%^aewt$Vg^9TImHIl_A zl-teMZ6vN`mhWDhPY}dO6^T|ki?u&tsa}Qm$rwy-cKH6(5h~>QPAAi#ww5b6Wgb_# znn3z}!vk?*{HPrpV8E>lY&ip6m}JHEajEa0lRxv0znLGOoV6b(TCJtNj)F*h!>Sjx zhG>r$-L4m-QWA%i5Ge()Qbu-dmygJyqM4 zI&|snl9V`27RXFYSbHzzH=n$@59UHi5HMU-xk?rsU` zknZk~Zjfe3LAtxU8$minx;rEVhM{YQ8W`q&=Xw91_m{obZ|$|NIIrWx6iDRdaB0}) z#0LqA<*2UQE&LcCi}vzMpn2~|S}Ba;3k&?~o(`LA4$=Aoq~-&dk6{^I^rZ&bCC9{B zC?6WRYvQpu=2`0B?Yc!C1mpD~`<-{(%%*%g2vMZ$ni7w)|nB1F_6gwYq5?bOs&i3}dbZ@)> zb|)R&TgDz8kzG^QH7I+QRZR^C&99-@f<3&y`&;kcQ%{oZI4HS_E#>1?p8#c+cwzx2 z#BVDdu&}WIRxXZE(OZm|Wp$+vU#T<19W8;`M-#tBmh!f#OP6NqN7QR&?|y$e+Wd_z z92hVE<{W35ds0c9dR~%y+gx!X@fgj{>H~8|EBbPOfSr0wfaMjn7o{I7OnVSI5rGR> z*Qe3vUfPUl6oGw>3u>JiG;$p7llh-L=g|?OiZXM}`ybMG4!6rYsJ*$Ch7W-frnG+L z4sMhS6GQAee3N$htRX52&C_UEU}5bnsXtKMd< zT#=vx)X~}G1d?9>1BmbNtVRB=4W#<%D5$h-8`;*TC#%SvgS%~lmCSga+$H|BQIm+N zs@FDUR(ofxi2XZ}Z5mt~ZW&^6Y90Wwoy!EBOR~ew_Ri!Lz&r4)bwQEJ7z$JQ_SYF; z)LqgFs-mdJGz{U4(pAaw!{m-T%4foRdPf}|j3Q)4v1h7OJuV;{>t>qM?fwwH)P9|J z{_9t3%SIAlgldlJX}qoTP@A;X*)O_3KZLQKOCPe&AlOZjnhLaL7#=YioNQWkqg z`5Eo$Gg{k{Yv!Z^T!D_}Wn&CL{kHVv>WS+PC@U~F5hv}*>sGZ#f;@?mBs}#p`uOplolP=#bs?J+RU>QW-JY7$(xa))F9ormfl`QnjnzN5K42yPUOyS2xY%l=_e*b>qE?HM3TlO zxum4^x;ZOj-DaE;1)51zxI@QqCT6LY)$->pa(6A3+D%?COdggmU!9}An~t>B{bEbk zY>-&cxlAWObA^vn04F5!XjMb!L__C9gr7nMyxk}P!TKjHlJrz$$$%HUL*O|v1~e5R zcnEY#q$-6aE!o zubX;sT&Z}gf=7g+jzy3aS03wxE`S!4P~+J?nlq6iCt;kg4qi>gvjBY3?%;foeXM;i z$*oP)+|Nhn4b&3Xyfp!EDd3GC#iw)nYBiYT5&RREJp7Tsby(MsXOX!UE0l5lhH}VE z8&9KxiQG!bEs&c{J~DgiIhv*-&Bx(AwE|WY6@ypE55xq31vp(9%vD@@Iy}_^*b&RE zX>6+W3OE<|$%p$up#KK1hd2E+OWSB*l4f1-=cLER>m2eB7rR*Fz6iYZC>Sx`@Jm`v z9=>_-XM85Te;_Gu`;Bp%Qu?yynWbbmurlWxsx+3)g4I#CEV^X!*yT;44ddB>7kE5l zka>{Xd!7|)2T>XTSLfL;+d{bWIK_tC14A0@^cD60E~jnDIL?+yUA!SsogSvb>u>wc z%*{I?jsf>{o+(m>6d%D${c4AgFc3gBWn+n`px(xc%|w_}l`!REN`R^S#e1}ysrJ^E z&coYVrzLCN>|z7Z?_c2G8;IrS-#S>?Kfm*vwJoar+mN&E$tqlfgA!MvrqiHEL!qq99*qQ(~>XO6xhwQr}V<4ETv?Q7Ke-vO?=h%5nn zcQsc1+YutUt>_@P z?K{&qc<iFChb-xBH)sH95-0UdmSQs&!9LaM&v7aH0tZH+P)CwaT+ z&LyT`hse?PktGwz=^rgxH<~+q){@t{#9{C6-0AZISR#kAy{-hh6bw2)JsqS^de z{l29YP(Tu3kYg2R<|JID3p#>8qNOdJ1|r+cclkDk4v$Ij*cr%%a=9Tq!xq$xr@0ZA|_JyB`%7 zGs4luDBQYk7_-!w#j!&1I$`kUZVIIj=R1t5CPQ_pYCsH_%Y z1JBB51E#&;*Ae-ByR5+c`X8)4h6~JBhe`3H6Aa&-0_@DQc}8v8oM`OWXEWitMj@`y z{Haa9bV){U7J)5S6ybr6wY&tEne|V7^^7B!L}kHGk-z{0-Z3f(wWV3oV7XkUpCN(c z&cMQV8dHHUy~&Iket=U8uRzCUTgjdra=+M#7??C>LW1wN=?;2z>-OLVN#6KkTwREK z3nJpsF*1aEE4w9u*q1NIM*-!FhR!7!BW_ky6HJzwvF-r&T$79Pox%z(Dp# zQSC?U^DJhkWSC@Gb#mLCYtJgt1n+7MGOi5C7QzjZeqTq~LCf&yZRWw&v&E34yxnBZ zW>EiQ7PqnELD${&p~KO89BPg9wAG~P>2-&XNC3$~m->PVOV3E%J(&GsQ8q(9jED&ATYzn|X$s12Q;@Hx-@ z2d+*BEqM1cZI8S4M7R@(mVFnOOH$Y;LzD+cQd9BVDT)zIx!k=%E z+Mdd(X+;CR?7OgNGIUMf%d9a@*>~jb$2O@7Yg|{ug|p^gz`NaF-&cGAbTB<>KLh>O zj6#!$8Lgpz-v53F|M#Q?toa>bJJ8QLVqw(Y16ZKmWk@pQd$foTfH$NV>kafQ649?P zE;P!9$nX+}#Dlh2&XcSGb;oxT8w18xj2^Ka(f2c{=^hE76^1q4$``cxtI#3iMP$~To8z6L=K;ogBhB)c@YrN@`geOL&QtcR#jTq&9~Ay zhc{JJXiA&d(H#b~SvGbsewW9MdRei~VTSf+=9cE){8hi>VLqpBsF%6r@M8X?BcfpR zc$|F%Pc6|nx|VdpvJZ6joJ)-*rq(i#z`bH|TnH;@=;cwDO}h>iVu{0~hkM3D-b{zs zdf-0`2^x2-m2-&_Na`C{Y>xW+0gX$GvG62a zuJPoTLq|e=P`29V$O+8b45VA8?0F#6_LZ`EQgx}9XF%1bEA*RERdVGQ zW&!+w2kX>KC<6lLMoZn>xLvezUU@TK4d3yR#Lx%jB8UN->tbQ|`59}j_m0h0fq@lS ztHex^>+x*0A$rxGtAC`~EuUYjMiz`shUji>VhNkW&{6pohREXv|6BRL?&be<)LJ@F z+a}~)L@z%!ppuGe3;Tuq2chg5$FwqIli#y6N=m*ot_w(F&ZcFm z2Y2~y2KbHL$d=X`F-R;DX1-G@R$S_W;5N5Cl8UAbY7AYxk%In`nwV3V3VEy?QoGLltiv@X7FxirlAlTg){cXi_}Cr(I@qgt&ekj){_=VY3h#6f&CCnU)v{OI#y z*dd3rP%5m^Te{vUqSH9IE~HfTgn#TdTA}7S9{dRRB#<3gLo6|Dz05%{eRt2)*?<+R zzt5E+>0-64EL>?8TT^w`ueXm6Z;ZS92Q(hMKC^4O!no`c%60ba-BO_=-alJWrnn?S zq{LBHH{V(Wygg6-M_+0|CU%KRoLF-L`q+H;a_(QxYm0+Ho%Cu4%h{n2T&0&)jZv(w0@%LB9!%X7E9v9bO=Nwxx8L<;#r8Z}> zYm2Ov-{D~%X9O&7QB+W=plQaF>aZHPalDp1>`!NZ*P=4tR0lS`ErZMX1g=9MRaat; z`o!N8k!p~87Bl23|M)YffQlKK>{7`xr>rFv{A7gu5h5gDxOYhFzk(ERUX3|VKsplE zI~kOJoQN~|>C6~)hAeR}^Xi)ONdIn)y}Plo>1{n>oncu(c(^iwX~o#qhFdgfnv#2V zd@ix7!q{UV59qiy5)ma#nM<3TYdwUF(JhJN^&`?X9l#86awV7{Hn)fL=RxBzSQx{} zg)98`6HR+L6kERI^IT5Ug-xTq;bQVc;BhT;v%rVytijIZ8>hsmMylVQ4df3%A$(x5 z>RKdj^<$R;T2)V#__9aah zPm}P)PWD55BFjf{;z!8f1eHISusHj9WWW}Drcm#c*GHxw>rVI_*gtvXjycO7u1}_= z^dexbo*UG<_1=jhbt`93fUNz(0NbBr~)4oF*DA zTThm`TXg6T%>LMBHU61k+nlx z8Oo&3)~xZ3lkw>6(f#c~)WK;*;e=TRiKmj*hW-yaB~~PCjnYsWN%}jDxmV+Jr8U@m z6+lyg`tz$ldB#%uPo$~XrHZ`uDh-Oy-R<@(6hXy$8i>>90ld@2Ne#-1Vt~8X$!aXg zO*WbRd-H@X7ARw1ek?hQ10BK;CA2PsTLD7O4tNZcWmuFb;k2wTwWj4<=-b2>0cq;{ zkeNM5)MHAXPyzoZ_+)6jEehkr?Qhv3MDfqnkA?zvTEZAQr9OD`1t&@w{*{kC6grga z&UzMN1ptr?UZW~3P+0F1!6xhjG+-~|%DpI}*R$fN7@9;<5l9kVm>C`>AI{EG0;>@B zxdaF{K#O$@8cU`xd6T^AN>+j$^~?WpChWT(qAxgwkMzI)1QqTTy4|Yd12jkwQg9VgTC5NBjEU^G!I!St5KO28*7BfC~9EkgArW zmqeLec9Y)Fx{YC?esk}G1}CW!@xWyd(;|*2id_5g1N5N(kSOQZ-0ZsqFHyElRd|vz zb?-@kn(Nh;@YkNFh<50?)U7n_2v%*>E3+>{xR<02dDHA1Y$j6S#e# zWMd1$Mi9@ik*4GOfg;%z5S2Q*)sH_U8QK5zqCZpy-VLcZiiLxmBLsaMKOmu+%Px1k zZ53|IA4%%;g|s^fi>b3)peN{^Z#EyVgX~(ItDvDXWcj;}JyIxRyMaCqRW|29^r6jiP%N?_}gb; ziG6c47fC%+9O->>b3o?*Xjia3&2KR#UpWdnRMi#2o$rmnahlACbf&c>e}bo)kY~w24AoGlZ%ab; zaQ?KG)}>$xV|7e@QW$3N6E?iE+H0WF0$*nZH45e<=zR(`4h9boJ)YaU=FlHft*J8& z(s+<0rp)cEZ2|uaVTu|jByxBb-|{W>ML_72bHog{_cfx3%tzSpXl|4yoH_BdltLu) z{q@JMK_4LdfXbwlqFjIEKg!k~}8_cyzXddp0>c zYZMg#c6YSAyrc-&Pa;{HCoreMjHIcK(#o|Ddo%NfQsoJs`6N?uwVJ2~XM2l)Vv!ZwMY+|uR~E+ED(4hOn^#4uYS_Ll zO}S=0Hmn}L7e$Qe*w%wVzA>Jde`}We%}% zEY1wrdm5gBD=)$x9epuzH=I^&qa3=@>Ez#dZiLBeV>xEd7;WW$&I3ItBAPbBVv|Sn z0%sw%V1=W>^q^V~0HI)Z$C9JU6fbGbTU42_bN#w2$1cK&>5pQQPp!8|z!{%C=-l-z z&Zm>meZ6SKMgBF8PTo^r9_jl?yQAOl5^FK2JCF=q;cV7Jd%XmrfN|KNekoM^$g#co znbi5?b@O4T#sZ1XIK#6I39`~V5NV7rolKt+W*Lw4?R1Gl*YkH9aqeGYLqN&7P*J!O z)N3xpXT=-QQw_1$$XBw=pGv!3c5R%ei)XBGos{Xq9PJLGahH;}{YN+II(WFd51M@c z`^UW>yy@C&e;zvVH)1cJDkw|D!}+oFE#3p+x;sU)wwvw5;#kXfa|J-4yCXb3Xp~-2 z=in`pm*U6&8R0jprFO5Cr@E4D<;|NG@l=Y{Z6Sss`p_-7 zCys7BI9&n4w*gK5vS{wkr55Vrfns)=$a8;*4?+rg-;wdofd5H34xc_Jj(D21p1xVo zT%FJ9)ks!z?&tgmA(%1_@k@X5x2+R9pxQl)P-ZSiRE z)KaHMQbME=$1OYe9F!Y}XYu70Ky90oH$u}oGhxdCy8>eB@ z?CG&J*->aX?7<#TdJf-R^{8iPEtx~!+qol*3(og+Klb!4g z?L=6tdd>J&_6GgxE0rRos2cjE zak3dISFNVZgGk=p@$|p^3c{|oHjl27(dzhZ3?Tuj9p`Z)ZcwL(i*-4akHm^l+z$eD z#ZDD>lOsC#V>S@!Tvc|bvjK@Z9k-W-P>Qrlwc2570>*|0)|*rj!Zq$qeIqua+3iwpqyEmn8 zse^wa_w&^S(?b73otc4G^(BCJ&j+HD2MdkY%+5ZCWRn2;iHRcGK;G+1)gDcrjjkL| zkH3)WR31=8moe7K7Hn|q_x6Tb=jlKBjY@N#0H&8bO*r{=*n5DjL8;XHcSX!E-|C38 z6gM+(-X^cZc$JG+|8%n9IHBWRU&oQ#FiKS_R%;FJg=xyh-G=C$DH*?x6PA^AS}BjH zzob5dJ>%Sr5z{}rsbnB>*TyL$f`FM|$`m-U_*&xtWQH8P;cV}ZqJ|dD}^v#X8*8|Zh zE&T!IFU&O4i7GbwugOm* z*WhMUSHx6~iZ@HKC&&!K$xa4U#YrAhR1PfC#DSK+IC52bd64>GQFL-#02P~WJaH!Q zHr}Wr(P^DgA@pyO6tJFnurq{S10s}-Z-TKWu%Qwf=ps>jZwQK0r#>nBtDnllIOs2& z<~RL0SK%wPbqiuJO(tGgL1nkl)N}=k`N-V4S`}Zt>8_k{{U8msX{2E2M_-<$Qd5)@ z`{jK~gUS%>36@YkbdQd;$PwM|=w-Kqpk-q$9ZRo>YmK6bTODr@m=T%1KP^ zRWJefy`2c^t-0{?s#hm2x$aK58(Z#qQL*5FKI$z6B|i(kXvCYWT=Jhb$(J#+QjUaK z#N_dW)%Y@(>o72A+E{Tut3ijMjz=2MadGFVJgQ%{&WDp^W`isE|IXNLJ-*S`2bg%>R!%1+n0!%!mNuM9rums0 z!g^s95QVk2t#o&X+p`X`;Mox_aE#WgMLlf*cKgxK8f()6fi!aBf=$I~zxp9d?)2;9 z4v1a<(H_rE8bjO*jNYNiO7eruV&*mv&H9$WbI~SgB5sInFPeR9V)7v{eb`>2^x61u z8g8@P;I{uO?`&;XgKeXMYog-W@=uoW@*o@VuD{jGGZxxzd(m}pJ`3GP#Hy7??zCqJ zL1Xq{euweMreDteIqTty{`1_%7}g*PZdEbnR{^64S9xFoGJS_aoG0a$$M|=br?Xf7 zN2;pi;QNgLVmvXf1d*u3&b@K&ucHF4A;U871$5|giR(w+aUT8@4VILbolwZL#%8cm zOdrd}yGo<$S;1Yg)YMpv+E_CC_AC3{Cut40Vg(odj11M0Tvo)}U=QEkj5^jLBWd@d zND9i<4I3&X;leOY>9AW+ZDNU7SvD_SaVY#^3vAq>_>?8N3C&S+Y z!tim!JMvhU&kSC?@n)PCgxOl*9o2l{8+}p=>?7CgCxc@yr_%N+uH{7@`7r7ZT~~U-D&OQ&Rcka ze|C9%ZSbds?X_?U7WuYB%2MY%pfFOS%Yj&ZDSfq;QU51~`2Wx4vB+m<<~byD@{Iec zR}cu}7)I?G4gE&8pn!eifY&-&JeZ`FW2FhShsnze`ol`k7YUGiSlx9-8ff#q$^KG( zXU|G56xi*f^7q~~aAv@KwTU@Cy1vGl3tX=q*4_BwaDza@MO7h9wlBsyU@+V54kNT- zN69_dnJq&lUNp0()7PS{VYsvkriK%xDnRAb<5uq&>`amco2DiHifrpYR<)X}SRt-z zF}0)l)U*LMcL|*7@!3sgH*#XKFt0}Z<``Tn)k%8_9uW9 z0@uZE3_L2-pTkfxT*BxsPg0!!HUY#99@UFF#K2JBn#wCh40R(YDfFcXr4XvAVbV%qx_yR)oGvC zh@Wimw1hqFw&7EE<5boOO{y}Mxlp@9Ey#FgbEpt!BdpS^+_5u#YueTi6+tJoOeI)N z*h-(2_R<6;uu0t}v>%8KXF#99mkDx~`f&G9L~dSmtC)1y=#2x+0B?n-?|!EYo|?& zh-uUMa3HxytO&XM4GByVqj51cbo5tylw|UzW`{OI2#T|Ve%Nx=)-@)qd)*+wO5u!* zN4{1>3YLQ-YVVF&BQO)+9nw;{ui;F%Lr0ULW1;*ALm`bhbHAQd0Zw=ArP3@gYr7JS zqP^wIvjR1$CRM4N;R1Tzb;ft4DxDOHL2Bzm1lwc~I$q2Lb)Q@R89K)<-Qe^fqMnjh z)sRiVG3|<;bx*yLmM|&BB0;aY(qzgrnb0~WwtEl7K`ef5C3I>EadAn*fJG|oHR5JQ zVx8`cy??uDlnb8{A(ARFc$U9c&OWP=ZjHe5OPmLD26IWMq!<4~;)l%x zfR}8$*E)T@MptybS#z@h#TIV9divK)4hM-b(spt^^*~7 zU?FIgDH&7SWWMxF;@g0AjRyPM&J;0)yi|)=c6kQxH`u0qXc68pK!xSjss)!u6>Je2 zdNlY6ZaWKgdqiw+HR|cpx^pVc_VubB=UM%*+03@|mTFY@nERWLq9Zq*Gs}=xvWQx>tSq5J8J1Ey1U&ZvNlSAoHwzKeSZbSRR7jv;#)rI%uvRR zk-sHGaL^IAbJ-{GiC!a8TR0h4!mgk1`?l$T6NHbKyKzUoLUYu=Wqaf|VhKF!Ss!Y) zuxLLz9#d-5PYjj!V#Nj%Po!IrDXinCm|HghlsBQqhOu#)6?N4cluwc3Xpwy77%l`= zh;##z>`MaIT^9RW3Mf}`)jnWy-jM)#C;khO|Iz46*eHKY%OT1#Kge8Y8lroaWxp(v zm8l#ud*(OsWb^4GvVq3b&e!jUdP|b0f}dbK-w1ENcZC=_hq^c!t1P$leR;x5M%Eye zR)Lz;D~}!xE=2~u`tnF(2J!V-iY^S&-BY?bsuY!JmB3oQ>mr%41*@WPll zzl791YmNM`6Ang`J9*Fw(Rs>0;$0>celxqF-`)$}sLUnLxnIRQt)nAY2ku7uR$Qgz z7Vko%zY?#+;d~{_Wg=`Ea4*1#R$IbFEDgZ#1!|S&4m0}Z>&mXcJbo5|uu%JJ6(LsS z7(ke=wv6`Nae)R?K_LYO$S2qLnwy)=R;!OS5EG|LZrogm>RPsyad}g7-`wrZr~`Sd zs5X_!$O;EBU0tsw^CSzu!JXUerYMPrtlQf=j=TV#WLc*pR1$?av@5>T%v@|>>o^J= zqRu38H+3%9FQIF?tU5?r{HY>UYSEhmCy$8^lTEQ}=)E5_B8z9T;`G_eP!artp>-m8 z_OtePT{3r_4x?h5`+B81li*`&dhIQzBkja#=Cbd@#>wOKqqm&EgY=L85z?E3R3-?T+gVP?_aep1ZB{kv^CGupFLi1DpDiMSY`Xe?y|G6`fTg%E$=O~a=S*_8$Ff2h z-QSBN1YF^SN4sUzvLQVVF&*5Iqo(E|%_xtRC%p>o79F!>3wnU=>P=$l?SQ1uE^@5e z$l|Qq2*3CiO4{69&I6=L1PCI8iySWcPa7dbd`30AO=B~W{rLk7ORe?45Uy_TCzwu@t2_f2L7YQR8ZbZ2r#Si(wY zI-W#kKU!a3T%RE>A=O&g8W|iwrn$XDRZCRzP-@6|7Pd2U$)3ZeYcJz!V|$+vUnbu) z#aG3H{MG22^DG^uR6sIFZ6VM|Ye*e0?2CHEa+SPvfy&(vxJP0b!jm&%n#OQTm-exw z#OgillV6oYoDW&pSy2B`vH00wmIWkzzz!mjUvftFH(ql^ZniS9cT(i{^sREei~=6Q zEHdc@G>EM{5quS*8ss1OC@Ce$*_R(u1TZ5vSQS8A_bdpJAi$@PZQaC6qSWnygqW=fMX`FU6{HAURaSJeRb3kf2roPcz6LjfQ}vd0faK`_Zhj@Ftv=vJBDU5c~F zO~ix`b@gKPbPibBOkisfOhgMQ#V^xYAS9O|IW(~Ukk*@uXyn$COSkK9*v)+_L^C%d z5fo7$^6R{yvI>R#_R$Fm%B3=ejNP_`Ny3Y_YzoAL=XWoDdvC3s`6g$w+DbZU0%!J? zIh`2M*f$9*>fDzB`9y7H4*%>}elEB<*jPzJ4{BwfgS(qa1Cl{*x%esC%TKUyW>u<7C}Z5{1lvGTv{O;e}d0^Gqb({OKaN7zxLQ?Se2W>P7rdyTXa zm{?2Hhi-~3_vKSJ6m#QX=u3KYk+WzPH{$z?r#YD+Ub4#qSQ>H~>`sDN2Ae&noj8n< znbT7yW;T6BmxDD_ zySqEX!IRbvPBXB2arrIumMRsksL|g+h6l4Od4d-Bn`U1a9O*V$YS0e2waj2%DBHhv z7`oywF$_B!mHb}y{)FS*nvI-K{H;W41Wc}V%NUytgZS}BZL zx@(|-FC<`sk;1NR(CiH=YngRx?zig&Gpi@!!7Ck( zhVg4>dKQ)sDC@V#^|z*aT&J>sb|x~*0T*8Dl8MAMx;}4KhL*VW%CWT- z)s$_OAo-NQ=gaA)7I__SOzvsEa4^<~gRk&I&NjHUnWe&7eSs{j5~_=!vtyM2#H+iCeg zQ}li>h(BCkyCf}yjI6-XwKh=$$!RKHJH$i>MH~7d1NWcD;~tR(<79V?@pdK%jr8~` zbRyt&Dg+kGHr1EUd7b6vc5#f+|Tx=d+oE@_ld_lqu1EZ$r(^F`{D_t+|y zJtFpcgeF&Wcy0o$4U_h9gOnxxCCDhdU4o;K33K0}Ka=EgHIZu+3J7({+xlcVB4c8a z;+nV^p?qW<1YYNJ>7<=Jx>eUYms&g(@dwZV-_%*ULeY**9`~)wW)z?D3xSGaB7G$W zWa3%}avy3!lmWxCMqJJOdujy#oGeWGNquRV_E6pqNtps{0L6nx zsMni~JLOqc+@dW~LlSpQTaqEv(|LW8x+Xh9`khI)E_-F7&(?)V=F%~Q)JY~k&aow` z4Db<+!DBje!%)GX3;CjKhv(H5JKx-Lf6A^Kx~K%Cx0&<@ryXWBo3=?=U2o<}ym0R{ zqjK=Sbp2I;P@iUWihlw}&u{u2t> z;q$K^Vt1a#=9RuKGK8!H=YhwCoUmD_hft1tb+1a8L?gf*)AOWdyB76gp9o()vqBn< z8$u^yJIp}mg5hx#=S65VhcF)(HULs{L+2KQdYwUX-~=*`9?rQ=hQqtrX%*(W^|a#6 zjLtu7zLYEoxNCh=qJoTKeUKM)5Y+!^e!yo9A7-ld#LJZeI^&t}xSdXG$@lR?J(*=opyT=I!MMThg#H&YJ zLTk(AfXQ3{XPwT(=15??7j?sxeyQHuV3BLnEytT2^lxA!KdaFE!Q529p#s<## zU%ao`+6QyKW{Z@}+J{c^PbP;<26NF+{m%`ML*nOA;M&?X_j~hXCg5$&yQ*FTh6v>3 zWzau%x0U9WTc}lZWr!5iX?bQZch_+7{_|mAVEky}NPgJ-R|k>2JG21}3TYaif-bo} z?)lBp1fcWLK4MtMnx@Iu7ja&dD{$>9mV+{!BUfeU#T3qN9kx=6SDV zF}FFiJf5?q!mQ$`igHpPU|vJCuhs6jMSJk+W;w@4QgFxV8^8*Od!DJ;3w<87x}3R@ zLA7tV?w(ElAm=H5f627S4&lJ!x}LMY2z(`|p2=D_pcCR9VlR%QjCnFF`VMOmCK*P* z4h8KsIA-BHWK$ch(JQrWB;XVHkf#xqQMXk^dn{Aq5`KFtM%J8roUGmb<4cxen{r5+ z7eT7CKI_Y7aN!X7ll1{Nl1|TB(4wVlwUb|-SgMf|EUJ)R=B$(7?X7I6^TC!|H8q|D zt~&nSJZtS4mF|B?m^)m}6@MOu9+KVJrrmLo<0q;j^%Jl(G^Hs$Zb^ne@IXj%^JOJG z%~+$pccQGHhYQ}xj(FmM8-;ZOtoWLviulcgl8rjS)_{K(hl|*nnd;`ZR^j&TlIwPoE*NlV+@W)av?|&LR=X`2iy?^#k7EN{RNk5*vh(# z`{AOck}HP~`Fr{UAMCf|1bqdWgjYs?vddC>(|?Rek1jT94@0#2CM}P!{HE8(XW?I? z#AVjj4*q6=F1g(6Dt*p5YN|eFZ{*g2h!>@D;yP1Iv!}yRM+mHCM_wNxlJG=Rn zh{>0t0Y8z(DP!YyAcZkY-jQ;9kB{N``a}Ig;B~HX($~kXp5TL9!h`RQ*=g)j<&lM( zoiufF`a!azKQnKbwE zMh1yeiGN6uDFYS>%>*S+^&(<0-Vj44KQhL z;V(Dl^8wV82Lgi(y1I(C)%d|J_NkNGX`x9Bn^OB5pOU9l=BG`t0ubGxg4mW-0S#ug zD#du`N=0oQfF94Ug?gfm?_bb)--fr7#@t>I`1F2S6B~jOQD@&bewyC>0x^#T<@eG) z6CdiYk~z3mV6se;kiwBlR+f}si-Xz@o5wGmVpGfg24y65PC}V19R5S93T0^Wag?hn zwm&L#Qi?;y`;SI5f4^6`z7ri3fCt0BI+6(% zJP+pBfStBZe;UWQatDh}lO80nsZPXw1M!v3I{Fu3M{?$x>UCgJDxy_+<^8YGQ`Evg@ zCiiXKTU)(oZhT)W(d(=;q1Z?MeIg!M11ztL9lBrg99~!CdN;O%K1rAQSTL~wjyvzx zILLwr1K7x$#hst88hy~^YMeSf709MkCt41^vqA`n3ko&} z^F&k0uF2524SajJLHuqo(WAXW?{Yq?9pi+nscmrKXB6{lOO_Iq;MIt*fVQA5wbUQs zt9%-Xa>Q2p1rba?)(~~rbpS{1^gpEg9Eo$5=l$)b%lScHOQ~CqPW1Kt6(4N*kS3b^ zog^l1;GU2iU*wZAcw5(B$2CcRcR(0bTE`e`LK4KQH-F25F2z);bgngMs`nPD3_cr} zDt%X==l_j;;%?h>?^yMN=||xJ+YIWQQ}C!hKFjBaGch$S-_hLe z(NMJezbGRL=q8h%ab=0Egsy#*>U&A3=)2~jpP=fTh~cuVUXM!SbIrz%ijH4mR%eW2 z;flKYnUA}@2k8oV@8-cj8CN^f)(i}U9-Hvz{_O7BcXfL$TFSmtA_t1!Xd<_MV!SZ+ zgB=KgmX*7*)MuO!Z45w>xIZSAH8ycu<%WM+E*5&y|88r`=>H79#Uo!7I|uE4`~v*JUv?F zrvi_7y`H7Lw~XkF7^xDX07!{?NtY8Tq5u4#2l;je9lsofh{=LS=ZZGHo-gNiFRN^s z_(=6D555grKPZWQZI^NmxU3v)-89_pi_vC55l+n+{|FQ&-YN_j^l0a)pN37v`#5uu zAV!XrTTac*I=5OLMm3E|fc6E0yobT&py#n+<$H_8-t~5eM$SpMM)sk8F*s;ZsK%*+kXKJnw7nH#OVtHzqCW78!6NLGyHYfJflY(!uCz;f3X z@!b;X4sI~W(H`HH<2P-EeC?JM>yCssQgfyO%E&aHPL>G^XkHX1-nm5khMUaWRBY0e zF;#}6w(UEhe4LfCj@GUY{D$_THDR0RLwyg-8I0jGkKN4DZ5vhB3^nojdGjF1b%8*j z#jH5Nga}YyYX>9WlP>G*Z&~75ftikHTQ%dxeU;XJmS+LLFz_p4>u(n(uel?XHSMcC z?4w~ zB@sVUc(-r-FLh2tg_*42w%A~9uu#G_^s_^VE^KgJti2ZMt`CNoo0*cYzB$L+jxY=s zuvI`+=Jk|g|2Z4sag$9r;SE4#1i5kB0YKi0&rVOjP;Vl%~Fgd%}&&NAEv12C@qE->EHiq|_wMQFVIQGAOe1{r^KMUX0Y9*QzLW zTDX7fy*KhzzbH~EB~r8E7d{Kg$UmkGF$>+*-7|px&Sb|oTvn7wT^LgleajhN?A+X( zF0In%ZClkXBpo6T{?oYXU8Afu_Fb~V`?W%Z53`0tKkU7fZ$T~u1dDSG+{Tp ztknvCV|kXPvsOFLdD7*U01Q3P7Dg(p;ZquPmQ-3|Gu`T`1LzR{TTr>V({LHgAeGD>o zddT>zQwBrP>a;XwutN1_-GDK;Y(x`UH=HZ!aPl0@Js2s8nQ4sm7~J5e12)K9WA1H( zsI?{a-jKOIM=^Hpl$VqUOjRfS9kcJflraKuPyNDYgcN2_#8MMQ-fsBc#w>MfVEMT4 ziBJB3vQMXvWa(3VTLKjj->v-J8J^uLYfFV%aGa5;JrBI>nbrtTR!d z1Y&9pVeGeTSz-CoT=D5A1*JY)Y8}+iJf$)(>|Uk%ZTl~R zn^D@`76TtiN3qZUw7LNoKX(8Y+B|2hO7!$OqETNK!bQS`-nwqv+Gx2@l{`$pM<||A zTLu#=mdu>eMuaDkMAN<(#|CB+(p>dkX0;QJ07TXGD8#lL;*d)2>}s~Uc=2&!npk>t zEm$_=@IYG%)VEV;X?(Dwe^FegwibnSkZx$<$LW2E>X^6^ktiF*9}8 zj2ZliFwUyw!VNZdGzTdW8-6$o7bN6wRC>1Lb^RmM%MU{oiwh>f25FKU?xC!G!}c}# zFY(jo8NHpl{!cp-%`y#BP6hri_k=U5Iak9j)@Q95d!ch0P!#a4BFSA0fUr@mb*XwR z$;%9iLIEitse*eUd=HGFpCIv5>jS2X96o{U`{hbio3V|~lrxaY4|*JlazqI!rtbMU zzvF!53C#um*J1ejh=Y!))z za)A3T{{NA5)^Sa}@BgO+K?xC%?(UTC?vfg%lr(}M%|xW7ySq!eL8M`TFmjZ{=-fmY zOy0lq`F;P`pL?9Mvvc3~6|d|0dRd#^$?`rA)jA1lLhn@_5*DQcwZ4>_{!fz)Z=;6B z8*XYE8F6=)RlhZ{ZFZYEGQ2p>aEQi!{=Rmn>qI(dHu{AS3 zoqv1uv)U=)F6B|GscHjV>h-R`=oL4SxfAdC-2>k7Z5d?@&gP?(P;3+6%h!v#708yE z-`DmMMjcx8WFD+&boPSlT6MTnVOEyylxj79SFd&fN4zSgZXNsQDXV7;vSGfDPJwxI z10G8ulcP}xYQrj^{sU;1i8&*qw5o$M1R5!9%?K0HrG)4=xRguh5nOZi6sJJu##->Q~ zl$rcj*v=BRO0j6E)86w@TCM)@?_I?GwdH$o8i1oaL^jRB)Zs)avYADG_0m~=eN6UI zoXhn=q_bfVw+B6iiCHVAbbGJwGC*@pf&--u=L?db)-HHIb6e;cd|k!X-_Q^qrh9H{gpesdoQdYAh34UwIiB66E^ zx^6rvKTpVhQZ7yk41f_~9mSQ$J7mdhrBCKurI`utF>+)NEU3Y*|`9izR#c zE9%+!^^miue0%7k8OZ8TYniEV+)(-2a&zQrf>XS<3vZjSaYmksER*$b$(h>HBZO1A zlTq%qE78q)IAQr$dRM(4e~#3+)2&^NEX6D66w|SK(OLtP#u~C_hQj0cVg^s>W)!?K zr1mu(uz>^#H6}ly&m87)+zPmpA>T+TKyT<@Wwu(Yd!4M^hoq0qT$^;_tW>yU9sg$c zcb*d=Qp|sJbOvV*xS;#G(LWFaN#!Vg6R23n!kHbEAC;i@WEC_G z+@txpk9%dlfJ=o~o7<(ZiCS*D|BDuc1O_LZA>O4 zd<>n2=KuzuA?F99=ypU_T4|5SoLIwFm0!@$XTcgn6&pUSzgo|=43=|p1%Ijz<1td` z%8T@!zjuQt32hw@SaheH`#yBDwD-j6$CL{FK04K%s6>V5V`vZ!6YYHhqf}9cHG!`n z&8WJWPS8N7<8zVfRyUM{CQpgUjdJGmFN35DRYw!U9QbNhAxe>Wai=R)W{dpoS&@7* zkV~#8`IhjRfTr)~>HAqPI*#JVrvJm>{Q8q{hT=4xYYew@HSSKV2y=;1CG7(Bp{*Be|nFytBPG2B16ifZ>sIO z6615Oys176ddt)m*guV+lqt%iS5$@d{Hr4_E<#Gi*U_hLN9R2-*hIin9eT+>asOX~ z=)dLvYY$xmB{KEvFdNsa!UQj-rf6~wp&L5c^E=5w4nE_5M4OAb*LXPbAAia8o$^k# z_$Gvt-)?hr5nCbl!@e463vTCE#Jjs<7Go6AwWO|*?edsL1@cQoWfa@$DgP3n8;8*1 zE9ttOjuSSKQiwgVLaU~nNPJOGvLYa$pp)Dck&c_z|MK~K*k0eAY-)`-v*8;kq2a4S z+Y<+JjL-OF42?Nds*D4Z^P+3a8j>m`PXpTVNI5xi|HF7SfHH{p&fBvEg0jNk_DHk6 z>bKy@8;Kf}-%QjOF%CTIt}r9;tc%Mng&i#TE9ZL=vUMke(}hC3*T!-U1$uJ&Up;Qr zqcG}~)cQB$KFb?U;tLCz zvK<#@)8|pR1w@1r0D)AMAvkF#xqFMRI-|1=M5G%BOJ@AaLf$weR zcU_+gIPn-%_*W50b%_}VVfF-!NeoL$o$FeLNC)@H$IXwYv~B-km^}pj=F~?Q!F9Fg z?hlFp@e1EhhrvZp(k%u9l9If)n(J&&si^I_uHu7jB7hyd{ZL*=v1Yt#(}m}NQ25|} zO_ZbCFw|!mqkX)xxR6bO6<-2zP4y0%>n8PCvMF2lK$XW1 z8buAeRW;^`NW*^eCzb`uT)14VaoUqqJo6Q+Twf8Fa35WE2v1ogVpUfx(I@>2UtD%Y)cI5UEvS()R?iZP6C<5@~^lFO? zlR@kmH%ZgIM`CUbVZr|>*asKcdx$*Ti;XNA-gWZUvYHxc>}z1NF$cWa$r46Cwt)2j zr;uY4GPo+o4te7~f!DTR`Ti0+)=@z}SM&qJi4S*U7E(>#x3&5&8Tkn(Ph9P@+tkRB znY~Fjv^U6oBW0OOvr12XJ&tRzzTfq2j?1s>^_%^l&j#8I-V8}{bYm6y>5=hSMl@&8 zy{fSCunjR0iBk)Y;340j>oxA0NNsABKctf>Ls=Zcml@H+hz(d{)BCDTS5B5ir*@*{ zdE{<5XDw}L>A0)Ma!y*+m@xJhtrdz5yLs&doMwwmpjSmh5S~R1GeFE`fgbg*8NIi8 zc1z;?Liv>hy~3xIz!0{g;gGiDJyU0~0-d3%Y0!K4`}B)J4!>;(vUI9Mn&vht5HW=MJ*mY(x6#R}5N^@>!%bv0m{0 zMBiR}@mJyQ(A`AAuMBUJ_EIH6Wi&GFsi1r2qXr^`GlXitzm4N=lyZ5$Tm46AFo418 zDV=cK=}x-J^G9H+2pKnEgk*q6Hs#oizlk^RpTFU=LZ!UNnwmV*HHA4(?mhgHh&mlu z%M~1tniD4oggDxGku3q;9a^XcI^#R~Hh4OE$MBS(YDz2NHYRAP3_ zx={7aRW)i5@l2(q1Kk}znG1mxmK>_2cvfcMd>9t5t!7bhRVPRujcwpjOwG)BF{{ba zEdj*o5$JCS@zgf$B;iLx+wBd3EHOXCK~Luyt(DCO_)T8eNkwg6kT+(}UKTM%hlEIe zR3Q~g98SnHxAkd0r0yV1{HQ?bobQ0*a%iec8cXU8w9+`Pg4=6K$4>j$b_O8(%uoy) zAo@V68RO|hH8t{?mjG46zpFd$V6!{EML{gid|_-8H(wwRY`K9r+RND3gl~Z)D1^Tm7kyo z&;^Lj9I%+5{#26KNtP*0EaS1v&2@f^+A^z?*G}E5CBF-;dw!Xo|CZWQM20bX=F_$9 z$t$OWS#gGevwEOK|bus$@6{Aad z;B7Wb2ULLIxbf1B(=-;&=CB%?ip_vL5!ASt!09^4+=D)u%ved|a$@cLPV;Y-tW{nh zFi7{^=vX&qXS3+L6Wj+mQLmp}C9-Y;9GJYOE9$2y4R)5!DlyLM(X0d>zk_z#j0rjh zUilw!89X!b$M(z%rDCgs0tmXJy}6gq0<2eEdprybz~eCb@`wGafB!SY<03}y2Tw8_ ztQ4~RzM8n-xVWY;RgqDLaXXI?_jG%fo$^#Xp2_GcO^=4Lkh^YnCx7BtALjC*Qj0Hl z9dKB3M;Gm%st>N*;HN%w^Tq1h`1PhB8XEJeg^mA(SIFYvA-T+6MPQR2x(X`h#dj)a zzo?RGrTVU#N;O`EhpXR{kpuI$uFF+I%iPnH>CFU8Cv_V#@CgA#sn42t1I_fIe$!FWy37|IO236m zQd21d2(F(bPT_9q>HPhs*%eI>qCRA{6#&oulnEEl?3;(rNe4nL+LpvTKI*>}J$)AF zu^YuH@%flFRU;sEyN#lp`gzmXwQjfI=uTW1*m_Ip_}Eye}Z=0!SR*G!Hc#i!_V~Yg11Wq_oq~I8`4>`~4(j9HEPc%KT5O zqmL>%tmyU#@_11QkDoGD>mbrR2_(@(<>seXc$i;3Er_+J{?vWYBpIfKDpS61FIo&~ zsk_A#y%c5|B@_1G@OK2#F`x_&Ji&{ z1|eQkWZ&EW2^`W%X+LyLYf?WQEff4r==LTn!*cjAmWR43!7A`_=KgYjB~xaFt)lKo zP60_+PLk=rkKlZ-pc*#)Qf*Ja6}0lin7j0rM_%&L0TdRvIssVd91ueo1T54EG+8S^ zTNU^2S$(8{ylFA@%I#d zH2!Qmji?Rk_cBILBawj*h;^jep?-_CIwVMW?U=wukCrVX8GwLHQXTPh&ZnkwQm|E3 z6^>>d%ERqJu&Twa2g~JYJUAV@F{1)?5x${r?DjA-R_bfTlgAKb!(bNROaJ=9zVp5^ z%U>?1+z@^TdO_=98&}gsd}X{VHkSU`U8G+a43U*aS^}20Lm+&yIicfLs}m=+^jC(i z)?Y}rsknsX$pfj4Szq%ikY5Cx&*k=Qe?;-X3&1DKd&-Ea9LBhbu}14g=we3bTV2i{ zDOb=6slDM=LC*gBbu08pEBXQIaUNDjoD;GGUsqLgOfgVqbyCGjnyOmZRg`1=mLP;1 z9)h&@KB&8#_z&YX>YaTjpngZWS$Dcc6Fh#;b?J)Z3y6ew>h{ogU0rD15Zf-vtOIia zw{Wuq`eNo#eTbBjg?ZY^cMaBz(qg-jMEVi}{8FOD@wal|5}DQ6^a1Y<=zkc}@_fZ_ z%+FW{7H`D%nA=r$*f8C?R$mx=deTXmG(M@XVwTf{-tj}3pgyA7tG6vxs}$?CD~~&p zvEF|P)*v@JNyRndVp!V{s$n@>I0G9$|I(1Z2A+Kv=6e(;@MjaO=ez%+(t`q`)wI4? z>#lD{NSyGISEtJe`ZHv-k7s7fcLjagbRwS(x+pe-NOkd4>pM07NGoGhv(+IYAo%aHW=x^5@lU~Lhvle1OBrk zLDV$2BB69^rcApv)a#_BCL!`QsoaF~T3DfyaLas6czP(?ANj*3^nOPc3c9arrqr>} z4i;T={+kz1 z<0*d6o~=vQIm7!FAP9XAv3|bHM~a+?7CtOC^NhPlZYd|ZOq=htyQ=PKR;YwFTh#QR z=*gDRl3x6K`ow0{upd1Yy`k3Du`=0p7#be1-djmRZ|0`%;d#s*V(_sWup()u2CUsQxXPnsBD;1xI87AlOO+TMQs8ZH2to1|jyM_r2765(;W}X*x!vx;flcZF5@ct;I-o{+@+e7cII^Xx3U`7cp*4EM_!zhCELgG z&p*J_j#y*6n-3T=q#l=o7I#T(_)zg=uR(1c%R1Hpk-R_3e5w$IMF$@il#c+J{5IQ> zZT9^|G|KT{-36HEAhonH2iaP-)-S&@oU(quJNP^%V1DUuFhs$+{D}@blzuM-tk7YGu|Awkc z#CjVM%0P#Lg|c5lK#)fR=(gss(X$koxz;($5bgVLHK(n1oZLThYw`TSlF2=r@zM#4 zi*aXa0LI&gH~Avq%TyTS*E`?qA13$mD7XKGtY(P!x=6finbz{h_{FvYyIXUlE*uqM z*fQ7-zY%MD{<9?eiG#^ow}JP=WIBrcEkUvP*%6Dz!+?Df!z7S!!H9}bk}hyQkvGfe zA$WuQn*k(yIU;YdtM{8$C4`THEe0+6ugu2MNe=XRZE9#V6&~u^Be*>S<^qfh(Szs? zzl-Z|T7 zBlY*g;!#8J0uJScn+I7_I{tH+K|j&9&QuZo1-I9yz88I&U*qVjnhOP)Mpm9jCq+*m zUWCLgRqltc#xax~L*DZdvbO$AV2g-p{8FTur0}mBd!1a_9F=FjATtlh`j4}EmUDrW z-t#sK6rr&U?U>^=Qj=7Dab2a?K2=Fm>MXC?1f(ER4ed#M$F_h%HKixAGv`m+Vrh3@ zZxrPP8^y$uikCjrBBp9ggLbGaA{jg4Lvc=@@eFWcrxd)EvxYGkvIn_E3<^-lucC} zEW@(nOvlas4-On*#f##KFa?0jVz1BNN`l9~8SLrS z?lt!;OF2>b{|>*(V);yE9d8WFS0+uTw^?x!d7xX?@2{9^a5PBcfvV;EpXg4#x!O%*yUh$V@kLPb6F zwNq#5MAXu$*j=;|+3{ag-W`Pr7+g0<(WZ>BblKxWrayp{ch2eW-E^g9VIDM^7A#-H zJdLfR8l=7x>#5gZyZ)JOgt7&nP7^ATw=SL~e4FFdB!gKsv3{gTc{3#QF}I2_jOxwZ zm&#tOk_YJnfO2ddjC?gQVB9=^?z_pp!v?*v7T57o!`~A9w=VqCD9&6s%Xs?TM1HZu z&J)S&&k{9=fegNV+ibw)u>>L48CpDCa>{u8cX>Hk*X2f%%{<114bIV6e>DBThHbVh z8NzX___=s?kQ3cq<~HED?2aC#Z>m-d+^;(~C-ewwkR7Ob|AAEVT_RSveb5qil%J6t zA3_MCaMzYCD1e%NNa8UEY$3O8lcrzad;Iz99~&wgPnPMJ!1C6-&?-G`w%#1!bRJVM z(IH2%DDdZW4P$=6JjTRHlUAtgU*>a+hR`v+b6Y#0V8axsBrkjfv^Lsih^Oywv)wOz zCw_M#UtwZ)rW&z5omGlvF46zAzAn<%RmP}!`9aJ=hpp3xXn0~U%jeM^paL2lYPop) z>3?b5Jzw&YJZ|=2&7_=>5C6~Vl`_a1x9bioR;6V^h33K@jEwC8XSR2VX`*l7gmV93 zOn2-s*dT4{0x0OXXLjF`E(pMS{be%qvws1JtGV~}N5b41$_v6kq9${66mZIfBK!|* z)71*fjsR`?pJ_KE>(f*lUVji(%f9Fp3vSu60ljJksQ(8f;)_t?xzVC_Oz0fMvis&) zKqE5k33) zI>;xsca)QklBftG#}u_1Q~tN}*Y+@dT7!`J9t;@3b&=ogXnLqGx+7ZmNMZXPw;?h^ zJY^FK{i0ib)QKEo{%DkW$;#g_pOLo1co(6Z6r+sAoWHpi_I7>b7QA!X8^EN57+la(CtquYRybsz=q`|cLj_$%rIX!(sVypqf)brXH znrECYscvCFI#2hgi;7o5xAdb=kgu|NSrKEc0$lFCqfsaKiW_2}z+GUoQBe}7Y|B0JRHw*A2{f+#-NMo}(WgtN4+0LKy= zm>)c1n^owBXm85FE$}P0bh$sV*e-v^(aAvG_eEn~f&~AG|L&%)_^_-xWv%0LEB47S zK3bSb?5y(ND7In zV!VrjC*Dl&a(@CL(l~zwG35CL*A33iO$7(b>MOS**|WSn3*Sn~Zn#vfk-I!k=8f!1 z56DZR&Tlnl;=U96ouFpRad>!G?@{vTaC&Rzz2=Iw0_w|xzQ1YUP|L{8PoB?=uFYRL zoq@CZeQY~ipnu`nqV3Iw{!q@v)B5x`L$6kDq=LSJ6o9FZdUV}AD?=9K1vL%_J?yp> zfGE1Wv`F>~56=kv?>{hB){(p^uBw(cO|R;lBjeH}b1t@;Xv3jfP0YJcr!*HEfr*S(jh8{5{{5sCDm+c_lKair;`OVY`V*5{=ADQ5I? zAAJsN-chQZ=#l<*;qozQSvmGp4h!;Z%Z4yERx|Od{ga7+#Hyg=bxqz3f;i14P$Ga( z;eK-Vj|2FgJ@9dvALMWIkVYCKgLONWWLBESJlhh4uW^1IcW5f{JA7NBcL7GshD?sN zmeWss5@cjFL$G#}lK3&4i5!pr!^kc|7Hyd#tpCHf`$Q;U)Z;v4*8SztJjSuOlvRdV zL5AE}7HK4g+UIA*b0nG_U$o?kpD9!UuABGkTy##7ajoAo z0MvAE>rpqWiL;AUNsb*j?R^()3vx9cn^Yx;EY17AMdEBGNv2MN})D6tr(4`w<~MIhbAuI8XJfBOhk`@7ZSa?e8;- z-g!3g{SezXSu+G!_b1!1=-TfWb0VtE!vS;x|fe2>B_4RjO zd5)4$JP#OCrNi+`W zczFcc;PJNiiITMQHgS|q#NuOwP5}6lI>gQ^XuNVH#_{NeF?>LI_&M4rKKjx7bi!ba z$(oHI!q9@1=0r8_yCSlaA}7VAb^A&~Mcc7oj4lN3}pbs9OIb?@sQs zn71kOkL_ZT#_xLlyn$Jk-AOB5v3DYr#XDRow4YBD zY9Q6edsY$nhmB3LKph)c9uj=znX9L;2N}-^G@!ePtx$YX@SRRZI&Cko{O>k0t0`VV7n7%bNoW3;sb0p(whmALUL=Tspn)Hn{U zgoa;C;yQfSmjq52pRfSb%uebpBq-ep%RCPs-_S+^5uvNM} z@PoM)WlMEb)ohHuDx>Q1XCfi+Ho@Se7o`M^CWT>6mY_-Aps z?)Y~>(5Fwrvo9Zv&Cv;mlHzI8ussUKC=aQ_?-fs8UJd`yk{AyFr0!;UqIZQCK%jZQ zZ>Sat(`-A)5G*Rs!C%uqA5J{_Ef@2oSErSsU%aTb5j z`CLV=FtYfFS1B4Fl#tN5_%3mtYxZ-;AGXBvJ9tVwJ?j;xZR~2U=c|oB$5AyDvAVho zaR=n&RSddrw>M*%+ZNzi@$vm$?Jo4gVZXXrv;pGg%&gf3W|QkEt|YrGmI3Z{a(z?K zm7Cv5PPpNr$l)2CxAf;y;`lW{m%PkJCp3s>0mTMrwQCl2!^S-TCOLKCO|)z7C}81C zl{In5ZLjdBO7Q<*Ne|LoU+K2g27%8WjBQ*DdRs0 zRNwcL4&3GJ5Q{Io7@r zqHI5s-^;H@vO*|^5STj>qgvSwWZs8d{3xYc%@l2NEodb;pTX)-B@EJ-DqkUKP#cLE z1wVhDf`9PJE?`4xQC4a6pO7kZ>55Low2YMw7(S9SnuKkpM+hD;yD1e^V3O4nH3!Uooxk zlGu9K|0jTakAxzSfW8ggyTA%XH&j_|>dTd}?X7~gHKl6roiynv^q6#CC^l$Hy0^GP zIhANpEpMdT0jBszpD#SbJT@q^i9+>Xf8+(XkG)E_+?HpAH)#ABHE{5LTTl{ENZ&}R zw2*N1{=oTy@}&HSW9er&ih(tNJ-qye^e*?F6RYJT@ea1q-A1#t@PIkq&QLeb(=mZS`7p zc>9o)8Ya#+QFr|<+hh^$M3}?+3VpykUeSXz?SvCchS^yRbPHs9HhKaG*D|TpE>Q?&l_P5!9;b?zIQDIM0#$j7OAm%sd!FQ{f#u|lC zR0*r9y6QghuL>EO%)XWcrjxi({*7+A86#uMn$NvS8jeS=FdB??dw%&%^RF3`vZ^vm zFxeDm*3dlm@oIGFS7-F4ol=Z{<>uUN_52P#quw~3Eh%I362a@1J6d^zT(ko z?U;IWw7vbYu4eV0DMzLt!MI??W{jxn8{@y#`U*Um@5BUmU85kc9(_pfSFF*i$cD!p zmTCLf-5;(euG`cUI3>y6J_RL3mF<$r5?NM@3-`P;z&s%4QF|`LDcmk8bQCB3P=uM@ z*!jkq!sC5n!J=Zk zg+4|B!a>7>e?GT}j@f^rwycxz)?&r_)isT`i5~^?dsN1Y$_>8m|aQ4S8}d=-`dp z7WyGiFFG|y?!geldOt}s=O zma|_S(Ft(cCv3CiJ}i3q^&9Q(X>@(rlD635diLW7Zbm4#kBz`zy_>ykT;Y?$r>%gK zjn5t;5pi&Gb?WmUM!7EQm&})s^Bmx4QIu$!@OSL*iH0w9w2>blKiW_9R753JhS`Wh zH!ZCMGhmy$+)0?R8`2qfwXS{YOgigt!}qOyuTwn^Z1V?ma^D|(Du4@It<=a!kymUs zYz{@K8nez&DLAGi)$TJnvAoMM-x-=2XD_6!8>GJ6inwtsd5T}C{tsgNv}p|B_sZ8? z0Sw6m7DY0~QY^iPRDGWiJ#HxXLONa4!^&aY`f^{+5$w@6aA5Rpm{bGAz-mM7499dH zCP{D|g;A$v`c2vJGd5Sz;yRJ(40|jLJY4`xA*a&Ok6F`e%l}EG`VV8C>Hz!oEWeSY zQcuGkfKdN^;>8Sz^jC0m0Yj-gzYp_PV?*$f|jFv>CxXey-c%bj5fq;M&f2YDPO42WIu-Egu8HI%85MYT77~vtar2^Uu|4szy@y)Y zT5(5)v;C%7dfrJY=^HukU>c^i{_8;HYjAdi^ZFf0V8jHq{8CEW4C_x{=xOv5qTFvs zsYqbSYT~wYKAR7ID{-z2Vy_9td2~hU)fZj7H!RYE`k547QQ5TzbIE!tFW!||yujTU z4a5HYGaX6-9j#c&3W+T_t@DIENmx!|9bVFpGVM;bp_e&n7-3AQ#(-6^GBsQocFO+Iq*MydJU z@w2oqoL!c5btj$T(8Sk>*;C3$W;#W!BJIb*iMelo*q^YJQBK`D!3vxGy-*4AIfZOR zX5SaYI7L5r{${N%`bRd(m|VKdo?N_7odN5njK^e67!QUxEi!ci#!Vr;ULOh6t8HAN zx?~@dwmKypYOy`3szT43X9w6?ME<2()0J%ehZ7*QS7%e zE8tnjFhdmaq!dNo0mD?n>#4OfvF?z;YVC?y#5hA4b({AVmNS1&?X1h~zFz>YAXlqu zt}&~&|4{Ci`XXBb9(A=EI(!J8tj+m=G+fd6<_!k1S0;CiZ{mW+g_sdxB!r;ugB+_u z*z|V>SNSzp&wg*kVB7tIHzL4&15>+!;H=)HuuH z-v?^oNP97?;>5kXb~aEE(lRE^(mO16`CoWbzMWp^h;C_((+!%Q%uP=j@)=T{u9y%O zd~1?Snf>H#ppS89h@a6PjJ2v)qoGM+Gy``q(iaubi9rL*n={VtTrI@CX&C1wx_VD#`-unG+}8e z{>SrV*?KQ#3O`So{17XNTn{Zr*x;KEg!6o=5PF-nD#K6P0sx$~--o6d1j<#ADxcCs z>31;gru+13*hDni2blFs+Dl;jei^q|6ie@+@b9VrzShLkO-jZ^K=G7X{b>M~9Ywvu zzDqI*eXxk62C*4BqFqB?tS>Q{C+_qwMCU6hWFyvI0dGF1%Pl5MO5#500)FB3=%Yks zJWG9pHjHKbCsv~@f@$!L(m+gZlKJb)j6?dC@&8%8lOaqtV(S$hNG7s$I`#>^sMOb7 z{be;R_Pw6ie7!Vq0{m(q{mcIZj4?2_$Bj zFz6zi@>vm``A$pqqBQZERfX0RYo7eOLYPCD;!i9jUqGNcr^)FtykFggw^7qxY)3$u zb<6qtLf>G`rt42PA(<@k4zO_-TZd{uIJX8Jm5VKgH}3qKG!)+KmJ_-jT2eGE{5q}9 z7Pe)n%ajn-Oy0NfW+KHtCV}AI_YT0{# zTE6CekwfrVYpj=Gp|aq1f?{?2tASnpc+KfzVUhnd8Gr&~n&ehj>NU8*K{spjAQ=j7 zz~VDSvGF%db~esh?CeqBkbgVRpfV>+ghFjWNGr=?6p4Sc3(?+Q3F76P{KcI3)P{ciI|VyT3AW_)z0n~DKYg$;PzY!3+eS5&G^MuZ z$-dNCAY3%-EK~oUICI%(2V(7f5(Xve#q7Qs=Iv9;-W{TK8XlTpyc4H>^NFF(y{6x< zzb|#_MSjb2MAi+xL>=dR$e=)W`zFt17$|q))MEJ}G9mj_GwU<12b;c;$0N+;;0c2b zN283~=X)$mNN@o-;mW{o>6WJExSZ z2M8E`4mAASfN^#D2Y$sbbIbd4ibr#xm8itS`xE9QPE=^)m{wwKYvrBiXI?YPmNtrM1MHwo-&5}gm4S!y6j|8qb`qwt2?_*)V))q&jjZWU zYdj<9g(3D;Pt;y^85gbjOAwT8{O8YeM)WA~6&|29Q8q6oFO3>kTo_9!w-ke)b%5I2 zQpd5NY4xgx>j}Yr=T_f7Vz=mcAe!pPj?$EN_LA`k^@qmJua%n=Z=x4sxyxmGk!YsMsC~^pGh*5d-2h+<)*u@ydrn zj!NSld_?6(2v3x0LIgq?a9TtHba&zdhBVW0jrOIRvQV&_OI^H%(fx`eI~VJX$xhQx zo9M6y$L%bk3)JISj%)L{$D`(8I&hZcXQ2lc0c%Fr6>7rs^QeSCxc$evjZkOh_q^fX z)B;ZGe|;~d*ZmQ~XV}3ot#J$N0d@tZ^73gv2E{Hy&Yg4h;oApi9i7Q*p>{~U%%!SS zy!$C`P3jp&6HiP`p~@efEQ=0${8+OuU%q;kVYxc&BmpZ{;b_;@@4o!Xc3G4vC2(L? zP~X1I{%GV%{W_&$&bxARW8>6EY_NeZf6P2}*^_XBCk|3~Zkz*hSzghTb5^%!)bGBD zhRef~4JWmY~1##aTO10vvq201tFBjzO+x;CGAR^P~gUt$;^+-wd*3N=3@B&|O@ zGb|LA&=9*r>Vx?P52@s3<#|HF#rJ31_W>Pjhkl@3-Lq4vGMO(si;QVdB~sO|o+XhO ztEoOOrrU`JAEocj;hB=!-_q{x`gn|*(Lh$8Z;$RnKF?jbGquz{4fm33D%U3*E3{x%f z(l_hdD7eb!Y5sjBa_+!1upwy3qe9UiYw{HED0|!qC-@^ukfc1) zOn%<+G95P;r@2Y~QR8$w>-)2K)Vb&G2g-j&s>wLlK`#}z;r%{Xrt5Ep`Z|NLAlu~( zfT^DYVRz$ZF!9UGpSs4+^9)~sG8U&$#NSqH@E2O4D36t(3ku}jrfJ-)5d@|C7|?~~oZ z`W2>8cZh8v;`sIvuvmk()A+D|yEpq}MlhAe%@Fgl+06LY*^i6YlMmSp;#NZyFcmKY znGQ1zn=Q@sS8BFxsob}XLp>7Y>+IMx0#)+N!0AH>21W^FeA5n!IF4H^Q13EwrF%O_ zlzw|WG&-2LZDKowD7^fc`REEP4UWh6j|L#!h7;FYm}4V!)1{M`v)!{j#q=wISJyT@ zkNqT4b~N3_!T6(dDWMDIr-awq84R5ahzTxJeHa7jEfu$8uy|Eq;u7D5e$JoU#rMvk zJTyrbrOs?h#O#KKjM&ZNamjBPO1CqLkjVpv=o)k{qMnrg(hu!-viu&b+yc~R@ zZisR9_F|j4y3cE9Gzr44 zB_<5M$Z>~gb`7Z|lnTB^xn3gE5ZhV^-z{CYn44|^-x`)2TRp!3F}1GTKmnFq<;k42 z(igdp=OkrZHSDv31R)|D_bW)C0H=&NoTdIW$ewUusomuj66s}6UFgP}b;b9jJ5hnQ zUM^+~ouq8Gr-I;0aV&{tgwnLnU&H9z|UzEbPp%e>!zs)HCFH8jb-a@vmJ z7U59~a2(ln^N+#q6Pe=;`viDr!Dd&K0dw|M3Xu8|WA}Z3d1hjrXo^7XS1ZO3=%L!Q z5r)?6C@hCmf!!_pV3OHC+cT$g5_1RE;z&0n>9|>kEgP@5HE-s=URHU+$HIKb9fsc*+|>x$ivd^w!Wau` z5N?H;ng4bsMTEj-UCzNsVC*@=MiF7XlFEU6mFb(n9%^jV<)OAdEu!IZ0HxS5 zlH*nCc^ojrQ*oG%z=4uHeE6Y3luQ=xd-x%pB$z_{sX!^rLB4 zU)&aF-%#18pCsb!6@s3~yuZo#IT zLiTWS`sgi=cn_iXSON2*W9?bz$}A?UE6`b;&u+5qS#eBQ=d;g2#sf>!j-0>NefG4B zX}-2jG9bSVrqYKZ&KoP>p;Fp)y^G$@v}-oh2p6ce-6o1L(>@wWB)?|w3b1>Iookpb8e-?7(JPx|>rNABJGetGqDmZe0lYBeZ?^_woPI_t@q zoILsp{r#6b$Dpv-99tm8qvbj20?1NV`1D*A(o=@?7MZUXZYXEj13e1s6N(qiz;Pj7;90&jD0q{^{1X^(Rxg3UEZDSuwRwyceBK|f z(ph=X36SBU*L|G(Y|nF`eKj}xH>fZH><1wCU#o~V*!?_F$%XB=Xgz(<3B;Tb+SGWk z_$q5T?!A8@bYPXzA_kO1=vm4U=FfHTs-;xTS zAX468JfJX7%N6^@!L<9e5Sa3k)O zq0{rf{}y6i98|P;9i(|RrJunH{KtA|2oOB#ql`LW8Y_I~x^O5BoZ?Ce&w{;z?BWUW z$7~y%s9CQB65hUD{YiZp^@AjosVPk7Hq41O+j2c40OH&SGi1CA74D5b3JW0OQd#(R zU8jMrK(QPa%_P_$r?=Fh)NV6OR88fDs$VG6bGh4+I@!f`rS@?pHGa`_+|9?dduUP{|=)4R%+ku#1^dsLJ&?bjGMI0qt5 zZSa8qVbs;NKInSO4T*We$&JTv9U}BiVou6lrjHIk*ef5n4>Obn%EhlLFc@-ATp)u4 zSZUvF)_Gz*cAhB}Q-5xIFsWueQ2c67%0Hb%HOJab!XOfeHv{9(I+VqO6lE_r)u2Aj zUbFRwuOvI)WB>3|VXsgJ84K-kGj@yMd|{a@J1^o3e2HkC3Il^@Pvs#3TvmZDtleEw z!s}soqrxwa?p3_^@z;0OJ5brr14b_2;|BUrUQy;Ce8cx%Sv6X(5b?e< z;SG1a=Mn}c)cxn;gqB01>6!1f5C#QV^{3F|#XCo)@3q;Jn^_+JkEXMXYO9O3HqaJp zDN@{vySux)J4H*-;smF~-Cc@16fYD=aY=yU4lNK|N`i$3-kbZ4`~5gSPcp_C=j^rj zT5~=#LFV~Euhp|gq_%`L684NV zzWI1Svj;kC&BzzF;5G;Tqvh6J&VTGcP36Tw?a5iJ_AUQ6mH!Xzzh9`Se7UEW$N89N zwc6QY5xOl1J)L?1on55-@adg~uB`#6CkkHy#x_aaMq~KX#SVkUh4k59~Jc>$M3&L zVRZb^16QkEaqdm9L?jWZc42BMtK&3%azj`8qW>c|+SmA?rsTwCpNU~~dMBpxlrknM z%yl0UoXoGUrZ!p>#)SLy;tI?_S;c)KA$!EqThX_ETzJ`FCs!rZAtfx^C1++j!LrEp zp(7qu+`0S5pm!WQcFUy-Sj>r+8b);M52^bsEEcoH?|Eg9WRP&&;9&Q>3sFkWty58I zRfMC;UhSx3sy(rbeIR>8cEph^NTLiP;a{-&BrS4z`r56?kgl0JefkfR$-9ELrxSyQ zT(JZ;p#Gr6#mT%#oi?I*!1X5n1k(&wsad++KB2 zua-xw)2SL}#&-*@pT#TGWyAo(DlP6$at#fH?F7Y4oRnDuB++#S8Z+3@v&~!$0I!KR z0MSBkh}Gzmr8cj-0Xld4JG9!f_0(pGxoe*Znp!@m@At^eSaM(9jWM5FQe z&#;YBr?zod(X%|+j;fHA0sSEIi^`?^fuv(}A~V5o=S6S?c)&~@(6F_k=^@cR2N0^v zH^6rFdD-}OCU@M(W4u`Y@R9d_C*LuvATbbU=q=QXe|u+lea+@LxT~ozdJp)%dAH(v zYzoLBO0PR+k?03L;t|_a8ylflWI^2~fSiKGL9Ysh!5|se?qH{qxx6kaf459*prdXK zcKO*xWoT(OErqFtLw$m<^;K&B_Xh4g7CyaZ3H*18a0m{Z$7%2hdG~o1RXrPF6@QeR zH6!>=MHWN}a7kl|;yC<{eK}2l5k}#;P1Mg3<=1`|+RuPx)N#is ztV z{}r0n0tgHb1)(;^%&|GOTbtt>t{Zd0;HDyVMy)@3uc%^PoPQ1!qQG%QKd8k?*y^8q z_AP^zO@*t$@^X=Xpj6zP+RI%<`G<)UnjNXz4sGeQ+?@3Xe;WEZNSiH86Dn9ow-^}bp{dd`Hp55KZ?kEHE z&RY!TxuM?)cXo89DI9uK47!|zspIQViP#j_*M9ENaRhM&BPl7VdA0o(H7S%k>eMrY zz=9+u5N^UNU7i=`=bhrM;y5DbL1Tr$}{abV&Rz&eSh4V6~E*Z^qYudCxwE&pse6)a&%2ZLw)4nsTDltNfk0 zWgVgUNdUN=xevcRQKTVq)^&EY@FSD&!39Moo{}UoSPj599LOt)y3ZYT!BO5e(XKNu zws0qxbU^UH=$O!jrVinz6;pI5M?1asoYSYt|InPGz*1I^gx+}sr<6|B6J@S{q+jEs z?p{W=!=5|r>cTyM>>d?xuUxN%iJ9D$`A1u`*kG!V|IpMzIm`$lc)g}0l5fmq`I8-~ z)AmXuxZW1A#s>BrmfK$$Z_%8J)~GRk&shA1iU-Zt>oj$u*Lx-&v+zjxD?tNvGyc-$rzWx_tCag%E$<_UhfP8vhFjC5e9en(AD!XZeJKI^fuk<8_T~jm} zf1nWr#`x~Wl`u}Wq+yttia)08_BYjtJf=~z`g>x)fkPjF(?%>?*=3fzff|fa7L*YI*4xSMTaQGHVMAH76F#Aai-W`8Jhus+2la zP$~xT<(-EheAj$Is@LOyijE7R;`Z8)jrse$L*c1wrluw*k$KPAMf5wPRVgXe#JQP7 zc|=KrMH}fORt|&EQwlBj#6sX?{DPFMAl!HbRpO-^Zh-Ko^kFy zp_RhM=2YkPPYs?b%e&0OZR6-Wb7P8dEVwNMR1}zN0V?^^K_)_~Z}zj#BilruIPGbj z$z=&Zera|?hZ|%4ZISJ#a-`VzbZ^2=jfp_#mr*dR7Op~cJ?viu9D&X1(o@&0gB%Gd z${Zp>W0rQCu3vWDjb91p42&&zjX~t02_==zPgxVK*NETR3)vPP-`vK{7!4)yjqC3Q zDKEXLcnQr4or=L9-S6rcdi?nrxs7Or>u8^!bT~)#^(-uz7Ok5In>siWoaiyY-|6qR z{I5rGMKTzQi}Cuz}L?{J3!Apd>$*MnYY#S$_}_1ZN7wAbBkO<`rqf{6t&8tfw7EwJk6Sr z-3%KKm~P&=SLh~`YFko!)w4Qvh^3ps{P0cH3-YE!HO9p{>bUhytZ21^Y0CV`Uy|+3 zC{9@soK*!LkaCb>IxWf%tkmzxx!H6!>rvB_EYlOMrK|e!joaudi+rlV+?4_Sr~@B< z1eK{q7&gouq=^Fp=1=n!*ljo|90n|-_+DY;YZ^EHL&Ko#q=8{kBvh%266{fDy~dwP z6L5X@>O|Hqgtno^n4j68aoRUaQvCf2A1)z5qhh}@FXVQiAAZ9Q3Y`C>5lZsHA`U=B zvV5Mxe-6?(txiQPETWp?D|ENYlK$B1j?RoCISrPYB@ZfTkPE)!3{&?Eov6s1IdRu# zoi_Mg0aTwi2jXixCVQ#WOw$o1l=Om5@2k)oB;ZOOl}TGyc<`k@W%;ti6-7+j37rpZ z2bB(ffIU^`X7~~fdC@=*2yBQyve8^@C8#-ck7Q_gXhn_7J5c{#!^&(KKy}^gk5JKN zh~R}Q2(4vTlG;-1``8_&?>#w}o-EYM9?g4PSITQ$GISkF`@c)I92%ojN2_HE=(57y zkcGVq{$4ZOIDP810nrsl=t41O!YGM@?pd97g=Wg({F_axqnQF8MzZu z<=?$gPXcW`LJT#MLhd4ZYd3&_vsjw#i@SQ3s4!42(#^BNFR7f~ex?_Fb@U=T2pp&E z-uAJYR6)DFz;kKNKZ^+#8NUIbKk1%YtT;8>>MS))-3!W;Qw+HMFB){dhIP^-KX^^} zpCpnA_T&{@cm0C`+-rc+u8+sG6523GTGoCTN`K0)4o{Ab@MraE*ZtfSjxvt2B~{uc6jFV( z&(LM0Q!7aq>7 zAKPP@0Oqok7T}uaIl_g8O=Ui<%9?)gPy`dy3wsCWoswwEmX8v!BGbk>gM-mTVZ7$0|LaCN#0i-2j(w;f z4F;6D3%nEcl8N+s1!6mj+*CMkE5t-2z$TVKpv@%~9M;!{yFGuXqAW&5oo89SN6F)u z1?I8FCLjIlsAy)@&_*GcjIz*)!#4~)ls4azgW)k_QWC8Z?jjW*>eIj=2w!z5cZNXO>C^5CT+xK2@dRE_U^#BbEz835`$*HE5fUzxqS@zfOI%8g z77v41qz;ItAy-UkhSRDnO%tFlL0%>?wYMx~yyP7_2$!ijdmQVZ_06gfC%+w%z-oy? zf61uC<~o^uJNYMmV~8@lq5dC@&(dwiA}oBf4X&F6B9GptI3%k%Y};sdpdE?57GI6U z@$c2TANnUZz7hpe{WdkqlJBK`ab3glWiWb6>6gm5h{uB-^~h-jE3hTIH?}@H2~HaE?oq%!m^%5XJPMj+kM*&ptm)k^SE~7Nt5qHd!C* z*}P6l;nXY2e%Gun1rZQb`G;g;9a&oqt=fMt4}_G#bM_%JUW>@hqxpKP;}t=bGcW4r zuC4HxFkvDcm&vWfY*x?8u=Wb}5{ocY75;&`l%czbsV9f&`%;y*Wvn%%o(j{ODn0QC)MFq=hvhcIZ#?okVuDFUwE8S*hk%-LSnLeyypW-w-iV!`CtA#R!^pEn+FDNOetv_ zGDHHR8gL}E(p7&1XQ^#u}OqUWu@QDQdUmKzXfyx7+^+oo>OnUrQMNOWaqL{d9*rNi4%^j#+#hPCkg&eZ2 za-Jg7?AK@@5V-0_^BGDufva51IZdnwNclx(4 zI$sZjwzP(1B57Gqd+Vv?9yekDoZa{>*58o`t<+KQV2gL)P!5`I!c)5%39k(A{e=5( zbtmurT+pK9WsElt$zQzr?|{wo>->){`0aRoX>6CXS`OojzEOy$csP zdE2w$R7u%$8OOuq!}Y_UcF^gq=6mG?xA4>$wC|;aj}{l?^xQKZ`Kr4e%?fr4;J|%O$2)uV%U<|;GIxm&sj_BQ5wfqxT)3LVNXYz$#QGW za#!FtRBBE}Mny+YT7HwB<%CA7@1;*s*WVypVVk)}li7Eed2d9#CjPAXnJeDN zEBpxXqE278rFwSQGzVBT6-sB1`*$U9zaU>iN4dz@=svbWZoywI4n)IHNi{MXOQ9W5 z6rF1~pVn)!`Bqy)D0M_9^>3MmAP-!OrSX)Q+B8q2(Cf2L75Ogfi7u*jh=g+ehnBtZ z2L%+C<}72H!_M6JsnQMK*bb|=CyE5dur%oWJU7pFd^2S4o&KN;@0sC7^gw6yktf*Q zy{YKFwVi}W7MJcy!}A|4Gurt#=lsdpafg1ZdhsI={YVoo>PtK+DfyEEvJT1!Ia_#C zM8O6x6e~xn84)qW@EvX>TYXC-Pawz${#%|iWBR$y*!ZFsV#9Jx^tgy3A;AlSm171g z9jbwzk0j>Q)E7UHbaXvH&s@cdnK&@$4zMkRWQPVH4-6V^ls!ko2jnTwu5mpG* z7n$5=hN%{#z67?LR-rTYR+mQ-RMed>CCY>-4N;mUYLc^)tBCfcLduYU8J4^auN&cu zQ+hzfnLx4t6VW?Ll9|OBJFax8_Z%<3EI8Z7vorQSxTt7dPR9o|j!Mm1Pw6+V?i+8O zp)KXuZk*%{4j@VB>+#MC{UU1qJCVx(08pIB(y{9{7u-pRgqX@omo3&?61i2fn$>Py6kIj|U zVCG8D2j%p9aY3BdjTq(GxM6*c)zujO#t-)q4lmOGCV0~z(`^*sxe17#YDC@~tqlqc z=M+|C20CPZ4d!bgxZ2YtIqvTz5co9C;({rNnt3vKO^Ga?`{U21z29+@ z&DpVm)n+6-E)BeeoL5grxqV15WGt6qJ0yY!Lp0R zlR=(s)k*E?;FPW|H%p_fNGe>9HQ~OJ((Q}W`R`_>bJppJDS33Ixn`|{C}e3Q6I~?J zH7T&AU;9uq`$y_dGwy3O?j`XsF|VXxqKBlF z2=CSt+k9G6wbbKLn>V!MBt1FDcPNk zCFuK7b49jTNZj|b)l7CPf-s_OLKkA{Zi@s$5(%=!n6izq%?s zv#%p_R$EM)?@Mw9c2e9wtLfCvlWu`IN7`~mZ2~bfr&{Cz>#?jToeY9(iq>Y{-IF`K zI_zsqNDN9uobB*WwnIf(g*P=k&MrexvYp*#8gYTr`roixLxPBHkaRt3$qit z$;uuc9(W4M1a$3Pk3RjqI))(SiD-v4DNl71WdIZ-uF;@#w|uha<*Vw)QOhOjIsoMl z|IMF9$Tki0h!$(D8Nw=@mCs)@eyduws0Qfcyy_>~o#y6t_?X*;=1+TYM=MSPmeH+{ zJ))Bub3o`HNu~tO?oKOy_ZHN+hB1T=|{uE^xn>8w#22eYZ)Oh9Fk(AKQ}fx}&X z#2jRC=7kk7Tw7*hu{+aFcw|78Cq|BVE0H>3!jX2bxb!Q$3^k0K^_EA3eKiNN%EM%e zZY^1WkmfKy$J|px^N&8uwGw5K`lj7F&I$Kj)C}soS*Y)kr_)-|3f?ks_*z}a`|!tW zwn(?4W+kSTMKV{ZF8}04TK>!W`G6@U4XeDN+Kg~NM5PvT2>x7u7{NKkJQg!8_g9mN zNFKtZ(KKZBLPsvGl3B^!Y|?P12_j@HUI@!DNcsj zd_hDVfJ^v6;!-`HkIwZ~wqmAB7Y0c)Y>JI~m~W+rz_*kxcd>N1p(9DPvwnh`8QXkm z&%XGOzLyy%5k<1O8LovZ`6g_h{xmW>r)pwhrSH^8HD27QAB4g4pXExa2y^g1@%(jb z(+#P-GEDq`en=}?@`gs7O1YKMq z&if*AYVijmPoAx$Jmf^cydS^_TbRVN0a&OaSe)%*5Q(|nrt`atdXJr-U6$j~7>HX1M?D@6X#o^! znu^-deVBGql8VGZKnS>l8pFo{vQ_V*dlo}qY9gV zjX-QdU?+?Qix+!AxC{NILHn23#}nNc-0vT74(SlHbP(%Le1)fei5i%;#&sGGzj*&n zChH%rePqqmM*Rx+p*r+kzsW*h`f`E!ny3X*)dOZl=r9_xcoK2M`yU#glMS6&x3Z*% zXIV?x1o{|JzcOm;P+kRZ5bFhcIQc&nygvZxJn;n)>c%TnM$DQ6|JXS%v3^JEv~%6IYdd__Pci*fN3)rlZ6U-k45gO ztIr=&<~OqZUdCTE0d~xyRK%!+@{HL01()4IQvueh4Ufpy_+4|_oOK< z0|g-{CQY&n>;vY9pD3f%*QTloCTD>1OcJH`p?~~}D?RLg@-ck%TN2YLngES z5TE1J^!{-N^bx=bU~igpWQym^>CM@$NT!!c<6&|i-1eyuedvg8VBC6K1lz*n$_gaN z@^q>j%}?(7iW7SjmE4Xk%?hYJh9R{6``6y~_&x5^sikt3Fu=Rh-@f(T$Y)^Jf9OwdTPsO5=CjW~BszFxeD1o4D`k zP;~N`9jr<*LA;`YxlLH|EcxSe1Ll*|TD>l>wlyZGKUKWXEFwA&u(%~=`dvklS7duO z6^2n!@rA@&Q^M;ygbGM1`f6(%}TqlH2-JmXV zRPEQJ%7_|0;di>KMfa%*70iDdhdBH#u*ZLj$Xl3bhLH9pPS^A&=A^c=$L)h zs=i=oAcLt1kpdCu$9Y(+^F9XS$G2uq;?_u76!Jm*T^JP45>9(%hO8%Tt(tPGEn0VX z;NQ?~KnGQ~+>ao^bLEnw@RLpXmt1SSvV+-1rexc)71Y9IB*r zKzc3PDsUSn+aRmK_oRBg^$>Q+QfMOBr(c%!DVeQ~7VYr8kFCSAKC0^JKifX*Te(=I z*1I)m`nr8B5j9KPdBu2!!^>1C0v*dqXY;huoh_hy1I|-&Ewa4pCiuEcUOKiN&t$VNQ6JHa_BL!8BAnEyeDl;0f)Z%_EP~D}+XM@v9Y$9LwCI zLhK5x+DAV3br%a>i+$N2&@@CTc?-(>mqJrMdRI}YRrco6V=YhWk2ZY6+OuhppqUb$ zQSxN7p&{s?H6|Q8sB5-BTWhePE zVWZQ8yL3^k>O2R7<+5LVya*0+B4QDjL6H!O?NFC8a(WQ{T+##_0k1w=!7j7>@h+AR z8_6o4=EfQ0`5S)_YIo}!jCvGUY&*VB9wkseru6$=aP5cRA~kh1DRqIec+FkO0N|?6 zq`j#V8eJtO_0mgN3sQ7a{gVj7-sS6CsmKRVQU71ISnk znw}`r9XZ)fAtGSSa@-%=2%7zBZ2BZzH2ya>qBoCTDyWVZKa? z@Om!6q}=x=`0CNsY3mpQ;zS|1UYjrI<&^<8HY=e+;eD7b|=rqc$_x}=9X-W-2ExU_SPzR{_~CU z#NF3d3zazms8BNYPF2`%BXBM7vmHu$q4_#!@{az6m04!U@-4UIq&m5qHI+?QcI2>T zv%-$iUa-CiLByZ7s@L`+FpD9MV|b(0NqdKhI7c+@>IE)k)NT!>dKeZ0=a5%*4y6Up zubr#}ODFf`*4CZA8Kw#e8b3EicV;?AyYztsr7Fs|^5`ea6z72pCytJwA9Fywp!e0? znOES&S^o&0F@epl{f_V}ecF0`{ulP-Foh5&B<82Oo5MfFgVYbT;L1b%SzYkIi0KFs z8w91aJ-4$aIrq-#1xAc!0wX@xtDFM$Cv;2iL9AAE?>sK&`K~q?3e*Y2I9j)4e zR~O*ocSutF`ENj&7=h2n04lbcC)W^DG*U>qc$*?euAfJt$llK@#XsFI*ErR%yf>K| zCI_-k&b^Iw)e5iA?mrkaqGJ^i=xW?-KI}Cnrc9l!l~Efj&yM8&4vKK*XljegrMHOm zmGp0=HmVD;wJ3_ZMn={ z+X2+6MeJmmFJt7Sh*AUgthaN=+c{p>)g$$*H_S<1UHP0pAMX;4njv zvi;)kWnPLGGq@{NDvAsq%G2$xY@br^%!I~O{ZOQM+bjHM+ZF z&rB#MC7POY(iYvEg}nb+DO=$kV~YE#=r?kI=cSGZUS%VPsx1%>FlNkZ+#Q$aFp%4t zMa0e~%BBjr+zNB8<>csVbz|f6ceV6_0%=Jy>W6)!?lmzndMbB z5E~(BHQdTF&>`t8o!#p0A~|Y(pJEp@iWYvAj#<-HjzVGnR%73#&-AG_%}iO!4E#D~ zD)&p-mn*RSQ{qu#)sbVWd=G`HW5f{^`&loLiN*G6>C0q+`oDB zOY*SlXYLdb7p+Z` zyK>7|){(1Wq!52yhTOQjeO32~gFF8EiH4mnP>M}aIJdi|R=KM+evyUldVpW!ttPi; ze{7a#t!vu+A{t=-`qv`nkbz{gq#^gIdgVs$neIH?>jwT4@IE`-OunhMtiNJq!_Q<9 z&j*}*=J+34pO;anlBD-nlCy42ih4}JM@sy4woZNs0(O=zn!)r<`qPT4{7TK$s; zGM?}MET*i13S{X){K!Oq#zQae9VQE@m6iL>jyScKE+q!YkI3aD#rz?xHt_*43j4t{IQuX`x%k_ivJaM8C|G;`>Ak$PG#j14{Y) zn|@r$3-qpbeGEGny=$L(HOl(}o~pLi$VkAZ#z?<`S5Bp}R210R$NFry18O7*Va<&= zA_Ix^L!sTsF<5QR(RbKi^(s}MLn43(_c4W-h~Tm!+6X`XGp3H%xuyD&3Tt#ds#7fn zM&#gU%^h~_B`fO%mi8Y%&rf7WmMd_ubBOqQkM-&w35J;CPn=cY> z_yulp1?~YuB@2`Yt#cmMZt#yU=u=XsZ}!G3(NhE|7_|9#e_6ySwf$ha+4tbtjY9h1 z#Rtx}uG%^IU*h$D{SR%_+o(N=CFY6Zi_)~RfzgMNBMU-!%`5e*%SsfnPIDeg)L^@# z_@;fF z5*OPyO0y6pCfzY9oG@pnEsOC%_$5U!F zYqvB%isTQ*^i@iRd5V}*tUo}+JNVz54}E=+YJ^M6UcYYR+NKJ9;=u82?P4dz_Skz> z3OIQ0kfIvEE%((ad5_Kl=NMMS3WCOJ-6I<^5gY^0Le!# z;u||w%0QBdc-74Cme!&O@rWZzRI4X~>n1Eh4;FWX*P0(XRbi$c-lw(zWO^<@t6lMc zvPFN9xA?V~gNcw7b_}bJ$7(!qqvLez=@xlx2P|?AjIv8CRYtamyBlTcRt$;*h<~<) znecIc{Cp>3{K8k|K}}Lv<@O~8``}BAM?=^>3^p<=5=?faQj1t_GzT8#t&B`no(B4w z&sL${Gj)=~A!YHD6c<5Gd}r#mJ-Q&b(z>6^Va;3Nia?pm%PW1j=}{YH%+`$53`@|0vU)KzuP%)bC<*^_;YUBvPGSK-I>P}9v?eXSN1;WHF@h= zGiyJDmk&)?+@lOZvI1?QS;|zLaf4H zBN+iz3NqCm!X-0Xg5xkc!+$B6(KpiSV%{gQ=DoJWU&&th+39E zFSIsy=4&^9(XO=~e;;3G&>*J5CWp4tMMVvv$yM7uuZh~Andg=K^6Z^AB|=8HRb#)|t%KG?w2%z-}F@!;nGK+fR-W?3ieU{gTv1q0)7s@_Wn6&xL^C zi`_hbHL0<3y2fn_Etbf#WJX@EcvP~zTDO93OaCh3hZ`aWY6$%orofzeqbNOI%FP(9 z=#BGFK?4^iiDV5&qzx&z`*w??1UhauN|u)1b%4k64zuv4_KjTs-*^Px^t4QuYC8ok zDVJFi* z$0^EtWYi5N0?mIX9O=2a zT=4vd26W)^R&Xr+tu-3#MuPE{X*prn)gjpg@{!&q&`%+GtmM;|PEK<+qSVy=q3h`vT$?|Aza={RhYc*1wv}$IJrW9=S)pTKEsA5kj zlf}<;TSvq@ID@VX094LhYe?SXR4SS(Xf`IFve0!LeB+U3RcF7m3I9m%K18L`74tFA zAf$6%PwEpO(~6?dgdxTOdVTrI%&*ou){0?%{JIs=3TgJ8neB_n7sgXKloUzu_^?zB zsOnaVSBY;IMsWp6OuyAoYHv=(2Tf1be)%$GMky?R%AUe`1wxF15R<&@&j!GV8NqP7 zuFl8m+3HFw^9^gW>IF4Y9YILaPo#eB=rn|+`?vUEKoWh-dhKiT&*s>FLa1`p4bjV%E#l z_XK#Gv#2c07GzJ23(CumU)aA|b*yLvYd1fc-w~^ZPER}P>bfGO0J>y`+U?{{BZAk| z>&|I31aEiAx=^uC&%r>!NgKoObj1>_dCoE>kNb%5;SgsJb=o^pA}S#9r*yT61eT_f zIjtV;(r!s1*Ke9k-I!%%tIu|~P@sd^sIQtzpic12|U6E6_ER6gt z_add$OQ{av+ve)%qn8Oxxr>d$T|X6V$gtUGIG6l~N0Zj?uX2!Ah=L8;A13229T||7^ zEfkSaL-wSB=T+`G?cL*6ced#gzNZRoj$4*PC+{enrKGH7cGs%*v0@LBmr-riiGwS4 zWkh)^LJ)Ri9;~-zWv1*xdAGtI@gsAOM~U8}k23LLk3SOU(vIgX$4ihTa{CDXnx$T* zw?!?(N@r|<%{o~>mg#RYU3-osj~i4*&@(9QEyUe+UE)8q&>UH);c@xoB5QBB#=0Ck)~c}U2&r?f^SJEH z2eZ*P(;YDGlgA-;Wt|8d>5v;R|6X=XY{6l&Hm!T^KNL4_cEQbJH-jlnGxrR>m8A>mp&mxDy0#qL6Ito>{e1*o0xNMpG93FnbCBg8_q;HJp3(y6XHA3{5O z;Ge4O36dT(D;9_!JS1FJagMB=J5M_aKfaRxqo=D?)r*HGAQ}1Q=hCgz#A(Yb3%~!+ z8ht)#lLZ(A(s3CxfO-T~iM8r? zscK(WdnY93rR~uh51JE2`-t&Z78<&yqN2M;NE9_1CholyBn%xA2T}aSVvU4LSt$^& z!v|Gq3qe~-_FaDeGI^xG$H>f69yH@tj`h$R{v02efuu61L;imTha?k%gC*GnHd3VQ)qdxCXSy zHCHt^h%+YFbV&-*^heog}?5 zu`u!BBBg=AibDByrnukkL$SQ6Wd3?Zrb4R7SBF*R(S|lv=_#40Kw3yd!ema>1|FTE zBa~X;TC)B~E>zbFck{TfCy1&1KeQxt+173~Qh9K-s|#+vGs%Bwyth{=ZCs0!^V9yy z9RmVnd(fP$y~S4{+lJCo>NH#TZtB8zCI*#+VS(5W#P?Xt?rGfo$wrt1&js_g-NF zc0bz}SHRs5M#N!3pW+VH_2(=WM^`txsv+!(vy2Q1Z@f!(_a0Kvgdj74E~>h3IatA! zag__yM{&WSwuqv`D}IFN3}p{Ar7YjGOVW#XE6hUkDAO!uY&24xf6uI~vUfX$>Q0U# zibj5hma*%`R|h@*7jUJ(o@8x!;F~U~__( zw|r#@U;HL{kfC01PQziin%UT^BzWwA$5P;geeJDDIH#pg=Bl@cl6S77{=Im9?G@Ae5@ zUH~Jk!yKjLlU7);b}&jao#*}-Ju$PNN*<3HkeR{Xl*+j4YEpo6DkYt^V=+t17}0ps zjwcC^m?2%&b0q`)u>^Yzs6~tbsM;5QFya#aeybu8Df!Fq9#Zrm7{Lc@ocU%681$d- z0&$*97!P)T>sn}*>Ox~%Bzl=;ZPiw>9L^)_NYjJG6YGLn5sJ)5Y}aHBr)7@>&$*F9 z2-OP2?hGxUXT{&ri$6@A`}~~Sqq!15v6q+j@?Cl{N9(D#x8lT0*mX(w!=|TLBwd+| z9BN$&hw~n`uCz+k%anOlnw7h4yBQUDaGitkBemuXDDJS)q#An^W5uROv$EwD=XpU# z??QJE4~d>Fz?HjZCn9_n%}<9Fi9PqqIDG3pbUTs+!^~e_p>3IRNC0UzWBcAG09Bv8 zf6T~)!)_;vZY&2VX%yyp5&?OI(fqbsPkN*UAEMO5)kiOpZW_r^i$qi(o075dWnj^n z!GS%6iNOI2o8f<_$BR-vM|G+1Li4kd@=;BaiB?F81FQ!^h*(t5B<}yFZgNOrxRj{r zudu*w)JWoF;qjfxP(TPFC3xlCB@sa$Qif7Aae_A!BKS~JB+StJiZRTFy*v2ivt5C` z84t^ja#yAeeJevyO1;g%x3ds3(pF$RPUp?}xuN8dURKyyA5s#|OvdBHfwy zCeJpViGpsQGHLO+H-+&Wm`JL1mMGeC&4!6p`9%E}quX^p^BTi2qiP~%rF)=MrxHdo zL7H}lCql=2_?*$6YH9Rzuk+9TntY{+L1A6d8606=GbOCE&yL7eWMTi0#McU|qIcak z#W<9T*I#1}(DX9V>vuZq&oZVKivDCP6=_8r2?*m$AvC9R%W`M~zgVttn;NE`{+kJ| za`JE*xEXwHE#*hRU>f|^(GSh>R`4sD>q7jr(jaQYUL5W~cc_|Mn`(A}GMT?&$&6xr z_<69^eXMI$t0R}+!zsI93jp@aqJ)lz$mvB82iL9SfUd?bsWD)~u3O)EMszCELv<{M z?6!v9FPfrnkmOz!1uWmVB;suVAM6?zeM{;hw+|i)BydE^S_mzT69Y&|~%3uS_|GQLusL zXA!z~Us?mSUT-o2#G=6>(WYVFl5oMm%kSTFKP4F;9Rogq$j0=l-WDWk=N>02Z-u)s zSgMu-O!&L{-TQ5fD?{%d;#&u#+tq8Z4&8eFIb)VSqC43Q5OXYf=xZ5j`fXzwu8K`L z;VKj7VC?EVLo}YKd^30Bhxu!K%0Z2VFs;zVVJ<3J|=9V7pi8!n~38 zADDWF)@QfUVYi3Wh{n*e2^hu~k*RUS4*PG49(iI5-G-Her!GY9DqngE_+)|$+rJ?t zALDD%PZ9(yyY;2SH5K|Y+#gtR^YUb0^OcI9^11x*M1ha#b~Uc#nAV_tvdvG_jW^Ie z?-hm~3a*L(+>%Hg`u;gfdm-|!jR%=^t4#+~)h#qzTe&z%sbBN-Ag}E|09g2aJ{Y1$ zgj@8>O8mIF{F?Fud6{gj^-Cx{O*hPUIt?ba)pRSNQ*ew=B$_7PtOXBIOxed6#|sXx zjOL#S*(&_F{{WnC@|WkIlqb+XAS2c^e=B~IH*@)~UWEnQ1X_JdPgvL)K|kKe#bX}r znD-DUIdv$?{X->QcNQP>KYLy8=n|LE9=jwnWy?kiAnQw>2v2 z#a$U_$VX5|QA`b}xc8wukJt3#sG(6!y7+I3wN2>%0EQ~2b|Fvep~Y4ROs0aOz5}lK zs=Gi|cx@r9lE=%}+wAfbP<{Qn;;JgXq_;7`L()nfJt`81e`DVjaw7ie!%#08ZC%3j z#a$f&vJt<)PmcAaa4HIWXkG~C5uq%|Ni?bW@mA!pw|kOWFj}0q6yKdcRw{vQF4O8$ z$RLeanH2mzxr%+*Z6ZV_Kcj7;x%A_OLKR{~JM2OK06v(pS8^F9S^rTMBYN6OObnm(6t=8GvtFbDNk zhcbXQWvECKUCML9y5U(BcxrqY%?K1rkUrbSJ2f|W{%pHoN*2!b79`U(H~#=c1C6cI z3i=iQ0Ch{(lqaIM>~ud4C|s^If^=PCsb>))H|o}9yB?*j+O?9`6=>H(XSTXeS52Gu&XADQ4gUZi7RR9ntEWa4{h@_Y z+ubS~Fs%V5)>ZW(mKkIbIuo%%a=@91P#Pn9xW;EDKww+Rtr`~`BQHcznET8wz+v0C)X@h*vRcb zCR*%CtvoyApe{q+#%I!5r~Ku5M`!tu<_mjB#Bs;0-YO`qIJi?lerE=6tgylK2b%c{ zR*U^BO1Lh>DmbVikPV3p4@%OamD-@?Wwq#De)9z0W*?+4_PF$s0BHC}#uWhq9-9uk zRFhhqLcE%0Ef81{YQl_Elep`WRE~F|`l!qtFf`<8@;Iy5{JZBEqqj>t$erhgLW=6- zaSSTE3IZwmvLyst0{qCDOU+4V;2s$vM+Lfa6;enP>4-a|3Vi|p064X(`5#3$x4)aQ zwZ@eWi>xYItkS?P=H$E}=Nk?z)%aVlY{}El!zNBPt|mYL_FWJ2qsjWGlziFdKQQ@c zO-rcnG%GD9%eR*|GF!Ez3{|8udV%DUCD?=ZYOFfuY&D!*+&Sruk8|3r{I%pS%n!^@ zIR0yXU*2gKdWC`0n?ca^ZEi~qI$4?|^)IA(B?eDLfmMteavS!*WgFwNn9RfoQ}c_= z7rKSUt*KpVlFXOVUQHz5SG>6NOS6*3BhTy;_D_auk2hourA<7HDIE8Oh&zkRkA(jK z!PfyPeVL>FYkpt;T>eyfPggos*O`AYsjI{ieMagSEJTE@W{qW}$W?f9>7`_5Dn zj7Ji8uK6t4@yi``YQYIcc3+#nTfB?=oBc#=3I703xar@cjMuw6P#T7!vQ+9ipilC3 z3z7%i^~RILn!~L6i}g=1+&s30sc)#x#z}3Nzui|1YF+|<%b$uPvG{OuPc*Mp(IvOP zx41NqP}6Qw>NJ>DSg8yY(C&>vLJcX?0T!4_nU%lhx1KashUdyg$4k1loZUkuyGjB` zShpgQmq)225aFsmSrZPdxPf`(U!9(I^52*(eA(tGt@R15q*+ql?jcuoBnc-{&JIE{{Wnw)U-`+&H6T*qYWm`OKViq(okfEMg)3|E3s}oXs2zf zTI6fJVE{QidrADp8cYJ#JAY9qE6CAD0Jh^`b44kTd0qs3`YqkNYe9|*a>G-}4+*}>}8yo|2KzwCiOjt(%s5k_g> zoA*{)o|~>&!vbGvcaUD%2dhQvLgClcsRxBd^dS4-GhYezU*~W9=HKQ|=YE-``Kr&# zHX0Odb0wGQtAAc-Zf*kdnlNW26-c27d2t;Nf-#f21S1`-=CJ;FdCOV0hTG3#-uzlY z4Yi~&NY>WsvD7n6kgX(n6w#iw*jFwQX_QAs{O|d>Cz~|=PA~B0m8WWYwXw6g)U9qV zo<~OF7`$!*yA@R&iQ1LJM2aPhVZv?V`gVt4u__x>{n7>XQ1O?N{?KZQHFwDtWZHAA z>M&{=Y}T6n$+y%I6hnBCGaHo*2NnoN8OKgX;bFc+jg$@Fx*9v!$L7x^eq4T1d8f?U z7n81Rqqn-#KO*hG&Q2dhBKQTO`t83aH z<~E@%@*9h3xW#(b*9@?Qh^r?APO9`Z4NNzfFCdE2DR(9y7Scc~LIWC8_Q+AlST!epjxo?eLhObQr2hcUQGR3j zvt9DWi>q1Nd0$WS4zq8gK>9wVZS|=d;u!8);3w5cmMBtal=5X%X8;D>f&A5)N93a& z?3By?a)U{ISMvAsSIR$`{$|$oxAMilnSGwOl=-Q6LLXjNn5 z>Cgr0deqgAQ(l7wBG{LhTk2di>EU?o5c7maLk1&qNIUQQRr~QKnM7L>pHz~%hfI>;;(@tVk`|0F+CKY52 z8H7xFt;N5rW-T<*$LXxCBNvXW2`X#el=)(nk8wTs2D+8xXxEKoJcu1>Q@P*9xI+S% z+uJ#YDU|#&5)_&p$7*|iIVL6gRsR4!^3iW@H2(lRYML$ImaJ}Kmq~zJ`GyGQMl#C7 z(vO&`GxS6DeL}UZGc!Y0Y!mKv-Jl7r&t6QE$vPL6m-F-UL&zFmm9%$;Z3|eQ-F16F z;?8SmL$SAss;FIy8iCST}!rx`a{PO<3(Cb5j~B(DG6T+6KF1@#BdT@*J4UB!q?ae0MdC zpCwqW)Ga8$a-kz{9Kwr~uxXa`{y8-lB*Mo@Afuw%%Nmxcma0D_9y zE*sUIq*py_Q?UE;EYs+WT4l|Z){ax_HuHxJ%j!_|qbrIw;*>jLrIpOjsl3;kkrG^7 z%GVMUQ5Y`As8yn<9sp#+O(}kcw*!(!LlaMhok#1!l^dNJHHp;GeiOeo6sYkgmf-@CQX~s|%6@El7Sr;|JsVE*CW9xJWb(n%V)EQ+G@8ol0PzgcboAMWG6vK;X2(sa zhA~CM@MLGiL1Vsc{Q2@7kL5-5I+f3rwU0Xai%qrDnr$i@h_4}rAOTCIli^m5lnq)F z+bEuRh>|+CepW(!pP5o7o$41z`9)I2{X%;EJB-u~otj%TT5PUDFDi;taZS7S#b0jz zPJUqiUHOyAdN<{t=9Z&r<$J#;U&*T2UEFEL`p;BHYP3^A8lI(2t=PR@ozvk!Uwe`-G`N=n#Eo|?6p*Ey#Gz7Mo+}}OPJS67-0Ax_q(ERcvR|0oF zY)+dX93XS%dOtjT&G~oduQW+{=Gz}BYm2Af87`ukY-jYnIasi8+;?5-4}Q6;%PD1% zkm~I*aN~^=bo-!x&Psk<+j(g}=N@fz+ZcSKYoo*dN=G3DB-5N4$MsPuXq}24x z%vz}894@+gc}`q+x-#$c-}0`_?|(IPy-FLuGWmu*KHl?0p4L(L8ekQ z5d!;@`FRpS>&bxrVR@7CT9uL zX?cx*i&SKlKh zQDOvd?b{;BVLRfk9{8&23IkJKxT>!rNoF-;`$w+$t1a^NvdFSr0=}Z|2UZK>2YgkV zSj*~160YQucIis@7^Efy?^^Ub)BAejmF|VOuPuqEztf7K{GJE+ntud^i2H}|$p$4$ z&itp=;f^Hcrrj2R(2`it<*?+_k&j)=BV030Ad*19bEi-M0-qtaSkx8c(=RTCVuh%B zG28Jyu-c>I^5m!ixVVlZ{JXzzZl?{PgiKm?jcnYnq?YBW_5*NJ{{REOQ9##;!q?LH`z)Qg3SnWT=s zw6aMof<`5zYOo*=g>s0Hev@uMdC%w1<@Ekf^G20n+@)uAKk#0GY+tl#PyOf7R0#L*W> zsKTrZSK=*SZ?lt#VJ0eRytRbyt(-? z=Z!bXQtFcGuXm$0Mel!}3mE?ZoL~I9wu_2f zA2i*_Q<|5kiO(>-Xf_9Jx*W^YZ(cxs<&GgzC(Qnb!?Ik8FHVYUyy(Ek=|MIzJzqaWvSRnXQSHb*K$Rs++IO(G=8rs746l`W z5twX)5x4&UoPzRov~k+Ka&QB=H?Ty8T&6#U^|fnEqjZ&PsV}&VEtT{DtM{ z^=(sEwYrXB1(uO^vL^*_rmhDnmK^{&W-MmfX9{?yoj))&tN#EbMdV*M=o+q@CB~y? ze{XYtr^#s=wYNW6WA%O}^#d=$C6 z7S;T@YHY6JySTWug};An7>MJHRkn8NR^!_(8KVfBX`U(MB!)_!L z1?Tur6H=RHvYdxk9AzfnHU9uPMgA1?ZwjjlCd8eu7rKS4P`jh~IfYyOpzZTWlQkkxH z0IQ2zb=|M*M!<15N&50(iB(9Tje~u9!hnNSyISqwdmJjdX%==zmsPZL7%GNK(&Yg) zA!|@7cQop8CegwiN;5RSrfq#k9}^3*3xBM3#@3P7TE*qsTSIx~M42qV-e~01BxQ&G zF{$`h=oph|;R+hAwR^9kL9cm`-$fG_jys(~S=C#mR6Rg6@EA!l=Ar;{OBN_2KCF7B zl5yxo%@}-$6~LNn(zO7yYSsWAwYX}x&*3%2D{Zby-SAQ4P@^5LP9kpWr?itcyu743zPPp@Kom^cPTl_4gG zLv{Niq}10Gzf~^3JpTYDbgv-k{#UU+Ub@$&()9RRSafL;>dtgU^_bkY!HES+C?|cW zGZ5J-{NnR3o9!l&RMH@670U?A9x9-*J@+FrqQt!VDQ|9Hjlhm1U`0y>9C{jWl1L9k z(k!iF)8*84X)Ud+tq66JNl!OFcv%SUTXJ3!Ln7VyId5gcg{po%peNc+j$<2^NBrWmmsj$% z%Lcb*;7ti4qPwpuc#ed3*yJ(h6J?uDadTpq_A7A>-G$6aEX8EEzq64;#c>k~Kfv2C zBkd_0^%;C**s#%WGI>ztQ3o+`|mTt~EFm0W9#s7K~v(Z;2&__+tYuOin=! zk5|ri(yY;m;vgr8G~c~PW9^V4o6#wMY6`ndfO6mqFcoj*73zLj6Cf3lu9q7RNX-w{ znMwi>jBg@*Y z)K@k#>b7fdWiy%Vp>7X(@QRCdKL~S0uX1ooLOj$9z0|CQUnC(?i=`UPo%}rb#&$Qlmb`K^Po=%CAkbfe_~9CNDw0^3Ubn!|1=8 z{{WO4M7j;OkNKge=nZResI}m}jv%ZqBd+QTijusP@~vr?!x*dT;*%mwdJtb{c?Vz7 z^!txHU0(TpHCw%3&wgY2^E}f=S}5*Jae&CdegzZ;mEO6h?F~;1#Cw4IosOFfjyS$? z{{WnT^G=(i{$^QeK2o$c8bW?w`G)RG7WF1bZl|-F85vqeF2JZ-j$BPELUSiUmyhx8 zW2wc$J|XSDky^)+W%3V}wGT9C^51GVx>cOh+|7A%4a<}Y&%!5OB-5d&;srAXT8M&2 zo0Tm+@_dUIouQk}+UJ(-P{F1r=1-Tb;q;3mBrwNw7>GzsLvbYokXwkaQC!)_AQ+8z zIA<5{0P-)e{{S$x?2LN5s}aVbsNlBwsmGWS z1D6~!t=|QHV@Ud!b!&NTr{CSAv)o+FKX*N} z3F=DGs04cDLH*hIS-vIiGH{KStdijt9*?cx{zUnY%et?We=fA0b4>FMiG?&v+v~YC z3#+L^m6F}yg;`eLfGyvK;LuYp7~%zWam43fo<;MlVoep_K-c1y-Uu6q?@)*^jK6I+()G+)gVb#xnk(BB?uSW9Tdt>#}} zOt?O&Sbi=ghxhOv_5Gy%uV%ojO|G8*032GrlHs=mParh+1~Eh8J9MrUQ)^oUJL;Nu zFZj;X`aTR*2-dc>rxi=4g3U;-qo<#oriA|hz~CumUzAq1NAnxW?fOE= zl{MQU#U0$5NInn()RJ;|{-DDz(pew;m&^DWd7K`QuK}yxkSW&YgKNwA3vu*`vD=pNN=Vga;G_55@91T+K6m z6aN4?RppP%-^;sg0^jnxQS$?fx$d6eYwHgY64TNUyeO?z-B>uO`&)F%vB;C;krMem zyuqa`Tvk9%^k5|4=4qJ-V|O<;6B4mrsz%hRx=Fo0j8ji={{Wm^@~mEP{Ls-ny&a{$ znDptTd9@ufYNAbR0v3~yk)x?m@h=w*$W&I8%H~&xXR`kQ&Q#y)F`^$W zSwZ`Ym(?{EniA5;1aiEx7ifS#3yPKKcA>~)JMNwu7G6{44K<9Tvx{qV)Gnc&;6uNrk}Rl9VD75b{{YDU0GLN%y{gghQ@0k=t8~T}mL$C7QDpXvW;&FYy|F+8>B@!A<-&vsyEu6oufpLsZ1mFpNKw_NCBqYi2FYwT#Th$(jreKZ!q~kUcR#nrrNBj zRglP+Hr#eRfgGd;z5tJy#FdNhU&`Cx&&yvr=zpIR{#t8#-<2%lp5oFdW`s1xNLnyX{7GF(mt z;kf5+$;*SF`qY$Qf&S0(<-9WPKVym|itNZUkIOI456sy!v(Xm=#lN!ukHb-8Ubi5qV5!wsPzNo@xs-_lV}a6lP0 zx2Jwzd9(9BUh>cUtB=axDQbGeIv3VGOT98HiI_FS%_MIyjaUX8hytUK-`_FifXY?_ zbhE}Ias%D}05JamHoWEL9ZSi#9$oyd^Bu+3hveJODC-t_wT0Rw?RgVNE5jrlWI;wI zwL(Qujx2DUJdYq)$1EZ%h?uIs?ZD)iQE*Nu$blOhvk3e+CWw<1j(h$3K<%IN!FcyAZg3E z2jxS7s>pm*`KRPvJIb-!&*c|e%?{<|`nB6BS*it0GN{h{!+J9NU_EU`Z+=&EfE z)!ihD?LcTqBV=l+sPU%bCkWdK%9-q>ZrcU$>?zae%bJNv^({Q!!04<&YLdM{@jrGX zC^YixZ64}tqoqKD>k)&q8dML%rcuJ%Y4yL8S|()FZdNt{905VG73$R79kN0+ylM1y z5ou_`C_bAQ5SPqkW`ZLSacHjhd7^IdL`V?cjI7N;$EMiyMn}E=M9u zk-&016mIk#hmJs&aoxQ(`dc}@TSp5ZppI@KiWAhWb_c+YhYEQvNft*b$)b%FnVy`P z+qwCl6N;eT24;{mfapN@*aPEG4{sb*KGM?U#PY^ll!T)@Nks@nK;NOLt$vIli9y^a z`?fRB(`td-9}(kBP=~p+4zk>#<-w~XhVD+>Y6U^?rGAVIgS54Y?jvbcfm)Vy*whWa zoCKv%*hH)8Ko)48oOj;7AH?AZvuQPyEN&XvfhB4V-W{=JB-%|n;@6GBk|;$5X+x4N zK-=q&`Nyxzch>y1t9hUEBhL-_fB9K1qiY10A_lpaP}OZ~Br60fLjM3)uQ?x(RoDQ; z{5E0|qDH}l)JfY@W4=nk6 z%J%mc7ef0@j_*&tzBL9I+2du7XHj1DH26hwIJoSA-@oF*bpjR%=hMILF9!1G=BJ$e zsiEt>Px9udmbw?3RSvagw$QT9%4_hJQqi8op&N9}X%lVU5H#~|tH(p?jzpT)gnasB zLo%q5Qi~A-=i&4HSXCS$Sj`ZSK&4LmeDPI78#pA2?050ST1!y1*p;Pz9>d&s!Ag+d zXmQ*Yn9`@I1C0f7q=KggkwNLm{GzQuZI3UWM5PU?rIwzo@*p$18Z$AV?Z1AV2Ydw5 zhN1EooupXq^sg%GPZ?UHjWXfT*ZF=5Qkhx5HbRF{^HV>TUVQ+xepAH)95JERbL{i*(+a-!Pa z?lxH`GxtB`VY=l z7TTtrX{BD=!v*`Y*}cSSI5fd}pswVaWw;_GDlK{L5wQ9b^B?k$^0-%Ay>tOUGtgz#@n8jz&?RIM``QUoVaNBuGHw6XF%1 zU55K~!X+WdusEW3pz>3z8BC8k^@|c*(xr*_J@N!Iq)ZoeMUp-ur=t)+@%y}RQW7bz zEqHdH%^V|#6`0DC`I8l^tDt`TV_|GG(TkbITFY+h>zG19qIu!{00ydm6ALXlK^sQTAn)% z{CZ)eT1#+?!;%qHYE*vJcIp0SAVV;MlVG9EC;|F={rMJPKArynoGU_~pTC#xrla($ zR0GrZEnLRb{XY@+w&M@%lO~5^uEkx7yA^gS{{a8g`icJlIo9Go$nP~f3V^zQ{YSxo zq;r2MTCy0mTl6Dgbn9Ol?l<azh^~G0?)!)MvR6=XFfa5TenZGg1I3)f|A{ho)N&O;ciWd4}E)jbml$qkWyegGO(Drz~nIRmQh7F?N@& zXrYN9cJ|2tguYApClqdMK&2S;sr*hftv#j8iARx9K9B}ERw2{K0xh}JDN#6AfG1fe6KFM=Em}!y#A9-sy(oof%rj~rz7&}au`L* zyxB@s8}fd;>%a4WnnkZ2cJEO0ZmBk!%WZuXt)w?sI)iWx9F_r`aETAYR<6Rizn0FM z^Cy))Q~b;GqfO=SBl%}R^BmfB_KOCuZ>!t9w@^K+o0arqx)Fj}K(#dig+Uu;yIaE| zD|b6d9vi-?H<)icrRH4@+eT~Ibsse8?%sv%wav`7cVXQ_HOgHeeoB?0PBb*_T)>va z$^&){<{e`BbtxNKmK{RjQYfB#h`m|Nr9-ZG`ARaBH!8l6?pCLt!}@&xK&^oM#M6aP|8MQ3`9$XxMv1D zRQe)+`Ni)b>Y9b$PhNdO8*8hJom|2_8CZzI8*>>~Qa9Ur_~w2LyEwVKlaKkyxxX$V{F}7XJe8$g zUHOJDFxe#6dWGbdmrU*()Dc`uB#t?N6@cQD+jG8T9E6srfCY7YsrhgDOXQtT%X**Y z{{ZKG=A)%~TSvaP(xlTgqZIe|H@7NUAhS2_<4~fkNZN#D@W*1@R=WstUZ1rt!+QLm>=~^YFqzQ9(43b9NC%%zLM2n8xlu(mi*<`f*aq?sN*<(Ah z`#;F!lgPU7=PlNsHN={1(`mMPE|Rf4vbBq}bKYF5u_uiWArK6H+YH2(g0I}?OSDCS z93L4D^fUs(Oz zk|mvriY1+>XzkGfGz=6nIfPD1K;ucX{{oneAWmOI^6t;;|p-&^c9tHX?<@U;)gH ziyE43kTSHx6k*BcL5TpG4*LO5yAa5&yD?r_#IP zt4!q3FxdMHRdA7rtpFYrAMN6E-nC)D`!1s5Rt{@U-w@+qBq7>h!_f`qWU-Pz-dxTm7Y}(^ zUEXD*JFz^A_pNsAw%Hm@qM>N?sQnpM+T`8aGRkBexGS#29)X26@H^sy^2<2h-6Fm9 zmROr~5+b_%*jN3$4UC3=GGAVR8Lg6?JsT*O=sRMHP>xMf=|e>B0q(Z3uKvcD@cA*~ zrH0Q?CxM#ewR#J2`oO}AO)WI-S5GG5++Cfh%+~b)cOPWp$Q0n|7k+H8T{g{~wGBL5L>|#B9d#nGj0N^ zf^z*pxwT-)!;BZxf0kZM@=xU^p=;$2%nQ9o$@d!GpDm^B{LC-3U3%8x2uY)n!kCHK zsKepz24#rH5bq_#&Bd2-(d2)Vkon~`O=t24@)JtX^!bk+U(=UBGoWb)v@c z{2@>mtwQ+bKOJ&&d=Wa7i}d&Nuk%Mw{F?H$pObV$Yogf2Znp7S+I%G;RiIc`s)jWj zkHz1uPHVH}rzcOR<2L;C@~`HnnzakbKQOF(tTo*WN|TVao<&O~iAnWUV`|BBKOXDw zhWkY3xPv{NxB@#ql)crwub|s$U-OZFkUFKiX`0(Dy6GZDYq;)D+q3jVS-~Qo5ak)5 zsZugJGa)K0GkV27)YbgEdFE|0)66%vZKUhX3P~loV9gs5QjS+{L-6UF=!*`EB?9=P z{&GX}Csh2Z@~)%i-5bkiS!;NmH9L7v`aD6;A5v5w5s2601HZAZ6D|MxS$Newz56)vv@-C%qdF4MamcO&L6D`H8w*u zx1-cq#JgOv05>Ky-;D(`CkX;4zoUyYAYLK)kD`7~PpkPOSp2)x?rijpY3}3K?Nyp) z)2x#4h~77Cxjc0~mq^73+|v$PlRPq&9{1ND;r{^n#;qSki^~$71vG6_&GFk=UFmwo z%$Mz^FEZCx$Jl^Gd`J}?4p|^-yt!@9@$hl%@mcTZ3lU2&Re%ww5vNCUx$2B*G601J_uEQqM{FI@cbwfvPHaEr{}lg^g< zrKg^B8z`)F`C07lZA>vW#P;!1iUpJ4RtMst+J^|LVG%KWKvf^WeQ%^`hVNDLY0=}X z5&6ensb8|M^?^`(bFeXqr{3`nJ%tkkBr{ zT>Y>Iaa_`8#!SiccJZ7?SI*XUT2_y7=KlaHYOuuKbG`h{^8NL=1Cyk4%EB9Re`a;# zA$a<#uq4oo-eTWQeZ|&H{`?+~tA92B04u!4-dWbPx6y9&)YYu+Y$Lh8UrydRCtpn( zRvd~aCKX~jc;=HFWeEc84rqX16#i&wT6da1C4VG5i=bJp-RoX!K3ll8l7B)eH34vu zyq>wJRP{h{Cr?hIgQj&^Z^8iiecS!6iw@akUQfFGyZ-<RpiP404{$r4Y!&+ z`+ujZjY=sw$qc1PjynU&u%u1^Ub0P2QU|XAfHD)w%p@I)@y>H^L5!pe(rmN*SRwP0Gw&_ zCz3qPKD+t1=07#*9!mVe)@*KJ)9!T0QALz6fF@|Ih@iW4pabIdlB~bHLS9}yqDKVHjWE|3FhaT z{D>JWx^tGz@=>Uc3XeDE1T+0X2AisUHgT~DDjsIliRy%XyLanP*$0r?xqt;bAXkud zQrdo?r0MnbJ`a!3X5ZC_kF^tZWF5XCz9~ap!8M$LSgRwbWOO`|L~f3UxHzf@l(qOq z#+&g6@2)C=mEGzWbKDQZY*i_lBr@;HJEpb#$MSU27hXE;kmQDrD=1y5 z)2>e!)EcvWC6#~9Q~qA-SKpd`Zu7R9JuN-8nc+*eV2ZLrhzPA}d)I7+QR*!8*#`g* zJ7{5oR0Bh|Yxs{$mM`ssL zU>omzn6tn8upm|Gup`@iq_?UDX83@p1QMVE4L*wCO5-ryl?NU?h)}z4({a-ZxJpM_ zaTTw^y}pc4(R22SAU+{LKdP9ebh0%mARkJP>AnS6b{ts~$8;alrYfh!Yw)CGcd9Kv zRdH3p5TCIaC#S%t_+eJvZSA5LcaWnOC1Hv+UUIi!DmDQ9rtCfOR7^LGEeO!Oxbjd` zEuG7?d-Rl7=S+bqUT)QQm&-n0U^{(I^nO035UF&!{+({cCi4FPmy!CEYiq!1PabC* zT2i(14wtD&ZEdtaFBu504?^%0!(X{-F)+Eqpity?De8DBP>`}&-$QcV;^JaQf4V)dpG~X-W zAk!#i^xMwAG=D90uglLm>i+J2el z?K;M2nA}>xuFL~UP;&u@4BOVER<$@{EYg_}AFQ99Kax6651A*JT;5%UEfm%qsRFPhsR2Ri25qJ|W5PN*+*!Oy)P>o6t@*|;{FUUd%kMw_ zSb6KslFQ~>OSv_PuQdrHrPaKOr_xnwBCT0Ksi*;o+>FJ{I0KV_jFKRMx0BUBHlUDx zS9x3W)AG~JzH-s*?)5>X>rhGNH`N&sEq<{l7GFwdqcX$cK|x%R-L7v2{{SBM zk$=uud1l|rf0#o^(lzZ{%$i5&oj&5i_glGZo4-bQM1@PZ9|2}8i%*A<8I6+qw&~<1 zIEK%f%5faM{y=>4w)g1={NbMpC-FkrL?!X^;|- zcEmtj-6GNwla7rp2|T&=Y45E;!&@ObM(5h$wQeEaAs<|m_MRRr>(&6;&XpD z7EFad1(X@sdbdIvhae5un8VqvqwC5}^nj~rthM>R2()s) zW9sRx`k7inInCvTp*#1&C#@WEyHdF;B^kr&aFu%&H3`^X=3LFMxidn1KV>%%xEC>Z zLxivlZlqUWz#n%SkP%Hw-OQr=VTl(ioWm)(>z4AV7n=sFz)TTp!6qroiEsYTOsi_kWvM;W zZT@qAJKIN|F6{K$#|WtRrXm&?;gRv)E1ldz3X1Ck=YJQaEl3Sxu;|vF`x5pdPPd0! z^T}&!vkYAhhS+C~7CTiQJ`oD#0&UxinjyBV##rctGA91cc}_BKEK{hrCxAMo)!N?5 z?lp!|GiC6@_#|ntLPj=9CW>@07#D#Xz*Q_k1hNpF*GRuHXH?juAVIko#oYTOErxd4 zKZh5b+ey7TUi;;RTRx7q*u5D-)86@op)2%Dr&;uXA2*nBu_ftISFKm0Q?u1s_Ip#s zrRLOP$91*nGauC~#fIw$FGYmO<8rk@*Z)D+WJa*`AKit$cDELY_8EJQzP>kn76 zy1pS^hn&Gja}%zc4)$FrK^D3urH--7DO;{{^vSKDf=Lc122C zR`Up7^}czDx=UFh8rNrs($R{Cc(ssNkL9*4jt6}YnNMUn*p(?ICp*K&a64{5uY0d~ zcO|!-lyI{D%}QH?EeD`WFJ5ZMVU%UI#uOY9~OGKC3tR5bX zymu9yzNh$ues``o^$hh7HhH>kSbAtdIp8RtIcE?eO#&j|GexKmEE1EcZ(~vP^4*b? z#U0sjkIQD^ba`;L`ai$11fCC_EctGaKtAnFq()lLjBj0hI08nfLE^#q{ft^f>h@c| zO-7!&Pt<8}L{4y_M>+DnUe?qsKp1ZSeT;vtLz*HS1gNn&H(E{&;?t<_#cbX=tPSo- z{Qi(p+vLJY8BvGxZx!AAE=t)@gI#8xA*Fw0w>!iu>-XwvY*j zrR#_KC(+QoLDX=U#3X58Kw4z<6pm98u$ z3FpDGBDaj@1Zk8TzQN8#3^VTQSw1!AJOlJ`V}t4VwVn25gJMHT7E`-&ZaAC)#*T#1 zs(nVv%eQti1$}G1IW)&gu}!6&bMO+ylN8>sZ@jvV)J4p~%M1|D4k4wyD7vPElUNfz1* zfP{uFDmwzEg&KGBT|2$}%->fD3=?q2$A8lw?S7$ug8s}J8#^4a7J^*I!YK0wM zJ+N?plVq7-n7O1*(9ETlx|z@GB9e2bbYuLmx8vJXRvV%B=x7k|c+y@mlt+1(B zn|*_EW=r6J&;r{YD(Q8stbGMssWqy`B(68!hzl4_T3IDf?J_!PF0J#IgylXVW~bNs zfEJd=#r}s^3c7OuKBJ#b%mklPTr)$%;E z{bJOC&*|Fpv!O0Xj~x|#v?Rz#SCtgVzT+yvHwotA*b?}HaLR^P&ev-neynxc?p0@= zzV+v<)SxLqUcEKm4B)hTkg4Rq>hNjO^sOukwlkscI?&;<{KIK^7H`$1g zX=2|_>a`|QWsYP|*fxM7_9Jtu7GAYXnvOsA)FD~-JsI$NNn@b!_rCo5P0h?Qr$pV> ztUf%(lHwL~d!`U##N(?K68R|Y$3mR)K}7nd)mRZykqqV|mlD8f?VX(vcgm+KD}&G& zHS%`R%8$NlT+V*ajTq}^OA617?jQ;e1K*P!B= zF|Dfj7l}&npKdDoCl7yy1%0csVz%v*9i#T?8$U{-=+`8?DDMev; z_Eu2M8HEP+5|&t~KEp>Nr>T(VRv_Y70!{@zW!J9Kw}_lH9|cz;PEoKGDC3h-bC`SJ z-~9FLl_rf{@=>dJDJOE<#L2|!S(Q*1NOr5cA9s~+y^Wm=S>~gU-Dxt5sd*E;#+UMV zwF>%Xf~$|C5{|BDLb=)sPLAJP|D@J1d~CFsr52h=xRp`;+I+NhilNTTR*7Ht{cgFD z6WJEs!Su_Lf7D4o+(T35jUo*UlO9S+p1O;vG_cY5){HLyd4jg#iIrurxZG>;$dxeI z%bqtV13SI~@pr^~P9d5gI_f}iHO`iKTdUAqzcg+Cs1&y&RED|@L0^v{!R`y;D>YbQ zjpSLc-$KKgGYl+zF!N**ZPS)AKn1ZPMJIOefEw)6!%0qk5pILc+HVRm$L-`!U7Hu8 zSm$Y0q|y(90o099^)tXL@^!82zTHc_?R$s%4wElj$Oc6oQqNt-?w3k{7ACAYj#$8G zrFO_Z>6=Ms$1-<|ztSS**Wq+q+K~jFpX-}+eP2=-eTIQ$D4;txOmx3Q(#Z$-84cr!oY6MRx@Jq=TzCw-F8W78JCRyyB|_~e6b~QXNY}+uxv-CwjLNsWO23j zinSDeh$LB-Q^(Bzxe$)&kP6hO!o4` zj^~1PeADXj0vtC3(apHsEtG2++I4L2+x%Qj+TQw-_RMLjMMlQ-lH@_Z%dh!&=pPMI z)eizdz%jcwgZjItmD~0M9|P5Cn`>h>zLL#&>r-BQD&(!|0-|R68qqgSOs<|=6u2|Q z={nIo37rPWsaR>m*ReeVly7!?L3nY)4C#3^NrguM^#J?Eqdk~gGjl< zw5#1fmM?RCD4#o)ryI6Z=@2@1(0On@i)l!;A;lfy;(BrAmO-iF)@>N&To$w~pRM_% zbP{h6ou^B?Ys3WpyPaRMrssc11a=A&Rz`j%5j@(64t2Trc*T$8^TQGzN;7An3*SSL z*a(eXVeH6+!p&|2bgCVrmkLX*CW%|7(auxMtaL5==zOyvZba~0%`2Z`U|4A5Z9y8* zySg8cX<@F?y@oq50)>#8onL|nF_9iItLK@vKGMhauP8<`Cyu_C(I}T|$R*j+b>*v^ zxPoqoGf$dParcBzQ@>%+K)1t-dWWj9&PH%sskOU9`H&uWWPf`4ECpSeZ$i`x*Q4_% z^53Ulv*peP0EajCkMB@jB-p8ALC6&&ie4n~BO)Flusc|TJ6a@e^Lc(_nvm0f`l1V- z&y%j@X^%;kdjVwO%cYrM+m#@BnLffy^qKV+ZI|p}5^*a&X?lupx2sOl@)zF%Zz?^B zXi?Z9j4pzPczZ>Wb~X zIx@)|GrArrGh9ZGP8{;OavH^&)icDmuqwnjZ&^%jhAj(@tb2--bu~P<@zN07de>qa zM%tn|!?hef)p(GL46^y`_KvAbo28%Umy!ChpD7z|5ksP>RMB9o_VMl0d9#|&WgPd2 zCzxT&^!1GGtE2nt63|lE+ig#aE3f7fR9*^p-dj;Pnn|=mj4!wg2Xo z!Xu5RfSV)}zt3K)Z1L2A_=@X=JgAS*`nTLtoOZEWU92GTh1>|3!!-oEO?;B$6|2k1 zz_W&3Ab9V$Z34{4VAfg*x7`WIK4*j`ZWA-Syb(|8siRK(dK-?}9zgMV?Am=0jwI5Z1IMP5gG`(G>0`t>1A530q!nv5I9bBh5 zrpAX7P|^zx+fzJf>1lXL@LDOVv=rrW*-g?{lFfOK+H@|b^rJr^6~2RqNuCQ+VUH+G z=86cOfx`mrmpPE2gL&Md4&RGs?x&5Fsa+&aeU=@#bZDD8eqR9Vkf8rY{}>Q*hvPoX zhi54O_NS;~Z!Z*Mw@X(?TdHXlwBf24s@3gxl@~60o4wgos3*nT`L3P*$l(f(gd&Sc z&^xNVn3)n^6aCq@RBf%Y|B8FG7%ttMXUS{Cs@Q3XWss#a%>espm#0{HUo3nhymjyL zmSWE)bVIO0`jJCtasa5d>!VY}wkdbyLLJg;Tj;HmNHWUg3}MgdVdszjfhu%_fXcw? z2O%EU5Oa$E@VbR1JssgeULLeoB<&B3Rz9d)XZp_nVyEyH?>WoZl`nOxZc?i9s`6OA zcEY;p&N}|8#DX{N4L#;5&h-=`$<0rq{*`3EOmFAx2>5zBn@js>{i26iD$<$Bc=Od$ z%-Nm)7>;}|Oc+5=Bj`M>8C0kpp>3X3bY!$VkkwQQ7wiT7e$b z7nW#$!8M?7EA8_;F`n>JxqqGA-JMVIz4ngq&pD0jk5|N2eyLx1T0%e2tUvlg{0^tD z^t%5)y!F3fSWy4wQ(|Um{g7aRDTU)Dr)f{M7M#tM)~f`Uu6Hg{=EGX940q?(g!r{4 ztAqhJ_5x;?GrPjOoO0V9taaz6D0;#nVUOEi+4*YE01?W8NwC3INI^a zDa|ZXJFz8aYojTtMVw zE|n!ni-*yk(i~{XOsGH2iV=vSW_cy{0>5+TN&$}Hx$`%_LI0i7#YzLK_{>!}zjw89 zjfB*C5aj}oCN(4@lFg^qn3{aP6U0Lu`%mkTCWkY?)NgYt<09?3|N9yg9M)Tgyc;5v`Ki(6EtwN*rQlcgjsu- z+^n{nuwp)%^!33Nl52HCkqMot)cU1OnL@YVk324QpI*Eu(J65sDjeeA2H8Y+$_zxC zJ&WZcKd&Gg@z7*Wd$`CHt5wiU0eTG3EU&JcIj(DMqjhR^>PqPstZTmi z;(+>MQoX3}g*eO9AHU}7LZ{|Bg({$&44ppXJpjL&Z5QMp-+Vt?k$h2nmdBVPH{2;E zt`PlBhb6P=e)_$=b-_r=2P{5PuQEq{8ig=p`4C|RcpccpU9_pWfCC+ol8!C^`^tog zA@X{{&!;HoMKWET7{xii-=KCHA~~5&VXW_ev30i`GCvi@`IX&xXQP43%p1TITYOF(aYfDz_EBb!eS9&5p3a< z5@!A^H?`a1VUJ5k=`nhV1FX=@&rj9BN+_7uwDZV#&n(a{(uPxBJl4}O0- z^NIgfNGLKQSVD3AxJI-^e)t?~ZhuP?sB)y1fAoYDnFT3FJZm9kZu_LPZuHwzYD?NB z@f+c5qOtVx5W;52vu=IVg*_t*&`F?OAUgE>*A@)O6vA%N3w+Q~}>+ z(?t|M5jx;JBhQZz?)iDs3+x2w5G5oUqFk|26_e=iKPET?+mHQubp(91G?QHJMHtI+ z81+0J7;2W;cgr=$9<T26-8^S^Y{5vUoS!&qB zJbtsNdeZ4KoWIw$_=!(^K|}h)_x$hIeh%m?C{Vxz@NvWB(QblfF9rG0%gpwg%a?sx zM+~qsP@UvPZg3*KSx2gQGQ9>DmxkHp6aO;LUnP|p>TWCyY+S=3;l9oi<}G72Kb~}W z{ZW#7Rbb|EU!2r*lhcPqY3`IDzS=o&-ZeJHt(aGOE!GpW|Q&#SX7MeZh(`=Yvgg z7le+4Z6qatZwv2#0Ti`!CqS|0`L&UqM8)eC*Mx}&stM^q=`a%gp47V;ldQ4JhxA&N zHNZ{gbgqcpIe~IGC~bz7`Fp^M3Li+q{IXt*t_za$eiN z)Q?3ufdydaEH1t}>!irgPcAOs2+cFnm$szvu|&YQrY*KXIR8@7d=kyw?(RI-*6`yE z;uX`W=krM`S)}vF%`$`4ql}>sx&`|a3PA=i$sbZPh_6+DbA!euEhR}9^S$>!4EP+U zGExkG(H+iMu5exvb>Use#~&8t7yI2Nq+hRPd%VqYr~gy;bZb%>J66hpy&0FXMu2Rl ztYKC4>b1!5v4>?f10FTEW}fBR*1nN%`7+7g^aRlt#=qhg$hFNf;T@0E+UfC~A5y>q z9kUQD2y3(VAD+A|$iP0!7$X?1OV%%`s{mSJB8MGhoFki6=F!*NDhB{_N92|V0Pcu@i2SKVOX4GOAOb9ag+N-@z^E-~(j z4ina(d-Ter`5D$1(}}U(1YFmf;*r zSH;1ASTMcg8BuuOzOb<-N>QRXO5*Hg(!%hsKRg@OqZJf~j0O`1*a z20L+`=;~q=eeZ46q%W&Z-&Y%Rvv$5yYfawgUuPT6#{G^mcYfB1%HUMAw3d~Nr8Yym z+HxnX-7;`fdn9L~p5|-)aPErc!u-?Qd!t6KzUN7%orD6RLawQX@>@G6?qk(-W3}kr zEYR6Re;95ZH@AQr!8-13$-V}uO$Cmh9g|i03e_8r6L?Tme}v|lRnXpqCmgB1LN9hf zSO47#=CM6~tW^qVB~2#bz)+1K4rmU^6782N*n)Uo7EG?Koj%A9Uu{@jJEU3BkkO?| zeRp(J|5f_CkmGm$3>8OVtIy@1N1^(_FqyGVJ&^aY-g#{tTwNRFF(PPbb@((MRP*LV?B7)>()-P|3D2 ztn=#5d7(>3z~P-(n|}t=54?asNK*1qK9vX1u|pFW+nutt9?BOBBm(jSO?Qzioan1u zl;y|EX4;Fr%vHpO2uzki2Bq9d@vKK~zUoCekyheEVc}hP(dj@m|BS%IaLkL9Cc1EL z_)OO)eG#_JE#>bqGAuwgxd=#L#o$sw^377e0Tao}%>mS{v~Fw9^@s8E^;GGEsGS_k zd+fyO_;xBQLa=Jr6j602z&x|P{>}-zK3<}V1}KN6Rqh#B2J`Da%+`oP=X~qZ@E>tX ziagT>GH$q6npu`nI8ZNvavP02$_!hDqM88=f+Sqb+Xd|ti`8L?-9z>3`C5FQqu5l` zM66rwf_MV*Mn_B&72E$?jqp4o;1Pc zYeAz0%YPNJW&t9O6@?}1t7e}_=JN^u*YCTe-ZP~m7_a^LInt&pS-Z~qRSVAyup@ME zv36#L!G#IH2aymKcqYntAQ`q!g3a7Xu`8ac*YQbZ?7IvSgAq2ZDZz&kN>QG5b-zoKNi4v1M z^D@%e7>MsoaOK@-($v(NTp_riH(XTWsp9*~ zs^CHAN2J*Dfb6L!Ufp}Fn2i7MU|<*Y{$BguR>_-gjI(c3ERges~o9?(~I!NcGn-lxEMT*AZ{7IjtghMyYs# zH0sg0qQB^B&i!~@MRnx7RzUOQU6DISnux~$ZF&6#e!tD5AOS8mDe{*pwe_`t_MM38 z_j6d=*ZLe%)s|+#t80;Zmip1U^N8Ju@6?Id(I0wANZVAm7ZoBu`{nO-&fF6?$AEM0 zeDB_PmBP02X&J8KC96`Bo%eJE+DU#VTdR93Jeyk6p3FSwt#cv>miMo=YD5WlkIwu5 z%dNW$y9)!ITujMNY9UKZFmIAkx;NfJhs?sdX(a2GyXhi6IugVF#Pq!Fd;&^0Wz%X**DX?Nd8+>Eg)`$H>EXbUCOC#b91pn$Ts#hVHYgT5%3r4%LBKXx#-A zs3z?HO8@Q-TLJJI6=EZA6VAs7V$^v}@w2oinfw{sRj0y={>9w+&+B@d+?iRmw#6H? zE=p(%mA5;YlLU6dK`$jew8w-7BLk_B0C-)LOepWxp0*k6edp+@41?rvdg8vdwRaX; zEL5O(uf#XwwT*<>Z0r-=>1vIwKQ5##4m9RclcB5ye<}%k;DDA}Q5mNFq#mShw9;GJ z=y6@rP;+21Qcdl#EZ-9uXA`Vb$q8-at2YZde4aP=jibxA=Yc}aoqsZ>SfL7gQ_GX* zed;5@>CNqNlCyfN?T~0RB(x+@)X%1hSHLu}65{|OB-iNmz90h{d$ROc{00??1_NFX zjE3UKSC!=}XIwPRk{v_lfI1I+F5G9N#mGit7igGP$?}vK(id)%mb#)7d z#tB;)rlZ6W3*6at$Wz49<6bpp`3*h0q8-ugLmYc?g;)t*T`eAZL*&e4vkTOr8^&))-vto1FRnP=G7{9x zGBVgiU^D+l%W(K^GD8pH`n_yq>H}Jvfuh5<7BbCu_xf;|wiPRl3Dd_Y-p0j-HTK$@ zhiP+oy)n?Im+g_gtT#@==P=Ar|M0V4>-3hH;Xgbv2aVC*t!g`C++Xwzil8bF7l$jH zJDs23{Bd@&JufI!Y?V%y&M)C%I0^L6p3as?5=!nSZ**7Fyj23aw?!?u!VcU_*D_oj zH?-@AwetA*dzMjO>fwV$9YO5!YAcWqf89`y@5TBDm#%0Jy}5xC>khMkoiR zEdHCdvQgq@J?x-Vx5zd(iReXI!+Bw<;WEON)G%swDi_1ck5_HeMvIE_Ds?KVW`s zGmM@y0?C%+>+_$B{(gu}_EC9p5MT!aA1)wazdm+%yy=d~bMY~{&3q0wi9GGNY=B}X zA&T~^b{-6i2O!^CYlH_|{>0DBBvIRX#-Z@{9uk<+$roNwq%vPsWy2$erDXmLJAtga zPq(4oS@EK0UPTcPl+7VRaM?CtVX!x7WeQ$U;?OnQP3(CiML^{+8q!(tgrj8PqxP$Ak9oe|S5V?MM7gQZ`36wTk+WH>()l z8!FzDAgE`2$V*qey33MfJA)6vJi`0-W~O}=K{pug)5ERFSua8F+6bMb9)%X+N;+Oi zV?-C*a(8gsyXklpB~+8-44oT8JZ_g3w^NF;Yb`rqG0wF}MpAlS2|D<4nss$^%-0UfHUaL~-TKP0@^)po`owM&2)Mf>rzaWtxGD!$H zpO8C{J1!7Y-jofRTe+*^C5gxfF{Th1wVDV3p61h|Ip0lhu13r*$@O0I@jfp9Fl$^K zIbx`kUM55(7#dV3Q$OlTjG!5Ts={X#zi?R?RBO1sZOxC_XthXzxCnQjGm|~&E4=fI zL0ad+AkqqDbszw#eyXR>=s8)IUAZ4~pFBbFi;;x7o#Q*D{e!a%g#%Qn;$0Zn$)Mi; z0Jhed8<_9i)^Ica#K!V@j>V$O{YIJNh<;Fa%DwS>yNBXrj{$p<@IKVcb1df0KVEk+ zFjZU+Bd1d}<*m4_rqQ@^Zqt&9;?=J3H8a-gH_D1n!P}52OMn3a1DOyksT&~2&#Alf z1Wl4i&q~5yeBH-eh76$5cL0Regn#!7#6$7UXyW zuUU5?DM9U_0~!+gIw=f~utOypNyW9b^tNzb^-mTe^Md-&AnwVNmnI6e-(=p=I)sB$ zB$8c9v^sMn`I9SC*Q8>Ci9=hx7e@2Ucrh3L)}9AP?RL8E>yG-*DtS46Z|2LOz4DxD z4{Knfm8Dl-zF8W(o*O3J&6JPtVp_kp;dUn<($0_j>&Wdx5_gb#_H+REf0sH*E4 z=OEm`DVq5w{|N)$QnS%3xUDRNB)Rf~H|AkOjpTlQ5MaP){Tfj@6y(QTX@0Krr&bwx zq3rn)!&dNyu9(~;SH@~J9yB(svwKsG{+m~p$$!zAx<=1QG1|Zf(|6U`jCm&)GRPC2 z_fM;E2seeQ6J9)^HL+2@FOvO?K~#WGR-Ab(_93I|qu&4U7E^sRCUTg&Ei%%>l?DGu z{fVz!^=xT_z%xbJs5McQ6dk+E6%3B-2C^8!k|ys@mR4Gv^-LLjC68`=UnXVPVMT># zTA+!?_SvBd77!qO-gFm83}UX%^`%7c8czrwb`ul*%gdp{7k?L8Zcvzc=7+i05IXcTT=atPkE*;{KGbv$16>Lz>=7F@NfEa-WH z`rV80Qv7jMTy?NQvt`wN>2uPpC*gZOJXxvBr1R_{BjKNM0G=tK_Q%);*zK;u>B@V$ z2chJ9uy|*Ox0maWgql7nO2co@orbmPYpjb`3sb@454>SanHgWKMh&QeXx>Ye*$ zK4Em=M+Hr_W;oZM&HVQr7EkP_iPEGj*!4&s-n@At;XRZ7`8FEYjw#Ji7QO5N%+nD+ zI1DjbdF|eOg9y_({S+>3o=&sWH?*fJX_CaO36eb3K0899{%qu7brbicXso33!+)TB z0psN&c)^{?@`=Dn?}T^ls%N6-{4mUDl787Op`|>^^fCB2TMRFly;h~fAR4~UjspaL zA$K$o1nVTJIYf-R3Kdo=ZhI*9?P_kFh#Dqun%L%Q@-_u^Yc=?a){IyEu{)a5+*`qkHf=ZW`ofhxZ&#qJ`mx)4pqD!4K676m}3EfeFDyF$!M=%g1 z+1LX9@&W-HubHd5wD4k`HEP%_7XtF1E?RZuIf^i{ho55+So?hvV1nlNjs}M3pRQW; zFGUaEY|qvyaZ}|c_y9AWDd&A1Sy@k20p}Vv<`LLEYz2x2ce3n#X@E$*f4YFU7R>3$ zYkr5?MycIXszQEb@h@p(jzoHE8j1VpKh~lvN1xbhEcDj+=YkzcC6B1n*W&KQE&fYr zX1F=aj`2=$v&IBh)N_pZSQsoEv>BRGD$w68IGO|2d5j}O(Ty^+!PN4p-y|6yo1Jc& z1AEB@<>uYW@HQv`Y@lVtzciZLHPQa{!nSQL`jXuAs!2zT5sJ;073)Vk0<$~oa z7vqN--M1Ta-2!Ho1+8TgzAWAC^Db+}O0D$$+^YMja*SaWjceV?}NLsc>` zt09d0iCY3{{rfcC0U@q+s|O5ZNq1ExsR10Luq$|b@QK=|+jZC-J;}B&b+TI=2tFle zURW)?XTO)+g8uzX&%)TjJi_`{Xe)R&iu|w9g|bJzznJ9b7g`iwuI#z6J4kpQgA~+l zZ%R$H5%f?f)F78qEW_abZ0mYC{^5o^rE7YL^DpA(+0$-W!6NrM7wm!A+`Mc3ioHU{ zLPhRtVdR~?krZaFSDZsqt4dBTM!X^2nO&!Bdo?<+g#F_t&o_)Wzd?Nz%|sNC>lXNXLNY&D-~J6s=8&?0rd`GGGu&aLkH< zb`mw;g<)xp78NE?g^&9nXYyy<`D0M`49xC1 zbVeDW4ajJ5$ZNOU?-RSlPU5v#FxGU8`bSprFduUInWh51B7=%-?6#&!X7d}Qf|)T6 z)azpfGrK5=COFnwQ{oI}!9S3FxWAwbgXc@#c`S_WH5b0=X7Qng2Usw5PJS7WvSkz<4hRd`hoCx9Y<(@by5twj7p&L`uRjvDFKwBB zU4QDVkP{mU5Fec`R{SWQM~8R=bQjOcnvJ@#em)=Oz#*A6kWX1MR1YEfKwa08fbI zpTU}qewC_gbe|>i2|R0z;hk^$>kpdc6+>pbQzd0RU&E;Q1@`NUWaNIlHT#Q$8->HM z`}@AapqUwKc%CwU6ItoUFE%!79K)ZlpA1lrAtKio)1$vJv>Whn?$Ps%dXEp_KZ>*y z6r`MgpV@0hl6t61^C0WgpLC+_r{M7mpXWSV-yBVaSwwBadLlMN%?J3FUj=VF-*ovV zHD@^Y!gN8-=9ZLP)={>HI?9Ui9S#~JQfT6i=2BZBAothP zb~eF{g$5radB3e=9Q^%L`WnJOvHgzksMcBAm)-0h!J=~l9p(>zTl#Nc2RQ|LSP`NIJ$H`;?3w>{@Sy1dF^4M<7MGZoQ;jVu4VTGzarj?7Y_=-32_OpJLz`eiPhpjNr)MTwn&P%cVORN#p8mKF_-?I*RV3 zOgQ_j%h$#IoTfDGv6DUVul~$zTEU% zyX_tS^2fAcmY+Y<<6SwcpxH(%CqR|}vTkKI*274*dTNuJgv5Y_9q6I8| zr&YGgd4y`3{m0fB>=easuqPXfSDn#v_8{@Xv~!&M+~c={lGd4# z3}<#1WvnNT=F0w)^R&j6{<}ogH!IX{Htkjz3>s-l53kO%1#}Y@w$~bUcJ$Q)(z#(x zn?Vb^9^Ri^3pU?Zrqm;R#dPU^hA=G_k7#bvvzZkEzD&-CkQ}K_7B_S+#e`p-)nTY1 zOke%*$ZsIRa`Ntb&Ct5wm=Xzlg%Oz?K|a_J?5lxwrOlI=k;I0sOv_2ZRITuRhL+iUu^4Q7=Yv%qzwR%q-vC?v4*gWDhzo_~di(i_ z0s=reD(xE1whYsUytg*wsjq5MkY>41Q0r7^O{wIq&5WI+!*z8tNOEtix{UIZC!Wz~ zJnzmpHBE$!)(1oFLD{wH_TP%QcVeNiW^5~p*HdC}1&nxM_=3l_+eU6-e z)@*pI>Ywyfh!|U*{h9CC1GE2Xa1nXI!p5p3mj9BH|Chnrrf$v!AE6)+cgd+Z@PaX& z;9NRba6SKXt|&cXBn>-1WPfm;ck%=sy^%@8X|h~U2vh#j{!go)FOxgAav*T*BJ9v4 zfyKPjYY2}wNmp9AP5XYC>egqTw-2P$G;T=B0Cpk*z`B>b{5*RhPs)ny41Go0&}daY zBJpY9*1&4KF*X%HfTwwofPnAA-_^8NY7p~-{o;0DhzH9*Be#_W=L=u(+RJI1lb}f& zy_(m}UTi+y0dbP^O{S7l+o?qEW(^a&{3?nh?;HEWCY#*BzRQXv7YF5HOtf*IamVo4 zORIK0zQeoAW5Kh`!zJ&b6*(T}Y+rbz-3&cXN_T&1L}DP=@rE-#FG%Kf ze=bT;p*cU$Uha`#P;82B2z8eD*l^~z@q2b$BzUS1e8d{F#MsBMetmE;B+>` zKyxo6-Wv$R+KTnpPEl*z6&sqF_mMY|mQi0;l2UuU6tv=0V7*=cwza~}&X8wFWho#Q zu?B}9$aUhjJL2z{Fr-zn6AR6!ZZy(z+1im40`uYo3ioyxo(q`wCgMAmvSs{`d#l9c z4xHzuKq7Lomnd|6nS9pVFc_i3uy;yWHJn-d$LHSG!C5vw?Xy@wx((Uqg(yItDfDnv z{e?+}39F)#BK)^c|Ez_6F@65qdDTPXQu?FAy>G5>A8Tn%nu9|!buES4y96ZZizF6i zAa7fdcA8vJsk(nq)qi{EyNenejlKJh;i%2^R||rBjOP(@_l&j@w@xR{sW|leZ$?;3 zD|7tR$O<3s9MG*j_s7XYJ1UNcvmTZb#HD zWBd-AU)zqn1?zJ8Zd7Kwgs|fM3w8B>_V;a^NJs?7o}SxXfRC5AydIi5OO;8K&#Exy z-8sT1I>B7G{X#}=E{2kv!6a>m|ANIH+R_?H_IC(Uga!wA+JTpS;ELr-P2m__zX;M^ zhhdIi+Al*1Dz**7xeWAr-n`)J@Jg>Ko`5u3Y5_9?WKhAMCO18WA2OwORuT^;O9(F= zoo)$nMYvmxZ#sniZD27UN@Afs?8H7X^O>TAZimpgO7+yDdEwcL2#U00th)qk2}(oQ z;yPQp7uzD_0GzDx4}*7WIg56!epajRuYD~K&6DJwNFyW6t<LycBB&slL;^(@_Q17(tEuSJr%m zk;bDh?wQ5@NV|b58+BH;k|+g`Eiuk5l_ttFz++HGc;lD0-|jDm(yXt(S>ZRk2Gdja zuhBmmOB}z<|6B?zEKLw9iQ7pY^JNC(k&y9V3Gq9PlAnx|woY)Q8Q~q<8-OkEOt9Pr z>>vwtxxL`QS6JEp46o;=Yc4W`(Qb8fjYGk2fNhl{KEeDYl!mcrY9v}gz6-R^F6NuD zTjz?E-0d?!yaQ{N3VOgRt8wiRc^mB4XQTh&T@-QlZd99Z&szL-lp}t>>lPwBgofrWOrc)0yk_-x% zvM5k4;hDW4m;CN&tlOmZ_}u{DVxO_(kb3*F>t75Ney(6$H0Rs#S0(%oa7@A14{N(} zLdnA;$}5)25Jk=!#-^ktxS7pvRjYUCG*N|8|8?Li7wf1!M^?SJ3rG<}C%Z_Ppy>Gv0w7!t$UG zly%jI1KCja4k_Qtu5EOvB1ZN~F@;L6BOn-iq@DA^e!|vwaAF%&$28;gw5%&O z|CD{3m?|~8?B#We?R$LKRZ3*~UqVI|zQ@+<=n#z1*4*MRv|HY2KIxCb>8Z*evCz3L z&E{v3yk-x&6?wJZ4knVl`kNT$lUNsF4-Ag|wYWgW3G!RICTcejaW>nH#zapA&{5fzw z*dThBcP9_RC(<&lE3)I3TD_(X230GUZm>>%?XPI}-P)q4p?MGeQp5hoQN6h>G8+fb$J${iguZk;Zlh@ z;M^<5px8=vln?BI!3s$qwa?3~z979(2PQNIq8?qpS+Djlc+`N5OV#$njWXkIBfDM+ z*QC7L8>K7}+`XM=Uh3{oHUtLM2c&(ca0X6Si;?LFUtSxSN4e>z{TTW9v4ziC9k=l` zD-y{%6+>Ae+p+WvM3#r%lit(15~v*na_Z3%iTxvgdPSkTi1FCB60`3q{I(e$IR zul!%G=-D(7J{{fCZ}6|eHN&mlPhsbRhvW2BvPIRrbEH#G9}`s`3!Vm~d3|<}NexZ6 zCwZ_&)S%JFQ#Sgu%!r%3j$@f1i%&2tqd&L@G{lFo%9u@*wNjyB>dj1|zorJv(HFp~ zKWIZwB8t2AX||~L7OyPtHQ|F@>Et+FmF>c#Odis zag|J8Cqh`TPv^Sp`H*uz*Gp4VhNnnSiVf(D)hmuOtHoy&inS`=vF-6`uAOw?vnoo zu;mi6j5Ka-yosH{CtPyrP5`}2vzTDY7D@Fj1L7a_OtP9C9eY*Oib>Bx0X&L?vON#= z3Y_jbi)5XqMCfmWw{Swk^X|C!JeufN1PW>S31N-U<^M23{^8CO%GWHIhMUegEMLM! zsc9+3;k+c;CWv`%Z1?M{AK~~UnBUdFp|nQHhgv_A&(=O?yg1NBLFt54W08c@hTupx zdUNd{g-pW~>R3^9d|{Q?zTx+%yrQzJ(Yq!KZen>0_x~``Zo*v(Ch|>;cb{ypYmQ7nZ>TCU~#SLu*^pqC)&cu=#0%bSKhdtF@vOU8uEjT zk04JX=P~imo65qeL!}^tthDhrH42FDS+?_rn>7T!cnSKJ2`j&%$n?9~vi}sHaF5kl ze3`G8uVY`&tta2d`Y}Uo@_D<|kj#KS_twa0))bw7*Jh;rZE5j|Mn-Uec>SrOTxG&gush`_W8d4LyGb6^_cEYD@gW z_=?cUV3uF_iqjtsIzDqan^)MGB)D5p8+tsQ|Ddosr~zSy9K0G74ZR2nf)C2N-F(A8 z$p7OL;DX<>9FTYq!gUV(sHZ?I{Cb~r;iuqUuDp-d($#z4_hYv{6gN0?CJVC2g|LYP5#=K2mR0;g_cQ2QU8g`Ulf^<`VlltoGv zxY-s^V=bNsK!P~)!PfQGtBV<7Nb3w|6=)u@V$_i>>c?-2M_;V5=IW@st2+Z0);~Lj#*FE|}8Rz)CS&^DTcY=e%rv~afH7OeEiImtO)JCTpXJcP{iGqnt z+G|@vg&X9{HtHTqs2w$uzJAUB^B;x}mgIRqhs=$Xoe_L}&aQr2%@O;#4Tb=0mBGW< zVj0NQ4z9?18ZqjliwW5nF%({6&PXe;|BE$ImfIoIOXy)7fLCJTEP6ehPx0zDtYL9s z=T#Y>h`Xlb9mAkkL}pFfhlJ+wIYAB zj(7Z4cv9JV+I(KWdYYe)f0ueP-fCRFkQGFSA4qA&#iC_|ZDBZSKX^6Nq)oT*I$eDJ z4VOa87z3@RJ}@EjnSS&^oR>e(>qx{XOxa8xntj*yptPMA#=e<%Y)WB5AH4GJOQ2?L zhb7!p!GJ|GhRgIjV&Wo9J?s68v+zmeLdg`t<8#ra7&Y2vlQoI7?c6 zr_(R2ikV6;NYXq$F%&pvNEq7F&EzIBEv@5=6Uh8{DHX8sEUCEvv&rf4k$2Mp@ zpIry4iCiZPQGPaDp~Y>{NNGCNPSGqN0$s|%0^2{IY>0S~bH&tJavbS9|KW>9U5u;3^9Fjao|O(TlIE79(# zS_Nd22(aemo*U>~T{O#o#Y|^4&y3Gd)$nR!CM!Kv1Suq6>S4U)NivORx5FT7nH6Ns z8h`_Pm&xpZ7?L7Ampf9AnrkRuSYI(8FR#N29|?xRr9c3qI2fajYc!QUOXiL0D;@Z( z?~^uk=-PRX-2W6t2g1VbVK`7zN#o9J)?!=575z3>$E!+^nc+fUg%CBCZD_;@LB;7q z9CaLBZHX_~8-)*iI{_8VgHDZWsKB$ENfRFn?OI#6z+-8FA>C@bKZjgdY^7h`Z1BWT zF8}l%%_Ob;G&h(C2YlA!B>)IHl{dJgKo(HH=m8~%Nv_AZOu2B zS;yL~nv|)G;XE;FnO(U5fZ%8xUK zvq>ryv3AS;%U<&gLjQXS+^A<@x#;BC%aAa^AwMq>nhPJE918u7VnwFPf6BayiuiwV zQZ(7>4PUj*N6506qW5t2eF04O0573s+6LHbh^>FgD+Wr|&ONo7xgO;mT8-JSnuazE zh0O+ptpI1$|1e+-Ot?9@j?Dxs)#DVO|Bouho5d83z&SHZH{73vn zZwMbO-+jXu zGn$`wOMak66c$a22F%~Anut6pt=l>Hgr}@}>J{o^Tv?nYe1z>|%E`qct;1FGD@i=d zaJk0KTg#ZLcH@T&Sf;3IGN|)k&)c44I_A$FV2k}iwP-Ng@HL+jBTKOFZA$0POy z>z<8`;UqUl)IElSH}u0Wk8rQ7m5wcvRxJ7kKEEv$l*qO|)bG5<@3oI}6l4%%)~wx( zbLqC#r^_f?tWsdSC@XtbK-@<2yW>gDRLx^b7c2cGC zJS<0btR8-?i#*WD2Mp4 zY)1#YR?1(<;tB`*D^WXSyT6+Hu1&&NeMZ#)U^6}a>es<;;~jZvTiUD!YwBDdZ_j%e zlzlAzhcTA@2Yg%Z%Y%|vBj|hd@PIKQCgKD6`W&T@l`WSs&Xb2tpD2UTKq-O)_GnVJ zzD1^o5oA|E-{5{29#B{&NqLJC-Khw$U$vdYRn*CRL>2bx3lR4v){OGR#Ige(a1jQf zM?b3_>%X&GAREI4;udD2xPi`pb(=$9Jm#?*g!Deyd@P*LblQ3H2hRxz!z>0b%JH)U zkMu#s)PXLvKUhdM2jaG?dCOPi%INIy9Q3?;<7U^?BX3ZdSYow>7Xat3I?CNI65Fl{7Rj9evUZIft|UDk(R! z0j`K*daEE&eVLJ^tsi@@T>I5!#{Xh$rF=IPVt+#PXD_|$_YUx=bLdFNyAUw{!{CRcwsaw_@8AgWwgz7!6&cWs_ zVW?hIw_0-p?RO1z?A!$ZLxoj>)%lH`&?wX&xZK1PztvYnBhg?%-(=m(0lRM?_Ql-} zqu+K3syqgQ7@O25mpXWHLvN3HTZN>4+{29If_4c+ET1&KETvqQ!&5wrl&HpV1=P01NkSm`( zoI1OEx24QaJr$Ik4bw2+z1Nj&Q}|a-+R30s%i>i&S}zQt*DXY&Q0MR#*}vp+*(;va zt0;HPcW+h?P4w5-E8dD%Hoh{3ad-0$pbPx6@-FZ^VqTMuEbX!OFvdJlQ(*s9dF6N( zy!hMG%hE*h(p-F#`t-OiCr;a)Rj;6;_@40t_KdX#QGDF3WVM8y;O~93~e?F4w-EhP8>n zaA?l$-*6*0sYTelNE>>ZoUhoRWP|s@XFYm83Ok5b1T4}qKVD}RPc0&Mh^ybT(cx;M z5tjaY)ZxwCnRUiYqoSE5Pl6TRMQt6Z_{!6mN@&Ss2UMgAr`&%$KPaXQj5fd72UH%|GjQjEI&i1E2;dNJ(#m^JOh%IPe?Kl;rHaxo6^qRx-RF-Oz#8O(2JemC?b{#J36|0#U zrw^x0%|I`~ zxU7c|k^$)m+{tqvP3HjN(^X#ky*K|~we+9WhobQ=-T_Q_VQzm6LF~-$E&n{tph#!u zr2HtlHuBG*ONdpusXa%~+%kf$YlX@pK*Ot1S#`aI*ia$+V>AVyYPd#eBwqd-<_bbg zDdL3c7feS_fBn%uCmrJ(`V&$t^EB!@E#O{rhfMJ&;6OItk-KA1WB0yMkUQ&jR#Ejfe9Sm}X8PJHkJcv0krI!a8`Efi+pdiD#I{%*+n{?ki6%Dh^b7(^! zAP3Unxg>Y<+VTJe{L@DN=2X7PmS+w*s_lJniZL96 z{-_1}K8rT!*r+zKWGDyr+MJzy+Z^hWbl!G;XnbgeST0{bMR%tBe8#-71}6uCsm|*y zz5TaaPpfFJc^m`uaDnZji>-F_lP5TT;$t4~VbCvxm&r#<^px_eXGy>Slx*!1NDsd$ z^55YMcX9o8Q|PjA;=dmQ$CBBq>**xqB2&p`d&v+lLKAo~MyfK8@%pL@4U7FNH$5ok zdZ)X;pRZalT~s;6yBKcOs?A4e(HHqjcoQOr3Tuwj2f2s32f zgc~AGGcDbm@1bpOUt~u5mZx4!FABU@t$L;BRTlBA7p`L!`fAsH{MU2j2kGFkXB9dN z-~hS4Z!`fXYlZ<_bY8thQkqgX8Gj+aR;${V%e}iQ4{KTvVO7>837!p-A&?AUH5ZAy5av}{KRag-i^?mlMH%bwO+W|jSbIFEuH6)P3-L- zI5AjVF%UAEJJIy+?)yeb#xdBRX_(H|okD3J9h0#9EHFv@n7J=Da}crOboxoJDly}1 zG+hodL*`)PHXq(ca{cB-DaZH4$k^*ol0?D3nbwAk?gkO5(7|E`WSXpgtS;hguuK6q z!`(5EYPLYwL`283?BW*u*UhIK@p!XrU(o@Z- z>GgxL_3*N$s%TS)@sj_+Tgl+8_}@b6%)@HzIpnkvWg84nhxJ;zu7vSTgmw^|E*U_A z-T{nI{IDd~VmTA04bcM#r|qBJJ-u~0vUfRY^84m13oBhmhd#xOiC;IX{$TID_~(S` zvjfC_O#i%R?inU+f$k@-?I9#jvkYHuhI+%Tm4;V^dm~qd0u&kkryDnST>eBtKxd6} zuX+<)k@I1IwKM*#irb^F8UF(Z2KEK>-_rz}E)+Wq-*&1vd=6bw=Du8Pv&{dqYM`c8 z<6>i@_~jKC!y)!hshy~smn6)$beey$7P!2<0v?XOx{$CMND4#~DwCA?B9SwB-&ct) zoFW6nD8R|yz1?B+){u#->pnvbC-Z=geTJcAC-YIich0|s&+>>GH(QM_pg|43Xn$2j zTYu4*Oi>@_D)E*kS;Dm0gsIQ&3`LYI|7(YD9-MD4NQJhDSLIp07p_VWYflLHGgj%htXzg!!hkJ7 zgh3~(_2VgmKLQwq_En+!L8#a!^Y9Nvipc5K5m&zb&OXv*(P&|jjIGFpPdLrnA z8(cP5%Mn=W|mYRp$>2!57bbfaH|s#Bc=y$y)=f0w_4-UFHv*;=a8CHXhx z%Q<)>TI6D4G@N9tdZEl=4J(~`Qc|=*)sW(JGA#z=;G@s_jXEN*3DpB+s>y^*1!ZUd zvvd>vsWK2FRMS=&2_8M07ha144yN~TqqesM5I-GhL|!@PZ`%x@D<>O>&i~q7fS9m=Vi1R!zWz?P8-hg}x_8K^6# zRGW}wS*mwgEHCLCe4ixCa$Q(pD5i;0ag39UkeY^wzz9)eaZ5c3|Y00I)oq@^xU(k3!u^&kFEF#-k!?pO5TGzT^ToyG71Q)X zDQZ#|5}HLkp(4SzMhwMVoi4jrBpktd%UL6)%)<>A0*2PtwajE19orO=9{g;d~ zOnu_Dv?%}uEu@g%c0Tl&y=0KP?_4wycwu8gdtBW89L^~NEERLo#c_X=*_AdBXc}rs zZbrTf$py9L4ksL?xdG(DZ8zkz)G+(TaFFd$;MXZftiv3h#;!Lq6Jd^NmquS2?edNM zCqsS7X$T~7-u;IGob{&%bBeuJLVJBc4L^e_)*p*OYUzuWUwFdfX`i@}Z>gddsZ^&|5yr%c$LxoO%2;2iMF7Ns?DPD6X^RF(T z1!>_dkvje#U$K}$ZE++!vQsQSG^1jQVexHHLWW9{B3J#`UNG_EJCTf}quj$bVrm%} zJh{_lOdDHd3 zUhx*HqHaA=TXR~{P|?e?!Zp19m}kyPi^Rb^w-zt@t5LW_G7ihoD9aIaTGqmQ>U?_2 zWW%^4OcJSx#02H2GYVLBn8qa^D~%DxqI#X7mJ-e^UFA9jW;gV_(*7!%b1s zbbO#jUhIj=KRL^4ql`yTjhH4-*NjM*_hc{iIiWXXN=im|0+JU@kso@Nk4AtEHLYdf zPRhWLqbelVbIBNd2f+_H0d+bZz7rdOC(SbHH$UtYeG|=IKfNK}eq}c=(EPY`Gij!> znfQm$$vgVvv!C|5i$W|Idzs!|fMnx-5S_LVaBRzGX;oxvGC1$e*xQxM;!~AWRh6K8 zG-P}WTJWUkp?BEZ;uEBp$(;1TYJ3JyHw8G_v_jw9*Z;~yd=PYB>20%$SwoEDzbGv1!)9`!ic zy)cfe5^KI>?{u_2+ZI)%Y9@=YA2$soke9l@-P5=}XH-RD6q|G}LnQe^mx2ylTatW0 z-xy;!Os1m}@0uGW0`{q*Og`dyXQmAOhr!_Zys+elEk%F0F}MKXr>*-2ocQRo44njm z!do%}Y8J~^*wvGgtYrj~iJt#U=_MrSkObUNwVFt{U%RTx8O^6P-Ed=mN zsV(lcc16zr3ZQtSF5TQbS>xJ=TPIVGEmXV+nl?8N`rvo#P<)7r2U?aT8PaRDKk9x$ zXz%D2u?@D}!DLx;^(GoiftxErQp{RDutBC>_pd$?=i$7zzQy()dcLJe`X3gbtq)Gw zbUS{lmeoPjBIWXhA)Ml7Q;%hyZs;FR-ezDdF^3mZz22-gdL9fx!*F2R5hxc_YBNe` zT);}T(hQfJ*pD;o=%UWS?4zsttwIw{XqS1kLmJk%Rl5mio}0dkh2Ny2P+(X%lO&sCEW1dD#wH_%5fG^q9HhrdBl=py#%0}#vouotj= z+XcxFvFdqFqzLemtJ8~LiP!N>YUA>2FP)s(c09lZ)4@Too05P7;5TvVDh?fdR#ms5 z>L?s3zT4ySRO1DwqO028VknZ`l8?FTz0YNNDQEtp*`s^7_5WC9)^q4o6t8!wn`Cwu z$kV-XL#?=}v39%SJ(pa%F7M-%Z<4?t=J3X^m<~Y-;T|Xe7#jW#Rm~s;)|Or=3oq>H z4&!??F&IzRFgU(H3uRg$B$lW{G0F8wV#q$x@qGsY9gBd zE6>cSvj>F5{IQ^eb5QHoC`n)^y2fb-nI?uazEddcx)?CXrwX@z?tKFLw%`p8vvI!U ziuhgyvRD{?Iep5NPKKV{1%X3nEo|Yj86q2}ToW4zc4)qb*te#lMvG4sQ?Hg0ecxFU z{;FdWj*M0q#Coi#(wUrDRe}&==>0}$>7xg#+S)~%I!SQLTH#d?o7rczK=U7pT;q#) z3ql=(dce$7ojP#{{j;fnQTTyCiLRGv*;g(^1RG2egxUM#PwsvXnGd$JLeYbm+zoyw0e+RQmNXP^#MT!wjs0i_Dt1R^ zSDdZdI`R9;^I{GIOjtDAg@mtv0X7{(vLZY&16(Cf>Y7sqys;hCM zw$ASLD+7({7MLu1pOh^0_V;~Q+f^xWR%6m1VK%6*mCEodSaj2A;lxRk?w>x;jFdDB z0*Yo9>H>bwb0ly~P0&#%3+IMPL2G)tzD0LYn3E_@O#CdZb`S6;tZ_RFoE;q&3u}S{ zlW`zsWqjKeosN9#!llpjs-f?pno6)ipb;?UkO*Ma$# zexS^g(vBzP@MN3qS=nGy>MwE24DdNr<$cEKNp-ZeW0x6_(a-$ZEs?w+j#cH+!c9h{6aR2GfIqve$7{#8)EMqWB(g3-7?e z)SilFl{HT>vo`o**?Rh*la*R?f|nQ>_yU=fZGw0SDHXT(`{pg3@ip1vB<1QXX1|u0 z)3It6I$4$vF?Rxi)`>ju@R)_GfF-0?{PQ=dH)C}Lst%T9n~!~~idI#$5=6_-uLou) zd8of;Sn+0zDDL1-K>`AlP30&~K4RQ|74MLwEPTRJ9)0rUdy6#?RH+>c7c00-Wpy|8 zba4t3P}GzQZAIKVLA)z`32+HYp!__KZ;vHqqfi0$R&IjZph5FN z_w4v#p}XmNW`X)9JPciHM3JcBXY;jUt5Cwvj_r#gU9gvaR&63p&&g1iRB2{HFCfge z|C0Hsxx*SXay)0=_Yw}$m{{)*UIzB*DFs_O)ZPZc7Dn+XSBeTAW~`!SS-88rKhl1o z&EFqYklW_B?a*HyJh*iF6v^qOjukVxW!n5W`if|=X-Zy%g+w4S1NT` zqY>U{{`4GiHBblN;n!x?XI|!^Y&+GAX4${+qrWPd4;v{&eN_t4m9hr(xDGmPVL`%E zPdBH!LwZOTdRCtX)CiX5b3W^DeM`Wf_?#y8$N75B{z2XXQgLQ1+`bn{-%&Bn+DD$h zl&Q%W0!pK-j8U!UdM$O{N|pQUjB%WlX6=$Sr`VqmHCjOF50PP5AV+TRSSW?Kl?UdX zR6YDj?-FrxVu=jG>9jj;ji>STUtmR2z*7rS;iLJ@eHXA(HaH;<*H5oZGGpA=HmsXi z#!p)@O7?PRV_#&yn7p!7p_l@_WJ%#vK2l&F<*`%Z>O}l&Z@XKr`umeoCB5HV+$d@x znR}t^Jen~!?_M+r4m`S3jCHis#IGvk>pKmo%TwNW|R_mn)IW&ew&> z734tkjU)$(?7=k_M`^2Wzm`SbY`qGMj=l4R^jr&-YZ$UFTn9YnrSIV_a^~BcBV}$T*(Pnr*yMNI zzOc7`f{l)u3<+fhWnbctSVPDSe_x zy=9B`@Az(n6v5 zOOslB=Qp!=Rq`h|Rv#n8r^2zx*CthbWI?)U*!h0(APTuZ!}SOWH~GQWVqfuhd6^>E z=}TU725tqOliDJ=J!#|@Y%*iJEeXTvUJ^)7wwA$ap3OOEorv~LAz1%D2=#ED2sxmT zK)UV@4Bru2M@_6C9}jdh*k*svot!!gsvCzixZu&LY9LtMf>vMdga}0M z&c4++$q4%yq;yK4He>M8Ha(kvg3QpiO=)LClz4xR&x>1UsP}UGwLTMwR+Xrs_@k%o zVM1wm7dBO5De=i@mOQFB7q8{&ZNe1E*x$(JaT>u=nbnW-cWS@phF@j>;ltsG_>eX` z)|L^Gvgm@9I%Z1LDZzbFT7^p|w=q=NXA)iM2tWh3xN?%Rv{5IH_ocym zY)f>_QLH!w0TE`PjCokqqfVpzxzgqHr&B&g+Ibt?^jA_lYkxhI`d1Nex%xldSIJDo z>q*QO>ASD&tH0;1p@fu(8>Zm>Y=kKNGGpr`$leMG&CJ~wt{0z3QjDO?zEQfX;ls`#)6lj&_n58*1 zp{rtgVYtf?vZuZqMg|;<0R^H2F&Kq?up#qeJWcJJ44^%zA)BoEG%;45#KeF{cB1mg zmTRZR>zACo(=*_RIL`z+e=L`zK2A(q>eXA)9)+n=n%&n<=}(T4uk5>_HBT}fmZAiP zyeoDO{R?Io!5{xV`b6%6-syY0UC&XyOC!fNAfxdO#@?~-nX--Im?&x+6H@tkIykO7 zQ2_(fOw&7dL~dAQS*@>bMEnJ%tM{__uhl?qJo+K_u03rFhsVChBGd`1g8yMm4a%Tg z5G&9d8whd>0a|w|W$evwZ^VAlu_amQVz@4f9EjG99+gt>2i_*IY({7aunBW3n1-H^Nm=)Q37bbzAb^ zs+&ALkXtr0*SV@xT-zB8pO{-n7gs`wG4j<~#S)P+o-F2^7yfk!%7yg`QYrGnE`r12Dnz5NhK$Ef&9I&y$v}%}W+@6HkU1VI0 zd)}lvLoQlmIZ26oip3++KyJf6S_PqHe0>I3iU&)mM`7?HAJ~f`DJ>*_#z7vR(_BYw zzNSer^EfS$61K^0oOSU>5fyXV7|bXWEhgu?D%*TWzU0n^D9Hj|blgN6D_L1UY4CHt8A z^6s7N&g)MGhu$(EfYF#N@2#xxv{pv*HuKL0S&*Q^H^-GcIk~Oh#y0-$1ghcs51Vi5 zD_?3)Ed^gBUeV&!REt1VdscbdOCm;$?MRv`Ojj1-Hc=d5ne$NmN5nr%80{>XKgb=GD; zAQ8Gq+3Rg1#ByBDqxIqeQ;BKzpQj+v4N53}en0n)h;>`F#3dq0;snCLF7);5OY|LJaMMTJTHj zikCjW^UCEIBF{U-Ygg5PW<5m+@EKYAC2!my`G)KK#i3KK-#jF(D-ZpzeFR#nIO9IM z$6FCbPz}5GB^uZAN$B+Q*e6-3?6+aqM||%2vV(#Stv`!G>7oJ}xN8728&B}JNR5x` zm^$A_NK=L}!b$%OpjMqrIl@J;E~N+3%s=-+_lPu#+iO`0NBuMs=hU742HxDD{wS#! z(_k|kdlBr!a8=Lyu4kcc3ymvSU7Kt~p6bm<`vV%WK=FDPnj-CfQl-!dHH=USHJo92 zIu@+cn$xhVvo~B;IULNI+|^8L;gnTUcVu$*Glo>JxRT-AP4 zBn~yBjXbdQ(&a^|48fe6HUUeaISf_!{TXj}h_C#|D9=}RnR@Mwgi8wUpay1-)kgGk z-`YOvUDxgg|1M832gED|lg?!o z23S)NG}!a3q6J@aPbYtVTQqNJubWS7yCN~+D>Wf)>%N4VTapT+N2|3IqGZORxnC@; zeTMsJ0hPa89VTum)<81fSKMx_C@COq*(QD~c%}{|;#;u@H%6`BTl67JN?=VU$CHu) z+Gi!+9`o8>m9Lc6v83MJbL{UY&UvB_AeB2CD6cbJjU9vRrR8PQO?@Y(f`vQN=Mk6-zxbLMacTdl8Ys}1^gMGj z2z?r1@N6qkg4OU~7^!_jcZe7&|Ro4*Uf6)Bk%8MgZ|bIRV~6;DYgQ zH3e5@R|W1=Ol|${%3r?ZOZHEs8L3?qO^|4FD&(z)Nwbo2h7`)^)PEQw7FmJx><3fq z^TVvskV2wWVAm`Q*@wCpwD6O99x4eFssGr9bxCKX5-@TIA3Um!W@GSs*`_9b4iKc3 zn|~Xw2AO6C6^Ef4k+BDm60er_4Qp<#{4m0WsAxkdCV5cSn%cXUnAjHNn^B#*1SN5n zHesOA*H8MheZqiZ(2MewjwSe1vw2JoDbU>SmcHQV*1Hx|wix$tEam=3G_h1)(qWUk zzwmze=223BdOR-^EoS4L?%&{UmZ@v0wxlaT-Fs%iYAW`QSHwA zBlxQ`$7gf``&L&peYJWtK=0=;ECk3P7$361uK@w`Y1=GGvh{G&sY>^4>jgfW^)Ov| zP0NOnjDt)JJ)fdDI!b0P{2o0g`!B;W=UM311$?G$%hnw;ms|kjHj?N)_91FTka>JG zx4Z#NbY&K$VyCidCPc^#hM|jOCP~&=my2rS%6s)Rtavn*WRr@>J8mOrE%KhLtYL45 zB1O}iH>C$G&ATUe`a)`7ClB$jDqoJciR~Yp;`cgI&gYa=l&4LA`gMIW9ZD3KT1}#j zOaoCN4lNaO9FAyY?`(&Z?KrB*aO^r$+Yfwa!fmT4#;KXpB_@1@&v~R0-2wUs^OfrS zjx}}k2o!`ubAW-`Tv9Fe86t2Q;{KvG+maZ6lYGRnRD}CQ9udc8g70;cipoy`Mh0A< z#q$>MeP$v`kPJouPwH0@7Q z76THytCG%XcR3tb=Xpwx&`D1^R$2c zWr4q$XTSSHa%+l8h%eP7-Z?wn5AKUl)-QTlm{xwwMDl+FL(5QI`}pjLfgLD-DaxvD z@S_cPSr}A9#b`Sm!FXp?J?7TOpF2`g@XSvn{Ve(ZLtQ&MI{s*aq}A3AGOhRMW_$Pz z2Y!>~@1?g6j(XcMkg#g>?_+u8^hZ6eH?-!d@l@8CQ=eZTM<3spAbRD|W8NZ`;0kCw z{6R^5;dS?XyLty(t9q5tQ(tRbDPFNA?4V<-^}p|vy1aTV3x8(Lp8(t}Akm-%c>~ZM zKYv@KI4)(2^$Dt3GvB$0ff|w*_gX^5ZZcTdGe(sz#OMPol0IMlo`~J+SE)>LumO@o zP(OifJDCA_Y|_6dCv@J-)0b6l@u??&>w&7-+r@zQx61C~p057kM%+fWajK4U;9sbI zEoJRZ>(2NLRPHru5Gt3?J}qWC4&UKE+_9Y1XEiJJp@mD(D`Vu*_sNnd&K5r~)6yF7 z=J{z-KI`dwwtTX&Rz8NSeSMC&N0hGTh?dFWbng~ES<^H^4}7SvYOe1hzDT2tOetL? ztmz2ZZ7(2u89ltzqSRLRZ$$60EKVhSmCn{#pLw<3@C`_dZ zRo1kIVn)D+t&Y3mg+?*bnM}+a1ts?P@ji;usjt2y3wdV4>dihcX^Z~7{k8e;x^~m) zRZBL270cygTR^wePr&!|HQkWuc%_zZ7t)TOzY0850TH-W7iV?>>9k#R=PCBH@Q!Rt z%X_B;_n>S}y^=0H}bnHWl6Db_v%(M@@OH2%%c{}hV7_Hnb9RZe|0c~nLXB7?Qfr4#LP+{-NR6%lM%j()`N z%N(rN0Oc&BEc?B!To^j7^rf44=#I**`_x3q*a`0%v)CT=T8Hk29ZrvMVd{i_tJluw9==3 zXL9}g%90GXGPCnaPUbip>tQHl_npKB74k^TTe-7wG~x;RFOQL4@HT9A^fAF*GJPM}CR_%u?Tzv-$LV{s3a2?r{6_LK?Fu zmKbnQsQvp_>}i-Z++EHCNPUo`kG?brK+_<}B9|?z+1-s4Jlxh@lj`kzwIK9n|pSqkhQr_bi)l~;m1lwjT2-hWlyX9d00q{w8Fc`|cY z_ot`D$$64i6|Wla^MxFR_E85qi2a=Jwnw}yf&wNfB2^&m_~yM;r#GLTy<3n&mv$xU zqUR7T%O#&R8`cpHDp#KIY>@*JvTsGk?sNg`3L4IU-W!C6m!Up2fR{%VGj7!S&5{h| zFS`FwbKHIwF^byDle`#x{dyBCwPK2tI(q~NH9+B`Y8tInT|h8sj*A=SAF}Xl9t^6F zPxw5lC}Vu!5Y$M?Gz0L$^Fe_S08er$I;IJ;9?h#-s-sh7duj=Xj$?&Ri}zYDs=MLQ z$uI0;0khe3riGPjvj0LN)SQRTI&XG_ZL(bGU)1j{6$3F}&V$2hE5*4@b1Ta83Mc;z zQ4alIzw2lsrHFGrF8#tho_TZhb^08RZ>R^_>QVazE9?zo2mG6c@n5F|nA23W1{~*V zI&yd1Ed0MG7O1nkCk6^{Y7#pDWL8dJY1yk?+D>_Q$zS~tAJ*lXhOO-_aeV0(Kc1wp zt#~=GcoFI>U4hVR{VKn?&ECg95{Gm|SnMSgrGEfdp#82GCC&$x(RbRwo{ipsCoZs6 zH5>(hI)xfTtu%Quh{PPYG>LF*+Nn4vC)YMB9g|cR3v4aj^EtE?rMArd2aRNkP@1_+ z`O0J_N#hFRx)IGwRHUTKb6pv#eofZLhEw&&Vy0q2n?35hlhr0cY+0-+2PEG47+4u8 zEpieLYJVrv%l)h5ua5{*xH1Gti122y3{Pa*-Vq1-@N>n8$oz-#m4!&(n^H-BGg*#w zFM*EEFo*cMR`P>G!%%(L*VXhLNY3$yA=paU(c8nO^e%&_W3{L@?7}D|Boniph@=r) zlt%Bd5j#!OK~EmTG%R*-W4FS8HS=7nfw_uC##Z zVGjBp2$Lv~t^>x;`qhyE{hFF7XLIC(eV0lEj70-;`j2DIE-qTCY!B1D?N4Y0&-g0= zfi-%^5e3}`ZmP_xP5e1mmbs)lOESh>%-Q@AWyK}0K&-e|7|dR`p%q~id4nS8(TWk+G2W(XHHZT92=OqBcnczY6+=DSs~=AjDl(~` z`3p9Q04!Jxr2qI#Qykk>r+5I)ck-v5yumjB6pHs<5}0A)88D0yG!~7LHReM-BSIBx2Hmavsw{y#j<*ed>`60=E?qK$R7@`D{OT)&y;-mVP#MyiML*4>NUcAvsVwIim z1m8nj$D_?^h22PP{qACv3%pq(Mpo7Wz3g)waJMU9314glAML=gfWEmGNnRBMCbC1b z7pv-MaMUCU&=BO|?h#Ajy?dug*O3m(OkJ0yM|lcp(KqyLQqS&b6#ji|^y3;H1$a3_ z`NZeeb;;a7BcxhnaY((sriRVNV`qPHabK%D(D}te^QEP`c$C(@IA)@rLT%lu|3q|C zULu2l67S0qJzjan0J_eLX6+_8y(YuJk{JXlf4`KXok)xXdoOgk1!poqPp}^HJXEH9 z)i{)O_KVw(AHyll8c5no4e*2WThCX6M)amxSS#bgPdqAG<`U)$b9|X769YCAJRifw zE1#Z^`&I%T50`G*3T>UqR+;a4>XeQ%yW~oa7fv=_zJR)0);TB6Ai!Gf(}{$Y+`q9D zm+j#faW^szP)MO|fkjm}f;}6M4HU3-x_+vpU?sLQt}uF>_;kL(f1yT`ojM_Zu9YZ{ zz#4aPaydv9(#7t~N6J)XMLx@BE4iO%Neg8KT;8ADU=o5pVk*)vzcFzCU3at^-@p1M zs!3+Sz40lxt!5bfWA~=Y9X!Upwp>&+g~Guj_Mt;wemuR6&Gu zA&H*KWZt+=j=bzw3uIH_FFC&7qdwChf8j|zdq~=+%&UUQtoOA`6R@veeaQ?z^tbP- zy?s_xF~K`5D!hVPriA6zGsH%EQhCyvLAFO%1YATs?IU-2>i zHWoqxieey{Xgox}_igLR8h%@uF6a-?WO8b~7JNLW3K$86H#e<@T=L&%9M4X8u~)s0 z;DCO54qadIo6z}Sf6hT2nRl!4I&2h@@xc+VH6K9Mh;A1vm(X2s!{^o*Nl z72f`1%6Z34mnYyBhTzezX1>*U1f0k-nV={bSWImheFl?xV{W~HaP{CHyUr=QdTPV6 zkVd9ti=`(&Qs*2dO++-YH7yaL(8#>C3@bqI_jRK*%GOb?6Kmct5?w{tes%bp2=^Py z_k}em&>(7z*TIduP^yve2DV3Ux+rDQcRvu@=|R`~hoHI-!WjQb*G@iK-miD%dbE1F z2m@Puw1N-$Ix|m?X8a5O5jHI#pU=VnpE|<54)v~9Q-t@W?!5iHjj5g7wTY#AQ=9=7 zRhW8yp7JfT==;o{dpNONn0La)4n%NTkF+ogi}3fOscH3_Im3{R%uTh z#P=W7U%`fkMd1$wbKVeXlt_cj8^{43-zj=~KToc&9k91{(AbnTRT)nDIu3m@_c=d@ z*y)Ayy-uT`%T&tmz=7u38|Yt^fyAZ_zy7c9Do+@YX+SlXXoIfuhh;+eK>f7tUF8iy zW-kNL2o#R!85VClCdx zJtaiw-GY6^rfnyRf1EyW8G&JZI{j;+*R&rzXNNae6PWip-+CiHM$;dk6UopzdhTYd z-|pXDzDrQ&I+IKN&XQv$#}Z_oKs10)uF$B)JNskkHU3HaAf9c&?5*DgAR9Sm*xw3= z6$oI=O+vhnyR4F!Lrhfy_!yH{us^fwFWJhC#HJ?BBC3uwSKg;Smp$pOhrW6S-Up0% z-uP@!GH|2(CS)?K)3W^=5xBjDyqI49GLtIvsCwGgbxWOJ9Xzs^1Y_#;n*#gaD|J^t zQC$p8dfP&fY0^&U=^v5_FqxE7wgm`__k-xrUW|I9Qe*ydwAd0`$F2^0hVL!PC^U9t zCL#26y*xAjAm@+BS{|oXkEEkix+!HU-vy7)l=PlzJEho(-=o&>ltm(T-i)X^zcGcJ zSBCBn+Gxar2!s!nFc$Cu)}G#ya;NaFy}&AYX_Lice!5Vkwj|_fk-?nGhV1*uJ6K2wMNigS1K`}b;osFd7ApkSl@Xj}vb3R( zH%ZJ4RtICSYQg;7fg11#CL(3fdkqIVKr|YxlW;mky0Gck z%p&f-JMt?>^^LLIjrqkuitPyTZXD%>HS7bNJp}^t4rG|(X94*UtM=$HzI8QKz1>ap zF=9A#wBn4q-*EnIf@1C$=@$h8OvPX|z_ju1$nDBi_H!lkVrP1qNim+U-S$A$gpkgc z8u~Xvm=7`sfDZ--dImtz8Q?8Q$F?WbFADhYqvxi~s7i1PyYjNuYe?UigCdkSb8UWd zus{$$_|QuQe`F@6xCSPKT$OBlvMB{y2fp0Am52Do`xdT4o)=KQR2?y&@T)^xu>kuR4T4biC?`X#}YB#VKkUiMv33NkXHLdAGE@s+b`03 zCZh@M=j)k)brZ5rntc-(sIewX;)BJCiCo)0DfDU|T0WAnfUiE6Ki_)k#B9bj+4?vK zS7v~5h4N0%;b%{;_LqU zF=u@l=3KngnEYJlvHX`WIBMm8E^wMD^5Xc|X>jVdvIFmdypB-wPuH#tZ5#v%D|k05 zs1GA;MC{%y(AZEoTRohOXuhr34yNE8~-HT$`czzyiv*eLG+Def%6^RZWZHvQ_nNxGdaH zWim0ZSR(dJX%V_mSf{i&@jLdoBoEt%Qpd_7mI6&;nR=Xe*Ag@@H!=?)E3}5*+QEV4 z>>+~Q(j(*^8eJL=jh#JFHsku|Qg0r0n+eA$k{w z`eG{Ab!-BfW@jAR35E?AuT^NMeHcj5CU(s9nhqqqF^3Q)jKvTtWna$@&M&#S;!1CA z-m9bRWyi9{PzUn z52){jknxTL#TFz@t)#AD7nJR_O)LD5cakg*gG0$XuZ+)*%#e{&7m2|#1COnm1Ms`a z{P*aH1s@unw_^>56vnxYIk=gxhAMw`6)^Xn*{_`NP?NMlG()nWt)$@*^vl8rYwU#Qt?hgFG)SA> zEh$ycfV_5CTUJpL9vU#BI{24XI!pUT!2$m4>japFA>5#=eUa&WDDDj0?+_7psc;e)SwEyTS zK^&U7aSP~k4e*HeD$Y>itJe}DOdSJ%x&J3l!Dh$0^f)$q{&hH|QnYE`UHptj*$nAyuAv%-qd z^@={O#)Zzcl8=y?a;|bZ*&SXLw&%4KG2Hyh`jP@~UvMgo2`+MzV(bv?My>mi$p*&2dw_r?pksXeCSxarzUy zau!`7lOB-vuv`GD`XF+Bnlw?j!adCQwDQ{EROu;dzv%k$u-&|=2O74AjVgjGCS@Jf zP4;ZAu7r`27_oKxj_@IP09C5&KTrwc#OUjcejZg2U$x63t@Bn%L!Z&sWY10@MM;G^ ztT?wio1Xd4eNXTu4iUEUlQ*RPs*7x?3=wK(Z)#boWvv+1c0s{25nOj-V^+a;Z3T33 z-FIFJpT-7_X2+A2v4lPJw75hoLOMwsB+#?a;kr7@O{FJBzbo~rjK6;SWR`YF^{;$j zfZkQ726BLZbppUGmK&(B$>qC|jGl(zLRZShEkG~<=AHC~st6h^j;o4aoc)dj4xaNLR+Yc{fKF38*vb6ZZ!32=8B`IC*vNle?W|q# zrpG45ra2~qGW<88JF);ZoWOx`Kf-u-Kr6zG`>B1djI3KYo0zY&eF&q%5vKL4IU{kI`H zcc?&&8Hvb^v!9yi&>+X0LK9=z(UA%6B*{6iR{Lw4yu^zpU6pV35!2cc_>*SDk z$c8M?9Na6=$ER+&4Q}5mEcBfpBO59ItrB#_IX&7cx@Ot{3@2zdoHWLHPN{MnMMuGmzBv# z@rS5WBb*Xo!$^a&@LgwGQ~((b9v!wZU{Ve=dX?$@Dor=j9W4JVgp-V8!kqLbt+m?gc?fgVqjM_HdLvyuIy~Xk51@oCbw&sarYKws8W)6sC$2%WId{2a_X`w^J7?cYq_6@%z0QPudUDVxlJ>% z{at4~@h`+um47B{ugBj)?wY@9&eZ;zsFJSW4_2M@Y*iU$Q0x~_ih77`4`T7UwI{@= zskgZ=?rFC3IdihaFo0W;W5+DpjqDU&4v?t$@H@=b2X$8;p7=T2R4889kqHFcX${uV zp}k*%5QSWqBG0VYTBYW*Eb16R?G^<(54_&qrNpb;l_nizSk<9W<=Zrk$Ffqhuq0cn z0~Fo9$F#MuGr;yjS;L>T@V{OgV`(p{Pomg`vpjY>v*qM;o^%Kyt^DDJP3=Y`y5V63 zNaYVmTNB#x>uJbfhN(NP-zN8CUd z>s_36H=I9lHJ=M4Kg78}4zVU|2GVsB8sII}&V6O) zok}t${j#%i1=dIAngx7k6}TtS4uj}Rb{JqI1iKCB=GZV*I;Iv;_7(2Etzb(%%jWcn=$E9HmT z_++ZBlA{%c-{jpMG29z0^h)TNUUYFIk}&_f!}DfT^7vbc`pMW7v*G00jiNnS(=4O1 z?iX1}VG;vlC8CdVa+X0&K(%d$8;9x#X8IB|a1U1V?PJO|LKpAD^GV+$;Y1!%3qc3a zDpZgu6xU8&msTc|-B%{P^6&Z!bR2No%8(W4JxmEppJIn8s9j{gJ;mwerK_Kxe$6F0 z4?g}Qg?sS<8KR+du&`$+kw7NK9KbV`*8SxnlZ0L~(g5yC;wl}~n4=SzBKeEF){Dab zX`C(;$z>d6hJ(#an+ksOYY+=B1;%a^6W2a8_()fb{oui~ZRvuE^HpR*RHZBpL!MOb zGc|e}k_J95{Ji^xzoW^iTkA#)8(&7TH@;{x7Ji%6{PD@ko>PjKiz`T*jBA2e|7ju1 z6`n_T{cYJ5KYEV=rjw1ngqs3h7ZA7xKg&8w?=1g*lG3Zi)%~B&Z>k4jP_F7gjAyBL zgXmexNc21D^qx*;68)_^=`7$5G$KO!;r(ofUFfy^FV!yjvMrV}lQ&%?T)gy{9ay}L zIx`Sbx{F7_?luM;i55eC60m=4sA$a{1V)L#tOfn|ka!bYhUm^kV|nD;#qB$`3Klp~ z4UYcw@qn*8IRW+gfjcTHmekjaonz4be%%DY4nN425kl7h?ljbs0<<8pTR&OAPxqjW&xFUF}ivYT~+2Uk2Dk|fkX|ueSpHElNDTL z?Ue;*FJwnfmxKDXiKN4}Z|^rOjqx}i>!i%cNTCbh{NvlN5Bt<2{!N(8Br7+4cK2c6 zZ>f8|G$%7}+i^|kN}5ewMO0`FB~vQX;l2aJ#@y`G1_+As8b)^#W)f^QFBtg`}v_lz$vno$5nmL8E3+AQ?VFFdr5lU-(r}S%ovjmfeF?*-`PTPmb;}?~a&W*d;%oGMm?6o!Aq{5m4-|LQJF`nbNkO z7cePA+-+E?w^s*0t%kYEI%&zF-W_DCw}VII?*4a2&S3na)+il$1b;5j3qIfK*dg3?P=6?1$8Nfsr`E9!bv=o|HCq*NN*=)GCh8$Y9CkPS;P{X4_fYno@Bl{RsAkQTWd}`n?(XE9=6BxWsIQl zJ;iG?juq8$RBz&R>7e;X53FNJSRL#21$vh<4^&WS?E+Mo{}LNO+pcei`bw9(v~sqr z&3MQNXgC-)5VR40Qq02IEJH1-YQ)*3r~?5V!aq1+dOJ)*3(sT@Jtlb^P-A_xjQOyj zl(V|7UtrW$e%f*}o=?{-W2!r%a8C;sR^#O1ixvmR%U(>ilZ7-j)%o0FkL|mslCen?!+|gNW2>P->Ng!CI zH5$Hr!m32~mf{gsNDE`&`!T}$EZddYv@!@X!s_E}&lfn@aoucQgy3YN+dg^SaGods z=6qT_{|867>k#Y8n`pW!GjRO37jGA8arIUfPA*Vm4O5obCJ4TM|H@x*^E`g*yB;&G zh`OTIwEO}VYj>wI8!Ih^ot*{IyJXOt_M5I#62T0yz2Xi2B?{47umi0HSgvnGqNBT& zX7$5-hUDRLC6ir$ab$VR9U^v#{Zu_hwYo?dx_*BAvHF*Kv|DiZdk#lP#&%{G z;F!aoSql*WrTE@t*TojAGZVAO$~o=Ry`plHYuFA|9b8c?WE0mhKGFtsVxu0Y@skb^ zvIzARG7gzSEvKC(KkfoUe>qQNCl;pkx|DU1v%lGAuBLAoIr&)VdDQ7n8mEKsn^>Cr zj=n)-8ha4g@0Q!~)Npf>Yw;rV=%+_wSJqF#bVVs_zgc%7$ixC<(j8GI zsQm*957^D_E7}rJ#^r*^&C4go$fY{r!DJU5_lKW_uY4`SXvLXF>p^TE;)6!`*@u&= zC0sl=JXyfY?GqvnlSGaE2al#82d_a%$LGax-SV)C!k>=P6&ZtKHV1zpHWG=y{y%x* z{2fsB%MidJtgWiM!XNqawcVs9-xqD`)d}#MQ81sQ|XzbgT7u;}< zmH=a%(6%_h*3ra=n*;6}8Q5l;(t$QJ2Htk79TFY!;g_)5q}Hq7iSjuKgN8>kTz`dV zwup@Jv_-La#P_JJV0W?;Jf8H{64S~C)a_hMByV1k8GT=GPza}}^QmxZI@;m2{}fP2 zjkvWm!N-5scFRfASb?~o=7_D-)kPll?S6-agS^8L4<(qK1tvlx*Lw%+tR$t6gYIv4 z*o=redZqLbLl>F-Lf4x@Lw0c$OCF3ups@LQW}}wUcXAd@8}JBOH0|0+CBws z>xQT}O^LyD;2HHh_7svP_|xQBn6|LUswdfW5r9x{YGL>iZ2>}5J(k-3gfT^lDIqeF zf~u-Qj5SdHUT|LJS09jMeLkPzopCX&QBL+`jK5qns>dsw=vVeWCg2+#b)Q zgd8U1c?|GtwL8P>%(j*1L1#V{W$QfpN5*Zx=Tfnrg)QpuxSHXLRBR?+2BJ!z=SfJb zL%kzQdOA`RzQPGdw_B5y+#=y;* zHlMb5y?d8|Q$Ll%Tj$mw@NKJdMuj6wB#|vQ?0y^Y~-E&uP1l(F#Ek?sK^=QK&+v zVw|t)#z40*fU-n6l!WNY!5?T%Cg85Y+Qa0X^Spmr;`%~n z1mguM`Oe6Zw4Mo6Qpo_Bv^8St$BfV0fxo25(5qc`+lM>!4-4Enb`IPu+zJ#ygQ-8R z^|TaNN2Rx=Sy1FA>%&L;-q!Y{L094RC%RO#(J4FWw4@|^hd+<;DDm}B46p`PRQJ>k zy%idoqx)U0FV$RmiL{jWM7-G3lPXku`{{V-j|q`Mli+IziUjoz#vte_nUM4c=~Fl- zT;k1h#Vc?3i6us8&_U>hc5&$`20EQ5dX)d4-&SJ<|Yk+U( z(-_^=vI9fIf?^P-aP!}NL<;}9$q>;a`SpE4=OC@Q0)4r{+hO8YPUaaD_AvFALy;T4 zQtodkQ&M}0MNc}9p8~mH@2#Z9CFxhH!SwCbre-?D=GGQN6&5Yvx7F&uIW--trXCgT z`jOuW(lCD$>Hx?oXryzY);_m~;IW>+OE7#P*_XKQ&s^wM8aZko|~{msve zda^pc%p==0S~3d#2Xp|4!Vpvf^j%)4-deU&5pnze_`pi`sMoMpOk_1RD} zR<;hv)>qYlrZWYoaUaKPWBKHz`x$BrigO3Q-qvrQ?zyl-T>=ZRL@$56JXRbj%ftAp z^Ysg$X9C?~m$pmoUmqz|kXP;dp6s=m<{Z2HCL-VhDpfz=6^{hkZ@xq-sP2;K${>?~nm(D{1^Am3~=q z`P#^eZuaQGO@12t`jfJtRoSP}M0wdxjt_g|%$^|=*n{sHv`aCs$l*oL=c;(8z7Wb@ zF%>WZ*MEz6PakW~ActB&nk{IyB9JJ8N$RwNoLVr;*MDY)u5z?QH*ROkX98yVp8bOl zcmr9ajSC5cbSMzR38{tpa&u3L7AU+dZOor;tcoSOslg296HMdACc2gzQs`8Wa<{87uVd;Fn>stptQ)-S>uOr(|O=F<-BwrY-#Cy9z-u z{!ZML<^FxWL9*=QouBQ^^O#ZxkcRn?)aU@pps|qs;`igr_$y5Ti&AB70;%kpJEdg2 zk9C{M>%9TtkiHQUiZk~+=%+gn9yOS8W1O@G#kv49evlb|%JA~#ik+2)jrnm#d`LgUCJ?8` zjg;KgS-eEB!b*lLZkBJ~n@U{AQ~dj9R9(+}D`zf2oDhmRa!H(e=^bVaL$`7pGOe88 zxpKiE%zqfH+ckijRXKY0x4Nvfyfy&q@iHO9PaR_5&Eaj0MF};#ildAf$ji(!>+12X zu!Vp*CyN)`&Cs1cNh(wq_!Fha?IcPSPTAUJ9GR)kCCzzjDi5U!zheg zNCASQ%d3_=eQR|sDGeyAhMHhqi4x~9X5LG zdYJe@-3>=VeH9KxE(y+@R~2!!9}EIQ21D!Y(jfK)#Wi6AZzpzDdesRDEaLVT(M_et zZz6#c5CnE*Uv+QXDB~(+_;JP59Tqjhw;M0GCGFAD&nhD%4A?aB>aeE;b;G3~Z!{c& z9sG)|n6=7Wh(4w&cgAb;5|f`$a%|;>KXaS-si^#?W0iT>ePtx8UjlF;kQwV0`(FgX zc#_bn6;JzX+m9)xiW|FMOk`O9495S5_0*!?lRbD<`7yiw_RMw`#4QBgYaL&BKwxR zkKuX#_x-_1zl0op)H?&&=Y2*<4mwDO&hIb=e9IwvMqr(mA1L(LGFvj6{OH&xC%sz< zPwG#yRKi~PNS)jLULf(%^ck?UWJh3io~By00ixv#CBz1%ld3ZEvwJ@Sqd$*)R+<0| zwS@4Kid@Q+IJWh2FwP?b8J;iXwn!%ucu>(BZ$!UW|HTKoEcxsLndXG=e6UNr0R1ku zI+l>a1&<9}^2b|BfGE=7G3QEb9I#3q2Bm&~4yviyH07(Pa?YqamWVS2Zw5PV$ElGS zGrCLCSG%@>@TMNWzgDg9>92kC9~N!*H|?TeA#Q6@Kk>ix`(Mc+{5GzbKcT+ zRi7MAy0T&%JuWEpYD}K(_hdXNZ$8k8SPTQR>;+`-^f&!?9yL9+kpn5iv%_V3*k>Adsdgz~lAU6f=QmNqMycZ~XHY{^ECt?2+f{`S0>Fqa`h@sNt`|r|vB9tzn zavRrg1NMeAznM0`Y%Px0IuLDHWX57$VWqxFlbB@T)e9^W_3YA!eE89YPpKb--Mp}{MohtW;{5d zR_8vQiNp)RHcQ40w%5-W|FPrvXff4!2cn8#AIh!9D3K%1QiK@w5Hzrm%=9DlM%PvG z#pL6k$}rVFLJP@$Gvs`bm$DnDm*+hqvDGul8?Rb*-3kjbq!7_kCh)3|g9Hh~$pV!+ zQ)T5u7ze31pPc({>^bcaESp37D(`*t*3+8=vp>!)Oj$NTclZ z%bc6emdl^im~3j;ac!*rh?4)y%?P873;?X~bRUjGSQ%ptrA6`d6atHtSQ04+c!c?R zyRZL1Y2ptb=z^$A$nBCXSUYz(pZ>fA9hVngZF`j9moPR4MkJe3DS)Z?S?WWmmg`I~ zg<|zM`uX$>~&qabeiJuJ}Y*0|k*E2b;sc!Eci*Qkn8jAP&^p84$FW4-Wa<;BDa zgxi%KJloTcD!VR47$DN2@Fu6?4wFTydA3xt=TG(JHli22l9K8*_qHC`fuzb;{Rc06 z2x1~ZKvY@PX!Fpq^8Dx&EsmDc8UCPYJlfy^rIvMmzy3UO|5A$*^XX(V`zEbw4aoP! z*t@*(cciJ>iP7xS=q9R@`jPd(nUad*s-u^cxO}7K*~iUu0p6x|{;1~c%$MUe_Mxq_ zLoG(8(x8S|=k?Mzx_h{y85{k->SO9!%51)(>f=2*QnNKl6GC+p3Ip{|PSKpIozVvL z2DTawibb3WW{Y@P=z$MD^cm&HlD)s9z^#l95faI|6SV5pJ1dAvmUo_uzx{!FYf27o z&Hu{-R`9kj-oE9wuJ-iw;g!B9Zf(O+<>z1bvVymf;;;9s(tjYvik!PLvg%+SRY&O? zFVbo<6^(vC{CIA{)wE^Nn%|<&*K=7)L0-lS=T}ok=M%Bf)kjPjSs!@lu$l1+_o=AE zw6hq$-Z3Kx5GvC^KOrjlJufH)-aW(T?2Dvvjr2Y`4{7@3^~5Ih3Vh$sr8w10{Z$!c zV5)5Jj}Y+O(?JwW1!xykpY&&&wWT=tUuqEUO(NE+Bj7)tk=xmg>PK0Q(%(L>4Ox;8 z?0bYpqPr0dNkP}aFn%Wg60}_Lda(H%l>bli_L3=+DSmSUm%I8`+4bPY#|lzy_)9{+ z;HnqJ&CwG&`OYDAoUy3B5lc==dg0Mj=jZ)hlhMFk*q57VLgt*Cf2}gBxNeA1j(4}*=T%b4ORAB);BGA!>^52`OFP&&aZJ;Ykm_5 z;y+^vQmB|1V4CD!x5}IM<&rfcUpbpE;12>n5$e`RsC~rqMXkaT!}WOwCuX~!3Bn^I z01-WJ-Dbt;AE!%#OK+OAY80xDNmhS-dTL8I#23zCF|{f zjW55!yhC;nK`4~OzE&Vo1BpG6uY}OLIGl37yR=%ul+t*}zM^(0qw1;z8T#3^YnITh zgHlMIWE{yP%W$6CAVVr(I%AtENY`-;7@F;L9<)%o{&7Ksd$7u}`x~QRP3vb>lgm1} zZP9Wux|u&AQn}0po97`0uB2P0$Hq(4sQ<7$1uV44=LpAtFsJ$M2YmgBwnQ5E=lBZl z|C1Rf8cUcWnr`4a5tYd>ZsXiPd!rk_i`mwL?)-@2XG!>z=|$W5Y2~dfp3OG<3+6`W zsdTDd{SPvEGU+neTZ-s5#P#=rb966%vhc}C46o$O#6R5)A&c>HHTF)Y?-z96*OD^( z)k9yHrqaI*u{`}a{Su_td;cGnvGOYb{%J;if-_7e2p`{2<2FEw4t*tsk^aeh8nHTo zq5waHz-;|D*L=^QejcUg;;L4FtI$>R498DX%FT<5V1`dHum{G_Binm>G|w7|Er*Ez zLTYgwVvWoz=1qg8jLCypNUDqpFNF=ZJ118M6|MOSM870Q?qP=%_Dh`ZJtO-;GFmtI zlT^#sy`(<~`bFF8j7SI=a%D556r|DX0OV7*u0>D=ypC%J-rCx3oS@z1EX_?K#622s z@b!14>*%8qQIm2-3qh*Uiz$G_HLc-~ZH%z0Db#8>G42|0rMFtRnBUenjQ*z$qm!=U z(NKz0;-)GDNzXP|1R-{r)&)l0vEimKZ5x&fA6Csh^9WUCv^RS`8B^kO#3`%*I3~#O z`An0q2=jp5@&H-5NIIKzvB2rG4Ugy|B68k$?Jif$pT7|nKd;J7#)%ve!=p6@4D@}E8*VPQ&+hiE{8G7l+RJf4#w6LD5 z!%Aqe!<+8T4Km%yNbYGZ;0QBfPtaQ+B`1yUixG~+qfj@X&wHU{t$O^UHaOs zKB@N~R{629(8hSRv;0As5_j9?8*I)?!VDSO&p3jr?;}>YeDdh!E+2)it_$2a}9_n!7aOU+%mcwdQC<=M*QwrQEaWyqtE{R z#Lq>LMbLy0(i**Qcu^q3+kkF>--C?}kn~OUY!y`})X_p~KmX`+2MQ`2eZ?CjqF(N^ zOwk*9ETcRbME}a9oCF2rTSyQAE;arTGekxz@6xu>QY($re^~QJ%+K~TEC=bcA6p3p z+!TpS221O_xT_BqpO|b0=zoxDZ7Y93WNbd$bAVe{gDRN}nDpz4sQ6sweQzJB&jB__ z2m_Dax?X7ZID*&)Oy>Vi5-WikfV2=#iVK8{8j>v>b|wMQ@Q>E8qi=XVnIT%`w(-rC z>fULplbr4(v*W|gg|WMGkhH+&iDU*E)>d?2&E(&#gC1yu`fLlLA`s6Uy9I>Zh7_eCpRh{=zqHHxn@J1h5~9_@XqjIGR3oMv%% z*th6Q`FT8P2Il~yJkgUY+p2FA!!BD>M{bP7SZ*YaRK>zj+1bwF5ke?qTZ&`^*C z$jwqiJ{FAk=kzJeUs<8G7M_uZvq^Xo$_zuj#x#Gd;)iDjP{* zQHx@`3rsTmj^4FS4vK;kafBG4N>p0Ap{-|j`b)5U2_ohSg;#;Dx-R&`P^`LV;J=Z| z?W#+f+bQr1)VMVtDsU25q5y&gNk!Kwm*~T7HUqee6YP z8LCWcIjx)_9NVGRy}fbEpJZdWlB95|?Yx;8Tmqyf-9>!>AfgC_sY}83#-p9F_jYJ6 z2EB>@n>_d^>p9*3OCDUf;{`@jWS#}d%coK<0eb6eM=z8$i!s(gX9~6Ib{nZQ3q|br z+Lj3^7F!?SOscW@IYi}IoB}aqyk<IN1tD!Ns{NNlX=rCB0%W{tBMXzg=5i8u8 z>O?GDCX4Io@n=HB>@v#}N?dlVH}2D*kBywg+v0?>x<4)%-NbM0f7&ifzaKL* zZVeJFa~DoNX3~tV?iLBb6x0k*8;E5T5}$NgKa)`H3a^t~zF)i?295NxAIUIu9@0C^ z?e(G;ms^ZGqL*G>uXmX3e%#8HJE!t`-#u&0gfp=_5?%OqW&x~%`P6KR*oHM^2?txx z+&TP*mCUqI(w&UimZ!AQ7k$E{J+dgLr%m!df5mmW;**l(gE2TmicD5lMN&{n(W;Ae zhAygj9MqLTQgb}Oyt&*J+!C_4V4JXSloxJP_=YpJT;JxC%{oTi>|2g z=Of~1any3zOg<{jH=%vo|BQ(vTw2I1q3>73h#*>(VeO|6RO;)vz4J?~ zoRwRa!aA4}$9I-!CC)253cQ?`T@=}GN6PTk{C~N=oP1pUot$yO({-E2)~W#IRlVW5 zrjlP*A01-?Y7o90II1#CaxbKfSbQ#4;`6v0t}Iim^@e6-3mLiF6b0Rstr_!wd9JwVb-ejfbLc9o#h-LWzcG7SMJeljSNrEzC6H#Ons8R?9Dz#V(ZrRf9IX-C z#luA^5sFP5k>Io0?}B_IE(X-M%QOmSGGmaLV50Fv6#n#u;!?dz%C*#eo%(@VE2X1T zgTiHT-7D))qZ0U^zjp7lN4%qWdEuXt+Anpj1#l~$^l2m9n?Lb&0s`n~tSue>ebtzD z0*JDp+&gx*j~bjS1~yb>2M8Y60G~tt(KaxS-U{=n-`Wl_K1qM$+GSauL*CjVrZ?mU z)=2y45LcR!qiPxfJ?ws;|JWpR5FaNNwT@gjM^eI0`!lk)Vrq{1OV7{PlU?sc+S@f^ zoO>OeqIA!vi;QFFx>EL-6TW9-(Oq}|yMa6Kibn7Qtj|9>lT7^RU${-QA6u_pdg1KhhqE8nn5u@Kk!(_(5C zNz;hqb-m(dHJ-slo7jlMfTUJW&q;A{lUvU>IF~vp=s{3L^-+jTG)_m3c4q{v*pX2p zYT%uFTG<;i?RKvNdPap!;ThEUw$LH8OE_$C#yy4oYwHKNHn6&TAHC)^sy+8#k z4q7?*>8VSDSA&p=~Wv5xtE}NN@2$xPPyF>itdV?>7ZHm1>uL3EJu)SBo#h z1g|Ci9iUC)4wBy-ZJ3f|ot32`$o|TNs48c!Q^&s*v_GiUoL8ZK!}Zr@^2?9t&oEE; zDj6d(Tk*4!jhn4mxM7q5$%U0-LC}{xp`G@U6`(5CM2%?8r;LkwG98kn*}TUxA;5AP z7I~zBpDjrH-E5hgh5bvo3nUA9B1mJt$u}?ylI0{em8JO)E3n&RJ1BAV3%=@y<*So+ z^MuL=BR$#QYq>8ToHhw17aA<2nLg{q!B50F$$N8?i+GQpIqZxwtlmlmi{HllzP=dU z7F)IOUsr8wLp(H8ItX)}89ve=MHGRYT1g{r9>S7_DQf%M2b%+}_Z{O7kbG0J&^{qA<5I-#jW3A(m0rnVh>x z(oy$FI>d7kQ*yDsD~b$(rL%>?)d zx9=YS>zN|p_xJbzJwNt-0o@97r6OJ3U6@}JHRavA_}OG@Qb5v8uj%?7DTJo59{YR2 z!!&{MqCpxB<9uDe5?fqcot0!tG_T^KZ0OtoU~DP2=G9ry8BICxp|&9(U79Jrw3N1l z@7zI?6vOwTm3Qs&jXw%tTvTcp_E%oq=+#4}gG1gQb@dMCl{@!YLg#-g;FJvwwGT@Z zoBq_NO!+(uPLw#<{?{D;Riw47?||EGu)m^1qVAklz>5Su z>(!qkq^h$jQ&CosX}b^)eyP>gGhWKwDpgl~G2y}of99&>xaS~@+Z{h@VrH73#VOe} zyS%7u>%^FJfbJ`ZYpLHTOCn(6C+>$Q3^8fM(IiO{`w9%>@`q1y;e@iYJ}>`g_m)k7FTbo7GVKKjtBg&d-hi-2qu2!qb(6C1==veu zg9&#cA|;Tb06D#FoZ+OgUYnz%Ro(v?Gy+_s2vq?m;&;wBf8Z>4qD&+xXy7fYsF-5) z_=@GCpkLZ#W*8?_l5GsWoRjtT7em*}Og??Lm@@sT%1ED-`E}yLAadpN&SgTNV0q|1 z{RGM!_(;x!1ZJmziyUSok8!ea`ot6Masy|2b=8FuC>1p5wMv}9@}p7z#`LGjIPBTR zX!J`YS8%`@%6^t~T=c4yU~nPQnfLCF(NiSE;A(8eAo(d(E+X-vDn0@`c#F3_#0OO~ z{jb?&%K>SgllRladOlpv)=*EuW4MK7zU5HhwoGt-m`7Vid`rhWy=2PzNQjzSjb)1X z;t~s5G5hJ226LpJbmx-Hfe7e7to>U`mATe9cB96&wg^t#BD_jufhHwweylC{*7&_> zJp+C2r;^yt?}?}djOPRrZzjaNWiIGf9b4*BhWjO7{#PRPB_|Axp93gs#H-Pue6b!o zb2MdZJwc5sBZ@uee2|kR#5PSyJ#kq-8H-NtU@!4fBWXva{2iaUkk?pEC0-HR62 z;!bgQEiS==ySsaW6m5Y(aS75u;5+%xIXAh>lbP&2Gw-Z-$@C<*{cIJUNN|c)@v9dI z8jYA)aEhiOLt?mCf5>t7&XcA#^5~V=p;S6OjicEH1?`9%Kr>{w)pA58`Fs`l7Y;;x+GZGk^n;Jt`N z6a`g}IU+Z+HilMJ)@+!_xkF86uGrMLVsrJftLjdX-d!`4V|iW|)$=%5$>}Vk!{H)O zt9@C}cudaR%2L>qKlx1!oo6NTMGVyI%HdT#_R8Pl$l|y$U-YKY%y9|U16677;THAb z7A(iIp~jJYtA!OFAKoEtWXnDqLdo@GwgGeZ0QA$HOa&gB~V%T@)qF-9x!V}Fuv#mcwjN~l&{8nLwZ zWswEW> z-kTaa=-!cQC#L*>#|4npH7~dfrRcb*`uJP%Yr+~UZn}u~ zXCVKmM-qXzwc5fC(sohqy9U)!zFw$ZAp}v7DZJ{i_m2hSW()IOZ*%$069e0flyUNu2%EP+QX_d&9uF^%N-82@x@b}|hDu~=?(2&I z<8flaDiaVv$fvfE$P93b|)XvocC|(0hQp{PTfd2Qx#2GU{_0NUMoyLKb zH+pB@h+y%E0LyurWGQ)9hQ6&PI|-_tLqzQzmVBW%q-D}FK%ByH1^XB1=pQR_iHs2PiG}FOlyT~c3E!-s- zY^btt#L!Ehp4`P2j!UKL%~`H5L=-3d~R<+~zu{ze&lLddhv{gxo| zvW1|DfB}Qs`xXcN^#Ic=ibw864~itLp9eWVJ}M84)lm*#nfA~(*xtQ#bc=ow$Z^&& zT60;MAXG`P=Ua~_OFBqcORCVp-MFRBCY*9__VC{?6EwoW_R2il#@{c*;VdaWKxu7qKJa}9@eOm#@Q zpajB`wD_uB3y`&p<*}Od(UGA`n}1Q@efka_LnJ};7;QA&k~>XSot_w~2MYpC6KnG| zp3BcJ7Hw7VcXM(lb0AV8nEl9>yd2h^xN46CP`1Rp{|{*@Wr}G~0NDPCd;ZApj_LcM z;vDYW$kCB!R5=3;ABASdu&rH*OSQcxFP*0%-@VDFsZX$p1R$fvdf($w!Ud*Ni&al} zN*#NB!n6|heH>O;(*^N`!Fi(W)Dd}j5CYK=W`*p{N-!a4?z4!xJ!Ny}q5W{LZcBrp zvyV!{D7&Sxx`t9ZU%STQS52jAII9~`Q->3_G$;l6w6i*eqBQ%bTF7FkYk4JC*o6FW zfNlG7SEL$VPfiWRU!3p_--p>B%6b&db5sJUYyd~Z3t6^_nH$N*z}^==tc`A5b9U|_ zop>uZC*`WZC0Md${TgUhJw<;fnXJFtugC}JjAn_C+l%F?#uKd^pvTd$$tE^sz&d!-NbxK6aZN6JH=Pt(z4`865NYwj0MSkv8u6YjU!;Y zd7Ix`cy@6y_$OXkDU?8Mx-2cXJ!EC+;b1tNBRZG zGa3ryTE(Nl2EFMU8r( zrJye+FntX2qlsp>Tx6*Y@~2qW=NYYa$l=}Gle&=+>jM%rciJgPV-}~)eRP;DF*1NR zrpy~jcnB8tjp&A4B{=f(D=6d7jxsQE-2RBB9R7h3$Id?&t&nliTO`+cb3HUAJ_V0N zoLb*N5>)cQqB z$%Xls&wrULxPR9-c@!+|qF~S+qO)TnG@+Yj|XbKruiXmD4Uw+p9JCyE{ z>c)<@l^v2wpIBRNw*|+46M)XcpU&cez1>ds%L%A-&Nynl_DgS! zy4W4p7gzC$m7Us3F0|v~;?cY<+T+P`XW9 zx2NVxIpt5PE)Qu1-}|28O>xQ_WjCx3O5X_d%fJZuq?96+tMouoP6_FjP2p}_7X$A$ z9p9Maz&TZ~Sqw9)4!`@HtG3zPJdZ9}1AL_#r)#1hiQA2D)`v7yCsmstAxTKM7o^=1 zRlVcX4KQWWN!5-gKM+Ir)QDy|I)0m(UfQ!9lQMuB`~&ggXCOpgCpAX`h{qEE;+wYW z#-)F)tQ~g7V>Ev9kn#{iN?jYsh4hm^Hr_T&+^znUP0^|fh20-pz@|z1B7@oy8w|1w zU>H)+uSC9L`R#rppIguMW3wg6`MA7AHBTMQk#ywH8+ zi7&5)W7;Y4Q=8_KPq`NvaBK|Khkrk!FZpgRSX4>G_0Uns3G8qhT1XXy7+p@wt=wbQ zpqTUB-=Ic+4Q22Lm+fn~I*Eu!6{0T~^YbS;`NGXVx7Z+pQ)Ny{D7*h?}4&{TtAm$`t zdr0Xd2R{UT?-H%?yB_vlU}b6`-~Xq|ihHP=$|AYdVPl(yl<)B;0ap;uBG00t3UqM@ z0y7&?MdpK%9FbnPhkTgMOx#w89_&ItWsxh9`iq|ud!mY4i0YY> zhe$W)*OV~sjS_0K;jo>OCA^rZck(VW@tf65^edgCC!LTA+0%3S0IV~H)fnH@J|_ba>9?I~%ER$uN(n5j!Hfx?WW+G${|x(ns!uQb#( zauu?tb5uXo@2~#I+zu5;k!vOr@faEE`hGfw4(YFNnQfmC`#fc}B6~UT`Qj2GXMW-O zswjf1)iu?a@%MkBD6p9;;a4ArX-HBCrHJYZj14MPIpmVkhn zJc6F!IpVFccqQTgV=jR4h^Vu+|6vev^EMy|N?9I_(@Lr(shjlkrRvhNkxb_IHs1|W z{6-l<7bqbC{{y=U#J(!D?M&X?N{t>Fk&yrO{_>nSc;iyd{TMvUDImnRJUV@V{P@pF z{Xe83gHi7H>Ce`$!8fb`_#tOHyFZ#-(IN25n}-XF)yyNv&8I*+!TZM?ZXcF&z5lDe zYWxrUgorGbApc)`tBsIRZza1}Bx`Cq(_)Ue2nE|AGVt}>ZOdz5lzno#!F1Q<2$d-f z^J)$$IBZ%e($N2FKdK}jU*p~*A{~y#7V~!6SkLccpr6lJ-CfEY!r&|RcKwj8NBsxD z;W0F?b2GTYLsgj6`Pe_JDyM)f5AzMG_`+6r{xaJD=bh>F2!-G(Y@R^-^p*{E*oVGb znEUeb7M(85H2-eI4>wE%(J;S%{ncZ3YRUf*iZ6Y81h}UGsCXF_Xd{d} zvUCj|qoziB|f(^aomaFsoZ#3S`vgr zm`%;Jn6jmglcAB$I{-EMY=|7x1zFcQwbP{6q!zy|gGs5NiA3KsEp)a6D!xutCV zYU)1Y(pTu>@?6)JZl|R#n>rXx!(5y}O0;{9tcQ2={*PqnVo;t85|og3%?*#&BG&ET zIv&K1t*wIBj)|=i1Bwb)ix7M>(kAJMLCF7FB+NDbp(;$r(N~PCb}exViN~GN_XIkw z2XEH^Jt@;m9F#f=bMZ+Gn86()L|>Utt~nKz;v-#P>|_GWqTf=)VsB z1UPdrt&2vasieYA&iWz$H8eeg==f1!S}}a=dyD*Ezj@U9rtRR!>(G4i;na zSNadhe`88a6T_f9nIh)bEHc4z4#8ZKr?^|Ogct`W9C93J!L=BA6dZhCD30C=7M=b^ z*gn6RV`EV}j>~%Q?G|MpvTUtd&S!rPv4oh-ajL<)p$xsXomryI6}yg`720h$P5|k3 zwiZrZYZ4ZWs{uW^yj*2(9QM-y%9qKU`(D-rcI5^A=%dZ=``1(bdQVGJRy}BRk ztPL^;mD^Us6zvhpo1fnAsGkb=cl0sXe@=YMRxH$vxJULQex~MU%_F&8sw-XCl!^$~n-@7-a6W)|JOm$xSPJ!Y!xwRd1LkE&Ky2cXlmXc{!yD0uDSD z6D>Vr*SJklhB6*y11e4ek{YUkmWX!QB6XKTb!K2pZfzJKEmSqk55Ur4b-YLsvjVXK z#k#^b;r|0S?Vx~T_I}7-T5@iOk9Iu{`~Ch02ZZ%hjh>~{KAk1W0udlvkx;J~Yf3ip=A*&iQh_VcUW$pfG z@L!zi(b@i6WZvOaD1Q=PHjzoE*-dDzmgyD~mc@%=CwJ^NRm=}VnIUsK0{lcPv;>^- zd_H;5Hgg99lA@vX-4>V8tFAKDe0%t@!}4F%M1zpGUtZjiHk8ZCXSVgL`dK>=QUg20 zzfI}SI`y>olP(1+Fte^ZK*T#+_Up8h)vaneBwp1?EM&=w3AwuA5I1K(24CNS>{cpt zL0<|I1%`L9^NHclPzC0w=DTtK4G;t4ZJA7;5q7F;_R5@!T7%1qq)0sX(EP#>eA^xP zC(aGilYsEIGBVorv%LHm8+TN~a@{nSuNv_5A9GK>CkX8z4@_cqZhp+z=?iGmd$Kim zKUo=NgYs4@DLS#cOZbfu_9ViQI~!>4Hptr-kwy51^$dmsXCwd04gJcG_v#=yc<7e# zSz-VVy5-V9Ezq|6BpK0l4Fim)z2ZfM&PdQo4--QLXE+4vSWXiMWk?+US(3oPwmDFh z1%!JECkxDVxgDE)zQ|&|;+_ySDKV$U{r>cnA?joG)eTAtw)Z#EjJc1uqqT-)wZEA7 z0gqQNTmpRj?+j=2g~tD!>*R^L+*WCmuQzp=?|>3t}Xphd13u z*d^6mpPF@`Gyk;PYEbqGhDYkxMrUtG_zF(yk9$pE3<)do>g=qgNT_^#NQJl3Y*=|% z=DMKhfgS>V&Y&xdV>dS+At`1NXntl{@?ay|Z;XRYP%Ixi>ue8jx2EzGvm*^H8JFCX z4wRVbrLK%E`MG@>*)-MGk?0Xm2Uciit`IO@GSacG z0jP-IjE|_u%hYB5+U82>ICkm2$$Sv7(2v%4t5(Ii3XEJhN|;Pf_p5!xELp-i2`gQD zl7$eKwRPp>Hdfc3<3wRIr(+_J2M+j4?W;a4DQLE|9!IPv7ZCBpE$SNSN=E#wD;DF? z@#dpki49aOEd5zCp7hE)4w8QoA+4v$%>mah)#pdAI%FsKKJxK%nsIcIU!!u{`iE6q zmew4KAaqM(t8_wsllOnwLqYYG9dSl5k+CUs7M!@`JrF^pZAu|&+j}?0Gi?zEWA9)6 zNmjpL9@OKfWW}mKw0}5W3JxhV`;<0L9=#JfA@bUkV`s>0!UXCA=#qSY^{nr^G@<^H zx8F4fx3BuPfvz~am{GGoOCvdSiv+*$=oVB|?>L(4t(NAWlAgCK+A5VFwpm#rqU0T# zXbDBC9;y6d&kREB!N6jz)q52{Z}$EdPEyhVaoRtIqxjuOIt1bE^a4Z(?nPFA_ou;b zrV^d>iTaSKN`FEsO7(wbHTh>2S)NsS;;jH)vo;)sWJC-b5L?0r5=)0YwM8KMIBRZ` zKC*i}%gH+q*b4~hlaCOzuQ+NKlOxf^-5ay2Fn04g)>!$w_ONE5my}j^go_`5J5y-b zv{f9g~UqtC56J1v^<`+BD$U~G0`Hd3yp0%Dl_?I*z&t3 zR;h_x@XGl8UOY zNo?jdi%|%kIK3sf{JX70BW_FX?l^+DwV<#w0EC6tI^l(%?nzmDNcx~&SXW=IJO!$lP%6e{%2F2cP`{KIe*e)`_j2(KwF2V-hNi zZ8-F4(3|Xawrr)oy)2)fxk2r^QRaB2Oo`HXI4qm6wxc}S=x4XP4|s*8>{9&;kUuqOipAwRJ>T{xsnY=>uuHkpPz&i1x z0S^Xy{RIhItD^i6?;G@mm{DX+yyq9kHBV*MjZKqY+5Dh%Xy(+Q3xFDPX+8EpN`pd= zc|~-X5^_2=Ee7WKm?nkvo_1=YP2Xb-dAH9cWq?)!%Tx~Q8re+It$hhTi!0j; z-K6W~tET)C$!AszqDf&>i%)YUppLNwrs6PdBh+4L$KHhTDnU-du zRkuBMgV^0%E>|`$_X)ZpZ<1~0%ckPNG{#wkC)sb7Ih>=( zi#bfj@GeK5oRX1xWva_q`30#x_+XY+3H?xpthYTc9hpG1oSLnzVb@I5RJycY7xR*6 z>U3lYQT`Sq^!)oPHvfoK^~gu|>XGZHY{{ibI!mGMG&&y$y~9`-HVccqJd-keJ13_S zh0m^S(^KEglrS?PdH|_XiabVrZLjR#go}m6-m_5;TdBH1i1$sbM>ofWG7Hz;CQ@sv`r& zvHy^YXs6u$p?U?kUsjwn=q1oWG(`qo9*Q|>$Ml9Z0SG5Skw#k8pQN+%G5&7qz3UKx zHJ7T*?UVa{h9{d&gGijj4>qitZbP56>aJ1LBI8hT-!&wVYYa}lazf-j3}DMb?vQdq$~pyT*j{+hUcBT@CqfMD@|wLeRj zUt}rOM}u=lgCEAV+!tn_EBH(3sM`5A%Qq}_T`!E6y3R$Of9q%c3foLl8xLJ{W~pRz zZU1hui>r($@aY)zrpAN2t~b1AEhac@uZktdnClJj247zU4dxQxd^VNJQ-UR@LlySmM}3N8|M*ti>=p;koG-At;<=;X-|3RkKFNE)Hu56Eg9?{tkWheTxo7F`$L zqe_z)c)&~UUxi9@?WuyGzBw*~3jTp+gCO8q?C18MBYg_WQ6*w(?{%LK#uONM!g9Fw za)V$;8oZNOA;Ig7?J7=Rp5BMLuhg3ktiRb|-J3*C6J6s%$(ZN#4rHc#ncKr?)LOru zYOP{+kUJ#fx76NFQERq!&X|45ZPQoTNN{M_{#kW_V(?A#OU+B=ll(vF!e2ihuAHRn z=?u!{PaPY8T`Ykq4=rl;GUJ4KnVx$g2>C^Py%A}amhahMl!qQe*7)aVfra!owY-L%XnePza9DoFFje(ckAL<9MOi5_sA77_)(*5 zHrCxz&p_nHa=$jSEwm&5eXkmIEu!?4Qg+WiGS;uq9@zR_#q_WKP00F~gR*v4SnaH1 ze3bwpde_GKGh*K9Z-K;?uYuOe8RQy@e4b1Qjc`#LWedITK`c9yI91!J#OB0m@G&zL zgH{tmyZ~X$y7I{SkOL&ndm!4ivc3O3{(1Skt#D;zuTxZnB8Z zdW*TWGsUOhh+(PfsJ4ae_J;^6z|NAM|3F zN4s{i%hh?~8ER5ry%1WF-B*9XD3KXGxKw^!s(agw|vi1 zsjBD-{0k$~cCXts6o)@DHAN7hT0i)lX{q-ILQ2@{V6C?etk_@FEHsjUu79Y?YP)G_ zx{`s-2RH(D&ga2|X zE)GBIo(A6vOi>p>j_68RlrI&+rqZjcY462(DvH{KglofogR#4|<3q6=^gA!NGCq_f zvW@(9ki?-X8$kL8zolo5;H6@1cImkT1Q9eMsGY~V41>_rR~3X{qCpU`wPWYP1{Iwr zS6_l5_5UyE=zkFRf2&V82zZ+=RO43vCdOiAQ{zRpL0+}w)kgI3qnSgYhT){+T6yQq ztjDcWj$rN?0`4LW04sjEY9>Fd7-3VlWg9Dc5y9>SA)Li9b_CC^I#?>?M~7VEUARFT zZ)VNe3x*uiT94sU zcQ!T~C<22$txX-~(ljicW8>1P7?+|>SxCxTABs(*MuEMgl+jyYvU^5II#MJzf&pks z?ssLV6P}r-HRWbjb9XpH}98;Ro^6f9q4v0z5j)6+73q&D2-%YM$H` zPBj$T%wSFk4DZ+#SnA(#cKStbGM9t4w>Vcat?d|0AIpd2dy#ELoVul3X*ez+bB{As zJdMLOEC$HN+Bg>h>J_YF{z%4L$*l zy3D9Cv~cQNF+BB9a0|qGR9MdE3vr~PmTtxduK-GgG2d$x!-tPzO*CF`?IWCGiiC~8 zpMFHySEg8-8lmUxI1=k@*Y4@jCSH+{d!HQ)MiUK@0xQo2n=-z)Fi~GJw~MmIzej~~ z0IG}^Pt4LUo2d!N!Qh8$QW}<{p`juTEqL^bRsZeaQB2;SZ?bK-twVKVnsJv_W+y9| zbA6xpRT2suWT_teVQy0J`dh(t(SAgbwi}bvQ_^uR**%bx{a&x#D5|&G`Y$1$9=lus z+$8yz_(!yJrJr$sDh^&fvmeYX=BX5yUHNjFn?R!d)>JtTE+L!^HlU;2sU$wQ!QhO(MOes+3*tyvoxiBx{o2{t1#fIQRqq8 z3HpSsG_A~FT6Y8>wav$YL)IZ7fLi|yQ#GAC@nV6<&k^s~8SgI}^KVt+B0iHw1Vl>@ z5n%u`RE3o+8qjmM}q<9n7$&RMB zr)=_(|4uxi#occK9PNqNYryoX4MSY~pXH#d+eJpLD|c#mEAs=rfYVR!S)VGjWa&Px zp#2*HsAjfCU^FIAU(=6aS^Ug~Sjz?eBI0|Kc+oGOTmf%=>rAm34E$g79QHpa_N*Ew z!B4pzptEcuA8sW#H_G!4#Vfk)cY5*ZQ@?Sd{8%sDE)C+FoJwm_-KpXf4=Z8G+6A5rO7=~o6B+`jMN z&jb+X;Q5d7(6p}5{0RS6hELZ#O-pnGRPf3^Sg@UMFmyTCgBA{$FZJ~cW({(EA7pee zCeHJIPB;s;J#VOR3e1V1|8DIXPOCtv8ZXSR=y?AwU)BP3vPOm$^(ngO-G)99pkL$5 zpNnZ#7i#aG2#eEi}wMdZPkm0R*`C0j=|hXnUzJ1@WMjpggDZvTL* zzBJW1Vl3*S_IKzWW{JVD3qU`bD9ML(=98;~<^|6Czd-KicRu8j6o^ zw0WsH9E_W{?-|;MQWt|-BxI)Y$A8E5Gi_w1p7(nE>(dCpViIY2U+5ztWTf&o)kMlM zj;>iTjYW|ZZQi`(6NFNpsn+ki%86G`?kzU{ONK>x$PYR~(khdAu@O4VvIQ~>d#TqWhs8O#dEJZY&&&D}qn79C`O&<4Fk}Ez z*2VWdDMqrT&&BH`xJrte0CrUMa{bK_qqFUctG!y-6!>JnenEDQ#-_5$wZ-b0j+Lr#F_+N1yo!y97MVT@28O7(ONIDN0e)zKSFKJ`n z+zhhSvo1pESA4Ojxhse@J+LF&{JH z8uqhyfReGy>XJ{fCXKk4!8a!UGGlAA$X})K+5PhCP%ffq1efpfE+N^Lqyk`yLWget z+80VVw^Tp`Y~olUo08epwcqd{tunq%53nJnHcjjGC!U0}NSj?nM@>dmU*hkw%6C1D zVSd4Czz9+)!eWjvrvH4Pa)h-jTU*!T6DeDtJ<{I(^;NvXNr(yPsx8YTudt+BYQ~5l z>rNN*27Ry2@B28qkBr-~PTiK;lk2|H#V+ZOI1(=XZA_q~`t}b$5&yzI=;Zbe(94xpxGLh%0u*XcAvemhl$m*Vt`v;C7#UNTa&g-%%91l zu%5eDp&NF(-H^3E>triNEauFZm)mjXNZEF$Asmx*jS}D@5mH>hGq&r*4@a^e@sf7C z>OL!*E07C-Qr}n-u}iM2$KY^6AiBWAKE$e8fOW7kmgD)anK>HJWv+uviqe^~QCZ`STVf&5ljU zF&_tKH7zl7hYM-w_k-xHkaDVeQB-?4kLM|bhyxW51c1AO;UHDV!lXpX7H56!bbEP?hgJ$ zY=m8(yo(=x;hv%XNQ|innQ3ERa@iVmreQYQxsEn+rDY&C)cUN)U&9vg@=xzFz%26G zn2zIu!hL)?RnVQq2lmgZ9)CW6<+RmEL*kt=lQ|di1|w(W`t}uKVct`1hRO{qk4472 z-RKuf-HZ_BaYDeL9mnfUvaHSye?1i)ccFNy9d~>c4VCqK((kL$zq`H8f@ro=!Gz_Y zA>H+lE(F(s)fP(wMbS|esbcQ{)Q+rRgATSIyzm1V@1tL~tm?+DnbLP90$L#hT`U`8 zOa9J1N^U9Ew`VEuY3PKPNBD&<4$PX|TMqQezJ2`Uh#406^|u19TH986)nHAPxrP&~ zrs4yX2Tx*VU;cw4-z>iAI-y>U0a$sZ*Iaod<|St@Dg{Gw%cQnc&my4k@k}TEoym7u zrpj1M5+XoApyl5gP6mED?yK3xBrn3gmPUrC9No^SDifFK`%fh$Cs!6&Ki`{6wcsq= zOyuvZmq8A!5=k2I9Dj6ZWfZuItLDsXW{qjK-)Hcc4!fr_%Sa2!6P5h?4+%4|_dQlk z|M-kjjq!^zH`$Bh<`JFQh#;3qN~dXFQu~DNoyrm3u9+Iq_9cVmpq;1ZLx+UF1UTbN zN~Oe@Tjz%C6=dLuvl>r`8yTjYxo?oe0hR#0F@c;A1~l@Ozma2Bo4g;Xajo7njXFG} z%d5Dj75#VZczLQH!7NZef7nG0)8)F#^(UXm2NA7?+BO3ky-@L zkqG@h<$T=4e(byC5N4{BxCjEjsm%e5X5>49JahzxPY7L}*>fU05}sz{;e% z%@569^i^2_*X~c}H^}o=$(2v}oKT;cP)?2`Xid`6$>MarQz$gfBL53oWtII?Q6BLL zrI}G#tl7}5{7l~t2LU(tm&UQ-p)Gn!x<%^n+Hfp#BX|yUA?k=+gVvGE*4s=H03LJ0 zA9W|W!KRo|bw;kXBL7ngQN;(TGe#zXu&z^^bok-X@Tvch@H-(*%k(coKQa_1Xh{-Y zo@`&QR{lfc%=r`)gcY_*J2??h>tK-{n)_-ArCfwu6lI*Atx@OwP8}M^Pfj$8)doIe zy~DPM!59^X2scA54)>-8=LSW#9lwNT1@%4ZIB+cQF((szoO(x9K#G}c^J82byZ5Z*=ge? zE#lkK$cQL<`TY?eyXyV$`P+whx9=*p{$hrg)c3eFyYgJw_d-|jvi@cgI$ujMRcj8a zMiTtFdmGOwjgi^w=FLL&yNfjP4$8C~!HgX_7Z(rabXLDPchA$fsnn8ZZpM>oSsgsh zwT@_|a^88eh;5Wh8eX{hBQv&Y_4bicIf^|B#$8fuSkB4ZGy{&~eRq5;_m#=e5i#RGHkrGVC%aW0*^B z9mh>1nCk{70tn`a5Dp}iX%r#o#90tylm_#&GF|C!1|q9-Ad9}AdZ(#|{Po?L>a@^X z|Gi&N+d`-R8p_>r2gO5~f_h=XPl9m5;~n0`j}~&g>dqy&1^Th^Ui%9|O(MP<7nuv9 zqCazO_D@t040#0F@abM+%4FxwmfkAc{XFYjk7+@6LK^FQ*1zCErugp*-6r8 zNQz>O7ymE|#`x;-YzjSwEEXWX&$lDJu&8)jK8dnv8guVv7Lj8ZOJNXesk{d4_(k)c zD9#os40a^@F)D9fGfe90(a(nbqX8xbU)J09khO^c6oQyl1SdXO0vem20zZt-Xn@sj z&GlGhw^?wC;;MPn&<+Zu3F8T6VZ@`ds2^iQR!##rJW{OxJ(C_6NgSis53-52R>NKp zk<~SI#zx30tZ&RuPxU3RxT(FKCoU`^y+sVrkQ%c5%+<1LMHkV#!01>O}FbgkOMlMsc8?N>LE2cOa&st zIKo2(_7QNR=-UJ*VI)47n`zqRrB!E#4s9#OiqP=U`9v7%r4j;7n0m8;a%V01A5yV> zh@)DWRLyJp?Y6i>(c;r`fgpTeSbHxT~nQM_Q@d4~_;7 zmra$x1c&mz56dKCJf@1kp%Q@3?4K!^Fwt}QY%%mQWnRogv2~TB-GbAh=d#r0zFKs! z+MLHiJ4ySrT0Q)&nm z@s5vDWdZG-{$wqPGW@Kb!nOR|x00O0YVw6!T1k2&Nf}O4(gtAVH6O-z zXiSM?(TjY`?KbUbD_>VmTvZ4)RU{|t({LaX9fOK{7)nG><+lci-4u!sy#&+mU$UGA^0sc!8BweXg#el}ve3Yzi;WR1Q2$|PeD6#?tl^#Cp z1UH=FRTfsZI2(4?yuBKhq$uoRiBNw-I%{bwhL~X`lo7(2$N3);`yhAy+PY!8;WXFm zndBJ@R3TXtou9TJxtjVw*6XzSvuSP)$-Ay~KtTUWE-ovh9~2J%ctbk-vBx`~=ZNqlEv0XDsbOQRde+eSnZHJKUXZ`RP5XfQk*5>Be&&qrQQ9UjBBLGeC zRtGF+>wk8^#epF{{^+xhR9@h_eu3Myg>AE)jg!rY#b7K`e{TD(WK;A_43o`n?l((b zqy4us1gUJXNcw06I#(n=T#};q1@{8n!2cmBTh)(FQOT?g^1{cfLd^Ubm@d69^kuMH z)R^LVW-3#JKg=+F`OT1peRRd_I3T^|%}EbiS=w~^qI%`zi~DsZol%>_c_tv@OCqBU zN>IigSBRQ_=WK}jl7wL2G=NRq0LrVJZNV!n8Bhet!`)%5Q&HnQm?_CvX6cAEO^byG~ymCS0`!DhwpkBk`l@S8GN2P)h-a!GJ8G8Tp5Yk2XKhLMHmT= z)J99A>ZGAK27YpWXPuL+`7Ymxbvo`dz~$+;4JPT3G7p~0hkAFO_eU{b8C_XMzsey> zzI@Hq%c8#(EvWTr4fn5Rb%S1MiWtT86X|CHP!$itt_}uwyBe%179`DgjDyRmY&AHD zAZC^7ompN*8=tJWknsMKEu>!rQ=;J~q*Y*sQor@b&%Iua9=9jiQjx`~{vz5ShSp-O zH5W#(w`3B5<0ToZFXKha>-y+HlUU1;pcDO#?bwNBoyr$#`?4Odlb2Lo;eS4VF}Aqr z+Y&MbalWryUfk0X&JPkO;b##yQTBL~2B}5oIUDNN-^|wrq-m~Iw45t3HZDg=tN7a9 z$L)HTwQ3eVhqrU_Xp^zAK2MY6U&;v(PF({_E?sD>XcIp=sCCpd$d0?PW^WI{=@{Co zcF?2wl}x~^h6XM#a1XuT?^p~A&$`YMxY{Htuo(XkqKClnGOZ@cLEjmGYA3scb#DeX z5evsRD-<@>$dLI@XT1vmk8@kkh4loE+KD%w9kW~gf0lW}xW#{KkN+XT;oT}BiWbP7 z&si%;LCo%h7dAGFp9G<-$CmdAce&tjjK-!}k9L)U`Jf?Omw)U=qfylx2##lZ21yf4 zxu{-c{j1^)#x6b%c_D9NoXtkzZ3@*RjONNwi9o? zYk=qh24A_tP1vhaYh{Oc@fjU4&ja^UlW*g3o&2(><0OF&>c<34l)6tn{Tq961@3_^ z840HOD&AHl{7QV7PEXfOY`u!NeZG+2{z8h?bb2U_))}br2GxJ@4WDW!Dm2~E>QOMk z&seO^K2FR`wQ1Q~or6K|+9^f(t4hDog-vK55pQ))2vYq+=i6EjdT|kGM2PLl)mRw& zi>`FL3_pjzZ)>Clqnfw#Pb>Hn;ZjTD%?33e;qZkni1?QVO^c^-|0FUQ&a$%@|JWDF zmQdHivi?|-H&r-$nKGvVdx$xrih{7qKxy@$(Q(0mlZSafS^f3c3oPq2+e0~Q5fA=h zXG!!7DAk@^uq}08Utpc#w7EReydaq?=DEO)kO@m_=c|5aBvFiZuVH3}(VtZ1F;Gt( zPO6Y@W@Em|=x2w{9Gx8`44o-Voc3lU${rjFLn2<6${nZm&+p~F#*hEnfgxWiZ6Qq4 zlUahLU{d~wY;KFW6qc$|cSbjk_g&>p-K;J&9o>md`4K7VCd^lPUFan#32~XGWkCq~ zMFygTqjRyjy$7Ttibi-t(6eCB z%vWR;W74)h$Pv_F36&_>Tq5=wb2CSJ>&8f|zZLsePQmyp<4c*`_rC|PiXR$d`4xfQ zF49l~(8W1lok~G;9^do3I@A`bwDI|bR1w{uW7$XB{{~ehj){SNz;b`Qg~gf2&5q(@ zPCiFw%K1b5vdB)83~bt%AG97?7Q4tzcT@D}`@RK0ZRq5|YuE@ujzN!g6Pdh8iA84Bk1L2Jzlt#y{$9N6vx z<0k)^VSSVed^65j%9V|?$E~#dqWe!#R67s1ASQ!UvKe8__JXd6xZl0He4F2_YDJW$ zYtQQLkLgO7CQ72Sq|6xa$pLR94@p+L!C!fK*_xLg2YBEJ_wk=*OM`rEW-{|sZtM3X z*}D&W8WGrU#@+1XyEldH4t*p;R#DNt@(i!@l5%aq^60*KqlhQ>mv(88TXeL>KS4wA zRkBpYL@^N>VWNwge@R;ywkO^TUcBip`!*8L=UuapH zb7!MZ19Z87XikAl>pYbxaL1Kz7#-J1e^+nm@|$Y^32MdO{y$88Wl$UKA8jZUC@or` zxVuAfcXxLw?!^nmi@R%!Yazv5i@Q4%iUgOEV1dAU_kU;Z%$-a=(BUI;)uC9na{Zaoq%r#RigTcW z2;J3ImAr1$#mRuof!bKt0fADl)MfpQQ?&pxSL68`e?G^9=36~6uBo9w8EYB!d_S;9 ziv|O9I9#6YncHodK=NlW?O#lX&u>_#Mf+pjlF6O+cj@KuuR11?T2ZQ6c<6lo?)hAW1+v_kJi)KL1_) z7-}#6tQ?e~@7ET4Gry8038gVJpGwTdg4Gx!(d_7S2MHIYeX#Cm0z0bI5%xItlmx@J z$;th;X`$BF2&^;*9)+I+L~$_(X-n-%%7NzJzZ>U=g#tYiY!cJk$}sE{KJ*((@ssou z}yXbYHKjP`j_It0DaGQbAtUur%-U85yX-&a%68 zk7pehG{=3N-gVPE`SLkgVd>Rda#HySzPD^y`~}5g!|$vEAfDrjxV`%D!WYl4&`+~3 z9*b(ttM1)(l}e62LUD{Lq|8NGdNirCPet=Eb<;0A1u{-o;qUit1&NZ}0eS(9HL418 zYqBae$yXEOq+D!6!TrD)A6j`1mL#~pP_<)P6tx>f%9}RuXdOa~s{iN~gR+O+p+W8u zd!zY?#e+$SS;Dl9(TVM3W{%1X1yVY?YIWK7r#So+BDSVqn<}S`d+XeN)3%1mzG-}V z34ec0VPVq-*S*+evtEure#~4dZ@!g{rF*R$?yp%$G5D5t{J7T?YBrnK@UQmSL>iY9CNyK8k~^hB)TBRkTa$q+6Xv>QjC&eWhQ)IrGC>H}4Rd+J&lb&6fGF*6`4F zjzwy0L&82O-Kaq1NvxPT=sHx82;}Atx~Kp^@Q4%v7k#Pa?5c{j|zSCh5z3=cS0kJW%$07Bz6 z(#{1x(ah2-pgj>Qo$5OS15n@`8%4qv&o=;n7ek1r=iBr=-g#15{<~YmyDJPn)I9`1{ z*{WMV*Y?(%&Ewy+O-y}&?Gh+y=k@+dIVsY|b^O`iT+H)vW8sbFQDQ`N8*JEpPd^@cfb01j`6PKOp`i>Z;;t~LltD=xxWSIpWup708SqS`rOIuI z$xH7?qi6T)Kaibrs(MDzRYKAP>eWIWe2h~J&fQ%@Mj-?3HfAXHqi^r*PQ%Uu^Wn0}G1DIy<#GX@C2+MkR(JS(Al^8sr-9?N;vC*RKi~Pr4NFOzQ~b50thF%-SZy8(h`=`3~aH z$~dIm{EmxUcOxw<0UCnBpH>=XBkr&eI8Q#;5i#uddN@rMp@oFURwB*POhD!b_M+sC z5&1}KA0O;xY9dhJ1`e!WY>js$Q$nl$fM%&lp+QWCT79v}9#;Q5^0cwkq3v2EmA8a{ zcQod~(DxdCupGU0atZxt+!WAIs~sq-iL;C^;roW!|5>C>`l74Y>XlNO^ zvY&T%wwi8Fc>HQLfSJ}k_(AVN0v5O7Q;e9NXX_p>GjV!!z0omNvi|Dr`nTgSVsye% z;T2^pN(!s;Mds|m78Gf{^-i<x>QsFb^QY`b`=kOK=nfRSJ>u@hs>n$ zOlFn;DpXU-{+FR~aCWxR;w8nA`cm_@DSg-Cvm`_0Zb;PLiq@(0QXRdG@5V`!i~*k2 zloujc!ko}yR#mc)wxv&~lq}Ug@stP~_A-^@%4}Z#raf|xTygCw=?Awav}A;zd;D%G zFS#;sSVTz1H*$~`EqT|L55;#hDb3oM)1AII=Z|TMjgu}SO5fJ;)i+isV!>ohjZJU= zbZ+4XMnd0PeSI~E-K`J9(zGhS7DDWd76W@l32wVv6=&}*=!CISdPPk2J7E5p81qdr zn^Utye*%+=W!TNVGil5Le?v9b42u+6NiyNDt>Ew4(>H4^lQ}XcE-CVrwz_SiK{Z@8 zT+b!^!&(O4W*U{vm(z9+=zpYP3Kt;~xuwT$b_B%eJ7tZ2DoW@r!m$IA{sXCtutz8? zA+}Ku1g|DmhF)q>Ubk>o`PV*IrL6WXosT_5VZ3z}|8cmC6v3=PIlq$e{KbJz`?vGq z9wvKA*w#r_GasD%x~Lhyx90GW?=eE{>XBvZr8M#NdXx3xo)CX7>dxKI=rWO zrC%X^<3SSR!e5oVs{NDAg`;zB9GYX830f-eQMd>g)QdinQ1oL$zx2nnkqxf8*CCeS zXAn#i6)1lTBpZhM!xa(~u(f&YXH5RR&fbM)4^{;7#K6@3ro9z*%ri^Db0F|}KU|C9 zz7<&ZaHB))$-=2a#K3a*G9roesQ=0%BELG-RjaM?o9Qg5GiCin~7Tbq~m9bB8QAF&2-22{QTIr!q4a}$oU))@<)68puZ4X_tH8IDS zlJ~8QNj!AS61Oa|2-`;=LU~6-=iwf|c3!NH2`SW8x_=x7d5w2+f=ff|D;Z{ zuunyC;Mvn;MeSIloXcqtd5kZC+cKkvTJ{*uFu=Bz1JXCQ{GX05F3Drn2WmP~0&N9u z$y$w=LGIMmdAro9DPv?wngO;|e#RIH$gb;Ee-Q0vS5*5 zV@1x6z@KFAhSsM=UXaU|m#ZqrSE|sA+5br>@sJTJ?B6j&hisKH)H%f)br-uzD~y^z zz?cCrk_{yGcUrw)tkgaTh7`>JT0@DaFT@o6ltBp&F7LSYb}rgX~lTF z9EwkGmyN>jA`=5dP5%77etSxsUeH&KSbY^><`QoZ`gprXSQ$2ws;>4`G5tOT9?YvP z;jGo^l;@Mzm5dsZ|+xtu^9Bz>v}8N(sr>LXeGc~5GM+etsxXBTqB z3g8ry7VMd>i?=g*+dT(h!qc6}xmx4kVlRK21){mJmmlgUeYje>YdBtvm%T zcXLe~Zr)(u*pjZEOdi(!MfOlnK+Zq)5$l5hg%npC)EOGDgLr@y6vC|__K9>|;w=}G zcz7E#!o=lt27CLBSeFXD$~gPHqx@QN{1(6R?hAP(xL*ukoL=;TO{CmEq>08?$dwyy zN&AyVqm#(nk>YA9ups1Xy&PyzoUg}MBq_L5fOY-y*$Szbb#8EEUnylX zz-VMj+Gd~*b>Gmhq(r{!1H zr6yl3JiA@Ev&Tf>G+g?zk(63buDK?(zAK)7ECp21cq}JyYx05XP`Ezwu!i+OpT|jV z=S~SQ6q-A``3|`XHkCrDMbUTB|C$?w{)BWYfON6LRSWgS39bP`LY?fPt(y~lu%uw^ z$mV1wBS*rG#EZ;iqP_NBpHkCKrW&BnCT@Pc!-qJ#DmfC@%=P!;<9O!-gk$^Bc^tT@oRn1nQ6+LoNmOVI4$*@X!VZK^LFXj`fI>Co#s&k@`~Fcdj& zMzkU`w&aDa5#59B5|vHObNg{+{}ol3u2vx|d|PhOJ7k*kqyORMxLf*|uzazfGg$<_ zNs>EWhnNZr?Q7oW5?>)fYrF~R)5cWH&IJYF{?P_sKLi@3sCWUH?FSuGrNguMd~)eG z5PSKkU6rc6(L|h3w9t)QBFO%DUl8|f#Jk|5*&SG#xo#Vj@z5eqw5hCQ)YZ9qCZ*&# zL&04WyNF*wThPw2ATLn!^)4u^EfI8e|70uM!B#Wg`?(W}meXt@aU$6=6JI6ei$ftg zATdCk%IgqV#ygy+y&7$)(T8+|oM;tNM;{}Nf_WS@3vnww za)rP1qm*8LZuYNIq}Uq>&Sd=0ay9AFOjeM)XBB} z^@ra7iW8Nb?D^YScVuvcjX3!Jh;~qz4vy!@bjsRrONQJ!JFE!eGlD;UlY9H5I+`49 zI!cVGYqB53&2OOqB#Fm{a7fT2lHq9Z=pd|0__uOmw=3l-x1QJ3F$SqG)OVqj?5$HB zj~??!ZToxsR%AwkrQ?3z`GTyWl`kIgW4&6?^WHrF0VO`87DLm`KLK?{!F5z-JFXF# ze{?Zyr~*X;gS{uBR5JqDp_dIIz+Zs|oS-i7aj<*%9?TfgyCk&f#G`NE5Q}*iTg{TF zKtbe@nuiKsBu;)y^{Z~OW1Go_aR~)knFP6^Qnf#!Rs^59D}wN&V#AWF{xOeoOdMTi zkcyo)(kXiJ{V=+XuX_R>zN=K*EP*U7=Cp%fF}b2xbzCc8k61>F3`mDP8~zNHgk*#p zR6GUO>H#%@{Yl(ApVT~bTQ3RPUvB1=){?ruBsiuhmr2fNMl8#Ku*qw}b0h040T2;< zfG4CgP&i1Ut?!glw_H*{P-~@}R~V}icK2^AW2l@&|K}qgg51Daf;YWG(aK?ad{^!?3fv4 zM1xHh+`1rJt3<;iT+PsR@Ync=d_jfQ;3FzShVeuCQjicY4gI@|HuFC(d0%#=nD$9T zr8cw8GmG(u2~)Nh%Z9(Xp^h{IB8x^kI%?}2^#MlXHg^mgBhECUA(!G0DFpbWp+W!f zBi?DT;0%HIj{}lP_VSH92=vQ+kv|FRoQ!2jN#d%r`BvhpM|}CKa;X8o$DzF8deLGG z;63b>=%TU{4=(t(o?P>IKWW%S@c)vN{#$(nDi0+%-6T>2^07*_7l84!605~P2Qk0( z;frnHQa5LY&hrxG=*cD{Y8p)9BaW56Hj9N5hA%LM@8Ag?%oRA%@Ys2!n+!whQ`I|3 zgmWJ$dPl*0wj+N^6_>s7zMr<{3ZwGHp!Z`T&`bkaHyJn`eA&Y^Ugoa)4+@L(D8zdQB~{dWbo!TmOi5k1r(^RLIR2p%`s6v?E4bkFZb?;<8p=A;@dowANJPwZ!?q`f0D-F9k?R3&lkuq`4h z+$H^rk=_j-Qp(Q@*VJq8DYuY$Q9<+1;)eIy}*uy z(l3vj1|Owd-Xhb5M(L3`IjNgOENx85UWZ!PIR#uHAcGn|Ew&vtz6*Qh$KN&fHnp|K z37YKfRdc(U8WfcSFiTz1mqv8nls?9RK{b^rl z5f^eXKD@b_aHV)_aov+QbI1rSC?>No2&;5cq2n|nU>)Fkt@0zvW{>x6at`#qH>LxK zL8@9rfFYDzXN9>6lg3F+6?{u`TgPo}N_=#zGyLXMEYCk$dB@4cH~D0A(zI!#PIkq8 z=ezqLi3T?ckgMGE=}yZqdg1TB?+t%WEkkgUoSHoFMI%vfrd(2YJsYOR+?eAs)p;?n z)z)dv}CFYilR!c<-Ze3d(0!5f>_m!lpNT?Y>+{`m5=Ia-K#;D?obgGwkntMSa7v{)>xv}yBd zqr`nh&y2WB12f5X{{%mwAfLOBW=HTse(#ZQKt~VlAqBZb!M4VxC!JN%Gxg(yx%O{a z849jA!N=3oRD}ub6p4CZ&@WoP$O0OtT*fSkqmNVz66~BIv_5rAj$m7cd=F=P4~#TI z=Sb>`>{Pl`<9Ww+vxX!~{9U?YAd(Pxcu7Gxd0tGn;366ee6fLNRSv=-*=}wezrq%^ zNySC&6gzW+F=HvMw)8s$FIQA%AH=Oy4#&eiG%ZyCYfRQERhF-{sK2k*)4W(Wy2=K=`GI#h zGB;G41(3*T?t0dmOmQzcRrn~Eeq)~-(QN9b1-QpKk5Hp4M_R9?s!s0X>Vq$Wq{vu} z+0oXkPPQH(Jeesw$m8&6;MC|gG3EqzxHM$8o1xmgp{}94Y1Ho}s*ci*Om}=(x7gi|y&XZ)>ORg!!ykPub!`tU>k)?V_&JT&Wjhg+7f^dB%fv z7t9NYbIK~r7WY~SVY#(p%bQ8{7t6@z!oBrPqt*^|Y(HDc$ zL2X2z6UOE4k zW8p!}-x3T2aVo9?8-J`m-Wv{RK2pT;Ch7kvZj3cu5F ze?~4}rd1v#=Xtv`8on5tvJ96Su@85xnacj9D?RTTIeMCnN!5~CdN(Tgppt>vZO-bj z0rX?x{{jrs;vHN=rTPm*53hbQVOyF&EMS`$n@rIA0wA&A^p3)5-YUtTH$JngB@W^* z4-pZLqhJh3P<3?`L`)(!0g0yoA1S$ld0S)aW4C9FRYS}$<&~l@9p2Y-QSt9M(HLp4 zSl;6@-@Ndo9#M^6MQ|y5js=+CuMz&%_;FPAM zEwq?*6kx#0{U;}DiiY*8Nq=h0M(n>NhVZ^2n?W9kX~g@5&$^-S2~xekiY-V(k_y4h3NkL-{?hnZgVJ?D|SqBhYi zkJAIQ#ghdNZ8wsoF>laeA8NR+fi7&OMGBIn2zp8_oR3SxZTleXA!A9gcG>H6JFE7mD7< z%#D3&1pso&WL2%zK@!7F2L)Sk8!1M*vd?}0tBhCv36jdG*AzbiS};b4pUp(O3vbk$ z2;r$tRs{;GZ;_B^nP|S^dx^IGS~lt7$Ue~c(PY8^5OO1}6_ORa0N4 z93)WjF}ZIPPg!ee0}XudB@|iQ3MTsbQD&8zUu*r3ZpI!yGxhIsDYPnaI9|S-lW~`f zN)DvMDE94)ziN3Tv$kp8;;j{uk_@?Ci(+#1uqpCsi*O)AMULiJ$j6I^(@xpJ-82gh zNA>X@tq4)Ikd;d62<}ffmC{|Qs@gMs?9Hqpy#9-m=7vlAMzwW5CJy#Wl#BWrTK=Ba z_4rSZwmFewd=Nf7i=zKPKkkj|03ierF<~(omiILI`B_1}S;`pPl7myisS&1{P~;;f zAXIu01RYYEJ@310g>eqGWmfp+*|F2&O-(r|iKHoAdOjX+y02@%hj#={9~r{nW{1ym zZvh~XX2zgln0lKp()`t)!=%b)zfb;VwHIz-x5P(>b@*#3nxbG<#yt_J;t4FK1l$IP z3i;i!4!Ew~7v{UvhG)O6y{7RE8lx&)p&0b5yV>|s{wh^lB;Kb$Q{`x1t5i#*v$^@> zB56Jip?bM`KVmjXPt?>jzc{UCeXd~p z7976yFD3nS3Ce3r8@smHrdn^|rCa8@pEr|zY(Xxdl)Ev70-+^|ayznm@Er%~3}N$| zRg7eDfqUv7-c;A=TQ8+QHvS`_b4``*KJ9T{ed3XN6KA6E>TPvJ7Cs7!ELARP<4+u^ zXPI7nns4JEH3hwgqhduWjp$&6^;c z@hc`FVN^i#rHLva8QvI)z7$+DDc_%P`XgFdnZAW7-&aF9O26mWUGUXkehnMy!`?^c zN+zX(py+o!IF7kC(|K_nSsXsp{SP$ost+1`}P>2l}QY;xBA{-kC~y z{fj>yi{gLZG4bK+zTT3?*=}ORXnx`NZ@&F;jHv=OK9DF041CYv*cc?7oV(Be032 zu0piwFtqSsJDAe?J?(aK+CJna0{uVGV6Us(xp<@E^*9DE8&Z{LG`1u+kH_Cd_^37Cty~Lsb~eC<(ozOvGcL@c zhm|i@Z~uOzcYDgwZ}71FK-yss3%BS$4_VMtc+J{{2GMj@zF6$l8NPCXQzhpygcIDh zgnS%kW#v(t9%yiHG9K^zwhKg%VnO4eZ(RHGZaMYz_l;ph1Z81nlitTjDZzrA+v&Jl z#F)c~?0?M*PTMYD`Z+1VZ-u=mZPMteKmn<}w0m*C!rqqqmuv`PoECh7VU};C&j@}Z zQ&Zp4_*v1swS--Xp$Mhqy$&3!QXV|i;3x3`nn2Jh+rRIJB=^f%NahY6j>LXR=7YCL zZ5IMOR~?)M5&UYk11Ioucta0npJ!dC$yNhguC0UmMPI)M?j`uww1{{!*2aPq(d zcTo99V9N0c#pv&l6=>t)5|gY!GWo=@;s6Ew9T(=Cf0Sr#4%iXII}X{sWMP<T%1R|I3iS-4CHyieGzxdU zZNPC`0q;v6^=fb?pUwk$&6wRSkef>VYG(I_7o9g)U0==qZFUEHxB5m(=!i`u8 zZGshp9bQzNUKC&}r3YrLW(`nq8P_;?Q;O77PS93VMNv<>;Z@=s(luG%C>|DXy{e+g z-hUwY=*|o$Q?Ny_*U8K0h3+x$WY*KR55gX8CMb{7%^yCcLOZ!aPaAboMHNZo4(ZU* z%7r>;Y%#w62TGARq7;R}ft!X9>b8B)lDi8cwp_#ir_y0AZv=$B7^uDFNU$ZEG-sDq zU&i=I)qibR`T%j`o+OruO6;bUL+myK-l^}At%yw^1j1b+%XS6wDQx8UIKUx!JfOFd5X@iwu7Tm>H?w@S9gqVdS(qMD0 zIeoyJrO0+08gz?3AIUsNuUnAZWXbJSYrm?wd3y1>8tZj|k@rDn>Pj8*vg#aqjap+5 z7s2$o`gVGs`Z_U(77}~=$(ugvc||yvhLxuz#E4mBQP@HcI}SRiT45a7RgUjFj4o)G zz_zVC5ucq3ii|@gQ4$7Aur3EsB(y?~*aBmLCz4+a~iRsqM4!F-wj`3dU0}Je-aE36!w3I$DO_mOsyP&K=>Kz7aeDb@5U$_KUV%X zAHoEz3CpE~V6rCW8k6}T*)*OhV;)6IW^);i;rQQVuKxD>I3k6a!A1?;OQL^@43ASL zL%cXDZRuEDqLj$!#-=7}EEq!S~^U6+ao^q zTV!NFs9j+=T#QLMy&cVEYDGRFX!+WMS2WHU*aVW}Q|7$rAtr(K^r+_uQnX{WTuDBfxzN2DP~gx$B0kl80D1f){U8gfN9 z>s4ibdar2R^rbYRR+L`it;iDp=q~AZv^Vb?+Pkc?1+&CDvL`GGw?A1-VT;1Er-g08 zcKeoo*@r!%soUy>ogy=lJ`3_`?~N(CE-FOvJ_^Vo{sO;WH(s^5aV3P_ebXRrUfb@& z`5E0V)AVUTQOdN=WTHZ}OBMR<(dBau(?L(t_J5$Y2NlDnu;6;{wF498cTs}2)^w@z zL)X#(*FWbe=GZIS!3_)E44GlvakR(}$uieM^ut^xRxL84?r`6N{PC0jro!Eb=$Qh@ zHXIHZDJVzxe&~P6d4GrqK^!0kx?nRMweZVJ8T#SpEf~h7!^J<2mnBlWCcXTj+!V;- z-*fMOIEfNch~X+V;50JB?aSb-V%hq z5}e`xB)uFW1nj{HyJHUvX^oWv0xRh1dmAGNf9PRX&c;-4d}~p2Ui|n;@LKcgv%)1b z|Fje$$X7VF10TLH0iwP;mw2DOrXQopg~t!}X$FZgz-(-#RVejha;(v6PgTm=m+Qm| zu_++LY(DJ$)b;quVD)@%yw2&IcEs%yIm`^HsR=}F0Q)d)+R<9}Mr<0~@a&jgHs|+H z;;J>=m&0IWld&K)r9w$^^9~1Tr01lSO;K_pic_0(k2X~ih5OX8b-&@7sNRBvr^Qf9 z5gZgcP)75~>{xu9?y3jPIt(MB$aiye@OW4^k4r7!YPEtTGL5dla_+UO^JNz973U&)184S%^Dr8vEt zVr)s{AwWBS^z^nmchm^{sZ}xOniMmYAH1SRw~^K$O{_!#C$$;(rsPp8omyZ-GeX0o zL#YzyMR61TYP)u%<{8=Wls;o0u+)?etDZROup?HbFkY&4eXr9S`rBQIh9Lkg0P~^F z*nPFaD2a`pYAi9mn_Gnh+-;)IqhuMVk=$#cX7j7fQDI%ws7gksY9uB8q3W%k5?}Sd z>ygYiKAJeAGU`j~Vg1t5ra`=E*_NEjp^k0ysTGROQL*ES)3~vf?G!?I8Ptib8Lz4w zmAxrQE%n+GN(i~DU;Qj9$f$VwvP#R~p`!Dtq7VHTOD_HL3Vyd_{Sw7E;q;VzldggN zha^}ixv;XEU#70(+0XX>5B8e-zkZ@AWH@F`HSe$T(zs-JVmyrrH!Otb#ob-~ajohh z2(RV3)K4PH2xkFS#|x^bi|-bE7kDaG-= z@<;)3sGkcDJ7E3~#2T1iES^d*-4dAr%a6{ih?}b+%xI{#^C88K-gFrlE#1w=6?a`2 zL$Cbp8%A&2M$>b@=9=5TDeXv7Yn8!?hdMg+5ZLIV6u=2l$a4)$J-nct&dbpLV|;R- zszGBCiM4CotonmGOn24$MQXqxg;v>Ez#^2s+HsQ0?$~+VO6`jK zDN$)%7fYr^V-j8OMZ3gAhBKTYQV)R#(SkV z5f>d*d}!tJg!G@%KjsWe$E{wSq@l|ayHhFAhSn!W503^s7+^G<6v*cB{54oI{-*6q zOS|-S9ZN$G#@|rId5BuhUob6RwmS7GkEvQHB^0gVJ&*(TaPYf2tNj`25t*V1fG+l6 zxE%~SsR#X4?osKC`_}8LpXy|gm9^QvWoW&vMP`kMP|&zOs;gy)Rn67KAt!0ND-5=nw3TVgRMpU zk@3xV1oce511*lKGJ1S$!NgdF%UxAms{=Z)~$hlF;}48 zzx-m9j;?H4x4oFAlQ5P%4GDpzX!;X(&sR8wWO$zJ?P$)s{%VOAqbB!$5|fL?#BBF8 zvDu#~E0FGiq3H_RwlUJG+DPqPeVIcEd^!{fXbvuu!a+g-QOkZtF=BEJXWU?EWj--P6OPJ!ZNg(Uu)`+`smLVUD;VlW0*w&?K{ z4O>_HntmqU+A#@Ye9h)lcY#reK1|^7x&HW{(b%73ZKm-lqc{#l2xUAB z$nX5*+XV{_^BfZM&Na!_>X`!>Jorv}p!%!NF8-i}ebqxWwuDbgw<(?1@m`4UFLy)< zk;vVQY0Jh9#jW;|2Ny}}?jPTbSdRJi(gDYuia3uW^m zT!>N2d0y#Ft(%AXEf2lT%gLr^H9_p+yUIhxgR4T($&iB`F@HQ5LIUztgWWh5fN^F) z#@qbw3=!1dL@?W{@P%wfz2cKRwkX`QLXH>%=gZ(}XR<-aTG{4ZK-?XeLC=^&@yT8|3H+ot1<;9Sg5DT3^_OQvT%=Qscv;j~) zUuW9vvC>#1>HC)zLQq2vr?rn2T?90CAnQUau?gv2_IU*@Rmr2RBythRJrT_F)% za;cJ07Lnog;WA@T)XpFQHD`A>N$?DzB)vmNHEKEb@FE>i`3D1~&;N21hWt}ypaWB! zEg1w!^V&*Bw~Ct4);f0%Au~B?BN{%deJo{j7leE4_Nq%Q=u@^g)7+I`=YEw>Mas$v z4haMZIeC+NlDW9<;hxoyZG|2pqgIK8Kx0KqFlczt=qwa0?J#A;bSQ1M>I(3_AGvocKe9SXU&5oBOS5OLgj9DEiFgCC8J^J^F*vKXL|%J%A17rG0by_{*!gmdcKm0p2BDLC3?Z5}dm zn^tk%I|d(&oy&XHpO=T6c{S#EZSp7w8-_L8K4_bEcuD^LkV<}c)|cp^uLC*zSa(YE zYLC?ujajiu4>=^2cNnGVhu4JCyH}XB+5#U_cG{gHm|iO$@RNG~VtG47TR?2tA&Y?& z){cwle;%a6ktXI?rumG_N`Y2MJ>(-H{FmDCxWHn*_OkXHz%=+mMQ~1Iy7in}OsY3u zl?B@^NDM+hG-jIrSz{3*pu?R=e9_}##TK~oIvHmP*Gb*{ghcCJIr`QTs3nK4j0{du zScZ>I(eJmUE+2hq75#8^>hR`dhmdFeVxuzSHA28wxMk_H?j#LgN5nULrs=LIlm<=y z%K%Huw}<2(wUV~a%NM(L1;|kfL#R{DQ}j5Qp`%{~7Hltp$k`5+h$;WpdocL6h{gDB<85JtBO@ zq+YL@5kGsC2QD)iz5%)VML0Y8)~1^SWsFhYQNUeQzacJ)vdz4mDE#3Pnst9T&!Mqg zxc7bz??hWDh!^20MbFmNiPtj8fG|Tp2wsT8C@jU0w0Y58Y~K7Kl|Ch}WmlR`_mx7; z*z*qmLV2%w#;1_Q0nf#xWqknbhzWf zJoMpH3SL&mV*=5oUI_Nd4nbwRzkvpH(b0F`Fzwn0dAwY+ywpv;s92i`bdzuMrq@4^+==IdMy=2#<&2MU5ds*B*!P&EC$Oh=r?_qaW@l;LH`(9PX z!vSWcDam^8{{~a}@@`&^W#HTk2DX&=r!US&G_6h2>l2sd+Q_EY+f=T*9lfq^inu0(|q39^8zA1hA{|i$w664DNWW z?CaNo%zcvt3MU)oJK0y~i17-rn>T#FU25&0<$vlwoZ`)P$mLk#mNr1^B}T zU%X_X3?rBO6Wi9!ZP`=Yj!S7rs!Qxdp6M|)uh8F7WW2cMGhMKwFORyp@RIa_zI!6j zQqL&!Eno>Ro_Q9+{)5oR6?eX_ScdkduI|R>jPJJP(`O->9|U%Cgu6m!G+*paG)i7{{8492rYY9kH}wP8 z{V>p!HLORQWRrPbYdTq_ zEZNnCeEuJ3*y9cbt0(&?u4sjvhLHc?iKY`7zhn82679h%bE<6Gt}izu%XljRUPu;f zCP5$4vEkW?KPgWG4A;Axkl^N1*ogd*g$D4A`v!DL^2rG=WSNZ$%-k$25yDAz_e=xm zg44g0WR$7lGS5!_LK5*X_e@TDTV0eYHvPHpUP~h+6L3-ytJkQt3i|Xh^_8Ac^V8U4w4JK>uuyeysznp&d zdAcrhhd|99y`;c|`_rHYOnJPJJsE-~2-Hc;UMVHr-T$ybT8ifGy$lf3%uOE*s0(1g z0N|AMw511p*Q!!wXEL6qT;u(OB{ku+iN+C=4>pj>BD$ztLX3>iX%foCl%z=51ayG{ zEUBHx=U#4G z8GT(5`c7s_z&LP`H_N!S&g(PeEoqmnyt}9Dl<$QpRT*Xnszy2d(I-mKz5CB0x^gut z(F>!Qz$Nq_DD}xE>0IOY&R)Ox$0JG}b}Yns zti+f6U%XmSbJ4@1Irz?$%H@W?1We>L5AqiHh1Xx$f5+kzv$Xeu!k^RcynT$tfDjUv zBJQ&QE^S~A2f>C_i1>TmQxXAu&-ts;5&eWp7 z8Y~g|5IvvsA84dqKO;GpksZh_LEl`}iHs zT1S)s+ds{Fc(IN2Bsl!X-FXFqvAE0fO!q-`6rDzwms57!*1tBOK1sqJ9@~nm#b|en zL7f<6$?Um{^WH#!OX1YT2WbmVf3Iod#EN9gMAG9EW}M-7WiZ^NiuG}-@(@2`@9}qO zufVmtvD*bQwP&)_9SghGXVB9v^AC*H>Su_`O1E_^)&2^BvXR#L)X&}a{sN3(iKbp= z&E>0izt5>HU6+ITNt0a>j*Iw-g_>}`7q2JS;6#9JMQk~|*UH`&MSo@P*_eb*i%HM; zx_S>p`po!V2@=LXqNb z#ogWA-GW20V1eT9PI1@bF2&ugXbS-f6etPOK*%@wXHMoIhlG9Y>}x;ruC;EV+wy(I z`V0jjLcq)ilGj>_ln>2V>Qfm$()Pr19Pm-(d{GNugYSQ{;taEKg}RVp^X&!sD5j@a zzpK1O8}$D>rwK^6peU`eifc1HP$CDtn#%TbwfY28(`;Y!8u7*Q*I(J2Hi~#4eK&{ zJnx#45ta54f8G-|w=`d}$jK+gjd0X(uLCU4TyXHJarSUvOpN=U1}EHI<$eGsfRF9g z6fq8%ne#X*4Nl5`=$J6*-Op9}AuW>cTq>z9`09OVWMG+y&qh$Q#Xf8ZexWDl&A^bI z^3LIU2AQvnf>I9eLd-6LsBCu4Jb> zuI!Np;r7RKM2WZFmDUHNXl{_OnXI~d=|~dFIY_`c_-;a+<9QajzIeJxyW_N*M(DP7 zcdXnmOR30m)2!#~yOmAXC%6ID-PbshPTomhj2{!8LM*hFOeL1Cuf+#7qoUTUj$51W zO&u`!w`pnIou#06sSEqmi@WNi1sW5B9V)nC-!NorS;`8LB(pC2wmf8frz=S4)FYxA)N^#>&e&0oP26*Me54^Y)5Ja`Ym(F_Xt$aa5)WKDLFSV; zcfzniezgdLA1WT)`ct3Xy@R$$+X%jaRB|H1uknuQai`w@XbTkAbY5D(ht0lqLinKl zL7wF22{M_*rO6Si)bjI84vxwbh8Gp9pYc?DyLOGqvt>wWdA)v5!=*;v9jjS93oe#y z9R&O%II2>Rc`?!cF<`3VN2Ks!r9b>O+Tod2`1V!L6H)-i_lEzxNr^qNoIIMgf+D7_ zlrr$xnYR3o0G1!q3r$lEgX$9*=4UFcAN&`^B>Uc-^(Gw26&5N^!1*a@gP6P8+iOfW z7P0D;83is4nP&zZBhuHtS_@&KF>q(Ek5*TB{OJF-f@~XxnvDrD$HnmeL)rb6U}R}R z>6~FmtE$Bp{*sMck&YB^>+=H5GSmOAXKGRR63*!S>o{|Vbyb>t&Bd}>%vOpr@&)8f)$c#Y`#mX9pm()V zKu)3k%jh}TPoLqwH0n;0Qu;#<9$fSU*Rt(Hn9amdSBW<7_VN!$)`|g(W>p(!%Wkvs?vQo{ zJ7~sh#@&Uq^j%=Y*3&aswNcTS4p~15H1<|2JP=g8swP0M_NnKVcGLBHYD#-G;W7e{ zv-dAk9+GLk&|gTY;C5pPG(AjTs;&H@gj+djYH96&^5fPXqPK06Yr-Po|2Yl*TX{T# z!?)9sOKyVyP>eWfOVS3Cz*>r4pic*$a`*kVO4J0ITDC5dNnM55SZW3aSxx;Ux z#uHKB*e%U&`T5BSE6??AF$9owmR;i7?8Er&fA*@YO}!shw8Nk|3s)HlL|%>cj!gz} zrpZq<_#v$k3Z_CLBI_w6wD-;YEw+#`!2J3qlW}PkdAl!h^N53w6G=nu?=cHCx^?2rc}XP8Oa6J}Q&$}1E)NB+dUAq9u6>iaP6gJP20D(t zS_fQ-Gsh_1>eUFN>$Jn@L;_}%+>-5{TRm59o=B|(fQj?D1&{e5=cn#^dTR&5*HoO0 z5tdqNKkt}w{FA0=K>Igqb6oE>o7|}vm;xBaw?H?CDE~JL< z61Q)dqjgOjd%B5~l__88O;*C?jfMbsPm#sqO0J*VtjQNJ^S6=I-jk6CbQKXJknXj8 z40nVYMSog($9CYUj7v?F>w$L$WuTc}j4QiY*&_W|Zf)_xVMt?+ck;krV5A1&`;~n# z^A)kcWt`xT(OG^efuOcf!v(O3Jw}mEE$iN9DSilTY1Ek3<`wsKW$dMY&S;T*J2Wk( z`s^oV!Zq3NIeMmEoZnAIkZNu^geA;r3GH!_-e7ZJrgW&#^>tNb9pOOzPu@%ijF^7i z!h`}xMUlVbvG^aePAG^`Ly@hu@G~qDhIztG4;V6so_@71$P5~;Dj!%48)RG>4`os@ zCzY*uFpQky^Eyk`aali}VI?A)N0#cosa)}`(?U)q$muU`{@O+feAP824K8*E6Uwz@ zyVU1V{SB~Z+}A!w>T+|%vFw_pC>JfVu2oBbu2>!;iw5~?2L@1+#!zTmPa^%nKJz7h zfz;U>5NF8wnFRIfmM)0NIdYc5vaEIoutMLyB;G{PuO=nHIKnt>X@zyOX<8fTBXD5) z&4KUiU}j(oOogO{*-al=k$6u;f5Lb51$@*YI%vmRqx1XM@@T_2!Xq zZ8YOkW{S9B@??vi#d*eUg_ZKqvn%;ysn)??twj**vHN5R%$((?#Rn`w_OMqk#U%_~ zhJQ_W8#rpQ;wz=i9yJ&V>cxtg)0*{OvHM`-Cxh6e&M0q&h3`%>BLZi>*E;1oKj~Lpc5yUk}lLS`;3!qcivPZ zda=y=U3i z6W=ZCwxhbZ+50Qv$mJoabZ%5caMr12f-0{fBJ>WEEmM|qcgWrzptN%!nftlshe^Yd zw^R;)(%kRYzjh8n`2KWJ;Q2_9xW>tLbH-y@R_a^_*B*T=n=yT|8L{UZ&QTa z)q$mad_Mep%M?bu&sy)Zt|Uqdc%rHOVU*D5PS4pJ(R0&>cE>ae=k{I8-Cc7Y8-dxm z=QyS6DF9m-Z5V}T=AYU;wXg??vX2?($0g95Z+pzAhk4BF*iZNK{zd`8>)2=AMrrsE znQg~8LpIG}wL1)hGk0oFNrW*BB;VEb8=07ZS}$bAO85A6mir`woZicMoGaNj&J6-ig_x3UwxD9F!;OuC?)PLZ|tib zl~__aum9RZV6STg|MM=T{h}`o`@W?b!MaXaxcl?>-r6SCU6-Tr9KF*f4=Oa_j!Qz^ z`BG&{zZ5=z4nl`Y5^ivYu!crI7BPmZ88{aNWNXkx(<`KqZ?a??NTYaDuK5Jms*F=O zjOJ_uwnUScHvU)x>5^KJ#HAp8Um6W@KEoDWNOc5bPu>Mz5Fsr%DD2AY=z02Zmrj-8 zd*_nGh2WMoOcN5U{P7G|SN2qdu?Z-lh-|OAm#9^ejNJ!&!r6HD((v}-yqzDjO@T%R zIqOyu4V(?LBt_SCx7rZ;D)t_xo*k~@so=_Opp^#U?7&esi4*hl3|93z!tUF{3_95t z7mEGUDxX`cVSYtNwn0=c(#UZXlxpJexVH9!`<=}lNmUa`L2*M#brx4`Yzbmd%P~|o zxpna-a4%9h8niA>h%Q^FN<>?W88+6kL}~4>BL3LeTtu;?QW~$t%2+DCm##oHi^Cn+PwL1mu5I=qk%|y24wwQ)lx=<)=v;)7;wDfEMeihg*>*x&sPAH}-Cqy?9 z{^~@U*J%tXB4q^{=|YRE3utmVCl;Qk80zqA>s3p^3%BoBP!2;#i?yU7h{(@X&|Hgd z9`h9c+sJ*Lgifp`8TV**Q}@U?f$3dBXjrGGdjL~W&K##s85oSXnnv$K32I_t?=~k* zBiARxXIMQfC1@+r*DLqG0HrQ55RJ|@4J0;OIxn4Z3NrS8lUr0wP`;cgiALdgUzoFQ zAm+Ii@Mjy00ig=8d>U_YbtO+Keb?^C zJ<&^uVCr}^f}72PWkE3->W_F!{k}XUI6s@{l8}v=+us(2M&g?(;HyxEpF6i@>q@7q zzp*`M2!jg2M$<9+CsIRxw8EIOLz2P#;XJ>*jzLiimkr$`a$@?Ue@X;AOeHZS*hxBVktq&6 zRW-hj@8E5W?*6cNCDW}@7p1xktqo_iOJ60Qrk(q^jl!mKp|Wc&#O%hfD&1WQY=_*K zKsKU8CoXri99Y$ycXm#hGYeCk)m`>}D_!Y^!KE)Mh2~kFgpZ8AN{PVsXXFD+yoN zWNeB3u3c3Nw5|D28MN)GEg+jU)v!k7gVcTR_a@M|(XhFj16+H2o~IVe;BUGX+Q!gi z#)X@co54kZ zrz?^_Rh?*A+3sEUn@=W)Yy~+&4d)iyL6{4DTNq%SL!I@={&bBF@G~jPmrePN=1M{7 zjkcD0Q7qm>!-w&SfiNnr>+&2ZXoN?q;gwK15`$)>2>st5b0O@wsz~EQg}c)4PO3&b zN^tlf=$tWLuEPq)Q8Pu{Rx3%n5v zBn7r`CBEiuln?S@HN^Cu$r+4s>-cwsw;O9w!a1TU7hF?n0w^f1fz=6tPaZSGbKRT1 zQgvR58TYLmuJ?D}4az5tG}4UEH*8m3rFM?$S)={pl!QY9TX&o7X{nTsLb1Y2)$aEZnV*c`& z{F1Cyj3K@Hw#oB8u35mWsTFmHtBCt+ql_A@KV205q z4)3FL&~w1!!wd$qzaCXt_EO`o!_PAspzQ}5O_jzfBH8yZ1iHs%hzgR|JQ@O=qdou5 zz$6OJCh^boQ>biee|kV?7$6Cz6e>Bm0BXt+Lq5v-N4-%6+_H#03aY6TV;<$ZXLHbk zU7*pa=LuOMh{?}*paqs)lPsoFu|CKTMh@nZ2IVe(Ri>*lgE$K9v5ImBzso<$% zaG=N*q31R4j}m%}!pi@Yhg8Ccg-%g?0;(!T)dp@|etSn!8@42h^GGcMilAR z{*jnOVyQcY&?s|Dyb4LLFFTtyy_pHq-?*WZ#!egiJ*9Xq$E#^THA#nI9*Ivu-|!Ix zo4{Yv-jf>H372I1i%f2(ewAP`cRV)u1y})*gVM}=tcJ#BcQ#3_F$|cPVI;s`E1~S)RI}bLbB^7>Rkv1a&8F6Z&gWv z0@Ok*Nk*S3OA;TH+%!e-qF*rtA84I%&)tY1%q>QX{gAY~a&s)h2jT0huW9ne$T;*M zw~++ud?LHNY8^WB2!AKe8McKi>ufsEtoX4kE7BJ(AX-1Xf`%sqc2DN*yP}%TE zL$t4u>0eo~?m(#P0RSJq?)FZ4)7FnzJ1*4t3astTC33w*N6KCuIqCOr2!Pez+k{vSwhqE+d zK&C@AsAn-h`wP3w#_Wsk#VL)Z2)3naqsqVc;kAZk^j@qPKY90}3FEgVJCT>Ig#2g} zLYEdqJ0xwp+JZf~x2vGQpkr-Uu_krR=9M_d2>YYR)bWj)@zQ0&IU1r+7)J!{%Kn}E z6j%y={C!z(sSjyxJ6*mb9(a8kZ~xmcT{4|KnFg(OM}E`<>0ZR6XQjS_$PG_#U4Yw8)6i z3iDjT&kcz<5$tfcQ|%pI^_xo-u#BU!lgxLvyL+R2+gqoo@IgOQC%ve3D!VOw4z3Sh zLAuf56DJyqk8?p2HFbV9<_iFZl|FvH4leDyg3@pN&11i(-{WaiMJh`+F4m+~kT@7P z(odEe#_ql?yLSRx!G8sudcwh0xy>OrFdMFzoQHr6lfmi=|69vgX|^l03as_azfeC8 zRB?dn21hulEot#N4K#8H0Ex{nlY*x6?(f1(-=B2%yR(iHYVcJVSoeNa7k8C4^Ne-a z`*ZuHdSsi)(iYy2ydBcZek$U<^%ui=YK>#`N}NrNIRV*T{%Fo?i9S~{R&FJ@!HCTW zj!MfJ{li=7roryNMAmql~l&#h~gpv4x#bqjDs89r-D@hPGsDcYnT2yt;E~$R7Zj_*wPF`{8tI**v@^IoYdvJ^KC z08(sV6{n!NP}k`p=aT73(%zw$k4z)~5SF?x_YEVr`zRDy+f!b`vP) zR%U>WtOUCmzvwGaX@gpCcwoWikgjTk71Xj2Smol49?&rmUzSCW)8Os?uXtSFnl{C? z^`vj`W!0G%mG^Be!Cd&B+)u4U>ai}xAE<7G$hfY}!VSmF63=3{dxq^8!qKbF;E#E3nMR}BUr@?x+Zy_|*U%Hk=LAu{o* z(XkWC%m1KFET|8+=ETcMEulZ#gu?xX%b(gt!g&G<;Rc2F7vWJ%aCphY21AnIbRiW$lX0JU$mo?8{8 zm9Dl_N6Rrkbz+1+gWm`pfS`Z=^&so89MB^3Plr(?$iC&_l&VvClfrfK}C+F75QPvA1O z?c1!%!cl&x(i2ejL3`_}SOPzOm)VW=-LTG@hzfs`A6rQ~3LD1DkG|qvTz3HJknOO) znTDkBm39IFA-np>ADQ$BT6kR=#}^TPpkFH_C9HaJ{yk&Nh-^!#i8gOUbR{sKMORTYX14SN~r zzZl_#X}3lbVfN0>$E$x`lM^)Fr&e8IZO3QE;|tJMCr*9s8MSqi@;&Wi zCagsT+Gu;=?yA_?(Knc+g`2TEMm4_jjzt>NVNdTDCJpY_Wj+OuuYgnLwQFDQ6*AUf z->@d0wpgTjTp;j3PMfss?)_$ka<(KmR$9f)JKS>ATip zm^E-0ayY*umCyZ$-$D_Bv0K1fQY;t0b6zGprW5#jb&RoS(XG}lB^TV9HXzUQ5 z!#sc>NT$(h=0fIy+*9zhDEVrQ@?2b1XI?ui`>l7y7c7iecS!LHssEWnx3q9$$(fWG zh(}8BPv^6gAVAP4XD1O>eWsrMcFdfzhjiA;Fm5pdr(1R)mf%4~qy^>v^Z9A2M4P!P zmocs2LtIV#OWqVM>*3$q5i}v&zL$wce?FO+A}>sbXQsmYZHUOnHs{=}EgEQXK}u`g z?;9HiOO?(}3uesQ(OmG6=EmjbMxDXkGt0dFr3ya6a;YYQah_Vug{ncW@tMK`Va>-X zLy)dc>elkzAG_Ezes4b$+eQgBj`=fHv{EK*10Yz*upZMC;ki|gclTOsVcx)3<^%9~ z_;TXBKSC3_l*j29$^^N_=yeqy^}@>9-SD$yi~zsC5OtLA;18h{-srald5w8Xc4>mu+3UBq?`dq_tE5pgje_YI;mR({XBRdQ3fUBGMRH zdLYfo%;WBTzGzA~lCmAJV`KuC8Nh$XJmL?5(K`CO&b{ERF6jif_#lkJlgYlHoW)B2 z-p$cXX}<}Z1@Te^>#^qYmwH@*lq@yu=V_MH8bp_UYA%{zYaMO)`qp)=HdAZkL@-W! zVH5A;ylgjM^k-MZ7kHGulim&t{nzlv6E+qYHRQTn=7RtDjiNY9Zg}=fuLrgJd!Up$ z{1yQ6rM>Q5M*0o0w&IT|0@X*dCCR8zF{LwQK! z$9MPa{41F@UjBF}=~t?nLMfrs9IwV4!Soi1ddq!m=F_RTd7w~4hgGf=G~E8_ zH7*Z;lzlU&)of;QTfS(TMHIWwID~m3TaL^PBIOmWljpf$ zy=PVbn zJ>AGdG3HorW-wvDV3`iE?z2$2r6-Aj&8~o)O)n+lyL%BCvl}mwvsBCDcE96P{5e>vm^JCKOkyB#V(JljRHdcv*I`Y`4?$DN zs!oQ*S4O(l@3|JoQcU4`MKuLw;1s_^f3_eW|BNSte6E*Dfi-gogLTi4bI%~g&5rKw zC>Pz^%!`%TN|keJaeblD#Hk~u!FG1k53>C`VD7Lpq>njGz;oWhprG@vF0l0B&O-ygWtOzg ze*Rh+|B+;7wyIf|-tq9K3vRz)i7cI*&JL#pB2zSj*+|v&9_^qs9#d&tDa|#gVRzBFOPS)-Jx_4{VV8srN7+4{qu#_5F!UBpGf4s1%VhZf;y@Bz=67a_Hw zLbEl2d}b-5gv~|D>;je-NfnMJ7954wC^Q5uF?5DwQ9~a$JKy^mQsU%r{D<<+kz+D) zc#mgSI6?8pwuR!z-~c?$hgeQd=5Uu%CAb8cDV%c+5(ruHEA(M~tT zT-Wn?veKxm3UwFd>o?x+DNg3i>U$MwkOL4^)xM`GEgtn#s5PLColXwvRYqRj;dtb3 zC+~69ukIZXG=V0kOR6}>^uD>ho+*(!%ce(}F2=;rz(a%Hn~()}K&DO%EUqeFvG;dr zk<;Dx#pQ9(4a?DuphFvTeNUL~CVb3u!b#+ht9}4pro#V8^Q|g%(3&P@eNk$3e8`qX@ zB9z3pfz@r@GM>Y!_&7d8DIwdEO@k! zt(b)*C^mJtK7VJWY_u-W_ia85qag^iQUxt?01FnOOD-WBu2q7$RLSdWV}a;i>IT9s zk{Y)>Om&Aj((_qGwwbB0S*cIw*k>pQ`U$gJ3L28H+q*hSqZ55jcojHEwy$?HrFkZO z$B#pD-Gg$j7grlTt@F~RsobdAkFSmDD9tB3s78l?ZpQb}o{uFGOg}RJCf8I|{?gP^6bi75dD`40mrs!UPKK`zLGMAik(LC~ z5H5S~UVAQ;ELpJvb7hey@G1Op?>VpNfbPHE_yy1vEPM>3O|c;N<$v;yuf+9S%Db^; zEH-&-4)Ki2&@|=K4J49>X5G?#r^?QpqMml>HVVSaw(FIInauQs@H`&Erf8%9K~ATn zi7l?HJI12ZwmrcU7z@jhFTX#A>#cbOOigg$u{naExkEmyexbTZr0#W1rHkOhk(R+- zoV?))ICK4(<#k{Ji!GZoK&Fd;Ux`XmXRWi}ozpRUYSSsOj)M3fsithw__Z|2wyn>n zpWQUVbM*LzvkOEO6K*q6#Y0Pf(%n}3T`+&P!O;Ujt`Ym!Pa~|7eYdpsP{KzG@myO zU5P@EtY9Hc@L_ZFk-)I5`RH`x7OjJZBdN`b$(A@t(z$!1jI?ha8?DSrrOB>5!QWZ~ z02#NhBoB~$f&YTvFW+0unOQMN4pv_n>Ci3jNK=5bWzJ)B6S}`!3N$}M$WdSUe_({2 z3gpqXC;YGg`&OW{5M$ij8g__qQ{;P@w!;R&b)iC9V34z{TqwLDO~hT2rf^w`ec-+V z#=X#|R9u2&=!%LDdilU&nJWo+gzARWm58)#Q-CTkWJ*^pps=CIP`qZzD z{+z<6KyT5zC6q?;of7f!qhrGK5P&I|UcK6>gp|f==Um-K<#Kn+_c*(4-CW*mcOXdL zS{2_&phgT~^dCJ>(J&hegd;2lx@74v)Y&mK#6oefY8I8iC{4^3snVxB8ka4KN~3Q(`(vMW3KKINuzqG~zjoPY6Zg^P zH=Z}XhK2$hV0DeaR|`WRXmmd|FUB2TC zovwJB6ypdx+X>Ja)%|lYNNNn}9$s+vI}|dW0r+gRKE2G%&`;`ED5H3*7QAz2&z6h( zx_x1d?yS8Zi7*2mE5U0v;8Vd(Z3h=V+Xv@6ru&BnGF&D6*Rs>25imM8nd*NSa%d)J z5wj?Pf5bm3q{0>62YHx2In-UdYM!yyFtB46A={O>a;b|8zO8#3Goz>RNV`*pCqFXg zd)uy^ea&H~`SdTKE61t(B!j@-UJ3CTnw8qEf42S2WVvzaf z^o6ipT4!aaIJoBYX}|PCZcH6D6uVD<<*O@iF@Fhj1cYfqz?*iELY>(8oc8e>-<^_N zL=^)e>puf|pKsP4kP)N?mmzd&`r z<%~qFaWh$JIelnVnN-lCz>{(c>rJdrMUTVtFOZ+wSV%=E!OZ4L@((_*4P>50t=zdY z-Axahr~y;}ByW_EQC1adf^p~ed38JQ(`RO=9CA>EB!@HvG-%-EgNG%Z zcl`Eue&_OrI&fY6bdiUUJN-D>NulV!j>*q&SR0knz{J$3pLS53z68UNNT*21;mmNM zkm&wRK7Xhn)Oh*s7G!r4On#bjtZyC0pyH6ldc05UL+=&h-Ld^$vI$<)WC)P0-MD|@ z7=tcB5@!!AAcSEa7h$UH5d3_*p+qe!)(cr6nRbj^=R!xKkbph8y#b)lVrZx;+EYA^hKJ>F z{(mWYsZ>xdMRQ1eDYh~Q+1((e_1pth<$xhuNI=2B@F~{KY0ggI-E(juzzwW_^1fJP zN9nF|KU8Nba_tHY@S*1)elQ2nK_X?U_l|!UNhenrTp1XIfoff#W(WsZ#oV&%6H_}- zIA(cIFK(4&759aplo==lYvILqs8pgzj>b5Cwzk@9yeDERKVG6JYHOO0d zE=`sF3P(#POY=X&H$T$yZ55MleUY9iq|GM}MnCE=2tJ;f8q^z2A|*2w56a%tk#l=& zGihA0c*>3EtM%|P{e&|iw;`MGhoU^+AmeaM=8^H{f7^CYRttxC%bB~=VmHF8cykUJ zZ~ArkP5ceYT>(?_9?L;O^bEpnHU(>+W^kM$Dax2q(gl73Pl9xxFrNw>o*ZnDtJBSd+$Lu%tqQ{;RH2GGf9o@3WQ zvwg3}@2n$m3Y$ZCBcY-<+Q{#SZ`-`{gEye1g=Cg-@^dK406YQRga+r8+b(d8CD zcIvPO1(Qo?-dUb;EL8rD-hC_BKau;^tqKM}PAnTI+@HdX09FNI-q2N;k-^5j>w@U$ zn@cMrt;~xo-8W@~IM-?~+2`sp;^J~~1x}e#xINO{sbQ{RS{MJJWIXP;x8&VR;2Xyp zsMvS)uC$PzldV}}Wxb=|lX>mhN`*H?FYbtuKN?~?xg^}vo+H*^7@azDB&}pAeWi5? znFVJc>i*o9_JwA)_2+bkLp&;ZI92Z{53I81_q21zQ2~<9$e|y3qpGHv4vgRh z?7OZ;vQJc|NCxNp>6_8YS*jPfkpx&8u3d{yol+u20G#238eVYiK$dE7aX6}8K119a zXOy|jQ^4?<)G+hask52EK)Qa!j5|YB@UmgQT}9AilgfM++u)og0qIW))?MBTzlK&o_+ zpvIP@)avfYHuh%E=YLxyn9HsI~2fvNk+-UM(G!@Ai@euZIq2`XZqZ7MKbNkbUuI zcd&)IiFsj)U@IiR#JxHxEymGendju!mf-d$tkI@*@T8{FqVD!(K`i`8+;AuQs^Nz* zY}UrX^@6nki&3|cnhjD@YjXb6b&dBAIl%#VdL4mp1^*6>J<+IvA5)cN46}4z23Ifp zY4BZZh@R3@o!nnYH3(-A-G;c4L-!4&b#`&p6-BS*g{v|XEKJDYC)tm=eoM1z5=M(V z(Tjzlr&m66^YofRD#2=Y9(AH-ZC4a@5$9K$_9>Mo1p`IKU5W(^_7dO!KEjW+PRVkl zxZK1yPQ{S=(G}B%!E(R@WJb}|fzW8xi_O81ecrwGuSo4L391^Q?IBb65hUh+86eJ^ z0>QyH_{E%_?^H=ml-^ByNDxhTW7;rXC=txYWX*Xcw3+&h6f1*}`5%i4VQS9BPMP!6 zHiK=wcb!%|Y8N|zix}mWEiKfQD7&BeM?D-Jn5$eBu{^j{!*u27=nb==uf=*0Q2H>- zHZb9Ubd5;2YXF;h$|Ko#UW8d2M*uTyzl|`Pk8Tcnym(-jY68{l4)uJ$>3i8Ei%?V9 zQK3f{|6})6xr~_D;oS0H#6~J(7s45euJ*yT(E<;Jg(oZN>S&hjkWWR#aXN?@NgO^i zKg`q;D(J|&S;{Z%%P<=J;=x#&{vAyb_kH~?ft+S}_OvobH@GCs3A6~fEXkYWgC$Vb zWn63N>|a~`qW`m^MpAoQqh2mE{O-mYRA5!uhk5FlUfPr}=iX>yq0Go<#^9rzQgQ4W zH^gi$eXM72rOwL%CZEhF?QV)@Z90^n@}j=@HC^Z8Qvs(-2=?q!rvNZ5w*)krs=WSF z&GmAYMG?5#t~rM z&84wurIPFGvA;r_ev|c8pH2dhvIsS+}bCSlBte_0Wrb5|1NhAEW z#gg#jNYZW-nGZ8gLI3*}=+0HqwZfQRUYY!1F093ON#Q?~P<`bn3fgLz=OD4%ws_rH z3lm^S7n(F=vfgpl`XT`cQb>yb!1qakLaaW8E=JZ>;qm)>k4fob&v5Y)kQ*{dILvg= zwVnm4QBy~+T#bIr`*ViTS%yZ*jm+m?8yLU$K?;7tUF3^g)Xia+!g~gQ*K|9ryy4&oA@_uaKHTbR;l z?dk69=}Ez=$+lseb(F#}=$1KF#cdAZi@Q-QO33BGKhE5^XMYpSJ@5Wz5fR)TJ6BR5 zx|v&NhDa`en@@TA{^Ts2VESeLwZ0#9i;00j0ml2c^0neQWC?z%SS6Lsf5QgUTPmnD zJv?1Zwqp>TxKQopEuTKwu+(fG^E}UTb)wj9$gY}n+x!lz5)bHW?;NFna%`sB{j3L{ zYIa$?p2kt!aUP#Sj#;9u%)j35?mZv9E}hL+DBqE@=OiGAmK1OyWv*h~tl>%HVcwUQ_<81H8jY$ab%v7%m%q zL)a2fv3nSviSyS5LMafMENY()czqgiFLl=tz$ahcw9x&k#_}JII|HY9dK!bLW=E;S z3j{Y@Rs*;8i^+HF)_8^ycnr4 zt8LOO$6LId34X-Anet)%=~ej=Y*6XA-Spo0k63Cks~mBe01ejVZp;027FV!;ayV0Y zcnKApk5TaX7!jI-+{MWOEeY|*NM2lm$-Cg6$)tF1-uBErZO&zHH?$hrHY3ez!~d=Q z-*mRs8VHfe@z&*&(Tk!|TA_F-5~mfpNWfuaxN7h7s z?aXc(Y^zNTVto9SQ+!AP>*b38yt%2%^Nv zyH>NCjIi;`o3IP|`1N+GY~b7J6ZMIih9m}BU}igSQo3gWc#E#%V+W;uINuj)ZK`$Z z4osUNhw#lWIY$pKgQ1EhCVAHuLl^j<92LC3~@bDZ|hcc0QwnMa7y z(@XOv59Pu>Bjhd*p(#6#$)_M8O0hh@nQOZ?(iRDGGw-vH{_#X{9ApU@8+)gcoa#QA z1oNMr#2v*CIjvyG1W#=w81K$5G(pZ{Zu zGWliA65W%KO4a>pjF3D>=al_Q@N{3Dlwj0&S-^PxKa{qsa8qh;QBxH4TA7x4-;aVGAl#<;-cZ_je*{!+xnT4f+frd2K}VF9!L_5c7vPJ9G zC#ge!C6^&(%6k~we&xx^3_nV#E4!e!UxT+c?OUBwxV2gA94xl7Pq(flnV(b$1n9m- z##rPdi0wHkp z03)!dUxcZ;Q4>b{h58Bxg!Ma}#NW5D|HcmR!!Pg+{z`H2p3#P+H$&=%PCTx@?XC)o z!H6?y=5#HSOgkTWvg-o_K|XH|LY1=rgiQFKqvsG=Ow+rXoXa4^ttXrTGc<*kX6s0$6_3lBYi@w4-+w6UrhvV$KgvH1Dw0+c zhsMfg=5#uF;jPKMOZ1>cbKrj{Gt}zq!|dQ}ZvNmwK6k-wbL|&Rk%pN}&qUiWqOSX^ zH26xKhp6*m;Vd#VVF1}QaL?P7{y^Bz@w(%ysByArc-Sz_cglSkc@KPtS=Y18a-R32 z?R_DaCKeVNYVa`pSIbGGRNj!wMo25@M9u2cd9JB=Jl{dz)Z6ZHR$(6*L&GW@xFxyw zh%%+?hQr_AZA(I+MPjolkgsoID%X^ClKRJi1z)w-yHU2WHp@hiW}}~kahJAo#H&(g z*gJ@yp|+38X7<*r^{%OHTQ#hLQkn$e2j`+acilS(S>&w=h18rVMx1JW3Nr&bDR00x zo-m%ofSmUvgGI{AZNin~w3g`kstI_zYo9_`CIvsx7k^Hp9H!tO6ggURZ?^HK%iAz{ zt~=Ib9?`p**W`M%QK*h%MUUnXeKo{Ck$mw8AfBY)#Ffo1tE+oY)Xrm3uj0x1E%7tm zcxg7Rk$bclST!mJ!0=^(UUt?3vCR)gJ-7Om-Z7X8X@@+|9~K1-wxkWSHDXjXFHx$u zs<4em*pY;3-o0vpC56Zk^w}j%4-U^G0}+rfjG|(t)nlmD*DHPvZpGl7&fwVfiXPtC zqF#E24?Dxyl&>`Jz8^(RW3_tnAhd@57dybzUw)w>@Ga|*ywlaWJbQRw+FU-Kp5ErYxx9gdsOIO^NTM&nBTUn*u#+LP|umnU@M>yVAW-Rh+(K^ zM76QQju9ei^bTQ;)Kat!Ti*SHl*iBhU<@FTA(>CM-}^sAeN|LjT^B8dQmm8~DbnKZ z4#nNw9f}qU6mO6~3&q`?;ts`~6nA$o7F?QOfspU!zxUw|Mjm*`$QkGCz0X>6&Nb(* ziX;~GTY+Q0Q}*ccR+Ka``dj_&gZ$OU=o5k9m&H-_LmHWZ_d}Ke)y+g2UZOp==_cl^ z!~(udVZNV!HP%lQ%vc0N-L)-T#+QBlgnh?^OWNkL=<(P*oU2GG3m^P8I6~36zqCxD z;@I9Gc9xpUpud}D0p68bYC$6JWhN?2K91@KhO48SB0depI2ND+69K;+I?GCL%Y2xO zee`2|Dy<@BnL@I^FHqyqMAQQPke;v`Kzy}RJzV0p`ofNR`RW$mSt(nEPO8g+j`vP; zR{_(>GV_6TFYpPTas)?hfEJe^pPS?61sA7Vg*LT_Ouol(P1i|MFH>z?KuWkIv8rJK zNF5$9hDr#N=SBLQVrfEa-cE_{k@pC<+sW#_qcLQks$j#Ep177))i)1>B~oS7BW>Yc zP%$g$oARUjF?O|ju2X;cyC_^|)9Nji%I1rwjc zcn89yuYOfwY*xF9-I0e0d#ari&>^jn#?*{XAQPBjIV1>cay@7grV&sy@n^j8mnPdd zi0t9J&Pw`G-51+2LbMDe3Y{@>b0^Ve!~mkDCGGqMJUKH(0>me$=>*1sWXQjtZFdBE z>=)2Ts(L~$aWHQRl2T4_xbwPKjxOZoWwJjErPWaydCQ$qhZzM&28P=nydBgT$^3yv zkS8S^xMX_-7IEGNKsWi<9q$PhC~N$bQnyoeA{RTTn-?qL5FwSQoHvRrUx#C+t;z>h zz3bsCG^1sPl0Go%j9N4G*%tN~7a<$SHve_H7)8QaB2N?GhZf_ad`ffjn31Qm%0_TT zF9RQDs-vhciXjd=m zWkSCBb=E!Lbt1nPn~E5c+GH7N5j<0sot zD+aB4{MGx`aHrDv4+;)>dGgkvIUC>d9*=4k|4yVO@bT2^bVO9$#nO+Z2P-&+d4TDo zht0MMY`FpMRiRc52NbDw&<1?DwNWvO;bC^DsMU8*D*NMv0|5)4ZhLhH8BG$h&(LTG z2^cTOEZAf0pnRTgxY<;y*Jo-r)oz3M)&{*a{*3Bm8aP*ji4a?_$o5e0k2MC) zXu5xrQ1i3bjlkB1>QgEwaFCo)#!^pbW>dpPYBJ^OQ_A9Q@tE)H;d^MkL2I%ayQ%rM zse0meA8y7s^#TX!R~PTFF5X1gyi&JjtRH;MY&v^1dy7~5em7kO!04D)EU2r0OZNJk zh7d+TVF|b=U8-uzgI`YilR&It=&wS7jaJ1p321q0Im`}fW@0Y$I*G;C#5mmkQeSVc z++#V5rGItYoK_Teb+|N=NHvf5)LzHb6+8KZ@w0^Jtf2Dd$JBq%&U@5u^cDRZvbeq)vgCVMdbht|a+y#HiL{`HTV$vBmJony+e=+EgW zUxU)t#No;CD&=crmi{jrr%d5a!#O>Fz<$y$s~yM$dJg)W?cLR-#;)cVJ3o0mqfqgI z4PEo-wY96AlhjgRoUMDA#hE`-1^0e~A!j1iD=G zXjNe^9mU}(03f$Z0uuZTksz3$XVLpK5y{&h;v@3ry?V-cuX)TQDiP7go8zMPFYq9D z7>f2jFVP5WxyE9MG{{^DGu_OH8WTg$y=L_BxZAWwVr#xE{H_nmW zyTgocoO1l*FJ&TV1`gA{n)wk~=7}cVAE@I3@{Xl4GCH42>uNE=n)98C)AfjB(@$_w zZ(4iZU)tyF=DEB?UFOip!oZEgPu-o%DJS>U0oDN@R9+%;hAi<1qd$?594oFe;u>p3 zMa6h30J(RPt|z$I^wpfRNu`6PRo|8n7Obv6Xt-}&Bq6+*c%35R&3JA++seR6w1fAI8_H*?VR54QdDifh!cF*uKJ+;} zKY?xt<*gJ&GA2voXUO1TR9JbX-t_|Atl8N{9Up{o^I;rNi`1_xh1bKIj@p$9hV!Zv zB$KKXTm+1K6)g^%Z2m?vJeZK$Z^yN|Hh$ew`={9}^696vZZos~LSQ9x8j8{U4~^$$ zO4A6MW8t{0ZMHu0tx?1Kbz;i93h5dp8s}!XouVaY^}p=`+=NOL6m|&M*n;0-hU!8g zO;rj-C;wbXt?6PxiSd$rm29ULLy}C^6FffX@zcHqDM#qs8ZM+6aRCu14>W$h2*yHu zn0M&JbWn*7>VJ=F8^cGV+rn1p{lqeL{Sw(q56ESz<+?%$WVwUnCPCT1tyX0<_6pEz zLg7^R=-{wbBYSXhea`vGBi1uR@X9&B*Rs>0Dvjr)lZN3fIhRb~d2r7~NV;^x5+ONN zf4^e(qek6jl_WKB?9HR%I1hVC5*2T$6HSi2IAgL@3+rXng;n!Tvxk9IG@tAFMr`Qc zWclNei<1guFww?QbkV0~?niEQY_24NYUXn@=Afq@$#Vm4eX}JCVJ%&6=tj!jWdR)J z6h?D>wc~2wS2Jv-rIGZ9STUVn_5zXguCwBDpk85vL`exqY@K|hz4W?5RdhqVu_$RH zDal#MANRFtZy%zt7x5!ODRffOJ7ua3>Ap~VlzgPojqTl486p|Ed-lrSpcIQ{O3pOf zL6eB8j!IKf`nUUx1xis_mT(9N7~|PQ*>bhDE~wO)9J`G7%X2@K|8440;C3KTEZ0ey zF|ro@cJT6_n<#$)w==3FOxU)9ruG6`ByCo@;h3qsdCZfzdxP7gAIpAPCs9Y&Eg6X` z-qd|0ddnEDu9v?P0+WJ|1{saTKmx>e#&fpx-STVOfesLl-JXb`Jt5I3758=V_cD~;aq zJ9n_S9TAx8_&Q0fn-uABIx`CL>*|EgK>Tt7`%2DMf(>Gn76l$&>nJeu+25M#b^}95 zB-z|eQAXa6Kr~0bC7c((gD_Aaxz1q$E!=j(J;1iwB^~6})E!UB_Xs(>b#$-ArYf40 zFhSP27-H(XVa2ccU&>~ChlP%Xp+H(u;0LHXOij@n(GLSWgR^heP_bC_9MlF4F2qGO zHo8@^>9l!E>LI?k{G_kx>B0N|uI#IG_Z7KCQMaQFDwPE0b`ubjVpAb0&-&7ob2FR* z2=s9gGXPwasdXBp+dp|w%;B~du8!!D^|$MljDr zF1xoe(HW+D>JO-^Q&+F$Z`ugM8}-~|5wBdRyQy1K7V8LNeJnp9fDa~&_xN5ZB32Nn zfm~E4>R#8}}-2%_^u6 zu7vy=F)C>^?=Yt~EsEMX;?o&=8db(FhIh-p%m0Q=N!vpR+h{0f}<#j2ZcLVWJ=-UmM0$SqtnkYhEFe6>da1-g&54S9a#r9E4CC zgyz#~F_p^f1Wr%9=+|f`yY);B*Hu%GHZR@~d=-!`*GBvHkP=ghCpm!Up`2p1*;;C>2QV7$QoG3r>&FsRn{A!7I%g z8k|I0FieCWuT@R)en(TB^39J2?Q?92CSkJ|{lXsJz)J&jF3JkFMMCWd7IXQFxlRY60@A1kj$0E1RRL)M>MMGvk2vrP z)D!UPZ2Vq$4&Qm(uXC|SjYE{oV*m#V^BZ= zybpDa0V=!QK~#e^d?T#XB{s+LH9=1f+=t8o5lp6$QkI;-{FgrL-wt9XI)Cnz$a|5^ zDUp-f-bL1mE4mkl0;WV$Bp|0z;S8&89c3sR1`)WV5NQ-@02XbcBp>2x3~PIzG!N&(g@=#w%EJbLz9MwB-*hB zhwG_~-75$)VqXd3esJ8LFl}j`Z$=hDUuDd^d=YKqh;6P8jqumD* zFf1OW5-rHH%CfYAieJXqFa>n=|A&U-5}>L)SL@%U%}VL0`I>h>?NyKb15NP9ow>o~ zIqDmQy@p?CEXQak_YMdwX=+T=%|~TGDWC3SXoC-D65kHhv@}ix2e~)@9^4_U@>BeE zpk?aHntkC=9y(7Mo`IHr_|U_MSTC;Y@?+QX2=E>Tme|a&Q=~gEcZfYWbn;&L>UWeZ%tpohTQhB|82I#%Z)MIWU71=+F!dYWc?e%3+#UwC_L5t7AT2A&TKCnZUyA!nWBmwM~eAVS1N*c2Dn8Z;7&asdztpw7OX zsGrc{G;`|J;Vr9X+cF=nDACs-MUyMEimb4-z%uV;B82Q-AJmqlp8BCw!vD-gsbwU}h+OEe!x$^I>$vvUV9LkSMShY=8;3vhaO9{kIJ zP{T5^!QG`gPd6Y&PF&fAqS@o|hqYWD9Tl}7k6tU!OBTR^QtV9H_Z!fg+G2JidmEA0tW zeK)dqy_l*~&HRBxZDn>ZsRR#Y7B6~Uu@VTuFo&8?BeYP_xM+>xP9ohUfU$1LxW>wG zgiY!NAZFd9olRtOw3!(c(<9FJj^p4K%&DHKcp0Ouf#EuP{rZWi3KRYhYlkXrC3=}AUkJj>WGXjgpz=eq4P5ylA{+@IN zCJG(5C0PV8Ov;CF8kW&Pzg7&bKPOk+HBlzbImebdChzew$Ll$dTl8ADpe|E1?J48) zv_eAb+2-$_z=jYi5~(TqR|On6LBgmbS^-XkdJ<=_kE>fwk8UmY#ilJc>w?IlE#(fgg~{}u%+J$wD_A%$U67GN`)w$zT|V%y9{J_Rq#Ft}Hh+DQ02 zvFE8DKyFV&6Ji{Z1pAVRSg3<5PRMt@@3brww~gVLAS}**!S!NqQ$d(AkUcXQ>RHTg z+v|>KfcYi4y0+A#P)qI|CsW_LmgbJ0aN}ox_dES;pNE%Q9J+J>+q4F&w*!x{e5 z_0sy37IqC!EkWg3g)*l$^uL?jyvETSV8Y7PN^0CVDCie^(ELlqy`;{OLsUYkLk1)j z>X+Gk;T$Y6IYCmQu)gPIAaHYl*~iA-*){-Hw_|?eL>T)sx{UgWn+wvgheK*Ui>A-|+39Co z%WEz&jVHOXKLuc7CY^jnU_vzb9p%W)kkQ(3e$x!a&o`gGuSP%EWN0}yZSv?{XO72J zHr&B?m2K}S^diZM7GfjHHUa`ZYn1SRIsobx`}@|bM>*sJJa(S_OCo7Bz)R9ibdbzu#hPP4^SMb4L7LZ--;ca<-$&Yn_GXPJ)uaWu8 z4?8!p<5kSWMvE681s9i6il&Csh@r?ObPFY~G_qRkZaLZ!wK{!o=mhr@-LNv{aY%>A zE(U9akE3l8ndUWOsH&jql*zbml#p`53O-Ql2V;h=@57uY^uy=>)=oZJrXS;UhOhS) zi!YS`v^Qm5HDAOE=#CN5&V>U$k8qKW7Bv*;q+AJ-NJ_#(%y$*;wGdAN{}X=2L1%Sj zjx7tQ?^RHessGDRCY~Z&JP*W3eA&(o{>M}Pw|IYrKy0;xWLyBI!R1aCQV>4zu*ZP4 zKExbw>_4>m+R?%|Tes)4o#V+!L3QynD<)+$TzorX;tjVEa^8=t^0WR971;DaP|j%D zZ}VLbp%?qnJ*NXm&rleaGE~1HRaCJ>fXXs^*^Id@mLMKy?3S>EP!2yqqx0jisIjK3 zyxRx*#P3>k3*IqLi;ACro7MMI{yC6LXa<=iJBSME2`_l(@r`7)hpTmv;dbTIIw5|2 zJNOo*g~vNvUpjwDv+P}bY-Kv}arTp?qOja`qNvePD^aK7DevXfapeF#t zSvisut63TN?keDW&ABeyMyOdHbF;Ndjs@n5YE?8$d^Cioj?l2qx4W7ts>*M_+{_6B zE;0FL7Y!2M2uMg5(sSU;7hYn>_oeEk`Pm}9`+pU2Ft(>6pR=ORMF^!)-qo!tm{S~V zLtm;&m7TroSZwa=;&T5*m%j%ihrzX6=zb&8SRGtXyOaQd5cJ6 z)xqC5afqAM%X)nr(u0gV)CB~yI6PAqpIClVX>O+yOqpwHf1Z06h4ErC`=3;k!bN8G zs=rcC6LCWH%dP@uxEIWQrjv5DbD;$WU??nfS6qMlY5ddgE#>0?f^?VAhTYei%i4*o z_+uS!O+o}|W(&&les3`Ug8NPA?XYIiz8ToVmF8NKe8v?2N>f7R(q$o-KhKE6!dx)W znY2jZgPOP%bfR#6Uo9e8Gzj4#(|;2IPSAj^wrJVyOo#$HV4&1xnjpIY?|IfWnfPs4 zA*wZN;>9mAj~H-`!x=`n+GwxUvJ^Kn)cz>b=L6s4;ZaU;_U@i9{WBF=e=0VX-d#7l z`TFPiVV#$q=UG!Z;L!fyBNlHd`r~b{rUGbO?fVt&c~qz-zIzoDps+CS_3()*1P~e2E_D@1WR578~c+{>Vx$zav`+AHX`uI2cI@ zTm!%v%TKfY^32pjK6HI}8fpvwkkbGdF0b}c=zm<*yj>}X1=CRHbbS@YagJ*pUU=!uD@=<1yqKCKa(+Kw%Js6w&VW}LBq&`~=)0Z9WOAsF zXYTRC4|s(*)H;+pC`b%!@{>9wI9!h6&^x*RC)wDhSG=x5uggEyzw<#+2Szol`c??GbN~q1dcJX+#upBIU|dy%tQ#e(7{74!5ADYRE5Bv68r#sDXV+K@Ke4R8~ zxqosO{{7qeP~Rm^`N)?($2%x_@t)G*3WVU`{-hR!!vu5aa<7!k0s4IV+!?z@%OjXe z^PNUOkDF#oc|GgX3C(BVI^P*1`3mPf$Y}e0fo5~EYF0|Dy^`;y&{o?jBsbdc#q9`U zm+|5*?Z_`hGvCYsz^pC4=b-q)7Q?fI^7~F;HSNvi28P0;1nNC3v9Y069Onzc6JrOu zGqtvNb>a~<$aa(1(GnL>Kqc-*(Xnk=)_^;R15$`Wc|P4ja}L0C{Bn78in2z>LV-p2 z%}|gg+i;62CUY55L_ik>D~iL5z6P5sRyqJgJz~j$FVlRa=1C5Y73Ft#h zih73X!qB86-8Ttca2s1KLB|A!eyPkY1O=&o+CA)=;Q^{m_)&Q_$L~yin#rfVp`qC@8@h)mxqvYI0bAc`J;3AN%Q@(TKVoQ&bUS|V%fsT2;HJa_w ztuc-IU8yne2UOAQncFTd^bPhe`x|_|m<9z0+?KN7k5*IMY2$;E`6+wOc9J^V61%e? zXWXdl!}Y!z$K|1fr66zK$J7VP*;&5I%}N0YzH@55giPfGE#Wz8Sh5rfWk^SQLA`+f zD+cp{YmhZ}+XD5)n;t=d(PkIzr5gr&ZALD(Tz{e--^nfWh*#4>ImG*%mjyUMrc9gL zCJDAY8z)o7UK82#Ow?C^ECG6_;CR*9XE{U+>iruIbx#vd_;T=&e5%Y2<#R?Wr z<%T$2a4Vnl>7wM8iU0edq@#m&E!Aj=hZBp0+O7d(fbq41k^|8s?L11jTzmM;Kk;}1 zZA&j%{L=6{mU+2_k+)|d8K_3=ko(#F-b#01k2$cMMm(pG{XOhU1M}~4*9bgzJ4;Py zD7@HW0nzpP%+c+VK5|QP0^9a(dcS;znXJgjSOWur>DnX$9ZBmcTGnA~_iG*?}e=ZSe&;`f&b{oRZ=L%Sa9KenS7 zO><>dDITa@%W}SDm;s#wHrfTcv?W_S*c8YB5zI8W1zBfdva?@g?p{-;-+|O&7T|R2 zj4AFTT+W)ut=bNuubZDRA`Nxz!(1uK!rb_ItarJ%W0iXM9i0yHQ=0Njz zrjneIZYxwzH<}?y0*OvK>J4yD637w$dIt{LfvHaK z=q`9aaM90OX)cRAULzPr7&!iTMO6Uft2UxnY;&j$Kb0?Be0%X5N4bv3S^wRtFI}F@ zcx6*$g;ufJ2b9(BW=PtqL8trfRT6KjtoM@vn7dB=CsiIi7>Jc~%RX$(#n?SBhbQJ# zr%&RjK)@G*Frd|h|GqvMBHF&Ymo!HVL*rJG0@teHT6*bXUDax#(|)qAe@K7iXOY5t z3t~L?qWHSi%imxfMYeWlyo-i{H-qcs2J8p#+{dIQun?1rg6ynUObh269FzB))~;XL zGjd+)E61=nrx@;hW=|Q3iCi!QD1~$9EJ*SGhsIzH6;A6OpvnoT8F4Dqu;qxUFyj!) zfNs7eUBKOO=J9(n5pVw{XGp0;9+)0&8p0vx?^dvpiQqCKawlTTV8!_l%^G}GCeUs8 zWQ97WbA$MSq9cZ|_mvR#RmsBlHS3CbF4LP4p6_VA7|Dm6m8d^Xh3Af%craI?Ezh9v zMltaQ=G5-Rb%Uv?seb|NYN-H4Nnu`w2I$+-7c|5t7ny6;{Z8Olnk*X=g!G!`pYaf- zQf;*TlVhhlDZv>~q_xX}qvD;0WWN|*OwO1q?Je`SV%0~FK@(uQz)K^}p@hhV*IC~b zdIF}wDAG+Tz1c#`XyJn?k<+@a^H@ND?ML4fb{?zh->)h;2{b#zvpvw35)6i|=-E27 zgFeZWdm}f8%bC_4O~XB^H-NCb{2kLJKgm@W_V!jEFF>tHw8P-_%6#0=&xLkz>zB@J6Tgh;InJ3D>^ z7^ju+^^tqajHUlveWC3u@=0;(6*(Vv40q8!A`P*-lD?ygmn88rM}5@)Q0FEM-f=abI1% zKp$iT(sD++K$T&f30WJcD7F&tCf$;Hp;)5pTGMQ8H@?HIXxvPx*pAl5R5W%G| z6PK^tr}j$?*zTJ8-})Mk#7hV%3d7N%JrT`{+~iNNx}i*(VtpB zTDQ_~nLQpztFUf=FCVBpO&7H|tOZ<_$FpLVa0-sR|4dLy{+ayb&ai8rER;djfo{j| zG#C~}0s3CP4KKQ%{1Kq0M%qK+)0*Are1rZ=#f_e8v`aS)R{M9$-`0@F&bbN5n~l~GGew@<8mSwKt%JK1r}SR5%Lsg>C$7VTg;34%gq zxGYAh;BM>7{f`XaZ1b1*PDS2PU$7-^V9f3|=A&hNI5vO(j9)6&#n0>HCXz0pVx!^m z-Sly*y}Y{c*_foIy@|Lkv|JBq!-ULS?>K4%tV}!x ziGx~%5eq-H!_{yTz465ouRGFD&zDz7*9r~eSg5o?%9pi+WQzlyFj{NtL z0>f##CivqqcxuKsPlg}O6~t8MjqZpOyJfC4+i^)I^S?iq#!nW!OfFZxLtgSDwmCPB zz8mP}65Qg8hjkb{AB4SmKengkSDv7i&-Ohb?lA^m`W4R}vIP|FbYmfjh)N{7N7JbX~4^Oh4#0sn?e zl8T5Sw}f@mO_==kQI~_UEse(bLOuIBNOuGHeqx&H3zP|5b^3LRv9;3Ml~L4leB|#< z9ig-|dI!9yb+X)#A-_r4S<%8h)~)l-5U znPeiA@PeQIH&eNLY`JoKv$sL@1z-k%6vu5q&S(M2^zf9$T)ag;Vx0;H&Ph_|6N_RMSrUCEVfy&yT@Qxny!esNO> zavN_z!PP+@e(cyU&R3@_F41E}3g;0=KIQ$ubEa1rycxGN+MuXRufqoEh7hSS_1RUqlM#x2+ZR0AExIim*w^F zWCjw5rYw|cDml%oKh^GK5>1=038&vk!ABg$OAjy9W*$ef8CEXy_g2gons1^MGWez_ zhnhs^c8RsGlP3`|@gKF=_ha9E`Slx|-9?+h9^0rxm?rvY}&Gy;QXdQpzcsFK0HyC;6d!1(24(y-Q&srDjn zBQE+N1yyliRSiBywE$I!3`tf<^_|#;2TJfr%|LlY`C&w17&x#r^VR!#U`WGh;DIug=o0H zp&0!WUqX|d(ZvGKKe@;`fdj}GOH4@5c0D}hU}sF{phs)cQXMg|95?|v6Zvc*rLpKb zX`_$?_Fu9Yj%FMBPWfttJ6FMALy?~^NC#sx1Ed790GYzeC;aR418?EKkZMckZie#` zeDgzxo!PH+R1B78e|wo$oqs|oc_aYI#|D24 z7rd?a$hHVn&VQcXQR)V9hx_0Zh0j6amKGNY<3{!B;Gt$B`bbp2#!$;RhdPlErA23N z$?9z8YTwPPdg|)_3OrWyHkM30ZX(c8m6DVa75EQrl$+ZOK93x$PgW~wyRrS8(4Xe; z@?7=7-amKXZDa1IKsl8!iNQyl!K^5ZElo<%CH)bA`0nCTg#n;puKEEY4C*WIm8F>U zI$e`sD0);}zq7?|H;RX>%Un0=%vSz~#zIKZku->xpvXZk9(QQmG6?I*4=wMjSFDQ( zAn9c2GuMe=EZ1r1+l}`golH_l>7&EBx5#R{uD4FE`fT-`8kX&s!3wX1Qmf4ihoshO>}x9hikxd4$Z74 z2sq$e!+YZ!(=Z^OdH#m3%b;WJ8iNO8$sCak$AqD@Lf|WaH{6zN&PT*Ud9pxwTG-$B zH_Gjj!fQu^WH^N&m&1#j=Xr!!Ru^!O|K8$Qts=%st-WYCVw8d&_| z7S-a*ju0H>z)ejqIJ^&_LWPH2JC-g{pXNR2Sc(+s)@4R6UKOr>CL)Z$`9dIHfp@HiFE-Dd=Ij^uK8?^i0h+{Ow0F{$kekV;TcNacJ(ayC@dAGGe^u5bmcU1BC>}`g!&8g} z(KP9t#YFk0f-MBEN7BknGq09WIn96mDU5}A7?F``D5UkX~C4U z?@w?56N6(@cUV!ci-RLSS1B=Pa&?Fm{ZO$8IZy%I{gP0oYz$PUy)QuQen|#1cSBd! zwGanfIn|q+&ccK;Un-nd=B3joaO?XRbkYtdQbas0Q}O;>p~8FFU))F?9U*p&5c_vY zMW~E8Zb)Sv7fqhwnR@ow{ruqI(z1$yY-2$Ady?a?-dl-zP>>b;3OZqk=w9TsU991% zy#baMoC@{|NNoy*Cs`v1cE)K zEcN4hNd_s7Lt}G;#HMN$ivn5I%_@}ymh+y%%kS>XJz~hO!ca9`s8nY6iN}$I+lEQg z4>@!d)$~Z_)=8&N(>xh+ zPshExQC>h-L%?I+T!xC|PgI zxlyjaxS23mybzSI;10jaF@f5X4l#n@QXfVXw4-gVURazj^7XiC_`h3Lsbowb`PehP9>GZh?nP z1=jEQ$7z2!g)yiQ)N21CGB|4xNvNRXjXK>5vm)uim;t9zjGz!@f@H||ODWWi=ex4) zO))`1W;+(O=lf?Iy80o|x&esFNro0_^b3#cL$bl2#<0Lr)UT!0J3roMyEYSuIto9U zI=1$P7d&b|W{~QHDrRlEZbsJW)USu86h?-r1SXCD2%+$y6n(SdK$ISlyvFbu%1cGE zbNkugTM>4Vpcwvl%IALuc2>%s75k&TTf)%ceCPuO3GoWGiNic4#27(7Ufl`USuMjQR#7myZ` z7D?~;>9yB;r3(@lPdck>*BETujyXFG;$H3X5QjA+YLJT2Vbgf&Aa*vAR73dK<_!uf ziSNt9*{T?B(I2DH@5KE!+)-+yeU*S2#6Bs68Rfsu)_pIPEq=?<`e;8KQR##%;mOjf z757%K$12uMJK1kF2@fR1EY^!Xh`{#$axjB9 z|IiqsD!!@KuQv0arld@YJ?bn~bfK zkNsCdhPF92*gS{V2I%?Wq+R7WnE3cuQ`t%dWm`hVmMMqbcp8EEsiTBH}w`3m^O2*BO$<56kLD zC$lr@J$#x5`4{17%pYt&*U(+wT!8_hyX!~qq8 zl>S4T$+?x#_`EE2MB~%E0J!s=Z~np9UJjL*Fd#w#iyu6%lK320fISgNuVSPJ(P%+R zaH4MgK|(4=t=)nkr{vy~5s0(GpQ=5sLyOZPQLHl_?H@^n_N%2tR~8Tvu@e~%o0*3x zHF)POD^At;<)_M*_-(}hp}BBi;^#zOI4`L5Xm4_^<*MHV)P6o3LfLke zf^Ww!#Q}q5V+>X^$u6*U zdl_KCkj4D3F($tkIDJ?IHZu2;l``hDKLHfR)!3#6a-*=nl56<7m4!jxi!0LmNilrq zmeLY9t{>XaZpEyzjs*QvK}$ano9hIG#UF&z*T7RW9}6y-+LG<1(b-?9zNt|%&AS^! zuP;O;M2|~}fSf?Fb1f49y-8A}nHFQChmv|7sO; zl}DmUNgY^1T8;P+cc!7s#8Y*pJwE4PvH`=_vRqqQd1vhXL7y>@W8w%@`mM}?t`%zV zXWASdG1{xXfG9@w?h4zbrDiiOCuwnq9NiMVcVRRKv_~%Zn=Or@ zdRFDTuZ}&l3IzK+%So zI!c!=Z-~~YIEbMc79u@P3t|Avqo;$B()50z&C` z_ks`EG+IKkDj(1_-nfR>V8h#W7s%B{VL+)YR6KlEHAu@zD#iDtdJIyn;d7hwtgvrY z$z4%uwfm|>P|2-D@FLY=@!>~~$8IWP5ETYf3X9F0itCwaCE;)jWgHG=(6H@B^4))E z@DWaSt5#UEDL9RzyQ{)k6i~XfUY^MqS0g(@B-X?RW$X|Aqj#Zw*j_wn+NAuVYY{O4 zAA!fgx8Q1!T1`hpRvFL~ubLFx+}!$O`2m)34+_zCQ7j)E$zywQ%FoQwaIn8O^3jV} zh53M*0-x_I`f0j*#j69q8+3D;kA5*9G37Gsj>N{XhV3&nL|LiOV+txRCMDKhGyujo?*j43Po z?XC5QLE7OZ<&)c;Goe9L#=Xz*5*|~wGM!qCUfUBKU*ZqtH6KAEYNQ2KZ;)_;c@fp5 z`92?}R6ElKm(yGCh!iLk=bp1J(-OGld0ui2J;pULzoHT*k}MBdlC($sgWf}!qUx1O zk$%k!&Ue?D7fflz!Ma=KAqI)h35WRYC#m+a^@|7Asmg2nV10I--HR1knZ~u1!-OQ# z8Kld+c%Idt4nb4yuH@b z^e1fyU7Fx<`c7c*G!u{wW(2*ft~YiO&1;Sc!mOCT+1LnRN`33XFWw{j<_|8!En5ix z`4Vg*%8iszZ1;K3HM~_mvO^8~U#B*FDXNc`B(UJ+Rz< zj>z!P;MJ9napQNkM3DCO#+I3tMOnSk;?Q9KNmf{H>49AMXJu>4zfZBtU1l#`SAPiZ z`?#_YKU|i>%?7DQD2!IAVbPWb8X#(Z7hnI>YpavljkaSofPw&|19EfwdeT`(Os`Nt zB%>4~z{BU|>c-v(YIU$8zC#k2oq4CK&#r3WhI{hK(;|WbUFkS^Y;%pQm3Zxhx?uqa zg7h6tS~NS{5!!8hg87203OkA_{!{fY!g&ozVrj4&!!TJFniC zwsTK$3ju>CDcsrutRYdKJC^BEIXC}}xr>U;x-rTcAU{Liae3QeuhCH0KNPdXK7=I3 z;WZ2&c|6B$hNdec`3p=gQ@&e3}Qs8Dz(Wx~e&QzoSxX4K=) zL^Q*=z5`yBmbuKHTIzNfGZbh7+%|Nxx35FTyTX00KeKe*j7WG{h+t(F!Le?9;ONmU zCwC}~fv5wc2&3YW#$s{YnhwsM%XNRSfk$aIC<|^24YYuBYqrdZ&)fz%Xpor?0lgqO zjx;~u5eyNh>~mOh?HIkTf0ZyTFI&BeC(c12;Kl^fao*=?gFtlK%vp5PwFq*$4Ozbw zA$Y4qo|?G$L9b1{FH^Xy00&*jCR7V7b{(5wAIi?LBNIF=2vk4o_4ZzA!J5CI`Q4so z7meJ|bSgD?pu62DY6~2l|31`}P?3gJ^}m?|V_^D#OzSeD3xem8_X@Hp*-#A5tZgB; z$+L_Z@!=~Z7SOq?a!Oge8mrf!U37aW^sc@}!wqfu)R*~7B*sjA@l(>U5GCs{(fylD zs2L~$sfE;Otv%Rb-(Y<1k29PB4h=i1QZ<+bIe2ch48-2k13?e`ftlM$4E+UH%zIqqwlpoi6B7=yUZ~P#*)q2qatkKmPmGvcBg3I-Ei6+7Gi(rU>7Qj# zInI4<)_1Dgi$m7ZHBg1QNx!ZVUPbw8{Po1oWM;(}Wa*Cc-qN}Q%=ZZY;66(Yhgcj) zP@AAq;51tDV!G$I<*PWiKZxKN{^FdV;z`lSeNO2mJ2$p_RJ(~m{wyBLRxGSREvR*5 zwbv1LP4?N%>;J>lSB6FLy?@iCq=bNkw4`)*gLDc4(hbrq0*iojcY|~z-K=znw4}na zNXss@u<-rQ?|JpSm=}BPH9IpqGw0mr{*>8vLV&~jwSAR-S**65TKt0rKk8=w7^=@b zUG}LP#W}jp_XB@UGtJYDv}(zSnRNqB^7hVbCtvo2)QjQ2Eb!6d zUeXN6L^G6CjtAq6EnNJ}8+-_Q2h3?X)VL`3ND4!9LR}(U)vwu2594pEP%;$yG#>Sv ziS(Qg@85y72wXAQPr*idJncBIzzRd) zzpE#AG6ZJMB@l~Zl`kQQ{Xiyk;$=liRN9(u>bp-zN3PRn(tT9eQ@3anBYZOi`x;-A z16dwvD+L;6Tpy0|!X*ta%+BVo19mColc;_+MCH769;`EFU+xJyp8==!qn|AQG1L+C z)~d*de;uHvQ@xF@!eTBZO4w~*aF6R)%w(IJxn%j2ru;X9VS6kXoZCYb5lqlNzf$As zs+5aM`B5Z{etMrBrCPH~VS<0H_V|)qc(cZ7W&AZ=kmOzWDY0dhn+8J(IQ2iYTyUn0 zIea(Ew@DnCenoc!u=@CNggWCuwySAIfE21h-cVmo1&jFkuOn|2{?Ze_KmlzN^x&R8 z+b3_)85-g|zjz+SiK5Wfm9~$qc)sh{vyl>JK6gw}d@Y7m`W)(KIrqcV-n=SFILuzk z*SH6`uwv*==D{}mI|M_X(1|3+6{y~i5aXYYbi-V^156mdb8ps0p- z`2-+QZr>)JE(&g6g9r)Vl`S@$@eb5UtzB>q22Vc3{!M5w&Hof|JLx>5R9~k1yiER@ z9X1am`cjKzQbhV7D=O6wS(nUsJnpGIs0cT$X1~H%x#*5pEXLtzP=9xk9^1b1U@VOg=)}l~TZK3*(h}B{&BSuog zzpc%ym=r~c)MyzwIZ_K5X0ms=qNu%j7{kGQW^j6i6AdIsXqM*is()+8vw1~m(C6N4 zPI>=1zlPyIyiy1>?@`3L1&yQKrFo)=k(j3l7pSp8jqj0_x9ZW8JGStfhJ#+AJ}p6= zg?gFF4PWj3IBlor3`OyG3_ijsTBv^G92*MNJ!wXEL@ zrS2+2AuLlE2|jsKy7nf^9P_)H zl>b~hi!5So zmh3w%C4a<}re2wBKwQcT;l;J)-EySKOU+eB17%gA=B^T2+qYSNP?gK56HkyIVfwb> zwX4|GLIRUj#%8>ohrP6) zh2S^QuxDSRRxeq>SK-n+krQPx24-=O;_+26FpH>i8j8*kX}%}#-D!Hg#lBpx+9z`) z*R-Xfc}Pgxw!@ayctC@>l{q+w=TU^yEkA|AKnHGUz?vPYx-^3{`F;C+aCG#T{SchY zk`C8{aQ1yg3fdwQ0gq2dI_B<;y_+bA0Ts0Grg(;%6H%m&?7YmGjS|wPMrdgV+h~o7aU#xpM6m*>Ri z*}=Pe_loleFccUlmD5z15pxM?Kga)Cv$*TvYrFKyeTZmZc*Na79e!8t>1%EJF?5bY zzntlVQ5`L?yP~xv0BH2NefdjXhdt>H_~rn}EP`z}9)h?mW_5Y8MvX5Ca}o01z*c;n z_TQiJ&@Hs|l09QeHNu6&%o-1{%saZ4rjUwQ0#_+^32f$v#Irm>8~>qMEL{l6zES1& z*|OMC9$t&_u>C^+HU6sRm63YmgZ;}kc&_JsZ2~SR^nvj0Nb36dsQX@`t>GRA1sVZv z7@B+jAU$0nbv9`W3Q$57ryl36%;kSWI%+QQ9xlEH@p?2db%Lx-yao+3a3axn$H#^H zzu6J^OBdnXprU)$c%VtoB>m}2lLSOb^)B7lHk$^1HIQQedbxBlj~oPxKiM%zn1jqG z1h*}bVwx5f?9iLH=3d*G`F7cv7+At=?Pd-RY5IHBa3ad4S8A=Z4?a9?)#~~<*Rx%` z8Q)4fyPK+KUSjI$>6DR8cn4bmcNpO5i8c8l_ic%bq`n*h&J6petQ{U)*MGm1V*CHH zOM>9rjz*0nw&EI9?Qe=-D+?<94P>S|Rdp z^RF0%{>EfuBXg%=@=ETWArV11TuhlIsf2Rtx{}_7(Bpv%kqtD84N-YZ*H%J+4wKT- zDStXm(GwQ$%94hE)mbQ?Sg8JbPk3(*m-Rx=%;C8TFE62;w?<4Ui2gq`?-w(GMDo6} z@SuTft~fK)eku4kud>0pWR@r^U74<<%)f6{3~D?2gMHs#7uP`J&%aqywPk#@Sb|Cl zbqkjNm4YR;Ghn=YR^epvjQ<|(^U7yj5Khq8Kx4*EA%GEA=Uc&qC zpF@&?qGK6&4*f|NX@xLB2$)-mx|rD+=V|BN>TVpbI-D<_zmLX9sK2cJq@c#FexS{m znqw0z;GN)Ra3S8;3Un>lCWCY;+bi`_?TDX64#m?4r)uwCq?V6U$+N)=HlSX{6W*}r^GxeOJ6X|H&B0n^4 z`NqI9PiDuKiYx7!IEf5eoqgTmwDF)-wL+$hYWutHOy&w@wQn=FQ0NO!;rf(M1q8xs z275Tze{U?P5LD)H|AGyxOqoj3gZs^Qwrsxz(c5)SzxFus-l1$bcr&K5*ZyVEzK z;jq1{F4GT8%$ZnutqXKtHoEaWw$Q@uk{tf(x;lD;*6ZfEic-T(n|Hzs=RQ0mqLgoN?hLhz`zdT8vae&M$FAPUv%@Tk zL#%7+AyOg+sur4yMnO9ZF8rd3R?nBTqHb3bD}9}nK5b#tvs7pjv3yb9M)+EogSSkiM{A|0Hb}SCC^AmjD)ugOU=2Z!Opg#nW4!kAaYiXT z+pmlXP0i!VjKWReAh=Xz^x92YX73LLB|)Q?z=&vi1;F{@0ybCp4KzkbN%)$F_r3MX z^Pd|Q+P}xiwQWBtrm1VZeU;%SWI(M(@vb9Pc;LE;a@VX&%QF?ms=r+IfM(j(-Se9+)&= z+g;85UinJynIbU$!stdM)?V5wea8*ewv1{=Mtnw^A3TWWn&vKSTIg#ScMXP|XUelD-jOVmpi0gb0Z$*{P=KvM~3o7F%(8Q}OS+x`` z$)tW9Q(F#1N7q4QH>GgxUm3sR4@)wY)ygtD(F zwJ`r_jeLk6E!aZ7K!6nxeoZNS_3d8~`wPD|8-Au;gWd?gH;R?lNH<0!>h>*rE5|KX zqI{*<_gm_s{8%3pfUtDeYLBP5nxQG!=~b%Q+oNx2mRxuhWx(j79!(fzD!OKJHYF#O zH2iOZvuf2vHsEE+ZcXDhzoDTIhFDh_J(PGYuCaPsZug+GgR^`o41{?}w1Z1tH!jL6 z;Ez-E$Zu$!+GR-NxqNZ87nyF@MpmlPE6dq>_h6Hv??r{t!pO%0rb%y?JA3C`*b*Xe zx-EZ_g6;Cs?{(iB)Z6CQ$;SxlYt}^VpG@ue$J(%5vJ|Qc+&9eVACi>(OU@9FffTrJ z@<7t~e&Y1cLhcj*?(|Uq;3c;OZJ+KQSqpvWym2T>e3o%|Lq;OwQt&?-tx;} zk&aX%{fU*Eb;E11m|U7?Z}5ni9?Rjhp(am?e{~_LGkI*0HqK1x>Pw3cGeK>n81(SH z_lD!Hn53q|MDN-d8B1meO)f&S$&+-)*i+Raz_H3IB|R6J^S$)2Hvyx7pFWw%IwM zAp#Q+blX;%JCplB2j(1x5b*qWL-4{F2=qCgPCn`S1b-%YYrMaO&T5t3Ec*YM+V%q4 zQDC57y}t#HEQ);nADSXDRI_*r@%dibhNMJ zG(J}^bD$F+DPZz?(tJ(NxIY_M?CTt4lojnvlv=u}=xFN^F6Mr=Z@QO=t8A!CA$N*4 z8YfE;4Dgm^F=G!=VTb}fgVdtg2mxegN=6nes0|+fc|PldLHp&_MUYfRybZ*Z-0MXuYZ*6QLRdiWqes5qe)D`l~xeV z@Iv>?@2bCqYbaP%rqm#BP1(8=y>({~f@^cLSFtV#Y+{cgOnEkP&$VYDsNI6)&C9r` zanrD4g`7O#x|oGlj9iNzswR_ zW^Y=@C{Ksa;t6q^`hkYMcFfMC4DWD90z4(CyY1wF@q*N5qpOU{8mhw4$I&*VWMfpU zuVVmnMWBwbq69NXc)!CcUZ1Jpu3X#$-h`ZJnk{5T=*&n6fP_BGmLP34wAkkLAeN#5 z``My-M#p8TujN^mg2!fM1g$%@5`K7GhK)3_%ev77f{P(Zx*sARX6Rkk`gU&gk*)gO z%Srie+^3_%aFQRDr9yOHgU$>R%I#-KVxoELH{oE!=NX1Hnw8x=R62ITt*Ehp=`2o3 zlx9GjzC>-RK3;X>=J{K16*aGBh;Znqlf1{1<6AR^tgs&HF3}!@s6R)5gEYe_ivy{dplI z`eZ+91-IIK{MxGVsNSw!z)#khT6H8zlJqWdjKC10*>9&)r$y6B2I<3=*Puz0a=nP* zoIK4tFy<>5zVNwc3V=ENM$HFud@Kh0et@c!|Q zM7u2WGf0mLyrPd{`4a*dFNF$=BE_yTlmtXj1y|Azqh4hg??;xXw|$oKlfLh z>MNUivy62hiWV`cNM1FW0FObu6SkV>6F<7iYiyz~W7%-Xcl4~`>Q$%R`Zdp9^=k4( zlDwvW5E-`fyVPNh^B;~0xrfkXXjPG{EELkxwyKqt?34;LQ2Ux*OlXl}sfF^4x+qiT zhH~rY{HoI{uz>;o2Rg_R9bqJF2!5-#>KlS{F0JBDtKJFmu`qig(HthGTXw(6akm(= zAY>{3$zy1{16E*%U%-jA5z$$G^ZZuGjn&~LhlFv_;*Zlo<@1V=9T&smjg|Rl2 z0#7!d`{hl0mfnluoqznU9~F8n)v_JXeyV_R%)6B5Q+(KrSr$0bz zdB#{q8-0slvG*Wt#=g~(n{>=giqXuJ|8aZe8~p^}GZka+KAqSQo~&!}>s%C_zU@D> zupe4nSCa6h4?rau5dmL&w+J*ugv|*>-(6E*6|(J&^)zhv6z^j>BXSRAQ1T|eTcc>FjG9Pdg6}>lt9PP! zxm=aoQ=6Wxhla){|L;qFFkw7xpkJ(wL&?=2QH=hu*Q#4Gr~EA5@^r^Ng}HG@f7W;% zlHjaHX_6D?SQ8RqL-LdII3*!s_?&33(tg>rNQQWczvw2N0PlZ@)d;(9hg=w6#476k zVbPZ~qyfLeem{DV()ZK3w5j0QUD6_AddVQEOt@ja_lt&++}EQk5&>p^d+2}ifIZ!AAZEYt;ucshfLtzU&#gjYTSMtHtC~-)<_YPPR>i!R{tODiK^+qI`X$W#T_p1L~8N4U9 zxbdZPNo8D9es`~%0ijLN?nM`?i<3(yiT>%$9WRHIs;wngrHW4Usw!$JuF;EiJF=v#ef3B$N68dzT> zpL$<8uB{B5MKZFJLb1QGkeQlwiHSRaWy??YpV(qxT)nN19Fvv^E9OuLWRIF&1M-OF zwh^qlyY?Si{-@WridEmsoKs0Je01)XSYG&+GcFERFa9ClTHLQfu?h7lnKR?kJT)`i;-p zR#3&r-T>88J z&d7Xm$uubX-LV$&svN`RE2Hn+=xEMu0RHeFTAr7}H!T5W(phWf(#H%@+ZY+fPnB`*|&wL@m7Us!U1&%O>l(5*{Gq zqpTQF^}Lg~9-B`)FKwu3mMM^UFlfSG_;RZrx46WX2O$`5B1WE2|j(= zho2y_r_B0fbIckW%8?gxs~1AE+KW5KYm13z&^yLSozo6@`CQ1AtDp92EM7WJk?EL(XRtF(353poNw^f_8P|)R zIj1C|AR6%V1n3&20NXi0{tYz-aylarwo^|YeFHrUzo{I?&UZGKaw(OK6BB&xg@m6= zkS+ydIG9uFp}|3_sC_^N&;;NWhm38HK3a&*98XlmVKL8k4Di23t*Uvr9mcYD^f-3ilN5pf91~=2sTvNS0hZ&!cFD2jR zHyI~XfSx7H@Iu2rg)J`;Q|H-IaCR-Srm^X?p;0xv?IGXvT1)REh^L;ZH`iL-@uNQl zTSVPw`}`uS^$DY;8(=^_oVB!cbvpQtn(4+kA~Rie=Vggg{wTu~FHtzSeod`PeY{~m z+=_6VWI!aC$k?L(WW$*(w0AX@3@rN>vMrq)(x#lxNT#aeEC%t+_uO>IgsK#`B(!jj`zxQBMm6*ox*U@%+iy$!Ba?X zeW)VnnJH=~Vosz7MMGwu)$U3arAOXUZ^sk0o4ZK9M z;Q0<=z}-%k?Wj0U#uTAk8GD`1In}yu5!Bq$t6BL5V$Ao zvWJw{5TNQ89Y=;pPplL{88R=n zc#J0NyQgcoT5=6YRnqm&!6r2Jd0OSpj@r66rDFhdDO~JcQ){q75FCF*ESo3Hz7NpP z0Y@J|bF_|bP`bPj@jWGu#`j6Q{*17kt}^KM17R_07Hh_4`u9Y{d(`B3?Pzse8j>oks8e^U%y6Ua}JIw4E=*fax+-1Y4{ z!&$k{xMGHyyg{V$VMTPm&@}gf0cIXK4e;4REfs`3Ik$KlYVk?7Ueey`4(rYKYoCpk zb1tXL@4iL2?9-cfi?xlMTj?U1=je?Puxz3lXrj%o;ZkFn3VG)HC)NgPd}!4OY4av; zLf6+eomZv9eZ#;r^@ucw#s3oKdyC}K?Cnokfu&8N`|N2fwqH(Y>b#f{q=pk!6dx5C z{6uv-(#Idn3j5B=$bRKHv$?WnPzaNGgr9yQp__Hk&jm%p7!Hd8^pMlNybnQC%D!x5 z9#!ae!g8(~fQDjrpZqI8?W6j##r$=Z0N*T_1>oC{v`bUXb@mj)uygz1mL;2mcIas% ze#UX-L296W16-PxDZ*SgCUVK{^!LwO%e4cQ1? zj9KbpREDfJ>znF?qs7rTwoDsZ?t*BcOf`%SK;G1|?}Nr2k1tR#)CsDpS4Yg%DkE?1 zTfNI}uHey8W9->LqtKbidfoJMf@J}n*I2l+j+f%_8Jxq(A5j9F<6KQ3+y6}{Phj}F z?;t-w+9Y)-dgm!ugkFX8-_-dm-u69??n0?vF7MAeO>6j8M-$B-@o3_zyx(JPxkUb7 zfY%iuWER8&F3nY$LY_=dAE-S>0t}AtGoc;D1_3>3GOTpin36PojUs>1g$L`G@0!sB z7Jt7@JrC|j;vdoyzaDKuR#|qdVUJKQyr<@*an?8ML@UWtky&f!444)AZPE7Zgbz7< zF;~oI4(c?9Ac$H$?OA?OQ&goWG^Td>qvw1v03NnUrHdW`m7Nzg$mr?Lp0C@dW?yqn zx{8$OTQEn<9k4EbdmZop8_0$y!x*xKbS9tCQn#OQIaMIM@&X6G_hrOq`n--I8%s@Y z*J)ii2qU5X1Q7uefWVFcO()rAWW!$0KGj>A?ty*r_m*{DS0@@=$)sk1AGy2T#)KX~ z?c%mkq8|LOxu*9xOoAA4k76jR(oZcIrh1Haq4c@1XAgLrX1$2pzsRPzbf(Ri3_MU` zc-mO|dcnGL^TVug^4LRvg*-&x4-Y=fGW4tGBzwo?p0qPQkx?3;s-k(%Hjb_vqJPQK&#!9)$n5L&QbdIx^O=CMxrKr8{@@f;$dw$jM*lRdb?Y^0w9XY9yNPRjDo4 zg(H0^;Be)PEQVgpLO7i${TT{OKJ84_A-&yI1f7{UGjZ1rZlE}IBMYe-e$#MI)jC6t z2-@adogB!a0IJEp63DO1_26MpL&&sN@vL^2<&F+*SRn4gyVxDbfljx|0Ang|Lmoao z8L{e!!FznyS4F~Q{xei!rP3l&a@F5<2ZqU+XbbV=l!NGcP|b#N8exrijXOA9wfW{L zE)AU@RUWME$mu0?;mkp)aRkgO$bS$AQ;WA`g9psUcNi4vd`&-h-wZR#&8vtIkY-gKC$vFbg=zMnDUwfyh5Bq_SGR@GSBMxSCrTh)0sU;Ts)IY6R}B`%UZ)W*6H1%BAD8_X@OX>-2{M4EBYY49qq@h- z?TZ@QQr>1=f(LLC<^6 znR3TC^Op*6z6UOd^45YQX@owr;ON}+N`aKohvIyC`GxE9wKl#t;u!1tAG;@EIm8gtUH3Y(rER5!A; z{O#y`x{`xeq;!7S-yvpCon#Z;e;0jZ#LRzsUZ<-XHSV!3I_(mBoBjIs5cPoZ7SO;6 zfmR42zxSHak7i{)v?KuVPJslZuCMw3)4;7gAmjdr^Zd^v6oGgOr3FbonV*=6ve%fayjughneW917$HafKGBKK<_G0VFu-(E{ z7a^hQ=}bHB`2+Jg1)lj$$GIdy`hKpTmhy&Ume_ZR=<0;w--hHAK;(JS@ZZtr56W;< zfZ5lMd_pqKn$pOrP^P|ho}i1cA`*2q%KN1!A6mHM6tIHopus?5JUuN+Z_T`J_Hfk4p{A490 z?K;3aO@rjf@)2cnYj~Wks}UMg36SqM69pL-h51iLIFTuAIQ3W-NvngGJjhQ8 z1D8D)+;9KLr%{XxHcKpBUMY1+v~^?sud!QEl){F=5_XMrbW)2`T?A^<@6P|82v3Vze%A`jgJF` zz*JXk{{)(^+(lN;9@MR$Hf)?RcdpoFY;k@IeXCFU(gt^UqBdP8h7jJ$smquCXZH<| z+(k;L0mFxOdDDpNgVm~;PnY67-fq0f8?PCymKb+f`=qidC_F@$v^znBk%bPUVdt+hBkHrxAr`UU;zvW`J((55| zIx=CMnwx|QLweGM*L8W^3u+Q^r&9q2nHo~GltA)n{Bx1FDnCpP&oZ-|VumhRU8h}W z&aQqNn;htHxDNPs_bde$S6H1;QQqvDW=YHZI;ST$t`es}mjaxHI!JgDDw$_9Ay6Gy zh7vBEAvZ8}*3>zjMEoSjGfF{zwczDc9fDE|cOwT=UDgg2cbO)quxx&FFqM+1Du_&?jbyq8 zhA`S|MbsQB$^~;ue_!0#Rp9@wEX%(SAIsXg0E+#GL#@vfp{_K^sqL@7S#FuBI}2}^ zt4c-T7m}_R%Q;&bJ(po+B+YF~S!U$on5Hu=;@KQco<{4^BhA!gg)=)v_46~!*G{f$ZmY1-=TXyzq+$!n z?6ptMPd1_ElSuKZ&<~-y|BHH6?eB;Ztal$FM)3w{`7Z@Bgs=9*Ni_=DD~MB z`B30RLOw>36Zefl{Vc`K+X7P6QJKgh3pnR z)G6{~kob|t_I1YmNT#7`3oo!o2mPmNz&k*~GvGlQvww_i+ zI*8A#6<(DiG%s`_qIYa;=C^D@_G=3q@HSyB-o)nZcs_m-qx0=2;FPN18m@WSF#2@% z!uB&;z3@E_RI6{TZ}rUN2qRv@L)ZAPy?()u4ot5wD^fQ-Lm*;j4O` zk*tKcFzGov>j@hUG358yd{%zc5o!*eT__b_0kVS6PX#<#@ik1>yR=Tfh*$LfNx{E4 zp&YoJMv^)j^gQc*xVZk_D5G0`@PK<>`|BEu0eZ-`-UKT%|7qv+1L&u3AF!l#`A8%O{7_E{`D0ZgCE| z>2!Q(f_RISbf`XZ6W-6mhUlXNSRxi1!X5o>J%Q^4UkjO7M${y|*KdZU9A5o={mw3Jd3h0fCuImVIG`Um(S96S%sTihLmcDZ8(*_2smR`2{;SLwSk zB9s>A|MxOX6Elk+X3G5D<#L**ZARb8&Z%61(M*DdzQo-!`r9$T17Z8$=(@^0@QM|q_N<; znM;rC+MHz?r|7*FzWx>Rw%4ygKrc3%O&}*(DC<^p)i-}Sk?m2d|DZncc{Pm0C}Ux< z#4wPw`7D*GyE+rDCvu-F*^<7y7eS*@(Gb-XBD>NT7Edh3Jt}%l%pTN zVK^~AaE~{ZR=YUPyv5l{FgklOL|w*D78yrRnVF=!@wWf*V_BnFKDEEz_lU6}Fci32 zUo5QkVW#&WHM$Y&{uCH>mK^H-j1<)+Uvlr__D+u=IUAdr7tpgv>D}1*cdl&-qRH|H51gjrIxBp6Yu?gYk^?N+MxTd z>69qj}oq~*MIk{Cuz2DW>;E%cWAQtb9h<2%9!?JFWLe^BSE^-o8fx55*L}6qi=i_j(L*pAy)rP&(v`tI>Ko z?d6+m8$-WCt45vQ70RpJTeM4pziok6-WjI^yxrMG$8S?(mJ~4G)Btd0XqLYVF^R-p z2J?jNfxE{DiL|)A_5giG=woiLFYRw5BQN`>ST_aj3}U9Mui#Ww5HT2fvPNNa=Qgxy z#vw{xZO|3-;wFDIc3V|HK&;N0znRb7O{Wpx*};8^@&u9bIKgky0W@IWPH{s-P|2T} zx;i7wz8=TGMON72z7*znm#}k>@XC)bKVn};9~8qV^DB@M2!cHZJ`2}?jsg4Si$)Ks zrMAw__O2d&)#Lu<8`Lv3f?B%CvxxT&!AB74E7h$C)Dj}$e}+NZOtRd^dDw8I;_PC7 z!v&7!*P@Y;WQGcs^6KBisgh?J5g)QLVs_4gk}FX|*2w?4^e7_Tp~Tb0T)?BWaNZ>R z!j`g7dh3RYOj&xt$cJ3JB{IM;@GptaU38Ky6pM;UF74}z)WN}p2ohj8lHE>F0>`x$u!~q(bo2`N>JpzpUHaN@l{Y(Vn@W~qjpP$>!9&m#D ze|4-=t@-f2zm=M~&{(oaF|44Kq+t?o?>GN9jJ8U>IF@|xFwQ4c#6i?oWCiSI0RFg^ z%h!~xr70=-xxG!~1Sivz8<9(w!LcvDRsnJoIMcdvin_$zz3rDo;3AkcR{V6>6^aZ1 zH%j4rEAgY|U-LeUT}$Uhtb79HQ!_23&*P3*l*(|{Pvx4lUET>2%Y&j(dk~m*T5!^a zlFWzI_67s3arnM!uFK7*Acs5Ua(|v zHdPwH3*d0-3CQPdLhI;Qg?(T2a0u5j6I-6D;nr_rmn5NTuAzlJ-vf1c!;r0r7gh@Z z^33|=YXN$>ONe`Qn8ujIqe9Kp6=yn98d#pBI3u9(QWxgWu_{~q*J<(*s+tPAfLeA8 z!xa(5?=01BNu8$1AB%W=Iu{9LPJ4AoY~1VKJf2$lA!QM(i_>bIi&u|avor~0u?>5s z7d+3VS!=Eu={NA%?uVIrnrqqVlIe46U(ct$+GRja&)#D{j&^h(eC{n@N=Fc#pBoi; z6|FQ}HD7c)4r?Iz+8?^ zG(GC8>s6~wy$$s%`&+pTCdB?>U4GvAA4Y|ZoJN`)dQL-x%v52;!jrY?Rq7OxqBj9q ztKJsls%klt1geuUO=K(Q0x@LfC3uqMyV>AEiGYK{;^38f7tx+_Dv5+V7RuEg`?6i> zAJOl^W~g=fb)Pj+at1Bv9^`!)nBkA$h%!RvBY#0JW(Wf&(vY^Mt9C1G#S-gWrY;?1 zKO&a=spOTO-mY?&o&Ao+{a}Kbn-d!ySaJbvC~=B%km^+8!Mr4L=(?kYo03sYuV`xMo6g$vwJJOq&RNK zPW}OK{F9%X@y|jW4ZfT~0{-$`{f)s@sHMpemw6NL{Vm-D?V0zjX?My=rwP@XwMY?6 zCAW(xyuq^Y9|9Ie)`6jXWk-&N?c!S%oy2IsX77wFJLF-)T57xCKdx~_!zXtQ;QLYb zvBZ0wX!v}PnR&VSce1y@8lr68Sz`3*%}N(tJZ(3+!R^&$Be4m{5`8Ob6?Fll3z_M; zY5EMB6>HAhQ-KbUvqgRs0j2f5jUjg2_lB)S!=$%RZ4{JsT~U zBk1l-X^`J~Ot(1tfNPV+b3_UZ(JG;?NG~#J_Bpev(%~f|=My;zbX{efcXlbqrmys* zNzAfQz-mn=S63AV7IewhEkjG~Um{|!uA-NGL{e*eAD3aNG7j?jGMG4}8{ z=(kk$ndtZpRnlixCw%IFO1Go*=3l%a2>h3od48gJMFZ^?jN_66Ea8F@%yu&_8cz=u z8pvDdR8U zAf*2rT5*?qxogRGsn2UH*aBKY=2ZRMc6NphnEd<3(rC!S@3pcPOU6I9=w<48$>b6= z!iUQ|++Kj6Jnd@MZLSjDjFcE~enD5PqwBqQsDxyFe;!E_TOS|BUQ zjr!wvZ;Y6*{Lq@)Y3=OJqA^yeQD(qu^0Qtw+Lc?McxF~$&M>v_+c#0N`xcue4%lTXe++tk`kv+kVlfi{c6&T$|Pe5kxS&QM<8^%6~Fql{gP z&jkNqYtJPHGcGad+YvZJ{gBYg3bonYj3Caq=<5%lIl8~i7j{+G=$+Ci_hJ-Q7G})C zrix4PkzkKg3J|j6Pmt#zMvhHF_!;3QximwF>8zr6@XAv6vvw`Tcb^|(8q0T#n~O;2 zW6(eFH*K79r7r%E%QDMV87~%{*fBc@GZ@6 zOQ2n@S{7gEr7REUUOA!RyDlSHU`jirZBL%mdZw@%{HM-TE2L>t+21$NHe(h`zlzb! z;f{st`^PtsclK2&(X?WRWKys9tg_cOz^Q$k&ah&BCu2+dpT2ic5HKz%q*`!&OHO{> zWyehyECv$<9W+-hZ`>a094LQHtgL|%PfFwLNUM-ampR{;=@=R_-p3`HZhE%-AQSi_ z=Eq>G8l3{qULU4?@@9ZLk5^DZVFlZ0Z0EWmJv95HL0vv(i`LFaem-_8_AdQ64Hju?Yyj9XnfU-r5`o08E9?1pHQTPK0_j7DOQ;}^@xW? zB6$J19MwOBmQ$E5_7*cB#46NZP2e%=3M=|;x&0qgZygoI`~QK0q9TYON_Tg6t278p zH!R&DAhC3a(%p@8cgHFrv2-_zu&^MtOD!&Z?tJe#_nzPWyJydtnVp&E{k&4rJs8Pi z03+{;a0#9)2T@)&Mi17R8zIyZc=}&Kx5AK8g$M0Hf*g9EI`j-R=EAN12L7^rO>xq1 zi=$HKTPg}qKbKvt{VRtaoG*Ke3d5HsNY3Yn z{{QxSg7S%XY7=UH+EFF(-y#1@TLAx8zA_-_eDdJyBzSD0o}kg+043=)Gukn(zMsn; zxfqhH#%d|J|B0Ttu55*S35`znx)Hi4)0a-^@S!K6Oxq)V`(X44kV2f(H&ged!?CT_ zc>CzneMTnSZl9XupW47)#*WCH`|t#dPUGmGiOst8)gcHeHo6@Lh|dM!K$Gdb1FEq~ z%n4>H1FRQI`s_#)+)BjNrKh6=k4n;c>YE#6qa1&8dG8@24K17?e2e)8nRFqK>dJUR z66%O|$=1ylw2~y|c>fXr_DwONMFD1gW{g=`5PpN5KOu}YbC z>nw@CZytWbj-`j^D(Jbl{H5StO-4fRQs&)YN4blDs=U%L`E8SBfNsgNVQMG0!|P=- zSqGlL>P?WJ=WqxTLTmrH9Y2#kc!-fx3Mc3F)K_JKZ_e+6-DPuZnPZX9u5?+SG;@m8 zt2g87)3==4i9GY%xwWm9pOq6!hgGjKezB&P!V2!SN%Bd9--kS>U*@&>#E`cTfVb#n z{$+dZqZ50t2Boib1E9ksmx^E?9kPjv(fHZa6XZsdLEtM#MoN!?8jx}*^b8|oNvlZc zIj}p&fwCVR_Dc|A@J;Zeg&Akx| z!uHPsr97j3o90Ae9u<&l`LtpM+kdB`ImGti;}PfjBCXoOB~Q>A;yQ~mv$2NiQ%`)@ z>=4ce|GQKzf7&%@*zOw|!>E_#@NKQ-%N@bPfbCNB4bGkIJme0)_n3;E7BXEz(;MwJ z=}fUk9%*7&9teL~7DFD<;(aF9D93g%dWM%z#SuC z0Fwr?6tvJYKsPl|0=f-Jx-80>BUA3^>7RQtRi6gBh}Pe#ns9zDjGle5YBNQ|nQ))T zTl)0vhh5*}?F$fk(nADMXpOpWOu3{nSU(yX&ty{tX-*mqQOA$$DMS;byO!3gFuUbW zX=-xlW_*i!|8GZ#nW!AAr}HUvdZ#8Q(X2f5JrSW)w5rtKgF8#ZO~9ktb1avGDM9<} zyTIy6&HeNi4J{Uh5$1p`t|VTh4m*6ein7j#j}y6FV8KhX3c@WC>j1pv(`x9`&`A$5 z2q}#-0UK-plxC1|rM|St$EGeL^_A_eO-vxh&g+lIXKbK^Dn8&FBR9c1OK~)*TLwfO zWjZ4pj8ZO=jzq`6Ijp;pb_wG^aXo8KyRo}f#1Q@h7ZLkFPRBcvX38e=9 zr4oov2-`xj{?F7qhqmF{ZyT^$C|wqwvXJAh%udR0z(G3M{~B|$IxH6GWZ77xkxB4o z4d7=QCLFxEc^IXnjN~vZ2(U{XPp^OyE#>An$_s99_i?s8ddJeJ+J?czA zK8#=SQru@%#Bix%doD>}U*e*Z#9mUO6#7CRyy=i+3YZ9#MO-ObfOmJ!Czw)VjkjE= z3up@)WuhPi=@D&8a#T^-%a)RTb{e0DUz7%ec}+3c`q@te(uQ@tC^PN^D;a{{xJt(B zXQA=+`hh?yz)9b%9z!>qs__BaIi>fd27?q2JFcfrTh$I{x_BzfAW*99flAeF$ngm* zphU9U5GnF}sba(N=KVR4ed^nANs*KW>J1X~P=(F}W z^F`eHroTFJ)$56ukLD`zufn-vv|1MawR4?EIQvzfM5H;+G&PO| z6;ltYimkpcFm&+u`-R}@%0Y{_K?HrFD9zQHo%*Brw+^XAs26#mgS*2GrU?ca2Kk|L zJ-QDJ;rgj(h8C$H&BabIx|Eq{!@_w>Ms+5DoEUoXg0l-$?P{SKrTlOI8O9~H-eX=U zNU;Gl!Sa9~TXUED9jkUTykk3c0Z`UAT=|4w7ar`~$UiuZm=Yfi-LH8Cg?^GF{7Pc9 zLJ37}Wtv4K0KY zePCP8-REUqPWW0cQX+i6AslX9`Z88?BiCM&x)1y3OstS>sj3HNU$zn53h~|tDh>Ti zHW0ZDd3K)6qyg%sEzEy8-I?Ow#7sTGI_ll?A?^rp9F)_*fH|_;BOGZjV^7WjhPnH# z7d{uJcfN0>7E-I!g#4N3SMPiVdA;F;R37K0AQuB1HMmX}sfuJQuN50v$n%0b0SmzN z`;b6LC5lQ1DVB1n!3J99+3W4dQwRsbj~%t{=6L36NzZpTab! z!$Wl=+#NSufo~APwZb281;(gR@}2t5iQN$zz1T3jhs4JD&M*B~Y{1KF0i3?=iy6a| zVxTKQ7yAWIr`-s(p&bi!ri*&g*Ef1B1~|-Q=gtwua7_+!h2*&`YOg|KCsUNmbP>S3 z(Pf!D?MBBCd9aPws^7_8FQw2l=;LKukdGCY8>^Zl7Of^UjE$6DWtAiUwwS$j^79kv zb`Ou!`wy%6vB1U>W3P)#l|x>_)G+ZVOK(d+$tn?yItG+rb|Sy~ZbY#v539{L@zbr~PG5ilEhw>UX7~Ky>cT&Kx=q9<25U zK-pvrC!2!RwR(GVjeo}y6H8Dei4Xf!Vf`&_+7M|;VObkwWQ=%k*|h7#)DF<9rOQQ$ zSXqFAAUXBH?#N($Cnc1rfWEnh-@-X-<++CoLFczn-xF^sY>I~OhP&sJ`HxH&lCqWa zb3pK`q{5&mwEKe=>Jw$~bPk-x-#Gx9UDr^5CDF*2Y`|VnV$GoV*y`V>3U%oZN+yduxWZBoUY}3-c$Rm8OtmQvqeO2to%KxsBv_#5&Lexfa$@4ui zvoT*Jpj-1Pu$h8p18W``JfGMY{Vj0jvi6;0xFue=jl%9CJJCyS+1cA(_=^!Tn|M7% z>B)DMl(AE4^F;<=bR+%LkFt*7g zqi0yJX&y%G>)HP5t3)ewdR0!s0qG+rh*@)k7cp&YZPfpmKXW~c7s`}PYD6UeGW?tB zWY#Mxq2L}b^b=G@HulQIh%$S!BK<$CB%e3`VSSkt<1jwCJbVW+(Z`}yK03a9SZ1>e zDFvPhQOMT^FTybk^R|?qd7fzhWjUjk*5xaFDdn~Zwdj5NPWDos3oH$SAWeIxi!t}( zcH&W?{teUt%45R93YnG1R~IVA>QW@Qjk8$R9kbh;=Px|xDk zD*KS(g0)kpJGyx()#|2;TpZ_ge5V_2Oj~62<9)#7XS`Rgk?uR4xy2`HB`phDdK6^P zf0Iy@0ekQPni+~p77DR&S{K{b-!3Ra(`$G`-2AG7m7d?z?+hfzsHV*k{4;X`yG{+o zDv454f2AX5*Let8s65*nF7*(nN_Vl~w+j zJN{%uH_CbR?-lIh4pBwl(opXup9y$+hY#Tw;I|J?+CQO!-H1wNOa|y2iTd3bvVOAf z>5gw*n*OV=_2gN*w^drKcBN^o(T{^AG?$%2IWFVny%IHP(P2c}4NEPUdPyoGo24S} zpP&X(v}o=^{)mqm7zgbi)I-3lYiMcH4YcwUWy0bz8L0e+pQrG3+v{%;#!GLpW*gu7 z=Nj_F2yBh!GchSLVi2f92{(6cw~*BTQ(Yp3m*yrVRx-Y7Ko~HAFIX@^}5RmbT(1i^o4=DxK#?M!!BaA<^SS zEK!<{$;VR@NzD8Um&I}e!a&%WD&fWVai^B~5%JAer*15Cqj=SMJnX@>u|f6rbhRXo zCQfq5`A`JuZdZMmv6I50xkxCS^x#UDq+@wV)+V;e}MT>fw-@SCf zPq|z)67#^fhYC>C^xx2*UG;S?!90pjOUY%A{pDVY*CY{$8!jyVsYX0p1E$j;{eb#x zM2!OB^d;SG0{@%3-!A<=(ZC21-x-#4Ylhda(R1pPE&l00tN;(a{|y!z zt*&aV&lE+!&fz~xx6z;cC&M8LuW{B+f*H5M7nY|i2 zbqH02Y~rxwhBqYiu!hnU7$rh%l$_PNzH=l!xd7khnzz3 zy1gFKj^;N-;ZLGiv5M(?A|ws6T*Rn^5sEh0I*7jRJvpfdO$$VI<*04YMpa&|5zJIf zf=OlF@$#y>_sjZPoB>J9_bZ@@T`!D%ek}_~g?1oIv^dBBgey69fHsZahemW>Dv9?f zYk9q(zV2q3^m~pER~1hoE}u;*2k*nmw}wZFtfF>;TvkiUu?B0nch96;5ix25@IBI{#qPMlGJ+aiVnAdySz1p zoq`~}?cR6P9FvbZ?YJA3EG*$GY?E4Etl!#?-IaiUOf74{I_*nYCB;sXOwrBxNShj< zeNSLapvlzuSG4oNb6#B)3NT~h!s^JFtL#sE#;bZRVr9SP^#$I7lqTIy)#(PsamEm<%oppk3rNkQq=`u+!G zG{*ziX~m;G9+bM z+FMI{^>kYVUEW{>14Q@}=6>TA2?M325JQdB(-48-CbgbTi#VX+VqsC0ko85e7uyb> zwkiKYHn3-v5I{GUK;mGs*2sq(IDwGXWzbCd79?UCznQNF;WaV;o^qXm{{>Z6 zDT4*G=%JF$urWILB>UIfo!(0!b2qnk5MUSMH-E6$kcdF350HM`P`x6{1Xm$0qEwxX zRQF03AJwXbsla?#_mPeZuYcnoIHN`#{zrs`XdKJ>_H-`>bv!sN)vN97v|o~T;y+T# zJVO2O@Dv>U8|BXWVzRDEJ-~8bQrBy((1o8lM2t`z)7%lUF+=N;GSM_1H>v$Hq>_u1>nHn3$e^hD^wD$bj{5f=#KXRqf5>DL6r?ukb<%yf&JbP=}*H$B$9&ju)wK|Eoux%;eUt zXLvSgHQ8NVkpKR8eyJpVRC10P)b{dH_FsIq9{e)oCS87W_WBsK5*3Tv$*Wn}s3kdj zJz`?V9c-|P#}(8Yyjn9p_I4Ue?zz_hGeM1~q3L$8^Bl`=K=SufY^vaG^7)2LKWp2x zlfT96#l>$9<-Ty>`VU8iX=!NqQl)z8`)d0uH9?dY2ZZiJ_J`WYY;lzCv3qt@4CyI=PLN6S;x zx{A^CTCsm{-H$nT-j7gY$EA5rm5(=Ovc0?gxbg$B>RuRyt#c|;r=-T$pklSGY4!AR zY=nm5yM~8fE3D+{JDMMDFQ~#t>!pZ2^#=D<^z06CSqnn`su7PdC^@{0TU>ndXy9o- z@2va? z%I?h|^B%lrkd??4g$|@f9X@Lkytdx@U`mH@tG}eXE5&V6dpSv^OW)8^ble(7Zu~;f z$ssjKdz=>o2+{LPG1@tLKv3>NB`zk0e*^wktS?{q9kGy%x`(7+3L z&$g{4`f($QX>_nilj8|%{Kgo9W^qs?e!&t#`7-@Me1nT~JyOyCuw(eC;-T;HCgz-^ z?PWf(=?`ta*g9X~dUi4NFKlBVGb&3g=}mO7VBKVRlxR8EpUeefV~=lo;RNpq!nAK} z!(3RjI5^)d7pHAt8>;1xJ#SYwA05D9sHr{g*g9U_tqvX{3N|{#+6aB2|B7aLBI zQZ{Ofnz$^tHS^^hogH`vtYgAsQw77ED%=y3Th4*HPXwRf%n5d18a>4$$8u4NeITcJ zV^C0hWZ?>JLvF{ov0OJ+O=m7IUnC{$C(pe-N8h?@N?$9U$MG#U!hq#EKMYebFfVsN z7gTfr=7#j#XsPO)!FuW<_M8%MLRyEI~3a#n1a-G^t$G)2&XcE^KqKJuO{} zE{knmP0%A})DtI!#xI z=1Pn0RsDGLtr*2D8z;+zsufjn%-D=J(nWQuJxn-jF8to=`;{9CwCmuw z?!>?3N@7(#04O<5ZYa-5o5Yz`RMBIih2y=Yau;eabzF-1q9eloDqvn49mW z9LbYzXKm=R*ocE@0^RXwo<&M`UqrNtYVLnnT2Wb=3x9G=lak zXF#jcY5H|)Cwt}E(4q->5~# zCPogKH+Rfdwl^)87oNYjH-6XonLWOz&BuYw(kRSpT#5cl!Ru|_3qLL3<<+`!mB53^ zsSAGZ!DR+9LR69%|4?gT;eSa1qn7wE0AN^VAe#F@Q(qZbcPvIZ(d*4GYnh!=;NTM z3388oS2Z9M4&Ddvofg0en2;ODQnO_~AFklHP6L+9?c}?ZE}gu@GIeS=afo(BPQ7ro z%pLAbeh{HS*Fk}&p}O655$dbt2WZ}dBc?FP$R7DM-I8*kyy4zLWPr4Jqi(wD`DNzk z`)`C}`T4?&j!lwBNkrR=e}F$inKl43HrrQTAuJQdU(w4RWJYGTmRuTf;m3qctNG=AfbIwlX8YCNRzdAT0*eh*#p z#C4rQ^WWfyd>DsNXanW@oW3rP=uLAHHs@&|b?PPOhQ&D1zR2+JfJFf8N#tzE4Np-O z6FdjEeK_e1pt&$L5W|hRig8F*Zm!Pxe!bmQv+LZq>=Xp>*tGowE*+eal%K6WyLs|I z>s9&fvK*zy(=T40Kt`e>$Y?FLyaBj zwHfp5`-x#k`4AsrwBf!A`WXyj=mnTUE$h