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[at32] auto formatted

This commit is contained in:
Meco Man 2021-03-14 15:15:52 +08:00
parent c3ffe18688
commit 1a6e348922
37 changed files with 391 additions and 391 deletions
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22
bsp/at32/Libraries/rt_drivers/drv_adc.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -17,7 +17,7 @@
#include <drv_log.h>
struct at32_adc
{
{
struct rt_adc_device at32_adc_device;
ADC_Type *ADC_Handler;
char *name;
@ -109,9 +109,9 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
ADC_InitType ADC_InitStructure;
RT_ASSERT(device != RT_NULL);
at32_adc_handler = device->parent.user_data;
at32_msp_adc_init(at32_adc_handler);
/* ADCx configuration ------------------------------------------------------*/
ADC_StructInit(&ADC_InitStructure);
ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
@ -121,14 +121,14 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NumOfChannel = 1;
ADC_Init(at32_adc_handler, &ADC_InitStructure);
/* ADCx regular channels configuration */
ADC_RegularChannelConfig(at32_adc_handler, at32_adc_get_channel(channel), 1, ADC_SampleTime_28_5);
/* ADCx regular channels configuration */
ADC_RegularChannelConfig(at32_adc_handler, at32_adc_get_channel(channel), 1, ADC_SampleTime_28_5);
/* Enable ADCx */
ADC_Ctrl(at32_adc_handler, ENABLE);
/* Enable ADCx reset calibration register */
/* Enable ADCx reset calibration register */
ADC_RstCalibration(at32_adc_handler);
/* Check the end of ADCx reset calibration register */
while(ADC_GetResetCalibrationStatus(at32_adc_handler));
@ -161,7 +161,7 @@ static rt_err_t at32_get_adc_value(struct rt_adc_device *device, rt_uint32_t cha
at32_adc_handler = device->parent.user_data;
/* Start ADCx Software Conversion */
/* Start ADCx Software Conversion */
ADC_SoftwareStartConvCtrl(at32_adc_handler, ENABLE);
/* Wait for the ADC to convert */

20
bsp/at32/Libraries/rt_drivers/drv_adc.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -19,32 +19,32 @@ extern "C" {
#endif
#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
.ADC_Handler = ADC1, \
.name = "adc1", \
}
}
#endif /* ADC1_CONFIG */
#ifndef ADC2_CONFIG
#define ADC2_CONFIG \
{ \
.ADC_Handler = ADC2, \
.name = "adc2", \
}
}
#endif /* ADC2_CONFIG */
#ifndef ADC3_CONFIG
#define ADC3_CONFIG \
{ \
.ADC_Handler = ADC3, \
.name = "adc3", \
}
#endif /* ADC3_CONFIG */
#endif
}
#endif /* ADC3_CONFIG */
#endif
#ifdef __cplusplus

8
bsp/at32/Libraries/rt_drivers/drv_can.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -311,8 +311,8 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
{
can_instance->CanConfig.FilterConfig.CAN_FilterNumber = filter_cfg->items[i].hdr & (0x1fU);
can_instance->CanConfig.FilterConfig.CAN_FilterIdHigh = (filter_cfg->items[i].id >> 13) & 0xFFFF;
can_instance->CanConfig.FilterConfig.CAN_FilterIdLow = ((filter_cfg->items[i].id << 3) |
(filter_cfg->items[i].ide << 2) |
can_instance->CanConfig.FilterConfig.CAN_FilterIdLow = ((filter_cfg->items[i].id << 3) |
(filter_cfg->items[i].ide << 2) |
(filter_cfg->items[i].rtr << 1)) & 0xFFFF;
can_instance->CanConfig.FilterConfig.CAN_FilterMskIdHigh = (filter_cfg->items[i].mask >> 16) & 0xFFFF;
can_instance->CanConfig.FilterConfig.CAN_FilterMskIdLow = filter_cfg->items[i].mask & 0xFFFF;
@ -499,7 +499,7 @@ static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
else
pmsg->ide = RxMessage.ExtId;
pmsg->rtr = RxMessage.RTR;
return RT_EOK;
}

4
bsp/at32/Libraries/rt_drivers/drv_can.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -22,7 +22,7 @@ extern "C" {
#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */
#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */
#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */
struct at32_baud_rate_tab
{
rt_uint32_t baud_rate;

64
bsp/at32/Libraries/rt_drivers/drv_eth.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -28,8 +28,8 @@
//#define DRV_DEBUG
#define LOG_TAG "drv.emac"
#define ETH_RXBUFNB 4
#define ETH_TXBUFNB 2
#define ETH_RXBUFNB 4
#define ETH_TXBUFNB 2
#define LINK_THREAD_STACK_SIZE 256
#define LINK_THREAD_PREORITY 21
@ -131,14 +131,14 @@ void NVIC_Configuration(void)
NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
/* 2 bit for pre-emption priority, 2 bits for subpriority */
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
/* Enable the Ethernet global Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
NVIC_Init(&NVIC_InitStructure);
}
/**
@ -173,7 +173,7 @@ void GPIO_Configuration(void)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
/*MII Mode GPIO configuration*/
/*MII Mode GPIO configuration*/
#ifdef MII_MODE
/**********************MII Tx Pin Define****************************/
/*
@ -193,7 +193,7 @@ void GPIO_Configuration(void)
GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
/**********************MII Rx Pin Define****************************/
/**********************MII Rx Pin Define****************************/
#if MII_RX_REMAP /*IO PIN remaped*/
/*
ETH_MII_RX_DV-->PD8
@ -208,7 +208,7 @@ void GPIO_Configuration(void)
*/
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_8 | GPIO_Pins_9 | GPIO_Pins_10 | GPIO_Pins_11 | GPIO_Pins_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_3;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
@ -233,11 +233,11 @@ void GPIO_Configuration(void)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_10;
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_10;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOB, &GPIO_InitStructure);
@ -255,8 +255,8 @@ void GPIO_Configuration(void)
GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
/**********************RMII Rx Pin Define****************************/
/**********************RMII Rx Pin Define****************************/
#if MII_RX_REMAP /*IO PIN remaped*/
/*
ETH_RMII_RX_DV-->PD8
@ -266,7 +266,7 @@ void GPIO_Configuration(void)
*/
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_8 | GPIO_Pins_9 | GPIO_Pins_10;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_1;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
@ -282,7 +282,7 @@ void GPIO_Configuration(void)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOC, &GPIO_InitStructure);
@ -314,7 +314,7 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev)
RCC_AHBPeriphClockCmd(RCC_AHBPERIPH_ETHMAC | RCC_AHBPERIPH_ETHMACTX |
RCC_AHBPERIPH_ETHMACRX, ENABLE);
/* MII/RMII Media interface selection ------------------------------------------*/
#ifdef MII_MODE /* Mode MII with AT32F407-EVAL */
GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII);
@ -361,31 +361,31 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev)
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
#endif
/*------------------------ DMA -----------------------------------*/
/*------------------------ DMA -----------------------------------*/
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;//ETH_DropTCPIPChecksumErrorFrame_Enable;
ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;//ETH_DropTCPIPChecksumErrorFrame_Enable;
ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
/* Configure Ethernet, check error */
if(ETH_Init(&ETH_InitStructure, PHY_ADDRESS) == ((uint32_t)0)) {
return RT_ERROR;
}
}
/* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */
ETH_DMAITConfig(ETH_DMA_INT_NIS | ETH_DMA_INT_R, ENABLE);
ETH_DMAITConfig(ETH_DMA_INT_NIS | ETH_DMA_INT_R, ENABLE);
/* Initialize Tx Descriptors list: Chain Mode */
ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
@ -396,7 +396,7 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev)
ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&at32_eth_device.dev_addr[0]);
/* Enable ETH transmition and recetion */
ETH_Start();
ETH_Start();
return RT_EOK;
}
@ -581,7 +581,7 @@ struct pbuf *rt_at32_eth_rx(rt_device_t dev)
{
rt_uint32_t i;
rt_uint8_t *ptr = (rt_uint8_t*)(DMARxDescToGet->Buffer1Addr);
AT32_ETH_PRINTF("rx_dump, len:%d\r\n", p->tot_len);
for(i=0; i<p->tot_len; i++)
{

2
bsp/at32/Libraries/rt_drivers/drv_eth.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

12
bsp/at32/Libraries/rt_drivers/drv_flash.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -160,14 +160,14 @@ int at32_flash_erase(rt_uint32_t addr, size_t size)
addr += FLASH_PAGE_SIZE;
}
FLASH_Lock();
__exit:
FLASH_Lock();
__exit:
if(result != RT_EOK)
{
return result;
}
return size;
}
@ -177,7 +177,7 @@ static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase(long offset, size_t size);
const struct fal_flash_dev at32_onchip_flash =
const struct fal_flash_dev at32_onchip_flash =
{
"onchip_flash",
AT32_FLASH_START_ADRESS,

2
bsp/at32/Libraries/rt_drivers/drv_flash.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

14
bsp/at32/Libraries/rt_drivers/drv_gpio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -13,7 +13,7 @@
#ifdef RT_USING_PIN
static const struct pin_index pins[] =
static const struct pin_index pins[] =
{
#if defined(GPIOA)
__AT32_PIN(0 , A, 0 ),
@ -414,7 +414,7 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
/* Configure GPIO_InitStructure */
GPIO_StructInit(&GPIO_InitStruct);
EXTI_StructInit(&EXTI_InitStruct);
GPIO_InitStruct.GPIO_Pins = irqmap->pinbit;
GPIO_InitStruct.GPIO_Pins = irqmap->pinbit;
GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
EXTI_InitStruct.EXTI_Line = irqmap->pinbit;
EXTI_InitStruct.EXTI_Mode = EXTI_Mode_Interrupt;
@ -462,24 +462,24 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
if (( irqmap->pinbit>=GPIO_Pins_5 )&&( irqmap->pinbit<=GPIO_Pins_9 ))
{
if(!(pin_irq_enable_mask&(GPIO_Pins_5|GPIO_Pins_6|GPIO_Pins_7|GPIO_Pins_8|GPIO_Pins_9)))
{
{
NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno;
}
}
else if (( irqmap->pinbit>=GPIO_Pins_10 )&&( irqmap->pinbit<=GPIO_Pins_15 ))
{
if(!(pin_irq_enable_mask&(GPIO_Pins_10|GPIO_Pins_11|GPIO_Pins_12|GPIO_Pins_13|GPIO_Pins_14|GPIO_Pins_15)))
{
{
NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno;
}
}
else
{
NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno;
}
}
NVIC_Init(&NVIC_InitStruct);
rt_hw_interrupt_enable(level);
rt_hw_interrupt_enable(level);
}
else
{

2
bsp/at32/Libraries/rt_drivers/drv_gpio.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

114
bsp/at32/Libraries/rt_drivers/drv_hwtimer.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -7,7 +7,7 @@
* Date Author Notes
* 2020-03-16 Leo first version
*/
#include <board.h>
#include "drv_hwtimer.h"
@ -20,35 +20,35 @@ enum
{
#ifdef BSP_USING_HWTMR1
TMR1_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR2
TMR2_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR3
TMR3_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR4
TMR4_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR5
TMR5_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR6
TMR6_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR7
TMR7_INDEX,
#endif
#endif
#ifdef BSP_USING_HW_TMR8
TMR8_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR9
TMR9_INDEX,
@ -56,11 +56,11 @@ enum
#ifdef BSP_USING_HWTMR10
TMR10_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR11
TMR11_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR12
TMR12_INDEX,
@ -68,11 +68,11 @@ enum
#ifdef BSP_USING_HWTMR13
TMR13_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR14
TMR14_INDEX,
#endif
#endif
#ifdef BSP_USING_HWTMR15
TMR15_INDEX,
@ -91,48 +91,48 @@ static struct at32_hwtimer at32_hwtimer_obj[] =
{
#ifdef BSP_USING_HWTMR1
TMR1_CONFIG,
#endif
#endif
#ifdef BSP_USING_HWTMR2
TMR2_CONFIG,
#endif
#ifdef BSP_USING_HWTMR3
TMR3_CONFIG,
#endif
#ifdef BSP_USING_HWTMR4
TMR4_CONFIG,
#endif
#ifdef BSP_USING_HWTMR5
TMR5_CONFIG,
#endif
#endif
#ifdef BSP_USING_HWTMR6
TMR6_CONFIG,
#endif
#ifdef BSP_USING_HWTMR7
TMR7_CONFIG,
#endif
#ifdef BSP_USING_HWTMR8
TMR8_CONFIG,
#endif
#ifdef BSP_USING_HWTMR9
TMR9_CONFIG,
#endif
#endif
#ifdef BSP_USING_HWTMR10
TMR10_CONFIG,
#endif
#ifdef BSP_USING_HWTMR11
TMR11_CONFIG,
#endif
#ifdef BSP_USING_HWTMR12
TMR12_CONFIG,
#endif
@ -164,20 +164,20 @@ static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
{
tim = (TMR_Type *)timer->parent.user_data;
tim_device = (struct at32_hwtimer *)timer;
/* timer clock enable */
at32_msp_hwtmr_init(tim);
/* timer init */
RCC_GetClocksFreq(&RCC_ClockStruct);
/* Set timer clock is 1Mhz */
prescaler_value = (uint32_t)(RCC_ClockStruct.SYSCLK_Freq / 10000) - 1;
TMR_TMReBaseStructure.TMR_Period = 10000 - 1;
TMR_TMReBaseStructure.TMR_DIV = prescaler_value;
TMR_TMReBaseStructure.TMR_ClockDivision = TMR_CKD_DIV1;
TMR_TMReBaseStructure.TMR_RepetitionCounter = 0;
if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
{
TMR_TMReBaseStructure.TMR_CounterMode = TMR_CounterDIR_Up;
@ -186,21 +186,21 @@ static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
{
TMR_TMReBaseStructure.TMR_CounterMode = TMR_CounterDIR_Down;
}
TMR_TimeBaseInit(tim, &TMR_TMReBaseStructure);
/* Enable the TMRx global Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = tim_device->tim_irqn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
TMR_INTConfig(tim, TMR_INT_Overflow ,ENABLE);
TMR_ClearITPendingBit(tim, TMR_INT_Overflow);
LOG_D("%s init success", tim_device->name);
}
}
}
static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
@ -211,7 +211,7 @@ static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_
RT_ASSERT(timer != RT_NULL);
tim = (TMR_Type *)timer->parent.user_data;
/* set tim cnt */
TMR_SetCounter(tim, 0);
/* set tim arr */
@ -225,10 +225,10 @@ static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_
{
TMR_SelectOnePulseMode(tim, TMR_OPMode_Repetitive);
}
/* start timer */
TMR_Cmd(tim, ENABLE);
return result;
}
@ -239,7 +239,7 @@ static void at32_timer_stop(rt_hwtimer_t *timer)
RT_ASSERT(timer != RT_NULL);
tim = (TMR_Type *)timer->parent.user_data;
/* stop timer */
TMR_Cmd(tim, ENABLE);
/* set tim cnt */
@ -253,7 +253,7 @@ static rt_uint32_t at32_timer_counter_get(rt_hwtimer_t *timer)
RT_ASSERT(timer != RT_NULL);
tim = (TMR_Type *)timer->parent.user_data;
return tim->CNT;
}
@ -267,22 +267,22 @@ static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
RT_ASSERT(arg != RT_NULL);
tim = (TMR_Type *)timer->parent.user_data;
switch(cmd)
{
case HWTIMER_CTRL_FREQ_SET:
{
rt_uint32_t freq;
rt_uint16_t val;
/* set timer frequence */
freq = *((rt_uint32_t *)arg);
/* time init */
RCC_GetClocksFreq(&RCC_ClockStruct);
val = RCC_ClockStruct.SYSCLK_Freq / freq;
TMR_DIVConfig(tim, val - 1, TMR_DIVReloadMode_Immediate);
}
break;
@ -292,7 +292,7 @@ static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
}
break;
}
return result;
}
@ -311,13 +311,13 @@ void TMR2_GLOBAL_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if(TMR_GetINTStatus(TMR2, TMR_INT_Overflow) == SET)
{
rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR2_INDEX].time_device);
TMR_ClearITPendingBit(TMR2, TMR_INT_Overflow);
}
/* leave interrupt */
rt_interrupt_leave();
@ -329,13 +329,13 @@ void TMR3_GLOBAL_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if(TMR_GetINTStatus(TMR3, TMR_INT_Overflow) == SET)
{
rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR3_INDEX].time_device);
TMR_ClearITPendingBit(TMR3, TMR_INT_Overflow);
}
/* leave interrupt */
rt_interrupt_leave();
@ -347,13 +347,13 @@ void TMR4_GLOBAL_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if(TMR_GetINTStatus(TMR4, TMR_INT_Overflow) == SET)
{
rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR4_INDEX].time_device);
TMR_ClearITPendingBit(TMR4, TMR_INT_Overflow);
}
/* leave interrupt */
rt_interrupt_leave();
@ -365,13 +365,13 @@ void TMR5_GLOBAL_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if(TMR_GetINTStatus(TMR5, TMR_INT_Overflow) == SET)
{
rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR5_INDEX].time_device);
TMR_ClearITPendingBit(TMR5, TMR_INT_Overflow);
}
/* leave interrupt */
rt_interrupt_leave();

24
bsp/at32/Libraries/rt_drivers/drv_hwtimer.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -26,7 +26,7 @@ extern "C" {
.maxcnt = 0xFFFF, \
.cntmode = HWTIMER_CNTMODE_UP, \
}
#endif /* TIM_DEV_INFO_CONFIG */
#endif /* TIM_DEV_INFO_CONFIG */
#ifdef BSP_USING_HWTMR2
#ifndef TMR2_CONFIG
@ -36,9 +36,9 @@ extern "C" {
.tim_irqn = TMR2_GLOBAL_IRQn, \
.name = "timer2", \
}
#endif /* TMR2_CONFIG */
#endif /* BSP_USING_HWTMR2 */
#endif /* TMR2_CONFIG */
#endif /* BSP_USING_HWTMR2 */
#ifdef BSP_USING_HWTMR3
#ifndef TMR3_CONFIG
#define TMR3_CONFIG \
@ -47,8 +47,8 @@ extern "C" {
.tim_irqn = TMR3_GLOBAL_IRQn, \
.name = "timer3", \
}
#endif /* TMR3_CONFIG */
#endif /* BSP_USING_HWTMR3 */
#endif /* TMR3_CONFIG */
#endif /* BSP_USING_HWTMR3 */
#ifdef BSP_USING_HWTMR4
#ifndef TMR4_CONFIG
@ -58,9 +58,9 @@ extern "C" {
.tim_irqn = TMR4_GLOBAL_IRQn, \
.name = "timer4", \
}
#endif /* TMR4_CONFIG */
#endif /* TMR4_CONFIG */
#endif /* BSP_USING_HWTMR4 */
#ifdef BSP_USING_HWTMR5
#ifndef TMR5_CONFIG
#define TMR5_CONFIG \
@ -69,9 +69,9 @@ extern "C" {
.tim_irqn = TMR5_GLOBAL_IRQn, \
.name = "timer5", \
}
#endif /* TMR5_CONFIG */
#endif /* BSP_USING_HWTMR5 */
#endif /* TMR5_CONFIG */
#endif /* BSP_USING_HWTMR5 */
#ifdef __cplusplus
}
#endif

2
bsp/at32/Libraries/rt_drivers/drv_log.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

52
bsp/at32/Libraries/rt_drivers/drv_pwm.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -37,52 +37,52 @@ struct at32_pwm
char *name;
};
static struct at32_pwm at32_pwm_obj[] =
static struct at32_pwm at32_pwm_obj[] =
{
#ifdef BSP_USING_TMR1_CH1
PWM1_CONFIG,
#endif
#ifdef BSP_USING_TMR1_CH2
PWM2_CONFIG,
#endif
#ifdef BSP_USING_TMR1_CH3
PWM3_CONFIG,
#endif
#ifdef BSP_USING_TMR1_CH4
PWM4_CONFIG,
#endif
#ifdef BSP_USING_TMR2_CH1
PWM5_CONFIG,
#endif
#ifdef BSP_USING_TMR2_CH2
PWM6_CONFIG,
#endif
#ifdef BSP_USING_TMR2_CH3
PWM7_CONFIG,
#endif
#ifdef BSP_USING_TMR2_CH4
PWM8_CONFIG,
#endif
#ifdef BSP_USING_TMR3_CH1
PWM9_CONFIG,
#endif
#ifdef BSP_USING_TMR3_CH2
PWM10_CONFIG,
#endif
#ifdef BSP_USING_TMR3_CH3
PWM11_CONFIG,
#endif
#ifdef BSP_USING_TMR3_CH4
PWM12_CONFIG,
#endif
@ -97,7 +97,7 @@ static struct rt_pwm_ops drv_ops =
static rt_err_t drv_pwm_enable(TMR_Type* TMRx, struct rt_pwm_configuration *configuration, rt_bool_t enable)
{
/* Get the value of channel */
rt_uint32_t channel = configuration->channel;
rt_uint32_t channel = configuration->channel;
if (!enable)
{
@ -137,7 +137,7 @@ static rt_err_t drv_pwm_enable(TMR_Type* TMRx, struct rt_pwm_configuration *conf
TMR_CCxCmd(TMRx, TMR_Channel_1, TMR_CCx_Enable);
}
}
/* TMRx enable counter */
TMR_Cmd(TMRx, ENABLE);
@ -173,7 +173,7 @@ static rt_err_t drv_pwm_get(TMR_Type* TMRx, struct rt_pwm_configuration *configu
configuration->pulse = (cc3 + 1) * (div + 1) * 1000UL / tim_clock;
if(channel == 4)
configuration->pulse = (cc4 + 1) * (div + 1) * 1000UL / tim_clock;
return RT_EOK;
}
@ -185,15 +185,15 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu
rt_uint64_t psc;
/* Get the channel number */
rt_uint32_t channel = configuration->channel;
/* Init timer pin and enable clock */
at32_msp_tmr_init(TMRx);
/* Convert nanosecond to frequency and duty cycle. */
period = (unsigned long long)configuration->period ;
psc = period / MAX_PERIOD + 1;
period = period / psc;
/* TMRe base configuration */
TMR_TimeBaseStructInit(&TMR_TMReBaseStructure);
TMR_TMReBaseStructure.TMR_Period = period;
@ -204,14 +204,14 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu
TMR_TimeBaseInit(TMRx, &TMR_TMReBaseStructure);
pulse = (unsigned long long)configuration->pulse;
/* PWM1 Mode configuration: Channel1 */
TMR_OCStructInit(&TMR_OCInitStructure);
TMR_OCInitStructure.TMR_OCMode = TMR_OCMode_PWM1;
TMR_OCInitStructure.TMR_OutputState = TMR_OutputState_Enable;
TMR_OCInitStructure.TMR_Pulse = pulse;
TMR_OCInitStructure.TMR_OCPolarity = TMR_OCPolarity_High;
if(channel == 1)
{
TMR_OC1Init(TMRx, &TMR_OCInitStructure);
@ -232,7 +232,7 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu
TMR_OC4Init(TMRx, &TMR_OCInitStructure);
TMR_OC4PreloadConfig(TMRx, TMR_OCPreload_Enable);
}
TMR_ARPreloadConfig(TMRx, ENABLE);
#if defined (SOC_SERIES_AT32F415)
@ -271,7 +271,7 @@ static int rt_hw_pwm_init(void)
{
int i = 0;
int result = RT_EOK;
for(i = 0; i < sizeof(at32_pwm_obj) / sizeof(at32_pwm_obj[0]); i++)
{
if(rt_device_pwm_register(&at32_pwm_obj[i].pwm_device, at32_pwm_obj[i].name, &drv_ops, at32_pwm_obj[i].tim_handle) == RT_EOK)
@ -280,9 +280,9 @@ static int rt_hw_pwm_init(void)
}
else
{
LOG_D("%s register failed", at32_pwm_obj[i].name);
result = -RT_ERROR;
}
LOG_D("%s register failed", at32_pwm_obj[i].name);
result = -RT_ERROR;
}
}
return result;

16
bsp/at32/Libraries/rt_drivers/drv_pwm.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -28,7 +28,7 @@ extern "C" {
}
#endif /* PWM1_CONFIG */
#endif /* BSP_USING_TMR1_CH1 */
#ifdef BSP_USING_TMR1_CH2
#ifndef PWM2_CONFIG
#define PWM2_CONFIG \
@ -72,7 +72,7 @@ extern "C" {
}
#endif /* PWM5_CONFIG */
#endif /* BSP_USING_TMR2_CH1 */
#ifdef BSP_USING_TMR2_CH2
#ifndef PWM6_CONFIG
#define PWM6_CONFIG \
@ -82,8 +82,8 @@ extern "C" {
.channel = 2 \
}
#endif /* PWM6_CONFIG */
#endif /* BSP_USING_TMR2_CH2 */
#endif /* BSP_USING_TMR2_CH2 */
#ifdef BSP_USING_TMR2_CH3
#ifndef PWM7_CONFIG
#define PWM7_CONFIG \
@ -93,7 +93,7 @@ extern "C" {
.channel = 3 \
}
#endif /* PWM7_CONFIG */
#endif /* BSP_USING_TMR2_CH3 */
#endif /* BSP_USING_TMR2_CH3 */
#ifdef BSP_USING_TMR2_CH4
#ifndef PWM8_CONFIG
@ -115,7 +115,7 @@ extern "C" {
.channel = 1 \
}
#endif /* PWM9_CONFIG */
#endif /* BSP_USING_TMR3_CH1 */
#endif /* BSP_USING_TMR3_CH1 */
#ifdef BSP_USING_TMR3_CH2
#ifndef PWM10_CONFIG
@ -149,7 +149,7 @@ extern "C" {
}
#endif /* PWM12_CONFIG */
#endif /* BSP_USING_TMR3_CH4 */
#ifdef __cplusplus
}
#endif

14
bsp/at32/Libraries/rt_drivers/drv_rtc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -79,10 +79,10 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
return -RT_ERROR;
}
#else
/* Set the RTC counter value */
RTC_SetCounter(time_stamp);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
/* Set the RTC counter value */
RTC_SetCounter(time_stamp);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
#endif /* SOC_SERIES_AT32F415 */
LOG_D("set rtc time.");
#ifdef SOC_SERIES_AT32F415
@ -117,7 +117,7 @@ static rt_err_t rt_rtc_config(struct rt_device *dev)
ERTC_InitType ERTC_InitStructure;
#endif
/* Allow access to BKP Domain */
PWR_BackupAccessCtrl(ENABLE);
PWR_BackupAccessCtrl(ENABLE);
#ifdef SOC_SERIES_AT32F415
#ifdef BSP_RTC_USING_LSI
@ -148,7 +148,7 @@ static rt_err_t rt_rtc_config(struct rt_device *dev)
#else
if (BKP_ReadBackupReg(BKP_DT1) != BKUP_REG_DATA)
#endif
{
{
LOG_I("RTC hasn't been configured, please use <date> command to config.");
#ifdef SOC_SERIES_AT32F415
/* Configure the ERTC data register and ERTC prescaler */

2
bsp/at32/Libraries/rt_drivers/drv_sdio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_sdio.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

8
bsp/at32/Libraries/rt_drivers/drv_soft_i2c.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -205,10 +205,10 @@ int rt_hw_i2c_init(void)
result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name);
RT_ASSERT(result == RT_EOK);
at32_i2c_bus_unlock(&soft_i2c_config[i]);
LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
soft_i2c_config[i].bus_name,
soft_i2c_config[i].scl,
soft_i2c_config[i].bus_name,
soft_i2c_config[i].scl,
soft_i2c_config[i].sda);
}

8
bsp/at32/Libraries/rt_drivers/drv_soft_i2c.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -37,7 +37,7 @@ struct at32_i2c
.bus_name = "i2c1", \
}
#endif
#ifdef BSP_USING_I2C2
#define i2c_bus_CONFIG \
{ \
@ -46,7 +46,7 @@ struct at32_i2c
.bus_name = "i2c2", \
}
#endif
#ifdef BSP_USING_I2C3
#define I2C3_BUS_CONFIG \
{ \
@ -55,7 +55,7 @@ struct at32_i2c
.bus_name = "i2c3", \
}
#endif
#ifdef BSP_USING_I2C4
#define I2C4_BUS_CONFIG \
{ \

40
bsp/at32/Libraries/rt_drivers/drv_spi.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -7,7 +7,7 @@
* Date Author Notes
* 2020-01-09 shelton first version
*/
#include <board.h>
#include "drv_spi.h"
@ -24,7 +24,7 @@
#ifdef DEBUG
#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
#else
#define DEBUG_PRINTF(...)
#define DEBUG_PRINTF(...)
#endif
/* private rt-thread spi ops function */
@ -81,13 +81,13 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
static rt_err_t configure(struct rt_spi_device* device,
struct rt_spi_configuration* configuration)
{
struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;
struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;
struct at32_spi *spi_instance = (struct at32_spi *)spi_bus->parent.user_data;
SPI_InitType SPI_InitStruct;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
at32_msp_spi_init(spi_instance->config->spix);
@ -162,7 +162,7 @@ static rt_err_t configure(struct rt_spi_device* device,
SPI_InitStruct.SPI_MCLKP = SPI_MCLKP_256;
}
} /* baudrate */
switch(configuration->mode & RT_SPI_MODE_3)
{
case RT_SPI_MODE_0:
@ -172,11 +172,11 @@ static rt_err_t configure(struct rt_spi_device* device,
case RT_SPI_MODE_1:
SPI_InitStruct.SPI_CPHA = SPI_CPHA_2EDGE;
SPI_InitStruct.SPI_CPOL = SPI_CPOL_LOW;
break;
break;
case RT_SPI_MODE_2:
SPI_InitStruct.SPI_CPHA = SPI_CPHA_1EDGE;
SPI_InitStruct.SPI_CPOL = SPI_CPOL_HIGH;
break;
break;
case RT_SPI_MODE_3:
SPI_InitStruct.SPI_CPHA = SPI_CPHA_2EDGE;
SPI_InitStruct.SPI_CPOL = SPI_CPOL_HIGH;
@ -200,7 +200,7 @@ static rt_err_t configure(struct rt_spi_device* device,
/* init SPI */
SPI_Init(spi_instance->config->spix, &SPI_InitStruct);
/* Enable SPI_MASTER */
SPI_Enable(spi_instance->config->spix, ENABLE);
SPI_Enable(spi_instance->config->spix, ENABLE);
SPI_CRCEN(spi_instance->config->spix, DISABLE);
return RT_EOK;
@ -213,9 +213,9 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
struct rt_spi_configuration * config = &device->config;
struct at32_spi_cs * at32_spi_cs = device->parent.user_data;
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
/* take CS */
if(message->cs_take)
{
@ -229,7 +229,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
const rt_uint8_t * send_ptr = message->send_buf;
rt_uint8_t * recv_ptr = message->recv_buf;
rt_uint32_t size = message->length;
DEBUG_PRINTF("spi poll transfer start: %d\n", size);
while(size--)
@ -240,12 +240,12 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
{
data = *send_ptr++;
}
// Todo: replace register read/write by at32 lib
//Wait until the transmit buffer is empty
while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_TE));
// Send the byte
SPI_I2S_TxData(spi_instance->config->spix, data);
SPI_I2S_TxData(spi_instance->config->spix, data);
//Wait until a data is received
while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_RNE));
@ -277,7 +277,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
//Wait until the transmit buffer is empty
while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_TE));
// Send the byte
SPI_I2S_TxData(spi_instance->config->spix, data);
SPI_I2S_TxData(spi_instance->config->spix, data);
//Wait until a data is received
while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_RNE));
@ -295,7 +295,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
/* release CS */
if(message->cs_release)
{
GPIO_SetBits(at32_spi_cs->GPIOx, at32_spi_cs->GPIO_Pin);
GPIO_SetBits(at32_spi_cs->GPIOx, at32_spi_cs->GPIO_Pin);
DEBUG_PRINTF("spi release cs\n");
}
@ -306,7 +306,7 @@ static struct at32_spi_config configs[] = {
#ifdef BSP_USING_SPI1
{SPI1, "spi1"},
#endif
#ifdef BSP_USING_SPI2
{SPI2, "spi2"},
#endif

2
bsp/at32/Libraries/rt_drivers/drv_spi.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

42
bsp/at32/Libraries/rt_drivers/drv_sram.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -38,7 +38,7 @@ static int rt_hw_sram_Init(void)
/* Init XMC pin */
at32_msp_xmc_init(XMC);
/*-- FSMC Configuration ------------------------------------------------------*/
p.XMC_AdrOpTime = 0x04;
p.XMC_AdrHoldTime = 0x04;
@ -53,7 +53,7 @@ static int rt_hw_sram_Init(void)
XMC_NORSRAMInitStructure.XMC_Dev = XMC_Dev_SRAM;
XMC_NORSRAMInitStructure.XMC_BusType = XMC_BusType_16b;
XMC_NORSRAMInitStructure.XMC_EnableBurstMode = XMC_BurstMode_Disable;
XMC_NORSRAMInitStructure.XMC_EnableAsynWait = XMC_AsynWait_Disable;
XMC_NORSRAMInitStructure.XMC_EnableAsynWait = XMC_AsynWait_Disable;
XMC_NORSRAMInitStructure.XMC_WaitSignalLv = XMC_WaitSignalLv_Low;
XMC_NORSRAMInitStructure.XMC_EnableBurstModeSplit = XMC_BurstModeSplit_Disable;
XMC_NORSRAMInitStructure.XMC_WaitSignalConfig = XMC_WaitSignalConfig_BeforeWaitState;
@ -63,9 +63,9 @@ static int rt_hw_sram_Init(void)
XMC_NORSRAMInitStructure.XMC_WriteBurstSyn = XMC_WriteBurstSyn_Disable;
XMC_NORSRAMInitStructure.XMC_RWTimingStruct = &p;
XMC_NORSRAMInitStructure.XMC_WTimingStruct = &p;
XMC_NORSRAMInit(&XMC_NORSRAMInitStructure);
XMC_NORSRAMInit(&XMC_NORSRAMInitStructure);
/*!< Enable FSMC Bank1_SRAM Bank */
XMC_NORSRAMCmd(XMC_Bank1_NORSRAM3, ENABLE);
@ -73,7 +73,7 @@ static int rt_hw_sram_Init(void)
/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
rt_memheap_init(&system_heap, "sram", (void *)EXT_SRAM_BEGIN, SRAM_LENGTH);
#endif
return result;
}
INIT_BOARD_EXPORT(rt_hw_sram_Init);
@ -81,11 +81,11 @@ INIT_BOARD_EXPORT(rt_hw_sram_Init);
#ifdef DRV_DEBUG
#ifdef FINSH_USING_MSH
/**
* @brief Writes a Half-word buffer to the FSMC SRAM memory.
* @param pBuffer : pointer to buffer.
* @param WriteAddr : SRAM memory internal address from which the data will be
* @brief Writes a Half-word buffer to the FSMC SRAM memory.
* @param pBuffer : pointer to buffer.
* @param WriteAddr : SRAM memory internal address from which the data will be
* written.
* @param NumHalfwordToWrite : number of half-words to write.
* @param NumHalfwordToWrite : number of half-words to write.
* @retval None
*/
static void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite)
@ -94,15 +94,15 @@ static void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t Num
{
/*!< Transfer data to the memory */
*(uint16_t *) (EXT_SRAM_BEGIN + WriteAddr) = *pBuffer++;
/*!< Increment the address*/
/*!< Increment the address*/
WriteAddr += 2;
}
}
}
/**
* @brief Reads a block of data from the FSMC SRAM memory.
* @param pBuffer : pointer to the buffer that receives the data read from the
* @param pBuffer : pointer to the buffer that receives the data read from the
* SRAM memory.
* @param ReadAddr : SRAM memory internal address to read from.
* @param NumHalfwordToRead : number of half-words to read.
@ -115,9 +115,9 @@ static void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHa
/*!< Read a half-word from the memory */
*pBuffer++ = *(__IO uint16_t*) (EXT_SRAM_BEGIN + ReadAddr);
/*!< Increment the address*/
/*!< Increment the address*/
ReadAddr += 2;
}
}
}
/**
@ -146,9 +146,9 @@ int sram_test(void)
/* Read data from XMC SRAM memory */
SRAM_ReadBuffer(RT_RxBuffer, RT_WRITE_READ_ADDR, RT_BUFFER_SIZE);
SRAM_ReadBuffer(RT_RxBuffer, RT_WRITE_READ_ADDR, RT_BUFFER_SIZE);
/* Read back SRAM memory and check content correctness */
/* Read back SRAM memory and check content correctness */
for (Index = 0x00; (Index < RT_BUFFER_SIZE) && (WriteReadStatus == 0); Index++)
{
if (RT_RxBuffer[Index] != RT_TxBuffer[Index])
@ -156,7 +156,7 @@ int sram_test(void)
WriteReadStatus = Index + 1;
}
}
if(WriteReadStatus == 0)
{
LOG_D("SRAM test success!");
@ -165,7 +165,7 @@ int sram_test(void)
{
LOG_E("SRAM test failed!");
}
return RT_EOK;
}
MSH_CMD_EXPORT(sram_test, sram test)

2
bsp/at32/Libraries/rt_drivers/drv_sram.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/at32/Libraries/rt_drivers/drv_usart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -15,7 +15,7 @@
#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \
!defined(BSP_USING_UART3)
#error "Please define at least one BSP_USING_UARTx"
/* this driver can be disabled at menuconfig ¡ú RT-Thread Components ¡ú Device Drivers */
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
#endif
struct at32_usart {

2
bsp/at32/Libraries/rt_drivers/drv_usart.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/Libraries/rt_drivers/drv_wdt.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/at32/at32f403a-start/applications/main.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/at32/at32f403a-start/board/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -7,7 +7,7 @@
* Date Author Notes
* 2018-11-06 balanceTWK first version
*/
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>

2
bsp/at32/at32f403a-start/board/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

20
bsp/at32/at32f403a-start/board/msp/at32_msp.c
View File

@ -195,34 +195,34 @@ void at32_msp_adc_init(void *Instance)
GPIO_InitType GPIO_InitStruct;
ADC_Type *ADCx = (ADC_Type *)Instance;
#ifdef BSP_USING_ADC1
#ifdef BSP_USING_ADC1
if(ADCx == ADC1)
{
{
/* ADC1 & GPIO clock enable */
RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC1 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE);
/* Configure ADC Channel as analog input */
/* Configure ADC Channel as analog input */
GPIO_StructInit(&GPIO_InitStruct);
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG;
GPIO_Init(GPIOC, &GPIO_InitStruct);
}
#endif
#ifdef BSP_USING_ADC2
#ifdef BSP_USING_ADC2
if(ADCx == ADC2)
{
/* ADC2 & GPIO clock enable */
RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC2 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE);
/* Configure ADC Channel as analog input */
/* Configure ADC Channel as analog input */
GPIO_StructInit(&GPIO_InitStruct);
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG;
GPIO_Init(GPIOC, &GPIO_InitStruct);
}
#endif
#endif
}
#endif /* BSP_USING_ADC */
@ -237,7 +237,7 @@ void at32_msp_hwtmr_init(void *Instance)
/* TMR3 clock enable */
RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_TMR3, ENABLE);
}
#endif
#endif
#ifdef BSP_USING_HWTMR4
if(TMRx == TMR4)

120
bsp/at32/at32f403a-start/board/msp/system_at32f4xx.c
View File

@ -17,7 +17,7 @@
*
* <h2><center>&copy; COPYRIGHT 2018 ArteryTek</center></h2>
******************************************************************************
*/
*/
/** @addtogroup CMSIS
* @{
@ -68,23 +68,23 @@
Clock (MHz)
PLL from HSE or HSI
SYSCLK HCLK PCLK2 PCLK1
24 24 24 24
36 36 36 36
48 48 48 24
56 56 56 28
72 72 72 36
96 96 48 48
108 108 54 54
120 120 60 60
144 144 72 72
150 150 75 75
168 168 84 84
176 176 88 88
192 192 96 96
200 200 100 100
224 224 112 112
240 240 120 120
SYSCLK HCLK PCLK2 PCLK1
24 24 24 24
36 36 36 36
48 48 48 24
56 56 56 28
72 72 72 36
96 96 48 48
108 108 54 54
120 120 60 60
144 144 72 72
150 150 75 75
168 168 84 84
176 176 88 88
192 192 96 96
200 200 100 100
224 224 112 112
240 240 120 120
*/
#if defined (AT32F403xx) || defined (AT32F413xx) || \
@ -143,7 +143,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
@ -573,7 +573,7 @@ static void SetSysClock(void)
/**
* @brief Setup the external memory controller.
* Called in startup_at32f4xx_xx.s/.c before jump to main.
* This function configures the external SRAM mounted
* This function configures the external SRAM mounted
* (AT32 High density devices). This SRAM will be used as program
* data memory (including heap and stack).
* @param None
@ -654,7 +654,7 @@ static void SetSysClockToHSE(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -674,7 +674,7 @@ static void SetSysClockToHSE(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -725,7 +725,7 @@ static void SetSysClockTo24M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -745,7 +745,7 @@ static void SetSysClockTo24M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -811,7 +811,7 @@ static void SetSysClockTo36M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -831,7 +831,7 @@ static void SetSysClockTo36M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -897,7 +897,7 @@ static void SetSysClockTo48M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -917,7 +917,7 @@ static void SetSysClockTo48M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -984,7 +984,7 @@ static void SetSysClockTo56M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1004,7 +1004,7 @@ static void SetSysClockTo56M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1071,7 +1071,7 @@ static void SetSysClockTo72M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1091,7 +1091,7 @@ static void SetSysClockTo72M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1158,7 +1158,7 @@ static void SetSysClockTo96M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1178,7 +1178,7 @@ static void SetSysClockTo96M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1249,7 +1249,7 @@ static void SetSysClockTo108M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1269,7 +1269,7 @@ static void SetSysClockTo108M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1341,7 +1341,7 @@ static void SetSysClockTo120M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1361,7 +1361,7 @@ static void SetSysClockTo120M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1440,7 +1440,7 @@ static void SetSysClockTo144M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1460,7 +1460,7 @@ static void SetSysClockTo144M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1475,7 +1475,7 @@ static void SetSysClockTo144M(void)
/* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
RCC->CFG &= RCC_CFG_PLLCFG_MASK;
#if defined (AT32F415xx)
RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18);
#else
@ -1539,7 +1539,7 @@ static void SetSysClockTo150M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1559,7 +1559,7 @@ static void SetSysClockTo150M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1634,7 +1634,7 @@ static void SetSysClockTo168M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1720,7 +1720,7 @@ static void SetSysClockTo176M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1806,7 +1806,7 @@ static void SetSysClockTo192M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1892,7 +1892,7 @@ static void SetSysClockTo200M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1978,7 +1978,7 @@ static void SetSysClockTo224M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -2064,7 +2064,7 @@ static void SetSysClockTo240M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -2168,7 +2168,7 @@ static void SetSysClockTo24MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2248,7 +2248,7 @@ static void SetSysClockTo36MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2328,7 +2328,7 @@ static void SetSysClockTo48MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2408,7 +2408,7 @@ static void SetSysClockTo56MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2488,7 +2488,7 @@ static void SetSysClockTo72MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2568,7 +2568,7 @@ static void SetSysClockTo96MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2653,7 +2653,7 @@ static void SetSysClockTo108MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2738,7 +2738,7 @@ static void SetSysClockTo120MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2830,7 +2830,7 @@ static void SetSysClockTo144MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2922,7 +2922,7 @@ static void SetSysClockTo150MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -3454,4 +3454,4 @@ static void SetSysClockTo240MHSI(void)
* @}
*/
/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/
/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/

2
bsp/at32/at32f407-start/applications/main.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/at32/at32f407-start/board/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -7,7 +7,7 @@
* Date Author Notes
* 2018-11-06 balanceTWK first version
*/
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>

2
bsp/at32/at32f407-start/board/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

20
bsp/at32/at32f407-start/board/msp/at32_msp.c
View File

@ -195,34 +195,34 @@ void at32_msp_adc_init(void *Instance)
GPIO_InitType GPIO_InitStruct;
ADC_Type *ADCx = (ADC_Type *)Instance;
#ifdef BSP_USING_ADC1
#ifdef BSP_USING_ADC1
if(ADCx == ADC1)
{
{
/* ADC1 & GPIO clock enable */
RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC1 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE);
/* Configure ADC Channel as analog input */
/* Configure ADC Channel as analog input */
GPIO_StructInit(&GPIO_InitStruct);
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG;
GPIO_Init(GPIOC, &GPIO_InitStruct);
}
#endif
#ifdef BSP_USING_ADC2
#ifdef BSP_USING_ADC2
if(ADCx == ADC2)
{
/* ADC2 & GPIO clock enable */
RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC2 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE);
/* Configure ADC Channel as analog input */
/* Configure ADC Channel as analog input */
GPIO_StructInit(&GPIO_InitStruct);
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG;
GPIO_Init(GPIOC, &GPIO_InitStruct);
}
#endif
#endif
}
#endif /* BSP_USING_ADC */
@ -237,7 +237,7 @@ void at32_msp_hwtmr_init(void *Instance)
/* TMR3 clock enable */
RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_TMR3, ENABLE);
}
#endif
#endif
#ifdef BSP_USING_HWTMR4
if(TMRx == TMR4)

120
bsp/at32/at32f407-start/board/msp/system_at32f4xx.c
View File

@ -17,7 +17,7 @@
*
* <h2><center>&copy; COPYRIGHT 2018 ArteryTek</center></h2>
******************************************************************************
*/
*/
/** @addtogroup CMSIS
* @{
@ -68,23 +68,23 @@
Clock (MHz)
PLL from HSE or HSI
SYSCLK HCLK PCLK2 PCLK1
24 24 24 24
36 36 36 36
48 48 48 24
56 56 56 28
72 72 72 36
96 96 48 48
108 108 54 54
120 120 60 60
144 144 72 72
150 150 75 75
168 168 84 84
176 176 88 88
192 192 96 96
200 200 100 100
224 224 112 112
240 240 120 120
SYSCLK HCLK PCLK2 PCLK1
24 24 24 24
36 36 36 36
48 48 48 24
56 56 56 28
72 72 72 36
96 96 48 48
108 108 54 54
120 120 60 60
144 144 72 72
150 150 75 75
168 168 84 84
176 176 88 88
192 192 96 96
200 200 100 100
224 224 112 112
240 240 120 120
*/
#if defined (AT32F403xx) || defined (AT32F413xx) || \
@ -143,7 +143,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
@ -573,7 +573,7 @@ static void SetSysClock(void)
/**
* @brief Setup the external memory controller.
* Called in startup_at32f4xx_xx.s/.c before jump to main.
* This function configures the external SRAM mounted
* This function configures the external SRAM mounted
* (AT32 High density devices). This SRAM will be used as program
* data memory (including heap and stack).
* @param None
@ -654,7 +654,7 @@ static void SetSysClockToHSE(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -674,7 +674,7 @@ static void SetSysClockToHSE(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -725,7 +725,7 @@ static void SetSysClockTo24M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -745,7 +745,7 @@ static void SetSysClockTo24M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -811,7 +811,7 @@ static void SetSysClockTo36M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -831,7 +831,7 @@ static void SetSysClockTo36M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -897,7 +897,7 @@ static void SetSysClockTo48M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -917,7 +917,7 @@ static void SetSysClockTo48M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -984,7 +984,7 @@ static void SetSysClockTo56M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1004,7 +1004,7 @@ static void SetSysClockTo56M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1071,7 +1071,7 @@ static void SetSysClockTo72M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1091,7 +1091,7 @@ static void SetSysClockTo72M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1158,7 +1158,7 @@ static void SetSysClockTo96M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1178,7 +1178,7 @@ static void SetSysClockTo96M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1249,7 +1249,7 @@ static void SetSysClockTo108M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1269,7 +1269,7 @@ static void SetSysClockTo108M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1341,7 +1341,7 @@ static void SetSysClockTo120M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1361,7 +1361,7 @@ static void SetSysClockTo120M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1440,7 +1440,7 @@ static void SetSysClockTo144M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1460,7 +1460,7 @@ static void SetSysClockTo144M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1475,7 +1475,7 @@ static void SetSysClockTo144M(void)
/* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
RCC->CFG &= RCC_CFG_PLLCFG_MASK;
#if defined (AT32F415xx)
RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18);
#else
@ -1539,7 +1539,7 @@ static void SetSysClockTo150M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1559,7 +1559,7 @@ static void SetSysClockTo150M(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -1634,7 +1634,7 @@ static void SetSysClockTo168M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1720,7 +1720,7 @@ static void SetSysClockTo176M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1806,7 +1806,7 @@ static void SetSysClockTo192M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1892,7 +1892,7 @@ static void SetSysClockTo200M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -1978,7 +1978,7 @@ static void SetSysClockTo224M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -2064,7 +2064,7 @@ static void SetSysClockTo240M(void)
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
#ifdef AT32F403xx
#ifdef AT32F403xx
WaitHseStbl(HSE_STABLE_DELAY);
#endif
if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
@ -2168,7 +2168,7 @@ static void SetSysClockTo24MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2248,7 +2248,7 @@ static void SetSysClockTo36MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2328,7 +2328,7 @@ static void SetSysClockTo48MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2408,7 +2408,7 @@ static void SetSysClockTo56MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2488,7 +2488,7 @@ static void SetSysClockTo72MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2568,7 +2568,7 @@ static void SetSysClockTo96MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2653,7 +2653,7 @@ static void SetSysClockTo108MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2738,7 +2738,7 @@ static void SetSysClockTo120MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2830,7 +2830,7 @@ static void SetSysClockTo144MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -2922,7 +2922,7 @@ static void SetSysClockTo150MHSI(void)
/* Flash 1 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
#endif
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
@ -3454,4 +3454,4 @@ static void SetSysClockTo240MHSI(void)
* @}
*/
/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/
/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/