feat : format code

1. ref https://github.com/mysterywolf/formatting

bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/n32g45x.h

@@ -1140,10 +1140,10 @@ typedef struct
     __IO uint32_t DAT29;
     __IO uint32_t DAT30;
     __IO uint32_t DAT31;
-    __IO uint32_t RESERVED2;	/*DAT32-DAT35 is reserved*/
-    __IO uint32_t RESERVED3;	/*DAT32-DAT35 is reserved*/
-    __IO uint32_t RESERVED4;	/*DAT32-DAT35 is reserved*/
-    __IO uint32_t RESERVED5;	/*DAT32-DAT35 is reserved*/
+    __IO uint32_t RESERVED2;    /*DAT32-DAT35 is reserved*/
+    __IO uint32_t RESERVED3;    /*DAT32-DAT35 is reserved*/
+    __IO uint32_t RESERVED4;    /*DAT32-DAT35 is reserved*/
+    __IO uint32_t RESERVED5;    /*DAT32-DAT35 is reserved*/
     __IO uint32_t RS_DELAY;
     __IO uint32_t ENH_CTRL0;
     __IO uint32_t DDR_TXDE;
@@ -7671,13 +7671,13 @@ typedef struct
 #define USART_CTRL1_UEN      ((uint16_t)0x2000) /*!< USART Enable */
 
 /******************  Bit definition for USART_CTRL2 register  *******************/
-#define USART_CTRL2_ADDR    	((uint16_t)0x000F) /*!< Address of the USART node */
-#define USART_CTRL2_LINBDL  	((uint16_t)0x0020) /*!< LIN Break Detection Length */
-#define USART_CTRL2_LINBDIEN	((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
-#define USART_CTRL2_LBCLK   	((uint16_t)0x0100) /*!< Last Bit Clock pulse */
-#define USART_CTRL2_CLKPHA  	((uint16_t)0x0200) /*!< Clock Phase */
-#define USART_CTRL2_CLKPOL  	((uint16_t)0x0400) /*!< Clock Polarity */
-#define USART_CTRL2_CLKEN   	((uint16_t)0x0800) /*!< Clock Enable */
+#define USART_CTRL2_ADDR        ((uint16_t)0x000F) /*!< Address of the USART node */
+#define USART_CTRL2_LINBDL      ((uint16_t)0x0020) /*!< LIN Break Detection Length */
+#define USART_CTRL2_LINBDIEN    ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CTRL2_LBCLK       ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
+#define USART_CTRL2_CLKPHA      ((uint16_t)0x0200) /*!< Clock Phase */
+#define USART_CTRL2_CLKPOL      ((uint16_t)0x0400) /*!< Clock Polarity */
+#define USART_CTRL2_CLKEN       ((uint16_t)0x0800) /*!< Clock Enable */
 
 #define USART_CTRL2_STPB   ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
 #define USART_CTRL2_STPB_0 ((uint16_t)0x1000) /*!< Bit 0 */
@@ -8335,7 +8335,7 @@ typedef struct
 
 /******************************************************************************/
 /*                                                                            */
-/*                                 QSPI Registers           	              */
+/*                                 QSPI Registers                             */
 /*                                                                            */
 /******************************************************************************/
 
@@ -8346,58 +8346,58 @@ typedef struct
 #define QSPI_CTRL0_DFS_2                            ((uint32_t)0x00000004) /*!< Bit 2 */
 #define QSPI_CTRL0_DFS_3                            ((uint32_t)0x00000008) /*!< Bit 3 */
 #define QSPI_CTRL0_DFS_4                            ((uint32_t)0x00000010) /*!< Bit 4 */
-#define QSPI_CTRL0_DFS_4_BIT               					((uint32_t)0x00000003)
-#define QSPI_CTRL0_DFS_5_BIT               					((uint32_t)0x00000004)
-#define QSPI_CTRL0_DFS_6_BIT               					((uint32_t)0x00000005)
-#define QSPI_CTRL0_DFS_7_BIT               					((uint32_t)0x00000006)
-#define QSPI_CTRL0_DFS_8_BIT               					((uint32_t)0x00000007)
-#define QSPI_CTRL0_DFS_9_BIT               					((uint32_t)0x00000008)
-#define QSPI_CTRL0_DFS_10_BIT              					((uint32_t)0x00000009)
-#define QSPI_CTRL0_DFS_11_BIT              					((uint32_t)0x0000000A)
-#define QSPI_CTRL0_DFS_12_BIT              					((uint32_t)0x0000000B)
-#define QSPI_CTRL0_DFS_13_BIT              					((uint32_t)0x0000000C)
-#define QSPI_CTRL0_DFS_14_BIT              					((uint32_t)0x0000000D)
-#define QSPI_CTRL0_DFS_15_BIT              					((uint32_t)0x0000000E)
-#define QSPI_CTRL0_DFS_16_BIT              					((uint32_t)0x0000000F)
-#define QSPI_CTRL0_DFS_17_BIT              					((uint32_t)0x00000010)
-#define QSPI_CTRL0_DFS_18_BIT              					((uint32_t)0x00000011)
-#define QSPI_CTRL0_DFS_19_BIT              					((uint32_t)0x00000012)
-#define QSPI_CTRL0_DFS_20_BIT              					((uint32_t)0x00000013)
-#define QSPI_CTRL0_DFS_21_BIT              					((uint32_t)0x00000014)
-#define QSPI_CTRL0_DFS_22_BIT              					((uint32_t)0x00000015)
-#define QSPI_CTRL0_DFS_23_BIT              					((uint32_t)0x00000016)
-#define QSPI_CTRL0_DFS_24_BIT              					((uint32_t)0x00000017)
-#define QSPI_CTRL0_DFS_25_BIT              					((uint32_t)0x00000018)
-#define QSPI_CTRL0_DFS_26_BIT              					((uint32_t)0x00000019)
-#define QSPI_CTRL0_DFS_27_BIT              					((uint32_t)0x0000001A)
-#define QSPI_CTRL0_DFS_28_BIT              					((uint32_t)0x0000001B)
-#define QSPI_CTRL0_DFS_29_BIT              					((uint32_t)0x0000001C)
-#define QSPI_CTRL0_DFS_30_BIT              					((uint32_t)0x0000001D)
-#define QSPI_CTRL0_DFS_31_BIT              					((uint32_t)0x0000001E)
-#define QSPI_CTRL0_DFS_32_BIT              					((uint32_t)0x0000001F)
+#define QSPI_CTRL0_DFS_4_BIT                                ((uint32_t)0x00000003)
+#define QSPI_CTRL0_DFS_5_BIT                                ((uint32_t)0x00000004)
+#define QSPI_CTRL0_DFS_6_BIT                                ((uint32_t)0x00000005)
+#define QSPI_CTRL0_DFS_7_BIT                                ((uint32_t)0x00000006)
+#define QSPI_CTRL0_DFS_8_BIT                                ((uint32_t)0x00000007)
+#define QSPI_CTRL0_DFS_9_BIT                                ((uint32_t)0x00000008)
+#define QSPI_CTRL0_DFS_10_BIT                               ((uint32_t)0x00000009)
+#define QSPI_CTRL0_DFS_11_BIT                               ((uint32_t)0x0000000A)
+#define QSPI_CTRL0_DFS_12_BIT                               ((uint32_t)0x0000000B)
+#define QSPI_CTRL0_DFS_13_BIT                               ((uint32_t)0x0000000C)
+#define QSPI_CTRL0_DFS_14_BIT                               ((uint32_t)0x0000000D)
+#define QSPI_CTRL0_DFS_15_BIT                               ((uint32_t)0x0000000E)
+#define QSPI_CTRL0_DFS_16_BIT                               ((uint32_t)0x0000000F)
+#define QSPI_CTRL0_DFS_17_BIT                               ((uint32_t)0x00000010)
+#define QSPI_CTRL0_DFS_18_BIT                               ((uint32_t)0x00000011)
+#define QSPI_CTRL0_DFS_19_BIT                               ((uint32_t)0x00000012)
+#define QSPI_CTRL0_DFS_20_BIT                               ((uint32_t)0x00000013)
+#define QSPI_CTRL0_DFS_21_BIT                               ((uint32_t)0x00000014)
+#define QSPI_CTRL0_DFS_22_BIT                               ((uint32_t)0x00000015)
+#define QSPI_CTRL0_DFS_23_BIT                               ((uint32_t)0x00000016)
+#define QSPI_CTRL0_DFS_24_BIT                               ((uint32_t)0x00000017)
+#define QSPI_CTRL0_DFS_25_BIT                               ((uint32_t)0x00000018)
+#define QSPI_CTRL0_DFS_26_BIT                               ((uint32_t)0x00000019)
+#define QSPI_CTRL0_DFS_27_BIT                               ((uint32_t)0x0000001A)
+#define QSPI_CTRL0_DFS_28_BIT                               ((uint32_t)0x0000001B)
+#define QSPI_CTRL0_DFS_29_BIT                               ((uint32_t)0x0000001C)
+#define QSPI_CTRL0_DFS_30_BIT                               ((uint32_t)0x0000001D)
+#define QSPI_CTRL0_DFS_31_BIT                               ((uint32_t)0x0000001E)
+#define QSPI_CTRL0_DFS_32_BIT                               ((uint32_t)0x0000001F)
 
 #define QSPI_CTRL0_FRF                              ((uint32_t)0x000000C0) /*!< FRF[1:0] bits (Frame Format) */
 #define QSPI_CTRL0_FRF_0                            ((uint32_t)0x00000040) /*!< Bit 0 */
 #define QSPI_CTRL0_FRF_1                            ((uint32_t)0x00000080) /*!< Bit 1 */
-#define QSPI_CTRL0_FRF_MOTOROLA            					((uint32_t)0x00000000)
-#define QSPI_CTRL0_FRF_TI                  					((uint32_t)0x00000040)
-#define QSPI_CTRL0_FRF_MICROWIRE           					((uint32_t)0x00000080)
+#define QSPI_CTRL0_FRF_MOTOROLA                             ((uint32_t)0x00000000)
+#define QSPI_CTRL0_FRF_TI                                   ((uint32_t)0x00000040)
+#define QSPI_CTRL0_FRF_MICROWIRE                            ((uint32_t)0x00000080)
 
 #define QSPI_CTRL0_SCPH                             ((uint32_t)0x00000100) /*!< SCPH (Serial Clock Phase) */
-#define QSPI_CTRL0_SCPH_FIRST_EDGE         					((uint32_t)0x00000000)
-#define QSPI_CTRL0_SCPH_SECOND_EDGE        					((uint32_t)0x00000100)
+#define QSPI_CTRL0_SCPH_FIRST_EDGE                          ((uint32_t)0x00000000)
+#define QSPI_CTRL0_SCPH_SECOND_EDGE                         ((uint32_t)0x00000100)
 
 #define QSPI_CTRL0_SCPOL                            ((uint32_t)0x00000200) /*!< SCPOL(Serial Clock Polarity) */
-#define QSPI_CTRL0_SCPOL_LOW               					((uint32_t)0x00000000)
-#define QSPI_CTRL0_SCPOL_HIGH              					((uint32_t)0x00000200)
+#define QSPI_CTRL0_SCPOL_LOW                                ((uint32_t)0x00000000)
+#define QSPI_CTRL0_SCPOL_HIGH                               ((uint32_t)0x00000200)
 
 #define QSPI_CTRL0_TMOD                             ((uint32_t)0x00000C00) /*!< TMOD[1:0] bits (Transfer Mode) */
 #define QSPI_CTRL0_TMOD_0                           ((uint32_t)0x00000400) /*!< Bit 0 */
 #define QSPI_CTRL0_TMOD_1                           ((uint32_t)0x00000800) /*!< Bit 1 */
-#define QSPI_CTRL0_TMOD_TX_AND_RX          					((uint32_t)0x00000000)
-#define QSPI_CTRL0_TMOD_TX_ONLY            					((uint32_t)0x00000400)
-#define QSPI_CTRL0_TMOD_RX_ONLY            					((uint32_t)0x00000800)
-#define QSPI_CTRL0_TMOD_EEPROM_READ        					((uint32_t)0x00000C00)
+#define QSPI_CTRL0_TMOD_TX_AND_RX                           ((uint32_t)0x00000000)
+#define QSPI_CTRL0_TMOD_TX_ONLY                             ((uint32_t)0x00000400)
+#define QSPI_CTRL0_TMOD_RX_ONLY                             ((uint32_t)0x00000800)
+#define QSPI_CTRL0_TMOD_EEPROM_READ                         ((uint32_t)0x00000C00)
 
 #define QSPI_CTRL0_SRL_EN                           ((uint32_t)0x00002000) /*!< SRL (Shift Register Loop) */
 #define QSPI_CTRL0_SSTE_EN                          ((uint32_t)0x00004000) /*!< SSTE(Slave Select Toggle Enable) */
@@ -8407,29 +8407,29 @@ typedef struct
 #define QSPI_CTRL0_CFS_1                            ((uint32_t)0x00020000) /*!< Bit 1 */
 #define QSPI_CTRL0_CFS_2                            ((uint32_t)0x00040000) /*!< Bit 2 */
 #define QSPI_CTRL0_CFS_3                            ((uint32_t)0x00080000) /*!< Bit 3 */
-#define QSPI_CTRL0_CFS_1_BIT          	   					((uint32_t)0x00000000)
-#define QSPI_CTRL0_CFS_2_BIT          	   					((uint32_t)0x00010000)
-#define QSPI_CTRL0_CFS_3_BIT          	   					((uint32_t)0x00020000)
-#define QSPI_CTRL0_CFS_4_BIT          	   					((uint32_t)0x00030000)
-#define QSPI_CTRL0_CFS_5_BIT          	   					((uint32_t)0x00040000)
-#define QSPI_CTRL0_CFS_6_BIT          	   					((uint32_t)0x00050000)
-#define QSPI_CTRL0_CFS_7_BIT          	   					((uint32_t)0x00060000)
-#define QSPI_CTRL0_CFS_8_BIT          	   					((uint32_t)0x00070000)
-#define QSPI_CTRL0_CFS_9_BIT          	   					((uint32_t)0x00080000)
-#define QSPI_CTRL0_CFS_10_BIT         	   					((uint32_t)0x00090000)
-#define QSPI_CTRL0_CFS_11_BIT         	   					((uint32_t)0x000A0000)
-#define QSPI_CTRL0_CFS_12_BIT         	   					((uint32_t)0x000B0000)
-#define QSPI_CTRL0_CFS_13_BIT         	   					((uint32_t)0x000C0000)
-#define QSPI_CTRL0_CFS_14_BIT         	   					((uint32_t)0x000D0000)
-#define QSPI_CTRL0_CFS_15_BIT         	   					((uint32_t)0x000E0000)
-#define QSPI_CTRL0_CFS_16_BIT         	   					((uint32_t)0x000F0000)
+#define QSPI_CTRL0_CFS_1_BIT                                ((uint32_t)0x00000000)
+#define QSPI_CTRL0_CFS_2_BIT                                ((uint32_t)0x00010000)
+#define QSPI_CTRL0_CFS_3_BIT                                ((uint32_t)0x00020000)
+#define QSPI_CTRL0_CFS_4_BIT                                ((uint32_t)0x00030000)
+#define QSPI_CTRL0_CFS_5_BIT                                ((uint32_t)0x00040000)
+#define QSPI_CTRL0_CFS_6_BIT                                ((uint32_t)0x00050000)
+#define QSPI_CTRL0_CFS_7_BIT                                ((uint32_t)0x00060000)
+#define QSPI_CTRL0_CFS_8_BIT                                ((uint32_t)0x00070000)
+#define QSPI_CTRL0_CFS_9_BIT                                ((uint32_t)0x00080000)
+#define QSPI_CTRL0_CFS_10_BIT                               ((uint32_t)0x00090000)
+#define QSPI_CTRL0_CFS_11_BIT                               ((uint32_t)0x000A0000)
+#define QSPI_CTRL0_CFS_12_BIT                               ((uint32_t)0x000B0000)
+#define QSPI_CTRL0_CFS_13_BIT                               ((uint32_t)0x000C0000)
+#define QSPI_CTRL0_CFS_14_BIT                               ((uint32_t)0x000D0000)
+#define QSPI_CTRL0_CFS_15_BIT                               ((uint32_t)0x000E0000)
+#define QSPI_CTRL0_CFS_16_BIT                               ((uint32_t)0x000F0000)
 
 #define QSPI_CTRL0_SPI_FRF                          ((uint32_t)0x00C00000) /*!< SPI_FRF[1:0] bits (SPI Frame Format) */
 #define QSPI_CTRL0_SPI_FRF_0                        ((uint32_t)0x00400000) /*!< Bit 0 */
 #define QSPI_CTRL0_SPI_FRF_1                        ((uint32_t)0x00800000) /*!< Bit 1 */
-#define QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT 					((uint32_t)0x00000000)
-#define QSPI_CTRL0_SPI_FRF_DUAL_FORMAT     					((uint32_t)0x00400000)
-#define QSPI_CTRL0_SPI_FRF_QUAD_FORMAT     					((uint32_t)0x00800000)
+#define QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT                  ((uint32_t)0x00000000)
+#define QSPI_CTRL0_SPI_FRF_DUAL_FORMAT                      ((uint32_t)0x00400000)
+#define QSPI_CTRL0_SPI_FRF_QUAD_FORMAT                      ((uint32_t)0x00800000)
 
 /*******************  Bit definition for QSPI_CTRL1 register  *******************/
 #define QSPI_CTRL1_NDF                              ((uint32_t)0x0000FFFF) /*!< NDF[15:0] bits (Numver of Data Frames) */
@@ -8455,12 +8455,12 @@ typedef struct
 
 /*******************  Bit definition for QSPI_MW_CTRL register  *******************/
 #define QSPI_MW_CTRL_MWMOD                          ((uint32_t)0x00000001) /*!< MWMO (Microwire Transfer Mode) */
-#define QSPI_MW_CTRL_MWMOD_UNSEQUENTIAL		  				((uint32_t)0x00000000)
-#define QSPI_MW_CTRL_MWMOD_SEQUENTIAL		  					((uint32_t)0x00000001)
+#define QSPI_MW_CTRL_MWMOD_UNSEQUENTIAL                     ((uint32_t)0x00000000)
+#define QSPI_MW_CTRL_MWMOD_SEQUENTIAL                           ((uint32_t)0x00000001)
 
 #define QSPI_MW_CTRL_MC_DIR                         ((uint32_t)0x00000002) /*!< MC_DIR (Direction of Data when Microwire Control) */
-#define QSPI_MW_CTRL_MC_DIR_RX              				((uint32_t)0x00000000)
-#define QSPI_MW_CTRL_MC_DIR_TX              				((uint32_t)0x00000002)
+#define QSPI_MW_CTRL_MC_DIR_RX                              ((uint32_t)0x00000000)
+#define QSPI_MW_CTRL_MC_DIR_TX                              ((uint32_t)0x00000002)
 
 #define QSPI_MW_CTRL_MHS_EN                         ((uint32_t)0x00000004) /*!< MHS_EN (Microwire Handshaking Enable) */
 
@@ -8530,12 +8530,12 @@ typedef struct
 /*******************  Bit definition for QSPI_STS register  *******************/
 #define QSPI_STS                                    ((uint32_t)0x0000007F) /*!< STS[6:0] (status flag) */
 #define QSPI_STS_BUSY                               ((uint32_t)0x00000001) /*!< BUSY (Transfer Busy Flag) */
-#define QSPI_STS_TXFNF    	                        ((uint32_t)0x00000002) /*!< TXFNF (Transmit FIFO not Full) */
+#define QSPI_STS_TXFNF                              ((uint32_t)0x00000002) /*!< TXFNF (Transmit FIFO not Full) */
 #define QSPI_STS_TXFE                               ((uint32_t)0x00000004) /*!< TXFE (Transmit FIFO not Empty) */
 #define QSPI_STS_RXFNE                              ((uint32_t)0x00000008) /*!< RXFNE (Receive FIFO not Empty) */
 #define QSPI_STS_RXFF                               ((uint32_t)0x00000010) /*!< RXFF (Receive FIFO not Full) */
 #define QSPI_STS_TX_ERR                             ((uint32_t)0x00000020) /*!< TX_ERR (Transmit Error) */
-#define QSPI_STS_DC_ERR		                        	((uint32_t)0x00000040) /*!< DC_ERR (Data Conflict Error) */
+#define QSPI_STS_DC_ERR                                 ((uint32_t)0x00000040) /*!< DC_ERR (Data Conflict Error) */
 
 /*******************  Bit definition for QSPI_IMASK register  *******************/
 #define QSPI_IMASK                                  ((uint32_t)0x0000007F) /*!< IMASK[6:0] (Interrupt of Mask) */
@@ -8684,24 +8684,24 @@ typedef struct
 #define QSPI_RS_DELAY_SDCN_5                        ((uint32_t)0x00000020) /*!< Bit 5 */
 #define QSPI_RS_DELAY_SDCN_6                        ((uint32_t)0x00000040) /*!< Bit 6 */
 #define QSPI_RS_DELAY_SDCN_7                        ((uint32_t)0x00000080) /*!< Bit 7 */
-#define QSPI_RS_DELAY_SDCN_0_CYCLES    							((uint32_t)0x00000000)
-#define QSPI_RS_DELAY_SDCN_1_CYCLES    							((uint32_t)0x00000001)
-#define QSPI_RS_DELAY_SDCN_2_CYCLES    							((uint32_t)0x00000002)
-#define QSPI_RS_DELAY_SDCN_3_CYCLES    							((uint32_t)0x00000003)
-#define QSPI_RS_DELAY_SDCN_4_CYCLES    							((uint32_t)0x00000004)
-#define QSPI_RS_DELAY_SDCN_5_CYCLES    							((uint32_t)0x00000005)
-#define QSPI_RS_DELAY_SDCN_6_CYCLES    							((uint32_t)0x00000006)
+#define QSPI_RS_DELAY_SDCN_0_CYCLES                             ((uint32_t)0x00000000)
+#define QSPI_RS_DELAY_SDCN_1_CYCLES                             ((uint32_t)0x00000001)
+#define QSPI_RS_DELAY_SDCN_2_CYCLES                             ((uint32_t)0x00000002)
+#define QSPI_RS_DELAY_SDCN_3_CYCLES                             ((uint32_t)0x00000003)
+#define QSPI_RS_DELAY_SDCN_4_CYCLES                             ((uint32_t)0x00000004)
+#define QSPI_RS_DELAY_SDCN_5_CYCLES                             ((uint32_t)0x00000005)
+#define QSPI_RS_DELAY_SDCN_6_CYCLES                             ((uint32_t)0x00000006)
 
-#define QSPI_RS_DELAY_SES                     			((uint32_t)0x00010000) /*!< SES (Sample Edge Select of Receive Data) */
-#define QSPI_RS_DELAY_SES_RISING_EDGE  							((uint32_t)0x00000000)
-#define QSPI_RS_DELAY_SES_FALLING_EDGE 							((uint32_t)0x00010000)
+#define QSPI_RS_DELAY_SES                               ((uint32_t)0x00010000) /*!< SES (Sample Edge Select of Receive Data) */
+#define QSPI_RS_DELAY_SES_RISING_EDGE                           ((uint32_t)0x00000000)
+#define QSPI_RS_DELAY_SES_FALLING_EDGE                          ((uint32_t)0x00010000)
 /*******************  Bit definition for QSPI_ENH_CTRL0 register  *******************/
 #define QSPI_ENH_CTRL0_TRANS_TYPE                   ((uint32_t)0x00000003) /*!< TRANS_TYPE[1:0] (Address and instruction transfer format) */
 #define QSPI_ENH_CTRL0_TRANS_TYPE_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
 #define QSPI_ENH_CTRL0_TRANS_TYPE_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD       		((uint32_t)0x00000000)
-#define QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF 		((uint32_t)0x00000001)
-#define QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF     		((uint32_t)0x00000002)
+#define QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD              ((uint32_t)0x00000000)
+#define QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF        ((uint32_t)0x00000001)
+#define QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF            ((uint32_t)0x00000002)
 
 #define QSPI_ENH_CTRL0_ADDR_LEN                     ((uint32_t)0x0000003C) /*!< ADDR_LEN[3:0] (Length of Address to transmit) */
 #define QSPI_ENH_CTRL0_ADDR_LEN_0                   ((uint32_t)0x00000004) /*!< Bit 0 */
@@ -8729,10 +8729,10 @@ typedef struct
 #define QSPI_ENH_CTRL0_INST_L                       ((uint32_t)0x00000300) /*!< INST_L[1:0] (Dual/Quad mode instruction length in bits) */
 #define QSPI_ENH_CTRL0_INST_L_0                     ((uint32_t)0x00000100) /*!< Bit 0 */
 #define QSPI_ENH_CTRL0_INST_L_1                     ((uint32_t)0x00000200) /*!< Bit 1 */
-#define QSPI_ENH_CTRL0_INST_L_0_LINE       					((uint32_t)0x00000000)
-#define QSPI_ENH_CTRL0_INST_L_4_LINE       					((uint32_t)0x00000100)
-#define QSPI_ENH_CTRL0_INST_L_8_LINE       					((uint32_t)0x00000200)
-#define QSPI_ENH_CTRL0_INST_L_16_LINE      					((uint32_t)0x00000300)
+#define QSPI_ENH_CTRL0_INST_L_0_LINE                        ((uint32_t)0x00000000)
+#define QSPI_ENH_CTRL0_INST_L_4_LINE                        ((uint32_t)0x00000100)
+#define QSPI_ENH_CTRL0_INST_L_8_LINE                        ((uint32_t)0x00000200)
+#define QSPI_ENH_CTRL0_INST_L_16_LINE                       ((uint32_t)0x00000300)
 
 #define QSPI_ENH_CTRL0_WAIT_CYCLES                  ((uint32_t)0x0000F800) /*!< WAIT_CYCLES[4:0] (Wait Cycles in Dual/Quad mode between control frames transmit and data reception) */
 #define QSPI_ENH_CTRL0_WAIT_CYCLES_0                ((uint32_t)0x00000800) /*!< Bit 0 */
@@ -8782,10 +8782,10 @@ typedef struct
 #define QSPI_ENH_CTRL0_XIP_MBL                      ((uint32_t)0x0C000000) /*!< XIP_MBL[1:0] (XIP Mode bits length) */
 #define QSPI_ENH_CTRL0_XIP_MBL_0                    ((uint32_t)0x04000000) /*!< Bit 0 */
 #define QSPI_ENH_CTRL0_XIP_MBL_1                    ((uint32_t)0x08000000) /*!< Bit 1 */
-#define QSPI_ENH_CTRL0_XIP_MBL_2_BIT   							((uint32_t)0x00000000)
-#define QSPI_ENH_CTRL0_XIP_MBL_4_BIT   							((uint32_t)0x04000000)
-#define QSPI_ENH_CTRL0_XIP_MBL_8_BIT   							((uint32_t)0x08000000)
-#define QSPI_ENH_CTRL0_XIP_MBL_16_BIT  							((uint32_t)0x0C000000)
+#define QSPI_ENH_CTRL0_XIP_MBL_2_BIT                            ((uint32_t)0x00000000)
+#define QSPI_ENH_CTRL0_XIP_MBL_4_BIT                            ((uint32_t)0x04000000)
+#define QSPI_ENH_CTRL0_XIP_MBL_8_BIT                            ((uint32_t)0x08000000)
+#define QSPI_ENH_CTRL0_XIP_MBL_16_BIT                           ((uint32_t)0x0C000000)
 
 
 #define QSPI_ENH_CTRL0_CLK_STRETCH_EN               ((uint32_t)0x40000000) /*!< CLK_STRETCH_EN (Enable Continuous Transfer in XIP mode) */
@@ -8868,9 +8868,9 @@ typedef struct
 #define QSPI_XIP_CTRL_TRANS_TYPE          ((uint32_t)0x00000003) /*!< TRANS_TYPE[1:0] (Address and instruction transfer format) */
 #define QSPI_XIP_CTRL_TRANS_TYPE_0        ((uint32_t)0x00000001) /*!< Bit 0 */
 #define QSPI_XIP_CTRL_TRANS_TYPE_1        ((uint32_t)0x00000002) /*!< Bit 1 */
-#define QSPI_XIP_CTRL_TRANS_TYPE_STANDARD_SPI    		  ((uint32_t)0x00000000)
-#define QSPI_XIP_CTRL_TRANS_TYPE_ADDRESS_BY_XIP_FRF  	((uint32_t)0x00000004)
-#define QSPI_XIP_CTRL_TRANS_TYPE_INSTRUCT_BY_XIP_FRF 	((uint32_t)0x00000008)
+#define QSPI_XIP_CTRL_TRANS_TYPE_STANDARD_SPI             ((uint32_t)0x00000000)
+#define QSPI_XIP_CTRL_TRANS_TYPE_ADDRESS_BY_XIP_FRF     ((uint32_t)0x00000004)
+#define QSPI_XIP_CTRL_TRANS_TYPE_INSTRUCT_BY_XIP_FRF    ((uint32_t)0x00000008)
 
 #define QSPI_XIP_CTRL_ADDR_LEN            ((uint32_t)0x000000F0) /*!< ADDR_LEN[3:0] (Length of Address to transmit) */
 #define QSPI_XIP_CTRL_ADDR_LEN_0          ((uint32_t)0x00000010) /*!< Bit 0 */
@@ -8973,7 +8973,7 @@ typedef struct
 #define QSPI_XIP_OUT_XTOUT_7              ((uint32_t)0x00000080) /*!< Bit 7 */
 /******************************************************************************/
 /*                                                                            */
-/*                                 TSC Registers           	                  */
+/*                                 TSC Registers                              */
 /*                                                                            */
 /******************************************************************************/
 #if     (TSC_USED_NEW_SDK)
@@ -9178,7 +9178,7 @@ typedef struct
 
 #else
 
-/****************  Bit definition for TSC_CTRL register 		   ****************/
+/****************  Bit definition for TSC_CTRL register            ****************/
 #define TSC_CTRL_DET_PERIOD                ((uint32_t)0x0000000F) /*!< DET_PERIOD[3:0] (Detect period) */
 #define TSC_CTRL_DET_PERIOD_0              ((uint32_t)0x00000001) /*!< Bit 0 */
 #define TSC_CTRL_DET_PERIOD_1              ((uint32_t)0x00000002) /*!< Bit 1 */
@@ -9653,7 +9653,7 @@ typedef struct
 
 /******************************************************************************/
 /*                                                                            */
-/*                                 DVP Registers           	                  */
+/*                                 DVP Registers                              */
 /*                                                                            */
 /******************************************************************************/
 

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_aes.h

@@ -54,28 +54,28 @@
 
 enum
 {
-	AES_Crypto_OK = 0x0,   //AES opreation success
-	AES_Init_OK = 0x0,   //AES Init opreation success
-	AES_Crypto_ModeError = 0x5a5a5a5a,	 //Working mode error(Neither ECB nor CBC nor CTR)
-	AES_Crypto_EnOrDeError,    //En&De error(Neither encryption nor decryption)
-	AES_Crypto_ParaNull,    // the part of input(output/iv) Null    
-	AES_Crypto_LengthError,     // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
-	                            //if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError
+    AES_Crypto_OK = 0x0,   //AES opreation success
+    AES_Init_OK = 0x0,   //AES Init opreation success
+    AES_Crypto_ModeError = 0x5a5a5a5a,   //Working mode error(Neither ECB nor CBC nor CTR)
+    AES_Crypto_EnOrDeError,    //En&De error(Neither encryption nor decryption)
+    AES_Crypto_ParaNull,    // the part of input(output/iv) Null
+    AES_Crypto_LengthError,     // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
+                                //if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError
 
-	AES_Crypto_KeyLengthError, //the keyWordLen must be 4 or 6 or 8; othets:return AES_Crypto_KeyLengthError
+    AES_Crypto_KeyLengthError, //the keyWordLen must be 4 or 6 or 8; othets:return AES_Crypto_KeyLengthError
   AES_Crypto_UnInitError, //AES uninitialized
 };
 
 typedef struct
 {
-	uint32_t *in;		// the part of input to be encrypted or decrypted
-	uint32_t *iv;		// the part of initial vector
-	uint32_t *out;		// the part of out
-	uint32_t *key;		// the part of key
-	uint32_t keyWordLen;   // the length(by word) of key
-	uint32_t inWordLen;	// the length(by word) of plaintext or cipher
-	uint32_t En_De;	// 0x44444444- encrypt, 0x55555555 - decrypt
-	uint32_t Mode;  // 0x11111111 - ECB, 0x22222222 - CBC, 0x33333333 - CTR
+    uint32_t *in;       // the part of input to be encrypted or decrypted
+    uint32_t *iv;       // the part of initial vector
+    uint32_t *out;      // the part of out
+    uint32_t *key;      // the part of key
+    uint32_t keyWordLen;   // the length(by word) of key
+    uint32_t inWordLen; // the length(by word) of plaintext or cipher
+    uint32_t En_De; // 0x44444444- encrypt, 0x55555555 - decrypt
+    uint32_t Mode;  // 0x11111111 - ECB, 0x22222222 - CBC, 0x33333333 - CTR
 }AES_PARM;
 
  /**
@@ -94,7 +94,7 @@ uint32_t  AES_Init(AES_PARM *parm);
  *        2.Input and output can be the same buffer
  *        3. IV can be NULL when ECB mode
  *        4. If Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
- *	         if Working mode is CTR,the length of input message cannot be zero;
+ *           if Working mode is CTR,the length of input message cannot be zero;
  *        5. If the input is in byte, make sure align by word.
  */
 uint32_t AES_Crypto(AES_PARM *parm);

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_algo_common.h

@@ -41,11 +41,11 @@
  */
 enum{
   Cpy_OK=0,//copy success
-	SetZero_OK = 0,//set zero success
-	XOR_OK = 0,   //XOR success
-	Reverse_OK = 0, //Reverse success
-	Cmp_EQUAL = 0, //Two big number are equal
-	Cmp_UNEQUAL = 1, //Two big number are not equal
+    SetZero_OK = 0,//set zero success
+    XOR_OK = 0,   //XOR success
+    Reverse_OK = 0, //Reverse success
+    Cmp_EQUAL = 0, //Two big number are equal
+    Cmp_UNEQUAL = 1, //Two big number are not equal
 
 };
 

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_hash.h

@@ -48,55 +48,55 @@
 #define  ALG_SHA224   (uint16_t)(0x000A)
 #define  ALG_SHA256   (uint16_t)(0x000B)
 #define  ALG_MD5      (uint16_t)(0x000C)
-#define  ALG_SM3	    (uint16_t)(0x0012)
+#define  ALG_SM3        (uint16_t)(0x0012)
 
 enum
 {
-	HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV
-	HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV 
-	HASH_Init_OK = 0,//hash init success
-	HASH_Start_OK = 0,//hash update success
-	HASH_Update_OK = 0,//hash update success
-	HASH_Complete_OK = 0,//hash complete success
-	HASH_Close_OK = 0,//hash close success
-	HASH_ByteLenPlus_OK = 0,//byte length plus success
-	HASH_PadMsg_OK = 0,//message padding success
-	HASH_ProcMsgBuf_OK = 0, //message processing success
-	SHA1_Hash_OK = 0,//sha1 operation success
-	SM3_Hash_OK = 0,//sm3 operation success
-	SHA224_Hash_OK = 0,//sha224 operation success
-	SHA256_Hash_OK = 0,//sha256 operation success
-	MD5_Hash_OK = 0,//MD5 operation success
+    HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV
+    HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV
+    HASH_Init_OK = 0,//hash init success
+    HASH_Start_OK = 0,//hash update success
+    HASH_Update_OK = 0,//hash update success
+    HASH_Complete_OK = 0,//hash complete success
+    HASH_Close_OK = 0,//hash close success
+    HASH_ByteLenPlus_OK = 0,//byte length plus success
+    HASH_PadMsg_OK = 0,//message padding success
+    HASH_ProcMsgBuf_OK = 0, //message processing success
+    SHA1_Hash_OK = 0,//sha1 operation success
+    SM3_Hash_OK = 0,//sm3 operation success
+    SHA224_Hash_OK = 0,//sha224 operation success
+    SHA256_Hash_OK = 0,//sha256 operation success
+    MD5_Hash_OK = 0,//MD5 operation success
 
-	HASH_Init_ERROR = 0x01044400,//hash init error
-	HASH_Start_ERROR, //hash start error
-	HASH_Update_ERROR, //hash update error
-	HASH_ByteLenPlus_ERROR,//hash byte plus error
+    HASH_Init_ERROR = 0x01044400,//hash init error
+    HASH_Start_ERROR, //hash start error
+    HASH_Update_ERROR, //hash update error
+    HASH_ByteLenPlus_ERROR,//hash byte plus error
 };
 
 typedef struct _HASH_CTX_ HASH_CTX;
 
 typedef struct
 {
-	const uint16_t HashAlgID;//choice hash algorithm
-	const uint32_t * const K, KLen;//K and word length of K
-	const uint32_t * const IV, IVLen;//IV and word length of IV
-	const uint32_t HASH_SACCR, HASH_HASHCTRL;//relate registers
-	const uint32_t BlockByteLen, BlockWordLen; //byte length of block, word length of block
-	const uint32_t DigestByteLen, DigestWordLen; //byte length of digest,word length of digest
-	const uint32_t Cycle; //interation times
-	uint32_t (* const ByteLenPlus)(uint32_t *, uint32_t); //function pointer
-	uint32_t (* const PadMsg)(HASH_CTX *); //function pointer
+    const uint16_t HashAlgID;//choice hash algorithm
+    const uint32_t * const K, KLen;//K and word length of K
+    const uint32_t * const IV, IVLen;//IV and word length of IV
+    const uint32_t HASH_SACCR, HASH_HASHCTRL;//relate registers
+    const uint32_t BlockByteLen, BlockWordLen; //byte length of block, word length of block
+    const uint32_t DigestByteLen, DigestWordLen; //byte length of digest,word length of digest
+    const uint32_t Cycle; //interation times
+    uint32_t (* const ByteLenPlus)(uint32_t *, uint32_t); //function pointer
+    uint32_t (* const PadMsg)(HASH_CTX *); //function pointer
 }HASH_ALG;
 
 typedef struct _HASH_CTX_
 {
-	const HASH_ALG	*hashAlg;//pointer to HASH_ALG
-	uint32_t		sequence;	// TRUE if the IV should be saved
-	uint32_t 	IV[16]; 
-	uint32_t		msgByteLen[4];
-  uint8_t		msgBuf[128+4];
-  uint32_t		msgIdx;
+    const HASH_ALG  *hashAlg;//pointer to HASH_ALG
+    uint32_t        sequence;   // TRUE if the IV should be saved
+    uint32_t    IV[16];
+    uint32_t        msgByteLen[4];
+  uint8_t       msgBuf[128+4];
+  uint32_t      msgIdx;
 }HASH_CTX;
 
 extern const HASH_ALG HASH_ALG_SHA1[1];

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_rng.h

@@ -49,8 +49,8 @@
 
 
 enum{
-	RNG_OK = 0x5a5a5a5a,
-	LENError = 0x311ECF50,   //RNG generation of key length error 
+    RNG_OK = 0x5a5a5a5a,
+    LENError = 0x311ECF50,   //RNG generation of key length error
     ADDRNULL = 0x7A9DB86C,   // This address is empty
 };
 

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_qspi.h

@@ -231,7 +231,7 @@ typedef struct
                                                     ((ENH_WAIT_CYCLES) == 0))
 
 #define IS_QSPI_ENH_INST_L(ENH_INST_L)                                                                                            \
-    (((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_0_LINE) || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_4_LINE) || 													\
+    (((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_0_LINE) || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_4_LINE) ||                                                    \
     ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_8_LINE)  || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_16_LINE))
 
 #define IS_QSPI_ENH_MD_BIT_EN(ENH_MD_BIT_EN) (((ENH_MD_BIT_EN) == QSPI_ENH_CTRL0_MD_BIT_EN) || ((ENH_MD_BIT_EN) == 0))