From 19d4c6809c59a0cecfaabd8565297c0e44503860 Mon Sep 17 00:00:00 2001 From: YJIE_1998 <1039241323@qq.com> Date: Thu, 5 Aug 2021 16:01:40 +0800 Subject: [PATCH] =?UTF-8?q?=E3=80=90=E6=B7=BB=E5=8A=A0=E3=80=91dma=5Fconfi?= =?UTF-8?q?g=20=E6=96=87=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../HAL_Drivers/config/f3/dma_config.h | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 bsp/stm32/libraries/HAL_Drivers/config/f3/dma_config.h diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f3/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f3/dma_config.h new file mode 100644 index 0000000000..f2b842485e --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/config/f3/dma_config.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-02 zylx first version + * 2019-01-08 SummerGift clean up the code + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler +#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN +#define UART2_RX_DMA_INSTANCE DMA1_Channel5 +#define UART2_RX_DMA_CHANNEL DMA1_Channel5_BASE +#define UART2_RX_DMA_IRQ DMA1_Channel5_IRQn +#endif + +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_DMA_TX_IRQHandler DMA1_Channel6_IRQHandler +#define UART2_TX_DMA_RCC RCC_AHBENR_DMA1EN +#define UART2_TX_DMA_INSTANCE DMA1_Channel6 +#define UART2_TX_DMA_CHANNEL DMA1_Channel6_BASE +#define UART2_TX_DMA_IRQ DMA1_Channel6_IRQn +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_CONFIG_H__ */