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[bsp][yichip] add yc3122-pos (#7526)

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Co-authored-by: supperthomas <78900636@qq.com>
This commit is contained in:
zhiqiandeng 2023-05-23 16:07:16 +08:00 committed by GitHub
parent 662aa1b7e2
commit 17ce4a462b
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
82 changed files with 64931 additions and 0 deletions
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1
.github/workflows/action.yml vendored
View File

@ -63,6 +63,7 @@ jobs:
- "at32/at32f425-start"
- "at32/at32f435-start"
- "at32/at32f437-start"
- "yichip/yc3122-pos"
- "hc32/ev_hc32f4a0_lqfp176"
- "hc32/ev_hc32f460_lqfp100_v2"
- "hc32l196"

998
bsp/yichip/yc3122-pos/.config Normal file
View File

@ -0,0 +1,998 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=8
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_DM is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x50001
# CONFIG_RT_USING_STDC_ATOMIC is not set
# CONFIG_RT_USING_CACHE is not set
# CONFIG_RT_USING_HW_ATOMIC is not set
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
# CONFIG_RT_USING_CPU_FFS is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
CONFIG_RT_USING_MSH=y
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# DFS: device virtual file system
#
# CONFIG_RT_USING_DFS is not set
# CONFIG_RT_USING_FAL is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_UNAMED_PIPE_NUMBER=64
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
# CONFIG_RT_USING_RANDOM is not set
# CONFIG_RT_USING_PWM is not set
CONFIG_RT_USING_MTD_NOR=y
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_FDT is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_SPI_BITOPS is not set
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
CONFIG_RT_USING_SFUD=y
CONFIG_RT_SFUD_USING_SFDP=y
CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
# CONFIG_RT_SFUD_USING_QSPI is not set
CONFIG_RT_SFUD_SPI_MAX_HZ=50000000
# CONFIG_RT_DEBUG_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_LCD is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_DEV_BUS is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
#
# Using USB
#
# CONFIG_RT_USING_USB is not set
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# C/C++ and POSIX layer
#
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
# CONFIG_RT_USING_POSIX_TIMER is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Interprocess Communication (IPC)
#
# CONFIG_RT_USING_POSIX_PIPE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
#
# Socket is in the 'Network' category
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
# CONFIG_RT_USING_AT is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LWIP is not set
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_IOTSHARP_SDK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_RYANW5500 is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
# CONFIG_PKG_USING_HM is not set
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
# CONFIG_PKG_USING_ZFTP is not set
# CONFIG_PKG_USING_WOL is not set
# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_LIBSODIUM is not set
# CONFIG_PKG_USING_LIBHYDROGEN is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
#
# JSON: JavaScript Object Notation, a lightweight data-interchange format
#
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PARSON is not set
#
# XML: Extensible Markup Language
#
# CONFIG_PKG_USING_SIMPLE_XML is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_LUATOS_SOC is not set
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
# CONFIG_PKG_USING_PIKASCRIPT is not set
# CONFIG_PKG_USING_RTT_RUST is not set
#
# multimedia packages
#
#
# LVGL: powerful and easy-to-use embedded GUI library
#
# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
#
# u8g2: a monochrome graphic library
#
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_3GPP_AMRNB is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
# CONFIG_PKG_USING_FDT is not set
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
#
# system packages
#
#
# enhanced kernel services
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_PERF_COUNTER is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_MCUBOOT is not set
# CONFIG_PKG_USING_TINYUSB is not set
# CONFIG_PKG_USING_CHERRYUSB is not set
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
# CONFIG_PKG_USING_FLASH_BLOB is not set
# CONFIG_PKG_USING_MLIBC is not set
#
# peripheral libraries and drivers
#
#
# sensors drivers
#
# CONFIG_PKG_USING_LSM6DSM is not set
# CONFIG_PKG_USING_LSM6DSL is not set
# CONFIG_PKG_USING_LPS22HB is not set
# CONFIG_PKG_USING_HTS221 is not set
# CONFIG_PKG_USING_LSM303AGR is not set
# CONFIG_PKG_USING_BME280 is not set
# CONFIG_PKG_USING_BME680 is not set
# CONFIG_PKG_USING_BMA400 is not set
# CONFIG_PKG_USING_BMI160_BMX160 is not set
# CONFIG_PKG_USING_SPL0601 is not set
# CONFIG_PKG_USING_MS5805 is not set
# CONFIG_PKG_USING_DA270 is not set
# CONFIG_PKG_USING_DF220 is not set
# CONFIG_PKG_USING_HSHCAL001 is not set
# CONFIG_PKG_USING_BH1750 is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_TSL4531 is not set
# CONFIG_PKG_USING_DS18B20 is not set
# CONFIG_PKG_USING_DHT11 is not set
# CONFIG_PKG_USING_DHTXX is not set
# CONFIG_PKG_USING_GY271 is not set
# CONFIG_PKG_USING_GP2Y10 is not set
# CONFIG_PKG_USING_SGP30 is not set
# CONFIG_PKG_USING_HDC1000 is not set
# CONFIG_PKG_USING_BMP180 is not set
# CONFIG_PKG_USING_BMP280 is not set
# CONFIG_PKG_USING_SHTC1 is not set
# CONFIG_PKG_USING_BMI088 is not set
# CONFIG_PKG_USING_HMC5883 is not set
# CONFIG_PKG_USING_MAX6675 is not set
# CONFIG_PKG_USING_TMP1075 is not set
# CONFIG_PKG_USING_SR04 is not set
# CONFIG_PKG_USING_CCS811 is not set
# CONFIG_PKG_USING_PMSXX is not set
# CONFIG_PKG_USING_RT3020 is not set
# CONFIG_PKG_USING_MLX90632 is not set
# CONFIG_PKG_USING_MLX90393 is not set
# CONFIG_PKG_USING_MLX90392 is not set
# CONFIG_PKG_USING_MLX90397 is not set
# CONFIG_PKG_USING_MS5611 is not set
# CONFIG_PKG_USING_MAX31865 is not set
# CONFIG_PKG_USING_VL53L0X is not set
# CONFIG_PKG_USING_INA260 is not set
# CONFIG_PKG_USING_MAX30102 is not set
# CONFIG_PKG_USING_INA226 is not set
# CONFIG_PKG_USING_LIS2DH12 is not set
# CONFIG_PKG_USING_HS300X is not set
# CONFIG_PKG_USING_ZMOD4410 is not set
# CONFIG_PKG_USING_ISL29035 is not set
# CONFIG_PKG_USING_MMC3680KJ is not set
# CONFIG_PKG_USING_QMP6989 is not set
# CONFIG_PKG_USING_BALANCE is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
#
# touch drivers
#
# CONFIG_PKG_USING_GT9147 is not set
# CONFIG_PKG_USING_GT1151 is not set
# CONFIG_PKG_USING_GT917S is not set
# CONFIG_PKG_USING_GT911 is not set
# CONFIG_PKG_USING_FT6206 is not set
# CONFIG_PKG_USING_FT5426 is not set
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
#
# Kendryte SDK
#
# CONFIG_PKG_USING_K210_SDK is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_MULTI_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_ILI9341 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_AIP650 is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_UKAL is not set
#
# miscellaneous packages
#
#
# project laboratory
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_CMATRIX is not set
# CONFIG_PKG_USING_SL is not set
# CONFIG_PKG_USING_CAL is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_HEATSHRINK is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
# CONFIG_PKG_USING_CONTROLLER is not set
# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
# CONFIG_PKG_USING_MFBD is not set
# CONFIG_PKG_USING_SLCAN2RTT is not set
# CONFIG_PKG_USING_SOEM is not set
# CONFIG_PKG_USING_QPARAM is not set
# CONFIG_PKG_USING_CorevMCU_CLI is not set
#
# Arduino libraries
#
# CONFIG_PKG_USING_RTDUINO is not set
#
# Projects
#
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
#
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
# CONFIG_PKG_USING_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
# CONFIG_PKG_USING_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
#
# Data Processing
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
#
# Data Storage
#
#
# Communication
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
#
# Device Control
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
#
# Uncategorized
#
CONFIG_SOC_YC3122=y
#
# Hardware Drivers Config
#
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
#
# UART Drivers
#
CONFIG_BSP_USING_UART0=y
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_INTER_FLASH is not set

27
bsp/yichip/yc3122-pos/Kconfig Normal file
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@ -0,0 +1,27 @@
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_YC3122
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
source "drivers/Kconfig"

9
bsp/yichip/yc3122-pos/Libraries/.ignore_format.yml Normal file
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@ -0,0 +1,9 @@
# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- CMSIS
- core
- sdk
- startup

11215
bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Include/YC3122.svd Normal file
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File diff suppressed because it is too large Load Diff

79
bsp/yichip/yc3122-pos/Libraries/CMSIS/Device/YICHIP/YC3122/Include/system_yc3122.h Normal file
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@ -0,0 +1,79 @@
/**************************************************************************//**
* @file system_<Device>.h
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for
* Device <Device>
* @version V3.10
* @date 23. November 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef SYSTEM_YC3122_H /* ToDo: replace '<Device>' with your device name */
#define SYSTEM_YC3122_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "yc3122.h"
#include "type.h"
#include "rom_api.h"
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_<Device>_H */

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;/*
; * Copyright (c) 2006-2020, YICHIP Development Team
; * @file yc_startup.s
; * @brief source file for setting startup
; *
; * Change Logs:
; * Date Author Version Notes
; * 2020-11-06 wushengyan V1.0.0 the first version
; * 2021-03-11 wushengyan V1.0.2 Change for New ROM
; */
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=4
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=4
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset Rom code change to 0x1000200
AREA RESET, CODE, READONLY ,ALIGN=4
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp
DCD Reset_Handler ;//reset 1
DCD 0x00000000 ;//NMI 2
DCD hard_fault_handler ;//HARD 3
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD svc_handler ;//SVC 11
DCD 0 ;
DCD 0 ;
DCD pendsv_handler ;//PENDSV 14
DCD systick_handler ;//SYSTICK 15
DCD USB_IRQHandler ;//IQR0
DCD I2C0_IRQHandler ;//IQR1
DCD I2C1_IRQHandler ;//IQR2
DCD QSPI_IRQHandler ;//IQR3
DCD SPI0_IRQHandler ;//IQR4
DCD SPI1_IRQHandler ;
DCD HSPI_IRQHandler ;
DCD SEC_IRQHandler ;
DCD UART0_IRQHandler ;
DCD UART1_IRQHandler ;
DCD UART2_IRQHandler ;
DCD UART3_IRQHandler ;
DCD MEMCP_IRQHandler ;
DCD SCI0_IRQHandler ;
DCD SCI1_IRQHandler ;
DCD MSR_IRQHandler ;
DCD GPIO_IRQHandler ;
DCD TMRG0_IRQHandler ;
DCD TMRG1_IRQHandler ;
DCD SDIO_IRQHandler ;
DCD PSARM_IRQHandler ;
DCD RSA_IRQHandler ;
DCD SM4_IRQHandler ;
DCD TRNG_IRQHandler ;
DCD WDT_IRQHandler ;
DCD DCMI_IRQHandler ;
DCD ADC_IRQHandler ;
DCD RTC_IRQHandler ;
DCD BIN_IRQHandler ;
DCD POWER_IRQHandler ;
DCD SOFTWARE_IRQHandler ;
DCD RISCV_IRQHandler ;
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
isr PROC
LDR R1,=0x1000200
LDR R0,[R0,R1]
BX R0
NOP
NOP
NOP
ENDP
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
hard_fault_handler PROC
EXPORT hard_fault_handler
IMPORT HardFault_Handler
ldr r0,=HardFault_Handler
bx r0
nop
ENDP
svc_handler PROC
EXPORT svc_handler
ldr r0,=SVC_IRQHandler
bx r0
nop
ENDP
pendsv_handler PROC
EXPORT pendsv_handler
IMPORT PendSV_Handler
ldr r0,=PendSV_Handler
bx r0
nop
ENDP
systick_handler PROC
EXPORT systick_handler
IMPORT SysTick_Handler
ldr r0,=SysTick_Handler
bx r0
nop
ENDP
ALIGN
Default_Handler PROC
; ToDo: Add here the export definition for the device specific external interrupts handler
EXPORT HARD_FAULT_IRQHandler [WEAK]
EXPORT SVC_IRQHandler [WEAK]
EXPORT PENDSV_IRQHandler [WEAK]
EXPORT SYSTICK_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT TIMER4_IRQHandler [WEAK]
EXPORT TIMER5_IRQHandler [WEAK]
EXPORT TIMER6_IRQHandler [WEAK]
EXPORT TIMER7_IRQHandler [WEAK]
EXPORT TIMER8_IRQHandler [WEAK]
EXPORT CHGRIN_IRQHandler [WEAK]
EXPORT VBAT_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT QSPI_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT HSPI_IRQHandler [WEAK]
EXPORT SEC_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT MEMCP_IRQHandler [WEAK]
EXPORT SCI0_IRQHandler [WEAK]
EXPORT SCI1_IRQHandler [WEAK]
EXPORT MSR_IRQHandler [WEAK]
EXPORT GPIO_IRQHandler [WEAK]
EXPORT TMRG0_IRQHandler [WEAK]
EXPORT TMRG1_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT PSARM_IRQHandler [WEAK]
EXPORT RSA_IRQHandler [WEAK]
EXPORT SM4_IRQHandler [WEAK]
EXPORT TRNG_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT BIN_IRQHandler [WEAK]
EXPORT POWER_IRQHandler [WEAK]
EXPORT SOFTWARE_IRQHandler [WEAK]
EXPORT RISCV_IRQHandler [WEAK]
; ToDo: Add here the names for the device specific external interrupts handler
HARD_FAULT_IRQHandler
SVC_IRQHandler
PENDSV_IRQHandler
SYSTICK_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
EXTI5_IRQHandler
EXTI6_IRQHandler
EXTI7_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
TIMER4_IRQHandler
TIMER5_IRQHandler
TIMER6_IRQHandler
TIMER7_IRQHandler
TIMER8_IRQHandler
CHGRIN_IRQHandler
VBAT_IRQHandler
USB_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
QSPI_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
HSPI_IRQHandler
SEC_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
MEMCP_IRQHandler
SCI0_IRQHandler
SCI1_IRQHandler
MSR_IRQHandler
GPIO_IRQHandler
TMRG0_IRQHandler
TMRG1_IRQHandler
SDIO_IRQHandler
PSARM_IRQHandler
RSA_IRQHandler
SM4_IRQHandler
TRNG_IRQHandler
WDT_IRQHandler
DCMI_IRQHandler
ADC_IRQHandler
RTC_IRQHandler
BIN_IRQHandler
POWER_IRQHandler
SOFTWARE_IRQHandler
RISCV_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, = __initial_sp
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

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;/*
; * Copyright (c) 2006-2020, YICHIP Development Team
; * @file yc_flash_start_gcc.s
; * @brief source file for setting flash_start_gcc
; *
; * Change Logs:
; * Date Author Version Notes
; * 2020-11-06 wushengyan V1.0.0 the first version
; */
.org 0x200
.global Reset_Handler,HARD_FAULT_IRQHandler,SVC_IRQHandler,PENDSV_IRQHandler,SYSTICK_IRQHandler
vectors:
.long 0x00030000
.long Reset_Handler ;//reset 1
.long 0x00000000 ;//NMI 2
.long hard_fault_handler ;//HARD 3
.long 0 ;
.long 0 ;
.long 0 ;
.long 0 ;
.long 0 ;
.long 0 ;
.long 0 ;
.long svc_handler ;//SVC 11
.long 0 ;
.long 0 ;
.long pendsv_handler ;//PENDSV 14
.long systick_handler ;//SYSTICK 15
.long USB_IRQHandler ;//IQR0
.long I2C0_IRQHandler ;//IQR1
.long I2C1_IRQHandler ;//IQR2
.long QSPI_IRQHandler ;//IQR3
.long SPI0_IRQHandler ;//IQR4
.long SPI1_IRQHandler ;
.long HSPI_IRQHandler ;
.long SEC_IRQHandler ;
.long UART0_IRQHandler ;
.long UART1_IRQHandler ;
.long UART2_IRQHandler ;
.long UART3_IRQHandler ;
.long MEMCP_IRQHandler ;
.long SCI0_IRQHandler ;
.long SCI1_IRQHandler ;
.long MSR_IRQHandler ;
.long GPIO_IRQHandler ;
.long TMRG0_IRQHandler ;
.long TMRG1_IRQHandler ;
.long SDIO_IRQHandler ;
.long PSARM_IRQHandler ;
.long RSA_IRQHandler ;
.long SM4_IRQHandler ;
.long TRNG_IRQHandler ;
.long WDT_IRQHandler ;
.long DCMI_IRQHandler ;
.long ADC_IRQHandler ;
.long RTC_IRQHandler ;
.long BIN_IRQHandler ;
.long POWER_IRQHandler ;
.long SOFTWARE_IRQHandler ;
.long RISCV_IRQHandler ;
.thumb_func
isr:
LDR R1,=0x1000200
LDR R0,[R0,R1]
BX R0
NOP
NOP
NOP
.thumb_func
Reset_Handler:
LDR R0,=SystemInit
BLX R0
LDR R0,=hardware_init
BX R0
hard_fault_handler:
ldr r0,=HardFault_Handler
bx r0
svc_handler:
ldr r0,=SVC_IRQHandler
bx r0
pendsv_handler:
ldr r0,=PendSV_Handler
bx r0
systick_handler:
ldr r0,=SysTick_Handler
bx r0
.thumb
.thumb_func
hardware_init:
ldr r1, =__exidx_start
ldr r2, =__data_start__
ldr r3, =__data_end__
sub r3, r2
ble .L_loop1_done
.L_loop1:
sub r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
.L_loop1_done:
;/* Single BSS section scheme.
; *
; * The BSS section is specified by following symbols
; * _sbss: start of the BSS section.
; * _ebss: end of the BSS section.
; *
; * Both addresses must be aligned to 4 bytes boundary.
; */
ldr r1, =__bss_start__
ldr r2, =__bss_end__
mov r0, #0
sub r2, r1
ble .L_loop3_done
.L_loop3:
sub r2, #4
str r0, [r1, r2]
bgt .L_loop3
.L_loop3_done:
ldr r0,=0x12345
ldr r3,=0x1111
bl main
.globl delay
.syntax unified
delay:
subs r0,#1
bne delay
nop
bx lr
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers
*/
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler HARD_FAULT_IRQHandler
def_irq_handler SVC_IRQHandler
def_irq_handler PENDSV_IRQHandler
def_irq_handler SYSTICK_IRQHandler
def_irq_handler EXTI0_IRQHandler
def_irq_handler EXTI1_IRQHandler
def_irq_handler EXTI2_IRQHandler
def_irq_handler EXTI3_IRQHandler
def_irq_handler EXTI4_IRQHandler
def_irq_handler TIMER0_IRQHandler
def_irq_handler TIMER1_IRQHandler
def_irq_handler TIMER2_IRQHandler
def_irq_handler TIMER3_IRQHandler
def_irq_handler TIMER4_IRQHandler
def_irq_handler TIMER5_IRQHandler
def_irq_handler TIMER6_IRQHandler
def_irq_handler TIMER7_IRQHandler
def_irq_handler TIMER8_IRQHandler
def_irq_handler CHGRIN_IRQHandler
def_irq_handler VBAT_IRQHandler
def_irq_handler USB_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler QSPI_IRQHandler
def_irq_handler SPI0_IRQHandler
def_irq_handler SPI1_IRQHandler
def_irq_handler HSPI_IRQHandler
def_irq_handler SEC_IRQHandler
def_irq_handler UART0_IRQHandler
def_irq_handler UART1_IRQHandler
def_irq_handler UART2_IRQHandler
def_irq_handler UART3_IRQHandler
def_irq_handler MEMCP_IRQHandler
def_irq_handler SCI0_IRQHandler
def_irq_handler SCI1_IRQHandler
def_irq_handler MSR_IRQHandler
def_irq_handler GPIO_IRQHandler
def_irq_handler TMRG0_IRQHandler
def_irq_handler TMRG1_IRQHandler
def_irq_handler SDIO_IRQHandler
def_irq_handler PSARM_IRQHandler
def_irq_handler RSA_IRQHandler
def_irq_handler SM4_IRQHandler
def_irq_handler TRNG_IRQHandler
def_irq_handler WDT_IRQHandler
def_irq_handler DCMI_IRQHandler
def_irq_handler ADC_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler BIN_IRQHandler
def_irq_handler POWER_IRQHandler
def_irq_handler SOFTWARE_IRQHandler
def_irq_handler RISCV_IRQHandler

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;/*
; * Copyright (c) 2006-2020, YICHIP Development Team
; * @file startup_yc3122.s
; * @brief source file for setting startup
; *
; * Change Logs:
; * Date Author Version Notes
; * 2022-11-08 kiven V1.0.0 the first version
; */
MODULE ?cstartup ; // 定义模块名称
;Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start ; // IAR 入口函数
EXTERN SystemInit ; // 系统初始化函数
PUBLIC _vector_table ; // 中断向量表地址
ALIGNROM 2
DATA ; // 定义数据段
_vector_table ;中断向量表
DCD sfe(CSTACK)
DCD Reset_Handler ;//reset 1
DCD 0x00000000 ;//NMI 2
DCD hard_fault_handler ;//HARD 3
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD svc_handler ;//SVC 11
DCD 0 ;
DCD 0 ;
DCD pendsv_handler ;//PENDSV 14
DCD systick_handler ;//SYSTICK 15
DCD USB_IRQHandler ;//IQR0
DCD I2C0_IRQHandler ;//IQR1
DCD I2C1_IRQHandler ;//IQR2
DCD QSPI_IRQHandler ;//IQR3
DCD SPI0_IRQHandler ;//IQR4
DCD SPI1_IRQHandler ;
DCD HSPI_IRQHandler ;
DCD SEC_IRQHandler ;
DCD UART0_IRQHandler ;
DCD UART1_IRQHandler ;
DCD UART2_IRQHandler ;
DCD UART3_IRQHandler ;
DCD MEMCP_IRQHandler ;
DCD SCI0_IRQHandler ;
DCD SCI1_IRQHandler ;
DCD MSR_IRQHandler ;
DCD GPIO_IRQHandler ;
DCD TMRG0_IRQHandler ;
DCD TMRG1_IRQHandler ;
DCD SDIO_IRQHandler ;
DCD PSARM_IRQHandler ;
DCD RSA_IRQHandler ;
DCD SM4_IRQHandler ;
DCD TRNG_IRQHandler ;
DCD WDT_IRQHandler ;
DCD DCMI_IRQHandler ;
DCD ADC_IRQHandler ;
DCD RTC_IRQHandler ;
DCD BIN_IRQHandler ;
DCD POWER_IRQHandler ;
DCD SOFTWARE_IRQHandler ;
DCD RISCV_IRQHandler ;
THUMB ;//进入THUMB模式（THUMB-2指令集）
SECTION .intvec:CODE:REORDER(2)
CODE
PUBLIC isr
isr
LDR R1,=_vector_table
LDR R0,[R0,R1]
BX R0
NOP
NOP
NOP
PUBLIC Reset_Handler
Reset_Handler
LDR R0, =sfe(CSTACK)
mov sp, R0
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
hard_fault_handler PROC
EXPORT hard_fault_handler
IMPORT HardFault_Handler
LDR r0,=HardFault_Handler
BX r0
nop
ENDP
svc_handler PROC
EXPORT svc_handler
ldr r0,=SVC_IRQHandler
BX r0
nop
ENDP
pendsv_handler PROC
EXPORT pendsv_handler
IMPORT PendSV_Handler
LDR r0,=PendSV_Handler
BX r0
nop
ENDP
systick_handler PROC
EXPORT systick_handler
IMPORT SysTick_Handler
LDR r0,=SysTick_Handler
BX r0
nop
ENDP
; // 定义默认的中断函数，这里只是弱定义，可以被用户自己定义的中断向量函数覆盖
PUBWEAK HARD_FAULT_IRQHandler
PUBWEAK SVC_IRQHandler
PUBWEAK PENDSV_IRQHandler
PUBWEAK SYSTICK_IRQHandler
PUBWEAK EXTI_IRQHandler
PUBWEAK TIMER0_IRQHandler
PUBWEAK TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
PUBWEAK TIMER3_IRQHandler
PUBWEAK TIMER4_IRQHandler
PUBWEAK TIMER5_IRQHandler
PUBWEAK TIMER6_IRQHandler
PUBWEAK TIMER7_IRQHandler
PUBWEAK TIMER8_IRQHandler
PUBWEAK CHGRIN_IRQHandler
PUBWEAK VBAT_IRQHandler
PUBWEAK USB_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK QSPI_IRQHandler
PUBWEAK SPI0_IRQHandler
PUBWEAK SPI1_IRQHandler
PUBWEAK HSPI_IRQHandler
PUBWEAK SEC_IRQHandler
PUBWEAK UART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK UART2_IRQHandler
PUBWEAK UART3_IRQHandler
PUBWEAK MEMCP_IRQHandler
PUBWEAK SCI0_IRQHandler
PUBWEAK SCI1_IRQHandler
PUBWEAK MSR_IRQHandler
PUBWEAK GPIO_IRQHandler
PUBWEAK TMRG0_IRQHandler
PUBWEAK TMRG1_IRQHandler
PUBWEAK SDIO_IRQHandler
PUBWEAK PSARM_IRQHandler
PUBWEAK RSA_IRQHandler
PUBWEAK SM4_IRQHandler
PUBWEAK TRNG_IRQHandler
PUBWEAK WDT_IRQHandler
PUBWEAK DCMI_IRQHandler
PUBWEAK ADC_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK BIN_IRQHandler
PUBWEAK POWER_IRQHandler
PUBWEAK SOFTWARE_IRQHandler
PUBWEAK RISCV_IRQHandler
; ToDo: Add here the names for the device specific external interrupts handler
HARD_FAULT_IRQHandler
SVC_IRQHandler
PENDSV_IRQHandler
SYSTICK_IRQHandler
EXTI_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
TIMER4_IRQHandler
TIMER5_IRQHandler
TIMER6_IRQHandler
TIMER7_IRQHandler
TIMER8_IRQHandler
CHGRIN_IRQHandler
VBAT_IRQHandler
USB_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
QSPI_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
HSPI_IRQHandler
SEC_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
MEMCP_IRQHandler
SCI0_IRQHandler
SCI1_IRQHandler
MSR_IRQHandler
GPIO_IRQHandler
TMRG0_IRQHandler
TMRG1_IRQHandler
SDIO_IRQHandler
PSARM_IRQHandler
RSA_IRQHandler
SM4_IRQHandler
TRNG_IRQHandler
WDT_IRQHandler
DCMI_IRQHandler
ADC_IRQHandler
RTC_IRQHandler
BIN_IRQHandler
POWER_IRQHandler
SOFTWARE_IRQHandler
RISCV_IRQHandler
B .
END

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/**************************************************************************//**
* @file system_<Device>.c
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Source File for
* Device <Device>
* @version V3.10
* @date 23. November 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include <stdint.h>
#include "system_yc3122.h"
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
/* ToDo: add here your necessary defines for device initialization
following is an example for different system frequencies */
#define __HSI (192000000UL)
#define __SYSTEM_CLOCK (__HSI / 4)
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
/* ToDo: initialize SystemCoreClock with the system core clock frequency value
achieved after system intitialization.
This means system core clock frequency after call to SystemInit() */
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* ToDo: add code to calculate the system frequency based upon the current
register settings.
This function can be used to retrieve the system core clock frequeny
after user changed register sittings. */
SystemCoreClock = __SYSTEM_CLOCK;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
/* ToDo: add code to initialize the system
do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
/* Write access code "0x55->0xaa->0x17" to set or clear "access_en" */
MLPM->ACCESS_CODE.reg = 0x55;
MLPM->ACCESS_CODE.reg = 0xaa;
MLPM->ACCESS_CODE.reg = 0x17;
if (MLPM->ACCESS_EN.reg != ENABLE)
{
MLPM->ACCESS_EN.reg = ENABLE;
}
MLPM->BAKEUP_REG1.reg = 0xaaaaaaaa;
}

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7
* @date 19. June 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.5
* @date 28. May 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.0
* @date 23. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if non-shareable) or 010b (if shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

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from building import *
import rtconfig
import os
cwd = GetCurrentDir()
path_sdk = os.path.join(cwd,'sdk')
path_core = os.path.join(cwd,'core')
path_cmin = os.path.join(cwd,'CMSIS','Include')
path_cmde = os.path.join(cwd,'CMSIS','Device','YICHIP','YC3122')
src = Glob('sdk/*.c')
CPPPATH = [path_sdk,path_core,path_cmin,os.path.join(path_cmde,'Include'),cwd]
src += Glob(path_cmde + '/Source/Templates/*.c')
src += ['core/system.c']
if rtconfig.PLATFORM in ['gcc']:
src += ['sdk/libyc_qspi.a']
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
src += ['sdk/yc_qspi.lib']
if rtconfig.PLATFORM in ['gcc']:
src += [path_cmde + '/Source/Templates/gcc/startup_yc3122.S']
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
src += [path_cmde + '/Source/Templates/arm/startup_yc3122.s']
elif rtconfig.PLATFORM in ['iccarm']:
src += [path_cmde + '/Source/Templates/iar/startup_yc3122.s']
group = DefineGroup('Libraries', src, depend = [''],CPPPATH = CPPPATH, CPPDEFINES = ['__USE_YC_M0__'])
Return('group')

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/*
* Copyright (c) 2006-2021, YICHIP Development Team
* @file yc_rom_api.h
* @brief source file for setting rom_api
*
* Change Logs:
* Date Author Version Notes
* 2021-06-23 wushengyan V1.0.0 the first version
*/
#ifndef __RV_31XX_H__
#define __RV_31XX_H__
#ifdef __USE_YC_RISC_V__
#include "type.h"
#ifdef __cplusplus
extern "C" {
#endif
/* IO definitions (access restrictions to peripheral registers) */
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*end IO definitions*/
#define __STATIC_INLINE static __inline
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC PLIC
- Core SysTick Register
******************************************************************************/
/******************** RISC-V REG START **************************************/
typedef struct
{
__IO uint32_t RV_PAUSE_EN : 1;
__IO uint32_t RV_PAUSE_START : 1;
__IO uint32_t RV_DCLK_EN : 1;
__IO uint32_t RV_QSORTCLK_EN : 1;
__IO uint32_t RV_BINCLK_EN : 1;
__IO uint32_t DBG_STEP_EN : 1;
__IO uint32_t FPU_STEP_DIS : 1;
__IO uint32_t LONGP_STEP_EN : 1;
__IO uint32_t RV_CORECLK_EN : 8;
__I uint32_t RV_CTRL_RSVD : 16;
__IO uint32_t RV_WKUP_SRC_EN : 32;
__IO uint32_t RV_PC_RTVEC : 32;
__IO uint32_t RV_STACK_ADDR : 32;
} RVCtrl_TypeDef;
typedef struct
{
__IO uint32_t ICE_CTRL : 16;
__IO uint32_t ICE_CMD : 4;
__I uint32_t ICE_CTRL_RSVD : 12;
__IO uint32_t ICE_BREAK0 : 25;
__I uint32_t ICE_BREAK0_RSVD : 7;
__IO uint32_t ICE_BREAK1 : 25;
__I uint32_t ICE_BREAK1_RSVD : 7;
__IO uint32_t ICE_REG_WDATA : 32;
__I uint32_t ICE_REG_RDATA : 32;
__IO uint32_t TRACE_ADDR : 25;
__I uint32_t TRACE_ADDR_RSVD : 7;
__I uint32_t TRACE_FIFO_RDATA : 25;
__I uint32_t TRACE_FIFO_RDATA_RSVD : 7;
__I uint32_t EXE_ADDR : 32;
__I uint32_t ICE_STATUS : 8;
__I uint32_t ICE_STATUS_RSVD : 24; //RV_CTRL
} RVIce_TypeDef;
typedef struct
{
__IO uint32_t BIN_CTRL_BLOCK_ENABLE : 1;
__IO uint32_t BIN_CTRL_GRID_MODE : 1;
__IO uint32_t BIN_CTRL_CUT_ENABLE : 1;
__IO uint32_t BIN_CTRL_SCALER_ENABLE : 1;
__IO uint32_t BIN_CTRL_INV_BIT_ENABLE : 1;
__I uint32_t BIN_CTRL_RSVD : 3;
__IO uint32_t RANGE : 8;
__IO uint32_t SUB_HEIGHT : 8;
__IO uint32_t SUB_WIDTH : 8;
__IO uint32_t RAW_BIN_BASEADDR : 24;
__I uint32_t RAW_BIN_BASEADDR_RSVD : 8;
__IO uint32_t RGB_BASEADDR : 24;
__I uint32_t RGB_BASEADDR_RSVD : 8;
__IO uint32_t AVG_BASEADDR : 24;
__I uint32_t AVG_BASEADDR_RSVD : 8;
__IO uint32_t SCA_BIN_BASEADDR : 24;
__I uint32_t SCA_BIN_BASEADDR_RSVD : 8;
__I uint32_t BIN_STATUS : 32;
__I uint32_t RAW_DOUT_ADDR_LOCK : 24;
__I uint32_t RAW_DOUT_ADDR_LOCK_RSVD : 8;
__I uint32_t SCA_DOUT_ADDR_LOCK : 24;
__I uint32_t SCA_DOUT_ADDR_LOCK_RSVD : 8;
__IO uint32_t QSORT_CTRL : 32;
__IO uint32_t QSORT_BASEADDR : 24;
__I uint32_t QSORT_BASEADDR_RSVD : 8;
__I uint32_t QSORT_DONE : 1;
__I uint32_t QSORT_DONE_RSVD : 31;
__IO uint32_t ONE_RGB_BASEADDR : 24;
__I uint32_t ONE_RGB_BASEADDR_RSVD : 8;
__IO uint32_t FAST_BIN_BASEADDR : 24;
__I uint32_t FAST_BIN_BASEADDR_RSVD : 8;
__IO uint32_t CANNY_BIN_BASEADDR : 24;
__I uint32_t CANNY_BIN_BASEADDR_RSVD : 8;
__IO uint32_t ONE_BIN_CTRL : 13;
__I uint32_t ONE_BIN_CTRL_RSVD : 19;
__IO uint32_t FAST_BIN_CTRL : 24;
__I uint32_t FAST_BIN_CTRL_RSVD : 8;
__IO uint32_t CANNY_BIN_CTRL : 23;
__I uint32_t CANNY_BIN_CTRL_RSVD : 9;
__IO uint32_t CANNY_BIN_CTRL1 : 12;
__I uint32_t CANNY_BIN_CTRL1_RSVD : 20;
__IO uint32_t ONE_BIN_STATUS : 21;
__I uint32_t ONE_BIN_STATUS_RSVD : 11;
__IO uint32_t FAST_BIN_BASEADDR_USED : 24;
__I uint32_t FAST_BIN_BASEADDR_USED_RSVD : 8;
__IO uint32_t CANNY_BIN_BASEADDR_USED : 24;
__I uint32_t CANNY_BIN_BASEADDR_USED_RSVD : 8;
} RVBin_TypeDef;
typedef struct
{
__IO uint32_t JTAG_SW_SEL :1;
__I uint32_t JTAG_SW_SEL_RSVD :3;
__IO uint32_t DAP_REG_BASE_ADDR :4;
__I uint32_t DAP_CTRL_RSVD :24;
__IO uint32_t RV_TM_EN :1;
__IO uint32_t RV_TM_EN_RSVD :31;
__IO uint32_t RV_TM_CNT :32;
__IO uint32_t M0_TO_RV_IE :1;
__I uint32_t M0_TO_RV_IE_RSVD :7;
__IO uint32_t M0_TO_RV_IRQ :1;
__I uint32_t M0_TO_RV_IRQ_RSVD :7;
__IO uint32_t RV_TO_M0_IRQ_TRIG :1;
__I uint32_t RV_TO_M0_IRQ_TRIG_RSVD :15;
__IO uint32_t IRQ_SW_EN :1;
__IO uint32_t IRQ_SW_PEND :1;
__I uint32_t IRQ_SW_RSVD :6;
__IO uint32_t IRQ_SW_CODE :8;
__I uint32_t RV_SW_IRQ_RSVD :16;
}RVIrq_TypeDef;
#define MPU_REGION_NUM 4
typedef struct
{
__IO uint8_t Protect_region[MPU_REGION_NUM];
} RVMPUREGION_TypeDef;
typedef struct
{
__IO uint32_t BaseAndLimit[MPU_REGION_NUM];
} RVMPUBASE_TypeDef;
#define BASE_LIMIT_REGION_NUM 4
typedef struct
{
__IO uint32_t MPU_ENABLE_CODE : 4;
__IO RVMPUREGION_TypeDef ICB_PROTECT;
__IO RVMPUREGION_TypeDef DTCM_PROTECT;
__IO RVMPUREGION_TypeDef ITCM_PROTECT;
__IO uint32_t USER_START : 24;
__IO uint32_t MPU_STS_CLR;
__I uint32_t FAULT_STATUS;
__I uint32_t FAULT_ADDR_ICB;
__I uint32_t FAULT_ADDR_DTCM;
__I uint32_t FAULT_ADDR_ITCM;
__IO RVMPUBASE_TypeDef ICB_BASE;
__IO RVMPUBASE_TypeDef DTCM_BASE;
__IO RVMPUBASE_TypeDef ITCM_BASE;
__IO RVMPUBASE_TypeDef ICB_LIMIT;
__IO RVMPUBASE_TypeDef DTCM_LIMIT;
__IO RVMPUBASE_TypeDef ITCM_LIMIT;
} RVMPU_TypeDef;
typedef struct
{
__IO uint32_t WDT_EN : 1;
__IO uint32_t WDT_EN_LOCK : 1;
__IO uint32_t WDT_ACT : 1;
__I uint32_t WDT_CTRL_RSVD1 : 5;
__IO uint32_t WDT_DIV : 4;
__I uint32_t WDT_CTRL_RSVD2 : 20;
__IO uint32_t WDT_KEY : 16;
__I uint32_t WDT_KEY_RSVD : 16;
__IO uint32_t WDT_RELOAD_VALUE : 32;
__I uint32_t WDT_CNT : 32;
__IO uint32_t WDT_IRQ_EN : 1;
__I uint32_t WDT_IRQ_EN_RSVD : 31;
__IO uint32_t WDT_IRQ : 1;
__I uint32_t WDT_IRQ_RSVD : 31;
} RVWdt_TypeDef;
#define YC3122_RV_BASE (0x000E0000UL) /* RV Base Address */
#define RV_CTRL_BASEADDR (YC3122_RV_BASE + 0x00000) //0xe0000
#define RV_ICE_BASEADDR (YC3122_RV_BASE + 0x00004) //0xe0004
#define RV_BIN_BASEADDR (YC3122_RV_BASE + 0x00034) //0xe0034
#define RV_IRQ_BASEADDR (YC3122_RV_BASE + 0x000D0) //0xe00d0
#define RV_SYSTICK_BASEADDR (YC3122_RV_BASE + 0x000D0) //0xe00d4
#define RV_MPU_BASEADDR (YC3122_RV_BASE + 0x00100) //0xe0100
#define RV_IRQ_PRIO_BASEADDR (YC3122_RV_BASE + 0x01000) //0xe1000
#define RV_IRQ_PEND_BASEADDR (YC3122_RV_BASE + 0x02000) //0xe2000
#define RV_IRQ_ENAB_BASEADDR (YC3122_RV_BASE + 0x03000) //0xe3000
#define RV_IRQ_THRD_BASEADDR (YC3122_RV_BASE + 0x04000) //0xe4000
#define RV_IRQ_CLAM_BASEADDR (YC3122_RV_BASE + 0x04004) //0xe4004
#define RV_WDT_BASEADDR (0xfb700) //0xfb700
#define RV_CTRL1 ((RVCtrl_TypeDef *)RV_CTRL_BASEADDR)
#define RV_ICE ((RVIce_TypeDef *)RV_ICE_BASEADDR)
#define RV_BIN ((RVBin_TypeDef *)RV_BIN_BASEADDR)
#define RISC_IRQ ((RVIrq_TypeDef *)RV_IRQ_BASEADDR)
/*risc-v mpu map start*/
#define RV_MPU_ICB_PROTECT_BASE (RV_MPU_BASEADDR + 0x0004)
#define RV_MPU_DTCM_PROTECT_BASE (RV_MPU_ICB_PROTECT_BASE + 0x0004)
#define RV_MPU_ITCM_PROTECT_BASE (RV_MPU_DTCM_PROTECT_BASE + 0x0004)
#define RV_MPU_ICB_BASE_BASE (RV_MPU_BASEADDR + 0x0040)
#define RV_MPU_DTCM_BASE_BASE (RV_MPU_ICB_BASE_BASE + 0x0010)
#define RV_MPU_ITCM_BASE_BASE (RV_MPU_DTCM_BASE_BASE + 0x0010)
#define RV_MPU_ICB_LIMIT_BASE (RV_MPU_BASEADDR + 0x0080)
#define RV_MPU_DTCM_LIMIT_BASE (RV_MPU_ICB_LIMIT_BASE + 0x0010)
#define RV_MPU_ITCM_LIMIT_BASE (RV_MPU_DTCM_LIMIT_BASE + 0x0010)
/*risc-v mpu reg start*/
#define RVMPU ((RVMPU_TypeDef *)RV_MPU_BASEADDR)
#define ICB_PROTECTION ((RVMPUREGION_TypeDef *)RV_MPU_ICB_PROTECT_BASE)
#define DTCM_PROTECTION ((RVMPUREGION_TypeDef *)RV_MPU_DTCM_PROTECT_BASE)
#define ITCM_PROTECTION ((RVMPUREGION_TypeDef *)RV_MPU_ITCM_PROTECT_BASE)
#define ICB_BASE ((RVMPUBASE_TypeDef *)RV_MPU_ICB_BASE_BASE)
#define DTCM_BASE ((RVMPUBASE_TypeDef *)RV_MPU_DTCM_BASE_BASE)
#define ITCM_BASE ((RVMPUBASE_TypeDef *)RV_MPU_ITCM_BASE_BASE)
#define ICB_LIMIT ((RVMPUBASE_TypeDef *)RV_MPU_ICB_LIMIT_BASE)
#define DTCM_LIMIT ((RVMPUBASE_TypeDef *)RV_MPU_DTCM_LIMIT_BASE)
#define ITCM_LIMIT ((RVMPUBASE_TypeDef *)RV_MPU_ITCM_LIMIT_BASE)
#define RV_WDT ((RVWdt_TypeDef *)RV_WDT_BASEADDR)
#define RV_IRQ_PRIO(x) *(volatile uint8_t*)(RV_IRQ_PRIO_BASEADDR + ((uint8_t)((uint8_t)(x)/2)))
#define RV_IRQ_PEND(x) *(volatile uint8_t*)(RV_IRQ_PEND_BASEADDR + ((uint8_t)((uint8_t)(x)/8)))
#define RV_IRQ_ENAB(x) *(volatile uint8_t*)(RV_IRQ_ENAB_BASEADDR + ((uint8_t)((uint8_t)(x)/8)))
#define RV_IRQ_THOD *(volatile int*)(RV_IRQ_THRD_BASEADDR)
#define RV_IRQ_CLAM *(volatile int*)(RV_IRQ_CLAM_BASEADDR)
/******************** RISC-V REG END **************************************/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
uint32_t TM_EN; /*!< Offset: 0x000 (R/W) SysTick Enable */
uint32_t TM_CNT; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
} SysTick_Type;
#define SysTick ((SysTick_Type *) RV_SYSTICK_BASEADDR ) /*!< SysTick configuration struct */
/******************************************************************************/
/**
* @method RV EnableIRQ
* @brief Enable IRQ
* @param IRQn : USB_IRQn...
* @retval NULL
*/
__STATIC_INLINE void RV_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
RV_IRQ_ENAB(IRQn) |= (uint32_t)(1UL << (uint8_t)((uint8_t)(IRQn)%8));
}
}
/**
* @method RV DisableIRQ
* @brief Disable IRQ
* @param IRQn : USB_IRQn...
* @retval NULL
*/
__STATIC_INLINE void RV_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
RV_IRQ_ENAB(IRQn) &= ~(uint32_t)(1UL << (uint8_t)((uint8_t)(IRQn)%8));
}
}
/**
* @method RV SetPriority
* @brief SetPriority IRQ
* @param IRQn : USB_IRQn...
* @param priority : 0~15
* @retval NULL
*/
__STATIC_INLINE void RV_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0 && priority > 0 && priority < 16)
{
RV_IRQ_PRIO(IRQn) |= (priority << (uint8_t)((uint8_t)(IRQn)%2)*4);
}
}
/**
* @method RV Get Pending Interrupt
* @brief Reads The PLIC pending register returns the pending bit
* @param IRQn : USB_IRQn...
* @retval 0: Interrupt status is not pending.
* 1: Interrupt status is pending
*/
__STATIC_INLINE uint32_t RV_GetPendingIRQ(IRQn_Type IRQn)
{
}
/**
* @method RV Get Interrupt Priority
* @brief Reads the priority of a device specific interrupt
* @param IRQn : USB_IRQn...
* @retval Interrupt Priority.
*/
__STATIC_INLINE uint32_t RV_GetPriority(IRQn_Type IRQn)
{
}
/**
* @method NVIC_Configuration
* @brief NVIC initialization function for risc-v.
* @param IRQn: Interrupt vector numbers could be 0~31.
* @param priority: Interrupt priority numbers could be 1~15.
* @param newstate: enable or disable
* @retval None
*/
__STATIC_INLINE void NVIC_Configuration(IRQn_Type IRQn, uint32_t priority,FunctionalState newstate)
{
if(newstate == ENABLE )
{
RV_EnableIRQ(IRQn);
RV_SetPriority(IRQn, priority);
}
else
{
RV_DisableIRQ(IRQn);
RV_SetPriority(IRQn, priority);
}
}
/**
* @method SysTick_Config
* @brief Initializes the System Timer and its interrupt (priority default 1)
* @param ticks: Number of ticks between two interrupts. (0~0xffffffff)
* @retval 0: FuncTion succeeded.
* 1: Function failed.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
SysTick->TM_CNT = ticks;
RV_EnableIRQ(34); /*set systick priority*/
RV_SetPriority(34,15);
SysTick->TM_EN = 1;
return (0UL);
}
/**
* @method __enable_irq
* @brief Enable IRQ Interrupts
* @retval NONE.
*/
__STATIC_INLINE void __enable_irq(void)
{
__asm("csrs mstatus,0x00000008");
}
/**
* @method __disable_irq
* @brief Disable IRQ Interrupts
* @retval NONE.
*/
__STATIC_INLINE void __disable_irq(void)
{
__asm("csrc mstatus,0x00000008");
}
/*make M0 and RV IRQ equ*/
#define NVIC_EnableIRQ RV_EnableIRQ
#define NVIC_DisableIRQ RV_DisableIRQ
#define NVIC_SetPriority RV_SetPriority
#define NVIC_GetPendingIRQ RV_GetPendingIRQ
/*end*/
#ifdef __cplusplus
}
#endif
#endif
#endif

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bsp/yichip/yc3122-pos/Libraries/core/rom_api.h Normal file
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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_rom_api.h
* @brief source file for setting rom_api
*
* Change Logs:
* Date Author Version Notes
* 2020-11-05 wushengyan V1.0.0 the first version
*/
#ifndef __ROM_API_H__
#define __ROM_API_H__
#define YC3122_AA (0)
#define YC3122_AB (1)
#define IC_DEVICE YC3122_AB
#if (IC_DEVICE == YC3122_AA)
/* TIMER */
#define FUNC_DELAY_US_ADDR (0x5030 + 1)
#define FUNC_DELAY_MS_ADDR (0x5068 + 1)
/* OTP */
#define FUNC_INIT_OTP_ADDR (0x5468 + 1)
#define FUNC_DEINIT_OTP_ADDR (0x54c8 + 1)
#define FUNC_READ_OTP_ADDR (0x5510 + 1)
#define FUNC_WRITE_OTP_ADDR (0x5648 + 1)
#define FUNC_READ_CHIPID_ADDR (0x56ac + 1)
#define FUNC_READ_CHIPLF_ADDR (0x56ba + 1)
/* LPM */
#define FUNC_LIGHT_SLEEP_ADDR (0x5338 + 1)
#define FUNC_DEEP_SLEEP_ADDR (0x535c + 1)
/* QSPI */
#define FUNC_ENC_WRITE_FLASH_ADDR (0x67c0 + 1)
#define FUNC_QSPI_FLASH_SECTORERASE_ADDR (0x59a8 + 1)
#define FUNC_QSPI_FLASH_BLOCKERASE_ADDR (0x59b4 + 1)
#define FUNC_QSPI_FLASH_BLOCK64ERASE_ADDR (0x59c0 + 1)
#define FUNC_QSPI_FLASH_WRITE_ADDR (0x58e8 + 1)
#define FUNC_QSPI_FLASH_READ_ADDR (0x59ea + 1)
#define FUNC_FLASH_BLANK_CHECK (0x670c + 1)
#define FUNC_PREFETCH (0x5398 + 1)
#define FUNC_READ_FLASH_ID (0x5a54 + 1)
#elif (IC_DEVICE == YC3122_AB)
/* TIMER */
#define FUNC_DELAY_US_ADDR (0x5020 + 1)
#define FUNC_DELAY_MS_ADDR (0x5058 + 1)
/* OTP */
#define FUNC_INIT_OTP_ADDR (0x5458 + 1)
#define FUNC_DEINIT_OTP_ADDR (0x54b8 + 1)
#define FUNC_READ_OTP_ADDR (0x5500 + 1)
#define FUNC_WRITE_OTP_ADDR (0x5638 + 1)
#define FUNC_READ_CHIPID_ADDR (0x569c + 1)
#define FUNC_READ_CHIPLF_ADDR (0x56aa + 1)
/* LPM */
#define FUNC_LIGHT_SLEEP_ADDR (0x5328 + 1)
#define FUNC_DEEP_SLEEP_ADDR (0x534c + 1)
/* QSPI */
#define FUNC_ENC_WRITE_FLASH_ADDR (0x6798 + 1)
#define FUNC_QSPI_FLASH_SECTORERASE_ADDR (0x5998 + 1)
#define FUNC_QSPI_FLASH_BLOCKERASE_ADDR (0x59a4 + 1)
#define FUNC_QSPI_FLASH_BLOCK64ERASE_ADDR (0x59b0 + 1)
#define FUNC_QSPI_FLASH_WRITE_ADDR (0x58d8 + 1)
#define FUNC_QSPI_FLASH_READ_ADDR (0x59da + 1)
#define FUNC_FLASH_BLANK_CHECK (0x66e4 + 1)
#define FUNC_PREFETCH (0x5388 + 1)
#define FUNC_READ_FLASH_ID (0x5a44 + 1)
#define FUNC_QSPI_FLASH_CMD (0x57ec + 1)
#endif
#endif

391
bsp/yichip/yc3122-pos/Libraries/core/system.c Normal file
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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_system.c
* @brief source file for setting system
*
* Change Logs:
* Date Author Version Notes
* 2020-11-05 wushengyan V1.0.0 the first version
*/
#include <stdarg.h>
#include "system.h"
//*****************************************************************************
//
//! A simple MyPrintf function supporting \%c, \%d, \%p, \%s, \%u,\%x, and \%X.
//!
//! \param format is the format string.
//! \param ... are the optional arguments, which depend on the contents of the
//! \return None.
//
//*****************************************************************************
typedef struct _PrintPort_TypeDef_
{
UART_TypeDef *PrintUart;
GPIO_TypeDef PrintRX_Port;
GPIO_Pin_TypeDef PrintRX_Pin;
GPIO_TypeDef PrintTX_Port;
GPIO_Pin_TypeDef PrintTX_Pin;
} PrintPort_TypeDef;
static PrintPort_TypeDef PrintPort_Struct =
{
.PrintUart = PRINTPORT,
.PrintRX_Port = PRINTRX_PORT,
.PrintRX_Pin = PRINTRX_IO_PIN,
.PrintTX_Port = PRINTTX_PORT,
.PrintTX_Pin = PRINTTX_IO_PIN,
};
//#define SIM_PLATFORM
void print_char(int data)
{
volatile int *ptr;
ptr = (volatile int *)0xE0300;
*ptr = data;
}
void printfsend(uint8_t *buf, int len)
{
uint8_t printbuf[256];
for (int i = 0; i < len; i++)
{
printbuf[i] = buf[i];
#ifdef SIM_PLATFORM
print_char(buf[i]);
#endif
}
#ifndef SIM_PLATFORM
//UART_SendBuf(PrintPort_Struct.PrintUart, printbuf, len);
UART_SendBuf(PRINTPORT, printbuf, len);
#endif
}
void MyPrintf(char *format, ...)
{
static const int8_t *const g_pcHex1 = "0123456789abcdef";
static const int8_t *const g_pcHex2 = "0123456789ABCDEF";
uint32_t ulIdx = 0, ulValue = 0, ulPos = 0, ulCount = 0, ulBase = 0, ulNeg = 0;
int8_t *pcStr = NULL, pcBuf[16] = {0}, cFill = 0;
char HexFormat;
va_list vaArgP;
va_start(vaArgP, format);
while (*format)
{
/* Find the first non-% character, or the end of the string. */
for (ulIdx = 0; (format[ulIdx] != '%') && (format[ulIdx] != '\0'); ulIdx++)
{}
/* Write this portion of the string. */
if (ulIdx > 0)
{
printfsend((uint8_t *)format, ulIdx);
}
format += ulIdx;
if (*format == '%')
{
format++;
/* Set the digit count to zero, and the fill character to space */
/* (i.e. to the defaults) */
ulCount = 0;
cFill = ' ';
again:
switch (*format++)
{
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
{
if ((format[-1] == '0') && (ulCount == 0))
{
cFill = '0';
}
ulCount *= 10;
ulCount += format[-1] - '0';
goto again;
}
case 'c':
{
ulValue = va_arg(vaArgP, unsigned long);
printfsend((uint8_t *)&ulValue, 1);
break;
}
case 'd':
{
ulValue = va_arg(vaArgP, unsigned long);
ulPos = 0;
if ((long)ulValue < 0)
{
ulValue = -(long)ulValue;
ulNeg = 1;
}
else
{
ulNeg = 0;
}
ulBase = 10;
goto convert;
}
case 's':
{
pcStr = (int8_t *)va_arg(vaArgP, char *);
for (ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++)
{}
printfsend((uint8_t *)pcStr, ulIdx);
if (ulCount > ulIdx)
{
ulCount -= ulIdx;
while (ulCount--)
{
printfsend((uint8_t *)" ", 1);
}
}
break;
}
case 'u':
{
ulValue = va_arg(vaArgP, unsigned long);
ulPos = 0;
ulBase = 10;
ulNeg = 0;
goto convert;
}
case 'X':
{
ulValue = va_arg(vaArgP, unsigned long);
ulPos = 0;
ulBase = 16;
ulNeg = 0;
HexFormat = 'X';
goto convert;
}
case 'x':
case 'p':
{
ulValue = va_arg(vaArgP, unsigned long);
ulPos = 0;
ulBase = 16;
ulNeg = 0;
HexFormat = 'x';
convert:
for (ulIdx = 1;
(((ulIdx * ulBase) <= ulValue) &&
(((ulIdx * ulBase) / ulBase) == ulIdx));
ulIdx *= ulBase, ulCount--)
{
}
if (ulNeg)
{
ulCount--;
}
if (ulNeg && (cFill == '0'))
{
pcBuf[ulPos++] = '-';
ulNeg = 0;
}
if ((ulCount > 1) && (ulCount < 16))
{
for (ulCount--; ulCount; ulCount--)
{
pcBuf[ulPos++] = cFill;
}
}
if (ulNeg)
{
pcBuf[ulPos++] = '-';
}
for (; ulIdx; ulIdx /= ulBase)
{
if (HexFormat == 'x')
pcBuf[ulPos++] = g_pcHex1[(ulValue / ulIdx) % ulBase];//x
else
pcBuf[ulPos++] = g_pcHex2[(ulValue / ulIdx) % ulBase];//X
}
printfsend((uint8_t *)pcBuf, ulPos);
break;
}
case '%':
{
printfsend((uint8_t *)format - 1, 1);
break;
}
default:
{
printfsend((uint8_t *)"ERROR", 5);
break;
}
}/* switch */
}/* if */
}/* while */
va_end(vaArgP);
}
void printv(uint8_t *buf, uint32_t len, char *s)
{
uint32_t i = 0;
uint32_t n = 0;
MyPrintf("\r\n%s:", s);
for (i = 0; i < len; i++)
{
if (i % 16 == 0)
{
MyPrintf("\r\n%08x:", n);
n += 16;
}
MyPrintf("%02x ", buf[i]);
}
MyPrintf("\r\n");
}
static void PrintPort_Init(void)
{
UART_InitTypeDef UART_InitStruct;
UART_InitStruct.BaudRate = PRINT_BAUD; //Configure serial port baud rate, the baud rate defaults to 128000.
UART_InitStruct.DataBits = DATABITS_8B;
UART_InitStruct.StopBits = STOPBITS_1;
UART_InitStruct.Parity = YC_PARITY_NONE;
UART_InitStruct.FlowCtrl = FLOWCTRL_NONE;
UART_InitStruct.RxMode = MODE_RX_ENABLE;
UART_InitStruct.SmartCard = SMARTCARD_DISABLE;
UART_InitStruct.CommMode = MODE_DUPLEX;
if (PrintPort_Struct.PrintUart == MUART0)
{
GPIO_Config(PrintPort_Struct.PrintRX_Port, PrintPort_Struct.PrintRX_Pin, UART0_RXD);
GPIO_Config(PrintPort_Struct.PrintTX_Port, PrintPort_Struct.PrintTX_Pin, UART0_TXD);
}
else if (PrintPort_Struct.PrintUart == MUART1)
{
GPIO_Config(PrintPort_Struct.PrintRX_Port, PrintPort_Struct.PrintRX_Pin, UART1_RXD);
GPIO_Config(PrintPort_Struct.PrintTX_Port, PrintPort_Struct.PrintTX_Pin, UART1_TXD);
}
else if (PrintPort_Struct.PrintUart == MUART2)
{
GPIO_Config(PrintPort_Struct.PrintRX_Port, PrintPort_Struct.PrintRX_Pin, UART2_RXD);
GPIO_Config(PrintPort_Struct.PrintTX_Port, PrintPort_Struct.PrintTX_Pin, UART2_TXD);
}
else if (PrintPort_Struct.PrintUart == MUART3)
{
GPIO_Config(PrintPort_Struct.PrintRX_Port, PrintPort_Struct.PrintRX_Pin, UART3_RXD);
GPIO_Config(PrintPort_Struct.PrintTX_Port, PrintPort_Struct.PrintTX_Pin, UART3_TXD);
}
UART_Init(PrintPort_Struct.PrintUart, &UART_InitStruct);
uint8_t print_irq = (PrintPort_Struct.PrintUart - MUART0) / (MUART1 - MUART0);
NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + print_irq));
NVIC_SetPriority((IRQn_Type)(UART0_IRQn + print_irq),1);
}
void PrintPort_Set(UART_TypeDef *UARTx)
{
PrintPort_Struct.PrintUart = UARTx;
// if(UARTx == MUART1)
// {
// PrintPort_Struct.PrintRX_Port = UART1RX_PORT;
// PrintPort_Struct.PrintRX_Pin = UART1RX_IO_PIN;
// PrintPort_Struct.PrintTX_Port = UART1TX_PORT;
// PrintPort_Struct.PrintTX_Pin = UART1TX_IO_PIN;
// }
}
void Board_Init(void)
{
/*fpga io func sel*/
#if (BOARD_TYPE == FPGA_BOARD)
uint8_t fpga_io_func_sel_list[][2] =
{
#ifdef __SPI0_FLASH_FPGA__
{0x02,0x01},
{0x08,0x01},
{0x21,0x40},
#endif
{0x00,0x00},
#ifdef __SPI1_FLASH_FPGA__
{0x05,0x01},
{0x08,0x01},
{0x21,0x80},
#endif
#ifdef __SCANNER_BF3007_BCTC_FPGA__
{0x01,0x01}, //func_sel1: ALT1 psram
{0x08,0x01}, //func_sel8: ALT1 tft
{0x09,0x01}, //func_sel9: ALT1 tft led
{0x02,0x01}, //func_sel9: ALT1 spia
{0x21,0x04}, //spi_sel:tft_spi_sel: SPIy
{0x20,0x02}, //iic_sel:iic0_sel: fingerprint i2c
{0x04,0x01}, //sel iica
{0x06,0x02}, //func_sel6: ALT2 fingerprint DCMI
{0x07,0x01}, //alt1 buzzer
#endif
};
for(uint8_t i = 0; i < (sizeof(fpga_io_func_sel_list)/2); i ++)
{
FPGA_reg_write(fpga_io_func_sel_list[i][0],fpga_io_func_sel_list[i][1]);
}
#endif
/*print init*/
PrintPort_Init();
}
void _assert_handler(const char *file, int line, const char *func)
{
#if defined (SDK_DEBUG)
if(PRINTPORT->CTRL.bit.RX_EN == MODE_RX_ENABLE) /*check printuart is init*/
{
MyPrintf("Assert trigger at file: %s line:%d func: %s\n ", file, line, func);
}
#endif
while (1);
}

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_system.h
* @brief source file for setting system
*
* Change Logs:
* Date Author Version Notes
* 2020-11-05 wushengyan V1.0.0 the first version
*/
#ifndef __SYSTEM_H__
#define __SYSTEM_H__
#define SDK_DEBUG //Debug switch
#include <string.h>
#include "yc_uart.h"
#include "rom_api.h"
#include "board_config.h"
#define BIT_SET(a,b) ((a) |= (1<<(b)))
#define BIT_CLEAR(a,b) ((a) &= ~(1<<(b)))
#define BIT_FLIP(a,b) ((a) ^= (1<<(b))) //bit Negation
#define BIT_GET(a,b) (((a) & (1<<(b)))>>(b))
/**
* @brief Print format string to serial port 0.You need to initialize the serial port 0 before you use MyPrintf.
*
* @param format : format string
* @param ...: format parameter
*/
void MyPrintf(char *format, ...);
void printv(uint8_t *buf, uint32_t len, char *s);
void PrintPort_Set(UART_TypeDef *UARTx);
void Board_Init(void);
void _assert_handler(const char *file, int line, const char *func);
#ifdef SDK_DEBUG
#define _ASSERT(x) \
if (!(x)) \
{ \
_assert_handler(__FILE__,__LINE__,__FUNCTION__);\
}
#else
#define _ASSERT(x)
#endif
#define YC_DEBUG_LOG(type, message) \
do \
{ \
if (type) \
MyPrintf message; \
} \
while (0)
#endif /*__SYSTEM_H__*/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_type.h
* @brief source file for setting type
*
* Change Logs:
* Date Author Version Notes
* 2020-11-05 wushengyan V1.0.0 the first version
*/
#ifndef __TYPE_H__
#define __TYPE_H__
#if defined (__CC_ARM) || defined ( __ICCARM__ )
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long uint64_t;
typedef unsigned char byte;
typedef unsigned short word;
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed int int32_t;
typedef signed long long int64_t;
#else
#include "stdio.h"
typedef unsigned char byte;
typedef unsigned short word;
#endif
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
*/
#define __NOINLINE noinline
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif
#ifndef Boolean
typedef enum {FALSE = 0, TRUE =1} Boolean;
#define IS_BOOLEAN(bool) ((bool == FALSE) || (bool == TRUE))
#endif
#ifndef FunctionalState
typedef enum {DISABLE = 0, ENABLE =1} FunctionalState;
#define IS_FUNCTIONAL_STATE(state) ((state== DISABLE) || (state == ENABLE))
#endif
#ifndef FunctionalState
typedef enum {ERROR = 0, SUCCESS = 1} ErrorStatus;
#define IS_ERROR_STATE(status) ((status== ERROR) || (status == SUCCESS))
#endif
#ifndef FlagStatus
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
#endif
#ifndef YC_NULL
#define YC_NULL (0)
#endif
#ifndef NULL
#define NULL (0)
#endif
#endif /*__TYPE_H__*/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_exit.c
* @brief source file for setting exit
*
* Change Logs:
* Date Author Version Notes
* 2021-12-24 yangzhengfeng V1.0.0 Modify the register module configuration
* 2021-01-03 wangjingfan V1.0.1 Compile error correction
* 2021-01-20 yangzhengfeng V1.0.2 Update library function
*/
#include "yc_exti.h"
/**
* @brief Clear interrupt flag
* @param EXTI_Line:EXTI_Line_0...EXTI_Line_4
* @param EXTI_PinSource:EXTI_PinSource0...EXTI_PinSource15
* @retval none
*/
void EXTI_ClearITPendingBit(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource)
{
_ASSERT(IS_EXTI_LINE(EXTI_Line));
_ASSERT(IS_EXTI_PIN_SOURCE(EXTI_PinSource));
MGPIO->IRQ_STATUS.reg[EXTI_Line] |= EXTI_PinSource;
}
/**
* @brief Deinitializes the EXTI registers to default reset values.
* @param none
* @retval none
*/
void EXTI_DeInit()
{
uint32_t i;
for (i = 0; i < EXIT_Num; i++)
{
MGPIO->INTR.reg[i] = 0;
MGPIO->IRQ_LEVEL.reg[i] = 0;
MGPIO->IRQ_RISE.reg[i] = 0;
MGPIO->IRQ_FALL.reg[i] = 0;
}
}
/**
* @brief get interrupt status
* @param EXTI_Line:EXTI_Line_0...EXTI_Line_4
* @retval none
*/
uint16_t EXTI_GetITLineStatus(EXTI_LineTypeDef EXTI_Line)
{
_ASSERT(IS_EXTI_LINE(EXTI_Line));
return MGPIO->INTR.reg[EXTI_Line];
}
/**
* @brief get interrupt pinsource status
* @param EXTI_Line:EXTI_Line_0...EXTI_Line_4
* @param EXTI_PinSource:EXTI_PinSource0...EXTI_PinSource15
* @retval none
*/
uint16_t EXTI_GetITEXTI_PinSourceStatus(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource)
{
_ASSERT(IS_EXTI_LINE(EXTI_Line));
_ASSERT(IS_EXTI_PIN_SOURCE(EXTI_PinSource));
if(MGPIO->INTR.reg[EXTI_Line] & EXTI_PinSource)
{
return ENABLE;
}
else
{
return DISABLE;
}
}
/**
* @brief EXTI LineConfig
* @param EXTI_Line:EXTI_Line_0...EXTI_Line_4
* @param EXTI_PinSource:EXTI_PinSource0...EXTI_PinSource15
* @param EXTI_Trigger:EXTI Trigger mode
* @retval none
*/
void EXTI_LineConfig(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource, EXTI_TriggerTypeDef EXTI_Trigger)
{
_ASSERT(IS_EXTI_LINE(EXTI_Line));
_ASSERT(IS_EXTI_PIN_SOURCE(EXTI_PinSource));
_ASSERT(IS_TRIG_TYPEDEF(EXTI_Trigger));
uint16_t val_intr_lts,val_intr_rts,val_intr_fts,val_intr_en;
switch (EXTI_Trigger)
{
case EXTI_Trigger_Off:
val_intr_en = ~EXTI_PinSource;
val_intr_lts = ~EXTI_PinSource;
val_intr_rts = ~EXTI_PinSource;
val_intr_fts = ~EXTI_PinSource;
break;
case EXTI_Trigger_HighLev:
val_intr_en = EXTI_PinSource;
val_intr_lts = ~EXTI_PinSource;
val_intr_rts = ~EXTI_PinSource;
val_intr_fts = ~EXTI_PinSource;
break;
case EXTI_Trigger_LowLev:
val_intr_en = EXTI_PinSource;
val_intr_lts = EXTI_PinSource;
val_intr_rts = ~EXTI_PinSource;
val_intr_fts = ~EXTI_PinSource;
break;
case EXTI_Trigger_Rising:
val_intr_en = EXTI_PinSource;
val_intr_lts = ~EXTI_PinSource;
val_intr_rts = EXTI_PinSource;
val_intr_fts = ~EXTI_PinSource;
break;
case EXTI_Trigger_Falling:
val_intr_en = EXTI_PinSource;
val_intr_lts = ~EXTI_PinSource;
val_intr_rts = ~EXTI_PinSource;
val_intr_fts = EXTI_PinSource;
break;
case EXTI_Trigger_Rising_Falling:
val_intr_en = EXTI_PinSource;
val_intr_lts = ~EXTI_PinSource;
val_intr_rts = EXTI_PinSource;
val_intr_fts = EXTI_PinSource;
break;
default:
break;
}
if (EXTI_Trigger == EXTI_Trigger_Off)
{
MGPIO->INTR.reg[EXTI_Line] &= val_intr_en;
MGPIO->IRQ_LEVEL.reg[EXTI_Line] &= val_intr_lts;
MGPIO->IRQ_RISE.reg[EXTI_Line] &= val_intr_rts;
MGPIO->IRQ_FALL.reg[EXTI_Line] &= val_intr_fts;
}
else if (EXTI_Trigger == EXTI_Trigger_HighLev )
{
MGPIO->IRQ_LEVEL.reg[EXTI_Line] &= val_intr_lts;
MGPIO->IRQ_RISE.reg[EXTI_Line] &= val_intr_rts;
MGPIO->IRQ_FALL.reg[EXTI_Line] &= val_intr_fts;
MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
}
else if (EXTI_Trigger == EXTI_Trigger_LowLev )
{
MGPIO->IRQ_LEVEL.reg[EXTI_Line] |= val_intr_lts;
MGPIO->IRQ_RISE.reg[EXTI_Line] &= val_intr_rts;
MGPIO->IRQ_FALL.reg[EXTI_Line] &= val_intr_fts;
MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
}
else if (EXTI_Trigger == EXTI_Trigger_Rising )
{
MGPIO->IRQ_LEVEL.reg[EXTI_Line] &= val_intr_lts;
MGPIO->IRQ_RISE.reg[EXTI_Line] |= val_intr_rts;
MGPIO->IRQ_FALL.reg[EXTI_Line] &= val_intr_fts;
MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
}
else if (EXTI_Trigger == EXTI_Trigger_Falling )
{
MGPIO->IRQ_LEVEL.reg[EXTI_Line] &= val_intr_lts;
MGPIO->IRQ_RISE.reg[EXTI_Line] &= val_intr_rts;
MGPIO->IRQ_FALL.reg[EXTI_Line] |= val_intr_fts;
MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
}
else if (EXTI_Trigger == EXTI_Trigger_Rising_Falling )
{
MGPIO->IRQ_LEVEL.reg[EXTI_Line] &= val_intr_lts;
MGPIO->IRQ_RISE.reg[EXTI_Line] |= val_intr_rts;
MGPIO->IRQ_FALL.reg[EXTI_Line] |= val_intr_fts;
MGPIO->INTR.reg[EXTI_Line] |= val_intr_en;
}
}
//extern void VBAT_IRQHandler(void);
//extern void EXTI0_IRQHandler(void);
//extern void EXTI1_IRQHandler(void);
//extern void EXTI2_IRQHandler(void);
//extern void EXTI3_IRQHandler(void);
//extern void EXTI4_IRQHandler(void);
//void GPIO_IRQHandler()
//{
// uint8_t Exti_irq_index;
// NVIC_DisableIRQ(GPIO_IRQn);
// if (MSYSCTRL->CHGR_EVENT_IRQ.bit.VBAT_OV & MSYSCTRL->CHGR_EVENT_ICTRL.bit.VBAT_OV_IE)
// {
// //VBAT_IRQHandler();
// }
// Exti_irq_index = MGPIO->IRQ_NUM.reg;
// if(MGPIO->INTR.reg[Exti_irq_index/EXIT_Pin_Num] &(1 << (Exti_irq_index%EXIT_Pin_Num)))
// {
// switch (Exti_irq_index/EXIT_Pin_Num)
// {
// case EXTI_Line_0:
// EXTI0_IRQHandler();
// break;
// case EXTI_Line_1:
// EXTI1_IRQHandler();
// break;
// case EXTI_Line_2:
// EXTI2_IRQHandler();
// break;
// case EXTI_Line_3:
// EXTI3_IRQHandler();
// break;
// case EXTI_Line_4:
// EXTI4_IRQHandler();
// break;
// default:
// break;
// }
// EXTI_ClearITPendingBit((EXTI_LineTypeDef)(Exti_irq_index/EXIT_Pin_Num),(EXTI_PIN_TypeDef)(BIT(Exti_irq_index%EXIT_Pin_Num)));
// }
// NVIC_EnableIRQ(GPIO_IRQn);
//}
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_exit.h
* @brief source file for setting exit
*
* Change Logs:
* Date Author Version Notes
* 2021-12-24 yangzhengfeng V1.0.0 Modify the register module configuration
* 2021-01-03 wangjingfan V1.0.1 Compile error correction
*/
#ifndef __YC_EXTI_H__
#define __YC_EXTI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "yc3122.h"
#include "yc_gpio.h"
/**
* @brief EXTI Trigger enumeration
*/
typedef enum
{
EXTI_Trigger_Off = 0,
EXTI_Trigger_HighLev = 1,
EXTI_Trigger_LowLev = 2,
EXTI_Trigger_Rising = 3,
EXTI_Trigger_Falling = 4,
EXTI_Trigger_Rising_Falling = 5,
EXTI_Trigger_DEFAULT_VAL = 0xff
} EXTI_TriggerTypeDef;
#define IS_TRIG_TYPEDEF(TRIGTYPE) ((TRIGTYPE) == EXTI_Trigger_Off || \
(TRIGTYPE) == EXTI_Trigger_HighLev || \
(TRIGTYPE) == EXTI_Trigger_LowLev || \
(TRIGTYPE) == EXTI_Trigger_Rising || \
(TRIGTYPE) == EXTI_Trigger_Falling || \
(TRIGTYPE) == EXTI_Trigger_Rising_Falling)
/**
* @brief EXTI Trigger source
*/
typedef enum
{
EXTI_Line_0 = 0,
EXTI_Line_1 = 1,
EXTI_Line_2 = 2,
EXTI_Line_3 = 3,
EXTI_Line_4 = 4,
EXTI_Line_DEFAULT_VAL = 0xff
} EXTI_LineTypeDef;
#define IS_EXTI_LINE(LINE) (((LINE) == EXTI_Line_0) || \
((LINE) == EXTI_Line_1) || \
((LINE) == EXTI_Line_2) || \
((LINE) == EXTI_Line_3) || \
((LINE) == EXTI_Line_4))
#define IS_EXTI_PIN_SOURCE(PIN) (((((PIN) & ~(uint16_t)0xFFFF)) == 0x00) && ((PIN) != (uint16_t)0x00))
#define EXTI_MODE_TypeDef GPIO_MODULE_TypeDef
#define EXTI_PIN_TypeDef GPIO_Pin_TypeDef
#define EXIT_Num GPIO_PORT_NUM
#define EXIT_Pin_Num GPIO_PIN_NUM
void EXTI_ClearITPendingBit(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource);
void EXTI_DeInit(void);
uint16_t EXTI_GetITLineStatus(EXTI_LineTypeDef EXTI_Line);
uint16_t EXTI_GetITEXTI_PinSourceStatus(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource);
void EXTI_LineConfig(EXTI_LineTypeDef EXTI_Line, EXTI_PIN_TypeDef EXTI_PinSource, EXTI_TriggerTypeDef EXTI_Trigger);
#ifdef __cplusplus
}
#endif
#endif /* __YC_EXTI_H__ */
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_gpio.c
* @brief source file for setting gpio
*
* Change Logs:
* Date Author Version Notes
* 2021-01-20 yangzhengfeng V1.0.2 Update library function
* 2021-07-29 xubo V1.0.3 Update library function
*/
#include "yc_gpio.h"
uint8_t const UnMapTb[256] = {
0u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x00 to 0x0F */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x10 to 0x1F */
5u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x20 to 0x2F */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x30 to 0x3F */
6u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x40 to 0x4F */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x50 to 0x5F */
5u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x60 to 0x6F */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x70 to 0x7F */
7u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x80 to 0x8F */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0x90 to 0x9F */
5u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xA0 to 0xAF */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xB0 to 0xBF */
6u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xC0 to 0xCF */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xD0 to 0xDF */
5u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, /* 0xE0 to 0xEF */
4u, 0u, 1u, 0u, 2u, 0u, 1u, 0u, 3u, 0u, 1u, 0u, 2u, 0u, 1u, 0u /* 0xF0 to 0xFF */
};
uint8_t UnMap(uint16_t x)
{
uint8_t lx = x;
uint8_t hx = x >> 8;
if(lx)
{
return UnMapTb[lx];
}
else
{
return UnMapTb[hx] + 8;
}
}
/**
* @method GPIO_Config
* @brief config gpio function(Only one can be configured at a time)
* @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)(Only one can be configured at a time)
* @param function:gpio function
* @retval none
*/
void GPIO_Config(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_FUN_TYPEDEF function)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
_ASSERT(IS_GPIO_FUN(function));
MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, GPIO_Pin)] = function;
}
/**
* @method GPIO_Init
* @brief gpio mode Init
* @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group.
* @param GPIO_InitStruct:GPIO_InitStruct
* @retval none
*/
void GPIO_Init(GPIO_TypeDef GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
_ASSERT(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
for(uint8_t i = 0; i < GPIO_PIN_NUM; i++)
{
if(GPIO_InitStruct->GPIO_Pin & (BIT0<<i))
{
MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, (BIT0<<i))] = GPIO_InitStruct->GPIO_Mode << 6;
}
}
}
/**
* @method GPIO_PullUpCmd
* @brief gpio pull up
* @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_7)
* @param NewState: new state of the port pin Pull Up.(ENABLE or DISABLE)
* @retval none
*/
void GPIO_PullUpCmd(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN(GPIO_Pin));
_ASSERT(IS_FUNCTIONAL_STATE(NewState));
uint8_t i = 0;
if (ENABLE == NewState)
{
for(i = 0; i<GPIO_PIN_NUM; i++)
{
MGPIO->CTRL.bit[GPIO_GetNum(GPIOx,(GPIO_Pin_TypeDef)(BIT0 << i))].MODE = GPIO_Mode_IPU;
}
}
else if (DISABLE == NewState)
{
for(i = 0; i<GPIO_PIN_NUM; i++)
{
MGPIO->CTRL.bit[GPIO_GetNum(GPIOx, (GPIO_Pin_TypeDef)(BIT0 << i))].MODE = GPIO_Mode_IN_FLOATING;
}
}
}
/**
* @method GPIO_ReadInputData
* @brief Reads the GPIO input data for 2byte.
* @param GPIOx_IN: where x can be (GPIOA_IN...GPIOF_IN) to select the GPIO group.
* @retval GPIO input data.
*/
uint16_t GPIO_ReadInputData(GPIO_TypeDef GPIOx)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
return MGPIO->IN_LEVEL.reg[GPIOx];
}
/**
* @method GPIO_ReadInputDataBit
* @brief Reads the GPIO input data(status) for bit.
* @param GPIOx_IN: where x can be (GPIOA_IN...GPIOF_IN) to select the GPIO group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
* @retval The input bit
*/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
if (((MGPIO->IN_LEVEL.reg[GPIOx]) & GPIO_Pin) != (uint32_t)Bit_RESET)
{
return (uint8_t)Bit_SET;
}
return (uint8_t)Bit_RESET;
}
/**
* @method GPIO_ReadOutputData
* @brief Reads the GPIO output data(status) for byte.
* @param GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
* @retval GPIO output data(status).
*/
uint16_t GPIO_ReadOutputData(GPIO_TypeDef GPIOx)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
return MGPIO->IN_LEVEL.reg[GPIOx];
}
/**
* @method GPIO_ReadOutputDataBit
* @brief Reads the GPIO output data(status) for bit.
* @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
* @retval The output status
*/
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
if (((MGPIO->IN_LEVEL.reg[GPIOx]) & GPIO_Pin) != (uint32_t)Bit_RESET)
{
return (uint8_t)Bit_SET;
}
return (uint8_t)Bit_RESET;
}
/**
* @method GPIO_ResetBit
* @brief Reset the GPIO bit data(status) for bit.
* @param GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
* @param GPIO_Pin: select the pin to reset.(GPIO_Pin_0...GPIO_Pin_15)
* @retval none
*/
void GPIO_ResetBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, GPIO_Pin)] = OUTPUT_LOW;
}
/**
* @method GPIO_ResetBits
* @brief Reset the GPIO bit data(status) for bit.
* @param GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
* @param GPIO_Pin: select the pin to reset.(GPIO_Pin_0...GPIO_Pin_15)
* @retval none
*/
void GPIO_ResetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN(GPIO_Pin));
for(uint8_t i = 0; i < GPIO_PIN_NUM; i++)
{
if(GPIO_Pin & (BIT0<<i))
{
MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, (BIT0<<i))] = OUTPUT_LOW;
}
}
}
/**
* @method GPIO_SetBit
* @brief Set the GPIO bit data(status) for bit.
* @param GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
* @retval none
*/
void GPIO_SetBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, GPIO_Pin)] = OUTPUT_HIGH;
}
/**
* @method GPIO_SetBits
* @brief Set the GPIO bit data(status) for bit.
* @param GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
* @retval none
*/
void GPIO_SetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN(GPIO_Pin));
for(uint8_t i = 0; i < GPIO_PIN_NUM; i++)
{
if(GPIO_Pin & (BIT0<<i))
{
MGPIO->CTRL.reg[GPIO_GetNum(GPIOx, (BIT0<<i))] = OUTPUT_HIGH;
}
}
}
/**
* @method GPIO_Write
* @brief Write the GPIO group data(status) for bit.
* @param GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
* @param value: select the value to read.(0 or 1)
* @retval none
*/
void GPIO_Write(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN(GPIO_Pin));
GPIO_SetBits(GPIOx, GPIO_Pin);
GPIO_ResetBits(GPIOx, (GPIO_Pin_TypeDef)(~GPIO_Pin));
}
/**
* @method GPIO_WriteBit
* @brief Write the GPIO bit data(status) for bit.
* @param GPIOx: where x can be (GPIOA...GPIOE) to select the GPIO group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
* @param BitVal: select the value to read.(0 or 1)
* @retval none
*/
void GPIO_WriteBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction BitVal)
{
_ASSERT(IS_GPIO_PORT(GPIOx));
_ASSERT(IS_GPIO_PIN_SINGLE(GPIO_Pin));
if (BitVal == Bit_SET)
GPIO_SetBit(GPIOx, GPIO_Pin);
else if (BitVal == Bit_RESET)
GPIO_ResetBit(GPIOx, GPIO_Pin);
}
/**
* @method GPIO_ODSet
* @brief Set the GPIO OD MODE
* @param GPIOx_Drv: where x can be (GPIOA_Drv...GPIOE_Drv) to select the GPIO_Drv group.
* @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)
* @param Drvtype: select the value to set DRV value.(0x00....0x11)
* @retval none
*/
void GPIO_ODSet(GPIO_OD_TypeDef GPIOx_OD, GPIO_ODTypeDef GPIO_OD_Set)
{
_ASSERT(IS_GPIO_OD(GPIOx_OD));
_ASSERT(IS_GPIO_MODE_OUT(GPIO_OD_Set));
(MGPIO->OD_CTRL.reg) |= (GPIO_OD_Set << GPIOx_OD);
}
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_gpio.h
* @brief source file for setting gpio
*
* Change Logs:
* Date Author Version Notes
* 2020-12-23 yangzhengfeng V1.1.0 Modify the register module configuration
*/
#ifndef __YC_GPIO_H__
#define __YC_GPIO_H__
#include "yc3122.h"
#include "system.h"
#ifdef __cplusplus
extern "C" {
#endif
uint8_t UnMap(uint16_t x);
#define GPIO_CONFIG(x) *((volatile uint8_t*)(MGPIO_BASE + x))
#define GPIO_GetNum(port, pin) ((port * GPIO_PIN_NUM) + UnMap(pin))
#define GPIO_OD_TypeDef uint8_t
#define GPIO_FUN_TYPEDEF uint8_t
#define GPIO_PORT_NUM 5
#define GPIO_PIN_NUM 16
#define GPIO_OD_PORTA_10 ((GPIO_OD_TypeDef)0x00) /*!< Pin 10 selected */
#define GPIO_OD_PORTB_06 ((GPIO_OD_TypeDef)0x01) /*!< Pin 20 selected */
#define GPIO_OD_PORTC_01 ((GPIO_OD_TypeDef)0x02) /*!< Pin 33 selected */
#define GPIO_OD_PORTC_08 ((GPIO_OD_TypeDef)0x03) /*!< Pin 40 selected */
#define GPIO_OD_PORTD_00 ((GPIO_OD_TypeDef)0x04) /*!< Pin 48 selected */
#define GPIO_OD_PORTD_12 ((GPIO_OD_TypeDef)0x05) /*!< Pin 60 selected */
#define GPIO_OD_PORTE_06 ((GPIO_OD_TypeDef)0x06) /*!< Pin 76 selected */
#define GPIO_OD_PORTE_12 ((GPIO_OD_TypeDef)0x07) /*!< Pin 70 selected */
#define IS_GPIO_OD(port_od) ((port_od == GPIO_OD_PORTA_10) || \
(port_od == GPIO_OD_PORTB_06) || \
(port_od == GPIO_OD_PORTC_01) || \
(port_od == GPIO_OD_PORTC_08) || \
(port_od == GPIO_OD_PORTD_00) || \
(port_od == GPIO_OD_PORTD_12) || \
(port_od == GPIO_OD_PORTE_06) || \
(port_od == GPIO_OD_PORTE_12))
typedef enum
{
GPIO_Pin_0 = BIT0,
GPIO_Pin_1 = BIT1,
GPIO_Pin_2 = BIT2,
GPIO_Pin_3 = BIT3,
GPIO_Pin_4 = BIT4,
GPIO_Pin_5 = BIT5,
GPIO_Pin_6 = BIT6,
GPIO_Pin_7 = BIT7,
GPIO_Pin_8 = BIT8,
GPIO_Pin_9 = BIT9,
GPIO_Pin_10 = BIT10,
GPIO_Pin_11 = BIT11,
GPIO_Pin_12 = BIT12,
GPIO_Pin_13 = BIT13,
GPIO_Pin_14 = BIT14,
GPIO_Pin_15 = BIT15
} GPIO_Pin_TypeDef;
#define IS_GPIO_PIN(PIN) (((((PIN) & ~(uint16_t)0xFFFF)) == 0x00) && ((PIN) != (uint16_t)0x00))
#define IS_GPIO_PIN_SINGLE(PIN) ((PIN == GPIO_Pin_0) || \
(PIN == GPIO_Pin_1) || \
(PIN == GPIO_Pin_2) || \
(PIN == GPIO_Pin_3) || \
(PIN == GPIO_Pin_4) || \
(PIN == GPIO_Pin_5) || \
(PIN == GPIO_Pin_6) || \
(PIN == GPIO_Pin_7) || \
(PIN == GPIO_Pin_8) || \
(PIN == GPIO_Pin_9) || \
(PIN == GPIO_Pin_10) || \
(PIN == GPIO_Pin_11) || \
(PIN == GPIO_Pin_12) || \
(PIN == GPIO_Pin_13) || \
(PIN == GPIO_Pin_14) || \
(PIN == GPIO_Pin_15))
typedef enum
{
GPIOA = 0,
GPIOB,
GPIOC,
GPIOD,
GPIOE
} GPIO_TypeDef;
#define IS_GPIO_PORT(port) (port <= GPIOE)
/******************* Bit definition for gpio funaction **********************/
#define INPUT ((GPIO_FUN_TYPEDEF) 0)
#define QSPI_NCS ((GPIO_FUN_TYPEDEF) 2) /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
#define QSPI_SCK ((GPIO_FUN_TYPEDEF) 3) /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
#define QSPI_IO0 ((GPIO_FUN_TYPEDEF) 4) /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
#define QSPI_IO1 ((GPIO_FUN_TYPEDEF) 5) /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
#define QSPI_IO2 ((GPIO_FUN_TYPEDEF) 6) /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
#define QSPI_IO3 ((GPIO_FUN_TYPEDEF) 7) /*Mapping the scope GPIO[32:0] and GPIO[76:56]*/
#define UART0_TXD ((GPIO_FUN_TYPEDEF) 8)
#define UART0_RXD ((GPIO_FUN_TYPEDEF) 9)
#define UART0_RTS ((GPIO_FUN_TYPEDEF)10)
#define UART0_CTS ((GPIO_FUN_TYPEDEF)11)
#define UART1_TXD ((GPIO_FUN_TYPEDEF)12) /*Mapping the scope GPIO[47:0]*/
#define UART1_RXD ((GPIO_FUN_TYPEDEF)13) /*Mapping the scope GPIO[47:0]*/
#define UART1_RTS ((GPIO_FUN_TYPEDEF)14) /*Mapping the scope GPIO[47:0]*/
#define UART1_CTS ((GPIO_FUN_TYPEDEF)15) /*Mapping the scope GPIO[47:0]*/
#define UART2_TXD ((GPIO_FUN_TYPEDEF)36) /*Mapping the scope GPIO[79:40]*/
#define UART2_RXD ((GPIO_FUN_TYPEDEF)37) /*Mapping the scope GPIO[79:40]*/
#define UART2_RTS ((GPIO_FUN_TYPEDEF)38) /*Mapping the scope GPIO[79:40]*/
#define UART2_CTS ((GPIO_FUN_TYPEDEF)39) /*Mapping the scope GPIO[79:40]*/
#define UART3_TXD ((GPIO_FUN_TYPEDEF)53) /*Each group of 4 GPIOs is mapped to CTS/TXD/RXD/RTS,mapping the scope GPIO[60:20]*/
#define UART3_RXD ((GPIO_FUN_TYPEDEF)53) /*Each group of 4 GPIOs is mapped to CTS/TXD/RXD/RTS,mapping the scope GPIO[60:20]*/
#define UART3_RTS ((GPIO_FUN_TYPEDEF)53) /*Each group of 4 GPIOs is mapped to CTS/TXD/RXD/RTS,mapping the scope GPIO[60:20]*/
#define UART3_CTS ((GPIO_FUN_TYPEDEF)53) /*Each group of 4 GPIOs is mapped to CTS/TXD/RXD/RTS,mapping the scope GPIO[60:20]*/
#define PWM_OUT ((GPIO_FUN_TYPEDEF)16) /*Each group of 8 GPIOs is mapped to PWM0~7*/
#define PWM_OUT8 ((GPIO_FUN_TYPEDEF)17) /*Mapping the scope GPIO[79:48]*/
#define PWM_OUT01 ((GPIO_FUN_TYPEDEF)40) /*GPIO_INDEX%8 is not a 0 and 1 pin, each two is a group, respectively mapped to PWM0/PWM1*/
#define PWM_OUT23 ((GPIO_FUN_TYPEDEF)41) /*GPIO_INDEX%8 is not a 2 and 3 pin, each two is a group, respectively mapped to PWM2/PWM3*/
#define DCMI_PCLK ((GPIO_FUN_TYPEDEF)18)
#define DCMI_VSYNC ((GPIO_FUN_TYPEDEF)19)
#define DCMI_HSYNC ((GPIO_FUN_TYPEDEF)20)
#define DCMI_D0 ((GPIO_FUN_TYPEDEF)21)
#define DCMI_D1 ((GPIO_FUN_TYPEDEF)22)
#define DCMI_D0_D13 ((GPIO_FUN_TYPEDEF)23) /*GPIO[7] to GPIO[76] is a group of 14, which are mapped to D13 to D0 respectively*/
#define SPID_SDIO ((GPIO_FUN_TYPEDEF)27) /*Every 3 GPIOs are a group, which are respectively mapped to SPI0_SDIO/SPI1_SDIO/SPI2_SDIO*/
#define SPID0_NCS ((GPIO_FUN_TYPEDEF)24) /*Mapping the scope GPIO[79:0]*/
#define SPID0_SCK ((GPIO_FUN_TYPEDEF)25) /*Mapping the scope GPIO[79:0]*/
#define SPID0_MOSI ((GPIO_FUN_TYPEDEF)26) /*Mapping the scope GPIO[79:0]*/
#define SPID0_MISO ((GPIO_FUN_TYPEDEF)28) /*Mapping the scope GPIO[79:0]*/
#define SPID1_NCS ((GPIO_FUN_TYPEDEF)48) /*Mapping the scope GPIO[79:0]*/
#define SPID1_SCK ((GPIO_FUN_TYPEDEF)49) /*Mapping the scope GPIO[79:0]*/
#define SPID1_MOSI ((GPIO_FUN_TYPEDEF)50) /*Mapping the scope GPIO[79:0]*/
#define SPID1_MISO ((GPIO_FUN_TYPEDEF)52) /*Mapping the scope GPIO[79:0]*/
#define SPID_SLV_IN ((GPIO_FUN_TYPEDEF)29) /*Each of 6 GPIOs is a group, which are mapped to MSPI0~2 NCS_IN/SCK_IN respectively*/
#define XTAL32K ((GPIO_FUN_TYPEDEF)30) /*Mapping the scope GPIO[15:0] and [74:48]*/
#define HSPI_NCS ((GPIO_FUN_TYPEDEF)31) /*Map to all pins*/
#define HSPI_SCK ((GPIO_FUN_TYPEDEF)32) /*Map to all pins*/
#define HSPI_MOSI ((GPIO_FUN_TYPEDEF)33) /*Map to all pins*/
#define HSPI_MISO ((GPIO_FUN_TYPEDEF)34) /*Map to all pins*/
#define DAC_OUT ((GPIO_FUN_TYPEDEF)35) /*Each group of 2 GPIOs is mapped to Out P/Out N respectively*/
#define SDIO ((GPIO_FUN_TYPEDEF)42) /*Each of 6 GPIOs is a group mapped to SDIO_CLK/SDIO_CMD/DAT0/DAT1/DAT2/DAT3*/
#define PSRAM_NCS ((GPIO_FUN_TYPEDEF)43)
#define PSRAM_SCK ((GPIO_FUN_TYPEDEF)44)
#define PSRAM_DATA_0 ((GPIO_FUN_TYPEDEF)45) /*Each group of 4 GPIOs is mapped to D0/D1/D2/D3 respectively*/
#define PSRAM_DATA_1 ((GPIO_FUN_TYPEDEF)45) /*Each group of 4 GPIOs is mapped to D0/D1/D2/D3 respectively*/
#define PSRAM_DATA_2 ((GPIO_FUN_TYPEDEF)45) /*Each group of 4 GPIOs is mapped to D0/D1/D2/D3 respectively*/
#define PSRAM_DATA_3 ((GPIO_FUN_TYPEDEF)45) /*Each group of 4 GPIOs is mapped to D0/D1/D2/D3 respectively*/
#define JTAG_RV_TCK ((GPIO_FUN_TYPEDEF)46) /*Each group of 4 GPIOs is mapped to TCK/TMS/TDI/TDO*/
#define JTAG_RV_TMS ((GPIO_FUN_TYPEDEF)46) /*Each group of 4 GPIOs is mapped to TCK/TMS/TDI/TDO*/
#define JTAG_RV_TDI ((GPIO_FUN_TYPEDEF)46) /*Each group of 4 GPIOs is mapped to TCK/TMS/TDI/TDO*/
#define JTAG_RV_TDO ((GPIO_FUN_TYPEDEF)46) /*Each group of 4 GPIOs is mapped to TCK/TMS/TDI/TDO*/
#define I2C0_SCL ((GPIO_FUN_TYPEDEF)58)
#define I2C0_SDA ((GPIO_FUN_TYPEDEF)59)
#define I2C1_SCL ((GPIO_FUN_TYPEDEF)47)
#define I2C1_SDA ((GPIO_FUN_TYPEDEF)47)
#define SCI7816_IO ((GPIO_FUN_TYPEDEF)56)
#define SCI7816_IO2 ((GPIO_FUN_TYPEDEF)51)
#define NFC_CLK_OUT ((GPIO_FUN_TYPEDEF)55)
#define ICE ((GPIO_FUN_TYPEDEF)57)
#define JTAG_SWCLK ((GPIO_FUN_TYPEDEF)60) /*The first 16 pins are mapped to SWCLK, and the latter pins are mapped to SWCLK/SWDIO for a group of 2 GPIOs*/
#define JTAG_SWDIO ((GPIO_FUN_TYPEDEF)61) /*The first 16 pins are mapped to SWDIO*/
#define OUTPUT_LOW ((GPIO_FUN_TYPEDEF)62)
#define OUTPUT_HIGH ((GPIO_FUN_TYPEDEF)63)
#define PULL_PU ((GPIO_FUN_TYPEDEF)64)
#define PULL_PD ((GPIO_FUN_TYPEDEF)128)
#define ANALOG ((GPIO_FUN_TYPEDEF)192)
#define IS_GPIO_FUN(fun) (fun <= 0xff)
#define IS_GPIO_MODE(mode) (((mode) == GPIO_Mode_IN_FLOATING) || \
((mode) == GPIO_Mode_IPU) || \
((mode) == GPIO_Mode_IPD) || \
((mode) == GPIO_Mode_AIN) || \
((mode) == GPIO_Mode_Out_PP))
/**
* @brief Bit_SET and Bit_RESET enumeration
*/
typedef enum
{
Bit_RESET = 0,
Bit_SET = 1
} BitAction;
/**
* @brief Configuration Mode enumeration
*/
typedef enum
{
GPIO_Mode_IN_FLOATING = 0x00,
GPIO_Mode_IPU = 0x01,
GPIO_Mode_IPD = 0x02,
GPIO_Mode_AIN = 0x03,
GPIO_Mode_Out_PP = 0x3E /*!< analog signal mode */
} GPIO_ModeTypeDef;
/**
* @brief Configuration GPIO OD enumeration
*/
typedef enum
{
GPIO_Mode_OD_RESET = 0x0,
GPIO_Mode_OD_SET = 0x1
} GPIO_ODTypeDef;
#define IS_GPIO_MODE_OUT(mode) (((mode) == GPIO_Mode_OD_RESET) || \
((mode) == GPIO_Mode_OD_SET))
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
GPIO_Pin_TypeDef GPIO_Pin;
GPIO_ModeTypeDef GPIO_Mode;
} GPIO_InitTypeDef;
uint32_t GPIO_GetGPIONum(GPIO_TypeDef GPIOx);
void GPIO_Config(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_FUN_TYPEDEF function);
void GPIO_Init(GPIO_TypeDef GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_PullUpCmd(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState);
uint16_t GPIO_ReadInputData(GPIO_TypeDef GPIOx);
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
void GPIO_ResetBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin);
void GPIO_SetBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
void GPIO_SetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin);
void GPIO_Write(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction BitVal);
void GPIO_ODSet(uint8_t GPIOx_OD, GPIO_ODTypeDef GPIO_OD_Set);
#ifdef __cplusplus
}
#endif
#endif /* __YC_GPIO_H__ */
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_qspi.h
* @brief This file contains all the functions prototypes for the IFlash library.
*
* Change Logs:
* Date Author Version Notes
* 2021-08-14 wushengyan V1.0.0 the first version
*/
#ifndef __YC_QSPI_H__
#define __YC_QSPI_H__
#include "yc3122.h"
#define BOOT_UART_DOWNLOAD_FLAG 0x5a5aa5a5
#define BOOT_USB_DOWNLOAD_FLAG 0xaa5555aa
#define BOOT_AUTO_SELECT_FLAG 0xffffffff
#define ENC_BULK_BUF_SIZE 0x9000
typedef enum {
YC_QFLASH_SIZE_UNKNOW = 0,
YC_QFLASH_SIZE_512KB = 1,
YC_QFLASH_SIZE_1MB = 2,
YC_QFLASH_SIZE_4MB = 3,
} yc_qspi_flash_size_enum;
typedef struct
{
uint16_t is_end;
uint16_t enc_index;
uint8_t enc_buf[ENC_BULK_BUF_SIZE];
} ENC_BulkTypeDef;
/**
* @method qspi_flash_pageerase
* @brief page erase (256byte)
* @param flash_addr
* @retval ERROR,SUCCESS
*/
uint8_t qspi_flash_pageerase(uint32_t flash_addr);
/**
* @method qspi_flash_sectorerase
* @brief sector erase (4K)
* @param flash_addr:flash addr (4k Bytes align)
* @retval ERROR,SUCCESS
*/
uint8_t qspi_flash_sectorerase(uint32_t flash_addr);
/**
* @method qspi_flash_blockerase32k
* @brief block erase (32K)
* @param flash_addr:flash addr (32k Bytes align)
* @retval ERROR,SUCCESS
*/
uint8_t qspi_flash_blockerase32k(uint32_t flash_addr);
/**
* @method qspi_flash_blockerase64k
* @brief block erase (64K)
* @param flash_addr:flash addr (64k Bytes align)
* @retval ERROR,SUCCESS
*/
uint8_t qspi_flash_blockerase64k(uint32_t flash_addr);
/**
* @method qspi_flash_write
* @brief write flash
* @param flash_addr:flash addr (when flash_addr%256!=0,256-(flash_addr%256)+len must less than 256)
* @param buf
* @param len
* @retval ERROR,SUCCESS
*/
uint8_t qspi_flash_write(uint32_t flash_addr, uint8_t *buf, uint32_t len);
/**
* @method qspi_flash_read
* @brief read flash
* @param flash_addr:flash addr
* @param buf
* @param len
* @retval ERROR,SUCCESS
*/
uint8_t qspi_flash_read(uint32_t flash_addr, uint8_t *buf, uint32_t len);
/**
* @method flash_blank_check
* @brief check logical addr data is blank
* @param startaddr:cpu addr
* @param len
* @retval TRUE: blank
* FALSE: not blank
*/
Boolean flash_blank_check(uint32_t startaddr, uint32_t len);
/**
* @method enc_write_flash
* @brief write data to flash with enc
* @param flash_addr:cpu addr (must 32 Bytes align)
* @param buf
* @param len:(must 32 Bytes align)
* @retval ERROR,SUCCESS
*/
uint8_t enc_write_flash(uint32_t flash_addr, uint8_t *buf, uint32_t len);
/**
* @method enc_read_flash
* @brief read flash data with enc
* @param flash_addr:cpu addr
* @param buf
* @param len
* @retval ERROR,SUCCESS
*/
uint8_t enc_read_flash(uint32_t flash_addr, uint8_t *buf, uint32_t len);
/**
* @method enc_read_flash_fast
* @brief enc read flash fast(You must sure that the read area is written by enc)
* @param flash_addr:cpu addr
* @param buf
* @param len
* @return SUCCESS or ERROR
*/
uint8_t enc_read_flash_fast(uint32_t flash_addr, uint8_t *buf, uint32_t len);
/**
* @method enc_erase_flash_32byte
* @brief erase 32 Bytes
* @param flash_addr : cpu addr (must 32 Bytes align)
* @retval ERROR,SUCCESS
*/
uint8_t enc_erase_flash_32byte(uint32_t flash_addr);
/**
* @method enc_erase_flash_32k
* @brief enc erase 32K Bytes
* @param flash_addr : cpu addr (must 32K Bytes align)
* @retval ERROR,SUCCESS
*/
uint8_t enc_erase_flash_32k(uint32_t flash_addr);
/**
* @brief enc erase flash app area
* @param addr:align at 32k for CPU addr
* @param len:erase len
* @return ERROR,SUCCESS
*/
uint8_t enc_earse_flash_app_area(uint32_t addr,uint32_t len);
/**
* @brief enc write download flag
* @param addr:BOOT_UART_DOWNLOAD_FLAG,BOOT_USB_DOWNLOAD_FLAG or BOOT_AUTO_SELECT_FLAG
* @return ERROR,SUCCESS
*/
uint8_t enc_write_download_flag(uint32_t flag);
/**
* @method enc_write_flash_bulk
* @brief write bulk data to flash with enc
* @param EncBulkStruct:enc buf struct
* @param flash_addr:cpu addr(start addr must 32k Bytes align)
* @param buf
* @param len: Integer multiple of 32 bytes
* @retval ERROR,SUCCESS
*/
uint8_t enc_write_flash_bulk(ENC_BulkTypeDef *EncBulkStruct,uint32_t flash_addr, uint8_t *buf, uint32_t len);
/**
* @method prefetch
* @brief fetch code to cache
* @param start_addr: code start addr
* @param end_addr : code end addr
* @retval NULL
*/
void prefetch(void *start_addr, void *end_addr);
/**
* @method read_flash_size
* @brief read the chip flash size
* @param NULL
* @retval yc_qspi_flash_size_enum
*/
yc_qspi_flash_size_enum read_flash_size(void);
/**
* @method qspi_GetVersion
* @brief get qspi lib version
* @param NULL
* @retval version
*/
uint32_t qspi_GetVersion(void);
#endif

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_uart.c
* @brief source file for setting uart
*
* Change Logs:
* Date Author Version Notes
* 2020-11-06 wushengyan V1.0.0 the first version
*/
#include "yc_uart.h"
#define uart_DMA_buf_len 1024
const UART_TypeDef * const UARTs[] = {MUART0, MUART1, MUART2, MUART3};
uint8_t uart0_DMA_buf[uart_DMA_buf_len] = {0};
uint8_t uart1_DMA_buf[uart_DMA_buf_len] = {0};
uint8_t uart2_DMA_buf[uart_DMA_buf_len] = {0};
uint8_t uart3_DMA_buf[uart_DMA_buf_len] = {0};
#define RX_ENABLE BIT0
#define UART_DMA_ENABLE BIT31
#define TX_INTR_ENABLE BIT31
#define Set_RxITNum_Mask 0xff00
#define Statu_RxNum_Mask (uint32_t)0xffff0000
/**
* @method UART_Buffer_Select
* @brief select UART buffer
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval NULL
*/
static uint8_t *UART_Buffer_Select(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
uint8_t *buffers[] = {uart0_DMA_buf, uart1_DMA_buf, uart2_DMA_buf, uart3_DMA_buf};
for (int i = 0; i < sizeof(UARTs) / sizeof(UARTs[0]); i++)
{
if ((void *)UARTs[i] == (void *)UARTx)
{
return buffers[i];
}
}
return NULL;
}
/**
* @method UART_DeInit
* @brief DeInit UART
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval None
*/
void UART_DeInit(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
UARTx->CTRL.reg = 0;
UARTx->RX_INT_LEN.reg = 0;
}
/**
* @method UART_Init
* @brief Initializes the UARTx peripheral according to
* the specified parameters.
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @param UART_InitStruct: pointer to a UART_InitTypeDef structure that
* contains the configuration information.
*/
void UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef *UART_InitStruct)
{
DMA_TypeDef *DMAx = NULL;
uint8_t *uartx_DMA_buf = NULL;
uint32_t temp_baudrate = 0;
_ASSERT(IS_UART(UARTx));
_ASSERT(IS_UART_RX_MODE(UART_InitStruct->RxMode));
_ASSERT(IS_UART_PARITY(UART_InitStruct->Parity));
_ASSERT(IS_UART_WORD_LENGTH(UART_InitStruct->DataBits));
_ASSERT(IS_UART_STOPBITS(UART_InitStruct->StopBits));
_ASSERT(IS_UART_FLOW_CTRL(UART_InitStruct->FlowCtrl));
_ASSERT(IS_UART_SMART_CARD(UART_InitStruct->SmartCard));
_ASSERT(IS_UART_COMM_MODE(UART_InitStruct->CommMode));
_ASSERT(IS_UART_BAUDRATE(UART_InitStruct->BaudRate));
DMAx = (DMA_TypeDef *)((uint32_t)UARTx - sizeof(DMA_TypeDef));
uartx_DMA_buf = UART_Buffer_Select(UARTx);
temp_baudrate = (48000000 / UART_InitStruct->BaudRate);
UART_DeInit(UARTx);
DMAx->DEST_ADDR.reg = (uint32_t)uartx_DMA_buf;
DMAx->LEN_LOW.bit.RX_LEN_L = uart_DMA_buf_len;
DMAx->CTRL.bit.LOOPBACK = 1;
DMAx->CTRL.bit.RESET = 1;
DMAx->CTRL.bit.RESET = 0;
UARTx->CTRL.bit.RX_EN = UART_InitStruct->RxMode;
UARTx->CTRL.bit.PARITY = UART_InitStruct->Parity;
UARTx->CTRL.bit.DATA_BITS = UART_InitStruct->DataBits;
UARTx->CTRL.bit.STOP_BITS = UART_InitStruct->StopBits;
UARTx->CTRL.bit.FLOW_CTRL = UART_InitStruct->FlowCtrl;
UARTx->CTRL.bit.SMART_CARD = UART_InitStruct->SmartCard;
UARTx->CTRL.bit.HDX_EN = UART_InitStruct->CommMode;
UARTx->CTRL.bit.RESET_BAUD = ENABLE;
UARTx->BAUD.bit.BAUD_RATE = temp_baudrate;
}
/**
* @method UART_StructInit
* @brief Fills each USART_InitStruct member with its default value.
* @param USART_InitStruct: pointer to a USART_InitTypeDef structure
* which will be initialized.
* @retval None
*/
void UART_StructInit(UART_InitTypeDef *UART_InitStruct)
{
UART_InitStruct->BaudRate = 9600;
UART_InitStruct->RxMode = MODE_RX_ENABLE;
UART_InitStruct->Parity = YC_PARITY_NONE;
UART_InitStruct->DataBits = DATABITS_8B;
UART_InitStruct->StopBits = STOPBITS_1;
UART_InitStruct->FlowCtrl = FLOWCTRL_NONE;
UART_InitStruct->SmartCard = SMARTCARD_DISABLE;
UART_InitStruct->CommMode = MODE_DUPLEX;
}
/**
* @method UART_ITConfig
* @brief Enable or disable the specified UART interrupt.
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @param UART_IT: specifies the UART interrupt sources
* This parameter can be one of the following values:
* @arg UART_IT_TX:interrupt trigger after send data completed.
* @arg UART_IT_RX:interrupt trigger when received data.
* @param NewState: new state of the specified UART interrupt
* This parameter can be ENABLE or DISABLE
*/
void UART_ITConfig(UART_TypeDef *UARTx, uint32_t UART_IT, FunctionalState NewState)
{
_ASSERT(IS_UART(UARTx));
_ASSERT(IS_UART_IT(UART_IT));
if (UART_IT == UART_IT_TX)
{
UARTx->BAUD.bit.TX_INT_EN = NewState;
}
else if (UART_IT == UART_IT_RX)
{
UARTx->RX_INT_LEN.bit.VAL = NewState;
}
}
/**
* @method UART_SendData
* @brief UART Send One Data
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval None
*/
void UART_SendData(UART_TypeDef *UARTx, uint8_t Data)
{
_ASSERT(IS_UART(UARTx));
volatile uint8_t buf[1];
buf[0] = Data;
DMA_TypeDef *DMAx = (DMA_TypeDef *)((uint32_t)UARTx - sizeof(DMA_TypeDef));
DMAx->SRC_ADDR.reg = (uint32_t)buf;
DMAx->LEN_LOW.bit.TX_LEN_L = 1;
DMAx->CTRL.bit.START = 1;
while (DMAx->STATUS.bit.DONE != 1);
}
/**
* @method UART_SendBuf
* @brief Transmits datas via UART DMA, the function will return after datas is sent.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @param buf: pointer to a buf that contains the data you want transmit.
* @param len: the buf length
* @retval None
*/
void UART_SendBuf(UART_TypeDef *UARTx, uint8_t *buf, uint32_t len)
{
_ASSERT(IS_UART(UARTx));
_ASSERT(NULL != buf);
_ASSERT(len < 0xfffff);
DMA_TypeDef *DMAx = (DMA_TypeDef *)((uint32_t)UARTx - sizeof(DMA_TypeDef));
DMAx->SRC_ADDR.reg = (uint32_t)buf;
DMAx->LEN_LOW.bit.TX_LEN_L = len & 0xffff;
DMAx->CTRL.bit.TX_LEN_H = len >> 16;
DMAx->CTRL.bit.START = 1;
while (DMAx->STATUS.bit.DONE != 1);
}
/**
* @method UART_ReceiveData
* @brief Receive single data through the USARTx peripheral.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval An one byte received data.
*/
uint8_t UART_ReceiveData(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
return UARTx->RX_DATA.bit.VAL;
}
/**
* @method UART_ReceiveBuf
* @brief Receives datas through the UART DMA.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @param buf: pointer to a buf that contains the data you want receive.
* @param len: the buf length, which size should be less than 20 bit (len < 0xfffff)
* @retval The length of received data before return.
*/
uint32_t UART_ReceiveBuf(UART_TypeDef *UARTx, uint8_t *buf, uint32_t len)
{
_ASSERT(IS_UART(UARTx));
_ASSERT(NULL != buf);
_ASSERT(len < 0xfffff);
uint32_t rcv_len = 0;
while ((UART_ReceiveDataLen(UARTx) > 0) && (rcv_len < len))
{
buf[rcv_len++] = UARTx->RX_DATA.bit.VAL;
}
return rcv_len;
}
/**
* @method UART_AutoFlowCtrlCmd
* @brief ENABLE or DISABLE UARTx auto flow control
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @param NewState: ENABLE or DISABLE auto flow control
* @retval None
*/
void UART_AutoFlowCtrlCmd(UART_TypeDef *UARTx, FunctionalState NewState)
{
_ASSERT(IS_UART(UARTx));
UARTx->CTRL.bit.FLOW_CTRL = NewState;
}
/**
* @method UART_GetITIdentity
* @brief Get IT Identity
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval IT Identity
*/
uint8_t UART_GetITIdentity(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
//return (0 || (UARTx->BAUD.bit.TX_INT_EN) || (UARTx->RX_INT_LEN.bit.VAL));
if((UARTx->RX_INT_LEN.reg > 0)&& (UARTx->STATUS.bit.RX_ITEMS_L >=UARTx->RX_INT_LEN.reg))
{
return UART_IT_RX;
}
else if(UARTx->BAUD.bit.TX_INT_EN)
{
return UART_IT_TX;
}
return 0;
}
/**
* @method UART_IsRXFIFOFull
* @brief Check if the Rx fifo is full or not.
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval TRUE: Rx fifo is full.
* FALSE: Rx fifo is not full
*/
Boolean UART_IsRXFIFOFull(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
return (Boolean)(UARTx->STATUS.bit.RX_FULL);
}
/**
* @method UART_IsRXFIFONotEmpty
* @brief Check if the Rx fifo is empty or not.
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval TRUE: Rx fifo is not empty.
* FALSE: Rx fifo is empty
*/
Boolean UART_IsRXFIFONotEmpty(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
return (Boolean)(!(UARTx->STATUS.bit.RX_EMPTY));
}
/**
* @method UART_IsBusy
* @brief Check if the UARTx is busy or not.
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval TRUE: UARTx is busy.
* FALSE: UARTx is not busy.
*/
Boolean UART_IsBusy(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
return (Boolean)(!(UARTx->STATUS.bit.RX_EMPTY));
}
/**
* @method UART_SetITTimeout
* @brief Sets the interruption time for serial port timeout.
* @param USARTx: Select the USART or the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @param timeout: 0x00~0xff
* @retval None
*/
void UART_SetITTimeout(UART_TypeDef *UARTx, uint16_t timeout)
{
_ASSERT(IS_UART(UARTx));
UARTx->TIMEOUT_INT.reg = timeout;
}
/**
* @method UART_SetRxITNum
* @brief Set the number of uart receive data intterupt trigger
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @param Bcnt: if the number of receive datas greater than Bcnt,interrupt trigger
* @retval None
*/
void UART_SetRxITNum(UART_TypeDef *UARTx, uint8_t Bcnt)
{
_ASSERT(IS_UART(UARTx));
UARTx->RX_INT_LEN.reg = Bcnt;
}
/**
* @method UART_ReceiveDataLen
* @brief Return the length of received data
* @param UARTx: Select the UART peripheral.
* This parameter can be one of the following values:
* MUART0, MUART1, MUART2 or MUART3.
* @retval Data len
*/
uint32_t UART_ReceiveDataLen(UART_TypeDef *UARTx)
{
_ASSERT(IS_UART(UARTx));
return (UARTx->STATUS.bit.RX_ITEMS_H << 16) + UARTx->STATUS.bit.RX_ITEMS_L;
}
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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/*
* Copyright (c); 2006-2020, YICHIP Development Team
* @file yc_uart.h
* @brief source file for setting uart
*
* Change Logs:
* Date Author Version Notes
* 2020-11-06 wushengyan V1.0.0 the first version
*/
#ifndef __YC_UART_H__
#define __YC_UART_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "yc3122.h"
#include "system.h"
/**
* @defgroup UARTx
*/
#define IS_UART(UARTx) (((UARTx) == MUART0) ||\
((UARTx) == MUART1) ||\
((UARTx) == MUART2) ||\
((UARTx) == MUART3))
/**
* @defgroup UART_RxMode
*/
#define MODE_RX_ENABLE 1
#define MODE_RX_DISABLE 0
#define IS_UART_RX_MODE(MODE) (((MODE) == MODE_RX_ENABLE) ||\
((MODE) == MODE_RX_DISABLE))
/**
* @defgroup USART_Parity
*/
#define YC_PARITY_NONE 0
#define YC_PARITY_EVEN 0
#define YC_PARITY_ODD 1
#define IS_UART_PARITY(PARITY) (((PARITY) == YC_PARITY_NONE) ||\
((PARITY) == YC_PARITY_EVEN) ||\
((PARITY) == YC_PARITY_ODD))
/**
* @defgroup UART_DataBits
*/
#define DATABITS_8B 0
#define DATABITS_9B 1
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == DATABITS_8B) || \
((LENGTH) == DATABITS_9B))
/**
* @defgroup UART_Stop_Bits
*/
#define STOPBITS_1 0
#define STOPBITS_2 1
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == STOPBITS_1) || \
((STOPBITS) == STOPBITS_2) )
/**
* @defgroup UART_Hardware_Flow_Control
*/
#define FLOWCTRL_NONE 0
#define FLOWCTRL_ENABLE 1
#define IS_UART_FLOW_CTRL(CTRL) (((CTRL) == FLOWCTRL_NONE) || \
((CTRL) == FLOWCTRL_ENABLE))
/**
* @defgroup UART_Smart_Card_Control
*/
#define SMARTCARD_ENABLE 1
#define SMARTCARD_DISABLE 0
#define IS_UART_SMART_CARD(CTRL) (((CTRL) == SMARTCARD_ENABLE) || \
((CTRL) == SMARTCARD_DISABLE))
/**
* @defgroup UART_CommMode
*/
#define MODE_SINGLE_LINE 1
#define MODE_DUPLEX 0
#define IS_UART_COMM_MODE(MODE) (((MODE) == MODE_SINGLE_LINE) ||\
((MODE) == MODE_DUPLEX))
/**
* @defgroup USART_BaudRate
*/
#define IS_UART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0x5B8) &&\
((BAUDRATE) < 0x0044AA21))
/**
* @defgroup UART_Interrupt_Type_definition
*/
#define UART_IT_TX 0x01
#define UART_IT_RX 0x02
#define IS_UART_IT(ITx) (((ITx) == UART_IT_TX) || ((ITx) == UART_IT_RX))
typedef struct
{
uint8_t RxMode; /*!< Specifies wether the Receive or Transmit mode
is enabled or disabled. This parameter can be
a value of @ref UART_Mode */
uint8_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of
@ref UART_Parity @note When parity is enabled,
the computed parity is inserted at
the MSB position of the transmitted data
(9th bit when the word length is set to
9 data bits; 8th bit when the word length is
set to 8 data bits);. */
uint8_t DataBits; /*!< Specifies the number of data bits transmitted
or received in a frame. This parameter can be
a value of @ref UART_DataBits */
uint8_t StopBits; /*!< Specifies the number of stop bits transmitted.
parameter can be a value of @ref UART_Stop_Bits */
uint8_t FlowCtrl; /*!< Specifies wether the hardware flow control mode
is enabled or disabled. This parameter can be
a value of @ref UART_Hardware_Flow_Control */
uint8_t SmartCard;
uint8_t CommMode;
uint32_t BaudRate; /*!< This member configures the USART
communication baud rate. */
} UART_InitTypeDef;
void UART_DeInit(UART_TypeDef *UARTx);
void UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef *UART_InitStruct);
void UART_StructInit(UART_InitTypeDef *UART_InitStruct);
void UART_ITConfig(UART_TypeDef *UARTx, uint32_t UART_IT, FunctionalState NewState);
void UART_SendData(UART_TypeDef *UARTx, uint8_t Data);
void UART_SendBuf(UART_TypeDef *UARTx, uint8_t *buf, uint32_t len);
uint8_t UART_ReceiveData(UART_TypeDef *UARTx);
uint32_t UART_ReceiveBuf(UART_TypeDef *UARTx, uint8_t *buf, uint32_t len);
void UART_AutoFlowCtrlCmd(UART_TypeDef *UARTx, FunctionalState NewState);
uint8_t UART_GetITIdentity(UART_TypeDef *UARTx);
Boolean UART_IsRXFIFOFull(UART_TypeDef *UARTx);
Boolean UART_IsRXFIFONotEmpty(UART_TypeDef *UARTx);
Boolean UART_IsBusy(UART_TypeDef *UARTx);
void UART_SetITTimeout(UART_TypeDef *UARTx, uint16_t timeout);
void UART_SetRxITNum(UART_TypeDef *UARTx, uint8_t Bcnt);
uint32_t UART_ReceiveDataLen(UART_TypeDef *UARTx);
#ifdef __cplusplus
}
#endif
#endif
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_wdt.c
* @brief This file provides all the WDT firmware functions.
*
* Change Logs:
* Date Author Version Notes
* 2021-01-04 yangzhengfeng V1.0.0 the first version
*/
#include "yc_wdt.h"
/**
* @brief Set WDT Clk Div
* @param Wdtclkdiv: Wdtclkdiv value equal 1 to 16
* @retval none
*/
void WDT_CLKDIV(uint32_t Wdtclkdiv)
{
_ASSERT(IS_WDT_CLKDI(Wdtclkdiv));
MWDT->CONFIG.bit.CLK_DIV = Wdtclkdiv;
}
/**
* @brief Set reload counter
* @param Reload: Reload counter equal to 2 to 31
* @retval none
*/
void WDT_SetReload(uint32_t Reload)
{
_ASSERT(IS_WDT_RELOAD(Reload));
MWDT->CONFIG.bit.RELOAD = Reload;
}
/**
* @brief Feed the watchdog function
* @param none
* @retval none
*/
void WDT_ReloadCounter(void)
{
MWDT->KICK.reg = COUNTER_RELOAD_KEY;
}
/**
* @brief Enable WDT
* @param none
* @retval none
*/
void WDT_Enable(void)
{
MWDT->CONFIG.bit.EN = ENABLE;
}
/**
* @brief Set WDT mode
* @param WDT_Mode : Select the following values :
* WDT_CPUReset
* WDT_Interrupt.
* @retval none
* @description If Select WDT_CPUReset Mode,the bit for WDT RESET will be set;if
* Select WDT_Interrupt the bit for WDT RESET will
*/
void WDT_ModeConfig(WDT_ModeTypeDef WDT_Mode)
{
_ASSERT(IS_WDT_MODE(WDT_Mode));
if(WDT_CPUReset == WDT_Mode)
{
MWDT->CONFIG.bit.MODE = WDT_CPUReset;
MRSTGEN->RST_EN.bit.WDT = ENABLE;
}
else if(WDT_Interrupt == WDT_Mode)
{
MWDT->CONFIG.bit.MODE = WDT_Interrupt;
MRSTGEN->RST_EN.bit.WDT = DISABLE;
}
}
/**
* @brief Get interrupt Status
* @param none
* @retval SET:interrupt ocuured.
*/
uint8_t WDT_GetITStatus(void)
{
uint16_t ret;
ret = MWDT->IRQ_STATUS.bit.STATE;
return ret ;
}
/**
* @brief Clear interrupt
* @param none
* @retval none
*/
void WDT_ClearITPendingBit(void)
{
MWDT->CLEAR.reg = 1;
}
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_wdt.h
* @brief This file provides all the WDT firmware functions.
*
* Change Logs:
* Date Author Version Notes
* 2021-01-04 yangzhengfeng V1.0.0 the first version
*/
#ifndef __YC_WDT_H__
#define __YC_WDT_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "yc3122.h"
#include "system.h"
typedef enum
{
WDT_CPUReset = 0,
WDT_Interrupt,
} WDT_ModeTypeDef;
#define WDTCLKDIV_1 0x00
#define WDTCLKDIV_2 0x01
#define WDTCLKDIV_3 0x02
#define WDTCLKDIV_4 0x03
#define WDTCLKDIV_5 0x04
#define WDTCLKDIV_6 0x05
#define WDTCLKDIV_7 0x06
#define WDTCLKDIV_8 0x07
#define WDTCLKDIV_9 0x08
#define WDTCLKDIV_10 0x09
#define WDTCLKDIV_11 0x0A
#define WDTCLKDIV_12 0x0B
#define WDTCLKDIV_13 0x0c
#define WDTCLKDIV_14 0x0D
#define WDTCLKDIV_15 0x0E
#define WDTCLKDIV_16 0x0F
/**************the value of feed dog************/
#define COUNTER_RELOAD_KEY 0x5937
#define ITSTATUS 0x01
#define IS_WDT_CLKDI(wdtclkdiv) (wdtclkdiv < 16)
#define IS_WDT_RELOAD(load) (load <= 0x1f)
#define IS_WDT_MODE(mode) ((mode == WDT_CPUReset) || (mode == WDT_Interrupt))
void WDT_CLKDIV(uint32_t Wdtclkdiv);
void WDT_SetReload(uint32_t Reload);
void WDT_ModeConfig(WDT_ModeTypeDef WDT_Mode);
void WDT_ClearITPendingBit(void);
void WDT_Enable(void);
void WDT_ReloadCounter(void);
uint8_t WDT_GetITStatus(void);
#ifdef __cplusplus
}
#endif
#endif /*__YC_WDT_H__*/
/************************ (C) COPYRIGHT Yichip Microelectronics *****END OF FILE****/

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file yc_startup_yc3122.s
* @brief source file for setting startup_yc3122
*
* Change Logs:
* Date Author Version Notes
* 2020-11-06 wushengyan V1.0.0 the first version
*/
#define REGBYTES (4)
/* Enable interrupts when returning from the handler */
#define MSTATUS_PRV1 0x1880
#define MSTATUS_MIE 0x00000008
#define MSTATUS_FS 0x00006000
.equ __stack_size,0x9000
.text
.globl flash_start
.globl delay
.globl __stack_size
.section .text.startup
flash_start:
la sp, _stack
/* set exception and irq mtvec */
la a0,trap
ori a0,a0,1
csrw mtvec,a0
/* enable fs */
li t0,MSTATUS_FS
csrs mstatus,t0
csrw fcsr,x0
/* Load data section */
la a0, _sidata
la a1, _sdata
la a2, _edata
bgeu a1,a2,2f
1:
lw t0, (a0)
sw t0, (a1)
addi a0,a0,4
addi a1,a1,4
bltu a1,a2,1b
2:
/* clear bss section */
la a0,_sbss
la a1,_ebss
bgeu a0,a1,2f
1:
sw zero,(a0)
addi a0,a0,4
bltu a0,a1,1b
2:
/*clear heap/statck*/
la a0,_ebss
la a1,_stack
bgeu a0,a1,2f
1:
sw zero,(a0)
addi a0,a0,4
bltu a0,a1,1b
2:
#ifndef __NO_SYSTEM_INIT
// jal systeminit
#endif
#ifndef __NO_BOARD_INIT
// jal board_init
#endif
li t0, 0x00000800
csrs 0x304,t0
li t0, MSTATUS_MIE
csrs mstatus, t0
jal main
/* never retch here*/
__exit:
j __exit
.macro DISABLE_MIE
csrc mstatus, MSTATUS_MIE
.endm
.macro ENABLE_MIE
csrs mstatus, MSTATUS_MIE
.endm
.macro GET_IRQ_NUM
li t1,0x000E4004
lw t1,0(t1)
li t3,0x01
li t5,0x00
get_irq_num_loop:
and t4, t1, t3
blt x0, t4, get_irq_num_end
addi t5, t5, 1
slli t3, t3, 1
j get_irq_num_loop
get_irq_num_end:
mv t1, t5
.endm
.macro SAVE_CONTEXT
addi sp,sp,-40*4
sw x1 , 0 *REGBYTES(sp) /* ra */
sw x4 , 1 *REGBYTES(sp) /* tp */
sw x5 , 2 *REGBYTES(sp) /* t0 */
sw x6 , 3 *REGBYTES(sp) /* t1 */
sw x7 , 4 *REGBYTES(sp) /* t2 */
sw x10, 5 *REGBYTES(sp) /* a0 */
sw x11, 6 *REGBYTES(sp) /* a1 */
sw x12, 7 *REGBYTES(sp) /* a2 */
sw x13, 8 *REGBYTES(sp) /* a3 */
sw x14, 9 *REGBYTES(sp) /* a4 */
sw x15, 10*REGBYTES(sp) /* a5 */
sw x16, 11*REGBYTES(sp) /* a6 */
sw x17, 12*REGBYTES(sp) /* a7 */
sw x28, 13*REGBYTES(sp) /* t3 */
sw x29, 14*REGBYTES(sp) /* t4 */
sw x30, 15*REGBYTES(sp) /* t5 */
sw x31, 16*REGBYTES(sp) /* t6 */
fsw f0, 17*REGBYTES(sp) /* ft0 */
fsw f1, 18*REGBYTES(sp) /* ft1 */
fsw f2, 19*REGBYTES(sp) /* ft2 */
fsw f3, 20*REGBYTES(sp) /* ft3 */
fsw f4, 21*REGBYTES(sp) /* ft4 */
fsw f5, 22*REGBYTES(sp) /* ft5 */
fsw f6, 23*REGBYTES(sp) /* ft6 */
fsw f7, 24*REGBYTES(sp) /* ft7 */
fsw f10,25*REGBYTES(sp) /* fa0 */
fsw f11,26*REGBYTES(sp) /* fa1 */
fsw f12,27*REGBYTES(sp) /* fa2 */
fsw f13,28*REGBYTES(sp) /* fa3 */
fsw f14,29*REGBYTES(sp) /* fa4 */
fsw f15,30*REGBYTES(sp) /* fa5 */
fsw f16,31*REGBYTES(sp) /* fa6 */
fsw f17,32*REGBYTES(sp) /* fa7 */
fsw f28,33*REGBYTES(sp) /* ft8 */
fsw f29,34*REGBYTES(sp) /* ft9 */
fsw f30,35*REGBYTES(sp) /* ft10*/
fsw f31,36*REGBYTES(sp) /* ft11*/
.endm
.macro RESTORE_CONTEXT
lw x1 , 0 *REGBYTES(sp) /* ra */
lw x4 , 1 *REGBYTES(sp) /* tp */
lw x5 , 2 *REGBYTES(sp) /* t0 */
lw x6 , 3 *REGBYTES(sp) /* t1 */
lw x7 , 4 *REGBYTES(sp) /* t2 */
lw x10, 5 *REGBYTES(sp) /* a0 */
lw x11, 6 *REGBYTES(sp) /* a1 */
lw x12, 7 *REGBYTES(sp) /* a2 */
lw x13, 8 *REGBYTES(sp) /* a3 */
lw x14, 9 *REGBYTES(sp) /* a4 */
lw x15, 10*REGBYTES(sp) /* a5 */
lw x16, 11*REGBYTES(sp) /* a6 */
lw x17, 12*REGBYTES(sp) /* a7 */
lw x28, 13*REGBYTES(sp) /* t3 */
lw x29, 14*REGBYTES(sp) /* t4 */
lw x30, 15*REGBYTES(sp) /* t5 */
lw x31, 16*REGBYTES(sp) /* t6 */
flw f0, 17*REGBYTES(sp) /* ft0 */
flw f1, 18*REGBYTES(sp) /* ft1 */
flw f2, 19*REGBYTES(sp) /* ft2 */
flw f3, 20*REGBYTES(sp) /* ft3 */
flw f4, 21*REGBYTES(sp) /* ft4 */
flw f5, 22*REGBYTES(sp) /* ft5 */
flw f6, 23*REGBYTES(sp) /* ft6 */
flw f7, 24*REGBYTES(sp) /* ft7 */
flw f10,25*REGBYTES(sp) /* fa0 */
flw f11,26*REGBYTES(sp) /* fa1 */
flw f12,27*REGBYTES(sp) /* fa2 */
flw f13,28*REGBYTES(sp) /* fa3 */
flw f14,29*REGBYTES(sp) /* fa4 */
flw f15,30*REGBYTES(sp) /* fa5 */
flw f16,31*REGBYTES(sp) /* fa6 */
flw f17,32*REGBYTES(sp) /* fa7 */
flw f28,33*REGBYTES(sp) /* ft8 */
flw f29,34*REGBYTES(sp) /* ft9 */
flw f30,35*REGBYTES(sp) /* ft10*/
flw f31,36*REGBYTES(sp) /* ft11*/
addi sp, sp, 40*REGBYTES
.endm
.macro SAVE_CSR_CONTEXT
csrr t0,mepc
csrr t1,mcause
sw t0,37*REGBYTES(sp) /* mepc */
sw t1,38*REGBYTES(sp) /* mcause */
.endm
.macro RESTORE_CSR_CONTEXT
lw t0,37*REGBYTES(sp) /* mepc */
lw t1,38*REGBYTES(sp) /* mcause */
csrw mcause, t1
csrw mepc, t0
.endm
.align 2
.global Default_IRQHandler
.weak Default_IRQHandler
.type Default_IRQHandler, %function
Default_IRQHandler:
SAVE_CONTEXT
SAVE_CSR_CONTEXT
/* get irq */
la t0,isr_table
// GET_IRQ_NUM /* t1: irq num */
li t1,0x000E4004 /* t1: irq num */
lw t1,0(t1)
slli t2, t1, 2
add t0, t0, t2
lw t2, (t0)
sw t1,39*REGBYTES(sp)
ENABLE_MIE
jalr t2 /* jump to irq */
DISABLE_MIE
/* clear pending mask*/
lw t1,39*REGBYTES(sp)
li t0,0x000E4004
sw t1,(t0)
/* enable pri mie*/
li t0, MSTATUS_PRV1
csrs mstatus, t0
RESTORE_CSR_CONTEXT
RESTORE_CONTEXT
mret
/* trap start*/
.section .text.trap
/* In CLIC mode, the exeception entry must be 64bytes aligned */
.align 6
.global trap
.weak trap
.type trap, %function
trap:
/* check for interrupt */
addi sp,sp,-4
sw t0,0x0(sp)
csrr t0,mcause
blt t0,x0, .Interrupt /* go to Interrupt*/
addi sp,sp,4
/* save regs */
addi sp,sp,-22*4
sw x1 , 0 *REGBYTES(sp)
sw x2 , 1 *REGBYTES(sp)
sw x3 , 2 *REGBYTES(sp)
sw x4 , 3 *REGBYTES(sp)
sw x5 , 4 *REGBYTES(sp)
sw x6 , 5 *REGBYTES(sp)
sw x7 , 6 *REGBYTES(sp)
sw x8 , 7 *REGBYTES(sp)
sw x9 , 8 *REGBYTES(sp)
sw x10, 9 *REGBYTES(sp)
sw x11, 10*REGBYTES(sp)
sw x12, 11*REGBYTES(sp)
sw x13, 12*REGBYTES(sp)
sw x14, 13*REGBYTES(sp)
sw x15, 14*REGBYTES(sp)
sw x16, 15*REGBYTES(sp)
sw x17, 16*REGBYTES(sp)
sw x28, 17*REGBYTES(sp)
sw x29, 18*REGBYTES(sp)
sw x30, 19*REGBYTES(sp)
sw x31, 20*REGBYTES(sp)
csrr a0, mepc
sw a0, 21*REGBYTES(sp)
csrr a0, mstatus
sw a0, 22*REGBYTES(sp)
mv a0, sp
jal trap_c
/*never reatch here */
j .
.Interrupt:
lw t0, 0x0(sp)
addi sp, sp, 4
j Default_IRQHandler
/* trap end*/
.global trap_c
.weak trap_c
.type trap_c,%function
trap_c:
j trap_c
.align 6
.weak Default_Handler
.global Default_Handler
.type Default_Handler, %function
Default_Handler:
j Default_Handler
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.globl \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler USB_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler QSPI_IRQHandler
def_irq_handler SPI0_IRQHandler
def_irq_handler SPI1_IRQHandler
def_irq_handler HSPI_IRQHandler
def_irq_handler SEC_IRQHandler
def_irq_handler UART0_IRQHandler
def_irq_handler UART1_IRQHandler
def_irq_handler UART2_IRQHandler
def_irq_handler UART3_IRQHandler
def_irq_handler MEMCP_IRQHandler
def_irq_handler SCI0_IRQHandler
def_irq_handler SCI1_IRQHandler
def_irq_handler MSR_IRQHandler
def_irq_handler GPIO_IRQHandler
def_irq_handler TMRG0_IRQHandler
def_irq_handler TMRG1_IRQHandler
def_irq_handler SDIO_IRQHandler
def_irq_handler PSARM_IRQHandler
def_irq_handler RSA_IRQHandler
def_irq_handler SM4_IRQHandler
def_irq_handler TRNG_IRQHandler
def_irq_handler WDT_IRQHandler
def_irq_handler DCMI_IRQHandler
def_irq_handler ADC_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler BIN_IRQHandler
def_irq_handler POWER_IRQHandler
def_irq_handler SOFTWARE_IRQHandler
def_irq_handler IPC_IRQHandler
def_irq_handler QR_IRQHandler
def_irq_handler ONE_BIN_IRQHandler
def_irq_handler SYSTICK_IRQHandler
def_irq_handler VBAT_IRQHandler
def_irq_handler EXTI0_IRQHandler
def_irq_handler EXTI1_IRQHandler
def_irq_handler EXTI2_IRQHandler
def_irq_handler EXTI3_IRQHandler
def_irq_handler EXTI4_IRQHandler
.align 4
isr_table:
.long USB_IRQHandler
.long I2C0_IRQHandler
.long I2C1_IRQHandler
.long QSPI_IRQHandler
.long SPI0_IRQHandler
.long SPI1_IRQHandler
.long HSPI_IRQHandler
.long SEC_IRQHandler
.long UART0_IRQHandler
.long UART1_IRQHandler
.long UART2_IRQHandler
.long UART3_IRQHandler
.long MEMCP_IRQHandler
.long SCI0_IRQHandler
.long SCI1_IRQHandler
.long MSR_IRQHandler
.long GPIO_IRQHandler
.long TMRG0_IRQHandler
.long TMRG1_IRQHandler
.long SDIO_IRQHandler
.long PSARM_IRQHandler
.long RSA_IRQHandler
.long SM4_IRQHandler
.long TRNG_IRQHandler
.long WDT_IRQHandler
.long DCMI_IRQHandler
.long ADC_IRQHandler
.long RTC_IRQHandler
.long BIN_IRQHandler
.long POWER_IRQHandler
.long SOFTWARE_IRQHandler
.long IPC_IRQHandler
.long QR_IRQHandler
.long ONE_BIN_IRQHandler
.long SYSTICK_IRQHandler

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# YC3122-pos 板级支持包 说明
标签： YICHIP、Cortex-M0、RISC_V YC3121、国产MCU
---
## 1. 简介
本文档为 YC3122-pos 的 BSP(板级支持包) 说明。
通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
### 1.1 开发板介绍
YC3122-pos 开发板由易兆微提供，可满足基础测试及高端开发需求。
开发板外观如下图所示：
YC3122-pos
![YC3122-pos](figures/YC3122-pos.png)
YC3122-pos 开发板板载资源如下：
- MCU：YC3122 ARM 32-bit Cortex-M0和RISC V 双核处理器，RISC V支持浮点算法主频 192MHz，512KB/1MB/4MB FLASH ，320KB SRAM
- 常用外设
- LED：4 个
- 梯形矩阵键盘
- 蜂鸣器
- USB
- UART
- I2C
- DCMI
- GPIO(80个)
- SDIO2.0
- ADC
- SPI LCD
- SPI NFC
- 7816接口 （接触IC卡，支持3V , 1.8V）
- 7811接口 （三轨磁条卡解码模块，支持ISO/ABA AAMVA 及IBM等标准卡）
- TIMER：9个32bi位 （支持PWM）
- TRNG：（1个真随机数发生器）
- 安全加密算法
- 对称算法：对称算法：DES、TDES、AES-128/192/256、国密IV（SM4）
- 非对称算法：RSA-1024/2048、国密II（SM2）、ECC
- HASH 校验算法：SHA-1/224/256/384/512、国密III（SM3）
- 调试接口：SWD / ICE

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from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# make a building
DoBuilding(TARGET, objs)

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from building import *
import os
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
group = group + SConscript(os.path.join(item, 'SConscript'))
Return('group')

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/*
* Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-09-09 WSY first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rtdbg.h>
/* defined the LED pin: PA12 */
#define LED_PIN (51)
#define FS_PARTITION_NAME "filesystem"
#ifdef BSP_USING_INTER_FLASH
#include <dfs_elm.h>
#include <dfs_file.h>
#include <unistd.h>
#include <dfs_fs.h>
#include <fal.h>
static void elmfs_sample(void)
{
fal_init();
struct rt_device *flash_dev = fal_blk_device_create(FS_PARTITION_NAME);
if (flash_dev == NULL)
{
LOG_E("Can't create a block device on '%s' partition.", FS_PARTITION_NAME);
}
else
{
LOG_I("Create a block device on the %s partition of flash successful...", FS_PARTITION_NAME);
}
if (dfs_mkfs("elm", flash_dev->parent.name) == 0)
{
LOG_I("dfs_mkfs ok!\n");
}
else
{
LOG_E("dfs_mkfs err!\n");
}
if (dfs_mount(flash_dev->parent.name, "/", "elm", 0, 0) == 0)
{
LOG_I("Filesystem initialized!");
}
else
{
LOG_E("Failed to initialize filesystem!");
LOG_D("You should create a filesystem on the block device first!");
}
struct statfs elm_stat;
if (statfs("/", &elm_stat) == 0)
{
LOG_I("elmfat filesystem block size:0x%x,total blocks:0x%x,free blocks:0x%x\n", elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree);
}
if (mkdir("/user", 0x777) == 0)
{
LOG_I("make a directory: '/user'.\n");
}
LOG_I("open file\n");
int fd = open("/user/test.txt", O_WRONLY | O_CREAT);
LOG_I("open file ok\n");
char str[] = "elmfat mount";
if (fd >= 0)
{
LOG_I("write file\n");
if (write(fd, str, sizeof(str)) == sizeof(str))
LOG_I("write data done.\n");
close(fd);
}
int size;
char buf[20];
fd = open("/user/test.txt", O_RDONLY);
if (fd >= 0)
{
LOG_I("read file\n");
size = read(fd, buf, sizeof(buf));
close(fd);
if (size == sizeof(str))
{
LOG_I("Read data from file test.txt(size:%d):%s\n", size, buf);
}
}
else
{
LOG_E("open err\n");
}
if (statfs("/", &elm_stat) == 0)
{
LOG_I("elmfat filesystem block size:0x%x,total blocks:0x%x,free blocks:0x%x\n", elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree);
}
}
#endif
int main(void)
{
#ifdef BSP_USING_INTER_FLASH
elmfs_sample();
#endif
int count = 1;
/* set LED4 pin mode to output */
rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
while (count++)
{
rt_pin_write(LED_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
return RT_EOK;
}

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menu "Hardware Drivers Config"
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menu "UART Drivers"
config BSP_USING_UART0
bool "Enable UART0 PC6/5(R/T)"
select RT_USING_SERIAL
default y
config BSP_USING_UART1
bool "Enable UART1 PC2/3(R/T)"
select RT_USING_SERIAL
default n
endmenu
config BSP_USING_INTER_FLASH
bool "Enable inter flash"
default n
endmenu
endmenu

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# RT-Thread building script for component
from building import *
import os
cwd = GetCurrentDir()
# add the general drivers.
src = Split("""
board.c
""")
# add gpio driver code
if GetDepend(['BSP_USING_GPIO']):
src += ['drv_gpio.c']
# add serial driver code
if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'):
src += ['drv_uart.c']
# add inter flash fal filesystem
if GetDepend('BSP_USING_INTER_FLASH'):
src += Glob('ports/*.c')
path_ports = os.path.join(cwd,'ports')
CPPPATH = [cwd,path_ports]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

58
bsp/yichip/yc3122-pos/drivers/board.c Normal file
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/*
* Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-09-09 WSY first version
*/
#include <board.h>
#if defined(BSP_USING_EXT_SRAM) && defined(RT_USING_MEMHEAP_AS_HEAP)
static struct rt_memheap system_heap;
#endif
#define SystemCoreClock (48000000)
static void bsp_clock_config(void)
{
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
}
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
#ifdef RT_USING_SERIAL
extern int rt_hw_uart_init(void);
#endif
void rt_hw_board_init()
{
bsp_clock_config();
#if defined(RT_USING_HEAP)
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
/* UART driver initialization is open by default */
#ifdef RT_USING_SERIAL
rt_hw_uart_init();
#endif
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}

43
bsp/yichip/yc3122-pos/drivers/board.h Normal file
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/*
* Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-09-09 WSY first version
*/
#ifndef BOARD_H__
#define BOARD_H__
#include <rtthread.h>
#include <yc3122.h>
#include "yc_gpio.h"
#include "yc_uart.h"
#include "yc_exti.h"
#define SRAM_BASE 0x20000
#define SRAM_SIZE 0x10000
#ifdef BSP_USING_EXT_SRAM
#define EXT_SRAM_BASE SRAMM_BASE
#define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE
#define EXT_SRAM_BEGIN EXT_SRAM_BASE
#define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE)
#endif
#define SRAM_END (SRAM_BASE + SRAM_SIZE)
#if defined(__ARMCC_VERSION)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section = "HEAP"
#define HEAP_rBEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END SRAM_END
#define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN)
extern void rt_hw_board_init(void);
#endif

269
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/*
* Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-09-09 WSY first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#include <rthw.h>
#define PIN_MAX_NUM (48)
typedef void (*pin_callback_t)(void *args);
struct pin
{
uint32_t package_index;
const char *name;
IRQn_Type irq;
rt_uint32_t irq_mode;
pin_callback_t callback;
void *callback_args;
};
typedef struct pin pin_t;
struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
};
static void yc_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
{
/* Configure GPIO_InitStructure */
if (mode == PIN_MODE_OUTPUT)
{
/* output setting */
GPIO_CONFIG(pin) = OUTPUT_LOW;
}
else if (mode == PIN_MODE_INPUT)
{
/* input setting: not pull. */
GPIO_CONFIG(pin) = INPUT;
}
else if (mode == PIN_MODE_INPUT_PULLUP)
{
/* input setting: pull up. */
GPIO_CONFIG(pin) = PULL_PU;
}
else if (mode == PIN_MODE_INPUT_PULLDOWN)
{
/* input setting: pull down. */
GPIO_CONFIG(pin) = PULL_PD;
}
else if (mode == PIN_MODE_OUTPUT_OD)
{
/* output setting: od. */
GPIO_CONFIG(pin) = PULL_PU;
}
}
static void yc_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
{
if (value)
{
GPIO_CONFIG(pin) = OUTPUT_HIGH;
}
else
{
GPIO_CONFIG(pin) = OUTPUT_LOW;
}
}
static rt_int8_t yc_pin_read(rt_device_t dev, rt_base_t pin)
{
//return GPIO_IN(pin / 16) & (1 << (pin % 16)) ? 1 : 0;
return GPIO_ReadInputDataBit((GPIO_TypeDef)(pin / 16), (GPIO_Pin_TypeDef)(1 << (pin % 16)));
}
static rt_err_t yc_pin_attach_irq(struct rt_device *device,
rt_base_t pin,
rt_uint8_t mode,
pin_callback_t cb,
void *args)
{
rt_int32_t index = -1;
rt_base_t level;
if (pin >= PIN_MAX_NUM)
{
return -RT_EINVAL;
}
index = pin;
level = rt_hw_interrupt_disable();
pin_irq_hdr_tab[index].pin = pin;
pin_irq_hdr_tab[index].hdr = cb;
pin_irq_hdr_tab[index].mode = mode;
pin_irq_hdr_tab[index].args = args;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t yc_pin_detach_irq(struct rt_device *device, rt_base_t pin)
{
rt_int32_t index = -1;
rt_base_t level;
if (pin >= PIN_MAX_NUM)
{
return -RT_EINVAL;
}
index = pin;
level = rt_hw_interrupt_disable();
pin_irq_hdr_tab[index].pin = -1;
pin_irq_hdr_tab[index].hdr = RT_NULL;
pin_irq_hdr_tab[index].mode = 0;
pin_irq_hdr_tab[index].args = RT_NULL;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t yc_pin_irq_enable(struct rt_device *device,
rt_base_t pin,
rt_uint8_t enabled)
{
rt_int32_t index;
rt_base_t level = 0;
rt_int8_t TrigMode = 0;
if (pin >= PIN_MAX_NUM)
{
return -RT_EINVAL;
}
index = pin;
if (enabled == PIN_IRQ_ENABLE)
{
switch (pin_irq_hdr_tab[index].mode)
{
case PIN_IRQ_MODE_RISING:
TrigMode = EXTI_Trigger_Rising;
break;
case PIN_IRQ_MODE_FALLING:
TrigMode = EXTI_Trigger_Falling;
break;
case PIN_IRQ_MODE_RISING_FALLING:
TrigMode = EXTI_Trigger_Rising_Falling;
break;
case PIN_IRQ_MODE_HIGH_LEVEL:
GPIO_CONFIG(pin) = PULL_PD;
TrigMode = EXTI_Trigger_HighLev;
break;
case PIN_IRQ_MODE_LOW_LEVEL:
GPIO_CONFIG(pin) = PULL_PU;
TrigMode = EXTI_Trigger_LowLev;
break;
default:
rt_hw_interrupt_enable(level);
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
NVIC_EnableIRQ(GPIO_IRQn);
EXTI_LineConfig((EXTI_LineTypeDef)(pin / 16), (EXTI_PIN_TypeDef)(1 << (pin % 16)), (EXTI_TriggerTypeDef)TrigMode);
rt_hw_interrupt_enable(level);
}
else if (enabled == PIN_IRQ_DISABLE)
{
NVIC_DisableIRQ(GPIO_IRQn);
MGPIO->INTR.reg[pin / 16] &= ~(1 << (pin % 16));
}
else
{
return -RT_ENOSYS;
}
return RT_EOK;
}
const static struct rt_pin_ops yc3122_pin_ops =
{
yc_pin_mode,
yc_pin_write,
yc_pin_read,
yc_pin_attach_irq,
yc_pin_detach_irq,
yc_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)
{
int result;
result = rt_device_pin_register("pin", &yc3122_pin_ops, RT_NULL);
return result;
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
void GPIO_IRQHandler(void)
{
// int i;
rt_interrupt_enter();
// for (i = 0; i < PIN_MAX_NUM; i++)
// {
// if ((GPIO_TRIG_MODE(i / 16) & (1 << (i % 16))) == (GPIO_IN(i / 16) & (1 << (i % 16))))
// {
// if (pin_irq_hdr_tab[i].hdr)
// {
// pin_irq_hdr_tab[i].hdr(pin_irq_hdr_tab[i].args);
// }
// }
// }
rt_interrupt_leave();
}

16
bsp/yichip/yc3122-pos/drivers/drv_gpio.h Normal file
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/*
* Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-09-09 WSY first version
*/
#ifndef DRV_GPIO_H__
#define DRV_GPIO_H__
int rt_hw_pin_init(void);
#endif

193
bsp/yichip/yc3122-pos/drivers/drv_uart.c Normal file
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/*
* Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-09-09 WSY first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
struct yc3122_uart
{
UART_TypeDef *uart;
IRQn_Type irq;
};
static rt_err_t yc3122_uart_configure(struct rt_serial_device *serial,
struct serial_configure *cfg)
{
struct yc3122_uart *uart;
UART_InitTypeDef UART_initStruct;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = (struct yc3122_uart *)serial->parent.user_data;
NVIC_DisableIRQ(uart->irq);
UART_initStruct.BaudRate = cfg->baud_rate;
UART_initStruct.FlowCtrl = FLOWCTRL_NONE ;
UART_initStruct.CommMode = MODE_DUPLEX;
UART_initStruct.SmartCard = SMARTCARD_DISABLE;
UART_initStruct.RxMode = MODE_RX_ENABLE;
switch (cfg->data_bits)
{
case DATA_BITS_9:
UART_initStruct.DataBits = DATABITS_9B;
break;
default:
UART_initStruct.DataBits = DATABITS_8B;
break;
}
switch (cfg->stop_bits)
{
case STOP_BITS_2:
UART_initStruct.StopBits = STOPBITS_2;
break;
default:
UART_initStruct.StopBits = STOPBITS_1;
break;
}
switch (cfg->parity)
{
case PARITY_ODD:
UART_initStruct.Parity = YC_PARITY_ODD;
break;
case PARITY_EVEN:
UART_initStruct.Parity = YC_PARITY_EVEN;
break;
default:
UART_initStruct.Parity = YC_PARITY_NONE;
break;
}
UART_Init(uart->uart, &UART_initStruct);
return RT_EOK;
}
static rt_err_t yc3122_uart_control(struct rt_serial_device *serial,
int cmd, void *arg)
{
struct yc3122_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct yc3122_uart *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
UART_SetRxITNum(uart->uart, 0);
NVIC_DisableIRQ(uart->irq);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
UART_ITConfig(uart->uart, UART_IT_RX, ENABLE);
UART_SetRxITNum(uart->uart, 1);
NVIC_EnableIRQ((IRQn_Type)uart->irq);
break;
}
return RT_EOK;
}
static int yc3122_uart_putc(struct rt_serial_device *serial, char c)
{
struct yc3122_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct yc3122_uart *)serial->parent.user_data;
while (UART_IsBusy(uart->uart));
UART_SendData(uart->uart, c);
return 1;
}
static int yc3122_uart_getc(struct rt_serial_device *serial)
{
int ch;
struct yc3122_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct yc3122_uart *)serial->parent.user_data;
ch = -1;
if (UART_ReceiveDataLen(uart->uart) != 0)
{
ch = UART_ReceiveData(uart->uart);
}
return ch;
}
static const struct rt_uart_ops yc3122_uart_ops =
{
yc3122_uart_configure,
yc3122_uart_control,
yc3122_uart_putc,
yc3122_uart_getc,
};
#if defined(BSP_USING_UART0)
/* UART0 device driver structure */
static struct yc3122_uart uart0;
static struct rt_serial_device serial0;
void UART0_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
/* UART in mode Receiver */
if (UART_GetITIdentity(uart0.uart) == UART_IT_RX)
{
rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_UART0 */
#if defined(BSP_USING_UART1)
/* UART1 device driver structure */
static struct yc3122_uart uart1;
static struct rt_serial_device serial1;
void UART1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
/* UART in mode Receiver */
if (UART_GetITIdentity(uart1.uart) == UART_IT_RX)
{
rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_UART1 */
int rt_hw_uart_init(void)
{
struct yc3122_uart *uart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#ifdef BSP_USING_UART0
GPIO_CONFIG(53) = UART0_TXD;
GPIO_CONFIG(54) = UART0_RXD;
uart = &uart0;
uart->uart = MUART0;
uart->irq = UART0_IRQn;
serial0.ops = &yc3122_uart_ops;
serial0.config = config;
/* register UART0 device */
rt_hw_serial_register(&serial0, RT_CONSOLE_DEVICE_NAME,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
#endif /* BSP_USING_UART0 */
#ifdef BSP_USING_UART1
GPIO_CONFIG(53) = UART1_TXD;
GPIO_CONFIG(54) = UART1_RXD;
uart = &uart1;
uart->uart = MUART1;
uart->irq = UART1_IRQn;
serial1.ops = &yc3122_uart_ops;
serial1.config = config;
/* register UART1 device */
rt_hw_serial_register(&serial1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
#endif /* BSP_USING_UART1 */
return 0;
}

16
bsp/yichip/yc3122-pos/drivers/drv_uart.h Normal file
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/*
* Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-09-09 WSY first version
*/
#ifndef DRV_UART_H__
#define DRV_UART_H__
int rt_hw_uart_init(void);
#endif

32
bsp/yichip/yc3122-pos/drivers/linker_scripts/link.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x1000200;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x1000200;
define symbol __ICFEDIT_region_ROM_end__ = 0x1ffffff;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0xF800;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

161
bsp/yichip/yc3122-pos/drivers/linker_scripts/link.lds Normal file
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/* Linker script to configure memory regions.
* Need modifying for a specific board.
* FLASH.ORIGIN: starting address of flash
* FLASH.LENGTH: length of flash
* RAM.ORIGIN: starting address of RAM bank 0
* RAM.LENGTH: length of RAM bank 0
*/
MEMORY
{
FLASH (rx) : ORIGIN = 0x1000000, LENGTH = 0x80000 /* 512K */
RAM (rwx) : ORIGIN = 0x20000, LENGTH = 0x10000 /* 64K */
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
*flash_start*.o
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
. = ALIGN(4);
__exidx_start = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__end__ = .;
PROVIDE(end = .);
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

16
bsp/yichip/yc3122-pos/drivers/linker_scripts/link.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x01000200 0x0007FE00 { ; load region size_region
ER_IROM1 0x01000200 0x0007FE00 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x00020004 0x0004FFFC { ; RW data
.ANY (+RW +ZI)
}
}

51
bsp/yichip/yc3122-pos/drivers/ports/fal_cfg.h Normal file
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/*
* File : fal_cfg.h
* COPYRIGHT (C) 2012-2018, Shanghai Real-Thread Technology Co., Ltd
*
* Change Logs:
* Date Author Notes
* 2018-08-21 MurphyZhao the first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
/* enable yc3122 onchip flash driver sample */
#define FAL_FLASH_PORT_DRIVER_YC3122
/* enable SFUD flash driver sample */
//#define FAL_FLASH_PORT_DRIVER_SFUD
extern const struct fal_flash_dev yc3122_onchip_flash;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&yc3122_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
#define APP_START_ADDR (0)
#define APP_SIZE (128*1024)
#define PARAM_START_ADDR (APP_START_ADDR+APP_SIZE)
#define PARAM_SIZE (64*1024)
#define DOWNLOAD_START_ADDR (PARAM_START_ADDR+PARAM_SIZE)
#define DOWNLOAD_SIZE (APP_SIZE)
#define FONT_START_ADDR (DOWNLOAD_START_ADDR+DOWNLOAD_SIZE)
#define FONT_SIZE (64*1024)
#define FILESYSTEM_ADDR (FONT_START_ADDR+FONT_SIZE)
#define FILESYSTEM_SIZE (128*1024)
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", APP_START_ADDR, APP_SIZE, 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash", PARAM_START_ADDR, PARAM_SIZE, 0}, \
{FAL_PART_MAGIC_WROD, "download", "onchip_flash", DOWNLOAD_START_ADDR, DOWNLOAD_SIZE, 0}, \
{FAL_PART_MAGIC_WROD, "font", "onchip_flash", FONT_START_ADDR, FONT_SIZE, 0}, \
{FAL_PART_MAGIC_WROD, "filesystem", "onchip_flash", FILESYSTEM_ADDR, FILESYSTEM_SIZE, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

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/*
* Copyright (c) 2006-2020, YICHIP Development Team
* @file
* @brief
*
* Change Logs:
* Date Author Version Notes
* 2020-11-06 dengzhiqian V1.0.0 the first version
*/
#include <fal.h>
#include "board.h"
#include "yc_qspi.h"
#include "rtdbg.h"
#define FLASH_START_ADRESS ((uint32_t)0x1000000)
#define FLASH_SIZE ((uint32_t)4 * 1024 * 1024)
#define FLASH_BLOCK_SIZE ((uint32_t)512)
#define FLASH_END_ADDRESS ((uint32_t)(FLASH_START_ADRESS + FLASH_SIZE))
#define FLASH_PAGE_NBPERBANK 256
#define FLASH_BANK_NUMBER 2
#define FLASH_PAGE_SIZE 256
// #define LOGOPEN
#ifdef LOGOPEN
#define YC3122_FLASH_DEBUG LOG_D
#else
#define YC3122_FLASH_DEBUG(...)
#endif
static int read(long offset, uint8_t *buf, size_t size)
{
uint32_t addr = yc3122_onchip_flash.addr + offset;
if ((addr + size) > FLASH_END_ADDRESS)
{
YC3122_FLASH_DEBUG("ERROR: read outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
return -1;
}
YC3122_FLASH_DEBUG("r_ addr:0x%x,size:0x%x\n", addr, size);
qspi_flash_read(addr, buf, size);
return size;
}
static int write(long offset, const uint8_t *buf, size_t size)
{
uint32_t addr = yc3122_onchip_flash.addr + offset;
if ((addr + size) > FLASH_END_ADDRESS)
{
YC3122_FLASH_DEBUG("ERROR: write outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
return -1;
}
if (size < 1)
{
return -1;
}
YC3122_FLASH_DEBUG("w_ addr:0x%x,size:0x%x\n", addr, size);
qspi_flash_write(addr, (uint8_t *)buf, size);
return size;
}
static int erase(long offset, size_t size)
{
uint32_t addr = yc3122_onchip_flash.addr + offset;
if ((addr + size) > FLASH_END_ADDRESS || addr % 0x100 != 0)
{
YC3122_FLASH_DEBUG("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
return -1;
}
YC3122_FLASH_DEBUG("s_ addr:0x%x,size:0x%x\n", addr, size);
if (addr % FLASH_PAGE_SIZE != 0)
{
YC3122_FLASH_DEBUG("ERROR: erase addr is not page alignment\n");
}
for (uint32_t i = 0; i < size; i += 256)
qspi_flash_pageerase(addr + i);
return size;
}
const struct fal_flash_dev yc3122_onchip_flash =
{
"onchip_flash",
FLASH_START_ADRESS,
FLASH_SIZE,
FLASH_BLOCK_SIZE,
{NULL, read, write, erase},
8,
};

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\project.ewp</path>
</project>
<batchBuild/>
</workspace>

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<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
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bsp/yichip/yc3122-pos/project.uvprojx Normal file
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239
bsp/yichip/yc3122-pos/rtconfig.h Normal file
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x50001
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_MTD_NOR
#define RT_USING_SPI
#define RT_USING_SFUD
#define RT_SFUD_USING_SFDP
#define RT_SFUD_USING_FLASH_INFO_TABLE
#define RT_SFUD_SPI_MAX_HZ 50000000
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
#define SOC_YC3122
/* Hardware Drivers Config */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
/* UART Drivers */
#define BSP_USING_UART0
#endif

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bsp/yichip/yc3122-pos/rtconfig.py Normal file
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# BSP Note: For TI EK-TM4C1294XL Tiva C Series Connected LancuhPad (REV D)
import os
import sys
# toolchains options
ARCH='arm'
CPU='cortex-m0'
CROSS_TOOL='gcc'
# device options
BSP_LIBRARY_TYPE = None
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'C:\gcc-arm-none-eabi-7-2018-q2-update-win32'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = 'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iccarm'
EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -Dgcc'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 -g'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M0 '
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --scatter "drivers\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
CFLAGS += ' -D__MICROLIB '
AFLAGS += ' --pd "__MICROLIB SETA 1" '
LFLAGS += ' --library_type=microlib '
EXEC_PATH += '/ARM/ARMCC/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf.exe --text -a -c --output=@L_asm.txt "!L" \nfromelf -z $TARGET'
elif PLATFORM == 'iccarm':
# toolchains
CC = 'iccarm'
CXX = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = '-Dewarm'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M0'
CFLAGS += ' -e'
CFLAGS += ' --fpu=None'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M0'
AFLAGS += ' --fpu None'
AFLAGS += ' -S'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = ' --config "drivers/linker_scripts/link.icf"'
LFLAGS += ' --entry __iar_program_start'
CXXFLAGS = CFLAGS
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT, dist_dir):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\template.ewp</path>
</project>
<batchBuild/>
</workspace>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>25000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>1</RunSim>
<RunTarget>0</RunTarget>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\build\keil\List\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<Books>
<Book>
<Number>0</Number>
<Title>Datasheet</Title>
<Path>DATASHTS\ST\STM32F4xx\DM00053488.pdf</Path>
</Book>
<Book>
<Number>1</Number>
<Title>Reference Manual</Title>
<Path>DATASHTS\ST\STM32F4xx\DM00031020.pdf</Path>
</Book>
<Book>
<Number>2</Number>
<Title>Technical Reference Manual</Title>
<Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path>
</Book>
<Book>
<Number>3</Number>
<Title>Generic User Guide</Title>
<Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path>
</Book>
</Books>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>0</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<tPdscDbg>0</tPdscDbg>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<nTsel>6</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U20090928 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-O207 -S0 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
</TargetOption>
</Target>
</ProjectOpt>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\build\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U788594195 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO31 -FD20000 -FCA000 -FN0</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
</ProjectOpt>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM0</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.5.1</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
<OutputName>rtthread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\build\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf.exe --text -a -c --output=@L_asm.txt "!L"</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> </SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM0</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> </TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4100</DriverSelection>
</Flash1>
<bUseTDR>0</bUseTDR>
<Flash2>Segger\JL2CM3.dll</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>1</RvctClst>
<GenPPlst>1</GenPPlst>
<AdsCpuType>"Cortex-M0"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>0</vShortEn>
<vShortWch>0</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\drivers\linker_scripts\link.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
</Project>