Merge pull request #4945 from wormsX/master
[BSP]: Support QEMU run for Xuantie-E9xx Series CPU.
This commit is contained in:
Bernard Xiong
GitHub
commit
146269ce2e
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@ -3,7 +3,7 @@ SMART-EVB is a development board provided by T-HEAD, based on FPGA to provide im
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## The main resources on board are as follows:
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1. SMART-EVB for E906/E906F/E906FD
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1. SMART-EVB for T-Head CPU E9xx Series
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| res | description |
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| -- | -- |
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@ -25,15 +25,21 @@ SMART-EVB is a development board provided by T-HEAD, based on FPGA to provide im
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# Compile T-HEAD BSP
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SMART-EVB BSP supports GCC compiler, the version information is:
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1. SMART-EVB for E906/E906F/E906FD
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1. SMART-EVB for E906/7/F/D/P
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| IDE/Compiler| version|
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| - | - |
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| GCC | gcc version 8.4.0 (C-SKY RISCV Tools V1.9.6 B20200616) |
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2. select cpu in rtconfig.py
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3. scons -c; scons
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# run smart-evb bsp
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# Quick start with qemu
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1. download qemu
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wget https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource/1356021/1612269502091/csky-qemu-x86_64-Ubuntu-16.04-20210202-1445.tar.gz
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2. qemu run
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qemu-system-riscv32 -cpu e906fdp -M smartl -kernel rtthread-e9xx.elf -nographic
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# Quick start with smart-evb
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1. Connect JTAG
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2. Connect the serial port
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3. riscv64-unknown-elf-gdb rtthread-e906f.elf
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@ -23,7 +23,7 @@ extern int __bss_end__;
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extern usart_handle_t console_handle;
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extern void ioreuse_initial(void);
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extern int rt_hw_usart_init(void);
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/**
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* This function will initial smart-evb board.
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@ -13,12 +13,7 @@
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#ifndef __CSI_CONFIG_H
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#define __CSI_CONFIG_H
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#define CONFIG_ARCH_RV32 1
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#define CONFIG_CPU_E906FD 1
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#define CONFIG_RV32_CORETIM 1
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#define CONFIG_CHIP_SMARTL_RV32 1
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#define CONFIG_BOARD_SMARTL_E906_EVB 1
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#define CONFIG_BOARD_NAME_STR "smartl_e906_evb"
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#define CONFIG_BOARD_NAME_STR "smart_e906_evb"
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#define CONFIG_SUPPORT_TSPEND 1
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#define CONFIG_ARCH_INTERRUPTSTACK 4096
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#define CONFIG_NEWLIB_WRAP 1
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@ -65,7 +65,10 @@ void systemmap_config(void)
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void SystemInit(void)
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{
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int i;
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#if ((CONFIG_CPU_E902 != 1) && (CONFIG_CPU_E902M != 1))
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systemmap_config();
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#endif
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/* enable mstatus FS */
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#if (__riscv_flen)
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uint32_t mstatus = __get_MSTATUS();
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@ -6,6 +6,9 @@ set *(int *)0x40011008=0x0
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set *(int *)0x4001101c=0x0
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set disassemble-next-line on
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show disassemble-next-line
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hb Default_Handler
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lo
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c
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@ -38,20 +38,6 @@
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#define RT_CONSOLEBUF_SIZE 128
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#define RT_CONSOLE_DEVICE_NAME "uart1"
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#define RT_VER_NUM 0x40003
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#define ARCH_RISCV
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#define ARCH_RISCV32
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#if(__riscv_flen == 64)
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#define ARCH_RISCV_FPU
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#define ARCH_RISCV_FPU_D
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#elif(__riscv_flen == 32)
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#define ARCH_RISCV_FPU
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#define ARCH_RISCV_FPU_S
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#else
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#endif
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#ifdef __riscv_zp64
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#define ARCH_RISCV_DSP
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#endif
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/* RT-Thread Components */
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@ -67,11 +67,5 @@ if PLATFORM == 'gcc':
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CXXFLAGS = CFLAGS
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# M_CFLAGS = DEVICE + ' -EL -G0 -O2 -mno-abicalls -fno-common -fno-exceptions -fno-omit-frame-pointer -mlong-calls -fno-pic '
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# M_CXXFLAGS = M_CFLAGS
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# M_LFLAGS = DEVICE + ' -EL -r -Wl,--gc-sections,-z,max-page-size=0x4' +\
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# ' -nostartfiles -static-libgcc'
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# M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
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DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
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POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
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@ -0,0 +1,24 @@
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#ifndef THEAD_CONFIG_H__
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#define THAED_CONFIG_H__
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#define ARCH_RISCV
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#define ARCH_RISCV32
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#if(__riscv_flen == 64)
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#define ARCH_RISCV_FPU
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#define ARCH_RISCV_FPU_D
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#elif(__riscv_flen == 32)
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#define ARCH_RISCV_FPU
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#define ARCH_RISCV_FPU_S
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#else
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#endif
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#ifdef __riscv_zp64
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#define ARCH_RISCV_DSP
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#endif
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#ifdef __riscv_xthead
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#ifdef __riscv_xtheade
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#define CONFIG_THEAD_EXT_SPUSHEN
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#endif
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#endif
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#endif
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@ -1,11 +1,13 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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* Copyright (c) 2021, Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020/08/20 zx.chen The T-HEAD RISC-V CPU E906 porting implementation
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* 2021/08/13 zx.chen update T-HEAD E9xx-series(E906/7/F/D/P) CPU porting code.
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*/
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#include "cpuport.h"
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@ -29,8 +31,6 @@ vPortYield:
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ret
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/*
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread);
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@ -56,12 +56,10 @@ rt_hw_context_switch_to:
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li t1, 1
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STORE t1, (t0)
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/* enable mexstatus SPUSHEN and SPSWAPEN */
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#if ((CONFIG_CPU_E906==1) || (CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906FD==1))
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uint32_t mexstatus;
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mexstatus = __get_MEXSTATUS();
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mexstatus |= (0x2 << 16);
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__set_MEXSTATUS(mexstatus);
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/* enable mexstatus SPUSHEN */
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#ifdef CONFIG_THEAD_EXT_SPUSHEN
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li t0, 0x10000
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csrs mexstatus, t0
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#endif
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csrw mscratch, sp
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@ -140,7 +138,7 @@ PendSV_Handler:
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lw t1, (t0)
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beqz t1, .switch_to_thead
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/* save from thread context */
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/* restore from thread context t0,t1 */
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lw t0, (-4)(sp)
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lw t1, (-8)(sp)
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@ -191,10 +189,6 @@ PendSV_Handler:
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csrr x1, mepc
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STORE x1, 0 * REGBYTES(sp)
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csrr x1, mstatus
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andi x1, x1, 8
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beqz x1, .save_mpie
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li x1, 0x80
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.save_mpie:
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STORE x1, 2 * REGBYTES(sp)
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/* x3 don't need save */
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STORE x4, 4 * REGBYTES(sp)
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@ -256,11 +250,9 @@ PendSV_Handler:
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csrw mepc, a1
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LOAD x1, 1 * REGBYTES(sp)
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/* force to machin mode(MPP=11) */
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li a1, 0x1880
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csrs mstatus, a1
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/* force to machine mode(MPP=11) */
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LOAD a1, 2 * REGBYTES(sp)
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csrs mstatus, a1
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csrw mstatus, a1
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/* x3 don't need restore */
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LOAD x4, 4 * REGBYTES(sp)
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LOAD x5, 5 * REGBYTES(sp)
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@ -1,11 +1,13 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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* Copyright (c) 2021, Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020/08/20 zx.chen The T-HEAD RISC-V CPU E906 porting code.
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* 2021/08/13 zx.chen update T-HEAD E9xx-series(E906/7/F/D/P) CPU porting code.
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*/
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#include <rthw.h>
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@ -143,8 +145,8 @@ rt_uint8_t *rt_hw_stack_init(void *tentry,
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rt_base_t rt_hw_interrupt_disable(void)
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{
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__asm volatile("csrc mstatus, 8");
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return 0;
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__asm volatile("csrrci a0, mstatus, 8");
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return;
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}
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/**
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@ -154,9 +156,10 @@ rt_base_t rt_hw_interrupt_disable(void)
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*
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* @return none
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*/
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/* XXX:rename rt_hw_interrupt_restore? */
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void rt_hw_interrupt_enable(rt_base_t level)
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{
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__asm volatile("csrs mstatus, 8");
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__asm volatile("csrw mstatus, a0");
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}
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/** shutdown CPU */
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@ -12,6 +12,7 @@
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#define CPUPORT_H__
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#include <rtconfig.h>
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#include <theadconfig.h>
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/* bytes of register width */
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#ifdef ARCH_RISCV_64
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