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[BSP]Update STM32F10xHAL bsp to RTT 3.0.0 

With USB Device Drivers
This commit is contained in:
uestczyh222 2017-11-15 21:14:09 +08:00 committed by Bernard Xiong
parent 0c6c08429d
commit 0b830302ca
24 changed files with 3697 additions and 2333 deletions
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184
bsp/stm32f10x_HAL/.config Normal file
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@ -0,0 +1,184 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_DEBUG=y
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_DEBUG_INIT=0
CONFIG_RT_DEBUG_THREAD=0
CONFIG_RT_USING_HOOK=y
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
# CONFIG_RT_USING_MODULE is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
CONFIG_FINSH_USING_MSH_ONLY=y
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
#
# Network stack
#
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# RT-Thread UI Engine
#
# CONFIG_RT_USING_GUIENGINE is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# RT-Thread online packages
#
#
# system packages
#
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_SQLITE is not set
#
# IoT - internet of things
#
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
#
# language packages
#
# CONFIG_PKG_USING_JERRYSCRIPT is not set
#
# multimedia packages
#
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_HELLO is not set
#
# BSP_SPECIAL CONFIG
#
CONFIG_STM32F10X_PIN_NUMBERS=64
# CONFIG_RT_USING_UART1 is not set
CONFIG_RT_USING_UART2=y
# CONFIG_RT_USING_UART3 is not set

59
bsp/stm32f10x_HAL/KConfig Normal file
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@ -0,0 +1,59 @@
mainmenu "RT-Thread Configuration"
config $BSP_DIR
string
option env="BSP_ROOT"
default "."
config $RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config $PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/KConfig"
source "$PKGS_DIR/KConfig"
if RT_USING_PIN
config STM32F10X_PIN_NUMBERS
int "number of stm32 pin numbers"
default 64
endif
if RT_USING_SERIAL
config RT_USING_UART1
bool "Using uart1"
default y
config RT_USING_UART2
bool "Using uart2"
default n
config RT_USING_UART3
bool "Using uart3"
default n
endif
if RT_USING_SPI
config RT_USING_SPI1
bool "Using spi1"
default y
config RT_USING_SPI2
bool "Using spi2"
default n
endif

12
bsp/stm32f10x_HAL/applications/SConscript
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@ -2,16 +2,8 @@ Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Split("""
application.c
startup.c
""")
if GetDepend('RT_USING_CAN'):
src += ['canapp.c']
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)

87
bsp/stm32f10x_HAL/applications/application.c
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@ -1,87 +0,0 @@
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard the first version
* 2013-07-12 aozima update for auto initial.
*/
/**
* @addtogroup STM32
*/
/*@{*/
#include <board.h>
#include <rtthread.h>
#ifdef RT_USING_COMPONENTS_INIT
#include <components.h>
#endif /* RT_USING_COMPONENTS_INIT */
#ifdef RT_USING_DFS
/* dfs filesystem:ELM filesystem init */
#include <dfs_elm.h>
/* dfs Filesystem APIs */
#include <dfs_fs.h>
#include <dfs_posix.h>
extern int dfs_init(void);
#endif
//ALIGN(RT_ALIGN_SIZE)
void rt_init_thread_entry(void *parameter)
{
/* Filesystem Initialization */
#ifdef RT_USING_SPI
stm32_hw_spi_init();
#endif
#if defined(RT_USING_DFS) && defined(RT_USING_DFS_ELMFAT)
dfs_init();
elm_init();
/* mount sd card fat partition 1 as root directory */
if (dfs_mount("flash0", "/", "elm", 0, 0) == 0)
{
rt_kprintf("File System initialized!\n");
}
else
{
rt_kprintf("File System initialzation failed!\n");
dfs_mkfs("elm","flash0");
HAL_NVIC_SystemReset();
}
#endif /* RT_USING_DFS */
}
int rt_application_init(void)
{
rt_thread_t init_thread;
// rt_err_t result;
#if (RT_THREAD_PRIORITY_MAX == 32)
init_thread = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
1024, 8, 20);
#else
init_thread = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
1024, 80, 20);
#endif
if (init_thread != RT_NULL)
rt_thread_startup(init_thread);
return 0;
}
/*@}*/

20
bsp/stm32f10x_HAL/applications/main.c Normal file
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@ -0,0 +1,20 @@
/*
* File : main.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2015-07-29 Arda.Fu first implementation
*/
#include <rtthread.h>
int main(void)
{
/* user app entry */
return 0;
}

118
bsp/stm32f10x_HAL/applications/startup.c
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@ -1,118 +0,0 @@
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-08-31 Bernard first implementation
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#ifdef RT_USING_FINSH
#include "shell.h"
#endif
/**
* @addtogroup STM32
*/
/*@{*/
extern int rt_application_init(void);
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#elif __ICCARM__
#pragma section="HEAP"
#else
extern int __bss_end;
#endif
/*******************************************************************************
* Function Name : assert_failed
* Description : Reports the name of the source file and the source line number
* where the assert error has occurred.
* Input : - file: pointer to the source file name
* - line: assert error line source number
* Output : None
* Return : None
*******************************************************************************/
void assert_failed(rt_uint8_t * file, rt_uint32_t line)
{
rt_kprintf("\n\r Wrong parameter value detected on\r\n");
rt_kprintf(" file %s\r\n", file);
rt_kprintf(" line %d\r\n", line);
while (1) ;
}
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* init board */
rt_hw_board_init();
/* show version */
rt_show_version();
#ifdef RT_USING_HEAP
#if STM32_EXT_SRAM
rt_system_heap_init((void*)STM32_EXT_SRAM_BEGIN, (void*)STM32_EXT_SRAM_END);
#else
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)STM32_SRAM_END);
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END);
#else
/* init memory system */
rt_system_heap_init((void*)&__bss_end, (void*)STM32_SRAM_END);
#endif
#endif /* STM32_EXT_SRAM */
#endif /* RT_USING_HEAP */
/* init scheduler system */
rt_system_scheduler_init();
/* initialize timer */
rt_system_timer_init();
/* init timer thread */
rt_system_timer_thread_init();
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
finsh_system_init();
finsh_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
}
/*@}*/

11
bsp/stm32f10x_HAL/drivers/SConscript
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@ -2,7 +2,7 @@ Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'drivers')
cwd = GetCurrentDir()
# add the general drivers.
src = Split("""
@ -11,11 +11,14 @@ stm32f1xx_it.c
""")
if GetDepend(['RT_USING_PIN']):
src += ['gpio.c']
src += ['drv_gpio.c']
if GetDepend(['RT_USING_SERIAL']):
src += ['usart.c']
src += ['drv_usart.c']
if GetDepend(['RT_USING_SPI']):
src += ['stm32_spi.c']
src += ['drv_spi.c']
if GetDepend(['RT_USING_USB_DEVICE']):
src += ['drv_usb.c']
CPPPATH = [cwd]

124
bsp/stm32f10x_HAL/drivers/board.c
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@ -11,6 +11,7 @@
* Date Author Notes
* 2009-01-05 Bernard first implementation
* 2017-10-20 ZYH emmm...setup for HAL Libraries
* 2017-11-15 ZYH update to 3.0.0
*/
#include <rthw.h>
@ -27,65 +28,64 @@
void HAL_MspInit(void)
{
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* System interrupt init*/
__HAL_RCC_AFIO_CLK_ENABLE();
/* MemoryManagement_IRQn interrupt configuration */
HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0);
/* BusFault_IRQn interrupt configuration */
HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0);
/* UsageFault_IRQn interrupt configuration */
HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0);
/* SVCall_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0);
/* DebugMonitor_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0);
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
/* System interrupt init*/
__HAL_RCC_AFIO_CLK_ENABLE();
/* MemoryManagement_IRQn interrupt configuration */
HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0);
/* BusFault_IRQn interrupt configuration */
HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0);
/* UsageFault_IRQn interrupt configuration */
HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0);
/* SVCall_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0);
/* DebugMonitor_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0);
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
/**DISABLE: JTAG-DP Disabled and SW-DP Disabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
/**DISABLE: JTAG-DP Disabled and SW-DP Disabled**/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
}
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
RT_ASSERT(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK);
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
RT_ASSERT(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK);
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
RT_ASSERT(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) == HAL_OK);
RT_ASSERT(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) == HAL_OK);
/**Configure the Systick interrupt time
*/
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
/**Configure the Systick interrupt time
*/
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND);
/**Configure the Systick
*/
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
/**Configure the Systick
*/
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
}
@ -95,14 +95,14 @@ void SystemClock_Config(void)
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
/* enter interrupt */
rt_interrupt_enter();
HAL_IncTick();
rt_tick_increase();
HAL_IncTick();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
/* leave interrupt */
rt_interrupt_leave();
}
/**
@ -110,16 +110,18 @@ void SysTick_Handler(void)
*/
void rt_hw_board_init(void)
{
HAL_Init();
SystemClock_Config();
#ifdef RT_USING_SERIAL
rt_hw_usart_init();
HAL_Init();
SystemClock_Config();
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
#ifdef RT_USING_PIN
rt_hw_pin_init();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}

22
bsp/stm32f10x_HAL/drivers/board.h
View File

@ -18,15 +18,6 @@
#define __BOARD_H__
#include "stm32f1xx_hal.h"
#ifdef RT_USING_SERIAL
#include "usart.h"
#endif
#ifdef RT_USING_PIN
#include "gpio.h"
#endif
#ifdef RT_USING_SPI
#include "stm32_spi.h"
#endif
/* board configuration */
/* whether use board external SRAM memory */
@ -45,8 +36,17 @@
// <i>Default: 64
#define STM32_SRAM_SIZE 20
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
// <<< Use Configuration Wizard in Context Menu >>>
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END STM32_SRAM_END
void rt_hw_board_init(void);

850
bsp/stm32f10x_HAL/drivers/drv_gpio.c Normal file
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@ -0,0 +1,850 @@
/*
* File : drv_gpio.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2015, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2017-10-20 ZYH the first version
* 2017-11-15 ZYH update to 3.0.0
*/
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
#include <rtthread.h>
#ifdef RT_USING_PIN
#define __STM32_PIN(index, gpio, gpio_index) {index, GPIO##gpio##_CLK_ENABLE, GPIO##gpio, GPIO_PIN_##gpio_index}
#define __STM32_PIN_DEFAULT {-1, 0, 0, 0}
static void GPIOA_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOA_CLK_ENABLE
__HAL_RCC_GPIOA_CLK_ENABLE();
#endif
}
static void GPIOB_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOB_CLK_ENABLE
__HAL_RCC_GPIOB_CLK_ENABLE();
#endif
}
static void GPIOC_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOC_CLK_ENABLE
__HAL_RCC_GPIOC_CLK_ENABLE();
#endif
}
#if (STM32F10X_PIN_NUMBERS >48)
static void GPIOD_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOD_CLK_ENABLE
__HAL_RCC_GPIOD_CLK_ENABLE();
#endif
}
#if (STM32F10X_PIN_NUMBERS >64)
static void GPIOE_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOE_CLK_ENABLE
__HAL_RCC_GPIOE_CLK_ENABLE();
#endif
}
static void GPIOF_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOF_CLK_ENABLE
__HAL_RCC_GPIOF_CLK_ENABLE();
#endif
}
static void GPIOG_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOG_CLK_ENABLE
__HAL_RCC_GPIOG_CLK_ENABLE();
#endif
}
static void GPIOH_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOH_CLK_ENABLE
__HAL_RCC_GPIOH_CLK_ENABLE();
#endif
}
#endif
#endif
/* STM32 GPIO driver */
struct pin_index
{
int index;
void (*rcc)(void);
GPIO_TypeDef *gpio;
uint32_t pin;
};
static const struct pin_index pins[] =
{
#if (STM32F10X_PIN_NUMBERS == 48)
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(2, C, 13),
__STM32_PIN(3, C, 14),
__STM32_PIN(4, C, 15),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(10, A, 0),
__STM32_PIN(11, A, 1),
__STM32_PIN(12, A, 2),
__STM32_PIN(13, A, 3),
__STM32_PIN(14, A, 4),
__STM32_PIN(15, A, 5),
__STM32_PIN(16, A, 6),
__STM32_PIN(17, A, 7),
__STM32_PIN(18, B, 0),
__STM32_PIN(19, B, 1),
__STM32_PIN(20, B, 2),
__STM32_PIN(21, B, 10),
__STM32_PIN(22, B, 11),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(25, B, 12),
__STM32_PIN(26, B, 13),
__STM32_PIN(27, B, 14),
__STM32_PIN(28, B, 15),
__STM32_PIN(29, A, 8),
__STM32_PIN(30, A, 9),
__STM32_PIN(31, A, 10),
__STM32_PIN(32, A, 11),
__STM32_PIN(33, A, 12),
__STM32_PIN(34, A, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(37, A, 14),
__STM32_PIN(38, A, 15),
__STM32_PIN(39, B, 3),
__STM32_PIN(40, B, 4),
__STM32_PIN(41, B, 5),
__STM32_PIN(42, B, 6),
__STM32_PIN(43, B, 7),
__STM32_PIN_DEFAULT,
__STM32_PIN(45, B, 8),
__STM32_PIN(46, B, 9),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
#endif
#if (STM32F10X_PIN_NUMBERS == 64)
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(2, C, 13),
__STM32_PIN(3, C, 14),
__STM32_PIN(4, C, 15),
__STM32_PIN(5, D, 0),
__STM32_PIN(6, D, 1),
__STM32_PIN_DEFAULT,
__STM32_PIN(8, C, 0),
__STM32_PIN(9, C, 1),
__STM32_PIN(10, C, 2),
__STM32_PIN(11, C, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(14, A, 0),
__STM32_PIN(15, A, 1),
__STM32_PIN(16, A, 2),
__STM32_PIN(17, A, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(20, A, 4),
__STM32_PIN(21, A, 5),
__STM32_PIN(22, A, 6),
__STM32_PIN(23, A, 7),
__STM32_PIN(24, C, 4),
__STM32_PIN(25, C, 5),
__STM32_PIN(26, B, 0),
__STM32_PIN(27, B, 1),
__STM32_PIN(28, B, 2),
__STM32_PIN(29, B, 10),
__STM32_PIN(30, B, 11),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(33, B, 12),
__STM32_PIN(34, B, 13),
__STM32_PIN(35, B, 14),
__STM32_PIN(36, B, 15),
__STM32_PIN(37, C, 6),
__STM32_PIN(38, C, 7),
__STM32_PIN(39, C, 8),
__STM32_PIN(40, C, 9),
__STM32_PIN(41, A, 8),
__STM32_PIN(42, A, 9),
__STM32_PIN(43, A, 10),
__STM32_PIN(44, A, 11),
__STM32_PIN(45, A, 12),
__STM32_PIN(46, A, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(49, A, 14),
__STM32_PIN(50, A, 15),
__STM32_PIN(51, C, 10),
__STM32_PIN(52, C, 11),
__STM32_PIN(53, C, 12),
__STM32_PIN(54, D, 2),
__STM32_PIN(55, B, 3),
__STM32_PIN(56, B, 4),
__STM32_PIN(57, B, 5),
__STM32_PIN(58, B, 6),
__STM32_PIN(59, B, 7),
__STM32_PIN_DEFAULT,
__STM32_PIN(61, B, 8),
__STM32_PIN(62, B, 9),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
#endif
#if (STM32F10X_PIN_NUMBERS == 100)
__STM32_PIN_DEFAULT,
__STM32_PIN(1, E, 2),
__STM32_PIN(2, E, 3),
__STM32_PIN(3, E, 4),
__STM32_PIN(4, E, 5),
__STM32_PIN(5, E, 6),
__STM32_PIN_DEFAULT,
__STM32_PIN(7, C, 13),
__STM32_PIN(8, C, 14),
__STM32_PIN(9, C, 15),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(15, C, 0),
__STM32_PIN(16, C, 1),
__STM32_PIN(17, C, 2),
__STM32_PIN(18, C, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(23, A, 0),
__STM32_PIN(24, A, 1),
__STM32_PIN(25, A, 2),
__STM32_PIN(26, A, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(29, A, 4),
__STM32_PIN(30, A, 5),
__STM32_PIN(31, A, 6),
__STM32_PIN(32, A, 7),
__STM32_PIN(33, C, 4),
__STM32_PIN(34, C, 5),
__STM32_PIN(35, B, 0),
__STM32_PIN(36, B, 1),
__STM32_PIN(37, B, 2),
__STM32_PIN(38, E, 7),
__STM32_PIN(39, E, 8),
__STM32_PIN(40, E, 9),
__STM32_PIN(41, E, 10),
__STM32_PIN(42, E, 11),
__STM32_PIN(43, E, 12),
__STM32_PIN(44, E, 13),
__STM32_PIN(45, E, 14),
__STM32_PIN(46, E, 15),
__STM32_PIN(47, B, 10),
__STM32_PIN(48, B, 11),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(51, B, 12),
__STM32_PIN(52, B, 13),
__STM32_PIN(53, B, 14),
__STM32_PIN(54, B, 15),
__STM32_PIN(55, D, 8),
__STM32_PIN(56, D, 9),
__STM32_PIN(57, D, 10),
__STM32_PIN(58, D, 11),
__STM32_PIN(59, D, 12),
__STM32_PIN(60, D, 13),
__STM32_PIN(61, D, 14),
__STM32_PIN(62, D, 15),
__STM32_PIN(63, C, 6),
__STM32_PIN(64, C, 7),
__STM32_PIN(65, C, 8),
__STM32_PIN(66, C, 9),
__STM32_PIN(67, A, 8),
__STM32_PIN(68, A, 9),
__STM32_PIN(69, A, 10),
__STM32_PIN(70, A, 11),
__STM32_PIN(71, A, 12),
__STM32_PIN(72, A, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(76, A, 14),
__STM32_PIN(77, A, 15),
__STM32_PIN(78, C, 10),
__STM32_PIN(79, C, 11),
__STM32_PIN(80, C, 12),
__STM32_PIN(81, D, 0),
__STM32_PIN(82, D, 1),
__STM32_PIN(83, D, 2),
__STM32_PIN(84, D, 3),
__STM32_PIN(85, D, 4),
__STM32_PIN(86, D, 5),
__STM32_PIN(87, D, 6),
__STM32_PIN(88, D, 7),
__STM32_PIN(89, B, 3),
__STM32_PIN(90, B, 4),
__STM32_PIN(91, B, 5),
__STM32_PIN(92, B, 6),
__STM32_PIN(93, B, 7),
__STM32_PIN_DEFAULT,
__STM32_PIN(95, B, 8),
__STM32_PIN(96, B, 9),
__STM32_PIN(97, E, 0),
__STM32_PIN(98, E, 1),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
#endif
#if (STM32F10X_PIN_NUMBERS == 144)
__STM32_PIN_DEFAULT,
__STM32_PIN(1, E, 2),
__STM32_PIN(2, E, 3),
__STM32_PIN(3, E, 4),
__STM32_PIN(4, E, 5),
__STM32_PIN(5, E, 6),
__STM32_PIN_DEFAULT,
__STM32_PIN(7, C, 13),
__STM32_PIN(8, C, 14),
__STM32_PIN(9, C, 15),
__STM32_PIN(10, F, 0),
__STM32_PIN(11, F, 1),
__STM32_PIN(12, F, 2),
__STM32_PIN(13, F, 3),
__STM32_PIN(14, F, 4),
__STM32_PIN(15, F, 5),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(18, F, 6),
__STM32_PIN(19, F, 7),
__STM32_PIN(20, F, 8),
__STM32_PIN(21, F, 9),
__STM32_PIN(22, F, 10),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(26, C, 0),
__STM32_PIN(27, C, 1),
__STM32_PIN(28, C, 2),
__STM32_PIN(29, C, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(34, A, 0),
__STM32_PIN(35, A, 1),
__STM32_PIN(36, A, 2),
__STM32_PIN(37, A, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(40, A, 4),
__STM32_PIN(41, A, 5),
__STM32_PIN(42, A, 6),
__STM32_PIN(43, A, 7),
__STM32_PIN(44, C, 4),
__STM32_PIN(45, C, 5),
__STM32_PIN(46, B, 0),
__STM32_PIN(47, B, 1),
__STM32_PIN(48, B, 2),
__STM32_PIN(49, F, 11),
__STM32_PIN(50, F, 12),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(53, F, 13),
__STM32_PIN(54, F, 14),
__STM32_PIN(55, F, 15),
__STM32_PIN(56, G, 0),
__STM32_PIN(57, G, 1),
__STM32_PIN(58, E, 7),
__STM32_PIN(59, E, 8),
__STM32_PIN(60, E, 9),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(63, E, 10),
__STM32_PIN(64, E, 11),
__STM32_PIN(65, E, 12),
__STM32_PIN(66, E, 13),
__STM32_PIN(67, E, 14),
__STM32_PIN(68, E, 15),
__STM32_PIN(69, B, 10),
__STM32_PIN(70, B, 11),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(73, B, 12),
__STM32_PIN(74, B, 13),
__STM32_PIN(75, B, 14),
__STM32_PIN(76, B, 15),
__STM32_PIN(77, D, 8),
__STM32_PIN(78, D, 9),
__STM32_PIN(79, D, 10),
__STM32_PIN(80, D, 11),
__STM32_PIN(81, D, 12),
__STM32_PIN(82, D, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(85, D, 14),
__STM32_PIN(86, D, 15),
__STM32_PIN(87, G, 2),
__STM32_PIN(88, G, 3),
__STM32_PIN(89, G, 4),
__STM32_PIN(90, G, 5),
__STM32_PIN(91, G, 6),
__STM32_PIN(92, G, 7),
__STM32_PIN(93, G, 8),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(96, C, 6),
__STM32_PIN(97, C, 7),
__STM32_PIN(98, C, 8),
__STM32_PIN(99, C, 9),
__STM32_PIN(100, A, 8),
__STM32_PIN(101, A, 9),
__STM32_PIN(102, A, 10),
__STM32_PIN(103, A, 11),
__STM32_PIN(104, A, 12),
__STM32_PIN(105, A, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(109, A, 14),
__STM32_PIN(110, A, 15),
__STM32_PIN(111, C, 10),
__STM32_PIN(112, C, 11),
__STM32_PIN(113, C, 12),
__STM32_PIN(114, D, 0),
__STM32_PIN(115, D, 1),
__STM32_PIN(116, D, 2),
__STM32_PIN(117, D, 3),
__STM32_PIN(118, D, 4),
__STM32_PIN(119, D, 5),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(122, D, 6),
__STM32_PIN(123, D, 7),
__STM32_PIN(124, G, 9),
__STM32_PIN(125, G, 10),
__STM32_PIN(126, G, 11),
__STM32_PIN(127, G, 12),
__STM32_PIN(128, G, 13),
__STM32_PIN(129, G, 14),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(132, G, 15),
__STM32_PIN(133, B, 3),
__STM32_PIN(134, B, 4),
__STM32_PIN(135, B, 5),
__STM32_PIN(136, B, 6),
__STM32_PIN(137, B, 7),
__STM32_PIN_DEFAULT,
__STM32_PIN(139, B, 8),
__STM32_PIN(140, B, 9),
__STM32_PIN(141, E, 0),
__STM32_PIN(142, E, 1),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
#endif
};
struct pin_irq_map
{
rt_uint16_t pinbit;
IRQn_Type irqno;
};
static const struct pin_irq_map pin_irq_map[] =
{
{GPIO_PIN_0, EXTI0_IRQn},
{GPIO_PIN_1, EXTI1_IRQn},
{GPIO_PIN_2, EXTI2_IRQn},
{GPIO_PIN_3, EXTI3_IRQn},
{GPIO_PIN_4, EXTI4_IRQn},
{GPIO_PIN_5, EXTI9_5_IRQn},
{GPIO_PIN_6, EXTI9_5_IRQn},
{GPIO_PIN_7, EXTI9_5_IRQn},
{GPIO_PIN_8, EXTI9_5_IRQn},
{GPIO_PIN_9, EXTI9_5_IRQn},
{GPIO_PIN_10, EXTI15_10_IRQn},
{GPIO_PIN_11, EXTI15_10_IRQn},
{GPIO_PIN_12, EXTI15_10_IRQn},
{GPIO_PIN_13, EXTI15_10_IRQn},
{GPIO_PIN_14, EXTI15_10_IRQn},
{GPIO_PIN_15, EXTI15_10_IRQn},
};
struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
{ -1, 0, RT_NULL, RT_NULL},
};
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
const struct pin_index *get_pin(uint8_t pin)
{
const struct pin_index *index;
if (pin < ITEM_NUM(pins))
{
index = &pins[pin];
if (index->index == -1)
index = RT_NULL;
}
else
{
index = RT_NULL;
}
return index;
};
void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
const struct pin_index *index;
index = get_pin(pin);
if (index == RT_NULL)
{
return;
}
HAL_GPIO_WritePin(index->gpio, index->pin, (GPIO_PinState)value);
}
int stm32_pin_read(rt_device_t dev, rt_base_t pin)
{
int value;
const struct pin_index *index;
value = PIN_LOW;
index = get_pin(pin);
if (index == RT_NULL)
{
return value;
}
value = HAL_GPIO_ReadPin(index->gpio, index->pin);
return value;
}
void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
const struct pin_index *index;
GPIO_InitTypeDef GPIO_InitStruct;
index = get_pin(pin);
if (index == RT_NULL)
{
return;
}
/* GPIO Periph clock enable */
index->rcc();
/* Configure GPIO_InitStructure */
GPIO_InitStruct.Pin = index->pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
if (mode == PIN_MODE_OUTPUT)
{
/* output setting */
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
}
else if (mode == PIN_MODE_INPUT)
{
/* input setting: not pull. */
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
}
else if (mode == PIN_MODE_INPUT_PULLUP)
{
/* input setting: pull up. */
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_PULLUP;
}
else if (mode == PIN_MODE_INPUT_PULLDOWN)
{
/* input setting: pull down. */
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
}
else if (mode == PIN_MODE_OUTPUT_OD)
{
/* output setting: od. */
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
GPIO_InitStruct.Pull = GPIO_NOPULL;
}
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
}
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
{
int i;
for (i = 0; i < 32; i++)
{
if ((0x01 << i) == bit)
{
return i;
}
}
return -1;
}
rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
{
rt_int32_t mapindex = bit2bitno(pinbit);
if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
{
return RT_NULL;
}
return &pin_irq_map[mapindex];
};
rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
const struct pin_index *index;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == pin &&
pin_irq_hdr_tab[irqindex].hdr == hdr &&
pin_irq_hdr_tab[irqindex].mode == mode &&
pin_irq_hdr_tab[irqindex].args == args)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
if (pin_irq_hdr_tab[irqindex].pin != -1)
{
rt_hw_interrupt_enable(level);
return RT_EBUSY;
}
pin_irq_hdr_tab[irqindex].pin = pin;
pin_irq_hdr_tab[irqindex].hdr = hdr;
pin_irq_hdr_tab[irqindex].mode = mode;
pin_irq_hdr_tab[irqindex].args = args;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
{
const struct pin_index *index;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
pin_irq_hdr_tab[irqindex].pin = -1;
pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
pin_irq_hdr_tab[irqindex].mode = 0;
pin_irq_hdr_tab[irqindex].args = RT_NULL;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled)
{
const struct pin_index *index;
const struct pin_irq_map *irqmap;
rt_base_t level;
rt_int32_t irqindex = -1;
GPIO_InitTypeDef GPIO_InitStruct;
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_ENOSYS;
}
if (enabled == PIN_IRQ_ENABLE)
{
irqindex = bit2bitno(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_ENOSYS;
}
irqmap = &pin_irq_map[irqindex];
/* GPIO Periph clock enable */
index->rcc();
/* Configure GPIO_InitStructure */
GPIO_InitStruct.Pin = index->pin;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
switch (pin_irq_hdr_tab[irqindex].mode)
{
case PIN_IRQ_MODE_RISING:
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
break;
case PIN_IRQ_MODE_FALLING:
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
break;
case PIN_IRQ_MODE_RISING_FALLING:
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
break;
}
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
HAL_NVIC_SetPriority(irqmap->irqno, 5, 0);
HAL_NVIC_EnableIRQ(irqmap->irqno);
rt_hw_interrupt_enable(level);
}
else if (enabled == PIN_IRQ_DISABLE)
{
irqmap = get_pin_irq_map(index->pin);
if (irqmap == RT_NULL)
{
return RT_ENOSYS;
}
HAL_NVIC_DisableIRQ(irqmap->irqno);
}
else
{
return RT_ENOSYS;
}
return RT_EOK;
}
const static struct rt_pin_ops _stm32_pin_ops =
{
stm32_pin_mode,
stm32_pin_write,
stm32_pin_read,
stm32_pin_attach_irq,
stm32_pin_dettach_irq,
stm32_pin_irq_enable,
};
int rt_hw_pin_init(void)
{
int result;
result = rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL);
return result;
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
rt_inline void pin_irq_hdr(int irqno)
{
if (pin_irq_hdr_tab[irqno].hdr)
{
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
}
}
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
pin_irq_hdr(bit2bitno(GPIO_Pin));
}
void EXTI0_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
rt_interrupt_leave();
}
void EXTI1_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
rt_interrupt_leave();
}
void EXTI2_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
rt_interrupt_leave();
}
void EXTI3_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
rt_interrupt_leave();
}
void EXTI4_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
rt_interrupt_leave();
}
void EXTI9_5_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
rt_interrupt_leave();
}
void EXTI15_10_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
rt_interrupt_leave();
}
#endif

3
bsp/stm32f10x_HAL/drivers/gpio.h → bsp/stm32f10x_HAL/drivers/drv_gpio.h
View File

@ -1,5 +1,5 @@
/*
* File : gpio.h
* File : drv_gpio.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2015, RT-Thread Development Team
*
@ -10,6 +10,7 @@
* Change Logs:
* Date Author Notes
* 2015-01-05 Bernard the first version
* 2017-11-35 ZYH update to 3.0.0
*/
#ifndef GPIO_H__
#define GPIO_H__

256
bsp/stm32f10x_HAL/drivers/stm32_spi.c → bsp/stm32f10x_HAL/drivers/drv_spi.c
View File

@ -1,5 +1,5 @@
/*
* File : gpio.c
* File : dev_gpio.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2015, RT-Thread Development Team
*
@ -10,15 +10,15 @@
* Change Logs:
* Date Author Notes
* 2017-10-20 ZYH the first version
* 2017-11-35 ZYH update to 3.0.0
*/
#include <board.h>
#include "spi_flash_w25qxx.h"
#define SPIRXEVENT 0x01
#define SPITXEVENT 0x02
#include <drv_spi.h>
#ifdef RT_USING_SPI
#define SPIRXEVENT 0x01
#define SPITXEVENT 0x02
#define SPITIMEOUT 2
#define SPICRCEN 0
@ -90,41 +90,41 @@ static rt_err_t stm32_spi_init(SPI_TypeDef *spix, struct rt_spi_configuration *c
}
else
{
hspi.Init.NSS = SPI_NSS_SOFT;
hspi.Init.NSS = SPI_NSS_SOFT;
// hspi.Init.NSS = SPI_NSS_HARD_OUTPUT;
}
if(cfg->max_hz >= HAL_RCC_GetPCLK2Freq()/2)
if (cfg->max_hz >= HAL_RCC_GetPCLK2Freq() / 2)
{
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
}
else if(cfg->max_hz >= HAL_RCC_GetPCLK2Freq()/4)
else if (cfg->max_hz >= HAL_RCC_GetPCLK2Freq() / 4)
{
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
}
else if(cfg->max_hz >= HAL_RCC_GetPCLK2Freq()/8)
else if (cfg->max_hz >= HAL_RCC_GetPCLK2Freq() / 8)
{
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
}
else if(cfg->max_hz >= HAL_RCC_GetPCLK2Freq()/16)
else if (cfg->max_hz >= HAL_RCC_GetPCLK2Freq() / 16)
{
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
}
else if(cfg->max_hz >= HAL_RCC_GetPCLK2Freq()/32)
else if (cfg->max_hz >= HAL_RCC_GetPCLK2Freq() / 32)
{
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
}
else if(cfg->max_hz >= HAL_RCC_GetPCLK2Freq()/64)
else if (cfg->max_hz >= HAL_RCC_GetPCLK2Freq() / 64)
{
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
}
else if(cfg->max_hz >= HAL_RCC_GetPCLK2Freq()/128)
else if (cfg->max_hz >= HAL_RCC_GetPCLK2Freq() / 128)
{
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;
}
else
{
/* min prescaler 256 */
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
/* min prescaler 256 */
hspi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
}
if (cfg->mode & RT_SPI_MSB)
{
@ -137,7 +137,7 @@ static rt_err_t stm32_spi_init(SPI_TypeDef *spix, struct rt_spi_configuration *c
hspi.Init.TIMode = SPI_TIMODE_DISABLE;
hspi.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi.Init.CRCPolynomial = 7;
hspi.State = HAL_SPI_STATE_RESET;
hspi.State = HAL_SPI_STATE_RESET;
if (HAL_SPI_Init(&hspi) != HAL_OK)
{
return RT_EIO;
@ -201,7 +201,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
struct stm32_spi * hspi = (struct stm32_spi *)device->bus->parent.user_data;
struct stm32_spi *hspi = (struct stm32_spi *)device->bus->parent.user_data;
struct stm32_hw_spi_cs *cs = device->parent.user_data;
if (message->cs_take)
@ -240,153 +240,143 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
rt_err_t spi_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
struct rt_spi_configuration *configuration)
{
struct stm32_spi * hspi = (struct stm32_spi *)device->bus->parent.user_data;
struct stm32_spi *hspi = (struct stm32_spi *)device->bus->parent.user_data;
hspi->cfg = configuration;
return stm32_spi_init(hspi->Instance, configuration);
}
const struct rt_spi_ops stm_spi_ops =
{
.configure = spi_configure,
.xfer = spixfer,
.configure = spi_configure,
.xfer = spixfer,
};
int stm32_spi_register_bus(SPI_TypeDef * SPIx,const char * name)
struct rt_spi_bus _spi_bus1, _spi_bus2;
struct stm32_spi _spi1, _spi2;
int stm32_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
{
struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)rt_malloc(sizeof(struct rt_spi_bus));
RT_ASSERT(spi_bus != RT_NULL);
struct stm32_spi * spi = (struct stm32_spi *)rt_malloc(sizeof(struct stm32_spi));
RT_ASSERT(spi != RT_NULL);
struct rt_spi_bus *spi_bus;
struct stm32_spi *spi;
if (SPIx == SPI1)
{
spi_bus = &_spi_bus1;
spi = &_spi1;
}
else if (SPIx == SPI2)
{
spi_bus = &_spi_bus2;
spi = &_spi2;
}
else
{
return -1;
}
spi->Instance = SPIx;
spi_bus->parent.user_data = spi;
return rt_spi_bus_register(spi_bus, name, &stm_spi_ops);
}
rt_err_t stm32_spi_bus_attach_device(rt_uint32_t pin,const char * bus_name,const char * device_name)
rt_err_t stm32_spi_bus_attach_device(rt_uint32_t pin, const char *bus_name, const char *device_name)
{
struct rt_spi_device * spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
RT_ASSERT(spi_device != RT_NULL);
struct stm32_hw_spi_cs * cs_pin = (struct stm32_hw_spi_cs *)rt_malloc(sizeof(struct stm32_hw_spi_cs));
struct stm32_hw_spi_cs *cs_pin = (struct stm32_hw_spi_cs *)rt_malloc(sizeof(struct stm32_hw_spi_cs));
RT_ASSERT(cs_pin != RT_NULL);
cs_pin->pin = pin;
rt_pin_mode(pin,PIN_MODE_OUTPUT);
rt_pin_mode(pin, PIN_MODE_OUTPUT);
rt_pin_write(pin, 1);
return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
}
int stm32_hw_spi_init(void)
{
stm32_spi_register_bus(SPI2,"spi2");
stm32_spi_bus_attach_device(33,"spi2","cs_b12");
return w25qxx_init("flash0","cs_b12");
int result = 0;
#ifdef RT_USING_SPI1
result = stm32_spi_register_bus(SPI1, "spi1");
#endif
#ifdef RT_USING_SPI2
result = stm32_spi_register_bus(SPI2, "spi2");
#endif
return result;
}
INIT_BOARD_EXPORT(stm32_hw_spi_init);
void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
void HAL_SPI_MspInit(SPI_HandleTypeDef *spiHandle)
{
GPIO_InitTypeDef GPIO_InitStruct;
if(spiHandle->Instance==SPI1)
{
/* USER CODE BEGIN SPI1_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct;
if (spiHandle->Instance == SPI1)
{
/* SPI1 clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**SPI1 GPIO Configuration
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_5 | GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE END SPI1_MspInit 0 */
/* SPI1 clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**SPI1 GPIO Configuration
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
}
else if (spiHandle->Instance == SPI2)
{
/* SPI2 clock enable */
__HAL_RCC_SPI2_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**SPI2 GPIO Configuration
PB13 ------> SPI2_SCK
PB14 ------> SPI2_MISO
PB15 ------> SPI2_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_13 | GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */
}
else if(spiHandle->Instance==SPI2)
{
/* USER CODE BEGIN SPI2_MspInit 0 */
/* USER CODE END SPI2_MspInit 0 */
/* SPI2 clock enable */
__HAL_RCC_SPI2_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**SPI2 GPIO Configuration
PB13 ------> SPI2_SCK
PB14 ------> SPI2_MISO
PB15 ------> SPI2_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_14;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN SPI2_MspInit 1 */
/* USER CODE END SPI2_MspInit 1 */
}
GPIO_InitStruct.Pin = GPIO_PIN_14;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
}
}
void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *spiHandle)
{
if(spiHandle->Instance==SPI1)
{
/* USER CODE BEGIN SPI1_MspDeInit 0 */
if (spiHandle->Instance == SPI1)
{
/* Peripheral clock disable */
__HAL_RCC_SPI1_CLK_DISABLE();
/* USER CODE END SPI1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SPI1_CLK_DISABLE();
/**SPI1 GPIO Configuration
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
/**SPI1 GPIO Configuration
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7);
}
else if (spiHandle->Instance == SPI2)
{
/* Peripheral clock disable */
__HAL_RCC_SPI2_CLK_DISABLE();
/* USER CODE BEGIN SPI1_MspDeInit 1 */
/* USER CODE END SPI1_MspDeInit 1 */
}
else if(spiHandle->Instance==SPI2)
{
/* USER CODE BEGIN SPI2_MspDeInit 0 */
/* USER CODE END SPI2_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SPI2_CLK_DISABLE();
/**SPI2 GPIO Configuration
PB13 ------> SPI2_SCK
PB14 ------> SPI2_MISO
PB15 ------> SPI2_MOSI
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15);
/* USER CODE BEGIN SPI2_MspDeInit 1 */
/* USER CODE END SPI2_MspDeInit 1 */
}
}
/**SPI2 GPIO Configuration
PB13 ------> SPI2_SCK
PB14 ------> SPI2_MISO
PB15 ------> SPI2_MOSI
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
}
}
#endif /*RT_USING_SPI*/

0
bsp/stm32f10x_HAL/drivers/stm32_spi.h → bsp/stm32f10x_HAL/drivers/drv_spi.h
View File

462
bsp/stm32f10x_HAL/drivers/drv_usart.c Normal file
View File

@ -0,0 +1,462 @@
/*
* File : drv_usart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2013, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard the first version
* 2010-03-29 Bernard remove interrupt Tx and DMA Rx mode
* 2013-05-13 aozima update for kehong-lingtai.
* 2015-01-31 armink make sure the serial transmit complete in putc()
* 2016-05-13 armink add DMA Rx mode
* 2017-01-19 aubr.cool add interrupt Tx mode
* 2017-04-13 aubr.cool correct Rx parity err
* 2017-10-20 ZYH porting to HAL Libraries(with out DMA)
* 2017-11-15 ZYH update to 3.0.0
*/
#include "board.h"
#include <rtdevice.h>
#include <drv_usart.h>
/* STM32 uart driver */
struct stm32_uart
{
UART_HandleTypeDef huart;
IRQn_Type irq;
};
static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = (struct stm32_uart *)serial->parent.user_data;
uart->huart.Init.BaudRate = cfg->baud_rate;
uart->huart.Init.HwFlowCtl = UART_HWCONTROL_NONE;
uart->huart.Init.Mode = UART_MODE_TX_RX;
uart->huart.Init.OverSampling = UART_OVERSAMPLING_16;
switch (cfg->data_bits)
{
case DATA_BITS_8:
uart->huart.Init.WordLength = UART_WORDLENGTH_8B;
break;
case DATA_BITS_9:
uart->huart.Init.WordLength = UART_WORDLENGTH_9B;
break;
default:
uart->huart.Init.WordLength = UART_WORDLENGTH_8B;
break;
}
switch (cfg->stop_bits)
{
case STOP_BITS_1:
uart->huart.Init.StopBits = UART_STOPBITS_1;
break;
case STOP_BITS_2:
uart->huart.Init.StopBits = UART_STOPBITS_2;
break;
default:
uart->huart.Init.StopBits = UART_STOPBITS_1;
break;
}
switch (cfg->parity)
{
case PARITY_NONE:
uart->huart.Init.Parity = UART_PARITY_NONE;
break;
case PARITY_ODD:
uart->huart.Init.Parity = UART_PARITY_ODD;
break;
case PARITY_EVEN:
uart->huart.Init.Parity = UART_PARITY_EVEN;
break;
default:
uart->huart.Init.Parity = UART_PARITY_NONE;
break;
}
if (HAL_UART_Init(&uart->huart) != HAL_OK)
{
return RT_ERROR;
}
return RT_EOK;
}
static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct stm32_uart *uart;
// rt_uint32_t ctrl_arg = (rt_uint32_t)(arg);
RT_ASSERT(serial != RT_NULL);
uart = (struct stm32_uart *)serial->parent.user_data;
switch (cmd)
{
/* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
NVIC_DisableIRQ(uart->irq);
/* disable interrupt */
__HAL_UART_DISABLE_IT(&uart->huart, USART_IT_RXNE);
break;
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
NVIC_EnableIRQ(uart->irq);
/* enable interrupt */
__HAL_UART_ENABLE_IT(&uart->huart, USART_IT_RXNE);
break;
}
return RT_EOK;
}
static int stm32_putc(struct rt_serial_device *serial, char c)
{
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct stm32_uart *)serial->parent.user_data;
while (__HAL_UART_GET_FLAG(&uart->huart, UART_FLAG_TXE) == RESET);
uart->huart.Instance->DR = c;
return 1;
}
static int stm32_getc(struct rt_serial_device *serial)
{
int ch;
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct stm32_uart *)serial->parent.user_data;
ch = -1;
if (__HAL_UART_GET_FLAG(&uart->huart, UART_FLAG_RXNE) != RESET)
{
ch = uart->huart.Instance->DR & 0xff;
}
return ch;
}
/**
* Uart common interrupt process. This need add to uart ISR.
*
* @param serial serial device
*/
static void uart_isr(struct rt_serial_device *serial)
{
struct stm32_uart *uart = (struct stm32_uart *) serial->parent.user_data;
RT_ASSERT(uart != RT_NULL);
if ((__HAL_UART_GET_FLAG(&uart->huart, UART_FLAG_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(&uart->huart, UART_IT_RXNE) != RESET))
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
__HAL_UART_CLEAR_FLAG(&uart->huart, UART_FLAG_RXNE);
}
}
static const struct rt_uart_ops stm32_uart_ops =
{
stm32_configure,
stm32_control,
stm32_putc,
stm32_getc,
};
#if defined(RT_USING_UART1)
/* UART1 device driver structure */
struct stm32_uart uart1 =
{
{USART1},
USART1_IRQn
};
struct rt_serial_device serial1;
void USART1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&serial1);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* RT_USING_UART1 */
#if defined(RT_USING_UART2)
/* UART1 device driver structure */
struct stm32_uart uart2 =
{
{USART2},
USART2_IRQn
};
struct rt_serial_device serial2;
void USART2_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&serial2);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* RT_USING_UART2 */
#if defined(RT_USING_UART3)
/* UART1 device driver structure */
struct stm32_uart uart3 =
{
{USART3},
USART3_IRQn
};
struct rt_serial_device serial3;
void USART3_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&serial3);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* RT_USING_UART2 */
static void MX_USART_UART_Init(UART_HandleTypeDef *uartHandle);
int rt_hw_usart_init(void)
{
struct stm32_uart *uart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
#if defined(RT_USING_UART1)
uart = &uart1;
config.baud_rate = BAUD_RATE_115200;
serial1.ops = &stm32_uart_ops;
serial1.config = config;
MX_USART_UART_Init(&uart->huart);
/* register UART1 device */
rt_hw_serial_register(&serial1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX ,
uart);
#endif /* RT_USING_UART1 */
#if defined(RT_USING_UART2)
uart = &uart2;
config.baud_rate = BAUD_RATE_115200;
serial2.ops = &stm32_uart_ops;
serial2.config = config;
MX_USART_UART_Init(&uart->huart);
/* register UART1 device */
rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX ,
uart);
#endif /* RT_USING_UART1 */
#if defined(RT_USING_UART3)
uart = &uart3;
config.baud_rate = BAUD_RATE_115200;
serial3.ops = &stm32_uart_ops;
serial3.config = config;
MX_USART_UART_Init(&uart->huart);
/* register UART1 device */
rt_hw_serial_register(&serial3, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX ,
uart);
#endif /* RT_USING_UART1 */
return 0;
}
INIT_BOARD_EXPORT(rt_hw_usart_init);
static void MX_USART_UART_Init(UART_HandleTypeDef *uartHandle)
{
uartHandle->Init.BaudRate = 115200;
uartHandle->Init.WordLength = UART_WORDLENGTH_8B;
uartHandle->Init.StopBits = UART_STOPBITS_1;
uartHandle->Init.Parity = UART_PARITY_NONE;
uartHandle->Init.Mode = UART_MODE_TX_RX;
uartHandle->Init.HwFlowCtl = UART_HWCONTROL_NONE;
uartHandle->Init.OverSampling = UART_OVERSAMPLING_16;
RT_ASSERT(HAL_UART_Init(uartHandle) == HAL_OK);
}
/* USART2 init function */
void HAL_UART_MspInit(UART_HandleTypeDef *uartHandle)
{
GPIO_InitTypeDef GPIO_InitStruct;
if (uartHandle->Instance == USART1)
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* USART1 clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USART1 interrupt Init */
HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(USART1_IRQn);
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
else if (uartHandle->Instance == USART2)
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* USART2 clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USART2 interrupt Init */
HAL_NVIC_SetPriority(USART2_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(USART2_IRQn);
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
else if (uartHandle->Instance == USART3)
{
/* USER CODE BEGIN USART3_MspInit 0 */
/* USER CODE END USART3_MspInit 0 */
/* USART3 clock enable */
__HAL_RCC_USART3_CLK_ENABLE();
/**USART3 GPIO Configuration
PB10 ------> USART3_TX
PB11 ------> USART3_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USART3 interrupt Init */
HAL_NVIC_SetPriority(USART3_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(USART3_IRQn);
/* USER CODE BEGIN USART3_MspInit 1 */
/* USER CODE END USART3_MspInit 1 */
}
}
void HAL_UART_MspDeInit(UART_HandleTypeDef *uartHandle)
{
if (uartHandle->Instance == USART1)
{
/* USER CODE BEGIN USART1_MspDeInit 0 */
/* USER CODE END USART1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART1_CLK_DISABLE();
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9 | GPIO_PIN_10);
/* USART1 interrupt Deinit */
HAL_NVIC_DisableIRQ(USART1_IRQn);
/* USER CODE BEGIN USART1_MspDeInit 1 */
/* USER CODE END USART1_MspDeInit 1 */
}
else if (uartHandle->Instance == USART2)
{
/* USER CODE BEGIN USART2_MspDeInit 0 */
/* USER CODE END USART2_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART2_CLK_DISABLE();
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2 | GPIO_PIN_3);
/* USART2 interrupt Deinit */
HAL_NVIC_DisableIRQ(USART2_IRQn);
/* USER CODE BEGIN USART2_MspDeInit 1 */
/* USER CODE END USART2_MspDeInit 1 */
}
else if (uartHandle->Instance == USART3)
{
/* USER CODE BEGIN USART3_MspDeInit 0 */
/* USER CODE END USART3_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART3_CLK_DISABLE();
/**USART3 GPIO Configuration
PB10 ------> USART3_TX
PB11 ------> USART3_RX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10 | GPIO_PIN_11);
/* USART3 interrupt Deinit */
HAL_NVIC_DisableIRQ(USART3_IRQn);
/* USER CODE BEGIN USART3_MspDeInit 1 */
/* USER CODE END USART3_MspDeInit 1 */
}
}

2
bsp/stm32f10x_HAL/drivers/usart.h → bsp/stm32f10x_HAL/drivers/drv_usart.h
View File

@ -17,6 +17,6 @@
#include <rthw.h>
#include <rtthread.h>
void rt_hw_usart_init(void);
int rt_hw_usart_init(void);
#endif

276
bsp/stm32f10x_HAL/drivers/drv_usb.c Normal file
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@ -0,0 +1,276 @@
/*
* File : drv_usb.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2015, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2017-10-30 ZYH the first version
* 2017-11-15 ZYH update to 3.0.0
*/
#include "drv_usb.h"
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#define USB_DISCONNECT_PIN 30 //PA9
static PCD_HandleTypeDef _stm_pcd;
static struct udcd _stm_udc;
static struct ep_id _ep_pool[] =
{
{0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED },
{0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED},
{0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED},
{0x2, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED},
{0x2, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED},
{0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED },
};
void USB_LP_CAN1_RX0_IRQHandler(void)
{
rt_interrupt_enter();
HAL_PCD_IRQHandler(&_stm_pcd);
rt_interrupt_leave();
}
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *pcd)
{
/* open ep0 OUT and IN */
HAL_PCD_EP_Open(pcd, 0x00, 0x40, EP_TYPE_CTRL);
HAL_PCD_EP_Open(pcd, 0x80, 0x40, EP_TYPE_CTRL);
rt_usbd_reset_handler(&_stm_udc);
}
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
rt_usbd_ep0_setup_handler(&_stm_udc, (struct urequest*)hpcd->Setup);
}
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
if (epnum == 0)
{
rt_usbd_ep0_in_handler(&_stm_udc);
}
else
{
rt_usbd_ep_in_handler(&_stm_udc, 0x80|epnum,hpcd->IN_ep[epnum].xfer_count);
}
}
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
rt_usbd_connect_handler(&_stm_udc);
}
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
// rt_usbd_sof_handler(&_stm_udc);
}
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
rt_usbd_disconnect_handler(&_stm_udc);
}
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
if (epnum != 0)
{
rt_usbd_ep_out_handler(&_stm_udc, epnum, hpcd->OUT_ep[epnum].xfer_count);
}
else
{
rt_usbd_ep0_out_handler(&_stm_udc,hpcd->OUT_ep[0].xfer_count);
}
}
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
{
if(state == 1)
{
rt_pin_write(USB_DISCONNECT_PIN,PIN_HIGH);
}
else
{
rt_pin_write(USB_DISCONNECT_PIN,PIN_LOW);
}
}
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
{
if(pcdHandle->Instance==USB)
{
__HAL_RCC_GPIOA_CLK_ENABLE();
rt_pin_mode(USB_DISCONNECT_PIN,PIN_MODE_OUTPUT);
rt_pin_write(USB_DISCONNECT_PIN,PIN_LOW);
/* Peripheral clock enable */
__HAL_RCC_USB_CLK_ENABLE();
/* Peripheral interrupt init */
HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
}
}
void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
{
if(pcdHandle->Instance==USB)
{
/* Peripheral clock disable */
__HAL_RCC_USB_CLK_DISABLE();
/* Peripheral interrupt Deinit*/
HAL_NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);
}
}
static rt_err_t _ep_set_stall(rt_uint8_t address)
{
HAL_PCD_EP_SetStall(&_stm_pcd, address);
return RT_EOK;
}
static rt_err_t _ep_clear_stall(rt_uint8_t address)
{
HAL_PCD_EP_ClrStall(&_stm_pcd, address);
return RT_EOK;
}
static rt_err_t _set_address(rt_uint8_t address)
{
HAL_PCD_SetAddress(&_stm_pcd, address);
return RT_EOK;
}
static rt_err_t _set_config(rt_uint8_t address)
{
return RT_EOK;
}
static rt_err_t _ep_enable(uep_t ep)
{
RT_ASSERT(ep != RT_NULL);
RT_ASSERT(ep->ep_desc != RT_NULL);
HAL_PCD_EP_Open(&_stm_pcd, ep->ep_desc->bEndpointAddress,
ep->ep_desc->wMaxPacketSize, ep->ep_desc->bmAttributes);
return RT_EOK;
}
static rt_err_t _ep_disable(uep_t ep)
{
RT_ASSERT(ep != RT_NULL);
RT_ASSERT(ep->ep_desc != RT_NULL);
HAL_PCD_EP_Close(&_stm_pcd, ep->ep_desc->bEndpointAddress);
return RT_EOK;
}
static rt_size_t _ep_read(rt_uint8_t address, void *buffer)
{
rt_size_t size = 0;
RT_ASSERT(buffer != RT_NULL);
return size;
}
static rt_size_t _ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size)
{
HAL_PCD_EP_Receive(&_stm_pcd, address, buffer, size);
return size;
}
static rt_size_t _ep_write(rt_uint8_t address, void *buffer, rt_size_t size)
{
HAL_PCD_EP_Transmit(&_stm_pcd, address, buffer, size);
return size;
}
static rt_err_t _ep0_send_status(void)
{
HAL_PCD_EP_Transmit(&_stm_pcd, 0x00, NULL, 0);
return RT_EOK;
}
static rt_err_t _suspend(void)
{
return RT_EOK;
}
static rt_err_t _wakeup(void)
{
return RT_EOK;
}
static rt_err_t _init(rt_device_t device)
{
PCD_HandleTypeDef *pcd;
/* Set LL Driver parameters */
pcd = (PCD_HandleTypeDef*)device->user_data;
pcd->Instance = USB;
pcd->Init.dev_endpoints = 8;
pcd->Init.speed = PCD_SPEED_FULL;
pcd->Init.ep0_mps = DEP0CTL_MPS_8;
pcd->Init.low_power_enable = DISABLE;
pcd->Init.lpm_enable = DISABLE;
pcd->Init.battery_charging_enable = DISABLE;
/* Initialize LL Driver */
HAL_PCD_Init(pcd);
HAL_PCDEx_PMAConfig(pcd , 0x00 , PCD_SNG_BUF, 0x18);
HAL_PCDEx_PMAConfig(pcd , 0x80 , PCD_SNG_BUF, 0x58);
HAL_PCDEx_PMAConfig(pcd , 0x81 , PCD_SNG_BUF, 0x98);
HAL_PCDEx_PMAConfig(pcd , 0x01 , PCD_SNG_BUF, 0x118);
HAL_PCDEx_PMAConfig(pcd , 0x82 , PCD_SNG_BUF, 0xD8);
HAL_PCDEx_PMAConfig(pcd , 0x02 , PCD_SNG_BUF, 0x158);
HAL_PCD_Start(pcd);
return RT_EOK;
}
const static struct udcd_ops _udc_ops =
{
_set_address,
_set_config,
_ep_set_stall,
_ep_clear_stall,
_ep_enable,
_ep_disable,
_ep_read_prepare,
_ep_read,
_ep_write,
_ep0_send_status,
_suspend,
_wakeup,
};
int stm_usbd_register(void)
{
rt_memset((void *)&_stm_udc, 0, sizeof(struct udcd));
_stm_udc.parent.type = RT_Device_Class_USBDevice;
_stm_udc.parent.init = _init;
_stm_udc.parent.user_data = &_stm_pcd;
_stm_udc.ops = &_udc_ops;
/* Register endpoint infomation */
_stm_udc.ep_pool = _ep_pool;
_stm_udc.ep0.id = &_ep_pool[0];
rt_device_register((rt_device_t)&_stm_udc, "usbd", 0);
rt_usb_device_init();
return 0;
}
INIT_DEVICE_EXPORT(stm_usbd_register);

20
bsp/stm32f10x_HAL/drivers/drv_usb.h Normal file
View File

@ -0,0 +1,20 @@
/*
* File : drv_usb.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2015, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2017-10-30 ZYH the first version
*/
#ifndef __STM32_USB_H__
#define __STM32_USB_H__
#include <rtthread.h>
int stm_usbd_register(void);
#endif

856
bsp/stm32f10x_HAL/drivers/gpio.c
View File

@ -1,856 +0,0 @@
/*
* File : gpio.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2015, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2017-10-20 ZYH the first version
*/
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
#ifdef RT_USING_PIN
#define STM32F10X_PIN_NUMBERS 64 //[48, 64, 100, 144 ]
#define __STM32_PIN(index, gpio, gpio_index) \
{ \
index, GPIO##gpio##_CLK_ENABLE, GPIO##gpio, GPIO_PIN_##gpio_index \
}
#define __STM32_PIN_DEFAULT \
{ \
-1, 0, 0, 0 \
}
static void GPIOA_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOA_CLK_ENABLE
__HAL_RCC_GPIOA_CLK_ENABLE();
#endif
}
static void GPIOB_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOB_CLK_ENABLE
__HAL_RCC_GPIOB_CLK_ENABLE();
#endif
}
static void GPIOC_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOC_CLK_ENABLE
__HAL_RCC_GPIOC_CLK_ENABLE();
#endif
}
#if (STM32F10X_PIN_NUMBERS !=48)
static void GPIOD_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOD_CLK_ENABLE
__HAL_RCC_GPIOD_CLK_ENABLE();
#endif
}
#if (STM32F10X_PIN_NUMBERS !=64)
static void GPIOE_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOE_CLK_ENABLE
__HAL_RCC_GPIOE_CLK_ENABLE();
#endif
}
static void GPIOF_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOF_CLK_ENABLE
__HAL_RCC_GPIOF_CLK_ENABLE();
#endif
}
static void GPIOG_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOG_CLK_ENABLE
__HAL_RCC_GPIOG_CLK_ENABLE();
#endif
}
static void GPIOH_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOH_CLK_ENABLE
__HAL_RCC_GPIOH_CLK_ENABLE();
#endif
}
#endif
#endif
/* STM32 GPIO driver */
struct pin_index
{
int index;
void (*rcc)(void);
GPIO_TypeDef *gpio;
uint32_t pin;
};
static const struct pin_index pins[] =
{
#if (STM32F10X_PIN_NUMBERS == 48)
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(2, C, 13),
__STM32_PIN(3, C, 14),
__STM32_PIN(4, C, 15),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(10, A, 0),
__STM32_PIN(11, A, 1),
__STM32_PIN(12, A, 2),
__STM32_PIN(13, A, 3),
__STM32_PIN(14, A, 4),
__STM32_PIN(15, A, 5),
__STM32_PIN(16, A, 6),
__STM32_PIN(17, A, 7),
__STM32_PIN(18, B, 0),
__STM32_PIN(19, B, 1),
__STM32_PIN(20, B, 2),
__STM32_PIN(21, B, 10),
__STM32_PIN(22, B, 11),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(25, B, 12),
__STM32_PIN(26, B, 13),
__STM32_PIN(27, B, 14),
__STM32_PIN(28, B, 15),
__STM32_PIN(29, A, 8),
__STM32_PIN(30, A, 9),
__STM32_PIN(31, A, 10),
__STM32_PIN(32, A, 11),
__STM32_PIN(33, A, 12),
__STM32_PIN(34, A, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(37, A, 14),
__STM32_PIN(38, A, 15),
__STM32_PIN(39, B, 3),
__STM32_PIN(40, B, 4),
__STM32_PIN(41, B, 5),
__STM32_PIN(42, B, 6),
__STM32_PIN(43, B, 7),
__STM32_PIN_DEFAULT,
__STM32_PIN(45, B, 8),
__STM32_PIN(46, B, 9),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
#endif
#if (STM32F10X_PIN_NUMBERS == 64)
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(2, C, 13),
__STM32_PIN(3, C, 14),
__STM32_PIN(4, C, 15),
__STM32_PIN(5, D, 0),
__STM32_PIN(6, D, 1),
__STM32_PIN_DEFAULT,
__STM32_PIN(8, C, 0),
__STM32_PIN(9, C, 1),
__STM32_PIN(10, C, 2),
__STM32_PIN(11, C, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(14, A, 0),
__STM32_PIN(15, A, 1),
__STM32_PIN(16, A, 2),
__STM32_PIN(17, A, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(20, A, 4),
__STM32_PIN(21, A, 5),
__STM32_PIN(22, A, 6),
__STM32_PIN(23, A, 7),
__STM32_PIN(24, C, 4),
__STM32_PIN(25, C, 5),
__STM32_PIN(26, B, 0),
__STM32_PIN(27, B, 1),
__STM32_PIN(28, B, 2),
__STM32_PIN(29, B, 10),
__STM32_PIN(30, B, 11),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(33, B, 12),
__STM32_PIN(34, B, 13),
__STM32_PIN(35, B, 14),
__STM32_PIN(36, B, 15),
__STM32_PIN(37, C, 6),
__STM32_PIN(38, C, 7),
__STM32_PIN(39, C, 8),
__STM32_PIN(40, C, 9),
__STM32_PIN(41, A, 8),
__STM32_PIN(42, A, 9),
__STM32_PIN(43, A, 10),
__STM32_PIN(44, A, 11),
__STM32_PIN(45, A, 12),
__STM32_PIN(46, A, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(49, A, 14),
__STM32_PIN(50, A, 15),
__STM32_PIN(51, C, 10),
__STM32_PIN(52, C, 11),
__STM32_PIN(53, C, 12),
__STM32_PIN(54, D, 2),
__STM32_PIN(55, B, 3),
__STM32_PIN(56, B, 4),
__STM32_PIN(57, B, 5),
__STM32_PIN(58, B, 6),
__STM32_PIN(59, B, 7),
__STM32_PIN_DEFAULT,
__STM32_PIN(61, B, 8),
__STM32_PIN(62, B, 9),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
#endif
#if (STM32F10X_PIN_NUMBERS == 100)
__STM32_PIN_DEFAULT,
__STM32_PIN(1, E, 2),
__STM32_PIN(2, E, 3),
__STM32_PIN(3, E, 4),
__STM32_PIN(4, E, 5),
__STM32_PIN(5, E, 6),
__STM32_PIN_DEFAULT,
__STM32_PIN(7, C, 13),
__STM32_PIN(8, C, 14),
__STM32_PIN(9, C, 15),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(15, C, 0),
__STM32_PIN(16, C, 1),
__STM32_PIN(17, C, 2),
__STM32_PIN(18, C, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(23, A, 0),
__STM32_PIN(24, A, 1),
__STM32_PIN(25, A, 2),
__STM32_PIN(26, A, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(29, A, 4),
__STM32_PIN(30, A, 5),
__STM32_PIN(31, A, 6),
__STM32_PIN(32, A, 7),
__STM32_PIN(33, C, 4),
__STM32_PIN(34, C, 5),
__STM32_PIN(35, B, 0),
__STM32_PIN(36, B, 1),
__STM32_PIN(37, B, 2),
__STM32_PIN(38, E, 7),
__STM32_PIN(39, E, 8),
__STM32_PIN(40, E, 9),
__STM32_PIN(41, E, 10),
__STM32_PIN(42, E, 11),
__STM32_PIN(43, E, 12),
__STM32_PIN(44, E, 13),
__STM32_PIN(45, E, 14),
__STM32_PIN(46, E, 15),
__STM32_PIN(47, B, 10),
__STM32_PIN(48, B, 11),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(51, B, 12),
__STM32_PIN(52, B, 13),
__STM32_PIN(53, B, 14),
__STM32_PIN(54, B, 15),
__STM32_PIN(55, D, 8),
__STM32_PIN(56, D, 9),
__STM32_PIN(57, D, 10),
__STM32_PIN(58, D, 11),
__STM32_PIN(59, D, 12),
__STM32_PIN(60, D, 13),
__STM32_PIN(61, D, 14),
__STM32_PIN(62, D, 15),
__STM32_PIN(63, C, 6),
__STM32_PIN(64, C, 7),
__STM32_PIN(65, C, 8),
__STM32_PIN(66, C, 9),
__STM32_PIN(67, A, 8),
__STM32_PIN(68, A, 9),
__STM32_PIN(69, A, 10),
__STM32_PIN(70, A, 11),
__STM32_PIN(71, A, 12),
__STM32_PIN(72, A, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(76, A, 14),
__STM32_PIN(77, A, 15),
__STM32_PIN(78, C, 10),
__STM32_PIN(79, C, 11),
__STM32_PIN(80, C, 12),
__STM32_PIN(81, D, 0),
__STM32_PIN(82, D, 1),
__STM32_PIN(83, D, 2),
__STM32_PIN(84, D, 3),
__STM32_PIN(85, D, 4),
__STM32_PIN(86, D, 5),
__STM32_PIN(87, D, 6),
__STM32_PIN(88, D, 7),
__STM32_PIN(89, B, 3),
__STM32_PIN(90, B, 4),
__STM32_PIN(91, B, 5),
__STM32_PIN(92, B, 6),
__STM32_PIN(93, B, 7),
__STM32_PIN_DEFAULT,
__STM32_PIN(95, B, 8),
__STM32_PIN(96, B, 9),
__STM32_PIN(97, E, 0),
__STM32_PIN(98, E, 1),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
#endif
#if (STM32F10X_PIN_NUMBERS == 144)
__STM32_PIN_DEFAULT,
__STM32_PIN(1, E, 2),
__STM32_PIN(2, E, 3),
__STM32_PIN(3, E, 4),
__STM32_PIN(4, E, 5),
__STM32_PIN(5, E, 6),
__STM32_PIN_DEFAULT,
__STM32_PIN(7, C, 13),
__STM32_PIN(8, C, 14),
__STM32_PIN(9, C, 15),
__STM32_PIN(10, F, 0),
__STM32_PIN(11, F, 1),
__STM32_PIN(12, F, 2),
__STM32_PIN(13, F, 3),
__STM32_PIN(14, F, 4),
__STM32_PIN(15, F, 5),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(18, F, 6),
__STM32_PIN(19, F, 7),
__STM32_PIN(20, F, 8),
__STM32_PIN(21, F, 9),
__STM32_PIN(22, F, 10),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(26, C, 0),
__STM32_PIN(27, C, 1),
__STM32_PIN(28, C, 2),
__STM32_PIN(29, C, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(34, A, 0),
__STM32_PIN(35, A, 1),
__STM32_PIN(36, A, 2),
__STM32_PIN(37, A, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(40, A, 4),
__STM32_PIN(41, A, 5),
__STM32_PIN(42, A, 6),
__STM32_PIN(43, A, 7),
__STM32_PIN(44, C, 4),
__STM32_PIN(45, C, 5),
__STM32_PIN(46, B, 0),
__STM32_PIN(47, B, 1),
__STM32_PIN(48, B, 2),
__STM32_PIN(49, F, 11),
__STM32_PIN(50, F, 12),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(53, F, 13),
__STM32_PIN(54, F, 14),
__STM32_PIN(55, F, 15),
__STM32_PIN(56, G, 0),
__STM32_PIN(57, G, 1),
__STM32_PIN(58, E, 7),
__STM32_PIN(59, E, 8),
__STM32_PIN(60, E, 9),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(63, E, 10),
__STM32_PIN(64, E, 11),
__STM32_PIN(65, E, 12),
__STM32_PIN(66, E, 13),
__STM32_PIN(67, E, 14),
__STM32_PIN(68, E, 15),
__STM32_PIN(69, B, 10),
__STM32_PIN(70, B, 11),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(73, B, 12),
__STM32_PIN(74, B, 13),
__STM32_PIN(75, B, 14),
__STM32_PIN(76, B, 15),
__STM32_PIN(77, D, 8),
__STM32_PIN(78, D, 9),
__STM32_PIN(79, D, 10),
__STM32_PIN(80, D, 11),
__STM32_PIN(81, D, 12),
__STM32_PIN(82, D, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(85, D, 14),
__STM32_PIN(86, D, 15),
__STM32_PIN(87, G, 2),
__STM32_PIN(88, G, 3),
__STM32_PIN(89, G, 4),
__STM32_PIN(90, G, 5),
__STM32_PIN(91, G, 6),
__STM32_PIN(92, G, 7),
__STM32_PIN(93, G, 8),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(96, C, 6),
__STM32_PIN(97, C, 7),
__STM32_PIN(98, C, 8),
__STM32_PIN(99, C, 9),
__STM32_PIN(100, A, 8),
__STM32_PIN(101, A, 9),
__STM32_PIN(102, A, 10),
__STM32_PIN(103, A, 11),
__STM32_PIN(104, A, 12),
__STM32_PIN(105, A, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(109, A, 14),
__STM32_PIN(110, A, 15),
__STM32_PIN(111, C, 10),
__STM32_PIN(112, C, 11),
__STM32_PIN(113, C, 12),
__STM32_PIN(114, D, 0),
__STM32_PIN(115, D, 1),
__STM32_PIN(116, D, 2),
__STM32_PIN(117, D, 3),
__STM32_PIN(118, D, 4),
__STM32_PIN(119, D, 5),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(122, D, 6),
__STM32_PIN(123, D, 7),
__STM32_PIN(124, G, 9),
__STM32_PIN(125, G, 10),
__STM32_PIN(126, G, 11),
__STM32_PIN(127, G, 12),
__STM32_PIN(128, G, 13),
__STM32_PIN(129, G, 14),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(132, G, 15),
__STM32_PIN(133, B, 3),
__STM32_PIN(134, B, 4),
__STM32_PIN(135, B, 5),
__STM32_PIN(136, B, 6),
__STM32_PIN(137, B, 7),
__STM32_PIN_DEFAULT,
__STM32_PIN(139, B, 8),
__STM32_PIN(140, B, 9),
__STM32_PIN(141, E, 0),
__STM32_PIN(142, E, 1),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
#endif
};
struct pin_irq_map
{
rt_uint16_t pinbit;
IRQn_Type irqno;
};
static const struct pin_irq_map pin_irq_map[] =
{
{GPIO_PIN_0, EXTI0_IRQn},
{GPIO_PIN_1, EXTI1_IRQn},
{GPIO_PIN_2, EXTI2_IRQn},
{GPIO_PIN_3, EXTI3_IRQn},
{GPIO_PIN_4, EXTI4_IRQn},
{GPIO_PIN_5, EXTI9_5_IRQn},
{GPIO_PIN_6, EXTI9_5_IRQn},
{GPIO_PIN_7, EXTI9_5_IRQn},
{GPIO_PIN_8, EXTI9_5_IRQn},
{GPIO_PIN_9, EXTI9_5_IRQn},
{GPIO_PIN_10, EXTI15_10_IRQn},
{GPIO_PIN_11, EXTI15_10_IRQn},
{GPIO_PIN_12, EXTI15_10_IRQn},
{GPIO_PIN_13, EXTI15_10_IRQn},
{GPIO_PIN_14, EXTI15_10_IRQn},
{GPIO_PIN_15, EXTI15_10_IRQn},
};
struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
};
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
const struct pin_index *get_pin(uint8_t pin)
{
const struct pin_index *index;
if (pin < ITEM_NUM(pins))
{
index = &pins[pin];
if (index->index == -1)
index = RT_NULL;
}
else
{
index = RT_NULL;
}
return index;
};
void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
const struct pin_index *index;
index = get_pin(pin);
if (index == RT_NULL)
{
return;
}
HAL_GPIO_WritePin(index->gpio, index->pin, (GPIO_PinState)value);
}
int stm32_pin_read(rt_device_t dev, rt_base_t pin)
{
int value;
const struct pin_index *index;
value = PIN_LOW;
index = get_pin(pin);
if (index == RT_NULL)
{
return value;
}
value = HAL_GPIO_ReadPin(index->gpio, index->pin);
return value;
}
void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
const struct pin_index *index;
GPIO_InitTypeDef GPIO_InitStruct;
index = get_pin(pin);
if (index == RT_NULL)
{
return;
}
/* GPIO Periph clock enable */
index->rcc();
/* Configure GPIO_InitStructure */
GPIO_InitStruct.Pin = index->pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
if (mode == PIN_MODE_OUTPUT)
{
/* output setting */
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
}
else if (mode == PIN_MODE_INPUT)
{
/* input setting: not pull. */
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
}
else if (mode == PIN_MODE_INPUT_PULLUP)
{
/* input setting: pull up. */
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_PULLUP;
}
else if (mode == PIN_MODE_INPUT_PULLDOWN)
{
/* input setting: pull down. */
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
}
else if (mode == PIN_MODE_OUTPUT_OD)
{
/* output setting: od. */
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
GPIO_InitStruct.Pull = GPIO_NOPULL;
}
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
}
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
{
int i;
for (i = 0; i < 32; i++)
{
if ((0x01 << i) == bit)
{
return i;
}
}
return -1;
}
rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
{
rt_int32_t mapindex = bit2bitno(pinbit);
if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
{
return RT_NULL;
}
return &pin_irq_map[mapindex];
};
rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
const struct pin_index *index;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == pin &&
pin_irq_hdr_tab[irqindex].hdr == hdr &&
pin_irq_hdr_tab[irqindex].mode == mode &&
pin_irq_hdr_tab[irqindex].args == args)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
if (pin_irq_hdr_tab[irqindex].pin != -1)
{
rt_hw_interrupt_enable(level);
return RT_EBUSY;
}
pin_irq_hdr_tab[irqindex].pin = pin;
pin_irq_hdr_tab[irqindex].hdr = hdr;
pin_irq_hdr_tab[irqindex].mode = mode;
pin_irq_hdr_tab[irqindex].args = args;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
{
const struct pin_index *index;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
pin_irq_hdr_tab[irqindex].pin = -1;
pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
pin_irq_hdr_tab[irqindex].mode = 0;
pin_irq_hdr_tab[irqindex].args = RT_NULL;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled)
{
const struct pin_index *index;
const struct pin_irq_map *irqmap;
rt_base_t level;
rt_int32_t irqindex = -1;
GPIO_InitTypeDef GPIO_InitStruct;
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_ENOSYS;
}
if (enabled == PIN_IRQ_ENABLE)
{
irqindex = bit2bitno(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_ENOSYS;
}
irqmap = &pin_irq_map[irqindex];
/* GPIO Periph clock enable */
index->rcc();
/* Configure GPIO_InitStructure */
GPIO_InitStruct.Pin = index->pin;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
switch (pin_irq_hdr_tab[irqindex].mode)
{
case PIN_IRQ_MODE_RISING:
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
break;
case PIN_IRQ_MODE_FALLING:
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
break;
case PIN_IRQ_MODE_RISING_FALLING:
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
break;
}
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
HAL_NVIC_SetPriority(irqmap->irqno, 5, 0);
HAL_NVIC_EnableIRQ(irqmap->irqno);
rt_hw_interrupt_enable(level);
}
else if (enabled == PIN_IRQ_DISABLE)
{
irqmap = get_pin_irq_map(index->pin);
if (irqmap == RT_NULL)
{
return RT_ENOSYS;
}
HAL_NVIC_DisableIRQ(irqmap->irqno);
}
else
{
return RT_ENOSYS;
}
return RT_EOK;
}
const static struct rt_pin_ops _stm32_pin_ops =
{
stm32_pin_mode,
stm32_pin_write,
stm32_pin_read,
stm32_pin_attach_irq,
stm32_pin_dettach_irq,
stm32_pin_irq_enable,
};
int rt_hw_pin_init(void)
{
int result;
result = rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL);
return result;
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
rt_inline void pin_irq_hdr(int irqno)
{
if (pin_irq_hdr_tab[irqno].hdr)
{
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
}
}
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
pin_irq_hdr(bit2bitno(GPIO_Pin));
}
void EXTI0_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
rt_interrupt_leave();
}
void EXTI1_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
rt_interrupt_leave();
}
void EXTI2_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
rt_interrupt_leave();
}
void EXTI3_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
rt_interrupt_leave();
}
void EXTI4_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
rt_interrupt_leave();
}
void EXTI9_5_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
rt_interrupt_leave();
}
void EXTI15_10_IRQHandler(void)
{
rt_interrupt_enter();
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
rt_interrupt_leave();
}
#endif

32
bsp/stm32f10x_HAL/drivers/stm32f1xx_hal_conf.h
View File

@ -55,18 +55,17 @@
/**
* @brief This is the list of modules to be used in the HAL driver
*/
// defined in rtconfig.h
// #define HAL_MODULE_ENABLED
#define HAL_MODULE_ENABLED
// #define HAL_ADC_MODULE_ENABLED
// #define HAL_CAN_MODULE_ENABLED
// #define HAL_CEC_MODULE_ENABLED
// #define HAL_CORTEX_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
// #define HAL_CRC_MODULE_ENABLED
// #define HAL_DAC_MODULE_ENABLED
// #define HAL_DMA_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
// #define HAL_ETH_MODULE_ENABLED
// #define HAL_FLASH_MODULE_ENABLED
// #define HAL_GPIO_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
// #define HAL_HCD_MODULE_ENABLED
// #define HAL_I2C_MODULE_ENABLED
// #define HAL_I2S_MODULE_ENABLED
@ -75,17 +74,24 @@
// #define HAL_NAND_MODULE_ENABLED
// #define HAL_NOR_MODULE_ENABLED
// #define HAL_PCCARD_MODULE_ENABLED
// #define HAL_PCD_MODULE_ENABLED
// #define HAL_PWR_MODULE_ENABLED
// #define HAL_RCC_MODULE_ENABLED
#ifdef RT_USING_USB_DEVICE
#define HAL_PCD_MODULE_ENABLED
#endif
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
// #define HAL_RTC_MODULE_ENABLED
// #define HAL_SD_MODULE_ENABLED
// #define HAL_SMARTCARD_MODULE_ENABLED
// #define HAL_SPI_MODULE_ENABLED
#ifdef RT_USING_SPI
#define HAL_SPI_MODULE_ENABLED
#endif
// #define HAL_SRAM_MODULE_ENABLED
// #define HAL_TIM_MODULE_ENABLED
// #define HAL_UART_MODULE_ENABLED
// #define HAL_USART_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#ifdef RT_USING_SERIAL
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#endif
// #define HAL_WWDG_MODULE_ENABLED
// #define HAL_MMC_MODULE_ENABLED

60
bsp/stm32f10x_HAL/drivers/stm32f1xx_it.c
View File

@ -42,7 +42,7 @@
/* External variables --------------------------------------------------------*/
/******************************************************************************/
/* Cortex-M3 Processor Interruption and Exception Handlers */
/* Cortex-M3 Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
@ -50,12 +50,12 @@
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
@ -65,15 +65,15 @@ void NMI_Handler(void)
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
}
/* USER CODE BEGIN MemoryManagement_IRQn 1 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
}
/* USER CODE BEGIN MemoryManagement_IRQn 1 */
/* USER CODE END MemoryManagement_IRQn 1 */
/* USER CODE END MemoryManagement_IRQn 1 */
}
/**
@ -81,15 +81,15 @@ void MemManage_Handler(void)
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
}
/* USER CODE BEGIN BusFault_IRQn 1 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
}
/* USER CODE BEGIN BusFault_IRQn 1 */
/* USER CODE END BusFault_IRQn 1 */
/* USER CODE END BusFault_IRQn 1 */
}
/**
@ -97,15 +97,15 @@ void BusFault_Handler(void)
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
}
/* USER CODE BEGIN UsageFault_IRQn 1 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
}
/* USER CODE BEGIN UsageFault_IRQn 1 */
/* USER CODE END UsageFault_IRQn 1 */
/* USER CODE END UsageFault_IRQn 1 */
}
/**
@ -113,12 +113,12 @@ void UsageFault_Handler(void)
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**

459
bsp/stm32f10x_HAL/drivers/usart.c
View File

@ -1,459 +0,0 @@
/*
* File : usart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2013, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard the first version
* 2010-03-29 Bernard remove interrupt Tx and DMA Rx mode
* 2013-05-13 aozima update for kehong-lingtai.
* 2015-01-31 armink make sure the serial transmit complete in putc()
* 2016-05-13 armink add DMA Rx mode
* 2017-01-19 aubr.cool add interrupt Tx mode
* 2017-04-13 aubr.cool correct Rx parity err
* 2017-10-20 ZYH porting to HAL Libraries(with out DMA)
*/
#include "board.h"
#include <rtdevice.h>
/* STM32 uart driver */
struct stm32_uart
{
UART_HandleTypeDef huart;
IRQn_Type irq;
};
static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = (struct stm32_uart *)serial->parent.user_data;
uart->huart.Init.BaudRate = cfg->baud_rate;
uart->huart.Init.HwFlowCtl = UART_HWCONTROL_NONE;
uart->huart.Init.Mode = UART_MODE_TX_RX;
uart->huart.Init.OverSampling = UART_OVERSAMPLING_16;
switch (cfg->data_bits)
{
case DATA_BITS_8:
uart->huart.Init.WordLength = UART_WORDLENGTH_8B;
break;
case DATA_BITS_9:
uart->huart.Init.WordLength = UART_WORDLENGTH_9B;
break;
default:
uart->huart.Init.WordLength = UART_WORDLENGTH_8B;
break;
}
switch (cfg->stop_bits)
{
case STOP_BITS_1:
uart->huart.Init.StopBits = UART_STOPBITS_1;
break;
case STOP_BITS_2:
uart->huart.Init.StopBits = UART_STOPBITS_2;
break;
default:
uart->huart.Init.StopBits = UART_STOPBITS_1;
break;
}
switch (cfg->parity)
{
case PARITY_NONE:
uart->huart.Init.Parity = UART_PARITY_NONE;
break;
case PARITY_ODD:
uart->huart.Init.Parity = UART_PARITY_ODD;
break;
case PARITY_EVEN:
uart->huart.Init.Parity = UART_PARITY_EVEN;
break;
default:
uart->huart.Init.Parity = UART_PARITY_NONE;
break;
}
if (HAL_UART_Init(&uart->huart) != HAL_OK)
{
return RT_ERROR;
}
return RT_EOK;
}
static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct stm32_uart* uart;
// rt_uint32_t ctrl_arg = (rt_uint32_t)(arg);
RT_ASSERT(serial != RT_NULL);
uart = (struct stm32_uart *)serial->parent.user_data;
switch (cmd)
{
/* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
NVIC_DisableIRQ(uart->irq);
/* disable interrupt */
__HAL_UART_DISABLE_IT(&uart->huart, USART_IT_RXNE);
break;
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
NVIC_EnableIRQ(uart->irq);
/* enable interrupt */
__HAL_UART_ENABLE_IT(&uart->huart, USART_IT_RXNE);
break;
}
return RT_EOK;
}
static int stm32_putc(struct rt_serial_device *serial, char c)
{
struct stm32_uart* uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct stm32_uart *)serial->parent.user_data;
while(__HAL_UART_GET_FLAG(&uart->huart,UART_FLAG_TXE) == RESET);
uart->huart.Instance->DR = c;
return 1;
}
static int stm32_getc(struct rt_serial_device *serial)
{
int ch;
struct stm32_uart* uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct stm32_uart *)serial->parent.user_data;
ch = -1;
if (__HAL_UART_GET_FLAG(&uart->huart,UART_FLAG_RXNE) != RESET)
{
ch = uart->huart.Instance->DR & 0xff;
}
return ch;
}
/**
* Uart common interrupt process. This need add to uart ISR.
*
* @param serial serial device
*/
static void uart_isr(struct rt_serial_device *serial) {
struct stm32_uart *uart = (struct stm32_uart *) serial->parent.user_data;
RT_ASSERT(uart != RT_NULL);
if((__HAL_UART_GET_FLAG(&uart->huart, UART_FLAG_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(&uart->huart,UART_IT_RXNE) != RESET))
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
__HAL_UART_CLEAR_FLAG(&uart->huart,UART_FLAG_RXNE);
}
}
static const struct rt_uart_ops stm32_uart_ops =
{
stm32_configure,
stm32_control,
stm32_putc,
stm32_getc,
};
#if defined(RT_USING_UART1)
/* UART1 device driver structure */
struct stm32_uart uart1 =
{
{USART1},
USART1_IRQn
};
struct rt_serial_device serial1;
void USART1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&serial1);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* RT_USING_UART1 */
#if defined(RT_USING_UART2)
/* UART1 device driver structure */
struct stm32_uart uart2 =
{
{USART2},
USART2_IRQn
};
struct rt_serial_device serial2;
void USART2_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&serial2);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* RT_USING_UART2 */
#if defined(RT_USING_UART3)
/* UART1 device driver structure */
struct stm32_uart uart3 =
{
{USART3},
USART3_IRQn
};
struct rt_serial_device serial3;
void USART3_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&serial3);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* RT_USING_UART2 */
static void MX_USART_UART_Init(UART_HandleTypeDef* uartHandle);
void rt_hw_usart_init(void)
{
struct stm32_uart* uart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
#if defined(RT_USING_UART1)
uart = &uart1;
config.baud_rate = BAUD_RATE_115200;
serial1.ops = &stm32_uart_ops;
serial1.config = config;
MX_USART_UART_Init(&uart->huart);
/* register UART1 device */
rt_hw_serial_register(&serial1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX ,
uart);
#endif /* RT_USING_UART1 */
#if defined(RT_USING_UART2)
uart = &uart2;
config.baud_rate = BAUD_RATE_115200;
serial2.ops = &stm32_uart_ops;
serial2.config = config;
MX_USART_UART_Init(&uart->huart);
/* register UART1 device */
rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX ,
uart);
#endif /* RT_USING_UART1 */
#if defined(RT_USING_UART3)
uart = &uart3;
config.baud_rate = BAUD_RATE_115200;
serial3.ops = &stm32_uart_ops;
serial3.config = config;
MX_USART_UART_Init(&uart->huart);
/* register UART1 device */
rt_hw_serial_register(&serial3, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX ,
uart);
#endif /* RT_USING_UART1 */
}
static void MX_USART_UART_Init(UART_HandleTypeDef* uartHandle)
{
uartHandle->Init.BaudRate = 115200;
uartHandle->Init.WordLength = UART_WORDLENGTH_8B;
uartHandle->Init.StopBits = UART_STOPBITS_1;
uartHandle->Init.Parity = UART_PARITY_NONE;
uartHandle->Init.Mode = UART_MODE_TX_RX;
uartHandle->Init.HwFlowCtl = UART_HWCONTROL_NONE;
uartHandle->Init.OverSampling = UART_OVERSAMPLING_16;
RT_ASSERT(HAL_UART_Init(uartHandle) == HAL_OK);
}
/* USART2 init function */
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
GPIO_InitTypeDef GPIO_InitStruct;
if(uartHandle->Instance==USART1)
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* USART1 clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USART1 interrupt Init */
HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(USART1_IRQn);
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
else if(uartHandle->Instance==USART2)
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* USART2 clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USART2 interrupt Init */
HAL_NVIC_SetPriority(USART2_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(USART2_IRQn);
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
else if(uartHandle->Instance==USART3)
{
/* USER CODE BEGIN USART3_MspInit 0 */
/* USER CODE END USART3_MspInit 0 */
/* USART3 clock enable */
__HAL_RCC_USART3_CLK_ENABLE();
/**USART3 GPIO Configuration
PB10 ------> USART3_TX
PB11 ------> USART3_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USART3 interrupt Init */
HAL_NVIC_SetPriority(USART3_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(USART3_IRQn);
/* USER CODE BEGIN USART3_MspInit 1 */
/* USER CODE END USART3_MspInit 1 */
}
}
void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
{
if(uartHandle->Instance==USART1)
{
/* USER CODE BEGIN USART1_MspDeInit 0 */
/* USER CODE END USART1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART1_CLK_DISABLE();
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
/* USART1 interrupt Deinit */
HAL_NVIC_DisableIRQ(USART1_IRQn);
/* USER CODE BEGIN USART1_MspDeInit 1 */
/* USER CODE END USART1_MspDeInit 1 */
}
else if(uartHandle->Instance==USART2)
{
/* USER CODE BEGIN USART2_MspDeInit 0 */
/* USER CODE END USART2_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART2_CLK_DISABLE();
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3);
/* USART2 interrupt Deinit */
HAL_NVIC_DisableIRQ(USART2_IRQn);
/* USER CODE BEGIN USART2_MspDeInit 1 */
/* USER CODE END USART2_MspDeInit 1 */
}
else if(uartHandle->Instance==USART3)
{
/* USER CODE BEGIN USART3_MspDeInit 0 */
/* USER CODE END USART3_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART3_CLK_DISABLE();
/**USART3 GPIO Configuration
PB10 ------> USART3_TX
PB11 ------> USART3_RX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11);
/* USART3 interrupt Deinit */
HAL_NVIC_DisableIRQ(USART3_IRQn);
/* USER CODE BEGIN USART3_MspDeInit 1 */
/* USER CODE END USART3_MspDeInit 1 */
}
}

1276
bsp/stm32f10x_HAL/project.uvoptx Normal file
View File

File diff suppressed because it is too large Load Diff

521
bsp/stm32f10x_HAL/project.uvprojx
View File

@ -1,7 +1,10 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rtthread-stm32</TargetName>
@ -16,28 +19,28 @@
<PackID>Keil.STM32F1xx_DFP.2.2.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x5000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec />
<StartupFile />
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:STM32F103RB$Device\Include\stm32f10x.h</RegisterFile>
<MemoryEnv />
<Cmp />
<Asm />
<Linker />
<OHString />
<InfinionOptionDll />
<SLE66CMisc />
<SLE66AMisc />
<SLE66LinkerMisc />
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:STM32F103RB$SVD\STM32F103xx.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath />
<IncludePath />
<LibPath />
<RegisterFilePath />
<DBRegisterFilePath />
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
@ -59,8 +62,8 @@
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
@ -69,8 +72,8 @@
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
@ -80,14 +83,14 @@
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
<UserProg2Name />
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString />
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
@ -101,8 +104,8 @@
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument />
<IncludeLibraryModules />
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
@ -111,7 +114,7 @@
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments />
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
</DllOption>
@ -136,10 +139,10 @@
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4 />
<pFcarmOut />
<pFcarmGrp />
<pFcArmRoot />
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
@ -172,7 +175,7 @@
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M3"</AdsCpuType>
<RvctDeviceName />
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
@ -304,7 +307,7 @@
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector />
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
@ -330,10 +333,10 @@
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls />
<MiscControls></MiscControls>
<Define>STM32F103xB, USE_HAL_DRIVER</Define>
<Undefine />
<IncludePath>applications;.;drivers;Libraries\CMSIS\Device\ST\STM32F1xx\Include;Libraries\STM32F1xx_HAL_Driver\Inc;Libraries\CMSIS\Include;..\..\components\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m3;..\..\libcpu\arm\common;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh</IncludePath>
<Undefine></Undefine>
<IncludePath>drivers;Libraries/CMSIS/Device/ST/STM32F1xx/Include;Libraries/STM32F1xx_HAL_Driver/Inc;Libraries/CMSIS/Include;applications;.;../../include;../../libcpu/arm/cortex-m3;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/finsh</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -348,10 +351,10 @@
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls />
<Define />
<Undefine />
<IncludePath />
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
@ -363,62 +366,39 @@
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase />
<ScatterFile />
<IncludeLibs />
<IncludeLibsPath />
<Misc> --keep *.o(FSymTab) --keep *.o(VSymTab) </Misc>
<LinkerInputFile />
<DisabledWarnings />
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc> --keep *.o(.rti_fn.*) --keep *.o(FSymTab)</Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Applications</GroupName>
<Files>
<File>
<FileName>application.c</FileName>
<FileType>1</FileType>
<FilePath>applications\application.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>startup.c</FileName>
<FileType>1</FileType>
<FilePath>applications\startup.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers</GroupName>
<Files>
<File>
<FileName>board.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\board.c</FilePath>
<FilePath>drivers/board.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f1xx_it.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\stm32f1xx_it.c</FilePath>
<FilePath>drivers/stm32f1xx_it.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>gpio.c</FileName>
<FileName>drv_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\gpio.c</FilePath>
<FilePath>drivers/drv_gpio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>usart.c</FileName>
<FileName>drv_usart.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\usart.c</FilePath>
<FilePath>drivers/drv_usart.c</FilePath>
</File>
</Files>
</Group>
@ -428,336 +408,252 @@
<File>
<FileName>system_stm32f1xx.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c</FilePath>
<FilePath>Libraries/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f1xx_hal_adc.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc.c</FilePath>
<FilePath>Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f1xx_hal_adc_ex.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc_ex.c</FilePath>
<FilePath>Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f1xx_hal_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c</FilePath>
<FilePath>Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f1xx_hal_gpio_ex.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c</FilePath>
<FilePath>Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f1xx_hal_flash.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash.c</FilePath>
<FilePath>Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f1xx_hal_flash_ex.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_flash_ex.c</FilePath>
<FilePath>Libraries/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f1xx_hal_dma.c</FileName>
<FileType>1</FileType>
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<RTE>
<apis />
<components />
<files />
<apis/>
<components/>
<files/>
</RTE>
</Project>

320
bsp/stm32f10x_HAL/rtconfig.h
View File

@ -1,220 +1,160 @@
/* RT-Thread config file */
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 8
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
/* RT-Thread Kernel */
/* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX 32
/* Tick per Second */
#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
/* RT_THREAD_PRIORITY_8 is not set */
#define RT_THREAD_PRIORITY_32
/* RT_THREAD_PRIORITY_256 is not set */
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_DEBUG
#define RT_THREAD_DEBUG
#define RT_USING_OVERFLOW_CHECK
/* Using Hook */
#define RT_DEBUG_INIT 0
#define RT_DEBUG_THREAD 0
#define RT_USING_HOOK
#define IDLE_THREAD_STACK_SIZE 256
/* RT_USING_TIMER_SOFT is not set */
/* Using Software Timer */
/* #define RT_USING_TIMER_SOFT */
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_TICK_PER_SECOND 10
/* Inter-Thread communication */
/* SECTION: IPC */
/* Using Semaphore*/
#define RT_USING_SEMAPHORE
/* Using Mutex */
#define RT_USING_MUTEX
/* Using Event */
#define RT_USING_EVENT
/* Using MailBox */
#define RT_USING_MAILBOX
/* Using Message Queue */
#define RT_USING_MESSAGEQUEUE
/* RT_USING_SIGNALS is not set */
/* Memory Management */
/* SECTION: Memory Management */
/* Using Memory Pool Management*/
#define RT_USING_MEMPOOL
/* Using Dynamic Heap Management */
#define RT_USING_MEMHEAP
/* RT_USING_NOHEAP is not set */
#define RT_USING_SMALL_MEM
/* RT_USING_SLAB is not set */
/* RT_USING_MEMHEAP_AS_HEAP is not set */
#define RT_USING_HEAP
/* Using Small MM */
#define RT_USING_SMALL_MEM
/* Kernel Device Object */
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
//#define RT_USING_COMPONENTS_INIT
/* SECTION: Device System */
/* Using Device System */
#define RT_USING_DEVICE
// <bool name="RT_USING_DEVICE_IPC" description="Using device communication" default="true" />
#define RT_USING_DEVICE_IPC
/* SECTION: device filesystem */
//#define RT_USING_DFS
#define RT_USING_DFS_ELMFAT
/* Reentrancy (thread safe) of the FatFs module. */
#define RT_DFS_ELM_REENTRANT
/* Number of volumes (logical drives) to be used. */
#define RT_DFS_ELM_DRIVES 1
/* #define RT_DFS_ELM_USE_LFN 1 */
/* #define RT_DFS_ELM_CODE_PAGE 936 */
#define RT_DFS_ELM_MAX_LFN 255
/* Maximum sector size to be handled. */
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 1
/* the max number of opened files */
#define DFS_FD_MAX 4
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
/* #define RT_USING_LWIP */
/* LwIP uses RT-Thread Memory Management */
#define RT_LWIP_USING_RT_MEM
/* Enable ICMP protocol*/
#define RT_LWIP_ICMP
/* Enable UDP protocol*/
#define RT_LWIP_UDP
/* Enable TCP protocol*/
#define RT_LWIP_TCP
/* Enable DNS */
#define RT_LWIP_DNS
/* the number of simulatenously active TCP connections*/
#define RT_LWIP_TCP_PCB_NUM 5
/* Using DHCP */
/* #define RT_LWIP_DHCP */
/* ip address of target*/
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 30
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR3 1
/* mask address of target*/
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
/* tcp thread options */
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 10
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
/* ethernet if thread options */
#define RT_LWIP_ETHTHREAD_PRIORITY 15
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 10
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
/* TCP sender buffer space */
#define RT_LWIP_TCP_SND_BUF 8192
/* TCP receive window. */
#define RT_LWIP_TCP_WND 8192
/* image support */
/* #define RTGUI_IMAGE_XPM */
/* #define RTGUI_IMAGE_BMP */
// <bool name="RT_USING_CMSIS_OS" description="Using CMSIS OS API" default="true" />
// #define RT_USING_CMSIS_OS
// <bool name="RT_USING_RTT_CMSIS" description="Using CMSIS in RTT" default="true" />
#define RT_USING_RTT_CMSIS
// <bool name="RT_USING_BSP_CMSIS" description="Using CMSIS in BSP" default="true" />
// #define RT_USING_BSP_CMSIS
/* nanopb support */
/* #define RT_USING_NANOPB */
#define RT_USING_CPU_FFS
#define HAL_MODULE_ENABLED
// #define HAL_ADC_MODULE_ENABLED
// #define HAL_CAN_MODULE_ENABLED
// #define HAL_CEC_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
// #define HAL_CRC_MODULE_ENABLED
// #define HAL_DAC_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
// #define HAL_ETH_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
// #define HAL_HCD_MODULE_ENABLED
// #define HAL_I2C_MODULE_ENABLED
// #define HAL_I2S_MODULE_ENABLED
// #define HAL_IRDA_MODULE_ENABLED
// #define HAL_IWDG_MODULE_ENABLED
// #define HAL_NAND_MODULE_ENABLED
// #define HAL_NOR_MODULE_ENABLED
// #define HAL_PCCARD_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
// #define HAL_RTC_MODULE_ENABLED
// #define HAL_SD_MODULE_ENABLED
// #define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
// #define HAL_SRAM_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
// #define HAL_WWDG_MODULE_ENABLED
// #define HAL_MMC_MODULE_ENABLED
#define RT_USING_SERIAL
#define RT_USING_PIN
#define RT_USING_UART1
#define RT_CONSOLE_DEVICE_NAME "uart1"
/* SECTION: Console options */
/* RT_USING_INTERRUPT_INFO is not set */
#define RT_USING_CONSOLE
/* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE 128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart2"
/* RT_USING_MODULE is not set */
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
/* C++ features */
/* RT_USING_CPLUSPLUS is not set */
/* Command shell */
/* SECTION: finsh, a C-Express shell */
#define RT_USING_FINSH
//#define FINSH_USING_MSH
/* Using symbol table */
#define FINSH_USING_HISTORY
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
/* FINSH_USING_AUTH is not set */
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_USING_MSH_ONLY
//#define RT_USING_SPI
/* Device virtual file system */
#define SPI_USE_DMA
/* RT_USING_DFS is not set */
#define RT_USING_W25QXX
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_USING_SERIAL
/* RT_USING_CAN is not set */
/* RT_USING_HWTIMER is not set */
/* RT_USING_I2C is not set */
#define RT_USING_PIN
/* RT_USING_MTD_NOR is not set */
/* RT_USING_MTD_NAND is not set */
/* RT_USING_RTC is not set */
/* RT_USING_SDIO is not set */
/* RT_USING_SPI is not set */
/* RT_USING_WDT is not set */
/* RT_USING_USB_HOST is not set */
/* RT_USING_USB_DEVICE is not set */
/* POSIX layer and C standard library */
/* RT_USING_LIBC is not set */
/* RT_USING_PTHREADS is not set */
/* Network stack */
/* light weight TCP/IP stack */
/* RT_USING_LWIP is not set */
/* Modbus master and slave stack */
/* RT_USING_MODBUS is not set */
/* RT-Thread UI Engine */
/* RT_USING_GUIENGINE is not set */
/* VBUS(Virtual Software BUS) */
/* RT_USING_VBUS is not set */
/* RT-Thread online packages */
/* system packages */
/* PKG_USING_PARTITION is not set */
/* PKG_USING_SQLITE is not set */
/* IoT - internet of things */
/* PKG_USING_CJSON is not set */
/* PKG_USING_PAHOMQTT is not set */
/* PKG_USING_WEBCLIENT is not set */
/* PKG_USING_MONGOOSE is not set */
/* PKG_USING_WEBTERMINAL is not set */
/* security packages */
/* PKG_USING_MBEDTLS is not set */
/* language packages */
/* PKG_USING_JERRYSCRIPT is not set */
/* multimedia packages */
/* tools packages */
/* PKG_USING_CMBACKTRACE is not set */
/* PKG_USING_EASYLOGGER is not set */
/* miscellaneous packages */
/* PKG_USING_HELLO is not set */
/* BSP_SPECIAL CONFIG */
#define STM32F10X_PIN_NUMBERS 64
/* RT_USING_UART1 is not set */
#define RT_USING_UART2
/* RT_USING_UART3 is not set */
#endif