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[BSP] fix compiling issue with libc

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This commit is contained in:
BernardXiong 2021-09-11 18:09:22 +08:00
parent 3dc820b371
commit 0b13409c16
12 changed files with 146 additions and 114 deletions
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2
bsp/gd32vf103v-eval/board/board.c
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@ -8,7 +8,7 @@
* 2019-07-23 tyustli first version
*
*/
#include <stddef.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"

1
bsp/gd32vf103v-eval/libraries/SConscript
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@ -8,7 +8,6 @@ cwd = GetCurrentDir()
src = Glob('GD32VF103_standard_peripheral/Source/*.c')
src += Glob('n22/env_Eclipse/*.c')
src += Glob('n22/stubs/*.c')
src += ['GD32VF103_standard_peripheral/system_gd32vf103.c',
'n22/drivers/n22_func.c',
'n22/env_Eclipse/start.S',

2
bsp/lpc1114/driver/drv_uart.c
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@ -8,7 +8,7 @@
* 2013-05-18 Bernard The first version for LPC40xx
* 2019-05-05 jg1uaa port to LPC1114
*/
#include <stddef.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>

28
bsp/mini2440/drivers/uart.c
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@ -1,11 +1,14 @@
/*
* File : uart.c
* Drivers for s3c2440 uarts.
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-09 Jonne Code refactoring for new bsp
*/
#include <stddef.h>
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
@ -132,7 +135,8 @@ static void rt_hw_uart_isr(int irqno, void *param)
}
}
static struct rt_uart_ops s3c2440_uart_ops = {
static struct rt_uart_ops s3c2440_uart_ops =
{
.configure = s3c2440_serial_configure,
.control = s3c2440_serial_control,
.putc = s3c2440_putc,
@ -140,35 +144,41 @@ static struct rt_uart_ops s3c2440_uart_ops = {
};
static struct rt_serial_device _serial0 = {
static struct rt_serial_device _serial0 =
{
.ops = &s3c2440_uart_ops,
.config = RT_SERIAL_CONFIG_DEFAULT,
.serial_rx = NULL,
.serial_tx = NULL
};
static struct hw_uart_device _hwserial0 = {
static struct hw_uart_device _hwserial0 =
{
.hw_base = 0x50000000,
.irqno = INTUART0
};
static struct rt_serial_device _serial1 = {
static struct rt_serial_device _serial1 =
{
.ops = &s3c2440_uart_ops,
.config = RT_SERIAL_CONFIG_DEFAULT,
.serial_rx = NULL,
.serial_tx = NULL
};
static struct hw_uart_device _hwserial1 = {
static struct hw_uart_device _hwserial1 =
{
.hw_base = 0x50004000,
.irqno = INTUART1
};
static struct rt_serial_device _serial2 = {
static struct rt_serial_device _serial2 =
{
.ops = &s3c2440_uart_ops,
.config = RT_SERIAL_CONFIG_DEFAULT,
.serial_rx = NULL,
.serial_tx = NULL
};
static struct hw_uart_device _hwserial2 = {
static struct hw_uart_device _hwserial2 =
{
.hw_base = 0x50008000,
.irqno = INTUART2
};

18
bsp/raspberry-pi/raspi4-32/driver/drv_eth.c
View File

@ -9,9 +9,12 @@
* 2020-10-30 bigmagic first version
*/
#include <rthw.h>
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include <lwip/sys.h>
#include <netif/ethernetif.h>
@ -428,7 +431,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
}
else
{
if(prev_recv_cnt == prod_index & 0xffff)
if (prev_recv_cnt == (prod_index & 0xffff))
{
return 0;
}
@ -437,11 +440,12 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
length = read32(desc_base + DMA_DESC_LENGTH_STATUS);
length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK;
addr = read32(desc_base + DMA_DESC_ADDRESS_LO);
/* To cater for the IP headepr alignment the hardware does.
* This would actually not be needed if we don't program
* RBUF_ALIGN_2B
*/
rt_hw_cpu_dcache_invalidate(addr,length);
rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *) addr, length);
*packetp = (rt_uint8_t *)(addr + RX_BUF_OFFSET);
rx_index = rx_index + 1;
@ -468,16 +472,16 @@ static int bcmgenet_gmac_eth_send(void *packet, int length)
void *desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE);
rt_uint32_t len_stat = length << DMA_BUFLENGTH_SHIFT;
rt_uint32_t prod_index, cons;
rt_uint32_t tries = 100;
rt_uint32_t prod_index;
prod_index = read32(MAC_REG + TDMA_PROD_INDEX);
len_stat |= 0x3F << DMA_TX_QTAG_SHIFT;
len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP;
rt_hw_cpu_dcache_clean((void*)packet, length);
write32((desc_base + DMA_DESC_ADDRESS_LO), packet);
rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)packet, length);
write32((desc_base + DMA_DESC_ADDRESS_LO), (rt_uint32_t)packet);
write32((desc_base + DMA_DESC_ADDRESS_HI), 0);
write32((desc_base + DMA_DESC_LENGTH_STATUS), len_stat);

1
bsp/raspberry-pi/raspi4-32/driver/mbox.h
View File

@ -12,6 +12,7 @@
#define __MBOX_H__
#include <rtthread.h>
#include "board.h"
//https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
//https://github.com/hermanhermitage/videocoreiv

1
bsp/tm4c123bsp/libraries/Drivers/drv_pwm.h
View File

@ -11,6 +11,7 @@
#ifndef __DRV_PWM_H__
#define __DRV_PWM_H__
#include <stdint.h>
#include<rtdevice.h>
#include<rthw.h>

1
bsp/tm4c123bsp/libraries/Drivers/drv_spi.h
View File

@ -11,6 +11,7 @@
#ifndef __DRV_SPI_H__
#define __DRV_SPI_H__
#include <stdint.h>
#include <rtdevice.h>
#include <rthw.h>
#include "drivers/spi.h"

1
components/drivers/include/drivers/pm.h
View File

@ -15,6 +15,7 @@
#ifndef __PM_H__
#define __PM_H__
#include <stdint.h>
#include <rtthread.h>
#ifndef PM_HAS_CUSTOM_CONFIG

2
components/drivers/phy/phy.c
View File

@ -8,7 +8,7 @@
* Date Author Notes
* 2020-09-27 wangqiang first version
*/
#include <stddef.h>
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>

1
components/net/netdev/src/netdev.c
View File

@ -10,6 +10,7 @@
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <rtthread.h>
#include <rthw.h>

38
libcpu/arm/zynqmp-r5/cache.c
View File

@ -9,6 +9,8 @@
* 2020-03-19 WangHuachen first version
* 2021-05-10 WangHuachen add more functions
*/
#include <stdint.h>
#include <rthw.h>
#include <rtdef.h>
@ -71,7 +73,8 @@ void Xil_DCacheEnable(void)
#elif defined (__ICCARM__)
mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
if ((CtrlReg & XREG_CP15_CONTROL_C_BIT)==0x00000000U) {
if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) == 0x00000000U)
{
/* invalidate the Data cache */
Xil_DCacheInvalidate();
@ -143,24 +146,28 @@ void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
if (len != 0U) {
if (len != 0U)
{
end = tempadr + len;
tempend = end;
/* Select L1 Data cache in CSSR */
mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
if ((tempadr & (cacheline-1U)) != 0U) {
if ((tempadr & (cacheline - 1U)) != 0U)
{
tempadr &= (~(cacheline - 1U));
Xil_DCacheFlushLine(tempadr);
}
if ((tempend & (cacheline-1U)) != 0U) {
if ((tempend & (cacheline - 1U)) != 0U)
{
tempend &= (~(cacheline - 1U));
Xil_DCacheFlushLine(tempend);
}
while (tempadr < tempend) {
while (tempadr < tempend)
{
/* Invalidate Data cache line */
asm_inval_dc_line_mva_poc(tempadr);
@ -211,8 +218,10 @@ void Xil_DCacheFlush(void)
Set = 0U;
/* Invalidate all the cachelines */
for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
for (WayIndex = 0U; WayIndex < NumWays; WayIndex++)
{
for (SetIndex = 0U; SetIndex < NumSet; SetIndex++)
{
C7Reg = Way | Set;
/* Flush by Set/Way */
asm_clean_inval_dc_line_sw(C7Reg);
@ -256,14 +265,16 @@ void Xil_DCacheFlushRange(INTPTR adr, u32 len)
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
if (len != 0x00000000U) {
if (len != 0x00000000U)
{
/* Back the starting address up to the start of a cache line
* perform cache operations until adr+len
*/
end = LocalAddr + len;
LocalAddr &= ~(cacheline - 1U);
while (LocalAddr < end) {
while (LocalAddr < end)
{
/* Flush Data cache line */
asm_clean_inval_dc_line_mva_poc(LocalAddr);
@ -301,7 +312,8 @@ void Xil_ICacheEnable(void)
#elif defined (__ICCARM__)
mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
#endif
if ((CtrlReg & XREG_CP15_CONTROL_I_BIT)==0x00000000U) {
if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) == 0x00000000U)
{
/* invalidate the instruction cache */
mtcp(XREG_CP15_INVAL_IC_POU, 0);
@ -374,7 +386,8 @@ void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
if (len != 0x00000000U) {
if (len != 0x00000000U)
{
/* Back the starting address up to the start of a cache line
* perform cache operations until adr+len
*/
@ -384,7 +397,8 @@ void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
/* Select cache L0 I-cache in CSSR */
mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
while (LocalAddr < end) {
while (LocalAddr < end)
{
/* Invalidate L1 I-cache line */
asm_inval_ic_line_mva_pou(LocalAddr);