wangjiyang added bsp/evb4020 & modified libcpu/arm/sep4020
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1128 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wangjiyang
parent
8732a6feb8
commit
08668dc481
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@ -5,38 +5,186 @@
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*
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*
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* The license and distribution terms for this file may be
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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* http://openlab.rt-thread.com/license/LICENSE
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*
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*
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* Change Logs:
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* Change Logs:
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* Date Author Notes
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* Date Author Notes
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* 2006-08-23 Bernard first version
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* 2006-03-13 Bernard first version
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*/
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*/
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#include <rtthread.h>
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#include <rtthread.h>
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#include <sep4020.h>
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extern rt_uint32_t rt_hw_interrupt_disable(void);
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//TODO
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#warning I DON'T KNOW IF THE MMU OPERATION WORKS ON SEP4020
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/**
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/**
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* @addtogroup AT91SAM7X
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* @addtogroup S3C24X0
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*/
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*/
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/*@{*/
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/*@{*/
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#define ICACHE_MASK (rt_uint32_t)(1 << 12)
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#define DCACHE_MASK (rt_uint32_t)(1 << 2)
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#ifdef __GNUC__
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rt_inline rt_uint32_t cp15_rd(void)
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{
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rt_uint32_t i;
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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return i;
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}
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rt_inline void cache_enable(rt_uint32_t bit)
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{
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__asm__ __volatile__( \
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"mrc p15,0,r0,c1,c0,0\n\t" \
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"orr r0,r0,%0\n\t" \
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"mcr p15,0,r0,c1,c0,0" \
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: \
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:"r" (bit) \
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:"memory");
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}
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rt_inline void cache_disable(rt_uint32_t bit)
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{
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__asm__ __volatile__( \
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"mrc p15,0,r0,c1,c0,0\n\t" \
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"bic r0,r0,%0\n\t" \
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"mcr p15,0,r0,c1,c0,0" \
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: \
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:"r" (bit) \
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:"memory");
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}
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#endif
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#ifdef __CC_ARM
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rt_inline rt_uint32_t cp15_rd(void)
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{
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rt_uint32_t i;
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__asm
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{
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mrc p15, 0, i, c1, c0, 0
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}
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return i;
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}
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rt_inline void cache_enable(rt_uint32_t bit)
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{
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rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, bit
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mcr p15, 0, value, c1, c0, 0
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}
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}
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rt_inline void cache_disable(rt_uint32_t bit)
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{
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rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, bit
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mcr p15, 0, value, c1, c0, 0
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}
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}
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#endif
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/**
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/**
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* this function will reset CPU
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* enable I-Cache
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*
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*/
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void rt_hw_cpu_icache_enable()
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{
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cache_enable(ICACHE_MASK);
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}
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/**
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* disable I-Cache
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*
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*/
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void rt_hw_cpu_icache_disable()
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{
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cache_disable(ICACHE_MASK);
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}
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/**
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* return the status of I-Cache
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*
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*/
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rt_base_t rt_hw_cpu_icache_status()
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{
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return (cp15_rd() & ICACHE_MASK);
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}
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/**
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* enable D-Cache
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*
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*/
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void rt_hw_cpu_dcache_enable()
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{
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cache_enable(DCACHE_MASK);
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}
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/**
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* disable D-Cache
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*
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*/
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void rt_hw_cpu_dcache_disable()
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{
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cache_disable(DCACHE_MASK);
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}
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/**
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* return the status of D-Cache
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*
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*/
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rt_base_t rt_hw_cpu_dcache_status()
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{
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return (cp15_rd() & DCACHE_MASK);
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}
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/**
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* reset cpu by dog's time-out
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*
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*
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*/
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*/
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void rt_hw_cpu_reset()
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void rt_hw_cpu_reset()
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{
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{
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/* enable watchdog */
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*(RP)(RTC_CTR) = 0x02;
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/*Enable watchdog reset*/
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*(RP)(RTC_INT_EN) = 0x20;
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/* Initialize watchdog timer count register */
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*(RP)(RTC_WD_CNT) = 0x0001;
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while(1); /* loop forever and wait for reset to happen */
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/* NEVER REACHED */
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}
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}
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/**
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/**
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* this function will shutdown CPU
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* shutdown CPU
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*
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*
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*/
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*/
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void rt_hw_cpu_shutdown()
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void rt_hw_cpu_shutdown()
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{
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{
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rt_uint32_t UNUSED level;
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rt_kprintf("shutdown...\n");
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rt_kprintf("shutdown...\n");
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while (1);
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level = rt_hw_interrupt_disable();
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RT_ASSERT(RT_NULL);
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}
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}
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/*@}*/
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/*@}*/
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@ -9,12 +9,11 @@
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*
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*
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* Change Logs:
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* Change Logs:
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* Date Author Notes
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* Date Author Notes
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* 2006-08-23 Bernard first version
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* 2006-03-13 Bernard first version
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* 2010-03-17 zchong SEP4020
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*/
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*/
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#include <rtthread.h>
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#include <rtthread.h>
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#include "sep4020.h"
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#include <sep4020.h>
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#define MAX_HANDLERS 32
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#define MAX_HANDLERS 32
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@ -26,13 +25,14 @@ rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrput_flag;
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rt_uint32_t rt_thread_switch_interrput_flag;
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/**
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/**
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* @addtogroup SEP4020
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* @addtogroup S3C24X0
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*/
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*/
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/*@{*/
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/*@{*/
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void rt_hw_interrupt_handler(int vector)
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rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
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{
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{
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rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
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rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
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return RT_NULL;
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}
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}
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/**
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/**
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{
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{
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register rt_uint32_t idx;
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register rt_uint32_t idx;
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/* disable all interrupts */
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/*Make sure all intc registers in proper state*/
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INTC_IER = 0x0;
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/* mask all interrupts */
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/*mask all the irq*/
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INTC_IMR = 0xFFFFFFFF;
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*(RP)(INTC_IMR) = 0xFFFFFFFF;
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/*enable all the irq*/
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*(RP)(INTC_IER) = 0XFFFFFFFF;
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/*Dont use any forced irq*/
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*(RP)(INTC_IFR) = 0x0;
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/*Disable all the fiq*/
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*(RP)(INTC_FIER) = 0x0;
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/*Mask all the fiq*/
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*(RP)(INTC_FIMR) = 0x0F;
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/*Dont use forced fiq*/
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*(RP)(INTC_FIFR) = 0x0;
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/*Intrrupt priority register*/
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*(RP)(INTC_IPLR) = 0x0;
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/* init exceptions table */
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/* init exceptions table */
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for(idx=0; idx < MAX_HANDLERS; idx++)
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for(idx=0; idx < MAX_HANDLERS; idx++)
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{
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{
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isr_table[idx] = (rt_isr_handler_t)rt_hw_interrupt_handler;
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isr_table[idx] = (rt_isr_handler_t)rt_hw_interrupt_handle;
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}
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}
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/* init interrupt nest, and context in thread sp */
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/* init interrupt nest, and context in thread sp */
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* This function will mask a interrupt.
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* This function will mask a interrupt.
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* @param vector the interrupt number
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* @param vector the interrupt number
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*/
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*/
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void rt_hw_interrupt_mask(int vector)
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void rt_hw_interrupt_mask(rt_uint32_t vector)
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{
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{
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INTC_IMR |= 1 << vector;
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*(RP)(INTC_IMR) |= 1 << vector;
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}
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}
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/**
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/**
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* This function will un-mask a interrupt.
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* This function will un-mask a interrupt.
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* @param vector the interrupt number
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* @param vector the interrupt number
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*/
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*/
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void rt_hw_interrupt_umask(int vector)
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void rt_hw_interrupt_umask(rt_uint32_t vector)
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{
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{
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/* un-mask interrupt */
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if(vector == 16)
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if ((vector == INT_NOTUSED0) || (vector == INT_NOTUSED16))
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{
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{
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rt_kprintf("Interrupt vec %d is not used!\n", vector);
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rt_kprintf("Interrupt vec %d is not used!\n", vector);
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// while(1);
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}
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}
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else if (vector == INTGLOBAL)
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INTC_IMR = 0x0;
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else
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else
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INTC_IMR &= ~(1 << vector);
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*(RP)(INTC_IMR) &= ~(1 << vector);
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}
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}
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/**
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/**
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* This function will install a interrupt service routine to a interrupt.
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* This function will install a interrupt service routine to a interrupt.
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* @param vector the interrupt number
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* @param vector the interrupt number
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* @param new_handler the interrupt service routine to be installed
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* @param new_handler the interrupt service routine to be installed
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* @param old_handler the old interrupt service routine
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* @param old_handler the old interrupt service routine
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*/
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*/
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void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
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void rt_hw_interrupt_install(rt_uint32_t vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
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{
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{
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if(vector >= 0 && vector < MAX_HANDLERS)
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if(vector < MAX_HANDLERS)
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{
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{
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if (*old_handler != RT_NULL) *old_handler = isr_table[vector];
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if (*old_handler != RT_NULL)
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if (new_handler != RT_NULL) isr_table[vector] = new_handler;
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*old_handler = isr_table[vector];
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if (new_handler != RT_NULL)
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isr_table[vector] = new_handler;
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}
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}
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}
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}
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@ -9,14 +9,12 @@
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*
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*
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* Change Logs:
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* Change Logs:
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* Date Author Notes
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* Date Author Notes
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* 2006-08-23 Bernard the first version
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* 2006-03-13 Bernard the first version
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*/
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*/
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#include <rtthread.h>
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#include <rtthread.h>
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#include <sep4020.h>
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#define SVCMODE 0x13
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/**
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/**
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* @addtogroup AT91SAM7
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* @addtogroup S3C24X0
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*/
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*/
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/*@{*/
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/*@{*/
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@ -33,11 +31,11 @@
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rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
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rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
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rt_uint8_t *stack_addr, void *texit)
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rt_uint8_t *stack_addr, void *texit)
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{
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{
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unsigned long *stk;
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rt_uint32_t *stk;
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stk = (unsigned long *)stack_addr;
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stk = (rt_uint32_t*)stack_addr;
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*(stk) = (unsigned long)tentry; /* entry point */
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*(stk) = (rt_uint32_t)tentry; /* entry point */
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*(--stk) = (unsigned long)texit; /* lr */
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*(--stk) = (rt_uint32_t)texit; /* lr */
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*(--stk) = 0; /* r12 */
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*(--stk) = 0; /* r12 */
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*(--stk) = 0; /* r11 */
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*(--stk) = 0; /* r11 */
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*(--stk) = 0; /* r10 */
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*(--stk) = 0; /* r10 */
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@ -50,9 +48,9 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
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*(--stk) = 0; /* r3 */
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*(--stk) = 0; /* r3 */
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*(--stk) = 0; /* r2 */
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*(--stk) = 0; /* r2 */
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*(--stk) = 0; /* r1 */
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*(--stk) = 0; /* r1 */
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*(--stk) = (unsigned long)parameter; /* r0 : argument */
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*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
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*(--stk) = SVCMODE; /* cpsr */
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*(--stk) = Mode_SVC; /* cpsr */
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*(--stk) = SVCMODE; /* spsr */
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*(--stk) = Mode_SVC; /* spsr */
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/* return task's current stack address */
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/* return task's current stack address */
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return (rt_uint8_t *)stk;
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return (rt_uint8_t *)stk;
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@ -8,8 +8,6 @@
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; 2010-03-17 zchong
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; 2010-03-17 zchong
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;=============================================================================================
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;=============================================================================================
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;
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PMU_PLTR EQU 0x10001000 ; PLL的稳定过渡时间
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PMU_PLTR EQU 0x10001000 ; PLL的稳定过渡时间
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PMU_PMCR EQU 0x10001004 ; 系统主时钟PLL的控制寄存器
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PMU_PMCR EQU 0x10001004 ; 系统主时钟PLL的控制寄存器
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PMU_PUCR EQU 0x10001008 ; USB时钟PLL的控制寄存器
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PMU_PUCR EQU 0x10001008 ; USB时钟PLL的控制寄存器
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@ -51,42 +49,51 @@ MODE_SVC32 EQU 0x00000013
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; Internal Memory Base Addresses
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; Internal Memory Base Addresses
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FLASH_BASE EQU 0x20000000
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FLASH_BASE EQU 0x20000000
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RAM_BASE EQU 0x04000000
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RAM_BASE EQU 0x04000000
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SDRAM_BASE EQU 0x30000000
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; Stack
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; Stack
|
||||||
UND_Stack_Size EQU 0x00000000
|
Unused_Stack_Size EQU 0x00000100
|
||||||
SVC_Stack_Size EQU 0x00000400
|
Svc_Stack_Size EQU 0x00001000
|
||||||
ABT_Stack_Size EQU 0x00000000
|
Abt_Stack_Size EQU 0x00000000
|
||||||
FIQ_Stack_Size EQU 0x00000000
|
Fiq_Stack_Size EQU 0x00000000
|
||||||
IRQ_Stack_Size EQU 0x00000100
|
Irq_Stack_Size EQU 0x00001000
|
||||||
USR_Stack_Size EQU 0x00000000
|
Usr_Stack_Size EQU 0x00000000
|
||||||
|
|
||||||
ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
|
|
||||||
FIQ_Stack_Size + IRQ_Stack_Size)
|
|
||||||
|
|
||||||
|
;SVC STACK
|
||||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Svc_Stack SPACE Svc_Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
Svc_Stack_Top
|
||||||
|
|
||||||
|
;IRQ STACK
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Irq_Stack SPACE Irq_Stack_Size
|
||||||
|
Irq_Stack_Top
|
||||||
|
|
||||||
|
;UNUSED STACK
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Unused_Stack SPACE Unused_Stack_Size
|
||||||
|
Unused_Stack_Top
|
||||||
|
|
||||||
Stack_Mem SPACE USR_Stack_Size
|
|
||||||
__initial_sp SPACE ISR_Stack_Size
|
|
||||||
Stack_Top
|
|
||||||
|
|
||||||
; Heap
|
; Heap
|
||||||
Heap_Size EQU 0x00000000
|
Heap_Size EQU 0x0000100
|
||||||
|
|
||||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
EXPORT Heap_Mem
|
||||||
__heap_base
|
__heap_base
|
||||||
Heap_Mem SPACE Heap_Size
|
Heap_Mem SPACE Heap_Size
|
||||||
__heap_limit
|
__heap_limit
|
||||||
|
|
||||||
|
|
||||||
PRESERVE8
|
PRESERVE8
|
||||||
|
|
||||||
; Area Definition and Entry Point
|
; Area Definition and Entry Point
|
||||||
; Startup Code must be linked first at Address at which it expects to run.
|
; Startup Code must be linked first at Address at which it expects to run.
|
||||||
|
|
||||||
AREA RESET, CODE, READONLY
|
AREA RESET, CODE, READONLY
|
||||||
ARM
|
ARM
|
||||||
|
|
||||||
; Exception Vectors
|
; Exception Vectors
|
||||||
; Mapped to Address 0.
|
; Mapped to Address 0.
|
||||||
; Absolute addressing mode must be used.
|
; Absolute addressing mode must be used.
|
||||||
; Dummy Handlers are implemented as infinite loops which can be modified.
|
; Dummy Handlers are implemented as infinite loops which can be modified.
|
||||||
|
|
@ -110,265 +117,268 @@ IRQ_Addr DCD IRQ_Handler
|
||||||
FIQ_Addr DCD FIQ_Handler
|
FIQ_Addr DCD FIQ_Handler
|
||||||
|
|
||||||
Undef_Handler B Undef_Handler
|
Undef_Handler B Undef_Handler
|
||||||
SWI_Handler B SWI_Handler
|
SWI_Handler B SWI_Handler
|
||||||
PAbt_Handler B PAbt_Handler
|
PAbt_Handler B Abort_Handler
|
||||||
DAbt_Handler B DAbt_Handler
|
DAbt_Handler B Abort_Handler
|
||||||
FIQ_Handler B FIQ_Handler
|
FIQ_Handler B FIQ_Handler
|
||||||
|
|
||||||
|
Abort_Handler PROC
|
||||||
|
ARM
|
||||||
|
EXPORT Abort_Handler
|
||||||
|
DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system.
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
|
||||||
; Reset Handler
|
; Reset Handler
|
||||||
|
;IMPORT __user_initial_stackheap
|
||||||
EXPORT Reset_Handler
|
EXPORT Reset_Handler
|
||||||
Reset_Handler
|
Reset_Handler
|
||||||
|
|
||||||
;****************************************************************
|
;****************************************************************
|
||||||
;* 关闭看门狗
|
;* Shutdown watchdog
|
||||||
;****************************************************************
|
;****************************************************************
|
||||||
LDR R0,=RTC_CTR
|
LDR R0,=RTC_CTR
|
||||||
LDR R1,=0x0
|
LDR R1,=0x0
|
||||||
STR R1,[R0]
|
STR R1,[R0]
|
||||||
|
|
||||||
;****************************************************************
|
;****************************************************************
|
||||||
;* 关中断
|
;* shutdown interrupts
|
||||||
;****************************************************************
|
;****************************************************************
|
||||||
MRS R0, CPSR
|
MRS R0, CPSR
|
||||||
BIC R0, R0, #MASK_MODE
|
BIC R0, R0, #MASK_MODE
|
||||||
ORR R0, R0, #MODE_SVC32
|
ORR R0, R0, #MODE_SVC32
|
||||||
ORR R0, R0, #I_Bit
|
ORR R0, R0, #I_Bit
|
||||||
ORR R0, R0, #F_Bit
|
ORR R0, R0, #F_Bit
|
||||||
MSR CPSR_c, r0
|
MSR CPSR_c, r0
|
||||||
|
|
||||||
LDR R0,=INTC_IER
|
LDR R0,=INTC_IER
|
||||||
LDR R1,=0x0
|
LDR R1,=0x0
|
||||||
STR R1,[R0]
|
STR R1,[R0]
|
||||||
LDR R0,=INTC_IMR
|
LDR R0,=INTC_IMR
|
||||||
LDR R1,=0xFFFFFFFF
|
LDR R1,=0xFFFFFFFF
|
||||||
STR R1,[R0]
|
STR R1,[R0]
|
||||||
|
|
||||||
LDR R0,=INTC_FIER
|
LDR R0,=INTC_FIER
|
||||||
LDR R1,=0x0
|
LDR R1,=0x0
|
||||||
STR R1,[R0]
|
STR R1,[R0]
|
||||||
LDR R0,=INTC_FIMR
|
LDR R0,=INTC_FIMR
|
||||||
LDR R1,=0x0F
|
LDR R1,=0x0F
|
||||||
STR R1,[R0]
|
STR R1,[R0]
|
||||||
|
|
||||||
;****************************************************************
|
;****************************************************************
|
||||||
;* 初始化PMU模块, 配置系统时钟
|
;* Initialize Stack Pointer
|
||||||
;****************************************************************
|
;****************************************************************
|
||||||
LDR R4, =PMU_PCSR ; 打开所有模块时钟
|
|
||||||
LDR R5, =0x0001ffff
|
|
||||||
STR R5, [ R4 ]
|
|
||||||
|
|
||||||
LDR R4, =PMU_PLTR ; 配置PLL稳定过度时间为保守值50us*100M.
|
LDR SP, =Svc_Stack_Top ;init SP_svc
|
||||||
LDR R5, =0x00fa00fa
|
|
||||||
STR R5, [ R4 ]
|
|
||||||
|
|
||||||
LDR R4, =PMU_PMDR ; 由SLOW模式进入NORMAL模式
|
MOV R4, #0xD2 ;chmod to irq and init SP_irq
|
||||||
LDR R5, =0x00000001
|
MSR cpsr_c, R4
|
||||||
STR R5, [ R4 ]
|
LDR SP, =Irq_Stack_Top
|
||||||
|
|
||||||
LDR R4, =PMU_PMCR ; 配置系统时钟为72MHz 2*Fin*9=2*4*9=72MHz
|
MOV R4, #0XD1 ;chomod to fiq and init SP_fiq
|
||||||
LDR R5, =0x00004009 ; MFCN 0->1 trigger PLL to reconfigure event when mode isn''t SLOW
|
MSR cpsr_c, R4
|
||||||
STR R5, [ R4 ]
|
LDR SP, =Unused_Stack_Top
|
||||||
LDR R4, =PMU_PMCR ;
|
|
||||||
LDR R5, =0x0000c009
|
MOV R4, #0XD7 ;chomod to abt and init SP_ABT
|
||||||
STR R5, [ R4 ]
|
MSR cpsr_c, R4
|
||||||
|
LDR SP, =Unused_Stack_Top
|
||||||
|
|
||||||
|
MOV R4, #0XDB ;chomod to undf and init SP_UNDF
|
||||||
|
MSR cpsr_c, R4
|
||||||
|
LDR SP, =Unused_Stack_Top
|
||||||
|
|
||||||
|
;chomod to abt and init SP_sys
|
||||||
|
MOV R4, #0xDF ;all interrupts disabled
|
||||||
|
MSR cpsr_c, R4 ;SYSTEM mode, @32-bit code mode
|
||||||
|
LDR SP, =Unused_Stack_Top
|
||||||
|
|
||||||
|
MOV R4, #0XD3 ;chmod to svc modle, CPSR IRQ bit is disable
|
||||||
|
MSR cpsr_c, R4
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
;****************************************************************
|
||||||
|
;* Initialize PMU & System Clock
|
||||||
|
;****************************************************************
|
||||||
|
|
||||||
|
LDR R4, =PMU_PCSR ; 打所有模块时钟
|
||||||
|
LDR R5, =0x0001ffff
|
||||||
|
STR R5, [ R4 ]
|
||||||
|
|
||||||
|
LDR R4, =PMU_PLTR ; 配置PLL稳定过度时间为保守值50us*100M.
|
||||||
|
LDR R5, =0x00fa00fa
|
||||||
|
STR R5, [ R4 ]
|
||||||
|
|
||||||
|
LDR R4, =PMU_PMDR ; 由SLOW模式进入NORMAL模式
|
||||||
|
LDR R5, =0x00000001
|
||||||
|
STR R5, [ R4 ]
|
||||||
|
|
||||||
|
LDR R4, =PMU_PMCR ; 配置系统时钟为80MHz
|
||||||
|
LDR R5, =0x00004009 ; 400b -- 88M
|
||||||
|
STR R5, [ R4 ]
|
||||||
|
|
||||||
|
;PMU_PMCR寄存器第15位需要有从低到高的翻转，才能触发PLL的时钟配置
|
||||||
|
LDR R4, =PMU_PMCR
|
||||||
|
LDR R5, =0x0000c009
|
||||||
|
STR R5, [ R4 ]
|
||||||
|
|
||||||
;****************************************************************
|
;****************************************************************
|
||||||
;* 初始化EMI
|
;* 初始化EMI
|
||||||
;****************************************************************
|
;****************************************************************
|
||||||
; LDR R4, =EMI_CSACONF ; CSA片选时序参数配置
|
|
||||||
; LDR R5, =0x08a6a6a1
|
|
||||||
; STR R5, [ R4 ]
|
|
||||||
|
|
||||||
; LDR R4, =EMI_CSECONF ; CSE片选时序参数配置,最保守配置
|
IF :DEF:INIT_EMI
|
||||||
; LDR R5, =0x8cfffff1
|
|
||||||
; STR R5, [ R4 ]
|
|
||||||
|
|
||||||
; LDR R4, =EMI_SDCONF1 ; SDRAM参数配置1
|
LDR R4, =EMI_CSACONF ; CSA片选时序参数配置
|
||||||
; LDR R5, =0x1E104177
|
LDR R5, =0x08a6a6a1
|
||||||
; STR R5, [ R4 ]
|
STR R5, [ R4 ]
|
||||||
|
|
||||||
; LDR R4, =EMI_SDCONF2 ; SDRAM参数配置2
|
LDR R4, =EMI_CSECONF ; CSE片选时序参数配置,最保守配置
|
||||||
; LDR R5, =0x80001860
|
LDR R5, =0x8cfffff1
|
||||||
; STR R5, [ R4 ]
|
STR R5, [ R4 ]
|
||||||
|
|
||||||
|
LDR R4, =EMI_SDCONF1 ; SDRAM参数配置1
|
||||||
|
LDR R5, =0x1E104177
|
||||||
|
STR R5, [ R4 ]
|
||||||
|
|
||||||
|
LDR R4, =EMI_SDCONF2 ; SDRAM参数配置2
|
||||||
|
LDR R5, =0x80001860
|
||||||
|
STR R5, [ R4 ]
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
; Copy Exception Vectors to Internal RAM
|
; Copy Exception Vectors to Internal RAM
|
||||||
|
|
||||||
IF :DEF:RAM_INTVEC
|
IF :DEF:RAM_INTVEC
|
||||||
ADR R8, Vectors ; Source
|
|
||||||
LDR R9, =RAM_BASE ; Destination
|
|
||||||
LDMIA R8!, {R0-R7} ; Load Vectors
|
|
||||||
STMIA R9!, {R0-R7} ; Store Vectors
|
|
||||||
LDMIA R8!, {R0-R7} ; Load Handler Addresses
|
|
||||||
STMIA R9!, {R0-R7} ; Store Handler Addresses
|
|
||||||
ENDIF
|
|
||||||
|
|
||||||
|
ADR R8, Vectors ; Source
|
||||||
|
LDR R9, =RAM_BASE ; Destination
|
||||||
|
LDMIA R8!, {R0-R7} ; Load Vectors
|
||||||
|
STMIA R9!, {R0-R7} ; Store Vectors
|
||||||
|
LDMIA R8!, {R0-R7} ; Load Handler Addresses
|
||||||
|
STMIA R9!, {R0-R7} ; Store Handler Addresses
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
; Remap on-chip RAM to address 0
|
; Remap on-chip RAM to address 0
|
||||||
|
|
||||||
IF :DEF:REMAP
|
IF :DEF:REMAP
|
||||||
LDR R0, =EMI_REMAPCONF
|
|
||||||
MOV R1, #0x80000000
|
|
||||||
STR R1, [R0, #0] ; Remap
|
|
||||||
ENDIF
|
|
||||||
|
|
||||||
|
LDR R0, =EMI_REMAPCONF
|
||||||
|
IF :DEF:RAM_INTVEC
|
||||||
|
MOV R1, #0x80000000
|
||||||
|
ELSE
|
||||||
|
MOV R1, #0x0000000b
|
||||||
|
ENDIF
|
||||||
|
STR R1, [R0, #0] ; Remap
|
||||||
|
|
||||||
; Setup Stack for each mode
|
ENDIF
|
||||||
|
|
||||||
LDR R0, =Stack_Top
|
;***************************************************************
|
||||||
|
;* Open irq interrupt
|
||||||
; Enter Undefined Instruction Mode and set its Stack Pointer
|
;***************************************************************
|
||||||
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
|
|
||||||
MOV SP, R0
|
|
||||||
SUB R0, R0, #UND_Stack_Size
|
|
||||||
|
|
||||||
; Enter Abort Mode and set its Stack Pointer
|
|
||||||
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
|
|
||||||
MOV SP, R0
|
|
||||||
SUB R0, R0, #ABT_Stack_Size
|
|
||||||
|
|
||||||
; Enter FIQ Mode and set its Stack Pointer
|
|
||||||
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
|
|
||||||
MOV SP, R0
|
|
||||||
SUB R0, R0, #FIQ_Stack_Size
|
|
||||||
|
|
||||||
; Enter IRQ Mode and set its Stack Pointer
|
|
||||||
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
|
|
||||||
MOV SP, R0
|
|
||||||
SUB R0, R0, #IRQ_Stack_Size
|
|
||||||
|
|
||||||
; Enter Supervisor Mode and set its Stack Pointer
|
|
||||||
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
|
|
||||||
MOV SP, R0
|
|
||||||
SUB R0, R0, #SVC_Stack_Size
|
|
||||||
|
|
||||||
; Enter User Mode and set its Stack Pointer
|
|
||||||
; MSR CPSR_c, #Mode_USR
|
|
||||||
IF :DEF:__MICROLIB
|
|
||||||
|
|
||||||
EXPORT __initial_sp
|
|
||||||
|
|
||||||
ELSE
|
|
||||||
|
|
||||||
; No usr mode stack here.
|
|
||||||
;MOV SP, R0
|
|
||||||
;SUB SL, SP, #USR_Stack_Size
|
|
||||||
|
|
||||||
ENDIF
|
|
||||||
|
|
||||||
|
MRS R4, cpsr
|
||||||
|
BIC R4, R4, #0x80 ; set bit7 to zero
|
||||||
|
MSR cpsr_c, R4
|
||||||
|
|
||||||
; Enter the C code
|
; Enter the C code
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0,=__main
|
||||||
|
BX R0
|
||||||
|
|
||||||
IMPORT __main
|
|
||||||
LDR R0, =__main
|
|
||||||
BX R0
|
|
||||||
|
|
||||||
IMPORT rt_interrupt_enter
|
IMPORT rt_interrupt_enter
|
||||||
IMPORT rt_interrupt_leave
|
IMPORT rt_interrupt_leave
|
||||||
IMPORT rt_thread_switch_interrput_flag
|
IMPORT rt_thread_switch_interrput_flag
|
||||||
IMPORT rt_interrupt_from_thread
|
IMPORT rt_interrupt_from_thread
|
||||||
IMPORT rt_interrupt_to_thread
|
IMPORT rt_interrupt_to_thread
|
||||||
IMPORT rt_hw_trap_irq
|
IMPORT rt_hw_trap_irq
|
||||||
IMPORT rt_hw_trap_abort
|
|
||||||
IMPORT rt_interrupt_nest
|
|
||||||
|
|
||||||
Abort_Handler PROC
|
IRQ_Handler PROC
|
||||||
EXPORT Abort_Handler
|
EXPORT IRQ_Handler
|
||||||
STMFD SP!, {R0-R12,LR}
|
STMFD sp!, {r0-r12,lr}
|
||||||
LDR R0, =rt_interrupt_nest
|
BL rt_interrupt_enter
|
||||||
LDR R1, [R0]
|
BL rt_hw_trap_irq
|
||||||
CMP R1, #0
|
BL rt_interrupt_leave
|
||||||
DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system.
|
|
||||||
BL rt_interrupt_enter
|
|
||||||
BL rt_hw_trap_abort
|
|
||||||
BL rt_interrupt_leave
|
|
||||||
B SWITCH
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
IRQ_Handler PROC
|
; if rt_thread_switch_interrput_flag set, jump to
|
||||||
EXPORT IRQ_Handler
|
; rt_hw_context_switch_interrupt_do and don't return
|
||||||
STMFD SP!, {R0-R12,LR}
|
LDR r0, =rt_thread_switch_interrput_flag
|
||||||
BL rt_interrupt_enter
|
LDR r1, [r0]
|
||||||
BL rt_hw_trap_irq
|
CMP r1, #1
|
||||||
BL rt_interrupt_leave
|
BEQ rt_hw_context_switch_interrupt_do
|
||||||
|
|
||||||
; if rt_thread_switch_interrput_flag set, jump to
|
LDMFD sp!, {r0-r12,lr}
|
||||||
; rt_hw_context_switch_interrupt_do and don't return
|
SUBS pc, lr, #4
|
||||||
SWITCH
|
ENDP
|
||||||
LDR R0, =rt_thread_switch_interrput_flag
|
|
||||||
LDR R1, [R0]
|
|
||||||
CMP R1, #1
|
|
||||||
BEQ rt_hw_context_switch_interrupt_do
|
|
||||||
|
|
||||||
LDMFD SP!, {R0-R12,LR}
|
|
||||||
SUBS PC, LR, #4
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
; /*
|
; /*
|
||||||
; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
|
; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
|
||||||
; */
|
; */
|
||||||
rt_hw_context_switch_interrupt_do PROC
|
rt_hw_context_switch_interrupt_do PROC
|
||||||
EXPORT rt_hw_context_switch_interrupt_do
|
EXPORT rt_hw_context_switch_interrupt_do
|
||||||
MOV r1, #0 ; clear flag
|
MOV r1, #0 ; clear flag
|
||||||
STR r1, [r0]
|
STR r1, [r0]
|
||||||
|
|
||||||
LDMFD sp!, {r0-r12,lr}; reload saved registers
|
LDMFD sp!, {r0-r12,lr}; reload saved registers
|
||||||
STMFD sp!, {r0-r3} ; save r0-r3
|
STMFD sp!, {r0-r3} ; save r0-r3
|
||||||
MOV r1, sp
|
MOV r1, sp
|
||||||
ADD sp, sp, #16 ; restore sp
|
ADD sp, sp, #16 ; restore sp
|
||||||
SUB r2, lr, #4 ; save old task's pc to r2
|
SUB r2, lr, #4 ; save old task's pc to r2
|
||||||
|
|
||||||
MRS r3, spsr ; get cpsr of interrupt thread
|
MRS r3, spsr ; get cpsr of interrupt thread
|
||||||
|
|
||||||
; switch to SVC mode and no interrupt
|
; switch to SVC mode and no interrupt
|
||||||
MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC
|
MSR cpsr_c, #I_Bit :OR F_Bit :OR Mode_SVC
|
||||||
|
|
||||||
STMFD sp!, {r2} ; push old task's pc
|
STMFD sp!, {r2} ; push old task's pc
|
||||||
STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
|
STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
|
||||||
MOV r4, r1 ; Special optimised code below
|
MOV r4, r1 ; Special optimised code below
|
||||||
MOV r5, r3
|
MOV r5, r3
|
||||||
LDMFD r4!, {r0-r3}
|
LDMFD r4!, {r0-r3}
|
||||||
STMFD sp!, {r0-r3} ; push old task's r3-r0
|
STMFD sp!, {r0-r3} ; push old task's r3-r0
|
||||||
STMFD sp!, {r5} ; push old task's cpsr
|
STMFD sp!, {r5} ; push old task's cpsr
|
||||||
MRS r4, spsr
|
MRS r4, spsr
|
||||||
STMFD sp!, {r4} ; push old task's spsr
|
STMFD sp!, {r4} ; push old task's spsr
|
||||||
|
|
||||||
LDR r4, =rt_interrupt_from_thread
|
LDR r4, =rt_interrupt_from_thread
|
||||||
LDR r5, [r4]
|
LDR r5, [r4]
|
||||||
STR sp, [r5] ; store sp in preempted tasks's TCB
|
STR sp, [r5] ; store sp in preempted tasks's TCB
|
||||||
|
|
||||||
LDR r6, =rt_interrupt_to_thread
|
LDR r6, =rt_interrupt_to_thread
|
||||||
LDR r6, [r6]
|
LDR r6, [r6]
|
||||||
LDR sp, [r6] ; get new task's stack pointer
|
LDR sp, [r6] ; get new task's stack pointer
|
||||||
|
|
||||||
LDMFD sp!, {r4} ; pop new task's spsr
|
LDMFD sp!, {r4} ; pop new task's spsr
|
||||||
MSR spsr_cxsf, r4
|
MSR spsr_cxsf, r4
|
||||||
LDMFD sp!, {r4} ; pop new task's psr
|
LDMFD sp!, {r4} ; pop new task's psr
|
||||||
MSR cpsr_cxsf, r4
|
MSR cpsr_cxsf, r4
|
||||||
|
|
||||||
LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
|
LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
|
||||||
ENDP
|
ENDP
|
||||||
|
|
||||||
IF :DEF:__MICROLIB
|
|
||||||
|
|
||||||
EXPORT __heap_base
|
|
||||||
EXPORT __heap_limit
|
|
||||||
|
|
||||||
ELSE
|
ALIGN
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
EXPORT __initial_sp
|
||||||
|
|
||||||
|
ELSE ;__MICROLIB
|
||||||
; User Initial Stack & Heap
|
; User Initial Stack & Heap
|
||||||
AREA |.text|, CODE, READONLY
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
IMPORT __use_two_region_memory
|
IMPORT __use_two_region_memory
|
||||||
EXPORT __user_initial_stackheap
|
EXPORT __user_initial_stackheap
|
||||||
__user_initial_stackheap
|
__user_initial_stackheap
|
||||||
|
|
||||||
LDR R0, = Heap_Mem
|
LDR R0, = Heap_Mem
|
||||||
LDR R1, = (Stack_Mem + IRQ_Stack_Size)
|
LDR R1, = (Svc_Stack + Svc_Stack_Size)
|
||||||
LDR R2, = (Heap_Mem + Heap_Size)
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
LDR R3, = Stack_Mem
|
LDR R3, = Svc_Stack
|
||||||
BX LR
|
BX LR
|
||||||
ENDIF
|
ALIGN
|
||||||
|
ENDIF
|
||||||
END
|
END
|
||||||
|
|
|
||||||
|
|
@ -9,58 +9,155 @@
|
||||||
*
|
*
|
||||||
* Change Logs:
|
* Change Logs:
|
||||||
* Date Author Notes
|
* Date Author Notes
|
||||||
* 2006-08-25 Bernard first version
|
* 2006-03-13 Bernard first version
|
||||||
* 2010-03-18 zchong for sep4020
|
* 2006-05-27 Bernard add skyeye support
|
||||||
|
* 2007-11-19 Yi.Qiu fix rt_hw_trap_irq function
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <rtthread.h>
|
#include <rtthread.h>
|
||||||
#include <rthw.h>
|
#include <rthw.h>
|
||||||
|
|
||||||
#include "sep4020.h"
|
#include <sep4020.h>
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @addtogroup SEP4020
|
* @addtogroup S3C24X0
|
||||||
*/
|
*/
|
||||||
/*@{*/
|
/*@{*/
|
||||||
|
|
||||||
|
extern struct rt_thread *rt_current_thread;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* this function will show registers of CPU
|
||||||
|
*
|
||||||
|
* @param regs the registers point
|
||||||
|
*/
|
||||||
|
|
||||||
|
void rt_hw_show_register (struct rt_hw_register *regs)
|
||||||
|
{
|
||||||
|
rt_kprintf("Execption:\n");
|
||||||
|
rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
|
||||||
|
rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
|
||||||
|
rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
|
||||||
|
rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
|
||||||
|
rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
|
||||||
|
rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* When ARM7TDMI comes across an instruction which it cannot handle,
|
||||||
|
* it takes the undefined instruction trap.
|
||||||
|
*
|
||||||
|
* @param regs system registers
|
||||||
|
*
|
||||||
|
* @note never invoke this function in application
|
||||||
|
*/
|
||||||
|
void rt_hw_trap_udef(struct rt_hw_register *regs)
|
||||||
|
{
|
||||||
|
rt_hw_show_register(regs);
|
||||||
|
|
||||||
|
rt_kprintf("undefined instruction\n");
|
||||||
|
rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
|
||||||
|
rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
|
||||||
|
|
||||||
|
rt_hw_cpu_shutdown();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* The software interrupt instruction (SWI) is used for entering
|
||||||
|
* Supervisor mode, usually to request a particular supervisor
|
||||||
|
* function.
|
||||||
|
*
|
||||||
|
* @param regs system registers
|
||||||
|
*
|
||||||
|
* @note never invoke this function in application
|
||||||
|
*/
|
||||||
|
void rt_hw_trap_swi(struct rt_hw_register *regs)
|
||||||
|
{
|
||||||
|
rt_hw_show_register(regs);
|
||||||
|
|
||||||
|
rt_kprintf("software interrupt\n");
|
||||||
|
rt_hw_cpu_shutdown();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* An abort indicates that the current memory access cannot be completed,
|
||||||
|
* which occurs during an instruction prefetch.
|
||||||
|
*
|
||||||
|
* @param regs system registers
|
||||||
|
*
|
||||||
|
* @note never invoke this function in application
|
||||||
|
*/
|
||||||
|
void rt_hw_trap_pabt(struct rt_hw_register *regs)
|
||||||
|
{
|
||||||
|
rt_hw_show_register(regs);
|
||||||
|
|
||||||
|
rt_kprintf("prefetch abort\n");
|
||||||
|
rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
|
||||||
|
rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
|
||||||
|
|
||||||
|
rt_hw_cpu_shutdown();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* An abort indicates that the current memory access cannot be completed,
|
||||||
|
* which occurs during a data access.
|
||||||
|
*
|
||||||
|
* @param regs system registers
|
||||||
|
*
|
||||||
|
* @note never invoke this function in application
|
||||||
|
*/
|
||||||
|
void rt_hw_trap_dabt(struct rt_hw_register *regs)
|
||||||
|
{
|
||||||
|
rt_hw_show_register(regs);
|
||||||
|
|
||||||
|
rt_kprintf("data abort\n");
|
||||||
|
rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
|
||||||
|
rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
|
||||||
|
|
||||||
|
rt_hw_cpu_shutdown();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Normally, system will never reach here
|
||||||
|
*
|
||||||
|
* @param regs system registers
|
||||||
|
*
|
||||||
|
* @note never invoke this function in application
|
||||||
|
*/
|
||||||
|
void rt_hw_trap_resv(struct rt_hw_register *regs)
|
||||||
|
{
|
||||||
|
rt_kprintf("not used\n");
|
||||||
|
rt_hw_show_register(regs);
|
||||||
|
rt_hw_cpu_shutdown();
|
||||||
|
}
|
||||||
|
|
||||||
extern rt_isr_handler_t isr_table[];
|
extern rt_isr_handler_t isr_table[];
|
||||||
|
|
||||||
void rt_hw_trap_irq()
|
void rt_hw_trap_irq()
|
||||||
{
|
{
|
||||||
rt_uint32_t intstat,intnum;
|
unsigned long intstat;
|
||||||
rt_uint8_t i = 0;
|
rt_uint32_t i = 0;
|
||||||
rt_isr_handler_t isr_func;
|
rt_isr_handler_t isr_func;
|
||||||
|
|
||||||
/* get interrupt source */
|
/*Get the final intrrupt source*/
|
||||||
intstat = INTC_IFSR;
|
intstat = *(RP)(INTC_IFSR);;
|
||||||
|
|
||||||
intnum = intstat;
|
/*Shift to get the intrrupt number*/
|
||||||
if (intstat == INTGLOBAL) return;
|
while(intstat != 1)
|
||||||
|
|
||||||
while(intnum != 0x00000001)
|
|
||||||
{
|
{
|
||||||
intnum = intnum>>1;
|
intstat = intstat >> 1;
|
||||||
i++;
|
i++;
|
||||||
}
|
}
|
||||||
/* get interrupt service routine */
|
/* get interrupt service routine */
|
||||||
isr_func = isr_table[i];
|
isr_func = isr_table[i];
|
||||||
|
|
||||||
/* turn to interrupt service routine */
|
/* turn to interrupt service routine */
|
||||||
isr_func(intstat);
|
isr_func(i);
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void rt_hw_trap_fiq()
|
void rt_hw_trap_fiq()
|
||||||
{
|
{
|
||||||
rt_kprintf("fast interrupt request\n");
|
rt_kprintf("fast interrupt request\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
extern struct rt_thread* rt_current_thread;
|
|
||||||
void rt_hw_trap_abort()
|
|
||||||
{
|
|
||||||
rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name);
|
|
||||||
rt_thread_suspend(rt_current_thread);
|
|
||||||
rt_schedule();
|
|
||||||
|
|
||||||
}
|
|
||||||
/*@}*/
|
/*@}*/
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue