[bsp][lpc55sxx] add i2s and wm8904 driver
This commit is contained in:
vandoul
Man, Jianting (Meco)
parent
d6e40f2a24
commit
0822f02606
@ -43,6 +43,12 @@ if GetDepend('BSP_USING_WDT'):
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if GetDepend('BSP_USING_PWM'):
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src += ['drv_pwm.c']
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if GetDepend('BSP_USING_I2S'):
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src += ['drv_i2s.c']
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if GetDepend('BSP_USING_WM8904'):
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src += ['drv_sound_wm8904.c']
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path = [cwd,cwd + '/config']
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
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301
bsp/lpc55sxx/Libraries/drivers/drv_i2s.c
Normal file
301
bsp/lpc55sxx/Libraries/drivers/drv_i2s.c
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@ -0,0 +1,301 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-03-12 Vandoul the first version
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*/
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#include <rtthread.h>
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#include "fsl_i2s.h"
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#include "fsl_i2s_dma.h"
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#include "drv_i2s.h"
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#define DBG_TAG "DRVI2S"
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#include "rtdbg.h"
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#ifdef BSP_USING_I2S
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#if !defined(BSP_USING_I2S0) && \
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!defined(BSP_USING_I2S1) && \
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!defined(BSP_USING_I2S2) && \
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!defined(BSP_USING_I2S3) && \
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!defined(BSP_USING_I2S4) && \
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!defined(BSP_USING_I2S5) && \
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!defined(BSP_USING_I2S6) && \
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!defined(BSP_USING_I2S7)
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#error "Please define at least one I2Sx"
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#endif
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#include <rtdevice.h>
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enum {
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#ifdef BSP_USING_I2S0
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I2S0_INDEX,
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#endif
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#ifdef BSP_USING_I2S1
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I2S1_INDEX,
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#endif
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#ifdef BSP_USING_I2S2
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I2S2_INDEX,
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#endif
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#ifdef BSP_USING_I2S3
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I2S3_INDEX,
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#endif
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#ifdef BSP_USING_I2S4
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I2S4_INDEX,
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#endif
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#ifdef BSP_USING_I2S5
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I2S5_INDEX,
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#endif
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#ifdef BSP_USING_I2S6
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I2S6_INDEX,
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#endif
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#ifdef BSP_USING_I2S7
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I2S7_INDEX,
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#endif
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};
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struct lpc_i2s_clock_and_irq_param
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{
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clock_attach_id_t i2s_clock;
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reset_ip_name_t i2s_reset_bit;
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IRQn_Type irq_type;
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};
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struct lpc_i2s
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{
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struct rt_device device;
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i2s_handle_t i2s_handle;
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struct lpc_i2s_config config;
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uint32_t index;
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I2S_Type *i2s_base;
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const char *device_name;
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};
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#define LPC_I2S_CONFIG_MODE_IS_SLAVE(dev) ((dev)->config.mode == LPC_I2S_CONFIG_MODE_SLAVE)
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#define LPC_I2S_CONFIG_MODE_IS_MASTER(dev) ((dev)->config.mode == LPC_I2S_CONFIG_MODE_MASTER)
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#define LPC_I2S_CLOCK_AND_IRQ_PARAM_INIT(index) {.i2s_clock = kPLL0_DIV_to_FLEXCOMM##index, .i2s_reset_bit = kFC##index##_RST_SHIFT_RSTn, .irq_type = FLEXCOMM##index##_IRQn,}
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const static struct lpc_i2s_clock_and_irq_param lpc_i2s_clock_and_irq_param_table[] =
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{
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#ifdef BSP_USING_I2S0
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// {.i2s_clock = kPLL0_DIV_to_FLEXCOMM0, .i2s_reset_bit = kFC0_RST_SHIFT_RSTn, .irq_type = FLEXCOMM0_IRQn,},
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LPC_I2S_CLOCK_AND_IRQ_PARAM_INIT(0),
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#endif
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#ifdef BSP_USING_I2S1
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LPC_I2S_CLOCK_AND_IRQ_PARAM_INIT(1),
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#endif
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#ifdef BSP_USING_I2S2
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LPC_I2S_CLOCK_AND_IRQ_PARAM_INIT(2),
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#endif
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#ifdef BSP_USING_I2S3
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LPC_I2S_CLOCK_AND_IRQ_PARAM_INIT(3),
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#endif
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#ifdef BSP_USING_I2S4
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LPC_I2S_CLOCK_AND_IRQ_PARAM_INIT(4),
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#endif
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#ifdef BSP_USING_I2S5
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LPC_I2S_CLOCK_AND_IRQ_PARAM_INIT(5),
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#endif
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#ifdef BSP_USING_I2S6
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LPC_I2S_CLOCK_AND_IRQ_PARAM_INIT(6),
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#endif
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#ifdef BSP_USING_I2S7
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LPC_I2S_CLOCK_AND_IRQ_PARAM_INIT(7),
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#endif
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};
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static struct lpc_i2s lpc_i2s_table[] =
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{
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#ifdef BSP_USING_I2S0
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{.index = I2S0_INDEX,.i2s_base = I2S0,.device_name = "i2s0"},
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#endif
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#ifdef BSP_USING_I2S1
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{.index = I2S1_INDEX,.i2s_base = I2S1,.device_name = "i2s1"},
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#endif
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#ifdef BSP_USING_I2S2
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{.index = I2S2_INDEX,.i2s_base = I2S2,.device_name = "i2s2"},
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#endif
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#ifdef BSP_USING_I2S3
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{.index = I2S3_INDEX,.i2s_base = I2S3,.device_name = "i2s3"},
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#endif
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#ifdef BSP_USING_I2S4
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{.index = I2S4_INDEX,.i2s_base = I2S4,.device_name = "i2s4"},
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#endif
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#ifdef BSP_USING_I2S5
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{.index = I2S5_INDEX,.i2s_base = I2S5,.device_name = "i2s5"},
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#endif
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#ifdef BSP_USING_I2S6
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{.index = I2S6_INDEX,.i2s_base = I2S6,.device_name = "i2s6"},
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#endif
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#ifdef BSP_USING_I2S7
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{.index = I2S7_INDEX,.i2s_base = I2S7,.device_name = "i2s7"},
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#endif
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};
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static void transfer_callback(I2S_Type *base, i2s_handle_t *handle, status_t completionStatus, void *userData)
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{
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struct lpc_i2s *i2s_dev = rt_container_of(handle, struct lpc_i2s, i2s_handle);
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if(LPC_I2S_CONFIG_MODE_IS_SLAVE(i2s_dev))
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{
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if(i2s_dev->device.rx_indicate != RT_NULL)
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{
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i2s_dev->device.rx_indicate(&i2s_dev->device, completionStatus);
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}
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}
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else
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{
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if(i2s_dev->device.tx_complete != RT_NULL)
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{
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i2s_dev->device.tx_complete(&i2s_dev->device, RT_NULL);
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}
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}
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}
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static void i2s_clock_and_irq_config(struct lpc_i2s *dev)
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{
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const struct lpc_i2s_clock_and_irq_param *clock_and_irq_param = &lpc_i2s_clock_and_irq_param_table[dev->index];
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// CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true);
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// CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 1U, false);
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CLOCK_AttachClk(clock_and_irq_param->i2s_clock);
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RESET_PeripheralReset(clock_and_irq_param->i2s_reset_bit);
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NVIC_ClearPendingIRQ(clock_and_irq_param->irq_type);
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/* Enable interrupts for I2S */
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EnableIRQ(clock_and_irq_param->irq_type);
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}
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rt_err_t rt_i2s_init(rt_device_t dev)
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{
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struct lpc_i2s *i2s_dev = rt_container_of(dev, struct lpc_i2s, device);
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i2s_clock_and_irq_config(i2s_dev);
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return RT_EOK;
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}
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rt_err_t rt_i2s_open(rt_device_t dev, rt_uint16_t oflag)
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{
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struct lpc_i2s *i2s_dev = rt_container_of(dev, struct lpc_i2s, device);
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i2s_config_t config;
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if(i2s_dev->config.mode == LPC_I2S_CONFIG_MODE_SLAVE)
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{
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RT_ASSERT(i2s_dev->config.is_blocking == 0);
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I2S_RxGetDefaultConfig(&config);
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config.divider = CLOCK_GetPll0OutFreq()/i2s_dev->config.sampling_rate/i2s_dev->config.data_bits/i2s_dev->config.channels;
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config.masterSlave = kI2S_MasterSlaveNormalSlave;
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I2S_RxInit(i2s_dev->i2s_base, &config);
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I2S_RxTransferCreateHandle(i2s_dev->i2s_base, &i2s_dev->i2s_handle, transfer_callback, NULL);
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}
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else if(i2s_dev->config.mode == LPC_I2S_CONFIG_MODE_MASTER)
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{
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RT_ASSERT(i2s_dev->config.is_blocking == 0);
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I2S_TxGetDefaultConfig(&config);
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config.divider = CLOCK_GetPll0OutFreq()/i2s_dev->config.sampling_rate/i2s_dev->config.data_bits/i2s_dev->config.channels;
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config.masterSlave = kI2S_MasterSlaveNormalMaster;
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I2S_TxInit(i2s_dev->i2s_base, &config);
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I2S_TxTransferCreateHandle(i2s_dev->i2s_base, &i2s_dev->i2s_handle, transfer_callback, NULL);
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}
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return RT_EOK;
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}
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rt_err_t rt_i2s_close(rt_device_t dev)
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{
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struct lpc_i2s *i2s_dev = rt_container_of(dev, struct lpc_i2s, device);
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I2S_Deinit(i2s_dev->i2s_base);
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return RT_EOK;
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}
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rt_ssize_t rt_i2s_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
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{
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struct lpc_i2s *i2s_dev = rt_container_of(dev, struct lpc_i2s, device);
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if(!LPC_I2S_CONFIG_MODE_IS_SLAVE(i2s_dev))
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{
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return -RT_ERROR;
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}
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i2s_transfer_t transfer;
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transfer.data = buffer;
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transfer.dataSize = size;
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if(kStatus_Success == I2S_RxTransferNonBlocking(i2s_dev->i2s_base, &i2s_dev->i2s_handle, transfer))
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return size;
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else
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return -RT_EBUSY;
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}
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rt_ssize_t rt_i2s_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
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{
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struct lpc_i2s *i2s_dev = rt_container_of(dev, struct lpc_i2s, device);
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if(!LPC_I2S_CONFIG_MODE_IS_MASTER(i2s_dev))
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{
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return -RT_ERROR;
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}
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i2s_transfer_t transfer;
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transfer.data = (uint8_t *)buffer;
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transfer.dataSize = size;
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if(kStatus_Success == I2S_TxTransferNonBlocking(i2s_dev->i2s_base, &i2s_dev->i2s_handle, transfer))
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return size;
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else
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return -RT_EBUSY;
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}
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rt_err_t rt_i2s_control(rt_device_t dev, int cmd, void *args)
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{
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struct lpc_i2s *i2s_dev = rt_container_of(dev, struct lpc_i2s, device);
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rt_err_t ret = RT_EOK;
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RT_ASSERT(dev != RT_NULL);
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RT_ASSERT(args != RT_NULL);
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switch(cmd)
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{
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case RT_I2S_CTRL_RESET:
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i2s_clock_and_irq_config(i2s_dev);
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break;
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case RT_I2S_CTRL_SET_CONFIG:
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{
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struct lpc_i2s_config *config = (struct lpc_i2s_config *)args;
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i2s_dev->config = *config;
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}
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break;
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default:
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ret = -RT_ERROR;
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break;
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}
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return ret;
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}
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#ifdef RT_USING_DEVICE_OPS
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const static struct rt_device_ops i2s_core_ops =
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{
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rt_i2s_init,
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rt_i2s_open,
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rt_i2s_close,
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rt_i2s_read,
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rt_i2s_write,
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rt_i2s_control,
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};
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#endif /* RT_USING_DEVICE_OPS */
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int rt_hw_i2s_init(void)
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{
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struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
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int i;
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for (i = 0; i < sizeof(lpc_i2s_table) / sizeof(lpc_i2s_table[0]); i++)
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{
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#ifdef RT_USING_DEVICE_OPS
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lpc_i2s_table[i].device.ops = &i2s_core_ops;
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#else
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lpc_i2s_table[i].device.init = rt_i2s_init;
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lpc_i2s_table[i].device.open = rt_i2s_open;
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lpc_i2s_table[i].device.close = rt_i2s_close;
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lpc_i2s_table[i].device.read = rt_i2s_read;
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lpc_i2s_table[i].device.write = rt_i2s_write;
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lpc_i2s_table[i].device.control = rt_i2s_control;
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#endif
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/* register UART device */
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rt_device_register(&lpc_i2s_table[i].device,
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lpc_i2s_table[i].device_name,
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
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}
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return 0;
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}
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INIT_BOARD_EXPORT(rt_hw_i2s_init);
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#endif
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43
bsp/lpc55sxx/Libraries/drivers/drv_i2s.h
Normal file
43
bsp/lpc55sxx/Libraries/drivers/drv_i2s.h
Normal file
@ -0,0 +1,43 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-03-12 Vandoul the first version
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*/
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#ifndef __DRV_I2S_H__
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#define __DRV_I2S_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rtthread.h>
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#pragma pack(push,1)
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struct lpc_i2s_config
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{
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uint32_t sampling_rate;
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uint8_t mode;
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uint8_t data_bits;
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uint8_t channels;
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uint8_t is_blocking;
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};
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#pragma pack(pop)
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#define LPC_I2S_CONFIG_MODE_NULL 0
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#define LPC_I2S_CONFIG_MODE_SLAVE 1
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#define LPC_I2S_CONFIG_MODE_MASTER 2
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#define RT_I2S_CTRL_RESET (RT_DEVICE_CTRL_BASE(Bus) + 1)
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#define RT_I2S_CTRL_SET_CONFIG (RT_DEVICE_CTRL_BASE(Bus) + 2)
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#ifdef __cplusplus
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}
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#endif
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#endif
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1123
bsp/lpc55sxx/Libraries/drivers/drv_sound_wm8904.c
Normal file
1123
bsp/lpc55sxx/Libraries/drivers/drv_sound_wm8904.c
Normal file
File diff suppressed because it is too large
Load Diff
214
bsp/lpc55sxx/Libraries/drivers/drv_sound_wm8904.h
Normal file
214
bsp/lpc55sxx/Libraries/drivers/drv_sound_wm8904.h
Normal file
@ -0,0 +1,214 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-03-12 Vandoul the first version
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*/
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#ifndef __DRV_SOUND_WM8904_H__
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#define __DRV_SOUND_WM8904_H__
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#include <rtthread.h>
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typedef enum
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{
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WM8904_RESET = 0x00,
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WM8904_ANALOG_ADC_0 = 0x0A,
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WM8904_POWER_MGMT_0 = 0x0C,
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WM8904_POWER_MGMT_2 = 0x0E,
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WM8904_POWER_MGMT_3 = 0x0F,
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WM8904_POWER_MGMT_6 = 0x12,
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WM8904_CLK_RATES_0 = 0x14,
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WM8904_CLK_RATES_1 = 0x15,
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WM8904_CLK_RATES_2 = 0x16,
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WM8904_AUDIO_IF_0 = 0x18,
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WM8904_AUDIO_IF_1 = 0x19,
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WM8904_AUDIO_IF_2 = 0x1A,
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WM8904_AUDIO_IF_3 = 0x1B,
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WM8904_DAC_DIG_1 = 0x21,
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WM8904_DAC_DIG_0 = 0x27,
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WM8904_ANALOG_LEFT_IN_0 = 0x2C,
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WM8904_ANALOG_RIGHT_IN_0 = 0x2D,
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WM8904_ANALOG_LEFT_IN_1 = 0x2E,
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WM8904_ANALOG_RIGHT_IN_1 = 0x2F,
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WM8904_ANALOG_OUT1_LEFT = 0x39,
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WM8904_ANALOG_OUT1_RIGHT = 0x3A,
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WM8904_ANALOG_OUT12_ZC = 0x3D,
|
||||
WM8904_DC_SERVO_0 = 0x43,
|
||||
WM8904_ANALOG_HP_0 = 0x5A,
|
||||
WM8904_CHRG_PUMP_0 = 0x62,
|
||||
WM8904_CLS_W_0 = 0x68,
|
||||
WM8904_WRT_SEQUENCER_0 = 0x6C,
|
||||
WM8904_WRT_SEQUENCER_3 = 0x6F,
|
||||
WM8904_WRT_SEQUENCER_4 = 0x70,
|
||||
WM8904_DAC_DIGITAL_VOLUME_LEFT = 0x1E,
|
||||
WM8904_DAC_DIGITAL_VOLUME_RIGHT = 0x1F,
|
||||
WM8904_ADC_DIGITAL_VOLUME_LEFT = 0x24,
|
||||
WM8904_ADC_DIGITAL_VOLUME_RIGHT = 0x25,
|
||||
WM8904_ANALOG_OUT2_LEFT = 0x3B,
|
||||
WM8904_ANALOG_OUT2_RIGHT = 0x3C,
|
||||
/* FLL control register */
|
||||
WM8904_FLL_CONTROL_1 = 0x74,
|
||||
WM8904_FLL_CONTROL_2 = 0x75,
|
||||
WM8904_FLL_CONTROL_3 = 0x76,
|
||||
WM8904_FLL_CONTROL_4 = 0x77,
|
||||
WM8904_FLL_CONTROL_5 = 0x78,
|
||||
/* GPIO control register */
|
||||
WM8904_GPIO_CONTROL_1 = 0x79,
|
||||
WM8904_GPIO_CONTROL_2 = 0x7A,
|
||||
WM8904_GPIO_CONTROL_3 = 0x7B,
|
||||
WM8904_GPIO_CONTROL_4 = 0x7C,
|
||||
/* FLL nco */
|
||||
WM89004_FLL_NCO_TEST_0 = 0xF7,
|
||||
WM89004_FLL_NCO_TEST_1 = 0xF8,
|
||||
}wm8904_reg_t;
|
||||
|
||||
#define WM8904_LRC_POLARITY_POS (4U)
|
||||
#define WM8904_LRC_POLARITY_NOOMAL (0)
|
||||
#define WM8904_LRC_POLARITY_INVERTED (1U << WM8904_LRC_POLARITY_POS)
|
||||
|
||||
typedef enum _wm8904_module
|
||||
{
|
||||
WM8904_MODULE_ADC = 0, /*!< module ADC */
|
||||
WM8904_MODULE_DAC, /*!< module DAC */
|
||||
WM8904_MODULE_PGA, /*!< module PGA */
|
||||
WM8904_MODULE_HEADPHONE, /*!< module headphone */
|
||||
WM8904_MODULE_LINEOUT, /*!< module line out */
|
||||
}wm8904_module_t;
|
||||
|
||||
enum
|
||||
{
|
||||
WM8904_HEADPHONE_LEFT = 1U,
|
||||
WM8904_HEADPHONE_RIGHT = 2U,
|
||||
WM8904_LINEOUT_LEFT = 4U,
|
||||
WM8904_LINEOUT_RIGHT = 8U,
|
||||
};
|
||||
|
||||
typedef enum _wm8904_timeslot{
|
||||
WM8904_TIMESLOT_0 = 0U,
|
||||
WM8904_TIMESLOT_1,
|
||||
}wm8904_timeslot_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
WM8904_PROTOCOL_RIGHT_JUSTIFIED = 0x00,
|
||||
WM8904_PROTOCOL_LEFT_JUSTIFIED = 0x01,
|
||||
WM8904_PROTOCOL_I2S = 0x02,
|
||||
WM8904_PROTOCOL_PCMA = 0x03,
|
||||
WM8904_PROTOCOL_PCMB = 0x13,
|
||||
}wm8904_protocol_t;
|
||||
|
||||
/*! @brief The SYSCLK / fs ratio. */
|
||||
typedef enum _wm8904_fs_ratio
|
||||
{
|
||||
WM8904_FSRATIO_64X = 0x0, /*!< SYSCLK is 64 * sample rate * frame width */
|
||||
WM8904_FSRATIO_128X = 0x1, /*!< SYSCLK is 128 * sample rate * frame width */
|
||||
WM8904_FSRATIO_192X = 0x2, /*!< SYSCLK is 192 * sample rate * frame width */
|
||||
WM8904_FSRATIO_256X = 0x3, /*!< SYSCLK is 256 * sample rate * frame width */
|
||||
WM8904_FSRATIO_384X = 0x4, /*!< SYSCLK is 384 * sample rate * frame width */
|
||||
WM8904_FSRATIO_512X = 0x5, /*!< SYSCLK is 512 * sample rate * frame width */
|
||||
WM8904_FSRATIO_768X = 0x6, /*!< SYSCLK is 768 * sample rate * frame width */
|
||||
WM8904_FSRATIO_1024X = 0x7, /*!< SYSCLK is 1024 * sample rate * frame width */
|
||||
WM8904_FSRATIO_1408X = 0x8, /*!< SYSCLK is 1408 * sample rate * frame width */
|
||||
WM8904_FSRATIO_1536X = 0x9 /*!< SYSCLK is 1536 * sample rate * frame width */
|
||||
} wm8904_fs_ratio_t;
|
||||
|
||||
/*! @brief Sample rate. */
|
||||
typedef enum _wm8904_sample_rate
|
||||
{
|
||||
WM8904_SAMPLERATE_8kHz = 0x0, /*!< 8 kHz */
|
||||
WM8904_SAMPLERATE_12kHz = 0x1, /*!< 12kHz */
|
||||
WM8904_SAMPLERATE_16kHz = 0x2, /*!< 16kHz */
|
||||
WM8904_SAMPLERATE_24kHz = 0x3, /*!< 24kHz */
|
||||
WM8904_SAMPLERATE_32kHz = 0x4, /*!< 32kHz */
|
||||
WM8904_SAMPLERATE_48kHz = 0x5, /*!< 48kHz */
|
||||
WM8904_SAMPLERATE_11025Hz = 0x6, /*!< 11.025kHz */
|
||||
WM8904_SAMPLERATE_22050Hz = 0x7, /*!< 22.05kHz */
|
||||
WM8904_SAMPLERATE_44100Hz = 0x8 /*!< 44.1kHz */
|
||||
} wm8904_sample_rate_t;
|
||||
|
||||
/*! @brief Bit width. */
|
||||
typedef enum _wm8904_bit_width
|
||||
{
|
||||
WM8904_BITWIDTH_16 = 0x0, /*!< 16 bits */
|
||||
WM8904_BITWIDTH_20 = 0x1, /*!< 20 bits */
|
||||
WM8904_BITWIDTH_24 = 0x2, /*!< 24 bits */
|
||||
WM8904_BITWIDTH_32 = 0x3 /*!< 32 bits */
|
||||
} wm8904_bit_width_t;
|
||||
|
||||
enum
|
||||
{
|
||||
WM8904_RECORD_SOURCE_DIFFERENTIAL_LINE = 1U, /*!< record source from differential line */
|
||||
WM8904_RECORD_SOURCE_LINE_INPUT = 2U, /*!< record source from line input */
|
||||
WM8904_RECORD_SOURCE_DIFFERENTIAL_MIC = 4U, /*!< record source from differential mic */
|
||||
WM8904_RECORD_SOURCE_DIGITAL_MIC = 8U, /*!< record source from digital microphone */
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
WM8904_RECORD_CHANNEL_LEFT1 = 1U, /*!< left record channel 1 */
|
||||
WM8904_RECORD_CHANNEL_LEFT2 = 2U, /*!< left record channel 2 */
|
||||
WM8904_RECORD_CHANNEL_LEFT3 = 4U, /*!< left record channel 3 */
|
||||
WM8904_RECORD_CHANNEL_RIGHT1 = 1U, /*!< right record channel 1 */
|
||||
WM8904_RECORD_CHANNEL_RIGHT2 = 2U, /*!< right record channel 2 */
|
||||
WM8904_RECORD_CHANNEL_RIGHT3 = 4U, /*!< right record channel 3 */
|
||||
WM8904_RECORD_CHANNEL_DIFFERENTIAL_POSITIVE1 = 1U, /*!< differential positive record channel 1 */
|
||||
WM8904_RECORD_CHANNEL_DIFFERENTIAL_POSITIVE2 = 2U, /*!< differential positive record channel 2 */
|
||||
WM8904_RECORD_CHANNEL_DIFFERENTIAL_POSITIVE3 = 4U, /*!< differential positive record channel 3 */
|
||||
WM8904_RECORD_CHANNEL_DIFFERENTIAL_NEGATIVE1 = 8U, /*!< differential negative record channel 1 */
|
||||
WM8904_RECORD_CHANNEL_DIFFERENTIAL_NEGATIVE2 = 16U, /*!< differential negative record channel 2 */
|
||||
WM8904_RECORD_CHANNEL_DIFFERENTIAL_NEGATIVE3 = 32U, /*!< differential negative record channel 3 */
|
||||
};
|
||||
|
||||
/*! @brief wm8904 play source
|
||||
*
|
||||
*/
|
||||
enum
|
||||
{
|
||||
WM8904_PLAY_SOURCE_PGA = 1U, /*!< play source PGA, bypass ADC */
|
||||
WM8904_PLAY_SOURCE_DAC = 4U, /*!< play source Input3 */
|
||||
};
|
||||
|
||||
/*! @brief wm8904_fll_clk_source */
|
||||
typedef enum _wm8904_fll_clk_source
|
||||
{
|
||||
WM8904_FLL_CLK_SOURCE_MCLK = 0U, /**< wm8904 FLL clock source from MCLK */
|
||||
}wm8904_fll_clk_source_t;
|
||||
|
||||
/*! @brief wm8904 fll configuration */
|
||||
typedef struct _wm8904_fll_config
|
||||
{
|
||||
wm8904_fll_clk_source_t source; /*!< fll reference clock source */
|
||||
rt_uint32_t ref_clock_hz; /*!< fll reference clock frequency */
|
||||
rt_uint32_t output_clock_hz; /*!< fll output clock frequency */
|
||||
}wm8904_fll_config_t;
|
||||
|
||||
/*! @brief Audio format configuration. */
|
||||
typedef struct _wm8904_audio_format
|
||||
{
|
||||
wm8904_fs_ratio_t fsRatio; /*!< SYSCLK / fs ratio */
|
||||
wm8904_sample_rate_t sampleRate; /*!< Sample rate */
|
||||
wm8904_bit_width_t bitWidth; /*!< Bit width */
|
||||
} wm8904_audio_format_t;
|
||||
|
||||
struct wm8904_config
|
||||
{
|
||||
const char *i2c_bus_name;
|
||||
const char *i2s_bus_name;
|
||||
int i2c_addr;
|
||||
wm8904_protocol_t protocol;
|
||||
wm8904_audio_format_t format;
|
||||
};
|
||||
|
||||
#define WM8904_I2C_ADDRESS (0x1A)
|
||||
#define WM8904_I2C_BITRATE (400000U)
|
||||
|
||||
/* WM8904 maximum volume */
|
||||
#define WM8904_MAP_HEADPHONE_LINEOUT_MAX_VOLUME 0x3FU
|
||||
#define WM8904_DAC_MAX_VOLUME 0xC0U
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user