From 05cc8415ad0b8ef36f4f6c6987528d8d12c8c02f Mon Sep 17 00:00:00 2001 From: lin <429426691@qq.com> Date: Fri, 21 Sep 2018 16:10:44 +0800 Subject: [PATCH] [BSP]Add sct and fix some drivers bug --- bsp/apollo2/board/adc.c | 87 +- bsp/apollo2/board/adc.h | 6 +- bsp/apollo2/board/board.c | 6 +- bsp/apollo2/board/flash.c | 2 +- bsp/apollo2/board/gpio.c | 146 +- bsp/apollo2/board/i2c.c | 44 +- bsp/apollo2/board/pdm.c | 101 +- bsp/apollo2/board/pdm.h | 2 +- bsp/apollo2/board/pwm.h | 2 + bsp/apollo2/board/rtc.c | 1 - bsp/apollo2/board/smbus.c | 17 +- bsp/apollo2/board/spi.c | 92 +- bsp/apollo2/board/uart.c | 21 +- bsp/apollo2/libraries/drivers/SConscript | 1 + bsp/apollo2/libraries/drivers/am_mcu_apollo.h | 2 +- .../libraries/drivers/hal/am_hal_adc.c | 2 +- .../libraries/drivers/hal/am_hal_adc.h | 12 +- .../libraries/drivers/hal/am_hal_cachectrl.c | 2 +- .../libraries/drivers/hal/am_hal_cachectrl.h | 12 +- .../libraries/drivers/hal/am_hal_clkgen.c | 28 +- .../libraries/drivers/hal/am_hal_clkgen.h | 12 +- .../libraries/drivers/hal/am_hal_ctimer.c | 21 +- .../libraries/drivers/hal/am_hal_ctimer.h | 14 +- .../libraries/drivers/hal/am_hal_debug.c | 2 +- .../libraries/drivers/hal/am_hal_debug.h | 12 +- .../libraries/drivers/hal/am_hal_flash.c | 43 +- .../libraries/drivers/hal/am_hal_flash.h | 28 +- .../libraries/drivers/hal/am_hal_global.c | 2 +- .../libraries/drivers/hal/am_hal_global.h | 12 +- .../libraries/drivers/hal/am_hal_gpio.c | 4 +- .../libraries/drivers/hal/am_hal_gpio.h | 19 +- .../drivers/hal/am_hal_i2c_bit_bang.c | 22 +- .../drivers/hal/am_hal_i2c_bit_bang.h | 21 +- .../libraries/drivers/hal/am_hal_interrupt.c | 8 +- .../libraries/drivers/hal/am_hal_interrupt.h | 11 +- .../libraries/drivers/hal/am_hal_iom.c | 1633 ++++++++++++----- .../libraries/drivers/hal/am_hal_iom.h | 120 +- .../libraries/drivers/hal/am_hal_ios.c | 56 +- .../libraries/drivers/hal/am_hal_ios.h | 10 +- .../libraries/drivers/hal/am_hal_itm.c | 31 +- .../libraries/drivers/hal/am_hal_itm.h | 13 +- .../libraries/drivers/hal/am_hal_mcuctrl.c | 2 +- .../libraries/drivers/hal/am_hal_mcuctrl.h | 12 +- .../libraries/drivers/hal/am_hal_otp.c | 2 +- .../libraries/drivers/hal/am_hal_otp.h | 12 +- .../libraries/drivers/hal/am_hal_pdm.c | 2 +- .../libraries/drivers/hal/am_hal_pdm.h | 11 +- .../libraries/drivers/hal/am_hal_pin.h | 69 +- .../libraries/drivers/hal/am_hal_pwrctrl.c | 2 +- .../libraries/drivers/hal/am_hal_pwrctrl.h | 11 +- .../libraries/drivers/hal/am_hal_queue.c | 2 +- .../libraries/drivers/hal/am_hal_queue.h | 2 +- .../libraries/drivers/hal/am_hal_reset.c | 2 +- .../libraries/drivers/hal/am_hal_reset.h | 2 +- .../libraries/drivers/hal/am_hal_rtc.c | 2 +- .../libraries/drivers/hal/am_hal_rtc.h | 12 +- .../libraries/drivers/hal/am_hal_stimer.c | 27 +- .../libraries/drivers/hal/am_hal_stimer.h | 12 +- .../libraries/drivers/hal/am_hal_sysctrl.c | 6 +- .../libraries/drivers/hal/am_hal_sysctrl.h | 10 +- .../libraries/drivers/hal/am_hal_systick.c | 2 +- .../libraries/drivers/hal/am_hal_systick.h | 2 +- .../libraries/drivers/hal/am_hal_tpiu.c | 4 +- .../libraries/drivers/hal/am_hal_tpiu.h | 12 +- .../libraries/drivers/hal/am_hal_ttp.c | 2 +- .../libraries/drivers/hal/am_hal_ttp.h | 2 +- .../libraries/drivers/hal/am_hal_uart.c | 2 +- .../libraries/drivers/hal/am_hal_uart.h | 12 +- .../libraries/drivers/hal/am_hal_vcomp.c | 2 +- .../libraries/drivers/hal/am_hal_vcomp.h | 12 +- .../libraries/drivers/hal/am_hal_wdt.c | 2 +- .../libraries/drivers/hal/am_hal_wdt.h | 2 +- .../libraries/drivers/regs/am_reg_adc.h | 2 +- .../drivers/regs/am_reg_base_addresses.h | 2 +- .../libraries/drivers/regs/am_reg_cachectrl.h | 2 +- .../libraries/drivers/regs/am_reg_clkgen.h | 13 +- .../libraries/drivers/regs/am_reg_ctimer.h | 4 +- .../libraries/drivers/regs/am_reg_flashctrl.h | 2 +- .../libraries/drivers/regs/am_reg_gpio.h | 24 +- .../libraries/drivers/regs/am_reg_iomstr.h | 2 +- .../libraries/drivers/regs/am_reg_ioslave.h | 2 +- .../libraries/drivers/regs/am_reg_itm.h | 2 +- .../libraries/drivers/regs/am_reg_jedec.h | 2 +- .../libraries/drivers/regs/am_reg_macros.h | 27 +- .../drivers/regs/am_reg_macros_asm.h | 2 +- .../libraries/drivers/regs/am_reg_mcuctrl.h | 3 +- .../libraries/drivers/regs/am_reg_nvic.h | 2 +- .../libraries/drivers/regs/am_reg_pdm.h | 2 +- .../libraries/drivers/regs/am_reg_pwrctrl.h | 2 +- .../libraries/drivers/regs/am_reg_rstgen.h | 2 +- .../libraries/drivers/regs/am_reg_rtc.h | 2 +- .../libraries/drivers/regs/am_reg_sysctrl.h | 45 +- .../libraries/drivers/regs/am_reg_systick.h | 2 +- .../libraries/drivers/regs/am_reg_tpiu.h | 2 +- .../libraries/drivers/regs/am_reg_uart.h | 2 +- .../libraries/drivers/regs/am_reg_vcomp.h | 2 +- .../libraries/drivers/regs/am_reg_wdt.h | 2 +- bsp/apollo2/libraries/startup/SConscript | 1 + bsp/apollo2/project.uvoptx | 1224 ++++++++++++ bsp/apollo2/project.uvprojx | 881 ++++----- bsp/apollo2/rtthread.sct | 14 + 101 files changed, 3751 insertions(+), 1459 deletions(-) create mode 100644 bsp/apollo2/rtthread.sct diff --git a/bsp/apollo2/board/adc.c b/bsp/apollo2/board/adc.c index 13be618ecf..a0044bcc37 100644 --- a/bsp/apollo2/board/adc.c +++ b/bsp/apollo2/board/adc.c @@ -19,46 +19,57 @@ * * Change Logs: * Date Author Notes - * 2017-12-04 Haley the first version + * 2017-09-18 Haley the first version */ +#include #include #include "am_mcu_apollo.h" -#include "board.h" #ifdef RT_USING_ADC -/* sem define */ -rt_sem_t adcsem = RT_NULL; +/* messagequeue define */ +struct rt_messagequeue adcbat_mq; -#define BATTERY_GPIO 29 /* Battery */ -#define BATTERY_ADC_PIN AM_HAL_PIN_29_ADCSE1 -#define BATTERY_ADC_CHANNEL AM_HAL_ADC_SLOT_CHSEL_SE1 /* BATTERY ADC采集通道 */ -#define BATTERY_ADC_CHANNELNUM 1 /* BATTERY ADC采集通道号 */ +#define BATTERY_GPIO 35 /* Battery */ +#define BATTERY_ADC_PIN AM_HAL_PIN_35_ADCSE7 +#define BATTERY_ADC_CHANNEL AM_HAL_ADC_SLOT_CHSEL_SE7 /* BATTERY ADC采集通道 */ +#define BATTERY_ADC_CHANNELNUM 7 /* BATTERY ADC采集通道号 */ #define ADC_CTIMER_NUM 3 /* ADC使用定时器 */ +#define ADC_CTIMER_COUNT (2048/512 - 1) #define ADC_CHANNEL_NUM 1 /* ADC采集通道个数 */ -#define ADC_SAMPLE_NUM 8 /* ADC采样个数, NE_OF_OUTPUT */ +#define ADC_SAMPLE_NUM 8 /* ADC采样个数 */ -rt_uint8_t bat_adc_cnt = (ADC_CHANNEL_NUM + 1)*ADC_SAMPLE_NUM; -rt_int16_t am_adc_buffer_pool[64]; +rt_uint8_t bat_adc_cnt = 0; +static rt_uint8_t am_adcbat_buffer_pool[256]; +static rt_int16_t am_adcbat_buffertemp[32]; -rt_uint8_t am_adc_data_get(rt_int16_t *buff, rt_uint16_t size) +rt_uint8_t am_adc_data_get(rt_uint8_t channel, rt_int16_t *buff, rt_uint16_t size) { - /* wait adc interrupt release sem forever */ - rt_sem_take(adcsem, RT_WAITING_FOREVER); + rt_uint8_t adc_bufftemp[32]; + + if (channel == BATTERY_ADC_CHANNELNUM) + { + /* wait adc message forever */ + rt_mq_recv(&adcbat_mq, adc_bufftemp, 32, RT_WAITING_FOREVER); + } /* copy the data */ - rt_memcpy(buff, am_adc_buffer_pool, size*sizeof(rt_int16_t)); + rt_memcpy(buff, adc_bufftemp, size*sizeof(rt_int16_t)); return 0; } -void am_adc_start(void) +void am_adc_start(rt_uint8_t channel) { - /* adcsem create */ - adcsem = rt_sem_create("adcsem", 0, RT_IPC_FLAG_FIFO); + /* messagequeue init */ + rt_mq_init(&adcbat_mq, "mq_adcbat", + &am_adcbat_buffer_pool[0], + 32 - sizeof(void*), + sizeof(am_adcbat_buffer_pool), + RT_IPC_FLAG_FIFO); /* Start the ctimer */ am_hal_ctimer_start(ADC_CTIMER_NUM, AM_HAL_CTIMER_TIMERA); @@ -67,13 +78,16 @@ void am_adc_start(void) am_hal_adc_trigger(); } -void am_adc_stop(void) +void am_adc_stop(rt_uint8_t channel) { /* Stop the ctimer */ am_hal_ctimer_stop(ADC_CTIMER_NUM, AM_HAL_CTIMER_TIMERA); - /* adcsem delete */ - rt_sem_delete(adcsem); + /* messagequeue delete */ + rt_mq_delete(&adceeg_mq); + + /* messagequeue delete */ + rt_mq_delete(&adcbat_mq); } /** @@ -87,6 +101,9 @@ void am_adc_isr(void) { uint32_t ui32Status, ui32FifoData; + /* enter interrupt */ + rt_interrupt_enter(); + /* Read the interrupt status */ ui32Status = am_hal_adc_int_status_get(true); @@ -101,20 +118,23 @@ void am_adc_isr(void) /* Read the value from the FIFO into the circular buffer */ ui32FifoData = am_hal_adc_fifo_pop(); - if(AM_HAL_ADC_FIFO_SLOT(ui32FifoData) == BATTERY_ADC_CHANNELNUM) - am_adc_buffer_pool[bat_adc_cnt++] = AM_HAL_ADC_FIFO_SAMPLE(ui32FifoData); - - if(bat_adc_cnt > (ADC_CHANNEL_NUM + 1)*ADC_SAMPLE_NUM - 1) + if (AM_HAL_ADC_FIFO_SLOT(ui32FifoData) == BATTERY_ADC_CHANNELNUM) { - /* shift data */ - rt_memmove(am_adc_buffer_pool, am_adc_buffer_pool + ADC_CHANNEL_NUM*ADC_SAMPLE_NUM, ADC_CHANNEL_NUM*ADC_SAMPLE_NUM*sizeof(rt_int16_t)); - bat_adc_cnt = (ADC_CHANNEL_NUM + 1)*ADC_SAMPLE_NUM; + am_adcbat_buffertemp[bat_adc_cnt++] = AM_HAL_ADC_FIFO_SAMPLE(ui32FifoData); + } - /* release adcsem */ - rt_sem_release(adcsem); + if ((bat_adc_cnt > ADC_SAMPLE_NUM + 2 - 1)) + { + bat_adc_cnt = 0; + + /* send the message */ + rt_mq_send(&adcbat_mq, am_adcbat_buffertemp, ADC_SAMPLE_NUM*sizeof(rt_int16_t)); } } while (AM_HAL_ADC_FIFO_COUNT(ui32FifoData) > 0); } + + /* leave interrupt */ + rt_interrupt_leave(); } static void timerA3_for_adc_init(void) @@ -129,7 +149,7 @@ static void timerA3_for_adc_init(void) am_hal_ctimer_int_enable(AM_HAL_CTIMER_INT_TIMERA3); /* Set 512 sample rate */ - am_hal_ctimer_period_set(ADC_CTIMER_NUM, AM_HAL_CTIMER_TIMERA, 3, 1); + am_hal_ctimer_period_set(ADC_CTIMER_NUM, AM_HAL_CTIMER_TIMERA, ADC_CTIMER_COUNT, 1); /* Enable the timer A3 to trigger the ADC directly */ am_hal_ctimer_adc_trigger_enable(); @@ -184,7 +204,10 @@ int rt_hw_adc_init(void) /* Enable the ADC */ am_hal_adc_enable(); - rt_kprintf("adc_init!\n"); + /* Trigger the ADC once */ + //am_hal_adc_trigger(); + + //rt_kprintf("adc_init!\n"); return 0; } diff --git a/bsp/apollo2/board/adc.h b/bsp/apollo2/board/adc.h index 7e1f1eebc4..4e4396bae3 100644 --- a/bsp/apollo2/board/adc.h +++ b/bsp/apollo2/board/adc.h @@ -32,8 +32,8 @@ * */ int rt_hw_adc_init(void); -rt_uint8_t am_adc_data_get(rt_int16_t *buff, rt_uint16_t size); -void am_adc_start(void); -void am_adc_stop(void); +rt_uint8_t am_adc_data_get(rt_uint8_t channel, rt_int16_t *buff, rt_uint16_t size); +void am_adc_start(rt_uint8_t channel); +void am_adc_stop(rt_uint8_t channel); #endif // __ADC_H_ diff --git a/bsp/apollo2/board/board.c b/bsp/apollo2/board/board.c index ed1ff52302..23bc332af4 100644 --- a/bsp/apollo2/board/board.c +++ b/bsp/apollo2/board/board.c @@ -104,15 +104,17 @@ void am_low_power_init(void) /* Turn off the voltage comparator as this is enabled on reset */ am_hal_vcomp_disable(); + #ifndef RT_USING_RTC /* Run the RTC off the LFRC */ am_hal_rtc_osc_select(AM_HAL_RTC_OSC_LFRC); /* Stop the XT and LFRC */ am_hal_clkgen_osc_stop(AM_HAL_CLKGEN_OSC_XT); - am_hal_clkgen_osc_stop(AM_HAL_CLKGEN_OSC_LFRC); + //am_hal_clkgen_osc_stop(AM_HAL_CLKGEN_OSC_LFRC); /* Disable the RTC */ am_hal_rtc_osc_disable(); + #endif } /** @@ -159,7 +161,7 @@ void rt_hw_board_init(void) /* Turn off unused Flash & SRAM */ am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_FLASH512K); - am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_SRAM32K); + //am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_SRAM32K); #endif diff --git a/bsp/apollo2/board/flash.c b/bsp/apollo2/board/flash.c index cc8e4dd499..ae224e85a1 100644 --- a/bsp/apollo2/board/flash.c +++ b/bsp/apollo2/board/flash.c @@ -140,7 +140,7 @@ int rt_hw_rom_init(void) /* register the device */ rt_device_register(&device, "rom", RT_DEVICE_FLAG_RDWR); - rt_kprintf("register device rom!\r\n"); + //rt_kprintf("register device rom!\r\n"); return 0; } diff --git a/bsp/apollo2/board/gpio.c b/bsp/apollo2/board/gpio.c index 3a422dd452..c2eb1be581 100644 --- a/bsp/apollo2/board/gpio.c +++ b/bsp/apollo2/board/gpio.c @@ -24,10 +24,14 @@ #include #include +#include #include "am_mcu_apollo.h" #ifdef RT_USING_PIN +#define APLLO2_PIN_NUMBERS 64 //[34, 64] +struct rt_pin_irq_hdr am_pin_irq_hdr_tab[64]; + void am_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) { if (mode == PIN_MODE_OUTPUT) @@ -43,12 +47,17 @@ void am_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) else if (mode == PIN_MODE_INPUT_PULLUP) { /* input setting: pull up. */ + am_hal_gpio_pin_config(pin, AM_HAL_GPIO_INPUT); + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ am_hal_gpio_pin_config(pin, AM_HAL_GPIO_OPENDRAIN); } else { /* input setting:default. */ - am_hal_gpio_pin_config(pin, AM_HAL_GPIO_INPUT); + am_hal_gpio_pin_config(pin, AM_HAL_GPIO_3STATE); } } @@ -58,40 +67,159 @@ void am_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { am_hal_gpio_out_bit_clear(pin); } - else + else if (value == PIN_HIGH) { am_hal_gpio_out_bit_set(pin); - } + } } int am_pin_read(rt_device_t dev, rt_base_t pin) { int value = PIN_LOW; - if (am_hal_gpio_input_bit_read(pin) == 0) + if (am_hal_gpio_pin_config_read(pin) == AM_HAL_GPIO_OUTPUT) { - value = PIN_LOW; + if (am_hal_gpio_out_bit_read(pin) == 0) + { + value = PIN_LOW; + } + else + { + value = PIN_HIGH; + } } else { - value = PIN_HIGH; + if (am_hal_gpio_input_bit_read(pin) == 0) + { + value = PIN_LOW; + } + else + { + value = PIN_HIGH; + } } return value; } -const static struct rt_pin_ops _am_pin_ops = +rt_err_t am_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + irqindex = pin; + + level = rt_hw_interrupt_disable(); + if(am_pin_irq_hdr_tab[irqindex].pin == pin && + am_pin_irq_hdr_tab[irqindex].hdr == hdr && + am_pin_irq_hdr_tab[irqindex].mode == mode && + am_pin_irq_hdr_tab[irqindex].args == args + ) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if(am_pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return -RT_EBUSY; + } + am_pin_irq_hdr_tab[irqindex].pin = pin; + am_pin_irq_hdr_tab[irqindex].hdr = hdr; + am_pin_irq_hdr_tab[irqindex].mode = mode; + am_pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +rt_err_t am_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + irqindex = pin; + + level = rt_hw_interrupt_disable(); + if(am_pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + am_pin_irq_hdr_tab[irqindex].pin = -1; + am_pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + am_pin_irq_hdr_tab[irqindex].mode = 0; + am_pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +rt_err_t am_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + irqindex = pin; + + if (enabled == PIN_IRQ_ENABLE) + { + level = rt_hw_interrupt_disable(); + + /* Configure the GPIO/button interrupt polarity */ + if (am_pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING) + { + am_hal_gpio_int_polarity_bit_set(am_pin_irq_hdr_tab[irqindex].pin, AM_HAL_GPIO_RISING); + } + else if (am_pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_FALLING) + { + am_hal_gpio_int_polarity_bit_set(am_pin_irq_hdr_tab[irqindex].pin, AM_HAL_GPIO_FALLING); + } + + /* Clear the GPIO Interrupt (write to clear) */ + am_hal_gpio_int_clear(AM_HAL_GPIO_BIT(am_pin_irq_hdr_tab[irqindex].pin)); + + /* Enable the GPIO/button interrupt */ + am_hal_gpio_int_enable(AM_HAL_GPIO_BIT(am_pin_irq_hdr_tab[irqindex].pin)); + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + if (am_hal_gpio_int_enable_get() != AM_HAL_GPIO_BIT(am_pin_irq_hdr_tab[irqindex].pin)) + { + return RT_ENOSYS; + } + + /* Disable the GPIO/button interrupt */ + am_hal_gpio_int_disable(AM_HAL_GPIO_BIT(am_pin_irq_hdr_tab[irqindex].pin)); + } + else + { + return RT_ENOSYS; + } + + return RT_EOK; +} + +const static struct rt_pin_ops am_pin_ops = { am_pin_mode, am_pin_write, am_pin_read, + am_pin_attach_irq, + am_pin_dettach_irq, + am_pin_irq_enable, }; int rt_hw_pin_init(void) { - rt_device_pin_register("pin", &_am_pin_ops, RT_NULL); + rt_device_pin_register("pin", &am_pin_ops, RT_NULL); - rt_kprintf("pin_init!\n"); + //rt_device_pin_irq_register("pin", &am_pin_ops, RT_NULL); + //rt_kprintf("pin_init!\n"); return 0; } diff --git a/bsp/apollo2/board/i2c.c b/bsp/apollo2/board/i2c.c index cb91cdd2e5..6d1bcdc0c0 100644 --- a/bsp/apollo2/board/i2c.c +++ b/bsp/apollo2/board/i2c.c @@ -25,7 +25,6 @@ #include #include #include "am_mcu_apollo.h" -#include "board.h" /* I2C0 */ #define AM_I2C0_IOM_INST 0 @@ -43,6 +42,14 @@ #define I2C2_GPIO_SDA 25 #define I2C2_GPIO_CFG_SDA AM_HAL_PIN_25_M2SDA +/* I2C3 */ +#define AM_I2C3_IOM_INST 3 + +#define I2C3_GPIO_SCL 42 +#define I2C3_GPIO_CFG_SCK AM_HAL_PIN_42_M3SCL +#define I2C3_GPIO_SDA 43 +#define I2C3_GPIO_CFG_SDA AM_HAL_PIN_43_M3SDA + /* I2C4 */ #define AM_I2C4_IOM_INST 4 @@ -76,7 +83,7 @@ rt_size_t rt_i2c_master_xfer(struct rt_i2c_bus_device *bus, struct am_i2c_bus * am_i2c_bus = (struct am_i2c_bus *)bus; struct rt_i2c_msg *msg; int i; - rt_int32_t ret = RT_EOK; + rt_uint32_t msg_len = 0; for (i = 0; i < num; i++) { @@ -84,16 +91,16 @@ rt_size_t rt_i2c_master_xfer(struct rt_i2c_bus_device *bus, if (msg->flags == RT_I2C_RD) { am_hal_iom_i2c_read(am_i2c_bus->u32Module, msg->addr, (uint32_t *)msg->buf, msg->len, AM_HAL_IOM_RAW); + msg_len += msg->len; } else if(msg->flags == RT_I2C_WR) { am_hal_iom_i2c_write(am_i2c_bus->u32Module, msg->addr, (uint32_t *)msg->buf, msg->len, AM_HAL_IOM_RAW); + msg_len += (msg->len - 1); } - - ret++; } - return ret; + return msg_len; } rt_err_t rt_i2c_bus_control(struct rt_i2c_bus_device *bus, @@ -136,7 +143,7 @@ static struct am_i2c_bus am_i2c_bus_0 = #ifdef RT_USING_I2C1 static struct am_i2c_bus am_i2c_bus_1 = { - {0}, + {1}, AM_I2C1_IOM_INST }; #endif @@ -144,7 +151,7 @@ static struct am_i2c_bus am_i2c_bus_1 = #ifdef RT_USING_I2C2 static struct am_i2c_bus am_i2c_bus_2 = { - {1}, + {2}, AM_I2C2_IOM_INST }; #endif @@ -152,7 +159,7 @@ static struct am_i2c_bus am_i2c_bus_2 = #ifdef RT_USING_I2C3 static struct am_i2c_bus am_i2c_bus_3 = { - {2}, + {3}, AM_I2C3_IOM_INST }; #endif @@ -160,7 +167,7 @@ static struct am_i2c_bus am_i2c_bus_3 = #ifdef RT_USING_I2C4 static struct am_i2c_bus am_i2c_bus_4 = { - {3}, + {4}, AM_I2C4_IOM_INST }; #endif @@ -203,6 +210,23 @@ int rt_i2c_init(void) rt_i2c_bus_device_register(&am_i2c->parent, "i2c2"); #endif +#ifdef RT_USING_I2C3 + /* init i2c gpio */ + am_hal_gpio_pin_config(I2C3_GPIO_SCL, I2C3_GPIO_CFG_SCK | AM_HAL_GPIO_PULL6K); + am_hal_gpio_pin_config(I2C3_GPIO_SDA, I2C3_GPIO_CFG_SDA | AM_HAL_GPIO_PULL6K); + + /* Initialize IOM 3 in I2C mode at 400KHz */ + am_hal_iom_pwrctrl_enable(AM_I2C3_IOM_INST); + g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_400KHZ; + am_hal_iom_config(AM_I2C3_IOM_INST, &g_sIOMConfig); + am_hal_iom_enable(AM_I2C3_IOM_INST); + + /* init i2c bus device */ + am_i2c = &am_i2c_bus_3; + am_i2c->parent.ops = &am_i2c_ops; + rt_i2c_bus_device_register(&am_i2c->parent, "i2c3"); +#endif + #ifdef RT_USING_I2C4 /* init i2c gpio */ am_hal_gpio_pin_config(I2C4_GPIO_SCL, I2C4_GPIO_CFG_SCK | AM_HAL_GPIO_PULL6K); @@ -220,7 +244,7 @@ int rt_i2c_init(void) rt_i2c_bus_device_register(&am_i2c->parent, "i2c4"); #endif - rt_kprintf("i2c_init!\n"); + //rt_kprintf("i2c_init!\n"); return 0; } diff --git a/bsp/apollo2/board/pdm.c b/bsp/apollo2/board/pdm.c index e97d2fa530..3eb46f7411 100644 --- a/bsp/apollo2/board/pdm.c +++ b/bsp/apollo2/board/pdm.c @@ -25,15 +25,15 @@ #include #include #include "am_mcu_apollo.h" -#include "board.h" #ifdef RT_USING_PDM -/* sem define */ -rt_sem_t pdmsem = RT_NULL; +/* messagequeue define */ +struct rt_messagequeue pdm_mq; -#define NWA_FRAME_MS 10 -#define NWA_FRAME_SAMPLES (16*NWA_FRAME_MS) /* 16k, 16bit, mono audio data */ +static rt_uint8_t am_pdm_buffer_pool[1024]; + +#define NWA_FRAME_SAMPLES 160 /* 8k, 16bit, mono audio data */ #define PDM_FIFO_THRESHOLD NWA_FRAME_SAMPLES #define PDM_GPIO_CLK 22 @@ -41,23 +41,16 @@ rt_sem_t pdmsem = RT_NULL; #define PDM_GPIO_DATA 23 #define PDM_GPIO_CFG_DATA AM_HAL_PIN_23_PDM_DATA -#define PING_PONG_BUF_SIZE 8000*NWA_FRAME_MS -static rt_uint16_t am_pdm_buffer_pool[PING_PONG_BUF_SIZE]; -static rt_uint8_t pdm_flag = 0; -static rt_uint16_t pdm_cnt = 0; - - static am_hal_pdm_config_t g_sPDMConfig = { - AM_HAL_PDM_PCFG_LRSWAP_DISABLE | AM_HAL_PDM_PCFG_RIGHT_PGA_P105DB | AM_HAL_PDM_PCFG_LEFT_PGA_P105DB - | AM_HAL_PDM_PCFG_MCLKDIV_DIV1 | AM_HAL_PDM_PCFG_SINC_RATE(48) | AM_HAL_PDM_PCFG_ADCHPD_ENABLE - | AM_HAL_PDM_PCFG_HPCUTOFF(0xB) | AM_HAL_PDM_PCFG_CYCLES(0x1) | AM_HAL_PDM_PCFG_SOFTMUTE_DISABLE - | AM_HAL_PDM_PCFG_PDMCORE_ENABLE, /* Set the PDM configuration */ - AM_REG_PDM_VCFG_IOCLKEN_EN | AM_HAL_PDM_VCFG_RSTB_NORMAL | AM_REG_PDM_VCFG_PDMCLKSEL_750KHz - | AM_HAL_PDM_VCFG_PDMCLK_ENABLE | AM_HAL_PDM_VCFG_I2SMODE_DISABLE | AM_HAL_PDM_VCFG_BCLKINV_DISABLE - | AM_HAL_PDM_VCFG_DMICDEL_DISABLE | AM_HAL_PDM_VCFG_SELAP_INTERNAL | AM_HAL_PDM_VCFG_PACK_DISABLE - | AM_HAL_PDM_VCFG_CHANNEL_RIGHT, /* Set the Voice Configuration */ - PDM_FIFO_THRESHOLD, /* Select the FIFO PCM sample threshold */ + AM_HAL_PDM_PCFG_LRSWAP_DISABLE | AM_HAL_PDM_PCFG_RIGHT_PGA_0DB | AM_HAL_PDM_PCFG_LEFT_PGA_0DB + | AM_HAL_PDM_PCFG_MCLKDIV_DIV1 | AM_HAL_PDM_PCFG_SINC_RATE(48) | AM_HAL_PDM_PCFG_ADCHPD_ENABLE + | AM_HAL_PDM_PCFG_HPCUTOFF(0x1) | AM_HAL_PDM_PCFG_CYCLES(0x1) | AM_HAL_PDM_PCFG_SOFTMUTE_DISABLE + | AM_HAL_PDM_PCFG_PDMCORE_ENABLE, /* Set the PDM configuration */ + AM_HAL_PDM_IOCLK_750KHZ | AM_HAL_PDM_VCFG_RSTB_NORMAL | AM_HAL_PDM_VCFG_PDMCLK_ENABLE + | AM_HAL_PDM_VCFG_I2SMODE_DISABLE | AM_HAL_PDM_VCFG_BCLKINV_DISABLE | AM_HAL_PDM_VCFG_DMICDEL_DISABLE + | AM_HAL_PDM_VCFG_SELAP_INTERNAL | AM_HAL_PDM_VCFG_PACK_DISABLE | AM_HAL_PDM_VCFG_CHANNEL_LEFT, /* Set the Voice Configuration */ + PDM_FIFO_THRESHOLD, /* Select the FIFO PCM sample threshold 0~256 */ }; /** @@ -71,28 +64,13 @@ static am_hal_pdm_config_t g_sPDMConfig = */ rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size) { - uint8_t temp; - int i; + rt_uint8_t pdm_rbufftemp[340]; - /* wait adc interrupt release sem forever */ - rt_sem_take(pdmsem, RT_WAITING_FOREVER); + /* wait pdm message forever */ + rt_mq_recv(&pdm_mq, pdm_rbufftemp, 340, RT_WAITING_FOREVER); - for(i = 0; i < PING_PONG_BUF_SIZE; i++) - { - temp = (uint8_t)(am_pdm_buffer_pool[i] & 0xFF); - /* lower byte */ - while ( AM_BFRn(UART, 0, FR, TXFF) ); - AM_REGn(UART, 0, DR) = temp; - - temp = (uint8_t)((am_pdm_buffer_pool[i] & 0xFF00)>>8); - /* higher byte */ - while ( AM_BFRn(UART, 0, FR, TXFF) ); - AM_REGn(UART, 0, DR) = temp; - } /* copy the data */ - //rt_memcpy(buff, am_pdm_buffer_pool, size*sizeof(rt_uint16_t)); - - pdm_flag = 0; + rt_memcpy(buff, (char *)pdm_rbufftemp, size); return 0; } @@ -108,12 +86,9 @@ rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size) */ void am_pdm_start(void) { - /* adcsem create */ - pdmsem = rt_sem_create("pdmsem", 0, RT_IPC_FLAG_FIFO); - /* Enable PDM */ - am_hal_pdm_enable(); am_hal_interrupt_enable(AM_HAL_INTERRUPT_PDM); + am_hal_pdm_enable(); } /** @@ -128,11 +103,8 @@ void am_pdm_start(void) void am_pdm_stop(void) { /* Disable PDM */ - am_hal_pdm_disable(); am_hal_interrupt_disable(AM_HAL_INTERRUPT_PDM); - - /* adcsem delete */ - rt_sem_delete(pdmsem); + am_hal_pdm_disable(); } /** @@ -153,7 +125,7 @@ uint8_t am_pdm_left_gain_get(void) /** * @brief Set the pdm left gain. * - * @param None. + * @param gain_val. * * This function Set the pdm left gain. * @@ -183,7 +155,7 @@ uint8_t am_pdm_right_gain_get(void) /** * @brief Set the pdm right gain. * - * @param None. + * @param gain_val. * * This function Set the pdm right gain. * @@ -204,33 +176,19 @@ void am_pdm_right_gain_set(uint8_t gain_val) */ void am_pdm_isr (void) { - uint32_t ui32FifoData; int i; + rt_int16_t pdm_sbufftemp[160]; /* Clear the PDM interrupt */ am_hal_pdm_int_clear(AM_HAL_PDM_INT_UNDFL | AM_HAL_PDM_INT_OVF | AM_HAL_PDM_INT_FIFO); for (i = 0; i < PDM_FIFO_THRESHOLD; i++) /* adjust as needed */ { - ui32FifoData = am_hal_pdm_fifo_data_read(); - - if(pdm_flag == 0) - { - am_pdm_buffer_pool[pdm_cnt * PDM_FIFO_THRESHOLD + i] = (uint16_t)ui32FifoData; - } + pdm_sbufftemp[i] = (rt_int16_t)am_hal_pdm_fifo_data_read(); } - if(pdm_flag == 0) - pdm_cnt ++; - - if(pdm_cnt == PING_PONG_BUF_SIZE/PDM_FIFO_THRESHOLD) /* 500 means 10 second logging under 8k sampling rate */ - { - pdm_cnt = 0; - pdm_flag = 1; - - /* release pdmsem */ - rt_sem_release(pdmsem); - } + /* send the message */ + rt_mq_send(&pdm_mq, pdm_sbufftemp, PDM_FIFO_THRESHOLD*sizeof(rt_int16_t)); } /** @@ -258,7 +216,14 @@ int rt_hw_pdm_init(void) /* Clear PDM interrupts */ am_hal_pdm_int_clear(AM_HAL_PDM_INT_UNDFL | AM_HAL_PDM_INT_OVF | AM_HAL_PDM_INT_FIFO); - rt_kprintf("pdm_init!\n"); + /* messagequeue init */ + rt_mq_init(&pdm_mq, "mq_pdm", + &am_pdm_buffer_pool[0], + 340 - sizeof(void*), + sizeof(am_pdm_buffer_pool), + RT_IPC_FLAG_FIFO); + + //rt_kprintf("pdm_init!\n"); return 0; } diff --git a/bsp/apollo2/board/pdm.h b/bsp/apollo2/board/pdm.h index b0fae857c4..43ed075da8 100644 --- a/bsp/apollo2/board/pdm.h +++ b/bsp/apollo2/board/pdm.h @@ -31,7 +31,7 @@ * @brief External function definitions * */ -int rt_hw_pdm_init(void); +int rt_pdm_init(void); rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size); void am_pdm_start(void); void am_pdm_stop(void); diff --git a/bsp/apollo2/board/pwm.h b/bsp/apollo2/board/pwm.h index 2c22e38891..53a6571264 100644 --- a/bsp/apollo2/board/pwm.h +++ b/bsp/apollo2/board/pwm.h @@ -32,5 +32,7 @@ * */ int rt_hw_pwm_init(void); +void am_pwm_start(int led); +void am_pwm_stop(int led); #endif // __PWM_H_ diff --git a/bsp/apollo2/board/rtc.c b/bsp/apollo2/board/rtc.c index 4ac1869472..1bc4779257 100644 --- a/bsp/apollo2/board/rtc.c +++ b/bsp/apollo2/board/rtc.c @@ -118,7 +118,6 @@ int rt_hw_rtc_init(void) #if RTC_CLK_SRC == XT /* Enable the XT for the RTC */ - //am_hal_clkgen_osc_start(AM_HAL_CLKGEN_OSC_LFRC); am_hal_clkgen_osc_start(AM_HAL_CLKGEN_OSC_XT); /* Select XT for RTC clock source */ diff --git a/bsp/apollo2/board/smbus.c b/bsp/apollo2/board/smbus.c index d2d801994e..ae41f9fac6 100644 --- a/bsp/apollo2/board/smbus.c +++ b/bsp/apollo2/board/smbus.c @@ -25,23 +25,22 @@ #include #include #include "am_mcu_apollo.h" -#include "board.h" #ifdef RT_USING_SMBUS #define SMBUS_GPIO_SDA 5 #define SMBUS_GPIO_SCL 6 -#define mSDA_LOW() am_hal_gpio_out_bit_clear(SMBUS_GPIO_SCL) /* Clear SDA line */ -#define mSDA_HIGH() am_hal_gpio_out_bit_set(SMBUS_GPIO_SCL) /* Set SDA line */ -#define mSCL_LOW() am_hal_gpio_out_bit_clear(SMBUS_GPIO_SDA) /* Clear SCL line */ -#define mSCL_HIGH() am_hal_gpio_out_bit_set(SMBUS_GPIO_SDA) /* Set SCL line */ +#define mSDA_LOW() am_hal_gpio_out_bit_clear(SMBUS_GPIO_SDA) /* Clear SDA line */ +#define mSDA_HIGH() am_hal_gpio_out_bit_set(SMBUS_GPIO_SDA) /* Set SDA line */ +#define mSCL_LOW() am_hal_gpio_out_bit_clear(SMBUS_GPIO_SCL) /* Clear SCL line */ +#define mSCL_HIGH() am_hal_gpio_out_bit_set(SMBUS_GPIO_SCL) /* Set SCL line */ -#define mSDA_READ() am_hal_gpio_input_bit_read(SMBUS_GPIO_SCL) /* Read SCL line */ +#define mSDA_READ() am_hal_gpio_input_bit_read(SMBUS_GPIO_SDA) /* Read SDA line */ -#define mSDA_IN() am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_INPUT | AM_HAL_GPIO_PULL6K) /* Set SDA as Input */ -#define mSDA_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_OUTPUT) /* Set SDA as Output */ -#define mSCL_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_OUTPUT) /* Set SCL as Output */ +#define mSDA_IN() am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_INPUT | AM_HAL_GPIO_PULL6K) /* Set SDA as Input */ +#define mSDA_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_OUTPUT) /* Set SDA as Output */ +#define mSCL_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_OUTPUT) /* Set SCL as Output */ #define ACK 0 #define NACK 1 diff --git a/bsp/apollo2/board/spi.c b/bsp/apollo2/board/spi.c index 5267329684..783f359af0 100644 --- a/bsp/apollo2/board/spi.c +++ b/bsp/apollo2/board/spi.c @@ -25,10 +25,9 @@ #include #include #include "am_mcu_apollo.h" -#include "board.h" #include "spi.h" -/* SPI1 */ +/* SPI0 */ #define AM_SPI0_IOM_INST 0 #define SPI0_GPIO_SCK 5 @@ -38,17 +37,17 @@ #define SPI0_GPIO_MOSI 7 #define SPI0_GPIO_CFG_MOSI AM_HAL_PIN_7_M0MOSI -/* SPI2 */ +/* SPI1 */ #define AM_SPI1_IOM_INST 1 static am_hal_iom_config_t g_sIOMConfig = { AM_HAL_IOM_SPIMODE, // ui32InterfaceMode - AM_HAL_IOM_8MHZ, // ui32ClockFrequency + AM_HAL_IOM_400KHZ, // ui32ClockFrequency 0, // bSPHA 0, // bSPOL - 4, // ui8WriteThreshold - 60, // ui8ReadThreshold + 80, // ui8WriteThreshold + 80, // ui8ReadThreshold }; /* AM spi driver */ @@ -64,7 +63,19 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat struct am_spi_bus * am_spi_bus = (struct am_spi_bus *)device->bus; rt_uint32_t max_hz = configuration->max_hz; - if(max_hz >= 8000000) + if(max_hz >= 24000000) + { + g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_24MHZ; + } + else if(max_hz >= 16000000) + { + g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_16MHZ; + } + else if(max_hz >= 12000000) + { + g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_12MHZ; + } + else if(max_hz >= 8000000) { g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_8MHZ; } @@ -147,7 +158,6 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat /* init SPI */ am_hal_iom_disable(am_spi_bus->u32Module); - am_hal_iom_pwrctrl_enable(am_spi_bus->u32Module); am_hal_iom_config(am_spi_bus->u32Module, &g_sIOMConfig); am_hal_iom_enable(am_spi_bus->u32Module); @@ -167,14 +177,12 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes /* take CS */ if (message->cs_take) { - ; + am_hal_gpio_out_bit_clear(am_spi_cs->chip_select); } // 读数据 if (recv_ptr != RT_NULL) { - u32TransferSize = u32BytesRemaining; - while (u32BytesRemaining) { /* Set the transfer size to either 64, or the number of remaining @@ -182,22 +190,21 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes if (u32BytesRemaining > 64) { u32TransferSize = 64; + am_hal_gpio_pin_config(SPI0_GPIO_MOSI, AM_HAL_GPIO_OUTPUT | AM_HAL_GPIO_PULL6K); + am_hal_gpio_out_bit_set(SPI0_GPIO_MOSI); am_hal_iom_spi_read(am_spi_bus->u32Module, am_spi_cs->chip_select, - (uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW); + (uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_RAW); + am_hal_gpio_pin_config(SPI0_GPIO_MOSI, SPI0_GPIO_CFG_MOSI | AM_HAL_GPIO_PULL6K); } else { u32TransferSize = u32BytesRemaining; - /* release CS */ - if(message->cs_release) { + am_hal_gpio_pin_config(SPI0_GPIO_MOSI, AM_HAL_GPIO_OUTPUT | AM_HAL_GPIO_PULL6K); + am_hal_gpio_out_bit_set(SPI0_GPIO_MOSI); am_hal_iom_spi_read(am_spi_bus->u32Module, am_spi_cs->chip_select, (uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_RAW); - } - else - { - am_hal_iom_spi_read(am_spi_bus->u32Module, am_spi_cs->chip_select, - (uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW); + am_hal_gpio_pin_config(SPI0_GPIO_MOSI, SPI0_GPIO_CFG_MOSI | AM_HAL_GPIO_PULL6K); } } @@ -207,33 +214,26 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes } // 写数据 - else if (send_ptr != RT_NULL) + else { while (u32BytesRemaining) { /* Set the transfer size to either 32, or the number of remaining bytes, whichever is smaller */ - if (u32BytesRemaining > 32) + if (u32BytesRemaining > 64) { - u32TransferSize = 32; + u32TransferSize = 64; am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select, - (uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW); + (uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_RAW); } else { u32TransferSize = u32BytesRemaining; - /* release CS */ - if (message->cs_release) { am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select, (uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_RAW); } - else - { - am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select, - (uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW); - } } u32BytesRemaining -= u32TransferSize; @@ -241,6 +241,12 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes } } + /* release CS */ + if(message->cs_release) + { + am_hal_gpio_out_bit_set(am_spi_cs->chip_select); + } + return message->length; } @@ -250,31 +256,31 @@ static const struct rt_spi_ops am_spi_ops = xfer }; -#ifdef RT_USING_SPI1 -static struct am_spi_bus am_spi_bus_1 = +#ifdef RT_USING_SPI0 +static struct am_spi_bus am_spi_bus_0 = { {0}, AM_SPI0_IOM_INST }; -#endif /* #ifdef RT_USING_SPI1 */ +#endif /* #ifdef RT_USING_SPI0 */ -#ifdef RT_USING_SPI2 -static struct ambiq_spi_bus ambiq_spi_bus_2 = +#ifdef RT_USING_SPI1 +static struct am_spi_bus am_spi_bus_1 = { - {1}, + {0}, AM_SPI1_IOM_INST }; -#endif /* #ifdef RT_USING_SPI2 */ +#endif /* #ifdef RT_USING_SPI1 */ int yr_hw_spi_init(void) { struct am_spi_bus* am_spi; -#ifdef RT_USING_SPI1 +#ifdef RT_USING_SPI0 /* init spi gpio */ am_hal_gpio_pin_config(SPI0_GPIO_SCK, SPI0_GPIO_CFG_SCK); - am_hal_gpio_pin_config(SPI0_GPIO_MISO, SPI0_GPIO_CFG_MISO); - am_hal_gpio_pin_config(SPI0_GPIO_MOSI, SPI0_GPIO_CFG_MOSI); + am_hal_gpio_pin_config(SPI0_GPIO_MISO, SPI0_GPIO_CFG_MISO | AM_HAL_GPIO_PULL6K); + am_hal_gpio_pin_config(SPI0_GPIO_MOSI, SPI0_GPIO_CFG_MOSI | AM_HAL_GPIO_PULL6K); /* Initialize IOM 0 in SPI mode at 100KHz */ am_hal_iom_pwrctrl_enable(AM_SPI0_IOM_INST); @@ -282,11 +288,11 @@ int yr_hw_spi_init(void) am_hal_iom_enable(AM_SPI0_IOM_INST); //init spi bus device - am_spi = &am_spi_bus_1; - rt_spi_bus_register(&am_spi->parent, "spi1", &am_spi_ops); + am_spi = &am_spi_bus_0; + rt_spi_bus_register(&am_spi->parent, "spi0", &am_spi_ops); #endif - rt_kprintf("spi init!\n"); + //rt_kprintf("spi init!\n"); return 0; } diff --git a/bsp/apollo2/board/uart.c b/bsp/apollo2/board/uart.c index 94a76299ba..fc3884bf2d 100644 --- a/bsp/apollo2/board/uart.c +++ b/bsp/apollo2/board/uart.c @@ -25,7 +25,6 @@ #include #include #include "am_mcu_apollo.h" -#include "board.h" /* USART0 */ #define AM_UART0_INST 0 @@ -165,8 +164,14 @@ static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_conf else if (cfg->stop_bits == STOP_BITS_2) uart_cfg.bTwoStopBits = true; - uart_cfg.ui32Parity = cfg->parity; - uart_cfg.ui32FlowCtrl = AM_HAL_UART_PARITY_NONE; + if (cfg->parity == PARITY_NONE) + uart_cfg.ui32Parity = AM_HAL_UART_PARITY_NONE; + else if (cfg->parity == PARITY_ODD) + uart_cfg.ui32Parity = AM_HAL_UART_PARITY_ODD; + else if (cfg->parity == PARITY_EVEN) + uart_cfg.ui32Parity = AM_HAL_UART_PARITY_EVEN; + + uart_cfg.ui32FlowCtrl = AM_HAL_UART_FLOW_CTRL_NONE; /* UART Config */ am_hal_uart_config(uart->uart_device, &uart_cfg); @@ -181,7 +186,7 @@ static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_conf am_hal_uart_enable(uart->uart_device); /* Enable interrupts */ - am_hal_uart_int_enable(uart->uart_device, AM_HAL_UART_INT_RX_TMOUT | AM_HAL_UART_INT_RX | AM_HAL_UART_INT_TX); + am_hal_uart_int_enable(uart->uart_device, AM_HAL_UART_INT_RX_TMOUT | AM_HAL_UART_INT_RX); /* Enable the uart interrupt in the NVIC */ am_hal_interrupt_enable(uart->uart_interrupt); @@ -231,7 +236,7 @@ static int am_putc(struct rt_serial_device *serial, char c) //if (txsize > 0) { am_hal_uart_char_transmit_buffered(uart->uart_device, c); - } + } /* Wait until busy bit clears to make sure UART fully transmitted last byte */ while ( am_hal_uart_flags_get(uart->uart_device) & AM_HAL_UART_FR_BUSY ); @@ -400,9 +405,6 @@ int rt_hw_uart_init(void) #if defined(RT_USING_UART0) uart = &uart0; config.baud_rate = BAUD_RATE_115200; - config.data_bits = DATA_BITS_8; - config.stop_bits = STOP_BITS_1; - config.parity = PARITY_NONE; RCC_Configuration(uart); @@ -418,9 +420,6 @@ int rt_hw_uart_init(void) #if defined(RT_USING_UART1) uart = &uart1; config.baud_rate = BAUD_RATE_115200; - config.data_bits = DATA_BITS_8; - config.stop_bits = STOP_BITS_1; - config.parity = PARITY_NONE; RCC_Configuration(uart); diff --git a/bsp/apollo2/libraries/drivers/SConscript b/bsp/apollo2/libraries/drivers/SConscript index 6e460fbc5f..da2298889c 100644 --- a/bsp/apollo2/libraries/drivers/SConscript +++ b/bsp/apollo2/libraries/drivers/SConscript @@ -10,6 +10,7 @@ hal/am_hal_clkgen.c hal/am_hal_debug.c hal/am_hal_cachectrl.c hal/am_hal_pwrctrl.c +hal/am_hal_mcuctrl.c hal/am_hal_sysctrl.c hal/am_hal_reset.c hal/am_hal_stimer.c diff --git a/bsp/apollo2/libraries/drivers/am_mcu_apollo.h b/bsp/apollo2/libraries/drivers/am_mcu_apollo.h index bf46aa61bb..ecd55de013 100644 --- a/bsp/apollo2/libraries/drivers/am_mcu_apollo.h +++ b/bsp/apollo2/libraries/drivers/am_mcu_apollo.h @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_MCU_APOLLO_H diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_adc.c b/bsp/apollo2/libraries/drivers/hal/am_hal_adc.c index 957408d0e5..87a6c60483 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_adc.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_adc.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_adc.h b/bsp/apollo2/libraries/drivers/hal/am_hal_adc.h index 86b48b162c..554e997441 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_adc.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_adc.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_ADC_H #define AM_HAL_ADC_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // //! @name Clock Selection @@ -309,6 +304,11 @@ am_hal_adc_config_t; (((value) & AM_REG_ADC_FIFO_COUNT_M) >> AM_REG_ADC_FIFO_COUNT_S) //! @} +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.c b/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.c index 26c41a22e3..49b879398e 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.h b/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.h index b8ce914b94..beb7104516 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.h @@ -38,17 +38,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_CACHECTRL_H #define AM_HAL_CACHECTRL_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // // Cache configuration structure @@ -186,6 +181,11 @@ extern const am_hal_cachectrl_config_t am_hal_cachectrl_defaults; AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE | \ AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512) +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.c b/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.c index d60d7e47b5..83ac822609 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -287,16 +287,20 @@ am_hal_clkgen_int_clear(uint32_t ui32Interrupt) //! AM_HAL_CLKGEN_OSC_LFRC //! AM_HAL_CLKGEN_OSC_XT //! -//! @return 0 None. +//! @return None. // //***************************************************************************** void am_hal_clkgen_osc_start(uint32_t ui32OscFlags) { - // - // Start the oscillator(s). - // - AM_REG(CLKGEN, OCTRL) &= ~ui32OscFlags; + if ( ui32OscFlags & (AM_HAL_CLKGEN_OSC_LFRC | AM_HAL_CLKGEN_OSC_XT) ) + { + // + // Start the oscillator(s). + // Note that these bits are cleared in order to enable the oscillator. + // + AM_REG(CLKGEN, OCTRL) &= ~ui32OscFlags; + } } //***************************************************************************** @@ -318,10 +322,14 @@ am_hal_clkgen_osc_start(uint32_t ui32OscFlags) void am_hal_clkgen_osc_stop(uint32_t ui32OscFlags) { - // - // Stop the oscillator(s). - // - AM_REG(CLKGEN, OCTRL) |= ui32OscFlags; + if ( ui32OscFlags & (AM_HAL_CLKGEN_OSC_LFRC | AM_HAL_CLKGEN_OSC_XT) ) + { + // + // Stop the oscillator(s). + // Note that these bits are set in order to stop the oscillator. + // + AM_REG(CLKGEN, OCTRL) |= ui32OscFlags; + } } //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.h b/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.h index fc50cb9b43..3ad31bbf7f 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.h @@ -38,17 +38,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_CLKGEN_H #define AM_HAL_CLKGEN_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // //! @name System Clock max frequency @@ -178,6 +173,11 @@ extern "C" (AM_REG_CLKGEN_UARTEN_UART0EN_##entype << \ AM_HAL_CLKGEN_UARTEN_UARTENn_S(module)) +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.c b/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.c index 13fc3c07cc..f3d06b6a76 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -68,11 +68,12 @@ // still pass in the event of a timer rollover. // //***************************************************************************** +//! Timer read workaround: Do count values differ by one tick or less. #define adjacent(A, B) (((A) == (B)) || (((A) + 1) == (B)) || ((B) == 0)) //***************************************************************************** // -// Array of function pointers for handling CTimer interrupts. +//! Array of function pointers for handling CTimer interrupts. // //***************************************************************************** am_hal_ctimer_handler_t am_hal_ctimer_ppfnHandlers[16]; @@ -162,10 +163,10 @@ back2back_reads( uint32_t u32TimerAddr, uint32_t u32Data[]) //***************************************************************************** // -// @brief Check to see if the given CTimer is using the HFRC -// -// Note - Calls to this function should be from inside a critical section. -// +//! @brief Check to see if the given CTimer is using the HFRC +//! +//! @note Calls to this function should be from inside a critical section. +//! //! @return None. // //***************************************************************************** @@ -501,7 +502,7 @@ am_hal_ctimer_config(uint32_t ui32TimerNumber, //! @param ui32TimerSegment specifies which segment of the timer should be //! enabled. //! -//! @param ui32Configval specifies the configuration options for the selected +//! @param ui32ConfigVal specifies the configuration options for the selected //! timer. //! //! This function should be used to perform the initial set-up of the @@ -823,7 +824,7 @@ uint32_t am_hal_ctimer_read(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) { volatile uint32_t ui32Value = 0; - uint32_t ui32Values[3] = {0}; + uint32_t ui32Values[4] = {0, }; uint32_t ui32TimerAddrTbl[4] = { REG_CTIMER_BASEADDR + AM_REG_CTIMER_TMR0_O, @@ -1023,7 +1024,7 @@ am_hal_ctimer_pin_disable(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) //! //! @param ui32TimerSegment specifies which segment of the timer to use. //! -//! @param bInvertOutpt determines whether the output should be inverted. If +//! @param bInvertOutput determines whether the output should be inverted. If //! true, the timer output pin for the selected timer segment will be //! inverted. //! @@ -1131,7 +1132,7 @@ am_hal_ctimer_compare_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment, pui32CmprRegA = (uint32_t *)(AM_REG_CTIMERn(0) + AM_REG_CTIMER_CMPRA0_O + (ui32TimerNumber * TIMER_OFFSET)); - pui32CmprRegB = pui32CmprRegA + CTIMER_CMPR_OFFSET; + pui32CmprRegB = pui32CmprRegA + CTIMER_CMPR_OFFSET / 4; // // Write the compare register with the selected value. diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.h b/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.h index fa1ebe16c4..dbd4d8e198 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_CTIMER_H #define AM_HAL_CTIMER_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // //! Number of timers @@ -114,7 +109,7 @@ extern "C" //! //! These options are to be used with the \e am_hal_ctimer_config_t structure //! used by \e am_hal_ctimer_config -//! @{ +//! @{ // //***************************************************************************** #define AM_HAL_CTIMER_CLK_PIN AM_REG_CTIMER_CTRL0_TMRA0CLK(0x0) @@ -208,6 +203,11 @@ am_hal_ctimer_config_t; //***************************************************************************** typedef void (*am_hal_ctimer_handler_t)(void); +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_debug.c b/bsp/apollo2/libraries/drivers/hal/am_hal_debug.c index 4078b5a5a0..4f79ca7b99 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_debug.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_debug.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_debug.h b/bsp/apollo2/libraries/drivers/hal/am_hal_debug.h index a482799c4f..3cb28d9367 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_debug.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_debug.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_DEBUG_H #define AM_HAL_DEBUG_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // // Debug assert macros. @@ -73,6 +68,11 @@ extern "C" #endif // AM_DEBUG_ASSERT +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function prototypes. diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_flash.c b/bsp/apollo2/libraries/drivers/hal/am_hal_flash.c index cd38da812c..db9f000a78 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_flash.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_flash.c @@ -54,7 +54,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -428,6 +428,47 @@ am_hal_flash_delay(uint32_t ui32Iterations) g_am_hal_flash.delay_cycles(ui32Iterations); } +//***************************************************************************** +// +//! @brief Delays for a desired amount of cycles while also waiting for a +//! status change. +//! +//! @param ui32usMaxDelay - Maximum number of ~1uS delay loops. +//! @param ui32Address - Address of the register for the status change. +//! @param ui32Mask - Mask for the status change. +//! @param ui32Value - Target value for the status change. +//! +//! This function will delay for approximately the given number of microseconds +//! while checking for a status change, exiting when either the given time has +//! expired or the status change is detected. +//! +//! @returns 0 = timeout. +//! 1 = status change detected. +// +//***************************************************************************** +uint32_t +am_hal_flash_delay_status_change(uint32_t ui32usMaxDelay, uint32_t ui32Address, + uint32_t ui32Mask, uint32_t ui32Value) +{ + while ( ui32usMaxDelay-- ) + { + // + // Check the status + // + if ( ( AM_REGVAL(ui32Address) & ui32Mask ) == ui32Value ) + { + return 1; + } + + // + // Call the BOOTROM cycle function to delay for about 1 microsecond. + // + am_hal_flash_delay( FLASH_CYCLES_US(1) ); + } + + return 0; +} // am_hal_flash_delay_status_change() + //***************************************************************************** // //! @brief Static Helper Function to check customer info valid bits erasure. diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_flash.h b/bsp/apollo2/libraries/drivers/hal/am_hal_flash.h index 66d6f5059c..dad39a6d23 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_flash.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_flash.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_FLASH_H #define AM_HAL_FLASH_H -#ifdef __cplusplus -extern "C" -{ -#endif - #include #include @@ -94,13 +89,19 @@ extern "C" // #define AM_HAL_FLASH_ADDR2ABSPAGE(addr) ( addr >> 13 ) +//***************************************************************************** +// +// Given an integer number of microseconds, convert to a value representing the +// number of am_hal_flash_delay() cycles that will provide that amount of delay. +// This macro is designed to take into account some of the call overhead. // -// Given a number of microseconds, convert to a value representing the number of -// cycles that will give that delay. This macro is basically taking into account -// some of the call overhead. // e.g. To provide a 2us delay: // am_hal_flash_delay( FLASH_CYCLES_US(2) ); // +// IMPORTANT - Apollo2 is spec'ed for only 48MHz operation, so this macro +// assumes that. +// +//***************************************************************************** #define FLASH_CYCLES_US(n) ((n * (AM_HAL_CLKGEN_FREQ_MAX_MHZ / 3)) - 4) // @@ -223,6 +224,11 @@ extern g_am_hal_flash_t g_am_hal_flash; #define AM_HAL_FLASH_INFO_CHUNK2INST(n) ((n >> 5) & 1 #define AM_HAL_FLASH_INFO_ADDR2CHUNK(n) ((n) >> 14) +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // Function prototypes for the helper functions @@ -254,6 +260,10 @@ extern void am_hal_flash_recovery(uint32_t ui32RecoveryKey); extern uint32_t am_hal_flash_load_ui32(uint32_t ui32Address); extern void am_hal_flash_store_ui32(uint32_t ui32Address, uint32_t ui32Data); extern void am_hal_flash_delay(uint32_t ui32Iterations); +extern uint32_t am_hal_flash_delay_status_change(uint32_t ui32Iterations, + uint32_t ui32Address, + uint32_t ui32Mask, + uint32_t ui32Value); // // These functions update security/protection bits in the customer INFO blOCK. diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_global.c b/bsp/apollo2/libraries/drivers/hal/am_hal_global.c index 498eb1627a..e9a3e2f67a 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_global.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_global.c @@ -43,7 +43,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_global.h b/bsp/apollo2/libraries/drivers/hal/am_hal_global.h index bb437b198a..0edb0fa745 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_global.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_global.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_GLOBAL_H #define AM_HAL_GLOBAL_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // // Macro definitions @@ -107,6 +102,11 @@ extern "C" //***************************************************************************** extern volatile uint32_t g_ui32HALflags; +#ifdef __cplusplus +extern "C" +{ +#endif + #ifdef __cplusplus } #endif diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.c b/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.c index 480118da6b..6715890737 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -479,7 +479,7 @@ am_hal_gpio_int_register(uint32_t ui32GPIONumber, //! //! This function gets the state of one GPIO polarity bit. //! -//! @note When the bit is a one the interrupt polarity is rising edge. +//! @note When the bit is a zero the interrupt polarity is rising edge. //! //! @return the current polarity. // diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.h b/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.h index 60e5cf36d6..553569e5ed 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_gpio.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -119,7 +119,7 @@ //***************************************************************************** // -// Output options +// Output options (OUTCFG) // //***************************************************************************** #define AM_HAL_GPIO_OUT_DISABLE ((0x0 << 1) << CFGVAL_GPIOCFG_S) @@ -127,6 +127,15 @@ #define AM_HAL_GPIO_OUT_OPENDRAIN ((0x2 << 1) << CFGVAL_GPIOCFG_S) #define AM_HAL_GPIO_OUT_3STATE ((0x3 << 1) << CFGVAL_GPIOCFG_S) +//***************************************************************************** +// +// Special options for IOM0 and IOM4 clocks. +// For 24MHz operation, a special enable must be selected. The 24MHZ select is +// selected via bit0 of OUTCFG (which is, in a way,an alias of OUT_PUSHPULL). +// +//***************************************************************************** +#define AM_HAL_GPIO_24MHZ_ENABLE ((0x1 << 1) << CFGVAL_GPIOCFG_S) + //***************************************************************************** // // Pad configuration options. @@ -498,13 +507,13 @@ //! @return None. // //***************************************************************************** -#define am_hal_gpio_int_polarity_bit_set(ui32PinNumber, ui32Polarity) \ - if ( (uint32_t)(ui32PinNumber) < AM_HAL_GPIO_MAX_PADS ) \ +#define am_hal_gpio_int_polarity_bit_set(ui32BitNum, ui32Polarity) \ + if ( (uint32_t)(ui32BitNum) < AM_HAL_GPIO_MAX_PADS ) \ { \ AM_CRITICAL_BEGIN_ASM \ \ AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL; \ - AM_HAL_GPIO_POL_W(ui32PinNumber, ui32Polarity); \ + AM_HAL_GPIO_POL_W(ui32BitNum, ui32Polarity); \ AM_REGn(GPIO, 0, PADKEY) = 0; \ \ AM_CRITICAL_END_ASM \ diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.c b/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.c index 18e61b98f6..8c8527d7f3 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.c @@ -41,7 +41,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -133,7 +133,7 @@ static am_hal_i2c_bit_bang_priv_t am_hal_i2c_bit_bang_priv; // Wait for any stretched clock to go high // If it times out - return failure // -static bool +static __inline bool i2c_pull_and_wait_scl_hi(void) { // Maximum time to wait for clock stretching @@ -165,7 +165,7 @@ i2c_pull_and_wait_scl_hi(void) //! returns None. // //***************************************************************************** -am_hal_i2c_bit_bang_enum_t +am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number, uint32_t sda_gpio_number) { @@ -192,7 +192,7 @@ am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number, // // Set up SCK GPIO configuration bi-direction, input // - am_hal_gpio_pin_config(sck_gpio_number, AM_HAL_PIN_OPENDRAIN); + am_hal_gpio_pin_config(sck_gpio_number, AM_HAL_PIN_OPENDRAIN | AM_HAL_GPIO_INPEN); // // Set SDA GPIO data bit high so we aren't pulling down the data line @@ -201,7 +201,7 @@ am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number, // // Set up SDA GPIO configuration bi-direction, input // - am_hal_gpio_pin_config(sda_gpio_number, AM_HAL_PIN_OPENDRAIN); + am_hal_gpio_pin_config(sda_gpio_number, AM_HAL_PIN_OPENDRAIN | AM_HAL_GPIO_INPEN); // Now make sure we have control of the clock line // @@ -284,7 +284,7 @@ am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number, //! returns the byte received // //***************************************************************************** -static am_hal_i2c_bit_bang_enum_t +static __inline am_hal_i2c_bit_bang_enum_e i2c_receive_byte(uint8_t *pRxByte, bool bNack) { int i; @@ -389,7 +389,7 @@ i2c_receive_byte(uint8_t *pRxByte, bool bNack) //! } // //***************************************************************************** -static am_hal_i2c_bit_bang_enum_t +static __inline am_hal_i2c_bit_bang_enum_e i2c_send_byte(uint8_t one_byte) { int i; @@ -478,13 +478,13 @@ i2c_send_byte(uint8_t one_byte) //! returns ENUM{AM_HAL_I2C_BIT_BANG_SUCCESS,AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED} // //***************************************************************************** -am_hal_i2c_bit_bang_enum_t +am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_receive(uint8_t address, uint32_t number_of_bytes, uint8_t *pData, uint8_t ui8Offset, bool bUseOffset, bool bNoStop) { uint32_t ui32I; - am_hal_i2c_bit_bang_enum_t status = AM_HAL_I2C_BIT_BANG_SUCCESS; + am_hal_i2c_bit_bang_enum_e status = AM_HAL_I2C_BIT_BANG_SUCCESS; if (i2c_pull_and_wait_scl_hi()) @@ -617,13 +617,13 @@ am_hal_i2c_bit_bang_receive(uint8_t address, uint32_t number_of_bytes, //! AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED} // //***************************************************************************** -am_hal_i2c_bit_bang_enum_t +am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_send(uint8_t address, uint32_t number_of_bytes, uint8_t *pData, uint8_t ui8Offset, bool bUseOffset, bool bNoStop) { uint32_t ui32I; - am_hal_i2c_bit_bang_enum_t status; + am_hal_i2c_bit_bang_enum_e status; bool data_naked = false; if (i2c_pull_and_wait_scl_hi()) diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.h b/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.h index a9571edbe5..bc2afa46fe 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.h @@ -40,17 +40,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_I2C_BIT_BANG_H #define AM_HAL_I2C_BIT_BANG_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // // Enumerated return constants @@ -63,24 +58,30 @@ typedef enum AM_HAL_I2C_BIT_BANG_DATA_NAKED, AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT, AM_HAL_I2C_BIT_BANG_DATA_TIMEOUT, -}am_hal_i2c_bit_bang_enum_t; + AM_HAL_I2C_BIT_BANG_STATUS_MAX, +}am_hal_i2c_bit_bang_enum_e; + +#ifdef __cplusplus +extern "C" +{ +#endif //***************************************************************************** // // External function definitions // //***************************************************************************** -extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number, +extern am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number, uint32_t sda_gpio_number); -extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_send(uint8_t address, +extern am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_send(uint8_t address, uint32_t number_of_bytes, uint8_t *pData, uint8_t ui8Offset, bool bUseOffset, bool bNoStop); -extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_receive(uint8_t address, +extern am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_receive(uint8_t address, uint32_t number_of_bytes, uint8_t *pData, uint8_t ui8Offset, diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.c b/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.c index 2f93b09cfc..5a404211e1 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.c @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -190,7 +190,7 @@ am_hal_interrupt_priority_set(uint32_t ui32Interrupt, uint32_t ui32Priority) // // OR in the new priority. // - *pui32PriorityReg |= (ui32Priority << ui32Shift); + *pui32PriorityReg = ui32OldPriority | (ui32Priority << ui32Shift); } //***************************************************************************** @@ -210,7 +210,7 @@ void am_hal_interrupt_pend_set(uint32_t ui32Interrupt) // // Check to see if the specified interrupt is valid for this MCU // - if ( ui32Interrupt > 47 ) + if ( ui32Interrupt > AM_HAL_INTERRUPT_MAX ) { return; } @@ -247,7 +247,7 @@ void am_hal_interrupt_pend_clear(uint32_t ui32Interrupt) // // Check to see if the specified interrupt is valid for this MCU // - if ( ui32Interrupt > 47 ) + if ( ui32Interrupt > AM_HAL_INTERRUPT_MAX ) { return; } diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.h b/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.h index a8523371eb..1ba1550271 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.h @@ -44,16 +44,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_INTERRUPT_H #define AM_HAL_INTERRUPT_H -#ifdef __cplusplus -extern "C" -{ -#endif //***************************************************************************** // //! @name ISR number macros. @@ -66,6 +62,7 @@ extern "C" // // Hardware interrupts // +#define AM_HAL_INTERRUPT_MAX (47) //AM_HAL_INTERRUPT_SOFTWARE3 #define AM_HAL_INTERRUPT_RESET 1 #define AM_HAL_INTERRUPT_NMI 2 #define AM_HAL_INTERRUPT_HARDFAULT 3 @@ -130,6 +127,10 @@ extern "C" //***************************************************************************** #define AM_HAL_INTERRUPT_PRIORITY(n) (((uint32_t)(n) & 0x7) << 5) +#ifdef __cplusplus +extern "C" +{ +#endif //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_iom.c b/bsp/apollo2/libraries/drivers/hal/am_hal_iom.c index 244c28732b..222aca352a 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_iom.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_iom.c @@ -42,14 +42,13 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #include #include #include "am_mcu_apollo.h" -//#include "am_util_delay.h" #ifdef __IAR_SYSTEMS_ICC__ #define AM_INSTR_CLZ(n) __CLZ(n) @@ -62,22 +61,6 @@ #define AM_ASSERT_INVALID_THRESHOLD (1) #endif -uint32_t am_util_wait_status_change(uint32_t ui32Iterations, uint32_t ui32Address, uint32_t ui32Mask, uint32_t ui32Value) -{ - int i; - for (i = 0; i < ui32Iterations; i++) - { - // Check the status - if (((*(uint32_t *)ui32Address) & ui32Mask) == ui32Value) - { - return 1; - } - // Call the BOOTROM cycle delay function to get about 1 usec @ 48MHz - am_hal_flash_delay(16); - } - return 0; -} - //***************************************************************************** // // Forcing optimizations @@ -111,6 +94,8 @@ internal_am_hal_iom_spi_cmd_construct(uint32_t ui32Operation, uint32_t ui32ChipSelect, uint32_t ui32NumBytes, uint32_t ui32Options); +static am_hal_iom_status_e +internal_iom_wait_i2c_scl_hi(uint32_t ui32Module); //***************************************************************************** // @@ -126,11 +111,6 @@ internal_am_hal_iom_spi_cmd_construct(uint32_t ui32Operation, // Global state variables // //***************************************************************************** -// -// Save error status from ISR, particularly for use in I2C queue mode. -// -uint32_t g_iom_error_status = 0; - // // Define a structure to map CE for IOM4 only. // @@ -149,6 +129,26 @@ const IOMPad_t g_IOMPads[] = {5, 47, 6}, {6, 35, 4}, {7, 38, 6} }; +typedef struct +{ + uint8_t module; // IOM module + uint8_t pad; // GPIO Pad + uint8_t funcsel; // FNCSEL value +} I2CPad_t; + +// Define the mapping between I2C SCL Pads, and FNCSEL values for all IOMs. +const I2CPad_t g_I2CPads[] = +{ + {0, 5, 0}, + {1, 8, 0}, + {2, 0, 7}, + {3, 42, 4}, + {4, 39, 4}, + {5, 48, 4}, + {2, 27, 4}, +}; + +// Defines for IOM 4 Workaround #define WORKAROUND_IOM 4 #define WORKAROUND_IOM_MOSI_PIN 44 #define WORKAROUND_IOM_MOSI_CFG AM_HAL_PIN_44_M4MOSI @@ -174,10 +174,15 @@ am_hal_iom_nb_buffer; // // Global State to keep track if there is an ongoing transaction // -volatile bool g_bIomBusy[AM_REG_IOMSTR_NUM_MODULES] = {0}; +volatile bool g_bIomBusy[AM_REG_IOMSTR_NUM_MODULES + 1] = {0}; am_hal_iom_nb_buffer g_psIOMBuffers[AM_REG_IOMSTR_NUM_MODULES]; +// +// Save error status from non-blocking calls +// +static am_hal_iom_status_e g_iom_error_status[AM_REG_IOMSTR_NUM_MODULES + 1]; + //***************************************************************************** // // Computed timeout. @@ -208,6 +213,19 @@ am_hal_iom_queue_flush_t am_hal_iom_queue_flush = am_hal_iom_sleeping_queue_flus //***************************************************************************** am_hal_iom_pwrsave_t am_hal_iom_pwrsave[AM_REG_IOMSTR_NUM_MODULES]; +//***************************************************************************** +// +// I2C BitBang to IOM error mapping +// +//***************************************************************************** +const am_hal_iom_status_e i2c_bb_errmap[AM_HAL_I2C_BIT_BANG_STATUS_MAX] = + { + AM_HAL_IOM_SUCCESS, // AM_HAL_I2C_BIT_BANG_SUCCESS, + AM_HAL_IOM_ERR_I2C_NAK, // AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED, + AM_HAL_IOM_ERR_I2C_NAK, // AM_HAL_I2C_BIT_BANG_DATA_NAKED, + AM_HAL_IOM_ERR_TIMEOUT, // AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT, + AM_HAL_IOM_ERR_TIMEOUT, // AM_HAL_I2C_BIT_BANG_DATA_TIMEOUT, + }; //***************************************************************************** // @@ -215,6 +233,50 @@ am_hal_iom_pwrsave_t am_hal_iom_pwrsave[AM_REG_IOMSTR_NUM_MODULES]; // //***************************************************************************** +//***************************************************************************** +// +// Get the error interrupt staus +// +//***************************************************************************** +// +//! @brief Returns the error status based on interrupt bits +//! +//! @param ui32Module - IOM module +//! ui32Status - Currently accumulated error status +//! +//! The function looks at the supplied interrupt error status bits and the +//! the current INTSTAT and maps the same to the enum am_hal_iom_status_e. +//! +//! @return Returns the appropriate error status in the form of am_hal_iom_status_e +//! +//***************************************************************************** +static am_hal_iom_status_e +internal_iom_get_int_err(uint32_t ui32Module, uint32_t ui32IntStatus) +{ + am_hal_iom_status_e ui32Status = AM_HAL_IOM_SUCCESS; + // + // Let's accumulate the errors + // + ui32IntStatus |= am_hal_iom_int_status_get(ui32Module, false); + + if (ui32IntStatus & AM_HAL_IOM_INT_SWERR) + { + // Error in hardware command issued or illegal access by SW + ui32Status = AM_HAL_IOM_ERR_INVALID_OPER; + } + else if (ui32IntStatus & AM_HAL_IOM_INT_I2CARBERR) + { + // Loss of I2C multi-master arbitration + ui32Status = AM_HAL_IOM_ERR_I2C_ARB; + } + else if (ui32IntStatus & AM_HAL_IOM_INT_NAK) + { + // I2C NAK + ui32Status = AM_HAL_IOM_ERR_I2C_NAK; + } + return ui32Status; +} + //***************************************************************************** // onebit() //***************************************************************************** @@ -315,6 +377,128 @@ isRevB0(void) } } +//***************************************************************************** +// +// Checks to see if this processor is a Rev B2 device. +// +// This is needed for the B2 I2C workaround. +// +//***************************************************************************** +static bool +isRevB2(void) +{ + // + // Check to make sure the major rev is B and the minor rev is zero. + // + if ( (AM_REG(MCUCTRL, CHIPREV) & 0xFF) == + (AM_REG_MCUCTRL_CHIPREV_REVMAJ_B | AM_REG_MCUCTRL_CHIPREV_REVMIN_REV2) ) + { + return true; + } + else + { + return false; + } +} + +//***************************************************************************** +// +// Checks and waits for the SCL line to be high +// This is to ensure clock hi time specs are not violated in case slave did +// clock stretching in previous transaction +// +//***************************************************************************** +static am_hal_iom_status_e +internal_iom_wait_i2c_scl_hi(uint32_t ui32Module) +{ + uint32_t ui32IOMGPIO = 0xDEADBEEF; + volatile uint32_t *pui32SCLPadreg; + uint32_t ui32SCLPadregVal; + uint32_t index; + uint8_t ui8PadRegVal; + uint8_t ui8FncSelVal; + uint32_t waitStatus; + + // Need to change the SCL pin as a GPIO and poll till it is set to hi + // For all the IOM's except for IOM2, there is a single designated pin for SCL + // IOM2 has two choices and we need to determine which one + + // + // Figure out which GPIO we are using for the SCL + // + for ( index = 0; index < (sizeof(g_I2CPads) / sizeof(I2CPad_t)); index++ ) + { + // + // Is this for the IOM that we are using? + // + if ( g_I2CPads[index].module == ui32Module ) + { + // + // Get the PAD register value + // + ui8PadRegVal = ((AM_REGVAL(AM_HAL_GPIO_PADREG(g_I2CPads[index].pad))) & + AM_HAL_GPIO_PADREG_M(g_I2CPads[index].pad)) >> + AM_HAL_GPIO_PADREG_S(g_I2CPads[index].pad); + + // + // Get the FNCSEL field value + // + ui8FncSelVal = (ui8PadRegVal & 0x38) >> 3; + + // + // Is the FNCSEL filed for this pad set to the expected value? + // + if ( ui8FncSelVal == g_I2CPads[index].funcsel ) + { + // This is the GPIO we need to use. + ui32IOMGPIO = g_I2CPads[index].pad; + break; + } + } + } + if (0xDEADBEEF == ui32IOMGPIO) + { + // SCL has not been configured + return AM_HAL_IOM_ERR_INVALID_CFG; + } + + // + // Save the locations and values of the SCL pin configuration + // information. + // + pui32SCLPadreg = (volatile uint32_t *)AM_HAL_GPIO_PADREG(ui32IOMGPIO); + ui32SCLPadregVal = *pui32SCLPadreg; + // + // Temporarily configure the override pin as an input. + // + am_hal_gpio_pin_config(ui32IOMGPIO, AM_HAL_PIN_INPUT); + + // + // Make sure SCL is high within standard timeout + // + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_HAL_GPIO_RD_REG(ui32IOMGPIO), AM_HAL_GPIO_RD_M(ui32IOMGPIO), + AM_HAL_GPIO_RD_M(ui32IOMGPIO)); + + // + // Write the GPIO PADKEY register + // + AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL; + // Revert back the original settings + *pui32SCLPadreg = ui32SCLPadregVal; + // + // Re-lock the GPIO PADKEY register + // + AM_REGn(GPIO, 0, PADKEY) = 0; + + if (waitStatus != 1) + { + return AM_HAL_IOM_ERR_TIMEOUT; + } + + return AM_HAL_IOM_SUCCESS; +} + //***************************************************************************** // //! @brief Returns the proper settings for the CLKCFG register. @@ -475,6 +659,53 @@ uint64_t iom_get_interface_clock_cfg(uint32_t ui32FreqHz, uint32_t ui32Phase ) } //iom_get_interface_clock_cfg() +//***************************************************************************** +// +//! @brief Clock setting for the I2C Clock Stretch Workaround +//! +//! This restricts the frequencies that can be used for I2C devices on +//! +//! @param ui32FreqHz - The desired interface frequency in Hz. +//! +//! @return None. +// +//***************************************************************************** +static +uint64_t iom_get_i2c_workaround_clock_cfg(uint32_t ui32FreqHz) +{ + uint32_t ui32Fsel; + + // Only allow certain SCL frequencies for clock stretching devices. + if (ui32FreqHz == AM_HAL_IOM_800KHZ) + { + ui32Fsel = 2; + } + else if (ui32FreqHz == AM_HAL_IOM_400KHZ) + { + ui32Fsel = 3; + } + else if (ui32FreqHz == AM_HAL_IOM_200KHZ) + { + ui32Fsel = 4; + } + else if (ui32FreqHz == AM_HAL_IOM_100KHZ) + { + ui32Fsel = 5; + } + else // Default is 100KHz. + { + ui32Fsel = 5; + } + + // Return the resulting CLKCFG register settings. + return (AM_REG_IOMSTR_CLKCFG_FSEL(ui32Fsel) | + AM_REG_IOMSTR_CLKCFG_DIV3(0) | + AM_REG_IOMSTR_CLKCFG_DIVEN(1) | + AM_REG_IOMSTR_CLKCFG_LOWPER(14) | + AM_REG_IOMSTR_CLKCFG_TOTPER(29)); + +} // iom_get_i2c_workaround_clock_cfg + //***************************************************************************** // //! @brief Enable the IOM in the power control block. @@ -777,27 +1008,42 @@ am_hal_iom_config(uint32_t ui32Module, const am_hal_iom_config_t *psConfig) #error AM_ASSERT_INVALID_THRESHOLD must be 0 or 1. #endif - // - // An exception occurs in the LOWPER computation when setting an interface - // frequency (such as a divide by 5 frequency) which results in a 60/40 - // duty cycle. The 60% cycle must occur in the appropriate half-period, - // as only one of the half-periods is active, depending on which phase - // is being selected. - // If SPHA=0 the low period must be 60%. If SPHA=1 high period must be 60%. - // Note that the predetermined frequency parameters use the formula - // lowper = (totper-1)/2, which results in a 60% low period. - // - ui32ClkCfg = iom_get_interface_clock_cfg(psConfig->ui32ClockFrequency, - psConfig->bSPHA ); + // Apply I2C clock stretching workaround if B2 silicon and IOM 1,2,3, or 5 + // Note: Only I2C clock speeds of AM_HAL_IOM_800KHZ, AM_HAL_IOM_400KHZ, + // AM_HAL_IOM_200KHZ, and AM_HAL_IOM_100KHZ are allowed. Other values will + // result in the default of AM_HAL_IOM_100KHZ. + if ((0 != ui32Module) && (4 != ui32Module) && (6 != ui32Module) && + isRevB2() && (AM_HAL_IOM_I2CMODE == psConfig->ui32InterfaceMode)) + { + // Set SPHA field to 1 on B2 silicon to enable the feature; + AM_REGn(IOMSTR, ui32Module, CFG) |= AM_REG_IOMSTR_CFG_SPHA_M; + ui32ClkCfg = iom_get_i2c_workaround_clock_cfg(psConfig->ui32ClockFrequency); + } + else + { + // + // An exception occurs in the LOWPER computation when setting an interface + // frequency (such as a divide by 5 frequency) which results in a 60/40 + // duty cycle. The 60% cycle must occur in the appropriate half-period, + // as only one of the half-periods is active, depending on which phase + // is being selected. + // If SPHA=0 the low period must be 60%. If SPHA=1 high period must be 60%. + // Note that the predetermined frequency parameters use the formula + // lowper = (totper-1)/2, which results in a 60% low period. + // + ui32ClkCfg = iom_get_interface_clock_cfg(psConfig->ui32ClockFrequency, + psConfig->bSPHA ); + } + if ( ui32ClkCfg ) { AM_REGn(IOMSTR, ui32Module, CLKCFG) = (uint32_t)ui32ClkCfg; } - + // // Compute the status timeout value. // - ui32StatusTimeout[ui32Module] = MAX_IOM_BITS * AM_HAL_IOM_MAX_FIFO_SIZE * + ui32StatusTimeout[ui32Module] = MAX_IOM_BITS * AM_HAL_IOM_MAX_FIFO_SIZE * IOM_OVERHEAD_FACTOR * (am_hal_clkgen_sysclk_get() / psConfig->ui32ClockFrequency); } @@ -1101,6 +1347,10 @@ am_hal_iom_workaround_word_write(uint32_t ui32ChipSelect, pui32CSPadreg, ui32CSPadregVal, ui32DelayTime, ui32ClkCfg, ui32LowClkCfg, bRising); + // + // Re-lock the GPIO PADKEY register + // + AM_REGn(GPIO, 0, PADKEY) = 0; // // Update the pointer and data counter. @@ -1274,21 +1524,29 @@ iom_workaround_loop(uint32_t ui32PadRegVal, volatile uint32_t *pui32PadReg, //! last word with bytes of any value. The IOM hardware will only read the //! first \e ui32NumBytes in the \e pui8Data array. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) { + am_hal_iom_status_e ui32Status; // // Validate parameters // - am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES, - "Trying to use an IOM module that doesn't exist."); - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Check to see if queues have been enabled. If they are, we'll actually @@ -1299,27 +1557,32 @@ am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, // // If the queue is on, go ahead and add this transaction to the queue. // - am_hal_iom_queue_spi_write(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_queue_spi_write(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, 0); - // - // Wait until the transaction actually clears. - // - am_hal_iom_queue_flush(ui32Module); + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } // // At this point, we've completed the transaction, and we can return. // - return; } else { // // Otherwise, we'll just do a polled transaction. // - am_hal_iom_spi_write_nq(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_spi_write_nq(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options); } + return ui32Status; } //***************************************************************************** @@ -1341,26 +1604,38 @@ am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, //! into 32-bit words, which are then placed into the \e pui32Data array. Only //! the first \e ui32NumBytes bytes in this array will contain valid data. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) { + am_hal_iom_status_e ui32Status; // // Validate parameters // - am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES, - "Trying to use an IOM module that doesn't exist."); - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); - + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big."); + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Check to see if queues have been enabled. If they are, we'll actually @@ -1371,27 +1646,131 @@ am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, // // If the queue is on, go ahead and add this transaction to the queue. // - am_hal_iom_queue_spi_read(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_queue_spi_read(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, 0); - // - // Wait until the transaction actually clears. - // - am_hal_iom_queue_flush(ui32Module); + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } // // At this point, we've completed the transaction, and we can return. // - return; } else { // // Otherwise, just perform a polled transaction. // - am_hal_iom_spi_read_nq(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_spi_read_nq(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options); } + return ui32Status; +} + +//***************************************************************************** +// +//! @brief Perform a simple full-duplex transaction to the SPI interface. +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32ChipSelect - Chip-select number for this transaction. +//! @param pui32TxData - Pointer to the bytes that will be sent. +//! @param pui32RxData - Pointer to the bytes that will be received. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional SPI transfer options. +//! +//! This function performs SPI full-duplex operation to a selected SPI device. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32TxData array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui32TxData array. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_spi_fullduplex(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32TxData, uint32_t *pui32RxData, + uint32_t ui32NumBytes, uint32_t ui32Options) +{ + am_hal_iom_status_e ui32Status; + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + // + // Full-Duplex operation is only supported for Apollo2 B2 Silicon. + // + if (!isRevB2()) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_OPER; + return ui32Status; + } + + // + // Check to see if queues have been enabled. If they are, we'll actually + // switch to the queued interface. + // +#if 0 + + // To be implemented!!! + if ( g_psIOMQueue[ui32Module].pui8Data != NULL ) + { + // + // If the queue is on, go ahead and add this transaction to the queue. + // + ui32Status = am_hal_iom_queue_spi_write(ui32Module, ui32ChipSelect, pui32Data, + ui32NumBytes, ui32Options, 0); + + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } + + // + // At this point, we've completed the transaction, and we can return. + // + } + else + { +#endif + // + // Otherwise, we'll just do a polled transaction. + // + ui32Status = am_hal_iom_spi_fullduplex_nq(ui32Module, ui32ChipSelect, + pui32TxData, pui32RxData, + ui32NumBytes, ui32Options); +#if 0 + } +#endif + + return ui32Status; } //***************************************************************************** @@ -1415,10 +1794,10 @@ am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, //! last word with bytes of any value. The IOM hardware will only read the //! first \e ui32NumBytes in the \e pui8Data array. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -uint32_t +am_hal_iom_status_e am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) @@ -1427,34 +1806,47 @@ am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t ui32SpaceInFifo; uint32_t ui32IntConfig; uint32_t ui32MaxFifoSize; - uint32_t ui32Status = 1; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; // // Validate parameters // - am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES, - "Trying to use an IOM module that doesn't exist."); - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big."); + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); // - // Wait until any earlier transactions have completed. - // - am_hal_iom_poll_complete(ui32Module); - // // Disable interrupts so that we don't get any undesired interrupts. // ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN); AM_REGn(IOMSTR, ui32Module, INTEN) = 0; - // Clear CMDCMP status - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; // // If we're on a B0 part, and we're using IOM4, our first byte coule be @@ -1545,23 +1937,27 @@ am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, // // Make sure CMDCMP was raised with standard timeout // - ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module], - AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, - AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } // - // Re-enable IOM interrupts. Make sure CMDCMP is cleared + // Re-enable IOM interrupts. // - AM_REGn(IOMSTR, ui32Module, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; - am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen"); - - // - // Return the status (0 = timeout; 1 = success) - // return ui32Status; - } //***************************************************************************** @@ -1583,10 +1979,10 @@ am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, //! into 32-bit words, which are then placed into the \e pui32Data array. Only //! the first \e ui32NumBytes bytes in this array will contain valid data. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -uint32_t +am_hal_iom_status_e am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) @@ -1594,26 +1990,36 @@ am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t ui32BytesInFifo; uint32_t ui32IntConfig; uint32_t bCmdCmp = false; - uint32_t ui32Status = 1; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; // // Validate parameters // - am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES, - "Trying to use an IOM module that doesn't exist."); - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big."); - - // - // Wait until the bus is idle, then start the requested READ transfer on - // the physical interface. - // - am_hal_iom_poll_complete(ui32Module); + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Disable interrupts so that we don't get any undesired interrupts. @@ -1625,10 +2031,8 @@ am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, // AM_REGn(IOMSTR, ui32Module, INTEN) = 0; - // - // Clear CMDCMP status - // - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; // // If we're on a B0 part, and we're using IOM4, our first byte coule be @@ -1654,11 +2058,22 @@ am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, // Wait for the dummy word to go out over the bus. // // Make sure the command complete has also been raised - ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module], - AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, - AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); - - + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + return ui32Status; + } + // Clear CMDCMP status AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); } @@ -1706,21 +2121,230 @@ am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, // // Make sure CMDCMP was raised, // - ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module], - AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, - AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } // // Re-enable IOM interrupts. Make sure CMDCMP is cleared // - AM_REGn(IOMSTR, ui32Module, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; - am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen"); - + return ui32Status; + +} + +//***************************************************************************** +// +//! @brief Perform a simple full-duplex operation to the SPI interface (without queuing) +//! +//! @param ui32Module - Module number for the IOM +//! @param ui32ChipSelect - Chip-select number for this transaction. +//! @param pui32Data - Pointer to the bytes that will be sent. +//! @param pui32Data - Pointer to the bytes that will be received. +//! @param ui32NumBytes - Number of bytes to send. +//! @param ui32Options - Additional SPI transfer options. +//! +//! This function performs SPI full-duplex operation to a selected SPI device. +//! +//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. +//! This means that you will need to byte-pack the \e pui32TxData array with the +//! data you intend to send over the interface. One easy way to do this is to +//! declare the array as a 32-bit integer array, but use an 8-bit pointer to +//! put your actual data into the array. If there are not enough bytes in your +//! desired message to completely fill the last 32-bit word, you may pad that +//! last word with bytes of any value. The IOM hardware will only read the +//! first \e ui32NumBytes in the \e pui32TxData array. +//! +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. +// +//***************************************************************************** +am_hal_iom_status_e +am_hal_iom_spi_fullduplex_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32TxData, uint32_t *pui32RxData, + uint32_t ui32NumBytes, uint32_t ui32Options) +{ + uint32_t ui32TransferSize; + uint32_t ui32SpaceInFifo; + uint32_t bCmdCmp = false; + uint32_t ui32IntConfig; + uint32_t ui32MaxFifoSize; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; + // - // Return the status (0 = timeout; 1 = success) + // Validate parameters // + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + // + // Full-Duplex operation is only supported for Apollo2 B2 Silicon. + // + if (!isRevB2()) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_OPER; + return ui32Status; + } + + // + // Put the IOM into Full-Duplex mode. + // + AM_REGn(IOMSTR, ui32Module, CFG) |= AM_REG_IOMSTR_CFG_FULLDUP_FULLDUP; + + ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? + AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); + // + // Disable interrupts so that we don't get any undesired interrupts. + // + ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN); + AM_REGn(IOMSTR, ui32Module, INTEN) = 0; + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + + // + // Figure out how many bytes we can write to the FIFO immediately. + // + ui32TransferSize = (ui32NumBytes <= ui32MaxFifoSize ? ui32NumBytes : + ui32MaxFifoSize); + // + // write up to the maximum FIFO size into the fifo. + // + am_hal_iom_fifo_write(ui32Module, pui32TxData, ui32TransferSize); + + // + // Start the write on the bus. + // + am_hal_iom_spi_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32ChipSelect, + ui32NumBytes, ui32Options); + + // + // Update the pointer and data counter. + // + pui32TxData += ui32TransferSize >> 2; + + // + // Keep looping until we're out of bytes to receive or command complete (error). + // + while ( ui32NumBytes ) + { + // + // Wait for FIFO to empty. + // + while (am_hal_iom_fifo_full_slots(ui32Module) > 0); + + am_hal_iom_fifo_read(ui32Module, pui32RxData, ui32TransferSize); + ui32NumBytes -= ui32TransferSize; + pui32RxData += ui32TransferSize >> 2; + + // + // Get the number of bytes that can be written (always a multiple of 4). + // + ui32SpaceInFifo = am_hal_iom_fifo_empty_slots(ui32Module); + + if ( ui32NumBytes <= ui32SpaceInFifo ) + { + // + // If the entire message will fit in the fifo, prepare to copy + // everything. + // + ui32TransferSize = ui32NumBytes; + } + else + { + // + // If only a portion of the message will fit in the fifo, prepare + // to copy the largest number of 4-byte blocks possible. + // + ui32TransferSize = ui32SpaceInFifo & ~(0x3); + } + + // + // Write this chunk to the fifo. + // + am_hal_iom_fifo_write(ui32Module, pui32TxData, ui32TransferSize); + + // + // Update the data pointer and bytes-left count. + // + pui32TxData += ui32TransferSize >> 2; + + // + // Check for Command Complete condition. + if ( bCmdCmp == true ) + { + // + // No more data expected. Get out of the loop + // + break; + } + + bCmdCmp = AM_BFRn(IOMSTR, ui32Module, INTSTAT, CMDCMP); + + } + + // + // Make sure CMDCMP was raised with standard timeout + // + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } + + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + + // + // Take the IOM out of Full-Duplex mode. + // + AM_REGn(IOMSTR, ui32Module, CFG) &= ~AM_REG_IOMSTR_CFG_FULLDUP_FULLDUP; + return ui32Status; } @@ -1754,15 +2378,19 @@ am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, //! last word with bytes of any value. The IOM hardware will only read the //! first \e ui32NumBytes in the \e pui8Data array. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. Note that +//! successful execution for non-blocking call only means the transaction was +//! successfully initiated. The status of the transaction is not known till the +//! callback is called on completion // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { + am_hal_iom_status_e ui32Status; uint32_t ui32TransferSize; uint32_t ui32MaxFifoSize; @@ -1771,24 +2399,32 @@ am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, // if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; } - - // - // Make sure the transfer isn't too long for the hardware to support. - // - am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big."); - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); - - ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? - AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); - // // Wait until the bus is idle // am_hal_iom_poll_complete(ui32Module); + // Reset the error status for non-blocking transfer + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + + ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? + AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); + // // Need to mark IOM busy to avoid another transaction to be scheduled. // This is to take care of a race condition in Queue mode, where the IDLE @@ -1796,10 +2432,8 @@ am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, // g_bIomBusy[ui32Module] = true; - // - // Clear CMDCMP status - // - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; // // Check to see if we need to do the workaround. @@ -1863,6 +2497,7 @@ am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, ui32NumBytes, ui32Options); } } + return ui32Status; } //***************************************************************************** @@ -1892,51 +2527,62 @@ am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, //! into 32-bit words, which are then placed into the \e pui32Data array. Only //! the first \e ui32NumBytes bytes in this array will contain valid data. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. Note that +//! successful execution for non-blocking call only means the transaction was +//! successfully initiated. The status of the transaction is not known till the +//! callback is called on completion // //***************************************************************************** -uint32_t +am_hal_iom_status_e am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { + am_hal_iom_status_e ui32Status; uint32_t ui32IntConfig; - uint32_t ui32Status = 1; - + uint32_t waitStatus; + // // Validate parameters // - am_hal_debug_assert_msg(ui32Module < AM_REG_IOMSTR_NUM_MODULES, - "Trying to use an IOM module that doesn't exist."); - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); - - // - // Make sure the transfer isn't too long for the hardware to support. - // - am_hal_debug_assert_msg(ui32NumBytes < 4096, "SPI transfer too big."); - + if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) + { + return AM_HAL_IOM_ERR_INVALID_MODULE; + } // // Wait until the bus is idle // am_hal_iom_poll_complete(ui32Module); + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + // + // Make sure the transfer isn't too long for the hardware to support. + // + if (ui32NumBytes >= 4096) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } + // // Need to mark IOM busy to avoid another transaction to be scheduled. // This is to take care of a race condition in Queue mode, where the IDLE // set is not a guarantee that the CMDCMP has been received // - g_bIomBusy[ui32Module] = true; - // - // Clear CMDCMP status - // - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; // - // If we're on a B0 part, and we're using IOM4, our first byte coule be + // If we're on a B0 part, and we're using IOM4, our first byte could be // corrupted, so we need to send a dummy word with chip-select held high to // get that first byte out of the way. This is only true for spi reads with // OFFSET values. @@ -1968,9 +2614,15 @@ am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, // Wait for the dummy word to go out over the bus. // // Make sure the command complete has also been raised - ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module], - AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, - AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + return ui32Status; + } // // Re-mark IOM as busy @@ -1981,7 +2633,7 @@ am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, // // Re-enable IOM interrupts. Make sure CMDCMP is cleared // - AM_REGn(IOMSTR, 4, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M); + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; AM_REGn(IOMSTR, 4, INTEN) = ui32IntConfig; } @@ -1999,9 +2651,7 @@ am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, // am_hal_iom_spi_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32ChipSelect, ui32NumBytes, ui32Options); - - am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen"); - + return ui32Status; } @@ -2097,10 +2747,10 @@ am_hal_iom_spi_cmd_run(uint32_t ui32Operation, uint32_t ui32Module, //! last word with bytes of any value. The IOM hardware will only read the //! first \e ui32NumBytes in the \e pui32Data array. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -uint32_t +am_hal_iom_status_e am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) @@ -2109,17 +2759,29 @@ am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t ui32SpaceInFifo; uint32_t ui32IntConfig; uint32_t ui32MaxFifoSize; - uint32_t ui32Status = 1; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; // // Validate parameters // if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) { - return 0; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until any earlier transactions have completed. + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Redirect to the bit-bang interface if the module number matches the @@ -2129,13 +2791,13 @@ am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, { if ( ui32Options & AM_HAL_IOM_RAW ) { - am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, (uint8_t *)pui32Data, 0, false, (ui32Options & AM_HAL_IOM_NO_STOP)); } else { - am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, (uint8_t *)pui32Data, ((ui32Options & 0xFF00) >> 8), true, @@ -2143,34 +2805,32 @@ am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, } // - // Return. + // Return. convert BB retCode to proper retCode here // - return 0; + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; + return ui32Status; } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big."); + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); - // - // Wait until any earlier transactions have completed. - // - am_hal_iom_poll_complete(ui32Module); - // // Disable interrupts so that we don't get any undesired interrupts. // ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN); AM_REGn(IOMSTR, ui32Module, INTEN) = 0; - // - // Clear CMDCMP status - // - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; // // Figure out how many bytes we can write to the FIFO immediately. @@ -2183,9 +2843,20 @@ am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, // // Start the write on the bus. // - am_hal_iom_i2c_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32BusAddress, + ui32Status = am_hal_iom_i2c_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32BusAddress, ui32NumBytes, ui32Options); + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status = ui32Status; + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + return ui32Status; + } // // Update the pointer and data counter. // @@ -2234,21 +2905,25 @@ am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, // // Make sure CMDCMP was raised, // - ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module], - AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, - AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } // - // Re-enable IOM interrupts. Make sure CMDCMP is cleared + // Re-enable IOM interrupts. // - AM_REGn(IOMSTR, ui32Module, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; - - am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen"); - - // - // Return the status (0 = timeout; 1 = success) - // return ui32Status; } @@ -2273,10 +2948,10 @@ am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, //! into 32-bit words, which are then placed into the \e pui32Data array. Only //! the first \e ui32NumBytes bytes in this array will contain valid data. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -uint32_t +am_hal_iom_status_e am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) @@ -2284,17 +2959,29 @@ am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t ui32BytesInFifo; uint32_t ui32IntConfig; uint32_t bCmdCmp = false; - uint32_t ui32Status = 1; + am_hal_iom_status_e ui32Status; + uint32_t waitStatus; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; // // Validate parameters // if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) { - return 0; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Redirect to the bit-bang interface if the module number matches the @@ -2304,13 +2991,13 @@ am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, { if ( ui32Options & AM_HAL_IOM_RAW ) { - am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, (uint8_t *)pui32Data, 0, false, (ui32Options & AM_HAL_IOM_NO_STOP)); } else { - am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, (uint8_t *)pui32Data, ((ui32Options & 0xFF00) >> 8), true, @@ -2318,20 +3005,20 @@ am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, } // - // Return. + // Return. convert i2c bb retCode // - return 0; + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; + return ui32Status; } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big."); - - // - // Wait until the bus is idle - // - am_hal_iom_poll_complete(ui32Module); + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Disable interrupts so that we don't get any undesired interrupts. @@ -2339,14 +3026,24 @@ am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, ui32IntConfig = AM_REGn(IOMSTR, ui32Module, INTEN); AM_REGn(IOMSTR, ui32Module, INTEN) = 0; - // - // Clear CMDCMP status - // - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; - am_hal_iom_i2c_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32BusAddress, + ui32Status = am_hal_iom_i2c_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32BusAddress, ui32NumBytes, ui32Options); + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status = ui32Status; + // + // Re-enable IOM interrupts. + // + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; + AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; + return ui32Status; + } + // // Start a loop to catch the Rx data. // @@ -2387,21 +3084,24 @@ am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, // // Make sure CMDCMP was raised, // - ui32Status = am_util_wait_status_change(ui32StatusTimeout[ui32Module], - AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, - AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + waitStatus = am_hal_flash_delay_status_change(ui32StatusTimeout[ui32Module], + AM_REG_IOMSTRn(ui32Module) + AM_REG_IOMSTR_INTSTAT_O, + AM_REG_IOMSTR_INTEN_CMDCMP_M, AM_REG_IOMSTR_INTEN_CMDCMP_M); + if (waitStatus != 1) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_TIMEOUT; + } + else + { + g_iom_error_status[ui32Module] = ui32Status = internal_iom_get_int_err(ui32Module, 0); + } // - // Re-enable IOM interrupts. Make sure CMDCMP is cleared + // Re-enable IOM interrupts. // - AM_REGn(IOMSTR, ui32Module, INTCLR) = (ui32IntConfig | AM_REG_IOMSTR_INTSTAT_CMDCMP_M); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; AM_REGn(IOMSTR, ui32Module, INTEN) = ui32IntConfig; - - am_hal_debug_assert_msg(ui32Status == 1,"IOM CMDCMP was not seen"); - - // - // Return the status (0 = timeout; 1 = success) - // return ui32Status; } @@ -2420,23 +3120,35 @@ am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, //! See the "Command Options" section for parameters that may be ORed together //! and used in the \b ui32Options parameter. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) { + am_hal_iom_status_e ui32Status; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; // // Validate parameters // if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Redirect to the bit-bang interface if the module number matches the @@ -2446,13 +3158,13 @@ am_hal_iom_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, { if ( ui32Options & AM_HAL_IOM_RAW ) { - am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, (uint8_t *)pui32Data, 0, false, (ui32Options & AM_HAL_IOM_NO_STOP)); } else { - am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, (uint8_t *)pui32Data, ((ui32Options & 0xFF00) >> 8), true, @@ -2460,15 +3172,20 @@ am_hal_iom_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, } // - // Return. + // Return. convert i2c bb retCode // - return; + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; + return ui32Status; } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big."); + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Check to see if queues have been enabled. If they are, we'll actually @@ -2479,27 +3196,32 @@ am_hal_iom_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, // // If the queue is on, go ahead and add this transaction to the queue. // - am_hal_iom_queue_i2c_write(ui32Module, ui32BusAddress, pui32Data, + ui32Status = am_hal_iom_queue_i2c_write(ui32Module, ui32BusAddress, pui32Data, ui32NumBytes, ui32Options, 0); - // - // Wait until the transaction actually clears. - // - am_hal_iom_queue_flush(ui32Module); + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } // // At this point, we've completed the transaction, and we can return. // - return; } else { // // Otherwise, we'll just do a polled transaction. // - am_hal_iom_i2c_write_nq(ui32Module, ui32BusAddress, pui32Data, + ui32Status = am_hal_iom_i2c_write_nq(ui32Module, ui32BusAddress, pui32Data, ui32NumBytes, ui32Options); } + return ui32Status; } //***************************************************************************** @@ -2530,23 +3252,35 @@ am_hal_iom_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, //! into 32-bit words, which are then placed into the \e pui32Data array. Only //! the first \e ui32NumBytes bytes in this array will contain valid data. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options) { + am_hal_iom_status_e ui32Status; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; // // Validate parameters // if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Redirect to the bit-bang interface if the module number matches the @@ -2556,13 +3290,13 @@ am_hal_iom_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, { if ( ui32Options & AM_HAL_IOM_RAW ) { - am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, (uint8_t *)pui32Data, 0, false, (ui32Options & AM_HAL_IOM_NO_STOP)); } else { - am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, (uint8_t *)pui32Data, ((ui32Options & 0xFF00) >> 8), true, @@ -2570,15 +3304,20 @@ am_hal_iom_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, } // - // Return. + // Return. convert i2c bb retCode // - return; + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; + return ui32Status; } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big."); + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } // // Check to see if queues have been enabled. If they are, we'll actually @@ -2589,27 +3328,32 @@ am_hal_iom_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, // // If the queue is on, go ahead and add this transaction to the queue. // - am_hal_iom_queue_i2c_read(ui32Module, ui32BusAddress, pui32Data, + ui32Status = am_hal_iom_queue_i2c_read(ui32Module, ui32BusAddress, pui32Data, ui32NumBytes, ui32Options, 0); - // - // Wait until the transaction actually clears. - // - am_hal_iom_queue_flush(ui32Module); + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Wait until the transaction actually clears. + // + am_hal_iom_queue_flush(ui32Module); + // g_iom_error_status gets set in the isr handling + ui32Status = g_iom_error_status[ui32Module]; + } // // At this point, we've completed the transaction, and we can return. // - return; } else { // // Otherwise, just perform a polled transaction. // - am_hal_iom_i2c_read_nq(ui32Module, ui32BusAddress, pui32Data, + ui32Status = am_hal_iom_i2c_read_nq(ui32Module, ui32BusAddress, pui32Data, ui32NumBytes, ui32Options); } + return ui32Status; } //***************************************************************************** @@ -2642,27 +3386,42 @@ am_hal_iom_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, //! last word with bytes of any value. The IOM hardware will only read the //! first \e ui32NumBytes in the \e pui32Data array. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. Note that +//! successful execution for non-blocking call only means the transaction was +//! successfully initiated. The status of the transaction is not known till the +//! callback is called on completion // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { + am_hal_iom_status_e ui32Status; uint32_t ui32TransferSize; uint32_t ui32MaxFifoSize; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; // // Validate parameters // if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Redirect to the bit-bang interface if the module number matches the @@ -2670,21 +3429,27 @@ am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, // if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE ) { + // Reset the error status for non-blocking transfer + g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; if ( ui32Options & AM_HAL_IOM_RAW ) { - am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, (uint8_t *)pui32Data, 0, false, (ui32Options & AM_HAL_IOM_NO_STOP)); } else { - am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_send(ui32BusAddress << 1, ui32NumBytes, (uint8_t *)pui32Data, ((ui32Options & 0xFF00) >> 8), true, (ui32Options & AM_HAL_IOM_NO_STOP)); } + // + // Return. convert i2c bb retCode + // + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; // // The I2C bit-bang interface is actually a blocking transfer, and it // doesn't trigger the interrupt handler, so we have to call the @@ -2694,16 +3459,17 @@ am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, { pfnCallback(); } - // - // Return. - // - return; + return ui32Status; } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big."); + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } ui32MaxFifoSize = ((0 == AM_BFRn(IOMSTR, ui32Module, CFG, FULLDUP)) ? AM_HAL_IOM_MAX_FIFO_SIZE : AM_HAL_IOM_MAX_FIFO_SIZE / 2); @@ -2714,21 +3480,13 @@ am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, ui32TransferSize = (ui32NumBytes <= ui32MaxFifoSize ? ui32NumBytes : ui32MaxFifoSize); - // - // Wait until any earlier transactions have completed, and then write our - // first word to the fifo. - // - am_hal_iom_poll_complete(ui32Module); - // Need to mark IOM busy to avoid another transaction to be scheduled. // This is to take care of a race condition in Queue mode, where the IDLE // set is not a guarantee that the CMDCMP has been received g_bIomBusy[ui32Module] = true; - // - // Clear CMDCMP status - // - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; if ( am_hal_iom_fifo_write(ui32Module, pui32Data, ui32TransferSize) > 0 ) { @@ -2750,9 +3508,14 @@ am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, // // Start the write on the bus. // - am_hal_iom_i2c_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32BusAddress, + ui32Status = am_hal_iom_i2c_cmd_run(AM_HAL_IOM_WRITE, ui32Module, ui32BusAddress, ui32NumBytes, ui32Options); + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } } + return ui32Status; } //***************************************************************************** @@ -2782,24 +3545,39 @@ am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, //! into 32-bit words, which are then placed into the \e pui32Data array. Only //! the first \e ui32NumBytes bytes in this array will contain valid data. //! -//! @return None. +//! @return returns AM_HAL_IOM_SUCCESS on successful execution. Note that +//! successful execution for non-blocking call only means the transaction was +//! successfully initiated. The status of the transaction is not known till the +//! callback is called on completion // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_i2c_read_nb(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { + am_hal_iom_status_e ui32Status; + am_hal_i2c_bit_bang_enum_e i2cBBStatus; // // Validate parameters // if ( ui32Module > AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // + // Wait until the bus is idle + // + am_hal_iom_poll_complete(ui32Module); + + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if (ui32NumBytes == 0) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Redirect to the bit-bang interface if the module number matches the @@ -2807,21 +3585,27 @@ am_hal_iom_i2c_read_nb(uint32_t ui32Module, uint32_t ui32BusAddress, // if ( ui32Module == AM_HAL_IOM_I2CBB_MODULE ) { + // Reset the error status for non-blocking transfer + g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; if ( ui32Options & AM_HAL_IOM_RAW ) { - am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, (uint8_t *)pui32Data, 0, false, (ui32Options & AM_HAL_IOM_NO_STOP)); } else { - am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, + i2cBBStatus = am_hal_i2c_bit_bang_receive((ui32BusAddress << 1) | 1, ui32NumBytes, (uint8_t *)pui32Data, ((ui32Options & 0xFF00) >> 8), true, (ui32Options & AM_HAL_IOM_NO_STOP)); } + // + // Return. convert i2c bb retCode + // + g_iom_error_status[ui32Module] = ui32Status = i2c_bb_errmap[i2cBBStatus]; // // The I2C bit-bang interface is actually a blocking transfer, and it // doesn't trigger the interrupt handler, so we have to call the @@ -2832,33 +3616,26 @@ am_hal_iom_i2c_read_nb(uint32_t ui32Module, uint32_t ui32BusAddress, pfnCallback(); } - // - // Return. - // - return; + return ui32Status; } // // Make sure the transfer isn't too long for the hardware to support. // - am_hal_debug_assert_msg(ui32NumBytes < 256, "I2C transfer too big."); + if (ui32NumBytes >= 256) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; + } - // - // Wait until the bus is idle - // - am_hal_iom_poll_complete(ui32Module); - - // // Need to mark IOM busy to avoid another transaction to be scheduled. // This is to take care of a race condition in Queue mode, where the IDLE // set is not a guarantee that the CMDCMP has been received // g_bIomBusy[ui32Module] = true; - // - // Clear CMDCMP status - // - AM_BFWn(IOMSTR, ui32Module, INTCLR, CMDCMP, 1); + // Clear interrupts + AM_REGn(IOMSTR, ui32Module, INTCLR) = AM_HAL_IOM_INT_ALL; // // Prepare the global IOM buffer structure. @@ -2871,8 +3648,13 @@ am_hal_iom_i2c_read_nb(uint32_t ui32Module, uint32_t ui32BusAddress, // // Start the read transaction on the bus. // - am_hal_iom_i2c_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32BusAddress, + ui32Status = am_hal_iom_i2c_cmd_run(AM_HAL_IOM_READ, ui32Module, ui32BusAddress, ui32NumBytes, ui32Options); + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } + return ui32Status; } //***************************************************************************** @@ -2887,28 +3669,32 @@ am_hal_iom_i2c_read_nb(uint32_t ui32Module, uint32_t ui32BusAddress, //! @param ui32Options - Additional I2C options to apply to this command. //! //! This function may be used along with am_hal_iom_fifo_write and -//! am_hal_iom_fifo_read to perform more complex I2C reads and writes. This -//! function +//! am_hal_iom_fifo_read to perform more complex I2C reads and writes. +//! This function has additional logic to make sure SCL is high before a new +//! transaction is initiated. //! -//! @return None. +//! @return 0 on success // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_i2c_cmd_run(uint32_t ui32Operation, uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t ui32NumBytes, uint32_t ui32Options) { uint32_t ui32Command; + am_hal_iom_status_e ui32Status = AM_HAL_IOM_SUCCESS; // // Validate parameters // if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + if (ui32NumBytes == 0) + { + return AM_HAL_IOM_ERR_INVALID_PARAM; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Start building the command from the operation parameter. @@ -2933,9 +3719,20 @@ am_hal_iom_i2c_cmd_run(uint32_t ui32Operation, uint32_t ui32Module, ui32Command |= (ui32Options & 0x5C00FF00); // - // Write the complete command word to the IOM command register. + // Wait for SCL to be high before initiating a new transaction + // This is to ensure clock hi time specs are not violated in case slave did + // clock stretching in previous transaction // - AM_REGn(IOMSTR, ui32Module, CMD) = ui32Command; + ui32Status = internal_iom_wait_i2c_scl_hi(ui32Module); + + if (ui32Status == AM_HAL_IOM_SUCCESS) + { + // + // Write the complete command word to the IOM command register. + // + AM_REGn(IOMSTR, ui32Module, CMD) = ui32Command; + } + return ui32Status; } //***************************************************************************** @@ -3099,9 +3896,13 @@ am_hal_iom_fifo_read(uint32_t ui32Module, uint32_t *pui32Data, // // Make sure we check the number of bytes we're reading from the FIFO. + // This doesn't make sense for Full-Duplex operations. // - am_hal_debug_assert_msg((am_hal_iom_fifo_full_slots(ui32Module) >= ui32NumBytes), + if ( AM_REG_IOMSTR_CFG_FULLDUP_NORMAL == (AM_REGn(IOMSTR, ui32Module, CFG) & AM_REG_IOMSTR_CFG_FULLDUP_M) ) + { + am_hal_debug_assert_msg((am_hal_iom_fifo_full_slots(ui32Module) >= ui32NumBytes), "The fifo doesn't contain the requested number of bytes."); + } // // Figure out how many whole words we're reading from the fifo, and how @@ -3270,35 +4071,20 @@ am_hal_iom_status_get(uint32_t ui32Module) //! @param ui32Module IOM instance to check the status of. //! //! This function returns status indicating whether the IOM has incurred any -//! errors or not. +//! errors or not for previous operation. +//! This function can be called when the callback is invoked to determine the +//! status of the transaction just completed. +//! This function can also be called after a blocking call, though it would +//! return the same status as returned from the call itself +//! This function should not be called for an ongoing transaction, and the +//! result of such operation is indeterministic //! -//! @return 0 if all is well. -//! Otherwise error status as a bitmask of: -//! AM_HAL_IOM_ERR_INVALID_MODULE -//! AM_HAL_IOM_INT_ARB Another master initiated an operation -//! simultaenously and the IOM lost. Or -//! the IOM started an operation but found -//! SDA already low. -//! AM_HAL_IOM_INT_START A START from another master detected. -//! SW must wait for STOP before continuing. -//! AM_HAL_IOM_INT_ICMD Attempt to issue a CMD while another -//! CMD was already in progress, or issue a -//! non-zero-len write CMD with empty FIFO. -//! AM_HAL_IOM_INT_IACC Attempt to read the FIFO on a write. Or -//! an attempt to write the FIFO on a read. -//! AM_HAL_IOM_INT_NAK Expected ACK from slave not received. -//! AM_HAL_IOM_INT_FOVFL Attempt to write the FIFO while full -//! (FIFOSIZ > 124). -//! AM_HAL_IOM_INT_FUNDFL Attempt to read FIFO when empty (that is -//! FIFOSIZ < 4). -//! Note - see the datasheet text for full explanations of the INT errs. +//! @return AM_HAL_IOM_SUCCESS if all is well. // //***************************************************************************** -uint32_t +am_hal_iom_status_e am_hal_iom_error_status_get(uint32_t ui32Module) { - uint32_t ui32intstat = 0; - // // Validate parameters // @@ -3310,27 +4096,7 @@ am_hal_iom_error_status_get(uint32_t ui32Module) return AM_HAL_IOM_ERR_INVALID_MODULE; } - if ( AM_REGn(IOMSTR, ui32Module, STATUS) & AM_REG_IOMSTR_STATUS_ERR_ERROR ) - { - // - // The IOM is currently indicating an error condition. - // Let's figure out what is going on. - // - ui32intstat = AM_REGn(IOMSTR, ui32Module, INTSTAT); - - // - // Filter out non-error bits. - // - ui32intstat &= AM_REG_IOMSTR_INTSTAT_ARB_M | - AM_REG_IOMSTR_INTSTAT_START_M | - AM_REG_IOMSTR_INTSTAT_ICMD_M | - AM_REG_IOMSTR_INTSTAT_IACC_M | - AM_REG_IOMSTR_INTSTAT_NAK_M | - AM_REG_IOMSTR_INTSTAT_FOVFL_M | - AM_REG_IOMSTR_INTSTAT_FUNDFL_M; - } - - return ui32intstat; + return (g_iom_error_status[ui32Module]); } //***************************************************************************** @@ -3366,6 +4132,9 @@ am_hal_iom_int_service(uint32_t ui32Module, uint32_t ui32Status) // psBuffer = &g_psIOMBuffers[ui32Module]; + // Keep accumulating any error indications + // This is to account for the case if the error indication comes before CMDCMP + g_iom_error_status[ui32Module] |= ui32Status; // // Figure out what type of interrupt this was. // @@ -3404,6 +4173,7 @@ am_hal_iom_int_service(uint32_t ui32Module, uint32_t ui32Status) // psBuffer->ui32State = BUFFER_IDLE; + g_iom_error_status[ui32Module] = internal_iom_get_int_err(ui32Module, g_iom_error_status[ui32Module]); // // If we have a callback, call it now. // @@ -3621,7 +4391,7 @@ am_hal_iom_queue_length_get(uint32_t ui32Module) void am_hal_iom_queue_start_next_msg(uint32_t ui32Module) { - am_hal_iom_queue_entry_t sIOMTransaction = {0}; + am_hal_iom_queue_entry_t sIOMTransaction = {0}; uint32_t ui32ChipSelect; uint32_t *pui32Data; @@ -3629,6 +4399,7 @@ am_hal_iom_queue_start_next_msg(uint32_t ui32Module) uint32_t ui32Options; am_hal_iom_callback_t pfnCallback; + am_hal_iom_status_e ui32Status = AM_HAL_IOM_SUCCESS; uint32_t ui32Critical; // @@ -3665,22 +4436,22 @@ am_hal_iom_queue_start_next_msg(uint32_t ui32Module) switch ( sIOMTransaction.ui32Operation ) { case AM_HAL_IOM_QUEUE_SPI_WRITE: - am_hal_iom_spi_write_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_spi_write_nb(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, pfnCallback); break; case AM_HAL_IOM_QUEUE_SPI_READ: - am_hal_iom_spi_read_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_spi_read_nb(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, pfnCallback); break; case AM_HAL_IOM_QUEUE_I2C_WRITE: - am_hal_iom_i2c_write_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_i2c_write_nb(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, pfnCallback); break; case AM_HAL_IOM_QUEUE_I2C_READ: - am_hal_iom_i2c_read_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_i2c_read_nb(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, pfnCallback); break; } @@ -3690,6 +4461,14 @@ am_hal_iom_queue_start_next_msg(uint32_t ui32Module) // Exit the critical section. // am_hal_interrupt_master_set(ui32Critical); + + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + // Preserve the error + g_iom_error_status[ui32Module] = ui32Status; + // Call the respective callback + pfnCallback(); + } } //***************************************************************************** @@ -3726,22 +4505,28 @@ am_hal_iom_queue_start_next_msg(uint32_t ui32Module) //! first \e ui32NumBytes in the \e pui8Data array. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { uint32_t ui32Critical; + am_hal_iom_status_e ui32Status; // // Validate parameters // if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if ( ui32NumBytes == 0 ) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Start a critical section. @@ -3761,7 +4546,7 @@ am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, // // Send the packet. // - am_hal_iom_spi_write_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_spi_write_nb(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, pfnCallback); } else @@ -3787,17 +4572,19 @@ am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, // // Didn't have enough memory. // - am_hal_debug_assert_msg(0, - "The IOM queue is full. Allocate more" - "memory to the IOM queue, or allow it more" - "time to empty between transactions."); + ui32Status = AM_HAL_IOM_ERR_RESOURCE_ERR; } } + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } // // Exit the critical section. // am_hal_interrupt_master_set(ui32Critical); + return ui32Status; } //***************************************************************************** @@ -3834,22 +4621,28 @@ am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, //! first \e ui32NumBytes in the \e pui8Data array. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { uint32_t ui32Critical; + am_hal_iom_status_e ui32Status; // // Validate parameters // if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if ( ui32NumBytes == 0 ) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // Start a critical section. // @@ -3868,7 +4661,7 @@ am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, // // Send the packet. // - am_hal_iom_spi_read_nb(ui32Module, ui32ChipSelect, pui32Data, + ui32Status = am_hal_iom_spi_read_nb(ui32Module, ui32ChipSelect, pui32Data, ui32NumBytes, ui32Options, pfnCallback); } else @@ -3894,17 +4687,19 @@ am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, // // Didn't have enough memory. // - am_hal_debug_assert_msg(0, - "The IOM queue is full. Allocate more" - "memory to the IOM queue, or allow it more" - "time to empty between transactions."); + ui32Status = AM_HAL_IOM_ERR_RESOURCE_ERR; } } + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } // // Exit the critical section. // am_hal_interrupt_master_set(ui32Critical); + return ui32Status; } //***************************************************************************** @@ -3941,11 +4736,12 @@ am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, //! first \e ui32NumBytes in the \e pui8Data array. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { + am_hal_iom_status_e ui32Status; uint32_t ui32Critical; // @@ -3953,10 +4749,15 @@ am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, // if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if ( ui32NumBytes == 0 ) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Start a critical section. @@ -3976,7 +4777,7 @@ am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, // // Send the packet. // - am_hal_iom_i2c_write_nb(ui32Module, ui32BusAddress, pui32Data, + ui32Status = am_hal_iom_i2c_write_nb(ui32Module, ui32BusAddress, pui32Data, ui32NumBytes, ui32Options, pfnCallback); } else @@ -4002,17 +4803,19 @@ am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, // // Didn't have enough memory. // - am_hal_debug_assert_msg(0, - "The IOM queue is full. Allocate more" - "memory to the IOM queue, or allow it more" - "time to empty between transactions."); + ui32Status = AM_HAL_IOM_ERR_RESOURCE_ERR; } } + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } // // Exit the critical section. // am_hal_interrupt_master_set(ui32Critical); + return ui32Status; } //***************************************************************************** @@ -4049,22 +4852,28 @@ am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, //! first \e ui32NumBytes in the \e pui8Data array. // //***************************************************************************** -void +am_hal_iom_status_e am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback) { uint32_t ui32Critical; + am_hal_iom_status_e ui32Status; // // Validate parameters // if ( ui32Module >= AM_REG_IOMSTR_NUM_MODULES ) { - return; + return AM_HAL_IOM_ERR_INVALID_MODULE; + } + // Reset the error status + ui32Status = g_iom_error_status[ui32Module] = AM_HAL_IOM_SUCCESS; + if ( ui32NumBytes == 0 ) + { + g_iom_error_status[ui32Module] = ui32Status = AM_HAL_IOM_ERR_INVALID_PARAM; + return ui32Status; } - am_hal_debug_assert_msg(ui32NumBytes > 0, - "Trying to do a 0 byte transaction"); // // Start a critical section. @@ -4084,7 +4893,7 @@ am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, // // Send the packet. // - am_hal_iom_i2c_read_nb(ui32Module, ui32BusAddress, pui32Data, + ui32Status = am_hal_iom_i2c_read_nb(ui32Module, ui32BusAddress, pui32Data, ui32NumBytes, ui32Options, pfnCallback); } else @@ -4110,16 +4919,19 @@ am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, // // Didn't have enough memory. // - am_hal_debug_assert_msg(0, "The IOM queue is full. Allocate more" - "memory to the IOM queue, or allow it more" - "time to empty between transactions."); + ui32Status = AM_HAL_IOM_ERR_RESOURCE_ERR; } } + if (ui32Status != AM_HAL_IOM_SUCCESS) + { + g_iom_error_status[ui32Module] = ui32Status; + } // // Exit the critical section. // am_hal_interrupt_master_set(ui32Critical); + return ui32Status; } //***************************************************************************** @@ -4222,16 +5034,17 @@ am_hal_iom_sleeping_queue_flush(uint32_t ui32Module) //! ui32Status = am_hal_iom_int_status(0, true); //! //! // +//! // Clear the interrupts. This should be done before calling service routine +//! // as otherwise we may lose re-triggered interrupts +//! // +//! am_hal_iom_int_clear(ui32Status); +//! +//! // //! // Fill or empty the FIFO, and either continue the current operation or //! // start the next one in the queue. If there was a callback, it will be //! // called here. //! // //! am_hal_iom_queue_service(0, ui32Status); -//! -//! // -//! // Clear the interrupts before leaving the ISR. -//! // -//! am_hal_iom_int_clear(ui32Status); //! } //! @endcode //! diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_iom.h b/bsp/apollo2/libraries/drivers/hal/am_hal_iom.h index e5a450f15c..88cb34641e 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_iom.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_iom.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -79,11 +79,13 @@ #define AM_HAL_IOM_2MHZ 2000000 #define AM_HAL_IOM_1_5MHZ 1500000 #define AM_HAL_IOM_1MHZ 1000000 +#define AM_HAL_IOM_800KHZ 800000 #define AM_HAL_IOM_750KHZ 750000 #define AM_HAL_IOM_500KHZ 500000 #define AM_HAL_IOM_400KHZ 400000 #define AM_HAL_IOM_375KHZ 375000 #define AM_HAL_IOM_250KHZ 250000 +#define AM_HAL_IOM_200KHZ 200000 #define AM_HAL_IOM_125KHZ 125000 #define AM_HAL_IOM_100KHZ 100000 #define AM_HAL_IOM_50KHZ 50000 @@ -176,18 +178,30 @@ #define AM_HAL_IOM_INT_FUNDFL AM_REG_IOMSTR_INTEN_FUNDFL_M #define AM_HAL_IOM_INT_THR AM_REG_IOMSTR_INTEN_THR_M #define AM_HAL_IOM_INT_CMDCMP AM_REG_IOMSTR_INTEN_CMDCMP_M -//! @} -//***************************************************************************** -// -//! @name IOM function errors -//! @brief Return values for IOM HAL function errors, such as with the function -//! am_hal_iom_error_status_get(). -//! -//! @{ -// -//***************************************************************************** -#define AM_HAL_IOM_ERR_INVALID_MODULE (1 << 30) +#define AM_HAL_IOM_INT_ALL ( \ + AM_HAL_IOM_INT_ARB | \ + AM_HAL_IOM_INT_STOP | \ + AM_HAL_IOM_INT_START | \ + AM_HAL_IOM_INT_ICMD | \ + AM_HAL_IOM_INT_IACC | \ + AM_HAL_IOM_INT_WTLEN | \ + AM_HAL_IOM_INT_NAK | \ + AM_HAL_IOM_INT_FOVFL | \ + AM_HAL_IOM_INT_FUNDFL | \ + AM_HAL_IOM_INT_THR | \ + AM_HAL_IOM_INT_CMDCMP) + +#define AM_HAL_IOM_INT_SWERR ( \ + AM_HAL_IOM_INT_ICMD | \ + AM_HAL_IOM_INT_FOVFL | \ + AM_HAL_IOM_INT_FUNDFL | \ + AM_HAL_IOM_INT_IACC) + +#define AM_HAL_IOM_INT_I2CARBERR ( \ + AM_HAL_IOM_INT_ARB | \ + AM_HAL_IOM_INT_START | \ + AM_HAL_IOM_INT_STOP) //! @} //***************************************************************************** @@ -204,6 +218,31 @@ #define AM_HAL_IOM_I2CBB_MODULE AM_REG_IOMSTR_NUM_MODULES //! @} +//***************************************************************************** +// +//! @name IOM Return Codes +//! @brief Enum definitions for defining return values for IOM APIs +//! +//! This enum defines possible values for non-void IOM APIs +//! +//! @{ +// +//***************************************************************************** +typedef enum +{ + AM_HAL_IOM_SUCCESS = 0, + AM_HAL_IOM_ERR_TIMEOUT, + AM_HAL_IOM_ERR_INVALID_MODULE, + AM_HAL_IOM_ERR_INVALID_PARAM, + AM_HAL_IOM_ERR_INVALID_CFG, + AM_HAL_IOM_ERR_INVALID_OPER, + AM_HAL_IOM_ERR_I2C_NAK, + AM_HAL_IOM_ERR_I2C_ARB, + AM_HAL_IOM_ERR_RESOURCE_ERR, +} am_hal_iom_status_e ; + +//! @} + //***************************************************************************** // //! @brief Union type for a word-aligned, byte-addressable array. @@ -271,7 +310,7 @@ typedef struct //! Select the SPI clock polarity (unused in I2C mode). // bool bSPOL; - + // //! @brief Select the FIFO write threshold. //! @@ -404,7 +443,11 @@ am_hal_iom_pwrsave_t; // //***************************************************************************** extern am_hal_iom_pwrsave_t am_hal_iom_pwrsave[AM_REG_IOMSTR_NUM_MODULES]; -extern uint32_t g_iom_error_status; + +#ifdef __cplusplus +extern "C" +{ +#endif //***************************************************************************** // @@ -420,23 +463,30 @@ extern void am_hal_iom_config(uint32_t ui32Module, extern uint32_t am_hal_iom_frequency_get(uint32_t ui32Module); extern void am_hal_iom_enable(uint32_t ui32Module); extern void am_hal_iom_disable(uint32_t ui32Module); -extern void am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern void am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern uint32_t am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_spi_fullduplex(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32TxData, uint32_t *pui32RxData, + uint32_t ui32NumBytes, uint32_t ui32Options); + +extern am_hal_iom_status_e am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern uint32_t am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern void am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_spi_fullduplex_nq(uint32_t ui32Module, uint32_t ui32ChipSelect, + uint32_t *pui32TxData, uint32_t *pui32RxData, + uint32_t ui32NumBytes, uint32_t ui32Options); +extern am_hal_iom_status_e am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); -extern uint32_t am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); @@ -445,39 +495,39 @@ extern void am_hal_iom_spi_cmd_run(uint32_t ui32Operation, uint32_t ui32ChipSelect, uint32_t ui32NumBytes, uint32_t ui32Options); -extern void am_hal_iom_i2c_write(uint32_t ui32Module, +extern am_hal_iom_status_e am_hal_iom_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern void am_hal_iom_i2c_read(uint32_t ui32Module, +extern am_hal_iom_status_e am_hal_iom_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern uint32_t am_hal_iom_i2c_write_nq(uint32_t ui32Module, +extern am_hal_iom_status_e am_hal_iom_i2c_write_nq(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern uint32_t am_hal_iom_i2c_read_nq(uint32_t ui32Module, +extern am_hal_iom_status_e am_hal_iom_i2c_read_nq(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options); -extern void am_hal_iom_i2c_write_nb(uint32_t ui32Module, +extern am_hal_iom_status_e am_hal_iom_i2c_write_nb(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); -extern void am_hal_iom_i2c_read_nb(uint32_t ui32Module, +extern am_hal_iom_status_e am_hal_iom_i2c_read_nb(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); -extern void am_hal_iom_i2c_cmd_run(uint32_t ui32Operation, +extern am_hal_iom_status_e am_hal_iom_i2c_cmd_run(uint32_t ui32Operation, uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t ui32NumBytes, @@ -485,7 +535,7 @@ extern void am_hal_iom_i2c_cmd_run(uint32_t ui32Operation, extern void am_hal_iom_command_repeat_set(uint32_t ui32Module, uint32_t ui32CmdCount); extern uint32_t am_hal_iom_status_get(uint32_t ui32Module); -extern uint32_t am_hal_iom_error_status_get(uint32_t ui32Module); +extern am_hal_iom_status_e am_hal_iom_error_status_get(uint32_t ui32Module); extern uint32_t am_hal_iom_fifo_write(uint32_t ui32Module, uint32_t *pui32Data, uint32_t ui32NumBytes); extern uint32_t am_hal_iom_fifo_read(uint32_t ui32Module, uint32_t *pui32Data, @@ -505,19 +555,19 @@ extern void am_hal_iom_queue_init(uint32_t ui32ModuleNum, uint32_t ui32QueueMemSize); extern uint32_t am_hal_iom_queue_length_get(uint32_t ui32Module); extern void am_hal_iom_sleeping_queue_flush(uint32_t ui32Module); -extern void am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); -extern void am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, +extern am_hal_iom_status_e am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); -extern void am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, +extern am_hal_iom_status_e am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); -extern void am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, +extern am_hal_iom_status_e am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress, uint32_t *pui32Data, uint32_t ui32NumBytes, uint32_t ui32Options, am_hal_iom_callback_t pfnCallback); @@ -533,7 +583,6 @@ extern void am_hal_iom_queue_service(uint32_t ui32Module, uint32_t ui32Statu void am_iomaster##x##_isr(void) \ { \ uint32_t ui32IntStatus; \ - g_iom_error_status = am_hal_iom_error_status_get(x); \ ui32IntStatus = am_hal_iom_int_status_get(x, false); \ am_hal_iom_int_clear(x, ui32IntStatus); \ am_hal_iom_queue_service(x, ui32IntStatus); \ @@ -543,12 +592,15 @@ void am_iomaster##x##_isr(void) \ void am_iomaster##x##_isr(void) \ { \ uint32_t ui32IntStatus; \ - g_iom_error_status = am_hal_iom_error_status_get(x); \ ui32IntStatus = am_hal_iom_int_status_get(x, false); \ am_hal_iom_int_clear(x, ui32IntStatus); \ am_hal_iom_int_service(x, ui32IntStatus); \ } +#ifdef __cplusplus +} +#endif + #endif // AM_HAL_IOM_H //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ios.c b/bsp/apollo2/libraries/drivers/hal/am_hal_ios.c index 0f34aa6efb..921d6eeade 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_ios.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ios.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -61,6 +61,7 @@ typedef struct volatile uint32_t ui32WriteIndex; volatile uint32_t ui32ReadIndex; volatile uint32_t ui32Length; + uint32_t ui32FifoInc; uint32_t ui32Capacity; } am_hal_ios_buffer_t; @@ -103,6 +104,23 @@ uint8_t *g_pui8FIFOPtr = (uint8_t *) REG_IOSLAVE_BASEADDR; uint8_t g_ui32HwFifoSize = 0; uint32_t g_ui32FifoBaseOffset = 0; +//***************************************************************************** +// +// Checks to see if this processor is a Rev B2 device. +// +// This is needed to disable SHELBY-1654 workaround. +// +//***************************************************************************** +bool +isRevB2(void) +{ + // + // Check to make sure the major rev is B and the minor rev is 2. + // + return ( (AM_REG(MCUCTRL, CHIPREV) & 0xFF) == \ + (AM_REG_MCUCTRL_CHIPREV_REVMAJ_B | (AM_REG_MCUCTRL_CHIPREV_REVMIN_REV0 + 2)) ); +} + //***************************************************************************** // //! @brief Enable the IOS in the power control block. @@ -957,7 +975,10 @@ am_hal_ios_fifo_service(uint32_t ui32Status) } } } - resync_fifoSize(); + if (!isRevB2()) + { + resync_fifoSize(); + } // // Need to retake the FIFO space, after Threshold interrupt has been reenabled @@ -1041,7 +1062,10 @@ am_hal_ios_fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes) ui32NumBytes -= ui32FIFOSpace; pui8Data += ui32FIFOSpace; }; - resync_fifoSize(); + if (!isRevB2()) + { + resync_fifoSize(); + } } // @@ -1102,6 +1126,8 @@ am_hal_ios_fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes) } } + // Number of bytes written + g_sSRAMBuffer.ui32FifoInc += totalBytes - ui32NumBytes; return (totalBytes - ui32NumBytes); } @@ -1114,7 +1140,7 @@ am_hal_ios_fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes) //! //! This function will write data from the caller-provided array to the IOS //! LRAM FIFO. This simple routine does not use SRAM buffering for large -//! messages. +//! messages. This function also updates the FIFOCTR. //! //! The maximum message size for the IO Slave is 128 bytes. //! @@ -1140,6 +1166,8 @@ am_hal_ios_fifo_write_simple(uint8_t *pui8Data, uint32_t ui32NumBytes) if ( ui32NumBytes <= ui32FIFOSpace ) { fifo_write(pui8Data, ui32NumBytes); + // Write FIFOINC + AM_BFW(IOSLAVE, FIFOINC, FIFOINC, ui32NumBytes); } else { @@ -1209,6 +1237,7 @@ am_hal_ios_buffer_init(am_hal_ios_buffer_t *psBuffer, void *pvArray, psBuffer->ui32ReadIndex = 0; psBuffer->ui32Length = 0; psBuffer->ui32Capacity = ui32Bytes; + psBuffer->ui32FifoInc = 0; psBuffer->pui8Data = (uint8_t *)pvArray; } @@ -1273,12 +1302,19 @@ am_hal_ios_fifo_buffer_init(uint8_t *pui8Buffer, uint32_t ui32NumBytes) //! @brief Update the FIFOCTR to inform host of available data to read. //! //! This function allows the application to indicate to HAL when it is safe to -//! update the FIFOCTR. +//! update the FIFOCTR. This function needs to be used in conjunction with +//! am_hal_ios_fifo_write(), which itself does not update the FIFOCTR //! +//! CAUTION: //! Application needs to implement some sort of //! synchronization with the host to make sure host is not reading FIFOCTR while //! it is being updated by the MCU, since the FIFOCTR read over -//! IO is not an atomic operation. +//! IO is not an atomic operation. Otherwise, some other logic could be implemented +//! by the host to detect and disregard transient values of FIFOCTR (e.g. multiple +//! reads till it gets a stable value). +//! For Pre-B2 parts, it is necessary to have this synchronization guarantee that +//! Host is not doing any READ operation - be it for FIFOCTR or FIFO itself when +//! this call is made, as otherwise the FIFOCTR value may get corrupted. //! //! //! @return None. @@ -1287,11 +1323,9 @@ am_hal_ios_fifo_buffer_init(uint8_t *pui8Buffer, uint32_t ui32NumBytes) void am_hal_ios_update_fifoctr(void) { - uint32_t ui32Val; - // Determine the available data - ui32Val = am_hal_ios_fifo_space_used(); - // Update FIFOCTR - AM_BFW(IOSLAVE, FIFOCTR, FIFOCTR, ui32Val); + // Write FIFOINC + AM_BFW(IOSLAVE, FIFOINC, FIFOINC, g_sSRAMBuffer.ui32FifoInc); + g_sSRAMBuffer.ui32FifoInc = 0; return; } diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ios.h b/bsp/apollo2/libraries/drivers/hal/am_hal_ios.h index b166c9c6e5..20af148d97 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_ios.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ios.h @@ -42,16 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_IOS_H #define AM_HAL_IOS_H -#ifdef __cplusplus -extern "C" -{ -#endif //***************************************************************************** // @@ -300,6 +296,10 @@ typedef struct } am_hal_ios_config_t; +#ifdef __cplusplus +extern "C" +{ +#endif //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_itm.c b/bsp/apollo2/libraries/drivers/hal/am_hal_itm.c index 0f57c0d417..8e7949edc7 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_itm.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_itm.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -56,30 +56,6 @@ // //***************************************************************************** -//***************************************************************************** -// -//! @brief Delays for a desired amount of microseconds. -//! -//! @note - This function is based on the similar function in am_util_delay.c, -//! please see that module for implementation details. It was necessary to -//! duplicate it here to avoid having to update every example to include the -//! am_util_delay.c module in its build. -//! -//! @returns None -// -//***************************************************************************** -void -am_hal_itm_delay_us(uint32_t ui32MicroSeconds) -{ - uint32_t ui32Iterations = ui32MicroSeconds * - (am_hal_clkgen_sysclk_get() / 3000000); - - // - // Call the BOOTROM cycle delay function - // - am_hal_flash_delay(ui32Iterations); -} - //***************************************************************************** // //! @brief Enables the ITM @@ -118,7 +94,7 @@ am_hal_itm_enable(void) AM_REGVAL(AM_REG_ITM_TER_O) = 0xffffffff; // - // Write to the ITM control and status register (don't enable yet). + // Write to the ITM control and status register. // AM_REGVAL(AM_REG_ITM_TCR_O) = AM_WRITE_SM(AM_REG_ITM_TCR_ATB_ID, 0x15) | @@ -129,6 +105,7 @@ am_hal_itm_enable(void) AM_WRITE_SM(AM_REG_ITM_TCR_SYNC_ENABLE, 0) | AM_WRITE_SM(AM_REG_ITM_TCR_TS_ENABLE, 0) | AM_WRITE_SM(AM_REG_ITM_TCR_ITM_ENABLE, 1); + } //***************************************************************************** @@ -203,7 +180,7 @@ am_hal_itm_not_busy(void) // // wait for 50us for the data to flush out // - am_hal_itm_delay_us(50); + am_hal_flash_delay(FLASH_CYCLES_US(50)); } //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_itm.h b/bsp/apollo2/libraries/drivers/hal/am_hal_itm.h index e747b0ab65..78f0b7a993 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_itm.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_itm.h @@ -42,18 +42,13 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_ITM_H #define AM_HAL_ITM_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // // Sync Packet Defines @@ -71,12 +66,16 @@ extern "C" #define AM_HAL_ITM_PRINT_NUM_REGS 1 extern uint32_t am_hal_itm_print_registers[AM_HAL_ITM_PRINT_NUM_REGS]; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions // //***************************************************************************** -extern void am_hal_itm_delay_us(uint32_t ui32MicroSeconds); extern void am_hal_itm_enable(void); extern void am_hal_itm_disable(void); extern void am_hal_itm_not_busy(void); diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.c b/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.c index f7b60e3c1a..3e5eeb2c59 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.h b/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.h index 6811006fd6..b93515347d 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_MCUCTRL_H #define AM_HAL_MCUCTRL_H -#ifdef __cplusplus -extern "C" -{ -#endif - // // Deprecate the am_hal_mcuctrl_bucks_enable() and disable() functions. // This functionality is now handled in pwrctrl. @@ -188,6 +183,11 @@ typedef struct } am_hal_mcuctrl_fault_t; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_otp.c b/bsp/apollo2/libraries/drivers/hal/am_hal_otp.c index 67d08448da..99ce2493b3 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_otp.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_otp.c @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #include "am_mcu_apollo.h" diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_otp.h b/bsp/apollo2/libraries/drivers/hal/am_hal_otp.h index d938e916fb..3ea13618d3 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_otp.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_otp.h @@ -38,17 +38,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_OTP_H #define AM_HAL_OTP_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // // Define some OTP values and macros. @@ -82,6 +77,11 @@ extern "C" #define AM_OTP_SRAM_LOCKOUT_S (2) #define AM_OTP_SRAM_LOCKOUT_M (0x1 << AM_OTP_SRAM_LOCKOUT_S) +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // Function prototypes diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.c b/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.c index 45acfab995..b8ca3dde5c 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.h b/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.h index a6e23d2698..77c0ad9488 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pdm.h @@ -42,13 +42,18 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_PDM_H #define AM_HAL_PDM_H +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // Macro definitions @@ -655,6 +660,10 @@ extern void am_hal_pdm_disable(void); extern uint32_t am_hal_pdm_int_status_get(bool bEnabledOnly); +#ifdef __cplusplus +} +#endif + #endif // AM_HAL_PDM_H //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pin.h b/bsp/apollo2/libraries/drivers/hal/am_hal_pin.h index 8a1068f882..0173881bae 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_pin.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pin.h @@ -41,7 +41,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -55,7 +55,7 @@ //***************************************************************************** #define AM_HAL_PIN_DIR_INPUT (AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_DIR_OUTPUT (AM_HAL_GPIO_OUT_PUSHPULL) -#define AM_HAL_PIN_DIR_OPENDRAIN (AM_HAL_GPIO_OUT_OPENDRAIN | AM_HAL_GPIO_INPEN) +#define AM_HAL_PIN_DIR_OPENDRAIN (AM_HAL_GPIO_OUT_OPENDRAIN) #define AM_HAL_PIN_DIR_3STATE (AM_HAL_GPIO_OUT_3STATE) //***************************************************************************** @@ -81,25 +81,25 @@ #define AM_HAL_PIN_0_MxSCKLB (AM_HAL_GPIO_FUNC(4)) #define AM_HAL_PIN_0_M2SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_0_MxSCLLB (AM_HAL_GPIO_FUNC(6)) -#define AM_HAL_PIN_0_M2SCL (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_0_M2SCL (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) -#define AM_HAL_PIN_1_SLSDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_1_SLSDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_1_SLMISO (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_1_UART0TX (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_1_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_1_MxMISOLB (AM_HAL_GPIO_FUNC(4)) #define AM_HAL_PIN_1_M2MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_1_MxSDALB (AM_HAL_GPIO_FUNC(6)) -#define AM_HAL_PIN_1_M2SDA (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_1_M2SDA (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) -#define AM_HAL_PIN_2_SLWIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_2_SLWIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_2_SLMOSI (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_2_UART0RX (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_2_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_2_MxMOSILB (AM_HAL_GPIO_FUNC(4)) #define AM_HAL_PIN_2_M2MOSI (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_2_MxWIR3LB (AM_HAL_GPIO_FUNC(6)) -#define AM_HAL_PIN_2_M2WIR3 (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_2_M2WIR3 (AM_HAL_GPIO_FUNC(7) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_3_UART0RTS (AM_HAL_GPIO_FUNC(0)) #define AM_HAL_PIN_3_SLnCE (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) @@ -109,7 +109,6 @@ #define AM_HAL_PIN_3_M2nCE0 (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_3_TRIG1 (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_3_I2S_WCLK (AM_HAL_GPIO_FUNC(7)) -#define AM_HAL_PIN_3_PSOURCE (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT | AM_HAL_GPIO_POWER) #define AM_HAL_PIN_4_UART0CTS (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_4_SLINT (AM_HAL_GPIO_FUNC(1)) @@ -119,17 +118,18 @@ #define AM_HAL_PIN_4_M2nCE5 (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_4_CLKOUT (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_4_32KHZ_XT (AM_HAL_GPIO_FUNC(7)) +// PSINK usage: GPIOWT=0 to activate the power switch, GPIOWT=1 to disable +#define AM_HAL_PIN_4_PSINK (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_POWER) -#define AM_HAL_PIN_5_M0SCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_5_M0SCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_5_M0SCK (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_5_UART0RTS (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_5_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_5_M0SCKLB (AM_HAL_GPIO_FUNC(4)) -#define AM_HAL_PIN_5_EXTHFA (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_5_M0SCLLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_5_M1nCE2 (AM_HAL_GPIO_FUNC(7)) -#define AM_HAL_PIN_6_M0SDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_6_M0SDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_6_M0MISO (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_6_UART0CTS (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_6_GPIO (AM_HAL_GPIO_FUNC(3)) @@ -138,7 +138,7 @@ #define AM_HAL_PIN_6_SLSDALB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_6_I2S_DAT (AM_HAL_GPIO_FUNC(7)) -#define AM_HAL_PIN_7_M0WIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_7_M0WIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_7_M0MOSI (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_7_CLKOUT (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_7_GPIO (AM_HAL_GPIO_FUNC(3)) @@ -147,7 +147,7 @@ #define AM_HAL_PIN_7_SLWIR3LB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_7_M1nCE1 (AM_HAL_GPIO_FUNC(7)) -#define AM_HAL_PIN_8_M1SCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_8_M1SCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_8_M1SCK (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_8_M0nCE4 (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_8_GPIO (AM_HAL_GPIO_FUNC(3)) @@ -156,7 +156,7 @@ #define AM_HAL_PIN_8_UART1TX (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_8_M1SCLLB (AM_HAL_GPIO_FUNC(7)) -#define AM_HAL_PIN_9_M1SDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_9_M1SDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_9_M1MISO (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_9_M0nCE5 (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_9_GPIO (AM_HAL_GPIO_FUNC(3)) @@ -165,7 +165,7 @@ #define AM_HAL_PIN_9_UART1RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_9_SLSDALB (AM_HAL_GPIO_FUNC(7)) -#define AM_HAL_PIN_10_M1WIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_10_M1WIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_10_M1MOSI (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_10_M0nCE6 (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_10_GPIO (AM_HAL_GPIO_FUNC(3)) @@ -182,7 +182,6 @@ #define AM_HAL_PIN_11_UART1CTS (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_11_UART0RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_11_PDM_DATA (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT) -#define AM_HAL_PIN_11_PSINK (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_12_ADCD0NSE9 (AM_HAL_GPIO_FUNC(0)) #define AM_HAL_PIN_12_M1nCE0 (AM_HAL_GPIO_FUNC(1)) @@ -198,7 +197,6 @@ #define AM_HAL_PIN_13_TCTB0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_13_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_13_M2nCE3 (AM_HAL_GPIO_FUNC(4)) -#define AM_HAL_PIN_13_EXTHFB (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_13_UART0RTS (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_13_UART1RX (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT) @@ -207,7 +205,6 @@ #define AM_HAL_PIN_14_UART1TX (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_14_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_14_M2nCE1 (AM_HAL_GPIO_FUNC(4)) -#define AM_HAL_PIN_14_EXTHFS (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_14_SWDCK (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_14_32KHZ_XT (AM_HAL_GPIO_FUNC(7)) @@ -216,7 +213,6 @@ #define AM_HAL_PIN_15_UART1RX (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_15_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_15_M2nCE2 (AM_HAL_GPIO_FUNC(4)) -#define AM_HAL_PIN_15_EXTXT (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_15_SWDIO (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_15_SWO (AM_HAL_GPIO_FUNC(7)) @@ -234,7 +230,6 @@ #define AM_HAL_PIN_17_TRIG1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_17_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_17_M4nCE3 (AM_HAL_GPIO_FUNC(4)) -#define AM_HAL_PIN_17_EXTLF (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_17_UART0RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_17_UART1CTS (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT) @@ -243,7 +238,6 @@ #define AM_HAL_PIN_18_TCTA1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_18_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_18_M4nCE1 (AM_HAL_GPIO_FUNC(4)) -#define AM_HAL_PIN_18_ANATEST2 (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_18_UART1TX (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_18_32KHZ_XT (AM_HAL_GPIO_FUNC(7)) @@ -252,7 +246,6 @@ #define AM_HAL_PIN_19_TCTB1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_19_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_19_TCTA1 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT) -#define AM_HAL_PIN_19_ANATEST1 (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_19_UART1RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_19_I2S_BCLK (AM_HAL_GPIO_FUNC(7)) @@ -277,6 +270,7 @@ #define AM_HAL_PIN_22_PDM_CLK (AM_HAL_GPIO_FUNC(4)) #define AM_HAL_PIN_22_TCTB1 (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_22_SWO (AM_HAL_GPIO_FUNC(7)) +// PSOURCE usage in pushpull: GPIOWT=1 to activate the power switch, GPIOWT=0 to disable #define AM_HAL_PIN_22_PSOURCE (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT | AM_HAL_GPIO_POWER) #define AM_HAL_PIN_23_UART0RX (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) @@ -299,17 +293,15 @@ #endif // defined (AM_PACKAGE_BGA) #if defined (AM_PACKAGE_BGA) -#define AM_HAL_PIN_25_EXTXT (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_25_M0nCE2 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_25_TCTA0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_25_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_25_M2SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_25_M2SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_25_M2MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_25_SLMISOLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_25_SLSDALB (AM_HAL_GPIO_FUNC(7)) #endif // defined (AM_PACKAGE_BGA) -#define AM_HAL_PIN_26_EXTLF (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_26_M0nCE3 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_26_TCTB0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_26_GPIO (AM_HAL_GPIO_FUNC(3)) @@ -319,11 +311,10 @@ #define AM_HAL_PIN_26_M3nCE0 (AM_HAL_GPIO_FUNC(7)) #if defined (AM_PACKAGE_BGA) -#define AM_HAL_PIN_27_EXTHF (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_27_M1nCE4 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_27_TCTA1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_27_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_27_M2SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_27_M2SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_27_M2SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_27_M2SCKLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_27_M2SCLLB (AM_HAL_GPIO_FUNC(7)) @@ -333,7 +324,7 @@ #define AM_HAL_PIN_28_M1nCE5 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_28_TCTB1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_28_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_28_M2WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_28_M2WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_28_M2MOSI (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_28_M5nCE3 (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_28_SLWIR3LB (AM_HAL_GPIO_FUNC(7)) @@ -353,7 +344,6 @@ #define AM_HAL_PIN_30_GPIO (AM_HAL_GPIO_FUNC(3)) #define AM_HAL_PIN_30_UART0TX (AM_HAL_GPIO_FUNC(4)) #define AM_HAL_PIN_30_UART1RTS (AM_HAL_GPIO_FUNC(5)) -#define AM_HAL_PIN_30_SWO (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_30_I2S_DAT (AM_HAL_GPIO_FUNC(7)) #endif // defined (AM_PACKAGE_BGA) @@ -433,7 +423,7 @@ #define AM_HAL_PIN_38_M1nCE3 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_38_UART0CTS (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_38_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_38_M3WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_38_M3WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_38_M3MOSI (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_38_M4nCE7 (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_38_SLWIR3LB (AM_HAL_GPIO_FUNC(7)) @@ -443,7 +433,7 @@ #define AM_HAL_PIN_39_UART1TX (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_39_CLKOUT (AM_HAL_GPIO_FUNC(2)) #define AM_HAL_PIN_39_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_39_M4SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_39_M4SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_39_M4SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_39_M4SCKLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_39_M4SCLLB (AM_HAL_GPIO_FUNC(7)) @@ -452,7 +442,7 @@ #define AM_HAL_PIN_40_UART1RX (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_40_TRIG0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_40_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_40_M4SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_40_M4SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_40_M4MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_40_SLMISOLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_40_SLSDALB (AM_HAL_GPIO_FUNC(7)) @@ -465,6 +455,7 @@ #define AM_HAL_PIN_41_M5nCE7 (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_41_M4nCE2 (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_41_UART0RTS (AM_HAL_GPIO_FUNC(7)) +// PSOURCE usage in pushpull: GPIOWT=1 to activate the power switch, GPIOWT=0 to disable #define AM_HAL_PIN_41_PSOURCE (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT | AM_HAL_GPIO_POWER) #if defined (AM_PACKAGE_BGA) @@ -472,7 +463,7 @@ #define AM_HAL_PIN_42_M0nCE0 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_42_TCTA0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_42_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_42_M3SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_42_M3SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_42_M3SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_42_M3SCKLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_42_M3SCLLB (AM_HAL_GPIO_FUNC(7)) @@ -483,7 +474,7 @@ #define AM_HAL_PIN_43_M0nCE1 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_43_TCTB0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_43_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_43_M3SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_43_M3SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_43_M3MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_43_SLMISOLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_43_SLSDALB (AM_HAL_GPIO_FUNC(7)) @@ -493,7 +484,7 @@ #define AM_HAL_PIN_44_M0nCE2 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_44_TCTA1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_44_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_44_M4WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_44_M4WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_44_M4MOSI (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_44_M5nCE6 (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_44_SLWIR3LB (AM_HAL_GPIO_FUNC(7)) @@ -506,7 +497,7 @@ #define AM_HAL_PIN_45_M4nCE3 (AM_HAL_GPIO_FUNC(4)) #define AM_HAL_PIN_45_M3nCE6 (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_45_M5nCE5 (AM_HAL_GPIO_FUNC(6)) -#define AM_HAL_PIN_45_TCTA1 (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT) +#define AM_HAL_PIN_45_SWO (AM_HAL_GPIO_FUNC(7)) #endif // defined (AM_PACKAGE_BGA) #if defined (AM_PACKAGE_BGA) @@ -524,7 +515,7 @@ #define AM_HAL_PIN_47_M0nCE5 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_47_TCTB2 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_47_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_47_M5WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE) +#define AM_HAL_PIN_47_M5WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_47_M5MOSI (AM_HAL_GPIO_FUNC(5)) #define AM_HAL_PIN_47_M4nCE5 (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_47_SLWIR3LB (AM_HAL_GPIO_FUNC(7)) @@ -533,7 +524,7 @@ #define AM_HAL_PIN_48_M0nCE6 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_48_TCTA3 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_48_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_48_M5SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_48_M5SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_48_M5SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_48_M5SCKLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_48_M5SCLLB (AM_HAL_GPIO_FUNC(7)) @@ -542,7 +533,7 @@ #define AM_HAL_PIN_49_M0nCE7 (AM_HAL_GPIO_FUNC(1)) #define AM_HAL_PIN_49_TCTB3 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_49_GPIO (AM_HAL_GPIO_FUNC(3)) -#define AM_HAL_PIN_49_M5SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN) +#define AM_HAL_PIN_49_M5SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN) #define AM_HAL_PIN_49_M5MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT) #define AM_HAL_PIN_49_SLMISOLB (AM_HAL_GPIO_FUNC(6)) #define AM_HAL_PIN_49_SLSDALB (AM_HAL_GPIO_FUNC(7)) diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.c b/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.c index cc91eeb159..b16b909308 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.h b/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.h index bc9adabf84..8068253900 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -319,6 +319,11 @@ #define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL \ AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // Function prototypes @@ -332,6 +337,10 @@ extern void am_hal_pwrctrl_bucks_enable(void); extern void am_hal_pwrctrl_bucks_disable(void); extern void am_hal_pwrctrl_low_power_init(void); +#ifdef __cplusplus +} +#endif + #endif // AM_HAL_PWRCTRL_H //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_queue.c b/bsp/apollo2/libraries/drivers/hal/am_hal_queue.c index 66a9846c29..f54b90a1e0 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_queue.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_queue.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_queue.h b/bsp/apollo2/libraries/drivers/hal/am_hal_queue.h index 11e8ace90a..8cab7dd907 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_queue.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_queue.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_QUEUE_H diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_reset.c b/bsp/apollo2/libraries/drivers/hal/am_hal_reset.c index 86d5cf10b7..19ef48dcd3 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_reset.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_reset.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_reset.h b/bsp/apollo2/libraries/drivers/hal/am_hal_reset.h index a3273dad10..5e914f4d18 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_reset.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_reset.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_RSTGEN_H diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.c b/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.c index 4630d5a117..44fccb49db 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.h b/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.h index 9304a6c67f..c49cdf25de 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_rtc.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_RTC_H #define AM_HAL_RTC_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // //! @name OSC Start and Stop @@ -149,6 +144,11 @@ typedef struct am_hal_rtc_time_struct uint32_t ui32Hundredths; }am_hal_rtc_time_t; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.c b/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.c index 0cdd706c9e..ed94beb5a1 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -136,11 +136,14 @@ am_hal_stimer_counter_clear(void) //! //! @param ui32CmprInstance is the compare register instance number (0-7). //! @param ui32Delta is the value to add to the STimer counter and load into -//! the comparator register. +//! the comparator register. It should be > 1 //! //! NOTE: There is no way to set an absolute value into a comparator register. //! Only deltas added to the STimer counter can be written to the compare //! registers. +//! CAUTION: The HAL implementation requires temporarily disabling the +//! comparison. To avoid the remote possibility of losing an interrupt +//! during that time, delta should always be set to a value greater than 1 //! //! @return None. // @@ -148,12 +151,32 @@ am_hal_stimer_counter_clear(void) void am_hal_stimer_compare_delta_set(uint32_t ui32CmprInstance, uint32_t ui32Delta) { + uint32_t cfgVal; + uint32_t ui32Critical = 0; if ( ui32CmprInstance > 7 ) { return; } + cfgVal = AM_REG(CTIMER, STCFG); + // We need to disable the compare temporarily while setting the delta value + // That leaves a corner case where we could miss the trigger if setting a very + // small delta. To avoid this, we take critical section, and we should ensure + // that delta value is at least > 1 + + // Disable the compare if already enabled, when setting the new value + AM_REG(CTIMER, STCFG) &= ~((AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << ui32CmprInstance)); + // + // Start a critical section. + // + ui32Critical = am_hal_interrupt_master_disable(); AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)) = ui32Delta; + // Restore Compare Enable bit + AM_REG(CTIMER, STCFG) |= cfgVal & (AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << ui32CmprInstance); + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32Critical); } //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.h b/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.h index bd4b09feae..5368c4af81 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_stimer.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_STIMER_H #define AM_HAL_STIMER_H -#ifdef __cplusplus -extern "C" -{ -#endif - // // Compute address of a given COMPARE or CAPTURE register. // Note - For Apollo2, the parameter n should be 0 (as only 1 stimer module @@ -204,6 +199,11 @@ am_hal_stimer_config_t; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.c b/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.c index 50e0b67915..57cd34b95d 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -731,8 +731,6 @@ am_hal_sysctrl_buck_update_complete(void) static void am_hal_sysctrl_buckA_ctimer_isr(void) { - volatile uint32_t ui32BuckTimer = g_ui32BuckTimer - 1; - // // Begin critical section. // Although a relatively long time, the following 2us delay is critically @@ -792,8 +790,6 @@ am_hal_sysctrl_buckA_ctimer_isr(void) static void am_hal_sysctrl_buckB_ctimer_isr(void) { - volatile uint32_t ui32BuckTimer = g_ui32BuckTimer - 1; - // // Begin critical section. // Although a relatively long time, the following 2us delay is critically diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.h b/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.h index 34c72b4173..17854f948b 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.h @@ -42,16 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_SYSCTRL_H #define AM_HAL_SYSCTRL_H -#ifdef __cplusplus -extern "C" -{ -#endif //***************************************************************************** // @@ -86,6 +82,10 @@ extern "C" // #define AM_HAL_SYSCTRL_BUCK_CTIMER_ZX_CONSTANT 0x01000000 // No timer, apply a constant value +#ifdef __cplusplus +extern "C" +{ +#endif //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_systick.c b/bsp/apollo2/libraries/drivers/hal/am_hal_systick.c index 3654910495..b09ee47c83 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_systick.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_systick.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_systick.h b/bsp/apollo2/libraries/drivers/hal/am_hal_systick.h index bd5e576938..8ecdf7fec2 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_systick.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_systick.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_SYSTICK_H diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.c b/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.c index 722f22fa13..151b0ce21d 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.c @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -350,7 +350,7 @@ am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig) // // Wait for 50us for the data to flush out. // - am_hal_itm_delay_us(50); + am_hal_flash_delay(FLASH_CYCLES_US(50)); } //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.h b/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.h index 9739034a18..6ef6b1f542 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_TPIU_H @@ -50,11 +50,6 @@ #include -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // // TPIU bit rate defines. @@ -165,6 +160,11 @@ typedef struct } am_hal_tpiu_config_t; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.c b/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.c index 77bde67b87..22de5e782b 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.c @@ -39,7 +39,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #include "am_mcu_apollo.h" diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.h b/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.h index b254c957a7..8879e98c83 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_ttp.h @@ -39,7 +39,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_TTP_H diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_uart.c b/bsp/apollo2/libraries/drivers/hal/am_hal_uart.c index 1a7e5aca31..4582cbb4e9 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_uart.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_uart.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_uart.h b/bsp/apollo2/libraries/drivers/hal/am_hal_uart.h index 4aab828582..b6209d112e 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_uart.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_uart.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_UART_H #define AM_HAL_UART_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // //! @name UART Interrupts @@ -270,6 +265,11 @@ am_hal_uart_pwrsave_t; //***************************************************************************** extern am_hal_uart_pwrsave_t am_hal_uart_pwrsave[AM_REG_UART_NUM_MODULES]; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.c b/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.c index 31e28855e4..37539c1d04 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.h b/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.h index a6ca991aae..cd0d81ad53 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.h @@ -42,17 +42,12 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_VCOMP_H #define AM_HAL_VCOMP_H -#ifdef __cplusplus -extern "C" -{ -#endif - //***************************************************************************** // //! @name Positive Input Selection @@ -145,6 +140,11 @@ typedef struct } am_hal_vcomp_config_t; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // // External function definitions diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.c b/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.c index 4e80113fd1..9676f973ac 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.c +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.c @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.h b/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.h index 63766fa458..b719158b8a 100644 --- a/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.h +++ b/bsp/apollo2/libraries/drivers/hal/am_hal_wdt.h @@ -42,7 +42,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_WDT_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_adc.h b/bsp/apollo2/libraries/drivers/regs/am_reg_adc.h index 54d2d8620f..90d3531f0f 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_adc.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_adc.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_ADC_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_base_addresses.h b/bsp/apollo2/libraries/drivers/regs/am_reg_base_addresses.h index 13a850d1c4..0a223b4a67 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_base_addresses.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_base_addresses.h @@ -37,7 +37,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_BASE_ADDRESSES_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_cachectrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_cachectrl.h index b933a08874..ac7e9d22d2 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_cachectrl.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_cachectrl.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_CACHECTRL_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_clkgen.h b/bsp/apollo2/libraries/drivers/regs/am_reg_clkgen.h index c769673d65..d9dae13622 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_clkgen.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_clkgen.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_CLKGEN_H @@ -66,7 +66,6 @@ #define AM_REG_CLKGEN_CCTRL_O 0x00000018 #define AM_REG_CLKGEN_STATUS_O 0x0000001C #define AM_REG_CLKGEN_HFADJ_O 0x00000020 -#define AM_REG_CLKGEN_HFVAL_O 0x00000024 #define AM_REG_CLKGEN_CLOCKEN_O 0x00000028 #define AM_REG_CLKGEN_CLOCKEN2_O 0x0000002C #define AM_REG_CLKGEN_CLOCKEN3_O 0x00000030 @@ -390,16 +389,6 @@ #define AM_REG_CLKGEN_HFADJ_HFADJEN_DIS 0x00000000 #define AM_REG_CLKGEN_HFADJ_HFADJEN_EN 0x00000001 -//***************************************************************************** -// -// CLKGEN_HFVAL - HFADJ readback -// -//***************************************************************************** -// Current HFTUNE value -#define AM_REG_CLKGEN_HFVAL_HFTUNERB_S 0 -#define AM_REG_CLKGEN_HFVAL_HFTUNERB_M 0x000007FF -#define AM_REG_CLKGEN_HFVAL_HFTUNERB(n) (((uint32_t)(n) << 0) & 0x000007FF) - //***************************************************************************** // // CLKGEN_CLOCKEN - Clock Enable Status diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_ctimer.h b/bsp/apollo2/libraries/drivers/regs/am_reg_ctimer.h index 278849a74d..7bc30aa3f2 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_ctimer.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_ctimer.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_CTIMER_H @@ -51,7 +51,7 @@ //***************************************************************************** #define AM_REG_CTIMER_NUM_MODULES 1 #define AM_REG_CTIMERn(n) \ - (REG_CTIMER_BASEADDR + 0x00000000 * n) + (REG_CTIMER_BASEADDR + 0x00000010 * n) //***************************************************************************** // diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_flashctrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_flashctrl.h index 0b103ea6fb..53cc2fb6d1 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_flashctrl.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_flashctrl.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_FLASHCTRL_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_gpio.h b/bsp/apollo2/libraries/drivers/regs/am_reg_gpio.h index 4690cd6111..1e3d424151 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_gpio.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_gpio.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_GPIO_H @@ -1348,7 +1348,7 @@ #define AM_REG_GPIO_PADREGB_PAD7FNCSEL_SLWIR3LB 0x30000000 #define AM_REG_GPIO_PADREGB_PAD7FNCSEL_M1nCE1 0x38000000 -// Pad 7 drive strentgh +// Pad 7 drive strength #define AM_REG_GPIO_PADREGB_PAD7STRNG_S 26 #define AM_REG_GPIO_PADREGB_PAD7STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGB_PAD7STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -1514,7 +1514,7 @@ #define AM_REG_GPIO_PADREGC_PAD11FNCSEL_UART0RX 0x30000000 #define AM_REG_GPIO_PADREGC_PAD11FNCSEL_PDM_DATA 0x38000000 -// Pad 11 drive strentgh +// Pad 11 drive strength #define AM_REG_GPIO_PADREGC_PAD11STRNG_S 26 #define AM_REG_GPIO_PADREGC_PAD11STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGC_PAD11STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -1673,7 +1673,7 @@ #define AM_REG_GPIO_PADREGD_PAD15FNCSEL_SWDIO 0x30000000 #define AM_REG_GPIO_PADREGD_PAD15FNCSEL_SWO 0x38000000 -// Pad 15 drive strentgh +// Pad 15 drive strength #define AM_REG_GPIO_PADREGD_PAD15STRNG_S 26 #define AM_REG_GPIO_PADREGD_PAD15STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGD_PAD15STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -1814,7 +1814,7 @@ #define AM_REG_GPIO_PADREGE_PAD19FNCSEL_UART1RX 0x30000000 #define AM_REG_GPIO_PADREGE_PAD19FNCSEL_I2S_BCLK 0x38000000 -// Pad 19 drive strentgh +// Pad 19 drive strength #define AM_REG_GPIO_PADREGE_PAD19STRNG_S 26 #define AM_REG_GPIO_PADREGE_PAD19STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGE_PAD19STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -1955,7 +1955,7 @@ #define AM_REG_GPIO_PADREGF_PAD23FNCSEL_TCTB1 0x30000000 #define AM_REG_GPIO_PADREGF_PAD23FNCSEL_UNDEF7 0x38000000 -// Pad 23 drive strentgh +// Pad 23 drive strength #define AM_REG_GPIO_PADREGF_PAD23STRNG_S 26 #define AM_REG_GPIO_PADREGF_PAD23STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGF_PAD23STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -2112,7 +2112,7 @@ #define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M2SCKLB 0x30000000 #define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M2SCLLB 0x38000000 -// Pad 27 drive strentgh +// Pad 27 drive strength #define AM_REG_GPIO_PADREGG_PAD27STRNG_S 26 #define AM_REG_GPIO_PADREGG_PAD27STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGG_PAD27STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -2262,7 +2262,7 @@ #define AM_REG_GPIO_PADREGH_PAD31FNCSEL_UNDEF6 0x30000000 #define AM_REG_GPIO_PADREGH_PAD31FNCSEL_UNDEF7 0x38000000 -// Pad 31 drive strentgh +// Pad 31 drive strength #define AM_REG_GPIO_PADREGH_PAD31STRNG_S 26 #define AM_REG_GPIO_PADREGH_PAD31STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGH_PAD31STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -2403,7 +2403,7 @@ #define AM_REG_GPIO_PADREGI_PAD35FNCSEL_UA0RTS 0x30000000 #define AM_REG_GPIO_PADREGI_PAD35FNCSEL_M3nCE2 0x38000000 -// Pad 35 drive strentgh +// Pad 35 drive strength #define AM_REG_GPIO_PADREGI_PAD35STRNG_S 26 #define AM_REG_GPIO_PADREGI_PAD35STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGI_PAD35STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -2553,7 +2553,7 @@ #define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M4SCKLB 0x30000000 #define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M4SCLLB 0x38000000 -// Pad 39 drive strentgh +// Pad 39 drive strength #define AM_REG_GPIO_PADREGJ_PAD39STRNG_S 26 #define AM_REG_GPIO_PADREGJ_PAD39STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGJ_PAD39STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -2703,7 +2703,7 @@ #define AM_REG_GPIO_PADREGK_PAD43FNCSEL_SLMISOLB 0x30000000 #define AM_REG_GPIO_PADREGK_PAD43FNCSEL_SLSDALB 0x38000000 -// Pad 43 drive strentgh +// Pad 43 drive strength #define AM_REG_GPIO_PADREGK_PAD43STRNG_S 26 #define AM_REG_GPIO_PADREGK_PAD43STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGK_PAD43STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) @@ -2869,7 +2869,7 @@ #define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M4nCE5 0x30000000 #define AM_REG_GPIO_PADREGL_PAD47FNCSEL_SLWIR3LB 0x38000000 -// Pad 47 drive strentgh +// Pad 47 drive strength #define AM_REG_GPIO_PADREGL_PAD47STRNG_S 26 #define AM_REG_GPIO_PADREGL_PAD47STRNG_M 0x04000000 #define AM_REG_GPIO_PADREGL_PAD47STRNG(n) (((uint32_t)(n) << 26) & 0x04000000) diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_iomstr.h b/bsp/apollo2/libraries/drivers/regs/am_reg_iomstr.h index c04cd2c04a..b33ed9b666 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_iomstr.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_iomstr.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_IOMSTR_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_ioslave.h b/bsp/apollo2/libraries/drivers/regs/am_reg_ioslave.h index 4a1c96ae3c..6e9f47b002 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_ioslave.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_ioslave.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_IOSLAVE_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_itm.h b/bsp/apollo2/libraries/drivers/regs/am_reg_itm.h index c007aa629a..91554948b7 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_itm.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_itm.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_ITM_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_jedec.h b/bsp/apollo2/libraries/drivers/regs/am_reg_jedec.h index 61560dc099..7f883a8333 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_jedec.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_jedec.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_JEDEC_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_macros.h b/bsp/apollo2/libraries/drivers/regs/am_reg_macros.h index e9662958c1..5378f1a858 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_macros.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_macros.h @@ -1,6 +1,7 @@ //***************************************************************************** // -//! @file am_reg_macros.h +// am_reg_macros.h +//! @file //! //! @brief Helper macros for using hardware registers. // @@ -37,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -106,10 +107,15 @@ extern "C" // Register access macros for single-instance modules // AM_REG - Write a register of a module. // AM_BFW - Write a value to a bitfield of a register. -// AM_BFWe - Use a defined enum value to write a value to a bitfield. +// AM_BFWe - Use a defined enum value to write a value to a register bitfield. // AM_BFR - Read a bitfield value from a register. -// AM_BFM - Read and mask a bitfield, but leave the value in its bit position. -// (Useful for comparing with enums.) +// AM_BFM - Read and mask a bitfield from a register, but leave the value in +// its bit position. Useful for comparing with enums. +// +// AM_BFV - Move a value to a bitfield. This macro is used for creating a +// value, it does not modify any register. +// AM_BFX - Extract the value of a bitfield from a 32-bit value, such as that +// read from a register. Does not read or modify any register. // //***************************************************************************** #define AM_REG(module, reg) \ @@ -139,16 +145,19 @@ extern "C" //***************************************************************************** // // Register access macros for multi-instance modules +// AM_REGADDRn - Calc the register address inside a multiple instance module. // AM_REGn - Write a register of a multiple instance module. // AM_BFWn - Write a value to a bitfield of a register in a multiple instance. // AM_BFWen - Use a defined enum value to write a value to a bitfield of a // register in a multiple instance. // AM_BFRn - Read a bitfield value from a register in a multiple instance. -// AM_BFMn - Read a bitfield, but leave the value in its bitfield position. // AM_BFMn - Read and mask a bitfield, but leave the value in its bit position. // (Useful for comparing with enums.) // //***************************************************************************** +#define AM_REGADDRn(module, instance, reg) \ + (AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O) + #define AM_REGn(module, instance, reg) \ AM_REGVAL(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O) @@ -187,9 +196,9 @@ extern "C" // no operator to simply write the value atomically. // AM_REGa_SET - Set bits in a single instance module according to the mask. // AM_REGa_CLR - Clear bits in a single instance module according to the mask. -// AM_REGna - Multiple module version of AM_REGa. -// AM_REGna_SET - Multiple instance version of AM_REGa_SET. -// AM_REGna_CLR - Multiple instance version of AM_REGa_CLR. +// AM_REGan - Multiple module version of AM_REGa. +// AM_REGan_SET - Multiple instance version of AM_REGa_SET. +// AM_REGan_CLR - Multiple instance version of AM_REGa_CLR. // AM_BFWa - Write a value to a register bitfield. // AM_BFWae - Use a defined enum value to write a value to a bitfield. // AM_BFWan - Write a value to a bitfield of a register in a multiple instance. diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_macros_asm.h b/bsp/apollo2/libraries/drivers/regs/am_reg_macros_asm.h index f02624d8e3..854019d911 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_macros_asm.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_macros_asm.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_mcuctrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_mcuctrl.h index ae066bf85d..b4b1e54428 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_mcuctrl.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_mcuctrl.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_MCUCTRL_H @@ -143,6 +143,7 @@ #define AM_REG_MCUCTRL_CHIPREV_REVMIN_M 0x0000000F #define AM_REG_MCUCTRL_CHIPREV_REVMIN(n) (((uint32_t)(n) << 0) & 0x0000000F) #define AM_REG_MCUCTRL_CHIPREV_REVMIN_REV0 0x00000000 +#define AM_REG_MCUCTRL_CHIPREV_REVMIN_REV2 0x00000002 //***************************************************************************** // diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_nvic.h b/bsp/apollo2/libraries/drivers/regs/am_reg_nvic.h index 349991e28f..c2657660f2 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_nvic.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_nvic.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_NVIC_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_pdm.h b/bsp/apollo2/libraries/drivers/regs/am_reg_pdm.h index 6a7c6aa3cf..042dfd2ce3 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_pdm.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_pdm.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_PDM_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_pwrctrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_pwrctrl.h index cac7cab36c..b4929ff39a 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_pwrctrl.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_pwrctrl.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_PWRCTRL_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_rstgen.h b/bsp/apollo2/libraries/drivers/regs/am_reg_rstgen.h index 1e76519744..0554bdd465 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_rstgen.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_rstgen.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_RSTGEN_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_rtc.h b/bsp/apollo2/libraries/drivers/regs/am_reg_rtc.h index 9da5bc816c..b830445c22 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_rtc.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_rtc.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_RTC_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_sysctrl.h b/bsp/apollo2/libraries/drivers/regs/am_reg_sysctrl.h index 4a00cc21d5..b82cd0dd70 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_sysctrl.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_sysctrl.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_SYSCTRL_H @@ -58,6 +58,8 @@ // Register offsets. // //***************************************************************************** +#define AM_REG_SYSCTRL_ICTR_O 0xE000E004 +#define AM_REG_SYSCTRL_ACTLR_O 0xE000E008 #define AM_REG_SYSCTRL_ICSR_O 0xE000ED04 #define AM_REG_SYSCTRL_VTOR_O 0xE000ED08 #define AM_REG_SYSCTRL_AIRCR_O 0xE000ED0C @@ -78,6 +80,47 @@ #define AM_REG_SYSCTRL_FPCAR_O 0xE000EF38 #define AM_REG_SYSCTRL_FPDSCR_O 0xE000EF3C +//***************************************************************************** +// +// SYSCTRL_ICTR - Interrupt Controller Type Register (NVIC) +// +//***************************************************************************** +// Total number of interrupt lines in groups of 32. +#define AM_REG_SYSCTRL_ICTR_INTLINESNUM_S 0 +#define AM_REG_SYSCTRL_ICTR_INTLINESNUM_M 0x0000000F +#define AM_REG_SYSCTRL_ICTR_INTLINESNUM(n) (((uint32_t)(n) << 0) & 0x0000000F) + +//***************************************************************************** +// +// SYSCTRL_ACTLR - Auxilliary Control Register +// +//***************************************************************************** +// Disables lazy stacking of floating point context. +#define AM_REG_SYSCTRL_ACTLR_DISFPCA_S 9 +#define AM_REG_SYSCTRL_ACTLR_DISFPCA_M 0x00000200 +#define AM_REG_SYSCTRL_ACTLR_DISFPCA(n) (((uint32_t)(n) << 9) & 0x00000200) + +// Disables floating point instructions completing out of order with respect to +// integer instructions. +#define AM_REG_SYSCTRL_ACTLR_DISOOFP_S 8 +#define AM_REG_SYSCTRL_ACTLR_DISOOFP_M 0x00000100 +#define AM_REG_SYSCTRL_ACTLR_DISOOFP(n) (((uint32_t)(n) << 8) & 0x00000100) + +// Disables folding of IT instructions. +#define AM_REG_SYSCTRL_ACTLR_DISFOLD_S 2 +#define AM_REG_SYSCTRL_ACTLR_DISFOLD_M 0x00000004 +#define AM_REG_SYSCTRL_ACTLR_DISFOLD(n) (((uint32_t)(n) << 2) & 0x00000004) + +// Disables write buffer use during default memory map accesses. +#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF_S 1 +#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF_M 0x00000002 +#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF(n) (((uint32_t)(n) << 1) & 0x00000002) + +// Disables interruption of multi-cycle instructions. +#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT_S 0 +#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT_M 0x00000001 +#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT(n) (((uint32_t)(n) << 0) & 0x00000001) + //***************************************************************************** // // SYSCTRL_ICSR - Interrupt Control and State Register diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_systick.h b/bsp/apollo2/libraries/drivers/regs/am_reg_systick.h index d68a8c4063..0d427dabe2 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_systick.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_systick.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_SYSTICK_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_tpiu.h b/bsp/apollo2/libraries/drivers/regs/am_reg_tpiu.h index e3719b60f8..f1822a74d5 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_tpiu.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_tpiu.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_TPIU_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_uart.h b/bsp/apollo2/libraries/drivers/regs/am_reg_uart.h index 493a947630..eabf749939 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_uart.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_uart.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_UART_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_vcomp.h b/bsp/apollo2/libraries/drivers/regs/am_reg_vcomp.h index 93c610e123..2df6cc8479 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_vcomp.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_vcomp.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_VCOMP_H diff --git a/bsp/apollo2/libraries/drivers/regs/am_reg_wdt.h b/bsp/apollo2/libraries/drivers/regs/am_reg_wdt.h index f95ddc1e8d..96fefd898f 100644 --- a/bsp/apollo2/libraries/drivers/regs/am_reg_wdt.h +++ b/bsp/apollo2/libraries/drivers/regs/am_reg_wdt.h @@ -38,7 +38,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 1.2.9 of the AmbiqSuite Development Package. +// This is part of revision 1.2.11 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_REG_WDT_H diff --git a/bsp/apollo2/libraries/startup/SConscript b/bsp/apollo2/libraries/startup/SConscript index bbaef37870..865befb6e9 100644 --- a/bsp/apollo2/libraries/startup/SConscript +++ b/bsp/apollo2/libraries/startup/SConscript @@ -18,6 +18,7 @@ elif rtconfig.CROSS_TOOL == 'iar': src = src + ['iar/' + 'startup_iar.c'] path = [cwd] +path += [cwd + '/cmsis/include'] CPPDEFINES = ['AM_PACKAGE_BGA', 'AM_PART_APOLLO2'] diff --git a/bsp/apollo2/project.uvoptx b/bsp/apollo2/project.uvoptx index a546ada74f..5578f1480e 100644 --- a/bsp/apollo2/project.uvoptx +++ b/bsp/apollo2/project.uvoptx @@ -161,4 +161,1228 @@ + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Board + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + board\adc.c + adc.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + board\flash.c + flash.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + board\gpio.c + gpio.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + board\i2c.c + i2c.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + board\led.c + led.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + board\pdm.c + pdm.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + board\pwm.c + pwm.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + board\rtc.c + rtc.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + board\smbus.c + smbus.c + 0 + 0 + + + 2 + 12 + 1 + 0 + 0 + 0 + board\spi.c + spi.c + 0 + 0 + + + 2 + 13 + 1 + 0 + 0 + 0 + board\uart.c + uart.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 3 + 14 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_clkgen.c + am_hal_clkgen.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_debug.c + am_hal_debug.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_cachectrl.c + am_hal_cachectrl.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_pwrctrl.c + am_hal_pwrctrl.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_mcuctrl.c + am_hal_mcuctrl.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_sysctrl.c + am_hal_sysctrl.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_reset.c + am_hal_reset.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_stimer.c + am_hal_stimer.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_ctimer.c + am_hal_ctimer.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_rtc.c + am_hal_rtc.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_interrupt.c + am_hal_interrupt.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_queue.c + am_hal_queue.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_iom.c + am_hal_iom.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_ios.c + am_hal_ios.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_vcomp.c + am_hal_vcomp.c + 0 + 0 + + + 3 + 29 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_flash.c + am_hal_flash.c + 0 + 0 + + + 3 + 30 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_gpio.c + am_hal_gpio.c + 0 + 0 + + + 3 + 31 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_uart.c + am_hal_uart.c + 0 + 0 + + + 3 + 32 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_adc.c + am_hal_adc.c + 0 + 0 + + + 3 + 33 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_pdm.c + am_hal_pdm.c + 0 + 0 + + + 3 + 34 + 1 + 0 + 0 + 0 + libraries\drivers\hal\am_hal_i2c_bit_bang.c + am_hal_i2c_bit_bang.c + 0 + 0 + + + 3 + 35 + 2 + 0 + 0 + 0 + libraries\startup\arm\startup_keil.s + startup_keil.s + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 4 + 36 + 1 + 0 + 0 + 0 + ..\..\src\clock.c + clock.c + 0 + 0 + + + 4 + 37 + 1 + 0 + 0 + 0 + ..\..\src\components.c + components.c + 0 + 0 + + + 4 + 38 + 1 + 0 + 0 + 0 + ..\..\src\device.c + device.c + 0 + 0 + + + 4 + 39 + 1 + 0 + 0 + 0 + ..\..\src\idle.c + idle.c + 0 + 0 + + + 4 + 40 + 1 + 0 + 0 + 0 + ..\..\src\ipc.c + ipc.c + 0 + 0 + + + 4 + 41 + 1 + 0 + 0 + 0 + ..\..\src\irq.c + irq.c + 0 + 0 + + + 4 + 42 + 1 + 0 + 0 + 0 + ..\..\src\kservice.c + kservice.c + 0 + 0 + + + 4 + 43 + 1 + 0 + 0 + 0 + ..\..\src\mem.c + mem.c + 0 + 0 + + + 4 + 44 + 1 + 0 + 0 + 0 + ..\..\src\mempool.c + mempool.c + 0 + 0 + + + 4 + 45 + 1 + 0 + 0 + 0 + ..\..\src\object.c + object.c + 0 + 0 + + + 4 + 46 + 1 + 0 + 0 + 0 + ..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 4 + 47 + 1 + 0 + 0 + 0 + ..\..\src\signal.c + signal.c + 0 + 0 + + + 4 + 48 + 1 + 0 + 0 + 0 + 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..\..\components\dfs\src\poll.c + poll.c + 0 + 0 + + + 6 + 60 + 1 + 0 + 0 + 0 + ..\..\components\dfs\src\select.c + select.c + 0 + 0 + + + 6 + 61 + 1 + 0 + 0 + 0 + ..\..\components\dfs\filesystems\devfs\devfs.c + devfs.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 7 + 62 + 1 + 0 + 0 + 0 + ..\..\components\drivers\i2c\i2c_core.c + i2c_core.c + 0 + 0 + + + 7 + 63 + 1 + 0 + 0 + 0 + ..\..\components\drivers\i2c\i2c_dev.c + i2c_dev.c + 0 + 0 + + + 7 + 64 + 1 + 0 + 0 + 0 + ..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 7 + 65 + 1 + 0 + 0 + 0 + ..\..\components\drivers\rtc\rtc.c + rtc_rtc.c + 0 + 0 + + + 7 + 66 + 1 + 0 + 0 + 0 + ..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + 7 + 67 + 1 + 0 + 0 + 0 + ..\..\components\drivers\spi\spi_core.c + spi_core.c + 0 + 0 + + + 7 + 68 + 1 + 0 + 0 + 0 + ..\..\components\drivers\spi\spi_dev.c + spi_dev.c + 0 + 0 + + + 7 + 69 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 7 + 70 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 7 + 71 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 7 + 72 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 7 + 73 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 7 + 74 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 7 + 75 + 1 + 0 + 0 + 0 + ..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 8 + 76 + 1 + 0 + 0 + 0 + ..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 8 + 77 + 1 + 0 + 0 + 0 + ..\..\components\finsh\symbol.c + symbol.c + 0 + 0 + + + 8 + 78 + 1 + 0 + 0 + 0 + ..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 8 + 79 + 1 + 0 + 0 + 0 + ..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 8 + 80 + 1 + 0 + 0 + 0 + ..\..\components\finsh\msh_cmd.c + msh_cmd.c + 0 + 0 + + + 8 + 81 + 1 + 0 + 0 + 0 + ..\..\components\finsh\msh_file.c + msh_file.c + 0 + 0 + + + 8 + 82 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_compiler.c + finsh_compiler.c + 0 + 0 + + + 8 + 83 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_error.c + finsh_error.c + 0 + 0 + + + 8 + 84 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_heap.c + finsh_heap.c + 0 + 0 + + + 8 + 85 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_init.c + finsh_init.c + 0 + 0 + + + 8 + 86 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_node.c + finsh_node.c + 0 + 0 + + + 8 + 87 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_ops.c + finsh_ops.c + 0 + 0 + + + 8 + 88 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_parser.c + finsh_parser.c + 0 + 0 + + + 8 + 89 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_var.c + finsh_var.c + 0 + 0 + + + 8 + 90 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_vm.c + finsh_vm.c + 0 + 0 + + + 8 + 91 + 1 + 0 + 0 + 0 + ..\..\components\finsh\finsh_token.c + finsh_token.c + 0 + 0 + + + + + libc + 0 + 0 + 0 + 0 + + 9 + 92 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\libc.c + libc.c + 0 + 0 + + + 9 + 93 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\mem_std.c + mem_std.c + 0 + 0 + + + 9 + 94 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\stdio.c + stdio.c + 0 + 0 + + + 9 + 95 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\stubs.c + stubs.c + 0 + 0 + + + 9 + 96 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\armlibc\time.c + time.c + 0 + 0 + + + diff --git a/bsp/apollo2/project.uvprojx b/bsp/apollo2/project.uvprojx index 13c1c51fe6..4346b8d5e4 100644 --- a/bsp/apollo2/project.uvprojx +++ b/bsp/apollo2/project.uvprojx @@ -1,7 +1,10 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rtthread-apollo2 @@ -15,28 +18,28 @@ AmbiqMicro.Apollo_DFP.1.0.0 http://s3.asia.ambiqmicro.com/pack/ IROM(0x00000000,0x100000) IRAM(0x10000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD10000000 -FC4000 -FN1 -FF0Apollo2 -FS00 -FL010000 -FP0($$Device:AMAPH1KK-KBR$Flash\Apollo2.FLM)) 0 $$Device:AMAPH1KK-KBR$Device\Include\apollo2.h - - - - - - - - - + + + + + + + + + $$Device:AMAPH1KK-KBR$SVD\apollo2.svd 0 0 - - - - - + + + + + 0 0 @@ -58,8 +61,8 @@ 0 0 - - + + 0 0 0 @@ -68,8 +71,8 @@ 0 0 - - + + 0 0 0 @@ -79,14 +82,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -100,8 +103,8 @@ 0 0 3 - - + + 1 @@ -149,18 +152,18 @@ 0 6 - - - - - + + + + + - - - - - + + + + + Segger\JL2CM3.dll @@ -176,10 +179,10 @@ 1 BIN\UL2CM3.DLL "" () - - - - + + + + 0 @@ -212,7 +215,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -344,7 +347,7 @@ 0x0 - + 1 @@ -367,10 +370,10 @@ 1 1 - - AM_PART_APOLLO2, RT_USING_ARM_LIBC, AM_PACKAGE_BGA, keil - - board;libraries/drivers;libraries/startup;applications;.;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/drivers/spi;../../components/drivers/include;../../components/drivers/include;../../components/libc/compilers/armlibc;../../components/finsh;../../components/dfs/include;../../components/dfs/filesystems/devfs + + AM_PART_APOLLO2, RT_USING_ARM_LIBC, AM_PACKAGE_BGA + + applications;.;board;libraries\drivers;libraries\startup;libraries\startup\cmsis\include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc @@ -384,10 +387,10 @@ 0 0 - - - - + + + + @@ -399,101 +402,89 @@ 0 0x00000000 0x20000000 - + .\build\rtthread.sct - - + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - + + + + Applications + + + main.c + 1 + applications\main.c + + + Board adc.c 1 - board/adc.c + board\adc.c - - board.c 1 - board/board.c + board\board.c - - flash.c 1 - board/flash.c + board\flash.c - - gpio.c 1 - board/gpio.c + board\gpio.c - - i2c.c 1 - board/i2c.c + board\i2c.c - - led.c 1 - board/led.c + board\led.c - - pdm.c 1 - board/pdm.c + board\pdm.c - - pwm.c 1 - board/pwm.c + board\pwm.c - - rtc.c 1 - board/rtc.c + board\rtc.c - - smbus.c 1 - board/smbus.c + board\smbus.c - - spi.c 1 - board/spi.c + board\spi.c - - uart.c 1 - board/uart.c + board\uart.c @@ -503,157 +494,112 @@ am_hal_clkgen.c 1 - libraries/drivers/hal/am_hal_clkgen.c + libraries\drivers\hal\am_hal_clkgen.c - - am_hal_debug.c 1 - libraries/drivers/hal/am_hal_debug.c + libraries\drivers\hal\am_hal_debug.c - - am_hal_cachectrl.c 1 - libraries/drivers/hal/am_hal_cachectrl.c + libraries\drivers\hal\am_hal_cachectrl.c - - am_hal_pwrctrl.c 1 - libraries/drivers/hal/am_hal_pwrctrl.c + libraries\drivers\hal\am_hal_pwrctrl.c + + + am_hal_mcuctrl.c + 1 + libraries\drivers\hal\am_hal_mcuctrl.c - - am_hal_sysctrl.c 1 - libraries/drivers/hal/am_hal_sysctrl.c + libraries\drivers\hal\am_hal_sysctrl.c - - am_hal_reset.c 1 - libraries/drivers/hal/am_hal_reset.c + libraries\drivers\hal\am_hal_reset.c - - am_hal_stimer.c 1 - libraries/drivers/hal/am_hal_stimer.c + libraries\drivers\hal\am_hal_stimer.c - - am_hal_ctimer.c 1 - libraries/drivers/hal/am_hal_ctimer.c + libraries\drivers\hal\am_hal_ctimer.c - - am_hal_rtc.c 1 - libraries/drivers/hal/am_hal_rtc.c + libraries\drivers\hal\am_hal_rtc.c - - am_hal_interrupt.c 1 - libraries/drivers/hal/am_hal_interrupt.c + libraries\drivers\hal\am_hal_interrupt.c - - am_hal_queue.c 1 - libraries/drivers/hal/am_hal_queue.c + libraries\drivers\hal\am_hal_queue.c - - am_hal_iom.c 1 - libraries/drivers/hal/am_hal_iom.c + libraries\drivers\hal\am_hal_iom.c - - am_hal_ios.c 1 - libraries/drivers/hal/am_hal_ios.c + libraries\drivers\hal\am_hal_ios.c - - am_hal_vcomp.c 1 - libraries/drivers/hal/am_hal_vcomp.c + libraries\drivers\hal\am_hal_vcomp.c - - am_hal_flash.c 1 - libraries/drivers/hal/am_hal_flash.c + libraries\drivers\hal\am_hal_flash.c - - am_hal_gpio.c 1 - libraries/drivers/hal/am_hal_gpio.c + libraries\drivers\hal\am_hal_gpio.c - - am_hal_uart.c 1 - libraries/drivers/hal/am_hal_uart.c + libraries\drivers\hal\am_hal_uart.c - - am_hal_adc.c 1 - libraries/drivers/hal/am_hal_adc.c + libraries\drivers\hal\am_hal_adc.c - - am_hal_pdm.c 1 - libraries/drivers/hal/am_hal_pdm.c + libraries\drivers\hal\am_hal_pdm.c - - am_hal_i2c_bit_bang.c 1 - libraries/drivers/hal/am_hal_i2c_bit_bang.c + libraries\drivers\hal\am_hal_i2c_bit_bang.c - - startup_keil.s 2 - libraries/startup/arm/startup_keil.s - - - - - Applications - - - main.c - 1 - applications/main.c + libraries\startup\arm\startup_keil.s @@ -663,98 +609,72 @@ clock.c 1 - ../../src/clock.c + ..\..\src\clock.c - - components.c 1 - ../../src/components.c + ..\..\src\components.c - - device.c 1 - ../../src/device.c + ..\..\src\device.c - - idle.c 1 - ../../src/idle.c + ..\..\src\idle.c - - ipc.c 1 - ../../src/ipc.c + ..\..\src\ipc.c - - irq.c 1 - ../../src/irq.c + ..\..\src\irq.c - - kservice.c 1 - ../../src/kservice.c + ..\..\src\kservice.c - - mem.c 1 - ../../src/mem.c + ..\..\src\mem.c - - mempool.c 1 - ../../src/mempool.c + ..\..\src\mempool.c - - object.c 1 - ../../src/object.c + ..\..\src\object.c - - scheduler.c 1 - ../../src/scheduler.c + ..\..\src\scheduler.c - - signal.c 1 - ../../src/signal.c + ..\..\src\signal.c - - thread.c 1 - ../../src/thread.c + ..\..\src\thread.c - - timer.c 1 - ../../src/timer.c + ..\..\src\timer.c @@ -764,301 +684,27 @@ cpuport.c 1 - ../../libcpu/arm/cortex-m4/cpuport.c + ..\..\libcpu\arm\cortex-m4\cpuport.c - - context_rvds.S 2 - ../../libcpu/arm/cortex-m4/context_rvds.S + ..\..\libcpu\arm\cortex-m4\context_rvds.S - - backtrace.c 1 - ../../libcpu/arm/common/backtrace.c + ..\..\libcpu\arm\common\backtrace.c - - div0.c 1 - ../../libcpu/arm/common/div0.c + ..\..\libcpu\arm\common\div0.c - - showmem.c 1 - ../../libcpu/arm/common/showmem.c - - - - - DeviceDrivers - - - pin.c - 1 - ../../components/drivers/misc/pin.c - - - - - i2c_core.c - 1 - ../../components/drivers/i2c/i2c_core.c - - - - - i2c_dev.c - 1 - ../../components/drivers/i2c/i2c_dev.c - - - - - serial.c - 1 - ../../components/drivers/serial/serial.c - - - - - rtc_rtc.c - 1 - ../../components/drivers/rtc/rtc.c - - - - - spi_core.c - 1 - ../../components/drivers/spi/spi_core.c - - - - - spi_dev.c - 1 - ../../components/drivers/spi/spi_dev.c - - - - - completion.c - 1 - ../../components/drivers/src/completion.c - - - - - dataqueue.c - 1 - ../../components/drivers/src/dataqueue.c - - - - - pipe.c - 1 - ../../components/drivers/src/pipe.c - - - - - ringbuffer.c - 1 - ../../components/drivers/src/ringbuffer.c - - - - - waitqueue.c - 1 - ../../components/drivers/src/waitqueue.c - - - - - workqueue.c - 1 - ../../components/drivers/src/workqueue.c - - - - - - - - - - - - - - - - - libc - - - libc.c - 1 - ../../components/libc/compilers/armlibc/libc.c - - - - - libc_syms.c - 1 - ../../components/libc/compilers/armlibc/libc_syms.c - - - - - mem_std.c - 1 - ../../components/libc/compilers/armlibc/mem_std.c - - - - - stdio.c - 1 - ../../components/libc/compilers/armlibc/stdio.c - - - - - stubs.c - 1 - ../../components/libc/compilers/armlibc/stubs.c - - - - - time.c - 1 - ../../components/libc/compilers/armlibc/time.c - - - - - finsh - - - shell.c - 1 - ../../components/finsh/shell.c - - - - - symbol.c - 1 - ../../components/finsh/symbol.c - - - - - cmd.c - 1 - ../../components/finsh/cmd.c - - - - - msh.c - 1 - ../../components/finsh/msh.c - - - - - msh_cmd.c - 1 - ../../components/finsh/msh_cmd.c - - - - - msh_file.c - 1 - ../../components/finsh/msh_file.c - - - - - finsh_compiler.c - 1 - ../../components/finsh/finsh_compiler.c - - - - - finsh_error.c - 1 - ../../components/finsh/finsh_error.c - - - - - finsh_heap.c - 1 - ../../components/finsh/finsh_heap.c - - - - - finsh_init.c - 1 - ../../components/finsh/finsh_init.c - - - - - finsh_node.c - 1 - ../../components/finsh/finsh_node.c - - - - - finsh_ops.c - 1 - ../../components/finsh/finsh_ops.c - - - - - finsh_parser.c - 1 - ../../components/finsh/finsh_parser.c - - - - - finsh_var.c - 1 - ../../components/finsh/finsh_var.c - - - - - finsh_vm.c - 1 - ../../components/finsh/finsh_vm.c - - - - - finsh_token.c - 1 - ../../components/finsh/finsh_token.c + ..\..\libcpu\arm\common\showmem.c @@ -1068,53 +714,296 @@ dfs.c 1 - ../../components/dfs/src/dfs.c + ..\..\components\dfs\src\dfs.c - - dfs_file.c 1 - ../../components/dfs/src/dfs_file.c + ..\..\components\dfs\src\dfs_file.c - - dfs_fs.c 1 - ../../components/dfs/src/dfs_fs.c + ..\..\components\dfs\src\dfs_fs.c - - dfs_posix.c 1 - ../../components/dfs/src/dfs_posix.c + ..\..\components\dfs\src\dfs_posix.c - - poll.c 1 - ../../components/dfs/src/poll.c + ..\..\components\dfs\src\poll.c - - select.c 1 - ../../components/dfs/src/select.c + ..\..\components\dfs\src\select.c - - devfs.c 1 - ../../components/dfs/filesystems/devfs/devfs.c + ..\..\components\dfs\filesystems\devfs\devfs.c + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 0 + 0 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + i2c_core.c + 1 + ..\..\components\drivers\i2c\i2c_core.c + + + i2c_dev.c + 1 + ..\..\components\drivers\i2c\i2c_dev.c + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + rtc_rtc.c + 1 + ..\..\components\drivers\rtc\rtc.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + spi_core.c + 1 + ..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\components\drivers\spi\spi_dev.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + symbol.c + 1 + ..\..\components\finsh\symbol.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + msh_cmd.c + 1 + ..\..\components\finsh\msh_cmd.c + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + + + libc + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + stdio.c + 1 + ..\..\components\libc\compilers\armlibc\stdio.c + + + stubs.c + 1 + ..\..\components\libc\compilers\armlibc\stubs.c + + + time.c + 1 + ..\..\components\libc\compilers\armlibc\time.c + diff --git a/bsp/apollo2/rtthread.sct b/bsp/apollo2/rtthread.sct new file mode 100644 index 0000000000..507ebdca1a --- /dev/null +++ b/bsp/apollo2/rtthread.sct @@ -0,0 +1,14 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00006000 0x000FFFFF { ; load region size_region + ER_IROM1 0x00006000 0x000FFFFF { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x10000000 0x00040000 { ; RW data + .ANY (+RW +ZI) + } +}