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add support for SmartFusion2 family FPGA

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whik 2020-06-05 21:56:40 +08:00
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810
bsp/smartfusion2/CMSIS/core_cm3.c Normal file
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/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/*******************************************************************************
* Microsemi SoC Products Group SVN revision number for the purpose of tracking
* changes done to original file supplied by ARM:
* SVN $Revision: 6671 $
* SVN $Date: 2014-07-04 12:15:22 +0100 (Fri, 04 Jul 2014) $
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION < 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
{
clrex
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
#if (__VER__ < 6020000)
uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
}
#endif
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
#if (__VER__ < 6020000)
void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
__ASM("bx lr");
}
#endif
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
#if (__VER__ < 6020000)
uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
}
#endif
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
#if (__VER__ < 6020000)
void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
__ASM("bx lr");
}
#endif
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
#if (__VER__ < 6020000)
uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
}
#endif
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
#if (__VER__ < 6020000)
uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
__ASM("bx lr");
}
#endif
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
#if (__VER__ < 6020000)
uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
__ASM("bx lr");
}
#endif
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
#if (__VER__ < 6020000)
uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
__ASM("bx lr");
}
#endif
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
#if (__VER__ < 6020000)
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
__ASM("bx lr");
}
#endif
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
#if (__VER__ < 6020000)
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
__ASM("bx lr");
}
#endif
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
__ASM("bx lr");
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__( ( naked ) );
uint32_t __get_PSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, psp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n\t"
"BX lr \n\t" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__( ( naked ) );
uint32_t __get_MSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, msp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n\t"
"BX lr \n\t" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif

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/*******************************************************************************
* (c) Copyright 2011-2013 Microsemi SoC Products Group. All rights reserved.
*
* SmartFusion2 Cortex Microcontroller Software Interface - Peripheral
* Access Layer.
*
* This file provides interfaces to perform register and register bit level
* read / write operations. These interfaces support bit-banding in case of
* Cortex-M3 CPU.
*
* SVN $Revision: 5263 $
* SVN $Date: 2013-03-21 14:44:58 +0000 (Thu, 21 Mar 2013) $
*/
#ifndef HW_REG_IO_H_
#define HW_REG_IO_H_
#include <stdint.h> /* Include standard types */
#if defined ( __CC_ARM )
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#endif
/*****************************************************************************************
* Definitions for register access
*/
#define HW_REG(addr) (*((volatile uint32_t *) (addr)))
static __INLINE void write_reg32(volatile uint32_t * reg, uint32_t val)
{
HW_REG(reg) = val;
}
static __INLINE void write_reg16(volatile uint16_t * reg, uint16_t val)
{
HW_REG(reg) = val;
}
static __INLINE void write_reg8(volatile uint8_t * reg, uint8_t val)
{
HW_REG(reg) = val;
}
static __INLINE uint32_t read_reg32(volatile uint32_t * reg)
{
return ( HW_REG(reg) );
}
static __INLINE uint16_t read_reg16(volatile uint16_t * reg)
{
return ( HW_REG(reg) );
}
static __INLINE uint8_t read_reg8(volatile uint8_t * reg)
{
return ( HW_REG(reg) );
}
/*****************************************************************************************
* Definitions for register bits access using bit-band aliases for Cortex-M3
*/
#define BITBAND(addr,bitnum) (((uint32_t)addr & 0xF0000000)+0x02000000+(((uint32_t)addr & 0xFFFFF)<<5)+(bitnum<<2))
#define HW_REG_BIT(reg,bitnum) (*(volatile unsigned int *)((BITBAND(reg,bitnum))))
/*****************************************************************************************
* Functions to set a bit field in Cortex-M3
*/
static __INLINE void set_bit_reg32(volatile uint32_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x1;
}
/*****************************************************************************************
* Functions to clear a bit field in Cortex-M3
*/
static __INLINE void clear_bit_reg32(volatile uint32_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x0;
}
/*****************************************************************************************
* Functions to read a bit field in Cortex-M3
*/
static __INLINE uint8_t read_bit_reg32(volatile uint32_t * reg, uint8_t bit)
{
return (HW_REG_BIT(reg,bit));
}
static __INLINE uint8_t read_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
return (HW_REG_BIT(reg,bit));
}
static __INLINE uint8_t read_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
return (HW_REG_BIT(reg,bit));
}
#endif /* HW_REG_IO_H_ */

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/*******************************************************************************
* (c) Copyright 2009-2013 Microsemi SoC Products Group. All rights reserved.
*
* Assertion implementation.
*
* This file provides the implementation of the ASSERT macro. This file can be
* modified to cater for project specific requirements regarding the way
* assertions are handled.
*
* SVN $Revision: 6422 $
* SVN $Date: 2014-05-14 14:37:56 +0100 (Wed, 14 May 2014) $
*/
#ifndef __MSS_ASSERT_H_
#define __MSS_ASSERT_H_
#if defined(NDEBUG)
#define ASSERT(CHECK)
#else /* NDEBUG */
#include <assert.h>
#if defined ( __GNUC__ )
/*
* SoftConsole assertion handling
*/
#define ASSERT(CHECK) \
do { \
if (!(CHECK)) \
{ \
__asm volatile ("BKPT\n\t"); \
} \
} while (0);
#elif defined ( __ICCARM__ )
/*
* IAR Embedded Workbench assertion handling.
* Call C library assert function which should result in error message
* displayed in debugger.
*/
#define ASSERT(X) assert(X)
#else
/*
* Keil assertion handling.
* Call C library assert function which should result in error message
* displayed in debugger.
*/
#ifndef __MICROLIB
#define ASSERT(X) assert(X)
#else
#define ASSERT(X)
#endif
#endif /* Tool Chain */
#endif /* NDEBUG */
#endif /* __MSS_ASSERT_H_ */

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/*******************************************************************************
* (c) Copyright 2014 Microsemi SoC Products Group. All rights reserved.
*
* Keil-MDK specific system initialization.
*
* SVN $Revision: 7375 $
* SVN $Date: 2015-05-01 14:57:40 +0100 (Fri, 01 May 2015) $
*/
#ifdef MSCC_NO_RELATIVE_PATHS
#include "m2sxxx.h"
#else
#include "..\m2sxxx.h"
#endif
#define ENVM_BASE_ADDRESS 0x60000000U
#define MDDR_BASE_ADDRESS 0xA0000000U
//extern unsigned int Image$$ER_RW$$Base;
//extern unsigned int Image$$ER_RO$$Base;
/*==============================================================================
* The __low_level_init() function is called after SystemInit. Therefore, the
* external RAM should be configured at this stage if it is used.
*/
/* void low_level_init(void)
{
volatile unsigned int rw_region_base;
volatile unsigned int readonly_region_base;
rw_region_base = (unsigned int)&Image$$ER_RW$$Base;
if (rw_region_base >= MDDR_BASE_ADDRESS)
{
/ --------------------------------------------------------------------------
* Remap MDDR to address 0x00000000.
/
SYSREG->ESRAM_CR = 0u;
SYSREG->ENVM_REMAP_BASE_CR = 0u;
SYSREG->DDR_CR = 1u;
}
readonly_region_base = (unsigned int)&Image$$ER_RO$$Base;
SCB->VTOR = readonly_region_base;
} */

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/*******************************************************************************
* (c) Copyright 2013 Microsemi SoC Products Group. All rights reserved.
*
* Redirection of the standard library I/O to one of the SmartFusion2
* MMUART.
*
* SVN $Revision: 7375 $
* SVN $Date: 2015-05-01 14:57:40 +0100 (Fri, 01 May 2015) $
*/
/*==============================================================================
* The content of this source file will only be compiled if either one of the
* following two defined symbols are defined in the project settings:
* - MICROSEMI_STDIO_THRU_MMUART0
* - MICROSEMI_STDIO_THRU_MMUART1
*
*/
#ifdef MICROSEMI_STDIO_THRU_MMUART0
#ifndef MICROSEMI_STDIO_THRU_UART
#define MICROSEMI_STDIO_THRU_UART
#endif
#endif /* MICROSEMI_STDIO_THRU_MMUART0 */
#ifdef MICROSEMI_STDIO_THRU_MMUART1
#ifndef MICROSEMI_STDIO_THRU_UART
#define MICROSEMI_STDIO_THRU_UART
#endif
#endif /* MICROSEMI_STDIO_THRU_MMUART1 */
/*==============================================================================
* Actual implementation.
*/
#ifdef MICROSEMI_STDIO_THRU_UART
#include <stdio.h>
#include <rt_misc.h>
#include "m2sxxx.h"
#include "mss_uart.h"
#include "core_uart_apb.h"
/*
* The baud rate will default to 57600 baud if no baud rate is specified though the
* MICROSEMI_STDIO_BAUD_RATE define.
*/
#ifndef MICROSEMI_STDIO_BAUD_RATE
#define MICROSEMI_STDIO_BAUD_RATE MSS_UART_115200_BAUD
#endif
#ifdef MICROSEMI_STDIO_THRU_MMUART0
static mss_uart_instance_t * const gp_my_uart = &g_mss_uart0;
#else
static mss_uart_instance_t * const gp_my_uart = &g_mss_uart1;
#endif
/*==============================================================================
* Flag used to indicate if the UART driver needs to be initialized.
*/
static int g_stdio_uart_init_done = 0;
#define LSR_THRE_MASK 0x20u
/*
* Disable semihosting apis
*/
#pragma import(__use_no_semihosting_swi)
/*==============================================================================
* sendchar()
*/
int sendchar(int ch)
{
uint32_t tx_ready;
//第一次调用时，初始化串口
if(!g_stdio_uart_init_done)
{
MSS_UART_init(gp_my_uart,
MICROSEMI_STDIO_BAUD_RATE,
MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY);
g_stdio_uart_init_done = 1;
}
do {
tx_ready = gp_my_uart->hw_reg->LSR & LSR_THRE_MASK;
} while(!tx_ready);
gp_my_uart->hw_reg->THR = ch;
return (ch);
}
/*==============================================================================
*
*/
struct __FILE { int handle; /* Add whatever you need here */ };
FILE __stdout;
FILE __stdin;
/*==============================================================================
* fputc()
*/
int fputc(int ch, FILE *f)
{
return (sendchar(ch));
}
/*==============================================================================
* fgetc()
*/
int fgetc(FILE *f)
{
uint8_t rx_size;
uint8_t rx_byte;
do {
rx_size = MSS_UART_get_rx(gp_my_uart, &rx_byte, 1);
} while(0u == rx_size);
return rx_byte;
}
/*==============================================================================
* ferror()
*/
int ferror(FILE *f)
{
/* Your implementation of ferror */
return EOF;
}
/*==============================================================================
* _ttywrch()
*/
void _ttywrch(int ch)
{
sendchar(ch);
}
/*==============================================================================
* _sys_exit()
*/
void _sys_exit(int return_code)
{
for(;;)
{
; /* endless loop */
}
}
#endif /* MICROSEMI_STDIO_THRU_UART */

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;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for debugging code executing in internal eSRAM.
;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
; * Some current (April 2015) dev kit memory map possibilities are
; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
; * --Some older physical memory map possibilities are
; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
; eNVM=256KB eRAM=64KB External memory = 64MB
RAM_LOAD 0x20000000 0x10000
{
; First half of RAM allocated to RO Execute and data
ER_RO 0x20000000 0x8000
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file
; Second half of RAM allocated to RW data, heap and stack
ER_RW 0x20008000 0x8000
{
.ANY (+RW +ZI)
}
}

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bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct Normal file
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;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for executing code in internal eNVM.
;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
; * Some current (April 2015) dev kit memory map possibilities are
; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
; * --Some older physical memory map possibilities are
; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
; eNVM=256KB eRAM=64KB External memory = 64MB
FLASH_LOAD 0x00000000 0x40000
{
; All R only code/data is located in ENVM
ER_RO 0x00000000 0x40000
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file
ER_RW 0x20000000 0x10000
{
.ANY (+RW +ZI)
}
}

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bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct Normal file
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;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for debugging code executing in external MDDR.
;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
; * Some current (April 2015) dev kit memory map possibilities are
; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
; * --Some older physical memory map possibilities are
; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
; eNVM=256KB eRAM=64KB External memory = 64MB
; Extern RAM 64M in total
; allocate 1/2 to progam, 1/2 to variable data
RAM_LOAD 0x00000000 0x04000000
{
; Total = 64MB (lowest common amount accross dev kits) 32MB - First half of external memory allocated to RO Code
ER_RO 0x00000000 0x02000000
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file as is the case below
STACKS 0x20000000 UNINIT
{
startup_m2sxxx.o (STACK)
}
; 32 MB- Second half of external memory allocated to RW data
ER_RW 0xA2000000 0x02000000
{
.ANY (+RW +ZI)
}
}

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;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for relocating code to external RAM.
;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
; * Some current (April 2015) dev kit memory map possibilities are
; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
; * --Some older physical memory map possibilities are
; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
; eNVM=256KB eRAM=64KB External memory = 64MB
FLASH_LOAD 0x60000000 0x40000
{
; All code required on start-up located here before relocation has occured
ER_RO 0x60000000 0x40000
{
*.o (RESET, +First)
*(InRoot$$Sections)
startup_m2sxxx.o
system_m2sxxx.o
sys_config.o
low_level_init.o
sys_config_SERDESIF_?.o
mscc_post_hw_cfg_init.o
ecc_error_handler.o
}
; MDDR_RAM 0xA0000000 0x4000000
; -MDDR is mapped to address space from 0 on startup
; This allows the use of cache which is restriced to this area.
; Code is copied to RAM_EXEC space on startup by boot code.
RAM_EXEC 0x00000000 0x00040000
{
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file as is the case below
STACKS 0x20000000 UNINIT
{
startup_m2sxxx.o (STACK)
}
; All internal RAM has been allocatd to the stack
; INTERNAL_RAM 0x20008000 0x10000
; {
; .ANY (+RW +ZI)
; }
; MDDR_RAM 0xA0000000 0x4000000 So use top half of this for RW data
; Bottom half has been assigned to R only code already
ER_RW 0xA2000000 0x2000000
{
.ANY (+RW +ZI)
}
}

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;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 startup code for Keil-MDK.
;
; SmartFusion2 vector table and startup code for ARM tool chain.
;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
stack_start
Stack_Mem SPACE Stack_Size
__initial_sp
stack_end
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
;===============================================================================
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WdogWakeup_IRQHandler
DCD RTC_Wakeup_IRQHandler
DCD SPI0_IRQHandler
DCD SPI1_IRQHandler
DCD I2C0_IRQHandler
DCD I2C0_SMBAlert_IRQHandler
DCD I2C0_SMBus_IRQHandler
DCD I2C1_IRQHandler
DCD I2C1_SMBAlert_IRQHandler
DCD I2C1_SMBus_IRQHandler
DCD UART0_IRQHandler
DCD UART1_IRQHandler
DCD EthernetMAC_IRQHandler
DCD DMA_IRQHandler
DCD Timer1_IRQHandler
DCD Timer2_IRQHandler
DCD CAN_IRQHandler
DCD ENVM0_IRQHandler
DCD ENVM1_IRQHandler
DCD ComBlk_IRQHandler
DCD USB_IRQHandler
DCD USB_DMA_IRQHandler
DCD PLL_Lock_IRQHandler
DCD PLL_LockLost_IRQHandler
DCD CommSwitchError_IRQHandler
DCD CacheError_IRQHandler
DCD DDR_IRQHandler
DCD HPDMA_Complete_IRQHandler
DCD HPDMA_Error_IRQHandler
DCD ECC_Error_IRQHandler
DCD MDDR_IOCalib_IRQHandler
DCD FAB_PLL_Lock_IRQHandler
DCD FAB_PLL_LockLost_IRQHandler
DCD FIC64_IRQHandler
DCD FabricIrq0_IRQHandler
DCD FabricIrq1_IRQHandler
DCD FabricIrq2_IRQHandler
DCD FabricIrq3_IRQHandler
DCD FabricIrq4_IRQHandler
DCD FabricIrq5_IRQHandler
DCD FabricIrq6_IRQHandler
DCD FabricIrq7_IRQHandler
DCD FabricIrq8_IRQHandler
DCD FabricIrq9_IRQHandler
DCD FabricIrq10_IRQHandler
DCD FabricIrq11_IRQHandler
DCD FabricIrq12_IRQHandler
DCD FabricIrq13_IRQHandler
DCD FabricIrq14_IRQHandler
DCD FabricIrq15_IRQHandler
DCD GPIO0_IRQHandler
DCD GPIO1_IRQHandler
DCD GPIO2_IRQHandler
DCD GPIO3_IRQHandler
DCD GPIO4_IRQHandler
DCD GPIO5_IRQHandler
DCD GPIO6_IRQHandler
DCD GPIO7_IRQHandler
DCD GPIO8_IRQHandler
DCD GPIO9_IRQHandler
DCD GPIO10_IRQHandler
DCD GPIO11_IRQHandler
DCD GPIO12_IRQHandler
DCD GPIO13_IRQHandler
DCD GPIO14_IRQHandler
DCD GPIO15_IRQHandler
DCD GPIO16_IRQHandler
DCD GPIO17_IRQHandler
DCD GPIO18_IRQHandler
DCD GPIO19_IRQHandler
DCD GPIO20_IRQHandler
DCD GPIO21_IRQHandler
DCD GPIO22_IRQHandler
DCD GPIO23_IRQHandler
DCD GPIO24_IRQHandler
DCD GPIO25_IRQHandler
DCD GPIO26_IRQHandler
DCD GPIO27_IRQHandler
DCD GPIO28_IRQHandler
DCD GPIO29_IRQHandler
DCD GPIO30_IRQHandler
DCD GPIO31_IRQHandler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
;===============================================================================
; Reset Handler
;
AREA |.text|, CODE, READONLY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
; IMPORT low_level_init
IMPORT __main
;---------------------------------------------------------------
; Initialize stack RAM content to initialize the error detection
; and correction (EDAC). This is done if EDAC is enabled for the
; eSRAM blocks or the ECC/SECDED is enabled for the MDDR.
; Register R11 is used to keep track of the RAM intialization
; decision outcome for later use for heap RAM initialization at
; the end of the startup code.
; Please note that the stack has to be located in eSRAM at this
; point and cannot be located in MDDR since MDDR is not available
; at this point.
; The bits of the content of register R11 have the foolwing
; meaning:
; reg11[0]: eSRAM EDAC enabled
; reg11[1]: MDDR ECC/SECDED enabled
;
MOV R11, #0
LDR R0, SF2_MDDR_MODE_CR
LDR R0, [R0]
LDR R1, SF2_EDAC_CR
LDR R1, [R1]
AND R1, R1, #3
AND R0, R0, #0x1C
CMP R0, #0x14
BNE check_esram_edac
ORR R11, R11, #2
check_esram_edac
CMP R1, #0
BEQ check_stack_init
ORR R11, R11, #1
check_stack_init
CMP R11, #0
BEQ call_system_init
clear_stack
LDR R0, =stack_start
LDR R1, =stack_end
LDR R2, RAM_INIT_PATTERN
BL fill_memory ; fill_memory takes r0 - r2 as arguments uses r4, r5, r6, r7, r8, r9, and does not preserve contents */
;---------------------------------------------------------------
; Call SystemInit() to perform Libero specified configuration.
;
call_system_init
LDR R0, =SystemInit
BLX R0
; LDR R0, =low_level_init
; BLX R0
;---------------------------------------------------------------
; Modify MDDR configuration if ECC/SECDED is enabled for MDDR.
; Enable write combining on MDDR bridge, disable non-bufferable
; regions.
;
adjust_mddr_cfg
AND R10, R11, #0x2
CMP R10, #0
BEQ branch_to_main
LDR R0, SF2_DDRB_NB_SIZE
LDR R1, SF2_DDRB_CR
LDR R2, [R0]
LDR R3, [R1]
push {R0, R1, R2, R3}
MOV R2, #0
MOV R3, #0xFF
STR R2, [R0]
STR R3, [R1]
; --------------------------------------------------------------
; Initialize heap RAM content to initialize the error detection
; and correction (EDAC). We use the decision made earlier in the
; startup code of whether or not the stack RAM should be
; initialized. This decision is held in register R11. A non-zero
; value indicates that the RAM content should be initialized.
;
clear_heap
CMP R11, #0
BEQ branch_to_main
LDR R0, =__heap_base
LDR R1, =__heap_limit
LDR R2, HEAP_INIT_PATTERN
BL fill_memory ; fill_memory takes r0 - r2 as arguments uses r4, r5, r6, r7, r8, r9, and does not preserve contents */
;---------------------------------------------------------------
; Branch to __main
;
branch_to_main
LDR R0, =__main
BX R0
ENDP
SF2_EDAC_CR DCD 0x40038038
SF2_DDRB_NB_SIZE DCD 0x40038030
SF2_DDRB_CR DCD 0x40038034
SF2_MDDR_MODE_CR DCD 0x40020818
RAM_INIT_PATTERN DCD 0x00000000
HEAP_INIT_PATTERN DCD 0x00000000
;------------------------------------------------------------------------------
; * fill_memory.
; * @brief Fills memory with Pattern contained in r2
; * This routine uses the stmne instruction to copy 4 words at a time which is very efficient
; * The instruction can only write to word aligned memory, hence the code at the start and end of this routine
; * to handle possible unaligned bytes at start and end.
; *
; * @param param1 r0: start address
; * @param param2 r1: end address
; * @param param3 r2: FILL PATTETN
; *
; * @note note: Most efficient if memory aligned. Linker ALIGN(4) command
; * should be used as per example linker scripts
; * Stack is not used in this routine
; * register contents r4, r5, r6, r7, r8, r9, will are used and will be returned undefined
; * @return none - Used Registers are not preserved
; */
fill_memory PROC
;push {r4, r5, r6, r7, r8, r9, lr} We will not use stack as may be not available */
cmp r0, r1
beq fill_memory_exit ; Exit early if source and destination the same */
; copy non-aligned bytes at the start */
and.w r6, r0, #3 ; see if non-alaigned bytes at the start */
cmp r6, #0
beq fill_memory_end_start ; no spare bytes at start, continue */
mov r5, #4
sub.w r4, r5, r6 ; now have number of non-aligned bytes in r4 */
mov r7, #8
mul r8, r7, r6 ; calculate number of shifts required to initalise pattern for non-aligned bytes */
mov r9, r2 ; copy pattern */
ror r9, r9, r8 ; Rotate right to keep pattern consistent */
fill_memory_spare_bytes_start ; From above, R0 contains source address, R1 contains destination address */
cmp r4, #0 ; no spare bytes at end- end now */
beq fill_memory_end_start
strb r9, [r0] ; fill byte */
ror.w r9, r9, r7 ; Rotate right by one byte for the next time, to keep pattern consistent */
add r0, r0, #1 ; add one to address */
subs r4, r4, #1 ; subtract one from byte count 1 */
b fill_memory_spare_bytes_start
fill_memory_end_start
mov r6, #0
mov r7, r1 ; save end address */
subs r1, r1, r0 ; Calculate number of bytes to fill */
mov r8,r1 ; Save copy of byte count */
asrs r1,r1, #4 ; Div by 16 to get number of chunks to move */
mov r9, r2 ; copy pattern */
mov r4, r2 ; copy pattern */
mov r5, r2 ; copy pattern */
cmp r1, r6 ; compare to see if all chunks copied */
beq fill_memory_spare_bytes_end
fill_memory_loop
it ne
stmne r0!, {r2, r4, r5, r9} ; copy pattern- note: stmne instruction must me word aligned (address in r0) */
add.w r6, r6, #1 ; use Thumb2- make sure condition code reg. not updated */
cmp r1, r6 ; compare to see if all chunks copied */
bne fill_memory_loop
fill_memory_spare_bytes_end ; copy spare bytes at the end if any */
and.w r8, r8, #15 ; get spare bytes --check can you do an ands? */
fill_memory_spare_end_loop ; From above, R0 contains source address, R1 contains destination address */
cmp r8, #0 ; no spare bytes at end- end now */
beq fill_memory_exit
strb r2, [r0]
ror.w r2, r2, #8 ; Rotate right by one byte for the next time, to keep pattern consistent */
add r0, r0, #1 ; add one to address */
subs r8, r8, #1 ; subtract one from byte count 1 */
b fill_memory_spare_end_loop
fill_memory_exit
bx lr ; We will not use pop as stack may be not available */
ENDP
;===============================================================================
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WdogWakeup_IRQHandler [WEAK]
EXPORT RTC_Wakeup_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C0_SMBAlert_IRQHandler [WEAK]
EXPORT I2C0_SMBus_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C1_SMBAlert_IRQHandler [WEAK]
EXPORT I2C1_SMBus_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT EthernetMAC_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT Timer1_IRQHandler [WEAK]
EXPORT Timer2_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT ENVM0_IRQHandler [WEAK]
EXPORT ENVM1_IRQHandler [WEAK]
EXPORT ComBlk_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT USB_DMA_IRQHandler [WEAK]
EXPORT PLL_Lock_IRQHandler [WEAK]
EXPORT PLL_LockLost_IRQHandler [WEAK]
EXPORT CommSwitchError_IRQHandler [WEAK]
EXPORT CacheError_IRQHandler [WEAK]
EXPORT DDR_IRQHandler [WEAK]
EXPORT HPDMA_Complete_IRQHandler [WEAK]
EXPORT HPDMA_Error_IRQHandler [WEAK]
EXPORT ECC_Error_IRQHandler [WEAK]
EXPORT MDDR_IOCalib_IRQHandler [WEAK]
EXPORT FAB_PLL_Lock_IRQHandler [WEAK]
EXPORT FAB_PLL_LockLost_IRQHandler [WEAK]
EXPORT FIC64_IRQHandler [WEAK]
EXPORT FabricIrq0_IRQHandler [WEAK]
EXPORT FabricIrq1_IRQHandler [WEAK]
EXPORT FabricIrq2_IRQHandler [WEAK]
EXPORT FabricIrq3_IRQHandler [WEAK]
EXPORT FabricIrq4_IRQHandler [WEAK]
EXPORT FabricIrq5_IRQHandler [WEAK]
EXPORT FabricIrq6_IRQHandler [WEAK]
EXPORT FabricIrq7_IRQHandler [WEAK]
EXPORT FabricIrq8_IRQHandler [WEAK]
EXPORT FabricIrq9_IRQHandler [WEAK]
EXPORT FabricIrq10_IRQHandler [WEAK]
EXPORT FabricIrq11_IRQHandler [WEAK]
EXPORT FabricIrq12_IRQHandler [WEAK]
EXPORT FabricIrq13_IRQHandler [WEAK]
EXPORT FabricIrq14_IRQHandler [WEAK]
EXPORT FabricIrq15_IRQHandler [WEAK]
EXPORT GPIO0_IRQHandler [WEAK]
EXPORT GPIO1_IRQHandler [WEAK]
EXPORT GPIO2_IRQHandler [WEAK]
EXPORT GPIO3_IRQHandler [WEAK]
EXPORT GPIO4_IRQHandler [WEAK]
EXPORT GPIO5_IRQHandler [WEAK]
EXPORT GPIO6_IRQHandler [WEAK]
EXPORT GPIO7_IRQHandler [WEAK]
EXPORT GPIO8_IRQHandler [WEAK]
EXPORT GPIO9_IRQHandler [WEAK]
EXPORT GPIO10_IRQHandler [WEAK]
EXPORT GPIO11_IRQHandler [WEAK]
EXPORT GPIO12_IRQHandler [WEAK]
EXPORT GPIO13_IRQHandler [WEAK]
EXPORT GPIO14_IRQHandler [WEAK]
EXPORT GPIO15_IRQHandler [WEAK]
EXPORT GPIO16_IRQHandler [WEAK]
EXPORT GPIO17_IRQHandler [WEAK]
EXPORT GPIO18_IRQHandler [WEAK]
EXPORT GPIO19_IRQHandler [WEAK]
EXPORT GPIO20_IRQHandler [WEAK]
EXPORT GPIO21_IRQHandler [WEAK]
EXPORT GPIO22_IRQHandler [WEAK]
EXPORT GPIO23_IRQHandler [WEAK]
EXPORT GPIO24_IRQHandler [WEAK]
EXPORT GPIO25_IRQHandler [WEAK]
EXPORT GPIO26_IRQHandler [WEAK]
EXPORT GPIO27_IRQHandler [WEAK]
EXPORT GPIO28_IRQHandler [WEAK]
EXPORT GPIO29_IRQHandler [WEAK]
EXPORT GPIO30_IRQHandler [WEAK]
EXPORT GPIO31_IRQHandler [WEAK]
WdogWakeup_IRQHandler
RTC_Wakeup_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
I2C0_IRQHandler
I2C0_SMBAlert_IRQHandler
I2C0_SMBus_IRQHandler
I2C1_IRQHandler
I2C1_SMBAlert_IRQHandler
I2C1_SMBus_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
EthernetMAC_IRQHandler
DMA_IRQHandler
Timer1_IRQHandler
Timer2_IRQHandler
CAN_IRQHandler
ENVM0_IRQHandler
ENVM1_IRQHandler
ComBlk_IRQHandler
USB_IRQHandler
USB_DMA_IRQHandler
PLL_Lock_IRQHandler
PLL_LockLost_IRQHandler
CommSwitchError_IRQHandler
CacheError_IRQHandler
DDR_IRQHandler
HPDMA_Complete_IRQHandler
HPDMA_Error_IRQHandler
ECC_Error_IRQHandler
MDDR_IOCalib_IRQHandler
FAB_PLL_Lock_IRQHandler
FAB_PLL_LockLost_IRQHandler
FIC64_IRQHandler
FabricIrq0_IRQHandler
FabricIrq1_IRQHandler
FabricIrq2_IRQHandler
FabricIrq3_IRQHandler
FabricIrq4_IRQHandler
FabricIrq5_IRQHandler
FabricIrq6_IRQHandler
FabricIrq7_IRQHandler
FabricIrq8_IRQHandler
FabricIrq9_IRQHandler
FabricIrq10_IRQHandler
FabricIrq11_IRQHandler
FabricIrq12_IRQHandler
FabricIrq13_IRQHandler
FabricIrq14_IRQHandler
FabricIrq15_IRQHandler
GPIO0_IRQHandler
GPIO1_IRQHandler
GPIO2_IRQHandler
GPIO3_IRQHandler
GPIO4_IRQHandler
GPIO5_IRQHandler
GPIO6_IRQHandler
GPIO7_IRQHandler
GPIO8_IRQHandler
GPIO9_IRQHandler
GPIO10_IRQHandler
GPIO11_IRQHandler
GPIO12_IRQHandler
GPIO13_IRQHandler
GPIO14_IRQHandler
GPIO15_IRQHandler
GPIO16_IRQHandler
GPIO17_IRQHandler
GPIO18_IRQHandler
GPIO19_IRQHandler
GPIO20_IRQHandler
GPIO21_IRQHandler
GPIO22_IRQHandler
GPIO23_IRQHandler
GPIO24_IRQHandler
GPIO25_IRQHandler
GPIO26_IRQHandler
GPIO27_IRQHandler
GPIO28_IRQHandler
GPIO29_IRQHandler
GPIO30_IRQHandler
GPIO31_IRQHandler
B .
ENDP
mscc_post_hw_cfg_init PROC
EXPORT mscc_post_hw_cfg_init [WEAK]
BX LR
ENDP
ALIGN
;===============================================================================
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

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/*******************************************************************************
* (c) Copyright 2012 Microsemi SoC Products Group. All rights reserved.
*
*
*
* SVN $Revision: 4410 $
* SVN $Date: 2012-07-16 14:36:17 +0100 (Mon, 16 Jul 2012) $
*/
#ifndef SYSTEM_INIT_CFG_TYPES_H_
#define SYSTEM_INIT_CFG_TYPES_H_
#ifdef __cplusplus
extern "C" {
#endif
/*============================================================================*/
/* DDR Configuration */
/*============================================================================*/
typedef struct
{
/*--------------------------------------------------------------------------
* DDR Controller registers.
*/
struct
{
uint16_t DYN_SOFT_RESET_CR;
uint16_t RESERVED0;
uint16_t DYN_REFRESH_1_CR;
uint16_t DYN_REFRESH_2_CR;
uint16_t DYN_POWERDOWN_CR;
uint16_t DYN_DEBUG_CR;
uint16_t MODE_CR;
uint16_t ADDR_MAP_BANK_CR;
uint16_t ECC_DATA_MASK_CR;
uint16_t ADDR_MAP_COL_1_CR;
uint16_t ADDR_MAP_COL_2_CR;
uint16_t ADDR_MAP_ROW_1_CR;
uint16_t ADDR_MAP_ROW_2_CR;
uint16_t INIT_1_CR;
uint16_t CKE_RSTN_CYCLES_1_CR;
uint16_t CKE_RSTN_CYCLES_2_CR;
uint16_t INIT_MR_CR;
uint16_t INIT_EMR_CR;
uint16_t INIT_EMR2_CR;
uint16_t INIT_EMR3_CR;
uint16_t DRAM_BANK_TIMING_PARAM_CR;
uint16_t DRAM_RD_WR_LATENCY_CR;
uint16_t DRAM_RD_WR_PRE_CR;
uint16_t DRAM_MR_TIMING_PARAM_CR;
uint16_t DRAM_RAS_TIMING_CR;
uint16_t DRAM_RD_WR_TRNARND_TIME_CR;
uint16_t DRAM_T_PD_CR;
uint16_t DRAM_BANK_ACT_TIMING_CR;
uint16_t ODT_PARAM_1_CR;
uint16_t ODT_PARAM_2_CR;
uint16_t ADDR_MAP_COL_3_CR;
uint16_t MODE_REG_RD_WR_CR;
uint16_t MODE_REG_DATA_CR;
uint16_t PWR_SAVE_1_CR;
uint16_t PWR_SAVE_2_CR;
uint16_t ZQ_LONG_TIME_CR;
uint16_t ZQ_SHORT_TIME_CR;
uint16_t ZQ_SHORT_INT_REFRESH_MARGIN_1_CR;
uint16_t ZQ_SHORT_INT_REFRESH_MARGIN_2_CR;
uint16_t PERF_PARAM_1_CR;
uint16_t HPR_QUEUE_PARAM_1_CR;
uint16_t HPR_QUEUE_PARAM_2_CR;
uint16_t LPR_QUEUE_PARAM_1_CR;
uint16_t LPR_QUEUE_PARAM_2_CR;
uint16_t WR_QUEUE_PARAM_CR;
uint16_t PERF_PARAM_2_CR;
uint16_t PERF_PARAM_3_CR;
uint16_t DFI_RDDATA_EN_CR;
uint16_t DFI_MIN_CTRLUPD_TIMING_CR;
uint16_t DFI_MAX_CTRLUPD_TIMING_CR;
uint16_t DFI_WR_LVL_CONTROL_1_CR;
uint16_t DFI_WR_LVL_CONTROL_2_CR;
uint16_t DFI_RD_LVL_CONTROL_1_CR;
uint16_t DFI_RD_LVL_CONTROL_2_CR;
uint16_t DFI_CTRLUPD_TIME_INTERVAL_CR;
uint16_t DYN_SOFT_RESET_CR2;
uint16_t AXI_FABRIC_PRI_ID_CR;
} ddrc;
/*--------------------------------------------------------------------------
* DDR PHY configuration registers
*/
struct
{
uint16_t LOOPBACK_TEST_CR;
uint16_t BOARD_LOOPBACK_CR;
uint16_t CTRL_SLAVE_RATIO_CR;
uint16_t CTRL_SLAVE_FORCE_CR;
uint16_t CTRL_SLAVE_DELAY_CR;
uint16_t DATA_SLICE_IN_USE_CR;
uint16_t LVL_NUM_OF_DQ0_CR;
uint16_t DQ_OFFSET_1_CR;
uint16_t DQ_OFFSET_2_CR;
uint16_t DQ_OFFSET_3_CR;
uint16_t DIS_CALIB_RST_CR;
uint16_t DLL_LOCK_DIFF_CR;
uint16_t FIFO_WE_IN_DELAY_1_CR;
uint16_t FIFO_WE_IN_DELAY_2_CR;
uint16_t FIFO_WE_IN_DELAY_3_CR;
uint16_t FIFO_WE_IN_FORCE_CR;
uint16_t FIFO_WE_SLAVE_RATIO_1_CR;
uint16_t FIFO_WE_SLAVE_RATIO_2_CR;
uint16_t FIFO_WE_SLAVE_RATIO_3_CR;
uint16_t FIFO_WE_SLAVE_RATIO_4_CR;
uint16_t GATELVL_INIT_MODE_CR;
uint16_t GATELVL_INIT_RATIO_1_CR;
uint16_t GATELVL_INIT_RATIO_2_CR;
uint16_t GATELVL_INIT_RATIO_3_CR;
uint16_t GATELVL_INIT_RATIO_4_CR;
uint16_t LOCAL_ODT_CR;
uint16_t INVERT_CLKOUT_CR;
uint16_t RD_DQS_SLAVE_DELAY_1_CR;
uint16_t RD_DQS_SLAVE_DELAY_2_CR;
uint16_t RD_DQS_SLAVE_DELAY_3_CR;
uint16_t RD_DQS_SLAVE_FORCE_CR;
uint16_t RD_DQS_SLAVE_RATIO_1_CR;
uint16_t RD_DQS_SLAVE_RATIO_2_CR;
uint16_t RD_DQS_SLAVE_RATIO_3_CR;
uint16_t RD_DQS_SLAVE_RATIO_4_CR;
uint16_t WR_DQS_SLAVE_DELAY_1_CR;
uint16_t WR_DQS_SLAVE_DELAY_2_CR;
uint16_t WR_DQS_SLAVE_DELAY_3_CR;
uint16_t WR_DQS_SLAVE_FORCE_CR;
uint16_t WR_DQS_SLAVE_RATIO_1_CR;
uint16_t WR_DQS_SLAVE_RATIO_2_CR;
uint16_t WR_DQS_SLAVE_RATIO_3_CR;
uint16_t WR_DQS_SLAVE_RATIO_4_CR;
uint16_t WR_DATA_SLAVE_DELAY_1_CR;
uint16_t WR_DATA_SLAVE_DELAY_2_CR;
uint16_t WR_DATA_SLAVE_DELAY_3_CR;
uint16_t WR_DATA_SLAVE_FORCE_CR;
uint16_t WR_DATA_SLAVE_RATIO_1_CR;
uint16_t WR_DATA_SLAVE_RATIO_2_CR;
uint16_t WR_DATA_SLAVE_RATIO_3_CR;
uint16_t WR_DATA_SLAVE_RATIO_4_CR;
uint16_t WRLVL_INIT_MODE_CR;
uint16_t WRLVL_INIT_RATIO_1_CR;
uint16_t WRLVL_INIT_RATIO_2_CR;
uint16_t WRLVL_INIT_RATIO_3_CR;
uint16_t WRLVL_INIT_RATIO_4_CR;
uint16_t WR_RD_RL_CR;
uint16_t RDC_FIFO_RST_ERRCNTCLR_CR;
uint16_t RDC_WE_TO_RE_DELAY_CR;
uint16_t USE_FIXED_RE_CR;
uint16_t USE_RANK0_DELAYS_CR;
uint16_t USE_LVL_TRNG_LEVEL_CR;
uint16_t CONFIG_CR;
uint16_t RD_WR_GATE_LVL_CR;
uint16_t DYN_RESET_CR;
} phy;
/*--------------------------------------------------------------------------
* FIC-64 registers
* These registers are 16-bit wide and 32-bit aligned.
*/
struct
{
uint16_t NB_ADDR_CR;
uint16_t NBRWB_SIZE_CR;
uint16_t WB_TIMEOUT_CR;
uint16_t HPD_SW_RW_EN_CR;
uint16_t HPD_SW_RW_INVAL_CR;
uint16_t SW_WR_ERCLR_CR;
uint16_t ERR_INT_ENABLE_CR;
uint16_t NUM_AHB_MASTERS_CR;
uint16_t LOCK_TIMEOUTVAL_1_CR;
uint16_t LOCK_TIMEOUTVAL_2_CR;
uint16_t LOCK_TIMEOUT_EN_CR;
} fic;
} ddr_subsys_cfg_t;
/*============================================================================*/
/* FDDR Configuration */
/*============================================================================*/
typedef struct
{
uint16_t PLL_CONFIG_LOW_1;
uint16_t PLL_CONFIG_LOW_2;
uint16_t PLL_CONFIG_HIGH;
uint16_t FACC_CLK_EN;
uint16_t FACC_MUX_CONFIG;
uint16_t FACC_DIVISOR_RATIO;
uint16_t PLL_DELAY_LINE_SEL;
uint16_t SOFT_RESET;
uint16_t IO_CALIB;
uint16_t INTERRUPT_ENABLE;
uint16_t AXI_AHB_MODE_SEL;
uint16_t PHY_SELF_REF_EN;
} fddr_sysreg_t;
/*============================================================================*/
/* PCI Express Bridge IP Core configuration. */
/*============================================================================*/
typedef struct
{
uint32_t * p_reg;
uint32_t value;
} cfg_addr_value_pair_t;
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_INIT_CFG_TYPES_H_ */

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/*******************************************************************************
* (c) Copyright 2012-2013 Microsemi SoC Products Group. All rights reserved.
*
* SmartFusion2 CMSIS system initialization.
*
* SVN $Revision: 5280 $
* SVN $Date: 2013-03-22 20:51:50 +0000 (Fri, 22 Mar 2013) $
*/
#ifndef SYSTEM_M2SXXX_H
#define SYSTEM_M2SXXX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Standard CMSIS global variables. */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/* SmartFusion2 specific clocks. */
extern uint32_t g_FrequencyPCLK0; /*!< Clock frequency of APB bus 0. */
extern uint32_t g_FrequencyPCLK1; /*!< Clock frequency of APB bus 1. */
extern uint32_t g_FrequencyPCLK2; /*!< Clock frequency of APB bus 2. */
extern uint32_t g_FrequencyFIC0; /*!< Clock frequecny of FPGA fabric interface controller 1. */
extern uint32_t g_FrequencyFIC1; /*!< Clock frequecny of FPGA fabric inteface controller 2. */
extern uint32_t g_FrequencyFIC64; /*!< Clock frequecny of 64-bit FPGA fabric interface controller. */
/***************************************************************************//**
* The SystemInit() is a standard CMSIS function called during system startup.
* It is meant to perform low level hardware setup such as configuring DDR and
* SERDES controllers.
*/
void SystemInit(void);
/***************************************************************************//**
* The SystemCoreClockUpdate() is a standard CMSIS function which can be called
* by the application in order to ensure that the SystemCoreClock global
* variable contains the up to date Cortex-M3 core frequency. Calling this
* function also updates the global variables containing the frequencies of the
* APB busses connecting the peripherals.
*/
void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif

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## 移植RT-Thread到Microsemi SmartFusion2系列FPGA芯片
### 1. BSP简介
移植 RT-Thread 操作系统到 一款 **FPGA 芯片——M2S010** 上，该芯片属于 [Microsemi](https://www.microsemi.com/)（现Microchip）SmartFusion2系列，是一款**智能混合型FPGA**，片上除了 FPGA Fabric 逻辑部分，还包括一个 ARM® Cortex™-M3 内核的 MCU，主频最高 166MHz ，256KB eNVM，64KB eSRAM，集成GPIO、UART、I2C、SPI、CAN、USB等基本外设。
> 关于 Microsemi，第三大 FPGA 厂商，原 Actel 半导体，2010 年，Microsemi 收购 Actel，2018 年， Microchip 收购 Microsemi。
SmartFusion2 内部框图
![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/Microsemi_Smartfusion2_BD.jpg)
### 2. 使用说明
#### 2.1 FPGA 工程设计
FPGA 部分使用 SmartDesign 图形化设计，不需要写 HDL 代码，时钟来自外部 50M 晶体输入，PLL 倍频 100M 提供给 MCU 使用，顶层配置如下图所示：
![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/2020-06-02_114736.jpg)
MSS 部分仅使用到了GPIO 和UART0，其他外设未启用，两个 GPIO 配置成输出模式：
![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/2020-06-02_114816.jpg)
配置完成的 FPGA 工程文件下载：[fpga_project.rar](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/fpga_project.rar)
#### 2.2 ARM 程序设计
ARM 程序使用 Keil MDK 5.26 开发，需要安装 M2S 系列芯片支持包：[Microsemi.M2Sxxx.1.0.64.pack](http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack)
如果官网下载失败，可以到以下地址下载：[Microsemi.M2Sxxx.1.0.64.pack](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/Microsemi.M2Sxxx.1.0.64.pack)
在官方生成的示例工程目录下，添加 RT-Thread 相关组件，并实现一些对接函数，最终的文件结构：
![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/2020-06-04_213532.png)
### 3. 下载和运行
为了能使用 ARM 调试器连接到 ARM 内核，而不是 FPGA，需要把 JTAG_SEL 引脚置为低电平。使用 ARM 调试器，如 JLink，对应连接 JTAG 口的 TMS、TCK、GND 引脚，如果连接正常，可以检测到 ARM 芯片，如下图所示：
![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/2020-06-02_115130.jpg)
配置对应的 Flash 编程算法：
![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/2020-06-02_115115.jpg)
下载完成：
![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/2020-06-02_115216.jpg)
如果编译 & 烧写无误，下载完成或者按下复位按键之后，会在串口上看到 RT-Thread 的启动 LOG 信息：
```c
\ | /
- RT - Thread Operating System
/ | \ 4.0.3 build Jun 2 2020
2006 - 2020 Copyright by rt-thread team
msh >
```
![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/2020-06-02_115305.jpg)
### 4. 外设支持
目前仅移植了 RT-Thread 内核，支持线程调度、线程间同步和通信等，支持 Finsh 组件，PIN、Serial 等设备驱动将会在以后添加。
### 5. 资料下载
独立的工程文件下载：
- FPGA 工程下载：[fpga_project.rar](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/fpga_project.rar)
- ARM 工程下载：[smartfusion_rtt-master-4.0.3.rar](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/smartfusion_rtt-master-4.0.3.rar)
### 6. 注意事项
- FPGA 开发环境基于 Libero V11.8.2.4，向上兼容，不支持低版本 IDE。
- ARM 开发环境基于 Keil MDK 5.26，如果使用SoftConsole IDE ，需要修改 `libcpu` 内的文件。
- 调试内部 ARM 核，需要把 JTAG_SEL 拉低，否则调试器连接不上。
- 使用 SoftConsole 开发环境可以直接使用官方的 Flash Pro 调试器进行 ARM 程序的调试。
- 内核时钟需要和 FPGA 中 MSS 配置的对应，Libero 自动生成的时钟文件，可以直接替换`bsp\smartfusion2\libraries\sys_config`文件夹下的文件 。
### 7. 参考资料
- [学习路线 - RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
- [Microsemi Libero系列中文教程](https://blog.csdn.net/whik1194/article/details/102901710)
### 8. 联系我
- 邮箱：wangchao149@foxmail.com
- 主页：www.wangchaochao.top
- 微信：wcc149

17
bsp/smartfusion2/del_obj_file.bat Normal file
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%删除obj目录下的多余文件%
del *.lnp /s
::del *.opt /s ::不允许删除JLINK的设置
del *.__i /s
del *.crf /s
del *.o /s
del *.d /s
del *.htm /s
%删除USER目录下的多余文件%
del *.map /s
del *.lst /s
del *.dep /s
del *.build_log.htm /s
del *.bak
echo 编译产生的其他文件已经删除

30
bsp/smartfusion2/hal/CortexM3/Keil/cpu_types.h Normal file
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/*******************************************************************************
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* SVN $Revision: 5258 $
* SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
*/
#ifndef __CPU_TYPES_H
#define __CPU_TYPES_H 1
#include <stdint.h>
/*------------------------------------------------------------------------------
*/
typedef unsigned int size_t;
/*------------------------------------------------------------------------------
* addr_t: address type.
* Used to specify the address of peripherals present in the processor's memory
* map.
*/
typedef unsigned int addr_t;
/*------------------------------------------------------------------------------
* psr_t: processor state register.
* Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the
* processor's state between disabling and restoring interrupts.
*/
typedef unsigned int psr_t;
#endif /* __CPU_TYPES_H */

32
bsp/smartfusion2/hal/CortexM3/Keil/hal.s Normal file
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;-------------------------------------------------------------------------------
; (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
;
; Interrupt disabling/restoration for critical section protection.
;
; SVN $Revision: 5261 $
; SVN $Date: 2013-03-21 19:52:41 +0530 (Thu, 21 Mar 2013) $
;
AREA |.text|, CODE, READONLY
EXPORT HAL_disable_interrupts
EXPORT HAL_restore_interrupts
;-------------------------------------------------------------------------------
;
;
HAL_disable_interrupts \
PROC
mrs r0, PRIMASK
cpsid I
bx lr
ENDP
;-------------------------------------------------------------------------------
;
;
HAL_restore_interrupts \
PROC
msr PRIMASK, r0
bx lr
ENDP
END

96
bsp/smartfusion2/hal/CortexM3/Keil/hw_macros.h Normal file
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/*******************************************************************************
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* Hardware registers access macros.
*
* THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW
* DEVELOPMENT.
*
* These macros are used to access peripheral's registers. They allow access to
* 8, 16 and 32 bit wide registers. All accesses to peripheral registers should
* be done through these macros in order to ease porting accross different
* processors/bus architectures.
*
* Some of these macros also allow to access a specific register field.
*
* SVN $Revision: 5258 $
* SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
*/
#ifndef __HW_REGISTER_MACROS_H
#define __HW_REGISTER_MACROS_H 1
/*------------------------------------------------------------------------------
* 32 bits registers access:
*/
#define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
#define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
#define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \
(*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
( \
(uint32_t) \
( \
(*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
(uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
) \
)
#define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \
(( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
/*------------------------------------------------------------------------------
* 32 bits memory access:
*/
#define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR)))
#define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE))
/*------------------------------------------------------------------------------
* 16 bits registers access:
*/
#define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
#define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
#define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \
(*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
( \
(uint16_t) \
( \
(*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
(uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
) \
)
#define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \
(( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
/*------------------------------------------------------------------------------
* 8 bits registers access:
*/
#define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
#define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
#define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \
(*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
( \
(uint8_t) \
( \
(*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
(uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
) \
)
#define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \
(( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
/*------------------------------------------------------------------------------
* 8 bits memory access:
*/
#define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR)))
#define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE))
#endif /* __HW_REGISTER_MACROS_H */

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bsp/smartfusion2/hal/CortexM3/Keil/hw_reg_access.s Normal file
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;******************************************************************************
; (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved.
;
; SVN $Revision: 5258 $
; SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
;
AREA |.text|, CODE, READONLY
EXPORT HW_set_32bit_reg
EXPORT HW_get_32bit_reg
EXPORT HW_set_32bit_reg_field
EXPORT HW_get_32bit_reg_field
EXPORT HW_set_16bit_reg
EXPORT HW_get_16bit_reg
EXPORT HW_set_16bit_reg_field
EXPORT HW_get_16bit_reg_field
EXPORT HW_set_8bit_reg
EXPORT HW_get_8bit_reg
EXPORT HW_set_8bit_reg_field
EXPORT HW_get_8bit_reg_field
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: uint32_t value
;
HW_set_32bit_reg \
PROC
STR R1, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
;
HW_get_32bit_reg \
PROC
LDR R0, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint32_t mask
; R3: uint32_t value
;
HW_set_32bit_reg_field \
PROC
PUSH {R1,R2,R3,LR}
LSL.W R3, R3, R1
AND.W R3, R3, R2
LDR R1, [R0]
MVN.W R2, R2
AND.W R1, R1, R2
ORR.W R1, R1, R3
STR R1, [R0]
POP {R1,R2,R3,PC}
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint32_t mask
;
HW_get_32bit_reg_field \
PROC
LDR R0, [R0]
AND.W R0, R0, R2
LSR.W R0, R0, R1
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: uint_fast16_t value
;
HW_set_16bit_reg \
PROC
STRH R1, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
;
HW_get_16bit_reg \
PROC
LDRH R0, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint_fast16_t mask
; R3: uint_fast16_t value
;
HW_set_16bit_reg_field \
PROC
PUSH {R1,R2,R3,LR}
LSL.W R3, R3, R1
AND.W R3, R3, R2
LDRH R1, [R0]
MVN.W R2, R2
AND.W R1, R1, R2
ORR.W R1, R1, R3
STRH R1, [R0]
POP {R1,R2,R3,PC}
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint_fast16_t mask
;
HW_get_16bit_reg_field \
PROC
LDRH R0, [R0]
AND.W R0, R0, R2
LSR.W R0, R0, R1
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: uint_fast8_t value
;
HW_set_8bit_reg \
PROC
STRB R1, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
;
HW_get_8bit_reg \
PROC
LDRB R0, [R0]
BX LR
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr,
; R1: int_fast8_t shift
; R2: uint_fast8_t mask
; R3: uint_fast8_t value
;
HW_set_8bit_reg_field \
PROC
PUSH {R1,R2,R3,LR}
LSL.W R3, R3, R1
AND.W R3, R3, R2
LDRB R1, [R0]
MVN.W R2, R2
AND.W R1, R1, R2
ORR.W R1, R1, R3
STRB R1, [R0]
POP {R1,R2,R3,PC}
ENDP
;------------------------------------------------------------------------------
; R0: addr_t reg_addr
; R1: int_fast8_t shift
; R2: uint_fast8_t mask
;
HW_get_8bit_reg_field \
PROC
LDRB R0, [R0]
AND.W R0, R0, R2
LSR.W R0, R0, R1
BX LR
ENDP
END

209
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/*******************************************************************************
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* Legacy Actel HAL Cortex NVIC control functions.
* The use of these functions should be replaced by calls to the equivalent
* CMSIS function in your application code.
*
* SVN $Revision: 7375 $
* SVN $Date: 2015-05-01 19:27:40 +0530 (Fri, 01 May 2015) $
*/
#include "cortex_nvic.h"
#ifdef MSCC_NO_RELATIVE_PATHS
#include "mss_assert.h"
#else
#include "../../CMSIS/mss_assert.h"
#endif
/***************************************************************************//**
*
*/
void NVIC_init( void )
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Simply remove the call to NVIC_init() from your application code.
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_set_handler
(
uint32_t interrupt_number,
hal_nvic_irq_handler_t handler
)
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please remove the call to NVIC_set_handler() from your application code
* and provide a function using one of the following function prototypes to
* handle interrupts from peripherals implemeted in the SmartFusion2 FPGA
* fabric:
* - void FabricIrq0_IRQHandler(void)
* - void FabricIrq1_IRQHandler(void)
* - void FabricIrq2_IRQHandler(void)
* - void FabricIrq3_IRQHandler(void)
* - void FabricIrq4_IRQHandler(void)
* - void FabricIrq5_IRQHandler(void)
* - void FabricIrq6_IRQHandler(void)
* - void FabricIrq7_IRQHandler(void)
* - void FabricIrq8_IRQHandler(void)
* - void FabricIrq9_IRQHandler(void)
* - void FabricIrq10_IRQHandler(void)
* - void FabricIrq11_IRQHandler(void)
* - void FabricIrq12_IRQHandler(void)
* - void FabricIrq13_IRQHandler(void)
* - void FabricIrq14_IRQHandler(void)
* - void FabricIrq15_IRQHandler(void)
* The function to implement depends on which MSS_INT_F2M[n] signal is used
* in your Libero design to connect the interrupt signal of the peripheral
* generating the interrupt.
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_set_priority
(
uint32_t interrupt_number,
uint8_t priority_level
)
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please replace calls to NVIC_set_priority() with a call to the CMSIS
* void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) function where
* IRQn is one of the following values:
* - FabricIrq0_IRQn
* - FabricIrq1_IRQn
* - FabricIrq2_IRQn
* - FabricIrq3_IRQn
* - FabricIrq4_IRQn
* - FabricIrq5_IRQn
* - FabricIrq6_IRQn
* - FabricIrq7_IRQn
* - FabricIrq8_IRQn
* - FabricIrq9_IRQn
* - FabricIrq10_IRQn
* - FabricIrq11_IRQn
* - FabricIrq12_IRQn
* - FabricIrq13_IRQn
* - FabricIrq14_IRQn
* - FabricIrq15_IRQn
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_enable_interrupt( uint32_t interrupt_number )
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please replace calls to NVIC_enable_interrupt() with a call to the CMSIS
* void NVIC_EnableIRQ(IRQn_Type IRQn) function where IRQn is one of the
* following values:
* - FabricIrq0_IRQn
* - FabricIrq1_IRQn
* - FabricIrq2_IRQn
* - FabricIrq3_IRQn
* - FabricIrq4_IRQn
* - FabricIrq5_IRQn
* - FabricIrq6_IRQn
* - FabricIrq7_IRQn
* - FabricIrq8_IRQn
* - FabricIrq9_IRQn
* - FabricIrq10_IRQn
* - FabricIrq11_IRQn
* - FabricIrq12_IRQn
* - FabricIrq13_IRQn
* - FabricIrq14_IRQn
* - FabricIrq15_IRQn
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_disable_interrupt( uint32_t interrupt_number )
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please replace calls to NVIC_disable_interrupt() with a call to the CMSIS
* void NVIC_DisableIRQ(IRQn_Type IRQn) function where IRQn is one of the
* following values:
* - FabricIrq0_IRQn
* - FabricIrq1_IRQn
* - FabricIrq2_IRQn
* - FabricIrq3_IRQn
* - FabricIrq4_IRQn
* - FabricIrq5_IRQn
* - FabricIrq6_IRQn
* - FabricIrq7_IRQn
* - FabricIrq8_IRQn
* - FabricIrq9_IRQn
* - FabricIrq10_IRQn
* - FabricIrq11_IRQn
* - FabricIrq12_IRQn
* - FabricIrq13_IRQn
* - FabricIrq14_IRQn
* - FabricIrq15_IRQn
*/
ASSERT(0);
}
/***************************************************************************//**
*
*/
void NVIC_clear_interrupt( uint32_t interrupt_number )
{
/*
* Please use the NVIC control functions provided by the SmartFusion2 CMSIS
* Hardware Abstraction Layer. The use of the Actel HAL NVIC control
* functions is obsolete on SmartFusion2 devices.
*
* Please replace calls to NVIC_clear_interrupt() with a call to the CMSIS
* void NVIC_ClearPendingIRQ(IRQn_Type IRQn) function where IRQn is one of the
* following values:
* - FabricIrq0_IRQn
* - FabricIrq1_IRQn
* - FabricIrq2_IRQn
* - FabricIrq3_IRQn
* - FabricIrq4_IRQn
* - FabricIrq5_IRQn
* - FabricIrq6_IRQn
* - FabricIrq7_IRQn
* - FabricIrq8_IRQn
* - FabricIrq9_IRQn
* - FabricIrq10_IRQn
* - FabricIrq11_IRQn
* - FabricIrq12_IRQn
* - FabricIrq13_IRQn
* - FabricIrq14_IRQn
* - FabricIrq15_IRQn
*/
ASSERT(0);
}

56
bsp/smartfusion2/hal/CortexM3/cortex_nvic.h Normal file
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/*******************************************************************************
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* Legacy Actel HAL Cortex NVIC control functions.
* The use of these functions should be replaced by calls to the equivalent
* CMSIS function in your application code.
*
* SVN $Revision: 5257 $
* SVN $Date: 2013-03-21 17:54:10 +0530 (Thu, 21 Mar 2013) $
*/
#ifndef CORTEX_NVIC_H_
#define CORTEX_NVIC_H_
#include <stdint.h>
typedef void (*hal_nvic_irq_handler_t)(void);
/*------------------------------------------------------------------------------
*
*/
void NVIC_init( void );
/*------------------------------------------------------------------------------
*
*/
void NVIC_set_handler
(
uint32_t interrupt_number,
hal_nvic_irq_handler_t handler
);
/*------------------------------------------------------------------------------
*
*/
void NVIC_set_priority
(
uint32_t interrupt_number,
uint8_t priority_level
);
/*------------------------------------------------------------------------------
*
*/
void NVIC_enable_interrupt( uint32_t interrupt_number );
/*------------------------------------------------------------------------------
*
*/
void NVIC_disable_interrupt( uint32_t interrupt_number );
/*------------------------------------------------------------------------------
*
*/
void NVIC_clear_interrupt( uint32_t interrupt_number );
#endif /*CORTEX_NVIC_H_*/

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/***************************************************************************//**
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* Hardware abstraction layer functions.
*
* SVN $Revision: 5258 $
* SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
*/
#ifndef HAL_H_
#define HAL_H_
#include "cpu_types.h"
#include "hw_reg_access.h"
/***************************************************************************//**
* Enable all interrupts at the processor level.
*/
void HAL_enable_interrupts( void );
/***************************************************************************//**
* Disable all interrupts at the processor core level.
* Return the interrupts enable state before disabling occured so that it can
* later be restored.
*/
psr_t HAL_disable_interrupts( void );
/***************************************************************************//**
* Restore the interrupts enable state at the processor core level.
* This function is normally passed the value returned from a previous call to
* HAL_disable_interrupts().
*/
void HAL_restore_interrupts( psr_t saved_psr );
/***************************************************************************//**
*/
#define FIELD_OFFSET(FIELD_NAME) (FIELD_NAME##_OFFSET)
#define FIELD_SHIFT(FIELD_NAME) (FIELD_NAME##_SHIFT)
#define FIELD_MASK(FIELD_NAME) (FIELD_NAME##_MASK)
/***************************************************************************//**
* The macro HAL_set_32bit_reg() allows writing a 32 bits wide register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to write. These strings are
* specified in a header file associated with the peripheral.
* VALUE: A variable of type uint32_t containing the value to write.
*/
#define HAL_set_32bit_reg(BASE_ADDR, REG_NAME, VALUE) \
(HW_set_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
/***************************************************************************//**
* The macro HAL_get_32bit_reg() is used to read the value of a 32 bits wide
* register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to read. These strings are
* specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint32_t value.
*/
#define HAL_get_32bit_reg(BASE_ADDR, REG_NAME) \
(HW_get_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)) ))
/***************************************************************************//**
* The macro HAL_set_32bit_reg_field() is used to write a field within a
* 32 bits wide register. The field written can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* VALUE: A variable of type uint32_t containing the field value to write.
*/
#define HAL_set_32bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
(HW_set_32bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME),\
(VALUE)))
/***************************************************************************//**
* The macro HAL_get_32bit_reg_field() is used to read a register field from
* within a 32 bit wide peripheral register. The field can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint32_t value.
*/
#define HAL_get_32bit_reg_field(BASE_ADDR, FIELD_NAME) \
(HW_get_32bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME)))
/***************************************************************************//**
* The macro HAL_set_16bit_reg() allows writing a 16 bits wide register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to write. These strings are
* specified in a header file associated with the peripheral.
* VALUE: A variable of type uint_fast16_t containing the value to write.
*/
#define HAL_set_16bit_reg(BASE_ADDR, REG_NAME, VALUE) \
(HW_set_16bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
/***************************************************************************//**
* The macro HAL_get_16bit_reg() is used to read the value of a 16 bits wide
* register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to read. These strings are
* specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint16_t value.
*/
#define HAL_get_16bit_reg(BASE_ADDR, REG_NAME) \
(HW_get_16bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) ))
/***************************************************************************//**
* The macro HAL_set_16bit_reg_field() is used to write a field within a
* 16 bits wide register. The field written can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* VALUE: A variable of type uint16_t containing the field value to write.
*/
#define HAL_set_16bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
(HW_set_16bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME),\
(VALUE)))
/***************************************************************************//**
* The macro HAL_get_16bit_reg_field() is used to read a register field from
* within a 8 bit wide peripheral register. The field can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint16_t value.
*/
#define HAL_get_16bit_reg_field(BASE_ADDR, FIELD_NAME) \
(HW_get_16bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME)))
/***************************************************************************//**
* The macro HAL_set_8bit_reg() allows writing a 8 bits wide register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to write. These strings are
* specified in a header file associated with the peripheral.
* VALUE: A variable of type uint_fast8_t containing the value to write.
*/
#define HAL_set_8bit_reg(BASE_ADDR, REG_NAME, VALUE) \
(HW_set_8bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
/***************************************************************************//**
* The macro HAL_get_8bit_reg() is used to read the value of a 8 bits wide
* register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to read. These strings are
* specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint8_t value.
*/
#define HAL_get_8bit_reg(BASE_ADDR, REG_NAME) \
(HW_get_8bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) ))
/***************************************************************************//**
*/
#define HAL_set_8bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
(HW_set_8bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME),\
(VALUE)))
/***************************************************************************//**
* The macro HAL_get_8bit_reg_field() is used to read a register field from
* within a 8 bit wide peripheral register. The field can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint8_t value.
*/
#define HAL_get_8bit_reg_field(BASE_ADDR, FIELD_NAME) \
(HW_get_8bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME)))
#endif /*HAL_H_*/

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/*******************************************************************************
* (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved.
*
* SVN $Revision: 7375 $
* SVN $Date: 2015-05-01 19:27:40 +0530 (Fri, 01 May 2015) $
*/
#ifndef HAL_ASSERT_HEADER
#define HAL_ASSERT_HEADER
#ifdef MSCC_NO_RELATIVE_PATHS
#include "mss_assert.h"
#else
#include "../CMSIS/mss_assert.h"
#endif
#if defined(NDEBUG)
/***************************************************************************//**
* HAL_ASSERT() is defined out when the NDEBUG symbol is used.
******************************************************************************/
#define HAL_ASSERT(CHECK)
#else
/***************************************************************************//**
* Default behaviour for HAL_ASSERT() macro:
*------------------------------------------------------------------------------
* Using the HAL_ASSERT() macro is the same as directly using the SmartFusion2
* CMSIS ASSERT() macro. The behaviour is toolchain specific and project
* setting specific.
******************************************************************************/
#define HAL_ASSERT(CHECK) ASSERT(CHECK);
#endif /* NDEBUG */
#endif /* HAL_ASSERT_HEADER */

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/***************************************************************************//**
* (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
*
* Hardware registers access functions.
* The implementation of these function is platform and toolchain specific.
* The functions declared here are implemented using assembler as part of the
* processor/toolchain specific HAL.
*
* SVN $Revision: 5258 $
* SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
*/
#ifndef HW_REG_ACCESS
#define HW_REG_ACCESS
/***************************************************************************//**
* HW_set_32bit_reg is used to write the content of a 32 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* write.
* @param value Value to be written into the peripheral register.
*/
void
HW_set_32bit_reg
(
addr_t reg_addr,
uint32_t value
);
/***************************************************************************//**
* HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @return 32 bits value read from the peripheral register.
*/
uint32_t
HW_get_32bit_reg
(
addr_t reg_addr
);
/***************************************************************************//**
* HW_set_32bit_reg_field is used to set the content of a field in a 32 bits
* wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* be written.
* @param shift Bit offset of the register field to be read within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
* @param value Value to be written in the specified field.
*/
void
HW_set_32bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint32_t mask,
uint32_t value
);
/***************************************************************************//**
* HW_get_32bit_reg_field is used to read the content of a field out of a
* 32 bits wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @param shift Bit offset of the register field to be written within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
*
* @return 32 bits value containing the register field value specified
* as parameter.
*/
uint32_t
HW_get_32bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint32_t mask
);
/***************************************************************************//**
* HW_set_16bit_reg is used to write the content of a 16 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* write.
* @param value Value to be written into the peripheral register.
*/
void
HW_set_16bit_reg
(
addr_t reg_addr,
uint_fast16_t value
);
/***************************************************************************//**
* HW_get_16bit_reg is used to read the content of a 16 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @return 16 bits value read from the peripheral register.
*/
uint16_t
HW_get_16bit_reg
(
addr_t reg_addr
);
/***************************************************************************//**
* HW_set_16bit_reg_field is used to set the content of a field in a 16 bits
* wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* be written.
* @param shift Bit offset of the register field to be read within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
* @param value Value to be written in the specified field.
*/
void HW_set_16bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint_fast16_t mask,
uint_fast16_t value
);
/***************************************************************************//**
* HW_get_16bit_reg_field is used to read the content of a field from a
* 16 bits wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @param shift Bit offset of the register field to be written within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
*
* @return 16 bits value containing the register field value specified
* as parameter.
*/
uint16_t HW_get_16bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint_fast16_t mask
);
/***************************************************************************//**
* HW_set_8bit_reg is used to write the content of a 8 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* write.
* @param value Value to be written into the peripheral register.
*/
void
HW_set_8bit_reg
(
addr_t reg_addr,
uint_fast8_t value
);
/***************************************************************************//**
* HW_get_8bit_reg is used to read the content of a 8 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @return 8 bits value read from the peripheral register.
*/
uint8_t
HW_get_8bit_reg
(
addr_t reg_addr
);
/***************************************************************************//**
* HW_set_8bit_reg_field is used to set the content of a field in a 8 bits
* wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* be written.
* @param shift Bit offset of the register field to be read within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
* @param value Value to be written in the specified field.
*/
void HW_set_8bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint_fast8_t mask,
uint_fast8_t value
);
/***************************************************************************//**
* HW_get_8bit_reg_field is used to read the content of a field from a
* 8 bits wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @param shift Bit offset of the register field to be written within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
*
* @return 16 bits value containing the register field value specified
* as parameter.
*/
uint8_t HW_get_8bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint_fast8_t mask
);
#endif /* HW_REG_ACCESS */

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/*******************************************************************************
* (c) Copyright 2008-2015 Microsemi SoC Products Group. All rights reserved.
*
* SmartFusion2 microcontroller subsystem GPIO bare metal driver implementation.
*
* SVN $Revision: 7749 $
* SVN $Date: 2015-09-04 14:32:09 +0530 (Fri, 04 Sep 2015) $
*/
#include "mss_gpio.h"
#include "../../CMSIS/mss_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/*-------------------------------------------------------------------------*//**
* Defines.
*/
#define GPIO_INT_ENABLE_MASK ((uint32_t)0x00000008uL)
#define OUTPUT_BUFFER_ENABLE_MASK 0x00000004u
#define NB_OF_GPIO ((uint32_t)32)
/*-------------------------------------------------------------------------*//**
* Lookup table of GPIO configuration registers address indexed on GPIO ID.
*/
static uint32_t volatile * const g_config_reg_lut[NB_OF_GPIO] =
{
&(GPIO->GPIO_0_CFG),
&(GPIO->GPIO_1_CFG),
&(GPIO->GPIO_2_CFG),
&(GPIO->GPIO_3_CFG),
&(GPIO->GPIO_4_CFG),
&(GPIO->GPIO_5_CFG),
&(GPIO->GPIO_6_CFG),
&(GPIO->GPIO_7_CFG),
&(GPIO->GPIO_8_CFG),
&(GPIO->GPIO_9_CFG),
&(GPIO->GPIO_10_CFG),
&(GPIO->GPIO_11_CFG),
&(GPIO->GPIO_12_CFG),
&(GPIO->GPIO_13_CFG),
&(GPIO->GPIO_14_CFG),
&(GPIO->GPIO_15_CFG),
&(GPIO->GPIO_16_CFG),
&(GPIO->GPIO_17_CFG),
&(GPIO->GPIO_18_CFG),
&(GPIO->GPIO_19_CFG),
&(GPIO->GPIO_20_CFG),
&(GPIO->GPIO_21_CFG),
&(GPIO->GPIO_22_CFG),
&(GPIO->GPIO_23_CFG),
&(GPIO->GPIO_24_CFG),
&(GPIO->GPIO_25_CFG),
&(GPIO->GPIO_26_CFG),
&(GPIO->GPIO_27_CFG),
&(GPIO->GPIO_28_CFG),
&(GPIO->GPIO_29_CFG),
&(GPIO->GPIO_30_CFG),
&(GPIO->GPIO_31_CFG)
};
/*-------------------------------------------------------------------------*//**
* Lookup table of Cortex-M3 GPIO interrupt number indexed on GPIO ID.
*/
static const IRQn_Type g_gpio_irqn_lut[NB_OF_GPIO] =
{
GPIO0_IRQn,
GPIO1_IRQn,
GPIO2_IRQn,
GPIO3_IRQn,
GPIO4_IRQn,
GPIO5_IRQn,
GPIO6_IRQn,
GPIO7_IRQn,
GPIO8_IRQn,
GPIO9_IRQn,
GPIO10_IRQn,
GPIO11_IRQn,
GPIO12_IRQn,
GPIO13_IRQn,
GPIO14_IRQn,
GPIO15_IRQn,
GPIO16_IRQn,
GPIO17_IRQn,
GPIO18_IRQn,
GPIO19_IRQn,
GPIO20_IRQn,
GPIO21_IRQn,
GPIO22_IRQn,
GPIO23_IRQn,
GPIO24_IRQn,
GPIO25_IRQn,
GPIO26_IRQn,
GPIO27_IRQn,
GPIO28_IRQn,
GPIO29_IRQn,
GPIO30_IRQn,
GPIO31_IRQn
};
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_init
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_init( void )
{
uint32_t inc;
/* reset MSS GPIO hardware */
SYSREG->SOFT_RST_CR |= SYSREG_GPIO_SOFTRESET_MASK;
SYSREG->SOFT_RST_CR |= (SYSREG_GPIO_7_0_SOFTRESET_MASK |
SYSREG_GPIO_15_8_SOFTRESET_MASK |
SYSREG_GPIO_23_16_SOFTRESET_MASK |
SYSREG_GPIO_31_24_SOFTRESET_MASK);
/* Clear any previously pended MSS GPIO interrupt */
for(inc = 0U; inc < NB_OF_GPIO; ++inc)
{
NVIC_DisableIRQ(g_gpio_irqn_lut[inc]);
NVIC_ClearPendingIRQ(g_gpio_irqn_lut[inc]);
}
/* Take MSS GPIO hardware out of reset. */
SYSREG->SOFT_RST_CR &= ~(SYSREG_GPIO_7_0_SOFTRESET_MASK |
SYSREG_GPIO_15_8_SOFTRESET_MASK |
SYSREG_GPIO_23_16_SOFTRESET_MASK |
SYSREG_GPIO_31_24_SOFTRESET_MASK);
SYSREG->SOFT_RST_CR &= ~SYSREG_GPIO_SOFTRESET_MASK;
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_config
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_config
(
mss_gpio_id_t port_id,
uint32_t config
)
{
uint32_t gpio_idx = (uint32_t)port_id;
ASSERT(gpio_idx < NB_OF_GPIO);
if(gpio_idx < NB_OF_GPIO)
{
*(g_config_reg_lut[gpio_idx]) = config;
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_set_output
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_set_output
(
mss_gpio_id_t port_id,
uint8_t value
)
{
uint32_t gpio_setting;
uint32_t gpio_idx = (uint32_t)port_id;
ASSERT(gpio_idx < NB_OF_GPIO);
if(gpio_idx < NB_OF_GPIO)
{
gpio_setting = GPIO->GPIO_OUT;
gpio_setting &= ~((uint32_t)0x01u << gpio_idx);
gpio_setting |= ((uint32_t)value & 0x01u) << gpio_idx;
GPIO->GPIO_OUT = gpio_setting;
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_drive_inout
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_drive_inout
(
mss_gpio_id_t port_id,
mss_gpio_inout_state_t inout_state
)
{
uint32_t outputs_state;
uint32_t config;
uint32_t gpio_idx = (uint32_t)port_id;
ASSERT(gpio_idx < NB_OF_GPIO);
if(gpio_idx < NB_OF_GPIO)
{
switch(inout_state)
{
case MSS_GPIO_DRIVE_HIGH:
/* Set output high */
outputs_state = GPIO->GPIO_OUT;
outputs_state |= (uint32_t)1 << gpio_idx;
GPIO->GPIO_OUT = outputs_state;
/* Enable output buffer */
config = *(g_config_reg_lut[gpio_idx]);
config |= OUTPUT_BUFFER_ENABLE_MASK;
*(g_config_reg_lut[gpio_idx]) = config;
break;
case MSS_GPIO_DRIVE_LOW:
/* Set output low */
outputs_state = GPIO->GPIO_OUT;
outputs_state &= ~((uint32_t)((uint32_t)1 << gpio_idx));
GPIO->GPIO_OUT = outputs_state;
/* Enable output buffer */
config = *(g_config_reg_lut[gpio_idx]);
config |= OUTPUT_BUFFER_ENABLE_MASK;
*(g_config_reg_lut[gpio_idx]) = config;
break;
case MSS_GPIO_HIGH_Z:
/* Disable output buffer */
config = *(g_config_reg_lut[gpio_idx]);
config &= ~OUTPUT_BUFFER_ENABLE_MASK;
*(g_config_reg_lut[gpio_idx]) = config;
break;
default:
ASSERT(0);
break;
}
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_enable_irq
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_enable_irq
(
mss_gpio_id_t port_id
)
{
uint32_t cfg_value;
uint32_t gpio_idx = (uint32_t)port_id;
ASSERT(gpio_idx < NB_OF_GPIO);
if(gpio_idx < NB_OF_GPIO)
{
cfg_value = *(g_config_reg_lut[gpio_idx]);
*(g_config_reg_lut[gpio_idx]) = (cfg_value | GPIO_INT_ENABLE_MASK);
NVIC_EnableIRQ(g_gpio_irqn_lut[gpio_idx]);
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_disable_irq
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_disable_irq
(
mss_gpio_id_t port_id
)
{
uint32_t cfg_value;
uint32_t gpio_idx = (uint32_t)port_id;
ASSERT(gpio_idx < NB_OF_GPIO);
if(gpio_idx < NB_OF_GPIO)
{
cfg_value = *(g_config_reg_lut[gpio_idx]);
*(g_config_reg_lut[gpio_idx]) = (cfg_value & ~GPIO_INT_ENABLE_MASK);
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_clear_irq
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_clear_irq
(
mss_gpio_id_t port_id
)
{
uint32_t gpio_idx = (uint32_t)port_id;
ASSERT(gpio_idx < NB_OF_GPIO);
if(gpio_idx < NB_OF_GPIO)
{
GPIO->GPIO_IRQ = ((uint32_t)1) << gpio_idx;
}
__ASM volatile ("dsb");
}
#ifdef __cplusplus
}
#endif

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/*******************************************************************************
* (c) Copyright 2008-2015 Microsemi SoC Products Group. All rights reserved.
*
* SmartFusion2 Microcontroller Subsystem GPIO bare metal software driver public
* API.
*
* SVN $Revision: 7748 $
* SVN $Date: 2015-09-04 11:36:30 +0530 (Fri, 04 Sep 2015) $
*/
/*=========================================================================*//**
@mainpage SmartFusion2 MSS GPIO Bare Metal Driver.
@section intro_sec Introduction
The SmartFusion2 Microcontroller Subsystem (MSS) includes a block of 32 general
purpose input/outputs (GPIO).
This software driver provides a set of functions for controlling the MSS GPIO
block as part of a bare metal system where no operating system is available.
This driver can be adapted for use as part of an operating system but the
implementation of the adaptation layer between this driver and the operating
system's driver model is outside the scope of this driver.
@section hw_dependencies Hardware Flow Dependencies
The configuration of all features of the MSS GPIOs is covered by this driver
with the exception of the SmartFusion2 IOMUX configuration. SmartFusion2
allows multiple non-concurrent uses of some external pins through IOMUX
configuration. This feature allows optimization of external pin usage by
assigning external pins for use by either the microcontroller subsystem or the
FPGA fabric. The MSS GPIOs share SmartFusion2 device external pins with the
FPGA fabric and with other MSS peripherals via an IOMUX. The MSS GPIO ports
can alternatively be routed to the FPGA fabric through an IOMUX.
The IOMUXs are configured using the SmartFusion2 MSS configurator tool. You
must ensure that the MSS GPIOs are enabled and configured in the SmartFusion2
MSS configurator if you wish to use them. For more information on IOMUXs,
refer to the IOMUX section of the SmartFusion2 Microcontroller Subsystem (MSS)
User’s Guide.
The base address, register addresses and interrupt number assignment for the
MSS GPIO block are defined as constants in the SmartFusion2 CMSIS HAL. You
must ensure that the latest SmartFusion2 CMSIS HAL is included in the project
settings of the software tool chain used to build your project and that it is
generated into your project.
@section theory_op Theory of Operation
The MSS GPIO driver functions are grouped into the following categories:
- Initialization
- Configuration
- Reading and setting GPIO state
- Interrupt control
Initialization
The MSS GPIO driver is initialized through a call to the MSS_GPIO_init()
function. The MSS_GPIO_init() function must be called before any other MSS
GPIO driver functions can be called.
Configuration
Each GPIO port is individually configured through a call to the
MSS_GPIO_config() function. Configuration includes deciding if a GPIO port
will be used as an input, an output or both. GPIO ports configured as inputs
can be further configured to generate interrupts based on the input's state.
Interrupts can be level or edge sensitive.
Reading and Setting GPIO State
The state of the GPIO ports can be read and set using the following functions:
- MSS_GPIO_get_inputs()
- MSS_GPIO_get_outputs()
- MSS_GPIO_set_outputs()
- MSS_GPIO_set_output()
- MSS_GPIO_drive_inout()
Interrupt Control
Interrupts generated by GPIO ports configured as inputs are controlled using
the following functions:
- MSS_GPIO_enable_irq()
- MSS_GPIO_disable_irq()
- MSS_GPIO_clear_irq()
*//*=========================================================================*/
#ifndef MSS_GPIO_H_
#define MSS_GPIO_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "../../CMSIS/m2sxxx.h"
/*-------------------------------------------------------------------------*//**
The mss_gpio_id_t enumeration is used to identify individual GPIO ports as an
argument to functions:
- MSS_GPIO_config()
- MSS_GPIO_set_output() and MSS_GPIO_drive_inout()
- MSS_GPIO_enable_irq(), MSS_GPIO_disable_irq() and MSS_GPIO_clear_irq()
*/
typedef enum __mss_gpio_id_t
{
MSS_GPIO_0 = 0,
MSS_GPIO_1 = 1,
MSS_GPIO_2 = 2,
MSS_GPIO_3 = 3,
MSS_GPIO_4 = 4,
MSS_GPIO_5 = 5,
MSS_GPIO_6 = 6,
MSS_GPIO_7 = 7,
MSS_GPIO_8 = 8,
MSS_GPIO_9 = 9,
MSS_GPIO_10 = 10,
MSS_GPIO_11 = 11,
MSS_GPIO_12 = 12,
MSS_GPIO_13 = 13,
MSS_GPIO_14 = 14,
MSS_GPIO_15 = 15,
MSS_GPIO_16 = 16,
MSS_GPIO_17 = 17,
MSS_GPIO_18 = 18,
MSS_GPIO_19 = 19,
MSS_GPIO_20 = 20,
MSS_GPIO_21 = 21,
MSS_GPIO_22 = 22,
MSS_GPIO_23 = 23,
MSS_GPIO_24 = 24,
MSS_GPIO_25 = 25,
MSS_GPIO_26 = 26,
MSS_GPIO_27 = 27,
MSS_GPIO_28 = 28,
MSS_GPIO_29 = 29,
MSS_GPIO_30 = 30,
MSS_GPIO_31 = 31
} mss_gpio_id_t;
/*-------------------------------------------------------------------------*//**
These constant definitions are used as an argument to the
MSS_GPIO_set_outputs() function to identify GPIO ports. A logical OR of these
constants can be used to specify multiple GPIO ports.
These definitions can also be used to identify GPIO ports through logical
operations on the return value of the MSS_GPIO_get_inputs() function.
*/
#define MSS_GPIO_0_MASK 0x00000001uL
#define MSS_GPIO_1_MASK 0x00000002uL
#define MSS_GPIO_2_MASK 0x00000004uL
#define MSS_GPIO_3_MASK 0x00000008uL
#define MSS_GPIO_4_MASK 0x00000010uL
#define MSS_GPIO_5_MASK 0x00000020uL
#define MSS_GPIO_6_MASK 0x00000040uL
#define MSS_GPIO_7_MASK 0x00000080uL
#define MSS_GPIO_8_MASK 0x00000100uL
#define MSS_GPIO_9_MASK 0x00000200uL
#define MSS_GPIO_10_MASK 0x00000400uL
#define MSS_GPIO_11_MASK 0x00000800uL
#define MSS_GPIO_12_MASK 0x00001000uL
#define MSS_GPIO_13_MASK 0x00002000uL
#define MSS_GPIO_14_MASK 0x00004000uL
#define MSS_GPIO_15_MASK 0x00008000uL
#define MSS_GPIO_16_MASK 0x00010000uL
#define MSS_GPIO_17_MASK 0x00020000uL
#define MSS_GPIO_18_MASK 0x00040000uL
#define MSS_GPIO_19_MASK 0x00080000uL
#define MSS_GPIO_20_MASK 0x00100000uL
#define MSS_GPIO_21_MASK 0x00200000uL
#define MSS_GPIO_22_MASK 0x00400000uL
#define MSS_GPIO_23_MASK 0x00800000uL
#define MSS_GPIO_24_MASK 0x01000000uL
#define MSS_GPIO_25_MASK 0x02000000uL
#define MSS_GPIO_26_MASK 0x04000000uL
#define MSS_GPIO_27_MASK 0x08000000uL
#define MSS_GPIO_28_MASK 0x10000000uL
#define MSS_GPIO_29_MASK 0x20000000uL
#define MSS_GPIO_30_MASK 0x40000000uL
#define MSS_GPIO_31_MASK 0x80000000uL
/*-------------------------------------------------------------------------*//**
These constant definitions are used as an argument to the MSS_GPIO_config()
function to specify the I/O mode of each GPIO port.
*/
#define MSS_GPIO_INPUT_MODE 0x0000000002uL
#define MSS_GPIO_OUTPUT_MODE 0x0000000005uL
#define MSS_GPIO_INOUT_MODE 0x0000000003uL
/*-------------------------------------------------------------------------*//**
These constant definitions are used as an argument to the MSS_GPIO_config()
function to specify the interrupt mode of each GPIO port.
*/
#define MSS_GPIO_IRQ_LEVEL_HIGH 0x0000000000uL
#define MSS_GPIO_IRQ_LEVEL_LOW 0x0000000020uL
#define MSS_GPIO_IRQ_EDGE_POSITIVE 0x0000000040uL
#define MSS_GPIO_IRQ_EDGE_NEGATIVE 0x0000000060uL
#define MSS_GPIO_IRQ_EDGE_BOTH 0x0000000080uL
/*-------------------------------------------------------------------------*//**
The mss_gpio_inout_state_t enumeration is used to specify the output state of
an INOUT GPIO port as an argument to the MSS_GPIO_drive_inout() function.
*/
typedef enum mss_gpio_inout_state
{
MSS_GPIO_DRIVE_LOW = 0,
MSS_GPIO_DRIVE_HIGH,
MSS_GPIO_HIGH_Z
} mss_gpio_inout_state_t;
/*-------------------------------------------------------------------------*//**
The MSS_GPIO_init() function initializes the SmartFusion2 MSS GPIO block. It
resets the MSS GPIO hardware block and it also clears any pending MSS GPIO
interrupts in the ARM Cortex-M3 interrupt controller. When the function exits,
it takes the MSS GPIO block out of reset.
@param
This function has no parameters.
@return
This function does not return a value.
*/
void MSS_GPIO_init( void );
/*-------------------------------------------------------------------------*//**
The MSS_GPIO_config() function is used to configure an individual GPIO port.
@param port_id
The port_id parameter identifies the GPIO port to be configured. An
enumeration item of the form MSS_GPIO_n, where n is the number of the GPIO
port, is used to identify the GPIO port. For example, MSS_GPIO_0 identifies
the first GPIO port and MSS_GPIO_31 is the last one.
@param config
The config parameter specifies the configuration to be applied to the GPIO
port identified by the port_id parameter. It is a logical OR of the required
I/O mode and the required interrupt mode. The interrupt mode is not relevant
if the GPIO is configured as an output only.
These I/O mode constants are allowed:
- MSS_GPIO_INPUT_MODE
- MSS_GPIO_OUTPUT_MODE
- MSS_GPIO_INOUT_MODE
These interrupt mode constants are allowed:
- MSS_GPIO_IRQ_LEVEL_HIGH
- MSS_GPIO_IRQ_LEVEL_LOW
- MSS_GPIO_IRQ_EDGE_POSITIVE
- MSS_GPIO_IRQ_EDGE_NEGATIVE
- MSS_GPIO_IRQ_EDGE_BOTH
@return
none.
Example:
The following call will configure GPIO 4 as an input generating interrupts on
a Low to High transition of the input:
@code
MSS_GPIO_config( MSS_GPIO_4, MSS_GPIO_INPUT_MODE | MSS_GPIO_IRQ_EDGE_POSITIVE );
@endcode
*/
void MSS_GPIO_config
(
mss_gpio_id_t port_id,
uint32_t config
);
/*-------------------------------------------------------------------------*//**
The MSS_GPIO_set_outputs() function is used to set the state of all GPIO ports
configured as outputs.
@param value
The value parameter specifies the state of the GPIO ports configured as
outputs. It is a bit mask of the form (MSS_GPIO_n_MASK | MSS_GPIO_m_MASK)
where n and m are numbers identifying GPIOs. For example, (MSS_GPIO_0_MASK |
MSS_GPIO_1_MASK | MSS_GPIO_2_MASK ) specifies that the first, second and
third GPIO outputs must be set High and all other GPIO outputs set Low. The
driver provides 32 mask constants, MSS_GPIO_0_MASK to MSS_GPIO_31_MASK
inclusive, for this purpose.
@return
none.
Example 1:
Set GPIOs outputs 0 and 8 high and all other GPIO outputs low.
@code
MSS_GPIO_set_outputs( MSS_GPIO_0_MASK | MSS_GPIO_8_MASK );
@endcode
Example 2:
Set GPIOs outputs 2 and 4 low without affecting other GPIO outputs.
@code
uint32_t gpio_outputs;
gpio_outputs = MSS_GPIO_get_outputs();
gpio_outputs &= ~( MSS_GPIO_2_MASK | MSS_GPIO_4_MASK );
MSS_GPIO_set_outputs( gpio_outputs );
@endcode
@see MSS_GPIO_get_outputs()
*/
static __INLINE void
MSS_GPIO_set_outputs
(
uint32_t value
)
{
GPIO->GPIO_OUT = value;
}
/*-------------------------------------------------------------------------*//**
The MSS_GPIO_set_output() function is used to set the state of a single GPIO
port configured as an output.
Note: Using bit-band writes might be a better option than this function for
performance critical applications where the application code is not
intended to be ported to a processor other than the ARM Cortex-M3 in
SmartFusion2. The bit-band write equivalent to this function would be:
GPIO_BITBAND->GPIO_OUT[port_id] = (uint32_t)value;
@param port_id
The port_id parameter identifies the GPIO port that is to have its output
set. An enumeration item of the form MSS_GPIO_n, where n is the number of
the GPIO port, is used to identify the GPIO port. For example, MSS_GPIO_0
identifies the first GPIO port and MSS_GPIO_31 is the last one.
@param value
The value parameter specifies the desired state for the GPIO output. A value
of 0 will set the output Low and a value of 1 will set the output High.
@return
This function does not return a value.
Example:
The following call will set GPIO output 12 High, leaving all other GPIO
outputs unaffected:
@code
_GPIO_set_output(MSS_GPIO_12, 1);
@endcode
*/
void MSS_GPIO_set_output
(
mss_gpio_id_t port_id,
uint8_t value
);
/*-------------------------------------------------------------------------*//**
The MSS_GPIO_get_inputs() function is used to read the current state all GPIO
ports configured as inputs.
@return
This function returns a 32-bit unsigned integer where each bit represents
the state of a GPIO input. The least significant bit represents the state of
GPIO input 0 and the most significant bit the state of GPIO input 31.
Example:
Read and assign the current state of the GPIO outputs to a variable.
@code
uint32_t gpio_inputs;
gpio_inputs = MSS_GPIO_get_inputs();
@endcode
*/
static __INLINE uint32_t
MSS_GPIO_get_inputs( void )
{
return GPIO->GPIO_IN;
}
/*-------------------------------------------------------------------------*//**
The MSS_GPIO_get_outputs() function is used to read the current state all GPIO
ports configured as outputs.
@return
This function returns a 32-bit unsigned integer where each bit represents
the state of a GPIO output. The least significant bit represents the state
of GPIO output 0 and the most significant bit the state of GPIO output 31.
Example:
Read and assign the current state of the GPIO outputs to a variable.
@code
uint32_t gpio_outputs;
gpio_outputs = MSS_GPIO_get_outputs();
@endcode
*/
static __INLINE uint32_t
MSS_GPIO_get_outputs( void )
{
return GPIO->GPIO_OUT;
}
/*-------------------------------------------------------------------------*//**
The MSS_GPIO_drive_inout() function is used to set the output state of a
single GPIO port configured as an INOUT. An INOUT GPIO can be in one of three
states:
- High
- Low
- High impedance
An INOUT output would typically be used where several devices can drive the
state of a shared signal line. The High and Low states are equivalent to the
High and Low states of a GPIO configured as an output. The High impedance
state is used to prevent the GPIO from driving its output state onto the
signal line, while at the same time allowing the input state of the GPIO to
be read.
@param port_id
The port_id parameter identifies the GPIO port for which you want to change
the output state. An enumeration item of the form MSS_GPIO_n, where n is the
number of the GPIO port, is used to identify the GPIO port. For example,
MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one.
@param inout_state
The inout_state parameter specifies the state of the GPIO port identified by
the port_id parameter. Allowed values of type mss_gpio_inout_state_t are as
follows:
- MSS_GPIO_DRIVE_HIGH
- MSS_GPIO_DRIVE_LOW
- MSS_GPIO_HIGH_Z (High impedance)
@return
This function does not return a value.
Example:
The call to MSS_GPIO_drive_inout() below will set the GPIO 7 output to the
high impedance state.
@code
MSS_GPIO_drive_inout( MSS_GPIO_7, MSS_GPIO_HIGH_Z );
@endcode
*/
void MSS_GPIO_drive_inout
(
mss_gpio_id_t port_id,
mss_gpio_inout_state_t inout_state
);
/*-------------------------------------------------------------------------*//**
The MSS_GPIO_enable_irq() function is used to enable interrupt generation for
the specified GPIO input. Interrupts are generated based on the state of the
GPIO input and the interrupt mode configured for it by MSS_GPIO_config().
@param port_id
The port_id parameter identifies the GPIO port for which you want to enable
interrupt generation. An enumeration item of the form MSS_GPIO_n, where n is
the number of the GPIO port, is used to identify the GPIO port. For example,
MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one.
@return
This function does not return a value.
Example:
The call to MSS_GPIO_enable_irq() below will allow GPIO 8 to generate
interrupts.
@code
MSS_GPIO_enable_irq( MSS_GPIO_8 );
@endcode
*/
void MSS_GPIO_enable_irq
(
mss_gpio_id_t port_id
);
/*-------------------------------------------------------------------------*//**
The MSS_GPIO_disable_irq() function is used to disable interrupt generation
for the specified GPIO input.
@param port_id
The port_id parameter identifies the GPIO port for which you want to disable
interrupt generation. An enumeration item of the form MSS_GPIO_n, where n is
the number of the GPIO port, is used to identify the GPIO port. For example,
MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one.
@return
This function does not return a value.
Example:
The call to MSS_GPIO_disable_irq() below will prevent GPIO 8 from generating
interrupts.
@code
MSS_GPIO_disable_irq( MSS_GPIO_8 );
@endcode
*/
void MSS_GPIO_disable_irq
(
mss_gpio_id_t port_id
);
/*-------------------------------------------------------------------------*//**
The MSS_GPIO_clear_irq() function is used to clear a pending interrupt from
the specified GPIO input.
Note: The MSS_GPIO_clear_irq() function must be called as part of any GPIO
interrupt service routine (ISR) in order to prevent the same interrupt
event retriggering a call to the GPIO ISR.
@param port_id
The port_id parameter identifies the GPIO port for which you want to clear
the interrupt. An enumeration item of the form MSS_GPIO_n, where n is the
number of the GPIO port, is used to identify the GPIO port. For example,
MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one.
@return
none.
Example:
The example below demonstrates the use of the MSS_GPIO_clear_irq() function
as part of the GPIO 9 interrupt service routine.
@code
void GPIO9_IRQHandler( void )
{
do_interrupt_processing();
MSS_GPIO_clear_irq( MSS_GPIO_9 );
}
@endcode
*/
void MSS_GPIO_clear_irq
(
mss_gpio_id_t port_id
);
#ifdef __cplusplus
}
#endif
#endif /* MSS_GPIO_H_ */

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@ -0,0 +1,752 @@
/*******************************************************************************
* (c) Copyright 2012-2016 Microsemi SoC Products Group. All rights reserved.
*
* SmartFusion2 COMBLK access functions.
*
* SVN $Revision: 8345 $
* SVN $Date: 2016-03-23 11:53:04 +0530 (Wed, 23 Mar 2016) $
*/
#include "mss_comblk.h"
#include "../../CMSIS/mss_assert.h"
/*==============================================================================
*
*/
/*------------------------------------------------------------------------------
* Control register bit masks.
*/
#define CR_FLUSHOUT_MASK 0x01u
#define CR_FLUSHIN_MASK 0x02u
#define CR_SIZETX_MASK 0x04u
#define CR_ENABLE_MASK 0x10u
#define CR_LOOPBACK_MASK 0x20u
/*------------------------------------------------------------------------------
* Status and interrupt enable registers bit masks.
*/
#define TXTOKAY_MASK 0x01u
#define RCVOKAY_MASK 0x02u
#define TXOVERFLOW_MASK 0x04u
#define RXUNDERFLOW_MASK 0x08u
/*------------------------------------------------------------------------------
* DATA8 register bit masks.
*/
#define DATA8_COMMAND_MASK 0x8000u
/*------------------------------------------------------------------------------
* COMBLK driver states.
*/
#define COMBLK_IDLE 0u
#define COMBLK_TX_CMD 1u
#define COMBLK_TX_DATA 2u
#define COMBLK_WAIT_RESPONSE 3u
#define COMBLK_RX_RESPONSE 4u
#define COMBLK_TX_PAGED_DATA 5u
#define POR_DIGEST_ERROR_OPCODE 0xF1u
/*==============================================================================
* COMBLK interrupt service routine.
*/
void ComBlk_IRQHandler(void);
/*==============================================================================
* Local functions.
*/
static void abort_current_cmd(void);
static void send_cmd_opcode(uint8_t opcode);
static uint32_t fill_tx_fifo(const uint8_t * p_cmd, uint32_t cmd_size);
static void handle_tx_okay_irq(void);
static void handle_rx_okay_irq(void);
static void complete_request(uint16_t response_length);
static void process_sys_ctrl_command(uint8_t cmd_opcode);
/*==============================================================================
* Global variables:
*/
static volatile uint8_t g_comblk_cmd_opcode = 0u;
static const uint8_t * g_comblk_p_cmd = 0u;
static volatile uint16_t g_comblk_cmd_size = 0u;
static const uint8_t * g_comblk_p_data = 0u;
static volatile uint32_t g_comblk_data_size = 0u;
static uint8_t * g_comblk_p_response = 0u;
static uint16_t g_comblk_response_size = 0u;
static volatile uint16_t g_comblk_response_idx = 0u;
static comblk_completion_handler_t g_comblk_completion_handler = 0;
static uint32_t (*g_comblk_page_handler)(uint8_t const ** pp_next_page) = 0;
static volatile uint8_t g_request_in_progress = 0u;
static uint8_t g_comblk_state = COMBLK_IDLE;
static volatile comblk_async_event_handler_t g_async_event_handler = 0;
/*==============================================================================
*
*/
void MSS_COMBLK_init
(
comblk_async_event_handler_t async_event_handler,
uint8_t* p_response
)
{
/*
* Disable and clear previous interrupts.
*/
NVIC_DisableIRQ(ComBlk_IRQn);
COMBLK->INT_ENABLE = 0u;
NVIC_ClearPendingIRQ(ComBlk_IRQn);
g_async_event_handler = async_event_handler;
/*
* Initialize COMBLK driver state variables:
*/
g_request_in_progress = 0u;
g_comblk_cmd_opcode = 0u;
g_comblk_p_cmd = 0u;
g_comblk_cmd_size = 0u;
g_comblk_p_data = 0u;
g_comblk_data_size = 0u;
g_comblk_p_response = p_response;
g_comblk_response_size = 0u;
g_comblk_response_idx = 0u;
g_comblk_completion_handler = 0;
g_comblk_state = COMBLK_IDLE;
/*
* Disable loopback before enabling the MSS COMM_BLK to ensure that any
* codes waiting in the TX FIFO of the System Controller’s COMM_BLK are
* not lost.
*/
COMBLK->CONTROL &= ~CR_LOOPBACK_MASK;
COMBLK->CONTROL |= CR_ENABLE_MASK;
/*--------------------------------------------------------------------------
* Enable receive interrupt to receive asynchronous events from the system
* controller.
*/
COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
COMBLK->INT_ENABLE |= RCVOKAY_MASK;
NVIC_EnableIRQ(ComBlk_IRQn);
}
/*==============================================================================
*
*/
void MSS_COMBLK_send_cmd_with_ptr
(
uint8_t cmd_opcode,
uint32_t cmd_params_ptr,
uint8_t * p_response,
uint16_t response_size,
comblk_completion_handler_t completion_handler
)
{
uint32_t tx_okay;
/*--------------------------------------------------------------------------
* Disable and clear previous interrupts.
*/
NVIC_DisableIRQ(ComBlk_IRQn);
COMBLK->INT_ENABLE = 0u;
NVIC_ClearPendingIRQ(ComBlk_IRQn);
/*--------------------------------------------------------------------------
* Abort current command if any.
*/
abort_current_cmd();
/*--------------------------------------------------------------------------
* Initialize COMBLK driver state variables.
*/
g_request_in_progress = 1u;
g_comblk_cmd_opcode = cmd_opcode;
g_comblk_p_cmd = 0u;
g_comblk_cmd_size = 0u;
g_comblk_p_data = 0u;
g_comblk_data_size = 0u;
g_comblk_p_response = p_response;
g_comblk_response_size = response_size;
g_comblk_response_idx = 0u;
g_comblk_page_handler = 0u;
g_comblk_completion_handler = completion_handler;
/*--------------------------------------------------------------------------
* Send command opcode as a single byte write to the Tx FIFO.
*/
send_cmd_opcode(g_comblk_cmd_opcode);
/*--------------------------------------------------------------------------
* Send the command parameters pointer to the Tx FIFO as a single 4 bytes
* write to the Tx FIFO.
*/
COMBLK->CONTROL |= CR_SIZETX_MASK;
/* Wait for space to become available in Tx FIFO. */
do {
tx_okay = COMBLK->STATUS & TXTOKAY_MASK;
} while(0u == tx_okay);
/* Send command opcode. */
COMBLK->DATA32 = cmd_params_ptr;
COMBLK->CONTROL &= ~CR_SIZETX_MASK;
g_comblk_state = COMBLK_WAIT_RESPONSE;
/*--------------------------------------------------------------------------
* Enable interrupt.
*/
COMBLK->INT_ENABLE |= RCVOKAY_MASK;
NVIC_EnableIRQ(ComBlk_IRQn);
}
/*==============================================================================
*
*/
void MSS_COMBLK_send_cmd
(
const uint8_t * p_cmd,
uint16_t cmd_size,
const uint8_t * p_data,
uint32_t data_size,
uint8_t * p_response,
uint16_t response_size,
comblk_completion_handler_t completion_handler
)
{
uint32_t size_sent;
ASSERT(cmd_size > 0);
/*
* Disable and clear previous interrupts.
*/
NVIC_DisableIRQ(ComBlk_IRQn);
COMBLK->INT_ENABLE = 0u;
NVIC_ClearPendingIRQ(ComBlk_IRQn);
/*
* Abort current command if any.
*/
abort_current_cmd();
/*
* Initialize COMBLK driver state variables:
*/
g_request_in_progress = 1u;
g_comblk_cmd_opcode = p_cmd[0];
g_comblk_p_cmd = p_cmd;
g_comblk_cmd_size = cmd_size;
g_comblk_p_data = p_data;
g_comblk_data_size = data_size;
g_comblk_p_response = p_response;
g_comblk_response_size = response_size;
g_comblk_response_idx = 0u;
g_comblk_page_handler = 0u;
g_comblk_completion_handler = completion_handler;
COMBLK->INT_ENABLE |= RCVOKAY_MASK;
/*
* Fill FIFO with command.
*/
send_cmd_opcode(g_comblk_cmd_opcode);
size_sent = fill_tx_fifo(&p_cmd[1], cmd_size - 1u);
++size_sent; /* Adjust for opcode byte sent. */
if(size_sent < cmd_size)
{
g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent;
g_comblk_p_cmd = &g_comblk_p_cmd[size_sent];
g_comblk_state = COMBLK_TX_CMD;
}
else
{
g_comblk_cmd_size = 0u;
if(g_comblk_data_size > 0u)
{
g_comblk_state = COMBLK_TX_DATA;
}
else
{
g_comblk_state = COMBLK_WAIT_RESPONSE;
}
}
/*
* Enable interrupt.
*/
NVIC_EnableIRQ(ComBlk_IRQn);
}
/*==============================================================================
*
*/
void MSS_COMBLK_send_paged_cmd
(
const uint8_t * p_cmd,
uint16_t cmd_size,
uint8_t * p_response,
uint16_t response_size,
comblk_page_handler_t page_read_handler,
comblk_completion_handler_t completion_handler
)
{
uint32_t size_sent;
uint8_t irq_enable = 0u;
ASSERT(cmd_size > 0u);
/*
* Disable and clear previous interrupts.
*/
NVIC_DisableIRQ(ComBlk_IRQn);
COMBLK->INT_ENABLE = 0u;
NVIC_ClearPendingIRQ(ComBlk_IRQn);
/*
* Abort current command if any.
*/
abort_current_cmd();
/*
* Initialize COMBLK driver state variables:
*/
g_request_in_progress = 1u;
g_comblk_cmd_opcode = p_cmd[0];
g_comblk_p_cmd = p_cmd;
g_comblk_cmd_size = cmd_size;
g_comblk_p_data = 0;
g_comblk_data_size = 0u;
g_comblk_p_response = p_response;
g_comblk_response_size = response_size;
g_comblk_response_idx = 0u;
g_comblk_page_handler = page_read_handler;
g_comblk_completion_handler = completion_handler;
/*
* Fill FIFO with command.
*/
send_cmd_opcode(g_comblk_cmd_opcode);
size_sent = fill_tx_fifo(&p_cmd[1], cmd_size - 1u);
++size_sent; /* Adjust for opcode byte sent. */
if(size_sent < cmd_size)
{
g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent;
g_comblk_p_cmd = &g_comblk_p_cmd[size_sent];
g_comblk_state = COMBLK_TX_CMD;
irq_enable = TXTOKAY_MASK | RCVOKAY_MASK;
}
else
{
g_comblk_cmd_size = 0u;
g_comblk_state = COMBLK_TX_PAGED_DATA;
irq_enable = TXTOKAY_MASK | RCVOKAY_MASK;
}
/*
* Enable interrupt.
*/
COMBLK->INT_ENABLE |= irq_enable;
NVIC_EnableIRQ(ComBlk_IRQn);
}
/*==============================================================================
* COMBLK interrupt handler.
*/
void ComBlk_IRQHandler(void)
{
uint8_t status;
uint8_t tx_okay;
uint8_t rcv_okay;
status = (uint8_t)COMBLK->STATUS;
/* Mask off interrupt that are not enabled.*/
status &= COMBLK->INT_ENABLE;
rcv_okay = status & RCVOKAY_MASK;
if(rcv_okay)
{
handle_rx_okay_irq();
}
tx_okay = status & TXTOKAY_MASK;
if(tx_okay)
{
handle_tx_okay_irq();
}
}
/*==============================================================================
*
*/
static void handle_tx_okay_irq(void)
{
switch(g_comblk_state)
{
/*----------------------------------------------------------------------
* The TX_OKAY interrupt should only be enabled for states COMBLK_TX_CMD
* and COMBLK_TX_DATA.
*/
case COMBLK_TX_CMD:
if(g_comblk_cmd_size > 0u)
{
uint32_t size_sent;
size_sent = fill_tx_fifo(g_comblk_p_cmd, g_comblk_cmd_size);
if(size_sent < g_comblk_cmd_size)
{
g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent;
g_comblk_p_cmd = &g_comblk_p_cmd[size_sent];
}
else
{
g_comblk_cmd_size = 0u;
if(g_comblk_data_size > 0u)
{
g_comblk_state = COMBLK_TX_DATA;
}
else
{
g_comblk_state = COMBLK_WAIT_RESPONSE;
}
}
}
else
{
/*
* This is an invalid situation indicating a bug in the driver
* or corrupted memory.
*/
ASSERT(0);
abort_current_cmd();
}
break;
case COMBLK_TX_DATA:
if(g_comblk_data_size > 0u)
{
uint32_t size_sent;
size_sent = fill_tx_fifo(g_comblk_p_data, g_comblk_data_size);
if(size_sent < g_comblk_data_size)
{
g_comblk_data_size = g_comblk_data_size - size_sent;
g_comblk_p_data = &g_comblk_p_data[size_sent];
}
else
{
COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
g_comblk_state = COMBLK_WAIT_RESPONSE;
}
}
else
{
/*
* This is an invalid situation indicating a bug in the driver
* or corrupted memory.
*/
ASSERT(0);
abort_current_cmd();
}
break;
case COMBLK_TX_PAGED_DATA:
/*
* Read a page of data if required.
*/
if(0u == g_comblk_data_size)
{
if(g_comblk_page_handler != 0)
{
g_comblk_data_size = g_comblk_page_handler(&g_comblk_p_data);
if(0u == g_comblk_data_size)
{
COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
g_comblk_state = COMBLK_WAIT_RESPONSE;
}
}
else
{
ASSERT(0);
abort_current_cmd();
}
}
/*
* Transmit the page data or move to COMBLK_WAIT_RESPONSE state if
* no further page data could be obtained by the call to the page
* handler above.
*/
if(0u == g_comblk_data_size)
{
COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
g_comblk_state = COMBLK_WAIT_RESPONSE;
}
else
{
uint32_t size_sent;
size_sent = fill_tx_fifo(g_comblk_p_data, g_comblk_data_size);
g_comblk_data_size = g_comblk_data_size - size_sent;
g_comblk_p_data = &g_comblk_p_data[size_sent];
}
break;
/*----------------------------------------------------------------------
* The TX_OKAY interrupt should NOT be enabled for states COMBLK_IDLE,
* COMBLK_WAIT_RESPONSE and COMBLK_RX_RESPONSE.
*/
case COMBLK_IDLE:
/* Fall through */
case COMBLK_WAIT_RESPONSE:
/* Fall through */
case COMBLK_RX_RESPONSE:
/* Fall through */
default:
COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
complete_request(0u);
g_comblk_state = COMBLK_IDLE;
break;
}
}
/*==============================================================================
*
*/
static void handle_rx_okay_irq(void)
{
uint16_t data16;
uint16_t is_command;
uint8_t data8;
data16 = (uint16_t)COMBLK->DATA8;
is_command = data16 & DATA8_COMMAND_MASK;
data8 = (uint8_t)data16;
switch(g_comblk_state)
{
/*----------------------------------------------------------------------
* MSS_COMBLK_init() enables the RCV_OKAY interrupt for the COMBLK_IDLE
* state to receive the asynchronous power-on-reset from the system
* controller.
*/
case COMBLK_IDLE:
if(is_command)
{
if(data8 != POR_DIGEST_ERROR_OPCODE)
{
uint8_t rxed_opcode;
rxed_opcode = data8;
process_sys_ctrl_command(rxed_opcode);
}
else
{
g_comblk_response_idx = 0;
g_comblk_p_response[g_comblk_response_idx] = data8;
g_comblk_response_idx++;
g_comblk_p_response[g_comblk_response_idx] = 0x00u;
g_comblk_state = COMBLK_RX_RESPONSE;
}
}
break;
/*----------------------------------------------------------------------
* The RCV_OKAY interrupt should only be enabled for states
* COMBLK_WAIT_RESPONSE and COMBLK_RX_RESPONSE.
*/
case COMBLK_WAIT_RESPONSE:
if(is_command)
{
uint8_t rxed_opcode;
rxed_opcode = data8;
if(rxed_opcode == g_comblk_cmd_opcode)
{
g_comblk_response_idx = 0u;
g_comblk_p_response[g_comblk_response_idx] = rxed_opcode;
++g_comblk_response_idx;
g_comblk_state = COMBLK_RX_RESPONSE;
}
else
{
process_sys_ctrl_command(rxed_opcode);
}
}
break;
case COMBLK_RX_RESPONSE:
if(is_command)
{
uint8_t rxed_opcode;
rxed_opcode = data8;
process_sys_ctrl_command(rxed_opcode);
}
else
{
if( g_comblk_p_response[g_comblk_response_idx-1] == POR_DIGEST_ERROR_OPCODE)
{
g_comblk_p_response[g_comblk_response_idx] = data8;
process_sys_ctrl_command(g_comblk_p_response[g_comblk_response_idx-1]);
g_comblk_state = COMBLK_IDLE;
}
else
{
if(g_comblk_response_idx < g_comblk_response_size)
{
uint8_t rxed_data;
rxed_data = data8;
g_comblk_p_response[g_comblk_response_idx] = rxed_data;
++g_comblk_response_idx;
}
if(g_comblk_response_idx == g_comblk_response_size)
{
complete_request(g_comblk_response_idx);
g_comblk_state = COMBLK_IDLE;
}
}
}
break;
/*----------------------------------------------------------------------
* The RCV_OKAY interrupt should NOT be enabled for states
* COMBLK_IDLE, COMBLK_TX_CMD and COMBLK_TX_DATA.
*/
case COMBLK_TX_PAGED_DATA:
/* This is needed because when there is an error, we need to terminate loading the data */
if(!is_command)
{
g_comblk_p_response[1] = data8;
complete_request(2u);
g_comblk_state = COMBLK_IDLE;
}
else
{
uint8_t rxed_opcode;
rxed_opcode = data8;
process_sys_ctrl_command(rxed_opcode);
}
break;
case COMBLK_TX_CMD:
/* Fall through */
case COMBLK_TX_DATA:
/* Fall through */
if(is_command)
{
uint8_t rxed_opcode;
rxed_opcode = data8;
process_sys_ctrl_command(rxed_opcode);
}
break;
default:
complete_request(0u);
g_comblk_state = COMBLK_IDLE;
break;
}
}
/*==============================================================================
*
*/
static void complete_request
(
uint16_t response_length
)
{
if(g_comblk_completion_handler != 0)
{
g_comblk_completion_handler(g_comblk_p_response, response_length);
g_comblk_completion_handler = 0;
g_request_in_progress = 0u;
}
}
/*==============================================================================
*
*/
static void abort_current_cmd(void)
{
if(g_request_in_progress)
{
uint32_t flush_in_progress;
/*
* Call completion handler just in case we are in a multi threaded system
* to avoid a task lockup.
*/
complete_request(g_comblk_response_idx);
/*
* Flush the FIFOs
*/
COMBLK->CONTROL |= CR_FLUSHOUT_MASK;
do {
flush_in_progress = COMBLK->CONTROL & CR_FLUSHOUT_MASK;
} while(flush_in_progress);
}
}
/*==============================================================================
*
*/
static void send_cmd_opcode
(
uint8_t opcode
)
{
uint32_t tx_okay;
/* Set transmit FIFO to transfer bytes. */
COMBLK->CONTROL &= ~CR_SIZETX_MASK;
/* Wait for space to become available in Tx FIFO. */
do {
tx_okay = COMBLK->STATUS & TXTOKAY_MASK;
} while(0u == tx_okay);
/* Send command opcode. */
COMBLK->FRAME_START8 = opcode;
}
/*==============================================================================
*
*/
static uint32_t fill_tx_fifo
(
const uint8_t * p_cmd,
uint32_t cmd_size
)
{
volatile uint32_t tx_okay;
uint32_t size_sent;
/* Set transmit FIFO to transfer bytes. */
COMBLK->CONTROL &= ~CR_SIZETX_MASK;
size_sent = 0u;
tx_okay = COMBLK->STATUS & TXTOKAY_MASK;
while((tx_okay != 0u) && (size_sent < cmd_size))
{
COMBLK->DATA8 = p_cmd[size_sent];
++size_sent;
tx_okay = COMBLK->STATUS & TXTOKAY_MASK;
}
return size_sent;
}
/*==============================================================================
*
*/
static void process_sys_ctrl_command(uint8_t cmd_opcode)
{
if(g_async_event_handler != 0)
{
g_async_event_handler(cmd_opcode);
}
}

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/*******************************************************************************
* (c) Copyright 2012-2016 Microsemi SoC Products Group. All rights reserved.
*
* SmartFusion2 COMBLK access functions.
*
* SVN $Revision: 8345 $
* SVN $Date: 2016-03-23 11:53:04 +0530 (Wed, 23 Mar 2016) $
*/
#ifndef __MSS_COMBLK_H_
#define __MSS_COMBLK_H_ 1
#include "../../CMSIS/m2sxxx.h"
#include "mss_comblk_page_handler.h"
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------
*
*/
typedef void(*comblk_completion_handler_t)(uint8_t * p_response, uint16_t response_size);
typedef void (*comblk_async_event_handler_t)(uint8_t event_opcode);
/*------------------------------------------------------------------------------
*
*/
void MSS_COMBLK_init
(
comblk_async_event_handler_t async_event_handler,
uint8_t* p_response
);
/*------------------------------------------------------------------------------
*
*/
void MSS_COMBLK_send_cmd_with_ptr
(
uint8_t cmd_opcode,
uint32_t cmd_params_ptr,
uint8_t * p_response,
uint16_t response_size,
comblk_completion_handler_t completion_handler
);
/*------------------------------------------------------------------------------
*
*/
void MSS_COMBLK_send_cmd
(
const uint8_t * p_cmd,
uint16_t cmd_size,
const uint8_t * p_data,
uint32_t data_size,
uint8_t * p_response,
uint16_t response_size,
comblk_completion_handler_t completion_handler
);
/*------------------------------------------------------------------------------
*
*/
void MSS_COMBLK_read
(
const uint8_t * p_data,
uint16_t cmd_size,
uint8_t * p_response,
uint16_t response_size,
comblk_completion_handler_t completion_handler
);
/*------------------------------------------------------------------------------
*
*/
void MSS_COMBLK_send_paged_cmd
(
const uint8_t * p_cmd,
uint16_t cmd_size,
uint8_t * p_response,
uint16_t response_size,
comblk_page_handler_t page_read_handler,
comblk_completion_handler_t completion_handler
);
#ifdef __cplusplus
}
#endif
#endif /* __MSS_COMBLK_H_ */

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/*******************************************************************************
* (c) Copyright 2012-2016 Microsemi SoC Products Group. All rights reserved.
*
* SmartFusion2 MSS COM block driver, page handler callback function prototype.
*
* SVN $Revision: 8345 $
* SVN $Date: 2016-03-23 11:53:04 +0530 (Wed, 23 Mar 2016) $
*/
#ifndef __MSS_COMBLK_PAGE_HANDLER_H_
#define __MSS_COMBLK_PAGE_HANDLER_H_ 1
#ifdef __cplusplus
extern "C" {
#endif
/*-------------------------------------------------------------------------*//**
The comblk_page_handler_t typedef specifies the function prototype of a COMBLK
page handler callback function. This callback is used by the system services
and COMBLK drivers as part of in-system programming (ISP) to retrieve the next
page of programming information to send to the SmartFusion2 System Controller
via the COMBLK.
The COMBLK page handler must be implemented by the application layer to return
the address of the next page of programming data to be sent to the
SmartFusion2 system controller. It must return the number of bytes contained
in the next page. Returning a value of zero indicates that all programming
data has been passed to the system services/COMBLK drivers.
@code
#define PAGE_LENGTH 512
uint8_t programming_data[PROG_DATA_LENGTH];
uint32_t prog_data_index = 0;
uint32_t page_read_handler
(
uint8_t const ** pp_next_page
)
{
uint32_t returned_page_length;
uint32_t remaining_length;
*pp_next_page = &programming_data[prog_data_index];
remaining_length = PROG_DATA_LENGTH - prog_data_index
if(remaining_length > PAGE_LENGTH)
{
returned_page_length = PAGE_LENGTH;
}
else
{
returned_page_length = remaining_length;
prog_data_index = PROG_DATA_LENGTH;
}
return returned_page_length;
}
@endcode
*/
typedef uint32_t (*comblk_page_handler_t)(uint8_t const ** pp_next_page);
#ifdef __cplusplus
}
#endif
#endif /* __MSS_COMBLK_PAGE_HANDLER_H_ */

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/*******************************************************************************
* (c) Copyright 2011-2013 Microsemi SoC Products Group. All rights reserved.
*
* Register bit offsets and masks defintions for SmartFusion2 MSS MMUART.
*
* SVN $Revision: 5610 $
* SVN $Date: 2013-04-05 18:49:30 +0530 (Fri, 05 Apr 2013) $
*/
#ifndef MSS_UART_REGS_H_
#define MSS_UART_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
Register Bit definitions
*/
/* Line Control register bit definitions */
#define SB 6u /* Set break */
#define DLAB 7u /* Divisor latch access bit */
/* FIFO Control register bit definitions */
#define RXRDY_TXRDYN_EN 0u /* Enable TXRDY and RXRDY signals */
#define CLEAR_RX_FIFO 1u /* Clear receiver FIFO */
#define CLEAR_TX_FIFO 2u /* Clear transimtter FIFO */
#define RDYMODE 3u /* Mode 0 or Mode 1 for TXRDY and RXRDY */
/* Modem Control register bit definitions */
#define LOOP 4u /* Local loopback */
#define RLOOP 5u /* Remote loopback */
#define ECHO 6u /* Automatic echo */
#define RLOOP_MASK 0x6u /* Remote loopback & Automatic echo*/
/* Line Status register bit definitions */
#define DR 0u /* Data ready */
#define THRE 5u /* Transmitter holding register empty */
#define TEMT 6u /* Transitter empty */
/* Interrupt Enable register bit definitions */
#define ERBFI 0u /* Enable receiver buffer full interrupt */
#define ETBEI 1u /* Enable transmitter buffer empty interrupt */
#define ELSI 2u /* Enable line status interrupt */
#define EDSSI 3u /* Enable modem status interrupt */
/* Multimode register 0 bit definitions */
#define ELIN 3u /* Enable LIN header detection */
#define ETTG 5u /* Enable transmitter time guard */
#define ERTO 6u /* Enable receiver time-out */
#define EFBR 7u /* Enable fractional baud rate mode */
/* Multimode register 1 bit definitions */
#define E_MSB_RX 0u /* MSB / LSB first for receiver */
#define E_MSB_TX 1u /* MSB / LSB first for transmitter */
#define EIRD 2u /* Enable IrDA modem */
#define EIRX 3u /* Input polarity for IrDA modem */
#define EITX 4u /* Output polarity for IrDA modem */
#define EITP 5u /* Output pulse width for IrDA modem */
/* Multimode register 2 bit definitions */
#define EERR 0u /* Enable ERR / NACK during stop time */
#define EAFM 1u /* Enable 9-bit address flag mode */
#define EAFC 2u /* Enable address flag clear */
#define ESWM 3u /* Enable single wire half-duplex mode */
/* Multimode Interrupt Enable register and
Multimode Interrupt Identification register definitions */
#define ERTOI 0u /* Enable receiver timeout interrupt */
#define ENACKI 1u /* Enable NACK / ERR interrupt */
#define EPID_PEI 2u /* Enable PID parity error interrupt */
#define ELINBI 3u /* Enable LIN break interrupt */
#define ELINSI 4u /* Enable LIN sync detection interrupt */
#ifdef __cplusplus
}
#endif
#endif /* MSS_UART_REGS_H_ */

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/*******************************************************************************
* (c) Copyright 2012 Microsemi SoC Products Group. All rights reserved.
*
* Smartfusion2 system configuration. This file is automatically generated
* by the Libero tools. It contains the Smartfusion2 system configuration that
* was selected during the hardware configuration flow.
*
*/
#include "../../CMSIS/m2sxxx.h"
#include "../../CMSIS/sys_init_cfg_types.h"
#include "sys_config.h"
/*==============================================================================
* !!! WARNING !!!
*==============================================================================
* The project including this file must be linked so that the content of this
* file is located in internal eNVM at run time. The content of this file is
* used to configure the system prior to RAM content initialization. This means
* that the content of the data structures below will be used before the copy
* from LMA to VMA takes place. The LMA and VMA locations of the content of this
* file must be identical for the system to be seamlessly configured as part of
* the CMSIS boot process.
*/
/*==============================================================================
* Clock configuration
*/
/* No configuration data structure required. */
/*==============================================================================
* Memory remapping configuration
*/
/* TBD. */
/*==============================================================================
* MDDR configuration
*/
#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
#include "sys_config_mddr_define.h"
MDDR_TypeDef * const g_m2s_mddr_addr = (MDDR_TypeDef *)0x40020800;
const ddr_subsys_cfg_t g_m2s_mddr_subsys_config =
{
/*---------------------------------------------------------------------
* DDR Controller registers.
* All registers are 16-bit wide unless mentioned beside the definition.
*/
{
MDDR_DDRC_DYN_SOFT_RESET_CR,
MDDR_DDRC_RESERVED0,
MDDR_DDRC_DYN_REFRESH_1_CR,
MDDR_DDRC_DYN_REFRESH_2_CR,
MDDR_DDRC_DYN_POWERDOWN_CR,
MDDR_DDRC_DYN_DEBUG_CR,
MDDR_DDRC_MODE_CR,
MDDR_DDRC_ADDR_MAP_BANK_CR,
MDDR_DDRC_ECC_DATA_MASK_CR,
MDDR_DDRC_ADDR_MAP_COL_1_CR,
MDDR_DDRC_ADDR_MAP_COL_2_CR,
MDDR_DDRC_ADDR_MAP_ROW_1_CR,
MDDR_DDRC_ADDR_MAP_ROW_2_CR,
MDDR_DDRC_INIT_1_CR,
MDDR_DDRC_CKE_RSTN_CYCLES_1_CR,
MDDR_DDRC_CKE_RSTN_CYCLES_2_CR,
MDDR_DDRC_INIT_MR_CR,
MDDR_DDRC_INIT_EMR_CR,
MDDR_DDRC_INIT_EMR2_CR,
MDDR_DDRC_INIT_EMR3_CR,
MDDR_DDRC_DRAM_BANK_TIMING_PARAM_CR,
MDDR_DDRC_DRAM_RD_WR_LATENCY_CR,
MDDR_DDRC_DRAM_RD_WR_PRE_CR,
MDDR_DDRC_DRAM_MR_TIMING_PARAM_CR,
MDDR_DDRC_DRAM_RAS_TIMING_CR,
MDDR_DDRC_DRAM_RD_WR_TRNARND_TIME_CR,
MDDR_DDRC_DRAM_T_PD_CR,
MDDR_DDRC_DRAM_BANK_ACT_TIMING_CR,
MDDR_DDRC_ODT_PARAM_1_CR,
MDDR_DDRC_ODT_PARAM_2_CR,
MDDR_DDRC_ADDR_MAP_COL_3_CR,
MDDR_DDRC_MODE_REG_RD_WR_CR,
MDDR_DDRC_MODE_REG_DATA_CR,
MDDR_DDRC_PWR_SAVE_1_CR,
MDDR_DDRC_PWR_SAVE_2_CR,
MDDR_DDRC_ZQ_LONG_TIME_CR,
MDDR_DDRC_ZQ_SHORT_TIME_CR,
MDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR,
MDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR,
MDDR_DDRC_PERF_PARAM_1_CR,
MDDR_DDRC_HPR_QUEUE_PARAM_1_CR,
MDDR_DDRC_HPR_QUEUE_PARAM_2_CR,
MDDR_DDRC_LPR_QUEUE_PARAM_1_CR,
MDDR_DDRC_LPR_QUEUE_PARAM_2_CR,
MDDR_DDRC_WR_QUEUE_PARAM_CR,
MDDR_DDRC_PERF_PARAM_2_CR,
MDDR_DDRC_PERF_PARAM_3_CR,
MDDR_DDRC_DFI_RDDATA_EN_CR,
MDDR_DDRC_DFI_MIN_CTRLUPD_TIMING_CR,
MDDR_DDRC_DFI_MAX_CTRLUPD_TIMING_CR,
MDDR_DDRC_DFI_WR_LVL_CONTROL_1_CR,
MDDR_DDRC_DFI_WR_LVL_CONTROL_2_CR,
MDDR_DDRC_DFI_RD_LVL_CONTROL_1_CR,
MDDR_DDRC_DFI_RD_LVL_CONTROL_2_CR,
MDDR_DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR,
MDDR_DDRC_DYN_SOFT_RESET_ALIAS_CR,
MDDR_DDRC_AXI_FABRIC_PRI_ID_CR,
},
/*---------------------------------------------------------------------
* DDR PHY configuration registers
*/
{
MDDR_PHY_LOOPBACK_TEST_CR,
MDDR_PHY_BOARD_LOOPBACK_CR,
MDDR_PHY_CTRL_SLAVE_RATIO_CR,
MDDR_PHY_CTRL_SLAVE_FORCE_CR,
MDDR_PHY_CTRL_SLAVE_DELAY_CR,
MDDR_PHY_DATA_SLICE_IN_USE_CR,
MDDR_PHY_LVL_NUM_OF_DQ0_CR,
MDDR_PHY_DQ_OFFSET_1_CR,
MDDR_PHY_DQ_OFFSET_2_CR,
MDDR_PHY_DQ_OFFSET_3_CR,
MDDR_PHY_DIS_CALIB_RST_CR,
MDDR_PHY_DLL_LOCK_DIFF_CR,
MDDR_PHY_FIFO_WE_IN_DELAY_1_CR,
MDDR_PHY_FIFO_WE_IN_DELAY_2_CR,
MDDR_PHY_FIFO_WE_IN_DELAY_3_CR,
MDDR_PHY_FIFO_WE_IN_FORCE_CR,
MDDR_PHY_FIFO_WE_SLAVE_RATIO_1_CR,
MDDR_PHY_FIFO_WE_SLAVE_RATIO_2_CR,
MDDR_PHY_FIFO_WE_SLAVE_RATIO_3_CR,
MDDR_PHY_FIFO_WE_SLAVE_RATIO_4_CR,
MDDR_PHY_GATELVL_INIT_MODE_CR,
MDDR_PHY_GATELVL_INIT_RATIO_1_CR,
MDDR_PHY_GATELVL_INIT_RATIO_2_CR,
MDDR_PHY_GATELVL_INIT_RATIO_3_CR,
MDDR_PHY_GATELVL_INIT_RATIO_4_CR,
MDDR_PHY_LOCAL_ODT_CR,
MDDR_PHY_INVERT_CLKOUT_CR,
MDDR_PHY_RD_DQS_SLAVE_DELAY_1_CR,
MDDR_PHY_RD_DQS_SLAVE_DELAY_2_CR,
MDDR_PHY_RD_DQS_SLAVE_DELAY_3_CR,
MDDR_PHY_RD_DQS_SLAVE_FORCE_CR,
MDDR_PHY_RD_DQS_SLAVE_RATIO_1_CR,
MDDR_PHY_RD_DQS_SLAVE_RATIO_2_CR,
MDDR_PHY_RD_DQS_SLAVE_RATIO_3_CR,
MDDR_PHY_RD_DQS_SLAVE_RATIO_4_CR,
MDDR_PHY_WR_DQS_SLAVE_DELAY_1_CR,
MDDR_PHY_WR_DQS_SLAVE_DELAY_2_CR,
MDDR_PHY_WR_DQS_SLAVE_DELAY_3_CR,
MDDR_PHY_WR_DQS_SLAVE_FORCE_CR,
MDDR_PHY_WR_DQS_SLAVE_RATIO_1_CR,
MDDR_PHY_WR_DQS_SLAVE_RATIO_2_CR,
MDDR_PHY_WR_DQS_SLAVE_RATIO_3_CR,
MDDR_PHY_WR_DQS_SLAVE_RATIO_4_CR,
MDDR_PHY_WR_DATA_SLAVE_DELAY_1_CR,
MDDR_PHY_WR_DATA_SLAVE_DELAY_2_CR,
MDDR_PHY_WR_DATA_SLAVE_DELAY_3_CR,
MDDR_PHY_WR_DATA_SLAVE_FORCE_CR,
MDDR_PHY_WR_DATA_SLAVE_RATIO_1_CR,
MDDR_PHY_WR_DATA_SLAVE_RATIO_2_CR,
MDDR_PHY_WR_DATA_SLAVE_RATIO_3_CR,
MDDR_PHY_WR_DATA_SLAVE_RATIO_4_CR,
MDDR_PHY_WRLVL_INIT_MODE_CR,
MDDR_PHY_WRLVL_INIT_RATIO_1_CR,
MDDR_PHY_WRLVL_INIT_RATIO_2_CR,
MDDR_PHY_WRLVL_INIT_RATIO_3_CR,
MDDR_PHY_WRLVL_INIT_RATIO_4_CR,
MDDR_PHY_WR_RD_RL_CR,
MDDR_PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR,
MDDR_PHY_RDC_WE_TO_RE_DELAY_CR,
MDDR_PHY_USE_FIXED_RE_CR,
MDDR_PHY_USE_RANK0_DELAYS_CR,
MDDR_PHY_USE_LVL_TRNG_LEVEL_CR,
MDDR_PHY_DYN_CONFIG_CR,
MDDR_PHY_RD_WR_GATE_LVL_CR,
MDDR_PHY_DYN_RESET_CR
},
/*---------------------------------------------------------------------
* FIC-64 registers
* These registers are 16-bit wide and 32-bit aligned.
*/
{
MDDR_DDR_FIC_NB_ADDR_CR,
MDDR_DDR_FIC_NBRWB_SIZE_CR,
MDDR_DDR_FIC_WB_TIMEOUT_CR,
MDDR_DDR_FIC_HPD_SW_RW_EN_CR,
MDDR_DDR_FIC_HPD_SW_RW_INVAL_CR,
MDDR_DDR_FIC_SW_WR_ERCLR_CR,
MDDR_DDR_FIC_ERR_INT_ENABLE_CR,
MDDR_DDR_FIC_NUM_AHB_MASTERS_CR,
MDDR_DDR_FIC_LOCK_TIMEOUTVAL_1_CR,
MDDR_DDR_FIC_LOCK_TIMEOUTVAL_2_CR,
MDDR_DDR_FIC_LOCK_TIMEOUT_EN_CR
}
};
#endif
/*==============================================================================
* FDDR configuration
*/
#if MSS_SYS_FDDR_CONFIG_BY_CORTEX
#include "sys_config_fddr_define.h"
FDDR_TypeDef * const g_m2s_fddr_addr = (FDDR_TypeDef *)0x40021000;
const fddr_sysreg_t g_m2s_fddr_sysreg_subsys_config =
{
0x0001u, /* PLL_CONFIG_LOW_1 */
0x0002u, /* PLL_CONFIG_LOW_2 */
0x0003u, /* PLL_CONFIG_HIGH */
0x0004u, /* FACC_CLK_EN */
0x0005u, /* FACC_MUX_CONFIG */
0x0006u, /* FACC_DIVISOR_RATIO */
0x0007u, /* PLL_DELAY_LINE_SEL */
0x0008u, /* SOFT_RESET */
0x0009u, /* IO_CALIB */
0x000Au, /* INTERRUPT_ENABLE */
0x000Bu, /* AXI_AHB_MODE_SEL */
0x000Cu /* PHY_SELF_REF_EN */
};
const ddr_subsys_cfg_t g_m2s_fddr_subsys_config =
{
/*---------------------------------------------------------------------
* DDR Controller registers.
* All registers are 16-bit wide unless mentioned beside the definition.
*/
{
FDDR_DDRC_DYN_SOFT_RESET_CR,
FDDR_DDRC_RESERVED0,
FDDR_DDRC_DYN_REFRESH_1_CR,
FDDR_DDRC_DYN_REFRESH_2_CR,
FDDR_DDRC_DYN_POWERDOWN_CR,
FDDR_DDRC_DYN_DEBUG_CR,
FDDR_DDRC_MODE_CR,
FDDR_DDRC_ADDR_MAP_BANK_CR,
FDDR_DDRC_ECC_DATA_MASK_CR,
FDDR_DDRC_ADDR_MAP_COL_1_CR,
FDDR_DDRC_ADDR_MAP_COL_2_CR,
FDDR_DDRC_ADDR_MAP_ROW_1_CR,
FDDR_DDRC_ADDR_MAP_ROW_2_CR,
FDDR_DDRC_INIT_1_CR,
FDDR_DDRC_CKE_RSTN_CYCLES_1_CR,
FDDR_DDRC_CKE_RSTN_CYCLES_2_CR,
FDDR_DDRC_INIT_MR_CR,
FDDR_DDRC_INIT_EMR_CR,
FDDR_DDRC_INIT_EMR2_CR,
FDDR_DDRC_INIT_EMR3_CR,
FDDR_DDRC_DRAM_BANK_TIMING_PARAM_CR,
FDDR_DDRC_DRAM_RD_WR_LATENCY_CR,
FDDR_DDRC_DRAM_RD_WR_PRE_CR,
FDDR_DDRC_DRAM_MR_TIMING_PARAM_CR,
FDDR_DDRC_DRAM_RAS_TIMING_CR,
FDDR_DDRC_DRAM_RD_WR_TRNARND_TIME_CR,
FDDR_DDRC_DRAM_T_PD_CR,
FDDR_DDRC_DRAM_BANK_ACT_TIMING_CR,
FDDR_DDRC_ODT_PARAM_1_CR,
FDDR_DDRC_ODT_PARAM_2_CR,
FDDR_DDRC_ADDR_MAP_COL_3_CR,
FDDR_DDRC_MODE_REG_RD_WR_CR,
FDDR_DDRC_MODE_REG_DATA_CR,
FDDR_DDRC_PWR_SAVE_1_CR,
FDDR_DDRC_PWR_SAVE_2_CR,
FDDR_DDRC_ZQ_LONG_TIME_CR,
FDDR_DDRC_ZQ_SHORT_TIME_CR,
FDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR,
FDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR,
FDDR_DDRC_PERF_PARAM_1_CR,
FDDR_DDRC_HPR_QUEUE_PARAM_1_CR,
FDDR_DDRC_HPR_QUEUE_PARAM_2_CR,
FDDR_DDRC_LPR_QUEUE_PARAM_1_CR,
FDDR_DDRC_LPR_QUEUE_PARAM_2_CR,
FDDR_DDRC_WR_QUEUE_PARAM_CR,
FDDR_DDRC_PERF_PARAM_2_CR,
FDDR_DDRC_PERF_PARAM_3_CR,
FDDR_DDRC_DFI_RDDATA_EN_CR,
FDDR_DDRC_DFI_MIN_CTRLUPD_TIMING_CR,
FDDR_DDRC_DFI_MAX_CTRLUPD_TIMING_CR,
FDDR_DDRC_DFI_WR_LVL_CONTROL_1_CR,
FDDR_DDRC_DFI_WR_LVL_CONTROL_2_CR,
FDDR_DDRC_DFI_RD_LVL_CONTROL_1_CR,
FDDR_DDRC_DFI_RD_LVL_CONTROL_2_CR,
FDDR_DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR,
FDDR_DDRC_DYN_SOFT_RESET_ALIAS_CR,
FDDR_DDRC_AXI_FABRIC_PRI_ID_CR
},
/*---------------------------------------------------------------------
* DDR PHY configuration registers
*/
{
FDDR_PHY_LOOPBACK_TEST_CR,
FDDR_PHY_BOARD_LOOPBACK_CR,
FDDR_PHY_CTRL_SLAVE_RATIO_CR,
FDDR_PHY_CTRL_SLAVE_FORCE_CR,
FDDR_PHY_CTRL_SLAVE_DELAY_CR,
FDDR_PHY_DATA_SLICE_IN_USE_CR,
FDDR_PHY_LVL_NUM_OF_DQ0_CR,
FDDR_PHY_DQ_OFFSET_1_CR,
FDDR_PHY_DQ_OFFSET_2_CR,
FDDR_PHY_DQ_OFFSET_3_CR,
FDDR_PHY_DIS_CALIB_RST_CR,
FDDR_PHY_DLL_LOCK_DIFF_CR,
FDDR_PHY_FIFO_WE_IN_DELAY_1_CR,
FDDR_PHY_FIFO_WE_IN_DELAY_2_CR,
FDDR_PHY_FIFO_WE_IN_DELAY_3_CR,
FDDR_PHY_FIFO_WE_IN_FORCE_CR,
FDDR_PHY_FIFO_WE_SLAVE_RATIO_1_CR,
FDDR_PHY_FIFO_WE_SLAVE_RATIO_2_CR,
FDDR_PHY_FIFO_WE_SLAVE_RATIO_3_CR,
FDDR_PHY_FIFO_WE_SLAVE_RATIO_4_CR,
FDDR_PHY_GATELVL_INIT_MODE_CR,
FDDR_PHY_GATELVL_INIT_RATIO_1_CR,
FDDR_PHY_GATELVL_INIT_RATIO_2_CR,
FDDR_PHY_GATELVL_INIT_RATIO_3_CR,
FDDR_PHY_GATELVL_INIT_RATIO_4_CR,
FDDR_PHY_LOCAL_ODT_CR,
FDDR_PHY_INVERT_CLKOUT_CR,
FDDR_PHY_RD_DQS_SLAVE_DELAY_1_CR,
FDDR_PHY_RD_DQS_SLAVE_DELAY_2_CR,
FDDR_PHY_RD_DQS_SLAVE_DELAY_3_CR,
FDDR_PHY_RD_DQS_SLAVE_FORCE_CR,
FDDR_PHY_RD_DQS_SLAVE_RATIO_1_CR,
FDDR_PHY_RD_DQS_SLAVE_RATIO_2_CR,
FDDR_PHY_RD_DQS_SLAVE_RATIO_3_CR,
FDDR_PHY_RD_DQS_SLAVE_RATIO_4_CR,
FDDR_PHY_WR_DQS_SLAVE_DELAY_1_CR,
FDDR_PHY_WR_DQS_SLAVE_DELAY_2_CR,
FDDR_PHY_WR_DQS_SLAVE_DELAY_3_CR,
FDDR_PHY_WR_DQS_SLAVE_FORCE_CR,
FDDR_PHY_WR_DQS_SLAVE_RATIO_1_CR,
FDDR_PHY_WR_DQS_SLAVE_RATIO_2_CR,
FDDR_PHY_WR_DQS_SLAVE_RATIO_3_CR,
FDDR_PHY_WR_DQS_SLAVE_RATIO_4_CR,
FDDR_PHY_WR_DATA_SLAVE_DELAY_1_CR,
FDDR_PHY_WR_DATA_SLAVE_DELAY_2_CR,
FDDR_PHY_WR_DATA_SLAVE_DELAY_3_CR,
FDDR_PHY_WR_DATA_SLAVE_FORCE_CR,
FDDR_PHY_WR_DATA_SLAVE_RATIO_1_CR,
FDDR_PHY_WR_DATA_SLAVE_RATIO_2_CR,
FDDR_PHY_WR_DATA_SLAVE_RATIO_3_CR,
FDDR_PHY_WR_DATA_SLAVE_RATIO_4_CR,
FDDR_PHY_WRLVL_INIT_MODE_CR,
FDDR_PHY_WRLVL_INIT_RATIO_1_CR,
FDDR_PHY_WRLVL_INIT_RATIO_2_CR,
FDDR_PHY_WRLVL_INIT_RATIO_3_CR,
FDDR_PHY_WRLVL_INIT_RATIO_4_CR,
FDDR_PHY_WR_RD_RL_CR,
FDDR_PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR,
FDDR_PHY_RDC_WE_TO_RE_DELAY_CR,
FDDR_PHY_USE_FIXED_RE_CR,
FDDR_PHY_USE_RANK0_DELAYS_CR,
FDDR_PHY_USE_LVL_TRNG_LEVEL_CR,
FDDR_PHY_DYN_CONFIG_CR,
FDDR_PHY_RD_WR_GATE_LVL_CR,
FDDR_PHY_DYN_RESET_CR,
},
/*---------------------------------------------------------------------
* FIC-64 registers
* These registers are 16-bit wide and 32-bit aligned.
*/
{
FDDR_DDR_FIC_NB_ADDR_CR,
FDDR_DDR_FIC_NBRWB_SIZE_CR,
FDDR_DDR_FIC_WB_TIMEOUT_CR,
FDDR_DDR_FIC_HPD_SW_RW_EN_CR,
FDDR_DDR_FIC_HPD_SW_RW_INVAL_CR,
FDDR_DDR_FIC_SW_WR_ERCLR_CR,
FDDR_DDR_FIC_ERR_INT_ENABLE_CR,
FDDR_DDR_FIC_NUM_AHB_MASTERS_CR,
FDDR_DDR_FIC_LOCK_TIMEOUTVAL_1_CR,
FDDR_DDR_FIC_LOCK_TIMEOUTVAL_2_CR,
FDDR_DDR_FIC_LOCK_TIMEOUT_EN_CR
}
};
#endif

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/*******************************************************************************
* (c) Copyright 2012 Microsemi SoC Products Group. All rights reserved.
*
* Smartfusion2 system configuration. This file is automatically generated
* by the Libero tools.
*
*/
#ifndef MSS_SYSTEM_CONFIGURATION
#define MSS_SYSTEM_CONFIGURATION
/*==============================================================================
* Clock configuration
*/
#include "sys_config_mss_clocks.h"
/*==============================================================================
* Memory remapping configuration
*/
/* TBD */
/*==============================================================================
* FACC_INIT (Cortex-M3 runs the FACC INIT procedure)
* Only set to 1 for design targeting the M2S050T_ES device
*/
#define MSS_SYS_FACC_INIT_BY_CORTEX 0
/*==============================================================================
* MDDR configuration
*/
#define MSS_SYS_MDDR_CONFIG_BY_CORTEX 0
/*==============================================================================
* FDDR configuration
*/
#define MSS_SYS_FDDR_CONFIG_BY_CORTEX 0
/*==============================================================================
* SERDES Interface configuration
*/
#define MSS_SYS_SERDES_0_CONFIG_BY_CORTEX 0
#if MSS_SYS_SERDES_0_CONFIG_BY_CORTEX
#include "sys_config_SERDESIF_0.h"
#endif
#define MSS_SYS_SERDES_1_CONFIG_BY_CORTEX 0
#if MSS_SYS_SERDES_1_CONFIG_BY_CORTEX
#include "sys_config_SERDESIF_1.h"
#endif
#define MSS_SYS_SERDES_2_CONFIG_BY_CORTEX 0
#if MSS_SYS_SERDES_2_CONFIG_BY_CORTEX
#include "sys_config_SERDESIF_2.h"
#endif
#define MSS_SYS_SERDES_3_CONFIG_BY_CORTEX 0
#if MSS_SYS_SERDES_3_CONFIG_BY_CORTEX
#include "sys_config_SERDESIF_3.h"
#endif
/*==============================================================================
* Cache configuration
*/
#define MSS_SYS_CACHE_CONFIG_BY_CORTEX 0
#endif /* MSS_SYSTEM_CONFIGURATION */

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/*=============================================================*/
/* Created by Microsemi SmartDesign Fri May 22 15:04:18 2020 */
/* */
/* Warning: Do not modify this file, it may lead to unexpected */
/* functional failures in your design. */
/* */
/*=============================================================*/
#ifndef SYS_CONFIG_MSS_CLOCKS
#define SYS_CONFIG_MSS_CLOCKS
#define MSS_SYS_M3_CLK_FREQ 100000000u
#define MSS_SYS_MDDR_CLK_FREQ 100000000u
#define MSS_SYS_APB_0_CLK_FREQ 100000000u
#define MSS_SYS_APB_1_CLK_FREQ 100000000u
#define MSS_SYS_APB_2_CLK_FREQ 25000000u
#define MSS_SYS_FIC_0_CLK_FREQ 100000000u
#define MSS_SYS_FIC_1_CLK_FREQ 100000000u
#define MSS_SYS_FIC64_CLK_FREQ 100000000u
#endif /* SYS_CONFIG_MSS_CLOCKS */

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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00040000 { ; load region size_region
ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00010000 { ; RW data
.ANY (+RW +ZI)
}
}

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<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
<events>
</events>
</component_viewer>

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bsp/smartfusion2/user/JLinkSettings.ini Normal file
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[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="ARM7"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

1
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91
bsp/smartfusion2/user/board.c Normal file
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/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-07-24 Tanek the first version
* 2018-11-12 Ernest Chen modify copyright
*/
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>
#define _SCB_BASE (0xE000E010UL)
#define _SYSTICK_CTRL (*(rt_uint32_t *)(_SCB_BASE + 0x0))
#define _SYSTICK_LOAD (*(rt_uint32_t *)(_SCB_BASE + 0x4))
#define _SYSTICK_VAL (*(rt_uint32_t *)(_SCB_BASE + 0x8))
#define _SYSTICK_CALIB (*(rt_uint32_t *)(_SCB_BASE + 0xC))
#define _SYSTICK_PRI (*(rt_uint8_t *)(0xE000ED23UL))
// Updates the variable SystemCoreClock and must be called
// whenever the core clock is changed during program execution.
extern void SystemCoreClockUpdate(void);
// Holds the system core clock, which is the system clock
// frequency supplied to the SysTick timer and the processor
// core clock.
extern uint32_t SystemCoreClock;
static uint32_t _SysTick_Config(rt_uint32_t ticks)
{
if ((ticks - 1) > 0xFFFFFF)
{
return 1;
}
_SYSTICK_LOAD = ticks - 1;
_SYSTICK_PRI = 0xFF;
_SYSTICK_VAL = 0;
_SYSTICK_CTRL = 0x07;
return 0;
}
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
#define RT_HEAP_SIZE 1024
static uint32_t rt_heap[RT_HEAP_SIZE]; // heap default size: 4K(1024 * 4)
RT_WEAK void *rt_heap_begin_get(void)
{
return rt_heap;
}
RT_WEAK void *rt_heap_end_get(void)
{
return rt_heap + RT_HEAP_SIZE;
}
#endif
/* This function will initial your board. */
void rt_hw_board_init()
{
/* System Clock Update */
SystemCoreClockUpdate();
/* System Tick Configuration */
_SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
/* Call components board initial (use INIT_BOARD_EXPORT()) */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
//#ifdef RT_USING_CONSOLE
// rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
//#endif
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
#endif
}
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}

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#include "config.h"
mss_uart_instance_t * const gp_my_uart0 = &g_mss_uart0;
/* gpio and uart0 initialization */
void boardInit(void)
{
/* mss gpio init */
MSS_GPIO_init();
MSS_GPIO_config(MSS_GPIO_0, MSS_GPIO_OUTPUT_MODE);
MSS_GPIO_config(MSS_GPIO_1, MSS_GPIO_OUTPUT_MODE);
/* mss uart0 init: 115200, 8, no, 1 */
MSS_UART_init(gp_my_uart0, MSS_UART_115200_BAUD,
MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
}
INIT_BOARD_EXPORT(boardInit);
/* mss uart0 transmit one byte data */
void MSS_UART_polled_tx_byte(mss_uart_instance_t *this_uart, const uint8_t byte)
{
uint32_t tx_ready;
do {
tx_ready = gp_my_uart0->hw_reg->LSR & 0x20u;
} while(!tx_ready);
gp_my_uart0->hw_reg->THR = byte;
}
/* docking finish component */
void rt_hw_console_output(const char *str)
{
while(*str != '\0')
{
if(*str == '\n')
MSS_UART_polled_tx_byte(gp_my_uart0, '\r');
MSS_UART_polled_tx_byte(gp_my_uart0, *str++);
while(!MSS_UART_tx_complete(&g_mss_uart0));
}
}
/* docking finish component */
char rt_hw_console_getchar(void)
{
char dat;
uint8_t rx_size;
do {
rx_size = MSS_UART_get_rx(gp_my_uart0, (uint8_t *)&dat, 1);
} while(0u == rx_size);
return dat;
}
/* custom finish command */
extern uint32_t SystemCoreClock;
void sayHello(void)
{
rt_kprintf("Hello RT-Thread! By SmartFusion2 M2S010\r\n");
rt_kprintf("MSS System Core Clock: %d\r\n", SystemCoreClock);
}
MSH_CMD_EXPORT(sayHello, "say hello to console");

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#ifndef __INIT_H__
#define __INIT_H__
#include "mss_gpio.h"
#include "mss_uart.h"
#include <rthw.h>
#include <rtthread.h>
void boardInit(void);
void MSS_UART_polled_tx_byte(mss_uart_instance_t *this_uart, const uint8_t byte);
void rt_hw_console_output(const char *str);
char rt_hw_console_getchar(void);
void sayHello(void);
#endif

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bsp/smartfusion2/user/main.c Normal file
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#include "config.h"
#include <rthw.h>
#include <rtthread.h>
#define LED0_PIN MSS_GPIO_0
#define LED1_PIN MSS_GPIO_1
int main(void)
{
int count = 0;
while(count++)
{
MSS_GPIO_set_output(LED0_PIN, 1);
MSS_GPIO_set_output(LED1_PIN, 1);
rt_thread_mdelay(500);
MSS_GPIO_set_output(LED0_PIN, 0);
MSS_GPIO_set_output(LED1_PIN, 0);
rt_thread_mdelay(500);
}
return RT_EOK;
}

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>project</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>100000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>..\OBJ\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
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<OutputName>project</OutputName>
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<FilePath>..\..\..\src\timer.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>RT-Thread/Libcpu</GroupName>
<Files>
<File>
<FileName>cpuport.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\libcpu\arm\cortex-m3\cpuport.c</FilePath>
</File>
<File>
<FileName>context_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\libcpu\arm\cortex-m3\context_rvds.S</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>RT-Thread/Finsh</GroupName>
<Files>
<File>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
</File>
<File>
<FileName>finsh_compiler.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\finsh_compiler.c</FilePath>
</File>
<File>
<FileName>finsh_error.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\finsh_error.c</FilePath>
</File>
<File>
<FileName>finsh_heap.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\finsh_heap.c</FilePath>
</File>
<File>
<FileName>finsh_init.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\finsh_init.c</FilePath>
</File>
<File>
<FileName>finsh_node.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\finsh_node.c</FilePath>
</File>
<File>
<FileName>finsh_ops.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\finsh_ops.c</FilePath>
</File>
<File>
<FileName>finsh_parser.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\finsh_parser.c</FilePath>
</File>
<File>
<FileName>finsh_token.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\finsh_token.c</FilePath>
</File>
<File>
<FileName>finsh_var.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\finsh_var.c</FilePath>
</File>
<File>
<FileName>finsh_vm.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\finsh_vm.c</FilePath>
</File>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh.c</FilePath>
</File>
<File>
<FileName>msh_file.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh_file.c</FilePath>
</File>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
</File>
<File>
<FileName>symbol.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\symbol.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files>
<file attr="config" category="source" name="bsp\board.c" version="3.1.3">
<instance index="0" removed="1">RTE\RTOS\board.c</instance>
<component Cbundle="RT-Thread" Cclass="RTOS" Cgroup="kernel" Cvendor="RealThread" Cversion="3.1.3" condition="CMSIS Core with RTOS"/>
<package license="License.txt" name="RT-Thread" schemaVersion="1.4" supportContact="https://www.rt-thread.org" url="https://www.rt-thread.org/download/mdk/" vendor="RealThread" version="3.1.3"/>
<targetInfos/>
</file>
<file attr="config" category="header" name="bsp\rtconfig.h" version="3.1.3">
<instance index="0" removed="1">RTE\RTOS\rtconfig.h</instance>
<component Cbundle="RT-Thread" Cclass="RTOS" Cgroup="kernel" Cvendor="RealThread" Cversion="3.1.3" condition="CMSIS Core with RTOS"/>
<package license="License.txt" name="RT-Thread" schemaVersion="1.4" supportContact="https://www.rt-thread.org" url="https://www.rt-thread.org/download/mdk/" vendor="RealThread" version="3.1.3"/>
<targetInfos/>
</file>
</files>
</RTE>
</Project>

160
bsp/smartfusion2/user/rtconfig.h Normal file
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@ -0,0 +1,160 @@
/* RT-Thread config file */
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
#if defined(__CC_ARM) || defined(__CLANG_ARM)
//#include "RTE_Components.h"
#define RT_USING_FINSH
#if defined(RTE_USING_FINSH)
#define RT_USING_FINSH
#endif //RTE_USING_FINSH
#endif //(__CC_ARM) || (__CLANG_ARM)
// <<< Use Configuration Wizard in Context Menu >>>
// <h>Basic Configuration
// <o>Maximal level of thread priority <8-256>
// <i>Default: 32
#define RT_THREAD_PRIORITY_MAX 8
// <o>OS tick per second
// <i>Default: 1000 (1ms)
#define RT_TICK_PER_SECOND 1000
// <o>Alignment size for CPU architecture data access
// <i>Default: 4
#define RT_ALIGN_SIZE 4
// <o>the max length of object name<2-16>
// <i>Default: 8
#define RT_NAME_MAX 8
// <c1>Using RT-Thread components initialization
// <i>Using RT-Thread components initialization
#define RT_USING_COMPONENTS_INIT
// </c>
#define RT_USING_USER_MAIN
//#define RT_USING_DEVICE
//#define RT_USING_PIN
//#define RT_USING_SERIAL
//#define RT_CONSOLE_DEVICE_NAME "uart0"
//#define RT_CONSOLEBUF_SIZE 128
// <o>the stack size of main thread<1-4086>
// <i>Default: 512
#define RT_MAIN_THREAD_STACK_SIZE 512
// </h>
// <h>Debug Configuration
// <c1>enable kernel debug configuration
// <i>Default: enable kernel debug configuration
//#define RT_DEBUG
// </c>
// <o>enable components initialization debug configuration<0-1>
// <i>Default: 0
#define RT_DEBUG_INIT 0
// <c1>thread stack over flow detect
// <i> Diable Thread stack over flow detect
//#define RT_USING_OVERFLOW_CHECK
// </c>
// </h>
// <h>Hook Configuration
// <c1>using hook
// <i>using hook
//#define RT_USING_HOOK
// </c>
// <c1>using idle hook
// <i>using idle hook
//#define RT_USING_IDLE_HOOK
// </c>
// </h>
// <e>Software timers Configuration
// <i> Enables user timers
#define RT_USING_TIMER_SOFT 0
#if RT_USING_TIMER_SOFT == 0
#undef RT_USING_TIMER_SOFT
#endif
// <o>The priority level of timer thread <0-31>
// <i>Default: 4
#define RT_TIMER_THREAD_PRIO 4
// <o>The stack size of timer thread <0-8192>
// <i>Default: 512
#define RT_TIMER_THREAD_STACK_SIZE 512
// </e>
// <h>IPC(Inter-process communication) Configuration
// <c1>Using Semaphore
// <i>Using Semaphore
#define RT_USING_SEMAPHORE
// </c>
// <c1>Using Mutex
// <i>Using Mutex
#define RT_USING_MUTEX
// </c>
// <c1>Using Event
// <i>Using Event
#define RT_USING_EVENT
// </c>
// <c1>Using MailBox
// <i>Using MailBox
#define RT_USING_MAILBOX
// </c>
// <c1>Using Message Queue
// <i>Using Message Queue
#define RT_USING_MESSAGEQUEUE
// </c>
// </h>
// <h>Memory Management Configuration
// <c1>Dynamic Heap Management
// <i>Dynamic Heap Management
#define RT_USING_HEAP
// </c>
// <c1>using small memory
// <i>using small memory
#define RT_USING_SMALL_MEM
// </c>
// <c1>using tiny size of memory
// <i>using tiny size of memory
//#define RT_USING_TINY_SIZE
// </c>
// </h>
// <h>Console Configuration
// <c1>Using console
// <i>Using console
#define RT_USING_CONSOLE
// </c>
// <o>the buffer size of console <1-1024>
// <i>the buffer size of console
// <i>Default: 128 (128Byte)
#define RT_CONSOLEBUF_SIZE 128
// </h>
#if defined(RT_USING_FINSH)
#define FINSH_USING_MSH
#define FINSH_USING_MSH_ONLY
// <h>Finsh Configuration
// <o>the priority of finsh thread <1-7>
// <i>the priority of finsh thread
// <i>Default: 6
#define __FINSH_THREAD_PRIORITY 5
#define FINSH_THREAD_PRIORITY (RT_THREAD_PRIORITY_MAX / 8 * __FINSH_THREAD_PRIORITY + 1)
// <o>the stack of finsh thread <1-4096>
// <i>the stack of finsh thread
// <i>Default: 4096 (4096Byte)
#define FINSH_THREAD_STACK_SIZE 1024
// <o>the history lines of finsh thread <1-32>
// <i>the history lines of finsh thread
// <i>Default: 5
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
// </h>
#endif
// <<< end of configuration section >>>
#endif