diff --git a/bsp/wch/arm/ch32f103c8-core/applications/main.c b/bsp/wch/arm/ch32f103c8-core/applications/main.c index 1d9e84e4c6..b991329cc0 100644 --- a/bsp/wch/arm/ch32f103c8-core/applications/main.c +++ b/bsp/wch/arm/ch32f103c8-core/applications/main.c @@ -14,5 +14,5 @@ int main(void) { - return RT_EOK; + return RT_EOK; } diff --git a/bsp/wch/arm/ch32f103c8-core/board/board.c b/bsp/wch/arm/ch32f103c8-core/board/board.c index 329f65ec94..c0494597a4 100644 --- a/bsp/wch/arm/ch32f103c8-core/board/board.c +++ b/bsp/wch/arm/ch32f103c8-core/board/board.c @@ -134,7 +134,7 @@ rt_uint32_t ch32f1_spi_clock_get(SPI_TypeDef *spix) return RCC_Clocks.PCLK1_Frequency; } - return RCC_Clocks.PCLK2_Frequency; + return RCC_Clocks.PCLK2_Frequency; } void ch32f1_i2c_clock_and_io_init(I2C_TypeDef *i2cx) diff --git a/bsp/wch/arm/ch32f103c8-core/board/ch32f10x_conf.h b/bsp/wch/arm/ch32f103c8-core/board/ch32f10x_conf.h index 5f7cf0c760..c141421413 100644 --- a/bsp/wch/arm/ch32f103c8-core/board/ch32f10x_conf.h +++ b/bsp/wch/arm/ch32f103c8-core/board/ch32f10x_conf.h @@ -4,8 +4,8 @@ * Version : V1.0.0 * Date : 2019/10/15 * Description : Library configuration file. -*******************************************************************************/ -#ifndef __CH32F10x_CONF_H +*******************************************************************************/ +#ifndef __CH32F10x_CONF_H #define __CH32F10x_CONF_H #include "ch32f10x_adc.h" @@ -27,7 +27,7 @@ #include "ch32f10x_tim.h" #include "ch32f10x_usart.h" #include "ch32f10x_wwdg.h" -#include "ch32f10x_misc.h" +#include "ch32f10x_misc.h" #endif /* __CH32F10x_CONF_H */ diff --git a/bsp/wch/arm/ch32f103c8-core/board/system_ch32f10x.c b/bsp/wch/arm/ch32f103c8-core/board/system_ch32f10x.c index a16a24041d..20856b686a 100644 --- a/bsp/wch/arm/ch32f103c8-core/board/system_ch32f10x.c +++ b/bsp/wch/arm/ch32f103c8-core/board/system_ch32f10x.c @@ -7,15 +7,15 @@ ****************************************************************************************/ #include "ch32f10x.h" -/* - * Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +/* + * Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after * reset the HSI is used as SYSCLK source). - * If none of the define below is enabled, the HSI is used as System clock source. + * If none of the define below is enabled, the HSI is used as System clock source. */ -// #define SYSCLK_FREQ_HSE HSE_VALUE -/* #define SYSCLK_FREQ_24MHz 24000000 */ -// #define SYSCLK_FREQ_48MHz 48000000 -/* #define SYSCLK_FREQ_56MHz 56000000 */ +// #define SYSCLK_FREQ_HSE HSE_VALUE +/* #define SYSCLK_FREQ_24MHz 24000000 */ +// #define SYSCLK_FREQ_48MHz 48000000 +/* #define SYSCLK_FREQ_56MHz 56000000 */ #define SYSCLK_FREQ_72MHz 72000000 @@ -23,10 +23,10 @@ /* #define VECT_TAB_SRAM */ /* Vector Table base offset field This value must be a multiple of 0x200 */ -#define VECT_TAB_OFFSET 0x0 +#define VECT_TAB_OFFSET 0x0 -/* Clock Definitions */ +/* Clock Definitions */ #ifdef SYSCLK_FREQ_HSE uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ #elif defined SYSCLK_FREQ_24MHz @@ -54,19 +54,19 @@ static void SetSysClock(void); #elif defined SYSCLK_FREQ_48MHz static void SetSysClockTo48(void); #elif defined SYSCLK_FREQ_56MHz - static void SetSysClockTo56(void); + static void SetSysClockTo56(void); #elif defined SYSCLK_FREQ_72MHz static void SetSysClockTo72(void); #endif #ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); + static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM */ /****************************************************************************************** * Function Name : SystemInit -* Description : Setup the microcontroller system Initialize the Embedded Flash Interface, +* Description : Setup the microcontroller system Initialize the Embedded Flash Interface, * the PLL and update the SystemCoreClock variable. * Input : None * Return : None @@ -78,14 +78,14 @@ void SystemInit (void) RCC->CTLR &= (uint32_t)0xFEF6FFFF; RCC->CTLR &= (uint32_t)0xFFFBFFFF; RCC->CFGR0 &= (uint32_t)0xFF80FFFF; - RCC->INTR = 0x009F0000; + RCC->INTR = 0x009F0000; SetSysClock(); - + #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif +#endif } @@ -98,27 +98,27 @@ void SystemInit (void) void SystemCoreClockUpdate (void) { uint32_t tmp = 0, pllmull = 0, pllsource = 0; - + tmp = RCC->CFGR0 & RCC_SWS; - + switch (tmp) { case 0x00: SystemCoreClock = HSI_VALUE; break; - case 0x04: + case 0x04: SystemCoreClock = HSE_VALUE; break; - case 0x08: + case 0x08: pllmull = RCC->CFGR0 & RCC_PLLMULL; - pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllsource = RCC->CFGR0 & RCC_PLLSRC; pllmull = ( pllmull >> 18) + 2; if (pllsource == 0x00) { SystemCoreClock = (HSI_VALUE >> 1) * pllmull; } else - { + { if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) { SystemCoreClock = (HSE_VALUE >> 1) * pllmull; @@ -133,15 +133,15 @@ void SystemCoreClockUpdate (void) SystemCoreClock = HSI_VALUE; break; } - + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; - SystemCoreClock >>= tmp; + SystemCoreClock >>= tmp; } /****************************************************************************************** * Function Name : SetSysClock -* Description : Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. +* Description : Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. * Input : None * Return : None *******************************************************************************************/ @@ -154,14 +154,14 @@ static void SetSysClock(void) #elif defined SYSCLK_FREQ_48MHz SetSysClockTo48(); #elif defined SYSCLK_FREQ_56MHz - SetSysClockTo56(); + SetSysClockTo56(); #elif defined SYSCLK_FREQ_72MHz SetSysClockTo72(); #endif - + /* If none of the define above is enabled, the HSI is used as System clock - * source (default after reset) - */ + * source (default after reset) + */ } @@ -169,27 +169,27 @@ static void SetSysClock(void) /****************************************************************************************** * Function Name : SystemInit_ExtMemCtl -* Description : Setup the external memory controller. +* Description : Setup the external memory controller. * Input : None * Return : None *******************************************************************************************/ -void SystemInit_ExtMemCtl(void) +void SystemInit_ExtMemCtl(void) { RCC->AHBENR = 0x00000114; RCC->APB2ENR = 0x000001E0; - - GPIOD->CRL = 0x44BB44BB; + + GPIOD->CRL = 0x44BB44BB; GPIOD->CRH = 0xBBBBBBBB; - GPIOE->CRL = 0xB44444BB; + GPIOE->CRL = 0xB44444BB; GPIOE->CRH = 0xBBBBBBBB; - GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRL = 0x44BBBBBB; GPIOF->CRH = 0xBBBB4444; - GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRL = 0x44BBBBBB; GPIOG->CRH = 0x44444B44; - + FSMC_Bank1->BTCR[4] = 0x00001011; FSMC_Bank1->BTCR[5] = 0x00000200; } @@ -207,15 +207,15 @@ void SystemInit_ExtMemCtl(void) static void SetSysClockToHSE(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - + + RCC->CTLR |= ((uint32_t)RCC_HSEON); - + /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; + StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CTLR & RCC_HSERDY) != RESET) @@ -225,7 +225,7 @@ static void SetSysClockToHSE(void) else { HSEStatus = (uint32_t)0x00; - } + } if (HSEStatus == (uint32_t)0x01) { @@ -233,17 +233,17 @@ static void SetSysClockToHSE(void) /* Flash 0 wait state */ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; - - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; - + /* Select HSE as system clock source */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; /* Wait till HSE is used as system clock source */ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) @@ -251,11 +251,11 @@ static void SetSysClockToHSE(void) } } else - { - /* If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } } #elif defined SYSCLK_FREQ_24MHz @@ -269,14 +269,14 @@ static void SetSysClockToHSE(void) static void SetSysClockTo24(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - + RCC->CTLR |= ((uint32_t)RCC_HSEON); - + /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; + StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CTLR & RCC_HSERDY) != RESET) @@ -286,7 +286,7 @@ static void SetSysClockTo24(void) else { HSEStatus = (uint32_t)0x00; - } + } if (HSEStatus == (uint32_t)0x01) { /* Enable Prefetch Buffer */ @@ -294,12 +294,12 @@ static void SetSysClockTo24(void) /* Flash 0 wait state */ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; @@ -307,25 +307,25 @@ static void SetSysClockTo24(void) RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3); /* Enable PLL */ RCC->CTLR |= RCC_PLLON; - + /* Wait till PLL is ready */ while((RCC->CTLR & RCC_PLLRDY) == 0) { } /* Select PLL as system clock source */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) { } } else - { - /* If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } } @@ -340,14 +340,14 @@ static void SetSysClockTo24(void) static void SetSysClockTo48(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - + + RCC->CTLR |= ((uint32_t)RCC_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; + StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CTLR & RCC_HSERDY) != RESET) @@ -357,7 +357,7 @@ static void SetSysClockTo48(void) else { HSEStatus = (uint32_t)0x00; - } + } if (HSEStatus == (uint32_t)0x01) { @@ -366,12 +366,12 @@ static void SetSysClockTo48(void) /* Flash 1 wait state */ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; - + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; + /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; @@ -387,19 +387,19 @@ static void SetSysClockTo48(void) } /* Select PLL as system clock source */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) { } } else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } } #elif defined SYSCLK_FREQ_56MHz @@ -413,14 +413,14 @@ static void SetSysClockTo48(void) static void SetSysClockTo56(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - + RCC->CTLR |= ((uint32_t)RCC_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; + StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CTLR & RCC_HSERDY) != RESET) @@ -430,7 +430,7 @@ static void SetSysClockTo56(void) else { HSEStatus = (uint32_t)0x00; - } + } if (HSEStatus == (uint32_t)0x01) { @@ -439,15 +439,15 @@ static void SetSysClockTo56(void) /* Flash 2 wait state */ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; - + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL7); @@ -460,19 +460,19 @@ static void SetSysClockTo56(void) /* Select PLL as system clock source */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) { } } else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } } #elif defined SYSCLK_FREQ_72MHz @@ -486,14 +486,14 @@ static void SetSysClockTo56(void) static void SetSysClockTo72(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - + RCC->CTLR |= ((uint32_t)RCC_HSEON); - + /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; + StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CTLR & RCC_HSERDY) != RESET) @@ -503,7 +503,7 @@ static void SetSysClockTo72(void) else { HSEStatus = (uint32_t)0x00; - } + } if (HSEStatus == (uint32_t)0x01) { @@ -512,15 +512,15 @@ static void SetSysClockTo72(void) /* Flash 2 wait state */ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); - FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; /* PCLK1 = HCLK */ RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); @@ -530,25 +530,25 @@ static void SetSysClockTo72(void) /* Wait till PLL is ready */ while((RCC->CTLR & RCC_PLLRDY) == 0) { - } + } /* Select PLL as system clock source */ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) { } } else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ } } #endif - +