From b6a9fad9eed5ceb7cff8635335fbb225777c41c5 Mon Sep 17 00:00:00 2001 From: Bernard Xiong Date: Mon, 3 Nov 2014 13:23:56 +0800 Subject: [PATCH] [BSP] Add GCC compiler support for mb9bf568r --- .../{ => arm}/startup_mb9bf56xr.s | 0 .../DeviceSupport/gcc/startup_mb9bf56xr.S | 288 ++++++ bsp/mb9bf568r/CMSIS/SConscript | 5 +- bsp/mb9bf568r/SConstruct | 3 +- bsp/mb9bf568r/project.uvopt | 844 ------------------ bsp/mb9bf568r/project.uvproj | 625 ------------- bsp/mb9bf568r/rtconfig.py | 18 +- bsp/mb9bf568r/rtthread-mb9bf568r.ld | 222 +++++ bsp/mb9bf568r/rtthread-mb9bf568r.sct | 23 + 9 files changed, 548 insertions(+), 1480 deletions(-) rename bsp/mb9bf568r/CMSIS/DeviceSupport/{ => arm}/startup_mb9bf56xr.s (100%) create mode 100644 bsp/mb9bf568r/CMSIS/DeviceSupport/gcc/startup_mb9bf56xr.S delete mode 100644 bsp/mb9bf568r/project.uvopt delete mode 100644 bsp/mb9bf568r/project.uvproj create mode 100644 bsp/mb9bf568r/rtthread-mb9bf568r.ld create mode 100644 bsp/mb9bf568r/rtthread-mb9bf568r.sct diff --git a/bsp/mb9bf568r/CMSIS/DeviceSupport/startup_mb9bf56xr.s b/bsp/mb9bf568r/CMSIS/DeviceSupport/arm/startup_mb9bf56xr.s similarity index 100% rename from bsp/mb9bf568r/CMSIS/DeviceSupport/startup_mb9bf56xr.s rename to bsp/mb9bf568r/CMSIS/DeviceSupport/arm/startup_mb9bf56xr.s diff --git a/bsp/mb9bf568r/CMSIS/DeviceSupport/gcc/startup_mb9bf56xr.S b/bsp/mb9bf568r/CMSIS/DeviceSupport/gcc/startup_mb9bf56xr.S new file mode 100644 index 0000000000..8830a4d2c7 --- /dev/null +++ b/bsp/mb9bf568r/CMSIS/DeviceSupport/gcc/startup_mb9bf56xr.S @@ -0,0 +1,288 @@ +/**************************************************************************//** + * @file startup_.s + * @brief CMSIS Cortex-M# Core Device Startup File for + * Device + * @version V3.01 + * @date 06. March 2012 + * + * @note Version CodeSourcery Sourcery G++ Lite (with CS3) + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Stack_Size, 0x00000400 + .section ".stack", "w" + .align 3 + .globl __cs3_stack_mem + .globl __cs3_stack_size +__cs3_stack_mem: + .if Stack_Size + .space Stack_Size + .endif + .size __cs3_stack_mem, . - __cs3_stack_mem + .set __cs3_stack_size, . - __cs3_stack_mem + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .equ Heap_Size, 0x00000100 + + .section ".heap", "w" + .align 3 + .globl __cs3_heap_start + .globl __cs3_heap_end +__cs3_heap_start: + .if Heap_Size + .space Heap_Size + .endif +__cs3_heap_end: + + +/* Vector Table */ + + .section ".cs3.interrupt_vector" + .globl __cs3_interrupt_vector_cortex_m + .type __cs3_interrupt_vector_cortex_m, %object + +__cs3_interrupt_vector_cortex_m: + .long __cs3_stack /* Top of Stack */ + .long __cs3_reset /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ +/* ToDo: Add here the vectors for the device specific external interrupts handler */ + .long CSV_Handler /* 0: Clock Super Visor */ + .long SWDT_Handler /* 1: Software Watchdog Timer */ + .long LVD_Handler /* 2: Low Voltage Detector */ + .long MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */ + .long INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */ + .long INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */ + .long DT_Handler /* 6: Dual Timer / Quad Decoder */ + .long MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */ + .long MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */ + .long MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */ + .long MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */ + .long MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */ + .long MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */ + .long MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */ + .long MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */ + .long MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */ + .long MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */ + .long MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */ + .long MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */ + .long MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */ + .long MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */ + .long MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */ + .long MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */ + .long PPG_Handler /* 23: PPG */ + .long TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */ + .long ADC0_IRQHandler /* 25: ADC0 */ + .long ADC1_IRQHandler /* 26: ADC1 */ + .long ADC2_IRQHandler /* 27: ADC2 */ + .long MFT_FRT_IRQHandler /* 28: Free-run Timer */ + .long MFT_IPC_IRQHandler /* 29: Input Capture */ + .long MFT_OPC_IRQHandler /* 30: Output Compare */ + .long BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */ + .long CAN0_IRQHandler /* 32: CAN ch.0 */ + .long CAN1_IRQHandler /* 33: CAN ch.1 */ + .long USBF_Handler /* 34: USB Function */ + .long USB_Handler /* 35: USB Function / USB HOST */ + .long RESERVED_1_IRQHandler /* 36: Reserved */ + .long RESERVED_2_IRQHandler /* 37: Reserved */ + .long DMAC0_Handler /* 38: DMAC ch.0 */ + .long DMAC1_Handler /* 39: DMAC ch.1 */ + .long DMAC2_Handler /* 40: DMAC ch.2 */ + .long DMAC3_Handler /* 41: DMAC ch.3 */ + .long DMAC4_Handler /* 42: DMAC ch.4 */ + .long DMAC5_Handler /* 43: DMAC ch.5 */ + .long DMAC6_Handler /* 44: DMAC ch.6 */ + .long DMAC7_Handler /* 45: DMAC ch.7 */ + .long RESERVED_3_IRQHandler /* 46: Reserved */ + .long RESERVED_4_IRQHandler /* 47: Reserved */ + + .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m + + + .thumb + + +/* Reset Handler */ + + .section .cs3.reset,"x",%progbits + .thumb_func + .globl __cs3_reset_cortex_m + .type __cs3_reset_cortex_m, %function +__cs3_reset_cortex_m: + .fnstart + LDR R0, =SystemInit + BLX R0 + LDR R0,=_start + BX R0 + .pool + .cantunwind + .fnend + .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m + + .section ".text" + +/* Exception Handlers */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + B . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + B . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + B . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + B . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + B . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + B . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + B . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + B . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + B . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + +/* ToDo: Add here the export definition for the device specific external interrupts handler */ +/* ToDo: Add here the names for the device specific external interrupts handler */ + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + B . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ CSV_Handler /* 0: Clock Super Visor */ + IRQ SWDT_Handler /* 1: Software Watchdog Timer */ + IRQ LVD_Handler /* 2: Low Voltage Detector */ + IRQ MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */ + IRQ INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */ + IRQ INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */ + IRQ DT_Handler /* 6: Dual Timer / Quad Decoder */ + IRQ MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */ + IRQ MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */ + IRQ MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */ + IRQ MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */ + IRQ MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */ + IRQ MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */ + IRQ MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */ + IRQ MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */ + IRQ MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */ + IRQ MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */ + IRQ MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */ + IRQ MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */ + IRQ MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */ + IRQ MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */ + IRQ MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */ + IRQ MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */ + IRQ PPG_Handler /* 23: PPG */ + IRQ TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */ + IRQ ADC0_IRQHandler /* 25: ADC0 */ + IRQ ADC1_IRQHandler /* 26: ADC1 */ + IRQ ADC2_IRQHandler /* 27: ADC2 */ + IRQ MFT_FRT_IRQHandler /* 28: Free-run Timer */ + IRQ MFT_IPC_IRQHandler /* 29: Input Capture */ + IRQ MFT_OPC_IRQHandler /* 30: Output Compare */ + IRQ BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */ + IRQ CAN0_IRQHandler /* 32: CAN ch.0 */ + IRQ CAN1_IRQHandler /* 33: CAN ch.1 */ + IRQ USBF_Handler /* 34: USB Function */ + IRQ USB_Handler /* 35: USB Function / USB HOST */ + IRQ RESERVED_1_IRQHandler /* 36: Reserved */ + IRQ RESERVED_2_IRQHandler /* 37: Reserved */ + IRQ DMAC0_Handler /* 38: DMAC ch.0 */ + IRQ DMAC1_Handler /* 39: DMAC ch.1 */ + IRQ DMAC2_Handler /* 40: DMAC ch.2 */ + IRQ DMAC3_Handler /* 41: DMAC ch.3 */ + IRQ DMAC4_Handler /* 42: DMAC ch.4 */ + IRQ DMAC5_Handler /* 43: DMAC ch.5 */ + IRQ DMAC6_Handler /* 44: DMAC ch.6 */ + IRQ DMAC7_Handler /* 45: DMAC ch.7 */ + IRQ RESERVED_3_IRQHandler /* 46: Reserved */ + IRQ RESERVED_4_IRQHandler /* 47: Reserved */ + + .end diff --git a/bsp/mb9bf568r/CMSIS/SConscript b/bsp/mb9bf568r/CMSIS/SConscript index f48594dfa3..6ab907fca5 100644 --- a/bsp/mb9bf568r/CMSIS/SConscript +++ b/bsp/mb9bf568r/CMSIS/SConscript @@ -9,9 +9,10 @@ CPPPATH = [cwd + '/Include', cwd + '/DeviceSupport'] # add for startup script if rtconfig.CROSS_TOOL == 'keil': - src += ['DeviceSupport/startup_mb9bf56xr.s'] - + src += ['DeviceSupport/arm/startup_mb9bf56xr.s'] +if rtconfig.CROSS_TOOL == 'gcc': + src += ['DeviceSupport/gcc/startup_mb9bf56xr.S'] group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/mb9bf568r/SConstruct b/bsp/mb9bf568r/SConstruct index a58e07aa4b..2a092f5a7e 100644 --- a/bsp/mb9bf568r/SConstruct +++ b/bsp/mb9bf568r/SConstruct @@ -10,11 +10,12 @@ else: sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] from building import * -TARGET = 'rtthread-stm32f4xx.' + rtconfig.TARGET_EXT +TARGET = 'rtthread-fm4.' + rtconfig.TARGET_EXT env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) diff --git a/bsp/mb9bf568r/project.uvopt b/bsp/mb9bf568r/project.uvopt deleted file mode 100644 index 9046d919e5..0000000000 --- a/bsp/mb9bf568r/project.uvopt +++ /dev/null @@ -1,844 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
- - - - rtthread-fm4 - 0x4 - ARM-ADS - - - Cortex-M4 FPU - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 - - - - 5237 - - - - - - - - - - - - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - template_mb9b56xx - 1 - 0 - 0 - 1 - 1 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - - 0 - 14 - - - - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - - 1 - 0 - 0 - 0 - 1 - 4105 - - BIN\CMSIS_AGDI.dll - "" () - - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 8 - 0 - 1 - 0 - 3 - 5 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 1 - 1 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x100000 - - - 1 - 0x200c0000 - 0x8000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x1fff0000 - 0x10000 - - - 0 - 0x20038000 - 0x10000 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - applications;.;CMSIS\Include;CMSIS\DeviceSupport;drivers;E:/work/xiaoyang/rt-thread/include;E:/work/xiaoyang/rt-thread/libcpu/arm/cortex-m4;E:/work/xiaoyang/rt-thread/libcpu/arm/common;E:/work/xiaoyang/rt-thread/components/finsh;E:/work/xiaoyang/rt-thread/components/init - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x00000000 - - - - --keep __fsym_* --keep __vsym_* --keep __rt_init* - - - - - - - - Applications - - - application.c - 1 - applications\application.c - - - demo.c - 1 - applications\demo.c - - - startup.c - 1 - applications\startup.c - - - - - CMSIS - - - system_mb9abxxx.c - 1 - CMSIS\DeviceSupport\system_mb9abxxx.c - - - startup_mb9bf56xr.s - 2 - CMSIS\DeviceSupport\startup_mb9bf56xr.s - - - - - Drivers - - - board.c - 1 - drivers\board.c - - - led.c - 1 - drivers\led.c - - - serial.c - 1 - drivers\serial.c - - - - - Kernel - - - clock.c - 1 - E:/work/xiaoyang/rt-thread/src\clock.c - - - device.c - 1 - E:/work/xiaoyang/rt-thread/src\device.c - - - idle.c - 1 - E:/work/xiaoyang/rt-thread/src\idle.c - - - ipc.c - 1 - E:/work/xiaoyang/rt-thread/src\ipc.c - - - irq.c - 1 - E:/work/xiaoyang/rt-thread/src\irq.c - - - kservice.c - 1 - E:/work/xiaoyang/rt-thread/src\kservice.c - - - mem.c - 1 - E:/work/xiaoyang/rt-thread/src\mem.c - - - mempool.c - 1 - E:/work/xiaoyang/rt-thread/src\mempool.c - - - object.c - 1 - E:/work/xiaoyang/rt-thread/src\object.c - - - scheduler.c - 1 - E:/work/xiaoyang/rt-thread/src\scheduler.c - - - thread.c - 1 - E:/work/xiaoyang/rt-thread/src\thread.c - - - timer.c - 1 - E:/work/xiaoyang/rt-thread/src\timer.c - - - - - CORTEX-M4 - - - cpuport.c - 1 - E:/work/xiaoyang/rt-thread/libcpu/arm/cortex-m4\cpuport.c - - - context_rvds.S - 2 - E:/work/xiaoyang/rt-thread/libcpu/arm/cortex-m4\context_rvds.S - - - backtrace.c - 1 - E:/work/xiaoyang/rt-thread/libcpu/arm/common\backtrace.c - - - div0.c - 1 - E:/work/xiaoyang/rt-thread/libcpu/arm/common\div0.c - - - showmem.c - 1 - E:/work/xiaoyang/rt-thread/libcpu/arm/common\showmem.c - - - - - finsh - - - shell.c - 1 - E:/work/xiaoyang/rt-thread/components/finsh\shell.c - - - symbol.c - 1 - E:/work/xiaoyang/rt-thread/components/finsh\symbol.c - - - cmd.c - 1 - E:/work/xiaoyang/rt-thread/components/finsh\cmd.c - - - finsh_compiler.c - 1 - E:/work/xiaoyang/rt-thread/components/finsh\finsh_compiler.c - - - finsh_error.c - 1 - E:/work/xiaoyang/rt-thread/components/finsh\finsh_error.c - - - finsh_heap.c - 1 - E:/work/xiaoyang/rt-thread/components/finsh\finsh_heap.c - - - finsh_init.c - 1 - E:/work/xiaoyang/rt-thread/components/finsh\finsh_init.c - - - finsh_node.c - 1 - E:/work/xiaoyang/rt-thread/components/finsh\finsh_node.c - - - finsh_ops.c - 1 - E:/work/xiaoyang/rt-thread/components/finsh\finsh_ops.c - - - finsh_parser.c - 1 - E:/work/xiaoyang/rt-thread/components/finsh\finsh_parser.c - - - finsh_var.c - 1 - E:/work/xiaoyang/rt-thread/components/finsh\finsh_var.c - - - finsh_vm.c - 1 - E:/work/xiaoyang/rt-thread/components/finsh\finsh_vm.c - - - finsh_token.c - 1 - E:/work/xiaoyang/rt-thread/components/finsh\finsh_token.c - - - - - Components - - - components.c - 1 - E:/work/xiaoyang/rt-thread/components/init\components.c - - - - - - - - diff --git a/bsp/mb9bf568r/rtconfig.py b/bsp/mb9bf568r/rtconfig.py index 4d97373f4e..d3cc5e967f 100644 --- a/bsp/mb9bf568r/rtconfig.py +++ b/bsp/mb9bf568r/rtconfig.py @@ -4,17 +4,17 @@ import os ARCH='arm' CPU='cortex-m4' CROSS_TOOL='keil' -BOARD_NAME = 'lpc408x' +BOARD_NAME = 'mb9bf568r' if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') + CROSS_TOOL = os.getenv('RTT_CC') if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'D:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin' + PLATFORM = 'gcc' + EXEC_PATH = r'D:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin' elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = 'D:/Keil' + PLATFORM = 'armcc' + EXEC_PATH = 'D:/Keil' elif CROSS_TOOL == 'iar': print '================ERROR============================' print 'Not support iar yet!' @@ -22,7 +22,7 @@ elif CROSS_TOOL == 'iar': exit(0) if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') + EXEC_PATH = os.getenv('RTT_EXEC_PATH') BUILD = 'debug' @@ -30,9 +30,10 @@ if PLATFORM == 'gcc': # toolchains PREFIX = 'arm-none-eabi-' CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' AS = PREFIX + 'gcc' AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' + LINK = PREFIX + 'g++' TARGET_EXT = 'elf' SIZE = PREFIX + 'size' OBJDUMP = PREFIX + 'objdump' @@ -51,6 +52,7 @@ if PLATFORM == 'gcc': AFLAGS += ' -gdwarf-2' else: CFLAGS += ' -O2' + CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/mb9bf568r/rtthread-mb9bf568r.ld b/bsp/mb9bf568r/rtthread-mb9bf568r.ld new file mode 100644 index 0000000000..8b9a6a37ac --- /dev/null +++ b/bsp/mb9bf568r/rtthread-mb9bf568r.ld @@ -0,0 +1,222 @@ +/* Linker script to configure memory regions + * + * Version:CodeSourcery Sourcery G++ Lite 2007q3-53 + * BugURL:https://support.codesourcery.com/GNUToolchain/ + * + * Copyright 2007 CodeSourcery. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. */ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(_start) +SEARCH_DIR(.) +GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro) + +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 /* 1024k */ + ram (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 /* 64k */ +} + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(__cs3_reset_cortex_m) +EXTERN(__cs3_interrupt_vector_cortex_m) +EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end) + +PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram); +PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end); +PROVIDE(__cs3_heap_start = _end); +PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram); + +SECTIONS +{ + .text : + { + CREATE_OBJECT_SYMBOLS + __cs3_region_start_rom = .; + *(.cs3.region-head.rom) + __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m; + *(.cs3.interrupt_vector) + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector"); + *(.rom) + *(.rom.b) + + __cs3_reset = __cs3_reset_cortex_m; + *(.cs3.reset) + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cs3_reset, "No reset code"); + + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + *(.rodata .rodata.* .gnu.linkonce.r.*) + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + *(.eh_frame_hdr) + *(.eh_frame) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cs3_regions = .; + LONG (0) + LONG (__cs3_region_init_ram) + LONG (__cs3_region_start_ram) + LONG (__cs3_region_init_size_ram) + LONG (__cs3_region_zero_size_ram) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + } + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + __exidx_end = .; + .text.align : + { + . = ALIGN(8); + _etext = .; + } >rom + __cs3_region_size_rom = LENGTH(rom); + __cs3_region_num = 1; + + .data : + { + __cs3_region_start_ram = .; + *(.cs3.region-head.ram) + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + *(.ram) + . = ALIGN (8); + _edata = .; + } >ram AT>rom + + .bss : + { + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + *(.ram.b) + . = ALIGN (8); + _end = .; + __end = .; + } >ram AT>rom + + .heap : + { + *(.heap) + } >ram + + __bss_end = .; + + .stack (__cs3_stack - __cs3_stack_size) : + { + *(.stack) + } >ram + + __cs3_region_init_ram = LOADADDR (.data); + __cs3_region_init_size_ram = _edata - __cs3_region_start_ram; + __cs3_region_zero_size_ram = _end - _edata; + __cs3_region_size_ram = LENGTH(ram); + __cs3_region_num = 1; + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/bsp/mb9bf568r/rtthread-mb9bf568r.sct b/bsp/mb9bf568r/rtthread-mb9bf568r.sct new file mode 100644 index 0000000000..5b025eb611 --- /dev/null +++ b/bsp/mb9bf568r/rtthread-mb9bf568r.sct @@ -0,0 +1,23 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00100000 { ; load region size_region + ER_IROM1 0x00000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x1FFF0000 0x00010000 { ; RW data + .ANY (+RW +ZI) + } + RW_IRAM2 0x20038000 0x00010000 { + .ANY (+RW +ZI) + } +} + +LR_IROM2 0x200C0000 0x00008000 { + ER_IROM2 0x200C0000 0x00008000 { ; load address = execution address + .ANY (+RO) + } +}