Merge pull request #369 from BernardXiong/master
[BSP] Add GCC compiler support for mb9bf568r
This commit is contained in:
Bernard Xiong
commit
00197fde12
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@ -0,0 +1,288 @@
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/**************************************************************************//**
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* @file startup_<Device>.s
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* @brief CMSIS Cortex-M# Core Device Startup File for
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* Device <Device>
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* @version V3.01
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* @date 06. March 2012
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*
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* @note Version CodeSourcery Sourcery G++ Lite (with CS3)
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* Copyright (C) 2012 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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/*
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// <h> Stack Configuration
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// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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*/
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.equ Stack_Size, 0x00000400
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.section ".stack", "w"
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.align 3
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.globl __cs3_stack_mem
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.globl __cs3_stack_size
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__cs3_stack_mem:
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.if Stack_Size
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.space Stack_Size
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.endif
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.size __cs3_stack_mem, . - __cs3_stack_mem
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.set __cs3_stack_size, . - __cs3_stack_mem
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/*
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// <h> Heap Configuration
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// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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*/
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.equ Heap_Size, 0x00000100
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.section ".heap", "w"
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.align 3
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.globl __cs3_heap_start
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.globl __cs3_heap_end
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__cs3_heap_start:
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.if Heap_Size
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.space Heap_Size
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.endif
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__cs3_heap_end:
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/* Vector Table */
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.section ".cs3.interrupt_vector"
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.globl __cs3_interrupt_vector_cortex_m
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.type __cs3_interrupt_vector_cortex_m, %object
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__cs3_interrupt_vector_cortex_m:
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.long __cs3_stack /* Top of Stack */
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.long __cs3_reset /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long MemManage_Handler /* MPU Fault Handler */
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.long BusFault_Handler /* Bus Fault Handler */
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.long UsageFault_Handler /* Usage Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long DebugMon_Handler /* Debug Monitor Handler */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External Interrupts */
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/* ToDo: Add here the vectors for the device specific external interrupts handler */
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.long CSV_Handler /* 0: Clock Super Visor */
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.long SWDT_Handler /* 1: Software Watchdog Timer */
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.long LVD_Handler /* 2: Low Voltage Detector */
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.long MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */
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.long INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */
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.long INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */
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.long DT_Handler /* 6: Dual Timer / Quad Decoder */
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.long MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */
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.long MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */
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.long MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */
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.long MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */
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.long MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */
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.long MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */
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.long MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */
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.long MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */
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.long MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */
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.long MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */
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.long MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */
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.long MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */
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.long MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */
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.long MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */
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.long MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */
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.long MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */
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.long PPG_Handler /* 23: PPG */
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.long TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */
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.long ADC0_IRQHandler /* 25: ADC0 */
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.long ADC1_IRQHandler /* 26: ADC1 */
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.long ADC2_IRQHandler /* 27: ADC2 */
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.long MFT_FRT_IRQHandler /* 28: Free-run Timer */
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.long MFT_IPC_IRQHandler /* 29: Input Capture */
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.long MFT_OPC_IRQHandler /* 30: Output Compare */
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.long BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */
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.long CAN0_IRQHandler /* 32: CAN ch.0 */
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.long CAN1_IRQHandler /* 33: CAN ch.1 */
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.long USBF_Handler /* 34: USB Function */
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.long USB_Handler /* 35: USB Function / USB HOST */
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.long RESERVED_1_IRQHandler /* 36: Reserved */
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.long RESERVED_2_IRQHandler /* 37: Reserved */
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.long DMAC0_Handler /* 38: DMAC ch.0 */
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.long DMAC1_Handler /* 39: DMAC ch.1 */
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.long DMAC2_Handler /* 40: DMAC ch.2 */
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.long DMAC3_Handler /* 41: DMAC ch.3 */
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.long DMAC4_Handler /* 42: DMAC ch.4 */
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.long DMAC5_Handler /* 43: DMAC ch.5 */
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.long DMAC6_Handler /* 44: DMAC ch.6 */
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.long DMAC7_Handler /* 45: DMAC ch.7 */
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.long RESERVED_3_IRQHandler /* 46: Reserved */
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.long RESERVED_4_IRQHandler /* 47: Reserved */
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.size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
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.thumb
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/* Reset Handler */
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.section .cs3.reset,"x",%progbits
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.thumb_func
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.globl __cs3_reset_cortex_m
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.type __cs3_reset_cortex_m, %function
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__cs3_reset_cortex_m:
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.fnstart
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LDR R0, =SystemInit
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BLX R0
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LDR R0,=_start
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BX R0
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.pool
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.cantunwind
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.fnend
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.size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
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.section ".text"
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/* Exception Handlers */
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.weak NMI_Handler
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.type NMI_Handler, %function
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NMI_Handler:
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B .
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.size NMI_Handler, . - NMI_Handler
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.weak HardFault_Handler
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.type HardFault_Handler, %function
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HardFault_Handler:
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B .
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.size HardFault_Handler, . - HardFault_Handler
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.weak MemManage_Handler
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.type MemManage_Handler, %function
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MemManage_Handler:
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B .
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.size MemManage_Handler, . - MemManage_Handler
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.weak BusFault_Handler
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.type BusFault_Handler, %function
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BusFault_Handler:
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B .
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.size BusFault_Handler, . - BusFault_Handler
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.weak UsageFault_Handler
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.type UsageFault_Handler, %function
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UsageFault_Handler:
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B .
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.size UsageFault_Handler, . - UsageFault_Handler
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.weak SVC_Handler
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.type SVC_Handler, %function
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SVC_Handler:
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B .
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.size SVC_Handler, . - SVC_Handler
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.weak DebugMon_Handler
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.type DebugMon_Handler, %function
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DebugMon_Handler:
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B .
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.size DebugMon_Handler, . - DebugMon_Handler
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.weak PendSV_Handler
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.type PendSV_Handler, %function
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PendSV_Handler:
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B .
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.size PendSV_Handler, . - PendSV_Handler
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.weak SysTick_Handler
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.type SysTick_Handler, %function
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SysTick_Handler:
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B .
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.size SysTick_Handler, . - SysTick_Handler
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/* IRQ Handlers */
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/* ToDo: Add here the export definition for the device specific external interrupts handler */
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/* ToDo: Add here the names for the device specific external interrupts handler */
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.globl Default_Handler
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.type Default_Handler, %function
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Default_Handler:
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B .
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.size Default_Handler, . - Default_Handler
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.macro IRQ handler
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.weak \handler
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.set \handler, Default_Handler
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.endm
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IRQ CSV_Handler /* 0: Clock Super Visor */
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IRQ SWDT_Handler /* 1: Software Watchdog Timer */
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IRQ LVD_Handler /* 2: Low Voltage Detector */
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IRQ MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */
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IRQ INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */
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IRQ INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */
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IRQ DT_Handler /* 6: Dual Timer / Quad Decoder */
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IRQ MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */
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IRQ MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */
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IRQ MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */
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IRQ MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */
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IRQ MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */
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IRQ MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */
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IRQ MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */
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IRQ MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */
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IRQ MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */
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IRQ MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */
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IRQ MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */
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IRQ MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */
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IRQ MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */
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IRQ MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */
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IRQ MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */
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IRQ MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */
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IRQ PPG_Handler /* 23: PPG */
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IRQ TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */
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IRQ ADC0_IRQHandler /* 25: ADC0 */
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IRQ ADC1_IRQHandler /* 26: ADC1 */
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IRQ ADC2_IRQHandler /* 27: ADC2 */
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IRQ MFT_FRT_IRQHandler /* 28: Free-run Timer */
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IRQ MFT_IPC_IRQHandler /* 29: Input Capture */
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IRQ MFT_OPC_IRQHandler /* 30: Output Compare */
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IRQ BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */
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IRQ CAN0_IRQHandler /* 32: CAN ch.0 */
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IRQ CAN1_IRQHandler /* 33: CAN ch.1 */
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IRQ USBF_Handler /* 34: USB Function */
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IRQ USB_Handler /* 35: USB Function / USB HOST */
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IRQ RESERVED_1_IRQHandler /* 36: Reserved */
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IRQ RESERVED_2_IRQHandler /* 37: Reserved */
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IRQ DMAC0_Handler /* 38: DMAC ch.0 */
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IRQ DMAC1_Handler /* 39: DMAC ch.1 */
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IRQ DMAC2_Handler /* 40: DMAC ch.2 */
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IRQ DMAC3_Handler /* 41: DMAC ch.3 */
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IRQ DMAC4_Handler /* 42: DMAC ch.4 */
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IRQ DMAC5_Handler /* 43: DMAC ch.5 */
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IRQ DMAC6_Handler /* 44: DMAC ch.6 */
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IRQ DMAC7_Handler /* 45: DMAC ch.7 */
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IRQ RESERVED_3_IRQHandler /* 46: Reserved */
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IRQ RESERVED_4_IRQHandler /* 47: Reserved */
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.end
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@ -9,9 +9,10 @@ CPPPATH = [cwd + '/Include', cwd + '/DeviceSupport']
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# add for startup script
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if rtconfig.CROSS_TOOL == 'keil':
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src += ['DeviceSupport/startup_mb9bf56xr.s']
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src += ['DeviceSupport/arm/startup_mb9bf56xr.s']
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if rtconfig.CROSS_TOOL == 'gcc':
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src += ['DeviceSupport/gcc/startup_mb9bf56xr.S']
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group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH)
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@ -10,11 +10,12 @@ else:
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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from building import *
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TARGET = 'rtthread-stm32f4xx.' + rtconfig.TARGET_EXT
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TARGET = 'rtthread-fm4.' + rtconfig.TARGET_EXT
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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@ -1,844 +0,0 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
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<SchemaVersion>1.0</SchemaVersion>
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<Header>### uVision Project, (C) Keil Software</Header>
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<Extensions>
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<cExt>*.c</cExt>
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<aExt>*.s*; *.src; *.a*</aExt>
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<oExt>*.obj</oExt>
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<lExt>*.lib</lExt>
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<tExt>*.txt; *.h; *.inc</tExt>
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<pExt>*.plm</pExt>
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<CppX>*.cpp</CppX>
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</Extensions>
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<DaveTm>
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<dwLowDateTime>0</dwLowDateTime>
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<dwHighDateTime>0</dwHighDateTime>
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</DaveTm>
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<Target>
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<TargetName>rtthread-fm4</TargetName>
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<ToolsetNumber>0x4</ToolsetNumber>
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<ToolsetName>ARM-ADS</ToolsetName>
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<TargetOption>
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<CLKADS>4000000</CLKADS>
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<OPTTT>
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<gFlags>1</gFlags>
|
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<BeepAtEnd>1</BeepAtEnd>
|
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<RunSim>1</RunSim>
|
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<RunTarget>0</RunTarget>
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</OPTTT>
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<OPTHX>
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<HexSelection>1</HexSelection>
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<FlashByte>65535</FlashByte>
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<HexRangeLowAddress>0</HexRangeLowAddress>
|
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<HexRangeHighAddress>0</HexRangeHighAddress>
|
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<HexOffset>0</HexOffset>
|
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</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DllOpt>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
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||||
<SimDllArguments></SimDllArguments>
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||||
<SimDlgDllName>DCM.DLL</SimDlgDllName>
|
||||
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
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<TargetDllName>SARMCM3.DLL</TargetDllName>
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||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDllName>TCM.DLL</TargetDlgDllName>
|
||||
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||
</DllOpt>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<nTsel>14</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
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||||
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|
||||
<FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_compiler.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>finsh_error.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_error.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>finsh_heap.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_heap.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>finsh_init.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_init.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>finsh_node.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_node.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>finsh_ops.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_ops.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>finsh_parser.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_parser.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>finsh_var.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_var.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>finsh_vm.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_vm.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>finsh_token.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_token.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Components</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>components.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>E:/work/xiaoyang/rt-thread/components/init\components.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
</Project>
|
||||
|
|
@ -4,17 +4,17 @@ import os
|
|||
ARCH='arm'
|
||||
CPU='cortex-m4'
|
||||
CROSS_TOOL='keil'
|
||||
BOARD_NAME = 'lpc408x'
|
||||
BOARD_NAME = 'mb9bf568r'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'D:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'D:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = 'D:/Keil'
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = 'D:/Keil'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
print '================ERROR============================'
|
||||
print 'Not support iar yet!'
|
||||
|
|
@ -22,7 +22,7 @@ elif CROSS_TOOL == 'iar':
|
|||
exit(0)
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
|
|
@ -30,9 +30,10 @@ if PLATFORM == 'gcc':
|
|||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
LINK = PREFIX + 'g++'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
|
|
@ -51,6 +52,7 @@ if PLATFORM == 'gcc':
|
|||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,222 @@
|
|||
/* Linker script to configure memory regions
|
||||
*
|
||||
* Version:CodeSourcery Sourcery G++ Lite 2007q3-53
|
||||
* BugURL:https://support.codesourcery.com/GNUToolchain/
|
||||
*
|
||||
* Copyright 2007 CodeSourcery.
|
||||
*
|
||||
* The authors hereby grant permission to use, copy, modify, distribute,
|
||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
||||
* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply. */
|
||||
|
||||
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
|
||||
ENTRY(_start)
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 /* 1024k */
|
||||
ram (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 /* 64k */
|
||||
}
|
||||
|
||||
/* These force the linker to search for particular symbols from
|
||||
* the start of the link process and thus ensure the user's
|
||||
* overrides are picked up
|
||||
*/
|
||||
EXTERN(__cs3_reset_cortex_m)
|
||||
EXTERN(__cs3_interrupt_vector_cortex_m)
|
||||
EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
|
||||
|
||||
PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
|
||||
PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
|
||||
PROVIDE(__cs3_heap_start = _end);
|
||||
PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
CREATE_OBJECT_SYMBOLS
|
||||
__cs3_region_start_rom = .;
|
||||
*(.cs3.region-head.rom)
|
||||
__cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
|
||||
*(.cs3.interrupt_vector)
|
||||
/* Make sure we pulled in an interrupt vector. */
|
||||
ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
|
||||
*(.rom)
|
||||
*(.rom.b)
|
||||
|
||||
__cs3_reset = __cs3_reset_cortex_m;
|
||||
*(.cs3.reset)
|
||||
/* Make sure we pulled in some reset code. */
|
||||
ASSERT (. != __cs3_reset, "No reset code");
|
||||
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.plt)
|
||||
*(.gnu.warning)
|
||||
*(.glue_7t) *(.glue_7) *(.vfp11_veneer)
|
||||
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
*(.gcc_except_table)
|
||||
*(.eh_frame_hdr)
|
||||
*(.eh_frame)
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(0x4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
__cs3_regions = .;
|
||||
LONG (0)
|
||||
LONG (__cs3_region_init_ram)
|
||||
LONG (__cs3_region_start_ram)
|
||||
LONG (__cs3_region_init_size_ram)
|
||||
LONG (__cs3_region_zero_size_ram)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
}
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} >rom
|
||||
__exidx_end = .;
|
||||
.text.align :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_etext = .;
|
||||
} >rom
|
||||
__cs3_region_size_rom = LENGTH(rom);
|
||||
__cs3_region_num = 1;
|
||||
|
||||
.data :
|
||||
{
|
||||
__cs3_region_start_ram = .;
|
||||
*(.cs3.region-head.ram)
|
||||
KEEP(*(.jcr))
|
||||
*(.got.plt) *(.got)
|
||||
*(.shdata)
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
*(.ram)
|
||||
. = ALIGN (8);
|
||||
_edata = .;
|
||||
} >ram AT>rom
|
||||
|
||||
.bss :
|
||||
{
|
||||
*(.shbss)
|
||||
*(.bss .bss.* .gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
*(.ram.b)
|
||||
. = ALIGN (8);
|
||||
_end = .;
|
||||
__end = .;
|
||||
} >ram AT>rom
|
||||
|
||||
.heap :
|
||||
{
|
||||
*(.heap)
|
||||
} >ram
|
||||
|
||||
__bss_end = .;
|
||||
|
||||
.stack (__cs3_stack - __cs3_stack_size) :
|
||||
{
|
||||
*(.stack)
|
||||
} >ram
|
||||
|
||||
__cs3_region_init_ram = LOADADDR (.data);
|
||||
__cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
|
||||
__cs3_region_zero_size_ram = _end - _edata;
|
||||
__cs3_region_size_ram = LENGTH(ram);
|
||||
__cs3_region_num = 1;
|
||||
|
||||
.stab 0 (NOLOAD) : { *(.stab) }
|
||||
.stabstr 0 (NOLOAD) : { *(.stabstr) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
|
||||
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
|
||||
.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
}
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x00000000 0x00100000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x00100000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x1FFF0000 0x00010000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
RW_IRAM2 0x20038000 0x00010000 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
LR_IROM2 0x200C0000 0x00008000 {
|
||||
ER_IROM2 0x200C0000 0x00008000 { ; load address = execution address
|
||||
.ANY (+RO)
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue