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rt-thread/bsp/cvitek/cv18xx_risc-v/board/Kconfig

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[bsp]add cv1800b (#7753)
2023-06-30 00:05:55 +08:00
menu "General Drivers Configuration"
menuconfig BSP_USING_UART
bool "Using UART"
select RT_USING_SERIAL
default y
if BSP_USING_UART
bsp:cvitek: add pinmux for uart Board level UART pinmux summary, following capability should be controlled by pinname whitelist. Duo: NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX GP3 UART4_RX PWR_GPIO[25] SD1_GPIO0__UART4_RX GP2 UART4_TX PWR_GPIO[26] SD1_GPIO1__UART4_TX Duo 256m: NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP3 UART1_RX XGPIOA[18] JTAG_CPU_TCK__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP2 UART1_TX XGPIOA[19] JTAG_CPU_TMS__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX Note: this patch also update the .config and rtconfig.h because this patch modify some configuration items's name, for example: RT_USIMG_UART0 -> BSP_USING_UART0. FIXME: only handle RISC-V related, no ARM. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-05-28 16:12:24 +08:00
config BSP_USING_UART0
bool "Enable UART 0"
default y
[bsp]add cv1800b (#7753)
2023-06-30 00:05:55 +08:00
bsp:cvitek: add pinmux for uart Board level UART pinmux summary, following capability should be controlled by pinname whitelist. Duo: NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX GP3 UART4_RX PWR_GPIO[25] SD1_GPIO0__UART4_RX GP2 UART4_TX PWR_GPIO[26] SD1_GPIO1__UART4_TX Duo 256m: NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP3 UART1_RX XGPIOA[18] JTAG_CPU_TCK__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP2 UART1_TX XGPIOA[19] JTAG_CPU_TMS__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX Note: this patch also update the .config and rtconfig.h because this patch modify some configuration items's name, for example: RT_USIMG_UART0 -> BSP_USING_UART0. FIXME: only handle RISC-V related, no ARM. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-05-28 16:12:24 +08:00
if BSP_USING_UART0
config BSP_UART0_RX_PINNAME
string "uart0 rx pin name"
default "UART0_RX"
config BSP_UART0_TX_PINNAME
string "uart0 tx pin name"
default "UART0_TX"
endif
config BSP_USING_UART1
bool "Enable UART 1"
default n
if BSP_USING_UART1
config BSP_UART1_RX_PINNAME
string "uart1 rx pin name"
default ""
config BSP_UART1_TX_PINNAME
string "uart1 tx pin name"
default ""
endif
config BSP_USING_UART2
bool "Enable UART 2"
default n
if BSP_USING_UART2
config BSP_UART2_RX_PINNAME
string "uart2 rx pin name"
default ""
config BSP_UART2_TX_PINNAME
string "uart2 tx pin name"
default ""
endif
config BSP_USING_UART3
bool "Enable UART 3"
default n
[bsp]add cv1800b (#7753)
2023-06-30 00:05:55 +08:00
bsp:cvitek: add pinmux for uart Board level UART pinmux summary, following capability should be controlled by pinname whitelist. Duo: NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX GP3 UART4_RX PWR_GPIO[25] SD1_GPIO0__UART4_RX GP2 UART4_TX PWR_GPIO[26] SD1_GPIO1__UART4_TX Duo 256m: NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP3 UART1_RX XGPIOA[18] JTAG_CPU_TCK__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP2 UART1_TX XGPIOA[19] JTAG_CPU_TMS__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX Note: this patch also update the .config and rtconfig.h because this patch modify some configuration items's name, for example: RT_USIMG_UART0 -> BSP_USING_UART0. FIXME: only handle RISC-V related, no ARM. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-05-28 16:12:24 +08:00
if BSP_USING_UART3
config BSP_UART3_RX_PINNAME
string "uart3 rx pin name"
default ""
config BSP_UART3_TX_PINNAME
string "uart3 tx pin name"
default ""
endif
[bsp]add cv1800b (#7753)
2023-06-30 00:05:55 +08:00
bsp:cvitek: add pinmux for uart Board level UART pinmux summary, following capability should be controlled by pinname whitelist. Duo: NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX GP3 UART4_RX PWR_GPIO[25] SD1_GPIO0__UART4_RX GP2 UART4_TX PWR_GPIO[26] SD1_GPIO1__UART4_TX Duo 256m: NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP3 UART1_RX XGPIOA[18] JTAG_CPU_TCK__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP2 UART1_TX XGPIOA[19] JTAG_CPU_TMS__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX Note: this patch also update the .config and rtconfig.h because this patch modify some configuration items's name, for example: RT_USIMG_UART0 -> BSP_USING_UART0. FIXME: only handle RISC-V related, no ARM. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-05-28 16:12:24 +08:00
config BSP_USING_UART4
bool "Enable UART 4"
default n
[bsp]add cv1800b (#7753)
2023-06-30 00:05:55 +08:00
bsp:cvitek: add pinmux for uart Board level UART pinmux summary, following capability should be controlled by pinname whitelist. Duo: NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX GP3 UART4_RX PWR_GPIO[25] SD1_GPIO0__UART4_RX GP2 UART4_TX PWR_GPIO[26] SD1_GPIO1__UART4_TX Duo 256m: NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP3 UART1_RX XGPIOA[18] JTAG_CPU_TCK__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP2 UART1_TX XGPIOA[19] JTAG_CPU_TMS__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX Note: this patch also update the .config and rtconfig.h because this patch modify some configuration items's name, for example: RT_USIMG_UART0 -> BSP_USING_UART0. FIXME: only handle RISC-V related, no ARM. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-05-28 16:12:24 +08:00
if BSP_USING_UART4
config BSP_UART4_RX_PINNAME
string "uart4 rx pin name"
default ""
config BSP_UART4_TX_PINNAME
string "uart4 tx pin name"
default ""
endif
[bsp]add cv1800b (#7753)
2023-06-30 00:05:55 +08:00
bsp:cvitek: add pinmux for uart Board level UART pinmux summary, following capability should be controlled by pinname whitelist. Duo: NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX GP3 UART4_RX PWR_GPIO[25] SD1_GPIO0__UART4_RX GP2 UART4_TX PWR_GPIO[26] SD1_GPIO1__UART4_TX Duo 256m: NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP3 UART1_RX XGPIOA[18] JTAG_CPU_TCK__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP2 UART1_TX XGPIOA[19] JTAG_CPU_TMS__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX Note: this patch also update the .config and rtconfig.h because this patch modify some configuration items's name, for example: RT_USIMG_UART0 -> BSP_USING_UART0. FIXME: only handle RISC-V related, no ARM. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-05-28 16:12:24 +08:00
config UART_IRQ_BASE
int
default 44
[bsp]add cv1800b (#7753)
2023-06-30 00:05:55 +08:00
endif
Accumulated patchsets for bsp/cvitek (#8968) * bsp: cvitek: kconfig: add wdt for cv18xx_riscv Add Watchdog timer in Kconfig. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * drv: cvitek: remove using macro from source file Building of source file should be controlled by SConscript, but not in source file itself. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add i2c for cv18xx_riscv Add I2C in Kconfig for c906B. Note, the IRQ# is different from that of c906L. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add rtc for cv18xx_riscv Add RTC in Kconfig for c906B. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: fix channel issue for pwm driver The original code confuses the concepts of controllers and channels. Fixed it and do some code cleanup. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for cv18xx_riscv Pinmux in driver code is controlled by SOC type, bcos driver code should be general and support all pins defined by SoC. Pinmux configuration in Kconfig is controlled by BOARD type, bcos when we operate on board, it does not expose all chip-level pin signals and we can only use part of them. Following is I2C signals exported by duo family. Details see https://milkv.io/docs/duo/overview. Note: we have not added support for duo-S. Duo === NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo 256m ======== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo S ===== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> * bsp:cvitek: remove using macro from source file for i2c Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: unify menu message text for i2c as other drivers Other dirvers has no extra word "HW". Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for c906_little Porting what we have done in commit "bsp:cvitek: add i2c pinmux config for cv18xx_riscv" to c906_little. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> --------- Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> Co-authored-by: flyingcys <flyingcys@163.com>
2024-05-22 08:19:07 +08:00
menuconfig BSP_USING_I2C
bool "Using I2C"
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
default n
if BSP_USING_I2C
config BSP_USING_I2C0
bool "Enable I2C0"
default n
bsp:cvitek: add pinmux for i2c Based on new pinmux framework, add configuration for uart. Board level pin available info is summarized and should be controlled by pin whitelist. Duo NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo256m NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo S(Note, we have not supported duo S, just list for memo) NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-05-28 16:33:30 +08:00
if BSP_USING_I2C0
config BSP_I2C0_SCL_PINNAME
string "i2c0 scl pin name"
default ""
config BSP_I2C0_SDA_PINNAME
string "i2c0 sda pin name"
default ""
endif
Accumulated patchsets for bsp/cvitek (#8968) * bsp: cvitek: kconfig: add wdt for cv18xx_riscv Add Watchdog timer in Kconfig. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * drv: cvitek: remove using macro from source file Building of source file should be controlled by SConscript, but not in source file itself. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add i2c for cv18xx_riscv Add I2C in Kconfig for c906B. Note, the IRQ# is different from that of c906L. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add rtc for cv18xx_riscv Add RTC in Kconfig for c906B. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: fix channel issue for pwm driver The original code confuses the concepts of controllers and channels. Fixed it and do some code cleanup. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for cv18xx_riscv Pinmux in driver code is controlled by SOC type, bcos driver code should be general and support all pins defined by SoC. Pinmux configuration in Kconfig is controlled by BOARD type, bcos when we operate on board, it does not expose all chip-level pin signals and we can only use part of them. Following is I2C signals exported by duo family. Details see https://milkv.io/docs/duo/overview. Note: we have not added support for duo-S. Duo === NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo 256m ======== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo S ===== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> * bsp:cvitek: remove using macro from source file for i2c Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: unify menu message text for i2c as other drivers Other dirvers has no extra word "HW". Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for c906_little Porting what we have done in commit "bsp:cvitek: add i2c pinmux config for cv18xx_riscv" to c906_little. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> --------- Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> Co-authored-by: flyingcys <flyingcys@163.com>
2024-05-22 08:19:07 +08:00
config BSP_USING_I2C1
bool "Enable I2C1"
default n
bsp:cvitek: add pinmux for i2c Based on new pinmux framework, add configuration for uart. Board level pin available info is summarized and should be controlled by pin whitelist. Duo NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo256m NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo S(Note, we have not supported duo S, just list for memo) NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-05-28 16:33:30 +08:00
if BSP_USING_I2C1
config BSP_I2C1_SCL_PINNAME
string "i2c1 scl pin name"
default ""
config BSP_I2C1_SDA_PINNAME
string "i2c1 sda pin name"
default ""
endif
config BSP_USING_I2C2
bool "Enable I2C2"
default n
if BSP_USING_I2C2
config BSP_I2C2_SCL_PINNAME
string "i2c2 scl pin name"
default ""
config BSP_I2C2_SDA_PINNAME
string "i2c2 sda pin name"
default ""
endif
config BSP_USING_I2C3
bool "Enable I2C3"
default n
if BSP_USING_I2C3
config BSP_I2C3_SCL_PINNAME
string "i2c3 scl pin name"
default ""
config BSP_I2C3_SDA_PINNAME
string "i2c3 sda pin name"
default ""
endif
config BSP_USING_I2C4
bool "Enable I2C4"
default n
if BSP_USING_I2C4
config BSP_I2C4_SCL_PINNAME
string "i2c4 scl pin name"
default ""
config BSP_I2C4_SDA_PINNAME
string "i2c4 sda pin name"
default ""
endif
Accumulated patchsets for bsp/cvitek (#8968) * bsp: cvitek: kconfig: add wdt for cv18xx_riscv Add Watchdog timer in Kconfig. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * drv: cvitek: remove using macro from source file Building of source file should be controlled by SConscript, but not in source file itself. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add i2c for cv18xx_riscv Add I2C in Kconfig for c906B. Note, the IRQ# is different from that of c906L. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add rtc for cv18xx_riscv Add RTC in Kconfig for c906B. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: fix channel issue for pwm driver The original code confuses the concepts of controllers and channels. Fixed it and do some code cleanup. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for cv18xx_riscv Pinmux in driver code is controlled by SOC type, bcos driver code should be general and support all pins defined by SoC. Pinmux configuration in Kconfig is controlled by BOARD type, bcos when we operate on board, it does not expose all chip-level pin signals and we can only use part of them. Following is I2C signals exported by duo family. Details see https://milkv.io/docs/duo/overview. Note: we have not added support for duo-S. Duo === NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo 256m ======== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo S ===== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> * bsp:cvitek: remove using macro from source file for i2c Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: unify menu message text for i2c as other drivers Other dirvers has no extra word "HW". Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for c906_little Porting what we have done in commit "bsp:cvitek: add i2c pinmux config for cv18xx_riscv" to c906_little. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> --------- Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> Co-authored-by: flyingcys <flyingcys@163.com>
2024-05-22 08:19:07 +08:00
config I2C_IRQ_BASE
int
default 49
endif
bsp:cvitek: add pinmux for adc Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-06-04 11:18:00 +08:00
menuconfig BSP_USING_ADC
[bsp/cvitek]add adc driver (#8562)
2024-02-28 00:04:31 +08:00
bool "Using ADC"
select RT_USING_ADC
default n
[bsp]add cv1800b (#7753)
2023-06-30 00:05:55 +08:00
bsp:cvitek: add pinmux for adc Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-06-04 11:18:00 +08:00
if BSP_USING_ADC
config BSP_USING_ADC_ACTIVE
bool "Enable ADC Controller in Active Domain"
default n
if BSP_USING_ADC_ACTIVE
config BSP_ACTIVE_ADC1_PINNAME
string "Pin name for VIN1 in Active Domain"
default ""
config BSP_ACTIVE_ADC2_PINNAME
string "Pin name for VIN2 in Active Domain"
default ""
config BSP_ACTIVE_ADC3_PINNAME
string "Pin name for VIN3 in Active Domain"
default ""
endif
config BSP_USING_ADC_NODIE
bool "Enable ADC Controller in No-die Domain"
default n
if BSP_USING_ADC_NODIE
config BSP_NODIE_ADC1_PINNAME
string "Pin name for VIN1 in No-die Domain"
default ""
config BSP_NODIE_ADC2_PINNAME
string "Pin name for VIN2 in No-die Domain"
default ""
config BSP_NODIE_ADC3_PINNAME
string "Pin name for VIN3 in No-die Domain"
default ""
endif
endif
[bsp][CV1800B] add SPI driver for CV1800B Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com>
2024-03-31 20:28:24 +08:00
config BSP_USING_SPI
bool "Using SPI"
select RT_USING_SPI
default n
bsp:cvitek: add pinmux for spi Board level pin available info: duo & duo256: NAME SPI CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP6 SPI2_SCK PWR_GPIO[23] SD1_CLK__SPI2_SCK GP7 SPI2_SDO PWR_GPIO[22] SD1_CMD__SPI2_SDO GP8 SPI2_SDI PWR_GPIO[21] SD1_D0__SPI2_SDI GP9 SPI2_CS_X PWR_GPIO[18] SD1_D3__SPI2_CS_X Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-05-28 18:45:53 +08:00
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI 0"
default n
if BSP_USING_SPI0
config BSP_SPI0_SCK_PINNAME
string "spi0 sck pin name"
default ""
config BSP_SPI0_SDO_PINNAME
string "spi0 sdo pin name"
default ""
config BSP_SPI0_SDI_PINNAME
string "spi0 sdi pin name"
default ""
config BSP_SPI0_CS_PINNAME
string "spi0 cs pin name"
default ""
endif
config BSP_USING_SPI1
bool "Enable SPI 1"
default n
if BSP_USING_SPI1
config BSP_SPI1_SCK_PINNAME
string "spi1 sck pin name"
default ""
config BSP_SPI1_SDO_PINNAME
string "spi1 sdo pin name"
default ""
config BSP_SPI1_SDI_PINNAME
string "spi1 sdi pin name"
default ""
config BSP_SPI1_CS_PINNAME
string "spi1 cs pin name"
default ""
endif
config BSP_USING_SPI2
bool "Enable SPI 2"
default n
if BSP_USING_SPI2
config BSP_SPI2_SCK_PINNAME
string "spi2 sck pin name"
default ""
config BSP_SPI2_SDO_PINNAME
string "spi2 sdo pin name"
default ""
config BSP_SPI2_SDI_PINNAME
string "spi2 sdi pin name"
default ""
config BSP_SPI2_CS_PINNAME
string "spi2 cs pin name"
default ""
endif
config BSP_USING_SPI3
bool "Enable SPI 3"
default n
if BSP_USING_SPI3
config BSP_SPI3_SCK_PINNAME
string "spi3 sck pin name"
default ""
config BSP_SPI3_SDO_PINNAME
string "spi3 sdo pin name"
default ""
config BSP_SPI3_SDI_PINNAME
string "spi3 sdi pin name"
default ""
config BSP_SPI3_CS_PINNAME
string "spi3 cs pin name"
default ""
endif
endif
Accumulated patchsets for bsp/cvitek (#8968) * bsp: cvitek: kconfig: add wdt for cv18xx_riscv Add Watchdog timer in Kconfig. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * drv: cvitek: remove using macro from source file Building of source file should be controlled by SConscript, but not in source file itself. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add i2c for cv18xx_riscv Add I2C in Kconfig for c906B. Note, the IRQ# is different from that of c906L. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add rtc for cv18xx_riscv Add RTC in Kconfig for c906B. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: fix channel issue for pwm driver The original code confuses the concepts of controllers and channels. Fixed it and do some code cleanup. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for cv18xx_riscv Pinmux in driver code is controlled by SOC type, bcos driver code should be general and support all pins defined by SoC. Pinmux configuration in Kconfig is controlled by BOARD type, bcos when we operate on board, it does not expose all chip-level pin signals and we can only use part of them. Following is I2C signals exported by duo family. Details see https://milkv.io/docs/duo/overview. Note: we have not added support for duo-S. Duo === NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo 256m ======== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo S ===== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> * bsp:cvitek: remove using macro from source file for i2c Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: unify menu message text for i2c as other drivers Other dirvers has no extra word "HW". Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for c906_little Porting what we have done in commit "bsp:cvitek: add i2c pinmux config for cv18xx_riscv" to c906_little. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> --------- Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> Co-authored-by: flyingcys <flyingcys@163.com>
2024-05-22 08:19:07 +08:00
menuconfig BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
if BSP_USING_WDT
config BSP_USING_WDT0
bool "Enable WDT0"
default n
config BSP_USING_WDT1
bool "Enable WDT1"
default n
config BSP_USING_WDT2
bool "Enable WDT2"
default n
endif
[bsp/cvitek]add pwm driver (#8571)
2024-03-02 16:16:22 +08:00
menuconfig BSP_USING_PWM
bool "Using PWM"
select RT_USING_PWM
default n
if BSP_USING_PWM
config BSP_USING_PWM0
bsp:cvitek: add pinmux for pwm Board level pin available info is summarized and list here for memo: Duo: NAME PWM CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- PWM-1 GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4 GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4 GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5 GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5 GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6 GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7 PWM-2 GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8 GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9 GP2 PWM10 PWR_GPIO[26] SD1_GPIO1__PWM_10 GP3 PWM11 PWR_GPIO[25] SD1_GPIO0__PWM_11 Duo256: NAME PWM CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- PWM-1 GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4 GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4 GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5 GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5 GP3 PWM6 XGPIOA[18] JTAG_CPU_TCK__PWM_6 GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6 GP2 PWM7 XGPIOA[19] JTAG_CPU_TMS__PWM_7 GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7 PWM-2 GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8 GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9 GP10 PWM10 XGPIOC[14] PAD_MIPI_TXM1__PWM_10 GP11 PWM11 XGPIOC[15] PAD_MIPI_TXP1__PWM_11 Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-05-28 17:47:48 +08:00
bool "Enable PWM 0"
default n
if BSP_USING_PWM0
config BSP_PWM0_0_PINNAME
string "pwm[0] pin name"
default ""
config BSP_PWM0_1_PINNAME
string "pwm[1] pin name"
default ""
config BSP_PWM0_2_PINNAME
string "pwm[2] pin name"
default ""
config BSP_PWM0_3_PINNAME
string "pwm[3] pin name"
default ""
endif
[bsp/cvitek]add pwm driver (#8571)
2024-03-02 16:16:22 +08:00
config BSP_USING_PWM1
bsp:cvitek: add pinmux for pwm Board level pin available info is summarized and list here for memo: Duo: NAME PWM CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- PWM-1 GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4 GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4 GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5 GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5 GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6 GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7 PWM-2 GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8 GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9 GP2 PWM10 PWR_GPIO[26] SD1_GPIO1__PWM_10 GP3 PWM11 PWR_GPIO[25] SD1_GPIO0__PWM_11 Duo256: NAME PWM CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- PWM-1 GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4 GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4 GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5 GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5 GP3 PWM6 XGPIOA[18] JTAG_CPU_TCK__PWM_6 GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6 GP2 PWM7 XGPIOA[19] JTAG_CPU_TMS__PWM_7 GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7 PWM-2 GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8 GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9 GP10 PWM10 XGPIOC[14] PAD_MIPI_TXM1__PWM_10 GP11 PWM11 XGPIOC[15] PAD_MIPI_TXP1__PWM_11 Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-05-28 17:47:48 +08:00
bool "Enable PWM 1"
default n
if BSP_USING_PWM1
config BSP_PWM1_4_PINNAME
string "pwm[4] pin name"
default ""
config BSP_PWM1_5_PINNAME
string "pwm[5] pin name"
default ""
config BSP_PWM1_6_PINNAME
string "pwm[6] pin name"
default ""
config BSP_PWM1_7_PINNAME
string "pwm[7] pin name"
default ""
endif
[bsp/cvitek]add pwm driver (#8571)
2024-03-02 16:16:22 +08:00
config BSP_USING_PWM2
bsp:cvitek: add pinmux for pwm Board level pin available info is summarized and list here for memo: Duo: NAME PWM CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- PWM-1 GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4 GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4 GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5 GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5 GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6 GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7 PWM-2 GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8 GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9 GP2 PWM10 PWR_GPIO[26] SD1_GPIO1__PWM_10 GP3 PWM11 PWR_GPIO[25] SD1_GPIO0__PWM_11 Duo256: NAME PWM CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- PWM-1 GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4 GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4 GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5 GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5 GP3 PWM6 XGPIOA[18] JTAG_CPU_TCK__PWM_6 GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6 GP2 PWM7 XGPIOA[19] JTAG_CPU_TMS__PWM_7 GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7 PWM-2 GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8 GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9 GP10 PWM10 XGPIOC[14] PAD_MIPI_TXM1__PWM_10 GP11 PWM11 XGPIOC[15] PAD_MIPI_TXP1__PWM_11 Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-05-28 17:47:48 +08:00
bool "Enable PWM 2"
default n
if BSP_USING_PWM2
config BSP_PWM2_8_PINNAME
string "pwm[8] pin name"
default ""
config BSP_PWM2_9_PINNAME
string "pwm[9] pin name"
default ""
config BSP_PWM2_10_PINNAME
string "pwm[10] pin name"
default ""
config BSP_PWM2_11_PINNAME
string "pwm[11] pin name"
default ""
endif
[bsp/cvitek]add pwm driver (#8571)
2024-03-02 16:16:22 +08:00
config BSP_USING_PWM3
bsp:cvitek: add pinmux for pwm Board level pin available info is summarized and list here for memo: Duo: NAME PWM CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- PWM-1 GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4 GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4 GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5 GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5 GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6 GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7 PWM-2 GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8 GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9 GP2 PWM10 PWR_GPIO[26] SD1_GPIO1__PWM_10 GP3 PWM11 PWR_GPIO[25] SD1_GPIO0__PWM_11 Duo256: NAME PWM CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- PWM-1 GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4 GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4 GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5 GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5 GP3 PWM6 XGPIOA[18] JTAG_CPU_TCK__PWM_6 GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6 GP2 PWM7 XGPIOA[19] JTAG_CPU_TMS__PWM_7 GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7 PWM-2 GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8 GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9 GP10 PWM10 XGPIOC[14] PAD_MIPI_TXM1__PWM_10 GP11 PWM11 XGPIOC[15] PAD_MIPI_TXP1__PWM_11 Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-05-28 17:47:48 +08:00
bool "Enable PWM 3"
default n
if BSP_USING_PWM3
config BSP_PWM3_12_PINNAME
string "pwm[12] pin name"
default ""
config BSP_PWM3_13_PINNAME
string "pwm[13] pin name"
default ""
config BSP_PWM3_14_PINNAME
string "pwm[14] pin name"
default ""
config BSP_PWM3_15_PINNAME
string "pwm[15] pin name"
default ""
endif
[bsp/cvitek]add pwm driver (#8571)
2024-03-02 16:16:22 +08:00
endif
Accumulated patchsets for bsp/cvitek (#8968) * bsp: cvitek: kconfig: add wdt for cv18xx_riscv Add Watchdog timer in Kconfig. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * drv: cvitek: remove using macro from source file Building of source file should be controlled by SConscript, but not in source file itself. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add i2c for cv18xx_riscv Add I2C in Kconfig for c906B. Note, the IRQ# is different from that of c906L. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add rtc for cv18xx_riscv Add RTC in Kconfig for c906B. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: fix channel issue for pwm driver The original code confuses the concepts of controllers and channels. Fixed it and do some code cleanup. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for cv18xx_riscv Pinmux in driver code is controlled by SOC type, bcos driver code should be general and support all pins defined by SoC. Pinmux configuration in Kconfig is controlled by BOARD type, bcos when we operate on board, it does not expose all chip-level pin signals and we can only use part of them. Following is I2C signals exported by duo family. Details see https://milkv.io/docs/duo/overview. Note: we have not added support for duo-S. Duo === NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo 256m ======== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo S ===== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> * bsp:cvitek: remove using macro from source file for i2c Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: unify menu message text for i2c as other drivers Other dirvers has no extra word "HW". Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for c906_little Porting what we have done in commit "bsp:cvitek: add i2c pinmux config for cv18xx_riscv" to c906_little. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> --------- Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> Co-authored-by: flyingcys <flyingcys@163.com>
2024-05-22 08:19:07 +08:00
config BSP_USING_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
[bsp]support cvitek sdhci drvier (#8849) support cvitek sdhci drvier
2024-04-24 05:40:22 +08:00
config BSP_USING_SDH
select RT_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
select RT_USING_DFS_ROMFS
bool "Enable Secure Digital Host Controller"
default n
[bsp/cvitek]add eth driver
2024-04-30 05:47:50 +08:00
config BSP_USING_ETH
bool "Enable Ethernet"
default n
select RT_USING_LWIP
select RT_USING_POSIX_FS
select RT_USING_POSIX_SOCKET
Accumulated patchsets for bsp/cvitek (#8968) * bsp: cvitek: kconfig: add wdt for cv18xx_riscv Add Watchdog timer in Kconfig. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * drv: cvitek: remove using macro from source file Building of source file should be controlled by SConscript, but not in source file itself. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add i2c for cv18xx_riscv Add I2C in Kconfig for c906B. Note, the IRQ# is different from that of c906L. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add rtc for cv18xx_riscv Add RTC in Kconfig for c906B. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: fix channel issue for pwm driver The original code confuses the concepts of controllers and channels. Fixed it and do some code cleanup. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for cv18xx_riscv Pinmux in driver code is controlled by SOC type, bcos driver code should be general and support all pins defined by SoC. Pinmux configuration in Kconfig is controlled by BOARD type, bcos when we operate on board, it does not expose all chip-level pin signals and we can only use part of them. Following is I2C signals exported by duo family. Details see https://milkv.io/docs/duo/overview. Note: we have not added support for duo-S. Duo === NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo 256m ======== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo S ===== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> * bsp:cvitek: remove using macro from source file for i2c Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: unify menu message text for i2c as other drivers Other dirvers has no extra word "HW". Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for c906_little Porting what we have done in commit "bsp:cvitek: add i2c pinmux config for cv18xx_riscv" to c906_little. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> --------- Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> Co-authored-by: flyingcys <flyingcys@163.com>
2024-05-22 08:19:07 +08:00
[bsp]add cv1800b (#7753)
2023-06-30 00:05:55 +08:00
endmenu