204 lines
11 KiB
C
204 lines
11 KiB
C
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////////////////////////////////////////////////////////////////////////////////
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/// @file reg_rtc.h
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/// @author AE TEAM
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/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
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/// MM32 FIRMWARE LIBRARY.
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#ifndef __REG_RTC_H
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#define __REG_RTC_H
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// Files includes
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#include <stdint.h>
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#include <stdbool.h>
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#include "types.h"
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC Base Address Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC_BASE (APB1PERIPH_BASE + 0x2800) ///< Base Address: 0x40002800
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC Registers Structure Definition
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////////////////////////////////////////////////////////////////////////////////
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typedef struct {
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union {
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__IO u32 CR; ///< Control Register, offset: 0x00
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__IO u32 CRH;
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};
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union {
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__IO u32 CSR; ///< Control & Status Register, offset: 0x04
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__IO u32 CRL;
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};
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__IO u32 PRLH; ///< Prescaler Reload Value High, offset: 0x08
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__IO u32 PRLL; ///< Prescaler Reload Value Low, offset: 0x0C
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__IO u32 DIVH; ///< Clock Divider High, offset: 0x10
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__IO u32 DIVL; ///< Clock Divider Low, offset: 0x14
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__IO u32 CNTH; ///< Counter High, offset: 0x18
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__IO u32 CNTL; ///< Counter Low, offset: 0x1C
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__IO u32 ALRH; ///< Alarm High, offset: 0x20
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__IO u32 ALRL; ///< Alarm Low, offset: 0x24
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__IO u32 MSRH; ///< Millisecond alarm high register offset: 0x28
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__IO u32 MSRL; ///< Millisecond alarm low register offset: 0x2C
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__IO u32 RESERVED0; ///< Reserved offset: 0x30
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__IO u32 RESERVED1; ///< Reserved offset: 0x34
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__IO u32 RESERVED2; ///< Reserved offset: 0x38
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__IO u32 LSE_CFG; ///< LSE configure register offset: 0x3C
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} RTC_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC type pointer Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC ((RTC_TypeDef*)RTC_BASE)
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC_CR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC_CR_SECIE_Pos (0)
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#define RTC_CR_SECIE (0x01U << RTC_CR_SECIE_Pos) ///< Second Interrupt Enable
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#define RTC_CR_ALRIE_Pos (1)
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#define RTC_CR_ALRIE (0x01U << RTC_CR_ALRIE_Pos) ///< Alarm Interrupt Enable
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#define RTC_CR_OWIE_Pos (2)
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#define RTC_CR_OWIE (0x01U << RTC_CR_OWIE_Pos) ///< OverfloW Interrupt Enable
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC_CSR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC_CSR_SECF_Pos (0)
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#define RTC_CSR_SECF (0x01 << RTC_CSR_SECF_Pos) ///< Second Flag
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#define RTC_CSR_ALRF_Pos (1)
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#define RTC_CSR_ALRF (0x01 << RTC_CSR_ALRF_Pos) ///< Alarm Flag
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#define RTC_CSR_OWF_Pos (2)
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#define RTC_CSR_OWF (0x01 << RTC_CSR_OWF_Pos) ///< OverfloW Flag
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#define RTC_CSR_RSF_Pos (3)
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#define RTC_CSR_RSF (0x01 << RTC_CSR_RSF_Pos) ///< Registers Synchronized Flag
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#define RTC_CSR_CNF_Pos (4)
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#define RTC_CSR_CNF (0x01 << RTC_CSR_CNF_Pos) ///< Configuration Flag
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#define RTC_CSR_RTOFF_Pos (5)
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#define RTC_CSR_RTOFF (0x01 << RTC_CSR_RTOFF_Pos) ///< RTC operation OFF
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#define RTC_CSR_ALPEN_Pos (6)
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#define RTC_CSR_ALPEN (0x01 << RTC_CSR_ALPEN_Pos) ///< RTC Alarm Loop Enable
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC_PRLH Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC_PRLH_PRL_Pos (0)
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#define RTC_PRLH_PRL (0x0F << RTC_PRLH_PRL_Pos) ///< RTC Prescaler Reload Value High
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC_PRLL Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC_PRLL_PRL_Pos (0)
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#define RTC_PRLL_PRL (0xFFFFU << RTC_PRLL_PRL_Pos) ///< RTC Prescaler Reload Value Low
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC_DIVH Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC_DIVH_DIV_Pos (0)
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#define RTC_DIVH_DIV (0x0F << RTC_DIVH_DIV_Pos) ///< RTC Clock Divider High
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC_DIVL Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC_DIVL_DIV_Pos (0)
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#define RTC_DIVL_DIV (0xFFFFU << RTC_DIVL_DIV_Pos) ///< RTC Clock Divider Low
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC_CNTH Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC_CNTH_CNT_Pos (0)
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#define RTC_CNTH_CNT (0xFFFFU << RTC_CNTH_CNT_Pos) ///< RTC Counter High
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC_CNTL Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC_CNTL_CNT_Pos (0)
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#define RTC_CNTL_CNT (0xFFFFU << RTC_CNTL_CNT_Pos) ///< RTC Counter Low
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC_ALRH Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC_ALRH_ALR_Pos (0)
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#define RTC_ALRH_ALR (0xFFFFU << RTC_ALRH_ALR_Pos) ///< RTC Alarm High
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC_ALRL Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC_ALRL_ALR_Pos (0)
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#define RTC_ALRL_ALR (0xFFFFU << RTC_ALRL_ALR_Pos) ///< RTC Alarm Low
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC_MSRH Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC_MSRH_MSR_Pos (0)
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#define RTC_MSRH_MSR (0xFFFFU << RTC_MSRH_MSR_Pos) ///< RTC MS Alarm Register High
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC_MSRL Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC_MSRL_MSR_Pos (0)
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#define RTC_MSRL_MSR (0xFFFFU << RTC_MSRL_MSR_Pos) ///< RTC MS Alarm Register Low
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC_LSE_CFG Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define RTC_LSE_CFG_TEST_Pos (0)
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#define RTC_LSE_CFG_TEST (0x0FU << RTC_LSE_CFG_TEST_Pos) ///< Test control signal
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#define RTC_LSE_CFG_DR_Pos (4)
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#define RTC_LSE_CFG_DR (0x03U << RTC_LSE_CFG_DR_Pos) ///< Drive capability selection
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#define RTC_LSE_CFG_RFB_SEL_Pos (6)
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#define RTC_LSE_CFG_RFB_SEL_3 (0x03U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 3M
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#define RTC_LSE_CFG_RFB_SEL_6 (0x02U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 6M
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#define RTC_LSE_CFG_RFB_SEL_10 (0x01U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 10M
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#define RTC_LSE_CFG_RFB_SEL_12 (0x00U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 12M
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#define RTC_LSE_CFG_IB_Pos (8)
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#define RTC_LSE_CFG_IB (0x01U << RTC_MSRL_MSR_Pos) ///< Bias current regulation
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/// @}
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/// @}
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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#endif
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////////////////////////////////////////////////////////////////////////////////
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