2020-09-11 10:11:25 +08:00
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/*
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* Copyright (C) 2017-2019 Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-20 zx.chen define default vector handlers.
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*/
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#include <csi_config.h>
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2021-07-14 20:12:55 +08:00
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#include <rtconfig.h>
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#include <cpuport.h>
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2020-09-11 10:11:25 +08:00
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/* Enable interrupts when returning from the handler */
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#define MSTATUS_PRV1 0x1880
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.section .bss
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.align 2
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.globl g_trapstackalloc
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.global g_trapstackbase
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.global g_top_trapstack
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g_trapstackalloc:
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g_trapstackbase:
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.space 768
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g_top_trapstack:
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.align 2
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.globl g_trap_sp
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.type g_trap_sp, object
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g_trap_sp:
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.long 0
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.size g_trap_sp, .-g_trap_sp
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irq_nested_level:
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.long 0
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#ifdef ARCH_RISCV_FPU
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irq_mstatus_fs_flag:
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.long 0
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#endif
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.text
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.align 2
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.global Default_IRQHandler
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.weak Default_IRQHandler
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.type Default_IRQHandler, %function
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Default_IRQHandler:
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ipush
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2021-07-14 20:12:55 +08:00
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#ifdef __riscv_flen
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2020-09-11 10:11:25 +08:00
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csrr t1, mstatus
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srli t1, t1, 13
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andi t1, t1, 0x3
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la t3, irq_mstatus_fs_flag
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sw t1, (t3)
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li t0, 0x3
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bne t1, t0, .F_RegNotSave1
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addi sp, sp, -(20 * FREGBYTES)
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FSTORE ft0, 0 * FREGBYTES(sp)
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FSTORE ft1, 1 * FREGBYTES(sp)
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FSTORE ft2, 2 * FREGBYTES(sp)
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FSTORE ft3, 3 * FREGBYTES(sp)
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FSTORE ft4, 4 * FREGBYTES(sp)
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FSTORE ft5, 5 * FREGBYTES(sp)
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FSTORE ft6, 6 * FREGBYTES(sp)
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FSTORE ft7, 7 * FREGBYTES(sp)
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FSTORE fa0, 8 * FREGBYTES(sp)
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FSTORE fa1, 9 * FREGBYTES(sp)
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FSTORE fa2, 10 * FREGBYTES(sp)
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FSTORE fa3, 11 * FREGBYTES(sp)
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FSTORE fa4, 12 * FREGBYTES(sp)
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FSTORE fa5, 13 * FREGBYTES(sp)
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FSTORE fa6, 14 * FREGBYTES(sp)
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FSTORE fa7, 15 * FREGBYTES(sp)
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FSTORE ft8, 16 * FREGBYTES(sp)
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FSTORE ft9, 17 * FREGBYTES(sp)
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FSTORE ft10, 18 * FREGBYTES(sp)
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FSTORE ft11, 19 * FREGBYTES(sp)
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.F_RegNotSave1:
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#endif
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csrr t1, mcause
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andi t1, t1, 0x3FF
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slli t1, t1, 2
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la t0, g_irqvector
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add t0, t0, t1
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lw t2, (t0)
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jalr t2
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li t0, MSTATUS_PRV1
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csrs mstatus, t0
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2021-07-14 20:12:55 +08:00
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#ifdef __riscv_flen
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2020-09-11 10:11:25 +08:00
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la t0, irq_mstatus_fs_flag
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lw t1, (t0)
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li t0, 0x3
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bne t1, t0, .F_RegNotLoad
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FLOAD ft0, 0 * FREGBYTES(sp)
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FLOAD ft1, 1 * FREGBYTES(sp)
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FLOAD ft2, 2 * FREGBYTES(sp)
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FLOAD ft3, 3 * FREGBYTES(sp)
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FLOAD ft4, 4 * FREGBYTES(sp)
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FLOAD ft5, 5 * FREGBYTES(sp)
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FLOAD ft6, 6 * FREGBYTES(sp)
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FLOAD ft7, 7 * FREGBYTES(sp)
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FLOAD fa0, 8 * FREGBYTES(sp)
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FLOAD fa1, 9 * FREGBYTES(sp)
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FLOAD fa2, 10 * FREGBYTES(sp)
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FLOAD fa3, 11 * FREGBYTES(sp)
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FLOAD fa4, 12 * FREGBYTES(sp)
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FLOAD fa5, 13 * FREGBYTES(sp)
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FLOAD fa6, 14 * FREGBYTES(sp)
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FLOAD fa7, 15 * FREGBYTES(sp)
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FLOAD ft8, 16 * FREGBYTES(sp)
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FLOAD ft9, 17 * FREGBYTES(sp)
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FLOAD ft10,18 * FREGBYTES(sp)
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FLOAD ft11,19 * FREGBYTES(sp)
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addi sp, sp, (20 * FREGBYTES)
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.F_RegNotLoad:
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#endif
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ipop
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/******************************************************************************
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* Functions:
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* void trap(void);
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* default exception handler
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******************************************************************************/
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.align 2
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.global trap
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.type trap, %function
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trap:
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/* Check for interrupt */
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2021-07-14 20:12:55 +08:00
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j .
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2020-09-11 10:11:25 +08:00
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addi sp, sp, -4
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sw t0, 0x0(sp)
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csrr t0, mcause
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blt t0, x0, .Lirq
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addi sp, sp, 4
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la t0, g_trap_sp
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addi t0, t0, -132
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sw x1, 0(t0)
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sw x2, 4(t0)
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sw x3, 8(t0)
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sw x4, 12(t0)
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sw x6, 20(t0)
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sw x7, 24(t0)
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sw x8, 28(t0)
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sw x9, 32(t0)
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sw x10, 36(t0)
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sw x11, 40(t0)
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sw x12, 44(t0)
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sw x13, 48(t0)
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sw x14, 52(t0)
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sw x15, 56(t0)
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sw x16, 60(t0)
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sw x17, 64(t0)
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sw x18, 68(t0)
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sw x19, 72(t0)
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sw x20, 76(t0)
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sw x21, 80(t0)
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sw x22, 84(t0)
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sw x23, 88(t0)
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sw x24, 92(t0)
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sw x25, 96(t0)
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sw x26, 100(t0)
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sw x27, 104(t0)
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sw x28, 108(t0)
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sw x29, 112(t0)
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sw x30, 116(t0)
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sw x31, 120(t0)
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csrr a0, mepc
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sw a0, 124(t0)
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csrr a0, mstatus
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sw a0, 128(t0)
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mv a0, t0
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lw t0, -4(sp)
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mv sp, a0
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sw t0, 16(sp)
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jal trap_c
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.Lirq:
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lw t0, 0x0(sp)
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addi sp, sp, 4
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j Default_IRQHandler
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.align 6
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.weak Default_Handler
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.global Default_Handler
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.type Default_Handler, %function
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Default_Handler:
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/* Check for nmi */
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addi sp, sp, -8
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sw t0, 0x0(sp)
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sw t1, 0x4(sp)
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csrr t0, mcause
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andi t0, t0, 0x3FF
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li t1, 24
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beq t0, t1, .NMI_Handler
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lw t0, 0x0(sp)
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lw t1, 0x4(sp)
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addi sp, sp, 8
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j trap
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.NMI_Handler:
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lw t0, 0x0(sp)
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lw t1, 0x4(sp)
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addi sp, sp, 8
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addi sp, sp, -64
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sw ra, 0(sp)
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sw t0, 4(sp)
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sw t1, 8(sp)
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sw t2, 12(sp)
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sw a0, 16(sp)
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sw a1, 20(sp)
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sw a2, 24(sp)
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sw a3, 28(sp)
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sw a4, 32(sp)
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sw a5, 36(sp)
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sw a6, 40(sp)
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sw a7, 44(sp)
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sw t3, 48(sp)
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sw t4, 52(sp)
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sw t5, 56(sp)
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sw t6, 60(sp)
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2021-07-14 20:12:55 +08:00
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#ifdef __riscv_flen
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2020-09-11 10:11:25 +08:00
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addi sp, sp, -(20*FREGBYTES)
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FSTORE ft0, 0 * FREGBYTES(sp)
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FSTORE ft1, 1 * FREGBYTES(sp)
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FSTORE ft2, 2 * FREGBYTES(sp)
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FSTORE ft3, 3 * FREGBYTES(sp)
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FSTORE ft4, 4 * FREGBYTES(sp)
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FSTORE ft5, 5 * FREGBYTES(sp)
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FSTORE ft6, 6 * FREGBYTES(sp)
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FSTORE ft7, 7 * FREGBYTES(sp)
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FSTORE fa0, 8 * FREGBYTES(sp)
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FSTORE fa1, 9 * FREGBYTES(sp)
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FSTORE fa2, 10 * FREGBYTES(sp)
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FSTORE fa3, 11 * FREGBYTES(sp)
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FSTORE fa4, 12 * FREGBYTES(sp)
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FSTORE fa5, 13 * FREGBYTES(sp)
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FSTORE fa6, 14 * FREGBYTES(sp)
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FSTORE fa7, 15 * FREGBYTES(sp)
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FSTORE ft8, 16 * FREGBYTES(sp)
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FSTORE ft9, 17 * FREGBYTES(sp)
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FSTORE ft10, 18 * FREGBYTES(sp)
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FSTORE ft11, 19 * FREGBYTES(sp)
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#endif
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la t0, g_nmivector
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lw t0, (t0)
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jalr t0
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2021-07-14 20:12:55 +08:00
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#ifdef __riscv_flen
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2020-09-11 10:11:25 +08:00
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FLOAD ft0, 0 * FREGBYTES(sp)
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FLOAD ft1, 1 * FREGBYTES(sp)
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FLOAD ft2, 2 * FREGBYTES(sp)
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FLOAD ft3, 3 * FREGBYTES(sp)
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FLOAD ft4, 4 * FREGBYTES(sp)
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FLOAD ft5, 5 * FREGBYTES(sp)
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FLOAD ft6, 6 * FREGBYTES(sp)
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FLOAD ft7, 7 * FREGBYTES(sp)
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FLOAD fa0, 8 * FREGBYTES(sp)
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FLOAD fa1, 9 * FREGBYTES(sp)
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FLOAD fa2, 10 * FREGBYTES(sp)
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FLOAD fa3, 11 * FREGBYTES(sp)
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FLOAD fa4, 12 * FREGBYTES(sp)
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FLOAD fa5, 13 * FREGBYTES(sp)
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FLOAD fa6, 14 * FREGBYTES(sp)
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FLOAD fa7, 15 * FREGBYTES(sp)
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FLOAD ft8, 16 * FREGBYTES(sp)
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FLOAD ft9, 17 * FREGBYTES(sp)
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FLOAD ft10, 18 * FREGBYTES(sp)
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FLOAD ft11, 19 * FREGBYTES(sp)
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addi sp, sp, (20 * FREGBYTES)
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#endif
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lw ra, 0(sp)
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lw t0, 4(sp)
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lw t1, 8(sp)
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lw t2, 12(sp)
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lw a0, 16(sp)
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lw a1, 20(sp)
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lw a2, 24(sp)
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lw a3, 28(sp)
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lw a4, 32(sp)
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lw a5, 36(sp)
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lw a6, 40(sp)
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lw a7, 44(sp)
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lw t3, 48(sp)
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lw t4, 52(sp)
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lw t5, 56(sp)
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lw t6, 60(sp)
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addi sp, sp, 64
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mret
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.size Default_Handler, . - Default_Handler
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.globl \handler_name
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.set \handler_name, Default_Handler
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.endm
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
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def_irq_handler STIM0_IRQHandler
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def_irq_handler STIM1_IRQHandler
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def_irq_handler STIM2_IRQHandler
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def_irq_handler STIM3_IRQHandler
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def_irq_handler TIM0_IRQHandler
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def_irq_handler TIM1_IRQHandler
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def_irq_handler TIM2_IRQHandler
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def_irq_handler TIM3_IRQHandler
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def_irq_handler USART_IRQHandler
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def_irq_handler GPIO0_IRQHandler
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def_irq_handler GPIO1_IRQHandler
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def_irq_handler GPIO2_IRQHandler
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def_irq_handler GPIO3_IRQHandler
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def_irq_handler GPIO4_IRQHandler
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def_irq_handler GPIO5_IRQHandler
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def_irq_handler GPIO6_IRQHandler
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def_irq_handler GPIO7_IRQHandler
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def_irq_handler PAD_IRQHandler
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def_irq_handler TIM6_IRQHandler
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def_irq_handler TIM7_IRQHandler
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def_irq_handler TIM8_IRQHandler
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def_irq_handler TIM9_IRQHandler
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def_irq_handler TIM10_IRQHandler
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def_irq_handler TIM11_IRQHandler
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