2020-09-11 10:11:25 +08:00
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/*
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* Copyright (C) 2017-2019 Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-20 zx.chen header file for timer driver
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*/
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#ifndef __DW_TIMER_H
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#define __DW_TIMER_H
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#include <stdio.h>
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#include "soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* define the bits for TxControl
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*/
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#define DW_TIMER_TXCONTROL_ENABLE (1UL << 0)
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#define DW_TIMER_TXCONTROL_MODE (1UL << 1)
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#define DW_TIMER_TXCONTROL_INTMASK (1UL << 2)
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#define DW_TIMER_TXCONTROL_TRIGGER (1UL << 4)
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#define DW_TIMER_INIT_DEFAULT_VALUE (0xffffffff / drv_get_timer_freq(0) * 1000000)
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typedef struct
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{
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__IOM uint32_t TxLoadCount; /* Offset: 0x000 (R/W) Receive buffer register */
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__IM uint32_t TxCurrentValue; /* Offset: 0x004 (R) Transmission hold register */
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__IOM uint8_t TxControl: 5; /* Offset: 0x008 (R/W) Clock frequency division low section register */
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2021-08-06 17:21:19 +08:00
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uint8_t RESERVED0[3];
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2020-09-11 10:11:25 +08:00
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__IM uint8_t TxEOI: 1; /* Offset: 0x00c (R) Clock frequency division high section register */
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2021-08-06 17:21:19 +08:00
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uint8_t RESERVED1[3];
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2020-09-11 10:11:25 +08:00
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__IM uint8_t TxIntStatus: 1; /* Offset: 0x010 (R) Interrupt enable register */
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2021-08-06 17:21:19 +08:00
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uint8_t RESERVED2[3];
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2020-09-11 10:11:25 +08:00
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} dw_timer_reg_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DW_TIMER_H */
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