339 lines
9.0 KiB
C
339 lines
9.0 KiB
C
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#include <nds32_intrinsic.h>
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#include "debug.h"
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#include "nds32.h"
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#include "cache.h"
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#define CACHE_NONE 0
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#define CACHE_WRITEBACK 2
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#define CACHE_WRITETHROUGH 3
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#if (defined(CONFIG_CPU_ICACHE_ENABLE) || defined(CONFIG_CPU_DCACHE_ENABLE))
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/* Cacheable */
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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#define CACHE_MODE CACHE_WRITETHROUGH
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#else
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#define CACHE_MODE CACHE_WRITEBACK
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#endif
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#else
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/* Uncacheable */
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#define CACHE_MODE CACHE_NONE
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#endif
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#define MMU_CTL_MSK \
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(MMU_CTL_mskD \
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| MMU_CTL_mskNTC0 \
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| MMU_CTL_mskNTC1 \
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| MMU_CTL_mskNTC2 \
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| MMU_CTL_mskNTC3 \
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| MMU_CTL_mskTBALCK \
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| MMU_CTL_mskMPZIU \
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| MMU_CTL_mskNTM0 \
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| MMU_CTL_mskNTM1 \
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| MMU_CTL_mskNTM2 \
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| MMU_CTL_mskNTM3)
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/*
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* NTC0: CACHE_MODE, NTC1~NTC3: Non-cacheable
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* MSC_CFG.ADR24 = 0 : NTM0~NTM3 are mapped to partition 0/0/0/0
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* MSC_CFG.ADR24 = 1 : NTM0~NTM3 are mapped to partition 0/1/2/3
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*/
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#define MMU_CTL_INIT \
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(0x0UL << MMU_CTL_offD \
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| (CACHE_MODE) << MMU_CTL_offNTC0 \
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| 0x0UL << MMU_CTL_offNTC1 \
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| 0x0UL << MMU_CTL_offNTC2 \
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| 0x0UL << MMU_CTL_offNTC3 \
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| 0x0UL << MMU_CTL_offTBALCK \
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| 0x0UL << MMU_CTL_offMPZIU \
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| 0x0UL << MMU_CTL_offNTM0 \
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| 0x0UL << MMU_CTL_offNTM1 \
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| 0x0UL << MMU_CTL_offNTM2 \
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| 0x0UL << MMU_CTL_offNTM3)
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#define MMU_CTL_INIT_ADR24 \
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(MMU_CTL_INIT \
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| 0x0UL << MMU_CTL_offNTM0 \
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| 0x1UL << MMU_CTL_offNTM1 \
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| 0x2UL << MMU_CTL_offNTM2 \
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| 0x3UL << MMU_CTL_offNTM3)
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#define CACHE_CTL_MSK \
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(CACHE_CTL_mskIC_EN \
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| CACHE_CTL_mskDC_EN \
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| CACHE_CTL_mskICALCK \
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| CACHE_CTL_mskDCALCK \
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| CACHE_CTL_mskDCCWF \
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| CACHE_CTL_mskDCPMW)
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/* ICache/DCache enable */
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#define CACHE_CTL_CACHE_ON \
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(0x1UL << CACHE_CTL_offIC_EN \
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| 0x1UL << CACHE_CTL_offDC_EN \
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| 0x0UL << CACHE_CTL_offICALCK \
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| 0x0UL << CACHE_CTL_offDCALCK \
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| 0x1UL << CACHE_CTL_offDCCWF \
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| 0x1UL << CACHE_CTL_offDCPMW)
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/*
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* Interrupt priority :
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* PIT(IRQ #2): highest priority
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* Others: lowest priority
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*/
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#define PRI1_DEFAULT 0xFFFFFFFF
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#define PRI2_DEFAULT 0xFFFFFFFF
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/* This must be a leaf function, no child function */
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void _nds32_init_mem(void) __attribute__((naked, optimize("Os")));
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void _nds32_init_mem(void)
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{
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/* Enable DLM */
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__nds32__mtsr(EDLM_BASE | 0x1, NDS32_SR_DLMB);
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__nds32__dsb();
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}
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/*
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* Initialize MMU configure and cache ability.
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*/
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static void mmu_init(void)
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{
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//#ifndef __NDS32_ISA_V3M__
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// unsigned int reg;
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//
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// /* MMU initialization: NTC0~NTC3, NTM0~NTM3 */
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// reg = (__nds32__mfsr(NDS32_SR_MMU_CTL) & ~MMU_CTL_MSK) | MMU_CTL_INIT;
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//
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// if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskADR24)
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// reg = (__nds32__mfsr(NDS32_SR_MMU_CTL) & ~MMU_CTL_MSK) | MMU_CTL_INIT_ADR24;
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// else
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// reg = (__nds32__mfsr(NDS32_SR_MMU_CTL) & ~MMU_CTL_MSK) | MMU_CTL_INIT;
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//
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// __nds32__mtsr(reg, NDS32_SR_MMU_CTL);
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// __nds32__dsb();
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//#endif
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}
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/*
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* Platform specific initialization
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*/
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static void plf_init(void)
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{
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/* Set default Hardware interrupts priority */
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__nds32__mtsr(PRI1_DEFAULT, NDS32_SR_INT_PRI);
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__nds32__mtsr(PRI2_DEFAULT, NDS32_SR_INT_PRI2);
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/* Mask all HW interrupts except SWI */
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__nds32__mtsr((1 << IRQ_SYS_TICK_VECTOR) | (1 << IRQ_SWI_VECTOR), NDS32_SR_INT_MASK2);
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/* Reset the PIT (timers) */
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REG32(PIT_INT_EN) = 0; /* disable all timer interrupt */
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REG32(PIT_CH_EN) = 0; /* disable all timer */
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REG32(PIT_INT_ST) = -1; /* clear pending events */
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REG32(PIT_CHNx_LOAD(0)) = 0; /* clean channel 0 reload */
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REG32(PIT_CHNx_LOAD(1)) = 0; /* clean channel 1 reload */
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REG32(PIT_CHNx_LOAD(2)) = 0; /* clean channel 2 reload */
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REG32(PIT_CHNx_LOAD(3)) = 0; /* clean channel 3 reload */
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}
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/*
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* All AE210P hardware initialization
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*/
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void hardware_init(void)
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{
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mmu_init(); /* mmu/cache */
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plf_init(); /* Perform any platform specific initializations */
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#if (defined(CONFIG_CPU_ICACHE_ENABLE) || defined(CONFIG_CPU_DCACHE_ENABLE))
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unsigned int reg;
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/* Invalid ICache */
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nds32_icache_flush();
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/* Invalid DCache */
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nds32_dcache_invalidate();
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/* Enable I/Dcache */
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reg = (__nds32__mfsr(NDS32_SR_CACHE_CTL) & ~CACHE_CTL_MSK) | CACHE_CTL_CACHE_ON;
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__nds32__mtsr(reg, NDS32_SR_CACHE_CTL);
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#endif
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}
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/********************************
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* HAL Level : Interrupt
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********************************/
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/* 32IVIC without SOC INTC */
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/*
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* mask/unmask priority >= _irqs_ interrupts
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* used in ISR & gie diable
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*/
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uint32_t hal_intc_irq_mask(int _irqs_)
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{
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uint32_t prv_msk = __nds32__mfsr(NDS32_SR_INT_MASK2);
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if (_irqs_ == -1 )
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{
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__nds32__mtsr(0, NDS32_SR_INT_MASK2);
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}
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else if (_irqs_ < 32 )
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{
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SR_CLRB32(NDS32_SR_INT_MASK2,_irqs_);
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}
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else
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{
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DEBUG(1,1,"_irqs_:%d, is invalid!\r\n",_irqs_);
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return -1;
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}
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return prv_msk;
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}
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void hal_intc_irq_unmask(uint32_t _msk_)
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{
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__nds32__mtsr( _msk_ , NDS32_SR_INT_MASK2);
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}
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void hal_intc_irq_clean(int _irqs_)
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{
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if ( _irqs_ == IRQ_SWI_VECTOR )
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{
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SR_CLRB32(NDS32_SR_INT_PEND, INT_PEND_offSWI);
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}
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else
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{
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/* PEND2 is W1C */
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SR_SETB32(NDS32_SR_INT_PEND2,_irqs_);
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}
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}
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void hal_intc_irq_clean_all()
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{
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__nds32__mtsr(-1,NDS32_SR_INT_PEND2);
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}
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void hal_intc_irq_disable(int _irqs_)
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{
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SR_CLRB32(NDS32_SR_INT_MASK2,_irqs_);
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}
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void hal_intc_irq_disable_all()
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{
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__nds32__mtsr(0x0,NDS32_SR_INT_MASK2);
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}
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void hal_intc_irq_enable(int _irqs_)
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{
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SR_SETB32(NDS32_SR_INT_MASK2,_irqs_);
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}
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void hal_intc_irq_set_priority( uint32_t _prio1_, uint32_t _prio2_ )
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{
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__nds32__mtsr(_prio1_, NDS32_SR_INT_PRI);
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__nds32__mtsr(_prio2_, NDS32_SR_INT_PRI2);
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}
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void hal_intc_irq_config(uint8_t _irq_, uint8_t _edge_, uint8_t _falling_){}
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void hal_intc_swi_enable()
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{
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//SR_SETB32(NDS32_SR_INT_MASK,16);
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SR_SETB32(NDS32_SR_INT_MASK2,IRQ_SWI_VECTOR);
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}
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void hal_intc_swi_disable()
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{
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SR_CLRB32(NDS32_SR_INT_MASK2,IRQ_SWI_VECTOR);
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}
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void hal_intc_swi_clean()
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{
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SR_CLRB32(NDS32_SR_INT_PEND, INT_PEND_offSWI);
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}
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void hal_intc_swi_trigger()
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{
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SR_SETB32(NDS32_SR_INT_PEND,INT_PEND_offSWI);
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}
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uint32_t hal_intc_get_all_pend()
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{
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return __nds32__mfsr(NDS32_SR_INT_PEND2);
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}
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/********************************
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* TIMER HAL Function
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********************************/
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static const uint8_t timer_irq[4] = {IRQ_PIT_VECTOR, IRQ_PIT_VECTOR, IRQ_PIT_VECTOR, IRQ_PIT_VECTOR};
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uint32_t hal_timer_irq_mask(uint32_t _tmr_ )
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{
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return hal_intc_irq_mask(timer_irq[_tmr_-1]);
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}
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void hal_timer_irq_unmask(uint32_t _msk_ )
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{
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hal_intc_irq_unmask(_msk_);
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}
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void hal_timer_irq_clear(uint32_t _tmr_ )
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{
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/* Clean IP pending, W1C */
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#ifndef CONFIG_TX_DEMO
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REG32(PIT_INT_ST) = (0x1 << (5*(_tmr_-1)));
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#endif
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hal_intc_irq_clean(timer_irq[_tmr_-1]);
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}
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void hal_timer_set_period(uint32_t _tmr_, uint32_t _period_ )
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{
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REG32(PIT_CHNx_LOAD(_tmr_-1)) = _period_;
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//REG32(PIT_CHNx_COUNT(_tmr_-1))= _period_;
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}
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void hal_timer_irq_control(uint32_t _tmr_, uint32_t enable )
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{
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if (enable)
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REG32(PIT_INT_EN) = REG32(PIT_INT_EN) | (0x1 << (5*(_tmr_-1)));
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else
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REG32(PIT_INT_EN) = REG32(PIT_INT_EN) & ~(0x1 << (5*(_tmr_-1)));
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}
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void hal_timer_set_upward(uint32_t _tmr_ ,uint32_t up)
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{
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if ( up )
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DEBUG(1,1,"PIT Timer only support downward!\r\n");
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}
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void hal_timer_start(uint32_t _tmr_)
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{
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/* config channel mode */
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/* 32 bits timer, APB clock */
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REG32(PIT_CHNx_CTL(_tmr_-1)) = ( PIT_CH_CTL_APBCLK | PIT_CH_CTL_TMR32 );
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/* enable channel */
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REG32(PIT_CH_EN) = REG32(PIT_CH_EN) | (0x1 << (5*(_tmr_-1)));
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}
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void hal_timer_stop(uint32_t _tmr_ )
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{
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REG32(PIT_CH_EN) = REG32(PIT_CH_EN) & ~(0x1 << (5*(_tmr_-1)));
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}
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uint32_t hal_timer_read(uint32_t _tmr_ )
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{
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/* By default, timer would decrease from load value to 0 */
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return REG32( PIT_CHNx_LOAD(_tmr_-1) ) - REG32( PIT_CHNx_COUNT(_tmr_-1) );
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}
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uint32_t hal_timer_count_read(uint32_t _tmr_ )
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{
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return REG32( PIT_CHNx_COUNT(_tmr_-1) );
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}
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uint32_t hal_timer_irq_status(uint32_t _tmr_)
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{
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/* return PIT int status */
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/* PIT need #channel & #timer */
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/* just return all int status */
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return REG32(PIT_INT_ST);
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}
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