340 lines
11 KiB
C
340 lines
11 KiB
C
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/*****************************************************************************
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* Copyright (c) 2019, Nations Technologies Inc.
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*
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* All rights reserved.
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* ****************************************************************************
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Nations' name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ****************************************************************************/
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/**
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* @file drv_spi.c
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* @author Nations
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* @version v1.0.0
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*
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* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
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*/
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#include "drv_spi.h"
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#if defined(RT_USING_SPI) && defined(RT_USING_PIN)
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#include <rtdevice.h>
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#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || \
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defined(BSP_USING_SPI3)
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/* #define DEBUG */
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#ifdef DEBUG
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#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
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#else
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#define DEBUG_PRINTF(...)
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#endif
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/* private rt-thread spi ops function */
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static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration)
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{
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SPI_InitType SPI_InitStructure;
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RCC_ClocksType RCC_ClockFreq;
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SPI_Module* spi_periph;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(configuration != RT_NULL);
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RCC_GetClocksFreqValue(&RCC_ClockFreq);
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spi_periph = (SPI_Module*)device->bus->parent.user_data;
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if(spi_periph != SPI1 && spi_periph != SPI2 && spi_periph != SPI3)
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{
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return RT_EIO;
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}
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if(configuration->data_width <= 8)
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{
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SPI_InitStructure.DataLen = SPI_DATA_SIZE_8BITS;
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}
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else if(configuration->data_width <= 16)
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{
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SPI_InitStructure.DataLen = SPI_DATA_SIZE_16BITS;
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}
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else
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{
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return RT_EIO;
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}
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{
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rt_uint32_t spi_apb_clock;
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rt_uint32_t max_hz;
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max_hz = configuration->max_hz;
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DEBUG_PRINTF("sys freq: %d\n", RCC_ClockFreq.SysclkFreq);
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DEBUG_PRINTF("CK_APB2 freq: %d\n", RCC_ClockFreq.Pclk2Freq);
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DEBUG_PRINTF("max freq: %d\n", max_hz);
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if (spi_periph == SPI1)
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{
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spi_apb_clock = RCC_ClockFreq.Pclk2Freq;
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}
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else
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{
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spi_apb_clock = RCC_ClockFreq.Pclk1Freq;
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}
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if(max_hz >= spi_apb_clock/2)
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{
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SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_2;
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}
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else if (max_hz >= spi_apb_clock/4)
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{
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SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_4;
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}
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else if (max_hz >= spi_apb_clock/8)
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{
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SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_8;
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}
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else if (max_hz >= spi_apb_clock/16)
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{
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SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_16;
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}
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else if (max_hz >= spi_apb_clock/32)
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{
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SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_32;
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}
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else if (max_hz >= spi_apb_clock/64)
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{
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SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_64;
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}
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else if (max_hz >= spi_apb_clock/128)
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{
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SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_128;
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}
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else
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{
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/* min prescaler 256 */
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SPI_InitStructure.BaudRatePres = SPI_BR_PRESCALER_256;
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}
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} /* baudrate */
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switch(configuration->mode & RT_SPI_MODE_3)
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{
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case RT_SPI_MODE_0:
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SPI_InitStructure.CLKPOL = SPI_CLKPOL_LOW;
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SPI_InitStructure.CLKPHA = SPI_CLKPHA_FIRST_EDGE;
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break;
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case RT_SPI_MODE_1:
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SPI_InitStructure.CLKPOL = SPI_CLKPOL_LOW;
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SPI_InitStructure.CLKPHA = SPI_CLKPHA_SECOND_EDGE;
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break;
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case RT_SPI_MODE_2:
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SPI_InitStructure.CLKPOL = SPI_CLKPOL_HIGH;
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SPI_InitStructure.CLKPHA = SPI_CLKPHA_FIRST_EDGE;
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break;
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case RT_SPI_MODE_3:
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SPI_InitStructure.CLKPOL = SPI_CLKPOL_HIGH;
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SPI_InitStructure.CLKPHA = SPI_CLKPHA_SECOND_EDGE;
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break;
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}
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/* MSB or LSB */
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if(configuration->mode & RT_SPI_MSB)
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{
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SPI_InitStructure.FirstBit = SPI_FB_MSB;
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}
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else
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{
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SPI_InitStructure.FirstBit = SPI_FB_LSB;
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}
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/*!< SPI configuration */
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SPI_InitStructure.DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX;
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SPI_InitStructure.SpiMode = SPI_MODE_MASTER;
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SPI_InitStructure.CLKPHA = SPI_CLKPHA_SECOND_EDGE;
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SPI_InitStructure.NSS = SPI_NSS_SOFT;
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SPI_InitStructure.CRCPoly = 7;
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SPI_Init(spi_periph, &SPI_InitStructure);
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/*!< Enable the sFLASH_SPI */
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SPI_Enable(spi_periph, ENABLE);
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return RT_EOK;
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}
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static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message)
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{
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struct n32_spi_cs *cs_pin = device->parent.user_data;
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SPI_Module* spi_periph = (SPI_Module*)device->bus->parent.user_data;
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struct rt_spi_configuration * config = &device->config;
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RT_ASSERT(device != NULL);
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RT_ASSERT(message != NULL);
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/* take CS */
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if(message->cs_take)
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{
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rt_pin_write(cs_pin->GPIO_Pin, PIN_LOW);
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DEBUG_PRINTF("spi take cs\n");
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}
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{
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if(config->data_width <= 8)
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{
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const rt_uint8_t * send_ptr = message->send_buf;
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rt_uint8_t * recv_ptr = message->recv_buf;
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rt_uint32_t size = message->length;
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DEBUG_PRINTF("spi poll transfer start: %d\n", size);
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while(size--)
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{
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rt_uint8_t data = 0xA5;
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if(send_ptr != RT_NULL)
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{
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data = *send_ptr++;
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}
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/*!< Loop while DAT register in not emplty */
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while (SPI_I2S_GetStatus(spi_periph, SPI_I2S_TE_FLAG) == RESET);
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// Send the byte
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SPI_I2S_TransmitData(spi_periph, data);
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//Wait until a data is received
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while(SPI_I2S_GetStatus(spi_periph, SPI_I2S_RNE_FLAG) == RESET);
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// Get the received data
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data = SPI_I2S_ReceiveData(spi_periph);
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if(recv_ptr != RT_NULL)
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{
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*recv_ptr++ = data;
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}
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}
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DEBUG_PRINTF("spi poll transfer finsh\n");
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}
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else if(config->data_width <= 16)
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{
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const rt_uint16_t * send_ptr = message->send_buf;
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rt_uint16_t * recv_ptr = message->recv_buf;
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rt_uint32_t size = message->length;
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while(size--)
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{
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rt_uint16_t data = 0xFF;
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if(send_ptr != RT_NULL)
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{
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data = *send_ptr++;
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}
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/*!< Loop while DAT register in not emplty */
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while (SPI_I2S_GetStatus(spi_periph, SPI_I2S_TE_FLAG) == RESET);
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// Send the byte
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SPI_I2S_TransmitData(spi_periph, data);
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//Wait until a data is received
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while(RESET == SPI_I2S_GetStatus(spi_periph, SPI_I2S_RNE_FLAG));
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// Get the received data
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data = SPI_I2S_ReceiveData(spi_periph);
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if(recv_ptr != RT_NULL)
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{
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*recv_ptr++ = data;
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}
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}
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}
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}
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/* release CS */
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if(message->cs_release)
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{
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rt_pin_write(cs_pin->GPIO_Pin, PIN_HIGH);
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DEBUG_PRINTF("spi release cs\n");
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}
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return message->length;
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}
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static struct rt_spi_ops spi_ops =
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{
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configure,
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xfer
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};
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int rt_hw_spi_init(void)
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{
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int result = 0;
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#ifdef BSP_USING_SPI1
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static struct rt_spi_bus spi_bus1;
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spi_bus1.parent.user_data = (void *)SPI1;
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result = rt_spi_bus_register(&spi_bus1, "spi1", &spi_ops);
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RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
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RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_SPI1, ENABLE);
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/* SPI1_SCK(PA5), SPI1_MISO(PA6) and SPI1_MOSI(PA7) GPIO pin configuration */
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GPIOInit(SPI1_SCK_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI1_SCK_PIN);
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GPIOInit(SPI1_MOSI_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI1_MOSI_PIN);
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GPIOInit(SPI1_MISO_GPIO_PORT, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, SPI1_MISO_PIN);
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#endif
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#ifdef BSP_USING_SPI2
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static struct rt_spi_bus spi_bus2;
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spi_bus2.parent.user_data = (void *)SPI2;
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result = rt_spi_bus_register(&spi_bus2, "spi2", &spi_ops);
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RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI2, ENABLE);
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/* SPI2_SCK(PB13), SPI2_MISO(PB14) and SPI2_MOSI(PB15) GPIO pin configuration */
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GPIOInit(SPI2_SCK_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI2_SCK_PIN);
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GPIOInit(SPI2_MOSI_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI2_MOSI_PIN);
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GPIOInit(SPI2_MISO_GPIO_PORT, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, SPI2_MISO_PIN);
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#endif
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#ifdef BSP_USING_SPI3
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static struct rt_spi_bus spi_bus3;
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spi_bus3.parent.user_data = (void *)SPI3;
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result = rt_spi_bus_register(&spi_bus3, "spi3", &spi_ops);
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/* Enable AFIO clock */
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RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
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GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_SW_ENABLE, ENABLE);
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RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_SPI3, ENABLE);
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/* SPI3_SCK(PB3), SPI3_MISO(PB4) and SPI3_MOSI(PB5) GPIO pin configuration */
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GPIOInit(SPI3_SCK_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI3_SCK_PIN);
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GPIOInit(SPI3_MOSI_GPIO_PORT, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, SPI3_MOSI_PIN);
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GPIOInit(SPI3_MISO_GPIO_PORT, GPIO_Mode_IN_FLOATING, GPIO_Speed_50MHz, SPI3_MISO_PIN);
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#endif
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_spi_init);
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#endif /* defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) */
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#endif
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