2023-05-11 10:25:21 +08:00
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/*
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2023-08-02 13:27:09 +08:00
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* Copyright (c) 2006-2023, RT-Thread Development Team
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2023-05-11 10:25:21 +08:00
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*
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2023-08-02 13:27:09 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2023-05-11 10:25:21 +08:00
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*
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2023-08-02 13:27:09 +08:00
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* Email: opensource_embedded@phytium.com.cn
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2023-05-11 10:25:21 +08:00
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*
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2023-08-02 13:27:09 +08:00
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* Change Logs:
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* Date Author Notes
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* 2022-07-07 liuzhihong first commit
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* 2023-07-14 liuzhihong support RT-Smart
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2023-05-11 10:25:21 +08:00
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*/
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2023-08-02 13:27:09 +08:00
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#ifndef __DRV_XMAC_H__
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#define __DRV_XMAC_H__
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#include <rtthread.h>
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#include <rtdevice.h>
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2023-11-21 17:42:23 +08:00
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#ifdef BSP_USING_ETH
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2023-08-02 13:27:09 +08:00
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#include <netif/ethernetif.h>
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#include "fxmac.h"
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#include "fkernel.h"
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#include "ferror_code.h"
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#include "fassert.h"
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#include "fxmac_bdring.h"
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#include "eth_ieee_reg.h"
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#include "fcpu_info.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define FREERTOS_XMAC_INIT_ERROR FT_CODE_ERR(ErrModPort, 0, 0x1)
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#define FREERTOS_XMAC_PARAM_ERROR FT_CODE_ERR(ErrModPort, 0, 0x2)
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#define FREERTOS_XMAC_NO_VALID_SPACE FT_CODE_ERR(ErrModPort, 0, 0x3)
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#define FXMAX_RX_BDSPACE_LENGTH 0x20000 /* default set 128KB*/
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#define FXMAX_TX_BDSPACE_LENGTH 0x20000 /* default set 128KB*/
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#define FXMAX_RX_PBUFS_LENGTH 16
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#define FXMAX_TX_PBUFS_LENGTH 16
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#define FXMAX_MAX_HARDWARE_ADDRESS_LENGTH 6
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/* configuration */
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#define FXMAC_OS_CONFIG_JUMBO BIT(0)
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#define FXMAC_OS_CONFIG_MULTICAST_ADDRESS_FILITER BIT(1) /* Allow multicast address filtering */
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#define FXMAC_OS_CONFIG_COPY_ALL_FRAMES BIT(2) /* enable copy all frames */
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#define FXMAC_OS_CONFIG_CLOSE_FCS_CHECK BIT(3) /* close fcs check */
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#define FXMAC_OS_CONFIG_RX_POLL_RECV BIT(4) /* select poll mode */
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/* Phy */
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#define FXMAC_PHY_SPEED_10M 10
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#define FXMAC_PHY_SPEED_100M 100
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#define FXMAC_PHY_SPEED_1000M 1000
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#define FXMAC_PHY_HALF_DUPLEX 0
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#define FXMAC_PHY_FULL_DUPLEX 1
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#define MAX_FRAME_SIZE_JUMBO (FXMAC_MTU_JUMBO + FXMAC_HDR_SIZE + FXMAC_TRL_SIZE)
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/* Byte alignment of BDs */
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#define BD_ALIGNMENT (FXMAC_DMABD_MINIMUM_ALIGNMENT*2)
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/* frame queue */
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#define PQ_QUEUE_SIZE 4096
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#define LINK_THREAD_STACK_LENGTH 0x20400
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typedef struct
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{
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uintptr data[PQ_QUEUE_SIZE];
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int head, tail, len;
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} PqQueue;
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typedef enum
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{
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FXMAC_OS_INTERFACE_SGMII = 0,
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FXMAC_OS_INTERFACE_RMII,
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FXMAC_OS_INTERFACE_RGMII,
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FXMAC_OS_INTERFACE_LENGTH
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} FXmacRtThreadInterface;
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typedef struct
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{
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u8 rx_bdspace[FXMAX_RX_BDSPACE_LENGTH] __attribute__((aligned(128))); /* 接收bd 缓冲区 */
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u8 tx_bdspace[FXMAX_RX_BDSPACE_LENGTH] __attribute__((aligned(128))); /* 发送bd 缓冲区 */
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uintptr rx_pbufs_storage[FXMAX_RX_PBUFS_LENGTH];
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uintptr tx_pbufs_storage[FXMAX_TX_PBUFS_LENGTH];
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} FXmacNetifBuffer;
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typedef struct
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{
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u32 instance_id;
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FXmacRtThreadInterface interface;
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u32 autonegotiation; /* 1 is autonegotiation ,0 is manually set */
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u32 phy_speed; /* FXMAC_PHY_SPEED_XXX */
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u32 phy_duplex; /* FXMAC_PHY_XXX_DUPLEX */
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} FXmacOsControl;
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typedef struct
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{
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struct eth_device parent; /* inherit from ethernet device */
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FXmac instance; /* Xmac controller */
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FXmacOsControl mac_config;
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FXmacNetifBuffer buffer; /* DMA buffer */
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/* queue to store overflow packets */
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PqQueue recv_q;
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PqQueue send_q;
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/* configuration */
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u32 config;
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2024-01-03 18:03:21 +08:00
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u32 is_link_up;
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2023-08-02 13:27:09 +08:00
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rt_uint8_t hwaddr[FXMAX_MAX_HARDWARE_ADDRESS_LENGTH]; /* MAC address */
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struct rt_thread _link_thread; /* link detect thread */
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rt_uint8_t _link_thread_stack[LINK_THREAD_STACK_LENGTH];/* link detect thread stack*/
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} FXmacOs;
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enum lwip_port_link_status
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{
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ETH_LINK_UNDEFINED = 0,
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ETH_LINK_UP,
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ETH_LINK_DOWN,
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ETH_LINK_NEGOTIATING
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};
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#ifdef __cplusplus
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}
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#endif
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#endif // !
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2023-11-21 17:42:23 +08:00
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#endif
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