2020-06-23 10:43:18 +08:00
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/*
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2023-01-09 10:20:16 +08:00
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* Copyright (c) 2006-2023, RT-Thread Development Team
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2020-06-23 10:43:18 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-06-18 thread-liu the first version
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2020-10-09 10:06:47 +08:00
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* 2020-10-09 thread-liu Porting for stm32h7xx
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2020-06-23 10:43:18 +08:00
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*/
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#include <board.h>
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2024-01-08 00:21:51 +08:00
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#include <rtthread.h>
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2020-06-23 10:43:18 +08:00
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2021-03-08 22:40:39 +08:00
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#if defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2)
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2020-06-23 10:43:18 +08:00
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#include "drv_config.h"
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//#define DRV_DEBUG
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#define LOG_TAG "drv.dac"
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#include <drv_log.h>
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static DAC_HandleTypeDef dac_config[] =
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{
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#ifdef BSP_USING_DAC1
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DAC1_CONFIG,
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#endif
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2021-03-08 22:40:39 +08:00
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2020-10-09 10:06:47 +08:00
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#ifdef BSP_USING_DAC2
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DAC2_CONFIG,
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#endif
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2020-06-23 10:43:18 +08:00
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};
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struct stm32_dac
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{
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DAC_HandleTypeDef DAC_Handler;
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struct rt_dac_device stm32_dac_device;
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};
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static struct stm32_dac stm32_dac_obj[sizeof(dac_config) / sizeof(dac_config[0])];
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2021-02-20 16:27:21 +08:00
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static rt_uint32_t stm32_dac_get_channel(rt_uint32_t channel)
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{
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rt_uint32_t stm32_channel = 0;
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switch (channel)
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{
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case 1:
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stm32_channel = DAC_CHANNEL_1;
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break;
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case 2:
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stm32_channel = DAC_CHANNEL_2;
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break;
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default:
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RT_ASSERT(0);
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break;
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}
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return stm32_channel;
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}
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2020-06-23 10:43:18 +08:00
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static rt_err_t stm32_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
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{
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2021-02-20 16:27:21 +08:00
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uint32_t dac_channel;
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2020-06-23 10:43:18 +08:00
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DAC_HandleTypeDef *stm32_dac_handler;
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RT_ASSERT(device != RT_NULL);
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stm32_dac_handler = device->parent.user_data;
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2020-12-15 17:58:12 +08:00
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#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
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2021-02-20 16:27:21 +08:00
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if ((channel <= 2) && (channel > 0))
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{
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/* set stm32 dac channel */
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dac_channel = stm32_dac_get_channel(channel);
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}
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else
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{
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2021-03-08 22:40:39 +08:00
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LOG_E("dac channel must be 1 or 2.");
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2021-02-20 16:27:21 +08:00
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return -RT_ERROR;
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}
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HAL_DAC_Start(stm32_dac_handler, dac_channel);
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2020-06-23 10:43:18 +08:00
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#endif
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2021-03-08 22:40:39 +08:00
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2020-06-23 10:43:18 +08:00
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return RT_EOK;
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}
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static rt_err_t stm32_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel)
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{
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2021-02-20 16:27:21 +08:00
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uint32_t dac_channel;
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2020-06-23 10:43:18 +08:00
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DAC_HandleTypeDef *stm32_dac_handler;
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RT_ASSERT(device != RT_NULL);
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stm32_dac_handler = device->parent.user_data;
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2021-03-08 22:40:39 +08:00
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2020-12-15 17:58:12 +08:00
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#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
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2021-02-20 16:27:21 +08:00
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if ((channel <= 2) && (channel > 0))
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{
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/* set stm32 dac channel */
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dac_channel = stm32_dac_get_channel(channel);
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}
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else
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{
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2021-03-08 22:40:39 +08:00
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LOG_E("dac channel must be 1 or 2.");
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2021-02-20 16:27:21 +08:00
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return -RT_ERROR;
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}
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HAL_DAC_Stop(stm32_dac_handler, dac_channel);
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2020-06-23 10:43:18 +08:00
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#endif
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2021-03-08 22:40:39 +08:00
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2020-06-23 10:43:18 +08:00
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return RT_EOK;
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}
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2022-04-23 06:59:27 +08:00
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static rt_uint8_t stm32_dac_get_resolution(struct rt_dac_device *device)
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{
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DAC_HandleTypeDef *stm32_dac_handler;
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RT_ASSERT(device != RT_NULL);
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stm32_dac_handler = device->parent.user_data;
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(void)stm32_dac_handler;
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2022-05-21 13:27:45 +08:00
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/* Only has supported DAC_ALIGN_12B_R, so it will return 12 bits */
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return 12;
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2022-04-23 06:59:27 +08:00
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}
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2020-06-23 10:43:18 +08:00
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static rt_err_t stm32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
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{
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uint32_t dac_channel;
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2021-03-08 22:40:39 +08:00
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DAC_ChannelConfTypeDef DAC_ChanConf;
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2020-06-23 10:43:18 +08:00
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DAC_HandleTypeDef *stm32_dac_handler;
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2021-03-08 22:40:39 +08:00
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2020-06-23 10:43:18 +08:00
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(value != RT_NULL);
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stm32_dac_handler = device->parent.user_data;
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2020-06-24 12:52:34 +08:00
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rt_memset(&DAC_ChanConf, 0, sizeof(DAC_ChanConf));
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2021-03-08 22:40:39 +08:00
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2020-12-15 17:58:12 +08:00
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#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
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2020-10-09 10:06:47 +08:00
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if ((channel <= 2) && (channel > 0))
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2020-06-23 10:43:18 +08:00
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{
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/* set stm32 dac channel */
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dac_channel = stm32_dac_get_channel(channel);
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}
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else
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{
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2021-03-08 22:40:39 +08:00
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LOG_E("dac channel must be 1 or 2.");
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2020-06-23 10:43:18 +08:00
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return -RT_ERROR;
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}
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2021-03-08 22:40:39 +08:00
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#endif
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2020-12-15 17:58:12 +08:00
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#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
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2021-03-08 22:40:39 +08:00
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DAC_ChanConf.DAC_Trigger = DAC_TRIGGER_NONE;
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2020-10-09 10:06:47 +08:00
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DAC_ChanConf.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
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2021-03-08 22:40:39 +08:00
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#endif
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2020-06-23 10:43:18 +08:00
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/* config dac out channel*/
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2020-06-24 12:52:34 +08:00
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if (HAL_DAC_ConfigChannel(stm32_dac_handler, &DAC_ChanConf, dac_channel) != HAL_OK)
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2020-06-23 10:43:18 +08:00
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{
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LOG_D("Config dac out channel Error!\n");
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return -RT_ERROR;
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}
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/* set dac channel out value*/
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if (HAL_DAC_SetValue(stm32_dac_handler, dac_channel, DAC_ALIGN_12B_R, *value) != HAL_OK)
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{
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LOG_D("Setting dac channel out value Error!\n");
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return -RT_ERROR;
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}
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/* start dac */
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if (HAL_DAC_Start(stm32_dac_handler, dac_channel) != HAL_OK)
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{
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LOG_D("Start dac Error!\n");
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return -RT_ERROR;
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}
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2021-03-08 22:40:39 +08:00
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2020-06-23 10:43:18 +08:00
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return RT_EOK;
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}
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static const struct rt_dac_ops stm_dac_ops =
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{
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.disabled = stm32_dac_disabled,
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.enabled = stm32_dac_enabled,
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.convert = stm32_set_dac_value,
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2022-04-23 06:59:27 +08:00
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.get_resolution = stm32_dac_get_resolution,
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2020-06-23 10:43:18 +08:00
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};
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static int stm32_dac_init(void)
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{
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int result = RT_EOK;
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/* save dac name */
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char name_buf[5] = {'d', 'a', 'c', '0', 0};
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int i = 0;
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for (i = 0; i < sizeof(dac_config) / sizeof(dac_config[0]); i++)
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{
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/* dac init */
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name_buf[3] = '0';
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stm32_dac_obj[i].DAC_Handler = dac_config[i];
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#if defined(DAC1)
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if (stm32_dac_obj[i].DAC_Handler.Instance == DAC1)
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{
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name_buf[3] = '1';
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}
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#endif
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#if defined(DAC2)
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if (stm32_dac_obj[i].dac_Handler.Instance == DAC2)
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{
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name_buf[3] = '2';
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}
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#endif
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if (HAL_DAC_Init(&stm32_dac_obj[i].DAC_Handler) != HAL_OK)
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{
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LOG_E("%s init failed", name_buf);
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result = -RT_ERROR;
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}
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else
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{
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/* register dac device */
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if (rt_hw_dac_register(&stm32_dac_obj[i].stm32_dac_device, name_buf, &stm_dac_ops, &stm32_dac_obj[i].DAC_Handler) == RT_EOK)
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{
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LOG_D("%s init success", name_buf);
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}
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else
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{
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LOG_E("%s register failed", name_buf);
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result = -RT_ERROR;
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}
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}
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}
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return result;
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}
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INIT_DEVICE_EXPORT(stm32_dac_init);
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#endif /* BSP_USING_DAC */
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