2020-06-20 14:04:27 +08:00
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/*
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2020-11-26 14:29:41 +08:00
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* Copyright (c) 2006-2022, RT-Thread Development Team
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2020-06-20 14:04:27 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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2020-11-26 14:29:41 +08:00
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* 2020-06-20 thread-liu first version
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2020-06-20 14:04:27 +08:00
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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2020-11-26 14:29:41 +08:00
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/* DMA1 stream0 */
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/* DMA1 stream1 */
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/* DMA1 stream2 */
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/* DMA1 stream3 */
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/* DMA1 stream4 */
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/* DMA1 stream5 */
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/* DMA1 stream6 */
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/* DMA1 stream7 */
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2020-06-20 14:04:27 +08:00
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/* DMA2 stream0 */
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2020-06-23 10:43:18 +08:00
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#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
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#define UART3_RX_DMA_IRQHandler DMA2_Stream0_IRQHandler
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#define UART3_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define UART3_RX_DMA_INSTANCE DMA2_Stream0
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#define UART3_RX_DMA_CHANNEL DMA_REQUEST_USART3_RX
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#define UART3_RX_DMA_IRQ DMA2_Stream0_IRQn
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2020-11-26 14:29:41 +08:00
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#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
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#define SPI5_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
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#define SPI5_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define SPI5_RX_DMA_INSTANCE DMA2_Stream0
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#define SPI5_RX_DMA_CHANNEL DMA_REQUEST_SPI5_RX
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#define SPI5_RX_DMA_IRQ DMA2_Stream0_IRQn
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2020-06-20 14:04:27 +08:00
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#endif
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/* DMA2 stream1 */
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2020-06-23 10:43:18 +08:00
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#if defined(BSP_UART3_TX_USING_DMA) && !defined(BSP_UART3_TX_USING_INSTANCE)
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#define UART3_TX_DMA_IRQHandler DMA2_Stream1_IRQHandler
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#define UART3_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define UART3_TX_DMA_INSTANCE DMA2_Stream1
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#define UART3_TX_DMA_CHANNEL DMA_REQUEST_USART3_TX
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#define UART3_TX_DMA_IRQ DMA2_Stream1_IRQn
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2020-11-26 14:29:41 +08:00
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#elif defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
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#define SPI5_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
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#define SPI5_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define SPI5_TX_DMA_INSTANCE DMA2_Stream1
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#define SPI5_TX_DMA_CHANNEL DMA_REQUEST_SPI5_TX
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#define SPI5_TX_DMA_IRQ DMA2_Stream1_IRQn
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2020-06-20 14:04:27 +08:00
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#endif
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/* DMA2 stream2 */
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#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
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#define QSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler
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#define QSPI_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define QSPI_DMA_INSTANCE DMA2_Stream2
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#define QSPI_DMA_CHANNEL DMA_CHANNEL_11
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#define QSPI_DMA_IRQ DMA2_Stream2_IRQn
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#endif
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/* DMA2 stream3 */
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2020-11-26 14:29:41 +08:00
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#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
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#define UART4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
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#define UART4_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define UART4_RX_DMA_INSTANCE DMA2_Stream3
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#define UART4_RX_DMA_CHANNEL DMA_REQUEST_UART4_RX
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#define UART4_RX_DMA_IRQ DMA2_Stream3_IRQn
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2020-06-20 14:04:27 +08:00
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#endif
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/* DMA2 stream4 */
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#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
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2020-11-26 14:29:41 +08:00
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#define UART4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
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2020-06-20 14:04:27 +08:00
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#define UART4_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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2020-11-26 14:29:41 +08:00
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#define UART4_TX_DMA_INSTANCE DMA2_Stream4
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2020-06-20 14:04:27 +08:00
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#define UART4_TX_DMA_CHANNEL DMA_REQUEST_UART4_TX
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2020-11-26 14:29:41 +08:00
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#define UART4_TX_DMA_IRQ DMA2_Stream4_IRQn
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#endif
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/* DMA2 stream5 */
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#if defined(BSP_USING_CRYP) && !defined(CRYP2_OUT_DMA_INSTANCE)
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#define CRYP2_DMA_OUT_IRQHandler DMA2_Stream5_IRQHandler
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#define CRYP2_OUT_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define CRYP2_OUT_DMA_INSTANCE DMA2_Stream5
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#define CRYP2_OUT_DMA_CHANNEL DMA_REQUEST_CRYP2_OUT
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#define CRYP2_OUT_DMA_IRQ DMA2_Stream5_IRQn
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2020-06-20 14:04:27 +08:00
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#endif
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/* DMA2 stream6 */
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2020-11-26 14:29:41 +08:00
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#if defined(BSP_USING_CRYP) && !defined(CRYP2_IN_DMA_INSTANCE)
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#define CRYP2_DMA_IN_IRQHandler DMA2_Stream6_IRQHandler
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#define CRYP2_IN_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define CRYP2_IN_DMA_INSTANCE DMA2_Stream6
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#define CRYP2_IN_DMA_CHANNEL DMA_REQUEST_CRYP2_IN
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#define CRYP2_IN_DMA_IRQ DMA2_Stream6_IRQn
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2020-06-20 14:04:27 +08:00
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#endif
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/* DMA2 stream7 */
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2020-11-26 14:29:41 +08:00
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#if defined(BSP_USING_HASH) && !defined(HASH2_IN_DMA_INSTANCE)
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#define HASH2_DMA_IN_IRQHandler DMA2_Stream7_IRQHandler
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#define HASH2_IN_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define HASH2_IN_DMA_INSTANCE DMA2_Stream7
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#define HASH2_IN_DMA_CHANNEL DMA_REQUEST_HASH2_IN
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#define HASH2_IN_DMA_IRQ DMA2_Stream7_IRQn
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2020-06-20 14:04:27 +08:00
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DMA_CONFIG_H__ */
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