194 lines
6.5 KiB
C
194 lines
6.5 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fxhci_roothub.c
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* Date: 2022-02-11 13:33:12
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* LastEditTime: 2022-02-18 09:17:02
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* Description: This files is for implementation of XHCI roothub function
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 Zhugengyu 2022/2/7 init commit
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*/
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#include "fdebug.h"
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#include "fusb.h"
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#include "fusb_generic_hub.h"
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#include "fxhci_private.h"
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#define FUSB_DEBUG_TAG "FXHCI_ROOTHUB"
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#define FUSB_ERROR(format, ...) FT_DEBUG_PRINT_E(FUSB_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FUSB_WARN(format, ...) FT_DEBUG_PRINT_W(FUSB_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FUSB_INFO(format, ...) FT_DEBUG_PRINT_I(FUSB_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FUSB_DEBUG(format, ...) FT_DEBUG_PRINT_D(FUSB_DEBUG_TAG, format, ##__VA_ARGS__)
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static int FXhciRootHubStatusChanged(FUsbDev *const dev)
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{
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FXhci *const xhci = FXHCI_INST_GET(dev->controller);
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FASSERT(xhci);
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u32 reg_val = FXhciReadOper32(&xhci->mmio, FXHCI_REG_OP_USBSTS);
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const int changed = !!(FXHCI_REG_OP_USBSTS_PCD & reg_val);
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/* clear port change bit */
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if (changed)
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{
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reg_val &= FXHCI_REG_OP_USBSTS_PRSRV_MASK;
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reg_val |= FXHCI_REG_OP_USBSTS_PCD;
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FXhciWriteOper32(&xhci->mmio, FXHCI_REG_OP_USBSTS, reg_val);
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}
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return changed;
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}
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static int FXhciRootHubPortStatusChanged(FUsbDev *const dev, const int port)
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{
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FXhci *const xhci = FXHCI_INST_GET(dev->controller);
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FASSERT(xhci);
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u32 portsc = FXhciReadPort32(&xhci->mmio, port - 1, FXHCI_REG_OP_PORTS_PORTSC);
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const int changed = !!(portsc & (FXHCI_REG_OP_PORTS_PORTSC_CSC | FXHCI_REG_OP_PORTS_PORTSC_PRC));
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/* always clear all the status change bits */
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portsc &= FXHCI_REG_OP_PORTS_PORTSC_RW_MASK;
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portsc |= 0x00fe0000;
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FXhciWritePort32(&xhci->mmio, port - 1, FXHCI_REG_OP_PORTS_PORTSC, portsc);
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return changed;
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}
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static int FXhciRootHubPortConnected(FUsbDev *const dev, const int port)
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{
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FXhci *const xhci = FXHCI_INST_GET(dev->controller);
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FASSERT(xhci);
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u32 portsc = FXhciReadPort32(&xhci->mmio, port - 1, FXHCI_REG_OP_PORTS_PORTSC);
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return portsc & FXHCI_REG_OP_PORTS_PORTSC_CCS;
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}
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static int FXhciRootHubPortInReset(FUsbDev *const dev, const int port)
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{
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FXhci *const xhci = FXHCI_INST_GET(dev->controller);
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FASSERT(xhci);
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u32 portsc = FXhciReadPort32(&xhci->mmio, port - 1, FXHCI_REG_OP_PORTS_PORTSC);
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return !!(portsc & FXHCI_REG_OP_PORTS_PORTSC_PR);
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}
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static int FXhciRootHubPortEnabled(FUsbDev *const dev, const int port)
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{
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FXhci *const xhci = FXHCI_INST_GET(dev->controller);
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FASSERT(xhci);
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u32 portsc = FXhciReadPort32(&xhci->mmio, port - 1, FXHCI_REG_OP_PORTS_PORTSC);
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return !!(portsc & FXHCI_REG_OP_PORTS_PORTSC_PED);
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}
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static FUsbSpeed FXhciRootHubPortSpeed(FUsbDev *const dev, const int port)
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{
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FXhci *const xhci = FXHCI_INST_GET(dev->controller);
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FASSERT(xhci);
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u32 portsc = FXhciReadPort32(&xhci->mmio, port - 1, FXHCI_REG_OP_PORTS_PORTSC);
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if (portsc & FXHCI_REG_OP_PORTS_PORTSC_PED)
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{
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return FXHCI_REG_OP_PORTS_PORTSC_PORT_SPEED_GET(portsc) - 1;
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}
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else
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{
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return FUSB_UNKNOWN_SPEED;
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}
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}
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static int FXhciRootHubResetPort(FUsbDev *const dev, const int port)
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{
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FXhci *const xhci = FXHCI_INST_GET(dev->controller);
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FASSERT(xhci);
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u32 portsc = FXhciReadPort32(&xhci->mmio, port - 1, FXHCI_REG_OP_PORTS_PORTSC);
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/* Trigger port reset. */
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portsc &= FXHCI_REG_OP_PORTS_PORTSC_RW_MASK;
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portsc |= FXHCI_REG_OP_PORTS_PORTSC_PR;
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FXhciWritePort32(&xhci->mmio, port - 1, FXHCI_REG_OP_PORTS_PORTSC, portsc);
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/* Wait for port_in_reset == 0, up to 150 * 1000us = 150ms */
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if (FUsbGenericHubWaitForPort(dev, port, 0, FXhciRootHubPortInReset,
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150, 1000) == 0)
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{
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FUSB_INFO("xhci_rh: Reset timed out at port %d ", port);
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}
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else
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{
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portsc = FXhciReadPort32(&xhci->mmio, port - 1, FXHCI_REG_OP_PORTS_PORTSC);
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portsc &= FXHCI_REG_OP_PORTS_PORTSC_RW_MASK;
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portsc |= FXHCI_REG_OP_PORTS_PORTSC_PRC | FXHCI_REG_OP_PORTS_PORTSC_WRC;
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FXhciWritePort32(&xhci->mmio, port - 1, FXHCI_REG_OP_PORTS_PORTSC, portsc);
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}
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return 0;
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}
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static int FXhciRootHubEnablePort(FUsbDev *const dev, int port)
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{
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FXhci *const xhci = FXHCI_INST_GET(dev->controller);
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FASSERT(xhci);
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u32 portsc = FXhciReadPort32(&xhci->mmio, port - 1, FXHCI_REG_OP_PORTS_PORTSC);
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/*
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* Before sending commands to a port, the Port Power in
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* PORTSC register should be enabled.
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*/
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portsc &= FXHCI_REG_OP_PORTS_PORTSC_RW_MASK;
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portsc |= FXHCI_REG_OP_PORTS_PORTSC_PP;
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FXhciWritePort32(&xhci->mmio, port - 1, FXHCI_REG_OP_PORTS_PORTSC, portsc);
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return 0;
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}
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static const FUsbGenericHubOps FXHCI_ROOTHUB_OPS =
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{
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.hub_status_changed = FXhciRootHubStatusChanged,
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.port_status_changed = FXhciRootHubPortStatusChanged,
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.port_connected = FXhciRootHubPortConnected,
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.port_in_reset = FXhciRootHubPortInReset,
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.port_enabled = FXhciRootHubPortEnabled,
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.port_speed = FXhciRootHubPortSpeed,
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.enable_port = FXhciRootHubEnablePort,
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.disable_port = NULL,
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.start_port_reset = NULL,
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.reset_port = FXhciRootHubResetPort,
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};
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/**
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* @name: FXhciRootHubInit
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* @msg: 初始化Roothub
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* @return {*}
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* @param {FUsbDev} *dev, Roothub实例
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*/
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void FXhciRootHubInit(FUsbDev *dev)
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{
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u32 reg_val;
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FXhci *xhci = FXHCI_INST_GET(dev->controller);
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FASSERT(xhci);
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/* we can set them here because a root hub _really_ shouldn't
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appear elsewhere */
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dev->address = 0;
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dev->hub = FUSB_NO_HUB;
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dev->port = FUSB_NO_PORT;
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reg_val = FXhciReadCap32(&xhci->mmio, FXHCI_REG_CAP_HCSPARAMS1);
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const int num_ports = FXHCI_REG_CAP_HCSPARAMS1_MAX_PORTS_GET(reg_val); /* TODO: maybe we need to read extended caps */
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FUsbGenericHubInit(dev, num_ports, &FXHCI_ROOTHUB_OPS);
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FUSB_INFO("xHCI: root hub init done ");
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}
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