167 lines
6.2 KiB
C
167 lines
6.2 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fgpio_hw.h
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-18 08:25:35
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* Description: This files is for GPIO register definition
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 zhugengyu 2022-3-1 init commit
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*/
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#ifndef DRIVERS_FGPIO_HW_H
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#define DRIVERS_FGPIO_HW_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/***************************** Include Files *********************************/
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#include "fio.h"
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#include "fkernel.h"
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/************************** Constant Definitions *****************************/
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/** @name Register Map
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*
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* Register offsets from the base address of an GPIO device.
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* @{
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*/
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#define FGPIO_SWPORTA_DR_OFFSET 0x00 /* WR Port A Output Data Register */
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#define FGPIO_SWPORTA_DDR_OFFSET 0x04 /* WR Port A Data Direction Register */
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#define FGPIO_EXT_PORTA_OFFSET 0x08 /* RO Port A Input Data Register */
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#define FGPIO_SWPORTB_DR_OFFSET 0x0c /* WR Port B Output Data Register */
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#define FGPIO_SWPORTB_DDR_OFFSET 0x10 /* WR Port B Data Direction Register */
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#define FGPIO_EXT_PORTB_OFFSET 0x14 /* RO Port B Input Data Register */
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#define FGPIO_INTEN_OFFSET 0x18 /* WR Port A Interrput Enable Register */
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#define FGPIO_INTMASK_OFFSET 0x1c /* WR Port A Interrupt Mask Register */
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#define FGPIO_INTTYPE_LEVEL_OFFSET 0x20 /* WR Port A Interrupt Level Register */
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#define FGPIO_INT_POLARITY_OFFSET 0x24 /* WR Port A Interrupt Polarity Register */
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#define FGPIO_INTSTATUS_OFFSET 0x28 /* RO Port A Interrupt Status Register */
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#define FGPIO_RAW_INTSTATUS_OFFSET 0x2c /* RO Port A Raw Interrupt Status Register */
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#define FGPIO_LS_SYNC_OFFSET 0x30 /* WR Level-sensitive Synchronization Enable Register */
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#define FGPIO_DEBOUNCE_OFFSET 0x34 /* WR Debounce Enable Register */
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#define FGPIO_PORTA_EOI_OFFSET 0x38 /* WO Port A Clear Interrupt Register */
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/** @name FGPIO_SWPORTA_DR_OFFSET Register
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*/
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#define FGPIO_SWPORTA_DR_SET(dir) SET_REG32_BITS((dir), 7, 0)
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#define FGPIO_SWPORTA_DR_GET(reg_val) GET_REG32_BITS((reg_val), 7, 0)
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#define FGPIO_SWPORTA_DR_MASK GENMASK(7, 0)
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/** @name FGPIO_SWPORTA_DDR_OFFSET Register
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*/
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#define FGPIO_SWPORTA_DDR_SET(dir) SET_REG32_BITS((dir), 7, 0)
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#define FGPIO_SWPORTA_DDR_GET(reg_val) GET_REG32_BITS((reg_val), 7, 0)
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#define FGPIO_SWPORTA_DDR_MASK GENMASK(7, 0)
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/** @name FGPIO_EXT_PORTA_OFFSET Register
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*/
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#define FGPIO_EXT_PORTA_SET(dir) SET_REG32_BITS((dir), 7, 0)
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#define FGPIO_EXT_PORTA_GET(reg_val) GET_REG32_BITS((reg_val), 7, 0)
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#define FGPIO_EXT_PORTA_MASK GENMASK(7, 0)
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/** @name FGPIO_SWPORTB_DR_OFFSET Register
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*/
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#define FGPIO_SWPORTB_DR_SET(dir) SET_REG32_BITS((dir), 7, 0)
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#define FGPIO_SWPORTB_DR_GET(reg_val) GET_REG32_BITS((reg_val), 7, 0)
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#define FGPIO_SWPORTB_DR_MASK GENMASK(7, 0)
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/** @name FGPIO_SWPORTB_DDR_OFFSET Register
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*/
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#define FGPIO_SWPORTB_DDR_SET(dir) SET_REG32_BITS((dir), 7, 0)
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#define FGPIO_SWPORTB_DDR_GET(reg_val) GET_REG32_BITS((reg_val), 7, 0)
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#define FGPIO_SWPORTB_DDR_MASK GENMASK(7, 0)
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/** @name FGPIO_EXT_PORTB_OFFSET Register
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*/
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#define FGPIO_EXT_PORTB_SET(dir) SET_REG32_BITS((dir), 7, 0)
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#define FGPIO_EXT_PORTB_GET(reg_val) GET_REG32_BITS((reg_val), 7, 0)
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#define FGPIO_EXT_PORTB_MASK GENMASK(7, 0)
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/** @name FGPIO_INTEN_OFFSET Register
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*/
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#define FGPIO_INTR_PORTA_EN(n) BIT(n) /* 1: enable the intr of n-th port in group-a */
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/** @name FGPIO_INTMASK_OFFSET Register
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*/
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#define FGPIO_INTR_PORTA_MASK(n) BIT(n) /* 1: disable the intr of n-th port in group-a */
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/** @name FGPIO_INTTYPE_LEVEL_OFFSET Register
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*/
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#define FGPIO_INTR_PORTA_LEVEL(n) BIT(n) /* 1: intr by edge, 0: intr by level */
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/** @name FGPIO_INT_POLARITY_OFFSET Register
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*/
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#define FGPIO_INTR_PORTA_POLARITY(n) BIT(n) /* 1: intr by rising-edge/high-level, 0: intr by falling-edge/low-level */
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/** @name FGPIO_INTSTATUS_OFFSET Register
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*/
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#define FGPIO_INTR_PORTA_STATUS(n) BIT(n) /* intr status */
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/** @name FGPIO_RAW_INTSTATUS_OFFSET Register
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*/
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#define FGPIO_INTR_PORTA_RAW_STATUS(n) BIT(n) /* intr status without masking */
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/** @name FGPIO_LS_SYNC_OFFSET Register
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*/
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#define FGPIO_PCLK_INTR_SYNC(n) BIT(n) /* 1: sync to pclk_intr */
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/** @name FGPIO_DEBOUNCE_OFFSET Register
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*/
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#define FGPIO_DEBOUNCE_CLK_CONFIG_SET(clk) SET_REG32_BITS((clk), 15, 7)
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#define FGPIO_DEBOUNCE_CLK_CONFIG_GET(reg_val) GET_REG32_BITS((reg_val), 15, 7)
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#define FGPIO_DEBOUNCE_CLK_CONFIG_MASK GENMASK(15, 7)
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#define FGPIO_DEBOUNCE_EN(n) BIT(n) /* 1: enable debounce */
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/** @name FGPIO_PORTA_EOI_OFFSET Register
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*/
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#define FGPIO_CLR_INTR_PORTA(n) BIT(n) /* 1: clear interrupt */
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/**************************** Type Definitions *******************************/
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/************************** Variable Definitions *****************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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static inline u32 FGpioReadReg32(uintptr base_addr, uintptr reg_off)
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{
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return FtIn32(base_addr + reg_off);
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}
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static inline void FGpioWriteReg32(uintptr base_addr, uintptr reg_off, const u32 reg_val)
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{
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FtOut32(base_addr + reg_off, reg_val);
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}
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static inline void FGpioSetBit32(uintptr base_addr, uintptr reg_off, u32 bit)
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{
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if (0 == bit)
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FtClearBit32(base_addr + reg_off, bit);
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else if (1 == bit)
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FtSetBit32(base_addr + reg_off, bit);
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}
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/************************** Function Prototypes ******************************/
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#ifdef __cplusplus
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}
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#endif
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#endif
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