273 lines
9.0 KiB
C
273 lines
9.0 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fxmac_bd.h
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* Date: 2022-04-06 14:46:52
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* LastEditTime: 2022-04-06 14:46:58
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* Description: This file is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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*/
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#ifndef DRIVERS_ETH_F_XMAC_BD_H
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#define DRIVERS_ETH_F_XMAC_BD_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "ftypes.h"
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#include "string.h"
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/**
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* @name: FXMAC_BD_READ
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* @msg: Read the given Buffer Descriptor word.
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* @param bd_ptr is the base address of the BD to read
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* @param offset is the word offset to be read
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* @return The 32-bit value of the field
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*/
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#define FXMAC_BD_READ(bd_ptr, offset) \
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(*(u32 *)((uintptr)((void *)(bd_ptr)) + (u32)(offset)))
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/**
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* @name: FXMAC_BD_WRITE
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* @msg: Write the given Buffer Descriptor word.
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* @param bd_ptr is the base address of the BD to write
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* @param Offset is the word offset to be written
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* @param data is the 32-bit value to write to the field
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* @return {*}
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*/
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#define FXMAC_BD_WRITE(bd_ptr, Offset, data) \
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(*(u32 *)((uintptr)(void *)(bd_ptr) + (u32)(Offset)) = (u32)(data))
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/**
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* @name: FXMAC_BD_SET_STATUS
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* @msg: Set the BD's Status field (word 1).
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* @param bd_ptr is the BD pointer to operate on
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* @param data is the value to write to BD's status field.
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*/
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#define FXMAC_BD_SET_STATUS(bd_ptr, data) \
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FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET, \
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FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) | (data))
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/**
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* @name: FXMAC_BD_IS_RX_NEW
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* @msg: Determine the new bit of the receive BD.
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* @param bd_ptr is the BD pointer to operate on
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*/
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#define FXMAC_BD_IS_RX_NEW(bd_ptr) \
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((FXMAC_BD_READ((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
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FXMAC_RXBUF_NEW_MASK) != 0U \
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? TRUE \
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: FALSE)
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/**
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* @name: FXMAC_BD_IS_TX_WRAP
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* @msg: Determine the wrap bit of the transmit BD which indicates end of the
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* BD list.
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* @param bd_ptr is the BD pointer to operate on
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*/
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#define FXMAC_BD_IS_TX_WRAP(bd_ptr) \
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((FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
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FXMAC_TXBUF_WRAP_MASK) != 0U \
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? TRUE \
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: FALSE)
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/**
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* @name: FXMAC_BD_IS_RX_WRAP
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* @msg: Determine the wrap bit of the receive BD which indicates end of the
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* BD list.
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* @param: bd_ptr is the BD pointer to operate on
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*/
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#define FXMAC_BD_IS_RX_WRAP(bd_ptr) \
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((FXMAC_BD_READ((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
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FXMAC_RXBUF_WRAP_MASK) != 0U \
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? TRUE \
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: FALSE)
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/**
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* @name: FXMAC_BD_SET_ADDRESS_TX
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* @msg: Set the BD's address field (word 0).
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* @param: bd_ptr is the BD pointer to operate on
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* @param: addr is the value to write to BD's status field.
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*/
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#if defined(__aarch64__) || defined(__arch64__)
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#define FXMAC_BD_SET_ADDRESS_TX(bd_ptr, addr) \
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FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_OFFSET, \
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(u32)((addr)&ULONG64_LO_MASK)); \
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FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_HI_OFFSET, \
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(u32)(((addr)&ULONG64_HI_MASK) >> 32U));
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#else
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#define FXMAC_BD_SET_ADDRESS_TX(bd_ptr, addr) \
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FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_OFFSET, (u32)(addr))
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#endif
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/**
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* @name: FXMAC_BD_SET_ADDRESS_RX
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* @msg: Set the BD's address field (word 0).
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* @param: bd_ptr is the BD pointer to operate on
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* @param: addr is the value to write to BD's status field.
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* @return {*}
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*/
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#ifdef __aarch64__
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#define FXMAC_BD_SET_ADDRESS_RX(bd_ptr, addr) \
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FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_OFFSET, \
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((FXMAC_BD_READ((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
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~FXMAC_RXBUF_ADD_MASK) | \
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((u32)((addr)&ULONG64_LO_MASK)))); \
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FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_HI_OFFSET, \
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(u32)(((addr)&ULONG64_HI_MASK) >> 32U));
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#else
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#define FXMAC_BD_SET_ADDRESS_RX(bd_ptr, addr) \
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FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_OFFSET, \
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((FXMAC_BD_READ((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
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~FXMAC_RXBUF_ADD_MASK) | \
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(u32)(addr)))
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#endif
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/**
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* @name: FXMAC_BD_SET_LENGTH
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* @msg: Set transfer length in bytes for the given BD. The length must be set each
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* time a BD is submitted to hardware.
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* @param: bd_ptr is the BD pointer to operate on
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* @param: len_bytes is the number of bytes to transfer.
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* @return {*}
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*/
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#define FXMAC_BD_SET_LENGTH(bd_ptr, len_bytes) \
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FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET, \
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((FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
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~FXMAC_TXBUF_LEN_MASK) | \
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(len_bytes)))
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/**
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* @name: FXMAC_BD_GET_LENGTH
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* @msg: For Tx channels, the returned value is the same as that written with
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* FXMAC_BD_SET_LENGTH(). For Rx channels, the returned value is the size of the received packet.
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* @param: bd_ptr is the BD pointer to operate on
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* @return {*}
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*/
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#define FXMAC_BD_GET_LENGTH(bd_ptr) \
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(FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
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FXMAC_RXBUF_LEN_MASK)
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/**
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* @name: FXMAC_GET_RX_FRAME_SIZE
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* @msg: The returned value is the size of the received packet.
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* This API supports jumbo frame sizes if enabled.
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* @param instance_p is the pointer to xmac instance
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* @param bd_ptr is the BD pointer to operate on
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*
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* @return Length field processed by hardware or set by
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* FXMAC_BD_SET_LENGTH().
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*/
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#define FXMAC_BD_JUMBO_LENGTH_MASK
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#define FXMAC_GET_RX_FRAME_SIZE(instance_p, bd_ptr) \
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(FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
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0x00003FFFU)
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/**
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* @name: FXMAC_BD_CLEAR_TX_USED
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* @msg: Software clears this bit to enable the buffer to be read by the hardware.
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* Hardware sets this bit for the first buffer of a frame once it has been
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* successfully transmitted. This macro clears this bit of transmit BD.
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* @param: bd_ptr is the BD pointer to operate on
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* @return {*}
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*/
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#define FXMAC_BD_CLEAR_TX_USED(bd_ptr) \
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(FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET, \
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FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
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(~FXMAC_TXBUF_USED_MASK)))
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#define FXMAC_BD_SET_CRC(bd_ptr) \
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(FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET, \
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FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
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(~FXMAC_TXBUF_NOCRC_MASK)))
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/**
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* @name: FXMAC_BD_SET_LAST
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* @msg: Tell the DMA engine that the given transmit BD marks the end of the current
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* packet to be processed.
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* @param bd_ptr is the BD pointer to operate on
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* @return {*}
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*/
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#define FXMAC_BD_SET_LAST(bd_ptr) \
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(FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET, \
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FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) | \
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FXMAC_TXBUF_LAST_MASK))
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/**
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* @name: FXMAC_BD_CLEAR_LAST
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* @msg: Tell the DMA engine that the current packet does not end with the given
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* BD.
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* @param bd_ptr is the BD pointer to operate on
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* @return {*}
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*/
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#define FXMAC_BD_CLEAR_LAST(bd_ptr) \
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(FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET, \
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FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
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~FXMAC_TXBUF_LAST_MASK))
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/**
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* @name: FXMAC_BD_CLEAR
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* @msg: Zero out BD fields
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* @param bd_ptr is the BD pointer to operate on
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* @return {*}
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*/
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#define FXMAC_BD_CLEAR(bd_ptr) \
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memset((bd_ptr), 0, sizeof(FXmacBd))
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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#ifdef __aarch64__
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/* Minimum BD alignment */
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#define FXMAC_DMABD_MINIMUM_ALIGNMENT 64U
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#define FXMAC_BD_NUM_WORDS 4U
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#else
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/* Minimum BD alignment */
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#define FXMAC_DMABD_MINIMUM_ALIGNMENT 4U
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#define FXMAC_BD_NUM_WORDS 2U
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#endif
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/**
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* The FXMAC_Bd is the type for buffer descriptors (BDs).
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*/
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typedef u32 FXmacBd[FXMAC_BD_NUM_WORDS];
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#ifdef __cplusplus
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}
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#endif
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#endif // !
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