159 lines
6.0 KiB
C
159 lines
6.0 KiB
C
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/*
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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __UART_I_H__
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#define __UART_I_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Register definitions for UART
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*/
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#define UART_RHB (0x00)
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#define UART_RBR (0x00) /* receive buffer register */
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#define UART_THR (0x00) /* transmit holding register */
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#define UART_DLL (0x00) /* divisor latch low register */
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#define UART_DLH (0x04) /* diviso latch high register */
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#define UART_IER (0x04) /* interrupt enable register */
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#define UART_IIR (0x08) /* interrupt identity register */
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#define UART_FCR (0x08) /* FIFO control register */
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#define UART_LCR (0x0c) /* line control register */
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#define UART_MCR (0x10) /* modem control register */
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#define UART_LSR (0x14) /* line status register */
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#define UART_MSR (0x18) /* modem status register */
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#define UART_SCH (0x1c) /* scratch register */
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#define UART_USR (0x7c) /* status register */
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#define UART_TFL (0x80) /* transmit FIFO level */
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#define UART_RFL (0x84) /* RFL */
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#define UART_HALT (0xa4) /* halt tx register */
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#define UART_RS485 (0xc0) /* RS485 control and status register */
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/*
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* register bit field define
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*/
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/* Interrupt Enable Register */
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#define UART_IER_MASK (0xff)
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#define UART_IER_PTIME (BIT(7))
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#define UART_IER_RS485 (BIT(4))
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#define UART_IER_MSI (BIT(3))
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#define UART_IER_RLSI (BIT(2))
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#define UART_IER_THRI (BIT(1))
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#define UART_IER_RDI (BIT(0))
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/* Interrupt ID Register */
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#define UART_IIR_FEFLAG_MASK (BIT(6)|BIT(7))
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#define UART_IIR_IID_MASK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
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#define UART_IIR_IID_MSTA (0)
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#define UART_IIR_IID_NOIRQ (1)
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#define UART_IIR_IID_THREMP (2)
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#define UART_IIR_IID_RXDVAL (4)
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#define UART_IIR_IID_LINESTA (6)
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#define UART_IIR_IID_BUSBSY (7)
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#define UART_IIR_IID_CHARTO (12)
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/* FIFO Control Register */
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#define UART_FCR_RXTRG_MASK (BIT(6)|BIT(7))
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#define UART_FCR_RXTRG_1CH (0 << 6)
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#define UART_FCR_RXTRG_1_4 (1 << 6)
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#define UART_FCR_RXTRG_1_2 (2 << 6)
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#define UART_FCR_RXTRG_FULL (3 << 6)
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#define UART_FCR_TXTRG_MASK (BIT(4)|BIT(5))
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#define UART_FCR_TXTRG_EMP (0 << 4)
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#define UART_FCR_TXTRG_2CH (1 << 4)
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#define UART_FCR_TXTRG_1_4 (2 << 4)
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#define UART_FCR_TXTRG_1_2 (3 << 4)
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#define UART_FCR_TXFIFO_RST (BIT(2))
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#define UART_FCR_RXFIFO_RST (BIT(1))
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#define UART_FCR_FIFO_EN (BIT(0))
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/* Line Control Register */
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#define UART_LCR_DLAB (BIT(7))
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#define UART_LCR_SBC (BIT(6))
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#define UART_LCR_PARITY_MASK (BIT(5)|BIT(4))
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#define UART_LCR_EPAR (1 << 4)
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#define UART_LCR_OPAR (0 << 4)
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#define UART_LCR_PARITY (BIT(3))
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#define UART_LCR_STOP (BIT(2))
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#define UART_LCR_DLEN_MASK (BIT(1)|BIT(0))
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#define UART_LCR_WLEN5 (0)
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#define UART_LCR_WLEN6 (1)
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#define UART_LCR_WLEN7 (2)
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#define UART_LCR_WLEN8 (3)
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/* Modem Control Register */
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#define UART_MCR_MODE_MASK (BIT(7)|BIT(6))
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#define UART_MCR_MODE_RS485 (2 << 6)
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#define UART_MCR_MODE_SIRE (1 << 6)
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#define UART_MCR_MODE_UART (0 << 6)
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#define UART_MCR_AFE (BIT(5))
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#define UART_MCR_LOOP (BIT(4))
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#define UART_MCR_RTS (BIT(1))
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#define UART_MCR_DTR (BIT(0))
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/* Line Status Rigster */
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#define UART_LSR_RXFIFOE (BIT(7))
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#define UART_LSR_TEMT (BIT(6))
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#define UART_LSR_THRE (BIT(5))
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#define UART_LSR_BI (BIT(4))
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#define UART_LSR_FE (BIT(3))
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#define UART_LSR_PE (BIT(2))
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#define UART_LSR_OE (BIT(1))
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#define UART_LSR_DR (BIT(0))
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#define UART_LSR_BRK_ERROR_BITS (0x1E) /* BI, FE, PE, OE bits */
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/* Modem Status Register */
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#define UART_MSR_DCD (BIT(7))
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#define UART_MSR_RI (BIT(6))
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#define UART_MSR_DSR (BIT(5))
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#define UART_MSR_CTS (BIT(4))
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#define UART_MSR_DDCD (BIT(3))
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#define UART_MSR_TERI (BIT(2))
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#define UART_MSR_DDSR (BIT(1))
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#define UART_MSR_DCTS (BIT(0))
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#define UART_MSR_ANY_DELTA (0x0F)
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#define MSR_SAVE_FLAGS (UART_MSR_ANY_DELTA)
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/* Status Register */
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#define UART_USR_RFF (BIT(4))
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#define UART_USR_RFNE (BIT(3))
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#define UART_USR_TFE (BIT(2))
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#define UART_USR_TFNF (BIT(1))
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#define UART_USR_BUSY (BIT(0))
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/* Halt Register */
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#define UART_HALT_LCRUP (BIT(2))
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#define UART_HALT_FORCECFG (BIT(1))
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#define UART_HALT_HTX (BIT(0))
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/* RS485 Control and Status Register */
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#define UART_RS485_RXBFA (BIT(3))
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#define UART_RS485_RXAFA (BIT(2))
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#ifdef __cplusplus
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}
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#endif
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#endif /* __UART_I_H__ */
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